1 /* --COPYRIGHT--,BSD\r
2 * Copyright (c) 2014, Texas Instruments Incorporated\r
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32 //*****************************************************************************\r
33 //\r
34 // eusci_a_uart.c - Driver for the eusci_a_uart Module.\r
35 //\r
36 //*****************************************************************************\r
37 \r
38 //*****************************************************************************\r
39 //\r
40 //! \addtogroup eusci_a_uart_api\r
41 //! @{\r
42 //\r
43 //*****************************************************************************\r
44 \r
45 #include "inc/hw_regaccess.h"\r
46 #include "inc/hw_memmap.h"\r
47 \r
48 #ifdef __MSP430_HAS_EUSCI_Ax__\r
49 #include "eusci_a_uart.h"\r
50 \r
51 #include <assert.h>\r
52 \r
53 //*****************************************************************************\r
54 //\r
55 //! \brief DEPRECATED - Advanced initialization routine for the UART block. The\r
56 //! values to be written into the clockPrescalar, firstModReg, secondModReg and\r
57 //! overSampling parameters should be pre-computed and passed into the\r
58 //! initialization function.\r
59 //!\r
60 //! Upon successful initialization of the UART block, this function will have\r
61 //! initialized the module, but the UART block still remains disabled and must\r
62 //! be enabled with EUSCI_A_UART_enable(). To calculate values for\r
63 //! clockPrescalar, firstModReg, secondModReg and overSampling please use the\r
64 //! link below.\r
65 //!\r
66 //! http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSP430BaudRateConverter/index.html\r
67 //!\r
68 //! \param baseAddress is the base address of the EUSCI_A_UART module.\r
69 //! \param selectClockSource selects Clock source.\r
70 //! Valid values are:\r
71 //! - \b EUSCI_A_UART_CLOCKSOURCE_SMCLK\r
72 //! - \b EUSCI_A_UART_CLOCKSOURCE_ACLK\r
73 //! \param clockPrescalar is the value to be written into UCBRx bits\r
74 //! \param firstModReg is First modulation stage register setting. This value\r
75 //! is a pre-calculated value which can be obtained from the Device\r
76 //! Users Guide. This value is written into UCBRFx bits of UCAxMCTLW.\r
77 //! \param secondModReg is Second modulation stage register setting. This value\r
78 //! is a pre-calculated value which can be obtained from the Device\r
79 //! Users Guide. This value is written into UCBRSx bits of UCAxMCTLW.\r
80 //! \param parity is the desired parity.\r
81 //! Valid values are:\r
82 //! - \b EUSCI_A_UART_NO_PARITY [Default]\r
83 //! - \b EUSCI_A_UART_ODD_PARITY\r
84 //! - \b EUSCI_A_UART_EVEN_PARITY\r
85 //! \param msborLsbFirst controls direction of receive and transmit shift\r
86 //! register.\r
87 //! Valid values are:\r
88 //! - \b EUSCI_A_UART_MSB_FIRST\r
89 //! - \b EUSCI_A_UART_LSB_FIRST [Default]\r
90 //! \param numberofStopBits indicates one/two STOP bits\r
91 //! Valid values are:\r
92 //! - \b EUSCI_A_UART_ONE_STOP_BIT [Default]\r
93 //! - \b EUSCI_A_UART_TWO_STOP_BITS\r
94 //! \param uartMode selects the mode of operation\r
95 //! Valid values are:\r
96 //! - \b EUSCI_A_UART_MODE [Default]\r
97 //! - \b EUSCI_A_UART_IDLE_LINE_MULTI_PROCESSOR_MODE\r
98 //! - \b EUSCI_A_UART_ADDRESS_BIT_MULTI_PROCESSOR_MODE\r
99 //! - \b EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE\r
100 //! \param overSampling indicates low frequency or oversampling baud generation\r
101 //! Valid values are:\r
102 //! - \b EUSCI_A_UART_OVERSAMPLING_BAUDRATE_GENERATION\r
103 //! - \b EUSCI_A_UART_LOW_FREQUENCY_BAUDRATE_GENERATION\r
104 //!\r
105 //! Modified bits are \b UCPEN, \b UCPAR, \b UCMSB, \b UC7BIT, \b UCSPB, \b\r
106 //! UCMODEx and \b UCSYNC of \b UCAxCTL0 register; bits \b UCSSELx and \b\r
107 //! UCSWRST of \b UCAxCTL1 register.\r
108 //!\r
109 //! \return STATUS_SUCCESS or STATUS_FAIL of the initialization process\r
110 //\r
111 //*****************************************************************************\r
112 bool EUSCI_A_UART_initAdvance( uint16_t baseAddress,\r
113 uint8_t selectClockSource,\r
114 uint16_t clockPrescalar,\r
115 uint8_t firstModReg,\r
116 uint8_t secondModReg,\r
117 uint8_t parity,\r
118 uint16_t msborLsbFirst,\r
119 uint16_t numberofStopBits,\r
120 uint16_t uartMode,\r
121 uint8_t overSampling\r
122 )\r
123 {\r
124 EUSCI_A_UART_initParam param = { 0 };\r
125 \r
126 param.selectClockSource = selectClockSource;\r
127 param.clockPrescalar = clockPrescalar;\r
128 param.firstModReg = firstModReg;\r
129 param.secondModReg = secondModReg;\r
130 param.parity = parity;\r
131 param.msborLsbFirst = msborLsbFirst;\r
132 param.numberofStopBits = numberofStopBits;\r
133 param.uartMode = uartMode;\r
134 param.overSampling = overSampling;\r
135 \r
136 return EUSCI_A_UART_init(baseAddress, ¶m);\r
137 }\r
138 \r
139 //*****************************************************************************\r
140 //\r
141 //! \brief Advanced initialization routine for the UART block. The values to be\r
142 //! written into the clockPrescalar, firstModReg, secondModReg and overSampling\r
143 //! parameters should be pre-computed and passed into the initialization\r
144 //! function.\r
145 //!\r
146 //! Upon successful initialization of the UART block, this function will have\r
147 //! initialized the module, but the UART block still remains disabled and must\r
148 //! be enabled with EUSCI_A_UART_enable(). To calculate values for\r
149 //! clockPrescalar, firstModReg, secondModReg and overSampling please use the\r
150 //! link below.\r
151 //!\r
152 //! http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSP430BaudRateConverter/index.html\r
153 //!\r
154 //! \param baseAddress is the base address of the EUSCI_A_UART module.\r
155 //! \param param is the pointer to struct for initialization.\r
156 //!\r
157 //! Modified bits are \b UCPEN, \b UCPAR, \b UCMSB, \b UC7BIT, \b UCSPB, \b\r
158 //! UCMODEx and \b UCSYNC of \b UCAxCTL0 register; bits \b UCSSELx and \b\r
159 //! UCSWRST of \b UCAxCTL1 register.\r
160 //!\r
161 //! \return STATUS_SUCCESS or STATUS_FAIL of the initialization process\r
162 //\r
163 //*****************************************************************************\r
164 bool EUSCI_A_UART_init(uint16_t baseAddress, EUSCI_A_UART_initParam *param)\r
165 {\r
166 assert(param != 0);\r
167 \r
168 assert(\r
169 (EUSCI_A_UART_MODE == param->uartMode) ||\r
170 (EUSCI_A_UART_IDLE_LINE_MULTI_PROCESSOR_MODE == param->uartMode) ||\r
171 (EUSCI_A_UART_ADDRESS_BIT_MULTI_PROCESSOR_MODE == param->uartMode) ||\r
172 (EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE == param->uartMode)\r
173 );\r
174 \r
175 assert(\r
176 (EUSCI_A_UART_CLOCKSOURCE_ACLK == param->selectClockSource) ||\r
177 (EUSCI_A_UART_CLOCKSOURCE_SMCLK == param->selectClockSource)\r
178 );\r
179 \r
180 assert(\r
181 (EUSCI_A_UART_MSB_FIRST == param->msborLsbFirst) ||\r
182 (EUSCI_A_UART_LSB_FIRST == param->msborLsbFirst)\r
183 );\r
184 \r
185 assert(\r
186 (EUSCI_A_UART_ONE_STOP_BIT == param->numberofStopBits) ||\r
187 (EUSCI_A_UART_TWO_STOP_BITS == param->numberofStopBits)\r
188 );\r
189 \r
190 assert(\r
191 (EUSCI_A_UART_NO_PARITY == param->parity) ||\r
192 (EUSCI_A_UART_ODD_PARITY == param->parity) ||\r
193 (EUSCI_A_UART_EVEN_PARITY == param->parity)\r
194 );\r
195 \r
196 bool retVal = STATUS_SUCCESS;\r
197 \r
198 //Disable the USCI Module\r
199 HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCSWRST;\r
200 \r
201 //Clock source select\r
202 HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCSSEL_3;\r
203 HWREG16(baseAddress + OFS_UCAxCTLW0) |= param->selectClockSource;\r
204 \r
205 //MSB, LSB select\r
206 HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCMSB;\r
207 HWREG16(baseAddress + OFS_UCAxCTLW0) |= param->msborLsbFirst;\r
208 \r
209 //UCSPB = 0(1 stop bit) OR 1(2 stop bits)\r
210 HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCSPB;\r
211 HWREG16(baseAddress + OFS_UCAxCTLW0) |= param->numberofStopBits;\r
212 \r
213 //Parity\r
214 switch (param->parity) {\r
215 case EUSCI_A_UART_NO_PARITY:\r
216 //No Parity\r
217 HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCPEN;\r
218 break;\r
219 case EUSCI_A_UART_ODD_PARITY:\r
220 //Odd Parity\r
221 HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCPEN;\r
222 HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCPAR;\r
223 break;\r
224 case EUSCI_A_UART_EVEN_PARITY:\r
225 //Even Parity\r
226 HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCPEN;\r
227 HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCPAR;\r
228 break;\r
229 }\r
230 \r
231 //BaudRate Control Register\r
232 HWREG16(baseAddress + OFS_UCAxBRW ) = param->clockPrescalar;\r
233 //Modulation Control Register\r
234 HWREG16(baseAddress + OFS_UCAxMCTLW) = ((param->secondModReg << 8)\r
235 + (param->firstModReg << 4) + param->overSampling );\r
236 \r
237 //Asynchronous mode & 8 bit character select & clear mode\r
238 HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCSYNC +\r
239 UC7BIT +\r
240 UCMODE_3\r
241 );\r
242 \r
243 //Configure UART mode.\r
244 HWREG16(baseAddress + OFS_UCAxCTLW0) |= param->uartMode;\r
245 \r
246 //Reset UCRXIE, UCBRKIE, UCDORM, UCTXADDR, UCTXBRK\r
247 HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCRXEIE + UCBRKIE + UCDORM +\r
248 UCTXADDR + UCTXBRK\r
249 );\r
250 \r
251 return retVal;\r
252 }\r
253 //*****************************************************************************\r
254 //\r
255 //! \brief Transmits a byte from the UART Module.\r
256 //!\r
257 //! This function will place the supplied data into UART transmit data register\r
258 //! to start transmission\r
259 //!\r
260 //! \param baseAddress is the base address of the EUSCI_A_UART module.\r
261 //! \param transmitData data to be transmitted from the UART module\r
262 //!\r
263 //! Modified bits of \b UCAxTXBUF register.\r
264 //!\r
265 //! \return None\r
266 //\r
267 //*****************************************************************************\r
268 void EUSCI_A_UART_transmitData( uint16_t baseAddress,\r
269 uint8_t transmitData\r
270 )\r
271 {\r
272 //If interrupts are not used, poll for flags\r
273 if (!(HWREG16(baseAddress + OFS_UCAxIE) & UCTXIE))\r
274 //Poll for transmit interrupt flag\r
275 while (!(HWREG16(baseAddress + OFS_UCAxIFG) & UCTXIFG)) ;\r
276 \r
277 HWREG16(baseAddress + OFS_UCAxTXBUF) = transmitData;\r
278 }\r
279 \r
280 //*****************************************************************************\r
281 //\r
282 //! \brief Receives a byte that has been sent to the UART Module.\r
283 //!\r
284 //! This function reads a byte of data from the UART receive data Register.\r
285 //!\r
286 //! \param baseAddress is the base address of the EUSCI_A_UART module.\r
287 //!\r
288 //! Modified bits of \b UCAxRXBUF register.\r
289 //!\r
290 //! \return Returns the byte received from by the UART module, cast as an\r
291 //! uint8_t.\r
292 //\r
293 //*****************************************************************************\r
294 uint8_t EUSCI_A_UART_receiveData(uint16_t baseAddress)\r
295 {\r
296 //If interrupts are not used, poll for flags\r
297 if (!(HWREG16(baseAddress + OFS_UCAxIE) & UCRXIE))\r
298 //Poll for receive interrupt flag\r
299 while (!(HWREG16(baseAddress + OFS_UCAxIFG) & UCRXIFG)) ;\r
300 \r
301 return HWREG16(baseAddress + OFS_UCAxRXBUF);\r
302 }\r
303 \r
304 //*****************************************************************************\r
305 //\r
306 //! \brief Enables individual UART interrupt sources.\r
307 //!\r
308 //! Enables the indicated UART interrupt sources. The interrupt flag is first\r
309 //! and then the corresponding interrupt is enabled. Only the sources that are\r
310 //! enabled can be reflected to the processor interrupt; disabled sources have\r
311 //! no effect on the processor. Does not clear interrupt flags.\r
312 //!\r
313 //! \param baseAddress is the base address of the EUSCI_A_UART module.\r
314 //! \param mask is the bit mask of the interrupt sources to be enabled.\r
315 //! Mask value is the logical OR of any of the following:\r
316 //! - \b EUSCI_A_UART_RECEIVE_INTERRUPT - Receive interrupt\r
317 //! - \b EUSCI_A_UART_TRANSMIT_INTERRUPT - Transmit interrupt\r
318 //! - \b EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT - Receive\r
319 //! erroneous-character interrupt enable\r
320 //! - \b EUSCI_A_UART_BREAKCHAR_INTERRUPT - Receive break character\r
321 //! interrupt enable\r
322 //! - \b EUSCI_A_UART_STARTBIT_INTERRUPT - Start bit received interrupt\r
323 //! enable\r
324 //! - \b EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT - Transmit complete\r
325 //! interrupt enable\r
326 //!\r
327 //! Modified bits of \b UCAxCTL1 register and bits of \b UCAxIE register.\r
328 //!\r
329 //! \return None\r
330 //\r
331 //*****************************************************************************\r
332 void EUSCI_A_UART_enableInterrupt(uint16_t baseAddress,\r
333 uint8_t mask\r
334 )\r
335 {\r
336 assert(!(mask & ~(EUSCI_A_UART_RECEIVE_INTERRUPT\r
337 | EUSCI_A_UART_TRANSMIT_INTERRUPT\r
338 | EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT\r
339 | EUSCI_A_UART_BREAKCHAR_INTERRUPT\r
340 | EUSCI_A_UART_STARTBIT_INTERRUPT\r
341 | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT)));\r
342 \r
343 uint8_t locMask;\r
344 \r
345 locMask = (mask & (EUSCI_A_UART_RECEIVE_INTERRUPT\r
346 | EUSCI_A_UART_TRANSMIT_INTERRUPT\r
347 | EUSCI_A_UART_STARTBIT_INTERRUPT\r
348 | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT));\r
349 \r
350 HWREG16(baseAddress + OFS_UCAxIE) |= locMask;\r
351 \r
352 locMask = (mask & (EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT\r
353 | EUSCI_A_UART_BREAKCHAR_INTERRUPT));\r
354 HWREG16(baseAddress + OFS_UCAxCTLW0) |= locMask;\r
355 \r
356 }\r
357 \r
358 //*****************************************************************************\r
359 //\r
360 //! \brief Disables individual UART interrupt sources.\r
361 //!\r
362 //! Disables the indicated UART interrupt sources. Only the sources that are\r
363 //! enabled can be reflected to the processor interrupt; disabled sources have\r
364 //! no effect on the processor.\r
365 //!\r
366 //! \param baseAddress is the base address of the EUSCI_A_UART module.\r
367 //! \param mask is the bit mask of the interrupt sources to be disabled.\r
368 //! Mask value is the logical OR of any of the following:\r
369 //! - \b EUSCI_A_UART_RECEIVE_INTERRUPT - Receive interrupt\r
370 //! - \b EUSCI_A_UART_TRANSMIT_INTERRUPT - Transmit interrupt\r
371 //! - \b EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT - Receive\r
372 //! erroneous-character interrupt enable\r
373 //! - \b EUSCI_A_UART_BREAKCHAR_INTERRUPT - Receive break character\r
374 //! interrupt enable\r
375 //! - \b EUSCI_A_UART_STARTBIT_INTERRUPT - Start bit received interrupt\r
376 //! enable\r
377 //! - \b EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT - Transmit complete\r
378 //! interrupt enable\r
379 //!\r
380 //! Modified bits of \b UCAxCTL1 register and bits of \b UCAxIE register.\r
381 //!\r
382 //! \return None\r
383 //\r
384 //*****************************************************************************\r
385 void EUSCI_A_UART_disableInterrupt(uint16_t baseAddress,\r
386 uint8_t mask\r
387 )\r
388 {\r
389 assert(!(mask & ~(EUSCI_A_UART_RECEIVE_INTERRUPT\r
390 | EUSCI_A_UART_TRANSMIT_INTERRUPT\r
391 | EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT\r
392 | EUSCI_A_UART_BREAKCHAR_INTERRUPT\r
393 | EUSCI_A_UART_STARTBIT_INTERRUPT\r
394 | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT)));\r
395 \r
396 uint8_t locMask;\r
397 \r
398 locMask = (mask & (EUSCI_A_UART_RECEIVE_INTERRUPT\r
399 | EUSCI_A_UART_TRANSMIT_INTERRUPT\r
400 | EUSCI_A_UART_STARTBIT_INTERRUPT\r
401 | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT));\r
402 HWREG16(baseAddress + OFS_UCAxIE) &= ~locMask;\r
403 \r
404 \r
405 locMask = (mask & (EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT\r
406 | EUSCI_A_UART_BREAKCHAR_INTERRUPT));\r
407 HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~locMask;\r
408 }\r
409 \r
410 //*****************************************************************************\r
411 //\r
412 //! \brief Gets the current UART interrupt status.\r
413 //!\r
414 //! This returns the interrupt status for the UART module based on which flag\r
415 //! is passed.\r
416 //!\r
417 //! \param baseAddress is the base address of the EUSCI_A_UART module.\r
418 //! \param mask is the masked interrupt flag status to be returned.\r
419 //! Mask value is the logical OR of any of the following:\r
420 //! - \b EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG\r
421 //! - \b EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG\r
422 //! - \b EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG\r
423 //! - \b EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG\r
424 //!\r
425 //! Modified bits of \b UCAxIFG register.\r
426 //!\r
427 //! \return Logical OR of any of the following:\r
428 //! - \b EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG\r
429 //! - \b EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG\r
430 //! - \b EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG\r
431 //! - \b EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG\r
432 //! \n indicating the status of the masked flags\r
433 //\r
434 //*****************************************************************************\r
435 uint8_t EUSCI_A_UART_getInterruptStatus(uint16_t baseAddress,\r
436 uint8_t mask)\r
437 {\r
438 assert(!(mask & ~(EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG\r
439 | EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG\r
440 | EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG\r
441 | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG)));\r
442 \r
443 return HWREG16(baseAddress + OFS_UCAxIFG) & mask;\r
444 }\r
445 \r
446 //*****************************************************************************\r
447 //\r
448 //! \brief Clears UART interrupt sources.\r
449 //!\r
450 //! The UART interrupt source is cleared, so that it no longer asserts. The\r
451 //! highest interrupt flag is automatically cleared when an interrupt vector\r
452 //! generator is used.\r
453 //!\r
454 //! \param baseAddress is the base address of the EUSCI_A_UART module.\r
455 //! \param mask is a bit mask of the interrupt sources to be cleared.\r
456 //! Mask value is the logical OR of any of the following:\r
457 //! - \b EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG\r
458 //! - \b EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG\r
459 //! - \b EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG\r
460 //! - \b EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG\r
461 //!\r
462 //! Modified bits of \b UCAxIFG register.\r
463 //!\r
464 //! \return None\r
465 //\r
466 //*****************************************************************************\r
467 void EUSCI_A_UART_clearInterruptFlag(uint16_t baseAddress, uint8_t mask)\r
468 {\r
469 assert(!(mask & ~(EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG\r
470 | EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG\r
471 | EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG\r
472 | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG)));\r
473 \r
474 //Clear the UART interrupt source.\r
475 HWREG16(baseAddress + OFS_UCAxIFG) &= ~(mask);\r
476 }\r
477 \r
478 //*****************************************************************************\r
479 //\r
480 //! \brief Enables the UART block.\r
481 //!\r
482 //! This will enable operation of the UART block.\r
483 //!\r
484 //! \param baseAddress is the base address of the EUSCI_A_UART module.\r
485 //!\r
486 //! Modified bits are \b UCSWRST of \b UCAxCTL1 register.\r
487 //!\r
488 //! \return None\r
489 //\r
490 //*****************************************************************************\r
491 void EUSCI_A_UART_enable(uint16_t baseAddress)\r
492 {\r
493 //Reset the UCSWRST bit to enable the USCI Module\r
494 HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCSWRST);\r
495 }\r
496 \r
497 //*****************************************************************************\r
498 //\r
499 //! \brief Disables the UART block.\r
500 //!\r
501 //! This will disable operation of the UART block.\r
502 //!\r
503 //! \param baseAddress is the base address of the EUSCI_A_UART module.\r
504 //!\r
505 //! Modified bits are \b UCSWRST of \b UCAxCTL1 register.\r
506 //!\r
507 //! \return None\r
508 //\r
509 //*****************************************************************************\r
510 void EUSCI_A_UART_disable(uint16_t baseAddress)\r
511 {\r
512 //Set the UCSWRST bit to disable the USCI Module\r
513 HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCSWRST;\r
514 }\r
515 \r
516 //*****************************************************************************\r
517 //\r
518 //! \brief Gets the current UART status flags.\r
519 //!\r
520 //! This returns the status for the UART module based on which flag is passed.\r
521 //!\r
522 //! \param baseAddress is the base address of the EUSCI_A_UART module.\r
523 //! \param mask is the masked interrupt flag status to be returned.\r
524 //! Mask value is the logical OR of any of the following:\r
525 //! - \b EUSCI_A_UART_LISTEN_ENABLE\r
526 //! - \b EUSCI_A_UART_FRAMING_ERROR\r
527 //! - \b EUSCI_A_UART_OVERRUN_ERROR\r
528 //! - \b EUSCI_A_UART_PARITY_ERROR\r
529 //! - \b EUSCI_A_UART_BREAK_DETECT\r
530 //! - \b EUSCI_A_UART_RECEIVE_ERROR\r
531 //! - \b EUSCI_A_UART_ADDRESS_RECEIVED\r
532 //! - \b EUSCI_A_UART_IDLELINE\r
533 //! - \b EUSCI_A_UART_BUSY\r
534 //!\r
535 //! Modified bits of \b UCAxSTAT register.\r
536 //!\r
537 //! \return Logical OR of any of the following:\r
538 //! - \b EUSCI_A_UART_LISTEN_ENABLE\r
539 //! - \b EUSCI_A_UART_FRAMING_ERROR\r
540 //! - \b EUSCI_A_UART_OVERRUN_ERROR\r
541 //! - \b EUSCI_A_UART_PARITY_ERROR\r
542 //! - \b EUSCI_A_UART_BREAK_DETECT\r
543 //! - \b EUSCI_A_UART_RECEIVE_ERROR\r
544 //! - \b EUSCI_A_UART_ADDRESS_RECEIVED\r
545 //! - \b EUSCI_A_UART_IDLELINE\r
546 //! - \b EUSCI_A_UART_BUSY\r
547 //! \n indicating the status of the masked interrupt flags\r
548 //\r
549 //*****************************************************************************\r
550 uint8_t EUSCI_A_UART_queryStatusFlags(uint16_t baseAddress,\r
551 uint8_t mask)\r
552 {\r
553 assert( 0x00 != mask && (EUSCI_A_UART_LISTEN_ENABLE +\r
554 EUSCI_A_UART_FRAMING_ERROR +\r
555 EUSCI_A_UART_OVERRUN_ERROR +\r
556 EUSCI_A_UART_PARITY_ERROR +\r
557 EUSCI_A_UART_BREAK_DETECT +\r
558 EUSCI_A_UART_RECEIVE_ERROR +\r
559 EUSCI_A_UART_ADDRESS_RECEIVED +\r
560 EUSCI_A_UART_IDLELINE +\r
561 EUSCI_A_UART_BUSY\r
562 ));\r
563 \r
564 return HWREG16(baseAddress + OFS_UCAxSTATW) & mask;\r
565 }\r
566 \r
567 //*****************************************************************************\r
568 //\r
569 //! \brief Sets the UART module in dormant mode\r
570 //!\r
571 //! Puts USCI in sleep mode Only characters that are preceded by an idle-line\r
572 //! or with address bit set UCRXIFG. In UART mode with automatic baud-rate\r
573 //! detection, only the combination of a break and sync field sets UCRXIFG.\r
574 //!\r
575 //! \param baseAddress is the base address of the EUSCI_A_UART module.\r
576 //!\r
577 //! Modified bits of \b UCAxCTL1 register.\r
578 //!\r
579 //! \return None\r
580 //\r
581 //*****************************************************************************\r
582 void EUSCI_A_UART_setDormant(uint16_t baseAddress)\r
583 {\r
584 HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCDORM;\r
585 }\r
586 \r
587 //*****************************************************************************\r
588 //\r
589 //! \brief Re-enables UART module from dormant mode\r
590 //!\r
591 //! Not dormant. All received characters set UCRXIFG.\r
592 //!\r
593 //! \param baseAddress is the base address of the EUSCI_A_UART module.\r
594 //!\r
595 //! Modified bits are \b UCDORM of \b UCAxCTL1 register.\r
596 //!\r
597 //! \return None\r
598 //\r
599 //*****************************************************************************\r
600 void EUSCI_A_UART_resetDormant(uint16_t baseAddress)\r
601 {\r
602 HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCDORM;\r
603 }\r
604 \r
605 //*****************************************************************************\r
606 //\r
607 //! \brief Transmits the next byte to be transmitted marked as address\r
608 //! depending on selected multiprocessor mode\r
609 //!\r
610 //! \param baseAddress is the base address of the EUSCI_A_UART module.\r
611 //! \param transmitAddress is the next byte to be transmitted\r
612 //!\r
613 //! Modified bits of \b UCAxTXBUF register and bits of \b UCAxCTL1 register.\r
614 //!\r
615 //! \return None\r
616 //\r
617 //*****************************************************************************\r
618 void EUSCI_A_UART_transmitAddress(uint16_t baseAddress,\r
619 uint8_t transmitAddress)\r
620 {\r
621 //Set UCTXADDR bit\r
622 HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCTXADDR;\r
623 \r
624 //Place next byte to be sent into the transmit buffer\r
625 HWREG16(baseAddress + OFS_UCAxTXBUF) = transmitAddress;\r
626 }\r
627 \r
628 //*****************************************************************************\r
629 //\r
630 //! \brief Transmit break.\r
631 //!\r
632 //! Transmits a break with the next write to the transmit buffer. In UART mode\r
633 //! with automatic baud-rate detection,\r
634 //! EUSCI_A_UART_AUTOMATICBAUDRATE_SYNC(0x55) must be written into UCAxTXBUF to\r
635 //! generate the required break/sync fields. Otherwise, DEFAULT_SYNC(0x00) must\r
636 //! be written into the transmit buffer. Also ensures module is ready for\r
637 //! transmitting the next data.\r
638 //!\r
639 //! \param baseAddress is the base address of the EUSCI_A_UART module.\r
640 //!\r
641 //! Modified bits of \b UCAxTXBUF register and bits of \b UCAxCTL1 register.\r
642 //!\r
643 //! \return None\r
644 //\r
645 //*****************************************************************************\r
646 void EUSCI_A_UART_transmitBreak(uint16_t baseAddress)\r
647 {\r
648 //Set UCTXADDR bit\r
649 HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCTXBRK;\r
650 \r
651 //If current mode is automatic baud-rate detection\r
652 if (EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE ==\r
653 (HWREG16(baseAddress + OFS_UCAxCTLW0) &\r
654 EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE))\r
655 HWREG16(baseAddress + OFS_UCAxTXBUF) = EUSCI_A_UART_AUTOMATICBAUDRATE_SYNC;\r
656 else\r
657 HWREG16(baseAddress + OFS_UCAxTXBUF) = DEFAULT_SYNC;\r
658 \r
659 //If interrupts are not used, poll for flags\r
660 if (!(HWREG16(baseAddress + OFS_UCAxIE) & UCTXIE))\r
661 //Poll for transmit interrupt flag\r
662 while (!(HWREG16(baseAddress + OFS_UCAxIFG) & UCTXIFG)) ;\r
663 }\r
664 \r
665 //*****************************************************************************\r
666 //\r
667 //! \brief Returns the address of the RX Buffer of the UART for the DMA module.\r
668 //!\r
669 //! Returns the address of the UART RX Buffer. This can be used in conjunction\r
670 //! with the DMA to store the received data directly to memory.\r
671 //!\r
672 //! \param baseAddress is the base address of the EUSCI_A_UART module.\r
673 //!\r
674 //! \return Address of RX Buffer\r
675 //\r
676 //*****************************************************************************\r
677 uint32_t EUSCI_A_UART_getReceiveBufferAddress(uint16_t baseAddress)\r
678 {\r
679 return baseAddress + OFS_UCAxRXBUF;\r
680 }\r
681 \r
682 //*****************************************************************************\r
683 //\r
684 //! \brief Returns the address of the TX Buffer of the UART for the DMA module.\r
685 //!\r
686 //! Returns the address of the UART TX Buffer. This can be used in conjunction\r
687 //! with the DMA to obtain transmitted data directly from memory.\r
688 //!\r
689 //! \param baseAddress is the base address of the EUSCI_A_UART module.\r
690 //!\r
691 //! \return Address of TX Buffer\r
692 //\r
693 //*****************************************************************************\r
694 uint32_t EUSCI_A_UART_getTransmitBufferAddress(uint16_t baseAddress)\r
695 {\r
696 return baseAddress + OFS_UCAxTXBUF;\r
697 }\r
698 \r
699 //*****************************************************************************\r
700 //\r
701 //! \brief Sets the deglitch time\r
702 //!\r
703 //! \param baseAddress is the base address of the EUSCI_A_UART module.\r
704 //! \param deglitchTime is the selected deglitch time\r
705 //! Valid values are:\r
706 //! - \b EUSCI_A_UART_DEGLITCH_TIME_2ns\r
707 //! - \b EUSCI_A_UART_DEGLITCH_TIME_50ns\r
708 //! - \b EUSCI_A_UART_DEGLITCH_TIME_100ns\r
709 //! - \b EUSCI_A_UART_DEGLITCH_TIME_200ns\r
710 //!\r
711 //! \return None\r
712 //\r
713 //*****************************************************************************\r
714 void EUSCI_A_UART_selectDeglitchTime(uint16_t baseAddress,\r
715 uint16_t deglitchTime\r
716 )\r
717 {\r
718 assert((EUSCI_A_UART_DEGLITCH_TIME_2ns == deglitchTime) ||\r
719 (EUSCI_A_UART_DEGLITCH_TIME_50ns == deglitchTime) ||\r
720 (EUSCI_A_UART_DEGLITCH_TIME_100ns == deglitchTime) ||\r
721 (EUSCI_A_UART_DEGLITCH_TIME_200ns == deglitchTime)\r
722 );\r
723 \r
724 HWREG16(baseAddress + OFS_UCAxCTLW1) &= ~(UCGLIT1 + UCGLIT0);\r
725 \r
726 HWREG16(baseAddress + OFS_UCAxCTLW1) |= deglitchTime;\r
727 }\r
728 \r
729 \r
730 #endif\r
731 //*****************************************************************************\r
732 //\r
733 //! Close the doxygen group for eusci_a_uart_api\r
734 //! @}\r
735 //\r
736 //*****************************************************************************\r