1 /* --COPYRIGHT--,BSD\r
2 * Copyright (c) 2014, Texas Instruments Incorporated\r
3 * All rights reserved.\r
4 *\r
5 * Redistribution and use in source and binary forms, with or without\r
6 * modification, are permitted provided that the following conditions\r
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10 * notice, this list of conditions and the following disclaimer.\r
11 *\r
12 * * Redistributions in binary form must reproduce the above copyright\r
13 * notice, this list of conditions and the following disclaimer in the\r
14 * documentation and/or other materials provided with the distribution.\r
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31 * --/COPYRIGHT--*/\r
32 //*****************************************************************************\r
33 //\r
34 // pmm.c - Driver for the pmm Module.\r
35 //\r
36 //*****************************************************************************\r
37 \r
38 //*****************************************************************************\r
39 //\r
40 //! \addtogroup pmm_api\r
41 //! @{\r
42 //\r
43 //*****************************************************************************\r
44 \r
45 #include "inc/hw_regaccess.h"\r
46 #include "inc/hw_memmap.h"\r
47 \r
48 #ifndef DRIVERLIB_LEGACY_MODE\r
49 \r
50 #ifdef __MSP430_HAS_PMM__\r
51 #include "pmm.h"\r
52 \r
53 #include <assert.h>\r
54 \r
55 //*****************************************************************************\r
56 //\r
57 //! \brief Enables the low-side SVS circuitry\r
58 //!\r
59 //!\r
60 //! Modified bits of \b PMMCTL0 register and bits of \b SVSMLCTL register.\r
61 //!\r
62 //! \return None\r
63 //\r
64 //*****************************************************************************\r
65 void PMM_enableSvsL(void)\r
66 {\r
67 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;\r
68 HWREG16(PMM_BASE + OFS_SVSMLCTL) |= SVSLE;\r
69 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;\r
70 }\r
71 \r
72 //*****************************************************************************\r
73 //\r
74 //! \brief Disables the low-side SVS circuitry\r
75 //!\r
76 //!\r
77 //! Modified bits of \b PMMCTL0 register and bits of \b SVSMLCTL register.\r
78 //!\r
79 //! \return None\r
80 //\r
81 //*****************************************************************************\r
82 void PMM_disableSvsL(void)\r
83 {\r
84 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;\r
85 HWREG16(PMM_BASE + OFS_SVSMLCTL) &= ~SVSLE;\r
86 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;\r
87 }\r
88 \r
89 //*****************************************************************************\r
90 //\r
91 //! \brief Enables the low-side SVM circuitry\r
92 //!\r
93 //!\r
94 //! Modified bits of \b PMMCTL0 register and bits of \b SVSMLCTL register.\r
95 //!\r
96 //! \return None\r
97 //\r
98 //*****************************************************************************\r
99 void PMM_enableSvmL(void)\r
100 {\r
101 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;\r
102 HWREG16(PMM_BASE + OFS_SVSMLCTL) |= SVMLE;\r
103 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;\r
104 }\r
105 \r
106 //*****************************************************************************\r
107 //\r
108 //! \brief Disables the low-side SVM circuitry\r
109 //!\r
110 //!\r
111 //! Modified bits of \b PMMCTL0 register and bits of \b SVSMLCTL register.\r
112 //!\r
113 //! \return None\r
114 //\r
115 //*****************************************************************************\r
116 void PMM_disableSvmL(void)\r
117 {\r
118 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;\r
119 HWREG16(PMM_BASE + OFS_SVSMLCTL) &= ~SVMLE;\r
120 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;\r
121 }\r
122 \r
123 //*****************************************************************************\r
124 //\r
125 //! \brief Enables the high-side SVS circuitry\r
126 //!\r
127 //!\r
128 //! Modified bits of \b PMMCTL0 register and bits of \b SVSMHCTL register.\r
129 //!\r
130 //! \return None\r
131 //\r
132 //*****************************************************************************\r
133 void PMM_enableSvsH(void)\r
134 {\r
135 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;\r
136 HWREG16(PMM_BASE + OFS_SVSMHCTL) |= SVSHE;\r
137 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;\r
138 }\r
139 \r
140 //*****************************************************************************\r
141 //\r
142 //! \brief Disables the high-side SVS circuitry\r
143 //!\r
144 //!\r
145 //! Modified bits of \b PMMCTL0 register and bits of \b SVSMHCTL register.\r
146 //!\r
147 //! \return None\r
148 //\r
149 //*****************************************************************************\r
150 void PMM_disableSvsH(void)\r
151 {\r
152 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;\r
153 HWREG16(PMM_BASE + OFS_SVSMHCTL) &= ~SVSHE;\r
154 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;\r
155 }\r
156 \r
157 //*****************************************************************************\r
158 //\r
159 //! \brief Enables the high-side SVM circuitry\r
160 //!\r
161 //!\r
162 //! Modified bits of \b PMMCTL0 register and bits of \b SVSMHCTL register.\r
163 //!\r
164 //! \return None\r
165 //\r
166 //*****************************************************************************\r
167 void PMM_enableSvmH(void)\r
168 {\r
169 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;\r
170 HWREG16(PMM_BASE + OFS_SVSMHCTL) |= SVMHE;\r
171 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;\r
172 }\r
173 \r
174 //*****************************************************************************\r
175 //\r
176 //! \brief Disables the high-side SVM circuitry\r
177 //!\r
178 //!\r
179 //! Modified bits of \b PMMCTL0 register and bits of \b SVSMHCTL register.\r
180 //!\r
181 //! \return None\r
182 //\r
183 //*****************************************************************************\r
184 void PMM_disableSvmH(void)\r
185 {\r
186 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;\r
187 HWREG16(PMM_BASE + OFS_SVSMHCTL) &= ~SVMHE;\r
188 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;\r
189 }\r
190 \r
191 //*****************************************************************************\r
192 //\r
193 //! \brief Enables the low-side SVS and SVM circuitry\r
194 //!\r
195 //!\r
196 //! Modified bits of \b PMMCTL0 register and bits of \b SVSMLCTL register.\r
197 //!\r
198 //! \return None\r
199 //\r
200 //*****************************************************************************\r
201 void PMM_enableSvsLSvmL(void)\r
202 {\r
203 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;\r
204 HWREG16(PMM_BASE + OFS_SVSMLCTL) |= (SVSLE + SVMLE);\r
205 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;\r
206 }\r
207 \r
208 //*****************************************************************************\r
209 //\r
210 //! \brief Disables the low-side SVS and SVM circuitry\r
211 //!\r
212 //!\r
213 //! Modified bits of \b PMMCTL0 register and bits of \b SVSMLCTL register.\r
214 //!\r
215 //! \return None\r
216 //\r
217 //*****************************************************************************\r
218 void PMM_disableSvsLSvmL(void)\r
219 {\r
220 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;\r
221 HWREG16(PMM_BASE + OFS_SVSMLCTL) &= ~(SVSLE + SVMLE);\r
222 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;\r
223 }\r
224 \r
225 //*****************************************************************************\r
226 //\r
227 //! \brief Enables the high-side SVS and SVM circuitry\r
228 //!\r
229 //!\r
230 //! Modified bits of \b PMMCTL0 register and bits of \b SVSMHCTL register.\r
231 //!\r
232 //! \return None\r
233 //\r
234 //*****************************************************************************\r
235 void PMM_enableSvsHSvmH(void)\r
236 {\r
237 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;\r
238 HWREG16(PMM_BASE + OFS_SVSMHCTL) |= (SVSHE + SVMHE);\r
239 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;\r
240 }\r
241 \r
242 //*****************************************************************************\r
243 //\r
244 //! \brief Disables the high-side SVS and SVM circuitry\r
245 //!\r
246 //!\r
247 //! Modified bits of \b PMMCTL0 register and bits of \b SVSMHCTL register.\r
248 //!\r
249 //! \return None\r
250 //\r
251 //*****************************************************************************\r
252 void PMM_disableSvsHSvmH(void)\r
253 {\r
254 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;\r
255 HWREG16(PMM_BASE + OFS_SVSMHCTL) &= ~(SVSHE + SVMHE);\r
256 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;\r
257 }\r
258 \r
259 //*****************************************************************************\r
260 //\r
261 //! \brief Enables the POR signal generation when a low-voltage event is\r
262 //! registered by the low-side SVS\r
263 //!\r
264 //!\r
265 //! Modified bits of \b PMMCTL0 register and bits of \b PMMIE register.\r
266 //!\r
267 //! \return None\r
268 //\r
269 //*****************************************************************************\r
270 void PMM_enableSvsLReset(void)\r
271 {\r
272 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;\r
273 HWREG16(PMM_BASE + OFS_PMMRIE) |= SVSLPE;\r
274 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;\r
275 }\r
276 \r
277 //*****************************************************************************\r
278 //\r
279 //! \brief Disables the POR signal generation when a low-voltage event is\r
280 //! registered by the low-side SVS\r
281 //!\r
282 //!\r
283 //! Modified bits of \b PMMCTL0 register and bits of \b PMMIE register.\r
284 //!\r
285 //! \return None\r
286 //\r
287 //*****************************************************************************\r
288 void PMM_disableSvsLReset(void)\r
289 {\r
290 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;\r
291 HWREG16(PMM_BASE + OFS_PMMRIE) &= ~SVSLPE;\r
292 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;\r
293 }\r
294 \r
295 //*****************************************************************************\r
296 //\r
297 //! \brief Enables the interrupt generation when a low-voltage event is\r
298 //! registered by the low-side SVM\r
299 //!\r
300 //!\r
301 //! Modified bits of \b PMMCTL0 register and bits of \b PMMIE register.\r
302 //!\r
303 //! \return None\r
304 //\r
305 //*****************************************************************************\r
306 void PMM_enableSvmLInterrupt(void)\r
307 {\r
308 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;\r
309 HWREG16(PMM_BASE + OFS_PMMRIE) |= SVMLIE;\r
310 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;\r
311 }\r
312 \r
313 //*****************************************************************************\r
314 //\r
315 //! \brief Disables the interrupt generation when a low-voltage event is\r
316 //! registered by the low-side SVM\r
317 //!\r
318 //!\r
319 //! Modified bits of \b PMMCTL0 register and bits of \b PMMIE register.\r
320 //!\r
321 //! \return None\r
322 //\r
323 //*****************************************************************************\r
324 void PMM_disableSvmLInterrupt(void)\r
325 {\r
326 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;\r
327 HWREG16(PMM_BASE + OFS_PMMRIE) &= ~SVMLIE;\r
328 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;\r
329 }\r
330 \r
331 //*****************************************************************************\r
332 //\r
333 //! \brief Enables the POR signal generation when a low-voltage event is\r
334 //! registered by the high-side SVS\r
335 //!\r
336 //!\r
337 //! Modified bits of \b PMMCTL0 register and bits of \b PMMIE register.\r
338 //!\r
339 //! \return None\r
340 //\r
341 //*****************************************************************************\r
342 void PMM_enableSvsHReset(void)\r
343 {\r
344 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;\r
345 HWREG16(PMM_BASE + OFS_PMMRIE) |= SVSHPE;\r
346 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;\r
347 }\r
348 \r
349 //*****************************************************************************\r
350 //\r
351 //! \brief Disables the POR signal generation when a low-voltage event is\r
352 //! registered by the high-side SVS\r
353 //!\r
354 //!\r
355 //! Modified bits of \b PMMCTL0 register and bits of \b PMMIE register.\r
356 //!\r
357 //! \return None\r
358 //\r
359 //*****************************************************************************\r
360 void PMM_disableSvsHReset(void)\r
361 {\r
362 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;\r
363 HWREG16(PMM_BASE + OFS_PMMRIE) &= ~SVSHPE;\r
364 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;\r
365 }\r
366 \r
367 //*****************************************************************************\r
368 //\r
369 //! \brief Enables the interrupt generation when a low-voltage event is\r
370 //! registered by the high-side SVM\r
371 //!\r
372 //!\r
373 //! Modified bits of \b PMMCTL0 register and bits of \b PMMIE register.\r
374 //!\r
375 //! \return None\r
376 //\r
377 //*****************************************************************************\r
378 void PMM_enableSvmHInterrupt(void)\r
379 {\r
380 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;\r
381 HWREG16(PMM_BASE + OFS_PMMRIE) |= SVMHIE;\r
382 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;\r
383 }\r
384 \r
385 //*****************************************************************************\r
386 //\r
387 //! \brief Disables the interrupt generation when a low-voltage event is\r
388 //! registered by the high-side SVM\r
389 //!\r
390 //!\r
391 //! Modified bits of \b PMMCTL0 register and bits of \b PMMIE register.\r
392 //!\r
393 //! \return None\r
394 //\r
395 //*****************************************************************************\r
396 void PMM_disableSvmHInterrupt(void)\r
397 {\r
398 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;\r
399 HWREG16(PMM_BASE + OFS_PMMRIE) &= ~SVMHIE;\r
400 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;\r
401 }\r
402 \r
403 //*****************************************************************************\r
404 //\r
405 //! \brief Clear all interrupt flags for the PMM\r
406 //!\r
407 //!\r
408 //! Modified bits of \b PMMCTL0 register and bits of \b PMMIFG register.\r
409 //!\r
410 //! \return None\r
411 //\r
412 //*****************************************************************************\r
413 void PMM_clearPMMIFGS(void)\r
414 {\r
415 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;\r
416 HWREG16(PMM_BASE + OFS_PMMIFG) = 0;\r
417 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;\r
418 }\r
419 \r
420 //*****************************************************************************\r
421 //\r
422 //! \brief Enables supervisor low side in LPM with twake-up-fast from LPM2,\r
423 //! LPM3, and LPM4\r
424 //!\r
425 //!\r
426 //! Modified bits of \b PMMCTL0 register and bits of \b SVSMLCTL register.\r
427 //!\r
428 //! \return None\r
429 //\r
430 //*****************************************************************************\r
431 void PMM_SvsLEnabledInLPMFastWake(void)\r
432 {\r
433 //These settings use SVSH/LACE = 0\r
434 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;\r
435 HWREG16(PMM_BASE + OFS_SVSMLCTL) |= (SVSLFP + SVSLMD);\r
436 HWREG16(PMM_BASE + OFS_SVSMLCTL) &= ~SVSMLACE;\r
437 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;\r
438 }\r
439 \r
440 //*****************************************************************************\r
441 //\r
442 //! \brief Enables supervisor low side in LPM with twake-up-slow from LPM2,\r
443 //! LPM3, and LPM4\r
444 //!\r
445 //!\r
446 //! Modified bits of \b PMMCTL0 register and bits of \b SVSMLCTL register.\r
447 //!\r
448 //! \return None\r
449 //\r
450 //*****************************************************************************\r
451 void PMM_SvsLEnabledInLPMSlowWake(void)\r
452 {\r
453 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;\r
454 HWREG16(PMM_BASE + OFS_SVSMLCTL) |= SVSLMD;\r
455 HWREG16(PMM_BASE + OFS_SVSMLCTL) &= ~(SVSLFP + SVSMLACE);\r
456 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;\r
457 }\r
458 \r
459 //*****************************************************************************\r
460 //\r
461 //! \brief Disables supervisor low side in LPM with twake-up-fast from LPM2,\r
462 //! LPM3, and LPM4\r
463 //!\r
464 //!\r
465 //! Modified bits of \b PMMCTL0 register and bits of \b SVSMLCTL register.\r
466 //!\r
467 //! \return None\r
468 //\r
469 //*****************************************************************************\r
470 void PMM_SvsLDisabledInLPMFastWake(void)\r
471 {\r
472 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;\r
473 HWREG16(PMM_BASE + OFS_SVSMLCTL) |= SVSLFP;\r
474 HWREG16(PMM_BASE + OFS_SVSMLCTL) &= ~(SVSLMD + SVSMLACE);\r
475 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;\r
476 }\r
477 \r
478 //*****************************************************************************\r
479 //\r
480 //! \brief Disables supervisor low side in LPM with twake-up-slow from LPM2,\r
481 //! LPM3, and LPM4\r
482 //!\r
483 //!\r
484 //! Modified bits of \b PMMCTL0 register and bits of \b SVSMLCTL register.\r
485 //!\r
486 //! \return None\r
487 //\r
488 //*****************************************************************************\r
489 void PMM_SvsLDisabledInLPMSlowWake(void)\r
490 {\r
491 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;\r
492 HWREG16(PMM_BASE + OFS_SVSMLCTL) &= ~(SVSLFP + SVSMLACE + SVSLMD);\r
493 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;\r
494 }\r
495 \r
496 //*****************************************************************************\r
497 //\r
498 //! \brief Enables supervisor high side in LPM with tpd = 20 ?s(1)\r
499 //!\r
500 //!\r
501 //! Modified bits of \b PMMCTL0 register and bits of \b SVSMHCTL register.\r
502 //!\r
503 //! \return None\r
504 //\r
505 //*****************************************************************************\r
506 void PMM_SvsHEnabledInLPMNormPerf(void)\r
507 {\r
508 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;\r
509 HWREG16(PMM_BASE + OFS_SVSMHCTL) |= SVSHMD;\r
510 HWREG16(PMM_BASE + OFS_SVSMHCTL) &= ~(SVSMHACE + SVSHFP);\r
511 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;\r
512 }\r
513 \r
514 //*****************************************************************************\r
515 //\r
516 //! \brief Enables supervisor high side in LPM with tpd = 2.5 ?s(1)\r
517 //!\r
518 //!\r
519 //! Modified bits of \b PMMCTL0 register and bits of \b SVSMHCTL register.\r
520 //!\r
521 //! \return None\r
522 //\r
523 //*****************************************************************************\r
524 void PMM_SvsHEnabledInLPMFullPerf(void)\r
525 {\r
526 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;\r
527 HWREG16(PMM_BASE + OFS_SVSMHCTL) |= (SVSHMD + SVSHFP);\r
528 HWREG16(PMM_BASE + OFS_SVSMHCTL) &= ~SVSMHACE;\r
529 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;\r
530 }\r
531 \r
532 //*****************************************************************************\r
533 //\r
534 //! \brief Disables supervisor high side in LPM with tpd = 20 ?s(1)\r
535 //!\r
536 //!\r
537 //! Modified bits of \b PMMCTL0 register and bits of \b SVSMHCTL register.\r
538 //!\r
539 //! \return None\r
540 //\r
541 //*****************************************************************************\r
542 void PMM_SvsHDisabledInLPMNormPerf(void)\r
543 {\r
544 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;\r
545 HWREG16(PMM_BASE + OFS_SVSMHCTL) &= ~(SVSMHACE + SVSHFP + SVSHMD);\r
546 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;\r
547 }\r
548 \r
549 //*****************************************************************************\r
550 //\r
551 //! \brief Disables supervisor high side in LPM with tpd = 2.5 ?s(1)\r
552 //!\r
553 //!\r
554 //! Modified bits of \b PMMCTL0 register and bits of \b SVSMHCTL register.\r
555 //!\r
556 //! \return None\r
557 //\r
558 //*****************************************************************************\r
559 void PMM_SvsHDisabledInLPMFullPerf(void)\r
560 {\r
561 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;\r
562 HWREG16(PMM_BASE + OFS_SVSMHCTL) |= SVSHFP;\r
563 HWREG16(PMM_BASE + OFS_SVSMHCTL) &= ~(SVSMHACE + SVSHMD);\r
564 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;\r
565 }\r
566 \r
567 //*****************************************************************************\r
568 //\r
569 //! \brief Optimized to provide twake-up-fast from LPM2, LPM3, and LPM4 with\r
570 //! least power\r
571 //!\r
572 //!\r
573 //! Modified bits of \b PMMCTL0 register and bits of \b SVSMLCTL register.\r
574 //!\r
575 //! \return None\r
576 //\r
577 //*****************************************************************************\r
578 void PMM_SvsLOptimizedInLPMFastWake(void)\r
579 {\r
580 //These setting use SVSH/LACE = 1\r
581 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;\r
582 HWREG16(PMM_BASE + OFS_SVSMLCTL) |= (SVSLFP + SVSLMD + SVSMLACE);\r
583 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;\r
584 }\r
585 \r
586 //*****************************************************************************\r
587 //\r
588 //! \brief Optimized to provide tpd = 2.5 ?s(1) in LPM with least power\r
589 //!\r
590 //!\r
591 //! Modified bits of \b PMMCTL0 register and bits of \b SVSMLCTL register.\r
592 //!\r
593 //! \return None\r
594 //\r
595 //*****************************************************************************\r
596 void PMM_SvsHOptimizedInLPMFullPerf(void)\r
597 {\r
598 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;\r
599 HWREG16(PMM_BASE + OFS_SVSMHCTL) |= (SVSHMD + SVSHFP + SVSMHACE);\r
600 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;\r
601 }\r
602 \r
603 //*****************************************************************************\r
604 //\r
605 //! \brief Increase Vcore by one level\r
606 //!\r
607 //! \param level level to which Vcore needs to be increased\r
608 //! Valid values are:\r
609 //! - \b PMM_CORE_LEVEL_0 [Default]\r
610 //! - \b PMM_CORE_LEVEL_1\r
611 //! - \b PMM_CORE_LEVEL_2\r
612 //! - \b PMM_CORE_LEVEL_3\r
613 //!\r
614 //! Modified bits of \b PMMCTL0 register, bits of \b PMMIFG register, bits of\r
615 //! \b PMMRIE register, bits of \b SVSMHCTL register and bits of \b SVSMLCTL\r
616 //! register.\r
617 //!\r
618 //! \return STATUS_SUCCESS or STATUS_FAIL\r
619 //\r
620 //*****************************************************************************\r
621 uint16_t PMM_setVCoreUp( uint8_t level)\r
622 {\r
623 uint32_t PMMRIE_backup, SVSMHCTL_backup, SVSMLCTL_backup;\r
624 \r
625 //The code flow for increasing the Vcore has been altered to work around\r
626 //the erratum FLASH37.\r
627 //Please refer to the Errata sheet to know if a specific device is affected\r
628 //DO NOT ALTER THIS FUNCTION\r
629 \r
630 //Open PMM registers for write access\r
631 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;\r
632 \r
633 //Disable dedicated Interrupts\r
634 //Backup all registers\r
635 PMMRIE_backup = HWREG16(PMM_BASE + OFS_PMMRIE);\r
636 HWREG16(PMM_BASE + OFS_PMMRIE) &= ~(SVMHVLRPE | SVSHPE | SVMLVLRPE |\r
637 SVSLPE | SVMHVLRIE | SVMHIE |\r
638 SVSMHDLYIE | SVMLVLRIE | SVMLIE |\r
639 SVSMLDLYIE\r
640 );\r
641 SVSMHCTL_backup = HWREG16(PMM_BASE + OFS_SVSMHCTL);\r
642 SVSMLCTL_backup = HWREG16(PMM_BASE + OFS_SVSMLCTL);\r
643 \r
644 //Clear flags\r
645 HWREG16(PMM_BASE + OFS_PMMIFG) = 0;\r
646 \r
647 //Set SVM highside to new level and check if a VCore increase is possible\r
648 HWREG16(PMM_BASE + OFS_SVSMHCTL) = SVMHE | SVSHE | (SVSMHRRL0 * level);\r
649 \r
650 //Wait until SVM highside is settled\r
651 while ((HWREG16(PMM_BASE + OFS_PMMIFG) & SVSMHDLYIFG) == 0) ;\r
652 \r
653 //Clear flag\r
654 HWREG16(PMM_BASE + OFS_PMMIFG) &= ~SVSMHDLYIFG;\r
655 \r
656 //Check if a VCore increase is possible\r
657 if ((HWREG16(PMM_BASE + OFS_PMMIFG) & SVMHIFG) == SVMHIFG) {\r
658 //-> Vcc is too low for a Vcore increase\r
659 //recover the previous settings\r
660 HWREG16(PMM_BASE + OFS_PMMIFG) &= ~SVSMHDLYIFG;\r
661 HWREG16(PMM_BASE + OFS_SVSMHCTL) = SVSMHCTL_backup;\r
662 \r
663 //Wait until SVM highside is settled\r
664 while ((HWREG16(PMM_BASE + OFS_PMMIFG) & SVSMHDLYIFG) == 0) ;\r
665 \r
666 //Clear all Flags\r
667 HWREG16(PMM_BASE +\r
668 OFS_PMMIFG) &= ~(SVMHVLRIFG | SVMHIFG | SVSMHDLYIFG |\r
669 SVMLVLRIFG | SVMLIFG |\r
670 SVSMLDLYIFG\r
671 );\r
672 \r
673 //Restore PMM interrupt enable register\r
674 HWREG16(PMM_BASE + OFS_PMMRIE) = PMMRIE_backup;\r
675 //Lock PMM registers for write access\r
676 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;\r
677 //return: voltage not set\r
678 return STATUS_FAIL;\r
679 }\r
680 \r
681 //Set also SVS highside to new level\r
682 //Vcc is high enough for a Vcore increase\r
683 HWREG16(PMM_BASE + OFS_SVSMHCTL) |= (SVSHRVL0 * level);\r
684 \r
685 //Wait until SVM highside is settled\r
686 while ((HWREG16(PMM_BASE + OFS_PMMIFG) & SVSMHDLYIFG) == 0) ;\r
687 \r
688 //Clear flag\r
689 HWREG16(PMM_BASE + OFS_PMMIFG) &= ~SVSMHDLYIFG;\r
690 \r
691 //Set VCore to new level\r
692 HWREG8(PMM_BASE + OFS_PMMCTL0_L) = PMMCOREV0 * level;\r
693 \r
694 //Set SVM, SVS low side to new level\r
695 HWREG16(PMM_BASE + OFS_SVSMLCTL) = SVMLE | (SVSMLRRL0 * level) |\r
696 SVSLE | (SVSLRVL0 * level);\r
697 \r
698 //Wait until SVM, SVS low side is settled\r
699 while ((HWREG16(PMM_BASE + OFS_PMMIFG) & SVSMLDLYIFG) == 0) ;\r
700 \r
701 //Clear flag\r
702 HWREG16(PMM_BASE + OFS_PMMIFG) &= ~SVSMLDLYIFG;\r
703 //SVS, SVM core and high side are now set to protect for the new core level\r
704 \r
705 //Restore Low side settings\r
706 //Clear all other bits _except_ level settings\r
707 HWREG16(PMM_BASE + OFS_SVSMLCTL) &= (SVSLRVL0 + SVSLRVL1 + SVSMLRRL0 +\r
708 SVSMLRRL1 + SVSMLRRL2\r
709 );\r
710 \r
711 //Clear level settings in the backup register,keep all other bits\r
712 SVSMLCTL_backup &=\r
713 ~(SVSLRVL0 + SVSLRVL1 + SVSMLRRL0 + SVSMLRRL1 + SVSMLRRL2);\r
714 \r
715 //Restore low-side SVS monitor settings\r
716 HWREG16(PMM_BASE + OFS_SVSMLCTL) |= SVSMLCTL_backup;\r
717 \r
718 //Restore High side settings\r
719 //Clear all other bits except level settings\r
720 HWREG16(PMM_BASE + OFS_SVSMHCTL) &= (SVSHRVL0 + SVSHRVL1 +\r
721 SVSMHRRL0 + SVSMHRRL1 +\r
722 SVSMHRRL2\r
723 );\r
724 \r
725 //Clear level settings in the backup register,keep all other bits\r
726 SVSMHCTL_backup &=\r
727 ~(SVSHRVL0 + SVSHRVL1 + SVSMHRRL0 + SVSMHRRL1 + SVSMHRRL2);\r
728 \r
729 //Restore backup\r
730 HWREG16(PMM_BASE + OFS_SVSMHCTL) |= SVSMHCTL_backup;\r
731 \r
732 //Wait until high side, low side settled\r
733 while (((HWREG16(PMM_BASE + OFS_PMMIFG) & SVSMLDLYIFG) == 0) ||\r
734 ((HWREG16(PMM_BASE + OFS_PMMIFG) & SVSMHDLYIFG) == 0)) ;\r
735 \r
736 //Clear all Flags\r
737 HWREG16(PMM_BASE + OFS_PMMIFG) &= ~(SVMHVLRIFG | SVMHIFG | SVSMHDLYIFG |\r
738 SVMLVLRIFG | SVMLIFG | SVSMLDLYIFG\r
739 );\r
740 \r
741 //Restore PMM interrupt enable register\r
742 HWREG16(PMM_BASE + OFS_PMMRIE) = PMMRIE_backup;\r
743 \r
744 //Lock PMM registers for write access\r
745 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;\r
746 \r
747 return STATUS_SUCCESS;\r
748 }\r
749 \r
750 //*****************************************************************************\r
751 //\r
752 //! \brief Decrease Vcore by one level\r
753 //!\r
754 //! \param level level to which Vcore needs to be decreased\r
755 //! Valid values are:\r
756 //! - \b PMM_CORE_LEVEL_0 [Default]\r
757 //! - \b PMM_CORE_LEVEL_1\r
758 //! - \b PMM_CORE_LEVEL_2\r
759 //! - \b PMM_CORE_LEVEL_3\r
760 //!\r
761 //! Modified bits of \b PMMCTL0 register, bits of \b PMMIFG register, bits of\r
762 //! \b PMMRIE register, bits of \b SVSMHCTL register and bits of \b SVSMLCTL\r
763 //! register.\r
764 //!\r
765 //! \return STATUS_SUCCESS\r
766 //\r
767 //*****************************************************************************\r
768 uint16_t PMM_setVCoreDown( uint8_t level)\r
769 {\r
770 uint32_t PMMRIE_backup, SVSMHCTL_backup, SVSMLCTL_backup;\r
771 \r
772 //The code flow for decreasing the Vcore has been altered to work around\r
773 //the erratum FLASH37.\r
774 //Please refer to the Errata sheet to know if a specific device is affected\r
775 //DO NOT ALTER THIS FUNCTION\r
776 \r
777 //Open PMM registers for write access\r
778 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;\r
779 \r
780 //Disable dedicated Interrupts\r
781 //Backup all registers\r
782 PMMRIE_backup = HWREG16(PMM_BASE + OFS_PMMRIE);\r
783 HWREG16(PMM_BASE + OFS_PMMRIE) &= ~(SVMHVLRPE | SVSHPE | SVMLVLRPE |\r
784 SVSLPE | SVMHVLRIE | SVMHIE |\r
785 SVSMHDLYIE | SVMLVLRIE | SVMLIE |\r
786 SVSMLDLYIE\r
787 );\r
788 SVSMHCTL_backup = HWREG16(PMM_BASE + OFS_SVSMHCTL);\r
789 SVSMLCTL_backup = HWREG16(PMM_BASE + OFS_SVSMLCTL);\r
790 \r
791 //Clear flags\r
792 HWREG16(PMM_BASE + OFS_PMMIFG) &= ~(SVMHIFG | SVSMHDLYIFG |\r
793 SVMLIFG | SVSMLDLYIFG\r
794 );\r
795 \r
796 //Set SVM, SVS high & low side to new settings in normal mode\r
797 HWREG16(PMM_BASE + OFS_SVSMHCTL) = SVMHE | (SVSMHRRL0 * level) |\r
798 SVSHE | (SVSHRVL0 * level);\r
799 HWREG16(PMM_BASE + OFS_SVSMLCTL) = SVMLE | (SVSMLRRL0 * level) |\r
800 SVSLE | (SVSLRVL0 * level);\r
801 \r
802 //Wait until SVM high side and SVM low side is settled\r
803 while ((HWREG16(PMM_BASE + OFS_PMMIFG) & SVSMHDLYIFG) == 0 ||\r
804 (HWREG16(PMM_BASE + OFS_PMMIFG) & SVSMLDLYIFG) == 0) ;\r
805 \r
806 //Clear flags\r
807 HWREG16(PMM_BASE + OFS_PMMIFG) &= ~(SVSMHDLYIFG + SVSMLDLYIFG);\r
808 //SVS, SVM core and high side are now set to protect for the new core level\r
809 \r
810 //Set VCore to new level\r
811 HWREG8(PMM_BASE + OFS_PMMCTL0_L) = PMMCOREV0 * level;\r
812 \r
813 //Restore Low side settings\r
814 //Clear all other bits _except_ level settings\r
815 HWREG16(PMM_BASE + OFS_SVSMLCTL) &= (SVSLRVL0 + SVSLRVL1 + SVSMLRRL0 +\r
816 SVSMLRRL1 + SVSMLRRL2\r
817 );\r
818 \r
819 //Clear level settings in the backup register,keep all other bits\r
820 SVSMLCTL_backup &=\r
821 ~(SVSLRVL0 + SVSLRVL1 + SVSMLRRL0 + SVSMLRRL1 + SVSMLRRL2);\r
822 \r
823 //Restore low-side SVS monitor settings\r
824 HWREG16(PMM_BASE + OFS_SVSMLCTL) |= SVSMLCTL_backup;\r
825 \r
826 //Restore High side settings\r
827 //Clear all other bits except level settings\r
828 HWREG16(PMM_BASE + OFS_SVSMHCTL) &= (SVSHRVL0 + SVSHRVL1 + SVSMHRRL0 +\r
829 SVSMHRRL1 + SVSMHRRL2\r
830 );\r
831 \r
832 //Clear level settings in the backup register, keep all other bits\r
833 SVSMHCTL_backup &=\r
834 ~(SVSHRVL0 + SVSHRVL1 + SVSMHRRL0 + SVSMHRRL1 + SVSMHRRL2);\r
835 \r
836 //Restore backup\r
837 HWREG16(PMM_BASE + OFS_SVSMHCTL) |= SVSMHCTL_backup;\r
838 \r
839 //Wait until high side, low side settled\r
840 while (((HWREG16(PMM_BASE + OFS_PMMIFG) & SVSMLDLYIFG) == 0) ||\r
841 ((HWREG16(PMM_BASE + OFS_PMMIFG) & SVSMHDLYIFG) == 0)) ;\r
842 \r
843 //Clear all Flags\r
844 HWREG16(PMM_BASE + OFS_PMMIFG) &= ~(SVMHVLRIFG | SVMHIFG | SVSMHDLYIFG |\r
845 SVMLVLRIFG | SVMLIFG | SVSMLDLYIFG\r
846 );\r
847 \r
848 //Restore PMM interrupt enable register\r
849 HWREG16(PMM_BASE + OFS_PMMRIE) = PMMRIE_backup;\r
850 //Lock PMM registers for write access\r
851 HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;\r
852 //Return: OK\r
853 return STATUS_SUCCESS;\r
854 }\r
855 \r
856 //*****************************************************************************\r
857 //\r
858 //! \brief Set Vcore to expected level\r
859 //!\r
860 //! \param level level to which Vcore needs to be decreased/increased\r
861 //! Valid values are:\r
862 //! - \b PMM_CORE_LEVEL_0 [Default]\r
863 //! - \b PMM_CORE_LEVEL_1\r
864 //! - \b PMM_CORE_LEVEL_2\r
865 //! - \b PMM_CORE_LEVEL_3\r
866 //!\r
867 //! Modified bits of \b PMMCTL0 register, bits of \b PMMIFG register, bits of\r
868 //! \b PMMRIE register, bits of \b SVSMHCTL register and bits of \b SVSMLCTL\r
869 //! register.\r
870 //!\r
871 //! \return STATUS_SUCCESS or STATUS_FAIL\r
872 //\r
873 //*****************************************************************************\r
874 bool PMM_setVCore( uint8_t level)\r
875 {\r
876 assert(\r
877 (PMM_CORE_LEVEL_0 == level) ||\r
878 (PMM_CORE_LEVEL_1 == level) ||\r
879 (PMM_CORE_LEVEL_2 == level) ||\r
880 (PMM_CORE_LEVEL_3 == level)\r
881 );\r
882 \r
883 uint8_t actlevel;\r
884 bool status = STATUS_SUCCESS;\r
885 \r
886 //Set Mask for Max. level\r
887 level &= PMMCOREV_3;\r
888 \r
889 //Get actual VCore\r
890 actlevel = (HWREG16(PMM_BASE + OFS_PMMCTL0) & PMMCOREV_3);\r
891 \r
892 //step by step increase or decrease\r
893 while ((level != actlevel) && (status == STATUS_SUCCESS)) {\r
894 if (level > actlevel)\r
895 status = PMM_setVCoreUp(++actlevel);\r
896 else\r
897 status = PMM_setVCoreDown(--actlevel);\r
898 }\r
899 \r
900 return status;\r
901 }\r
902 \r
903 //*****************************************************************************\r
904 //\r
905 //! \brief Returns interrupt status\r
906 //!\r
907 //! \param mask is the mask for specifying the required flag\r
908 //! Mask value is the logical OR of any of the following:\r
909 //! - \b PMM_SVSMLDLYIFG\r
910 //! - \b PMM_SVMLIFG\r
911 //! - \b PMM_SVMLVLRIFG\r
912 //! - \b PMM_SVSMHDLYIFG\r
913 //! - \b PMM_SVMHIFG\r
914 //! - \b PMM_SVMHVLRIFG\r
915 //! - \b PMM_PMMBORIFG\r
916 //! - \b PMM_PMMRSTIFG\r
917 //! - \b PMM_PMMPORIFG\r
918 //! - \b PMM_SVSHIFG\r
919 //! - \b PMM_SVSLIFG\r
920 //! - \b PMM_PMMLPM5IFG\r
921 //!\r
922 //! \return Logical OR of any of the following:\r
923 //! - \b PMM_SVSMLDLYIFG\r
924 //! - \b PMM_SVMLIFG\r
925 //! - \b PMM_SVMLVLRIFG\r
926 //! - \b PMM_SVSMHDLYIFG\r
927 //! - \b PMM_SVMHIFG\r
928 //! - \b PMM_SVMHVLRIFG\r
929 //! - \b PMM_PMMBORIFG\r
930 //! - \b PMM_PMMRSTIFG\r
931 //! - \b PMM_PMMPORIFG\r
932 //! - \b PMM_SVSHIFG\r
933 //! - \b PMM_SVSLIFG\r
934 //! - \b PMM_PMMLPM5IFG\r
935 //! \n indicating the status of the masked interrupts\r
936 //\r
937 //*****************************************************************************\r
938 uint16_t PMM_getInterruptStatus(uint16_t mask)\r
939 {\r
940 return (HWREG16(PMM_BASE + OFS_PMMIFG)) & mask;\r
941 }\r
942 \r
943 #endif\r
944 #endif\r
945 //*****************************************************************************\r
946 //\r
947 //! Close the doxygen group for pmm_api\r
948 //! @}\r
949 //\r
950 //*****************************************************************************\r