1 /* --COPYRIGHT--,BSD\r
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32 //*****************************************************************************\r
33 //\r
34 // usci_uart.c - Driver for the usci_uart Module.\r
35 //\r
36 //*****************************************************************************\r
37 \r
38 //*****************************************************************************\r
39 //\r
40 //! \addtogroup usci_uart_api\r
41 //! @{\r
42 //\r
43 //*****************************************************************************\r
44 \r
45 #include "inc/hw_regaccess.h"\r
46 #include "inc/hw_memmap.h"\r
47 \r
48 #ifdef __MSP430_HAS_USCI_Ax__\r
49 #include "usci_uart.h"\r
50 \r
51 #include <assert.h>\r
52 \r
53 //*****************************************************************************\r
54 //\r
55 //! \brief DEPRECATED - Advanced initialization routine for the UART block. The\r
56 //! values to be written into the clockPrescalar, firstModReg, secondModReg and\r
57 //! overSampling parameters should be pre-computed and passed into the\r
58 //! initialization function.\r
59 //!\r
60 //! Upon successful initialization of the UART block, this function will have\r
61 //! initialized the module, but the UART block still remains disabled and must\r
62 //! be enabled with USCI_UART_enable(). To calculate values for clockPrescalar,\r
63 //! firstModReg, secondModReg and overSampling please use the link below.\r
64 //!\r
65 //! http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSP430BaudRateConverter/index.html\r
66 //!\r
67 //! \param baseAddress is the base address of the USCI_UART module.\r
68 //! \param selectClockSource selects Clock source.\r
69 //! Valid values are:\r
70 //! - \b USCI_UART_CLOCKSOURCE_SMCLK\r
71 //! - \b USCI_UART_CLOCKSOURCE_ACLK\r
72 //! \param clockPrescalar is the value to be written into UCBRx bits\r
73 //! \param firstModReg is First modulation stage register setting. This value\r
74 //! is a pre-calculated value which can be obtained from the Device\r
75 //! Users Guide. This value is written into UCBRFx bits of UCAxMCTLW.\r
76 //! \param secondModReg is Second modulation stage register setting. This value\r
77 //! is a pre-calculated value which can be obtained from the Device\r
78 //! Users Guide. This value is written into UCBRSx bits of UCAxMCTLW.\r
79 //! \param parity is the desired parity.\r
80 //! Valid values are:\r
81 //! - \b USCI_UART_NO_PARITY [Default]\r
82 //! - \b USCI_UART_ODD_PARITY\r
83 //! - \b USCI_UART_EVEN_PARITY\r
84 //! \param msborLsbFirst controls direction of receive and transmit shift\r
85 //! register.\r
86 //! Valid values are:\r
87 //! - \b USCI_UART_MSB_FIRST\r
88 //! - \b USCI_UART_LSB_FIRST [Default]\r
89 //! \param numberofStopBits indicates one/two STOP bits\r
90 //! Valid values are:\r
91 //! - \b USCI_UART_ONE_STOP_BIT [Default]\r
92 //! - \b USCI_UART_TWO_STOP_BITS\r
93 //! \param uartMode selects the mode of operation\r
94 //! Valid values are:\r
95 //! - \b USCI_UART_MODE [Default]\r
96 //! - \b USCI_UART_IDLE_LINE_MULTI_PROCESSOR_MODE\r
97 //! - \b USCI_UART_ADDRESS_BIT_MULTI_PROCESSOR_MODE\r
98 //! - \b USCI_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE\r
99 //! \param overSampling indicates low frequency or oversampling baud generation\r
100 //! Valid values are:\r
101 //! - \b USCI_UART_OVERSAMPLING_BAUDRATE_GENERATION\r
102 //! - \b USCI_UART_LOW_FREQUENCY_BAUDRATE_GENERATION\r
103 //!\r
104 //! Modified bits are \b UCPEN, \b UCPAR, \b UCMSB, \b UC7BIT, \b UCSPB, \b\r
105 //! UCMODEx and \b UCSYNC of \b UCAxCTL0 register; bits \b UCSSELx and \b\r
106 //! UCSWRST of \b UCAxCTL1 register.\r
107 //!\r
108 //! \return STATUS_SUCCESS or STATUS_FAIL of the initialization process\r
109 //\r
110 //*****************************************************************************\r
111 bool USCI_UART_initAdvance( uint16_t baseAddress,\r
112 uint8_t selectClockSource,\r
113 uint16_t clockPrescalar,\r
114 uint8_t firstModReg,\r
115 uint8_t secondModReg,\r
116 uint8_t parity,\r
117 uint8_t msborLsbFirst,\r
118 uint8_t numberofStopBits,\r
119 uint8_t uartMode,\r
120 uint8_t overSampling\r
121 )\r
122 {\r
123 USCI_UART_initParam param = { 0 };\r
124 \r
125 param.selectClockSource = selectClockSource;\r
126 param.clockPrescalar = clockPrescalar;\r
127 param.firstModReg = firstModReg;\r
128 param.secondModReg = secondModReg;\r
129 param.parity = parity;\r
130 param.msborLsbFirst = msborLsbFirst;\r
131 param.numberofStopBits = numberofStopBits;\r
132 param.uartMode = uartMode;\r
133 param.overSampling = overSampling;\r
134 \r
135 return USCI_UART_init(baseAddress, ¶m);\r
136 }\r
137 \r
138 //*****************************************************************************\r
139 //\r
140 //! \brief Advanced initialization routine for the UART block. The values to be\r
141 //! written into the clockPrescalar, firstModReg, secondModReg and overSampling\r
142 //! parameters should be pre-computed and passed into the initialization\r
143 //! function.\r
144 //!\r
145 //! Upon successful initialization of the UART block, this function will have\r
146 //! initialized the module, but the UART block still remains disabled and must\r
147 //! be enabled with USCI_UART_enable(). To calculate values for clockPrescalar,\r
148 //! firstModReg, secondModReg and overSampling please use the link below.\r
149 //!\r
150 //! http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSP430BaudRateConverter/index.html\r
151 //!\r
152 //! \param baseAddress is the base address of the USCI_UART module.\r
153 //! \param param is the pointer to struct for initialization.\r
154 //!\r
155 //! Modified bits are \b UCPEN, \b UCPAR, \b UCMSB, \b UC7BIT, \b UCSPB, \b\r
156 //! UCMODEx and \b UCSYNC of \b UCAxCTL0 register; bits \b UCSSELx and \b\r
157 //! UCSWRST of \b UCAxCTL1 register.\r
158 //!\r
159 //! \return STATUS_SUCCESS or STATUS_FAIL of the initialization process\r
160 //\r
161 //*****************************************************************************\r
162 bool USCI_UART_init(uint16_t baseAddress, USCI_UART_initParam *param)\r
163 {\r
164 assert(param != 0);\r
165 \r
166 assert(\r
167 (USCI_UART_MODE == param->uartMode) ||\r
168 (USCI_UART_IDLE_LINE_MULTI_PROCESSOR_MODE == param->uartMode) ||\r
169 (USCI_UART_ADDRESS_BIT_MULTI_PROCESSOR_MODE == param->uartMode) ||\r
170 (USCI_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE == param->uartMode)\r
171 );\r
172 \r
173 assert(\r
174 (USCI_UART_CLOCKSOURCE_ACLK == param->selectClockSource) ||\r
175 (USCI_UART_CLOCKSOURCE_SMCLK == param->selectClockSource)\r
176 );\r
177 \r
178 assert(\r
179 (USCI_UART_MSB_FIRST == param->msborLsbFirst) ||\r
180 (USCI_UART_LSB_FIRST == param->msborLsbFirst)\r
181 );\r
182 \r
183 assert(\r
184 (USCI_UART_ONE_STOP_BIT == param->numberofStopBits) ||\r
185 (USCI_UART_TWO_STOP_BITS == param->numberofStopBits)\r
186 );\r
187 \r
188 assert(\r
189 (USCI_UART_NO_PARITY == param->parity) ||\r
190 (USCI_UART_ODD_PARITY == param->parity) ||\r
191 (USCI_UART_EVEN_PARITY == param->parity)\r
192 );\r
193 \r
194 bool retVal = STATUS_SUCCESS;\r
195 \r
196 //Disable the USCI Module\r
197 HWREG8(baseAddress + OFS_UCAxCTL1) |= UCSWRST;\r
198 \r
199 //Clock source select\r
200 HWREG8(baseAddress + OFS_UCAxCTL1) &= ~UCSSEL_3;\r
201 HWREG8(baseAddress + OFS_UCAxCTL1) |= param->selectClockSource;\r
202 \r
203 //MSB, LSB select\r
204 HWREG8(baseAddress + OFS_UCAxCTL0) &= ~UCMSB;\r
205 HWREG8(baseAddress + OFS_UCAxCTL0) |= param->msborLsbFirst;\r
206 \r
207 //UCSPB = 0(1 stop bit) OR 1(2 stop bits)\r
208 HWREG8(baseAddress + OFS_UCAxCTL0) &= ~UCSPB;\r
209 HWREG8(baseAddress + OFS_UCAxCTL0) |= param->numberofStopBits;\r
210 \r
211 //Parity\r
212 switch (param->parity) {\r
213 case USCI_UART_NO_PARITY:\r
214 //No Parity\r
215 HWREG8(baseAddress + OFS_UCAxCTL0) &= ~UCPEN;\r
216 break;\r
217 case USCI_UART_ODD_PARITY:\r
218 //Odd Parity\r
219 HWREG8(baseAddress + OFS_UCAxCTL0) |= UCPEN;\r
220 HWREG8(baseAddress + OFS_UCAxCTL0) &= ~UCPAR;\r
221 break;\r
222 case USCI_UART_EVEN_PARITY:\r
223 //Even Parity\r
224 HWREG8(baseAddress + OFS_UCAxCTL0) |= UCPEN;\r
225 HWREG8(baseAddress + OFS_UCAxCTL0) |= UCPAR;\r
226 break;\r
227 }\r
228 \r
229 //Modulation Control Registers\r
230 HWREG16(baseAddress + OFS_UCAxBRW ) = param->clockPrescalar;\r
231 HWREG8(baseAddress + OFS_UCAxMCTL) = ((param->firstModReg << 4) +\r
232 (param->secondModReg << 1) +\r
233 param->overSampling );\r
234 \r
235 //Asynchronous mode & 8 bit character select & clear mode\r
236 HWREG8(baseAddress + OFS_UCAxCTL0) &= ~(UCSYNC +\r
237 UC7BIT +\r
238 UCMODE_3\r
239 );\r
240 \r
241 //Configure UART mode.\r
242 HWREG8(baseAddress + OFS_UCAxCTL0) |= param->uartMode;\r
243 \r
244 //Reset UCRXIE, UCBRKIE, UCDORM, UCTXADDR, UCTXBRK\r
245 HWREG8(baseAddress + OFS_UCAxCTL1) &= ~(UCRXEIE + UCBRKIE + UCDORM +\r
246 UCTXADDR + UCTXBRK\r
247 );\r
248 \r
249 return retVal;\r
250 } //*****************************************************************************\r
251 //\r
252 //! \brief Transmits a byte from the UART Module.\r
253 //!\r
254 //! This function will place the supplied data into UART transmit data register\r
255 //! to start transmission\r
256 //!\r
257 //! \param baseAddress is the base address of the USCI_UART module.\r
258 //! \param transmitData data to be transmitted from the UART module\r
259 //!\r
260 //! Modified bits of \b UCAxTXBUF register.\r
261 //!\r
262 //! \return None\r
263 //\r
264 //*****************************************************************************\r
265 void USCI_UART_transmitData( uint16_t baseAddress,\r
266 uint8_t transmitData\r
267 )\r
268 {\r
269 //If interrupts are not used, poll for flags\r
270 if (!(HWREG8(baseAddress + OFS_UCAxIE) & UCTXIE))\r
271 //Poll for transmit interrupt flag\r
272 while (!(HWREG8(baseAddress + OFS_UCAxIFG) & UCTXIFG)) ;\r
273 \r
274 HWREG8(baseAddress + OFS_UCAxTXBUF) = transmitData;\r
275 }\r
276 \r
277 //*****************************************************************************\r
278 //\r
279 //! \brief Receives a byte that has been sent to the UART Module.\r
280 //!\r
281 //! This function reads a byte of data from the UART receive data Register.\r
282 //!\r
283 //! \param baseAddress is the base address of the USCI_UART module.\r
284 //!\r
285 //! Modified bits of \b UCAxRXBUF register.\r
286 //!\r
287 //! \return Returns the byte received from by the UART module, cast as an\r
288 //! uint8_t.\r
289 //\r
290 //*****************************************************************************\r
291 uint8_t USCI_UART_receiveData(uint16_t baseAddress)\r
292 {\r
293 //If interrupts are not used, poll for flags\r
294 if (!(HWREG8(baseAddress + OFS_UCAxIE) & UCRXIE))\r
295 //Poll for receive interrupt flag\r
296 while (!(HWREG8(baseAddress + OFS_UCAxIFG) & UCRXIFG)) ;\r
297 \r
298 return HWREG8(baseAddress + OFS_UCAxRXBUF);\r
299 }\r
300 \r
301 //*****************************************************************************\r
302 //\r
303 //! \brief Enables individual UART interrupt sources.\r
304 //!\r
305 //! Enables the indicated UART interrupt sources. The interrupt flag is first\r
306 //! and then the corresponding interrupt is enabled. Only the sources that are\r
307 //! enabled can be reflected to the processor interrupt; disabled sources have\r
308 //! no effect on the processor. Does not clear interrupt flags.\r
309 //!\r
310 //! \param baseAddress is the base address of the USCI_UART module.\r
311 //! \param mask is the bit mask of the interrupt sources to be enabled.\r
312 //! Mask value is the logical OR of any of the following:\r
313 //! - \b USCI_UART_RECEIVE_INTERRUPT - Receive interrupt\r
314 //! - \b USCI_UART_TRANSMIT_INTERRUPT - Transmit interrupt\r
315 //! - \b USCI_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT - Receive erroneous-\r
316 //! character interrupt enable\r
317 //! - \b USCI_UART_BREAKCHAR_INTERRUPT - Receive break character\r
318 //! interrupt enable\r
319 //!\r
320 //! Modified bits of \b UCAxCTL1 register and bits of \b UCAxIE register.\r
321 //!\r
322 //! \return None\r
323 //\r
324 //*****************************************************************************\r
325 void USCI_UART_enableInterrupt(uint16_t baseAddress,\r
326 uint8_t mask\r
327 )\r
328 {\r
329 assert(!(mask & ~(USCI_UART_RECEIVE_INTERRUPT\r
330 | USCI_UART_TRANSMIT_INTERRUPT\r
331 | USCI_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT\r
332 | USCI_UART_BREAKCHAR_INTERRUPT)));\r
333 \r
334 uint8_t locMask;\r
335 \r
336 locMask = (mask & (USCI_UART_RECEIVE_INTERRUPT\r
337 | USCI_UART_TRANSMIT_INTERRUPT));\r
338 HWREG8(baseAddress + OFS_UCAxIE) |= locMask;\r
339 \r
340 locMask = (mask & (USCI_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT\r
341 | USCI_UART_BREAKCHAR_INTERRUPT));\r
342 HWREG8(baseAddress + OFS_UCAxCTL1) |= locMask;\r
343 }\r
344 \r
345 //*****************************************************************************\r
346 //\r
347 //! \brief Disables individual UART interrupt sources.\r
348 //!\r
349 //! Disables the indicated UART interrupt sources. Only the sources that are\r
350 //! enabled can be reflected to the processor interrupt; disabled sources have\r
351 //! no effect on the processor.\r
352 //!\r
353 //! \param baseAddress is the base address of the USCI_UART module.\r
354 //! \param mask is the bit mask of the interrupt sources to be disabled.\r
355 //! Mask value is the logical OR of any of the following:\r
356 //! - \b USCI_UART_RECEIVE_INTERRUPT - Receive interrupt\r
357 //! - \b USCI_UART_TRANSMIT_INTERRUPT - Transmit interrupt\r
358 //! - \b USCI_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT - Receive erroneous-\r
359 //! character interrupt enable\r
360 //! - \b USCI_UART_BREAKCHAR_INTERRUPT - Receive break character\r
361 //! interrupt enable\r
362 //!\r
363 //! Modified bits of \b UCAxCTL1 register and bits of \b UCAxIE register.\r
364 //!\r
365 //! \return None\r
366 //\r
367 //*****************************************************************************\r
368 void USCI_UART_disableInterrupt(uint16_t baseAddress,\r
369 uint8_t mask\r
370 )\r
371 {\r
372 assert(!(mask & ~(USCI_UART_RECEIVE_INTERRUPT\r
373 | USCI_UART_TRANSMIT_INTERRUPT\r
374 | USCI_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT\r
375 | USCI_UART_BREAKCHAR_INTERRUPT)));\r
376 \r
377 uint8_t locMask;\r
378 \r
379 if (locMask = (mask & (USCI_UART_RECEIVE_INTERRUPT\r
380 | USCI_UART_TRANSMIT_INTERRUPT)))\r
381 HWREG8(baseAddress + OFS_UCAxIE) &= ~locMask;\r
382 \r
383 if (locMask = (mask & (USCI_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT\r
384 | USCI_UART_BREAKCHAR_INTERRUPT)))\r
385 HWREG8(baseAddress + OFS_UCAxCTL1) &= ~locMask;\r
386 }\r
387 \r
388 //*****************************************************************************\r
389 //\r
390 //! \brief Gets the current UART interrupt status.\r
391 //!\r
392 //! This returns the interrupt status for the UART module based on which flag\r
393 //! is passed.\r
394 //!\r
395 //! \param baseAddress is the base address of the USCI_UART module.\r
396 //! \param mask is the masked interrupt flag status to be returned.\r
397 //! Mask value is the logical OR of any of the following:\r
398 //! - \b USCI_UART_RECEIVE_INTERRUPT_FLAG - Receive interrupt flag\r
399 //! - \b USCI_UART_TRANSMIT_INTERRUPT_FLAG - Transmit interrupt flag\r
400 //!\r
401 //! Modified bits of \b UCAxIFG register.\r
402 //!\r
403 //! \return Logical OR of any of the following:\r
404 //! - \b USCI_UART_RECEIVE_INTERRUPT_FLAG Receive interrupt flag\r
405 //! - \b USCI_UART_TRANSMIT_INTERRUPT_FLAG Transmit interrupt flag\r
406 //! \n indicating the status of the masked flags\r
407 //\r
408 //*****************************************************************************\r
409 uint8_t USCI_UART_getInterruptStatus(uint16_t baseAddress,\r
410 uint8_t mask)\r
411 {\r
412 assert(!(mask & ~(USCI_UART_RECEIVE_INTERRUPT_FLAG\r
413 | USCI_UART_TRANSMIT_INTERRUPT_FLAG)));\r
414 \r
415 return HWREG8(baseAddress + OFS_UCAxIFG) & mask;\r
416 }\r
417 \r
418 //*****************************************************************************\r
419 //\r
420 //! \brief Clears UART interrupt sources.\r
421 //!\r
422 //! The UART interrupt source is cleared, so that it no longer asserts. The\r
423 //! highest interrupt flag is automatically cleared when an interrupt vector\r
424 //! generator is used.\r
425 //!\r
426 //! \param baseAddress is the base address of the USCI_UART module.\r
427 //! \param mask is a bit mask of the interrupt sources to be cleared.\r
428 //! Mask value is the logical OR of any of the following:\r
429 //! - \b USCI_UART_RECEIVE_INTERRUPT_FLAG - Receive interrupt flag\r
430 //! - \b USCI_UART_TRANSMIT_INTERRUPT_FLAG - Transmit interrupt flag\r
431 //!\r
432 //! Modified bits of \b UCAxIFG register.\r
433 //!\r
434 //! \return None\r
435 //\r
436 //*****************************************************************************\r
437 void USCI_UART_clearInterruptFlag(uint16_t baseAddress, uint8_t mask)\r
438 {\r
439 assert(!(mask & ~(USCI_UART_RECEIVE_INTERRUPT_FLAG\r
440 | USCI_UART_TRANSMIT_INTERRUPT_FLAG)));\r
441 \r
442 //Clear the UART interrupt source.\r
443 HWREG8(baseAddress + OFS_UCAxIFG) &= ~(mask);\r
444 }\r
445 \r
446 //*****************************************************************************\r
447 //\r
448 //! \brief Enables the UART block.\r
449 //!\r
450 //! This will enable operation of the UART block.\r
451 //!\r
452 //! \param baseAddress is the base address of the USCI_UART module.\r
453 //!\r
454 //! Modified bits are \b UCSWRST of \b UCAxCTL1 register.\r
455 //!\r
456 //! \return None\r
457 //\r
458 //*****************************************************************************\r
459 void USCI_UART_enable(uint16_t baseAddress)\r
460 {\r
461 //Reset the UCSWRST bit to enable the USCI Module\r
462 HWREG8(baseAddress + OFS_UCAxCTL1) &= ~(UCSWRST);\r
463 }\r
464 \r
465 //*****************************************************************************\r
466 //\r
467 //! \brief Disables the UART block.\r
468 //!\r
469 //! This will disable operation of the UART block.\r
470 //!\r
471 //! \param baseAddress is the base address of the USCI_UART module.\r
472 //!\r
473 //! Modified bits are \b UCSWRST of \b UCAxCTL1 register.\r
474 //!\r
475 //! \return None\r
476 //\r
477 //*****************************************************************************\r
478 void USCI_UART_disable(uint16_t baseAddress)\r
479 {\r
480 //Set the UCSWRST bit to disable the USCI Module\r
481 HWREG8(baseAddress + OFS_UCAxCTL1) |= UCSWRST;\r
482 }\r
483 \r
484 //*****************************************************************************\r
485 //\r
486 //! \brief Gets the current UART status flags.\r
487 //!\r
488 //! This returns the status for the UART module based on which flag is passed.\r
489 //!\r
490 //! \param baseAddress is the base address of the USCI_UART module.\r
491 //! \param mask is the masked interrupt flag status to be returned.\r
492 //! Mask value is the logical OR of any of the following:\r
493 //! - \b USCI_UART_LISTEN_ENABLE\r
494 //! - \b USCI_UART_FRAMING_ERROR\r
495 //! - \b USCI_UART_OVERRUN_ERROR\r
496 //! - \b USCI_UART_PARITY_ERROR\r
497 //! - \b USCI_UART_BREAK_DETECT\r
498 //! - \b USCI_UART_RECEIVE_ERROR\r
499 //! - \b USCI_UART_ADDRESS_RECEIVED\r
500 //! - \b USCI_UART_IDLELINE\r
501 //! - \b USCI_UART_BUSY\r
502 //!\r
503 //! Modified bits of \b UCAxSTAT register.\r
504 //!\r
505 //! \return Logical OR of any of the following:\r
506 //! - \b USCI_UART_LISTEN_ENABLE\r
507 //! - \b USCI_UART_FRAMING_ERROR\r
508 //! - \b USCI_UART_OVERRUN_ERROR\r
509 //! - \b USCI_UART_PARITY_ERROR\r
510 //! - \b USCI_UART_BREAK_DETECT\r
511 //! - \b USCI_UART_RECEIVE_ERROR\r
512 //! - \b USCI_UART_ADDRESS_RECEIVED\r
513 //! - \b USCI_UART_IDLELINE\r
514 //! - \b USCI_UART_BUSY\r
515 //! \n indicating the status of the masked interrupt flags\r
516 //\r
517 //*****************************************************************************\r
518 uint8_t USCI_UART_queryStatusFlags(uint16_t baseAddress,\r
519 uint8_t mask)\r
520 {\r
521 assert(0x00 != mask && (USCI_UART_LISTEN_ENABLE +\r
522 USCI_UART_FRAMING_ERROR +\r
523 USCI_UART_OVERRUN_ERROR +\r
524 USCI_UART_PARITY_ERROR +\r
525 USCI_UART_BREAK_DETECT +\r
526 USCI_UART_RECEIVE_ERROR +\r
527 USCI_UART_ADDRESS_RECEIVED +\r
528 USCI_UART_IDLELINE +\r
529 USCI_UART_BUSY\r
530 ));\r
531 \r
532 return HWREG8(baseAddress + OFS_UCAxSTAT) & mask;\r
533 }\r
534 \r
535 //*****************************************************************************\r
536 //\r
537 //! \brief Sets the UART module in dormant mode\r
538 //!\r
539 //! Puts USCI in sleep mode. Only characters that are preceded by an idle-line\r
540 //! or with address bit set UCRXIFG. In UART mode with automatic baud-rate\r
541 //! detection, only the combination of a break and sync field sets UCRXIFG.\r
542 //!\r
543 //! \param baseAddress is the base address of the USCI_UART module.\r
544 //!\r
545 //! Modified bits of \b UCAxCTL1 register.\r
546 //!\r
547 //! \return None\r
548 //\r
549 //*****************************************************************************\r
550 void USCI_UART_setDormant(uint16_t baseAddress)\r
551 {\r
552 HWREG8(baseAddress + OFS_UCAxCTL1) |= UCDORM;\r
553 }\r
554 \r
555 //*****************************************************************************\r
556 //\r
557 //! \brief Re-enables UART module from dormant mode\r
558 //!\r
559 //! Not dormant. All received characters set UCRXIFG.\r
560 //!\r
561 //! \param baseAddress is the base address of the USCI_UART module.\r
562 //!\r
563 //! Modified bits are \b UCDORM of \b UCAxCTL1 register.\r
564 //!\r
565 //! \return None\r
566 //\r
567 //*****************************************************************************\r
568 void USCI_UART_resetDormant(uint16_t baseAddress)\r
569 {\r
570 HWREG8(baseAddress + OFS_UCAxCTL1) &= ~UCDORM;\r
571 }\r
572 \r
573 //*****************************************************************************\r
574 //\r
575 //! \brief Transmits the next byte to be transmitted marked as address\r
576 //! depending on selected multiprocessor mode\r
577 //!\r
578 //! \param baseAddress is the base address of the USCI_UART module.\r
579 //! \param transmitAddress is the next byte to be transmitted\r
580 //!\r
581 //! Modified bits of \b UCAxTXBUF register and bits of \b UCAxCTL1 register.\r
582 //!\r
583 //! \return None\r
584 //\r
585 //*****************************************************************************\r
586 void USCI_UART_transmitAddress(uint16_t baseAddress,\r
587 uint8_t transmitAddress)\r
588 {\r
589 //Set UCTXADDR bit\r
590 HWREG8(baseAddress + OFS_UCAxCTL1) |= UCTXADDR;\r
591 \r
592 //Place next byte to be sent into the transmit buffer\r
593 HWREG8(baseAddress + OFS_UCAxTXBUF) = transmitAddress;\r
594 }\r
595 \r
596 //*****************************************************************************\r
597 //\r
598 //! \brief Transmit break.\r
599 //!\r
600 //! Transmits a break with the next write to the transmit buffer. In UART mode\r
601 //! with automatic baud-rate detection, USCI_UART_AUTOMATICBAUDRATE_SYNC(0x55)\r
602 //! must be written into UCAxTXBUF to generate the required break/sync fields.\r
603 //! Otherwise, DEFAULT_SYNC(0x00) must be written into the transmit buffer.\r
604 //! Also ensures module is ready for transmitting the next data.\r
605 //!\r
606 //! \param baseAddress is the base address of the USCI_UART module.\r
607 //!\r
608 //! Modified bits of \b UCAxTXBUF register and bits of \b UCAxCTL1 register.\r
609 //!\r
610 //! \return None\r
611 //\r
612 //*****************************************************************************\r
613 void USCI_UART_transmitBreak(uint16_t baseAddress)\r
614 {\r
615 //Set UCTXADDR bit\r
616 HWREG8(baseAddress + OFS_UCAxCTL1) |= UCTXBRK;\r
617 \r
618 //If current mode is automatic baud-rate detection\r
619 if (USCI_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE ==\r
620 (HWREG8(baseAddress + OFS_UCAxCTL0) &\r
621 USCI_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE))\r
622 HWREG8(baseAddress + OFS_UCAxTXBUF) = USCI_UART_AUTOMATICBAUDRATE_SYNC;\r
623 else\r
624 HWREG8(baseAddress + OFS_UCAxTXBUF) = DEFAULT_SYNC;\r
625 \r
626 //If interrupts are not used, poll for flags\r
627 if (!(HWREG8(baseAddress + OFS_UCAxIE) & UCTXIE))\r
628 //Poll for transmit interrupt flag\r
629 while (!(HWREG8(baseAddress + OFS_UCAxIFG) & UCTXIFG)) ;\r
630 }\r
631 \r
632 //*****************************************************************************\r
633 //\r
634 //! \brief Returns the address of the RX Buffer of the UART for the DMA module.\r
635 //!\r
636 //! Returns the address of the UART RX Buffer. This can be used in conjunction\r
637 //! with the DMA to store the received data directly to memory.\r
638 //!\r
639 //! \param baseAddress is the base address of the USCI_UART module.\r
640 //!\r
641 //! \return Address of RX Buffer\r
642 //\r
643 //*****************************************************************************\r
644 uint32_t USCI_UART_getReceiveBufferAddressForDMA(uint16_t baseAddress)\r
645 {\r
646 return baseAddress + OFS_UCAxRXBUF;\r
647 }\r
648 \r
649 //*****************************************************************************\r
650 //\r
651 //! \brief Returns the address of the TX Buffer of the UART for the DMA module.\r
652 //!\r
653 //! Returns the address of the UART TX Buffer. This can be used in conjunction\r
654 //! with the DMA to obtain transmitted data directly from memory.\r
655 //!\r
656 //! \param baseAddress is the base address of the USCI_UART module.\r
657 //!\r
658 //! \return Address of TX Buffer\r
659 //\r
660 //*****************************************************************************\r
661 uint32_t USCI_UART_getTransmitBufferAddressForDMA(uint16_t baseAddress)\r
662 {\r
663 return baseAddress + OFS_UCAxTXBUF;\r
664 }\r
665 \r
666 \r
667 #endif\r
668 //*****************************************************************************\r
669 //\r
670 //! Close the doxygen group for usci_uart_api\r
671 //! @}\r
672 //\r
673 //*****************************************************************************\r