diff --git a/source/driverlib/MSP430F5xx_6xx/eusci_uart.c b/source/driverlib/MSP430F5xx_6xx/eusci_uart.c
--- /dev/null
@@ -0,0 +1,735 @@
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// eusci_uart.c - Driver for the eusci_uart Module.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup eusci_uart_api\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "inc/hw_regaccess.h"\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_EUSCI_Ax__\r
+#include "eusci_uart.h"\r
+\r
+#include <assert.h>\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief DEPRECATED - Advanced initialization routine for the UART block. The\r
+//! values to be written into the clockPrescalar, firstModReg, secondModReg and\r
+//! overSampling parameters should be pre-computed and passed into the\r
+//! initialization function.\r
+//!\r
+//! Upon successful initialization of the UART block, this function will have\r
+//! initialized the module, but the UART block still remains disabled and must\r
+//! be enabled with EUSCI_UART_enable(). To calculate values for\r
+//! clockPrescalar, firstModReg, secondModReg and overSampling please use the\r
+//! link below.\r
+//!\r
+//! http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSP430BaudRateConverter/index.html\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_UART module.\r
+//! \param selectClockSource selects Clock source.\r
+//! Valid values are:\r
+//! - \b EUSCI_UART_CLOCKSOURCE_SMCLK\r
+//! - \b EUSCI_UART_CLOCKSOURCE_ACLK\r
+//! \param clockPrescalar is the value to be written into UCBRx bits\r
+//! \param firstModReg is First modulation stage register setting. This value\r
+//! is a pre-calculated value which can be obtained from the Device\r
+//! Users Guide. This value is written into UCBRFx bits of UCAxMCTLW.\r
+//! \param secondModReg is Second modulation stage register setting. This value\r
+//! is a pre-calculated value which can be obtained from the Device\r
+//! Users Guide. This value is written into UCBRSx bits of UCAxMCTLW.\r
+//! \param parity is the desired parity.\r
+//! Valid values are:\r
+//! - \b EUSCI_UART_NO_PARITY [Default]\r
+//! - \b EUSCI_UART_ODD_PARITY\r
+//! - \b EUSCI_UART_EVEN_PARITY\r
+//! \param msborLsbFirst controls direction of receive and transmit shift\r
+//! register.\r
+//! Valid values are:\r
+//! - \b EUSCI_UART_MSB_FIRST\r
+//! - \b EUSCI_UART_LSB_FIRST [Default]\r
+//! \param numberofStopBits indicates one/two STOP bits\r
+//! Valid values are:\r
+//! - \b EUSCI_UART_ONE_STOP_BIT [Default]\r
+//! - \b EUSCI_UART_TWO_STOP_BITS\r
+//! \param uartMode selects the mode of operation\r
+//! Valid values are:\r
+//! - \b EUSCI_UART_MODE [Default]\r
+//! - \b EUSCI_UART_IDLE_LINE_MULTI_PROCESSOR_MODE\r
+//! - \b EUSCI_UART_ADDRESS_BIT_MULTI_PROCESSOR_MODE\r
+//! - \b EUSCI_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE\r
+//! \param overSampling indicates low frequency or oversampling baud generation\r
+//! Valid values are:\r
+//! - \b EUSCI_UART_OVERSAMPLING_BAUDRATE_GENERATION\r
+//! - \b EUSCI_UART_LOW_FREQUENCY_BAUDRATE_GENERATION\r
+//!\r
+//! Modified bits are \b UCPEN, \b UCPAR, \b UCMSB, \b UC7BIT, \b UCSPB, \b\r
+//! UCMODEx and \b UCSYNC of \b UCAxCTL0 register; bits \b UCSSELx and \b\r
+//! UCSWRST of \b UCAxCTL1 register.\r
+//!\r
+//! \return STATUS_SUCCESS or STATUS_FAIL of the initialization process\r
+//\r
+//*****************************************************************************\r
+bool EUSCI_UART_initAdvance( uint16_t baseAddress,\r
+ uint8_t selectClockSource,\r
+ uint16_t clockPrescalar,\r
+ uint8_t firstModReg,\r
+ uint8_t secondModReg,\r
+ uint8_t parity,\r
+ uint16_t msborLsbFirst,\r
+ uint16_t numberofStopBits,\r
+ uint16_t uartMode,\r
+ uint8_t overSampling\r
+ )\r
+{\r
+ EUSCI_UART_initParam param = { 0 };\r
+\r
+ param.selectClockSource = selectClockSource;\r
+ param.clockPrescalar = clockPrescalar;\r
+ param.firstModReg = firstModReg;\r
+ param.secondModReg = secondModReg;\r
+ param.parity = parity;\r
+ param.msborLsbFirst = msborLsbFirst;\r
+ param.numberofStopBits = numberofStopBits;\r
+ param.uartMode = uartMode;\r
+ param.overSampling = overSampling;\r
+\r
+ return EUSCI_UART_init(baseAddress, ¶m);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Advanced initialization routine for the UART block. The values to be\r
+//! written into the clockPrescalar, firstModReg, secondModReg and overSampling\r
+//! parameters should be pre-computed and passed into the initialization\r
+//! function.\r
+//!\r
+//! Upon successful initialization of the UART block, this function will have\r
+//! initialized the module, but the UART block still remains disabled and must\r
+//! be enabled with EUSCI_UART_enable(). To calculate values for\r
+//! clockPrescalar, firstModReg, secondModReg and overSampling please use the\r
+//! link below.\r
+//!\r
+//! http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSP430BaudRateConverter/index.html\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_UART module.\r
+//! \param param is the pointer to struct for initialization.\r
+//!\r
+//! Modified bits are \b UCPEN, \b UCPAR, \b UCMSB, \b UC7BIT, \b UCSPB, \b\r
+//! UCMODEx and \b UCSYNC of \b UCAxCTL0 register; bits \b UCSSELx and \b\r
+//! UCSWRST of \b UCAxCTL1 register.\r
+//!\r
+//! \return STATUS_SUCCESS or STATUS_FAIL of the initialization process\r
+//\r
+//*****************************************************************************\r
+bool EUSCI_UART_init(uint16_t baseAddress, EUSCI_UART_initParam *param)\r
+{\r
+ assert(param != 0);\r
+\r
+ assert(\r
+ (EUSCI_UART_MODE == param->uartMode) ||\r
+ (EUSCI_UART_IDLE_LINE_MULTI_PROCESSOR_MODE == param->uartMode) ||\r
+ (EUSCI_UART_ADDRESS_BIT_MULTI_PROCESSOR_MODE == param->uartMode) ||\r
+ (EUSCI_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE == param->uartMode)\r
+ );\r
+\r
+ assert(\r
+ (EUSCI_UART_CLOCKSOURCE_ACLK == param->selectClockSource) ||\r
+ (EUSCI_UART_CLOCKSOURCE_SMCLK == param->selectClockSource)\r
+ );\r
+\r
+ assert(\r
+ (EUSCI_UART_MSB_FIRST == param->msborLsbFirst) ||\r
+ (EUSCI_UART_LSB_FIRST == param->msborLsbFirst)\r
+ );\r
+\r
+ assert(\r
+ (EUSCI_UART_ONE_STOP_BIT == param->numberofStopBits) ||\r
+ (EUSCI_UART_TWO_STOP_BITS == param->numberofStopBits)\r
+ );\r
+\r
+ assert(\r
+ (EUSCI_UART_NO_PARITY == param->parity) ||\r
+ (EUSCI_UART_ODD_PARITY == param->parity) ||\r
+ (EUSCI_UART_EVEN_PARITY == param->parity)\r
+ );\r
+\r
+ bool retVal = STATUS_SUCCESS;\r
+\r
+ //Disable the USCI Module\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCSWRST;\r
+\r
+ //Clock source select\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCSSEL_3;\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) |= param->selectClockSource;\r
+\r
+ //MSB, LSB select\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCMSB;\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) |= param->msborLsbFirst;\r
+\r
+ //UCSPB = 0(1 stop bit) OR 1(2 stop bits)\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCSPB;\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) |= param->numberofStopBits;\r
+\r
+ //Parity\r
+ switch (param->parity) {\r
+ case EUSCI_UART_NO_PARITY:\r
+ //No Parity\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCPEN;\r
+ break;\r
+ case EUSCI_UART_ODD_PARITY:\r
+ //Odd Parity\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCPEN;\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCPAR;\r
+ break;\r
+ case EUSCI_UART_EVEN_PARITY:\r
+ //Even Parity\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCPEN;\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCPAR;\r
+ break;\r
+ }\r
+\r
+ //BaudRate Control Register\r
+ HWREG16(baseAddress + OFS_UCAxBRW ) = param->clockPrescalar;\r
+ //Modulation Control Register\r
+ HWREG16(baseAddress + OFS_UCAxMCTLW) = ((param->secondModReg << 8)\r
+ + (param->firstModReg << 4) + param->overSampling );\r
+\r
+ //Asynchronous mode & 8 bit character select & clear mode\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCSYNC +\r
+ UC7BIT +\r
+ UCMODE_3\r
+ );\r
+\r
+ //Configure UART mode.\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) |= param->uartMode;\r
+\r
+ //Reset UCRXIE, UCBRKIE, UCDORM, UCTXADDR, UCTXBRK\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCRXEIE + UCBRKIE + UCDORM +\r
+ UCTXADDR + UCTXBRK\r
+ );\r
+\r
+ return retVal;\r
+}\r
+//*****************************************************************************\r
+//\r
+//! \brief Transmits a byte from the UART Module.\r
+//!\r
+//! This function will place the supplied data into UART transmit data register\r
+//! to start transmission\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_UART module.\r
+//! \param transmitData data to be transmitted from the UART module\r
+//!\r
+//! Modified bits of \b UCAxTXBUF register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void EUSCI_UART_transmitData( uint16_t baseAddress,\r
+ uint8_t transmitData\r
+ )\r
+{\r
+ //If interrupts are not used, poll for flags\r
+ if (!(HWREG16(baseAddress + OFS_UCAxIE) & UCTXIE))\r
+ //Poll for transmit interrupt flag\r
+ while (!(HWREG16(baseAddress + OFS_UCAxIFG) & UCTXIFG)) ;\r
+\r
+ HWREG16(baseAddress + OFS_UCAxTXBUF) = transmitData;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Receives a byte that has been sent to the UART Module.\r
+//!\r
+//! This function reads a byte of data from the UART receive data Register.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_UART module.\r
+//!\r
+//! Modified bits of \b UCAxRXBUF register.\r
+//!\r
+//! \return Returns the byte received from by the UART module, cast as an\r
+//! uint8_t.\r
+//\r
+//*****************************************************************************\r
+uint8_t EUSCI_UART_receiveData(uint16_t baseAddress)\r
+{\r
+ //If interrupts are not used, poll for flags\r
+ if (!(HWREG16(baseAddress + OFS_UCAxIE) & UCRXIE))\r
+ //Poll for receive interrupt flag\r
+ while (!(HWREG16(baseAddress + OFS_UCAxIFG) & UCRXIFG)) ;\r
+\r
+ return HWREG16(baseAddress + OFS_UCAxRXBUF);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Enables individual UART interrupt sources.\r
+//!\r
+//! Enables the indicated UART interrupt sources. The interrupt flag is first\r
+//! and then the corresponding interrupt is enabled. Only the sources that are\r
+//! enabled can be reflected to the processor interrupt; disabled sources have\r
+//! no effect on the processor. Does not clear interrupt flags.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_UART module.\r
+//! \param mask is the bit mask of the interrupt sources to be enabled.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b EUSCI_UART_RECEIVE_INTERRUPT - Receive interrupt\r
+//! - \b EUSCI_UART_TRANSMIT_INTERRUPT - Transmit interrupt\r
+//! - \b EUSCI_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT - Receive erroneous-\r
+//! character interrupt enable\r
+//! - \b EUSCI_UART_BREAKCHAR_INTERRUPT - Receive break character\r
+//! interrupt enable\r
+//! - \b EUSCI_UART_STARTBIT_INTERRUPT - Start bit received interrupt\r
+//! enable\r
+//! - \b EUSCI_UART_TRANSMIT_COMPLETE_INTERRUPT - Transmit complete\r
+//! interrupt enable\r
+//!\r
+//! Modified bits of \b UCAxCTL1 register and bits of \b UCAxIE register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void EUSCI_UART_enableInterrupt(uint16_t baseAddress,\r
+ uint8_t mask\r
+ )\r
+{\r
+ assert(!(mask & ~(EUSCI_UART_RECEIVE_INTERRUPT\r
+ | EUSCI_UART_TRANSMIT_INTERRUPT\r
+ | EUSCI_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT\r
+ | EUSCI_UART_BREAKCHAR_INTERRUPT\r
+ | EUSCI_UART_STARTBIT_INTERRUPT\r
+ | EUSCI_UART_TRANSMIT_COMPLETE_INTERRUPT)));\r
+\r
+ uint8_t locMask;\r
+\r
+ locMask = (mask & (EUSCI_UART_RECEIVE_INTERRUPT\r
+ | EUSCI_UART_TRANSMIT_INTERRUPT\r
+ | EUSCI_UART_STARTBIT_INTERRUPT\r
+ | EUSCI_UART_TRANSMIT_COMPLETE_INTERRUPT));\r
+\r
+ HWREG16(baseAddress + OFS_UCAxIE) |= locMask;\r
+\r
+ locMask = (mask & (EUSCI_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT\r
+ | EUSCI_UART_BREAKCHAR_INTERRUPT));\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) |= locMask;\r
+\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Disables individual UART interrupt sources.\r
+//!\r
+//! Disables the indicated UART interrupt sources. Only the sources that are\r
+//! enabled can be reflected to the processor interrupt; disabled sources have\r
+//! no effect on the processor.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_UART module.\r
+//! \param mask is the bit mask of the interrupt sources to be disabled.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b EUSCI_UART_RECEIVE_INTERRUPT - Receive interrupt\r
+//! - \b EUSCI_UART_TRANSMIT_INTERRUPT - Transmit interrupt\r
+//! - \b EUSCI_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT - Receive erroneous-\r
+//! character interrupt enable\r
+//! - \b EUSCI_UART_BREAKCHAR_INTERRUPT - Receive break character\r
+//! interrupt enable\r
+//! - \b EUSCI_UART_STARTBIT_INTERRUPT - Start bit received interrupt\r
+//! enable\r
+//! - \b EUSCI_UART_TRANSMIT_COMPLETE_INTERRUPT - Transmit complete\r
+//! interrupt enable\r
+//!\r
+//! Modified bits of \b UCAxCTL1 register and bits of \b UCAxIE register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void EUSCI_UART_disableInterrupt(uint16_t baseAddress,\r
+ uint8_t mask\r
+ )\r
+{\r
+ assert(!(mask & ~(EUSCI_UART_RECEIVE_INTERRUPT\r
+ | EUSCI_UART_TRANSMIT_INTERRUPT\r
+ | EUSCI_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT\r
+ | EUSCI_UART_BREAKCHAR_INTERRUPT\r
+ | EUSCI_UART_STARTBIT_INTERRUPT\r
+ | EUSCI_UART_TRANSMIT_COMPLETE_INTERRUPT)));\r
+\r
+ uint8_t locMask;\r
+\r
+ locMask = (mask & (EUSCI_UART_RECEIVE_INTERRUPT\r
+ | EUSCI_UART_TRANSMIT_INTERRUPT\r
+ | EUSCI_UART_STARTBIT_INTERRUPT\r
+ | EUSCI_UART_TRANSMIT_COMPLETE_INTERRUPT));\r
+ HWREG16(baseAddress + OFS_UCAxIE) &= ~locMask;\r
+\r
+\r
+ locMask = (mask & (EUSCI_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT\r
+ | EUSCI_UART_BREAKCHAR_INTERRUPT));\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~locMask;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Gets the current UART interrupt status.\r
+//!\r
+//! This returns the interrupt status for the UART module based on which flag\r
+//! is passed.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_UART module.\r
+//! \param mask is the masked interrupt flag status to be returned.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b EUSCI_UART_RECEIVE_INTERRUPT_FLAG\r
+//! - \b EUSCI_UART_TRANSMIT_INTERRUPT_FLAG\r
+//! - \b EUSCI_UART_STARTBIT_INTERRUPT_FLAG\r
+//! - \b EUSCI_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG\r
+//!\r
+//! Modified bits of \b UCAxIFG register.\r
+//!\r
+//! \return Logical OR of any of the following:\r
+//! - \b EUSCI_UART_RECEIVE_INTERRUPT_FLAG\r
+//! - \b EUSCI_UART_TRANSMIT_INTERRUPT_FLAG\r
+//! - \b EUSCI_UART_STARTBIT_INTERRUPT_FLAG\r
+//! - \b EUSCI_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG\r
+//! \n indicating the status of the masked flags\r
+//\r
+//*****************************************************************************\r
+uint8_t EUSCI_UART_getInterruptStatus(uint16_t baseAddress,\r
+ uint8_t mask)\r
+{\r
+ assert(!(mask & ~(EUSCI_UART_RECEIVE_INTERRUPT_FLAG\r
+ | EUSCI_UART_TRANSMIT_INTERRUPT_FLAG\r
+ | EUSCI_UART_STARTBIT_INTERRUPT_FLAG\r
+ | EUSCI_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG)));\r
+\r
+ return HWREG16(baseAddress + OFS_UCAxIFG) & mask;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Clears UART interrupt sources.\r
+//!\r
+//! The UART interrupt source is cleared, so that it no longer asserts. The\r
+//! highest interrupt flag is automatically cleared when an interrupt vector\r
+//! generator is used.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_UART module.\r
+//! \param mask is a bit mask of the interrupt sources to be cleared.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b EUSCI_UART_RECEIVE_INTERRUPT_FLAG\r
+//! - \b EUSCI_UART_TRANSMIT_INTERRUPT_FLAG\r
+//! - \b EUSCI_UART_STARTBIT_INTERRUPT_FLAG\r
+//! - \b EUSCI_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG\r
+//!\r
+//! Modified bits of \b UCAxIFG register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void EUSCI_UART_clearInterruptFlag(uint16_t baseAddress, uint8_t mask)\r
+{\r
+ assert(!(mask & ~(EUSCI_UART_RECEIVE_INTERRUPT_FLAG\r
+ | EUSCI_UART_TRANSMIT_INTERRUPT_FLAG\r
+ | EUSCI_UART_STARTBIT_INTERRUPT_FLAG\r
+ | EUSCI_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG)));\r
+\r
+ //Clear the UART interrupt source.\r
+ HWREG16(baseAddress + OFS_UCAxIFG) &= ~(mask);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Enables the UART block.\r
+//!\r
+//! This will enable operation of the UART block.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_UART module.\r
+//!\r
+//! Modified bits are \b UCSWRST of \b UCAxCTL1 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void EUSCI_UART_enable(uint16_t baseAddress)\r
+{\r
+ //Reset the UCSWRST bit to enable the USCI Module\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCSWRST);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Disables the UART block.\r
+//!\r
+//! This will disable operation of the UART block.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_UART module.\r
+//!\r
+//! Modified bits are \b UCSWRST of \b UCAxCTL1 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void EUSCI_UART_disable(uint16_t baseAddress)\r
+{\r
+ //Set the UCSWRST bit to disable the USCI Module\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCSWRST;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Gets the current UART status flags.\r
+//!\r
+//! This returns the status for the UART module based on which flag is passed.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_UART module.\r
+//! \param mask is the masked interrupt flag status to be returned.\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b EUSCI_UART_LISTEN_ENABLE\r
+//! - \b EUSCI_UART_FRAMING_ERROR\r
+//! - \b EUSCI_UART_OVERRUN_ERROR\r
+//! - \b EUSCI_UART_PARITY_ERROR\r
+//! - \b EUSCI_UART_BREAK_DETECT\r
+//! - \b EUSCI_UART_RECEIVE_ERROR\r
+//! - \b EUSCI_UART_ADDRESS_RECEIVED\r
+//! - \b EUSCI_UART_IDLELINE\r
+//! - \b EUSCI_UART_BUSY\r
+//!\r
+//! Modified bits of \b UCAxSTAT register.\r
+//!\r
+//! \return Logical OR of any of the following:\r
+//! - \b EUSCI_UART_LISTEN_ENABLE\r
+//! - \b EUSCI_UART_FRAMING_ERROR\r
+//! - \b EUSCI_UART_OVERRUN_ERROR\r
+//! - \b EUSCI_UART_PARITY_ERROR\r
+//! - \b EUSCI_UART_BREAK_DETECT\r
+//! - \b EUSCI_UART_RECEIVE_ERROR\r
+//! - \b EUSCI_UART_ADDRESS_RECEIVED\r
+//! - \b EUSCI_UART_IDLELINE\r
+//! - \b EUSCI_UART_BUSY\r
+//! \n indicating the status of the masked interrupt flags\r
+//\r
+//*****************************************************************************\r
+uint8_t EUSCI_UART_queryStatusFlags(uint16_t baseAddress,\r
+ uint8_t mask)\r
+{\r
+ assert( 0x00 != mask && (EUSCI_UART_LISTEN_ENABLE +\r
+ EUSCI_UART_FRAMING_ERROR +\r
+ EUSCI_UART_OVERRUN_ERROR +\r
+ EUSCI_UART_PARITY_ERROR +\r
+ EUSCI_UART_BREAK_DETECT +\r
+ EUSCI_UART_RECEIVE_ERROR +\r
+ EUSCI_UART_ADDRESS_RECEIVED +\r
+ EUSCI_UART_IDLELINE +\r
+ EUSCI_UART_BUSY\r
+ ));\r
+\r
+ return HWREG16(baseAddress + OFS_UCAxSTATW) & mask;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets the UART module in dormant mode\r
+//!\r
+//! Puts USCI in sleep mode Only characters that are preceded by an idle-line\r
+//! or with address bit set UCRXIFG. In UART mode with automatic baud-rate\r
+//! detection, only the combination of a break and sync field sets UCRXIFG.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_UART module.\r
+//!\r
+//! Modified bits of \b UCAxCTL1 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void EUSCI_UART_setDormant(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCDORM;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Re-enables UART module from dormant mode\r
+//!\r
+//! Not dormant. All received characters set UCRXIFG.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_UART module.\r
+//!\r
+//! Modified bits are \b UCDORM of \b UCAxCTL1 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void EUSCI_UART_resetDormant(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCDORM;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Transmits the next byte to be transmitted marked as address\r
+//! depending on selected multiprocessor mode\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_UART module.\r
+//! \param transmitAddress is the next byte to be transmitted\r
+//!\r
+//! Modified bits of \b UCAxTXBUF register and bits of \b UCAxCTL1 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void EUSCI_UART_transmitAddress(uint16_t baseAddress,\r
+ uint8_t transmitAddress)\r
+{\r
+ //Set UCTXADDR bit\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCTXADDR;\r
+\r
+ //Place next byte to be sent into the transmit buffer\r
+ HWREG16(baseAddress + OFS_UCAxTXBUF) = transmitAddress;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Transmit break.\r
+//!\r
+//! Transmits a break with the next write to the transmit buffer. In UART mode\r
+//! with automatic baud-rate detection, EUSCI_UART_AUTOMATICBAUDRATE_SYNC(0x55)\r
+//! must be written into UCAxTXBUF to generate the required break/sync fields.\r
+//! Otherwise, DEFAULT_SYNC(0x00) must be written into the transmit buffer.\r
+//! Also ensures module is ready for transmitting the next data.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_UART module.\r
+//!\r
+//! Modified bits of \b UCAxTXBUF register and bits of \b UCAxCTL1 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void EUSCI_UART_transmitBreak(uint16_t baseAddress)\r
+{\r
+ //Set UCTXADDR bit\r
+ HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCTXBRK;\r
+\r
+ //If current mode is automatic baud-rate detection\r
+ if (EUSCI_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE ==\r
+ (HWREG16(baseAddress + OFS_UCAxCTLW0) &\r
+ EUSCI_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE))\r
+ HWREG16(baseAddress + OFS_UCAxTXBUF) = EUSCI_UART_AUTOMATICBAUDRATE_SYNC;\r
+ else\r
+ HWREG16(baseAddress + OFS_UCAxTXBUF) = DEFAULT_SYNC;\r
+\r
+ //If interrupts are not used, poll for flags\r
+ if (!(HWREG16(baseAddress + OFS_UCAxIE) & UCTXIE))\r
+ //Poll for transmit interrupt flag\r
+ while (!(HWREG16(baseAddress + OFS_UCAxIFG) & UCTXIFG)) ;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns the address of the RX Buffer of the UART for the DMA module.\r
+//!\r
+//! Returns the address of the UART RX Buffer. This can be used in conjunction\r
+//! with the DMA to store the received data directly to memory.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_UART module.\r
+//!\r
+//! \return Address of RX Buffer\r
+//\r
+//*****************************************************************************\r
+uint32_t EUSCI_UART_getReceiveBufferAddress(uint16_t baseAddress)\r
+{\r
+ return baseAddress + OFS_UCAxRXBUF;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns the address of the TX Buffer of the UART for the DMA module.\r
+//!\r
+//! Returns the address of the UART TX Buffer. This can be used in conjunction\r
+//! with the DMA to obtain transmitted data directly from memory.\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_UART module.\r
+//!\r
+//! \return Address of TX Buffer\r
+//\r
+//*****************************************************************************\r
+uint32_t EUSCI_UART_getTransmitBufferAddress(uint16_t baseAddress)\r
+{\r
+ return baseAddress + OFS_UCAxTXBUF;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets the deglitch time\r
+//!\r
+//! \param baseAddress is the base address of the EUSCI_UART module.\r
+//! \param deglitchTime is the selected deglitch time\r
+//! Valid values are:\r
+//! - \b EUSCI_UART_DEGLITCH_TIME_2ns\r
+//! - \b EUSCI_UART_DEGLITCH_TIME_50ns\r
+//! - \b EUSCI_UART_DEGLITCH_TIME_100ns\r
+//! - \b EUSCI_UART_DEGLITCH_TIME_200ns\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void EUSCI_UART_selectDeglitchTime(uint16_t baseAddress,\r
+ uint16_t deglitchTime\r
+ )\r
+{\r
+ assert((EUSCI_UART_DEGLITCH_TIME_2ns == deglitchTime) ||\r
+ (EUSCI_UART_DEGLITCH_TIME_50ns == deglitchTime) ||\r
+ (EUSCI_UART_DEGLITCH_TIME_100ns == deglitchTime) ||\r
+ (EUSCI_UART_DEGLITCH_TIME_200ns == deglitchTime)\r
+ );\r
+\r
+ HWREG16(baseAddress + OFS_UCAxCTLW1) &= ~(UCGLIT1 + UCGLIT0);\r
+\r
+ HWREG16(baseAddress + OFS_UCAxCTLW1) |= deglitchTime;\r
+}\r
+\r
+\r
+#endif\r
+//*****************************************************************************\r
+//\r
+//! Close the doxygen group for eusci_uart_api\r
+//! @}\r
+//\r
+//*****************************************************************************\r