diff --git a/source/driverlib/MSP430F5xx_6xx/timer_d.c b/source/driverlib/MSP430F5xx_6xx/timer_d.c
--- /dev/null
@@ -0,0 +1,2401 @@
+/* --COPYRIGHT--,BSD\r
+ * Copyright (c) 2014, Texas Instruments Incorporated\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ * --/COPYRIGHT--*/\r
+//*****************************************************************************\r
+//\r
+// timer_d.c - Driver for the timer_d Module.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup timer_d_api\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "inc/hw_regaccess.h"\r
+#include "inc/hw_memmap.h"\r
+\r
+#ifdef __MSP430_HAS_TxD7__\r
+#include "timer_d.h"\r
+\r
+#include <assert.h>\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief Starts TIMER_D counter\r
+//!\r
+//! NOTE: This function assumes that the timer has been previously configured\r
+//! using TIMER_D_configureContinuousMode, TIMER_D_configureUpMode or\r
+//! TIMER_D_configureUpDownMode.\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_DA module.\r
+//! \param timerMode selects the mode of the timer\r
+//! Valid values are:\r
+//! - \b TIMER_D_STOP_MODE\r
+//! - \b TIMER_D_UP_MODE\r
+//! - \b TIMER_D_CONTINUOUS_MODE [Default]\r
+//! - \b TIMER_D_UPDOWN_MODE\r
+//!\r
+//! Modified bits of \b TDxCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+#include "tlv.h"\r
+void TIMER_D_startCounter( uint16_t baseAddress,\r
+ uint16_t timerMode\r
+ )\r
+{\r
+ assert(\r
+ (TIMER_D_UPDOWN_MODE == timerMode) ||\r
+ (TIMER_D_CONTINUOUS_MODE == timerMode) ||\r
+ (TIMER_D_UP_MODE == timerMode)\r
+ );\r
+\r
+ HWREG16(baseAddress + OFS_TDxCTL0) |= timerMode;\r
+}\r
+//*****************************************************************************\r
+//\r
+//! \brief Configures timer in continuous mode.\r
+//!\r
+//! This API does not start the timer. Timer needs to be started when required\r
+//! using the TIMER_D_start API.\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//! \param param is the pointer to struct for continuous mode initialization.\r
+//!\r
+//! Modified bits of \b TDxCTL0 register and bits of \b TDxCTL1 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+\r
+void TIMER_D_initContinuousMode(uint16_t baseAddress,\r
+ TIMER_D_initContinuousModeParam *param)\r
+{\r
+ assert(param != 0);\r
+\r
+ assert(\r
+ (TIMER_D_DO_CLEAR == param->timerClear) ||\r
+ (TIMER_D_SKIP_CLEAR == param->timerClear)\r
+ );\r
+\r
+ assert(\r
+ (TIMER_D_TDIE_INTERRUPT_ENABLE == param->timerInterruptEnable_TDIE) ||\r
+ (TIMER_D_TDIE_INTERRUPT_DISABLE == param->timerInterruptEnable_TDIE)\r
+ );\r
+\r
+ assert(\r
+ (TIMER_D_CLOCKSOURCE_EXTERNAL_TDCLK == param->clockSource) ||\r
+ (TIMER_D_CLOCKSOURCE_ACLK == param->clockSource) ||\r
+ (TIMER_D_CLOCKSOURCE_SMCLK == param->clockSource) ||\r
+ (TIMER_D_CLOCKSOURCE_INVERTED_EXTERNAL_TDCLK == param->clockSource)\r
+ );\r
+\r
+ assert(\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_1 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_2 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_4 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_8 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_3 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_5 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_6 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_7 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_10 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_12 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_14 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_16 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_20 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_24 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_28 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_32 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_40 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_48 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_56 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_64 == param->clockSourceDivider)\r
+ );\r
+\r
+ assert(\r
+ (TIMER_D_CLOCKINGMODE_EXTERNAL_CLOCK == param->clockingMode) ||\r
+ (TIMER_D_CLOCKINGMODE_HIRES_LOCAL_CLOCK == param->clockingMode) ||\r
+ (TIMER_D_CLOCKINGMODE_AUXILIARY_CLK == param->clockingMode)\r
+ );\r
+\r
+ HWREG16(baseAddress +\r
+ OFS_TDxCTL0) &= ~(TIMER_D_CLOCKSOURCE_INVERTED_EXTERNAL_TDCLK +\r
+ TIMER_D_UPDOWN_MODE +\r
+ TIMER_D_DO_CLEAR +\r
+ TIMER_D_TDIE_INTERRUPT_ENABLE +\r
+ ID__8\r
+ );\r
+ HWREG16(baseAddress + OFS_TDxCTL1) &= ~(TDCLKM0 + TDCLKM1 + TDIDEX_7);\r
+\r
+ HWREG16(baseAddress + OFS_TDxCTL0) |= param->clockSource;\r
+ HWREG16(baseAddress + OFS_TDxCTL1) |= (param->clockingMode +\r
+ ((param->clockSourceDivider & 0x7) << 8));\r
+\r
+ HWREG16(baseAddress + OFS_TDxCTL0) |= (param->timerClear +\r
+ param->timerInterruptEnable_TDIE +\r
+ ((param->clockSourceDivider >> 3) << 6));\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief DEPRECATED - Configures timer in continuous mode.\r
+//!\r
+//! This API does not start the timer. Timer needs to be started when required\r
+//! using the TIMER_D_start API.\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//! \param clockSource selects Clock source.\r
+//! Valid values are:\r
+//! - \b TIMER_D_CLOCKSOURCE_EXTERNAL_TDCLK [Default]\r
+//! - \b TIMER_D_CLOCKSOURCE_ACLK\r
+//! - \b TIMER_D_CLOCKSOURCE_SMCLK\r
+//! - \b TIMER_D_CLOCKSOURCE_INVERTED_EXTERNAL_TDCLK\r
+//! \param clockSourceDivider is the divider for clock source.\r
+//! Valid values are:\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_1 [Default]\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_2\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_3\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_4\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_5\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_6\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_7\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_8\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_10\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_12\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_14\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_16\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_20\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_24\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_28\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_32\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_40\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_48\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_56\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_64\r
+//! \param clockingMode is the selected clock mode register values.\r
+//! Valid values are:\r
+//! - \b TIMER_D_CLOCKINGMODE_EXTERNAL_CLOCK [Default]\r
+//! - \b TIMER_D_CLOCKINGMODE_HIRES_LOCAL_CLOCK\r
+//! - \b TIMER_D_CLOCKINGMODE_AUXILIARY_CLK\r
+//! \param timerInterruptEnable_TDIE is to enable or disable timer interrupt\r
+//! Valid values are:\r
+//! - \b TIMER_D_TDIE_INTERRUPT_ENABLE\r
+//! - \b TIMER_D_TDIE_INTERRUPT_DISABLE [Default]\r
+//! \param timerClear decides if timer clock divider, count direction, count\r
+//! need to be reset.\r
+//! Valid values are:\r
+//! - \b TIMER_D_DO_CLEAR\r
+//! - \b TIMER_D_SKIP_CLEAR [Default]\r
+//!\r
+//! Modified bits of \b TDxCTL0 register and bits of \b TDxCTL1 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+\r
+void TIMER_D_configureContinuousMode( uint16_t baseAddress,\r
+ uint16_t clockSource,\r
+ uint16_t clockSourceDivider,\r
+ uint16_t clockingMode,\r
+ uint16_t timerInterruptEnable_TDIE,\r
+ uint16_t timerClear\r
+ )\r
+{\r
+ TIMER_D_initContinuousModeParam param = { 0 };\r
+\r
+ param.clockSource = clockSource;\r
+ param.clockSourceDivider = clockSourceDivider;\r
+ param.clockingMode = clockingMode;\r
+ param.timerInterruptEnable_TDIE = timerInterruptEnable_TDIE;\r
+ param.timerClear = timerClear;\r
+\r
+ TIMER_D_initContinuousMode(baseAddress, ¶m);\r
+}\r
+//*****************************************************************************\r
+//\r
+//! \brief Configures timer in up mode.\r
+//!\r
+//! This API does not start the timer. Timer needs to be started when required\r
+//! using the TIMER_D_start API.\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//! \param param is the pointer to struct for up mode initialization.\r
+//!\r
+//! Modified bits of \b TDxCCR0 register, bits of \b TDxCCTL0 register, bits of\r
+//! \b TDxCTL0 register and bits of \b TDxCTL1 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void TIMER_D_initUpMode(uint16_t baseAddress, TIMER_D_initUpModeParam *param)\r
+{\r
+ assert(param != 0);\r
+\r
+ assert(\r
+ (TIMER_D_DO_CLEAR == param->timerClear) ||\r
+ (TIMER_D_SKIP_CLEAR == param->timerClear)\r
+ );\r
+\r
+ assert(\r
+ (TIMER_D_CLOCKSOURCE_EXTERNAL_TDCLK == param->clockSource) ||\r
+ (TIMER_D_CLOCKSOURCE_ACLK == param->clockSource) ||\r
+ (TIMER_D_CLOCKSOURCE_SMCLK == param->clockSource) ||\r
+ (TIMER_D_CLOCKSOURCE_INVERTED_EXTERNAL_TDCLK == param->clockSource)\r
+ );\r
+\r
+ assert(\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_1 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_2 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_4 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_8 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_3 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_5 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_6 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_7 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_10 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_12 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_14 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_16 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_20 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_24 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_28 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_32 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_40 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_48 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_56 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_64 == param->clockSourceDivider)\r
+ );\r
+\r
+ assert(\r
+ (TIMER_D_CLOCKINGMODE_EXTERNAL_CLOCK == param->clockingMode) ||\r
+ (TIMER_D_CLOCKINGMODE_HIRES_LOCAL_CLOCK == param->clockingMode) ||\r
+ (TIMER_D_CLOCKINGMODE_AUXILIARY_CLK == param->clockingMode)\r
+ );\r
+\r
+ HWREG16(baseAddress + OFS_TDxCTL0) &=\r
+ ~(TIMER_D_CLOCKSOURCE_INVERTED_EXTERNAL_TDCLK +\r
+ TIMER_D_UPDOWN_MODE +\r
+ TIMER_D_DO_CLEAR +\r
+ TIMER_D_TDIE_INTERRUPT_ENABLE +\r
+ ID__8\r
+ );\r
+ HWREG16(baseAddress + OFS_TDxCTL1) &= ~(TDCLKM0 + TDCLKM1 + TDIDEX_7);\r
+\r
+ HWREG16(baseAddress + OFS_TDxCTL0) |= param->clockSource;\r
+ HWREG16(baseAddress + OFS_TDxCTL1) |= (param->clockingMode +\r
+ ((param->clockSourceDivider & 0x7) << 8));\r
+\r
+ HWREG16(baseAddress + OFS_TDxCTL0) |= (TIMER_D_STOP_MODE +\r
+ param->timerClear +\r
+ param->timerInterruptEnable_TDIE +\r
+ ((param->clockSourceDivider >> 3) << 6));\r
+\r
+ if (TIMER_D_CCIE_CCR0_INTERRUPT_ENABLE ==\r
+ param->captureCompareInterruptEnable_CCR0_CCIE)\r
+ HWREG16(baseAddress + OFS_TDxCCTL0) |= TIMER_D_CCIE_CCR0_INTERRUPT_ENABLE;\r
+ else\r
+ HWREG16(baseAddress + OFS_TDxCCTL0) &= ~TIMER_D_CCIE_CCR0_INTERRUPT_ENABLE;\r
+\r
+ HWREG16(baseAddress + OFS_TDxCCR0) = param->timerPeriod;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief DEPRECATED - Configures timer in up mode.\r
+//!\r
+//! This API does not start the timer. Timer needs to be started when required\r
+//! using the TIMER_D_start API.\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//! \param clockSource selects Clock source.\r
+//! Valid values are:\r
+//! - \b TIMER_D_CLOCKSOURCE_EXTERNAL_TDCLK [Default]\r
+//! - \b TIMER_D_CLOCKSOURCE_ACLK\r
+//! - \b TIMER_D_CLOCKSOURCE_SMCLK\r
+//! - \b TIMER_D_CLOCKSOURCE_INVERTED_EXTERNAL_TDCLK\r
+//! \param clockSourceDivider is the divider for clock source.\r
+//! Valid values are:\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_1 [Default]\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_2\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_3\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_4\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_5\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_6\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_7\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_8\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_10\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_12\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_14\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_16\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_20\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_24\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_28\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_32\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_40\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_48\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_56\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_64\r
+//! \param clockingMode is the selected clock mode register values.\r
+//! Valid values are:\r
+//! - \b TIMER_D_CLOCKINGMODE_EXTERNAL_CLOCK [Default]\r
+//! - \b TIMER_D_CLOCKINGMODE_HIRES_LOCAL_CLOCK\r
+//! - \b TIMER_D_CLOCKINGMODE_AUXILIARY_CLK\r
+//! \param timerPeriod is the specified timer period. This is the value that\r
+//! gets written into the CCR0. Limited to 16 bits [uint16_t]\r
+//! \param timerInterruptEnable_TDIE is to enable or disable timer interrupt\r
+//! Valid values are:\r
+//! - \b TIMER_D_TDIE_INTERRUPT_ENABLE\r
+//! - \b TIMER_D_TDIE_INTERRUPT_DISABLE [Default]\r
+//! \param captureCompareInterruptEnable_CCR0_CCIE is to enable or disable\r
+//! timer CCR0 captureComapre interrupt.\r
+//! Valid values are:\r
+//! - \b TIMER_D_CCIE_CCR0_INTERRUPT_ENABLE\r
+//! - \b TIMER_D_CCIE_CCR0_INTERRUPT_DISABLE [Default]\r
+//! \param timerClear decides if timer clock divider, count direction, count\r
+//! need to be reset.\r
+//! Valid values are:\r
+//! - \b TIMER_D_DO_CLEAR\r
+//! - \b TIMER_D_SKIP_CLEAR [Default]\r
+//!\r
+//! Modified bits of \b TDxCCR0 register, bits of \b TDxCCTL0 register, bits of\r
+//! \b TDxCTL0 register and bits of \b TDxCTL1 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+\r
+void TIMER_D_configureUpMode( uint16_t baseAddress,\r
+ uint16_t clockSource,\r
+ uint16_t clockSourceDivider,\r
+ uint16_t clockingMode,\r
+ uint16_t timerPeriod,\r
+ uint16_t timerInterruptEnable_TDIE,\r
+ uint16_t captureCompareInterruptEnable_CCR0_CCIE,\r
+ uint16_t timerClear\r
+ )\r
+{\r
+ TIMER_D_initUpModeParam param = { 0 };\r
+\r
+ param.clockSource = clockSource;\r
+ param.clockSourceDivider = clockSourceDivider;\r
+ param.clockingMode = clockingMode;\r
+ param.timerPeriod = timerPeriod;\r
+ param.timerInterruptEnable_TDIE = timerInterruptEnable_TDIE;\r
+ param.captureCompareInterruptEnable_CCR0_CCIE =\r
+ captureCompareInterruptEnable_CCR0_CCIE;\r
+ param.timerClear = timerClear;\r
+\r
+ TIMER_D_initUpMode(baseAddress, ¶m);\r
+\r
+}\r
+//*****************************************************************************\r
+//\r
+//! \brief Configures timer in up down mode.\r
+//!\r
+//! This API does not start the timer. Timer needs to be started when required\r
+//! using the TIMER_D_start API.\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//! \param param is the pointer to struct for up-down mode initialization.\r
+//!\r
+//! Modified bits of \b TDxCCR0 register, bits of \b TDxCCTL0 register, bits of\r
+//! \b TDxCTL0 register and bits of \b TDxCTL1 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void TIMER_D_initUpDownMode(uint16_t baseAddress,\r
+ TIMER_D_initUpDownModeParam *param)\r
+{\r
+ assert(param != 0);\r
+\r
+ assert(\r
+ (TIMER_D_DO_CLEAR == param->timerClear) ||\r
+ (TIMER_D_SKIP_CLEAR == param->timerClear)\r
+ );\r
+\r
+ assert(\r
+ (TIMER_D_CLOCKSOURCE_EXTERNAL_TDCLK == param->clockSource) ||\r
+ (TIMER_D_CLOCKSOURCE_ACLK == param->clockSource) ||\r
+ (TIMER_D_CLOCKSOURCE_SMCLK == param->clockSource) ||\r
+ (TIMER_D_CLOCKSOURCE_INVERTED_EXTERNAL_TDCLK == param->clockSource)\r
+ );\r
+\r
+ assert(\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_1 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_2 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_4 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_8 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_3 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_5 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_6 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_7 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_10 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_12 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_14 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_16 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_20 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_24 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_28 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_32 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_40 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_48 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_56 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_64 == param->clockSourceDivider)\r
+ );\r
+\r
+ assert(\r
+ (TIMER_D_CLOCKINGMODE_EXTERNAL_CLOCK == param->clockingMode) ||\r
+ (TIMER_D_CLOCKINGMODE_HIRES_LOCAL_CLOCK == param->clockingMode) ||\r
+ (TIMER_D_CLOCKINGMODE_AUXILIARY_CLK == param->clockingMode)\r
+ );\r
+\r
+ HWREG16(baseAddress + OFS_TDxCTL0) &=\r
+ ~(TIMER_D_CLOCKSOURCE_INVERTED_EXTERNAL_TDCLK +\r
+ TIMER_D_UPDOWN_MODE +\r
+ TIMER_D_DO_CLEAR +\r
+ TIMER_D_TDIE_INTERRUPT_ENABLE +\r
+ ID__8\r
+ );\r
+ HWREG16(baseAddress + OFS_TDxCTL1) &= ~(TDCLKM0 + TDCLKM1 + TDIDEX_7);\r
+\r
+ HWREG16(baseAddress + OFS_TDxCTL0) |= param->clockSource;\r
+ HWREG16(baseAddress + OFS_TDxCTL1) |= (param->clockingMode +\r
+ ((param->clockSourceDivider & 0x7) << 8));\r
+\r
+ HWREG16(baseAddress + OFS_TDxCTL0) |= (TIMER_D_STOP_MODE +\r
+ param->timerClear +\r
+ param->timerInterruptEnable_TDIE +\r
+ ((param->clockSourceDivider >> 3) << 6));\r
+\r
+ if (TIMER_D_CCIE_CCR0_INTERRUPT_ENABLE ==\r
+ param->captureCompareInterruptEnable_CCR0_CCIE)\r
+ HWREG16(baseAddress + OFS_TDxCCTL0) |= TIMER_D_CCIE_CCR0_INTERRUPT_ENABLE;\r
+ else\r
+ HWREG16(baseAddress + OFS_TDxCCTL0) &= ~TIMER_D_CCIE_CCR0_INTERRUPT_ENABLE;\r
+\r
+ HWREG16(baseAddress + OFS_TDxCCR0) = param->timerPeriod;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief DEPRECATED - Configures timer in up down mode.\r
+//!\r
+//! This API does not start the timer. Timer needs to be started when required\r
+//! using the TIMER_D_start API.\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//! \param clockSource selects Clock source.\r
+//! Valid values are:\r
+//! - \b TIMER_D_CLOCKSOURCE_EXTERNAL_TDCLK [Default]\r
+//! - \b TIMER_D_CLOCKSOURCE_ACLK\r
+//! - \b TIMER_D_CLOCKSOURCE_SMCLK\r
+//! - \b TIMER_D_CLOCKSOURCE_INVERTED_EXTERNAL_TDCLK\r
+//! \param clockSourceDivider is the divider for clock source.\r
+//! Valid values are:\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_1 [Default]\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_2\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_3\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_4\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_5\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_6\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_7\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_8\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_10\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_12\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_14\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_16\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_20\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_24\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_28\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_32\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_40\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_48\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_56\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_64\r
+//! \param clockingMode is the selected clock mode register values.\r
+//! Valid values are:\r
+//! - \b TIMER_D_CLOCKINGMODE_EXTERNAL_CLOCK [Default]\r
+//! - \b TIMER_D_CLOCKINGMODE_HIRES_LOCAL_CLOCK\r
+//! - \b TIMER_D_CLOCKINGMODE_AUXILIARY_CLK\r
+//! \param timerPeriod is the specified timer period\r
+//! \param timerInterruptEnable_TDIE is to enable or disable timer interrupt\r
+//! Valid values are:\r
+//! - \b TIMER_D_TDIE_INTERRUPT_ENABLE\r
+//! - \b TIMER_D_TDIE_INTERRUPT_DISABLE [Default]\r
+//! \param captureCompareInterruptEnable_CCR0_CCIE is to enable or disable\r
+//! timer CCR0 captureComapre interrupt.\r
+//! Valid values are:\r
+//! - \b TIMER_D_CCIE_CCR0_INTERRUPT_ENABLE\r
+//! - \b TIMER_D_CCIE_CCR0_INTERRUPT_DISABLE [Default]\r
+//! \param timerClear decides if timer clock divider, count direction, count\r
+//! need to be reset.\r
+//! Valid values are:\r
+//! - \b TIMER_D_DO_CLEAR\r
+//! - \b TIMER_D_SKIP_CLEAR [Default]\r
+//!\r
+//! Modified bits of \b TDxCCR0 register, bits of \b TDxCCTL0 register, bits of\r
+//! \b TDxCTL0 register and bits of \b TDxCTL1 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+\r
+void TIMER_D_configureUpDownMode(\r
+ uint16_t baseAddress,\r
+ uint16_t clockSource,\r
+ uint16_t clockSourceDivider,\r
+ uint16_t clockingMode,\r
+ uint16_t timerPeriod,\r
+ uint16_t timerInterruptEnable_TDIE,\r
+ uint16_t captureCompareInterruptEnable_CCR0_CCIE,\r
+ uint16_t timerClear\r
+ )\r
+{\r
+ TIMER_D_initUpDownModeParam param = { 0 };\r
+\r
+ param.clockSource = clockSource;\r
+ param.clockSourceDivider = clockSourceDivider;\r
+ param.clockingMode = clockingMode;\r
+ param.timerPeriod = timerPeriod;\r
+ param.timerInterruptEnable_TDIE = timerInterruptEnable_TDIE;\r
+ param.captureCompareInterruptEnable_CCR0_CCIE =\r
+ captureCompareInterruptEnable_CCR0_CCIE;\r
+ param.timerClear = timerClear;\r
+\r
+ TIMER_D_initUpDownMode(baseAddress, ¶m);\r
+}\r
+//*****************************************************************************\r
+//\r
+//! \brief Initializes Capture Mode\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//! \param param is the pointer to struct for capture mode initialization.\r
+//!\r
+//! Modified bits of \b TDxCCTLn register and bits of \b TDxCTL2 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void TIMER_D_initCaptureMode(uint16_t baseAddress,\r
+ TIMER_D_initCaptureModeParam *param)\r
+{\r
+ assert(param != 0);\r
+\r
+ assert((TIMER_D_CAPTURECOMPARE_REGISTER_0 == param->captureRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_1 == param->captureRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_2 == param->captureRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_3 == param->captureRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_4 == param->captureRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_5 == param->captureRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_6 == param->captureRegister)\r
+ );\r
+\r
+ assert((TIMER_D_CAPTUREMODE_NO_CAPTURE == param->captureMode) ||\r
+ (TIMER_D_CAPTUREMODE_RISING_EDGE == param->captureMode) ||\r
+ (TIMER_D_CAPTUREMODE_FALLING_EDGE == param->captureMode) ||\r
+ (TIMER_D_CAPTUREMODE_RISING_AND_FALLING_EDGE == param->captureMode)\r
+ );\r
+\r
+ assert((TIMER_D_CAPTURE_INPUTSELECT_CCIxA == param->captureInputSelect) ||\r
+ (TIMER_D_CAPTURE_INPUTSELECT_CCIxB == param->captureInputSelect) ||\r
+ (TIMER_D_CAPTURE_INPUTSELECT_GND == param->captureInputSelect) ||\r
+ (TIMER_D_CAPTURE_INPUTSELECT_Vcc == param->captureInputSelect)\r
+ );\r
+\r
+ assert((TIMER_D_CAPTURE_ASYNCHRONOUS == param->synchronizeCaptureSource) ||\r
+ (TIMER_D_CAPTURE_SYNCHRONOUS == param->synchronizeCaptureSource)\r
+ );\r
+\r
+ assert(\r
+ (TIMER_D_CAPTURECOMPARE_INTERRUPT_DISABLE == param->captureInterruptEnable) ||\r
+ (TIMER_D_CAPTURECOMPARE_INTERRUPT_ENABLE == param->captureInterruptEnable)\r
+ );\r
+\r
+ assert((TIMER_D_OUTPUTMODE_OUTBITVALUE == param->captureOutputMode) ||\r
+ (TIMER_D_OUTPUTMODE_SET == param->captureOutputMode) ||\r
+ (TIMER_D_OUTPUTMODE_TOGGLE_RESET == param->captureOutputMode) ||\r
+ (TIMER_D_OUTPUTMODE_SET_RESET == param->captureOutputMode) ||\r
+ (TIMER_D_OUTPUTMODE_TOGGLE == param->captureOutputMode) ||\r
+ (TIMER_D_OUTPUTMODE_RESET == param->captureOutputMode) ||\r
+ (TIMER_D_OUTPUTMODE_TOGGLE_SET == param->captureOutputMode) ||\r
+ (TIMER_D_OUTPUTMODE_RESET_SET == param->captureOutputMode)\r
+ );\r
+\r
+ assert((TIMER_D_SINGLE_CAPTURE_MODE == param->channelCaptureMode) ||\r
+ (TIMER_D_DUAL_CAPTURE_MODE == param->channelCaptureMode)\r
+ );\r
+\r
+ //CaptureCompare register 0 only supports certain modes\r
+ assert((TIMER_D_CAPTURECOMPARE_REGISTER_0 == param->captureRegister) &&\r
+ ((TIMER_D_OUTPUTMODE_OUTBITVALUE == param->captureOutputMode) ||\r
+ (TIMER_D_OUTPUTMODE_SET == param->captureOutputMode) ||\r
+ (TIMER_D_OUTPUTMODE_TOGGLE == param->captureOutputMode) ||\r
+ (TIMER_D_OUTPUTMODE_RESET == param->captureOutputMode)));\r
+\r
+ HWREG16(baseAddress + param->captureRegister ) |= CAP;\r
+\r
+ HWREG8(baseAddress + OFS_TDxCTL2) |=\r
+ (param->channelCaptureMode << ((param->captureRegister - TIMER_D_CAPTURECOMPARE_REGISTER_0) / 6));\r
+\r
+ HWREG16(baseAddress + param->captureRegister) &=\r
+ ~(TIMER_D_CAPTUREMODE_RISING_AND_FALLING_EDGE +\r
+ TIMER_D_CAPTURE_INPUTSELECT_Vcc +\r
+ TIMER_D_CAPTURE_SYNCHRONOUS +\r
+ TIMER_D_DO_CLEAR +\r
+ TIMER_D_TDIE_INTERRUPT_ENABLE +\r
+ CM_3\r
+ );\r
+\r
+ HWREG16(baseAddress + param->captureRegister) |= (param->captureMode +\r
+ param->captureInputSelect +\r
+ param->synchronizeCaptureSource +\r
+ param->captureInterruptEnable +\r
+ param->captureOutputMode\r
+ );\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief DEPRECATED - Initializes Capture Mode\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//! \param captureRegister selects the Capture register being used. Refer to\r
+//! datasheet to ensure the device has the capture compare register\r
+//! being used\r
+//! Valid values are:\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_0\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_1\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_2\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_3\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_4\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_5\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_6\r
+//! \param captureMode is the capture mode selected.\r
+//! Valid values are:\r
+//! - \b TIMER_D_CAPTUREMODE_NO_CAPTURE [Default]\r
+//! - \b TIMER_D_CAPTUREMODE_RISING_EDGE\r
+//! - \b TIMER_D_CAPTUREMODE_FALLING_EDGE\r
+//! - \b TIMER_D_CAPTUREMODE_RISING_AND_FALLING_EDGE\r
+//! \param captureInputSelect decides the Input Select\r
+//! Valid values are:\r
+//! - \b TIMER_D_CAPTURE_INPUTSELECT_CCIxA [Default]\r
+//! - \b TIMER_D_CAPTURE_INPUTSELECT_CCIxB\r
+//! - \b TIMER_D_CAPTURE_INPUTSELECT_GND\r
+//! - \b TIMER_D_CAPTURE_INPUTSELECT_Vcc\r
+//! \param synchronizeCaptureSource decides if capture source should be\r
+//! synchronized with timer clock\r
+//! Valid values are:\r
+//! - \b TIMER_D_CAPTURE_ASYNCHRONOUS [Default]\r
+//! - \b TIMER_D_CAPTURE_SYNCHRONOUS\r
+//!\r
+//! Modified bits of \b TDxCCTLn register and bits of \b TDxCTL2 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+\r
+void TIMER_D_initCapture(uint16_t baseAddress,\r
+ uint16_t captureRegister,\r
+ uint16_t captureMode,\r
+ uint16_t captureInputSelect,\r
+ uint16_t synchronizeCaptureSource,\r
+ uint16_t captureInterruptEnable,\r
+ uint16_t captureOutputMode,\r
+ uint8_t channelCaptureMode\r
+ )\r
+{\r
+ TIMER_D_initCaptureModeParam param = { 0 };\r
+\r
+ param.captureRegister = captureRegister;\r
+ param.captureMode = captureMode;\r
+ param.captureInputSelect = captureInputSelect;\r
+ param.synchronizeCaptureSource = synchronizeCaptureSource;\r
+ param.captureInterruptEnable = captureInterruptEnable;\r
+ param.captureOutputMode = captureOutputMode;\r
+ param.channelCaptureMode = channelCaptureMode;\r
+\r
+ TIMER_D_initCaptureMode(baseAddress, ¶m);\r
+}\r
+//*****************************************************************************\r
+//\r
+//! \brief Initializes Compare Mode\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//! \param param is the pointer to struct for compare mode initialization.\r
+//!\r
+//! Modified bits of \b TDxCCTLn register and bits of \b TDxCCRn register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void TIMER_D_initCompareMode(uint16_t baseAddress,\r
+ TIMER_D_initCompareModeParam *param)\r
+{\r
+ assert(param != 0);\r
+\r
+ assert((TIMER_D_CAPTURECOMPARE_REGISTER_0 == param->compareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_1 == param->compareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_2 == param->compareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_3 == param->compareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_4 == param->compareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_5 == param->compareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_6 == param->compareRegister)\r
+ );\r
+\r
+ assert((TIMER_D_CAPTURECOMPARE_INTERRUPT_ENABLE == param->compareInterruptEnable) ||\r
+ (TIMER_D_CAPTURECOMPARE_INTERRUPT_DISABLE == param->compareInterruptEnable)\r
+ );\r
+\r
+ assert((TIMER_D_OUTPUTMODE_OUTBITVALUE == param->compareOutputMode) ||\r
+ (TIMER_D_OUTPUTMODE_SET == param->compareOutputMode) ||\r
+ (TIMER_D_OUTPUTMODE_TOGGLE_RESET == param->compareOutputMode) ||\r
+ (TIMER_D_OUTPUTMODE_SET_RESET == param->compareOutputMode) ||\r
+ (TIMER_D_OUTPUTMODE_TOGGLE == param->compareOutputMode) ||\r
+ (TIMER_D_OUTPUTMODE_RESET == param->compareOutputMode) ||\r
+ (TIMER_D_OUTPUTMODE_TOGGLE_SET == param->compareOutputMode) ||\r
+ (TIMER_D_OUTPUTMODE_RESET_SET == param->compareOutputMode)\r
+ );\r
+\r
+ //CaptureCompare register 0 only supports certain modes\r
+ assert((TIMER_D_CAPTURECOMPARE_REGISTER_0 == param->compareRegister) &&\r
+ ((TIMER_D_OUTPUTMODE_OUTBITVALUE == param->compareOutputMode) ||\r
+ (TIMER_D_OUTPUTMODE_SET == param->compareOutputMode) ||\r
+ (TIMER_D_OUTPUTMODE_TOGGLE == param->compareOutputMode) ||\r
+ (TIMER_D_OUTPUTMODE_RESET == param->compareOutputMode)));\r
+\r
+ HWREG16(baseAddress + param->compareRegister ) &= ~CAP;\r
+\r
+ HWREG16(baseAddress + param->compareRegister) &=\r
+ ~(TIMER_D_CAPTURECOMPARE_INTERRUPT_ENABLE +\r
+ TIMER_D_OUTPUTMODE_RESET_SET\r
+ );\r
+\r
+ HWREG16(baseAddress + param->compareRegister) |= (param->compareInterruptEnable +\r
+ param->compareOutputMode\r
+ );\r
+\r
+ HWREG16(baseAddress + param->compareRegister + 2) = param->compareValue;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief DEPRECATED - Initializes Compare Mode\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//! \param compareRegister selects the Capture register being used.\r
+//! Valid values are:\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_0\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_1\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_2\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_3\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_4\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_5\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_6\r
+//! \param compareInterruptEnable is to enable or disable timer captureComapre\r
+//! interrupt.\r
+//! Valid values are:\r
+//! - \b TIMER_D_CAPTURECOMPARE_INTERRUPT_ENABLE\r
+//! - \b TIMER_D_CAPTURECOMPARE_INTERRUPT_DISABLE [Default]\r
+//! \param compareOutputMode specifies the output mode.\r
+//! Valid values are:\r
+//! - \b TIMER_D_OUTPUTMODE_OUTBITVALUE [Default]\r
+//! - \b TIMER_D_OUTPUTMODE_SET\r
+//! - \b TIMER_D_OUTPUTMODE_TOGGLE_RESET\r
+//! - \b TIMER_D_OUTPUTMODE_SET_RESET\r
+//! - \b TIMER_D_OUTPUTMODE_TOGGLE\r
+//! - \b TIMER_D_OUTPUTMODE_RESET\r
+//! - \b TIMER_D_OUTPUTMODE_TOGGLE_SET\r
+//! - \b TIMER_D_OUTPUTMODE_RESET_SET\r
+//! \param compareValue is the count to be compared with in compare mode\r
+//!\r
+//! Modified bits of \b TDxCCTLn register and bits of \b TDxCCRn register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+\r
+void TIMER_D_initCompare( uint16_t baseAddress,\r
+ uint16_t compareRegister,\r
+ uint16_t compareInterruptEnable,\r
+ uint16_t compareOutputMode,\r
+ uint16_t compareValue\r
+ )\r
+{\r
+ TIMER_D_initCompareModeParam param = { 0 };\r
+\r
+ param.compareRegister = compareRegister;\r
+ param.compareInterruptEnable = compareInterruptEnable;\r
+ param.compareOutputMode = compareOutputMode;\r
+ param.compareValue = compareValue;\r
+\r
+ TIMER_D_initCompareMode(baseAddress, ¶m);\r
+}\r
+//*****************************************************************************\r
+//\r
+//! \brief Enable timer interrupt\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//!\r
+//! Modified bits of \b TDxCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+\r
+void TIMER_D_enableTimerInterrupt(uint16_t baseAddress)\r
+{\r
+ HWREG8(baseAddress + OFS_TDxCTL0) &= ~TDIFG;\r
+ HWREG8(baseAddress + OFS_TDxCTL0) |= TDIE;\r
+}\r
+//*****************************************************************************\r
+//\r
+//! \brief Enable High Resolution interrupt\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//! \param mask is the mask of interrupts to enable\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b TIMER_D_HIGH_RES_FREQUENCY_UNLOCK\r
+//! - \b TIMER_D_HIGH_RES_FREQUENCY_LOCK\r
+//! - \b TIMER_D_HIGH_RES_FAIL_HIGH\r
+//! - \b TIMER_D_HIGH_RES_FAIL_LOW\r
+//!\r
+//! Modified bits of \b TDxHINT register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+\r
+void TIMER_D_enableHighResInterrupt(uint16_t baseAddress,\r
+ uint16_t mask)\r
+{\r
+ HWREG16(baseAddress + OFS_TDxHINT) &= ~(mask >> 8);\r
+ HWREG16(baseAddress + OFS_TDxHINT) |= mask;\r
+}\r
+//*****************************************************************************\r
+//\r
+//! \brief Disable timer interrupt\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//!\r
+//! Modified bits of \b TDxCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+\r
+void TIMER_D_disableTimerInterrupt(uint16_t baseAddress)\r
+{\r
+ HWREG8(baseAddress + OFS_TDxCTL0) &= ~TDIE;\r
+}\r
+//*****************************************************************************\r
+//\r
+//! \brief Disable High Resolution interrupt\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//! \param mask is the mask of interrupts to disable\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b TIMER_D_HIGH_RES_FREQUENCY_UNLOCK\r
+//! - \b TIMER_D_HIGH_RES_FREQUENCY_LOCK\r
+//! - \b TIMER_D_HIGH_RES_FAIL_HIGH\r
+//! - \b TIMER_D_HIGH_RES_FAIL_LOW\r
+//!\r
+//! Modified bits of \b TDxHINT register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+\r
+void TIMER_D_disableHighResInterrupt(uint16_t baseAddress,\r
+ uint16_t mask)\r
+{\r
+ HWREG16(baseAddress + OFS_TDxHINT) &= ~mask;\r
+}\r
+//*****************************************************************************\r
+//\r
+//! \brief Get timer interrupt status\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//!\r
+//! \return One of the following:\r
+//! - \b TIMER_D_INTERRUPT_NOT_PENDING\r
+//! - \b TIMER_D_INTERRUPT_PENDING\r
+//! \n indicating the timer interrupt status\r
+//\r
+//*****************************************************************************\r
+\r
+uint32_t TIMER_D_getTimerInterruptStatus(uint16_t baseAddress)\r
+{\r
+ return HWREG8(baseAddress + OFS_TDxCTL0) & TDIFG;\r
+}\r
+//*****************************************************************************\r
+//\r
+//! \brief Enable capture compare interrupt\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//! \param captureCompareRegister is the selected capture compare register\r
+//! Valid values are:\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_0\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_1\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_2\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_3\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_4\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_5\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_6\r
+//!\r
+//! Modified bits of \b TDxCCTLn register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+\r
+void TIMER_D_enableCaptureCompareInterrupt(uint16_t baseAddress,\r
+ uint16_t captureCompareRegister\r
+ )\r
+{\r
+ assert((TIMER_D_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_1 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_2 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_3 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_4 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_5 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_6 == captureCompareRegister)\r
+ );\r
+\r
+ HWREG8(baseAddress + captureCompareRegister) &= ~CCIFG;\r
+ HWREG16(baseAddress + captureCompareRegister) |= CCIE;\r
+}\r
+//*****************************************************************************\r
+//\r
+//! \brief Disable capture compare interrupt\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//! \param captureCompareRegister is the selected capture compare register\r
+//! Valid values are:\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_0\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_1\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_2\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_3\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_4\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_5\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_6\r
+//!\r
+//! Modified bits of \b TDxCCTLn register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+\r
+void TIMER_D_disableCaptureCompareInterrupt(uint16_t baseAddress,\r
+ uint16_t captureCompareRegister\r
+ )\r
+{\r
+ assert((TIMER_D_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_1 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_2 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_3 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_4 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_5 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_6 == captureCompareRegister)\r
+ );\r
+ HWREG16(baseAddress + captureCompareRegister) &= ~CCIE;\r
+}\r
+//*****************************************************************************\r
+//\r
+//! \brief Return capture compare interrupt status\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//! \param captureCompareRegister is the selected capture compare register\r
+//! Valid values are:\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_0\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_1\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_2\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_3\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_4\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_5\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_6\r
+//! \param mask is the mask for the interrupt status\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b TIMER_D_CAPTURE_OVERFLOW\r
+//! - \b TIMER_D_CAPTURECOMPARE_INTERRUPT_FLAG\r
+//!\r
+//! \return Logical OR of any of the following:\r
+//! - \b TIMER_D_CAPTURE_OVERFLOW\r
+//! - \b TIMER_D_CAPTURECOMPARE_INTERRUPT_FLAG\r
+//! \n indicating the status of the masked flags\r
+//\r
+//*****************************************************************************\r
+\r
+uint32_t TIMER_D_getCaptureCompareInterruptStatus(uint16_t baseAddress,\r
+ uint16_t captureCompareRegister,\r
+ uint16_t mask\r
+ )\r
+{\r
+ return HWREG16(baseAddress + captureCompareRegister) & mask;\r
+}\r
+//*****************************************************************************\r
+//\r
+//! \brief Returns High Resolution interrupt status\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//! \param mask is the mask for the interrupt status\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b TIMER_D_HIGH_RES_FREQUENCY_UNLOCK\r
+//! - \b TIMER_D_HIGH_RES_FREQUENCY_LOCK\r
+//! - \b TIMER_D_HIGH_RES_FAIL_HIGH\r
+//! - \b TIMER_D_HIGH_RES_FAIL_LOW\r
+//!\r
+//! Modified bits of \b TDxHINT register.\r
+//!\r
+//! \return Logical OR of any of the following:\r
+//! - \b TIMER_D_HIGH_RES_FREQUENCY_UNLOCK\r
+//! - \b TIMER_D_HIGH_RES_FREQUENCY_LOCK\r
+//! - \b TIMER_D_HIGH_RES_FAIL_HIGH\r
+//! - \b TIMER_D_HIGH_RES_FAIL_LOW\r
+//! \n indicating the status of the masked interrupts\r
+//\r
+//*****************************************************************************\r
+\r
+uint16_t TIMER_D_getHighResInterruptStatus(uint16_t baseAddress,\r
+ uint16_t mask)\r
+{\r
+ mask = (mask >> 8);\r
+ return (HWREG16(baseAddress + OFS_TDxHINT) & mask) << 8;\r
+}\r
+//*****************************************************************************\r
+//\r
+//! \brief Reset/Clear the timer clock divider, count direction, count\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//!\r
+//! Modified bits of \b TDxCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+\r
+void TIMER_D_clear(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_TDxCTL0) |= TDCLR;\r
+}\r
+//*****************************************************************************\r
+//\r
+//! \brief Clears High Resolution interrupt status\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//! \param mask is the mask for the interrupts to clear\r
+//! Mask value is the logical OR of any of the following:\r
+//! - \b TIMER_D_HIGH_RES_FREQUENCY_UNLOCK\r
+//! - \b TIMER_D_HIGH_RES_FREQUENCY_LOCK\r
+//! - \b TIMER_D_HIGH_RES_FAIL_HIGH\r
+//! - \b TIMER_D_HIGH_RES_FAIL_LOW\r
+//!\r
+//! Modified bits of \b TDxHINT register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+\r
+void TIMER_D_clearHighResInterruptStatus(uint16_t baseAddress,\r
+ uint16_t mask)\r
+{\r
+ mask = (mask >> 8);\r
+ HWREG16(baseAddress + OFS_TDxHINT) &= ~mask;\r
+}\r
+//*****************************************************************************\r
+//\r
+//! \brief Get synchronized capturecompare input\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//! \param captureCompareRegister selects the Capture register being used.\r
+//! Valid values are:\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_0\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_1\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_2\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_3\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_4\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_5\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_6\r
+//! \param synchronized is to select type of capture compare input.\r
+//! Valid values are:\r
+//! - \b TIMER_D_READ_SYNCHRONIZED_CAPTURECOMPAREINPUT\r
+//! - \b TIMER_D_READ_CAPTURE_COMPARE_INPUT\r
+//!\r
+//! \return One of the following:\r
+//! - \b TIMER_D_CAPTURECOMPARE_INPUT_HIGH\r
+//! - \b TIMER_D_CAPTURECOMPARE_INPUT_LOW\r
+//\r
+//*****************************************************************************\r
+\r
+uint8_t TIMER_D_getSynchronizedCaptureCompareInput\r
+ (uint16_t baseAddress,\r
+ uint16_t captureCompareRegister,\r
+ uint16_t synchronized\r
+ )\r
+{\r
+ assert((TIMER_D_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_1 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_2 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_3 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_4 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_5 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_6 == captureCompareRegister)\r
+ );\r
+\r
+ assert((TIMER_D_READ_CAPTURE_COMPARE_INPUT == synchronized) ||\r
+ (TIMER_D_READ_SYNCHRONIZED_CAPTURECOMPAREINPUT == synchronized)\r
+ );\r
+\r
+ if (HWREG16(baseAddress + captureCompareRegister) & synchronized)\r
+ return TIMER_D_CAPTURECOMPARE_INPUT_HIGH;\r
+ else\r
+ return TIMER_D_CAPTURECOMPARE_INPUT_LOW;\r
+}\r
+//*****************************************************************************\r
+//\r
+//! \brief Get output bit for output mode\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//! \param captureCompareRegister selects the Capture register being used.\r
+//! Valid values are:\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_0\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_1\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_2\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_3\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_4\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_5\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_6\r
+//!\r
+//! \return One of the following:\r
+//! - \b TIMER_D_OUTPUTMODE_OUTBITVALUE_HIGH\r
+//! - \b TIMER_D_OUTPUTMODE_OUTBITVALUE_LOW\r
+//\r
+//*****************************************************************************\r
+\r
+uint8_t TIMER_D_getOutputForOutputModeOutBitValue\r
+ (uint16_t baseAddress,\r
+ uint16_t captureCompareRegister\r
+ )\r
+{\r
+ assert((TIMER_D_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_1 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_2 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_3 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_4 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_5 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_6 == captureCompareRegister)\r
+ );\r
+\r
+ if (HWREG16(baseAddress + captureCompareRegister) & OUT)\r
+ return TIMER_D_OUTPUTMODE_OUTBITVALUE_HIGH;\r
+ else\r
+ return TIMER_D_OUTPUTMODE_OUTBITVALUE_LOW;\r
+}\r
+//*****************************************************************************\r
+//\r
+//! \brief Get current capturecompare count\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//! \param captureCompareRegister selects the Capture register being used.\r
+//! Valid values are:\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_0\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_1\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_2\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_3\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_4\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_5\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_6\r
+//!\r
+//! \return current count as uint16_t\r
+//\r
+//*****************************************************************************\r
+\r
+uint16_t TIMER_D_getCaptureCompareCount\r
+ (uint16_t baseAddress,\r
+ uint16_t captureCompareRegister\r
+ )\r
+{\r
+ assert((TIMER_D_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_1 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_2 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_3 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_4 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_5 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_6 == captureCompareRegister)\r
+ );\r
+\r
+ return HWREG16(baseAddress + captureCompareRegister + 2);\r
+}\r
+//*****************************************************************************\r
+//\r
+//! \brief Get current capture compare latch register count\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//! \param captureCompareRegister selects the Capture register being used.\r
+//! Valid values are:\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_0\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_1\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_2\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_3\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_4\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_5\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_6\r
+//!\r
+//! \return current count as uint16_t\r
+//\r
+//*****************************************************************************\r
+\r
+uint16_t TIMER_D_getCaptureCompareLatchCount\r
+ (uint16_t baseAddress,\r
+ uint16_t captureCompareRegister\r
+ )\r
+{\r
+ assert((TIMER_D_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_1 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_2 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_3 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_4 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_5 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_6 == captureCompareRegister)\r
+ );\r
+\r
+ return HWREG16(baseAddress + captureCompareRegister + 4);\r
+}\r
+//*****************************************************************************\r
+//\r
+//! \brief Get current capturecompare input signal\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//! \param captureCompareRegister selects the Capture register being used.\r
+//! Valid values are:\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_0\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_1\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_2\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_3\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_4\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_5\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_6\r
+//!\r
+//! \return One of the following:\r
+//! - \b TIMER_D_CAPTURECOMPARE_INPUT\r
+//! - \b 0x00\r
+//! \n indicating the current input signal\r
+//\r
+//*****************************************************************************\r
+\r
+uint8_t TIMER_D_getCaptureCompareInputSignal\r
+ (uint16_t baseAddress,\r
+ uint16_t captureCompareRegister\r
+ )\r
+{\r
+ assert((TIMER_D_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_1 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_2 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_3 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_4 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_5 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_6 == captureCompareRegister)\r
+ );\r
+\r
+ return (HWREG8(baseAddress + captureCompareRegister) & CCI);\r
+}\r
+//*****************************************************************************\r
+//\r
+//! \brief Set output bit for output mode\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//! \param captureCompareRegister selects the Capture register being used.\r
+//! Valid values are:\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_0\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_1\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_2\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_3\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_4\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_5\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_6\r
+//! \param outputModeOutBitValue the value to be set for out bit\r
+//! Valid values are:\r
+//! - \b TIMER_D_OUTPUTMODE_OUTBITVALUE_HIGH\r
+//! - \b TIMER_D_OUTPUTMODE_OUTBITVALUE_LOW\r
+//!\r
+//! Modified bits of \b TDxCCTLn register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+\r
+void TIMER_D_setOutputForOutputModeOutBitValue\r
+ (uint16_t baseAddress,\r
+ uint16_t captureCompareRegister,\r
+ uint8_t outputModeOutBitValue\r
+ )\r
+{\r
+ assert((TIMER_D_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_1 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_2 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_3 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_4 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_5 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_6 == captureCompareRegister)\r
+ );\r
+\r
+ assert((TIMER_D_OUTPUTMODE_OUTBITVALUE_HIGH == outputModeOutBitValue) ||\r
+ (TIMER_D_OUTPUTMODE_OUTBITVALUE_LOW == outputModeOutBitValue)\r
+ );\r
+\r
+ HWREG16(baseAddress + captureCompareRegister) &= ~OUT;\r
+ HWREG16(baseAddress + captureCompareRegister) |= outputModeOutBitValue;\r
+}\r
+//*****************************************************************************\r
+//\r
+//! \brief Generate a PWM with timer running in up mode\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//! \param param is the pointer to struct for PWM configuration.\r
+//!\r
+//! Modified bits of \b TDxCCTLn register, bits of \b TDxCCR0 register, bits of\r
+//! \b TDxCCTL0 register, bits of \b TDxCTL0 register and bits of \b TDxCTL1\r
+//! register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void TIMER_D_outputPWM(uint16_t baseAddress, TIMER_D_outputPWMParam *param)\r
+{\r
+ assert(param != 0);\r
+\r
+ assert((TIMER_D_CAPTURECOMPARE_REGISTER_0 == param->compareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_1 == param->compareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_2 == param->compareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_3 == param->compareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_4 == param->compareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_5 == param->compareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_6 == param->compareRegister)\r
+ );\r
+\r
+ assert(\r
+ (TIMER_D_CLOCKSOURCE_EXTERNAL_TDCLK == param->clockSource) ||\r
+ (TIMER_D_CLOCKSOURCE_ACLK == param->clockSource) ||\r
+ (TIMER_D_CLOCKSOURCE_SMCLK == param->clockSource) ||\r
+ (TIMER_D_CLOCKSOURCE_INVERTED_EXTERNAL_TDCLK == param->clockSource)\r
+ );\r
+\r
+ assert(\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_1 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_2 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_4 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_8 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_3 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_5 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_6 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_7 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_10 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_12 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_14 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_16 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_20 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_24 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_28 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_32 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_40 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_48 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_56 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_64 == param->clockSourceDivider)\r
+ );\r
+\r
+ assert(\r
+ (TIMER_D_CLOCKINGMODE_EXTERNAL_CLOCK == param->clockingMode) ||\r
+ (TIMER_D_CLOCKINGMODE_HIRES_LOCAL_CLOCK == param->clockingMode) ||\r
+ (TIMER_D_CLOCKINGMODE_AUXILIARY_CLK == param->clockingMode)\r
+ );\r
+\r
+ assert((TIMER_D_OUTPUTMODE_OUTBITVALUE == param->compareOutputMode) ||\r
+ (TIMER_D_OUTPUTMODE_SET == param->compareOutputMode) ||\r
+ (TIMER_D_OUTPUTMODE_TOGGLE_RESET == param->compareOutputMode) ||\r
+ (TIMER_D_OUTPUTMODE_SET_RESET == param->compareOutputMode) ||\r
+ (TIMER_D_OUTPUTMODE_TOGGLE == param->compareOutputMode) ||\r
+ (TIMER_D_OUTPUTMODE_RESET == param->compareOutputMode) ||\r
+ (TIMER_D_OUTPUTMODE_TOGGLE_SET == param->compareOutputMode) ||\r
+ (TIMER_D_OUTPUTMODE_RESET_SET == param->compareOutputMode)\r
+ );\r
+\r
+ HWREG16(baseAddress + OFS_TDxCTL1) &= ~(TDCLKM0 + TDCLKM1 + TDIDEX_7);\r
+\r
+ HWREG16(baseAddress + OFS_TDxCTL0) &=\r
+ ~(TIMER_D_CLOCKSOURCE_INVERTED_EXTERNAL_TDCLK +\r
+ TIMER_D_UPDOWN_MODE + TIMER_D_DO_CLEAR +\r
+ TIMER_D_TDIE_INTERRUPT_ENABLE +\r
+ ID__8\r
+ );\r
+\r
+ HWREG16(baseAddress + OFS_TDxCTL0) |= param->clockSource;\r
+ HWREG16(baseAddress + OFS_TDxCTL1) |= (param->clockingMode +\r
+ ((param->clockSourceDivider & 0x7) << 8));\r
+\r
+ HWREG16(baseAddress + OFS_TDxCTL0) |= (TIMER_D_UP_MODE +\r
+ TIMER_D_DO_CLEAR +\r
+ ((param->clockSourceDivider >> 3) << 6));\r
+\r
+ HWREG16(baseAddress + OFS_TDxCCR0) = param->timerPeriod;\r
+\r
+ HWREG16(baseAddress + OFS_TDxCCTL0) &=\r
+ ~(TIMER_D_CAPTURECOMPARE_INTERRUPT_ENABLE +\r
+ TIMER_D_OUTPUTMODE_RESET_SET\r
+ );\r
+ HWREG16(baseAddress + param->compareRegister) |= param->compareOutputMode;\r
+\r
+ HWREG16(baseAddress + param->compareRegister + 2) = param->dutyCycle;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief DEPRECATED - Generate a PWM with timer running in up mode\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//! \param clockSource selects Clock source.\r
+//! Valid values are:\r
+//! - \b TIMER_D_CLOCKSOURCE_EXTERNAL_TDCLK [Default]\r
+//! - \b TIMER_D_CLOCKSOURCE_ACLK\r
+//! - \b TIMER_D_CLOCKSOURCE_SMCLK\r
+//! - \b TIMER_D_CLOCKSOURCE_INVERTED_EXTERNAL_TDCLK\r
+//! \param clockSourceDivider is the divider for clock source.\r
+//! Valid values are:\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_1 [Default]\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_2\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_3\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_4\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_5\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_6\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_7\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_8\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_10\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_12\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_14\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_16\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_20\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_24\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_28\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_32\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_40\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_48\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_56\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_64\r
+//! \param clockingMode is the selected clock mode register values.\r
+//! Valid values are:\r
+//! - \b TIMER_D_CLOCKINGMODE_EXTERNAL_CLOCK [Default]\r
+//! - \b TIMER_D_CLOCKINGMODE_HIRES_LOCAL_CLOCK\r
+//! - \b TIMER_D_CLOCKINGMODE_AUXILIARY_CLK\r
+//! \param timerPeriod is the specified timer period\r
+//! \param compareRegister selects the compare register being used.\r
+//! Valid values are:\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_0\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_1\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_2\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_3\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_4\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_5\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_6\r
+//! \param compareOutputMode specifies the output mode.\r
+//! Valid values are:\r
+//! - \b TIMER_D_OUTPUTMODE_OUTBITVALUE [Default]\r
+//! - \b TIMER_D_OUTPUTMODE_SET\r
+//! - \b TIMER_D_OUTPUTMODE_TOGGLE_RESET\r
+//! - \b TIMER_D_OUTPUTMODE_SET_RESET\r
+//! - \b TIMER_D_OUTPUTMODE_TOGGLE\r
+//! - \b TIMER_D_OUTPUTMODE_RESET\r
+//! - \b TIMER_D_OUTPUTMODE_TOGGLE_SET\r
+//! - \b TIMER_D_OUTPUTMODE_RESET_SET\r
+//! \param dutyCycle specifies the dutycycle for the generated waveform\r
+//!\r
+//! Modified bits of \b TDxCCTLn register, bits of \b TDxCCR0 register, bits of\r
+//! \b TDxCCTL0 register, bits of \b TDxCTL0 register and bits of \b TDxCTL1\r
+//! register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+\r
+void TIMER_D_generatePWM( uint16_t baseAddress,\r
+ uint16_t clockSource,\r
+ uint16_t clockSourceDivider,\r
+ uint16_t clockingMode,\r
+ uint16_t timerPeriod,\r
+ uint16_t compareRegister,\r
+ uint16_t compareOutputMode,\r
+ uint16_t dutyCycle\r
+ )\r
+{\r
+ TIMER_D_outputPWMParam param = { 0 };\r
+\r
+ param.clockSource = clockSource;\r
+ param.clockSourceDivider = clockSourceDivider;\r
+ param.clockingMode = clockingMode;\r
+ param.timerPeriod = timerPeriod;\r
+ param.compareRegister = compareRegister;\r
+ param.compareOutputMode = compareOutputMode;\r
+ param.dutyCycle = dutyCycle;\r
+\r
+ TIMER_D_outputPWM(baseAddress, ¶m);\r
+}\r
+//*****************************************************************************\r
+//\r
+//! \brief Stops the timer\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//!\r
+//! Modified bits of \b TDxCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+\r
+void TIMER_D_stop( uint16_t baseAddress )\r
+{\r
+ HWREG16(baseAddress + OFS_TDxCTL0) &= ~MC_3;\r
+ HWREG16(baseAddress + OFS_TDxCTL0) |= MC_0;\r
+}\r
+//*****************************************************************************\r
+//\r
+//! \brief Sets the value of the capture-compare register\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//! \param compareRegister selects the Capture register being used.\r
+//! Valid values are:\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_0\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_1\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_2\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_3\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_4\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_5\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_6\r
+//! \param compareValue is the count to be compared with in compare mode\r
+//!\r
+//! Modified bits of \b TDxCCRn register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+\r
+void TIMER_D_setCompareValue( uint16_t baseAddress,\r
+ uint16_t compareRegister,\r
+ uint16_t compareValue\r
+ )\r
+{\r
+ assert((TIMER_D_CAPTURECOMPARE_REGISTER_0 == compareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_1 == compareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_2 == compareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_3 == compareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_4 == compareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_5 == compareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_6 == compareRegister)\r
+ );\r
+\r
+ HWREG16(baseAddress + compareRegister + 0x02) = compareValue;\r
+}\r
+//*****************************************************************************\r
+//\r
+//! \brief Clears the Timer TDIFG interrupt flag\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//!\r
+//! Modified bits are \b TDIFG of \b TDxCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+\r
+void TIMER_D_clearTimerInterruptFlag(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_TDxCTL0) &= ~TDIFG;\r
+}\r
+//*****************************************************************************\r
+//\r
+//! \brief Clears the capture-compare interrupt flag\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//! \param captureCompareRegister selects the Capture-compare register being\r
+//! used.\r
+//! Valid values are:\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_0\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_1\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_2\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_3\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_4\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_5\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_6\r
+//!\r
+//! Modified bits are \b CCIFG of \b TDxCCTLn register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+\r
+void TIMER_D_clearCaptureCompareInterruptFlag(uint16_t baseAddress,\r
+ uint16_t captureCompareRegister\r
+ )\r
+{\r
+ assert((TIMER_D_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_1 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_2 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_3 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_4 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_5 == captureCompareRegister) ||\r
+ (TIMER_D_CAPTURECOMPARE_REGISTER_6 == captureCompareRegister)\r
+ );\r
+\r
+ HWREG16(baseAddress + captureCompareRegister) &= ~CCIFG;\r
+}\r
+//*****************************************************************************\r
+//\r
+//! \brief Configures TIMER_D in free running mode\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//! \param desiredHighResFrequency selects the desired High Resolution\r
+//! frequency used.\r
+//! Valid values are:\r
+//! - \b TIMER_D_HIGHRES_64MHZ\r
+//! - \b TIMER_D_HIGHRES_128MHZ\r
+//! - \b TIMER_D_HIGHRES_200MHZ\r
+//! - \b TIMER_D_HIGHRES_256MHZ\r
+//!\r
+//! Modified bits of \b TDxHCTL1 register, bits of \b TDxHCTL0 register and\r
+//! bits of \b TDxCTL1 register.\r
+//!\r
+//! \return STATUS_SUCCESS or STATUS_FAIL\r
+//\r
+//*****************************************************************************\r
+\r
+uint8_t TIMER_D_initHighResGeneratorInFreeRunningMode\r
+ (uint16_t baseAddress,\r
+ uint8_t desiredHighResFrequency\r
+ )\r
+{\r
+ struct s_TLV_Timer_D_Cal_Data * pTD0CAL;\r
+ uint8_t TD0CAL_bytes;\r
+\r
+ assert((TIMER_D_HIGHRES_64MHZ == desiredHighResFrequency) ||\r
+ (TIMER_D_HIGHRES_128MHZ == desiredHighResFrequency) ||\r
+ (TIMER_D_HIGHRES_200MHZ == desiredHighResFrequency) ||\r
+ (TIMER_D_HIGHRES_256MHZ == desiredHighResFrequency)\r
+ );\r
+\r
+ // Read the TimerD TLV Data\r
+ TLV_getInfo(TLV_TAG_TIMER_D_CAL,\r
+ 0,\r
+ &TD0CAL_bytes,\r
+ (uint16_t**)&pTD0CAL\r
+ );\r
+\r
+ if (0x00 == TD0CAL_bytes)\r
+ // No TimerD free running cal data found\r
+ return STATUS_FAIL;\r
+\r
+ HWREG16(baseAddress + OFS_TDxHCTL1) = TDHCLKTRIM6;\r
+ HWREG16(baseAddress + OFS_TDxCTL1) = 0x00;\r
+ HWREG16(baseAddress + OFS_TDxHCTL0) = 0x00;\r
+\r
+ switch ( desiredHighResFrequency ) {\r
+ case TIMER_D_HIGHRES_64MHZ:\r
+ HWREG16(baseAddress + OFS_TDxHCTL1) = pTD0CAL->TDH0CTL1_64;\r
+ break;\r
+\r
+ case TIMER_D_HIGHRES_128MHZ:\r
+ HWREG16(baseAddress + OFS_TDxHCTL1) = pTD0CAL->TDH0CTL1_128;\r
+ break;\r
+\r
+ case TIMER_D_HIGHRES_200MHZ:\r
+ HWREG16(baseAddress + OFS_TDxHCTL1) = pTD0CAL->TDH0CTL1_200;\r
+ break;\r
+\r
+ case TIMER_D_HIGHRES_256MHZ:\r
+ HWREG16(baseAddress + OFS_TDxHCTL1) = pTD0CAL->TDH0CTL1_256;\r
+ break;\r
+ }\r
+\r
+ // Select Hi-res local clock\r
+ HWREG16(baseAddress + OFS_TDxCTL1) |= TDCLKM_1;\r
+\r
+ // CALEN=0 => free running mode; enable Hi-res mode\r
+ if (TIMER_D_HIGHRES_256MHZ == desiredHighResFrequency)\r
+ HWREG16(baseAddress + OFS_TDxHCTL0) |= TDHM_1;\r
+\r
+ HWREG16(baseAddress + OFS_TDxHCTL0) |= TDHEN;\r
+\r
+ return STATUS_SUCCESS;\r
+\r
+}\r
+//*****************************************************************************\r
+//\r
+//! \brief Configures TIMER_D in Regulated mode\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//! \param param is the pointer to struct for high resolution generator in\r
+//! regulated mode.\r
+//!\r
+//! Modified bits of \b TDxHCTL0 register, bits of \b TDxCTL0 register and bits\r
+//! of \b TDxCTL1 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void TIMER_D_initHighResGeneratorInRegulatedMode(uint16_t baseAddress,\r
+ TIMER_D_initHighResGeneratorInRegulatedModeParam *param)\r
+{\r
+ assert(param != 0);\r
+\r
+ assert(\r
+ (TIMER_D_CLOCKSOURCE_EXTERNAL_TDCLK == param->clockSource) ||\r
+ (TIMER_D_CLOCKSOURCE_ACLK == param->clockSource) ||\r
+ (TIMER_D_CLOCKSOURCE_SMCLK == param->clockSource) ||\r
+ (TIMER_D_CLOCKSOURCE_INVERTED_EXTERNAL_TDCLK == param->clockSource)\r
+ );\r
+\r
+ assert(\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_1 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_2 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_4 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_8 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_3 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_5 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_6 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_7 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_10 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_12 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_14 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_16 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_20 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_24 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_28 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_32 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_40 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_48 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_56 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_64 == param->clockSourceDivider)\r
+ );\r
+\r
+ assert(\r
+ (TIMER_D_CLOCKINGMODE_EXTERNAL_CLOCK == param->clockingMode) ||\r
+ (TIMER_D_CLOCKINGMODE_HIRES_LOCAL_CLOCK == param->clockingMode) ||\r
+ (TIMER_D_CLOCKINGMODE_AUXILIARY_CLK == param->clockingMode)\r
+ );\r
+\r
+ assert((TIMER_D_HIGHRES_CLK_MULTIPLY_FACTOR_8x == param->highResClockMultiplyFactor) ||\r
+ (TIMER_D_HIGHRES_CLK_MULTIPLY_FACTOR_16x == param->highResClockMultiplyFactor)\r
+ );\r
+\r
+ assert((TIMER_D_HIGHRES_CLK_DIVIDER_1 == param->highResClockDivider) ||\r
+ (TIMER_D_HIGHRES_CLK_DIVIDER_2 == param->highResClockDivider) ||\r
+ (TIMER_D_HIGHRES_CLK_DIVIDER_4 == param->highResClockDivider) ||\r
+ (TIMER_D_HIGHRES_CLK_DIVIDER_8 == param->highResClockDivider)\r
+ );\r
+\r
+ /**********how abt MCx and TDCLGRPx and CNTLx*/\r
+ HWREG16(baseAddress + OFS_TDxCTL0) &= ~(TDSSEL_3 + TDHD_3 + TDCLR + ID__8);\r
+ HWREG16(baseAddress + OFS_TDxCTL1) &= ~(TDCLKM0 + TDCLKM1 + TDIDEX_7);\r
+\r
+ HWREG16(baseAddress + OFS_TDxCTL0) |= (param->clockSource +\r
+ ((param->clockSourceDivider >> 3) << 6));\r
+ HWREG16(baseAddress + OFS_TDxCTL1) |= (param->clockingMode +\r
+ ((param->clockSourceDivider & 0x7) << 8));\r
+\r
+ // Select Hi-res local clock\r
+ // Calibration and Hi-res mode enable\r
+ HWREG16(baseAddress + OFS_TDxCTL1) |= TDCLKM_1;\r
+ // Select Hi-res local clock\r
+ HWREG16(baseAddress + OFS_TDxHCTL0) = TDHREGEN + TDHEN;\r
+ HWREG16(baseAddress + OFS_TDxHCTL0) |= param->highResClockMultiplyFactor +\r
+ param->highResClockDivider;\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! \brief DEPRECATED - Configures TIMER_D in Regulated mode\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//! \param clockSource selects Clock source.\r
+//! Valid values are:\r
+//! - \b TIMER_D_CLOCKSOURCE_EXTERNAL_TDCLK [Default]\r
+//! - \b TIMER_D_CLOCKSOURCE_ACLK\r
+//! - \b TIMER_D_CLOCKSOURCE_SMCLK\r
+//! - \b TIMER_D_CLOCKSOURCE_INVERTED_EXTERNAL_TDCLK\r
+//! \param clockSourceDivider is the divider for clock source.\r
+//! Valid values are:\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_1 [Default]\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_2\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_3\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_4\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_5\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_6\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_7\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_8\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_10\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_12\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_14\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_16\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_20\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_24\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_28\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_32\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_40\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_48\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_56\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_64\r
+//! \param clockingMode is the selected clock mode register values.\r
+//! Valid values are:\r
+//! - \b TIMER_D_CLOCKINGMODE_EXTERNAL_CLOCK [Default]\r
+//! - \b TIMER_D_CLOCKINGMODE_HIRES_LOCAL_CLOCK\r
+//! - \b TIMER_D_CLOCKINGMODE_AUXILIARY_CLK\r
+//! \param highResClockMultiplyFactor selects the high resolution multiply\r
+//! factor.\r
+//! Valid values are:\r
+//! - \b TIMER_D_HIGHRES_CLK_MULTIPLY_FACTOR_8x\r
+//! - \b TIMER_D_HIGHRES_CLK_MULTIPLY_FACTOR_16x\r
+//! \param highResClockDivider selects the high resolution divider.\r
+//! Valid values are:\r
+//! - \b TIMER_D_HIGHRES_CLK_DIVIDER_1\r
+//! - \b TIMER_D_HIGHRES_CLK_DIVIDER_2\r
+//! - \b TIMER_D_HIGHRES_CLK_DIVIDER_4\r
+//! - \b TIMER_D_HIGHRES_CLK_DIVIDER_8\r
+//!\r
+//! Modified bits of \b TDxHCTL0 register, bits of \b TDxCTL0 register and bits\r
+//! of \b TDxCTL1 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+\r
+void TIMER_D_configureHighResGeneratorInRegulatedMode(uint16_t baseAddress,\r
+ uint16_t clockSource,\r
+ uint16_t clockSourceDivider,\r
+ uint16_t clockingMode,\r
+ uint8_t highResClockMultiplyFactor,\r
+ uint8_t highResClockDivider\r
+ )\r
+{\r
+ TIMER_D_initHighResGeneratorInRegulatedModeParam param = { 0 };\r
+\r
+ param.clockSource = clockSource;\r
+ param.clockSourceDivider = clockSourceDivider;\r
+ param.clockingMode = clockingMode;\r
+ param.highResClockMultiplyFactor = highResClockMultiplyFactor;\r
+ param.highResClockDivider = highResClockDivider;\r
+\r
+ TIMER_D_initHighResGeneratorInRegulatedMode(baseAddress, ¶m);\r
+\r
+}\r
+//*****************************************************************************\r
+//\r
+//! \brief Combine TDCCR to get PWM\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//! \param param is the pointer to struct for PWM generation using two CCRs.\r
+//!\r
+//! Modified bits of \b TDxCCTLn register, bits of \b TDxCCR0 register, bits of\r
+//! \b TDxCCTL0 register, bits of \b TDxCTL0 register and bits of \b TDxCTL1\r
+//! register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+void TIMER_D_combineTDCCRToOutputPWM(uint16_t baseAddress,\r
+ TIMER_D_combineTDCCRToOutputPWMParam *param)\r
+{\r
+ assert(param != 0);\r
+\r
+ assert(\r
+ (TIMER_D_COMBINE_CCR1_CCR2 == param->combineCCRRegistersCombination) ||\r
+ (TIMER_D_COMBINE_CCR3_CCR4 == param->combineCCRRegistersCombination) ||\r
+ (TIMER_D_COMBINE_CCR5_CCR6 == param->combineCCRRegistersCombination)\r
+ );\r
+\r
+ assert(\r
+ (TIMER_D_CLOCKSOURCE_EXTERNAL_TDCLK == param->clockSource) ||\r
+ (TIMER_D_CLOCKSOURCE_ACLK == param->clockSource) ||\r
+ (TIMER_D_CLOCKSOURCE_SMCLK == param->clockSource) ||\r
+ (TIMER_D_CLOCKSOURCE_INVERTED_EXTERNAL_TDCLK == param->clockSource)\r
+ );\r
+\r
+ assert(\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_1 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_2 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_4 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_8 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_3 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_5 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_6 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_7 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_10 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_12 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_14 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_16 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_20 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_24 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_28 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_32 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_40 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_48 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_56 == param->clockSourceDivider) ||\r
+ (TIMER_D_CLOCKSOURCE_DIVIDER_64 == param->clockSourceDivider)\r
+ );\r
+\r
+ assert(\r
+ (TIMER_D_CLOCKINGMODE_EXTERNAL_CLOCK == param->clockingMode) ||\r
+ (TIMER_D_CLOCKINGMODE_HIRES_LOCAL_CLOCK == param->clockingMode) ||\r
+ (TIMER_D_CLOCKINGMODE_AUXILIARY_CLK == param->clockingMode)\r
+ );\r
+\r
+ assert((TIMER_D_OUTPUTMODE_OUTBITVALUE == param->compareOutputMode) ||\r
+ (TIMER_D_OUTPUTMODE_SET == param->compareOutputMode) ||\r
+ (TIMER_D_OUTPUTMODE_TOGGLE_RESET == param->compareOutputMode) ||\r
+ (TIMER_D_OUTPUTMODE_SET_RESET == param->compareOutputMode) ||\r
+ (TIMER_D_OUTPUTMODE_TOGGLE == param->compareOutputMode) ||\r
+ (TIMER_D_OUTPUTMODE_RESET == param->compareOutputMode) ||\r
+ (TIMER_D_OUTPUTMODE_TOGGLE_SET == param->compareOutputMode) ||\r
+ (TIMER_D_OUTPUTMODE_RESET_SET == param->compareOutputMode)\r
+ );\r
+\r
+ HWREG16(baseAddress + OFS_TDxCCTL2) &= ~OUTMOD_7;\r
+ HWREG16(baseAddress + OFS_TDxCCTL2) |= param->compareOutputMode;\r
+\r
+ HWREG16(baseAddress + OFS_TDxCCR0) = param->timerPeriod;\r
+\r
+ HWREG16(baseAddress + OFS_TDxCCR1 + (0x05 *\r
+ (param->combineCCRRegistersCombination - TIMER_D_COMBINE_CCR1_CCR2))) = param->dutyCycle1;\r
+ HWREG16(baseAddress + OFS_TDxCCR2 + (0x05 *\r
+ (param->combineCCRRegistersCombination - TIMER_D_COMBINE_CCR1_CCR2))) = param->dutyCycle2;\r
+\r
+ HWREG16(baseAddress + OFS_TDxCTL0) &= ~ID__8;\r
+ HWREG16(baseAddress + OFS_TDxCTL1) &= ~(TDCLKM0 + TDCLKM1 + TDIDEX_7);\r
+\r
+ HWREG16(baseAddress + OFS_TDxCTL0) |= (param->clockSource +\r
+ ((param->clockSourceDivider >> 3) << 6));\r
+ HWREG16(baseAddress + OFS_TDxCTL1) |= (param->clockingMode +\r
+ ((param->clockSourceDivider & 0x7) << 8));\r
+ HWREG16(baseAddress + OFS_TDxCTL1) |=\r
+ (TD2CMB << (param->combineCCRRegistersCombination - TIMER_D_COMBINE_CCR1_CCR2));\r
+} //*****************************************************************************\r
+//\r
+//! \brief DEPRECATED - Combine TDCCR to get PWM\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//! \param clockSource selects Clock source.\r
+//! Valid values are:\r
+//! - \b TIMER_D_CLOCKSOURCE_EXTERNAL_TDCLK [Default]\r
+//! - \b TIMER_D_CLOCKSOURCE_ACLK\r
+//! - \b TIMER_D_CLOCKSOURCE_SMCLK\r
+//! - \b TIMER_D_CLOCKSOURCE_INVERTED_EXTERNAL_TDCLK\r
+//! \param clockSourceDivider is the divider for clock source.\r
+//! Valid values are:\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_1 [Default]\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_2\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_3\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_4\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_5\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_6\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_7\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_8\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_10\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_12\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_14\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_16\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_20\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_24\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_28\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_32\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_40\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_48\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_56\r
+//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_64\r
+//! \param clockingMode is the selected clock mode register values.\r
+//! Valid values are:\r
+//! - \b TIMER_D_CLOCKINGMODE_EXTERNAL_CLOCK [Default]\r
+//! - \b TIMER_D_CLOCKINGMODE_HIRES_LOCAL_CLOCK\r
+//! - \b TIMER_D_CLOCKINGMODE_AUXILIARY_CLK\r
+//! \param timerPeriod is the specified timer period\r
+//! \param combineCCRRegistersCombination selects desired CCR registers to\r
+//! combine\r
+//! Valid values are:\r
+//! - \b TIMER_D_COMBINE_CCR1_CCR2\r
+//! - \b TIMER_D_COMBINE_CCR3_CCR4 - (available on TIMER_D5, TIMER_D7)\r
+//! - \b TIMER_D_COMBINE_CCR5_CCR6 - (available only on TIMER_D7)\r
+//! \param compareOutputMode specifies the output mode.\r
+//! Valid values are:\r
+//! - \b TIMER_D_OUTPUTMODE_OUTBITVALUE [Default]\r
+//! - \b TIMER_D_OUTPUTMODE_SET\r
+//! - \b TIMER_D_OUTPUTMODE_TOGGLE_RESET\r
+//! - \b TIMER_D_OUTPUTMODE_SET_RESET\r
+//! - \b TIMER_D_OUTPUTMODE_TOGGLE\r
+//! - \b TIMER_D_OUTPUTMODE_RESET\r
+//! - \b TIMER_D_OUTPUTMODE_TOGGLE_SET\r
+//! - \b TIMER_D_OUTPUTMODE_RESET_SET\r
+//! \param dutyCycle1 specifies the dutycycle for the generated waveform\r
+//! \param dutyCycle2 specifies the dutycycle for the generated waveform\r
+//!\r
+//! Modified bits of \b TDxCCTLn register, bits of \b TDxCCR0 register, bits of\r
+//! \b TDxCCTL0 register, bits of \b TDxCTL0 register and bits of \b TDxCTL1\r
+//! register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+\r
+void TIMER_D_combineTDCCRToGeneratePWM( uint16_t baseAddress,\r
+ uint16_t clockSource,\r
+ uint16_t clockSourceDivider,\r
+ uint16_t clockingMode,\r
+ uint16_t timerPeriod,\r
+ uint16_t combineCCRRegistersCombination,\r
+ uint16_t compareOutputMode,\r
+ uint16_t dutyCycle1,\r
+ uint16_t dutyCycle2\r
+ )\r
+{\r
+ TIMER_D_combineTDCCRToOutputPWMParam param = { 0 };\r
+\r
+ param.clockSource = clockSource;\r
+ param.clockSourceDivider = clockSourceDivider;\r
+ param.clockingMode = clockingMode;\r
+ param.timerPeriod = timerPeriod;\r
+ param.combineCCRRegistersCombination = combineCCRRegistersCombination;\r
+ param.compareOutputMode = compareOutputMode;\r
+ param.dutyCycle1 = dutyCycle1;\r
+ param.dutyCycle2 = dutyCycle2;\r
+\r
+ TIMER_D_combineTDCCRToOutputPWM(baseAddress, ¶m);\r
+}\r
+//*****************************************************************************\r
+//\r
+//! \brief Selects TIMER_D Latching Group\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//! \param groupLatch selects the group latch\r
+//! Valid values are:\r
+//! - \b TIMER_D_GROUP_NONE [Default]\r
+//! - \b TIMER_D_GROUP_CL12_CL23_CL56\r
+//! - \b TIMER_D_GROUP_CL123_CL456\r
+//! - \b TIMER_D_GROUP_ALL\r
+//!\r
+//! Modified bits are \b TDCLGRP of \b TDxCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+\r
+void TIMER_D_selectLatchingGroup(uint16_t baseAddress,\r
+ uint16_t groupLatch)\r
+{\r
+ assert((TIMER_D_GROUP_NONE == groupLatch) ||\r
+ (TIMER_D_GROUP_CL12_CL23_CL56 == groupLatch) ||\r
+ (TIMER_D_GROUP_CL123_CL456 == groupLatch) ||\r
+ (TIMER_D_GROUP_ALL == groupLatch)\r
+ );\r
+\r
+ HWREG16(baseAddress + OFS_TDxCTL0) &= ~TDCLGRP_3;\r
+ HWREG16(baseAddress + OFS_TDxCTL0) |= groupLatch;\r
+}\r
+//*****************************************************************************\r
+//\r
+//! \brief Selects TIMER_D counter length\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//! \param counterLength selects the value of counter length.\r
+//! Valid values are:\r
+//! - \b TIMER_D_COUNTER_16BIT [Default]\r
+//! - \b TIMER_D_COUNTER_12BIT\r
+//! - \b TIMER_D_COUNTER_10BIT\r
+//! - \b TIMER_D_COUNTER_8BIT\r
+//!\r
+//! Modified bits are \b CNTL of \b TDxCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+\r
+void TIMER_D_selectCounterLength(uint16_t baseAddress,\r
+ uint16_t counterLength\r
+ )\r
+{\r
+ assert((TIMER_D_COUNTER_8BIT == counterLength) ||\r
+ (TIMER_D_COUNTER_10BIT == counterLength) ||\r
+ (TIMER_D_COUNTER_12BIT == counterLength) ||\r
+ (TIMER_D_COUNTER_16BIT == counterLength)\r
+ );\r
+\r
+ HWREG16(baseAddress + OFS_TDxCTL0) &= ~CNTL_3;\r
+ HWREG16(baseAddress + OFS_TDxCTL0) |= counterLength;\r
+}\r
+//*****************************************************************************\r
+//\r
+//! \brief Selects Compare Latch Load Event\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//! \param compareRegister selects the compare register being used.\r
+//! Valid values are:\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_0\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_1\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_2\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_3\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_4\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_5\r
+//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_6\r
+//! \param compareLatchLoadEvent selects the latch load event\r
+//! Valid values are:\r
+//! - \b TIMER_D_LATCH_ON_WRITE_TO_TDxCCRn_COMPARE_REGISTER [Default]\r
+//! - \b TIMER_D_LATCH_WHEN_COUNTER_COUNTS_TO_0_IN_UP_OR_CONT_MODE\r
+//! - \b TIMER_D_LATCH_WHEN_COUNTER_COUNTS_TO_0_IN_UPDOWN_MODE\r
+//! - \b\r
+//! TIMER_D_LATCH_WHEN_COUNTER_COUNTS_TO_CURRENT_COMPARE_LATCH_VALUE\r
+//!\r
+//! Modified bits are \b CLLD of \b TDxCCTLn register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+\r
+void TIMER_D_initCompareLatchLoadEvent(uint16_t baseAddress,\r
+ uint16_t compareRegister,\r
+ uint16_t compareLatchLoadEvent\r
+ )\r
+{\r
+ assert((TIMER_D_LATCH_ON_WRITE_TO_TDxCCRn_COMPARE_REGISTER == compareLatchLoadEvent) ||\r
+ (TIMER_D_LATCH_WHEN_COUNTER_COUNTS_TO_0_IN_UP_OR_CONT_MODE == compareLatchLoadEvent) ||\r
+ (TIMER_D_LATCH_WHEN_COUNTER_COUNTS_TO_0_IN_UPDOWN_MODE == compareLatchLoadEvent) ||\r
+ (TIMER_D_LATCH_WHEN_COUNTER_COUNTS_TO_CURRENT_COMPARE_LATCH_VALUE\r
+ == compareLatchLoadEvent)\r
+ );\r
+\r
+ HWREG16(baseAddress + compareRegister) &= ~CLLD_3;\r
+ HWREG16(baseAddress + compareRegister) |= compareLatchLoadEvent;\r
+}\r
+//*****************************************************************************\r
+//\r
+//! \brief Disable High Resolution fast wakeup\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//!\r
+//! Modified bits are \b TDHFW of \b TDxHCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+\r
+void TIMER_D_disableHighResFastWakeup(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_TDxHCTL0) &= ~TDHFW;\r
+}\r
+//*****************************************************************************\r
+//\r
+//! \brief Enable High Resolution fast wakeup\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//!\r
+//! Modified bits are \b TDHFW of \b TDxHCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+\r
+void TIMER_D_enableHighResFastWakeup(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_TDxHCTL0) |= TDHFW;\r
+}\r
+//*****************************************************************************\r
+//\r
+//! \brief Disable High Resolution Clock Enhanced Accuracy\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//!\r
+//! Modified bits are \b TDHEAEN of \b TDxHCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+\r
+void TIMER_D_disableHighResClockEnhancedAccuracy(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_TDxHCTL0) &= ~TDHEAEN;\r
+}\r
+//*****************************************************************************\r
+//\r
+//! \brief Enable High Resolution Clock Enhanced Accuracy\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//!\r
+//! Modified bits are \b TDHEAEN of \b TDxHCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+\r
+void TIMER_D_enableHighResClockEnhancedAccuracy(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_TDxHCTL0) |= TDHEAEN;\r
+}\r
+//*****************************************************************************\r
+//\r
+//! \brief Disable High Resolution Clock Enhanced Accuracy\r
+//!\r
+//! High-resolution generator is on if the TIMER_D counter\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//!\r
+//! Modified bits are \b TDHRON of \b TDxHCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+\r
+void TIMER_D_DisableHighResGeneratorForceON(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_TDxHCTL0) &= ~TDHRON;\r
+}\r
+//*****************************************************************************\r
+//\r
+//! \brief Enable High Resolution Clock Enhanced Accuracy\r
+//!\r
+//! High-resolution generator is on in all TIMER_D MCx modes. The PMM remains\r
+//! in high-current mode.\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//!\r
+//! Modified bits are \b TDHRON of \b TDxHCTL0 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+\r
+void TIMER_D_EnableHighResGeneratorForceON(uint16_t baseAddress)\r
+{\r
+ HWREG16(baseAddress + OFS_TDxHCTL0) |= TDHRON;\r
+}\r
+//*****************************************************************************\r
+//\r
+//! \brief Select High Resolution Coarse Clock Range\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//! \param highResCoarseClockRange selects the High Resolution Coarse Clock\r
+//! Range\r
+//! Valid values are:\r
+//! - \b TIMER_D_HIGHRES_BELOW_15MHz [Default]\r
+//! - \b TIMER_D_HIGHRES_ABOVE_15MHz\r
+//!\r
+//! Modified bits are \b TDHCLKCR of \b TDxHCTL1 register.\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+\r
+void TIMER_D_selectHighResCoarseClockRange(uint16_t baseAddress,\r
+ uint16_t highResCoarseClockRange\r
+ )\r
+{\r
+ assert((TIMER_D_HIGHRES_BELOW_15MHz == highResCoarseClockRange) ||\r
+ (TIMER_D_HIGHRES_ABOVE_15MHz == highResCoarseClockRange)\r
+ );\r
+ HWREG16(baseAddress + OFS_TDxHCTL1) &= ~TDHCLKCR;\r
+ HWREG16(baseAddress + OFS_TDxHCTL1) |= highResCoarseClockRange;\r
+}\r
+//*****************************************************************************\r
+//\r
+//! \brief Select High Resolution Clock Range Selection\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//! \param highResClockRange selects the High Resolution Clock Range. Refer to\r
+//! datasheet for frequency details\r
+//! Valid values are:\r
+//! - \b TIMER_D_CLOCK_RANGE0 [Default]\r
+//! - \b TIMER_D_CLOCK_RANGE1\r
+//! - \b TIMER_D_CLOCK_RANGE2\r
+//!\r
+//! \return None\r
+//\r
+//*****************************************************************************\r
+\r
+void TIMER_D_selectHighResClockRange(uint16_t baseAddress,\r
+ uint16_t highResClockRange\r
+ )\r
+{\r
+ assert((TIMER_D_CLOCK_RANGE0 == highResClockRange) ||\r
+ (TIMER_D_CLOCK_RANGE1 == highResClockRange) ||\r
+ (TIMER_D_CLOCK_RANGE2 == highResClockRange)\r
+ );\r
+ HWREG16(baseAddress + OFS_TDxHCTL1) &= ~TDHCLKCR;\r
+ HWREG16(baseAddress + OFS_TDxHCTL1) |= highResClockRange;\r
+}\r
+//*****************************************************************************\r
+//\r
+//! \brief Reads the current timer count value\r
+//!\r
+//! Reads the current count value of the timer. There is a majority vote system\r
+//! in place to confirm an accurate value is returned. The TIMER_D_THRESHOLD\r
+//! #define in the corresponding header file can be modified so that the votes\r
+//! must be closer together for a consensus to occur.\r
+//!\r
+//! \param baseAddress is the base address of the TIMER_D module.\r
+//!\r
+//! \return Majority vote of timer count value\r
+//\r
+//*****************************************************************************\r
+\r
+uint16_t TIMER_D_getCounterValue(uint16_t baseAddress)\r
+{\r
+ uint16_t voteOne, voteTwo, res;\r
+\r
+ voteTwo = HWREG16(baseAddress + OFS_TDxR);\r
+\r
+ do {\r
+ voteOne = voteTwo;\r
+ voteTwo = HWREG16(baseAddress + OFS_TDxR);\r
+\r
+ if (voteTwo > voteOne)\r
+ res = voteTwo - voteOne;\r
+ else if (voteOne > voteTwo)\r
+ res = voteOne - voteTwo;\r
+ else\r
+ res = 0;\r
+\r
+ } while ( res > TIMER_D_THRESHOLD);\r
+\r
+ return voteTwo;\r
+}\r
+\r
+#endif\r
+//*****************************************************************************\r
+//\r
+//! Close the doxygen group for timer_d_api\r
+//! @}\r
+//\r
+//*****************************************************************************\r