From: Max Groening Date: Wed, 25 Mar 2015 10:00:13 +0000 (+0100) Subject: MSP-BSL v3.0 X-Git-Url: https://git.ti.com/gitweb?p=msp430-bsl%2Fmsp430-bsl.git;a=commitdiff_plain;h=9dd3b69c062e9a94d6253c1e4158ebdd61fe3b3d MSP-BSL v3.0 * SPI support added. Supports now UART, I2C and SPI for MSP430/MSP432 BSLs. * USB stack updated. --- diff --git a/BSL_Comm.c b/BSL_Comm.c deleted file mode 100644 index f68d2c5..0000000 --- a/BSL_Comm.c +++ /dev/null @@ -1,106 +0,0 @@ -/* - * BSL_Comm.c - * - * The I2C state machine. - * - * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include "BSL_Comm.h" -#include "descriptors.h" -#include "USB_API\USB_Common\types.h" // Basic Type declarations -#include "USB_API\USB_CDC_API\UsbCdc.h" // USB-specific functions - -// Description: -// Analyzes incoming usbdata -// return: I2C write trigger -unsigned int length = 0; -unsigned char state = SWAIT; - -unsigned char CoreCommand[256]; -unsigned char i = 0; - -extern volatile BYTE bDataReceiveCompleted_event[]; // data receive completed event - -unsigned char UART_FSM(BYTE* dataBuffer) -{ - unsigned int retvalue = 0; - - switch(state) - { - case(SWAIT): // wait for UART_HEADER to start the data sequence - USBCDC_receiveData(dataBuffer, UART_HEADER_LENGTH, CDC0_INTFNUM); - if(dataBuffer[0] == UART_HEADER) - { - length = 0; - state = SSTART; - } - else if (dataBuffer[0] == UART_CMD_HEADER) - { - state = SCMD; - } - - retvalue = 0; - break; - case(SSTART): // read in length bytes - bDataReceiveCompleted_event[0] = FALSE; - USBCDC_receiveData(dataBuffer + UART_HEADER_LENGTH, UART_LENGTH_LENGTH, CDC0_INTFNUM); - while (bDataReceiveCompleted_event[0] == FALSE){}; // wait until data received - length = ((unsigned char) dataBuffer[1 + UART_HEADER_LENGTH] << 8) | dataBuffer[0 + UART_HEADER_LENGTH]; - state = SDATA; - retvalue = 0; - break; - case(SDATA): // read in all data (length bytes) plus CRC - bDataReceiveCompleted_event[0] = FALSE; - USBCDC_receiveData(dataBuffer + UART_HEADER_LENGTH + UART_LENGTH_LENGTH, length + UART_CRC_LENGTH, CDC0_INTFNUM); - while (bDataReceiveCompleted_event[0] == FALSE){}; - - USBCDC_rejectData(CDC0_INTFNUM); // discard leftover bytes - - state = SWAIT; - retvalue = UART_HEADER_LENGTH + UART_LENGTH_LENGTH + length + UART_CRC_LENGTH; - break; - - case SCMD: - USBCDC_receiveData(dataBuffer, UART_CMD_LENGTH, CDC0_INTFNUM); - retvalue = dataBuffer[0]; - state = SWAIT; - break; - - default: - state = SWAIT; - retvalue = 0; - break; - } - return retvalue; -} diff --git a/BSL_Comm.h b/BSL_Comm.h deleted file mode 100644 index eac56b5..0000000 --- a/BSL_Comm.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * BSL_Comm.h - * - * The I2C state machine. - * - * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef BSL_COMM_H_ -#define BSL_COMM_H_ -#include "USB_API/USB_Common/types.h" // Basic Type declarations - -#define UART_HEADER 0x80 -#define UART_CMD_HEADER 0xA0 -#define UART_HEADER_LENGTH 1 // length in byte -#define UART_LENGTH_LENGTH 2 // length in byte -#define UART_CRC_LENGTH 2 // length in byte -#define UART_CMD_LENGTH 1 // length in byte - -// define STATES -#define SWAIT 0x00 -#define SSTART 0x01 -#define SLENGTH 0x02 -#define SDATA 0x03 -#define SSEND 0x04 -#define SCMD 0x05 - - - -unsigned char UART_FSM(BYTE *dataBuffer); - -#endif /*BSL_COMM_H_*/ diff --git a/F5xx_F6xx_Core_Lib/HAL_FLASH.c b/F5xx_F6xx_Core_Lib/HAL_FLASH.c deleted file mode 100644 index bcf3d7f..0000000 --- a/F5xx_F6xx_Core_Lib/HAL_FLASH.c +++ /dev/null @@ -1,127 +0,0 @@ -/******************************************************************************* - * - * HAL_FLASH.c - * Flash Library for flash memory controller of MSP430F5xx/6xx family - * - * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Created: Version 1.0 11/24/2009 - * Updated: Version 2.0 01/18/2011 - * - ******************************************************************************/ - -#include "msp430.h" -#include "HAL_FLASH.h" - -void Flash_SegmentErase(uint16_t *Flash_ptr) -{ - FCTL3 = FWKEY; // Clear Lock bit - FCTL1 = FWKEY + ERASE; // Set Erase bit - *Flash_ptr = 0; // Dummy write to erase Flash seg - while (FCTL3 & BUSY); // test busy - FCTL1 = FWKEY; // Clear WRT bit - FCTL3 = FWKEY + LOCK; // Set LOCK bit -} - -uint8_t Flash_EraseCheck(uint16_t *Flash_ptr, uint16_t len) -{ - uint16_t i; - - for (i = 0; i < len; i++) { // was erasing successfull? - if (*(Flash_ptr + i) != 0xFF) { - return FLASH_STATUS_ERROR; - } - } - - return FLASH_STATUS_OK; -} - -void FlashWrite_8(uint8_t *Data_ptr, uint8_t *Flash_ptr, uint16_t count) -{ - FCTL3 = FWKEY; // Clear Lock bit - FCTL1 = FWKEY+WRT; // Enable byte/word write mode - - while (count > 0) { - while (FCTL3 & BUSY); // test busy - *Flash_ptr++ = *Data_ptr++; // Write to Flash - count--; - } - - FCTL1 = FWKEY; // Clear write bit - FCTL3 = FWKEY + LOCK; // Set LOCK bit -} - -void FlashWrite_16(uint16_t *Data_ptr, uint16_t *Flash_ptr, uint16_t count) -{ - FCTL3 = FWKEY; // Clear Lock bit - FCTL1 = FWKEY+WRT; // Enable byte/word write mode - - while (count > 0) { - while (FCTL3 & BUSY); // test busy - *Flash_ptr++ = *Data_ptr++; // Write to Flash - count--; - } - - FCTL1 = FWKEY; // Clear Erase bit - FCTL3 = FWKEY + LOCK; // Set LOCK bit -} - -void FlashWrite_32(uint32_t *Data_ptr, uint32_t *Flash_ptr, uint16_t count) -{ - FCTL3 = FWKEY; // Clear Lock bit - FCTL1 = FWKEY + BLKWRT; // Enable long-word write - - while (count > 0) { - while (FCTL3 & BUSY); // test busy - *Flash_ptr++ = *Data_ptr++; // Write to Flash - count--; - } - - FCTL1 = FWKEY; // Clear Erase bit - FCTL3 = FWKEY + LOCK; // Set LOCK bit -} - -void FlashMemoryFill_32(uint32_t value, uint32_t *Flash_ptr, uint16_t count) -{ - FCTL3 = FWKEY; // Clear Lock bit - FCTL1 = FWKEY + BLKWRT; // Enable long-word write - - while (count > 0) { - while (FCTL3 & BUSY); // test busy - *Flash_ptr++ = value; // Write to Flash - count--; - } - - FCTL1 = FWKEY; // Clear Erase bit - FCTL3 = FWKEY + LOCK; // Set LOCK bit -} diff --git a/F5xx_F6xx_Core_Lib/HAL_FLASH.h b/F5xx_F6xx_Core_Lib/HAL_FLASH.h deleted file mode 100644 index 32a1d50..0000000 --- a/F5xx_F6xx_Core_Lib/HAL_FLASH.h +++ /dev/null @@ -1,106 +0,0 @@ -/******************************************************************************* - * - * HAL_FLASH.h - * Flash Library for flash memory controller of MSP430F5xx/6xx family - * - * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Created: Version 1.0 11/24/2009 - * Updated: Version 2.0 01/18/2011 - * - ******************************************************************************/ - -#ifndef HAL_FLASH_H -#define HAL_FLASH_H - -#include - -//****************************************************************************** -// Defines -//****************************************************************************** - -#define FLASH_STATUS_OK 0 -#define FLASH_STATUS_ERROR 1 - -/******************************************************************************* - * \brief Erase a single segment of the flash memory - * - * \param *Flash_ptr Pointer into the flash segment to erase - ******************************************************************************/ -extern void Flash_SegmentErase(uint16_t *Flash_ptr); - -/******************************************************************************* - * \brief Erase Check of the flash memory - * - * \param *Flash_ptr Pointer into the flash segment to erase - * \param len give the len in word - ******************************************************************************/ -extern uint8_t Flash_EraseCheck(uint16_t *Flash_ptr, uint16_t len); - -/******************************************************************************* - * \brief Write data into the flash memory (Byte format) - * - * \param *Data_ptr Pointer to the Data to write - * \param *Flash_ptr Pointer into the flash to write data to - * \param count number of data to write - ******************************************************************************/ -extern void FlashWrite_8(uint8_t *Data_ptr, uint8_t *Flash_ptr, uint16_t count); - -/******************************************************************************* - * \brief Write data into the flash memory (Word format) - * - * \param *Data_ptr Pointer to the Data to write - * \param *Flash_ptr Pointer into the flash to write data to - * \param count number of data to write - ******************************************************************************/ -extern void FlashWrite_16(uint16_t *Data_ptr, uint16_t *Flash_ptr, uint16_t count); - -/******************************************************************************* - * \brief Write data into the flash memory (Long format) - * - * \param *Data_ptr Pointer to the Data to write - * \param *Flash_ptr Pointer into the flash to write data to - * \param count number of data to write - ******************************************************************************/ -extern void FlashWrite_32(uint32_t *Data_ptr, uint32_t *Flash_ptr, uint16_t count); - -/******************************************************************************* - * \brief Fill data into the flash memory (Long format) - * - * \param value Pointer to the Data to write - * \param *Flash_ptr pointer into the flash to write data to - * \param count number of data to write (= byte * 4) - ******************************************************************************/ -extern void FlashMemoryFill_32(uint32_t value, uint32_t *Flash_ptr, uint16_t count); - -#endif /* HAL_FLASH_H */ diff --git a/F5xx_F6xx_Core_Lib/HAL_MACROS.h b/F5xx_F6xx_Core_Lib/HAL_MACROS.h deleted file mode 100644 index 398074f..0000000 --- a/F5xx_F6xx_Core_Lib/HAL_MACROS.h +++ /dev/null @@ -1,51 +0,0 @@ -/* **************************************************************************** - * - * HAL_MACROS.h - * Flash Library for flash memory controller of MSP430F5xx/6xx family - * - * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Created: Version 1.0 11/24/2009 - * Updated: Version 2.0 12/15/2010 - * -******************************************************************************/ - -#ifndef HAL_MACROS_H -#define HAL_MACROS_H - -/* - * This macro is for use by other macros to form a fully valid C statement. - */ -#define st(x) do { x } while (__LINE__ == -1) - -#endif /* HAL_MACROS_H */ diff --git a/F5xx_F6xx_Core_Lib/HAL_PMAP.c b/F5xx_F6xx_Core_Lib/HAL_PMAP.c deleted file mode 100644 index a8b0e0d..0000000 --- a/F5xx_F6xx_Core_Lib/HAL_PMAP.c +++ /dev/null @@ -1,80 +0,0 @@ -/******************************************************************************* - * - * HAL_PMAP.c - * Port Mapper Library for PMAP controller of MSP430F5xx/6xx family - * - * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Created: Version 1.0 11/24/2009 - * Updated: Version 2.0 12/15/2010 - * - ******************************************************************************/ - -#include "msp430.h" -#include "HAL_PMAP.h" - -// Check and define PMAP function only if the device has port mapping capability -// Note: This macro is defined in the device-specific header file if this -// feature is available on a given MSP430. -#ifdef __MSP430_HAS_PORT_MAPPING__ - -void configure_ports(const uint8_t *port_mapping, uint8_t *PxMAPy, - uint8_t num_of_ports, uint8_t port_map_reconfig) -{ - uint16_t i; - - // Store current interrupt state, then disable all interrupts - uint16_t globalInterruptState = __get_SR_register() & GIE; - __disable_interrupt(); - - // Get write-access to port mapping registers: - PMAPPWD = PMAPPW; - - if (port_map_reconfig) { - // Allow reconfiguration during runtime: - PMAPCTL = PMAPRECFG; - } - - // Configure Port Mapping: - for (i = 0; i < num_of_ports * 8; i++) { - PxMAPy[i] = port_mapping[i]; - } - - // Disable write-access to port mapping registers: - PMAPPWD = 0; - - // Restore previous interrupt state - __bis_SR_register(globalInterruptState); -} - -#endif /* __MSP430_HAS_PORT_MAPPING__ */ diff --git a/F5xx_F6xx_Core_Lib/HAL_PMAP.h b/F5xx_F6xx_Core_Lib/HAL_PMAP.h deleted file mode 100644 index 3dcf35e..0000000 --- a/F5xx_F6xx_Core_Lib/HAL_PMAP.h +++ /dev/null @@ -1,60 +0,0 @@ -/******************************************************************************* - * - * HAL_PMAP.h - * Port Mapper Library for PMAP controller of MSP430F5xx/6xx family - * - * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Created: Version 1.0 11/24/2009 - * Updated: Version 2.0 12/15/2010 - * - ******************************************************************************/ - -#ifndef HAL_PMAP_H -#define HAL_PMAP_H - -#include - -/******************************************************************************* - * \brief Configures the MSP430 Port Mapper - * - * \param *port_mapping Pointer to init Data - * \param PxMAPy Pointer start of first Port Mapper to initialize - * \param num_of_ports Number of Ports to initialize - * \param port_map_reconfig Flag to enable/disable reconfiguration - * - ******************************************************************************/ -extern void configure_ports(const uint8_t *port_mapping, uint8_t *PxMAPy, - uint8_t num_of_ports, uint8_t port_map_reconfig); - -#endif /* HAL_PMAP_H */ diff --git a/F5xx_F6xx_Core_Lib/HAL_PMM.c b/F5xx_F6xx_Core_Lib/HAL_PMM.c deleted file mode 100644 index aa113db..0000000 --- a/F5xx_F6xx_Core_Lib/HAL_PMM.c +++ /dev/null @@ -1,273 +0,0 @@ -/******************************************************************************* - * - * HAL_PMM.c - * Power Management Module Library for MSP430F5xx/6xx family - * - * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Created: Version 1.0 11/24/2009 - * Updated: Version 2.0 12/15/2010 - * Modified SetVcoreUp() and SetVcoreDown() functions - * - ******************************************************************************/ - -#include "msp430.h" -#include "HAL_PMM.h" - -#define _HAL_PMM_DISABLE_SVML_ -#define _HAL_PMM_DISABLE_SVSL_ -#define _HAL_PMM_DISABLE_FULL_PERFORMANCE_ - -#ifdef _HAL_PMM_DISABLE_SVML_ -#define _HAL_PMM_SVMLE SVMLE -#else -#define _HAL_PMM_SVMLE 0 -#endif - -#ifdef _HAL_PMM_DISABLE_SVSL_ -#define _HAL_PMM_SVSLE SVSLE -#else -#define _HAL_PMM_SVSLE 0 -#endif - -#ifdef _HAL_PMM_DISABLE_FULL_PERFORMANCE_ -#define _HAL_PMM_SVSFP SVSLFP -#define _HAL_PMM_SVMFP SVMLFP -#else -#define _HAL_PMM_SVSFP 0 -#define _HAL_PMM_SVMFP 0 -#endif - -/******************************************************************************* - * \brief Increase Vcore by one level - * - * \param level Level to which Vcore needs to be increased - * \return status Success/failure - ******************************************************************************/ -static uint16_t SetVCoreUp(uint8_t level) -{ - uint16_t PMMRIE_backup, SVSMHCTL_backup, SVSMLCTL_backup; - - // The code flow for increasing the Vcore has been altered to work around - // the erratum FLASH37. - // Please refer to the Errata sheet to know if a specific device is affected - // DO NOT ALTER THIS FUNCTION - - // Open PMM registers for write access - PMMCTL0_H = 0xA5; - - // Disable dedicated Interrupts - // Backup all registers - PMMRIE_backup = PMMRIE; - PMMRIE &= ~(SVMHVLRPE | SVSHPE | SVMLVLRPE | SVSLPE | SVMHVLRIE | - SVMHIE | SVSMHDLYIE | SVMLVLRIE | SVMLIE | SVSMLDLYIE ); - SVSMHCTL_backup = SVSMHCTL; - SVSMLCTL_backup = SVSMLCTL; - - // Clear flags - PMMIFG = 0; - - // Set SVM highside to new level and check if a VCore increase is possible - SVSMHCTL = SVMHE | SVSHE | (SVSMHRRL0 * level); - - // Wait until SVM highside is settled - while ((PMMIFG & SVSMHDLYIFG) == 0); - - // Clear flag - PMMIFG &= ~SVSMHDLYIFG; - - // Check if a VCore increase is possible - if ((PMMIFG & SVMHIFG) == SVMHIFG) { // -> Vcc is too low for a Vcore increase - // recover the previous settings - PMMIFG &= ~SVSMHDLYIFG; - SVSMHCTL = SVSMHCTL_backup; - - // Wait until SVM highside is settled - while ((PMMIFG & SVSMHDLYIFG) == 0); - - // Clear all Flags - PMMIFG &= ~(SVMHVLRIFG | SVMHIFG | SVSMHDLYIFG | SVMLVLRIFG | SVMLIFG | SVSMLDLYIFG); - - PMMRIE = PMMRIE_backup; // Restore PMM interrupt enable register - PMMCTL0_H = 0x00; // Lock PMM registers for write access - return PMM_STATUS_ERROR; // return: voltage not set - } - - // Set also SVS highside to new level - // Vcc is high enough for a Vcore increase - SVSMHCTL |= (SVSHRVL0 * level); - - // Wait until SVM highside is settled - while ((PMMIFG & SVSMHDLYIFG) == 0); - - // Clear flag - PMMIFG &= ~SVSMHDLYIFG; - - // Set VCore to new level - PMMCTL0_L = PMMCOREV0 * level; - - // Set SVM, SVS low side to new level - SVSMLCTL = SVMLE | (SVSMLRRL0 * level) | SVSLE | (SVSLRVL0 * level); - - // Wait until SVM, SVS low side is settled - while ((PMMIFG & SVSMLDLYIFG) == 0); - - // Clear flag - PMMIFG &= ~SVSMLDLYIFG; - // SVS, SVM core and high side are now set to protect for the new core level - - // Restore Low side settings - // Clear all other bits _except_ level settings - SVSMLCTL &= (SVSLRVL0+SVSLRVL1+SVSMLRRL0+SVSMLRRL1+SVSMLRRL2); - - // Clear level settings in the backup register,keep all other bits - SVSMLCTL_backup &= ~(SVSLRVL0+SVSLRVL1+SVSMLRRL0+SVSMLRRL1+SVSMLRRL2); - - // Restore low-side SVS monitor settings - SVSMLCTL |= SVSMLCTL_backup; - - // Restore High side settings - // Clear all other bits except level settings - SVSMHCTL &= (SVSHRVL0+SVSHRVL1+SVSMHRRL0+SVSMHRRL1+SVSMHRRL2); - - // Clear level settings in the backup register,keep all other bits - SVSMHCTL_backup &= ~(SVSHRVL0+SVSHRVL1+SVSMHRRL0+SVSMHRRL1+SVSMHRRL2); - - // Restore backup - SVSMHCTL |= SVSMHCTL_backup; - - // Wait until high side, low side settled - while (((PMMIFG & SVSMLDLYIFG) == 0) && ((PMMIFG & SVSMHDLYIFG) == 0)); - - // Clear all Flags - PMMIFG &= ~(SVMHVLRIFG | SVMHIFG | SVSMHDLYIFG | SVMLVLRIFG | SVMLIFG | SVSMLDLYIFG); - - PMMRIE = PMMRIE_backup; // Restore PMM interrupt enable register - PMMCTL0_H = 0x00; // Lock PMM registers for write access - - return PMM_STATUS_OK; -} - -/******************************************************************************* - * \brief Decrease Vcore by one level - * - * \param level Level to which Vcore needs to be decreased - * \return status Success/failure - ******************************************************************************/ -static uint16_t SetVCoreDown(uint8_t level) -{ - uint16_t PMMRIE_backup, SVSMHCTL_backup, SVSMLCTL_backup; - - // The code flow for decreasing the Vcore has been altered to work around - // the erratum FLASH37. - // Please refer to the Errata sheet to know if a specific device is affected - // DO NOT ALTER THIS FUNCTION - - // Open PMM registers for write access - PMMCTL0_H = 0xA5; - - // Disable dedicated Interrupts - // Backup all registers - PMMRIE_backup = PMMRIE; - PMMRIE &= ~(SVMHVLRPE | SVSHPE | SVMLVLRPE | SVSLPE | SVMHVLRIE | - SVMHIE | SVSMHDLYIE | SVMLVLRIE | SVMLIE | SVSMLDLYIE ); - SVSMHCTL_backup = SVSMHCTL; - SVSMLCTL_backup = SVSMLCTL; - - // Clear flags - PMMIFG &= ~(SVMHIFG | SVSMHDLYIFG | SVMLIFG | SVSMLDLYIFG); - - // Set SVM, SVS high & low side to new settings in normal mode - SVSMHCTL = SVMHE | (SVSMHRRL0 * level) | SVSHE | (SVSHRVL0 * level); - SVSMLCTL = SVMLE | (SVSMLRRL0 * level) | SVSLE | (SVSLRVL0 * level); - - // Wait until SVM high side and SVM low side is settled - while ((PMMIFG & SVSMHDLYIFG) == 0 || (PMMIFG & SVSMLDLYIFG) == 0); - - // Clear flags - PMMIFG &= ~(SVSMHDLYIFG + SVSMLDLYIFG); - // SVS, SVM core and high side are now set to protect for the new core level - - // Set VCore to new level - PMMCTL0_L = PMMCOREV0 * level; - - // Restore Low side settings - // Clear all other bits _except_ level settings - SVSMLCTL &= (SVSLRVL0+SVSLRVL1+SVSMLRRL0+SVSMLRRL1+SVSMLRRL2); - - // Clear level settings in the backup register,keep all other bits - SVSMLCTL_backup &= ~(SVSLRVL0+SVSLRVL1+SVSMLRRL0+SVSMLRRL1+SVSMLRRL2); - - // Restore low-side SVS monitor settings - SVSMLCTL |= SVSMLCTL_backup; - - // Restore High side settings - // Clear all other bits except level settings - SVSMHCTL &= (SVSHRVL0+SVSHRVL1+SVSMHRRL0+SVSMHRRL1+SVSMHRRL2); - - // Clear level settings in the backup register, keep all other bits - SVSMHCTL_backup &= ~(SVSHRVL0+SVSHRVL1+SVSMHRRL0+SVSMHRRL1+SVSMHRRL2); - - // Restore backup - SVSMHCTL |= SVSMHCTL_backup; - - // Wait until high side, low side settled - while (((PMMIFG & SVSMLDLYIFG) == 0) && ((PMMIFG & SVSMHDLYIFG) == 0)); - - // Clear all Flags - PMMIFG &= ~(SVMHVLRIFG | SVMHIFG | SVSMHDLYIFG | SVMLVLRIFG | SVMLIFG | SVSMLDLYIFG); - - PMMRIE = PMMRIE_backup; // Restore PMM interrupt enable register - PMMCTL0_H = 0x00; // Lock PMM registers for write access - return PMM_STATUS_OK; // Return: OK -} - -uint16_t SetVCore(uint8_t level) -{ - uint16_t actlevel; - uint16_t status = 0; - - level &= PMMCOREV_3; // Set Mask for Max. level - actlevel = (PMMCTL0 & PMMCOREV_3); // Get actual VCore - // step by step increase or decrease - while (((level != actlevel) && (status == 0)) || (level < actlevel)) { - if (level > actlevel) { - status = SetVCoreUp(++actlevel); - } - else { - status = SetVCoreDown(--actlevel); - } - } - - return status; -} diff --git a/F5xx_F6xx_Core_Lib/HAL_PMM.h b/F5xx_F6xx_Core_Lib/HAL_PMM.h deleted file mode 100644 index aecb77d..0000000 --- a/F5xx_F6xx_Core_Lib/HAL_PMM.h +++ /dev/null @@ -1,106 +0,0 @@ -/******************************************************************************* - * - * HAL_PMM.h - * Power Management Module Library for MSP430F5xx/6xx family - * - * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Created: Version 1.0 11/24/2009 - * Updated: Version 2.0 12/15/2010 - * - ******************************************************************************/ - -#ifndef HAL_PMM_H -#define HAL_PMM_H - -#include -#include "HAL_MACROS.h" - -/******************************************************************************* - * Macros - ******************************************************************************/ -#define ENABLE_SVSL() st(PMMCTL0_H = 0xA5; SVSMLCTL |= SVSLE; PMMCTL0_H = 0x00;) -#define DISABLE_SVSL() st(PMMCTL0_H = 0xA5; SVSMLCTL &= ~SVSLE; PMMCTL0_H = 0x00;) -#define ENABLE_SVML() st(PMMCTL0_H = 0xA5; SVSMLCTL |= SVMLE; PMMCTL0_H = 0x00;) -#define DISABLE_SVML() st(PMMCTL0_H = 0xA5; SVSMLCTL &= ~SVMLE; PMMCTL0_H = 0x00;) -#define ENABLE_SVSH() st(PMMCTL0_H = 0xA5; SVSMHCTL |= SVSHE; PMMCTL0_H = 0x00;) -#define DISABLE_SVSH() st(PMMCTL0_H = 0xA5; SVSMHCTL &= ~SVSHE; PMMCTL0_H = 0x00;) -#define ENABLE_SVMH() st(PMMCTL0_H = 0xA5; SVSMHCTL |= SVMHE; PMMCTL0_H = 0x00;) -#define DISABLE_SVMH() st(PMMCTL0_H = 0xA5; SVSMHCTL &= ~SVMHE; PMMCTL0_H = 0x00;) -#define ENABLE_SVSL_SVML() st(PMMCTL0_H = 0xA5; SVSMLCTL |= (SVSLE + SVMLE); PMMCTL0_H = 0x00;) -#define DISABLE_SVSL_SVML() st(PMMCTL0_H = 0xA5; SVSMLCTL &= ~(SVSLE + SVMLE); PMMCTL0_H = 0x00;) -#define ENABLE_SVSH_SVMH() st(PMMCTL0_H = 0xA5; SVSMHCTL |= (SVSHE + SVMHE); PMMCTL0_H = 0x00;) -#define DISABLE_SVSH_SVMH() st(PMMCTL0_H = 0xA5; SVSMHCTL &= ~(SVSHE + SVMHE); PMMCTL0_H = 0x00;) - -#define ENABLE_SVSL_RESET() st(PMMCTL0_H = 0xA5; PMMRIE |= SVSLPE; PMMCTL0_H = 0x00;) -#define DISABLE_SVSL_RESET() st(PMMCTL0_H = 0xA5; PMMRIE &= ~SVSLPE; PMMCTL0_H = 0x00;) -#define ENABLE_SVML_INTERRUPT() st(PMMCTL0_H = 0xA5; PMMRIE |= SVMLIE; PMMCTL0_H = 0x00;) -#define DISABLE_SVML_INTERRUPT() st(PMMCTL0_H = 0xA5; PMMRIE &= ~SVMLIE; PMMCTL0_H = 0x00;) -#define ENABLE_SVSH_RESET() st(PMMCTL0_H = 0xA5; PMMRIE |= SVSHPE; PMMCTL0_H = 0x00;) -#define DISABLE_SVSH_RESET() st(PMMCTL0_H = 0xA5; PMMRIE &= ~SVSHPE; PMMCTL0_H = 0x00;) -#define ENABLE_SVMH_INTERRUPT() st(PMMCTL0_H = 0xA5; PMMRIE |= SVMHIE; PMMCTL0_H = 0x00;) -#define DISABLE_SVMH_INTERRUPT() st(PMMCTL0_H = 0xA5; PMMRIE &= ~SVMHIE; PMMCTL0_H = 0x00;) -#define CLEAR_PMM_IFGS() st(PMMCTL0_H = 0xA5; PMMIFG = 0; PMMCTL0_H = 0x00;) - -// These settings use SVSH/LACE = 0 -#define SVSL_ENABLED_IN_LPM_FAST_WAKE() st(PMMCTL0_H = 0xA5; SVSMLCTL |= (SVSLFP+SVSLMD); SVSMLCTL &= ~SVSMLACE; PMMCTL0_H = 0x00;) -#define SVSL_ENABLED_IN_LPM_SLOW_WAKE() st(PMMCTL0_H = 0xA5; SVSMLCTL |= SVSLMD; SVSMLCTL &= ~(SVSLFP+SVSMLACE); PMMCTL0_H = 0x00;) - -#define SVSL_DISABLED_IN_LPM_FAST_WAKE() st(PMMCTL0_H = 0xA5; SVSMLCTL |= SVSLFP; SVSMLCTL &= ~(SVSLMD+SVSMLACE); PMMCTL0_H = 0x00;) -#define SVSL_DISABLED_IN_LPM_SLOW_WAKE() st(PMMCTL0_H = 0xA5; SVSMLCTL &= ~(SVSLFP+SVSMLACE+SVSLMD); PMMCTL0_H = 0x00;) - -#define SVSH_ENABLED_IN_LPM_NORM_PERF() st(PMMCTL0_H = 0xA5; SVSMHCTL |= SVSHMD; SVSMHCTL &= ~(SVSMHACE+SVSHFP); PMMCTL0_H = 0x00;) -#define SVSH_ENABLED_IN_LPM_FULL_PERF() st(PMMCTL0_H = 0xA5; SVSMHCTL |= (SVSHMD+SVSHFP); SVSMHCTL &= ~SVSMHACE; PMMCTL0_H = 0x00;) - -#define SVSH_DISABLED_IN_LPM_NORM_PERF() st(PMMCTL0_H = 0xA5; SVSMHCTL &= ~(SVSMHACE+SVSHFP+SVSHMD);PMMCTL0_H = 0x00;) -#define SVSH_DISABLED_IN_LPM_FULL_PERF() st(PMMCTL0_H = 0xA5; SVSMHCTL |= SVSHFP; SVSMHCTL &= ~(SVSMHACE+SVSHMD); PMMCTL0_H = 0x00;) - -// These setting use SVSH/LACE = 1 -#define SVSL_OPTIMIZED_IN_LPM_FAST_WAKE() st(PMMCTL0_H = 0xA5; SVSMLCTL |= (SVSLFP+SVSLMD+SVSMLACE); PMMCTL0_H = 0x00;) -#define SVSH_OPTIMIZED_IN_LPM_FULL_PERF() st(PMMCTL0_H = 0xA5; SVSMHCTL |= (SVSHMD+SVSHFP+SVSMHACE); PMMCTL0_H = 0x00;) - -/******************************************************************************* - * Defines - ******************************************************************************/ -#define PMM_STATUS_OK 0 -#define PMM_STATUS_ERROR 1 - -/******************************************************************************* - * \brief Set Vcore to expected level - * - * \param level Level to which Vcore needs to be increased/decreased - * \return status Success/failure - ******************************************************************************/ -extern uint16_t SetVCore(uint8_t level); - -#endif /* HAL_PMM_H */ diff --git a/F5xx_F6xx_Core_Lib/HAL_TLV.c b/F5xx_F6xx_Core_Lib/HAL_TLV.c deleted file mode 100644 index 431b440..0000000 --- a/F5xx_F6xx_Core_Lib/HAL_TLV.c +++ /dev/null @@ -1,158 +0,0 @@ -/******************************************************************************* - * - * HAL_TLV.c - * Provides Functions to Read the TLV Data Section of the MSP430 Devices - * - * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Updated: Version 2.0 01/17/2011 - * - ******************************************************************************/ - -#include "msp430.h" -#include "HAL_TLV.h" - -void Get_TLV_Info(uint8_t tag, uint8_t instance, uint8_t *length, uint16_t **data_address) -{ - char *TLV_address = (char *)TLV_START; // TLV Structure Start Address - - while((TLV_address < (char *)TLV_END) - && ((*TLV_address != tag) || instance) // check for tag and instance - && (*TLV_address != TLV_TAGEND)) // do range check first - { - if (*TLV_address == tag) instance--; // repeat till requested instance is reached - TLV_address += *(TLV_address + 1) + 2; // add (Current TAG address + LENGTH) + 2 - } - - if (*TLV_address == tag) // Check if Tag match happened.. - { - *length = *(TLV_address + 1); // Return length = Address + 1 - *data_address = (uint16_t *)(TLV_address + 2); // Return address of first data/value info = Address + 2 - } - else // If there was no tag match and the end of TLV structure was reached.. - { - *length = 0; // Return 0 for TAG not found - *data_address = 0; // Return 0 for TAG not found - } -} - -uint16_t Get_Device_Type(void) -{ - uint16_t *pDeviceType = (uint16_t *)DEVICE_ID_0; - return pDeviceType[0]; // Return Value from TLV Table -} - -uint16_t Get_TLV_Memory(uint8_t instance) -{ - uint8_t *pPDTAG; - uint8_t bPDTAG_bytes; - uint16_t count; - - instance *= 2; // set tag for word access comparison - - // TLV access Function Call - Get_TLV_Info(TLV_PDTAG, 0, &bPDTAG_bytes, (uint16_t **)&pPDTAG); // Get Peripheral data pointer - - for (count = 0;count <= instance; count += 2) - { - if (pPDTAG[count] == 0) return 0; // Return 0 if end reached - if (count == instance) return (pPDTAG[count] | pPDTAG[count+1]<<8); - } - - return 0; // Return 0: not found -} - -uint16_t Get_TLV_Peripheral(uint8_t tag, uint8_t instance) -{ - uint8_t *pPDTAG; - uint8_t bPDTAG_bytes; - uint16_t count = 0; - uint16_t pcount = 0; - - Get_TLV_Info(TLV_PDTAG, 0, &bPDTAG_bytes, (uint16_t **)&pPDTAG); // Get Peripheral data pointer - - // read memory configuration from TLV to get offset for Peripherals - while (Get_TLV_Memory(count)) { - count++; - } - - pcount = pPDTAG[count * 2 + 1]; // get number of Peripheral entries - count++; // inc count to first Periperal - pPDTAG += count*2; // adjust point to first address of Peripheral - count = 0; // set counter back to 0 - pcount *= 2; // align pcount for work comparision - - // TLV access Function Call - for (count = 0; count <= pcount; count += 2) { - if (pPDTAG[count+1] == tag) { // test if required Peripheral is found - if (instance > 0) { // test if required instance is found - instance--; - } - else { - return (pPDTAG[count] | pPDTAG[count + 1] << 8); // Return found data - } - } - } - - return 0; // Return 0: not found -} - -uint8_t Get_TLV_Interrupt(uint8_t tag) -{ - uint8_t *pPDTAG; - uint8_t bPDTAG_bytes; - uint16_t count = 0; - uint16_t pcount = 0; - - Get_TLV_Info(TLV_PDTAG, 0, &bPDTAG_bytes, (uint16_t **)&pPDTAG); // Get Peripheral data pointer - - // read memory configuration from TLV to get offset for Peripherals - while (Get_TLV_Memory(count)) - { - count++; - } - - pcount = pPDTAG[count * 2 + 1]; - count++; // inc count to first Periperal - pPDTAG += (pcount + count) * 2; // adjust point to first address of Peripheral - count = 0; // set counter back to 0 - - // TLV access Function Call - for (count = 0; count <= tag; count += 2) - { - if (pPDTAG[count] == 0) return 0; // Return 0: not found/end of table - if (count == tag) return (pPDTAG[count]); // Return found data - } - - return 0; // Return 0: not found -} diff --git a/F5xx_F6xx_Core_Lib/HAL_TLV.h b/F5xx_F6xx_Core_Lib/HAL_TLV.h deleted file mode 100644 index 042129a..0000000 --- a/F5xx_F6xx_Core_Lib/HAL_TLV.h +++ /dev/null @@ -1,228 +0,0 @@ -/******************************************************************************* - * - * HAL_TLV.c - * Provides Functions to Read the TLV Data Section of the MSP430 Devices - * - * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Updated: Version 2.0 01/17/2011 - * - ******************************************************************************/ - -#ifndef HAL_TLV_H -#define HAL_TLV_H - -#include - -/******************************************************************************* - * Device Descriptors - Fixed Memory Locations - ******************************************************************************/ -#define DEVICE_ID_0 (0x1A04) -#define DEVICE_ID_1 (0x1A05) - -/******************************************************************************* - * Data Types - ******************************************************************************/ -struct s_TLV_Die_Record { - uint8_t die_record[10]; -}; - -struct s_TLV_ADC_Cal_Data { - uint16_t adc_gain_factor; - uint16_t adc_offset; - uint16_t adc_ref15_30_temp; - uint16_t adc_ref15_85_temp; - uint16_t adc_ref20_30_temp; - uint16_t adc_ref20_85_temp; - uint16_t adc_ref25_30_temp; - uint16_t adc_ref25_85_temp; -}; - -struct s_TLV_Timer_D_Cal_Data { - uint16_t TDH0CTL1_64; - uint16_t TDH0CTL1_128; - uint16_t TDH0CTL1_200; - uint16_t TDH0CTL1_256; -}; - -struct s_TLV_REF_Cal_Data { - uint16_t ref_ref15; - uint16_t ref_ref20; - uint16_t adc_ref25; -}; - -/******************************************************************************* - * Tag Defines - ******************************************************************************/ -#define TLV_LDTAG (0x01) /* Legacy descriptor (1xx, 2xx, - 4xx families) */ -#define TLV_PDTAG (0x02) /* Peripheral discovery descriptor */ -#define TLV_Reserved3 (0x03) /* Future usage */ -#define TLV_Reserved4 (0x04) /* Future usage */ -#define TLV_BLANK (0x05) /* Blank descriptor */ -#define TLV_Reserved6 (0x06) /* Future usage */ -#define TLV_Reserved7 (0x07) /* Serial Number */ -#define TLV_DIERECORD (0x08) /* Die Record */ -#define TLV_ADCCAL (0x11) /* ADC12 calibration */ -#define TLV_ADC12CAL (0x11) /* ADC12 calibration */ -#define TLV_ADC10CAL (0x13) /* ADC10 calibration */ -#define TLV_REFCAL (0x12) /* REF calibration */ -#define TLV_TIMER_D_CAL (0x15) /* Timer_Dx calibration */ -#define TLV_TAGEXT (0xFE) /* Tag extender */ -#define TLV_TAGEND (0xFF) /* Tag End of Table */ - -/******************************************************************************* - * Peripheral Defines - ******************************************************************************/ -#define TLV_PID_NO_MODULE (0x00) /* No Module */ -#define TLV_PID_PORTMAPPING (0x10) /* Port Mapping */ -#define TLV_PID_MSP430CPUXV2 (0x23) /* MSP430CPUXV2 */ -#define TLV_PID_JTAG (0x09) /* JTAG */ -#define TLV_PID_SBW (0x0F) /* SBW */ -#define TLV_PID_EEM_XS (0x02) /* EEM X-Small */ -#define TLV_PID_EEM_S (0x03) /* EEM Small */ -#define TLV_PID_EEM_M (0x04) /* EEM Medium */ -#define TLV_PID_EEM_L (0x05) /* EEM Large */ -#define TLV_PID_PMM (0x30) /* PMM */ -#define TLV_PID_PMM_FR (0x32) /* PMM FRAM */ -#define TLV_PID_FCTL (0x39) /* Flash */ -#define TLV_PID_CRC16 (0x3C) /* CRC16 */ -#define TLV_PID_CRC16_RB (0x3D) /* CRC16 Reverse */ -#define TLV_PID_WDT_A (0x40) /* WDT_A */ -#define TLV_PID_SFR (0x41) /* SFR */ -#define TLV_PID_SYS (0x42) /* SYS */ -#define TLV_PID_RAMCTL (0x44) /* RAMCTL */ -#define TLV_PID_DMA_1 (0x46) /* DMA 1 */ -#define TLV_PID_DMA_3 (0x47) /* DMA 3 */ -#define TLV_PID_UCS (0x48) /* UCS */ -#define TLV_PID_DMA_6 (0x4A) /* DMA 6 */ -#define TLV_PID_DMA_2 (0x4B) /* DMA 2 */ -#define TLV_PID_PORT1_2 (0x51) /* Port 1 + 2 / A */ -#define TLV_PID_PORT3_4 (0x52) /* Port 3 + 4 / B */ -#define TLV_PID_PORT5_6 (0x53) /* Port 5 + 6 / C */ -#define TLV_PID_PORT7_8 (0x54) /* Port 7 + 8 / D */ -#define TLV_PID_PORT9_10 (0x55) /* Port 9 + 10 / E */ -#define TLV_PID_PORT11_12 (0x56) /* Port 11 + 12 / F */ -#define TLV_PID_PORTU (0x5E) /* Port U */ -#define TLV_PID_PORTJ (0x5F) /* Port J */ -#define TLV_PID_TA2 (0x60) /* Timer A2 */ -#define TLV_PID_TA3 (0x61) /* Timer A1 */ -#define TLV_PID_TA5 (0x62) /* Timer A5 */ -#define TLV_PID_TA7 (0x63) /* Timer A7 */ -#define TLV_PID_TB3 (0x65) /* Timer B3 */ -#define TLV_PID_TB5 (0x66) /* Timer B5 */ -#define TLV_PID_TB7 (0x67) /* Timer B7 */ -#define TLV_PID_RTC (0x68) /* RTC */ -#define TLV_PID_BT_RTC (0x69) /* BT + RTC */ -#define TLV_PID_BBS (0x6A) /* Battery Backup Switch */ -#define TLV_PID_RTC_B (0x6B) /* RTC_B */ -#define TLV_PID_TD2 (0x6C) /* Timer D2 */ -#define TLV_PID_TD3 (0x6D) /* Timer D1 */ -#define TLV_PID_TD5 (0x6E) /* Timer D5 */ -#define TLV_PID_TD7 (0x6F) /* Timer D7 */ -#define TLV_PID_TEC (0x70) /* Imer Event Control */ -#define TLV_PID_RTC_C (0x71) /* RTC_C */ -#define TLV_PID_AES (0x80) /* AES */ -#define TLV_PID_MPY16 (0x84) /* MPY16 */ -#define TLV_PID_MPY32 (0x85) /* MPY32 */ -#define TLV_PID_MPU (0x86) /* MPU */ -#define TLV_PID_USCI_AB (0x90) /* USCI_AB */ -#define TLV_PID_USCI_A (0x91) /* USCI_A */ -#define TLV_PID_USCI_B (0x92) /* USCI_B */ -#define TLV_PID_EUSCI_A (0x94) /* eUSCI_A */ -#define TLV_PID_EUSCI_B (0x95) /* eUSCI_B */ -#define TLV_PID_REF (0xA0) /* Shared Reference */ -#define TLV_PID_COMP_B (0xA8) /* COMP_B */ -#define TLV_PID_COMP_D (0xA9) /* COMP_D */ -#define TLV_PID_USB (0x98) /* USB */ -#define TLV_PID_LCD_B (0xB1) /* LCD_B */ -#define TLV_PID_LCD_C (0xB2) /* LCD_C */ -#define TLV_PID_DAC12_A (0xC0) /* DAC12_A */ -#define TLV_PID_SD16_B_1 (0xC8) /* SD16_B 1 Channel */ -#define TLV_PID_SD16_B_2 (0xC9) /* SD16_B 2 Channel */ -#define TLV_PID_SD16_B_3 (0xCA) /* SD16_B 3 Channel */ -#define TLV_PID_SD16_B_4 (0xCB) /* SD16_B 4 Channel */ -#define TLV_PID_SD16_B_5 (0xCC) /* SD16_B 5 Channel */ -#define TLV_PID_SD16_B_6 (0xCD) /* SD16_B 6 Channel */ -#define TLV_PID_SD16_B_7 (0xCE) /* SD16_B 7 Channel */ -#define TLV_PID_SD16_B_8 (0xCF) /* SD16_B 8 Channel */ -#define TLV_PID_ADC12_A (0xD1) /* ADC12_A */ -#define TLV_PID_ADC10_A (0xD3) /* ADC10_A */ -#define TLV_PID_ADC10_B (0xD4) /* ADC10_B */ -#define TLV_PID_SD16_A (0xD8) /* SD16_A */ -#define TLV_PID_TI_BSL (0xFC) /* BSL */ - -/******************************************************************************* - * \brief Get Information out of the TLV Table - * - * \param tag Tag of the TLV entry - * \param instance Instance of the Tag of the TLV entry - * \param *length return: Length of the information if found - * \param **data_address return: start pointer of Data - ******************************************************************************/ -void Get_TLV_Info(uint8_t tag, uint8_t instance, uint8_t *length, - uint16_t **data_address); - -/******************************************************************************* - * \brief Get Device Type out of the TLV Table - * - * \return Device dependent value - ******************************************************************************/ -uint16_t Get_Device_Type(void); - -/******************************************************************************* - * \brief Get Memory Info out of the TLV Table - * - * \param instance Index of the Instance [0..] - * \return Memory Data found - ******************************************************************************/ -uint16_t Get_TLV_Memory(uint8_t instance); - -/******************************************************************************* - * \brief Get Peripheral Info out of the TLV Table - * - * \param tag Tag of the TLV entry - * \param instance Index of the Instance [0..] - * \return Peripheral Data found - ******************************************************************************/ -uint16_t Get_TLV_Peripheral(uint8_t tag, uint8_t instance); - -/******************************************************************************* - * \brief Get Interrupt Info out of the TLV Table - * - * \param tag Tag of the TLV entry - * \return Interrupt Data found - ******************************************************************************/ -uint8_t Get_TLV_Interrupt(uint8_t tag); - -#endif /* HAL_TLV_H */ diff --git a/F5xx_F6xx_Core_Lib/HAL_UCS.c b/F5xx_F6xx_Core_Lib/HAL_UCS.c deleted file mode 100644 index 9294fdd..0000000 --- a/F5xx_F6xx_Core_Lib/HAL_UCS.c +++ /dev/null @@ -1,293 +0,0 @@ -/******************************************************************************* - * - * HAL_UCS.c - * Provides Functions to Initialize the UCS/FLL and clock sources - * - * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Created: Version 1.0 11/24/2009 - * Updated: Version 2.0 12/15/2010 - * Added Functions: XT2_Stop() and XT1_Stop() - * Modified all functions to preserve drive settings - * - ******************************************************************************/ - -#include "msp430.h" -#include "HAL_UCS.h" - -/******************************************************************************* - * Check and define required Defines - ******************************************************************************/ -#ifndef XT1LFOFFG // Defines if not available in header file -#define XT1LFOFFG 0 -#endif - -#ifndef XT1HFOFFG // Defines if not available in header file -#define XT1HFOFFG 0 -#endif - -#ifndef XT2OFFG // Defines if not available in header file -#define XT2OFFG 0 -#endif - -#ifndef XTS // Defines if not available in header file -#define XTS 0 -#endif - -#ifndef XT2DRIVE_3 // Defines if not available in header file -#define XT2DRIVE_3 0 -#endif - -void LFXT_Start(uint16_t xtdrive) -{ - // If the drive setting is not already set to maximum - // Set it to max for LFXT startup - if ((UCSCTL6 & XT1DRIVE_3)!= XT1DRIVE_3) { - UCSCTL6_L |= XT1DRIVE1_L + XT1DRIVE0_L; // Highest drive setting for XT1startup - } - - while (SFRIFG1 & OFIFG) { // Check OFIFG fault flag - UCSCTL7 &= ~(DCOFFG+XT1LFOFFG+XT1HFOFFG+XT2OFFG); // Clear OSC flaut Flags fault flags - SFRIFG1 &= ~OFIFG; // Clear OFIFG fault flag - } - - UCSCTL6 = (UCSCTL6 & ~(XT1DRIVE_3)) | (xtdrive); // set requested Drive mode -} - -uint16_t LFXT_Start_Timeout(uint16_t xtdrive, uint16_t timeout) -{ - // If the drive setting is not already set to maximum - // Set it to max for LFXT startup - if ((UCSCTL6 & XT1DRIVE_3)!= XT1DRIVE_3) { - UCSCTL6_L |= XT1DRIVE1_L+XT1DRIVE0_L; // Highest drive setting for XT1startup - } - - while ((SFRIFG1 & OFIFG) && timeout--){ // Check OFIFG fault flag - UCSCTL7 &= ~(DCOFFG+XT1LFOFFG+XT1HFOFFG+XT2OFFG); // Clear OSC flaut Flags fault flags - SFRIFG1 &= ~OFIFG; // Clear OFIFG fault flag - } - - UCSCTL6 = (UCSCTL6 & ~(XT1DRIVE_3)) |(xtdrive); // set Drive mode - - if (timeout) - return (UCS_STATUS_OK); - else - return (UCS_STATUS_ERROR); -} - -void XT1_Start(uint16_t xtdrive) -{ - // Check if drive value is the expected one - if ((UCSCTL6 & XT1DRIVE_3) != xtdrive) { - UCSCTL6 &= ~XT1DRIVE_3; // Clear XT1drive field - UCSCTL6 |= xtdrive; // Set requested value - } - - UCSCTL6 &= ~XT1OFF; // Enable XT1 - UCSCTL6 |= XTS; // Enable HF mode - - while (SFRIFG1 & OFIFG) { // Check OFIFG fault flag - UCSCTL7 &= ~(DCOFFG+XT1LFOFFG+XT1HFOFFG+XT2OFFG); // Clear OSC flaut Flags - SFRIFG1 &= ~OFIFG; // Clear OFIFG fault flag - } -} - -uint16_t XT1_Start_Timeout(uint16_t xtdrive, uint16_t timeout) -{ - // Check if drive value is the expected one - if ((UCSCTL6 & XT1DRIVE_3) != xtdrive) { - UCSCTL6 &= ~XT1DRIVE_3; // Clear XT1drive field - UCSCTL6 |= xtdrive; // Set requested value - } - - UCSCTL6 &= ~XT1OFF; // Enable XT1 - UCSCTL6 |= XTS; // Enable HF mode - - while ((SFRIFG1 & OFIFG) && timeout--) { // Check OFIFG fault flag - UCSCTL7 &= ~(DCOFFG+XT1LFOFFG+XT1HFOFFG+XT2OFFG); // Clear OSC flaut Flags - SFRIFG1 &= ~OFIFG; // Clear OFIFG fault flag - } - - if (timeout) { - return UCS_STATUS_OK; - } - else { - return UCS_STATUS_ERROR; - } -} - -void XT1_Bypass(void) -{ - UCSCTL6 |= XT1BYPASS; - - while (SFRIFG1 & OFIFG) { // Check OFIFG fault flag - UCSCTL7 &= ~(DCOFFG+XT1LFOFFG+XT1HFOFFG+XT2OFFG); // Clear OSC flaut Flags - SFRIFG1 &= ~OFIFG; // Clear OFIFG fault flag - } -} - -void XT1_Stop(void) -{ - UCSCTL6 |= XT1OFF; // Switch off XT1 oscillator -} - -void XT2_Start(uint16_t xtdrive) -{ - // Check if drive value is the expected one - if ((UCSCTL6 & XT2DRIVE_3) != xtdrive) { - UCSCTL6 &= ~XT2DRIVE_3; // Clear XT2drive field - UCSCTL6 |= xtdrive; // Set requested value - } - - UCSCTL6 &= ~XT2OFF; - - while (SFRIFG1 & OFIFG) { // Check OFIFG fault flag - UCSCTL7 &= ~(DCOFFG+XT1LFOFFG+XT1HFOFFG+XT2OFFG); // Clear OSC flaut Flags - SFRIFG1 &= ~OFIFG; // Clear OFIFG fault flag - } -} - -uint16_t XT2_Start_Timeout(uint16_t xtdrive, uint16_t timeout) -{ - // Check if drive value is the expected one - if ((UCSCTL6 & XT2DRIVE_3) != xtdrive) { - UCSCTL6 &= ~XT2DRIVE_3; // Clear XT2drive field - UCSCTL6 |= xtdrive; // Set requested value - } - - UCSCTL6 &= ~XT2OFF; - - while ((SFRIFG1 & OFIFG) && timeout--) { // Check OFIFG fault flag - UCSCTL7 &= ~(DCOFFG+XT1LFOFFG+XT1HFOFFG+XT2OFFG); // Clear OSC flaut Flags - SFRIFG1 &= ~OFIFG; // Clear OFIFG fault flag - } - - if (timeout) { - return UCS_STATUS_OK; - } - else { - return UCS_STATUS_ERROR; - } -} - -void XT2_Bypass(void) -{ -#ifdef XT2BYPASS // On devices without XT2 this function will be empty - UCSCTL6 |= XT2BYPASS; - - while (SFRIFG1 & OFIFG) { // Check OFIFG fault flag - UCSCTL7 &= ~(DCOFFG+XT1LFOFFG+XT1HFOFFG+XT2OFFG); // Clear OSC flaut Flags - SFRIFG1 &= ~OFIFG; // Clear OFIFG fault flag - } -#endif -} - -void XT2_Stop(void) -{ - UCSCTL6 |= XT2OFF; // Switch off XT2 oscillator -} - -void Init_FLL_Settle(uint16_t fsystem, uint16_t ratio) -{ - volatile uint16_t x = ratio * 32; - - Init_FLL(fsystem, ratio); - - while (x--) { - __delay_cycles(30); - } -} - -void Init_FLL(uint16_t fsystem, uint16_t ratio) -{ - uint16_t d, dco_div_bits; - uint16_t mode = 0; - - // Save actual state of FLL loop control, then disable it. This is needed to - // prevent the FLL from acting as we are making fundamental modifications to - // the clock setup. - uint16_t srRegisterState = __get_SR_register() & SCG0; - __bic_SR_register(SCG0); - - d = ratio; - dco_div_bits = FLLD__2; // Have at least a divider of 2 - - if (fsystem > 16000) { - d >>= 1 ; - mode = 1; - } - else { - fsystem <<= 1; // fsystem = fsystem * 2 - } - - while (d > 512) { - dco_div_bits = dco_div_bits + FLLD0; // Set next higher div level - d >>= 1; - } - - UCSCTL0 = 0x0000; // Set DCO to lowest Tap - - UCSCTL2 &= ~(0x03FF); // Reset FN bits - UCSCTL2 = dco_div_bits | (d - 1); - - if (fsystem <= 630) // fsystem < 0.63MHz - UCSCTL1 = DCORSEL_0; - else if (fsystem < 1250) // 0.63MHz < fsystem < 1.25MHz - UCSCTL1 = DCORSEL_1; - else if (fsystem < 2500) // 1.25MHz < fsystem < 2.5MHz - UCSCTL1 = DCORSEL_2; - else if (fsystem < 5000) // 2.5MHz < fsystem < 5MHz - UCSCTL1 = DCORSEL_3; - else if (fsystem < 10000) // 5MHz < fsystem < 10MHz - UCSCTL1 = DCORSEL_4; - else if (fsystem < 20000) // 10MHz < fsystem < 20MHz - UCSCTL1 = DCORSEL_5; - else if (fsystem < 40000) // 20MHz < fsystem < 40MHz - UCSCTL1 = DCORSEL_6; - else - UCSCTL1 = DCORSEL_7; - - while (SFRIFG1 & OFIFG) { // Check OFIFG fault flag - UCSCTL7 &= ~(DCOFFG+XT1LFOFFG+XT1HFOFFG+XT2OFFG); // Clear OSC flaut Flags - SFRIFG1 &= ~OFIFG; // Clear OFIFG fault flag - } - - if (mode == 1) { // fsystem > 16000 - SELECT_MCLK_SMCLK(SELM__DCOCLK + SELS__DCOCLK); // Select DCOCLK - } - else { - SELECT_MCLK_SMCLK(SELM__DCOCLKDIV + SELS__DCOCLKDIV); // Select DCODIVCLK - } - - __bis_SR_register(srRegisterState); // Restore previous SCG0 -} diff --git a/F5xx_F6xx_Core_Lib/HAL_UCS.h b/F5xx_F6xx_Core_Lib/HAL_UCS.h deleted file mode 100644 index e72f051..0000000 --- a/F5xx_F6xx_Core_Lib/HAL_UCS.h +++ /dev/null @@ -1,163 +0,0 @@ -/******************************************************************************* - * - * HAL_UCS.h - * Provides Functions to Initialize the UCS/FLL and clock sources - * - * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Created: Version 1.0 11/24/2009 - * Updated: Version 2.0 12/15/2010 - * Added Functions: XT2_Stop() and XT1_Stop() - * - ******************************************************************************/ - -#ifndef HAL_UCS_H -#define HAL_UCS_H - -#include -#include "hal_macros.h" - -/******************************************************************************* - * Macros - ******************************************************************************/ - -/* Select source for FLLREF e.g. SELECT_FLLREF(SELREF__XT1CLK) */ -#define SELECT_FLLREF(source) st(UCSCTL3 = (UCSCTL3 & ~(SELREF_7)) | (source);) -/* Select source for ACLK e.g. SELECT_ACLK(SELA__XT1CLK) */ -#define SELECT_ACLK(source) st(UCSCTL4 = (UCSCTL4 & ~(SELA_7)) | (source);) -/* Select source for MCLK e.g. SELECT_MCLK(SELM__XT2CLK) */ -#define SELECT_MCLK(source) st(UCSCTL4 = (UCSCTL4 & ~(SELM_7)) | (source);) -/* Select source for SMCLK e.g. SELECT_SMCLK(SELS__XT2CLK) */ -#define SELECT_SMCLK(source) st(UCSCTL4 = (UCSCTL4 & ~(SELS_7)) | (source);) -/* Select source for MCLK and SMCLK e.g. SELECT_MCLK_SMCLK(SELM__DCOCLK + SELS__DCOCLK) */ -#define SELECT_MCLK_SMCLK(sources) st(UCSCTL4 = (UCSCTL4 & ~(SELM_7 + SELS_7)) | (sources);) - -/* set ACLK/x */ -#define ACLK_DIV(x) st(UCSCTL5 = (UCSCTL5 & ~(DIVA_7)) | (DIVA__##x);) -/* set MCLK/x */ -#define MCLK_DIV(x) st(UCSCTL5 = (UCSCTL5 & ~(DIVM_7)) | (DIVM__##x);) -/* set SMCLK/x */ -#define SMCLK_DIV(x) st(UCSCTL5 = (UCSCTL5 & ~(DIVS_7)) | (DIVS__##x);) -/* Select divider for FLLREF e.g. SELECT_FLLREFDIV(2) */ -#define SELECT_FLLREFDIV(x) st(UCSCTL3 = (UCSCTL3 & ~(FLLREFDIV_7))|(FLLREFDIV__##x);) - -/******************************************************************************* - * Defines - ******************************************************************************/ -#define UCS_STATUS_OK 0 -#define UCS_STATUS_ERROR 1 - -/******************************************************************************* - * \brief Startup routine for 32kHz Crystal on LFXT1 - * - * \param xtdrive Bits defining the LFXT drive mode after startup - ******************************************************************************/ -extern void LFXT_Start(uint16_t xtdrive); - -/******************************************************************************* - * \brief Startup routine for 32kHz Crystal on LFXT1 with timeout counter - * - * \param xtdrive Bits defining the LFXT drive mode after startup - * \param timeout Value for the timeout counter - ******************************************************************************/ -extern uint16_t LFXT_Start_Timeout(uint16_t xtdrive, uint16_t timeout); - -/******************************************************************************* - * \brief Startup routine for XT1 - * - * \param xtdrive Bits defining the XT drive mode - ******************************************************************************/ -extern void XT1_Start(uint16_t xtdrive); - -/******************************************************************************* - * \brief Startup routine for XT1 with timeout counter - * - * \param xtdrive Bits defining the XT drive mode - * \param timeout Value for the timeout counter - ******************************************************************************/ -extern uint16_t XT1_Start_Timeout(uint16_t xtdrive, uint16_t timeout); - -/******************************************************************************* - * \brief Use XT1 in Bypasss mode - ******************************************************************************/ -extern void XT1_Bypass(void); - -/******************************************************************************* - * \brief Stop XT1 oscillator - ******************************************************************************/ -extern void XT1_Stop(void); - -/******************************************************************************* - * \brief Startup routine for XT2 - * - * \param xtdrive Bits defining the XT drive mode - ******************************************************************************/ -extern void XT2_Start(uint16_t xtdrive); - -/******************************************************************************* - * \brief Startup routine for XT2 with timeout counter - * - * \param xtdrive Bits defining the XT drive mode - * \param timeout Value for the timeout counter - ******************************************************************************/ -extern uint16_t XT2_Start_Timeout(uint16_t xtdrive, uint16_t timeout); - -/******************************************************************************* - * \brief Use XT2 in Bypasss mode for MCLK - ******************************************************************************/ -extern void XT2_Bypass(void); - -/******************************************************************************* - * \brief Stop XT2 oscillator - ******************************************************************************/ -extern void XT2_Stop(void); - -/******************************************************************************* - * \brief Initializes FLL of the UCS and wait till settled before allowing - * code execution to resume. The use of this function is preferred - * over the use of Init_FLL(). - * - * \param fsystem Required system frequency (MCLK) in kHz - * \param ratio Ratio between fsystem and FLLREFCLK - ******************************************************************************/ -extern void Init_FLL_Settle(uint16_t fsystem, uint16_t ratio); - -/******************************************************************************* - * \brief Initializes FLL of the UCS - * - * \param fsystem Required system frequency (MCLK) in kHz - * \param ratio Ratio between fsystem and FLLREFCLK - ******************************************************************************/ -extern void Init_FLL(uint16_t fsystem, uint16_t ratio); - -#endif /* HAL_UCS_H */ diff --git a/I2C.c b/I2C.c deleted file mode 100644 index 4f4faab..0000000 --- a/I2C.c +++ /dev/null @@ -1,347 +0,0 @@ -/* - * I2C.c - * - * The I2C communication functions and BSL invoke sequence. - * - * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include -#include "I2C.h" -#include "uart.h" -#include "msp430.h" -#include "main.h" - -unsigned char *PTxData; // Pointer to TX data -int TXByteCtr; -unsigned char *PRxData; // Pointer to RX data -int RXByteCtr; -unsigned char RxBuffer[256]; - -unsigned char ACK = 0; -unsigned int rxlength = 0; - -#define UART_HEADER 0x80 -#define UART_HEADER_LENGTH 1 // length in byte -#define UART_LENGTH_LENGTH 2 // length in byte -#define UART_CRC_LENGTH 2 // length in byte - -#define TIMEOUT_RECEPTION 1000000 - -enum -{ - I2C_IDLE, - I2C_RECEIVING, - I2C_RECEIVE_COMPLETE, - I2C_TRANSMITTING, - I2C_TRANSMIT_COMPLETE, - I2C_ERROR -} I2C_Status_e; - -void InvokeBSLSequence(void) -{ - PJDIR |= (RESET_PIN | TEST_PIN); - Delay(INVOKE_DELAY); - // invoke BSL, classic - //Start: all high - PJOUT = RESET_PIN+TEST_PIN+TCK_PIN; - Delay(INVOKE_DELAY); - Delay(INVOKE_DELAY); - //Delay(INVOKE_DELAY); - - //Step 1 - //RESET LOW - //TEST LOW - //TCK HIGHT - //PJOUT = TCK_PIN; - //Delay(INVOKE_DELAY); - - //Step 2 - //RESET LOW - //TEST HIGH - //TCK LOW - PJOUT = TEST_PIN; - Delay(INVOKE_DELAY); - Delay(INVOKE_DELAY); - - //Step 3 - //RESET LOW - //TEST LOW - //TCK HIGH - //PJOUT = 0; - //Delay(INVOKE_DELAY); - //Delay(20); - - //Step 4 - //RESET LOW - //TEST HIGH - //TCK LOW - //PJOUT = TEST_PIN; - //Delay(INVOKE_DELAY); - - //Step 5 - //RESET HIGH - //TEST HIGH - //TCK LOW - PJOUT = TEST_PIN + RESET_PIN; - Delay(INVOKE_DELAY); - Delay(INVOKE_DELAY); - Delay(INVOKE_DELAY); - Delay(INVOKE_DELAY); - - //Step 6 - //RESET HIGH - //TEST LOW - //TCK HIGH - PJOUT = RESET_PIN; - Delay(INVOKE_DELAY); - Delay(INVOKE_DELAY); - Delay(INVOKE_DELAY); -} - - -//! Initialization of the USCI Module for I2C -int8_t InitI2C(unsigned char eeprom_i2c_address, uint32_t bitrate) -{ - int8_t ret =1; - - //Simple port mapping - __disable_interrupt(); // Disable Interrupts before altering Port Mapping registers - PMAPKEYID = PMAPKEY; - P4MAP4 = PM_UCB0SCL; - P4MAP5 = PM_UCB0SDA; - PMAPKEYID = 0; - __enable_interrupt(); - - UCB0CTL1 = UCSWRST; // Enable SW reset - - UCB0CTL0 = UCMST + UCMODE_3 + UCSYNC; // I2C Master, synchronous mode - UCB0CTL1 = UCSSEL_2 + UCSWRST; // Use SMCLK, keep SW reset - - - switch(bitrate) - { - case 100001: - P1OUT ^= (BIT0|BIT1); - InvokeBSLSequence(); - P1OUT |= (BIT0); - UCB0BR0 = SCL_CLOCK_DIV(100000); // set prescaler - break; - case 100000: - P1OUT |= (BIT0); - UCB0BR0 = SCL_CLOCK_DIV(100000); // set prescaler - break; - case 400001: - P1OUT ^= (BIT0|BIT1); - InvokeBSLSequence(); - P1OUT |= (BIT1); - UCB0BR0 = SCL_CLOCK_DIV(400000); // set prescaler - break; - case 400000: - P1OUT |= (BIT1); - UCB0BR0 = SCL_CLOCK_DIV(400000); // set prescaler - break; - default: - ret = 1; - } - - UCB0BR1 = 0; - UCB0I2CSA = eeprom_i2c_address; // Set slave address - - I2C_PORT_SEL |= SDA_PIN + SCL_PIN; // select module function for the used I2C pins - - UCB0CTL1 &= ~UCSWRST; // Clear SW reset, resume operation - - PRxData = RxBuffer; // Incase no receive buffer is assigned - - if(UCB0STAT & UCBBUSY) // test if bus to be free - { // otherwise a manual Clock on is generated - I2C_PORT_SEL &= ~SCL_PIN; // Select Port function for SCL - I2C_PORT_OUT &= ~SCL_PIN; // - I2C_PORT_DIR |= SCL_PIN; // drive SCL low - I2C_PORT_SEL |= SDA_PIN + SCL_PIN; // select module function for the used I2C pins - }; - - I2C_Status_e = I2C_IDLE; - - return ret; -} - -int16_t i2cSendMessage(unsigned char* I2cMessage, int messageLength) -{ - UCB0IE &= ~UCRXIE; // disable RX ready interrupt - UCB0IFG &= ~(UCTXIFG + UCSTPIFG + UCNACKIFG); // clear TX ready and stop interrupt flag - UCB0IE |= UCTXIE | UCNACKIE; // enable TX ready interrupt - - PTxData = (unsigned char *)I2cMessage; // TX array start address - - TXByteCtr = messageLength ; // Load TX byte counter - - I2C_Status_e = I2C_TRANSMITTING; - UCB0CTL1 |= UCTR + UCTXSTT; // I2C TX, start condition - // while (UCB0CTL1 & UCTXSTT); // Start condition sent? - // while (UCB0STAT & UCBBUSY); // wait for bus to be free !!!!! - // UCB0IE &= ~UCSTPIE; // disable STOP interrupt - - while(I2C_Status_e == I2C_TRANSMITTING); - - if(I2C_Status_e == I2C_TRANSMIT_COMPLETE) - { - // check for commands that doesn't require an ack - PTxData = (unsigned char *)I2cMessage; // TX array start address - - if((*(PTxData + UART_HEADER_LENGTH + UART_LENGTH_LENGTH) == 0x1B)) - return 0; - else - return 1; - } - else if(I2C_Status_e == I2C_ERROR) - { - return -1; - } - - return -1; - -} - -// returns number of received bytes -int16_t i2cReceiveMessage(unsigned char* I2cMessage) -{ - uint32_t timeout; - - UCB0CTL1 &= ~UCTR; - UCB0IE |= UCRXIE; // Enable RX interrupt - - PRxData = (unsigned char *)I2cMessage; // Start of RX buffer - RXByteCtr = 1; // Load RX byte counter - - ACK = 0; - I2C_Status_e = I2C_RECEIVING; - UCB0CTL1 |= UCTXSTT; - //__bis_SR_register(LPM0_bits + GIE); // Enter LPM0, enable interrupts - // Remain in LPM0 until all data - // is RX'd - timeout = TIMEOUT_RECEPTION; - while((I2C_Status_e == I2C_RECEIVING) && (timeout-- != 0x00)); - - if((timeout == 0) || (I2C_Status_e == I2C_ERROR)) - { - i2cStopSending(); - timeout = TIMEOUT_RECEPTION; - while((UCB0CTL1 & UCTXSTP) && (timeout-- != 0)); - } - - if(I2C_Status_e == I2C_RECEIVE_COMPLETE) - { - return (rxlength > 0) ? 1 + I2C_HEADER_LENGTH + I2C_LENGTH_LENGTH + rxlength + I2C_CRC_LENGTH : 1 + I2C_HEADER_LENGTH + I2C_LENGTH_LENGTH; - } - else - return -1; - -} - -void i2cStopSending(void) -{ - UCB0CTL1 |= UCTXSTP; -} - -// ISR for I2C -#pragma vector = USCI_B0_VECTOR -__interrupt void USCI_B0_ISR(void) -{ - switch(__even_in_range(UCB0IV,USCI_I2C_UCTXIFG)) - { - case USCI_NONE: break; // Vector 0: No interrupts - case USCI_I2C_UCALIFG: break; // Vector 2: UCALIFG - case USCI_I2C_UCNACKIFG: - I2C_Status_e = I2C_ERROR; - break; // Vector 4: NACKIFG - case USCI_I2C_UCSTTIFG: break; // Vector 6: STTIFG - case USCI_I2C_UCSTPIFG: break; // Vector 8: STPIFG - case USCI_I2C_UCRXIFG: // Vector 10: RXIFG - - if (ACK == 0) - { - *PRxData++ = UCB0RXBUF; // Move RX data to address PRxData - if(*(PRxData-1) != BSL_RESPONSE_ACK) - { - UCB0CTL1 |= UCTXSTP; // Generate I2C stop condition - } - else - { - ACK = 1; - RXByteCtr = I2C_HEADER_LENGTH + I2C_LENGTH_LENGTH; // receives the next three bytes - rxlength = 0; - } - } - else - { - RXByteCtr--; // Decrement RX byte counter - if(RXByteCtr) - { - *PRxData++ = UCB0RXBUF; // Move RX data to address PRxData - if((RXByteCtr == 1) && (rxlength > 0)) // Only one byte left? - UCB0CTL1 |= UCTXSTP; // Generate I2C stop condition - } - else if(rxlength == 0) - { - *PRxData++ = UCB0RXBUF; // Move RX data to address PRxData - rxlength = ((unsigned int) *(PRxData-1) << 8) | *(PRxData-2); - if(rxlength == 0) UCB0CTL1 |= UCTXSTP; // stop receiving if no bytes required - RXByteCtr = rxlength + I2C_CRC_LENGTH; - } - else - { - *PRxData = UCB0RXBUF; // Move final RX data to PRxData - I2C_Status_e = I2C_RECEIVE_COMPLETE; - //__bic_SR_register_on_exit(LPM0_bits); // Exit active CPU - } - } - break; - case USCI_I2C_UCTXIFG: // Vector 12: TXIFG - if(TXByteCtr) // Check TX byte counter - { - UCB0TXBUF = *PTxData++; // Load TX buffer - TXByteCtr--; // Decrement TX byte counter - } - else - { - //UCB0CTL1 |= UCTXSTP; // Generate I2C stop condition - I2C_Status_e = I2C_TRANSMIT_COMPLETE; - //__bic_SR_register_on_exit(LPM0_bits); // Exit active CPU - } - break; - default: - break; - } -} diff --git a/I2C.h b/I2C.h deleted file mode 100644 index b7f52e2..0000000 --- a/I2C.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * I2C.h - * - * The I2C communication functions and BSL invoke sequence. - * - * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef I2C_H_ -#define I2C_H_ - -#include - -#define BSL_SLAVE_ADDR 0x48 - -#define I2C_PORT_SEL P4SEL -#define I2C_PORT_OUT P4OUT -#define I2C_PORT_REN P4REN -#define I2C_PORT_DIR P4DIR - -#define SDA_PIN BIT5 -#define SCL_PIN BIT4 -#define SCL_CLOCK_DIV(X) (USB_MCLK_FREQ/X) - -#define RESET_HIGH {PJOUT |= BIT1;} -#define RESET_LOW {PJOUT &= ~BIT1;} -#define TEST_HIGH {PJOUT |= BIT2;} -#define TEST_LOW {PJOUT &= ~BIT2;} -#define RESET_PIN BIT1 -#define TEST_PIN BIT2 -#define TCK_PIN BIT3 - -#define INVOKE_DELAY 1000 - -// Timing for Pin Toggling during BSL Entry Sequence -// TEST PIN reset time = 10us (must be less than 15us) -#define BSL_ENTRY_SEQUENCE_TIME 50 - -//#define BSL_PORT_DIR P6DIR -//#define BSL_PORT_OUT P6OUT -//#define BSL_RESET_PIN (BIT0 + BIT1) -//#define BSL_TEST_PIN BIT2 - -#define BSL_RESPONSE_ACK 0x00 -#define BSL_NO_RESPONSE_REQUIRED 0xAE - -#define BSL_ERROR_HEADER_INCORRECT 0x51 -#define BSL_ERROR_INCORRECT_RESPONSE_CRC 0xA0 -#define BSL_ERROR_OK 0x00 - -#define I2C_HEADER 0x80 -#define I2C_HEADER_LENGTH 1 // length in byte -#define I2C_LENGTH_LENGTH 2 // length in byte -#define I2C_CRC_LENGTH 2 // length in byte - - -// Init I2C module B0 and according port settings -int8_t InitI2C(unsigned char eeprom_i2c_address, uint32_t bitrate); -int16_t i2cSendMessage(unsigned char* I2cMessage, int messageLength); -int16_t i2cReceiveMessage(unsigned char* I2cMessage); -void i2cBslEntrySequence(void); -void i2cStopSending(void); - -#endif /*I2C_H_*/ diff --git a/LICENSE.txt b/LICENSE.txt deleted file mode 100644 index d5a2a7e..0000000 --- a/LICENSE.txt +++ /dev/null @@ -1,24 +0,0 @@ -Copyright (c) 2012, Texas Instruments -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - * Neither the name of the Texas Instruments Incorporated nor the - names of its contributors may be used to endorse or promote products - derived from this software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL TEXAS INSTRUMENTS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \ No newline at end of file diff --git a/README.md b/README.md index 73a8d8f..f0f1373 100644 --- a/README.md +++ b/README.md @@ -1,15 +1,15 @@ -MSPBSL_USB_Tool -=============== - -This firmware is designed to allow USB to UART communication for the purpose of programming an MSP430 BootStrapLoader. It requires special hardware, described below. - -This firmware is based on the MSP430 CDC UART Bridge, which can be found in the USB developer package: http://www.ti.com/tool/msp430usbdevpack - -Hardware to run this firmware can be found here: https://www.olimex.com/Products/MSP430/BSL/MSP430-BSL/ - -Schematics are available here: https://www.olimex.com/Products/MSP430/BSL/MSP430-BSL/resources/MSP430-BSL_Rev_B.pdf - -Note: When downloading the firmware via ZIP, the linebreaks in the text files might be incompatible with your OS. This is particularly important if you plan to use the text file output image with a tool to write the firmware onto the Rocket. Some TI provided tools require windows-format linebreaks, whereas the Zip web download comes in UNIX-style. This can be worked around in two ways: - -- Fetch the source code using GIT running on your host OS, having it automatically change the formatting -- Manually change the linebreaks in the downloaded TXT file. +MSPBSL_USB_Tool +=============== + +This firmware is designed to allow USB to UART, I2C and SPI communication for the purpose of programming an MSP430/MSP432 Bootstrap Loader (BSL). It requires special hardware, described below. + +This firmware is based on the MSP430 CDC UART Bridge, which can be found in the USB developer package: http://www.ti.com/tool/msp430usbdevpack + +Hardware to run this firmware can be found here: https://www.olimex.com/Products/MSP430/BSL/MSP430-BSL/ + +Schematics are available here: https://www.olimex.com/Products/MSP430/BSL/MSP430-BSL/resources/MSP430-BSL_Rev_B.pdf + +Note: When downloading the firmware via ZIP, the linebreaks in the text files might be incompatible with your OS. This is particularly important if you plan to use the text file output image with a tool to write the firmware onto the Rocket. Some TI provided tools require windows-format linebreaks, whereas the Zip web download comes in UNIX-style. This can be worked around in two ways: + +- Fetch the source code using GIT running on your host OS, having it automatically change the formatting +- Manually change the linebreaks in the downloaded TXT file. diff --git a/USB_API/USB_CDC_API/UsbCdc.c b/USB_API/USB_CDC_API/UsbCdc.c deleted file mode 100644 index 537cf1e..0000000 --- a/USB_API/USB_CDC_API/UsbCdc.c +++ /dev/null @@ -1,1015 +0,0 @@ -/* - * UsbCdc.c - * - * CDC specific USB functions - * - * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/*----------------------------------------------------------------------------+ -| | -| Texas Instruments | -| | -| MSP430 USB-Example (CDC Driver) | -| | -+-----------------------------------------------------------------------------+ -| Source: UsbCdc.c, File Version 1.01 2009/12/03 | -| Author: RSTO | -| | -| WHO WHEN WHAT | -| --- ---------- ------------------------------------------------ | -| RSTO 2008/09/03 born | -| RSTO 2008/09/19 Changed USBCDC_sendData to send more then 64bytes| -| RSTO 2008/12/23 enhancements of CDC API | -| RSTO 2008/05/19 updated USBCDC_intfStatus() | -| RSTO 2009/05/26 added USBCDC_bytesInUSBBuffer() | -| RSTO 2009/05/28 changed USBCDC_sendData() | -| RSTO 2009/07/17 updated USBCDC_bytesInUSBBuffer() | -| RSTO 2009/10/21 move __disable_interrupt() before | -| checking for suspend | -| MSP,Biju 2009/12/28 Fix for the bug "Download speed is slow" | -+----------------------------------------------------------------------------*/ -#include - -#ifdef _CDC_ - - -#include "../USB_Common/device.h" -#include "../USB_Common/types.h" // Basic Type declarations -#include "../USB_Common/defMSP430USB.h" -#include "../USB_Common/usb.h" // USB-specific Data Structures -#include "../USB_CDC_API/UsbCdc.h" - -#include -#include "uart.h" -#include "baudrateselect.h" - -// Local Macros -#define INTFNUM_OFFSET(X) (X - CDC0_INTFNUM) // Get the CDC offset - -static struct _CdcParams -{ - ULONG lBaudrate; // holds baudrate - BYTE bDataBits; // holds Data Bits - BYTE bStopBits; // holds Stopa Bits - BYTE bParity; // holds Parity -}CdcParams[CDC_NUM_INTERFACES]; - -static struct _CdcWrite -{ - WORD nCdcBytesToSend; // holds counter of bytes to be sent - WORD nCdcBytesToSendLeft; // holds counter how many bytes is still to be sent - const BYTE* pUsbBufferToSend; // holds the buffer with data to be sent - BYTE bCurrentBufferXY; // is 0 if current buffer to write data is X, or 1 if current buffer is Y - BYTE bZeroPacketSent; // = FALSE; - BYTE last_ByteSend; -} CdcWriteCtrl[CDC_NUM_INTERFACES]; - -static struct _CdcRead -{ - BYTE *pUserBuffer; // holds the current position of user's receiving buffer. If NULL- no receiving operation started - BYTE *pCurrentEpPos; // current positon to read of received data from curent EP - WORD nBytesToReceive; // holds how many bytes was requested by receiveData() to receive - WORD nBytesToReceiveLeft; // holds how many bytes is still requested by receiveData() to receive - BYTE * pCT1; // holds current EPBCTxx register - BYTE * pCT2; // holds next EPBCTxx register - BYTE * pEP2; // holds addr of the next EP buffer - BYTE nBytesInEp; // how many received bytes still available in current EP - BYTE bCurrentBufferXY; // indicates which buffer is used by host to transmit data via OUT endpoint3 -} CdcReadCtrl[CDC_NUM_INTERFACES]; - -extern WORD wUsbEventMask; - -//function pointers -extern VOID *(*USB_TX_memcpy)(VOID * dest, const VOID * source, size_t count); -extern VOID *(*USB_RX_memcpy)(VOID * dest, const VOID * source, size_t count); - - -/*----------------------------------------------------------------------------+ -| Global Variables | -+----------------------------------------------------------------------------*/ - -extern __no_init tEDB __data16 tInputEndPointDescriptorBlock[]; -extern __no_init tEDB __data16 tOutputEndPointDescriptorBlock[]; - - -VOID CdcResetData() -{ - - // indicates which buffer is used by host to transmit data via OUT endpoint3 - X buffer is first - //CdcReadCtrl[intfIndex].bCurrentBufferXY = X_BUFFER; - - memset(&CdcWriteCtrl, 0, sizeof(CdcWriteCtrl)); - memset(&CdcReadCtrl, 0, sizeof(CdcReadCtrl)); - -} - -/* -Sends data over interface intfNum, of size size and starting at address data. -Returns: kUSBCDC_sendStarted - kUSBCDC_sendComplete - kUSBCDC_intfBusyError -*/ -BYTE USBCDC_sendData(const BYTE* data, WORD size, BYTE intfNum) -{ - BYTE edbIndex; - unsigned short bGIE; - - edbIndex= stUsbHandle[intfNum].edb_Index; - - if (size == 0) - { - return kUSBCDC_generalError; - } - - bGIE = (__get_SR_register() &GIE); //save interrupt status - // atomic operation - disable interrupts - __disable_interrupt(); // Disable global interrupts - - // do not access USB memory if suspended (PLL off). It may produce BUS_ERROR - if ((bFunctionSuspended) || - (bEnumerationStatus != ENUMERATION_COMPLETE)) - { - // data can not be read because of USB suspended - __bis_SR_register(bGIE); //restore interrupt status - return kUSBCDC_busNotAvailable; - } - - if (CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].nCdcBytesToSendLeft != 0) - { - // the USB still sends previous data, we have to wait - __bis_SR_register(bGIE); //restore interrupt status - return kUSBCDC_intfBusyError; - } - - //This function generate the USB interrupt. The data will be sent out from interrupt - - CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].nCdcBytesToSend = size; - CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].nCdcBytesToSendLeft = size; - CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].pUsbBufferToSend = data; - - //trigger Endpoint Interrupt - to start send operation - USBIEPIFG |= 1<<(edbIndex+1); //IEPIFGx; - - __bis_SR_register(bGIE); //restore interrupt status - - return kUSBCDC_sendStarted; -} - -#define EP_MAX_PACKET_SIZE_CDC 0x40 - -//this function is used only by USB interrupt -BOOL CdcToHostFromBuffer(BYTE intfNum) -{ - BYTE byte_count, nTmp2; - BYTE * pEP1; - BYTE * pEP2; - BYTE * pCT1; - BYTE * pCT2; - BYTE bWakeUp = FALSE; //TRUE for wake up after interrupt - BYTE edbIndex; - - edbIndex = stUsbHandle[intfNum].edb_Index; - - if (CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].nCdcBytesToSendLeft == 0) // do we have somtething to send? - { - if (!CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].bZeroPacketSent) // zero packet was not yet sent - { - CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].bZeroPacketSent = TRUE; - - if(CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].last_ByteSend == EP_MAX_PACKET_SIZE_CDC) - { - if (CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY == X_BUFFER) - { - tInputEndPointDescriptorBlock[edbIndex].bEPBCTX = 0; - } - else - { - tInputEndPointDescriptorBlock[edbIndex].bEPBCTY = 0; - } - CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY = (CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY+1)&0x01; //switch buffer - } - - CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].nCdcBytesToSend = 0; // nothing to send - - //call event callback function - if (wUsbEventMask & kUSB_sendCompletedEvent) - { - bWakeUp = USBCDC_handleSendCompleted(intfNum); - } - - } // if (!bSentZeroPacket) - - return bWakeUp; - } - - CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].bZeroPacketSent = FALSE; // zero packet will be not sent: we have data - - if (CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY == X_BUFFER) - { - //this is the active EP buffer - pEP1 = (BYTE*)stUsbHandle[intfNum].iep_X_Buffer; - pCT1 = &tInputEndPointDescriptorBlock[edbIndex].bEPBCTX; - - //second EP buffer - pEP2 = (BYTE*)stUsbHandle[intfNum].iep_Y_Buffer; - pCT2 = &tInputEndPointDescriptorBlock[edbIndex].bEPBCTY; - } - else - { - //this is the active EP buffer - pEP1 = (BYTE*)stUsbHandle[intfNum].iep_Y_Buffer; - pCT1 = &tInputEndPointDescriptorBlock[edbIndex].bEPBCTY; - - //second EP buffer - pEP2 = (BYTE*)stUsbHandle[intfNum].iep_X_Buffer; - pCT2 = &tInputEndPointDescriptorBlock[edbIndex].bEPBCTX; - } - - // how many byte we can send over one endpoint buffer - byte_count = (CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].nCdcBytesToSendLeft > EP_MAX_PACKET_SIZE_CDC) ? EP_MAX_PACKET_SIZE_CDC : CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].nCdcBytesToSendLeft; - nTmp2 = *pCT1; - - if(nTmp2 & EPBCNT_NAK) - { - USB_TX_memcpy(pEP1, CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].pUsbBufferToSend, byte_count); // copy data into IEP3 X or Y buffer - *pCT1 = byte_count; // Set counter for usb In-Transaction - CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY = (CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY+1)&0x01; //switch buffer - CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].nCdcBytesToSendLeft -= byte_count; - CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].pUsbBufferToSend += byte_count; // move buffer pointer - CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].last_ByteSend = byte_count; - - //try to send data over second buffer - nTmp2 = *pCT2; - if ((CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].nCdcBytesToSendLeft > 0) && // do we have more data to send? - (nTmp2 & EPBCNT_NAK)) // if the second buffer is free? - { - // how many byte we can send over one endpoint buffer - byte_count = (CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].nCdcBytesToSendLeft > EP_MAX_PACKET_SIZE_CDC) ? EP_MAX_PACKET_SIZE_CDC : CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].nCdcBytesToSendLeft; - - USB_TX_memcpy(pEP2, CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].pUsbBufferToSend, byte_count); // copy data into IEP3 X or Y buffer - *pCT2 = byte_count; // Set counter for usb In-Transaction - CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY = (CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY+1)&0x01; //switch buffer - CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].nCdcBytesToSendLeft -= byte_count; - CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].pUsbBufferToSend += byte_count; //move buffer pointer - CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].last_ByteSend = byte_count; - } - } - return bWakeUp; -} - -/* -Aborts an active send operation on interface intfNum. -Returns the number of bytes that were sent prior to the abort, in size. -*/ -BYTE USBCDC_abortSend(WORD* size, BYTE intfNum) -{ - unsigned short bGIE; - - bGIE = (__get_SR_register() &GIE); //save interrupt status - __disable_interrupt(); //disable interrupts - atomic operation - - *size = (CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].nCdcBytesToSend - CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].nCdcBytesToSendLeft); - CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].nCdcBytesToSend = 0; - CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].nCdcBytesToSendLeft = 0; - - __bis_SR_register(bGIE); //restore interrupt status - return kUSB_succeed; -} - -// This function copies data from OUT endpoint into user's buffer -// Arguments: -// pEP - pointer to EP to copy from -// pCT - pointer to pCT control reg -// -VOID CopyUsbToBuff(BYTE* pEP, BYTE* pCT, BYTE intfNum) -{ - BYTE nCount; - - // how many byte we can get from one endpoint buffer - nCount = (CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft > CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp) ? CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp : CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft; - - USB_RX_memcpy(CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer, pEP, nCount); // copy data from OEP3 X or Y buffer - CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft -= nCount; - CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer += nCount; // move buffer pointer - // to read rest of data next time from this place - - if (nCount == CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp) // all bytes are copied from receive buffer? - { - //switch current buffer - CdcReadCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY = (CdcReadCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY+1) &0x01; - - CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = 0; - - //clear NAK, EP ready to receive data - *pCT = 0x00; - } - else - { - CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp -= nCount; - CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCurrentEpPos = pEP + nCount; - } -} - -/* -Receives data over interface intfNum, of size size, into memory starting at address data. -Returns: - kUSBCDC_receiveStarted if the receiving process started. - kUSBCDC_receiveCompleted all requested date are received. - kUSBCDC_receiveInProgress previous receive opereation is in progress. The requested receive operation can be not started. - kUSBCDC_generalError error occurred. -*/ -BYTE USBCDC_receiveData(BYTE* data, WORD size, BYTE intfNum) -{ - BYTE nTmp1; - BYTE edbIndex; - unsigned short bGIE; - - edbIndex=stUsbHandle[intfNum].edb_Index; - - if ((size == 0) || // read size is 0 - (data == NULL)) - { - return kUSBCDC_generalError; - } - - bGIE = (__get_SR_register() &GIE); //save interrupt status - // atomic operation - disable interrupts - __disable_interrupt(); // Disable global interrupts - - // do not access USB memory if suspended (PLL off). It may produce BUS_ERROR - if ((bFunctionSuspended) || - (bEnumerationStatus != ENUMERATION_COMPLETE)) - { - // data can not be read because of USB suspended - __bis_SR_register(bGIE); //restore interrupt status - return kUSBCDC_busNotAvailable; - } - - if (CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer != NULL) // receive process already started - { - __bis_SR_register(bGIE); //restore interrupt status - return kUSBCDC_intfBusyError; - } - - CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceive = size; // bytes to receive - CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft = size; // left bytes to receive - CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer = data; // set user receive buffer - - //read rest of data from buffer, if any - if (CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp > 0) - { - // copy data from pEP-endpoint into User's buffer - CopyUsbToBuff(CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCurrentEpPos, CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1, intfNum); - - if (CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft == 0) // the Receive opereation is completed - { - CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer = NULL; // no more receiving pending - if (wUsbEventMask & kUSB_receiveCompletedEvent) - { - USBCDC_handleReceiveCompleted(intfNum); // call event handler in interrupt context - } - __bis_SR_register(bGIE); //restore interrupt status - return kUSBCDC_receiveCompleted; // receive completed - } - - // check other EP buffer for data - exchange pCT1 with pCT2 - if (CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 == &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX) - { - CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 = &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY; - CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCurrentEpPos = (BYTE*)stUsbHandle[intfNum].oep_Y_Buffer; - } - else - { - CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 = &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX; - CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCurrentEpPos = (BYTE*)stUsbHandle[intfNum].oep_X_Buffer; - } - - nTmp1 = *CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1; - //try read data from second buffer - if (nTmp1 & EPBCNT_NAK) // if the second buffer has received data? - { - nTmp1 = nTmp1 &0x7f; // clear NAK bit - CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = nTmp1; // holds how many valid bytes in the EP buffer - CopyUsbToBuff(CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCurrentEpPos, CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1, intfNum); - } - - if (CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft == 0) // the Receive opereation is completed - { - CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer = NULL; // no more receiving pending - if (wUsbEventMask & kUSB_receiveCompletedEvent) - { - USBCDC_handleReceiveCompleted(intfNum); // call event handler in interrupt context - } - __bis_SR_register(bGIE); //restore interrupt status - return kUSBCDC_receiveCompleted; // receive completed - } - } //read rest of data from buffer, if any - - //read 'fresh' data, if available - nTmp1 = 0; - if (CdcReadCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY == X_BUFFER) //this is current buffer - { - if (tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX & EPBCNT_NAK) //this buffer has a valid data packet - { - //this is the active EP buffer - //pEP1 - CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCurrentEpPos = (BYTE*)stUsbHandle[intfNum].oep_X_Buffer; - CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 = &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX; - - //second EP buffer - CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pEP2 = (BYTE*)stUsbHandle[intfNum].oep_Y_Buffer; - CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2 = &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY; - nTmp1 = 1; //indicate that data is available - } - } - else - {// Y_BUFFER - if (tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY & EPBCNT_NAK) - { - //this is the active EP buffer - CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCurrentEpPos = (BYTE*)stUsbHandle[intfNum].oep_Y_Buffer; - CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 = &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY; - - //second EP buffer - CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pEP2 = (BYTE*)stUsbHandle[intfNum].oep_X_Buffer; - CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2 = &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX; - nTmp1 = 1; //indicate that data is available - } - } - - if (nTmp1) - { - // how many byte we can get from one endpoint buffer - nTmp1 = *CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1; - while(nTmp1 == 0) - { - nTmp1 = *CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1; - } - - if(nTmp1 & EPBCNT_NAK) - { - nTmp1 = nTmp1 &0x7f; // clear NAK bit - CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = nTmp1; // holds how many valid bytes in the EP buffer - - CopyUsbToBuff(CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCurrentEpPos, CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1, intfNum); - - nTmp1 = *CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2; - //try read data from second buffer - if ((CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft > 0) && // do we have more data to send? - (nTmp1 & EPBCNT_NAK)) // if the second buffer has received data? - { - nTmp1 = nTmp1 &0x7f; // clear NAK bit - CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = nTmp1; // holds how many valid bytes in the EP buffer - CopyUsbToBuff(CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pEP2, CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2, intfNum); - CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 = CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2; - } - } - } - - if (CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft == 0) // the Receive opereation is completed - { - CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer = NULL; // no more receiving pending - if (wUsbEventMask & kUSB_receiveCompletedEvent) - { - USBCDC_handleReceiveCompleted(intfNum); // call event handler in interrupt context - } - __bis_SR_register(bGIE); //restore interrupt status - return kUSBCDC_receiveCompleted; - } - - //interrupts enable - __bis_SR_register(bGIE); //restore interrupt status - return kUSBCDC_receiveStarted; -} - - -//this function is used only by USB interrupt. -//It fills user receiving buffer with received data -BOOL CdcToBufferFromHost(BYTE intfNum) -{ - BYTE * pEP1; - BYTE nTmp1; - BYTE bWakeUp = FALSE; // per default we do not wake up after interrupt - - BYTE edbIndex; - edbIndex = stUsbHandle[intfNum].edb_Index; - - if (CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft == 0) // do we have somtething to receive? - { - CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer = NULL; // no more receiving pending - return bWakeUp; - } - - // No data to receive... - if (!((tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX | - tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY) - & 0x80)) - { - return bWakeUp; - } - - if (CdcReadCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY == X_BUFFER) //X is current buffer - { - //this is the active EP buffer - pEP1 = (BYTE*)stUsbHandle[intfNum].oep_X_Buffer; - CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 = &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX; - - //second EP buffer - CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pEP2 = (BYTE*)stUsbHandle[intfNum].oep_Y_Buffer; - CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2 = &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY; - } - else - { - //this is the active EP buffer - pEP1 = (BYTE*)stUsbHandle[intfNum].oep_Y_Buffer; - CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 = &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY; - - //second EP buffer - CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pEP2 = (BYTE*)stUsbHandle[intfNum].oep_X_Buffer; - CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2 = &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX; - } - - // how many byte we can get from one endpoint buffer - nTmp1 = *CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1; - - if(nTmp1 & EPBCNT_NAK) - { - nTmp1 = nTmp1 &0x7f; // clear NAK bit - CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = nTmp1; // holds how many valid bytes in the EP buffer - - CopyUsbToBuff(pEP1, CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1, intfNum); - - nTmp1 = *CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2; - //try read data from second buffer - if ((CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft > 0) && // do we have more data to send? - (nTmp1 & EPBCNT_NAK)) // if the second buffer has received data? - { - nTmp1 = nTmp1 &0x7f; // clear NAK bit - CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = nTmp1; // holds how many valid bytes in the EP buffer - CopyUsbToBuff(CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pEP2, CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2, intfNum); - CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 = CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2; - } - } - - if (CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft == 0) // the Receive opereation is completed - { - CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer = NULL; // no more receiving pending - if (wUsbEventMask & kUSB_receiveCompletedEvent) - { - bWakeUp = USBCDC_handleReceiveCompleted(intfNum); - } - - if (CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp) // Is not read data still available in the EP? - { - if (wUsbEventMask & kUSB_dataReceivedEvent) - { - bWakeUp = USBCDC_handleDataReceived(intfNum); - } - } - } - return bWakeUp; -} - -// helper for USB interrupt handler -BOOL CdcIsReceiveInProgress(BYTE intfNum) -{ - return (CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer != NULL); -} - - -/* -Aborts an active receive operation on interface intfNum. - Returns the number of bytes that were received and transferred - to the data location established for this receive operation. -*/ -BYTE USBCDC_abortReceive(WORD* size, BYTE intfNum) -{ - //interrupts disable - unsigned short bGIE; - - bGIE = (__get_SR_register() &GIE); //save interrupt status - // atomic operation - disable interrupts - __disable_interrupt(); // Disable global interrupts - - *size = 0; //set received bytes count to 0 - - //is receive operation underway? - if (CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer) - { - //how many bytes are already received? - *size = CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceive - CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft; - - CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = 0; - CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer = NULL; - CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft = 0; - } - - //restore interrupt status - __bis_SR_register(bGIE); //restore interrupt status - return kUSB_succeed; -} - -/* -This function rejects payload data that has been received from the host. -*/ -BYTE USBCDC_rejectData(BYTE intfNum) -{ - BYTE edbIndex; - unsigned short bGIE; - edbIndex = stUsbHandle[intfNum].edb_Index; - - bGIE = (__get_SR_register() &GIE); //save interrupt status - - // atomic operation - disable interrupts - __disable_interrupt(); // Disable global interrupts - - // do not access USB memory if suspended (PLL off). It may produce BUS_ERROR - if (bFunctionSuspended) - { - __bis_SR_register(bGIE); //restore interrupt status - return kUSBCDC_busNotAvailable; - } - - //Is receive operation underway? - // - do not flush buffers if any operation still active. - if (!CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer) - { - BYTE tmp1 = tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX & EPBCNT_NAK; - BYTE tmp2 = tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY & EPBCNT_NAK; - - if (tmp1 ^ tmp2) // switch current buffer if any and only ONE of buffers is full - { - //switch current buffer - CdcReadCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY = (CdcReadCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY+1) &0x01; - } - - tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX = 0; //flush buffer X - tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY = 0; //flush buffer Y - CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = 0; // indicates that no more data available in the EP - } - - __bis_SR_register(bGIE); //restore interrupt status - return kUSB_succeed; -} - -/* -This function indicates the status of the itnerface intfNum. - If a send operation is active for this interface, - the function also returns the number of bytes that have been transmitted to the host. - If a receiver operation is active for this interface, the function also returns - the number of bytes that have been received from the host and are waiting at the assigned address. - -returns kUSBCDC_waitingForSend (indicates that a call to USBCDC_SendData() - has been made, for which data transfer has not been completed) - -returns kUSBCDC_waitingForReceive (indicates that a receive operation - has been initiated, but not all data has yet been received) - -returns kUSBCDC_dataWaiting (indicates that data has been received - from the host, waiting in the USB receive buffers) -*/ -BYTE USBCDC_intfStatus(BYTE intfNum, WORD* bytesSent, WORD* bytesReceived) -{ - BYTE ret = 0; - unsigned short bGIE; - BYTE edbIndex; - - *bytesSent = 0; - *bytesReceived = 0; - - edbIndex = stUsbHandle[intfNum].edb_Index; - - bGIE = (__get_SR_register() &GIE); //save interrupt status - __disable_interrupt(); //disable interrupts - atomic operation - - // Is send operation underway? - if (CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].nCdcBytesToSendLeft != 0) - { - ret |= kUSBCDC_waitingForSend; - *bytesSent = CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].nCdcBytesToSend - CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].nCdcBytesToSendLeft; - } - - //Is receive operation underway? - if (CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer != NULL) - { - ret |= kUSBCDC_waitingForReceive; - *bytesReceived = CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceive - CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft; - } - else // receive operation not started - { - // do not access USB memory if suspended (PLL off). It may produce BUS_ERROR - if (!bFunctionSuspended) - { - if((tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX & EPBCNT_NAK) | //any of buffers has a valid data packet - (tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY & EPBCNT_NAK)) - { - ret |= kUSBCDC_dataWaiting; - } - } - } - - if ((bFunctionSuspended) || - (bEnumerationStatus != ENUMERATION_COMPLETE)) - { - // if suspended or not enumerated - report no other tasks pending - ret = kUSBCDC_busNotAvailable; - } - - //restore interrupt status - __bis_SR_register(bGIE); //restore interrupt status - - __no_operation(); - return ret; -} - -/* -Returns how many bytes are in the buffer are received and ready to be read. -*/ -BYTE USBCDC_bytesInUSBBuffer(BYTE intfNum) -{ - BYTE bTmp1 = 0; - unsigned short bGIE; - BYTE edbIndex; - edbIndex = stUsbHandle[intfNum].edb_Index; - - bGIE = (__get_SR_register() &GIE); //save interrupt status - // atomic operation - disable interrupts - __disable_interrupt(); // Disable global interrupts - - if ((bFunctionSuspended) || - (bEnumerationStatus != ENUMERATION_COMPLETE)) - { - __bis_SR_register(bGIE); //restore interrupt status - // if suspended or not enumerated - report 0 bytes available - return 0; - } - - if (CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp > 0) // If a RX operation is underway, part of data may was read of the OEP buffer - { - bTmp1 = CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp; - if (*CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2 & EPBCNT_NAK) // the next buffer has a valid data packet - { - bTmp1 += *CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2 & 0x7F; - } - } - else - { - if (tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX & EPBCNT_NAK) //this buffer has a valid data packet - { - bTmp1 = tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX & 0x7F; - } - if (tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY & EPBCNT_NAK) //this buffer has a valid data packet - { - bTmp1 += tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY & 0x7F; - } - } - - __bis_SR_register(bGIE); //restore interrupt status - return bTmp1; -} - - -//---------------------------------------------------------------------------- -// Line Coding Structure -// dwDTERate | 4 | Data terminal rate, in bits per second -// bCharFormat | 1 | Stop bits, 0 = 1 Stop bit, 1 = 1,5 Stop bits, 2 = 2 Stop bits -// bParityType | 1 | Parity, 0 = None, 1 = Odd, 2 = Even, 3= Mark, 4 = Space -// bDataBits | 1 | Data bits (5,6,7,8,16) -//---------------------------------------------------------------------------- -VOID usbGetLineCoding0(VOID) -{ - abUsbRequestReturnData[6] = CdcParams[CDC0_INTFNUM].bDataBits; // Data bits = 8 - abUsbRequestReturnData[5] = CdcParams[CDC0_INTFNUM].bParity; // No Parity - abUsbRequestReturnData[4] = CdcParams[CDC0_INTFNUM].bStopBits; // Stop bits = 1 - - abUsbRequestReturnData[3] = CdcParams[CDC0_INTFNUM].lBaudrate >> 24; - abUsbRequestReturnData[2] = CdcParams[CDC0_INTFNUM].lBaudrate >> 16; - abUsbRequestReturnData[1] = CdcParams[CDC0_INTFNUM].lBaudrate >> 8; - abUsbRequestReturnData[0] = CdcParams[CDC0_INTFNUM].lBaudrate; - - wBytesRemainingOnIEP0 = 0x07; // amount of data to be send over EP0 to host - usbSendDataPacketOnEP0((PBYTE)&abUsbRequestReturnData[0]); // send data to host -} - -#if CDC_NUM_INTERFACES >= 2 -//---------------------------------------------------------------------------- -VOID usbGetLineCoding1(VOID) -{ - abUsbRequestReturnData[6] = CdcParams[CDC1_INTFNUM].bDataBits; // Data bits = 8 - abUsbRequestReturnData[5] = CdcParams[CDC1_INTFNUM].bParity; // No Parity - abUsbRequestReturnData[4] = CdcParams[CDC1_INTFNUM].bStopBits; // Stop bits = 1 - - abUsbRequestReturnData[3] = CdcParams[CDC1_INTFNUM].lBaudrate >> 24; - abUsbRequestReturnData[2] = CdcParams[CDC1_INTFNUM].lBaudrate >> 16; - abUsbRequestReturnData[1] = CdcParams[CDC1_INTFNUM].lBaudrate >> 8; - abUsbRequestReturnData[0] = CdcParams[CDC1_INTFNUM].lBaudrate; - - wBytesRemainingOnIEP0 = 0x07; // amount of data to be send over EP0 to host - usbSendDataPacketOnEP0((PBYTE)&abUsbRequestReturnData[0]); // send data to host -} -#endif - -#if CDC_NUM_INTERFACES >= 3 -//---------------------------------------------------------------------------- -VOID usbGetLineCoding2(VOID) -{ - abUsbRequestReturnData[6] = CdcParams[CDC2_INTFNUM].bDataBits; // Data bits = 8 - abUsbRequestReturnData[5] = CdcParams[CDC2_INTFNUM].bParity; // No Parity - abUsbRequestReturnData[4] = CdcParams[CDC2_INTFNUM].bStopBits; // Stop bits = 1 - - abUsbRequestReturnData[3] = CdcParams[CDC2_INTFNUM].lBaudrate >> 24; - abUsbRequestReturnData[2] = CdcParams[CDC2_INTFNUM].lBaudrate >> 16; - abUsbRequestReturnData[1] = CdcParams[CDC2_INTFNUM].lBaudrate >> 8; - abUsbRequestReturnData[0] = CdcParams[CDC2_INTFNUM].lBaudrate; - - wBytesRemainingOnIEP0 = 0x07; // amount of data to be send over EP0 to host - usbSendDataPacketOnEP0((PBYTE)&abUsbRequestReturnData[0]); // send data to host -} -#endif -//---------------------------------------------------------------------------- - -VOID usbSetLineCoding0(VOID) -{ - usbReceiveDataPacketOnEP0((PBYTE) &abUsbRequestIncomingData); // receive data over EP0 from Host -} - -//---------------------------------------------------------------------------- -#if CDC_NUM_INTERFACES >= 2 -VOID usbSetLineCoding1(VOID) -{ - usbReceiveDataPacketOnEP0((PBYTE) &abUsbRequestIncomingData); // receive data over EP0 from Host -} -#endif -//---------------------------------------------------------------------------- -#if CDC_NUM_INTERFACES >= 3 -VOID usbSetLineCoding2(VOID) -{ - usbReceiveDataPacketOnEP0((PBYTE) &abUsbRequestIncomingData); // receive data over EP0 from Host -} -#endif -//---------------------------------------------------------------------------- -#define SET_DTR0 P4OUT |= 0x08 -#define CLR_DTR0 P4OUT &= ~0x08 -#define CLR_RTS0 {P4OUT |= 0x04 ;P2OUT &= ~0x01;} -#define SET_RTS0 {P4OUT &= ~0x04;P2OUT |= 0x01;} - -VOID usbSetControlLineState0(VOID) -{ -#ifdef UART_BASED - if ((tSetupPacket.wValue & 0x03) == 0x03) - { - CLR_RTS0; - SET_RTS0; - CLR_RTS0; - SET_DTR0; - __delay_cycles(50); - SET_RTS0; - } - else - { - SET_RTS0; - CLR_DTR0; - __delay_cycles(50); - } -#endif - usbSendZeroLengthPacketOnIEP0(); // Send ZLP for status stage -} -#if CDC_NUM_INTERFACES >= 2 -VOID usbSetControlLineState1(VOID) -{ - if (tSetupPacket.wValue & 0x01) - {SET_DTR1;} - else - {CLR_DTR1;} - if (tSetupPacket.wValue & 0x02) - {SET_RTS1;} - else - {CLR_RTS1;} - usbSendZeroLengthPacketOnIEP0(); // Send ZLP for status stage -} -#endif -#if CDC_NUM_INTERFACES >= 3 -VOID usbSetControlLineState2(VOID) -{ - if (tSetupPacket.wValue & 0x01) - SET_DTR2; - else - CLR_DTR2; - if (tSetupPacket.wValue & 0x02) - SET_RTS2; - else - CLR_RTS2; - usbSendZeroLengthPacketOnIEP0(); // Send ZLP for status stage -} -#endif -//---------------------------------------------------------------------------- - -VOID Handler_SetLineCoding0(VOID) -{ - // Baudrate Settings - CdcParams[CDC0_INTFNUM].lBaudrate = (ULONG)abUsbRequestIncomingData[3] << 24 | - (ULONG)abUsbRequestIncomingData[2]<<16 | (ULONG)abUsbRequestIncomingData[1]<<8 | - abUsbRequestIncomingData[0]; - - // Stop bits - CdcParams[CDC0_INTFNUM].bStopBits = abUsbRequestIncomingData[4]; - // Parit - CdcParams[CDC0_INTFNUM].bParity = abUsbRequestIncomingData[5]; - // Data bits - CdcParams[CDC0_INTFNUM].bDataBits = abUsbRequestIncomingData[6]; - #ifdef UART0_INTFNUM - if(!InitUart0(CdcParams[CDC0_INTFNUM].lBaudrate)) - CdcParams[CDC0_INTFNUM].lBaudrate = 0; - #elif defined (I2C_BASED) - if (!BaudrateSelect(CdcParams[CDC0_INTFNUM].lBaudrate)) - CdcParams[CDC0_INTFNUM].lBaudrate = 0; - #else - CdcParams[CDC0_INTFNUM].lBaudrate = 0; - #endif -} - -//---------------------------------------------------------------------------- -VOID Handler_SetLineCoding1(VOID) -{ -#if CDC_NUM_INTERFACES >= 2 - // Baudrate Settings - CdcParams[CDC1_INTFNUM].lBaudrate = (ULONG)abUsbRequestIncomingData[3] << 24 | - (ULONG)abUsbRequestIncomingData[2]<<16 | (ULONG)abUsbRequestIncomingData[1]<<8 | - abUsbRequestIncomingData[0]; - - // Stop bits - CdcParams[CDC1_INTFNUM].bStopBits = abUsbRequestIncomingData[4]; - // Parit - CdcParams[CDC1_INTFNUM].bParity = abUsbRequestIncomingData[5]; - // Data bits - CdcParams[CDC1_INTFNUM].bDataBits = abUsbRequestIncomingData[6]; - - #ifdef UART1_INTFNUM - if(!InitUart1(CdcParams[CDC1_INTFNUM].lBaudrate)) - CdcParams[CDC1_INTFNUM].lBaudrate = 0; - #else - CdcParams[CDC1_INTFNUM].lBaudrate = 0; - #endif -#endif -} -//---------------------------------------------------------------------------- -VOID Handler_SetLineCoding2(VOID) -{ -#if CDC_NUM_INTERFACES >= 3 - // Baudrate Settings - CdcParams[CDC2_INTFNUM].lBaudrate = (ULONG)abUsbRequestIncomingData[3] << 24 | - (ULONG)abUsbRequestIncomingData[2]<<16 |(ULONG)abUsbRequestIncomingData[1]<<8 | - abUsbRequestIncomingData[0]; - - // Stop bits - CdcParams[CDC2_INTFNUM].bStopBits = abUsbRequestIncomingData[4]; - // Parit - CdcParams[CDC2_INTFNUM].bParity = abUsbRequestIncomingData[5]; - // Data bits - CdcParams[CDC2_INTFNUM].bDataBits = abUsbRequestIncomingData[6]; - - #ifdef UART1_INTFNUM - if(!InitUart1(CdcParams[CDC2_INTFNUM].lBaudrate)) - CdcParams[CDC2_INTFNUM].lBaudrate = 0; - #else - CdcParams[CDC2_INTFNUM].lBaudrate = 0; - #endif -#endif -} -#endif //ifdef _CDC_ - -/*----------------------------------------------------------------------------+ -| End of source file | -+----------------------------------------------------------------------------*/ -/*------------------------ Nothing Below This Line --------------------------*/ diff --git a/USB_API/USB_CDC_API/UsbCdc.h b/USB_API/USB_CDC_API/UsbCdc.h deleted file mode 100644 index c9fe4d7..0000000 --- a/USB_API/USB_CDC_API/UsbCdc.h +++ /dev/null @@ -1,203 +0,0 @@ -/* - * UsbCdc.h - * - * CDC specific USB functions - * - * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/*----------------------------------------------------------------------------+ -| | -| Texas Instruments | -| | -| MSP430 USB-Example (CDC Driver) | -| | -+-----------------------------------------------------------------------------+ -| Source: UsbCdc.h, File Version 1.00 2009/12/03 | -| Author: RSTO | -| | -| WHO WHEN WHAT | -| --- ---------- ------------------------------------------------ | -| RSTO 2008/09/03 born | -| RSTO 2008/12/23 enhancements of CDC API | -| RSTO 2009/05/15 added param to USBCDC_rejectData() | -| RSTO 2009/05/26 added USBCDC_bytesInUSBBuffer() | -| MSP,Biju 2009/12/03 file versioning started | -| | -+----------------------------------------------------------------------------*/ -#ifndef _UsbCdc_H_ -#define _UsbCdc_H_ - -#ifdef __cplusplus -extern "C" -{ -#endif - - -#define kUSBCDC_sendStarted 0x01 -#define kUSBCDC_sendComplete 0x02 -#define kUSBCDC_intfBusyError 0x03 -#define kUSBCDC_receiveStarted 0x04 -#define kUSBCDC_receiveCompleted 0x05 -#define kUSBCDC_receiveInProgress 0x06 -#define kUSBCDC_generalError 0x07 -#define kUSBCDC_busNotAvailable 0x08 - - -/*---------------------------------------------------------------------------- -These functions can be used in application -+----------------------------------------------------------------------------*/ - -/* -Sends data over interface intfNum, of size size and starting at address data. - Returns: kUSBCDC_sendStarted - kUSBCDC_sendComplete - kUSBCDC_intfBusyError -*/ -BYTE USBCDC_sendData(const BYTE* data, WORD size, BYTE intfNum); - -/* -Receives data over interface intfNum, of size size, into memory starting at address data. -*/ -BYTE USBCDC_receiveData(BYTE* data, WORD size, BYTE intfNum); - -/* -Aborts an active receive operation on interface intfNum. - size: the number of bytes that were received and transferred - to the data location established for this receive operation. -*/ -BYTE USBCDC_abortReceive(WORD* size, BYTE intfNum); - - -#define kUSBCDC_noDataWaiting 1 //returned by USBCDC_rejectData() if no data pending - -/* -This function rejects payload data that has been received from the host. -*/ -BYTE USBCDC_rejectData(BYTE intfNum); - -/* -Aborts an active send operation on interface intfNum. Returns the number of bytes that were sent prior to the abort, in size. -*/ -BYTE USBCDC_abortSend(WORD* size, BYTE intfNum); - - -#define kUSBCDC_waitingForSend 0x01 -#define kUSBCDC_waitingForReceive 0x02 -#define kUSBCDC_dataWaiting 0x04 -#define kUSBCDC_busNotAvailable 0x08 -#define kUSB_allCdcEvents 0xFF - -/* -This function indicates the status of the interface intfNum. - If a send operation is active for this interface, - the function also returns the number of bytes that have been transmitted to the host. - If a receiver operation is active for this interface, the function also returns - the number of bytes that have been received from the host and are waiting at the assigned address. - -returns kUSBCDC_waitingForSend (indicates that a call to USBCDC_SendData() - has been made, for which data transfer has not been completed) - -returns kUSBCDC_waitingForReceive (indicates that a receive operation - has been initiated, but not all data has yet been received) - -returns kUSBCDC_dataWaiting (indicates that data has been received - from the host, waiting in the USB receive buffers) -*/ -BYTE USBCDC_intfStatus(BYTE intfNum, WORD* bytesSent, WORD* bytesReceived); - -/* -Returns how many bytes are in the buffer are received and ready to be read. -*/ -BYTE USBCDC_bytesInUSBBuffer(BYTE intfNum); - - -/*---------------------------------------------------------------------------- -Event-Handling routines -+----------------------------------------------------------------------------*/ - -/* -This event indicates that data has been received for interface intfNum, but no data receive operation is underway. -returns TRUE to keep CPU awake -*/ -BYTE USBCDC_handleDataReceived(BYTE intfNum); - -/* -This event indicates that a send operation on interface intfNum has just been completed. -returns TRUE to keep CPU awake -*/ -BYTE USBCDC_handleSendCompleted(BYTE intfNum); - -/* -This event indicates that a receive operation on interface intfNum has just been completed. -returns TRUE to keep CPU awake -*/ -BYTE USBCDC_handleReceiveCompleted(BYTE intfNum); - - -/*---------------------------------------------------------------------------- -These functions is to be used ONLY by USB stack, and not by application -+----------------------------------------------------------------------------*/ - -/** -Send a packet with the settings of the second uart back to the usb host -*/ -VOID usbGetLineCoding0(VOID); -VOID usbGetLineCoding1(VOID); -VOID usbGetLineCoding2(VOID); - -/** -Prepare EP0 to receive a packet with the settings for the second uart -*/ -VOID usbSetLineCoding0(VOID); -VOID usbSetLineCoding1(VOID); -VOID usbSetLineCoding2(VOID); - -/** -Function set or reset RTS -*/ -VOID usbSetControlLineState0(VOID); -VOID usbSetControlLineState1(VOID); -VOID usbSetControlLineState2(VOID); - -/** -Readout the settings (send from usb host) for the second uart -*/ -VOID Handler_SetLineCoding0(VOID); -VOID Handler_SetLineCoding1(VOID); -VOID Handler_SetLineCoding2(VOID); - -#ifdef __cplusplus -} -#endif -#endif //_UsbCdc_H_ diff --git a/USB_API/USB_Common/UsbIsr.h b/USB_API/USB_Common/UsbIsr.h deleted file mode 100644 index ad1bf66..0000000 --- a/USB_API/USB_Common/UsbIsr.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * UsbIsr.h - * - * USB ISR routines - * - * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/*----------------------------------------------------------------------------+ -| | -| Texas Instruments | -| | -| MSP430 USB-Example (CDC/HID Driver) | -| | -+-----------------------------------------------------------------------------+ -| Source: UsbIsr.h, File Version 1.00 2009/12/03 | -| Author: RSTO | -| | -| WHO WHEN WHAT | -| --- ---------- ------------------------------------------------ | -| RSTO 2008/09/03 born | -| RSTO 2008/12/23 enhancements of CDC API | -+----------------------------------------------------------------------------*/ - -#ifndef _ISR_H_ -#define _ISR_H_ - -#ifdef __cplusplus -extern "C" -{ -#endif - -/** -Handle incoming setup packet. -returns TRUE to keep CPU awake -*/ -BYTE SetupPacketInterruptHandler(VOID); - -/** -Handle VBuss on signal. -*/ -VOID PWRVBUSonHandler(VOID); - -/** -Handle VBuss off signal. -*/ -VOID PWRVBUSoffHandler(VOID); - -/** -Handle In-requests from control pipe. -*/ -VOID IEP0InterruptHandler(VOID); - -/** -Handle Out-requests from control pipe. -*/ -VOID OEP0InterruptHandler(VOID); - -/*----------------------------------------------------------------------------+ -| End of header file | -+----------------------------------------------------------------------------*/ - -#ifdef __cplusplus -} -#endif -#endif /* _ISR_H_ */ - -/*------------------------ Nothing Below This Line --------------------------*/ diff --git a/USB_API/USB_Common/defMSP430USB.h b/USB_API/USB_Common/defMSP430USB.h deleted file mode 100644 index e3364f7..0000000 --- a/USB_API/USB_Common/defMSP430USB.h +++ /dev/null @@ -1,210 +0,0 @@ -/* - * defMSP430USB.h - * - * Contains USB Constants, Type Definitions & Macros - * - * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/*----------------------------------------------------------------------------+ -| | -| Texas Instruments | -| | -| MSP430 USB-Example (CDC/HID Driver) | -| | -+-----------------------------------------------------------------------------+ -| Source: defMSP430USB.h, File Version 1.00 2009/12/03 | -| Author: RSTO | -| | -| Description: | -| Contains USB Constants, Type Definitions & Macros | -| | -| WHO WHEN WHAT | -| --- ---------- ------------------------------------------------ | -| RSTO 2008/09/03 born | -| MSP,Biju 2009/10/21 Changes for composite support | -| MSP,Biju 2009/12/03 file versioning started | -+----------------------------------------------------------------------------*/ - -#ifndef _defMSP430USB_H -#define _defMSP430USB_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -/*----------------------------------------------------------------------------+ -| Constant Definitions | -+----------------------------------------------------------------------------*/ -#define YES 1 -#define NO 0 - -#define TRUE 1 -#define FALSE 0 - -#define NOERR 0 -#define ERR 1 - -#define NO_ERROR 0 -#define ERROR 1 - -#define DISABLE 0 -#define ENABLE 1 - - -/*----------------------------------------------------------------------------+ -| USB Constants, Type Definition & Macro | -+----------------------------------------------------------------------------*/ - -// USB related Constant -#define MAX_ENDPOINT_NUMBER 0x07 // A maximum of 7 endpoints is available -#define EP0_MAX_PACKET_SIZE 0x08 -#define EP0_PACKET_SIZE 0x08 -#define EP_MAX_PACKET_SIZE 0x40 - -// Base addresses of transmit and receive buffers -#define OEP1_X_BUFFER_ADDRESS 0x1C00 // Input Endpoint 1 X Buffer Base-address -#define OEP1_Y_BUFFER_ADDRESS 0x1C40 // Input Endpoint 1 Y Buffer Base-address -#define IEP1_X_BUFFER_ADDRESS 0x1C80 // Output Endpoint 1 X Buffer Base-address -#define IEP1_Y_BUFFER_ADDRESS 0x1CC0 // Output Endpoint 1 Y Buffer Base-address - -#define OEP2_X_BUFFER_ADDRESS 0x1D00 // Input Endpoint 2 X Buffer Base-address -#define OEP2_Y_BUFFER_ADDRESS 0x1D40 // Input Endpoint 2 Y Buffer Base-address -#define IEP2_X_BUFFER_ADDRESS 0x1D80 // Output Endpoint 2 X Buffer Base-address -#define IEP2_Y_BUFFER_ADDRESS 0x1DC0 // Output Endpoint 2 Y Buffer Base-address - -#define OEP3_X_BUFFER_ADDRESS 0x1E00 // Input Endpoint 2 X Buffer Base-address -#define OEP3_Y_BUFFER_ADDRESS 0x1E40 // Input Endpoint 2 Y Buffer Base-address -#define IEP3_X_BUFFER_ADDRESS 0x1E80 // Output Endpoint 2 X Buffer Base-address -#define IEP3_Y_BUFFER_ADDRESS 0x1EC0 // Output Endpoint 2 Y Buffer Base-address - -#define OEP4_X_BUFFER_ADDRESS 0x1F00 // Input Endpoint 2 X Buffer Base-address -#define OEP4_Y_BUFFER_ADDRESS 0x1F40 // Input Endpoint 2 Y Buffer Base-address -#define IEP4_X_BUFFER_ADDRESS 0x1F80 // Output Endpoint 2 X Buffer Base-address -#define IEP4_Y_BUFFER_ADDRESS 0x1FC0 // Output Endpoint 2 Y Buffer Base-address - -#define OEP5_X_BUFFER_ADDRESS 0x2000 // Input Endpoint 2 X Buffer Base-address -#define OEP5_Y_BUFFER_ADDRESS 0x2040 // Input Endpoint 2 Y Buffer Base-address -#define IEP5_X_BUFFER_ADDRESS 0x2080 // Output Endpoint 2 X Buffer Base-address -#define IEP5_Y_BUFFER_ADDRESS 0x20C0 // Output Endpoint 2 Y Buffer Base-address - -#define OEP6_X_BUFFER_ADDRESS 0x2100 // Input Endpoint 2 X Buffer Base-address -#define OEP6_Y_BUFFER_ADDRESS 0x2140 // Input Endpoint 2 Y Buffer Base-address -#define IEP6_X_BUFFER_ADDRESS 0x2180 // Output Endpoint 2 X Buffer Base-address -#define IEP6_Y_BUFFER_ADDRESS 0x21C0 // Output Endpoint 2 Y Buffer Base-address - -#define OEP7_X_BUFFER_ADDRESS 0x2200 // Input Endpoint 2 X Buffer Base-address -#define OEP7_Y_BUFFER_ADDRESS 0x2240 // Input Endpoint 2 Y Buffer Base-address -#define IEP7_X_BUFFER_ADDRESS 0x2280 // Output Endpoint 2 X Buffer Base-address -#define IEP7_Y_BUFFER_ADDRESS 0x22C0 // Output Endpoint 2 Y Buffer Base-address - -#define X_BUFFER 0 -#define Y_BUFFER 1 - -//Macros for end point numbers -#define EP1 1 -#define EP2 2 -#define EP3 3 -#define EP4 4 -#define EP5 5 -#define EP6 6 -#define EP7 7 - -// addresses of pipes for endpoints -#define EP1_OUT_ADDR 0x01 //address for endpoint 1 -#define EP2_OUT_ADDR 0x02 //address for endpoint 2 -#define EP3_OUT_ADDR 0x03 //address for endpoint 3 -#define EP4_OUT_ADDR 0x04 //address for endpoint 4 -#define EP5_OUT_ADDR 0x05 //address for endpoint 5 -#define EP6_OUT_ADDR 0x06 //address for endpoint 6 -#define EP7_OUT_ADDR 0x07 //address for endpoint 7 - -//Input end points -#define EP1_IN_ADDR 0x81 //address for endpoint 1 -#define EP2_IN_ADDR 0x82 //address for endpoint 2 -#define EP3_IN_ADDR 0x83 //address for endpoint 3 -#define EP4_IN_ADDR 0x84 //address for endpoint 4 -#define EP5_IN_ADDR 0x85 //address for endpoint 5 -#define EP6_IN_ADDR 0x86 //address for endpoint 6 -#define EP7_IN_ADDR 0x87 //address for endpoint 7 - - -// EDB Data Structure -typedef struct _tEDB -{ - BYTE bEPCNF; // Endpoint Configuration - BYTE bEPBBAX; // Endpoint X Buffer Base Address - BYTE bEPBCTX; // Endpoint X Buffer byte Count - BYTE bSPARE0; // no used - BYTE bSPARE1; // no used - BYTE bEPBBAY; // Endpoint Y Buffer Base Address - BYTE bEPBCTY; // Endpoint Y Buffer byte Count - BYTE bEPSIZXY; // Endpoint XY Buffer Size -} tEDB, *tpEDB; - -typedef struct _tEDB0 -{ - BYTE bIEPCNFG; // Input Endpoint 0 Configuration Register - BYTE bIEPBCNT; // Input Endpoint 0 Buffer Byte Count - BYTE bOEPCNFG; // Output Endpoint 0 Configuration Register - BYTE bOEPBCNT; // Output Endpoint 0 Buffer Byte Count -} tEDB0, *tpEDB0; - -// EndPoint Desciptor Block Bits -#define EPCNF_USBIE 0x04 // USB Interrupt on Transaction Completion. Set By MCU - // 0:No Interrupt, 1:Interrupt on completion -#define EPCNF_STALL 0x08 // USB Stall Condition Indication. Set by UBM - // 0: No Stall, 1:USB Install Condition -#define EPCNF_DBUF 0x10 // Double Buffer Enable. Set by MCU - // 0: Primary Buffer Only(x-buffer only), 1:Toggle Bit Selects Buffer - -#define EPCNF_TOGGLE 0x20 // USB Toggle bit. This bit reflects the toggle sequence bit of DATA0 and DATA1. - -#define EPCNF_UBME 0x80 // UBM Enable or Disable bit. Set or Clear by MCU. - // 0:UBM can't use this endpoint - // 1:UBM can use this endpoint -#define EPBCNT_BYTECNT_MASK 0x7F // MASK for Buffer Byte Count -#define EPBCNT_NAK 0x80 // NAK, 0:No Valid in buffer, 1:Valid packet in buffer - -//definitions for MSP430 USB-module -#define START_OF_USB_BUFFER 0x1C00 - -// input and output buffers for EP0 -#define USBIEP0BUF 0x2378 -#define USBOEP0BUF 0x2370 - -#ifdef __cplusplus -} -#endif -#endif /*_defMSP430USB_H */ diff --git a/USB_API/USB_Common/device.h b/USB_API/USB_Common/device.h deleted file mode 100644 index 498e025..0000000 --- a/USB_API/USB_Common/device.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * device.h - * - * Device family definitions - * - * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/*----------------------------------------------------------------------------+ -| | -| Texas Instruments | -| | -| MSP430 USB-Example (CDC/HID Driver) | -| | -+-----------------------------------------------------------------------------+ -| Source: device.h, File Version 1.00 2009/12/03 | -| Author: RSTO | -| | -| Description: | -| This file is included in other source code files | -| and this only one place to change the included device header | -+----------------------------------------------------------------------------*/ - - -#include - -#if defined (__MSP430F6638__) || defined (__MSP430F6637__) || defined (__MSP430F6636__) || \ - defined (__MSP430F6635__) || defined (__MSP430F6634__) || defined (__MSP430F6633__) || \ - defined (__MSP430F6632__) || defined (__MSP430F6631__) || defined (__MSP430F6630__) || \ - defined (__MSP430F5638__) || defined (__MSP430F5637__) || defined (__MSP430F5636__) || \ - defined (__MSP430F5635__) || defined (__MSP430F5634__) || defined (__MSP430F5633__) || \ - defined (__MSP430F5632__) || defined (__MSP430F5631__) || defined (__MSP430F5630__) - #define __MSP430F563x_F663x -#elif defined (__MSP430F5510__) || defined (__MSP430F5509__) || defined (__MSP430F5508__) || \ - defined (__MSP430F5507__) || defined (__MSP430F5506__) || defined (__MSP430F5505__) || \ - defined (__MSP430F5504__) || defined (__MSP430F5503__) || defined (__MSP430F5502__) || \ - defined (__MSP430F5501__) || defined (__MSP430F5500__) - #define __MSP430F550x -#elif defined (__MSP430F5529) || defined (__MSP430F5528__) || defined (__MSP430F5527__) || \ - defined (__MSP430F5526__) || defined (__MSP430F5525__) || defined (__MSP430F5524__) || \ - defined (__MSP430F5522__) || defined (__MSP430F5521__) || defined (__MSP430F5519__) || \ - defined (__MSP430F5517__) || defined (__MSP430F5515__) || defined (__MSP430F5514__) || \ - defined (__MSP430F5513__) - #define __MSP430F552x -#else - #error Define a constant of format __MSP430Fxxxx__ within the projects preprocessor settings, - according to the device being used. -#endif -/*------------------------ Nothing Below This Line --------------------------*/ diff --git a/USB_API/USB_Common/dma.c b/USB_API/USB_Common/dma.c deleted file mode 100644 index 3f9c8d0..0000000 --- a/USB_API/USB_Common/dma.c +++ /dev/null @@ -1,213 +0,0 @@ -/* - * dma.c - * - * DMA transfer functions - * - * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/*----------------------------------------------------------------------------+ -| | -| Texas Instruments | -| | -| MSP430 USB-Example (HID/CDC Driver) | -| | -+-----------------------------------------------------------------------------+ -| Source: dma.c, File Version 1.02 2009/12/03 | -| Author: RSTO | -| | -| WHO WHEN WHAT | -| --- ---------- ------------------------------------------------ | -| RSTO 2009/03/03 born | -| RSTO 2009/04/08 Redefine memcpy() | -| RSTO 2009/04/16 use 16 bit access to DMA regs | -| RSTO 2009/09/18 fixed trigger selection for DMA with bit set | -| RSTO 2009/11/03 do not transfer via DMA if length is zero | -| MSP,Biju 2009/12/03 Review comments addressed, file versioning | -| started | -| RSTO 2010/01/08 added support for large mem model | -+----------------------------------------------------------------------------*/ - -#include "../USB_Common/device.h" -#include "../USB_Common/types.h" // Basic Type declarations -#include "../USB_Common/defMSP430USB.h" -#include -#include - -#ifdef __REGISTER_MODEL__ -/* for IAR */ -# if __REGISTER_MODEL__ == __REGISTER_MODEL_REG20__ -# define __DMA_ACCESS_REG__ (void __data20 *) -# else -# define __DMA_ACCESS_REG__ (unsigned short) -# endif -#else -/* for CCS */ -# define __DMA_ACCESS_REG__ (__SFR_FARPTR)(unsigned long) -#endif - -//function pointers -VOID *(*USB_TX_memcpy)(VOID * dest, const VOID * source, size_t count); -VOID *(*USB_RX_memcpy)(VOID * dest, const VOID * source, size_t count); - -VOID * memcpyDMA0(VOID * dest, const VOID * source, size_t count); -VOID * memcpyDMA1(VOID * dest, const VOID * source, size_t count); -VOID * memcpyDMA2(VOID * dest, const VOID * source, size_t count); - -// NOTE: this functin works only with data in the area <64k (small memory model) -VOID * memcpyV(VOID * dest, const VOID * source, size_t count) -{ - WORD i; - volatile BYTE bTmp; - for (i=0; i - -#include -#include -#include - -/*----------------------------------------------------------------------------+ - | Internal Constant Definition | - +----------------------------------------------------------------------------*/ -#define NO_MORE_DATA 0xFFFF -#define EPBCT_NAK 0x80 -#define EPCNF_TOGLE 0x20 - -#define DIRECTION_IN 0x80 -#define DIRECTION_OUT 0x00 - -/*----------------------------------------------------------------------------+ -| Internal Variables | -+----------------------------------------------------------------------------*/ - -static BYTE bConfigurationNumber; // Set to 1 when USB device has been - // configured, set to 0 when unconfigured - -static BYTE bInterfaceNumber; // interface number - -WORD wBytesRemainingOnIEP0; // For endpoint zero transmitter only - // Holds count of bytes remaining to be - // transmitted by endpoint 0. A value - // of 0 means that a 0-length data packet - // A value of 0xFFFF means that transfer - // is complete. - -WORD wBytesRemainingOnOEP0; // For endpoint zero transmitter only - // Holds count of bytes remaining to be - // received by endpoint 0. A value - // of 0 means that a 0-length data packet - // A value of 0xFFFF means that transfer - // is complete. - -static PBYTE pbIEP0Buffer; // A buffer pointer to input end point 0 - // Data sent back to host is copied from - // this pointed memory location - -static PBYTE pbOEP0Buffer; // A buffer pointer to output end point 0 - // Data sent from host is copied to - // this pointed memory location - -static BYTE bHostAskMoreDataThanAvailable=0; - -BYTE abUsbRequestReturnData[USB_RETURN_DATA_LENGTH]; -BYTE abUsbRequestIncomingData[USB_RETURN_DATA_LENGTH]; - -__no_init BYTE abramSerialStringDescriptor[34]; - -BYTE bStatusAction; -BYTE bFunctionSuspended=FALSE; // TRUE if function is suspended -BYTE bEnumerationStatus = 0; //is 0 if not enumerated - -static BYTE bRemoteWakeup; - -WORD wUsbEventMask; //used by USB_getEnabledEvents() and USB_setEnabledEvents() - -#ifdef _MSC_ -extern void USBMSC_reset(void); -void MscResetData(); -extern BOOL bMcsCommandSupported; -extern BOOL isMSCConfigured; - -extern BYTE bMscResetRequired; -#endif - -/*----------------------------------------------------------------------------+ -| Global Variables | -+----------------------------------------------------------------------------*/ -/*----------------------------------------------------------------------------+ -| Hardware Related Structure Definition | -+----------------------------------------------------------------------------*/ - -#ifdef __IAR_SYSTEMS_ICC__ - -#pragma location = 0x2380 -__no_init tDEVICE_REQUEST __data16 tSetupPacket; - -#pragma location = 0x0920 -__no_init tEDB0 __data16 tEndPoint0DescriptorBlock; - -#pragma location = 0x23C8 -__no_init tEDB __data16 tInputEndPointDescriptorBlock[7]; - -#pragma location = 0x2388 -__no_init tEDB __data16 tOutputEndPointDescriptorBlock[7]; - -#pragma location = 0x2378 -__no_init BYTE __data16 abIEP0Buffer[EP0_MAX_PACKET_SIZE]; - -#pragma location = 0x2370 -__no_init BYTE __data16 abOEP0Buffer[EP0_MAX_PACKET_SIZE]; - -#pragma location = OEP1_X_BUFFER_ADDRESS - __no_init BYTE __data16 pbXBufferAddressEp1[EP_MAX_PACKET_SIZE]; - -#pragma location = OEP1_Y_BUFFER_ADDRESS - __no_init BYTE __data16 pbYBufferAddressEp1[EP_MAX_PACKET_SIZE]; - -#pragma location = IEP1_X_BUFFER_ADDRESS - __no_init BYTE __data16 pbXBufferAddressEp81[EP_MAX_PACKET_SIZE]; - -#pragma location = IEP1_Y_BUFFER_ADDRESS - __no_init BYTE __data16 pbYBufferAddressEp81[EP_MAX_PACKET_SIZE]; - -#pragma location = OEP2_X_BUFFER_ADDRESS - __no_init BYTE __data16 pbXBufferAddressEp2[EP_MAX_PACKET_SIZE]; - -#pragma location = OEP2_Y_BUFFER_ADDRESS - __no_init BYTE __data16 pbYBufferAddressEp2[EP_MAX_PACKET_SIZE]; - -#pragma location = IEP2_X_BUFFER_ADDRESS - __no_init BYTE __data16 pbXBufferAddressEp82[EP_MAX_PACKET_SIZE]; - -#pragma location = IEP2_Y_BUFFER_ADDRESS - __no_init BYTE __data16 pbYBufferAddressEp82[EP_MAX_PACKET_SIZE]; - -#pragma location = OEP3_X_BUFFER_ADDRESS -__no_init BYTE __data16 pbXBufferAddressEp3[EP_MAX_PACKET_SIZE]; - -#pragma location = OEP3_Y_BUFFER_ADDRESS -__no_init BYTE __data16 pbYBufferAddressEp3[EP_MAX_PACKET_SIZE]; - -#pragma location = IEP3_X_BUFFER_ADDRESS -__no_init BYTE __data16 pbXBufferAddressEp83[EP_MAX_PACKET_SIZE]; - -#pragma location = IEP3_Y_BUFFER_ADDRESS -__no_init BYTE __data16 pbYBufferAddressEp83[EP_MAX_PACKET_SIZE]; - -#pragma location = OEP4_X_BUFFER_ADDRESS -__no_init BYTE __data16 pbXBufferAddressEp4[EP_MAX_PACKET_SIZE]; - -#pragma location = OEP4_Y_BUFFER_ADDRESS -__no_init BYTE __data16 pbYBufferAddressEp4[EP_MAX_PACKET_SIZE]; - -#pragma location = IEP4_X_BUFFER_ADDRESS -__no_init BYTE __data16 pbXBufferAddressEp84[EP_MAX_PACKET_SIZE]; - -#pragma location = IEP4_Y_BUFFER_ADDRESS -__no_init BYTE __data16 pbYBufferAddressEp84[EP_MAX_PACKET_SIZE]; - -#pragma location = OEP5_X_BUFFER_ADDRESS -__no_init BYTE __data16 pbXBufferAddressEp5[EP_MAX_PACKET_SIZE]; - -#pragma location = OEP5_Y_BUFFER_ADDRESS -__no_init BYTE __data16 pbYBufferAddressEp5[EP_MAX_PACKET_SIZE]; - -#pragma location = IEP5_X_BUFFER_ADDRESS -__no_init BYTE __data16 pbXBufferAddressEp85[EP_MAX_PACKET_SIZE]; - -#pragma location = IEP5_Y_BUFFER_ADDRESS -__no_init BYTE __data16 pbYBufferAddressEp85[EP_MAX_PACKET_SIZE]; - -#pragma location = OEP6_X_BUFFER_ADDRESS -__no_init BYTE __data16 pbXBufferAddressEp6[EP_MAX_PACKET_SIZE]; - -#pragma location = OEP6_Y_BUFFER_ADDRESS -__no_init BYTE __data16 pbYBufferAddressEp6[EP_MAX_PACKET_SIZE]; - -#pragma location = IEP6_X_BUFFER_ADDRESS -__no_init BYTE __data16 pbXBufferAddressEp86[EP_MAX_PACKET_SIZE]; - -#pragma location = IEP6_Y_BUFFER_ADDRESS -__no_init BYTE __data16 pbYBufferAddressEp86[EP_MAX_PACKET_SIZE]; - -#pragma location = OEP7_X_BUFFER_ADDRESS -__no_init BYTE __data16 pbXBufferAddressEp7[EP_MAX_PACKET_SIZE]; - -#pragma location = OEP7_Y_BUFFER_ADDRESS -__no_init BYTE __data16 pbYBufferAddressEp7[EP_MAX_PACKET_SIZE]; - -#pragma location = IEP7_X_BUFFER_ADDRESS -__no_init BYTE __data16 pbXBufferAddressEp87[EP_MAX_PACKET_SIZE]; - -#pragma location = IEP7_Y_BUFFER_ADDRESS -__no_init BYTE __data16 pbYBufferAddressEp87[EP_MAX_PACKET_SIZE]; - - - -#endif - -#ifdef __TI_COMPILER_VERSION__ -extern __no_init tDEVICE_REQUEST tSetupPacket; -extern __no_init tEDB0 tEndPoint0DescriptorBlock; -extern __no_init tEDB tInputEndPointDescriptorBlock[7]; -extern __no_init tEDB tOutputEndPointDescriptorBlock[7]; -extern __no_init BYTE abIEP0Buffer[EP0_MAX_PACKET_SIZE]; -extern __no_init BYTE abOEP0Buffer[EP0_MAX_PACKET_SIZE]; -extern __no_init BYTE pbXBufferAddressEp1[EP_MAX_PACKET_SIZE]; -extern __no_init BYTE pbYBufferAddressEp1[EP_MAX_PACKET_SIZE]; -extern __no_init BYTE pbXBufferAddressEp81[EP_MAX_PACKET_SIZE]; -extern __no_init BYTE pbYBufferAddressEp81[EP_MAX_PACKET_SIZE]; -extern __no_init BYTE pbXBufferAddressEp2[EP_MAX_PACKET_SIZE]; -extern __no_init BYTE pbYBufferAddressEp2[EP_MAX_PACKET_SIZE]; -extern __no_init BYTE pbXBufferAddressEp82[EP_MAX_PACKET_SIZE]; -extern __no_init BYTE pbYBufferAddressEp82[EP_MAX_PACKET_SIZE]; -extern __no_init BYTE pbXBufferAddressEp3[EP_MAX_PACKET_SIZE]; -extern __no_init BYTE pbYBufferAddressEp3[EP_MAX_PACKET_SIZE]; -extern __no_init BYTE pbXBufferAddressEp83[EP_MAX_PACKET_SIZE]; -extern __no_init BYTE pbYBufferAddressEp83[EP_MAX_PACKET_SIZE]; - -extern __no_init BYTE pbXBufferAddressEp4[EP_MAX_PACKET_SIZE]; -extern __no_init BYTE pbYBufferAddressEp4[EP_MAX_PACKET_SIZE]; -extern __no_init BYTE pbXBufferAddressEp84[EP_MAX_PACKET_SIZE]; -extern __no_init BYTE pbYBufferAddressEp84[EP_MAX_PACKET_SIZE]; - -extern __no_init BYTE pbXBufferAddressEp5[EP_MAX_PACKET_SIZE]; -extern __no_init BYTE pbYBufferAddressEp5[EP_MAX_PACKET_SIZE]; -extern __no_init BYTE pbXBufferAddressEp85[EP_MAX_PACKET_SIZE]; -extern __no_init BYTE pbYBufferAddressEp85[EP_MAX_PACKET_SIZE]; - -#endif - -VOID CdcResetData(); -VOID HidResetData(); - -VOID USB_InitSerialStringDescriptor(VOID); -VOID USB_initMemcpy(VOID); - -//---------------------------------------------------------------------------- -BYTE USB_init(VOID) -{ - WORD bGIE = __get_SR_register() &GIE; //save interrupt status - // atomic operation - disable interrupts - __disable_interrupt(); // Disable global interrupts - - // configuration of USB module - USBKEYPID = 0x9628; // set KEY and PID to 0x9628 -> access to configuration registers enabled - - USBPHYCTL = PUSEL; // use DP and DM as USB terminals (not needed because an external PHY is connected to port 9) - - USBPWRCTL = VUSBEN + SLDOAON; // enable primary and secondary LDO (3.3 and 1.8 V) - { - volatile unsigned int i; - for (i =0; i < USB_MCLK_FREQ/1000*2/10; i++); // wait some time for LDOs (1ms delay) - } - - USBPWRCTL = VUSBEN + SLDOAON + VBONIE; // enable interrupt VBUSon - USBKEYPID = 0x9600; // access to configuration registers disabled - - //reset events mask - wUsbEventMask = 0; - - //init Serial Number -#if (USB_STR_INDEX_SERNUM != 0) - USB_InitSerialStringDescriptor(); -#endif - - // init memcpy() function: DMA or non-DMA - USB_initMemcpy(); -#ifdef _MSC_ - MscResetCtrlLun(); -#endif - - __bis_SR_register(bGIE); //restore interrupt status - return kUSB_succeed; -} - -//---------------------------------------------------------------------------- -// This function will be compiled only if -#if (USB_STR_INDEX_SERNUM != 0) -VOID USB_InitSerialStringDescriptor(VOID) -{ - BYTE i,j,hexValue; - PBYTE pbSerNum; - BYTE bBytes; - - j=1; // we start with second byte, first byte (lenght) will be filled later - pbSerNum=0; - abramSerialStringDescriptor[j++] = DESC_TYPE_STRING; - - // TLV access Function Call - Get_TLV_Info(TLV_DIERECORD, 0, (uint8_t *)&bBytes, (uint16_t **)&pbSerNum); //The die record used for serial number - if (bBytes == 0) // no serial number available - { - // use 00 as serial number = no serial number available - abramSerialStringDescriptor[0] = 4; //length - abramSerialStringDescriptor[j++] = 0; // no serial number available - abramSerialStringDescriptor[j++] = 0; // no serial number available - } - else - { - for(i=0; (i> 4; - if(hexValue < 10 ) abramSerialStringDescriptor[j++] = (hexValue + '0'); - else abramSerialStringDescriptor[j++] = (hexValue + 55); - abramSerialStringDescriptor[j++] = 0x00; // needed for UNI-Code - - hexValue = (*pbSerNum & 0x0F); - if(hexValue < 10 ) abramSerialStringDescriptor[j++] = (hexValue + '0'); - else abramSerialStringDescriptor[j++] = (hexValue + 55); - abramSerialStringDescriptor[j++] = 0x00; // needed for UNI-Code - } - abramSerialStringDescriptor[0] = i*4 +2; // calculate the length - } -} -#endif - -//---------------------------------------------------------------------------- - -BYTE USB_enable() -{ - volatile unsigned int i; - volatile unsigned int j = 0; - - if (!(USBPWRCTL & USBBGVBV)) // check USB Bandgap and VBUS valid - { - return kUSB_generalError; - } - - if ((USBCNF & USB_EN) && - (USBPLLCTL & UPLLEN)) - { - return kUSB_succeed; // exit if PLL is already enalbed - } - - USBKEYPID = 0x9628; // set KEY and PID to 0x9628 -> access to configuration registers enabled - XT2_Start(XT2DRIVE_3); - USBPLLDIVB = USB_XT_FREQ; // Settings desired frequency - - USBPLLCTL = UPFDEN + UPLLEN; // Select XT1 as Ref / Select PLL for USB / Discrim. on, enable PLL - - //Wait some time till PLL is settled - do - { - USBPLLIR = 0x0000; // make sure no interrupts can occur on PLL-module - -#ifdef __MSP430F6638 - //wait 1 ms till enable USB - for (i =0; i < USB_MCLK_FREQ/1000*1/10; i++); -#else - //wait 1/2 ms till enable USB - for (i =0; i < USB_MCLK_FREQ/1000* 1/2 /10; i++); -#endif - - if (j++ > 10) - { - USBKEYPID = 0x9600; // access to configuration registers disabled - return kUSB_generalError; - } - }while (USBPLLIR != 0); - - USBCNF |= USB_EN; // enable USB module - USBKEYPID = 0x9600; // access to configuration registers disabled - return kUSB_succeed; -} - -/* -Disables the USB module and PLL. -*/ -BYTE USB_disable(VOID) -{ - USBKEYPID = 0x9628; // set KEY and PID to 0x9628 -> access to configuration registers enabled - USBCNF = 0; // disable USB module - USBPLLCTL &= ~UPLLEN; // disable PLL - USBKEYPID = 0x9600; // access to configuration registers disabled - bEnumerationStatus = 0x00; // device is not enumerated - bFunctionSuspended = FALSE;// device is not suspended - return kUSB_succeed; -} - -/* -Enables/disables various USB events. -*/ -BYTE USB_setEnabledEvents(WORD events) -{ - wUsbEventMask = events; - return kUSB_succeed; -} - -/* -Returns which events are enabled and which are disabled. -*/ -WORD USB_getEnabledEvents() -{ - return wUsbEventMask; -} - -/* -Reset USB-SIE and global variables. -*/ -BYTE USB_reset() -{ - int i; - USBKEYPID = 0x9628; // set KEY and PID to 0x9628 -> access to configuration registers enabled - - //reset should be on the bus after this! - bEnumerationStatus = 0x00; // Device not enumerated yet - bFunctionSuspended = FALSE; // Device is not in suspend mode - - bRemoteWakeup = DISABLE; - - bConfigurationNumber = 0x00; // device unconfigured - bInterfaceNumber = 0x00; - - // FRSTE handling: - // Clear FRSTE in the RESRIFG interrupt service routine before re-configuring USB control registers. - // Set FRSTE at the beginning of SUSRIFG, SETUP, IEPIFG.EP0 and OEPIFG.EP0 interrupt service routines. - USBCTL = 0; // Function Reset Connection disable (FRSTE) - - wBytesRemainingOnIEP0 = NO_MORE_DATA; - wBytesRemainingOnOEP0 = NO_MORE_DATA; - bStatusAction = STATUS_ACTION_NOTHING; - - //The address reset normally will be done automatically during bus function reset - USBFUNADR = 0x00; // reset address of USB device (unconfigured) - - /* Set settings for EP0 */ - // NAK both 0 endpoints and enable endpoint 0 interrupt - tEndPoint0DescriptorBlock.bIEPBCNT = EPBCNT_NAK; - tEndPoint0DescriptorBlock.bOEPBCNT = EPBCNT_NAK; - tEndPoint0DescriptorBlock.bIEPCNFG = EPCNF_USBIE | EPCNF_UBME | EPCNF_STALL; // 8 byte data packet - tEndPoint0DescriptorBlock.bOEPCNFG = EPCNF_USBIE | EPCNF_UBME | EPCNF_STALL; // 8 byte data packet - - USBOEPIE = USB_OUTEP_INT_EN; - USBIEPIE = USB_INEP_INT_EN; - - // loop for initialization all of used enpoints - for(i=0; i < (CDC_NUM_INTERFACES + HID_NUM_INTERFACES + MSC_NUM_INTERFACES); i++) - { - BYTE edbIndex = stUsbHandle[i].edb_Index; - - /* Set settings for IEPx */ - tInputEndPointDescriptorBlock[edbIndex].bEPCNF = EPCNF_USBIE | EPCNF_UBME | EPCNF_DBUF; //double buffering - tInputEndPointDescriptorBlock[edbIndex].bEPBBAX = (BYTE)(((stUsbHandle[i].iep_X_Buffer - START_OF_USB_BUFFER) >> 3) & 0x00ff); - tInputEndPointDescriptorBlock[edbIndex].bEPBBAY = (BYTE)(((stUsbHandle[i].iep_Y_Buffer - START_OF_USB_BUFFER) >> 3) & 0x00ff); - tInputEndPointDescriptorBlock[edbIndex].bEPBCTX = EPBCNT_NAK; - tInputEndPointDescriptorBlock[edbIndex].bEPBCTY = EPBCNT_NAK; - tInputEndPointDescriptorBlock[edbIndex].bEPSIZXY = MAX_PACKET_SIZE; - - /* Set settings for OEPx */ - tOutputEndPointDescriptorBlock[edbIndex].bEPCNF = EPCNF_USBIE | EPCNF_UBME | EPCNF_DBUF ; //double buffering - tOutputEndPointDescriptorBlock[edbIndex].bEPBBAX = (BYTE)(((stUsbHandle[i].oep_X_Buffer - START_OF_USB_BUFFER) >> 3) & 0x00ff); - tOutputEndPointDescriptorBlock[edbIndex].bEPBBAY = (BYTE)(((stUsbHandle[i].oep_Y_Buffer - START_OF_USB_BUFFER) >> 3) & 0x00ff); - tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX = 0x00; - tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY = 0x00; - tOutputEndPointDescriptorBlock[edbIndex].bEPSIZXY = MAX_PACKET_SIZE; - -# ifdef _CDC_ - /* Additional interrupt end point for CDC */ - if(stUsbHandle[i].dev_Class == CDC_CLASS) - { - // The decriptor tool always generates the managemnet endpoint before the data endpoint - tInputEndPointDescriptorBlock[edbIndex-1].bEPCNF = EPCNF_USBIE | EPCNF_UBME | EPCNF_DBUF; //double buffering - tInputEndPointDescriptorBlock[edbIndex-1].bEPBBAX = (BYTE)(((stUsbHandle[i].intepEP_X_Buffer - START_OF_USB_BUFFER) >> 3) & 0x00ff); - tInputEndPointDescriptorBlock[edbIndex-1].bEPBBAY = (BYTE)(((stUsbHandle[i].intepEP_Y_Buffer - START_OF_USB_BUFFER) >> 3) & 0x00ff); - tInputEndPointDescriptorBlock[edbIndex-1].bEPBCTX = EPBCNT_NAK; - tInputEndPointDescriptorBlock[edbIndex-1].bEPBCTY = EPBCNT_NAK; - tInputEndPointDescriptorBlock[edbIndex-1].bEPSIZXY = MAX_PACKET_SIZE; - } -# endif - } - -# ifdef _HID_ - HidResetData(); // reset HID specific data structures -# endif // _HID_ - -# ifdef _MSC_ - isMSCConfigured = FALSE; - USBMSC_reset(); - MscResetData(); -# endif - -# ifdef _CDC_ - CdcResetData(); // reset CDC specific data structures -# endif // _CDC_ - - USBCTL = FEN; // enable function - USBIFG = 0; // make sure no interrupts are pending - - USBIE = SETUPIE | RSTRIE | SUSRIE; // enable USB specific interrupts (setup, reset, suspend) - USBKEYPID = 0x9600; // access to configuration registers disabled - return kUSB_succeed; -} - -/* -Instruct USB module to make itself available to the PC for connection, by pulling PUR high. -*/ -BYTE USB_connect() -{ - USBKEYPID = 0x9628; // set KEY and PID to 0x9628 -> access to configuration registers enabled - USBCNF |= PUR_EN; // generate rising edge on DP -> the host enumerates our device as full speed device - USBPWRCTL |= VBOFFIE; // enable interrupt VUSBoff - USBKEYPID = 0x9600; // access to configuration registers disabled - - // after this the enumeration may take place - __no_operation(); - __no_operation(); - __no_operation(); - __no_operation(); - __no_operation(); - __no_operation(); - __no_operation(); - - return kUSB_succeed; -} - -/* -Force a disconnect from the PC by pulling PUR low. -*/ -BYTE USB_disconnect() -{ - USBKEYPID = 0x9628; // set KEY and PID to 0x9628 -> access to configuration registers enabled - USBCNF &= ~PUR_EN; // disconnect pull up resistor - logical disconnect from HOST - USBPWRCTL &= ~VBOFFIE; // disable interrupt VUSBoff - USBKEYPID = 0x9600; // access to configuration registers disabled - bEnumerationStatus = 0; // not enumerated - bFunctionSuspended = FALSE; // device is not suspended - return kUSB_succeed; -} - -/* -Force a remote wakeup of the USB host. -*/ -BYTE USB_forceRemoteWakeup() -{ - if (bFunctionSuspended == FALSE) // device is not suspended - { - return kUSB_NotSuspended; - } - if(bRemoteWakeup == ENABLE) - { - volatile unsigned int i; - USBCTL |= RWUP; // USB - Device Remote Wakeup Request - this bit is self-cleaned - return kUSB_succeed; - } - return kUSB_generalError; -} - -/* -Returns the status of the USB connection. -*/ -BYTE USB_connectionInfo() -{ - BYTE retVal = 0; - if (USBPWRCTL & USBBGVBV) - { - retVal |= kUSB_vbusPresent; - } - - if (bEnumerationStatus == ENUMERATION_COMPLETE) - { - retVal |= kUSB_Enumerated; - } - - if (USBCNF & PUR_EN) - { - retVal |= kUSB_purHigh; - } - - if (bFunctionSuspended == TRUE) - { - retVal |= kUSB_suspended; - } - else - { - retVal |= kUSB_NotSuspended; - } - return retVal; -} - -/* -Returns the state of the USB connection. -*/ -BYTE USB_connectionState() -{ - // If no VBUS present - if (!(USBPWRCTL & USBBGVBV)) - { - return ST_USB_DISCONNECTED; - } - - // If VBUS present, but PUR is low - if ((USBPWRCTL & USBBGVBV)&&(!(USBCNF & PUR_EN))) - { - return ST_USB_CONNECTED_NO_ENUM; - } - - // If VBUS present, PUR is high, and enumeration is complete, and not suspended - if ((USBPWRCTL & USBBGVBV) && (USBCNF & PUR_EN) - && (bEnumerationStatus == ENUMERATION_COMPLETE) - && (!(bFunctionSuspended == TRUE))) - { - return ST_ENUM_ACTIVE; - } - - // If VBUS present, PUR is high, and enumeration is NOT complete, and suspended - if ((USBPWRCTL & USBBGVBV) && (USBCNF & PUR_EN) - && (!(bEnumerationStatus == ENUMERATION_COMPLETE)) - && (bFunctionSuspended == TRUE)) - { - return ST_NOENUM_SUSPENDED; - } - - // If VBUS present, PUR is high, and enumeration is complete, and suspended - if ((USBPWRCTL & USBBGVBV) && (USBCNF & PUR_EN) - && (bEnumerationStatus == ENUMERATION_COMPLETE) - && (bFunctionSuspended == TRUE)) - { - return ST_ENUM_SUSPENDED; - } - - // If VBUS present, PUR is high, but no enumeration yet - if ((USBPWRCTL & USBBGVBV) && (USBCNF & PUR_EN) - && (!(bEnumerationStatus == ENUMERATION_COMPLETE))) - { - return ST_ENUM_IN_PROGRESS; - } - - return ST_ERROR; -} - -//---------------------------------------------------------------------------- - -BYTE USB_suspend(VOID) -{ - - bFunctionSuspended = TRUE; - USBKEYPID = 0x9628; // set KEY and PID to 0x9628 -> access to configuration registers enabled - USBCTL |= FRSTE; // Function Reset Connection Enable - USBIFG &= ~SUSRIFG; // clear interrupt flag - - if(USB_DISABLE_XT_SUSPEND) - { - if (USB_PLL_XT == 2) - { - USBPLLCTL &= ~UPLLEN; // disable PLL - UCSCTL6 |= XT2OFF; // disable XT2 - } - else - { - USBPLLCTL &= ~UPLLEN; // disable PLL - UCSCTL6 |= XT1OFF; - } - } - - USBIE = RESRIE; // disable USB specific interrupts (setup, suspend, reset), enable resume. - // If the reset occured during device in suspend, the resume-interrupt will come, after - reset interrupt - USBKEYPID = 0x9600; // access to configuration registers disabled - - return kUSB_succeed; -} - -//---------------------------------------------------------------------------- - -BYTE USB_resume(VOID) -{ - USB_enable(); // enable PLL - - USBIFG &= ~(RESRIFG | SUSRIFG); // clear interrupt flags - USBIE = SETUPIE | RSTRIE | SUSRIE; // enable USB specific interrupts (setup, reset, suspend) - - bFunctionSuspended = FALSE; - return kUSB_succeed; -} - -//---------------------------------------------------------------------------- - -VOID usbStallEndpoint0(VOID) -{ - tEndPoint0DescriptorBlock.bIEPCNFG |= EPCNF_STALL; - tEndPoint0DescriptorBlock.bOEPCNFG |= EPCNF_STALL; -} - -//---------------------------------------------------------------------------- - -VOID usbClearOEP0ByteCount(VOID) -{ - tEndPoint0DescriptorBlock.bOEPBCNT = 0x00; -} - -//---------------------------------------------------------------------------- - -VOID usbStallOEP0(VOID) -{ - // in standard USB request, there is not control write request with data stage - // control write, stall output endpoint 0 - // wLength should be 0 in all cases - tEndPoint0DescriptorBlock.bOEPCNFG |= EPCNF_STALL; -} - -//---------------------------------------------------------------------------- - -VOID usbSendNextPacketOnIEP0(VOID) -{ - BYTE bPacketSize,bIndex; - - // First check if there are bytes remaining to be transferred - if(wBytesRemainingOnIEP0 != NO_MORE_DATA) - { - if(wBytesRemainingOnIEP0 > EP0_PACKET_SIZE) - { - // More bytes are remaining than will fit in one packet - // there will be More IN Stage - bPacketSize = EP0_PACKET_SIZE; - wBytesRemainingOnIEP0 -= EP0_PACKET_SIZE; - bStatusAction = STATUS_ACTION_DATA_IN; - } - else if (wBytesRemainingOnIEP0 < EP0_PACKET_SIZE) - { - // The remaining data will fit in one packet. - // This case will properly handle wBytesRemainingOnIEP0 == 0 - bPacketSize = (BYTE)wBytesRemainingOnIEP0; - wBytesRemainingOnIEP0 = NO_MORE_DATA; // No more data need to be Txed - bStatusAction = STATUS_ACTION_NOTHING; - } - else - { - bPacketSize = EP0_PACKET_SIZE; - if(bHostAskMoreDataThanAvailable == TRUE) - { - wBytesRemainingOnIEP0 = 0; - bStatusAction = STATUS_ACTION_DATA_IN; - } - else - { - wBytesRemainingOnIEP0 = NO_MORE_DATA; - bStatusAction = STATUS_ACTION_NOTHING; - } - } - - for(bIndex=0; bIndex= wTemp) - { - wBytesRemainingOnIEP0 = wTemp; - bHostAskMoreDataThanAvailable = FALSE; - } - else - { - bHostAskMoreDataThanAvailable = TRUE; - } - usbSendNextPacketOnIEP0(); -} - -//---------------------------------------------------------------------------- -VOID usbReceiveNextPacketOnOEP0(VOID) -{ - BYTE bIndex,bByte; - - bByte = tEndPoint0DescriptorBlock.bOEPBCNT & EPBCNT_BYTECNT_MASK; - - if(wBytesRemainingOnOEP0 >= (WORD)bByte) - { - for(bIndex=0;bIndex 0) - { - usbClearOEP0ByteCount(); - bStatusAction = STATUS_ACTION_DATA_OUT; - } - else - { - usbStallOEP0(); - bStatusAction = STATUS_ACTION_NOTHING; - } - } - else - { - usbStallOEP0(); - bStatusAction = STATUS_ACTION_NOTHING; - } -} - -//---------------------------------------------------------------------------- - -VOID usbReceiveDataPacketOnEP0(PBYTE pbBuffer) -{ - - pbOEP0Buffer = pbBuffer; - - wBytesRemainingOnOEP0 = tSetupPacket.wLength; - bStatusAction = STATUS_ACTION_DATA_OUT; - - usbClearOEP0ByteCount(); -} - -//---------------------------------------------------------------------------- - -VOID usbSendZeroLengthPacketOnIEP0(VOID) -{ - wBytesRemainingOnIEP0 = NO_MORE_DATA; - bStatusAction = STATUS_ACTION_NOTHING; - tEndPoint0DescriptorBlock.bIEPBCNT = 0x00; -} - -//---------------------------------------------------------------------------- - -VOID usbClearEndpointFeature(VOID) -{ - BYTE bEndpointNumber; - - // EP is from EP1 to EP7 while C language start from 0 - bEndpointNumber = (tSetupPacket.wIndex & EP_DESC_ADDR_EP_NUM); - if(bEndpointNumber == 0x00) usbSendZeroLengthPacketOnIEP0(); - else - { - bEndpointNumber--; - if(bEndpointNumber < MAX_ENDPOINT_NUMBER) - { - if((tSetupPacket.wIndex & EP_DESC_ADDR_DIR_IN) == EP_DESC_ADDR_DIR_IN) - { -#ifdef _MSC_ - if (!bMscResetRequired) { -#endif - tInputEndPointDescriptorBlock[bEndpointNumber].bEPCNF &= ~(EPCNF_STALL | EPCNF_TOGGLE ); -#ifdef _MSC_ - } -#endif -# ifdef _MSC_ - if (stUsbHandle[MSC0_INTFNUM].edb_Index == bEndpointNumber) - { - MscReadControl.bCurrentBufferXY = 0; //Set current buffer to X - bMcsCommandSupported = TRUE; - } -# endif - } - else - { -#ifdef _MSC_ - if (!bMscResetRequired) { -#endif - tOutputEndPointDescriptorBlock[bEndpointNumber].bEPCNF &= ~(EPCNF_STALL | EPCNF_TOGGLE ); -#ifdef _MSC_ - } -#endif -# ifdef _MSC_ - if (stUsbHandle[MSC0_INTFNUM].edb_Index == bEndpointNumber) - { - MscWriteControl.bCurrentBufferXY = 0; //Set current buffer to X - bMcsCommandSupported = TRUE; - } -# endif - } - usbSendZeroLengthPacketOnIEP0(); - } - } -} - -//---------------------------------------------------------------------------- - -VOID usbGetConfiguration(VOID) -{ - usbClearOEP0ByteCount(); // for status stage - wBytesRemainingOnIEP0 = 1; - usbSendDataPacketOnEP0((PBYTE)&bConfigurationNumber); -} - -//---------------------------------------------------------------------------- - -VOID usbGetDeviceDescriptor(VOID) -{ - usbClearOEP0ByteCount(); - wBytesRemainingOnIEP0 = SIZEOF_DEVICE_DESCRIPTOR; - usbSendDataPacketOnEP0((PBYTE) &abromDeviceDescriptor); -} - -//---------------------------------------------------------------------------- - -VOID usbGetConfigurationDescriptor(VOID) -{ - usbClearOEP0ByteCount(); - wBytesRemainingOnIEP0 = sizeof(abromConfigurationDescriptorGroup); - usbSendDataPacketOnEP0((PBYTE)&abromConfigurationDescriptorGroup); -} - -//---------------------------------------------------------------------------- - -VOID usbGetStringDescriptor(VOID) -{ - WORD bIndex; - BYTE bVal = (BYTE)tSetupPacket.wValue; - - usbClearOEP0ByteCount(); // for status stage -#if (USB_STR_INDEX_SERNUM != 0) - - if(bVal == 0x03) - { - wBytesRemainingOnIEP0 = abramSerialStringDescriptor[0]; - usbSendDataPacketOnEP0((PBYTE)&abramSerialStringDescriptor); - } - else -#endif - { - bIndex = 0x00; - while(bVal-- > 0x00) bIndex += abromStringDescriptor[bIndex]; - wBytesRemainingOnIEP0 = abromStringDescriptor[bIndex]; - usbSendDataPacketOnEP0((PBYTE)&abromStringDescriptor[bIndex]); - } -} - -//---------------------------------------------------------------------------- - -VOID usbGetInterface(VOID) -{ - - // not fully supported, return one byte, zero - usbClearOEP0ByteCount(); // for status stage - wBytesRemainingOnIEP0 = 0x02; - abUsbRequestReturnData[0] = 0x00; // changed to report alternative setting byte - abUsbRequestReturnData[1] = bInterfaceNumber; - usbSendDataPacketOnEP0((PBYTE)&abUsbRequestReturnData[0]); -} - -//---------------------------------------------------------------------------- - -VOID usbGetDeviceStatus(VOID) -{ - if((abromConfigurationDescriptorGroup.abromConfigurationDescriptorGenric.mattributes & - CFG_DESC_ATTR_SELF_POWERED) == CFG_DESC_ATTR_SELF_POWERED) - { - abUsbRequestReturnData[0] = DEVICE_STATUS_SELF_POWER; - } - if(bRemoteWakeup == ENABLE) - { - abUsbRequestReturnData[0] |= DEVICE_STATUS_REMOTE_WAKEUP; - } - usbClearOEP0ByteCount(); // for status stage - - // Return self power status and remote wakeup status - wBytesRemainingOnIEP0 = 2; - usbSendDataPacketOnEP0((PBYTE)&abUsbRequestReturnData[0]); -} - -//---------------------------------------------------------------------------- - -VOID usbGetInterfaceStatus(VOID) -{ - // check bIndexL for index number (not supported) - usbClearOEP0ByteCount(); // for status stage - - // Return two zero bytes - wBytesRemainingOnIEP0 = 2; - abUsbRequestReturnData[0] = 0x00; // changed to support multiple interfaces - abUsbRequestReturnData[1] = bInterfaceNumber; - usbSendDataPacketOnEP0((PBYTE)&abUsbRequestReturnData[0]); -} - -//---------------------------------------------------------------------------- - -VOID usbGetEndpointStatus(VOID) -{ - BYTE bEndpointNumber; - - // Endpoint number is bIndexL - bEndpointNumber = tSetupPacket.wIndex & EP_DESC_ADDR_EP_NUM; - if(bEndpointNumber == 0x00) - { - if((tSetupPacket.wIndex & EP_DESC_ADDR_DIR_IN) == EP_DESC_ADDR_DIR_IN) - { - // input endpoint 0 - abUsbRequestReturnData[0] = (BYTE)(tEndPoint0DescriptorBlock.bIEPCNFG & EPCNF_STALL); - } - else - { - // output endpoint 0 - abUsbRequestReturnData[0] = (BYTE)(tEndPoint0DescriptorBlock.bOEPCNFG & EPCNF_STALL); - } - abUsbRequestReturnData[0] = abUsbRequestReturnData[0] >> 3; // STALL is on bit 3 - usbClearOEP0ByteCount(); // for status stage - wBytesRemainingOnIEP0 = 0x02; - usbSendDataPacketOnEP0((PBYTE)&abUsbRequestReturnData[0]); - } - else - { - bEndpointNumber--; - // EP is from EP1 to EP7 while C language start from 0 - // Firmware should NOT response if specified endpoint is not supported. (charpter 8) - if(bEndpointNumber < MAX_ENDPOINT_NUMBER) - { - if(tSetupPacket.wIndex & EP_DESC_ADDR_DIR_IN) - { - // input endpoint - abUsbRequestReturnData[0] = (BYTE)(tInputEndPointDescriptorBlock[bEndpointNumber].bEPCNF & EPCNF_STALL); - }else - { - // output endpoint - abUsbRequestReturnData[0] = (BYTE)(tOutputEndPointDescriptorBlock[bEndpointNumber].bEPCNF & EPCNF_STALL); - } - } // no response if endpoint is not supported. - abUsbRequestReturnData[0] = abUsbRequestReturnData[0] >> 3; // STALL is on bit 3 - usbClearOEP0ByteCount(); - wBytesRemainingOnIEP0 = 0x02; - usbSendDataPacketOnEP0((PBYTE)&abUsbRequestReturnData[0]); - } -} - -//---------------------------------------------------------------------------- -VOID usbSetAddress(VOID) -{ - usbStallOEP0(); // control write without data stage - - // bValueL contains device address - if(tSetupPacket.wValue < 128) - { - // hardware will update the address after status stage - // therefore, firmware can set the address now. - USBFUNADR = tSetupPacket.wValue; - usbSendZeroLengthPacketOnIEP0(); - } - else - { - usbStallEndpoint0(); - } -} - -//---------------------------------------------------------------------------- - -VOID usbSetConfiguration(VOID) -{ - usbStallOEP0(); // control write without data stage - - // configuration number is in bValueL - // change the code if more than one configuration is supported - bConfigurationNumber = tSetupPacket.wValue; - usbSendZeroLengthPacketOnIEP0(); - - if (bConfigurationNumber == 1) - { - bEnumerationStatus = ENUMERATION_COMPLETE; // set device as enumerated - } - else - { - bEnumerationStatus = 0; //device is not configured == config # is zero - } -} - -//---------------------------------------------------------------------------- - -VOID usbClearDeviceFeature(VOID) -{ - // bValueL contains feature selector - if(tSetupPacket.wValue == FEATURE_REMOTE_WAKEUP) - { - bRemoteWakeup = DISABLE; - usbSendZeroLengthPacketOnIEP0(); - } - else - { - usbStallEndpoint0(); - } -} - -//---------------------------------------------------------------------------- - -VOID usbSetDeviceFeature(VOID) -{ - // bValueL contains feature selector - if(tSetupPacket.wValue == FEATURE_REMOTE_WAKEUP) - { - bRemoteWakeup = ENABLE; - usbSendZeroLengthPacketOnIEP0(); - } - else - { - usbStallEndpoint0(); - } -} - -//---------------------------------------------------------------------------- - -VOID usbSetEndpointFeature(VOID) -{ - BYTE bEndpointNumber; - - // wValue contains feature selector - // bIndexL contains endpoint number - // Endpoint number is in low byte of wIndex - if(tSetupPacket.wValue == FEATURE_ENDPOINT_STALL) - { - bEndpointNumber = tSetupPacket.wIndex & EP_DESC_ADDR_EP_NUM; - if(bEndpointNumber == 0x00) usbSendZeroLengthPacketOnIEP0(); // do nothing for endpoint 0 - else - { - bEndpointNumber--; - // Firmware should NOT response if specified endpoint is not supported. (charpter 8) - if(bEndpointNumber < MAX_ENDPOINT_NUMBER) - { - if(tSetupPacket.wIndex & EP_DESC_ADDR_DIR_IN) - { - // input endpoint - tInputEndPointDescriptorBlock[bEndpointNumber].bEPCNF |= EPCNF_STALL; - } - else - { - // output endpoint - tOutputEndPointDescriptorBlock[bEndpointNumber].bEPCNF |= EPCNF_STALL; - } - usbSendZeroLengthPacketOnIEP0(); - } // no response if endpoint is not supported. - } - } - else - { - usbStallEndpoint0(); - } -} - -//---------------------------------------------------------------------------- - -VOID usbSetInterface(VOID) -{ - // bValueL contains alternative setting - // bIndexL contains interface number - // change code if more than one interface is supported - usbStallOEP0(); // control write without data stage - bInterfaceNumber = tSetupPacket.wIndex; -#ifdef _MSC_ - tInputEndPointDescriptorBlock[stUsbHandle[MSC0_INTFNUM].edb_Index].bEPCNF &= ~(EPCNF_TOGGLE); - tOutputEndPointDescriptorBlock[stUsbHandle[MSC0_INTFNUM].edb_Index].bEPCNF &= ~(EPCNF_TOGGLE); - MscReadControl.bCurrentBufferXY = 0; //Set current buffer to X - MscWriteControl.bCurrentBufferXY = 0; //Set current buffer to X -#endif - usbSendZeroLengthPacketOnIEP0(); -} - -//---------------------------------------------------------------------------- - -VOID usbInvalidRequest(VOID) -{ - // check if setup overwrite is set - // if set, do nothing since we might decode it wrong - // setup packet buffer could be modified by hardware if another setup packet - // was sent while we are deocding setup packet - if ((USBIFG & STPOWIFG) == 0x00) - { - usbStallEndpoint0(); - } -} - -typedef VOID (*tpF)(VOID); - -BYTE usbDecodeAndProcessUsbRequest(VOID) -{ - BYTE bMask,bResult,bTemp; - const BYTE* pbUsbRequestList; - BYTE bWakeUp = FALSE; - ptDEVICE_REQUEST ptSetupPacket = &tSetupPacket; - BYTE bRequestType,bRequest; - tpF lAddrOfFunction; - - // point to beginning of the matrix - pbUsbRequestList = (PBYTE)&tUsbRequestList[0]; - - while(1) - { - bRequestType = *pbUsbRequestList++; - bRequest = *pbUsbRequestList++; - - if(((bRequestType == 0xff) && (bRequest == 0xff)) || - (tSetupPacket.bmRequestType == (USB_REQ_TYPE_INPUT | USB_REQ_TYPE_VENDOR | USB_REQ_TYPE_DEVICE)) || - (tSetupPacket.bmRequestType == (USB_REQ_TYPE_OUTPUT | USB_REQ_TYPE_VENDOR | USB_REQ_TYPE_DEVICE))) - { - pbUsbRequestList -= 2; - break; - } - - if((bRequestType == tSetupPacket.bmRequestType) && (bRequest == tSetupPacket.bRequest)) - { - // compare the first two - bResult = 0xc0; - bMask = 0x20; - // first two bytes matched, compare the rest - for(bTemp = 2; bTemp < 8; bTemp++) - { - if (*((BYTE*)ptSetupPacket + bTemp) == *pbUsbRequestList) - { - bResult |= bMask; - } - pbUsbRequestList++; - bMask = bMask >> 1; - } - // now we have the result - if((*pbUsbRequestList & bResult) == *pbUsbRequestList) - { - pbUsbRequestList -= 8; - break; - } - else - { - pbUsbRequestList += (sizeof(tDEVICE_REQUEST_COMPARE)-8); - } - } - else - { - pbUsbRequestList += (sizeof(tDEVICE_REQUEST_COMPARE)-2); - } - } - - // if another setup packet comes before we have the chance to process current - // setup request, we return here without processing the request - // this check is not necessary but still kept here to reduce response(or simulation) time - - if((USBIFG & STPOWIFG) != 0x00) - { - return bWakeUp; - } - - // now we found the match and jump to the function accordingly. - lAddrOfFunction = ((tDEVICE_REQUEST_COMPARE*)pbUsbRequestList)->pUsbFunction; - - // call function - (*lAddrOfFunction)(); - - // perform enumeration complete event: - // when SetAddress was called and USBADDR is not zero - if ((lAddrOfFunction == &usbSetAddress) && (USBFUNADR != 0)) - { - bWakeUp = USB_handleEnumCompleteEvent(); - } - return bWakeUp; -} - -/*----------------------------------------------------------------------------+ -| End of source file | -+----------------------------------------------------------------------------*/ -/*------------------------ Nothing Below This Line --------------------------*/ diff --git a/USB_API/USB_Common/usb.h b/USB_API/USB_Common/usb.h deleted file mode 100644 index 68e50e7..0000000 --- a/USB_API/USB_Common/usb.h +++ /dev/null @@ -1,491 +0,0 @@ -/* - * usb.h - * - * Common USB functions - * - * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/*----------------------------------------------------------------------------+ -| | -| Texas Instruments | -| | -| MSP430 USB-Example (CDC/HID/MSC Driver) | -| | -+-----------------------------------------------------------------------------+ -| Source: Usb.h, File Version 1.04 2010/10/30 | -| Author: RSTO | -| | -| WHO WHEN WHAT | -| --- ---------- ------------------------------------------------ | -| RSTO 2008/09/03 born | -| RSTO 2008/12/23 enhancements of CDC API | -| RSTO 2009/05/15 changed USB_connectionStatus() | -| to USB_connectionInfo() | -| RSTO 2009/05/26 remove kUSB_failedEnumEvent | -| RSTO 2009/07/17 added __data16 qualifier for USB buffers | -| MSP,Biju 2009/10/20 Composite support changes | -| RSTO 2009/11/05 added event ST_NOENUM_SUSPENDED | -| MSP,Biju 2009/12/28 macros DESC_TYPE_IAD added due to IAD | -| support | -| RSTO 2010/10/30 added kUSB_allXXXEvents | -+----------------------------------------------------------------------------*/ - -#ifndef _USB_H_ -#define _USB_H_ - -#ifdef __cplusplus -extern "C" -{ -#endif - -/*----------------------------------------------------------------------------+ -| Constant Definition | -+----------------------------------------------------------------------------*/ -#define USB_RETURN_DATA_LENGTH 8 -#define SIZEOF_DEVICE_REQUEST 0x08 - -// Bit definitions for DEVICE_REQUEST.bmRequestType -// Bit 7: Data direction -#define USB_REQ_TYPE_OUTPUT 0x00 // 0 = Host sending data to device -#define USB_REQ_TYPE_INPUT 0x80 // 1 = Device sending data to host - -// Bit 6-5: Type -#define USB_REQ_TYPE_MASK 0x60 // Mask value for bits 6-5 -#define USB_REQ_TYPE_STANDARD 0x00 // 00 = Standard USB request -#define USB_REQ_TYPE_CLASS 0x20 // 01 = Class specific -#define USB_REQ_TYPE_VENDOR 0x40 // 10 = Vendor specific - -// Bit 4-0: Recipient -#define USB_REQ_TYPE_RECIP_MASK 0x1F // Mask value for bits 4-0 -#define USB_REQ_TYPE_DEVICE 0x00 // 00000 = Device -#define USB_REQ_TYPE_INTERFACE 0x01 // 00001 = Interface -#define USB_REQ_TYPE_ENDPOINT 0x02 // 00010 = Endpoint -#define USB_REQ_TYPE_OTHER 0x03 // 00011 = Other - -// Values for DEVICE_REQUEST.bRequest -// Standard Device Requests -#define USB_REQ_GET_STATUS 0 -#define USB_REQ_CLEAR_FEATURE 1 -#define USB_REQ_SET_FEATURE 3 -#define USB_REQ_SET_ADDRESS 5 -#define USB_REQ_GET_DESCRIPTOR 6 -#define USB_REQ_SET_DESCRIPTOR 7 -#define USB_REQ_GET_CONFIGURATION 8 -#define USB_REQ_SET_CONFIGURATION 9 -#define USB_REQ_GET_INTERFACE 10 -#define USB_REQ_SET_INTERFACE 11 -#define USB_REQ_SYNCH_FRAME 12 - -// CDC CLASS Requests -#define USB_CDC_GET_LINE_CODING 0x21 -#define USB_CDC_SET_LINE_CODING 0x20 -#define USB_CDC_SET_CONTROL_LINE_STATE 0x22 - -// HID CLASS Requests -#define USB_HID_REQ 0x81 -#define USB_REQ_GET_REPORT 0x01 -#define USB_REQ_GET_IDLE 0x02 -#define USB_REQ_SET_REPORT 0x09 -#define USB_REQ_SET_IDLE 0x0A -#define USB_REQ_SET_PROTOCOL 0x0B -#define USB_REQ_GET_PROTOCOL 0x03 - -// MSC CLASS Requests -#define USB_MSC_RESET_BULK 0xFF -#define USB_MSC_GET_MAX_LUN 0xFE - -//HID Values for HID Report Types (tSetup.bValueH) -#define USB_REQ_HID_INPUT 0x01 -#define USB_REQ_HID_OUTPUT 0x02 -#define USB_REQ_HID_FEATURE 0x03 - - -// Descriptor Type Values -#define DESC_TYPE_DEVICE 1 // Device Descriptor (Type 1) -#define DESC_TYPE_CONFIG 2 // Configuration Descriptor (Type 2) -#define DESC_TYPE_STRING 3 // String Descriptor (Type 3) -#define DESC_TYPE_INTERFACE 4 // Interface Descriptor (Type 4) -#define DESC_TYPE_ENDPOINT 5 // Endpoint Descriptor (Type 5) -#define DESC_TYPE_DEVICE_QUALIFIER 6 // Endpoint Descriptor (Type 6) -#define DESC_TYPE_IAD 0x0B -#define DESC_TYPE_HUB 0x29 // Hub Descriptor (Type 6) -#define DESC_TYPE_HID 0x21 // HID Descriptor -#define DESC_TYPE_REPORT 0x22 // Report Descriptor -#define DESC_TYPE_PHYSICAL 0x23 // Physical Descriptor - -// Feature Selector Values -#define FEATURE_REMOTE_WAKEUP 1 // Remote wakeup (Type 1) -#define FEATURE_ENDPOINT_STALL 0 // Endpoint stall (Type 0) - -// Device Status Values -#define DEVICE_STATUS_REMOTE_WAKEUP 0x02 -#define DEVICE_STATUS_SELF_POWER 0x01 - -// Maximum descriptor size -#define MAX_DESC_SIZE 256 - -// DEVICE_DESCRIPTOR structure -#define SIZEOF_DEVICE_DESCRIPTOR 0x12 -#define OFFSET_DEVICE_DESCRIPTOR_VID_L 0x08 -#define OFFSET_DEVICE_DESCRIPTOR_VID_H 0x09 -#define OFFSET_DEVICE_DESCRIPTOR_PID_L 0x0A -#define OFFSET_DEVICE_DESCRIPTOR_PID_H 0x0B -#define OFFSET_CONFIG_DESCRIPTOR_POWER 0x07 -#define OFFSET_CONFIG_DESCRIPTOR_CURT 0x08 - -// CONFIG_DESCRIPTOR structure -#define SIZEOF_CONFIG_DESCRIPTOR 0x09 - -// HID DESCRIPTOR structure -//#define SIZEOF_HID_DESCRIPTOR 0x09 - -// Bit definitions for CONFIG_DESCRIPTOR.bmAttributes -#define CFG_DESC_ATTR_SELF_POWERED 0x40 // Bit 6: If set, device is self powered -#define CFG_DESC_ATTR_BUS_POWERED 0x80 // Bit 7: If set, device is bus powered -#define CFG_DESC_ATTR_REMOTE_WAKE 0x20 // Bit 5: If set, device supports remote wakeup - -// INTERFACE_DESCRIPTOR structure -#define SIZEOF_INTERFACE_DESCRIPTOR 0x09 - -// ENDPOINT_DESCRIPTOR structure -#define SIZEOF_ENDPOINT_DESCRIPTOR 0x07 - -// Bit definitions for EndpointDescriptor.EndpointAddr -#define EP_DESC_ADDR_EP_NUM 0x0F // Bit 3-0: Endpoint number -#define EP_DESC_ADDR_DIR_IN 0x80 // Bit 7: Direction of endpoint, 1/0 = In/Out - -// Bit definitions for EndpointDescriptor.EndpointFlags -#define EP_DESC_ATTR_TYPE_MASK 0x03 // Mask value for bits 1-0 -#define EP_DESC_ATTR_TYPE_CONT 0x00 // Bit 1-0: 00 = Endpoint does control transfers -#define EP_DESC_ATTR_TYPE_ISOC 0x01 // Bit 1-0: 01 = Endpoint does isochronous transfers -#define EP_DESC_ATTR_TYPE_BULK 0x02 // Bit 1-0: 10 = Endpoint does bulk transfers -#define EP_DESC_ATTR_TYPE_INT 0x03 // Bit 1-0: 11 = Endpoint does interrupt transfers - -// Definition to indicate valid/invalid data -#define DATA_VALID 1 -#define DATA_INVALID 0 - -extern __no_init tDEVICE_REQUEST __data16 tSetupPacket; -extern __no_init BYTE __data16 abIEP0Buffer[]; -extern __no_init BYTE __data16 abOEP0Buffer[]; -extern __no_init BYTE __data16 pbXBufferAddressEp1[]; -extern __no_init BYTE __data16 pbYBufferAddressEp1[]; -extern __no_init BYTE __data16 pbXBufferAddressEp81[]; -extern __no_init BYTE __data16 pbYBufferAddressEp81[]; -extern __no_init BYTE __data16 pbXBufferAddressEp2[]; -extern __no_init BYTE __data16 pbYBufferAddressEp2[]; -extern __no_init BYTE __data16 pbXBufferAddressEp82[]; -extern __no_init BYTE __data16 pbYBufferAddressEp82[]; - -extern __no_init BYTE __data16 pbXBufferAddressEp3[]; -extern __no_init BYTE __data16 pbYBufferAddressEp3[]; -extern __no_init BYTE __data16 pbXBufferAddressEp83[]; -extern __no_init BYTE __data16 pbYBufferAddressEp83[]; - -extern __no_init BYTE __data16 pbXBufferAddressEp4[]; -extern __no_init BYTE __data16 pbYBufferAddressEp4[]; -extern __no_init BYTE __data16 pbXBufferAddressEp84[]; -extern __no_init BYTE __data16 pbYBufferAddressEp84[]; - -extern __no_init BYTE __data16 pbXBufferAddressEp5[]; -extern __no_init BYTE __data16 pbYBufferAddressEp5[]; -extern __no_init BYTE __data16 pbXBufferAddressEp85[]; -extern __no_init BYTE __data16 pbYBufferAddressEp85[]; - - -extern __no_init BYTE __data16 pbXBufferAddressEp6[]; -extern __no_init BYTE __data16 pbYBufferAddressEp6[]; -extern __no_init BYTE __data16 pbXBufferAddressEp86[]; -extern __no_init BYTE __data16 pbYBufferAddressEp86[]; - -extern __no_init BYTE __data16 pbXBufferAddressEp7[]; -extern __no_init BYTE __data16 pbYBufferAddressEp7[]; -extern __no_init BYTE __data16 pbXBufferAddressEp87[]; -extern __no_init BYTE __data16 pbYBufferAddressEp87[]; - -extern WORD wBytesRemainingOnIEP0; -extern WORD wBytesRemainingOnOEP0; -extern BYTE abUsbRequestReturnData[]; -extern BYTE abUsbRequestIncomingData[]; -extern BYTE bEnumerationStatus; -extern BYTE bFunctionSuspended; - -//Function return values -#define kUSB_succeed 0x00 -#define kUSB_generalError 0x01 -#define kUSB_notEnabled 0x02 -//#define kUSB_VbusNotPresent 0x03 - -//return values USB_connectionInfo(), USB_connect() -#define kUSB_vbusPresent 0x01 -#define kUSB_busActive 0x02 // frame sync packets are being received -#define kUSB_ConnectNoVBUS 0x04 -#define kUSB_suspended 0x08 -#define kUSB_NotSuspended 0x10 -#define kUSB_Enumerated 0x20 -#define kUSB_purHigh 0x40 - -// Parameters for function USB_setEnabledEvents() -#define kUSB_clockFaultEvent 0x0001 -#define kUSB_VbusOnEvent 0x0002 -#define kUSB_VbusOffEvent 0x0004 -#define kUSB_UsbResetEvent 0x0008 -#define kUSB_UsbSuspendEvent 0x0010 -#define kUSB_UsbResumeEvent 0x0020 -#define kUSB_dataReceivedEvent 0x0040 -#define kUSB_sendCompletedEvent 0x0080 -#define kUSB_receiveCompletedEvent 0x0100 -#define kUSB_allUsbEvents 0x01FF - -// USB connection states -#define ST_USB_DISCONNECTED 0x80 -#define ST_USB_CONNECTED_NO_ENUM 0x81 -#define ST_ENUM_IN_PROGRESS 0x82 -#define ST_ENUM_ACTIVE 0x83 -#define ST_ENUM_SUSPENDED 0x84 -//#define ST_FAILED_ENUM 0x85 -#define ST_ERROR 0x86 -#define ST_NOENUM_SUSPENDED 0x87 - -VOID usbStallInEndpoint(BYTE); -VOID usbStallOutEndpoint(BYTE); -VOID usbStallEndpoint(BYTE); -VOID usbClearOEPByteCount(BYTE); - - -/*---------------------------------------------------------------------------- -These functions can be used in application -+----------------------------------------------------------------------------*/ - -/* -MSP430 USB Module Management functions -*/ - -/** -Init the USB HW interface. -*/ -BYTE USB_init(VOID); - -/** -Init and start the USB PLL. -*/ -BYTE USB_enable(); - -/** -Disables the USB module and PLL. -*/ -BYTE USB_disable(VOID); - -/* -Enables/disables various USB events. -*/ -BYTE USB_setEnabledEvents(WORD events); - -/* -Returns which events are enabled and which are disabled. -*/ -WORD USB_getEnabledEvents(); - -/* -Instruct USB module to make itself available to the PC for connection, by pulling PUR high. -*/ -BYTE USB_connect(); - -/* -Force a disconnect from the PC by pulling PUR low. -*/ -BYTE USB_disconnect(); - -/** -Reset USB-SIE and global variables. -*/ -BYTE USB_reset(); - -/** -Suspend USB. -*/ -BYTE USB_suspend(VOID); - -/** -Resume USB. -*/ -BYTE USB_resume(VOID); - -/* -Force a remote wakeup of the USB host. - This method can be generated only if device supports - remote wake-up feature in some of its configurations. - The method wakes-up the USB bus only if wake-up feature is enabled by the host. -*/ -BYTE USB_forceRemoteWakeup(); - -/* -Returns the status of the USB connection. -*/ -BYTE USB_connectionInfo(); - -/* -Returns the state of the USB connection. -*/ -BYTE USB_connectionState(); - -/* -Event-Handling routines -*/ - -/* -If this function gets executed, it's a sign that the output of the USB PLL has failed. -returns TRUE to keep CPU awake -*/ -BYTE USB_handleClockEvent(); - -/* -If this function gets executed, it indicates that a valid voltage has just been applied to the VBUS pin. -returns TRUE to keep CPU awake -*/ -BYTE USB_handleVbusOnEvent(); - -/* -If this function gets executed, it indicates that a valid voltage has just been removed from the VBUS pin. -returns TRUE to keep CPU awake -*/ -BYTE USB_handleVbusOffEvent(); - -/* -If this function gets executed, it indicates that the USB host has issued a USB reset event to the device. -returns TRUE to keep CPU awake -*/ -BYTE USB_handleResetEvent(); - -/* -If this function gets executed, it indicates that the USB host has chosen to suspend this device after a period of active operation. -returns TRUE to keep CPU awake -*/ -BYTE USB_handleSuspendEvent(); - -/* -If this function gets executed, it indicates that the USB host has chosen to resume this device after a period of suspended operation. -returns TRUE to keep CPU awake -*/ -BYTE USB_handleResumeEvent(); - -/* -If this function gets executed, it indicates that the USB host has enumerated this device : -after host assigned the address to the device. -returns TRUE to keep CPU awake -*/ -BYTE USB_handleEnumCompleteEvent(); - -/** -Send stall handshake for in- and out-endpoint0 (control pipe) -*/ -VOID usbStallEndpoint0(VOID); - -/** -Clear byte counter for endpoint0 (control pipe) -*/ -VOID usbClearOEP0ByteCount(VOID); - -/** -Send stall handshake for out-endpoint0 (control pipe) -*/ -VOID usbStallOEP0(VOID); - -/** -Send further data over control pipe if needed. - Function is called from control-in IRQ. Do not call from user application -*/ -VOID usbSendNextPacketOnIEP0(VOID); - -/** -Send data over control pipe to host. - Number of bytes to transmit should be set with - global varible "wBytesRemainingOnIEP0" before function is called. -*/ -VOID usbSendDataPacketOnEP0(PBYTE pbBuffer); - -/** -Receive further data from control pipe if needed. - Function is called from control-out IRQ. Do not call from user application -*/ -VOID usbReceiveNextPacketOnOEP0(VOID); - -/** -Receive data from control pipe. - Number of bytes to receive should be set with - global varible "wBytesRemainingOnOEP0" before function is called. -*/ -VOID usbReceiveDataPacketOnEP0(PBYTE pbBuffer); - -/** -Send zero length packet on control pipe. -*/ -VOID usbSendZeroLengthPacketOnIEP0(VOID); - -/*Send data to host.*/ -BYTE MscSendData(const BYTE* data, WORD size); - -/** -Decode incoming usb setup packet and call corresponding function - usbDecodeAndProcessUsbRequest is called from IRQ. Do not call from user application -*/ -BYTE usbDecodeAndProcessUsbRequest(VOID); -VOID usbClearEndpointFeature(VOID); -VOID usbGetConfiguration(VOID); -VOID usbGetDeviceDescriptor(VOID); -VOID usbGetConfigurationDescriptor(VOID); -VOID usbGetStringDescriptor(VOID); -VOID usbGetInterface(VOID); -VOID usbGetDeviceStatus(VOID); -VOID usbGetEndpointStatus(VOID); -VOID usbGetInterfaceStatus(VOID); -VOID usbSetAddress(VOID); -VOID usbSetConfiguration(VOID); -VOID usbClearDeviceFeature(VOID); -VOID usbSetDeviceFeature(VOID); -VOID usbSetEndpointFeature(VOID); -VOID usbSetInterface(VOID); -VOID usbInvalidRequest(VOID); - - -#define ENUMERATION_COMPLETE 0x01 - -/*----------------------------------------------------------------------------+ -| End of header file | -+----------------------------------------------------------------------------*/ -#ifdef __cplusplus -} -#endif -#endif /* _USB_H */ -/*------------------------ Nothing Below This Line --------------------------*/ diff --git a/USB_API/USB_HID_API/UsbHid.c b/USB_API/USB_HID_API/UsbHid.c deleted file mode 100644 index 0282afb..0000000 --- a/USB_API/USB_HID_API/UsbHid.c +++ /dev/null @@ -1,932 +0,0 @@ -/* - * UsbHid.c - * - * USB HID send and receive functions - * - * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/*----------------------------------------------------------------------------+ -| | -| Texas Instruments | -| | -| MSP430 USB-Example (HID Driver) | -| | -+-----------------------------------------------------------------------------+ -| Source: UsbHid.c, File Version 1.00 2009/12/03 | -| Author: RSTO | -| | -| WHO WHEN WHAT | -| --- ---------- ------------------------------------------------ | -| RSTO 2009/02/20 ported from CdcHid | -| RSTO 2009/05/19 updated USBHID_intfStatus() | -| RSTO 2009/05/26 added USBHID_bytesInUSBBuffer() | -| RSTO 2009/05/28 changed USBHID_sendData() | -| RSTO 2009/06/09 updated USBHID_bytesInUSBBuffer() | -| MSP/Biju 2009/10/21 Changes for composite support | -| RSTO 2009/10/21 move __disable_interrupt() before | -| checking for suspend | -+----------------------------------------------------------------------------*/ - -#include "../USB_Common/device.h" -#include "../USB_Common/types.h" // Basic Type declarations -#include "../USB_Common/defMSP430USB.h" -#include "../USB_Common/usb.h" // USB-specific Data Structures -#include "UsbHid.h" -#include -#include - -#ifdef _HID_ - -//function pointers -extern VOID *(*USB_TX_memcpy)(VOID * dest, const VOID * source, size_t count); -extern VOID *(*USB_RX_memcpy)(VOID * dest, const VOID * source, size_t count); - -// Local Macros -#define INTFNUM_OFFSET(X) (X - HID0_INTFNUM) // Get the HID offset - -static struct _HidWrite -{ - WORD nHidBytesToSend; // holds counter of bytes to be sent - WORD nHidBytesToSendLeft; // holds counter how many bytes is still to be sent - const BYTE* pHidBufferToSend; // holds the buffer with data to be sent - BYTE bCurrentBufferXY; // indicates which buffer is to use next for for write into IN OUT endpoint -} HidWriteCtrl[HID_NUM_INTERFACES]; - -static struct _HidRead -{ - BYTE *pUserBuffer; // holds the current position of user's receiving buffer. If NULL- no receiving operation started - BYTE *pCurrentEpPos; // current positon to read of received data from curent EP - WORD nBytesToReceive; // holds how many bytes was requested by receiveData() to receive - WORD nBytesToReceiveLeft; // holds how many bytes is still requested by receiveData() to receive - BYTE * pCT1; // holds current EPBCTxx register - BYTE * pCT2; // holds next EPBCTxx register - BYTE * pEP2; // holds addr of the next EP buffer - BYTE nBytesInEp; // how many received bytes still available in current EP - BYTE bCurrentBufferXY; // indicates which buffer is used by host to transmit data via OUT endpoint -} HidReadCtrl[HID_NUM_INTERFACES]; - -extern WORD wUsbEventMask; - -/*----------------------------------------------------------------------------+ -| Global Variables | -+----------------------------------------------------------------------------*/ - -extern __no_init tEDB __data16 tInputEndPointDescriptorBlock[]; -extern __no_init tEDB __data16 tOutputEndPointDescriptorBlock[]; - - -VOID HidCopyUsbToBuff(BYTE* pEP, BYTE* pCT, BYTE); - -/*----------------------------------------------------------------------------+ -| Functions' implementatin | -+----------------------------------------------------------------------------*/ - -//resets internal HID data structure -VOID HidResetData() -{ - // indicates which buffer is used by host to transmit data via OUT endpoint3 - X buffer is first - //HidReadCtrl[intfIndex].bCurrentBufferXY = X_BUFFER; - - memset(&HidReadCtrl, 0, sizeof(HidReadCtrl)); - memset(&HidWriteCtrl, 0, sizeof(HidWriteCtrl)); -} - - -/* -Sends a pre-built report reportData to the host. - Returns: kUSBHID_sendComplete - kUSBHID_intfBusyError - kUSBCDC_busNotAvailable -*/ -BYTE USBHID_sendReport(const BYTE * reportData, BYTE intfNum) -{ - BYTE byte_count; - BYTE * pEP1; - BYTE * pCT1; - - BYTE edbIndex; - edbIndex = stUsbHandle[intfNum].edb_Index; - - // do not access USB memory if suspended (PLL off). It may produce BUS_ERROR - if ((bFunctionSuspended) || - (bEnumerationStatus != ENUMERATION_COMPLETE)) - { - return kUSBHID_busNotAvailable; - } - - if (HidWriteCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY == X_BUFFER) - { - //this is the active EP buffer - pEP1 = (BYTE*)stUsbHandle[intfNum].iep_X_Buffer; - pCT1 = &tInputEndPointDescriptorBlock[edbIndex].bEPBCTX; - } - else - { - //this is the active EP buffer - pEP1 = (BYTE*)stUsbHandle[intfNum].iep_Y_Buffer; - pCT1 = &tInputEndPointDescriptorBlock[edbIndex].bEPBCTY; - } - - byte_count = USBHID_REPORT_LENGTH; // we support only one length of report - - if(*pCT1 & EPBCNT_NAK) // if this EP is empty - { - USB_TX_memcpy(pEP1, reportData, byte_count); // copy data into IEP X or Y buffer - *pCT1 = byte_count; // Set counter for usb In-Transaction - HidWriteCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY = (HidWriteCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY+1)&0x01; //switch buffer - return kUSBHID_sendComplete; - } - return kUSBHID_intfBusyError; -} - -/* -Receives report reportData from the host. -Return: kUSBHID_receiveCompleted - kUSBHID_generalError - kUSBCDC_busNotAvailable -*/ -BYTE USBHID_receiveReport(BYTE * reportData, BYTE intfNum) -{ - BYTE ret = kUSBHID_generalError; - BYTE nTmp1 = 0; - - BYTE edbIndex; - edbIndex = stUsbHandle[intfNum].edb_Index; - - // do not access USB memory if suspended (PLL off). It may produce BUS_ERROR - if ((bFunctionSuspended) || - (bEnumerationStatus != ENUMERATION_COMPLETE)) - { - return kUSBHID_busNotAvailable; - } - - if (HidReadCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY == X_BUFFER) //this is current buffer - { - if (tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX & EPBCNT_NAK) //this buffer has a valid data packet - { - //this is the active EP buffer - //pEP1 - HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCurrentEpPos = (BYTE*)stUsbHandle[intfNum].oep_X_Buffer; - HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 = &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX; - - //second EP buffer - HidReadCtrl[INTFNUM_OFFSET(intfNum)].pEP2 = (BYTE*)stUsbHandle[intfNum].oep_Y_Buffer; - HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2 = &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY; - nTmp1 = 1; //indicate that data is available - } - } - else // Y_BUFFER - { - if (tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY & EPBCNT_NAK) - { - //this is the active EP buffer - HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCurrentEpPos = (BYTE*)stUsbHandle[intfNum].oep_Y_Buffer; - HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 = &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY; - - //second EP buffer - HidReadCtrl[INTFNUM_OFFSET(intfNum)].pEP2 = (BYTE*)stUsbHandle[intfNum].oep_X_Buffer; - HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2 = &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX; - nTmp1 = 1; //indicate that data is available - } - } - - if (nTmp1) - { - // how many byte we can get from one endpoint buffer - nTmp1 = *HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1; - - if(nTmp1 & EPBCNT_NAK) - { - nTmp1 = nTmp1 &0x7f; // clear NAK bit - HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = nTmp1; // holds how many valid bytes in the EP buffer - - USB_RX_memcpy(reportData, HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCurrentEpPos, nTmp1); - //memcpy(reportData, HidReadCtrl.pEP1, nTmp1); - HidReadCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY = (HidReadCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY+1) &0x01; - HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = 0; - *HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 = 0; // clear NAK, EP ready to receive data - - ret = kUSBHID_receiveCompleted; - } - } - return ret; -} - - -/* -Sends data over interface intfNum, of size size and starting at address data. -Returns: kUSBHID_sendStarted - kUSBHID_sendComplete - kUSBHID_intBusyError -*/ -BYTE USBHID_sendData(const BYTE* data, WORD size, BYTE intfNum) -{ - unsigned short bGIE; - BYTE edbIndex; - edbIndex = stUsbHandle[intfNum].edb_Index; - - if (size == 0) - { - return kUSBHID_generalError; - } - - bGIE = (__get_SR_register() &GIE); //save interrupt status - - // atomic operation - disable interrupts - __disable_interrupt(); // Disable global interrupts - - // do not access USB memory if suspended (PLL off). It may produce BUS_ERROR - if ((bFunctionSuspended) || - (bEnumerationStatus != ENUMERATION_COMPLETE)) - { - // data can not be read because of USB suspended - __bis_SR_register(bGIE); //restore interrupt status - return kUSBHID_busNotAvailable; - } - - if (HidWriteCtrl[INTFNUM_OFFSET(intfNum)].nHidBytesToSendLeft != 0) - { - // the USB still sends previous data, we have to wait - __bis_SR_register(bGIE); //restore interrupt status - return kUSBHID_intfBusyError; - } - - //This function generate the USB interrupt. The data will be sent out from interrupt - - HidWriteCtrl[INTFNUM_OFFSET(intfNum)].nHidBytesToSend = size; - HidWriteCtrl[INTFNUM_OFFSET(intfNum)].nHidBytesToSendLeft = size; - HidWriteCtrl[INTFNUM_OFFSET(intfNum)].pHidBufferToSend = data; - - //trigger Endpoint Interrupt - to start send operation - USBIEPIFG |= 1<<(edbIndex+1); //IEPIFGx; - - __bis_SR_register(bGIE); //restore interrupt status - - return kUSBHID_sendStarted; -} - -//this function is used only by USB interrupt -BOOL HidToHostFromBuffer(BYTE intfNum) -{ - BYTE byte_count, nTmp2; - BYTE * pEP1; - BYTE * pEP2; - BYTE * pCT1; - BYTE * pCT2; - BYTE bWakeUp = FALSE; // per default we do not wake up after interrupt - - BYTE edbIndex; - edbIndex = stUsbHandle[intfNum].edb_Index; - - if (HidWriteCtrl[INTFNUM_OFFSET(intfNum)].nHidBytesToSendLeft == 0) // do we have somtething to send? - { - - HidWriteCtrl[INTFNUM_OFFSET(intfNum)].nHidBytesToSend = 0; - - //call event callback function - if (wUsbEventMask & kUSB_sendCompletedEvent) - { - bWakeUp = USBHID_handleSendCompleted(intfNum); - } - return bWakeUp; - } - - if(!(tInputEndPointDescriptorBlock[edbIndex].bEPCNF & EPCNF_TOGGLE)) - { - //this is the active EP buffer - pEP1 = (BYTE*)stUsbHandle[intfNum].iep_X_Buffer; - pCT1 = &tInputEndPointDescriptorBlock[edbIndex].bEPBCTX; - - //second EP buffer - pEP2 = (BYTE*)stUsbHandle[intfNum].iep_Y_Buffer; - pCT2 = &tInputEndPointDescriptorBlock[edbIndex].bEPBCTY; - } - else - { - //this is the active EP buffer - pEP1 = (BYTE*)stUsbHandle[intfNum].iep_Y_Buffer; - pCT1 = &tInputEndPointDescriptorBlock[edbIndex].bEPBCTY; - - //second EP buffer - pEP2 = (BYTE*)stUsbHandle[intfNum].iep_X_Buffer; - pCT2 = &tInputEndPointDescriptorBlock[edbIndex].bEPBCTX; - } - - // how many byte we can send over one endpoint buffer - // 2 bytes a reserved: [0] - HID Report Descriptor, [1] - count of valid bytes - byte_count = (HidWriteCtrl[INTFNUM_OFFSET(intfNum)].nHidBytesToSendLeft > EP_MAX_PACKET_SIZE-2) ? EP_MAX_PACKET_SIZE-2 : HidWriteCtrl[INTFNUM_OFFSET(intfNum)].nHidBytesToSendLeft; - nTmp2 = *pCT1; - - if(nTmp2 & EPBCNT_NAK) - { - USB_TX_memcpy(pEP1+2, HidWriteCtrl[INTFNUM_OFFSET(intfNum)].pHidBufferToSend, byte_count); // copy data into IEP3 X or Y buffer - pEP1[0] = 0x3F; // set HID report descriptor: 0x3F - pEP1[1] = byte_count; // set HID report descriptor - - // 64 bytes will be send: we use only one HID report descriptor - *pCT1 = 0x40; // Set counter for usb In-Transaction - - HidWriteCtrl[INTFNUM_OFFSET(intfNum)].nHidBytesToSendLeft -= byte_count; - HidWriteCtrl[INTFNUM_OFFSET(intfNum)].pHidBufferToSend += byte_count; // move buffer pointer - - //try to send data over second buffer - nTmp2 = *pCT2; - if ((HidWriteCtrl[INTFNUM_OFFSET(intfNum)].nHidBytesToSendLeft > 0) && // do we have more data to send? - (nTmp2 & EPBCNT_NAK)) // if the second buffer is free? - { - // how many byte we can send over one endpoint buffer - byte_count = (HidWriteCtrl[INTFNUM_OFFSET(intfNum)].nHidBytesToSendLeft > EP_MAX_PACKET_SIZE-2) ? EP_MAX_PACKET_SIZE-2 : HidWriteCtrl[INTFNUM_OFFSET(intfNum)].nHidBytesToSendLeft; - - USB_TX_memcpy(pEP2+2, HidWriteCtrl[INTFNUM_OFFSET(intfNum)].pHidBufferToSend, byte_count); // copy data into IEP3 X or Y buffer - pEP2[0] = 0x3F; // set HID report descriptor: 0x3F - pEP2[1] = byte_count; // set byte count of valid data - - // 64 bytes will be send: we use only one HID report descriptor - *pCT2 = 0x40; // Set counter for usb In-Transaction - - HidWriteCtrl[INTFNUM_OFFSET(intfNum)].nHidBytesToSendLeft -= byte_count; - HidWriteCtrl[INTFNUM_OFFSET(intfNum)].pHidBufferToSend += byte_count; // move buffer pointer - } - } - return bWakeUp; -} - -/* -Aborts an active send operation on interface intfNum. -Returns the number of bytes that were sent prior to the abort, in size. -*/ -BYTE USBHID_abortSend(WORD* size, BYTE intfNum) -{ - unsigned short bGIE; - bGIE = (__get_SR_register() &GIE); //save interrupt status - - __disable_interrupt(); //disable interrupts - atomic operation - - *size = (HidWriteCtrl[INTFNUM_OFFSET(intfNum)].nHidBytesToSend - HidWriteCtrl[INTFNUM_OFFSET(intfNum)].nHidBytesToSendLeft); - HidWriteCtrl[INTFNUM_OFFSET(intfNum)].nHidBytesToSend = 0; - HidWriteCtrl[INTFNUM_OFFSET(intfNum)].nHidBytesToSendLeft = 0; - - __bis_SR_register(bGIE); //restore interrupt status - return kUSB_succeed; -} - -// This function copies data from OUT endpoint into user's buffer -// Arguments: -// pEP - pointer to EP to copy from -// pCT - pointer to pCT control reg -// -VOID HidCopyUsbToBuff(BYTE* pEP, BYTE* pCT,BYTE intfNum) -{ - BYTE nCount; - - // how many byte we can get from one endpoint buffer - nCount = (HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft > HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp) ? HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp : HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft; - - USB_RX_memcpy(HidReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer, pEP, nCount); // copy data from OEPx X or Y buffer - HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft -= nCount; - HidReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer += nCount; // move buffer pointer - // to read rest of data next time from this place - - if (nCount == HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp) // all bytes are copied from receive buffer? - { - //switch current buffer - HidReadCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY = (HidReadCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY+1) &0x01; - - HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = 0; - - //clear NAK, EP ready to receive data - *pCT = 0; - } - else - { - HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp -= nCount; - HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCurrentEpPos = pEP + nCount; - } -} - - -/* -Receives data over interface intfNum, of size size, into memory starting at address data. -Returns: - kUSBHID_receiveStarted if the receiving process started. - kUSBHID_receiveCompleted all requested date are received. - kUSBHID_receiveInProgress previous receive opereation is in progress. The requested receive operation can be not started. - kUSBHID_generalError error occurred. -*/ -BYTE USBHID_receiveData(BYTE* data, WORD size, BYTE intfNum) -{ - BYTE nTmp1; - unsigned short bGIE; - BYTE edbIndex; - edbIndex = stUsbHandle[intfNum].edb_Index; - - if ((size == 0) || // read size is 0 - (data == NULL)) - { - return kUSBHID_generalError; - } - - bGIE = (__get_SR_register() &GIE); //save interrupt status - - // atomic operation - disable interrupts - __disable_interrupt(); // Disable global interrupts - - // do not access USB memory if suspended (PLL off). It may produce BUS_ERROR - if ((bFunctionSuspended) || - (bEnumerationStatus != ENUMERATION_COMPLETE)) - { - __bis_SR_register(bGIE); //restore interrupt status - return kUSBHID_busNotAvailable; - } - - if (HidReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer != NULL) // receive process already started - { - __bis_SR_register(bGIE); //restore interrupt status - return kUSBHID_receiveInProgress; - } - - HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceive = size; // bytes to receive - HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft = size; // left bytes to receive - HidReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer = data; // set user receive buffer - - //read rest of data from buffer, if any - if (HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp > 0) - { - // copy data from pEP-endpoint into User's buffer - HidCopyUsbToBuff(HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCurrentEpPos, HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1,intfNum); - - if (HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft == 0) // the Receive opereation is completed - { - HidReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer = NULL; // no more receiving pending - USBHID_handleReceiveCompleted(intfNum); // call event handler in interrupt context - __bis_SR_register(bGIE); //restore interrupt status - return kUSBHID_receiveCompleted; // receive completed - } - - // check other EP buffer for data - exchange pCT1 with pCT2 - if (HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 == &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX) - { - HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 = &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY; - HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCurrentEpPos = (BYTE*)stUsbHandle[intfNum].oep_Y_Buffer; - } - else - { - HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 = &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX; - HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCurrentEpPos = (BYTE*)stUsbHandle[intfNum].oep_X_Buffer; - } - nTmp1 = *HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1; - //try read data from second buffer - if (nTmp1 & EPBCNT_NAK) // if the second buffer has received data? - { - nTmp1 = nTmp1 &0x7f; // clear NAK bit - HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = *(HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCurrentEpPos+1); // holds how many valid bytes in the EP buffer - if (HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp > nTmp1-2) - { - HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = nTmp1-2; - } - HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCurrentEpPos += 2; // here starts user data - HidCopyUsbToBuff(HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCurrentEpPos, HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1,intfNum); - } - - if (HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft == 0) // the Receive opereation is completed - { - HidReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer = NULL; // no more receiving pending - USBHID_handleReceiveCompleted(intfNum); // call event handler in interrupt context - __bis_SR_register(bGIE); //restore interrupt status - return kUSBHID_receiveCompleted; // receive completed - } - } //read rest of data from buffer, if any - - //read 'fresh' data, if available - nTmp1 = 0; - if (HidReadCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY == X_BUFFER) //this is current buffer - { - if (tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX & EPBCNT_NAK) //this buffer has a valid data packet - { - //this is the active EP buffer - //pEP1 - HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCurrentEpPos = (BYTE*)stUsbHandle[intfNum].oep_X_Buffer; - HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 = &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX; - - //second EP buffer - HidReadCtrl[INTFNUM_OFFSET(intfNum)].pEP2 = (BYTE*)stUsbHandle[intfNum].oep_Y_Buffer; - HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2 = &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY; - nTmp1 = 1; //indicate that data is available - } - } - else // Y_BUFFER - { - if (tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY & EPBCNT_NAK) - { - //this is the active EP buffer - HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCurrentEpPos = (BYTE*)stUsbHandle[intfNum].oep_Y_Buffer; - HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 = &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY; - - //second EP buffer - HidReadCtrl[INTFNUM_OFFSET(intfNum)].pEP2 = (BYTE*)stUsbHandle[intfNum].oep_X_Buffer; - HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2 = &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX; - nTmp1 = 1; //indicate that data is available - } - } - - if (nTmp1) - { - // how many byte we can get from one endpoint buffer - nTmp1 = *HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1; - - if(nTmp1 & EPBCNT_NAK) - { - nTmp1 = nTmp1 &0x7f; // clear NAK bit - HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = *(HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCurrentEpPos+1); // holds how many valid bytes in the EP buffer - if (HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp > nTmp1-2) - { - HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = nTmp1-2; - } - HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCurrentEpPos += 2; // here starts user data - HidCopyUsbToBuff(HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCurrentEpPos, HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1,intfNum); - - nTmp1 = *HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2; - //try read data from second buffer - if ((HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft > 0) && // do we have more data to receive? - (nTmp1 & EPBCNT_NAK)) // if the second buffer has received data? - { - nTmp1 = nTmp1 &0x7f; // clear NAK bit - HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = *(HidReadCtrl[INTFNUM_OFFSET(intfNum)].pEP2+1); // holds how many valid bytes in the EP buffer - if (HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp > nTmp1-2) - { - HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = nTmp1-2; - } - HidReadCtrl[INTFNUM_OFFSET(intfNum)].pEP2 += 2; // here starts user data - HidCopyUsbToBuff(HidReadCtrl[INTFNUM_OFFSET(intfNum)].pEP2, HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2,intfNum); - HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 = HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2; - } - } - } - - if (HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft == 0) // the Receive opereation is completed - { - HidReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer = NULL; // no more receiving pending - USBHID_handleReceiveCompleted(intfNum); // call event handler in interrupt context - __bis_SR_register(bGIE); //restore interrupt status - return kUSBHID_receiveCompleted; - } - - //interrupts enable - __bis_SR_register(bGIE); //restore interrupt status - return kUSBHID_receiveStarted; -} - -//this function is used only by USB interrupt. -//It fills user receiving buffer with received data -BOOL HidToBufferFromHost(BYTE intfNum) -{ - BYTE * pEP1; - BYTE nTmp1; - BYTE bWakeUp = FALSE; // per default we do not wake up after interrupt - - BYTE edbIndex; - edbIndex = stUsbHandle[intfNum].edb_Index; - - if (HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft == 0) // do we have somtething to receive? - { - HidReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer = NULL; // no more receiving pending - return bWakeUp; - } - - // No data to receive... - if (!((tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX | - tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY) - & 0x80)) - { - return bWakeUp; - } - - if (HidReadCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY == X_BUFFER) //X is current buffer - { - //this is the active EP buffer - pEP1 = (BYTE*)stUsbHandle[intfNum].oep_X_Buffer; - HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 = &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX; - - //second EP buffer - HidReadCtrl[INTFNUM_OFFSET(intfNum)].pEP2 = (BYTE*)stUsbHandle[intfNum].oep_Y_Buffer; - HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2 = &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY; - } - else - { - //this is the active EP buffer - pEP1 = (BYTE*)stUsbHandle[intfNum].oep_Y_Buffer; - HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 = &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY; - - //second EP buffer - HidReadCtrl[INTFNUM_OFFSET(intfNum)].pEP2 = (BYTE*)stUsbHandle[intfNum].oep_X_Buffer; - HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2 = &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX; - } - - // how many byte we can get from one endpoint buffer - nTmp1 = *HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1; - - if(nTmp1 & EPBCNT_NAK) - { - nTmp1 = nTmp1 &0x7f; // clear NAK bit - HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = *(pEP1+1); // holds how many valid bytes in the EP buffer - if (HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp > nTmp1-2) - { - HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = nTmp1-2; - } - pEP1 += 2; // here starts user data - HidCopyUsbToBuff(pEP1, HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1,intfNum); - - nTmp1 = *HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2; - //try read data from second buffer - if ((HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft > 0) && // do we have more data to send? - (nTmp1 & EPBCNT_NAK)) // if the second buffer has received data? - { - nTmp1 = nTmp1 &0x7f; // clear NAK bit - HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = *(pEP1+1); // holds how many valid bytes in the EP buffer - if (HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp > nTmp1-2) - { - HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = nTmp1-2; - } - HidReadCtrl[INTFNUM_OFFSET(intfNum)].pEP2 += 2; // here starts user data - HidCopyUsbToBuff(HidReadCtrl[INTFNUM_OFFSET(intfNum)].pEP2, HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2,intfNum); - HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 = HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2; - } - } - - if (HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft == 0) // the Receive opereation is completed - { - HidReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer = NULL; // no more receiving pending - if (wUsbEventMask & kUSB_receiveCompletedEvent) - { - bWakeUp = USBHID_handleReceiveCompleted(intfNum); - } - - if (HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp) // Is not read data still available in the EP? - { - if (wUsbEventMask & kUSB_dataReceivedEvent) - { - bWakeUp = USBHID_handleDataReceived(intfNum); - } - } - } - return bWakeUp; -} - -// helper for USB interrupt handler -BOOL HidIsReceiveInProgress(BYTE intfNum) -{ - return (HidReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer != NULL); -} - - -/* -Aborts an active receive operation on interface intfNum. - Returns the number of bytes that were received and transferred - to the data location established for this receive operation. -*/ -BYTE USBHID_abortReceive(WORD* size, BYTE intfNum) -{ - unsigned short bGIE; - - bGIE = (__get_SR_register() &GIE); //save interrupt status - __disable_interrupt(); //disable interrupts - atomic operation - - *size = 0; //set received bytes count to 0 - - //is receive operation underway? - if (HidReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer) - { - //how many bytes are already received? - *size = HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceive - HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft; - - HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = 0; - HidReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer = NULL; - HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft = 0; - } - - //restore interrupt status - __bis_SR_register(bGIE); //restore interrupt status - return kUSB_succeed; -} - -/* -This function rejects payload data that has been received from the host. -*/ -BYTE USBHID_rejectData(BYTE intfNum) -{ - unsigned short bGIE; - BYTE edbIndex; - edbIndex = stUsbHandle[intfNum].edb_Index; - - bGIE = (__get_SR_register() &GIE); //save interrupt status - - //interrupts disable - __disable_interrupt(); - - // do not access USB memory if suspended (PLL off). It may produce BUS_ERROR - if (bFunctionSuspended) - { - __bis_SR_register(bGIE); //restore interrupt status - return kUSBHID_busNotAvailable; - } - - //Is receive operation underway? - // - do not flush buffers if any operation still active. - if (!HidReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer) - { - BYTE tmp1 = tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX & EPBCNT_NAK; - BYTE tmp2 = tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY & EPBCNT_NAK; - - if (tmp1 ^ tmp2) // switch current buffer if any and only ONE of the buffers is full - { - //switch current buffer - HidReadCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY = (HidReadCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY+1) &0x01; - } - - tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX = 0; //flush buffer X - tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY = 0; //flush buffer Y - HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = 0; // indicates that no more data available in the EP - } - - __bis_SR_register(bGIE); //restore interrupt status - return kUSB_succeed; -} - -/* -This function indicates the status of the interface intfNum. - If a send operation is active for this interface, - the function also returns the number of bytes that have been transmitted to the host. - If a receiver operation is active for this interface, the function also returns - the number of bytes that have been received from the host and are waiting at the assigned address. - -returns kUSBHID_waitingForSend (indicates that a call to USBHID_SendData() - has been made, for which data transfer has not been completed) - -returns kUSBHID_waitingForReceive (indicates that a receive operation - has been initiated, but not all data has yet been received) - -returns kUSBHID_dataWaiting (indicates that data has been received - from the host, waiting in the USB receive buffers) -*/ -BYTE USBHID_intfStatus(BYTE intfNum, WORD* bytesSent, WORD* bytesReceived) -{ - BYTE ret = 0; - unsigned short bGIE; - BYTE edbIndex; - - *bytesSent = 0; - *bytesReceived = 0; - - edbIndex = stUsbHandle[intfNum].edb_Index; - - bGIE = (__get_SR_register() &GIE); //save interrupt status - __disable_interrupt(); //disable interrupts - atomic operation - - // Is send operation underway? - if (HidWriteCtrl[INTFNUM_OFFSET(intfNum)].nHidBytesToSendLeft != 0) - { - ret |= kUSBHID_waitingForSend; - *bytesSent = HidWriteCtrl[INTFNUM_OFFSET(intfNum)].nHidBytesToSend - HidWriteCtrl[INTFNUM_OFFSET(intfNum)].nHidBytesToSendLeft; - } - - //Is receive operation underway? - if (HidReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer != NULL) - { - ret |= kUSBHID_waitingForReceive; - *bytesReceived = HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceive - HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft; - } - else // not receive operation started - { - // do not access USB memory if suspended (PLL off). It may produce BUS_ERROR - if (!bFunctionSuspended) - { - if((tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX & EPBCNT_NAK) | //any of buffers has a valid data packet - (tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY & EPBCNT_NAK)) - { - ret |= kUSBHID_dataWaiting; - } - } - } - - if ((bFunctionSuspended) || - (bEnumerationStatus != ENUMERATION_COMPLETE)) - { - // if suspended or not enumerated - report no other tasks pending - ret = kUSBHID_busNotAvailable; - } - - //restore interrupt status - __bis_SR_register(bGIE); //restore interrupt status - - return ret; -} - -/* -Returns how many bytes are in the buffer are received and ready to be read. -*/ -BYTE USBHID_bytesInUSBBuffer(BYTE intfNum) -{ - BYTE bTmp1 = 0; - BYTE bTmp2; - - BYTE edbIndex; - unsigned short bGIE; - - bGIE = (__get_SR_register() &GIE); //save interrupt status - - edbIndex = stUsbHandle[intfNum].edb_Index; - - //interrupts disable - __disable_interrupt(); - - if ((bFunctionSuspended) || - (bEnumerationStatus != ENUMERATION_COMPLETE)) - { - // if suspended or not enumerated - report 0 bytes available - __bis_SR_register(bGIE); //restore interrupt status - return 0; - } - - if (HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp > 0) // If a RX operation is underway, part of data may was read of the OEP buffer - { - bTmp1 = HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp; - if (*HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2 & EPBCNT_NAK) // the next buffer has a valid data packet - { - bTmp2 = *(HidReadCtrl[INTFNUM_OFFSET(intfNum)].pEP2+1); // holds how many valid bytes in the EP buffer - if (bTmp2 > (*HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2 & 0x7F) -2) // check if all data received correctly - { - bTmp1 += (*HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2 & 0x7F) -2; - } - else - { - bTmp1 += bTmp2; - } - } - } - else - { - if (tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX & EPBCNT_NAK) //this buffer has a valid data packet - { - bTmp2 = tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX & 0x7F; - bTmp1 = *((BYTE*)stUsbHandle[intfNum].oep_X_Buffer+1); - if (bTmp2-2 < bTmp1) // check if the count (second byte) is valid - { - bTmp1 = bTmp2 - 2; - } - } - if (tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY & EPBCNT_NAK) //this buffer has a valid data packet - { - bTmp2 = tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY & 0x7F; - if (bTmp2-2 > *((BYTE*)stUsbHandle[intfNum].oep_Y_Buffer+1)) // check if the count (second byte) is valid - { - bTmp1 += *((BYTE*)stUsbHandle[intfNum].oep_Y_Buffer+1); - } - else - { - bTmp1 += bTmp2 - 2; - } - } - } - - //interrupts enable - __bis_SR_register(bGIE); //restore interrupt status - return bTmp1; -} - -#endif //ifdef _HID_ - -/*----------------------------------------------------------------------------+ -| End of source file | -+----------------------------------------------------------------------------*/ -/*------------------------ Nothing Below This Line --------------------------*/ diff --git a/USB_API/USB_HID_API/UsbHid.h b/USB_API/USB_HID_API/UsbHid.h deleted file mode 100644 index c3de0d8..0000000 --- a/USB_API/USB_HID_API/UsbHid.h +++ /dev/null @@ -1,180 +0,0 @@ -/* - * UsbHid.h - * - * USB HID send and receive functions - * - * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/*----------------------------------------------------------------------------+ -| | -| Texas Instruments | -| | -| MSP430 USB-Example (HID Driver) | -| | -+-----------------------------------------------------------------------------+ -| Source: UsbHid.h, File Version 1.00 2009/12/03 | -| Author: RSTO | -| | -| WHO WHEN WHAT | -| --- ---------- ------------------------------------------------ | -| RSTO 2009/02/20 portet from UsbCdc.h | -| RSTO 2009/05/15 added param to USBHID_rejectData() | -| RSTO 2009/05/26 added USBHID_bytesInUSBBuffer() | -+----------------------------------------------------------------------------*/ -#ifndef _UsbHid_H_ -#define _UsbHid_H_ - -#ifdef __cplusplus -extern "C" -{ -#endif - - -#define kUSBHID_sendStarted 0x01 -#define kUSBHID_sendComplete 0x02 -#define kUSBHID_intfBusyError 0x03 -#define kUSBHID_receiveStarted 0x04 -#define kUSBHID_receiveCompleted 0x05 -#define kUSBHID_receiveInProgress 0x06 -#define kUSBHID_generalError 0x07 -#define kUSBHID_busNotAvailable 0x08 - -/*---------------------------------------------------------------------------- -These functions can be used in application -+----------------------------------------------------------------------------*/ - -/* -Sends a pre-built report reportData to the host. - Returns: kUSBHID_sendComplete - kUSBHID_intfBusyError - kUSBHID_busSuspended -*/ -BYTE USBHID_sendReport(const BYTE * reportData, BYTE intfNum); - -/* -Receives report reportData from the host. -Return: kUSBHID_receiveCompleted - kUSBHID_generalError - kUSBHID_busSuspended -*/ -BYTE USBHID_receiveReport(BYTE * reportData, BYTE intfNum); - -/* -Sends data over interface intfNum, of size size and starting at address data. - Returns: kUSBHID_sendStarted - kUSBHID_sendComplete - kUSBHID_intfBusyError -*/ -BYTE USBHID_sendData(const BYTE* data, WORD size, BYTE intfNum); - -/* -Receives data over interface intfNum, of size size, into memory starting at address data. -*/ -BYTE USBHID_receiveData(BYTE* data, WORD size, BYTE intfNum); - -/* -Aborts an active receive operation on interface intfNum. - size: the number of bytes that were received and transferred - to the data location established for this receive operation. -*/ -BYTE USBHID_abortReceive(WORD* size, BYTE intfNum); - - -#define kUSBHID_noDataWaiting 1 //returned by USBHID_rejectData() if no data pending - -/* -This function rejects payload data that has been received from the host. -*/ -BYTE USBHID_rejectData(BYTE intfNum); - -/* -Aborts an active send operation on interface intfNum. Returns the number of bytes that were sent prior to the abort, in size. -*/ -BYTE USBHID_abortSend(WORD* size, BYTE intfNum); - - -#define kUSBHID_waitingForSend 0x01 -#define kUSBHID_waitingForReceive 0x02 -#define kUSBHID_dataWaiting 0x04 -#define kUSBHID_busNotAvailable 0x08 -/* -This function indicates the status of the interface intfNum. - If a send operation is active for this interface, - the function also returns the number of bytes that have been transmitted to the host. - If a receiver operation is active for this interface, the function also returns - the number of bytes that have been received from the host and are waiting at the assigned address. - -returns kUSBHID_waitingForSend (indicates that a call to USBHID_SendData() - has been made, for which data transfer has not been completed) - -returns kUSBHID_waitingForReceive (indicates that a receive operation - has been initiated, but not all data has yet been received) - -returns kUSBHID_dataWaiting (indicates that data has been received - from the host, waiting in the USB receive buffers) -*/ -BYTE USBHID_intfStatus(BYTE intfNum, WORD* bytesSent, WORD* bytesReceived); - -/* -Returns how many bytes are in the buffer are received and ready to be read. -*/ -BYTE USBHID_bytesInUSBBuffer(BYTE intfNum); - -/*---------------------------------------------------------------------------- -Event-Handling routines -+----------------------------------------------------------------------------*/ - -/* -This event indicates that data has been received for port port, but no data receive operation is underway. -returns TRUE to keep CPU awake -*/ -BYTE USBHID_handleDataReceived(BYTE intfNum); - -/* -This event indicates that a send operation on port port has just been completed. -returns TRUE to keep CPU awake -*/ -BYTE USBHID_handleSendCompleted(BYTE intfNum); - -/* -This event indicates that a receive operation on port port has just been completed. -returns TRUE to keep CPU awake -*/ -BYTE USBHID_handleReceiveCompleted(BYTE intfNum); - - -#ifdef __cplusplus -} -#endif -#endif //_UsbHid_H_ diff --git a/USB_API/USB_HID_API/UsbHidReportHandler.c b/USB_API/USB_HID_API/UsbHidReportHandler.c deleted file mode 100644 index 6e12cf9..0000000 --- a/USB_API/USB_HID_API/UsbHidReportHandler.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * UsbHidReportHandler.c - * - * USB HID functions for Report Handler - * - * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/*----------------------------------------------------------------------------+ -| | -| Texas Instruments | -| | -| MSP430 USB-Example (HID Driver) | -| | -+-----------------------------------------------------------------------------+ -| Source: HidReportHandler.c, File Version 1.00 2009/12/03 | -| Author: RSTO | -| | -| WHO WHEN WHAT | -| --- ---------- ------------------------------------------------ | -| RSTO 2009/03/03 born | -| RSTO 2009/07/17 added __data16 qualifier for USB buffers | -+----------------------------------------------------------------------------*/ - -#include "../USB_Common/device.h" -#include "../USB_Common/types.h" // Basic Type declarations -#include "../USB_Common/defMSP430USB.h" -#include "../USB_Common/usb.h" // USB-specific Data Structures -#include "UsbHidReportHandler.h" -#include - -#ifdef _HID_ - -extern __no_init tEDB0 __data16 tEndPoint0DescriptorBlock; -extern __no_init tEDB __data16 tInputEndPointDescriptorBlock[]; -extern __no_init tEDB __data16 tOutputEndPointDescriptorBlock[]; - - -//---------------------------------------------------------------------------- - -VOID Handler_InReport(VOID) -{ -} - -//---------------------------------------------------------------------------- - -VOID Handler_InFeature(VOID) -{ - switch((BYTE)tSetupPacket.wValue) // tSetupPacket.wValue is contains HID-Report-ID - { - case 1: - // user's specified code... - break; - - case 2: - // user's specified code... - break; - - default:; - } - usbSendDataPacketOnEP0((PBYTE)&abUsbRequestReturnData); -} - -//---------------------------------------------------------------------------- - -VOID Handler_OutReport(VOID) -{ -} - -//---------------------------------------------------------------------------- - -VOID Handler_OutFeature(VOID) -{ - switch((BYTE)tSetupPacket.wValue) // tSetupPacket.wValue is contains HID-Report-ID - { - case 1: - // user's specified code... - break; - - case 2: - // user's specified code... - break; - - default:; - } -} - -#endif //_HID_ -/*----------------------------------------------------------------------------+ -| End of source file | -+----------------------------------------------------------------------------*/ -/*------------------------ Nothing Below This Line --------------------------*/ diff --git a/USB_API/USB_HID_API/UsbHidReportHandler.h b/USB_API/USB_HID_API/UsbHidReportHandler.h deleted file mode 100644 index 0e6021b..0000000 --- a/USB_API/USB_HID_API/UsbHidReportHandler.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * UsbHidReportHandler.h - * - * USB HID functions for Report Handler - * - * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/*----------------------------------------------------------------------------+ -| | -| Texas Instruments | -| | -| MSP430 USB-Example (HID Driver) | -| | -+-----------------------------------------------------------------------------+ -| Source: HidReportHandler.h, File Version 1.00 2009/12/03 | -| Author: RSTO | -| | -| WHO WHEN WHAT | -| --- ---------- ------------------------------------------------ | -| RSTO 2009/03/03 born | -+----------------------------------------------------------------------------*/ - -#ifndef _HidReportHandler_H_ -#define _HidReportHandler_H_ - -#ifdef __cplusplus -extern "C" -{ -#endif - -/** -Parses setup packet for report id and call function which belongs to report id - Called function will generate InReport. -*/ -VOID Handler_InReport(VOID); - -/** -Parses setup packet for report id and call function which belongs to report id -Called function will generate InFeatureReport. -*/ -VOID Handler_InFeature(VOID); - -/** -Parses setup packet for report id and call function which belongs to report id. -*/ -VOID Handler_OutReport(VOID); - -/** -Parses setup packet for report id and call function which belongs to report id. -*/ -VOID Handler_OutFeature(VOID); - -#ifdef __cplusplus -} -#endif -#endif //_HidReportHandler_H_ diff --git a/USB_API/USB_HID_API/UsbHidReq.c b/USB_API/USB_HID_API/UsbHidReq.c deleted file mode 100644 index b444d2f..0000000 --- a/USB_API/USB_HID_API/UsbHidReq.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - * UsbHidReq.c - * - * USB HID Request functions - * - * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/*----------------------------------------------------------------------------+ -| | -| Texas Instruments | -| | -| MSP430 USB-Example (HID Driver) | -| | -+-----------------------------------------------------------------------------+ -| Source: UsbHidReq.c, File Version 1.00 2009/12/03 | -| Author: RSTO | -| | -| WHO WHEN WHAT | -| --- ---------- ------------------------------------------------ | -| RSTO 2009/03/03 born | -| MSP/Biju 2009/10/21 Changes for composite support | -+----------------------------------------------------------------------------*/ - -#include "../USB_Common/device.h" -#include "../USB_Common/types.h" // Basic Type declarations -#include "../USB_Common/defMSP430USB.h" -#include "../USB_Common/usb.h" // USB-specific Data Structures -#include "UsbHidReportHandler.h" -#include - -#ifdef _HID_ - -VOID usbClearOEP0ByteCount(VOID); -VOID usbSendDataPacketOnEP0(PBYTE pbBuffer); -VOID usbReceiveDataPacketOnEP0(PBYTE pbBuffer); - - -VOID usbGetHidDescriptor(VOID) -{ - static BYTE intfNum; - if(intfNum >= HID_NUM_INTERFACES) - { - intfNum = 0; - } - usbClearOEP0ByteCount(); - wBytesRemainingOnIEP0 = 9; - usbSendDataPacketOnEP0((PBYTE)&abromConfigurationDescriptorGroup.stHid[intfNum].blength_hid_descriptor); - intfNum++; -} - -//---------------------------------------------------------------------------- -VOID usbGetReportDescriptor(VOID) -{ - wBytesRemainingOnIEP0 = SIZEOF_REPORT_DESCRIPTOR; - usbSendDataPacketOnEP0((PBYTE)&abromReportDescriptor); -} - -//---------------------------------------------------------------------------- - -VOID usbSetReport(VOID) -{ - usbReceiveDataPacketOnEP0((PBYTE) &abUsbRequestIncomingData); // receive data over EP0 from Host -} - -//---------------------------------------------------------------------------- - -VOID usbGetReport(VOID) -{ - switch((BYTE)tSetupPacket.wValue) - { - case USB_REQ_HID_FEATURE: - Handler_InFeature(); - break; - case USB_REQ_HID_INPUT: - Handler_InReport(); - break; - default:; - } -} - -#endif //_HID_ -/*----------------------------------------------------------------------------+ -| End of source file | -+----------------------------------------------------------------------------*/ -/*------------------------ Nothing Below This Line --------------------------*/ diff --git a/USB_API/USB_HID_API/UsbHidReq.h b/USB_API/USB_HID_API/UsbHidReq.h deleted file mode 100644 index 40731d1..0000000 --- a/USB_API/USB_HID_API/UsbHidReq.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * UsbHidReq.h - * - * USB HID Request functions - * - * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/*----------------------------------------------------------------------------+ -| | -| Texas Instruments | -| | -| MSP430 USB-Example (HID Driver) | -| | -+-----------------------------------------------------------------------------+ -| Source: UsbHidReq.h, File Version 1.00 2009/12/03 | -| Author: RSTO | -| | -| WHO WHEN WHAT | -| --- ---------- ------------------------------------------------ | -| RSTO 2009/03/03 born | -| MSP,Biju 2009/12/03 file versioning started | -+----------------------------------------------------------------------------*/ - -#ifndef _UsbHidReq_H_ -#define _UsbHidReq_H_ - -#ifdef __cplusplus -extern "C" -{ -#endif - - -/** -Return Hid descriptor to host over control endpoint -*/ -VOID usbGetHidDescriptor(VOID); -/** -Return HID report descriptor to host over control endpoint -*/ -VOID usbGetReportDescriptor(VOID); - - -/** -Receive Out-report from host -*/ -VOID usbSetReport(VOID); - -/** -Return In-report or In-feature-report to host over interrupt endpoint -*/ -VOID usbGetReport(VOID); - -#ifdef __cplusplus -} -#endif -#endif //_UsbHidReq_H_ diff --git a/USB_API/USB_MSC_API/UsbMsc.h b/USB_API/USB_MSC_API/UsbMsc.h deleted file mode 100644 index 1de929d..0000000 --- a/USB_API/USB_MSC_API/UsbMsc.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - * UsbMsc.h - * - * This file contains API declarations for function to use by User Application. - * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/*----------------------------------------------------------------------------+ - | | - | Texas Instruments | - | | - | MSP430 USB-Example (MSC Driver) | - | | - +-----------------------------------------------------------------------------+ - | Source: UsbMsc.h, File Version 1.01 | - | Description: This file contains API declarations for function to use by | - | User Application. | - | Author: RSTO | - | | - | WHO WHEN WHAT | - | --- ---------- ------------------------------------------------ | - | RSTO 2010/10/29 Created | - +----------------------------------------------------------------------------*/ -#ifndef _USB_MSC_H_ -#define _USB_MSC_H_ - -#include "UsbMscScsi.h" - -#ifdef __cplusplus -extern "C" -{ -#endif - -/*Return values of getState() and USBMSC_poll() API */ -#define kUSBMSC_idle 0 -#define kUSBMSC_readInProgress 1 -#define kUSBMSC_writeInProgress 2 -#define kUSBMSC_cmdBeingProcessed 3 -#define kUSBMSC_okToSleep 4 -#define kUSBMSC_processBuffer 5 - -/*----------------------------------------------------------------------------+ -| Function Prototypes | -+----------------------------------------------------------------------------*/ -/*Function to handle the MSC SCSI state machine */ -BYTE USBMSC_poll(VOID); - -/* MSC functions */ -BOOL MSCToHostFromBuffer(); -BOOL MSCFromHostToBuffer(); -BYTE USBMSC_bufferProcessed(VOID); -BYTE USBMSC_getState(); -BYTE USBMSC_updateMediaInfo(BYTE lun, struct USBMSC_mediaInfoStr *info); - -BYTE USBMSC_handleBufferEvent(VOID); -BYTE USBMSC_registerBufInfo( BYTE* RWbuf_x, BYTE* RWbuf_y, WORD size); - -#ifdef __cplusplus -} -#endif -#endif //_USB_MSC_H_ diff --git a/USB_API/USB_MSC_API/UsbMscReq.c b/USB_API/USB_MSC_API/UsbMscReq.c deleted file mode 100644 index 69dbe58..0000000 --- a/USB_API/USB_MSC_API/UsbMscReq.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Usb_Msc_Req.c - * - * This file contains the APIs specific to MSC class (Class specific requests) - * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/*----------------------------------------------------------------------------+ - | | - | Texas Instruments | - | | - | MSP430 USB-Example (MSC Driver) | - | | - +-----------------------------------------------------------------------------+ - | Source: Usb_Msc_Req.c, File Version 1.02 | - | Description: This file contains the APIs specific to MSC class | - | (Class specific requests) | - | Author: Biju,MSP | - | | - | WHO WHEN WHAT | - | --- ---------- ------------------------------------------------ | - | MSP 2010/02/01 born | - | Biju,MSP 2010/07/15 CV bug fix | | - +----------------------------------------------------------------------------*/ -/*----------------------------------------------------------------------------+ - | Includes | - +----------------------------------------------------------------------------*/ - -#include - -#ifdef _MSC_ - -#include "../USB_Common/types.h" // Basic Type declarations -#include "../USB_Common/device.h" -#include "../USB_Common/defMSP430USB.h" -#include "../USB_Common/usb.h" // USB-specific Data Structures -#include "../USB_MSC_API/UsbMscScsi.h" -#include "../USB_MSC_API/UsbMscReq.h" -#include "../USB_MSC_API/UsbMsc.h" - -extern __no_init tEDB __data16 tInputEndPointDescriptorBlock[]; -extern __no_init tEDB __data16 tOutputEndPointDescriptorBlock[]; -BOOL isMSCConfigured = FALSE; -extern BYTE bMscResetRequired; - -/*----------------------------------------------------------------------------+ - | Functions | - +----------------------------------------------------------------------------*/ -VOID USBMSC_reset(VOID) -{ - Msc_ResetStateMachine(); - Msc_ResetFlags(); - Msc_ResetStruct(); - isMSCConfigured = TRUE; - - bMscResetRequired = FALSE; - tInputEndPointDescriptorBlock[stUsbHandle[MSC0_INTFNUM].edb_Index].bEPCNF - &= ~(EPCNF_STALL | EPCNF_TOGGLE ); - tOutputEndPointDescriptorBlock[stUsbHandle[MSC0_INTFNUM].edb_Index].bEPCNF - &= ~(EPCNF_STALL | EPCNF_TOGGLE ); - usbSendZeroLengthPacketOnIEP0(); // status stage for control transfer -} - -//---------------------------------------------------------------------------- -VOID Get_MaxLUN(VOID) -{ - BYTE maxLunNumber = MSC_MAX_LUN_NUMBER - 1; - wBytesRemainingOnIEP0 = 1; - isMSCConfigured = TRUE; - usbSendDataPacketOnEP0((PBYTE)&maxLunNumber); -} - -#endif // _MSC_ -/*----------------------------------------------------------------------------+ -| End of source file | -+----------------------------------------------------------------------------*/ -/*------------------------ Nothing Below This Line --------------------------*/ diff --git a/USB_API/USB_MSC_API/UsbMscReq.h b/USB_API/USB_MSC_API/UsbMscReq.h deleted file mode 100644 index 96db944..0000000 --- a/USB_API/USB_MSC_API/UsbMscReq.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * UsbMscReq.h - * - * This file contains function declarations of MSC class specific Request - * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/*----------------------------------------------------------------------------+ - | | - | Texas Instruments | - | | - | MSP430 USB-Example (MSC Driver) | - | | - +-----------------------------------------------------------------------------+ - | Source: Usb_Msc_Req.h, File Version 1.0 | - | Description: This file contains function declarations of MSC class specific| - | Requests. | - | Author: MSP | - | | - | WHO WHEN WHAT | - | --- ---------- ------------------------------------------------ | - | MSP 01/02/2010 born | - +----------------------------------------------------------------------------*/ -#ifndef _USB_MSC_REQ_H_ -#define _USB_MSC_REQ_H_ - -#ifdef __cplusplus -extern "C" -{ -#endif - -/* MSC Class defined Request.Reset State-Machine and makes endpoints ready again*/ -VOID USBMSC_reset(VOID); - -/* MSC Class defined Request.Tells the host the number of supported logical units*/ -VOID Get_MaxLUN(VOID); - -#ifdef __cplusplus -} -#endif -#endif //_USB_MSC_REQ_H_ - diff --git a/USB_API/USB_MSC_API/UsbMscScsi.c b/USB_API/USB_MSC_API/UsbMscScsi.c deleted file mode 100644 index b1a3a73..0000000 --- a/USB_API/USB_MSC_API/UsbMscScsi.c +++ /dev/null @@ -1,1517 +0,0 @@ -/* - * UsbMscScsi.c - * - * This file contains the SCSI command handlers, MSC stack internal functions. - * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - - /*----------------------------------------------------------------------------+ - | | - | Texas Instruments | - | | - | MSP430 USB-Example (MSC Driver) | - | | - +-----------------------------------------------------------------------------+ - | Source: Msc_Scsi.c, File Version 1.03 | - | Description: This file contains the SCSI command handlers, MSC stack | - | internal functions. | - | Author: Biju, MSP | - | | - | WHO WHEN WHAT | - | --- ---------- ------------------------------------------------ | - | MSP 2010/02/16 Created | - | Biju,MSP 2010/07/15 Fixed CV bugs | - | RSTO 2010/10/15 Improoving READ/WRITE functionality | - +----------------------------------------------------------------------------*/ - -/*----------------------------------------------------------------------------+ - | Includes | - +----------------------------------------------------------------------------*/ -#include "../USB_Common/types.h" -#include "../USB_Common/device.h" -#include "../USB_Common/defMSP430USB.h" -#include "../USB_Common/usb.h" -#include "../USB_MSC_API/UsbMscScsi.h" -#include "../USB_MSC_API/UsbMsc.h" -#include -#include - -#ifdef _MSC_ - -/*----------------------------------------------------------------------------+ - | Internal Definitions | - +----------------------------------------------------------------------------*/ -//Error codes -#define RESCODE_CURRENT_ERROR 0x70 - -#define S_NO_SENSE 0x00 -#define S_NOT_READY 0x02 -#define S_MEDIUM_ERROR 0x03 -#define S_ILLEGAL_REQUEST 0x05 -#define S_UNITATTN 0x06 -#define S_WRITE_PROTECTED 0x07 -#define S_ABORTED_COMMAND 0x0B - -#define ASC_NOT_READY 0x04 -#define ASCQ_NOT_READY 0x03 - -#define ASC_MEDIUM_NOT_PRESENT 0x3A -#define ASCQ_MEDIUM_NOT_PRESENT 0x00 - -#define ASC_INVALID_COMMAND_OP_CODE 0x20 -#define ASCQ_INVALID_COMMAND_OP_CODE 0x00 - -#define ASC_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE 0x21 -#define ASCQ_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE 0x00 - -#define ASC_INVALID_FIELD_IN_CDB 0x24 -#define ASCQ_INVALID_FIELD_IN_CDB 0x00 - -#define ASC_INVALID_PARAMETER_LIST 0x26 -#define ASCQ_INVALID_PARAMETER_LIST 0x02 - -#define ASC_ABORTED_DATAPHASE_ERROR 0x4B -#define ASCQ_ABORTED_DATAPHASE_ERROR 0x00 - -#define ASC_ILLEGAL_REQUEST 0x20 -#define ASCQ_ILLEGAL_REQUEST 0x00 - -#define ASC_UNITATTN_READY_NOTREADY 0x28 -#define ASCQ_UNITATTN_READY_NOTREADY 0x00 - -#define ASC_WRITE_PROTECTED 0X27 -#define ASCQ_WRITE_PROTECTED 0X00 - -#define ASC_WRITE_FAULT 0x03 -#define ASCQ_WRITE_FAULT 0x00 - -#define ASC_UNRECOVERED_READ 0x11 -#define ASCQ_UNRECOVERED_READ 0x00 - -#define DIRECTION_IN 0x80 -#define DIRECTION_OUT 0x00 - -#define EP_MAX_PACKET_SIZE 0x40 - -/*----------------------------------------------------------------------------+ - | Global Variables | - +----------------------------------------------------------------------------*/ - -/*Variable to track command status */ -static volatile BYTE Scsi_Status = SCSI_PASSED; -/*Flag to indicate read/write command is recieved from host */ -BOOL bMcsCommandSupported = TRUE; - -/*Flag to inidicate whether any CBW recieved from host*/ -BOOL bMscCbwReceived; -extern BOOL isMSCConfigured; -// Buffer pointers passed by application -BYTE *xBufferAddr; -BYTE *yBufferAddr; - -/* Structure internal to stack for maintaining LBA info,buffer address etc */ -USBMSC_RWbuf_Info sRwbuf; - -volatile DWORD Scsi_Residue; -__no_init CBW McsCbw; -__no_init CSW McsCsw; -REQUEST_SENSE_RESPONSE RequestSenseResponse; - -VOID usbStallEndpoint(BYTE); -BYTE Scsi_Verify_CBW(); - -extern struct config_struct USBMSC_config; - -extern VOID *(*USB_TX_memcpy)(VOID * dest, const VOID * source, size_t count); -extern VOID *(*USB_RX_memcpy)(VOID * dest, const VOID * source, size_t count); - -extern __no_init tEDB __data16 tInputEndPointDescriptorBlock[]; -extern __no_init tEDB __data16 tOutputEndPointDescriptorBlock[]; - -struct _MscWriteControl MscWriteControl; -struct _MscReadControl MscReadControl; -struct _MscControl MscControl; - -// Most non-removable media would have these initialization values -struct _CtrlLun sCtrlLun[MSC_MAX_LUN_NUMBER]; - -//BYTE bMediaPresent = TRUE; -//BYTE bWriteProtected = FALSE; -BYTE bUnitAttention = FALSE; -BYTE bMscCbwFailed = FALSE; -BYTE Scsi_Standard_Inquiry_Data[256]; -BYTE bMscResetRequired = FALSE; - -/*----------------------------------------------------------------------------+ - | Initiliazing Command data | - +----------------------------------------------------------------------------*/ -struct _Scsi_Read_Capacity Scsi_Read_Capacity_10[MSC_MAX_LUN_NUMBER]; -const struct _Report_Luns Report_Luns = {{0x02,0x00,0x00,0x00}, - {0x00,0x00,0x00,0x00}, - {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}}; - -BYTE Scsi_Mode_Sense_6[SCSI_MODE_SENSE_6_CMD_LEN]= {0x03,0,0,0 }; // No mode sense parameter - -BYTE Scsi_Mode_Sense_10[SCSI_MODE_SENSE_10_CMD_LEN]= {0,0x06,0,0,0,0,0,0 }; // No mode sense parameter - -BYTE Scsi_Read_Format_Capacity[SCSI_READ_FORMAT_CAPACITY_CMD_LEN] = {0x00,0x00,0x00,0x08,0x01,0x00,0x00,0x00,0x03,0x00,0x02,0x00}; - -/*Default values initialized for SCSI Inquiry data */ -const BYTE bScsi_Standard_Inquiry_Data[SCSI_SCSI_INQUIRY_CMD_LEN]= { - 0x00, // Peripheral qualifier & peripheral device type - 0x80, // Removable medium - 0x02, // Version of the standard (SPC-2) - 0x02, // No NormACA, No HiSup, response data format=2 - 0x1F, // No extra parameters - 0x00, // No flags - 0x00, // 0x80 => BQue => Basic Task Management supported - 0x00, // No flags - /* 'T','I',' ',' ',' ',' ',' ',' ', - 'M','a','s','s',' ','S','t','o','r','a','g','e', */ -}; - -/*----------------------------------------------------------------------------+ - | Functions | - +----------------------------------------------------------------------------*/ -VOID Reset_RequestSenseResponse(VOID) -{ - int i; - - RequestSenseResponse.ResponseCode = RESCODE_CURRENT_ERROR; - RequestSenseResponse.VALID = 0; // no data in the information field - RequestSenseResponse.Obsolete = 0x00; - RequestSenseResponse.SenseKey = S_NO_SENSE; - RequestSenseResponse.ILI = 0; - RequestSenseResponse.EOM = 0; - RequestSenseResponse.FILEMARK = 0; - RequestSenseResponse.Information[0] = 0x00; - RequestSenseResponse.Information[1] = 0x00; - RequestSenseResponse.Information[2] = 0x00; - RequestSenseResponse.Information[3] = 0x00; - RequestSenseResponse.AddSenseLen = 0x0a; - RequestSenseResponse.CmdSpecificInfo[0]= 0x00; - RequestSenseResponse.CmdSpecificInfo[1]= 0x00; - RequestSenseResponse.CmdSpecificInfo[2]= 0x00; - RequestSenseResponse.CmdSpecificInfo[3]= 0x00; - RequestSenseResponse.ASC = 0x00; - RequestSenseResponse.ASCQ = 0x00; - RequestSenseResponse.FRUC = 0x00; - RequestSenseResponse.SenseKeySpecific[0] = 0x00; - RequestSenseResponse.SenseKeySpecific[1] = 0x00; - RequestSenseResponse.SenseKeySpecific[2] = 0x00; - for (i=0; i<14; i++) { - RequestSenseResponse.padding[i] = 0x00; - } -} - -//---------------------------------------------------------------------------- - -BYTE Check_CBW(BYTE intfNum,BYTE Dir_Dev_Exp, DWORD Bytes_Dev_Exp) -{ - if(McsCbw.CBWCB[0] ==SCSI_INQUIRY || McsCbw.CBWCB[0] == SCSI_REQUEST_SENSE) - { - return SUCCESS; - } - - if(Dir_Dev_Exp == McsCbw.bmCBWFlags) // all is right. Host is sending direction as expected by device - { - if(McsCbw.dCBWDataTransferLength < Bytes_Dev_Exp) // Host expect less data to send or receive then device - { - Scsi_Status = SCSI_PHASE_ERROR; - Scsi_Residue =0 ; - if (McsCbw.bmCBWFlags == DIRECTION_IN) - { - usbStallInEndpoint(intfNum); - } - else - { - usbStallOutEndpoint(intfNum); - } - } - else if((McsCbw.dCBWDataTransferLength > Bytes_Dev_Exp) && - (McsCbw.CBWCB[0]!=SCSI_MODE_SENSE_6) && - (McsCbw.CBWCB[0]!=SCSI_MODE_SENSE_10)) - { - Scsi_Status = SCSI_FAILED; - Scsi_Residue = McsCbw.dCBWDataTransferLength - Bytes_Dev_Exp; - if (McsCbw.bmCBWFlags == DIRECTION_IN) - { - usbStallInEndpoint(intfNum); - } - else - { - usbStallOutEndpoint(intfNum); - } - } - else - { - return SUCCESS; - } - } - - else //Direction mismatch - { - Scsi_Residue = McsCbw.dCBWDataTransferLength; - Scsi_Status = SCSI_FAILED; - if(McsCbw.bmCBWFlags == DIRECTION_IN) - { - usbStallInEndpoint(intfNum); - } - else if((McsCbw.bmCBWFlags == DIRECTION_OUT)&&(McsCbw.CBWCB[0] == SCSI_READ_10)) - { - usbStallOutEndpoint(intfNum); - } - } - - // Indicates a generic failure. Read/write failure/sense data is handled separately - if(Scsi_Status != SCSI_READWRITE_FAIL) - { - - RequestSenseResponse.ResponseCode = RESCODE_CURRENT_ERROR; - RequestSenseResponse.VALID = 1; - RequestSenseResponse.AddSenseLen = 0xA0; - RequestSenseResponse.SenseKey = S_ILLEGAL_REQUEST; - RequestSenseResponse.ASC = ASC_INVALID_PARAMETER_LIST; - RequestSenseResponse.ASCQ = ASCQ_INVALID_PARAMETER_LIST; - } - - return FAILURE; -} - -//---------------------------------------------------------------------------- -BYTE Scsi_Verify_CBW() -{ - /*(5.2.3) Devices must consider the CBW meaningful if no reserved bits - are set, the LUN number indicates a LUN supported by the device, - bCBWCBLength is in the range of 1 through 16, and the length and - content of the CBWCB field are appropriate to the SubClass. - */ - if((bMscResetRequired || McsCbw.dCBWSignature!=CBW_SIGNATURE) || // Check for correct CBW signature - ((McsCbw.bmCBWFlags!=DIRECTION_IN && McsCbw.bmCBWFlags!=DIRECTION_OUT) || - (McsCbw.bCBWLUN&0xF0) || // Upper bits have to be zero - (McsCbw.bCBWCBLength>16))) // maximum length is 16 - - { - bMscResetRequired = TRUE; - usbStallEndpoint(MSC0_INTFNUM); - usbClearOEPByteCount(MSC0_INTFNUM); - Scsi_Status = SCSI_FAILED; - Scsi_Residue = 0; - return FAILURE; - } - Scsi_Status = SCSI_PASSED; - return SUCCESS; -} - -//---------------------------------------------------------------------------- -BYTE Scsi_Send_CSW(BYTE intfNum) -{ - BYTE retval=0; - // Populate the CSW to be sent - McsCsw.dCSWSignature=CSW_SIGNATURE; - McsCsw.dCSWTag=McsCbw.dCBWTag; - McsCsw.bCSWStatus=Scsi_Status; - McsCsw.dCSWDataResidue=Scsi_Residue; - retval = MscSendData((PBYTE)&McsCsw, CSW_LENGTH); //Sending CSW - Scsi_Status = SCSI_PASSED; - return retval; -} -//---------------------------------------------------------------------------- - -VOID Scsi_Inquiry(BYTE intfNum) -{ - //int index; - - //clear the inquiry array - memset(Scsi_Standard_Inquiry_Data, 256, 0); - //copy the inquiry data from flash to RAM - - memcpy(Scsi_Standard_Inquiry_Data,bScsi_Standard_Inquiry_Data,SCSI_SCSI_INQUIRY_CMD_LEN); - - - - //get the values from USB_Config - Scsi_Standard_Inquiry_Data[1] = USBMSC_config.LUN[McsCbw.bCBWLUN].removable; - memcpy(&Scsi_Standard_Inquiry_Data[8],USBMSC_config.LUN[McsCbw.bCBWLUN].t10VID,8); - memcpy(&Scsi_Standard_Inquiry_Data[16],USBMSC_config.LUN[McsCbw.bCBWLUN].t10PID,16); - memcpy(&Scsi_Standard_Inquiry_Data[32],USBMSC_config.LUN[McsCbw.bCBWLUN].t10rev,4); - - if(McsCbw.dCBWDataTransferLength < SCSI_SCSI_INQUIRY_CMD_LEN) - { - if(McsCbw.dCBWDataTransferLength == 0) - { - Scsi_Residue = 0; - return; - } - if(SUCCESS == MscSendData((PBYTE)Scsi_Standard_Inquiry_Data, McsCbw.dCBWDataTransferLength)) - { - Scsi_Residue = 0; - } - else - { - Scsi_Status = SCSI_FAILED; - } - } - else if(McsCbw.dCBWDataTransferLength > SCSI_SCSI_INQUIRY_CMD_LEN) - { - Reset_RequestSenseResponse(); - - RequestSenseResponse.ResponseCode = RESCODE_CURRENT_ERROR; - RequestSenseResponse.VALID = 1; - RequestSenseResponse.SenseKey = S_ILLEGAL_REQUEST; - RequestSenseResponse.ASC = ASC_INVALID_FIELD_IN_CDB; - RequestSenseResponse.ASCQ = ASCQ_INVALID_FIELD_IN_CDB; - usbStallInEndpoint(intfNum); - Scsi_Status = SCSI_FAILED; - } - else - { - if(SUCCESS == MscSendData((PBYTE)Scsi_Standard_Inquiry_Data,SCSI_SCSI_INQUIRY_CMD_LEN)) - { - Scsi_Residue = 0; - } - else - { - Scsi_Status = SCSI_FAILED; - } - } -} - -//---------------------------------------------------------------------------- - -VOID Scsi_Read_Capacity10(BYTE intfNum) -{ - if(FAILURE == Check_CBW(intfNum,DIRECTION_IN,SCSI_READ_CAPACITY_CMD_LEN)) - return; - if(SUCCESS != MscSendData( (PBYTE)&Scsi_Read_Capacity_10[McsCbw.bCBWLUN], SCSI_READ_CAPACITY_CMD_LEN)) - Scsi_Status = SCSI_FAILED; -} - -//---------------------------------------------------------------------------- - -VOID Scsi_Read10(BYTE intfNum) -{ - WORD wLBA_len; - unsigned short bGIE; - DWORD dLBA; - - /* Get first LBA: convert 4 bytes into DWORD */ - dLBA = McsCbw.CBWCB[2]; - dLBA <<= 8; - dLBA += McsCbw.CBWCB[3]; - dLBA <<= 8; - dLBA += McsCbw.CBWCB[4]; - dLBA <<= 8; - dLBA += McsCbw.CBWCB[5]; - - /* Get number of requested logical blocks */ - wLBA_len = McsCbw.CBWCB[7]; - wLBA_len <<=8; - wLBA_len += McsCbw.CBWCB[8]; - - if(FAILURE == Check_CBW( intfNum, DIRECTION_IN, ((DWORD)wLBA_len) * MscControl.lbaSize)) - return; - - bGIE = (__get_SR_register() & GIE); //save interrupt status - __disable_interrupt(); - - // Populating stack internal structure required for READ/WRITE - MscReadControl.lba = dLBA; // the first LBA number. - MscReadControl.lbaCount = wLBA_len; // how many LBAs to read. - - sRwbuf.bufferAddr = xBufferAddr; - sRwbuf.lun = McsCbw.bCBWLUN; - - //set LBA count - sRwbuf.lbCount = wLBA_len > MscControl.lbaBufCapacity ? MscControl.lbaBufCapacity : wLBA_len; - sRwbuf.operation = kUSBMSC_READ; - sRwbuf.lba = dLBA; - sRwbuf.returnCode = kUSBMSC_RWSuccess; - sRwbuf.XorY = 0; - //buffer is prepared, let user's Application fill data. - USBMSC_handleBufferEvent(); - - __bis_SR_register(bGIE); //restore interrupt status -} - -//---------------------------------------------------------------------------- - -VOID Scsi_Write10(BYTE intfNum) -{ - WORD wLBA_len; - unsigned short bGIE; - /* Get first LBA: convert 4 bytes into DWORD */ - DWORD dLBA = McsCbw.CBWCB[2]; - dLBA <<= 8; - dLBA += McsCbw.CBWCB[3]; - dLBA <<= 8; - dLBA += McsCbw.CBWCB[4]; - dLBA <<= 8; - dLBA += McsCbw.CBWCB[5]; - - /* Get number of requested logical blocks */ - wLBA_len = McsCbw.CBWCB[7]; - wLBA_len <<=8; - wLBA_len += McsCbw.CBWCB[8]; - - if(FAILURE == Check_CBW(intfNum,DIRECTION_OUT,((DWORD)wLBA_len) * MscControl.lbaSize)) - return; - bGIE = (__get_SR_register() &GIE); //save interrupt status - __disable_interrupt(); - - //calculate the whole size to receive (Host to MSP430) - MscWriteControl.dwBytesToReceiveLeft = (DWORD)wLBA_len * MscControl.lbaSize; - MscWriteControl.pUserBuffer = xBufferAddr; - MscWriteControl.wFreeBytesLeft = MscControl.wMscUserBufferSize; - - /*Populating stack internal structure required for READ/WRITE */ - sRwbuf.bufferAddr = xBufferAddr; - sRwbuf.lun = McsCbw.bCBWLUN; - MscWriteControl.bWriteProcessing = TRUE; // indicate that we are in WRITE phase - sRwbuf.XorY = 0; - MscWriteControl.lba = dLBA; - MscWriteControl.wCurrentByte = 0; //reset internal variable - MscWriteControl.lbaCount = 0; //reset internal variable - - __bis_SR_register(bGIE); //restore interrupt status -} - -//---------------------------------------------------------------------------- - -VOID Scsi_Mode_Sense6(BYTE intfNum) -{ - if(FAILURE == Check_CBW(intfNum,DIRECTION_IN,SCSI_MODE_SENSE_6_CMD_LEN)) - return; - /* Fix for SDOCM00077834 - Set WP bit. WP bit is BIT7 in byte 3 */ - Scsi_Mode_Sense_6[2] |= (sCtrlLun[McsCbw.bCBWLUN].bWriteProtected << 0x7); - - if(SUCCESS != MscSendData((PBYTE)Scsi_Mode_Sense_6, SCSI_MODE_SENSE_6_CMD_LEN)) - Scsi_Status = SCSI_FAILED; -} - -//---------------------------------------------------------------------------- - -VOID Scsi_Mode_Sense10(BYTE intfNum) -{ - if(FAILURE == Check_CBW(intfNum,DIRECTION_IN,SCSI_MODE_SENSE_10_CMD_LEN)) - return; - /* Fix for SDOCM00077834 - Set WP bit. WP bit is BIT7 in byte 3 */ - Scsi_Mode_Sense_10[4] |= (sCtrlLun[McsCbw.bCBWLUN].bWriteProtected << 0x7); - - if(SUCCESS != MscSendData((PBYTE)Scsi_Mode_Sense_10, SCSI_MODE_SENSE_10_CMD_LEN)) - Scsi_Status = SCSI_FAILED; -} - -//---------------------------------------------------------------------------- - -VOID Scsi_Request_Sense(BYTE intfNum) -{ - if(FAILURE == Check_CBW(intfNum,DIRECTION_IN,SCSI_REQ_SENSE_CMD_LEN)) - { - return; - } - - // If there is attention needed, setup the request sense response. The - // bUnitAttention flag is set in USBMSC_updateMediaInfo() when the volume - // is removed or inserted. Note that the response is different for the - // removed and inserted case. - if(bUnitAttention == TRUE) - { - // Check if the volume was removed. - if(sCtrlLun[McsCbw.bCBWLUN].bMediaPresent == kUSBMSC_MEDIA_NOT_PRESENT) - { - Reset_RequestSenseResponse(); - RequestSenseResponse.VALID = 1; - RequestSenseResponse.SenseKey = S_NOT_READY; - RequestSenseResponse.ASC = ASC_MEDIUM_NOT_PRESENT; - RequestSenseResponse.ASCQ = ASCQ_MEDIUM_NOT_PRESENT; - } - // Otherwise it was inserted. - else - { - Reset_RequestSenseResponse(); - RequestSenseResponse.VALID = 1; - RequestSenseResponse.SenseKey = S_UNITATTN; - RequestSenseResponse.ASC = ASC_UNITATTN_READY_NOTREADY; - RequestSenseResponse.ASCQ = ASCQ_UNITATTN_READY_NOTREADY; - } - } - - if(McsCbw.dCBWDataTransferLength < SCSI_REQ_SENSE_CMD_LEN) - { - if(SUCCESS == MscSendData((PBYTE)&RequestSenseResponse,McsCbw.dCBWDataTransferLength)) - { - Scsi_Residue = 0; - } - else - { - Scsi_Status = SCSI_FAILED; - } - } - else if(McsCbw.dCBWDataTransferLength > SCSI_REQ_SENSE_CMD_LEN) - { - RequestSenseResponse.AddSenseLen += (McsCbw.dCBWDataTransferLength - SCSI_REQ_SENSE_CMD_LEN); - if(SUCCESS == MscSendData((PBYTE)&RequestSenseResponse, McsCbw.dCBWDataTransferLength)) - { - Scsi_Residue = 0; - } - else - { - Scsi_Status = SCSI_FAILED; - } - } - else - { - if(SUCCESS == MscSendData((PBYTE)&RequestSenseResponse,SCSI_REQ_SENSE_CMD_LEN)) - { - Scsi_Residue = 0; - } - else - { - Scsi_Status = SCSI_FAILED; - } - } - - // Clear the bUnitAttention flag after the response was properly sent via - // MscSendData(). - if(bUnitAttention == TRUE) - { - bUnitAttention = FALSE; - } -} - -//---------------------------------------------------------------------------- - -VOID Scsi_Test_Unit_Ready(BYTE intfNum) -{ - if(SUCCESS != Check_CBW(intfNum,DIRECTION_OUT,0)) - Scsi_Status = SCSI_FAILED; - - Reset_RequestSenseResponse(); -} - -//---------------------------------------------------------------------------- - -VOID Scsi_Unknown_Request(BYTE intfNum) -{ - Reset_RequestSenseResponse(); - - RequestSenseResponse.ResponseCode = RESCODE_CURRENT_ERROR; - RequestSenseResponse.VALID = 1; - RequestSenseResponse.AddSenseLen = 0xA0; - RequestSenseResponse.SenseKey = S_ILLEGAL_REQUEST; - RequestSenseResponse.ASC = ASC_INVALID_COMMAND_OP_CODE; - RequestSenseResponse.ASCQ = ASCQ_INVALID_COMMAND_OP_CODE; - Scsi_Residue = 0; - Scsi_Status = SCSI_FAILED; - - if (McsCbw.dCBWDataTransferLength && (McsCbw.bmCBWFlags == DIRECTION_IN)) - { - bMcsCommandSupported = FALSE; - usbStallInEndpoint(intfNum); - } - if (McsCbw.dCBWDataTransferLength && (McsCbw.bmCBWFlags == DIRECTION_OUT)) - { - bMcsCommandSupported = FALSE; - usbStallOutEndpoint(intfNum); - } -} - -//---------------------------------------------------------------------------- - -VOID Scsi_Report_Luns(BYTE intfNum) -{ - if(FAILURE == Check_CBW( intfNum, DIRECTION_IN, SCSI_REPORT_LUNS_CMD_LEN)) - return; - if(SUCCESS != MscSendData( (PBYTE)&Report_Luns, SCSI_REPORT_LUNS_CMD_LEN)) - Scsi_Status = SCSI_FAILED; -} - -//---------------------------------------------------------------------------- - -BYTE Scsi_Cmd_Parser(BYTE intfNum) -{ - BYTE ret = kUSBMSC_cmdBeingProcessed; - //Scsi_Status = SCSI_FAILED; - Scsi_Residue = McsCbw.dCBWDataTransferLength; - - // fails the commands during UNIT ATTENTION - if((bUnitAttention) &&(McsCbw.CBWCB[0] != SCSI_INQUIRY) && (McsCbw.CBWCB[0] !=SCSI_REQUEST_SENSE)) - { - Scsi_Status = SCSI_FAILED; - return kUSB_generalError; - } - - if(!McsCbw.bCBWCBLength) - return kUSB_generalError; - - switch(McsCbw.CBWCB[0]) // SCSI Operation code - { - case SCSI_READ_10: - if(xBufferAddr == NULL) // Check for null address. - { - ret = kUSB_generalError; - SET_RequestsenseNotReady(); - Scsi_Status = SCSI_FAILED; - usbStallInEndpoint(intfNum); - break; - } - - if(sCtrlLun[McsCbw.bCBWLUN].bMediaPresent == kUSBMSC_MEDIA_NOT_PRESENT) // Check for media present. Do this for any command that accesses media. - { - ret = kUSB_generalError; - SET_RequestsenseMediaNotPresent(); - usbStallInEndpoint(intfNum); - break; - } - Scsi_Read10(intfNum); - break; - - case SCSI_WRITE_10: - if(xBufferAddr == NULL) // Check for null address. - { - ret = kUSB_generalError; - SET_RequestsenseNotReady(); - Scsi_Status = SCSI_FAILED; - break; - } - - if(sCtrlLun[McsCbw.bCBWLUN].bMediaPresent == kUSBMSC_MEDIA_NOT_PRESENT) // Check for media present. Do this for any command that accesses media. - { - ret = kUSB_generalError; - SET_RequestsenseMediaNotPresent(); - usbStallOutEndpoint(intfNum); - break; - } - - if(sCtrlLun[McsCbw.bCBWLUN].bWriteProtected) // Do this only for WRITE - { - ret = kUSB_generalError; - // Set REQUEST SENSE with "write protected" - Reset_RequestSenseResponse(); - RequestSenseResponse.VALID = 1; - RequestSenseResponse.SenseKey = S_WRITE_PROTECTED; - RequestSenseResponse.ASC =ASC_WRITE_PROTECTED; - RequestSenseResponse.ASCQ = ASCQ_WRITE_PROTECTED; - MscWriteControl.bWriteProcessing = FALSE; - // Send CSW with error status - Scsi_Residue = 1; - Scsi_Status = SCSI_FAILED; - usbStallOutEndpoint(intfNum); - break; - } - - Scsi_Write10(intfNum); - break; - - case START_STOP_UNIT: - case PREVENT_ALLW_MDM: - case SCSI_MODE_SELECT_10: - case SCSI_MODE_SELECT_6: - case SCSI_TEST_UNIT_READY: - if(sCtrlLun[McsCbw.bCBWLUN].bMediaPresent == kUSBMSC_MEDIA_NOT_PRESENT) // Check for media present. Do this for any command that accesses media. - { - ret = kUSB_generalError; - SET_RequestsenseMediaNotPresent(); - break; - } - Scsi_Test_Unit_Ready(intfNum); - break; - - case SCSI_INQUIRY: - Scsi_Inquiry(intfNum); - break; - - case SCSI_MODE_SENSE_6: - Scsi_Mode_Sense6(intfNum); - break; - - case SCSI_MODE_SENSE_10: - Scsi_Mode_Sense10(intfNum); - break; - - case SCSI_READ_CAPACITY_10: - if(sCtrlLun[McsCbw.bCBWLUN].bMediaPresent == kUSBMSC_MEDIA_NOT_PRESENT) // Check for media present. Do this for any command that accesses media. - { - ret = kUSB_generalError; - SET_RequestsenseMediaNotPresent(); - usbStallInEndpoint(intfNum); - break; - } - Scsi_Read_Capacity10(intfNum); - break; - - case SCSI_REQUEST_SENSE: - Scsi_Request_Sense(intfNum); - break; - - case SCSI_REPORT_LUNS: - if(sCtrlLun[McsCbw.bCBWLUN].bMediaPresent == kUSBMSC_MEDIA_NOT_PRESENT) // Check for media present. Do this for any command that accesses media. - { - ret = kUSB_generalError; - SET_RequestsenseMediaNotPresent(); - if (McsCbw.bmCBWFlags == DIRECTION_IN) - { - usbStallInEndpoint(intfNum); - } - else - { - usbStallOutEndpoint(intfNum); - } - break; - } - Scsi_Report_Luns(intfNum); - break; - case SCSI_VERIFY: - /* Fix for SDOCM00078183 */ - /* NOTE: we are assuming that BYTCHK=0 and PASSing the command. */ - break; - - default: - ret = kUSB_generalError; - Scsi_Unknown_Request(intfNum); - break; - } - return ret; -} - -//------------------------------------------------------------------------------------------------------- -/* This function is called only from ISR(only on Input endpoint interrupt to transfer data to host) - This function actually performs the data transfer to host Over USB */ -BOOL MSCToHostFromBuffer() -{ - // Check if there are any pending LBAs to process - BYTE * pEP1; - BYTE * pEP2; - BYTE * pCT1; - BYTE * pCT2; - BYTE bWakeUp = FALSE; // per default we do not wake up after interrupt - BYTE edbIndex; - BYTE bCount; - - MscReadControl.bIsIdle = FALSE; - - // Check if there are any pending data to send - if (MscReadControl.dwBytesToSendLeft == 0) - { - //no more data to send - clear ready busy status - MscReadControl.bReadProcessing = FALSE; - - //check if more LBA to send out pending... - if (MscReadControl.lbaCount > 0) - { - sRwbuf.lba = MscReadControl.lba; //update current lba - sRwbuf.lbCount = MscControl.lbaBufCapacity > MscReadControl.lbaCount ? - MscReadControl.lbaCount : MscControl.lbaBufCapacity; //update LBA count - sRwbuf.bufferAddr = xBufferAddr; //buffer for place data in - sRwbuf.operation = kUSBMSC_READ; //start data READ phase - sRwbuf.returnCode = kUSBMSC_RWSuccess; - sRwbuf.XorY = 0; //only one buffer is active - //buffer is prepared, let user's Application fill data. - USBMSC_handleBufferEvent(); - } - return TRUE; //data sent out - wake up! - } - - edbIndex = stUsbHandle[MSC0_INTFNUM].edb_Index; - - //check if the endpoint is stalled = do not send data. - if (tInputEndPointDescriptorBlock[edbIndex].bEPCNF & EPCNF_STALL) - { - return TRUE; - } - - // send one chunk of 64 bytes - //check what is current buffer: X or Y - if (MscReadControl.bCurrentBufferXY == X_BUFFER) //X is current buffer - { - //this is the active EP buffer - pEP1 = (BYTE*)stUsbHandle[MSC0_INTFNUM].iep_X_Buffer; - pCT1 = &tInputEndPointDescriptorBlock[edbIndex].bEPBCTX; - - //second EP buffer - pEP2 = (BYTE*)stUsbHandle[MSC0_INTFNUM].iep_Y_Buffer; - pCT2 = &tInputEndPointDescriptorBlock[edbIndex].bEPBCTY; - } - else - { - //this is the active EP buffer - pEP1 = (BYTE*)stUsbHandle[MSC0_INTFNUM].iep_Y_Buffer; - pCT1 = &tInputEndPointDescriptorBlock[edbIndex].bEPBCTY; - - //second EP buffer - pEP2 = (BYTE*)stUsbHandle[MSC0_INTFNUM].iep_X_Buffer; - pCT2 = &tInputEndPointDescriptorBlock[edbIndex].bEPBCTX; - } - - // how many byte we can send over one endpoint buffer - bCount = (MscReadControl.dwBytesToSendLeft > EP_MAX_PACKET_SIZE) ? EP_MAX_PACKET_SIZE : MscReadControl.dwBytesToSendLeft; - - if(*pCT1 & EPBCNT_NAK) - { - USB_TX_memcpy(pEP1, MscReadControl.pUserBuffer, bCount); // copy data into IEPx X or Y buffer - *pCT1 = bCount; // Set counter for usb In-Transaction - MscReadControl.bCurrentBufferXY = (MscReadControl.bCurrentBufferXY+1)&0x01; //switch buffer - MscReadControl.dwBytesToSendLeft -= bCount; - MscReadControl.pUserBuffer += bCount; // move buffer pointer - - //try to send data over second buffer - if ((MscReadControl.dwBytesToSendLeft > 0) && // do we have more data to send? - (*pCT2 & EPBCNT_NAK)) // if the second buffer is free? - { - // how many byte we can send over one endpoint buffer - bCount = (MscReadControl.dwBytesToSendLeft > EP_MAX_PACKET_SIZE) ? EP_MAX_PACKET_SIZE : MscReadControl.dwBytesToSendLeft; - // copy data into IEPx X or Y buffer - USB_TX_memcpy(pEP2, MscReadControl.pUserBuffer, bCount); - // Set counter for usb In-Transaction - *pCT2 = bCount; - //switch buffer - MscReadControl.bCurrentBufferXY = (MscReadControl.bCurrentBufferXY+1)&0x01; - MscReadControl.dwBytesToSendLeft -= bCount; - //move buffer pointer - MscReadControl.pUserBuffer += bCount; - } - } // if(*pCT1 & EPBCNT_NAK) - return bWakeUp; -} - -//------------------------------------------------------------------------------------------------------ - -//This function used to initialize the sending process. -//Use this by functiosn for send CSW or send LBA -//To use only by STACK itself, not by application -//Returns: SUCCESS or FAILURE -BYTE MscSendData(const BYTE* data, WORD size) -{ - BYTE edbIndex; - unsigned short bGIE; - - edbIndex= stUsbHandle[MSC0_INTFNUM].edb_Index; - - if (size == 0) - { - return FAILURE; - } - - bGIE = (__get_SR_register() &GIE); //save interrupt status - // atomic operation - disable interrupts - __disable_interrupt(); // Disable global interrupts - - // do not access USB memory if suspended (PLL off). It may produce BUS_ERROR - if ((bFunctionSuspended) || - (bEnumerationStatus != ENUMERATION_COMPLETE)) - { - // data can not be read because of USB suspended - __bis_SR_register(bGIE); //restore interrupt status - return FAILURE; - } - - if ((MscReadControl.dwBytesToSendLeft != 0) || // data was not sent out - (MscReadControl.bReadProcessing == TRUE)) //still processing previous data - { - // the USB still sends previous data, we have to wait - __bis_SR_register(bGIE); //restore interrupt status - return FAILURE; - } - - //This function generate the USB interrupt. The data will be sent out from interrupt - - MscReadControl.bReadProcessing = TRUE; //set reading busy status. - MscReadControl.dwBytesToSendLeft = size; - MscReadControl.pUserBuffer = (BYTE*)data; - - //trigger Endpoint Interrupt - to start send operation - USBIEPIFG |= 1<<(edbIndex+1); //IEPIFGx; - - __bis_SR_register(bGIE); //restore interrupt status - - return SUCCESS; -} - -// This function copies data from OUT endpoint into user's buffer -// This function to call only from MSCFromHostToBuffer() -// Arguments: -// pEP - pointer to EP to copy from -// pCT - pointer to EP control reg -// -VOID MscCopyUsbToBuff(BYTE* pEP, BYTE* pCT) -{ - BYTE nCount; - nCount = *pCT &(~EPBCNT_NAK); - - //how many bytes we can receive to avoid overflow - nCount = (nCount > MscWriteControl.dwBytesToReceiveLeft) ? MscWriteControl.dwBytesToReceiveLeft : nCount; - - USB_RX_memcpy(MscWriteControl.pUserBuffer, pEP, nCount); // copy data from OEPx X or Y buffer - MscWriteControl.dwBytesToReceiveLeft -= nCount; - MscWriteControl.pUserBuffer += nCount; // move buffer pointer - // to read rest of data next time from this place - MscWriteControl.wFreeBytesLeft -= nCount; //update counter - - MscWriteControl.wCurrentByte += nCount; - if (MscWriteControl.wCurrentByte >= MscControl.lbaSize) - { - MscWriteControl.wCurrentByte = 0; - MscWriteControl.lbaCount++; - } - - //switch current buffer - MscWriteControl.bCurrentBufferXY = (MscWriteControl.bCurrentBufferXY+1) &0x01; - - //clear NAK, EP ready to receive data - *pCT = 0x00; -} - -//------------------------------------------------------------------------------------------------------ -/* This function is called only from ISR(only on Output endpoint interrupt, to recv data from host) - This function actually recieves the data from host Over USB */ -BOOL MSCFromHostToBuffer() -{ - BYTE * pEP1; - BYTE nTmp1; - BYTE bWakeUp = FALSE; // per default we do not wake up after interrupt - BYTE edbIndex; - edbIndex = stUsbHandle[MSC0_INTFNUM].edb_Index; - - MscReadControl.bIsIdle = FALSE; - - if (bMscCbwReceived == TRUE) - { - //previous CBW is not performed, so exit interrupt hendler - //and trigger it again later - return TRUE; //true for wake up! - } - - if (!MscWriteControl.bWriteProcessing) //receiving CBW - { - //CBW will be received here.... - //check what is current buffer: X or Y - if (MscWriteControl.bCurrentBufferXY == X_BUFFER) //X is current buffer - { - //this is the active EP buffer - pEP1 = (BYTE*)stUsbHandle[MSC0_INTFNUM].oep_X_Buffer; - MscWriteControl.pCT1 = &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX; - MscWriteControl.pCT2 = &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY; - } - else - { - //this is the active EP buffer - pEP1 = (BYTE*)stUsbHandle[MSC0_INTFNUM].oep_Y_Buffer; - MscWriteControl.pCT1 = &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY; - MscWriteControl.pCT2 = &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX; - } - - // how many byte we can get from one endpoint buffer - nTmp1 = *MscWriteControl.pCT1; - - if(nTmp1 & EPBCNT_NAK) - { - BYTE nCount; - - //switch current buffer - MscWriteControl.bCurrentBufferXY = (MscWriteControl.bCurrentBufferXY+1) &0x01; - - nTmp1 = nTmp1 &0x7f; // clear NAK bit - nCount = (nTmp1 > sizeof(McsCbw)) ? sizeof(McsCbw) : nTmp1; - USB_RX_memcpy(&McsCbw, pEP1, nCount); // copy data from OEPx X or Y buffer - - //clear NAK, EP ready to receive data - *MscWriteControl.pCT1 = 0x00; - - //set flag and check the CBW from the usbmsc_poll - bMscCbwReceived = TRUE; - - // second 64b buffer will be not read out here because the CBW is <64 bytes - } - - bWakeUp = TRUE; //wake up to perform CBW - return bWakeUp; - } - - //if we are here - LBAs will be received - - /*Check if there are any pending LBAs to process */ - if (MscWriteControl.dwBytesToReceiveLeft > 0) - { - // read one chunk of 64 bytes - - //check what is current buffer: X or Y - if (MscWriteControl.bCurrentBufferXY == X_BUFFER) //X is current buffer - { - //this is the active EP buffer - pEP1 = (BYTE*)stUsbHandle[MSC0_INTFNUM].oep_X_Buffer; - MscWriteControl.pCT1 = &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX; - - //second EP buffer - MscWriteControl.pEP2 = (BYTE*)stUsbHandle[MSC0_INTFNUM].oep_Y_Buffer; - MscWriteControl.pCT2 = &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY; - } - else - { - //this is the active EP buffer - pEP1 = (BYTE*)stUsbHandle[MSC0_INTFNUM].oep_Y_Buffer; - MscWriteControl.pCT1 = &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY; - - //second EP buffer - MscWriteControl.pEP2 = (BYTE*)stUsbHandle[MSC0_INTFNUM].oep_X_Buffer; - MscWriteControl.pCT2 = &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX; - } - - // how many byte we can get from one endpoint buffer - nTmp1 = *MscWriteControl.pCT1; - - if((nTmp1 & EPBCNT_NAK) && - (MscWriteControl.wFreeBytesLeft >= 64)) - { - //copy data from Endpoint - MscCopyUsbToBuff(pEP1, MscWriteControl.pCT1); - - nTmp1 = *MscWriteControl.pCT2; - - //try read data from second buffer - if ((MscWriteControl.dwBytesToReceiveLeft > 0) && // do we have more data to send? - (MscWriteControl.wFreeBytesLeft >= 64) && - (nTmp1 & EPBCNT_NAK)) // if the second buffer has received data? - { - //copy data from Endpoint - MscCopyUsbToBuff(MscWriteControl.pEP2, MscWriteControl.pCT2); - //MscWriteControl.pCT1 = MscWriteControl.pCT2; - } - - if ((MscWriteControl.wFreeBytesLeft == 0) || // user's buffer is full, give it to User - (MscWriteControl.dwBytesToReceiveLeft == 0)) //or no bytes to read left - give it to User - { - sRwbuf.operation = kUSBMSC_WRITE; - sRwbuf.lba = MscWriteControl.lba; //copy lba number - MscWriteControl.lba += MscWriteControl.lbaCount; - sRwbuf.lbCount = MscWriteControl.lbaCount; //copy lba count - MscWriteControl.wCurrentByte = 0; - MscWriteControl.lbaCount = 0; - - //call event handler, we are ready with data - bWakeUp = USBMSC_handleBufferEvent(); - } //if (wFreeBytesLeft == 0) - } - }// if (MscWriteControl.dwBytesToReceiveLeft > 0) - else - { - //perform error handling here, if required. - bWakeUp = TRUE; - } - return bWakeUp; -} - -//-------------------------------------------------------------------------------------- -/*This function is called by application to indicate buffer processed and ready for stack to operate on */ -BYTE USBMSC_bufferProcessed() -{ - unsigned short bGIE; - - bGIE = (__get_SR_register() &GIE); //save interrupt status - // Disable interrupt - __disable_interrupt(); - - /* Fix for SDOCM00078384 */ - /* Reset bWriteProcessing after last buffer is processed by the application */ - if (sRwbuf.operation == kUSBMSC_WRITE && MscWriteControl.dwBytesToReceiveLeft == 0) // the Receive opereation (MSC_WRITE) is completed - { - MscWriteControl.pUserBuffer = NULL; // no more receiving pending - MscWriteControl.bWriteProcessing = FALSE; //ready to receive next CBW - } - - if (sRwbuf.operation == kUSBMSC_WRITE && sRwbuf.returnCode == kUSBMSC_RWSuccess) - { - //initialize user buffer. - MscWriteControl.pUserBuffer = xBufferAddr; - MscWriteControl.wFreeBytesLeft = MscControl.wMscUserBufferSize; - sRwbuf.operation = NULL; //no operation pending... - //read out next portion of data if available. - MSCFromHostToBuffer(); - - - } - else if (sRwbuf.operation == kUSBMSC_READ && sRwbuf.returnCode == kUSBMSC_RWSuccess) - { - WORD wCnt = sRwbuf.lbCount * MscControl.lbaSize; - - //trigger sending LBA(s) - MscSendData(sRwbuf.bufferAddr, wCnt); - - if (sRwbuf.lbCount >= MscReadControl.lbaCount) - { - //all bytes sent, reset structure - MscReadControl.lbaCount = 0; - } - else - { - //update read structure - MscReadControl.lbaCount -= sRwbuf.lbCount; - MscReadControl.lba += sRwbuf.lbCount; - } - sRwbuf.operation = NULL; //no operation pending... - } - - switch(sRwbuf.returnCode) - { - case kUSBMSC_RWSuccess: - Scsi_Residue = 0; - Reset_RequestSenseResponse(); - break; - // Set RequestSenseResponse if necessary? Maybe initialized values OK? - - case kUSBMSC_RWNotReady: - Scsi_Status =SCSI_FAILED; - Scsi_Residue = 1; - Reset_RequestSenseResponse(); - RequestSenseResponse.VALID = 1; - RequestSenseResponse.SenseKey = S_NOT_READY; - RequestSenseResponse.ASC = ASC_NOT_READY; - RequestSenseResponse.ASCQ = ASCQ_NOT_READY; - break; - - case kUSBMSC_RWIllegalReq: - Scsi_Status = SCSI_FAILED; - Scsi_Residue = 0; - Reset_RequestSenseResponse(); - RequestSenseResponse.VALID = 1; - RequestSenseResponse.SenseKey = S_ILLEGAL_REQUEST; - RequestSenseResponse.ASC = ASC_ILLEGAL_REQUEST; - RequestSenseResponse.ASCQ = ASCQ_ILLEGAL_REQUEST; - break; - - case kUSBMSC_RWUnitAttn: - Scsi_Status = SCSI_FAILED; - Scsi_Residue = 0; - Reset_RequestSenseResponse(); - RequestSenseResponse.VALID = 1; - RequestSenseResponse.SenseKey = S_UNITATTN; - RequestSenseResponse.ASC = ASC_UNITATTN_READY_NOTREADY; - RequestSenseResponse.ASCQ = ASCQ_UNITATTN_READY_NOTREADY; - break; - - case kUSBMSC_RWLbaOutOfRange: - Scsi_Status = SCSI_FAILED; - Scsi_Residue = 0; - Reset_RequestSenseResponse(); - RequestSenseResponse.VALID = 1; - RequestSenseResponse.SenseKey = S_ILLEGAL_REQUEST; - RequestSenseResponse.ASC = ASC_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; - RequestSenseResponse.ASCQ = ASCQ_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; - break; - - case kUSBMSC_RWMedNotPresent: - Scsi_Status = SCSI_FAILED; - Scsi_Residue = 0; - Reset_RequestSenseResponse(); - RequestSenseResponse.VALID = 1; - RequestSenseResponse.SenseKey = S_NOT_READY; - RequestSenseResponse.ASC =ASC_MEDIUM_NOT_PRESENT; - RequestSenseResponse.ASCQ = ASCQ_MEDIUM_NOT_PRESENT; - break; - - case kUSBMSC_RWDevWriteFault: - Scsi_Status = SCSI_FAILED; - Scsi_Residue = 0; - Reset_RequestSenseResponse(); - RequestSenseResponse.VALID = 1; - RequestSenseResponse.SenseKey = S_MEDIUM_ERROR; - RequestSenseResponse.ASC =ASC_WRITE_FAULT; - RequestSenseResponse.ASCQ = ASCQ_WRITE_FAULT; - break; - - case kUSBMSC_RWUnrecoveredRead: - Scsi_Status = SCSI_FAILED; - Scsi_Residue = 0; - Reset_RequestSenseResponse(); - RequestSenseResponse.VALID = 1; - RequestSenseResponse.SenseKey = S_MEDIUM_ERROR; - RequestSenseResponse.ASC = ASC_UNRECOVERED_READ; - RequestSenseResponse.ASCQ = ASCQ_UNRECOVERED_READ; - break; - - case kUSBMSC_RWWriteProtected: - Scsi_Status = SCSI_FAILED; - Scsi_Residue = 0; - Reset_RequestSenseResponse(); - RequestSenseResponse.VALID = 1; - RequestSenseResponse.SenseKey = S_WRITE_PROTECTED; - RequestSenseResponse.ASC = ASC_WRITE_PROTECTED; - RequestSenseResponse.ASCQ = ASCQ_WRITE_PROTECTED; - break; - // case breakouts for all the codes - } - - if(sRwbuf.returnCode != kUSBMSC_RWSuccess) - { - sRwbuf.operation = NULL; //no operation pending... - if (McsCbw.bmCBWFlags == DIRECTION_IN) - { - usbStallInEndpoint(MSC0_INTFNUM); - MscReadControl.bReadProcessing = FALSE; //ready to receive next CBW - MscReadControl.pUserBuffer = NULL; // no more receiving pending - MscReadControl.lbaCount = 0; - } - else - { - //we need to stall only if not all af data was transfered - if (MscWriteControl.dwBytesToReceiveLeft > 0) - { - usbStallOutEndpoint(MSC0_INTFNUM); - } - MscWriteControl.bWriteProcessing = FALSE; //ready to receive next CBW - MscWriteControl.pUserBuffer = NULL; // no more receiving pending - *MscWriteControl.pCT1 = 0x00; //clear NAK, EP ready to receive next data - *MscWriteControl.pCT2 = 0x00; //clear NAK, EP ready to receive next data - } - } - - __bis_SR_register(bGIE); //restore interrupt status - return kUSB_succeed; -} - -//------------------------------------------------------------------------------------------- -VOID Msc_ResetFlags() -{ - bMscCbwReceived = FALSE; -} - -//------------------------------------------------------------------------------------------- -VOID Msc_ResetStruct() -{ - memset(&sRwbuf,0,sizeof(USBMSC_RWbuf_Info)); - memset(&McsCbw,0,sizeof(CBW)); - memset(&McsCsw,0,sizeof(CSW)); - - MscReadControl.pUserBuffer = NULL; - MscReadControl.dwBytesToSendLeft = 0; - MscReadControl.bReadProcessing = FALSE; - - MscWriteControl.bWriteProcessing = FALSE; - MscWriteControl.pUserBuffer = NULL; - MscWriteControl.dwBytesToReceiveLeft = 0; // holds how many bytes is still requested by WRITE operation (Host to MSP430) - // we do not reset the bCurrentBufferXY, becuase the buffer doesnt changed if he MSC reseted. - // The bCurrentBufferXY should be reseted in USB_Reset() - - Reset_RequestSenseResponse(); -} - -//------------------------------------------------------------------------------------------- -VOID MscResetData() -{ - Msc_ResetStruct(); - - memset(&MscWriteControl , 0, sizeof(MscWriteControl)); - memset(&MscReadControl, 0, sizeof(MscReadControl)); -} - -//------------------------------------------------------------------------------------------- -VOID MscResetCtrlLun() -{ - int i; - for(i =0; i < MSC_MAX_LUN_NUMBER; i++) - { - sCtrlLun[i].bMediaPresent = 0x80; - sCtrlLun[i].bWriteProtected = FALSE; - } -} - -//------------------------------------------------------------------------------------------- -/* This function can be called by application to get the current status of stack operation */ -BYTE USBMSC_getState() -{ - BYTE state; - if (sRwbuf.operation == 0 && MscReadControl.bIsIdle == TRUE) - state = kUSBMSC_idle; - else if(sRwbuf.operation == kUSBMSC_READ && sRwbuf.lbCount > 0) - state = kUSBMSC_readInProgress; - else if(sRwbuf.operation == kUSBMSC_WRITE && sRwbuf.lbCount > 0) - state = kUSBMSC_writeInProgress; - else if(sRwbuf.operation == 0 && MscReadControl.bIsIdle == FALSE) - state = kUSBMSC_cmdBeingProcessed; - return state; -} - -//------------------------------------------------------------------------------------------- -BYTE USBMSC_updateMediaInfo( BYTE lun, struct USBMSC_mediaInfoStr *info) -{ - BYTE state; - - Scsi_Read_Capacity_10[lun].lLba[0] = (BYTE)(info->lastBlockLba >> 24); - Scsi_Read_Capacity_10[lun].lLba[1] = (BYTE)(info->lastBlockLba >> 16); - Scsi_Read_Capacity_10[lun].lLba[2] = (BYTE)(info->lastBlockLba >> 8); - Scsi_Read_Capacity_10[lun].lLba[3] = (BYTE)(info->lastBlockLba); - - Scsi_Read_Capacity_10[lun].bLength[0] = (BYTE)(info->bytesPerBlock >> 24); - Scsi_Read_Capacity_10[lun].bLength[1] = (BYTE)(info->bytesPerBlock >> 16); - Scsi_Read_Capacity_10[lun].bLength[2] = (BYTE)(info->bytesPerBlock >> 8); - Scsi_Read_Capacity_10[lun].bLength[3] = (BYTE)(info->bytesPerBlock); - - MscControl.lbaSize = (WORD)Scsi_Read_Capacity_10[lun].bLength[2] << 8 | Scsi_Read_Capacity_10[lun].bLength[3]; - MscControl.lbaBufCapacity = MscControl.wMscUserBufferSize / MscControl.lbaSize; - - // If the LUN was reported as not removable, then leave mediaPresent/mediaChanged as - // their initialized defaults. - if(USBMSC_config.LUN[lun].removable) - { - if(((sCtrlLun[lun].bMediaPresent== kUSBMSC_MEDIA_NOT_PRESENT)) && (info->mediaPresent == kUSBMSC_MEDIA_PRESENT)) // If media was inserted... - { - // Set Unit Attention flag. This flag is used in Scsi_Request_Sense(). - bUnitAttention = TRUE; - Scsi_Status = SCSI_FAILED; - } - - if((sCtrlLun[lun].bMediaPresent == kUSBMSC_MEDIA_PRESENT && ((info->mediaPresent == kUSBMSC_MEDIA_NOT_PRESENT))) || // If media was removed... - ((info->mediaPresent == kUSBMSC_MEDIA_PRESENT) && (info->mediaChanged))) // Or if media still present, but has changed... - { - // Set Unit Attention flag. This flag is used in Scsi_Request_Sense(). - bUnitAttention = TRUE; - Scsi_Status = SCSI_FAILED; - state = USBMSC_getState(); - - if(state == kUSBMSC_readInProgress || state == kUSBMSC_writeInProgress) - { - if (McsCbw.bmCBWFlags == DIRECTION_IN) - { - usbStallInEndpoint(MSC0_INTFNUM); - } - else - { - usbStallOutEndpoint(MSC0_INTFNUM); - } - - Msc_ResetStateMachine(); - Msc_ResetFlags(); - Msc_ResetStruct(); - isMSCConfigured = TRUE; - - Scsi_Send_CSW(MSC0_INTFNUM); - } - } - sCtrlLun[lun].bMediaPresent = info->mediaPresent; - } - - sCtrlLun[lun].bWriteProtected = info->writeProtected; - return kUSB_succeed; -} - -//------------------------------------------------------------------------------------------- -BYTE USBMSC_registerBufInfo(BYTE *RWbuf_x, BYTE *RWbuf_y, WORD size) -{ - MscControl.wMscUserBufferSize = 0; - xBufferAddr = NULL; - yBufferAddr = NULL; //this version supports only X buffer. - - //check if arguments are valid - if ((size < MscControl.lbaSize) || - (RWbuf_x == NULL) || - (RWbuf_y != NULL)) //this version supports only X buffer, so the y-buffer should be NULL - { - return kUSB_generalError; - } - - MscControl.wMscUserBufferSize = size; - xBufferAddr = RWbuf_x; - return kUSB_succeed; -} - -//------------------------------------------------------------------------------------------- -VOID SET_RequestsenseNotReady() -{ - // Set REQUEST SENSE with "not ready" - Reset_RequestSenseResponse(); - RequestSenseResponse.VALID = 1; - RequestSenseResponse.SenseKey = S_NOT_READY; - RequestSenseResponse.ASC =ASC_NOT_READY; - RequestSenseResponse.ASCQ = ASCQ_NOT_READY; - // Send CSW with error status - Scsi_Status = SCSI_FAILED; -} - -//------------------------------------------------------------------------------------------- -VOID SET_RequestsenseMediaNotPresent() -{ - // Set REQUEST SENSE with "not ready" - Reset_RequestSenseResponse(); - RequestSenseResponse.VALID = 1; - RequestSenseResponse.SenseKey = S_NOT_READY; - RequestSenseResponse.ASC =ASC_MEDIUM_NOT_PRESENT; - RequestSenseResponse.ASCQ = ASCQ_MEDIUM_NOT_PRESENT; - // Send CSW with error status - Scsi_Status = SCSI_FAILED; -} - -//------------------------------------------------------------------------------------------- -VOID usbClearOEPByteCount(BYTE intfNum) -{ - BYTE edbIndex; - edbIndex = stUsbHandle[intfNum].edb_Index; - tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX = 0; -} - -//------------------------------------------------------------------------------------------- -VOID usbStallEndpoint(BYTE intfNum) -{ - BYTE edbIndex; - edbIndex = stUsbHandle[intfNum].edb_Index; - tOutputEndPointDescriptorBlock[edbIndex].bEPCNF |= EPCNF_STALL; - tInputEndPointDescriptorBlock[edbIndex].bEPCNF |= EPCNF_STALL; -} - -//------------------------------------------------------------------------------------------- -VOID usbStallInEndpoint(BYTE intfNum) -{ - BYTE edbIndex; - edbIndex = stUsbHandle[intfNum].edb_Index; - tInputEndPointDescriptorBlock[edbIndex].bEPCNF |= EPCNF_STALL; -} - -//------------------------------------------------------------------------------------------- -VOID usbStallOutEndpoint(BYTE intfNum) -{ - BYTE edbIndex; - edbIndex = stUsbHandle[intfNum].edb_Index; - tOutputEndPointDescriptorBlock[edbIndex].bEPCNF |= EPCNF_STALL; -} - -//------------------------------------------------------------------------------------------- -USBMSC_RWbuf_Info* USBMSC_fetchInfoStruct(VOID) -{ - return &sRwbuf; -} -#endif //_MSC_ - -/*----------------------------------------------------------------------------+ -| End of source file | -+----------------------------------------------------------------------------*/ -/*------------------------ Nothing Below This Line --------------------------*/ diff --git a/USB_API/USB_MSC_API/UsbMscScsi.h b/USB_API/USB_MSC_API/UsbMscScsi.h deleted file mode 100644 index 924b59c..0000000 --- a/USB_API/USB_MSC_API/UsbMscScsi.h +++ /dev/null @@ -1,336 +0,0 @@ -/* - * UsbMscScsi.h - * - * This file contains all the structure,function declarations used by stack - * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/*----------------------------------------------------------------------------+ - | | - | Texas Instruments | - | | - | MSP430 USB-Example (MSC Driver) | - | | - +-----------------------------------------------------------------------------+ - | Source: Msc_Scsi.h, File Version 1.02 | - | Description: This file contains all the structure,function declarations | - | used by stack | - | Author: Biju,MSP | - | | - | WHO WHEN WHAT | - | --- ---------- ------------------------------------------------ | - | MSP 2010/02/16 Created | - | Biju,MSP 2010/07/15 CV bug fix | - +----------------------------------------------------------------------------*/ -#ifndef _UMSC_SCSI_H_ -#define _UMSC_SCSI_H_ - -#include - -#ifdef __cplusplus -extern "C" -{ -#endif - -/*Macros for CBW, CSW signatures */ -#define CBW_SIGNATURE 0x43425355u -#define CSW_SIGNATURE 0x53425355u - -/*CBW, CSW length in bytes */ -#define CBW_LENGTH 31 -#define CSW_LENGTH 13 - -/*SCSI Commands - Mandatory only implemented */ -#define SCSI_TEST_UNIT_READY 0x00 -#define SCSI_REQUEST_SENSE 0x03 -#define SCSI_INQUIRY 0x12 -#define SCSI_MODE_SENSE_6 0x1A -#define SCSI_MODE_SENSE_10 0x5A -#define SCSI_READ_CAPACITY_10 0x25 -#define SCSI_READ_10 0x28 -#define SCSI_WRITE_10 0x2A -#define SCSI_READ_FORMAT_CAPACITIES 0x23 -#define SCSI_MODE_SELECT_6 0x15 -#define SCSI_MODE_SELECT_10 0x55 -#define PREVENT_ALLW_MDM 0x1E -#define START_STOP_UNIT 0x1B -#define SCSI_REPORT_LUNS 0xA0 -#define SCSI_VERIFY 0x2F - -/*SCSI Status codes. Used in CSW response */ -#define SCSI_PASSED 0 -#define SCSI_FAILED 1 -#define SCSI_PHASE_ERROR 2 -#define SCSI_READWRITE_FAIL 2 - -#define kUSBMSC_RWSuccess 0 -#define kUSBMSC_RWNotReady 1 -#define kUSBMSC_RWIllegalReq 2 -#define kUSBMSC_RWUnitAttn 3 -#define kUSBMSC_RWLbaOutOfRange 4 -#define kUSBMSC_RWMedNotPresent 5 -#define kUSBMSC_RWDevWriteFault 6 -#define kUSBMSC_RWUnrecoveredRead 7 -#define kUSBMSC_RWWriteProtected 8 - - - /* Macros to indicate READ or WRITE operation */ -#define kUSBMSC_READ 1 -#define kUSBMSC_WRITE 2 - -#define kUSBMSC_MEDIA_PRESENT 0x81 -#define kUSBMSC_MEDIA_NOT_PRESENT 0x82 - -#define kUSBMSC_WRITE_PROTECTED 0x00 - -/* Defines for MSC SCSI State-Machine */ -#define MSC_READY 0x00 -#define MSC_COMMAND_TRANSPORT 0x01 -#define MSC_DATA_IN 0x02 -#define MSC_DATA_OUT 0x03 -#define MSC_STATUS_TRANSPORT 0x04 -#define MSC_DATA 0x05 -#define MSC_WAIT4RESET 0x06 - -/*Lengths of SCSI commands(in bytes) */ -#define SCSI_SCSI_INQUIRY_CMD_LEN 36 -#define SCSI_READ_CAPACITY_CMD_LEN 8 -#define SCSI_MODE_SENSE_6_CMD_LEN 4 -#define SCSI_MODE_SENSE_10_CMD_LEN 8 -#define SCSI_REQ_SENSE_CMD_LEN 18 -#define SCSI_READ_FORMAT_CAPACITY_CMD_LEN 12 -#define SCSI_REPORT_LUNS_CMD_LEN 16 -/*----------------------------------------------------------------------------+ -| Type defines and structures | -+----------------------------------------------------------------------------*/ -/*CBW Structure */ -typedef struct _CBW -{ - DWORD dCBWSignature; - DWORD dCBWTag; - DWORD dCBWDataTransferLength; - BYTE bmCBWFlags; - BYTE bCBWLUN; - BYTE bCBWCBLength; - BYTE CBWCB[16]; -} CBW, *pCBW; - -/*CSW structure */ -typedef struct _CSW -{ - DWORD dCSWSignature; - DWORD dCSWTag; - DWORD dCSWDataResidue; - BYTE bCSWStatus; -} CSW, *pCSW; - -/*Request Response union(Required for Request sense command) */ -typedef struct -{ - BYTE ResponseCode:7; - BYTE VALID:1; - BYTE Obsolete; - BYTE SenseKey:4; - BYTE Resv:1; - BYTE ILI:1; - BYTE EOM:1; - BYTE FILEMARK:1; - BYTE Information[4]; - BYTE AddSenseLen; - BYTE CmdSpecificInfo[4]; - BYTE ASC; - BYTE ASCQ; - BYTE FRUC; - BYTE SenseKeySpecific[3]; - BYTE padding[14]; /* padding to cover case where host requests 24 bytes of sense data */ - -} REQUEST_SENSE_RESPONSE; - -/*Read capacity union(Required for READ CAPACITY command)*/ -typedef struct -{ - DWORD Last_LBA; - BYTE Resv; - BYTE Size_LBA[3]; -} SCSI_READ_CAPACITY; - -/*Structure internal to stack for holding LBA,buffer addr etc information*/ -typedef struct -{ - // BYTE intfNum; - BYTE lun; - BYTE operation; - DWORD lba; - BYTE lbCount; - BYTE *bufferAddr; - BYTE returnCode; - BYTE XorY; -}USBMSC_RWbuf_Info; - -/*Structure exposed(shared) to application. Populated by stack */ -struct LBAInfo -{ - BYTE intfNum; - BYTE lun; - DWORD dLBA; - int iLBA_Count; - BYTE operation; - BYTE *bufferAddr; - BYTE returnCode; - BYTE XorY; -}; - -/*Media info structure */ -struct USBMSC_mediaInfoStr -{ - DWORD lastBlockLba; - DWORD bytesPerBlock; - BYTE mediaPresent; - BYTE mediaChanged; - BYTE writeProtected; -}; - -/*Lun entry Structures */ -struct _LUN_entry_struct -{ - BYTE number; - BYTE PDT; - BYTE removable; - char t10VID[8]; - char t10PID[16]; - char t10rev[4]; -}; - -struct config_struct -{ - struct _LUN_entry_struct LUN[MSC_MAX_LUN_NUMBER]; -}; - -struct _Report_Luns -{ - BYTE LunListLength[4]; - BYTE Reserved[4]; - BYTE LunList1[8]; -}; - -struct _Scsi_Read_Capacity -{ - BYTE lLba[4]; // Last logical block address - BYTE bLength[4]; // Block length, in this case 0x200 = 512 bytes for each Logical Block -}; - -//structure for controlling WRITE phase (HOST to MSP430) -struct _MscWriteControl -{ - DWORD dwBytesToReceiveLeft; // holds how many bytes is still requested by WRITE operation: - // Host to MSP430. - WORD wFreeBytesLeft; // free bytes left in UserBuffer - DWORD lba; // holds the current LBA number. This is the first LBA in the UserBuffer - BYTE *pUserBuffer; // holds the current position of user's receiving buffer. - //If NULL- no receiving operation started - WORD wCurrentByte; // how many bytes in current LBA are received - BYTE lbaCount; // how many LBA we have received in current User Buffer - BYTE * pCT1; // holds current EPBCTxx register - BYTE * pCT2; // holds next EPBCTxx register - BYTE * pEP2; // holds addr of the next EP buffer - BYTE bCurrentBufferXY; // indicates which buffer is used by host to transmit data via OUT - BYTE bWriteProcessing; // indicated if the current state is DATA WRITE phase or CBW receiwing -}; - -//structure for controlling READ phase (MSP430 to HOST) -struct _MscReadControl -{ - DWORD dwBytesToSendLeft;// holds how many bytes is still requested by WRITE operation (Host to MSP430) - BYTE *pUserBuffer; // holds the current position of user's receiving buffer. - //If NULL- no receiving operation started - DWORD lba; // holds the current LBA number. This is the first LBA in the UserBuffer. - BYTE * pCT1; // holds current EPBCTxx register - BYTE * pCT2; // holds next EPBCTxx register - BYTE * pEP2; // holds addr of the next EP buffer - BYTE lbaCount; // how many LBA we have to send to Host - BYTE bCurrentBufferXY; // indicates which buffer is used by host to transmit data via OUT - BYTE bReadProcessing; // indicated if the current state is DATA READ phase or CSW sending - // initiated by McsDataSend() - BYTE bIsIdle; // -}; - -//structure for common control of MSC stack -struct _MscControl -{ - WORD wMscUserBufferSize; - WORD lbaSize; // limitid to WORD, but could be increased if required. - BYTE lbaBufCapacity; // how many LBAs (max) contains UserBuffer for read/write operation (>=1) -}; - - -struct _CtrlLun -{ - BYTE bMediaPresent; - BYTE bWriteProtected; -}; -extern struct _MscWriteControl MscWriteControl; -extern struct _MscReadControl MscReadControl; -extern struct _MscControl MscControl; - -/*----------------------------------------------------------------------------+ -| Extern Variables | -+----------------------------------------------------------------------------*/ -extern volatile DWORD Scsi_Residue; - -extern CBW cbw; -extern CSW csw; -extern REQUEST_SENSE_RESPONSE RequestSenseResponse; - -/*----------------------------------------------------------------------------+ -| Function Prototypes | -+----------------------------------------------------------------------------*/ - -/*SCSI Wrapper functions */ -BYTE Scsi_Cmd_Parser(BYTE opcode); -BYTE Scsi_Send_CSW(BYTE intfNum); - -/*Function to reset MSC SCSI state machine */ -VOID Msc_ResetStateMachine(VOID); -VOID Msc_ResetFlags(VOID); -VOID Msc_ResetStruct(VOID); -VOID SET_RequestsenseNotReady(VOID); -VOID SET_RequestsenseMediaNotPresent(VOID); -VOID MscResetCtrlLun(VOID); - -USBMSC_RWbuf_Info* USBMSC_fetchInfoStruct(VOID); -#ifdef __cplusplus -} -#endif -#endif // _MSC_SCSI_H_ - diff --git a/USB_API/USB_MSC_API/UsbMscStateMachine.c b/USB_API/USB_MSC_API/UsbMscStateMachine.c deleted file mode 100644 index 36c4b84..0000000 --- a/USB_API/USB_MSC_API/UsbMscStateMachine.c +++ /dev/null @@ -1,203 +0,0 @@ -/* - * UsbMscStateMachine.c - * - * This file contains the core function that handles the MSC SCSI state machine. - * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - - /*----------------------------------------------------------------------------+ - | | - | Texas Instruments | - | | - | MSP430 USB-Example (MSC Driver) | - | | - +-----------------------------------------------------------------------------+ - | Source: Msc_State_Machine.c, File Version 1.01 | - | Description: This file contains the core function that handles the MSC SCSI| - | state machine. | - | Author: Biju,MSP | - | | - | WHO WHEN WHAT | - | --- ---------- ------------------------------------------------ | - | MSP 2010/02/16 Created | - | Biju,MSP 2010/07/15 CV Bug fix | - | RSTO 2010/10/30 state machine rework | - +----------------------------------------------------------------------------*/ -/*File includes */ -#include "../USB_Common/device.h" -#include "../USB_Common/types.h" -#include "../USB_Common/defMSP430USB.h" -#include "../USB_MSC_API/UsbMscScsi.h" -#include "../USB_MSC_API/UsbMsc.h" -#include "../USB_Common/usb.h" -#include -#include - -#ifdef _MSC_ - -/*Macros to indicate data direction */ -#define DIRECTION_IN 0x80 -#define DIRECTION_OUT 0x00 - -/*Flags to monitor data send/recv.Will be set in ISR accordingly */ -extern BOOL bMscCbwReceived; //Flag to indicate whether any CBW recieved from host -extern BOOL bMcsCommandSupported; //Flag to know if its a supported command -extern BOOL bMscCbwFailed; - -/* Variable that holds the MSC SCSI state */ -static BOOL bMscSendCsw = FALSE; -extern BOOL isMSCConfigured; - -/*Buffer pointers passed by application */ -extern BYTE *xBufferAddr; -extern BYTE *yBufferAddr; -extern __no_init tEDB __data16 tInputEndPointDescriptorBlock[]; - -BYTE Scsi_Verify_CBW(); - -/*----------------------------------------------------------------------------+ - | Functions | -+----------------------------------------------------------------------------*/ -VOID Msc_ResetStateMachine(VOID) -{ - bMscSendCsw = FALSE; - Scsi_Residue = 0; -} - -//---------------------------------------------------------------------------- -/*This is the core function called by application to handle the MSC SCSI state - machine */ -BYTE USBMSC_poll() -{ - BYTE edbIndex; - BYTE ret; - - edbIndex = stUsbHandle[MSC0_INTFNUM].edb_Index; - - //check if currently transmitting data.. - if (MscReadControl.bReadProcessing == TRUE) - { - BYTE bGIE; - bGIE = (__get_SR_register() &GIE); //save interrupt status - // atomic operation - disable interrupts - __disable_interrupt(); // Disable global interrupts - if ((MscReadControl.dwBytesToSendLeft == 0) && - (MscReadControl.lbaCount == 0)) - { - //data is no more processing - clear flags.. - MscReadControl.bReadProcessing = FALSE; - __bis_SR_register(bGIE); //restore interrupt status - } - else - { - if (!(tInputEndPointDescriptorBlock[edbIndex].bEPCNF & EPCNF_STALL)) //if it is not stalled - contiune communication - { - USBIEPIFG |= 1<<(edbIndex+1); //trigger IN interrupt to finish data tranmition - } - __bis_SR_register(bGIE); //restore interrupt status - return kUSBMSC_processBuffer; - } - } - - if(isMSCConfigured == FALSE) - { - return kUSBMSC_okToSleep; - } - - if (!bMscSendCsw) - { - - ret = kUSBMSC_processBuffer; - if (bMscCbwReceived) - { - if (Scsi_Verify_CBW() == SUCCESS) - { - MscReadControl.bIsIdle = FALSE; - // Successful reception of CBW - // Parse the CBW opcode and invoke the right command handler function - Scsi_Cmd_Parser(MSC0_INTFNUM); - bMscSendCsw = TRUE; - } - bMscCbwReceived = FALSE; //CBW is performed! - } - else - { - if(!MscReadControl.bIsIdle) - { - return kUSBMSC_processBuffer; - } - else - { - return kUSBMSC_okToSleep; - } - } - //check if any of out pipes has pending data and trigger interrupt - - if ((MscWriteControl.pCT1 != NULL) && - ((*MscWriteControl.pCT1 & EPBCNT_NAK ) || - (*MscWriteControl.pCT2 & EPBCNT_NAK ))) - { - USBOEPIFG |= 1<<(edbIndex+1); //trigger OUT interrupt again - return kUSBMSC_processBuffer; //do not asleep, as data is coming in - //and follow up data perform will be required. - } - } - - if (bMscSendCsw) - { - if (bMcsCommandSupported == TRUE) - { - // watiting till transport is finished! - if ((MscWriteControl.bWriteProcessing == FALSE) && - (MscReadControl.bReadProcessing == FALSE) && - (MscReadControl.lbaCount == 0)) - { - // Send CSW - if(SUCCESS == Scsi_Send_CSW(MSC0_INTFNUM)) - { - MscReadControl.bIsIdle = TRUE; - bMscSendCsw = FALSE; - ret = kUSBMSC_okToSleep; - } - } - } - } - return ret; -} - -#endif // _MSC_ -/*----------------------------------------------------------------------------+ -| End of source file | -+----------------------------------------------------------------------------*/ -/*------------------------ Nothing Below This Line --------------------------*/ diff --git a/USB_API/USB_MSC_API/UsbMscStateMachine.h b/USB_API/USB_MSC_API/UsbMscStateMachine.h deleted file mode 100644 index e9363f7..0000000 --- a/USB_API/USB_MSC_API/UsbMscStateMachine.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * UsbMscStateMachine.h - * - * This file contains the core function that handles the MSC SCSI state machine. - * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/*----------------------------------------------------------------------------+ - | | - | Texas Instruments | - | | - | MSP430 USB-Example (MSC Driver) | - | | - +-----------------------------------------------------------------------------+ - | Source: UsbMsc.h, File Version 1.01 | - | Description: This file contains API declarations for function to use by | - | User Application. | - | Author: Biju,MSP | - | | - | WHO WHEN WHAT | - | --- ---------- ------------------------------------------------ | - | RSTO 2010/10/29 Created | - +----------------------------------------------------------------------------*/ -#ifndef _USB_MSCSTATE_H_ -#define _USB_MSCSTATE_H_ - -#ifdef __cplusplus -extern "C" -{ -#endif - - //this file is obsolete. To delete in next version. - -#ifdef __cplusplus -} -#endif -#endif //_USB_MSCSTATE_H_ - diff --git a/USB_config/MSP430_CDC.inf b/USB_config/MSP430_CDC.inf deleted file mode 100644 index 0a57fd2..0000000 --- a/USB_config/MSP430_CDC.inf +++ /dev/null @@ -1,92 +0,0 @@ -; Copyright (c) 2010 Texas Instruments -; MSP430 Virtual COM Port Installation file for Win2000/XP/Vista/7 -; -; Port drivers setup -; -; Supported operating systems: -; Windows 32-bit and 64-bit -[Version] - -Signature="$Windows NT$" -CatalogFile=MSP430_CDC.cat -Class=Ports -ClassGuid={4D36E978-E325-11CE-BFC1-08002BE10318} -Provider=%TI% -DriverVer=09/06/2010, 1.02 - -[Manufacturer] -%TI%=DeviceList, NTamd64 - -[DestinationDirs] -FakeModemCopyFileSection=12 -DefaultDestDir=12 - -[SourceDisksNames] - -[SourceDisksFiles] - -;You can modify next string and place your VID and PID -[DeviceList] -%DESCRIPTION0%=TIUSB, USB\Vid_2047&Pid_0300 - -[DeviceList.NTamd64] -%DESCRIPTION0%=TIUSB.NTamd64, USB\Vid_2047&Pid_0300 - - ;------------------------------------------------------------------------------ -; Windows 32-bit Sections -;------------------------------------------------------------------------------ - -[TIUSB.nt] -include=mdmcpq.inf -CopyFiles=FakeModemCopyFileSection -AddReg=TIUSB.nt.AddReg - -[TIUSB.nt.AddReg] -HKR,,NTMPDriver,,*ntkern -HKR,,NTMPDriver,,usbser.sys -HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider" -HKR,,PortSubClass,1,01 - -[TIUSB.nt.Services] -AddService=usbser, 0x00000002, DriverService - -[TIUSB.nt.HW] -include=mdmcpq.inf - -[DriverService] -DisplayName=%DESCRIPTION% -ServiceType=1 -StartType=3 -ErrorControl=1 -ServiceBinary=%12%\usbser.sys -LoadOrderGroup=Base - -;------------------------------------------------------------------------------ -; Windows 64-bit Sections -;------------------------------------------------------------------------------ - -[TIUSB.NTamd64] -include=mdmcpq.inf -CopyFiles=FakeModemCopyFileSection -AddReg=TIUSB.NTamd64.AddReg - -[TIUSB.NTamd64.AddReg] -HKR,,NTMPDriver,,*ntkern -HKR,,NTMPDriver,,usbser.sys -HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider" -HKR,,PortSubClass,1,01 - -[TIUSB.NTamd64.Services] -AddService=usbser, 0x00000002, DriverService - -[TIUSB.NTamd64.HW] -include=mdmcpq.inf - -;------------------------------------------------------------------------------ -; String Definitions -;------------------------------------------------------------------------------ - -[Strings] -TI="Texas Instruments" -DESCRIPTION="MSP430-USB Example" -DESCRIPTION0="Virtual UART0" diff --git a/USB_config/descriptors.dat b/USB_config/descriptors.dat deleted file mode 100644 index da02a66..0000000 Binary files a/USB_config/descriptors.dat and /dev/null differ diff --git a/USB_config/descriptors.h b/USB_config/descriptors.h deleted file mode 100644 index f1b8301..0000000 --- a/USB_config/descriptors.h +++ /dev/null @@ -1,343 +0,0 @@ -// (c)2010 by Texas Instruments Incorporated, All Rights Reserved. -/*-----------------------------------------------------------------------------+ -| | -| Texas Instruments | -| | -| This is an automatically generated script by MSP430 USB Descriptor Tool | -| | -| Descriptor Tool Version: 3.0.10 | -| Date: 2011/10/25 21:16:05 | -| | -| Descriptor.h | -|-----------------------------------------------------------------------------*/ - -#ifndef _DESCRIPTORS_H_ -#define _DESCRIPTORS_H_ - -#ifdef __cplusplus -extern "C" -{ -#endif - -/*-----------------------------------------------------------------------------+ -| Include files | -|-----------------------------------------------------------------------------*/ -#include - -//*********************************************************************************************** -// CDC or HID - Define both for composite support -//*********************************************************************************************** -#define _CDC_ // Needed for CDC inteface -//*********************************************************************************************** -// CONFIGURATION CONSTANTS -//*********************************************************************************************** -// These constants configure the API stack and help define the USB descriptors. -// Refer to Sec. 6 of the MSP430 USB CDC API Programmer's Guide for descriptions of these constants. - -// Configuration Constants that can change -// #define that relates to Device Descriptor -#define USB_VID 0x2047 // Vendor ID (VID) -#define USB_PID 0x030B // Product ID (PID) -/*----------------------------------------------------------------------------+ -| Firmware Version | -| How to detect version number of the FW running on MSP430? | -| on Windows Open ControlPanel->Systems->Hardware->DeviceManager->Ports-> | -| Msp430->ApplicationUART->Details | -+----------------------------------------------------------------------------*/ -#define VER_FW_H 0x01 // Device release number, in binary-coded decimal -#define VER_FW_L 0x00 // Device release number, in binary-coded decimal -// If a serial number is to be reported, set this to the index within the string descriptor -//of the dummy serial number string. It will then be automatically handled by the API. -// If no serial number is to be reported, set this to 0. -#define USB_STR_INDEX_SERNUM 3 - - -#define DESCRIPTOR_TOTAL_LENGTH 67 // wTotalLength, This is the sum of configuration descriptor length + CDC descriptor length + HID descriptor length -#define USB_NUM_INTERFACES 2 // Number of implemented interfaces. - -#define CDC0_COMM_INTERFACE 0 // Comm interface number of CDC0 -#define CDC0_DATA_INTERFACE 1 // Data interface number of CDC0 -#define CDC0_INTEP_ADDR 0x81 // Interrupt Endpoint Address of CDC0 -#define CDC0_OUTEP_ADDR 0x02 // Output Endpoint Address of CDC0 -#define CDC0_INEP_ADDR 0x82 // Input Endpoint Address of CDC0 - -#define CDC_NUM_INTERFACES 1 // Total Number of CDCs implemented. should set to 0 if there are no CDCs implemented. -#define HID_NUM_INTERFACES 0 // Total Number of HIDs implemented. should set to 0 if there are no HIDs implemented. -#define MSC_NUM_INTERFACES 0 // Total Number of MSCs implemented. should set to 0 if there are no MSCs implemented. -// Interface numbers for the implemented CDSs and HIDs, This is to use in the Application(main.c) and in the interupt file(UsbIsr.c). -#define CDC0_INTFNUM 0 -#define MSC_MAX_LUN_NUMBER 1 // Maximum number of LUNs supported - -#define USB_OUTEP_INT_EN BIT0 | BIT2 -#define USB_INEP_INT_EN BIT0 | BIT1 | BIT2 -// MCLK frequency of MCU, in Hz -// For running higher frequencies the Vcore voltage adjustment may required. -// Please refer to Data Sheet of the MSP430 device you use -#define USB_MCLK_FREQ 20000000 // MCLK frequency of MCU, in Hz -#define USB_PLL_XT 2 // Defines which XT is used by the PLL (1=XT1, 2=XT2) -#define USB_XT_FREQ USBPLL_SETCLK_4_0 // Indicates the freq of the crystal on the oscillator indicated by USB_PLL_XT -#define USB_DISABLE_XT_SUSPEND 1 // If non-zero, then USB_suspend() will disable the oscillator - // that is designated by USB_PLL_XT; if zero, USB_suspend won't - // affect the oscillator -#define USB_DMA_CHAN 0x00 // Set to 0xFF if no DMA channel will be used 0..7 for selected DMA channel - - - -// Controls whether the remote wakeup feature is supported by this device. -// A value of 0x20 indicates that is it supported (this value is the mask for -// the bmAttributes field in the configuration descriptor). -// A value of zero indicates remote wakeup is not supported. -// Other values are undefined, as they will interfere with bmAttributes. -#define USB_SUPPORT_REM_WAKE 0x00 - -// Controls whether the application is self-powered to any degree. Should be -// set to 0x40, unless the USB device is fully supplied by the bus. -#define USB_SUPPORT_SELF_POWERED 0x80 - -// Controls what the device reports to the host regarding how much power it will -// consume from VBUS. Expressed in 2mA units; that is, the number of mA -// communicated is twice the value of this field. -#define USB_MAX_POWER 0x32 -//Configuration constants that can not change ( Fixed Values) -#define CDC_CLASS 2 -#define HID_CLASS 3 -#define MSC_CLASS 4 - -#define MAX_PACKET_SIZE 0x40 // Max size of the USB packets. - -//*********************************************************************************************** -// DESCRIPTOR CONSTANTS -//*********************************************************************************************** -#define SIZEOF_DEVICE_DESCRIPTOR 0x12 -#define SIZEOF_REPORT_DESCRIPTOR 36 -#define USBHID_REPORT_LENGTH 64 // length of whole HID report (including Report ID) -#define CONFIG_STRING_INDEX 4 -#define INTF_STRING_INDEX 5 -#define USB_CONFIG_VALUE 0x01 -//*********************************************************************************************** -// OUTWARD DECLARATIONS -//*********************************************************************************************** - -//Calculates the endpoint descriptor block number from given address -#define EDB(addr) ((addr&0x07)-1) - -/* Structure for generic part of configuration descriptor */ -struct abromConfigurationDescriptorGenric -{ - BYTE sizeof_config_descriptor; // bLength - BYTE desc_type_config; // bDescriptorType: 2 - BYTE sizeof_configuration_descriptor1; // wTotalLength - BYTE sizeof_configuration_descriptor2; - BYTE usb_num_configurations; // bNumInterfaces - BYTE bconfigurationvalue; // bConfigurationValue - BYTE config_string_index; // iConfiguration Description offset - BYTE mattributes; // bmAttributes, bus power, remote wakeup - BYTE usb_max_power; // Max. Power Consumption at 2mA unit -}; - -/************************************************CDC Descriptor**************************/ -struct abromConfigurationDescriptorCdc -{ -// interface descriptor (9 bytes) - BYTE blength_intf; // blength: interface descriptor size - BYTE desc_type_interface; // bdescriptortype: interface - BYTE interface_number_cdc; // binterfacenumber - BYTE balternatesetting; // balternatesetting: alternate setting - BYTE bnumendpoints; // bnumendpoints: three endpoints used - BYTE binterfaceclass; // binterfaceclass: communication interface class - BYTE binterfacesubclass; // binterfacesubclass: abstract control model - BYTE binterfaceprotocol; // binterfaceprotocol: common at commands - BYTE intf_string_index; // interface: -//header functional descriptor - BYTE blength_header; // blength: endpoint descriptor size - BYTE bdescriptortype_header; // bdescriptortype: cs_interface - BYTE bdescriptorsubtype_header; // bdescriptorsubtype: header func desc - BYTE bcdcdc1; - BYTE bcdcdc2; // bcdcdc: spec release number - -//call managment functional descriptor - BYTE bfunctionlength; // bfunctionlength - BYTE bdescriptortype_c; // bdescriptortype: cs_interface - BYTE bdescriptorsubtype_c; // bdescriptorsubtype: call management func desc - BYTE bmcapabilities; // bmcapabilities: d0+d1 - BYTE intf_number_cdc; // bdatainterface: 0 - -//acm functional descriptor - BYTE bfunctionlength_acm; // bfunctionlength - BYTE bdescriptortype_acm; // bdescriptortype: cs_interface - BYTE bdescriptorsubtype_acm; // bdescriptorsubtype: abstract control management desc - BYTE bmcapabilities_acm; // bmcapabilities - -// Union Functional Descriptor - BYTE bLength_ufd; // Size, in bytes - BYTE bdescriptortype_ufd; // bDescriptorType: CS_INTERFACE - BYTE bdescriptorsubtype_ufd; // bDescriptorSubtype: Union Functional Desc - BYTE bmasterinterface_ufd; // bMasterInterface -- the controlling intf for the union - BYTE bslaveinterface_ufd; // bSlaveInterface -- the controlled intf for the union - -//Interrupt end point related fields - BYTE sizeof_epintep_descriptor; // blength: endpoint descriptor size - BYTE desc_type_epintep; // bdescriptortype: endpoint - BYTE cdc_intep_addr; // bendpointaddress: (in2) - BYTE epintep_desc_attr_type_int; // bmattributes: interrupt - BYTE epintep_wmaxpacketsize1; - BYTE epintep_wmaxpacketsize; // wmaxpacketsize, 64 bytes - BYTE epintep_binterval; // binterval - -// Data interface descriptor (9 bytes) - BYTE blength_slaveintf; // blength: interface descriptor size - BYTE desc_type_slaveinterface; // bdescriptortype: interface - BYTE interface_number_slavecdc; // binterfacenumber - BYTE balternatesetting_slave; // balternatesetting: alternate setting - BYTE bnumendpoints_slave; // bnumendpoints: three endpoints used - BYTE binterfaceclass_slave; // binterfaceclass: data interface class - BYTE binterfacesubclass_slave; // binterfacesubclass: abstract control model - BYTE binterfaceprotocol_slave; // binterfaceprotocol: common at commands - BYTE intf_string_index_slave; // interface: - -// Bulk out end point related fields - BYTE sizeof_outep_descriptor; // blength: endpoint descriptor size - BYTE desc_type_outep; // bdescriptortype: endpoint - BYTE cdc_outep_addr; // bendpointaddress: (out3) - BYTE outep_desc_attr_type_bulk; // bmattributes: bulk - BYTE outep_wmaxpacketsize1; - BYTE outep_wmaxpacketsize2; // wmaxpacketsize, 64 bytes - BYTE outep_binterval; // binterval: ignored for bulk transfer - -// Bulk in related fields - BYTE sizeof_inep_descriptor; // blength: endpoint descriptor size - BYTE desc_type_inep; // bdescriptortype: endpoint - BYTE cdc_inep_addr; // bendpointaddress: (in3) - BYTE inep_desc_attr_type_bulk; // bmattributes: bulk - BYTE inep_wmaxpacketsize1; - BYTE inep_wmaxpacketsize2; // wmaxpacketsize, 64 bytes - BYTE inep_binterval; // binterval: ignored for bulk transfer -} ; - -/**************************************HID descriptor structure *************************/ -struct abromConfigurationDescriptorHid -{ -//INTERFACE DESCRIPTOR (9 bytes) - BYTE sizeof_interface_descriptor; // Desc Length - BYTE desc_type_interface; // DescriptorType - BYTE interface_number_hid; // Interface number - BYTE balternatesetting; // Any alternate settings if supported - BYTE bnumendpoints; // Number of end points required - BYTE binterfaceclass; // Class ID - BYTE binterfacesubclass; // Sub class ID - BYTE binterfaceprotocol; // Protocol - BYTE intf_string_index; // String Index - -//hid descriptor (9 bytes) - BYTE blength_hid_descriptor; // HID Desc length - BYTE hid_descriptor_type; // HID Desc Type - BYTE hidrevno1; // Rev no - BYTE hidrevno2; // Rev no - 2nd part - BYTE tcountry; // Country code - BYTE numhidclasses; // Number of HID classes to follow - BYTE report_descriptor_type; // Report desc type - BYTE tlength; // Total length of report descriptor - BYTE size_rep_desc; - -//input end point descriptor (7 bytes) - BYTE size_inp_endpoint_descriptor; // End point desc size - BYTE desc_type_inp_endpoint; // Desc type - BYTE hid_inep_addr; // Input end point address - BYTE ep_desc_attr_type_inp_int; // Type of end point - BYTE inp_wmaxpacketsize1; // Max packet size - BYTE inp_wmaxpacketsize2; - BYTE inp_binterval; // bInterval in ms - - // Output end point descriptor; (7 bytes) - BYTE size_out_endpoint_descriptor; // Output endpoint desc size - BYTE desc_type_out_endpoint; // Desc type - BYTE hid_outep_addr; // Output end point address - BYTE ep_desc_attr_type_out_int; // End point type - BYTE out_wmaxpacketsize1; // Max packet size - BYTE out_wmaxpacketsize2; - BYTE out_binterval; // bInterval in ms -}; - -/**************************************MSC descriptor structure *************************/ -struct abromConfigurationDescriptorMsc -{ -// INTERFACE DESCRIPTOR (9 bytes) - BYTE sizeof_interface_descriptor; // Desc Length - BYTE desc_type_interface; // DescriptorType - BYTE interface_number_hid; // Interface number - BYTE balternatesetting; // Any alternate settings if supported - BYTE bnumendpoints; // Number of end points required - BYTE binterfaceclass; // Class ID - BYTE binterfacesubclass; // Sub class ID - BYTE binterfaceprotocol; // Protocol - BYTE intf_string_index; // String Index - -// input end point descriptor (7 bytes) - BYTE size_inp_endpoint_descriptor; // End point desc size - BYTE desc_type_inp_endpoint; // Desc type - BYTE hid_inep_addr; // Input end point address - BYTE ep_desc_attr_type_inp_int; // Type of end point - BYTE inp_wmaxpacketsize1; // Max packet size - BYTE inp_wmaxpacketsize2; - BYTE inp_binterval; // bInterval in ms - -// Output end point descriptor; (7 bytes) - BYTE size_out_endpoint_descriptor; // Output endpoint desc size - BYTE desc_type_out_endpoint; // Desc type - BYTE hid_outep_addr; // Output end point address - BYTE ep_desc_attr_type_out_int; // End point type - BYTE out_wmaxpacketsize1; // Max packet size - BYTE out_wmaxpacketsize2; - BYTE out_binterval; // bInterval in ms -}; - -/* Global structure having Generic,CDC,HID, MSC structures */ -struct abromConfigurationDescriptorGroup -{ - /* Generic part of config descriptor */ - const struct abromConfigurationDescriptorGenric abromConfigurationDescriptorGenric; -#ifdef _MSC_ - /* MSC descriptor structure */ - const struct abromConfigurationDescriptorMsc stMsc[MSC_NUM_INTERFACES]; -#endif -#ifdef _CDC_ - /* CDC descriptor structure */ - const struct abromConfigurationDescriptorCdc stCdc[CDC_NUM_INTERFACES]; -#endif -#ifdef _HID_ - /* HID descriptor structure */ - const struct abromConfigurationDescriptorHid stHid[HID_NUM_INTERFACES]; -#endif -}; - -extern const struct abromConfigurationDescriptorGroup abromConfigurationDescriptorGroup; -extern BYTE const abromDeviceDescriptor[SIZEOF_DEVICE_DESCRIPTOR]; -extern BYTE const abromStringDescriptor[]; -extern BYTE const abromReportDescriptor[SIZEOF_REPORT_DESCRIPTOR]; - -/* Handle Structure - Will be populated in descriptors.c based on number of CDC,HID interfaces */ -struct tUsbHandle -{ - BYTE ep_In_Addr; // Input EP Addr - BYTE ep_Out_Addr; // Output EP Addr - BYTE edb_Index; // The EDB index - BYTE dev_Class; // Device Class- 2 for CDC, 3 for HID - WORD intepEP_X_Buffer; // Interupt X Buffer Addr - WORD intepEP_Y_Buffer; // Interupt Y Buffer Addr - WORD oep_X_Buffer; // Output X buffer Addr - WORD oep_Y_Buffer; // Output Y buffer Addr - WORD iep_X_Buffer; // Input X Buffer Addr - WORD iep_Y_Buffer; // Input Y Buffer Addr -}; - -extern const struct tUsbHandle stUsbHandle[CDC_NUM_INTERFACES + HID_NUM_INTERFACES + MSC_NUM_INTERFACES]; -extern const tDEVICE_REQUEST_COMPARE tUsbRequestList[]; - -#ifdef __cplusplus -} -#endif - -#endif - -/*------------------------ Nothing Below This Line --------------------------*/ - diff --git a/baudrateselect.c b/baudrateselect.c deleted file mode 100644 index 9926966..0000000 --- a/baudrateselect.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - * baudrateselect.c - * - * Forwards baudrade change requests to individual peripheral modules. - * - * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include -#include "uart.h" -#include "i2c.h" -#include "main.h" - -extern enum active_peripherals active_peripheral; - -/* Configures the peripheral module selected by baudrate change */ -BYTE BaudrateSelect(ULONG lBaudrate) -{ - BYTE baudIndex; - - switch(lBaudrate) - { - /* UART peripheral */ - case 1200: - active_peripheral = UART; - baudIndex = InitUart(lBaudrate); - break; - case 2400: - active_peripheral = UART; - baudIndex = InitUart(lBaudrate); - break; - case 4800: - active_peripheral = UART; - baudIndex = InitUart(lBaudrate); - break; - case 4801: - active_peripheral = UART; - baudIndex = InitUart(lBaudrate); - break; - case 4802: - active_peripheral = UART; - baudIndex = InitUart(lBaudrate); - break; - case 9600: - active_peripheral = UART; - baudIndex = InitUart(lBaudrate); - break; - case 9601: - active_peripheral = UART; - baudIndex = InitUart(lBaudrate); - break; - /* reserved for future devices invoke sequence - case 9602: newInvoke(2); break; - case 9603: newInvoke(3); break; - case 9604: newInvoke(4); break; - case 9605: newInvoke(5); break; - case 9606: newInvoke(6); break; - case 9607: newInvoke(7); break; - case 9608: newInvoke(8); break; - case 9609: newInvoke(9); break; - case 9610: newInvoke(10); break; - case 9611: newInvoke(11); break; - case 9612: newInvoke(12); break; - case 9613: newInvoke(13); break; - case 9614: newInvoke(14); break; - case 9615: newInvoke(15); break; - case 9616: newInvoke(16); break; - case 9617: newInvoke(17); break; - case 9618: newInvoke(18); break; - */ - case 19200: - active_peripheral = UART; - baudIndex = InitUart(lBaudrate); - break; - case 38400: - active_peripheral = UART; - baudIndex = InitUart(lBaudrate); - break; - case 57600: - active_peripheral = UART; - baudIndex = InitUart(lBaudrate); - break; - case 115200: - active_peripheral = UART; - baudIndex = InitUart(lBaudrate); - break; - case 230400: - active_peripheral = UART; - baudIndex = InitUart(lBaudrate); - break; - case 460800: - active_peripheral = UART; - baudIndex = InitUart(lBaudrate); - break; - case 921600: - active_peripheral = UART; - baudIndex = InitUart(lBaudrate); - break; - - /* I2C peripheral */ - case 100000: - active_peripheral = I2C; - baudIndex = InitI2C(BSL_SLAVE_ADDR, lBaudrate); - break; - case 100001: - active_peripheral = I2C; - baudIndex = InitI2C(BSL_SLAVE_ADDR, lBaudrate); - break; - case 400000: - active_peripheral = I2C; - baudIndex = InitI2C(BSL_SLAVE_ADDR, lBaudrate); - break; - case 400001: - active_peripheral = I2C; - baudIndex = InitI2C(BSL_SLAVE_ADDR, lBaudrate); - break; - - default: - baudIndex = 0; - break; - - } - - return baudIndex; -} diff --git a/baudrateselect.h b/baudrateselect.h deleted file mode 100644 index cba4080..0000000 --- a/baudrateselect.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * baudrateselect.h - * - * Forwards baudrade change requests to individual peripheral modules. - * - * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef BAUDRATESELECT_H_ -#define BAUDRATESELECT_H_ - -/* Configures the peripheral module selected by baudrate change */ -BYTE BaudrateSelect(ULONG lBaudrate); - -#endif //BAUDRATESELECT_H_ \ No newline at end of file diff --git a/doc/MSP-BSL User's Guide.pdf b/doc/MSP-BSL User's Guide.pdf new file mode 100644 index 0000000..bed449a Binary files /dev/null and b/doc/MSP-BSL User's Guide.pdf differ diff --git a/firmware/MSP-BSL_3.0.d43 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+2C 24 B0 13 2A A6 21 52 4C 93 F2 23 92 53 2C 24 +B2 90 0A 01 2C 24 02 20 82 43 2C 24 10 01 5E 42 +23 09 7E F0 7F 00 4E 4E 82 9E 50 24 1D 28 4F 43 +09 3C 4F 4F 1D 42 54 24 DD 4F 70 23 00 00 92 53 +54 24 5F 53 4F 9E F5 2B 4E 4E 82 8E 50 24 82 93 +50 24 05 24 B0 13 F0 B2 E2 43 F1 27 10 01 B0 13 +02 B3 C2 43 F1 27 10 01 B0 13 02 B3 C2 43 F1 27 +10 01 1B 15 3B 40 08 1A 09 3C CB 9C 00 00 01 20 +7D 53 5A 4B 01 00 4A 4A 0B 5A 2B 53 3B 90 FF 1A +08 2C CB 9C 00 00 02 20 4D 93 03 24 FB 93 00 00 +EC 23 CB 9C 00 00 07 20 DE 4B 01 00 00 00 2B 53 +8F 4B 00 00 04 3C CE 43 00 00 8F 43 00 00 1A 17 +10 01 1B 15 4B 4C 5C 43 7B F0 03 00 1A 42 20 01 +7A F0 03 00 01 3C 4C 43 4B 9A 16 24 4C 93 14 24 +4A 9B 08 2C 5A 53 4C 4A B0 13 08 95 0C 93 F3 27 +5C 43 F2 3F 7A 53 4C 4A B0 13 5E 9C 0C 93 02 24 +5C 43 EA 3F 4C 43 E8 3F 1A 17 10 01 B2 40 98 AF +58 24 B2 40 00 00 5A 24 B2 40 98 AF 5C 24 B2 40 +00 00 5E 24 70 12 20 00 70 12 C0 00 4F 43 0E 43 +3D 40 00 10 4C 43 B0 13 06 AB B2 40 66 A8 58 24 +B2 40 00 00 5A 24 B2 40 66 A8 5C 24 B2 40 00 00 +5E 24 21 52 10 01 3B 15 31 80 0A 00 4A 4C 0B 4E +58 41 16 00 59 41 18 00 0C 41 0C 53 3E 40 05 00 +B0 13 2C B2 C1 4A 00 00 81 4D 02 00 81 4B 04 00 +C1 4F 06 00 C1 48 07 00 C1 49 08 00 0C 41 0C 53 +B0 13 12 A4 31 50 0A 00 38 17 10 01 82 93 82 23 +1C 20 5F 42 84 23 7F F0 0F 00 4F 93 03 20 B0 13 +4A B2 15 3C 7F 53 7F 90 07 00 11 2C C2 93 84 23 +05 34 4F 4F 5F 0A FF D2 C8 23 04 3C 4F 4F 5F 0A +FF D2 88 23 B0 13 4A B2 02 3C B0 13 C6 B2 4C 43 +10 01 3B 15 0A 4C 0B 4D 0E 43 2D 43 7C 42 B0 13 +C8 A1 0E 43 3D 40 05 00 5C 43 B0 13 C8 A1 0E 4A +0F 4B 0E 5E 0E 4F 0E 6E 0F 43 0F 6F 0D 4E 08 4D +0C 4A 0D 4B 3E 40 E8 03 0F 43 B0 13 80 AD 0D 48 +B0 13 44 AE 38 17 10 01 1F 42 6C 01 3F F0 00 C0 +0F 9C 05 24 B2 F0 FF 3F 6C 01 82 DC 6C 01 B2 C0 +00 10 6C 01 B2 C0 00 01 6C 01 F2 C2 6E 01 E2 C3 +02 01 F2 B2 6E 01 03 28 3D 53 0D 93 F6 23 0D 93 +02 24 5C 43 10 01 4C 43 10 01 4C 43 F2 D0 10 00 +3C 09 03 3C F2 F0 FA 00 3E 09 C2 93 80 23 03 34 +D2 D3 3C 09 02 3C D2 C3 3C 09 C2 43 F1 27 4F 43 +04 3C 4F 4F CF 43 E1 27 5F 53 7F 92 FA 2B B0 13 +EE A2 D2 B3 3E 09 E6 2F 10 01 5F 42 84 23 7F F0 +0F 00 4F 93 03 20 B0 13 4A B2 14 3C 7F 53 7F 90 +07 00 10 2C C2 93 84 23 06 34 4F 4F 5F 0A FF F0 +D7 00 C8 23 05 3C 4F 4F 5F 0A FF F0 D7 00 88 23 +B0 13 4A B2 4C 43 10 01 3E 40 0A 00 0D 43 3C 40 +10 24 B0 13 1A B2 3E 40 10 00 0D 43 3C 40 1A 24 +B0 13 1A B2 3E 42 0D 43 3C 40 08 24 B0 13 1A B2 +0E 43 05 3C 0F 4E 5F 0A FF 42 0C 24 1E 53 1E 93 +F9 3B 10 01 3B 15 4B 4C 4A 4D B0 13 72 9F 48 4C +4A 93 04 24 3C 40 FF 01 B0 13 E2 B2 4B 93 0C 24 +B0 13 72 AE 5C B3 08 28 B0 13 1A 94 4C 93 04 20 +B0 13 DC 8F B0 13 F4 B0 4C 48 38 17 10 01 7E 40 +03 00 17 3C D2 D3 02 02 E2 D3 02 02 3F 40 CE 12 +3D 40 13 00 3F 53 3D 63 FD 2F D2 C3 02 02 E2 C3 +02 02 3F 40 CE 12 3D 40 13 00 3F 53 3D 63 FD 2F +7E 53 5E 93 E7 2F 10 01 0A 12 4A 43 F2 D0 10 00 +3C 09 C2 43 21 09 E2 93 F1 27 0D 20 B0 13 CE A9 +C2 93 F1 27 0A 20 F2 90 20 00 81 23 06 20 B0 13 +A2 A4 4A 4C 02 3C F2 D2 22 09 4C 4A 3A 41 10 01 +09 12 0A 12 0B 12 0A 43 0B 43 39 40 20 00 0C 5C +0D 6D 0A 6A 0B 6B 0A 8E 0B 7F 04 28 1C D3 39 53 +F6 23 04 3C 0A 5E 0B 6F 39 53 F1 23 0E 4A 0F 4B +3B 41 3A 41 39 41 10 01 D2 43 F2 27 B2 40 28 96 +00 09 F2 D0 10 00 3C 09 F2 C0 40 00 3E 09 B2 C0 +00 01 10 09 B0 13 DA B2 F2 40 20 00 3D 09 B2 40 +00 96 00 09 4C 43 10 01 5F 42 2E 09 4F 4F 1D 43 +4E 4C 5E 53 5E 83 02 30 CE 18 0D 5D 5E 53 0F FD +1E 43 5C 53 5C 83 02 30 CC 18 0E 5E 5C 53 C2 CE +2E 09 0C 4F 10 01 5F 42 2F 09 4F 4F 1D 43 4E 4C +5E 53 5E 83 02 30 CE 18 0D 5D 5E 53 0F FD 1E 43 +5C 53 5C 83 02 30 CC 18 0E 5E 5C 53 C2 CE 2F 09 +0C 4F 10 01 21 83 0F 4D 44 18 0F 5F 81 4F 00 00 +B0 13 CE 96 05 3C 03 43 03 43 3F 42 3F 53 FE 2F +2F 41 0E 4F 3E 53 81 4E 00 00 0F 93 F4 23 21 53 +10 01 4C 43 B2 B2 08 09 01 28 5C D3 D2 93 F3 27 +02 20 7C D0 20 00 A2 B3 02 09 02 28 7C D0 40 00 +D2 93 F2 27 02 20 7C D2 10 01 7C D0 10 00 10 01 +0A 12 4A 4C 3A 50 16 05 1F 15 00 18 FA 41 00 00 +4F 4C 3F 50 10 05 BF F0 FF F3 00 00 4C 4C 3C 50 +10 05 5D 06 8C DD 00 00 3A 41 10 01 0A 12 4A 4C +3A 50 12 05 1F 15 00 18 FA 41 00 00 4F 4C 3F 50 +10 05 BF F0 FF FC 00 00 4C 4C 3C 50 10 05 8C DD +00 00 3A 41 10 01 4F 4C 0F 5F 1F 4F 1A 81 5C B3 +4E 7E 5E F3 4E 93 03 24 3D F0 FF 00 8D 10 0E 4F +3E 50 0A 00 8E CD 00 00 2F 52 8F DD 00 00 10 01 +4F 4C 0F 5F 1F 4F 1A 81 5C B3 4E 7E 5E F3 4E 93 +03 24 3D F0 FF 00 8D 10 0E 4F 2E 52 8E DD 00 00 +3F 50 0A 00 8F DD 00 00 10 01 F2 B0 40 00 4F 81 +02 28 D2 43 E1 27 D2 93 F4 27 02 20 E2 D3 E1 27 +B0 13 F0 B2 A2 43 4E 24 3C 40 E1 27 B0 13 42 B0 +4C 43 10 01 4C 43 B0 13 02 B3 D2 42 82 23 DE 27 +B0 13 4A B2 D2 93 DE 27 04 20 D2 43 F3 27 80 00 +30 B3 C2 43 F3 27 10 01 0A 12 21 83 0A 43 09 3C +0F 4D 0F 5A E1 4F 00 00 0F 4C 0F 5A EF 41 00 00 +1A 53 0A 9E F5 2B 21 53 3A 41 10 01 B2 40 28 96 +00 09 A2 C3 02 09 B2 C0 00 04 08 09 B2 40 00 96 +00 09 C2 43 F3 27 C2 43 F2 27 4C 43 10 01 F2 F0 +F0 00 6E 01 E2 C3 02 01 E2 B3 02 01 03 28 3C 53 +0C 93 F5 23 5C 42 6E 01 4C 4C 3C F0 0F 00 10 01 +B2 40 28 96 00 09 82 43 02 09 B2 C0 00 01 10 09 +B2 40 00 96 00 09 C2 43 F3 27 C2 43 F2 27 4C 43 +10 01 B0 13 02 B3 B2 90 80 00 82 23 06 2C D2 42 +82 23 3F 09 B0 13 4A B2 02 3C B0 13 C6 B2 4C 43 +10 01 82 4C 52 24 1F 42 86 23 82 9F 4E 24 05 28 +82 4F 4E 24 C2 43 E0 27 02 3C D2 43 E0 27 80 00 +92 A7 4F 4C 0F 5F 1F 4F 1A 81 5C B3 4E 7E 5E F3 +4E 93 03 24 3D F0 FF 00 8D 10 2F 53 8F CD 00 00 +10 01 B0 13 F0 B2 A2 43 4E 24 C2 43 E1 27 D2 42 +DF 27 E2 27 3C 40 E1 27 B0 13 42 B0 4C 43 10 01 +B0 13 F0 B2 A2 43 4E 24 C2 43 E1 27 D2 42 DF 27 +E2 27 3C 40 E1 27 B0 13 42 B0 4C 43 10 01 0F 4C +3F 50 0C 00 2F 4F 7F D0 80 00 4F 4F 3F 50 00 5A +3C 50 0C 00 8C 4F 00 00 10 01 F2 D0 10 00 3C 09 +C2 43 23 09 D2 93 F1 27 02 20 80 00 92 A7 F2 D2 +20 09 10 01 B2 40 28 96 00 09 A2 D3 02 09 B2 D0 +00 04 08 09 B2 40 00 96 00 09 4C 43 10 01 B0 13 +1A 94 F2 F0 9F 00 3E 09 F2 40 C4 00 3D 09 C2 43 +F2 27 4C 43 10 01 92 93 82 23 05 20 D2 43 F4 27 +B0 13 4A B2 02 3C B0 13 C6 B2 4C 43 10 01 92 93 +82 23 05 20 C2 43 F4 27 B0 13 4A B2 02 3C B0 13 +C6 B2 4C 43 10 01 B0 13 F0 B2 B2 40 43 00 4E 24 +3C 40 48 81 B0 13 42 B0 4C 43 10 01 B0 13 F0 B2 +B2 40 12 00 4E 24 3C 40 36 81 B0 13 42 B0 4C 43 +10 01 5D 42 82 23 5C 42 84 23 B0 13 20 B3 B0 13 +4A B2 4C 43 10 01 B0 13 1A 94 4C 93 04 20 B0 13 +DC 8F B0 13 F4 B0 5C 43 10 01 4C 4C 5C 0E 8C 93 +1A 24 02 24 5C 43 01 3C 4C 43 4C 4C 10 01 B0 13 +F0 B2 92 43 4E 24 3C 40 DE 27 B0 13 42 B0 4C 43 +10 01 0F 4C 04 3C FF 4D 00 00 1F 53 3E 53 0E 93 +FA 23 10 01 B0 13 02 B3 D2 42 84 23 DF 27 B0 13 +4A B2 4C 43 10 01 82 4C 54 24 92 42 86 23 50 24 +E2 43 F1 27 80 00 F0 B2 0F 4C 0F 5D 03 3C CC 43 +00 00 1C 53 0C 9F FB 23 10 01 0F 4C 04 3C CF 4D +00 00 1F 53 3E 53 0E 93 FA 23 10 01 0C 12 8C 43 +00 00 2C 53 1E 83 FB 23 3C 41 10 01 4C 4C 3C 50 +10 05 BC D0 10 00 00 00 10 01 B2 43 4E 24 C2 43 +F1 27 C2 43 21 09 10 01 D2 B3 3E 09 02 2C B0 13 +C6 B2 4C 43 10 01 4C 4C 3C 50 10 05 BC C0 10 00 +00 00 10 01 4C 4C 3C 50 10 05 9C D3 00 00 10 01 +3C 40 E9 27 B0 13 F6 B1 4C 43 10 01 4C 4C 3C 50 +10 05 2C 4C 3C F2 10 01 0C 4E 0D 4F B0 13 E2 8D +4C 43 10 01 B0 13 BC AF B0 13 00 B0 5C 43 10 01 +4C 4C 3C 50 1A 05 8C 4D 00 00 10 01 4C 4C DC 43 +D8 26 4C 43 10 01 F2 D2 20 09 F2 D2 22 09 10 01 +4C 4C DC 43 D9 26 4C 43 10 01 B2 D0 00 01 6C 01 +10 01 82 4C 56 24 4C 43 10 01 3C 40 06 24 10 01 +C2 43 23 09 10 01 A2 C2 08 05 10 01 A2 D2 08 05 +10 01 F2 D2 22 09 10 01 C2 DC 2F 09 10 01 C2 DC +2E 09 10 01 E2 D2 E0 05 10 01 C2 CC 02 01 10 01 +4C 43 10 01 4C 43 10 01 80 00 4C B3 80 00 28 B3 +5C 43 10 01 5C 43 10 01 5C 43 10 01 5C 43 10 01 +5C 43 10 01 80 00 D2 B1 1F 15 10 01 FF 3F 03 43 +@FFE6 +84 82 +@FFEE +2E 84 FE 83 +@FFFA +C6 83 +@FFFE +5C 82 +q diff --git a/initMCU.c b/initMCU.c deleted file mode 100644 index 8e18114..0000000 --- a/initMCU.c +++ /dev/null @@ -1,240 +0,0 @@ -/* - * initMCU.c - * - * Provides initialization functions. - * - * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include -#include "USB_API/USB_Common/types.h" -#include "USB_API/USB_Common/device.h" -#include "F5xx_F6xx_Core_Lib/HAL_UCS.h" -#include "F5xx_F6xx_Core_Lib/HAL_PMM.h" - -#include "USB_config/descriptors.h" -#include "USB_API/USB_Common/usb.h" // USB-specific functions -#include "USB_API/USB_CDC_API/UsbCdc.h" - -#include "uart.h" -#include "i2c.h" - -void Port_Mapping(void); - -//---------------------------------------------------------------------------- -VOID Init_Clock(VOID) -{ - #if defined (__MSP430F563x_F663x) - while(BAKCTL & LOCKIO) // Unlock XT1 pins for operation - BAKCTL &= ~(LOCKIO); // enable XT1 pins - // Workaround for USB7 - UCSCTL6 &= ~XT1OFF; - #endif - if (USB_PLL_XT == 2) - { - #if defined (__MSP430F552x) || defined (__MSP430F550x) - P5SEL |= 0x0C; // enable XT2 pins for F5529 - #elif defined (__MSP430F563x_F663x) - P7SEL |= 0x0C; - #endif - // Use the REFO oscillator to source the FLL and ACLK - UCSCTL3 = (UCSCTL3 & ~(SELREF_7)) | (SELREF__REFOCLK); - UCSCTL4 = (UCSCTL4 & ~(SELA_7)) | (SELA__REFOCLK); - - // MCLK will be driven by the FLL (not by XT2), referenced to the REFO - Init_FLL(USB_MCLK_FREQ/1000, USB_MCLK_FREQ/32768); // Start the FLL, at the freq indicated by the config constant USB_MCLK_FREQ - - //XT2_Start(XT2DRIVE_3); // Start the "USB crystal" - } - else - { - #if defined (__MSP430F552x) || defined (__MSP430F550x) - P5SEL |= 0x10; // enable XT1 pins - #endif - // Use the REFO oscillator to source the FLL and ACLK -// UCSCTL3 = SELREF__REFOCLK; -// UCSCTL4 = (UCSCTL4 & ~(SELA_7)) | (SELA__REFOCLK); - - P5SEL |= 0x30; // enable XT1 pins for F5509 - LFXT_Start(XT1DRIVE_3); - // Use the LFXT1 oscillator to source the FLL and ACLK - UCSCTL3 = SELA__XT1CLK; - UCSCTL4 = (UCSCTL4 & ~(SELA_7)) | (SELA__XT1CLK); - - - // MCLK will be driven by the FLL (not by XT2), referenced to the REFO - Init_FLL(USB_MCLK_FREQ/1000, USB_MCLK_FREQ/32768); // set FLL (DCOCLK) - - //XT1_Start(XT1DRIVE_3); // Start the "USB crystal" - } -} - -//---------------------------------------------------------------------------- -VOID Init_Ports(VOID) -{ - // Drive all I/O's as output-low, making sure there's no shoot-through current. There - // should be no floating I/Os, to prevent unnecessary current draw during USB suspend. - PAOUT = 0x0000; - PASEL = 0x0000; - PAREN = 0xF0FF; - PADIR = 0x0F00; - - PBOUT = 0x0000; - PBSEL = 0x0000; - PBREN = 0xFFFF; - - PCOUT = 0x0000; - PCSEL = 0x0000; - PCREN = 0xFFFF; - - #ifndef __MSP430F550x - PDOUT = 0x0000; // If using a device other than: - PDSEL = 0x0000; // F5510, F5529, F5638, or F6638 - PDREN = 0xF0FF; - PDDIR = 0xFFFF; // you may need to comment out these lines - #endif - - - #if defined (__MSP430F563x_F663x) - P9OUT = 0x00; - P9SEL = 0x00; - P9REN = 0xFF; - #endif - - PJDIR = (0xFFFF - RESET_PIN - TEST_PIN); - PJOUT = 0x0000; - - P1DIR |= 0x03; // for LEDs -} - - - -//---------------------------------------------------------------------------- -VOID Init_StartUp(VOID) -{ - WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer - - __disable_interrupt(); // Disable global interrupts - - Init_Ports(); // Init ports (do first ports because clocks do change ports) - SetVCore(3); // USB core requires the VCore set to 1.8 volt, independ of CPU clock frequency - Init_Clock(); - - __enable_interrupt(); // enable global interrupts - - Port_Mapping(); - -#ifdef UART_BASED - #ifdef UART0_INTFNUM - InitUart0(9600); - #endif - - #ifdef UART1_INTFNUM - InitUart1(9600); - #endif -#endif - -#ifdef I2C_BASED -#ifdef UART0_INTFNUM - InitI2C(BSL_SLAVE_ADDR, 400000); - #endif -#endif - -} - -//---------------------------------------------------------------------------- -VOID ConfigUSB(VOID) -{ - USB_init(); // Init USB - - // Enable various USB event handling routines - - USB_setEnabledEvents(kUSB_VbusOnEvent+kUSB_VbusOffEvent+kUSB_receiveCompletedEvent - +kUSB_dataReceivedEvent+kUSB_UsbSuspendEvent+kUSB_UsbResumeEvent+kUSB_UsbResetEvent); - - - // See if we're already attached physically to USB, and if so, connect to it - // Normally applications don't invoke the event handlers, but this is an exception. - - if (USB_connectionInfo() & kUSB_vbusPresent) - { - if (USB_enable() == kUSB_succeed) - { - USB_reset(); - USB_connect(); - } - } - -} - -//---------------------------------------------------------------------------- -void Port_Mapping(void) -{ - // Disable Interrupts before altering Port Mapping registers - __disable_interrupt(); - // Enable Write-access to modify port mapping registers - PMAPPWD = 0x02D52; - - #ifdef PORT_MAP_RECFG - // Allow reconfiguration during runtime - PMAPCTL = PMAPRECFG; - #endif - - #ifdef __MSP430F550x - //P4MAP0 = PM_UCA0RXD; - //P4MAP1 = PM_UCA0TXD; -#ifdef UART_BASED - P4MAP4 = PM_UCA0TXD; - P4MAP5 = PM_UCA0RXD; -#elif I2C_BASED - P4MAP4 = PM_UCB0SCL; - P4MAP5 = PM_UCB0SDA; -#else -#error Define a valid interface -#endif - //P4MAP7 = PM_MCLK; - #endif - #ifdef __MSP430F563x_F663x - P2MAP0 = PM_UCA0TXD; - P2MAP1 = PM_UCA0RXD; - #endif - - // Disable Write-Access to modify port mapping registers - PMAPPWD = 0; - #ifdef PORT_MAP_EINT - __enable_interrupt(); // Re-enable all interrupts - #endif -} -//---------------------------------------------------------------------------- -//End of file. -//---------------------------------------------------------------------------- diff --git a/initMCU.h b/initMCU.h deleted file mode 100644 index 4908151..0000000 --- a/initMCU.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * initMCU.h - * - * Provides initialization functions. - * - * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef INITMCU_H_ -#define INITMCU_H_ - -VOID Init_Clock(VOID); -VOID Init_Ports(VOID); -VOID Init_StartUp(VOID); -VOID ConfigUSB(VOID); - -#endif /*INITMCU_H_*/ diff --git a/main.c b/main.c deleted file mode 100644 index 5103db8..0000000 --- a/main.c +++ /dev/null @@ -1,313 +0,0 @@ -/* - * main.c - * - * Main function of MSP430-BSL. Based on MSP430 USB-Example (CDC/HID Driver) - * - * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include -#include "USB_API/USB_Common/device.h" -#include "USB_API/USB_Common/types.h" // Basic Type declarations -#include "USB_API/USB_Common/usb.h" // USB-specific functions -#include "USB_config/descriptors.h" -#include "USB_API/USB_CDC_API/UsbCdc.h" -#include "usb/usbConstructs.h" - -#include "main.h" -#include "initMCU.h" -#include "timer.h" - -#include -#include - -enum active_peripherals active_peripheral = I2C; - -#if (!defined (UART_BASED) && !defined(I2C_BASED)) -#error "Define a valid interface" -#endif - -#include "i2c.h" -#include "uart.h" - -#ifdef I2C_BASED -#include "BSL_Comm.h" -BYTE dataBuffer[300]; // buffer for data receiving -volatile BYTE bDataSendCompleted_event[CDC_NUM_INTERFACES] = {FALSE}; -volatile BYTE bDataReceiveCompleted_event[CDC_NUM_INTERFACES] = {FALSE}; // data receive completed event -unsigned char UART_FSM(BYTE* dataBuffer); -#endif - -//------------------------------------------------------------------------------ -VOID BlinkLed(VOID) -{ - //static BYTE nCount = 0; - - //if(nCount++ > 100) - //{ - // nCount = 0; - TogglePin(1,0);// Toggle LED P1.0 - //} -} - -/*----------------------------------------------------------------------------+ -| Main Routine | -+----------------------------------------------------------------------------*/ -VOID main(VOID) -{ -#ifdef I2C_BASED - BYTE ret; - WORD bytes_sent, bytes_received; - int16_t sendDataLength = 0; - unsigned int BSLCommandLength = 0; - int16_t requireSlaveAnswer = 1; -#endif - - Init_StartUp(); //initialize device - ConfigUSB(); //configure USB - Delay(3000000); // !!! Do not remove this delay !!! - Init_TimerA2(); - TogglePin(1,0); - TogglePin(1,1); - __delay_cycles(5000000); - TogglePin(1,0); - TogglePin(1,1); - __delay_cycles(5000000); - TogglePin(1,0); - TogglePin(1,1); - __delay_cycles(5000000); - TogglePin(1,0); - TogglePin(1,1); - __delay_cycles(5000000); - __enable_interrupt(); // enable global interrupts -#ifdef UART_BASED - while(1); -#elif defined (I2C_BASED) - while(1) - { - if(active_peripheral == UART) - { - //Check the USB state and directly main loop accordingly - switch (USB_connectionState()) - { - case ST_USB_DISCONNECTED: - // __bis_SR_register(LPM3_bits + GIE); //Enter LPM3 w/ interrupts enabled - _NOP(); //For Debugger - break; - - case ST_USB_CONNECTED_NO_ENUM: - break; - - case ST_ENUM_ACTIVE: - //__bis_SR_register(LPM0_bits + GIE); //Enter LPM0 (can't do LPM3 when active) - //_NOP(); //For Debugger - - ret = USBCDC_intfStatus(CDC0_INTFNUM, &bytes_sent, &bytes_received); - if (ret & kUSBCDC_dataWaiting) - { - //_NOP(); // Send data received from USB to UART - USBCDC_receiveData(dataBuffer, 1, CDC0_INTFNUM); - while(UCA0STAT & UCBUSY); - UCA0TXBUF = dataBuffer[0]; - } - -// if(UCA0IFG & UCRXIFG) -// { -// _NOP(); // Send data received from UART to USB -// bDataSendCompleted_event[0] = FALSE; -// ret = USBCDC_sendData((BYTE*)&UCA0RXBUF, 1, CDC0_INTFNUM); -// while (bDataSendCompleted_event == FALSE){}; -// UCA0IFG &= ~UCRXIFG; -// } - - break; - - case ST_ENUM_SUSPENDED: - // P1OUT &= ~BIT0; //When suspended, turn off LED - // __bis_SR_register(LPM3_bits + GIE); //Enter LPM3 w/ interrupts - _NOP(); - break; - - case ST_ENUM_IN_PROGRESS: - break; - - case ST_NOENUM_SUSPENDED: - // P1OUT &= ~BIT0; - //__bis_SR_register(LPM3_bits + GIE); - _NOP(); - break; - - case ST_ERROR: - _NOP(); - break; - - default:; - } - } - else if(active_peripheral == I2C) - { - //Check the USB state and directly main loop accordingly - switch (USB_connectionState()) - { - case ST_USB_DISCONNECTED: - // __bis_SR_register(LPM3_bits + GIE); //Enter LPM3 w/ interrupts enabled - _NOP(); //For Debugger - break; - - case ST_USB_CONNECTED_NO_ENUM: - break; - - case ST_ENUM_ACTIVE: - //__bis_SR_register(LPM0_bits + GIE); //Enter LPM0 (can't do LPM3 when active) - //_NOP(); //For Debugger - - ret = USBCDC_intfStatus(CDC0_INTFNUM, &bytes_sent, &bytes_received); - if (ret & kUSBCDC_dataWaiting) - { - BSLCommandLength = UART_FSM(dataBuffer); - } - if (BSLCommandLength > 0) - { - // Special command to just get data - if (BSLCommandLength == 0x01) - { - // If response is OK, request response from Slave - sendDataLength = i2cReceiveMessage(dataBuffer); - if ((requireSlaveAnswer < 0) || (sendDataLength < 0)) - { - // If there was an error, report to PC - sendDataLength = 1; - dataBuffer[0] = 0x55; // Temporary error code - } - } - else - { - requireSlaveAnswer = i2cSendMessage(dataBuffer, BSLCommandLength); - i2cStopSending(); - __delay_cycles(10000); - - if (requireSlaveAnswer == 0x00) - { - sendDataLength = 0; // Don't send response to PC - } - else if(requireSlaveAnswer > 0) - { - // If response is OK, request response from Slave - sendDataLength = i2cReceiveMessage(dataBuffer); - } - - if ((requireSlaveAnswer < 0) || (sendDataLength < 0)) - { - // If there was an error, report to PC - sendDataLength = 1; - dataBuffer[0] = 0x55; // Temporary error code - } - BSLCommandLength = 0; - } - } - - if (sendDataLength > 0) - { - //send data back to PC - bDataSendCompleted_event[0] = FALSE; - ret = USBCDC_sendData((BYTE*)&dataBuffer, sendDataLength, CDC0_INTFNUM); - while (bDataSendCompleted_event == FALSE){}; -/* - do - { - ret = USBCDC_intfStatus(CDC0_INTERFACE_NUMBER, &bytes_sent, &bytes_received); - } - while (ret & kUSBCDC_waitingForSend); -*/ - sendDataLength = 0; - __no_operation(); - } - - break; - - case ST_ENUM_SUSPENDED: - // P1OUT &= ~BIT0; //When suspended, turn off LED - // __bis_SR_register(LPM3_bits + GIE); //Enter LPM3 w/ interrupts - _NOP(); - break; - - case ST_ENUM_IN_PROGRESS: - break; - - case ST_NOENUM_SUSPENDED: - // P1OUT &= ~BIT0; - //__bis_SR_register(LPM3_bits + GIE); - _NOP(); - break; - - case ST_ERROR: - _NOP(); - break; - - default:; - } - } - } -#endif - -} //main() - -//------------------------------------------------------------------------------ -#pragma vector = UNMI_VECTOR -__interrupt VOID UNMI_ISR(VOID) -{ - switch (__even_in_range(SYSUNIV, SYSUNIV_BUSIFG)) - { - case SYSUNIV_NONE: - __no_operation(); - break; - case SYSUNIV_NMIIFG: - __no_operation(); - break; - case SYSUNIV_OFIFG: - UCSCTL7 &= ~(DCOFFG+0+0+0); // Clear OSC flaut Flags fault flags - SFRIFG1 &= ~OFIFG; // Clear OFIFG fault flag - break; - case SYSUNIV_ACCVIFG: - __no_operation(); - break; - case SYSUNIV_BUSIFG: - SYSBERRIV = 0; // clear bus error flag - USB_disable(); // Disable - } -} - - -//------------------------------------------------------------------------------ -//End of file. -//------------------------------------------------------------------------------ diff --git a/main.h b/main.h deleted file mode 100644 index 1a118eb..0000000 --- a/main.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * main.h - * - * Main function of MSP430-BSL. Based on MSP430 USB-Example (CDC/HID Driver) - * - * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef _MAIN_H_ -#define _MAIN_H_ - -#include "USB_API/USB_Common/device.h" - -#ifdef __cplusplus -extern "C" -{ -#endif - -/** -Call all needed Init_...() functions. - Needed Init_...() functions depends on build settings. -*/ - -enum active_peripherals{UART, I2C}; - -// Macro definition -#define SetPinOut(px,py) P##px##DIR |= (1< - - - - - - - - - -ASP Software Manifest - - - - - - - - - - - - - -
- -

 

- -

- - - - - - - - - - - - - - - - - - - -                                                                                                             -February 13, 2014

- -

 

- -

 

- -

- - -MSP430-BSL -Manifest

- -

 

- -

 

- -

 

- -

Legend (explanation of the fields in the -Manifest Table below)

- -

 

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-

Software Name

- 		-

The name of the application or file

-
-

Version

- 		-

Version of the application or file

-
-

License Type

- 		-

Type of license(s) under which TI will be providing software - to the licensee (e.g. BSD, GPLv2, TI TSPA License, TI Commercial License). - See Open Source Reference License Disclaimer in the Disclaimers Section.

-
-

Location

- 		-

The directory name and path on the media (or in an - archive) where the Software is located.

-
-

Delivered As

- 		-

This field will either be “Source”, “Binary” or - “Source and Binary” and is the form the content of the Software is delivered - in.  If the Software is delivered in an - archive format, this field applies to the contents of the archive. If the - word Limited is used with Source, as in “Limited Source” or “Limited Source - and Binary” then only portions of the Source for the application are - provided.

-
-

Modified by TI

- 		-

This field will either be “Yes” or “No”. A “Yes” means - TI has made changes to the Software. A “No” means TI has not made any - changes. Note: This field is not applicable for Software “Obtained from” TI.

-
-

Obtained from

- 		-

This field specifies from where or from whom TI - obtained the Software. It may be a URL to an Open Source site, a 3rd - party licensor, or TI (if TI developed the software). If this field contains - a link to Open Source software, the date TI downloaded the Software is also - recorded. See Links Disclaimer in the Disclaimers Section.

-
- -

 

- -

 

- -

 

- -

DISCLAIMERS

- -

 

- -

Export Control Classification Number (ECCN)

- -

 

- -

Any use of ECCNs -listed in the Manifest is at the user’s risk and without recourse to TI.   Your company, as the exporter of record, is -responsible for determining the correct classification of any item at the time -of export. Any export classification by TI of Software is for TI’s internal use -only and shall not be construed as a representation or warranty regarding the -proper export classification for such Software or whether an export license or -other documentation is required for exporting such Software.  -

- -

 

- -

Links in the Manifest

- -

 

- -

Any links appearing on this Manifest -(for example in the “Obtained from” field) were verified at the time the -Manifest was created. TI makes no guarantee that any listed links will remain -active in the future.

- -

Open Source License -References

- -

Your company is responsible for -confirming the applicable license terms for any open source Software listed in -this Manifest that was not “Obtained from” TI.  -Any open source license specified in this Manifest for Software that was -not “Obtained from” TI is for TI’s internal use only and shall not be construed -as a representation or warranty regarding the proper open source license terms -for such Software.

- -
- - -

 

- -

Export Information

- -

 

- -

ECCN for Software included in this release: EAR99

- -

 

- -

ECCN for Technology (e.g., user documentation, -specifications) included in this release: EAR99

- -

 

- -

 

- -

Manifest

- -

 

- -

See Legend above for a description of the columns and -possible values.

- -

 

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-

Software Name

- 		-

Version

- 		-

License Type

- 		-

Delivered

-

As

- 		-

Modified by

-

TI

- 		-

 

-
-

MSP430-BSL

- 		-

2.1

- 		-

BSD 3-Clause

- 		-

Source

- 		-

yes

- 		-

Location

- 		-

<installed path>/*

-
-

Obtained from

- 		-

TI

-
-

MSP430 USB Stack and Examples

- 		-

 

- 		-

BSD 3-Clause

- 		-

Source

- 		-

yes

- 		-

Location

- 		-

<installed path>/F5xx_F6xx_Core_Lib/*

-

<installed path>/usb/*

-

<installed path>/USB_API/*

-

<installed path>/USB_config/*

-
-

Obtained from

- 		-

TI

-
- -

 

- -

 

- -

Credits

- -

 

- -

 

- -

Licenses

- -

 

- -

 

- -

Copyright (C) 2014 Texas Instruments Incorporated - -http://www.ti.com/

- -

 

- -

 

- -

Redistribution and use in source and binary forms, with or -without modification, are permitted provided that the following conditions are -met:

- -

 

- -

·         -Redistributions of source code must retain the -above copyright notice, this list of conditions and the following disclaimer.

- -

 

- -

·         -Redistributions in binary form must reproduce -the above copyright notice, this list of conditions and the following -disclaimer in the documentation and/or other materials provided with the distribution.

- -

 

- -

·         -Neither the name of Texas Instruments Incorporated -nor the names of its contributors may be used to endorse or promote products -derived from this software without specific prior written permission.

- -

 

- -

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND -CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED ARRANTIES, INCLUDING, -BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, -OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING -IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE.

- -

 

- -
- - - - + + + + + + + + + + +ASP Software Manifest + + + + + + + + + + + + + +
+ +

 

+ +

+ + + + + + + + + + + + + + + + + + + +                                                                                                             +February 9, 2015

+ +

 

+ +

 

+ +

+ + +MSP430-BSL +Manifest

+ +

 

+ +

 

+ +

 

+ +

Legend (explanation of the fields in the +Manifest Table below)

+ +

 

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+

Software Name

+ 		+

The name of the application or file

+
+

Version

+ 		+

Version of the application or file

+
+

License Type

+ 		+

Type of license(s) under which TI will be providing software + to the licensee (e.g. BSD, GPLv2, TI TSPA License, TI Commercial License). + See Open Source Reference License Disclaimer in the Disclaimers Section.

+
+

Location

+ 		+

The directory name and path on the media (or in an + archive) where the Software is located.

+
+

Delivered As

+ 		+

This field will either be “Source”, “Binary” or + “Source and Binary” and is the form the content of the Software is delivered + in.  If the Software is delivered in an + archive format, this field applies to the contents of the archive. If the + word Limited is used with Source, as in “Limited Source” or “Limited Source + and Binary” then only portions of the Source for the application are + provided.

+
+

Modified by TI

+ 		+

This field will either be “Yes” or “No”. A “Yes” means + TI has made changes to the Software. A “No” means TI has not made any + changes. Note: This field is not applicable for Software “Obtained from” TI.

+
+

Obtained from

+ 		+

This field specifies from where or from whom TI + obtained the Software. It may be a URL to an Open Source site, a 3rd + party licensor, or TI (if TI developed the software). If this field contains + a link to Open Source software, the date TI downloaded the Software is also + recorded. See Links Disclaimer in the Disclaimers Section.

+
+ +

 

+ +

 

+ +

 

+ +

DISCLAIMERS

+ +

 

+ +

Export Control Classification Number (ECCN)

+ +

 

+ +

Any use of ECCNs +listed in the Manifest is at the user’s risk and without recourse to TI.   Your company, as the exporter of record, is +responsible for determining the correct classification of any item at the time +of export. Any export classification by TI of Software is for TI’s internal use +only and shall not be construed as a representation or warranty regarding the +proper export classification for such Software or whether an export license or +other documentation is required for exporting such Software.  +

+ +

 

+ +

Links in the Manifest

+ +

 

+ +

Any links appearing on this Manifest +(for example in the “Obtained from” field) were verified at the time the +Manifest was created. TI makes no guarantee that any listed links will remain +active in the future.

+ +

Open Source License +References

+ +

Your company is responsible for +confirming the applicable license terms for any open source Software listed in +this Manifest that was not “Obtained from” TI.  +Any open source license specified in this Manifest for Software that was +not “Obtained from” TI is for TI’s internal use only and shall not be construed +as a representation or warranty regarding the proper open source license terms +for such Software.

+ +
+ + +

 

+ +

Export Information

+ +

 

+ +

ECCN for Software included in this release: EAR99

+ +

 

+ +

ECCN for Technology (e.g., user documentation, +specifications) included in this release: EAR99

+ +

 

+ +

 

+ +

Manifest

+ +

 

+ +

See Legend above for a description of the columns and +possible values.

+ +

 

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+

Software Name

+ 		+

Version

+ 		+

License Type

+ 		+

Delivered

+

As

+ 		+

Modified by

+

TI

+ 		+

 

+
+

MSP-BSL

+ 		+

3.0

+ 		+

BSD 3-Clause

+ 		+

Source and Binary

+ 		+

yes

+ 		+

Location

+ 		+

<installed path>/*

+
+

Obtained from

+ 		+

TI

+
+

MSP430 USB Stack and Examples

+ 		+

4.10.02

+ 		+

BSD 3-Clause

+ 		+

Source

+ 		+

yes

+ 		+

Location

+ 		+

<installed path>/source/driverlib/*

+

<installed path>/source/USB_API/*

+

<installed path>/source/USB_app/*

+

<installed path>/source/USB_config/*

+
+

Obtained from

+ 		+

TI

+
+ +

 

+ +

 

+ +

Credits

+ +

 

+ +

 

+ +

Licenses

+ +

 

+ +

 

+ +

Copyright (C) 2014 Texas Instruments Incorporated - +http://www.ti.com/

+ +

 

+ +

 

+ +

Redistribution and use in source and binary forms, with or +without modification, are permitted provided that the following conditions are +met:

+ +

 

+ +

·         +Redistributions of source code must retain the +above copyright notice, this list of conditions and the following disclaimer.

+ +

 

+ +

·         +Redistributions in binary form must reproduce +the above copyright notice, this list of conditions and the following +disclaimer in the documentation and/or other materials provided with the distribution.

+ +

 

+ +

·         +Neither the name of Texas Instruments Incorporated +nor the names of its contributors may be used to endorse or promote products +derived from this software without specific prior written permission.

+ +

 

+ +

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED ARRANTIES, INCLUDING, +BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, +OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE.

+ +

 

+ +
+ + + + diff --git a/CDC_UART_Bridge_F5509.ewd b/source/MSP_BSL.ewd similarity index 93% rename from CDC_UART_Bridge_F5509.ewd rename to source/MSP_BSL.ewd index e1cb7df..ee8b2d3 100644 --- a/CDC_UART_Bridge_F5509.ewd +++ b/source/MSP_BSL.ewd @@ -1,779 +1,739 @@ - - - - 2 - - I2C_BASED - - MSP430 - - 1 - - C-SPY - 4 - - 26 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 430FET - 1 - - 25 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SIM430 - 1 - - 4 - 1 - 1 - - - - - - - - - - - $TOOLKIT_DIR$\plugins\Lcd\lcd.ewplugin - 1 - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin - 0 - - - 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rename from CDC_UART_Bridge_F5509.ewp rename to source/MSP_BSL.ewp index c683234..4ad80fb 100644 --- a/CDC_UART_Bridge_F5509.ewp +++ b/source/MSP_BSL.ewp @@ -1,2176 +1,2369 @@ - - - - 2 - - I2C_BASED - - MSP430 - - 1 - - General - 13 - - 30 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICC430 - 4 - - 36 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - A430 - 5 - - 14 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - XLINK - 4 - - 25 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - XAR - 4 - - 0 - 1 - 1 - - - - - - - ULP430 - 1 - - 1 - 1 - 1 - - - - - - - - - BILINK - 0 - - - - - RELEASE - - MSP430 - - 0 - - General - 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$PROJ_DIR$\USB_API\USB_HID_API\UsbHid.h + + + $PROJ_DIR$\USB_API\USB_HID_API\UsbHidReq.c + + + $PROJ_DIR$\USB_API\USB_HID_API\UsbHidReq.h + + + + USB_MSC_API + + USB_app + + $PROJ_DIR$\USB_app\usbConstructs.c + + + $PROJ_DIR$\USB_app\usbConstructs.h + + + $PROJ_DIR$\USB_app\usbEventHandling.c + + + + $PROJ_DIR$\USB_API\USB_MSC_API\UsbMsc.h + + + $PROJ_DIR$\USB_API\USB_MSC_API\UsbMscReq.c + + + $PROJ_DIR$\USB_API\USB_MSC_API\UsbMscReq.h + + + $PROJ_DIR$\USB_API\USB_MSC_API\UsbMscScsi.c + + + $PROJ_DIR$\USB_API\USB_MSC_API\UsbMscScsi.h + + + $PROJ_DIR$\USB_API\USB_MSC_API\UsbMscStateMachine.c + + + $PROJ_DIR$\USB_API\USB_MSC_API\UsbMscStateMachine.h + + + + USB_PHDC_API + + $PROJ_DIR$\USB_API\USB_PHDC_API\UsbPHDC.c + + + $PROJ_DIR$\USB_API\USB_PHDC_API\UsbPHDC.h + + + + + USB_config + + $PROJ_DIR$\USB_config\descriptors.c + + + $PROJ_DIR$\USB_Config\descriptors.h + + + $PROJ_DIR$\USB_config\UsbIsr.c + + + + $PROJ_DIR$\hal.c + + + $PROJ_DIR$\hal.h + + + $PROJ_DIR$\main.c + + + $PROJ_DIR$\peripherals.c + + + $PROJ_DIR$\peripherals.h + + + + diff --git a/CDC_UART_Bridge.eww b/source/MSP_BSL.eww similarity index 68% rename from CDC_UART_Bridge.eww rename to source/MSP_BSL.eww index 1c8de3e..f32963e 100644 --- a/CDC_UART_Bridge.eww +++ b/source/MSP_BSL.eww @@ -1,10 +1,10 @@ - - - - - $WS_DIR$\CDC_UART_Bridge_F5509.ewp - - - - - + + + + + $WS_DIR$\MSP_BSL.ewp + + + + + diff --git a/source/USB_API/USB_CDC_API/UsbCdc.c b/source/USB_API/USB_CDC_API/UsbCdc.c new file mode 100644 index 0000000..49687c2 --- /dev/null +++ b/source/USB_API/USB_CDC_API/UsbCdc.c @@ -0,0 +1,1101 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +/** @file UsbCdc.c + * @brief Contains APIs related to CDC (Virtual COMport) device class + */ + + +// +//! \cond +// + +/* + * ======== UsbCdc.c ======== + */ +#include + +#ifdef _CDC_ + + +#include "../USB_Common/device.h" +#include "../USB_Common/defMSP430USB.h" +#include "../USB_Common/usb.h" //USB-specific Data Structures +#include "../USB_CDC_API/UsbCdc.h" + +#include + +//Local Macros +#define INTFNUM_OFFSET(X) (X - CDC0_INTFNUM) //Get the CDC offset + +static struct _CdcControl { + uint32_t lBaudrate; + uint8_t bDataBits; + uint8_t bStopBits; + uint8_t bParity; +} CdcControl[CDC_NUM_INTERFACES]; + +static struct _CdcWrite { + uint16_t nCdcBytesToSend; //holds counter of bytes to be sent + uint16_t nCdcBytesToSendLeft; //holds counter how many bytes is still to be sent + const uint8_t* pUsbBufferToSend; //holds the buffer with data to be sent + uint8_t bCurrentBufferXY; //is 0 if current buffer to write data is X, or 1 if current buffer is Y + uint8_t bZeroPacketSent; //= FALSE; + uint8_t last_ByteSend; +} CdcWriteCtrl[CDC_NUM_INTERFACES]; + +static struct _CdcRead { + uint8_t *pUserBuffer; //holds the current position of user's receiving buffer. If NULL- no receiving + //operation started + uint8_t *pCurrentEpPos; //current positon to read of received data from curent EP + uint16_t nBytesToReceive; //holds how many bytes was requested by receiveData() to receive + uint16_t nBytesToReceiveLeft; //holds how many bytes is still requested by receiveData() to receive + uint8_t * pCT1; //holds current EPBCTxx register + uint8_t * pCT2; //holds next EPBCTxx register + uint8_t * pEP2; //holds addr of the next EP buffer + uint8_t nBytesInEp; //how many received bytes still available in current EP + uint8_t bCurrentBufferXY; //indicates which buffer is used by host to transmit data via OUT endpoint3 +} CdcReadCtrl[CDC_NUM_INTERFACES]; + +#ifdef BRIDGE_CDC_PRESENT + +static struct _CdcBridgeCtrl { + uint8_t *uartRx; + uint8_t *uartTx; + uint8_t *uartIFG; + uint16_t *usbToUartDmaChSz; + uint16_t *usbToUartDmaChCtl; + uint8_t ctsState; +} CdcBridgeCtrl; + +#endif + +extern uint16_t wUsbEventMask; + +//function pointers +extern void *(*USB_TX_memcpy)(void * dest, const void * source, size_t count); +extern void *(*USB_RX_memcpy)(void * dest, const void * source, size_t count); + + +/*----------------------------------------------------------------------------+ + | Global Variables | + +----------------------------------------------------------------------------*/ + +extern __no_init tEDB __data16 tInputEndPointDescriptorBlock[]; +extern __no_init tEDB __data16 tOutputEndPointDescriptorBlock[]; + + +void CdcResetData () +{ + int16_t i; + + //indicates which buffer is used by host to transmit data via OUT endpoint3 - X buffer is first + //CdcReadCtrl[intfIndex].bCurrentBufferXY = X_BUFFER; + + memset(&CdcWriteCtrl, 0, sizeof(CdcWriteCtrl)); + memset(&CdcReadCtrl, 0, sizeof(CdcReadCtrl)); + memset(&CdcControl, 0, sizeof(CdcControl)); + + for (i = 0; i < CDC_NUM_INTERFACES; i++){ + CdcControl[i].bDataBits = 8; + } +} + +// +//! \endcond +// + +//***************************************************************************** +// +//! Begins a Send Operation to the USB Host. +//! +//! \param *data is an array of data to be sent. +//! \param size is the number of bytes to be sent, starting from address +//! \b data. +//! \param intfNum selects which data should be transmitted over. +//! +//! Initiates sending of a user buffer over CDC interface \b intfNum, of size +//! \b size and starting at address \b data. If \b size is larger than the +//! packet size, the function handles all packetization and buffer management. +//! \b size has no inherent upper limit (beyond being a 16-bit value). +//! +//! In most cases where a send operation is successfully started, the function +//! will return \b kUSBCDC_sendStarted. A send operation is said to be underway. At +//! some point, either before or after the function returns, the send operation +//! will complete, barring any events that would preclude it. (Even if the +//! operation completes before the function returns, the return code will still +//! be \b kUSBCDC_sendStarted.) +//! If the bus is not connected when the function is called, the function +//! returns \b kUSBCDC_busNotAvailable, and no operation is begun. If \b size is 0, +//! the function returns \b kUSBCDC_generalError. If a previous send operation is +//! already underway for this data interface, the function returns with +//! \b kUSBCDC_intfBusyError. +//! +//! USB includes low-level mechanisms that ensure valid transmission of data. +//! +//! See Sec. 7.2 of \e "Programmer's Guide: MSP430 USB API Stack for CDC/PHDC/HID/MSC" for a detailed discussion of +//! send operations. +//! +//! \return Any of the following: +//! - \b kUSBCDC_sendStarted: a send operation was successfully +//! started +//! - \b kUSBCDC_intfBusyError: a previous send operation is +//! underway +//! - \b kUSBCDC_busNotAvailable: the bus is either suspended or +//! disconnected +//! - \b kUSBCDC_generalError: \b size was zero, or other error +// +//***************************************************************************** + +uint8_t USBCDC_sendData (const uint8_t* data, uint16_t size, uint8_t intfNum) +{ + uint8_t edbIndex; + uint16_t state; + + edbIndex = stUsbHandle[intfNum].edb_Index; + + if (size == 0){ + return (kUSBCDC_generalError); + } + + state = usbDisableInEndpointInterrupt(edbIndex); + + //do not access USB memory if suspended (PLL uce BUS_ERROR + if ((bFunctionSuspended) || + (bEnumerationStatus != ENUMERATION_COMPLETE)){ + //data can not be read because of USB suspended + usbRestoreInEndpointInterrupt(state); //restore interrupt status + return (kUSBCDC_busNotAvailable); + } + + if (CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].nCdcBytesToSendLeft != 0){ + //the USB still sends previous data, we have to wait + usbRestoreInEndpointInterrupt(state); //restore interrupt status + return (kUSBCDC_intfBusyError); + } + + //This function generate the USB interrupt. The data will be sent out from interrupt + + CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].nCdcBytesToSend = size; + CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].nCdcBytesToSendLeft = size; + CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].pUsbBufferToSend = data; + + //trigger Endpoint Interrupt - to start send operation + USBIEPIFG |= 1 << (edbIndex + 1); //IEPIFGx; + + usbRestoreInEndpointInterrupt(state); + + return (kUSBCDC_sendStarted); +} + +// +//! \cond +// + +#define EP_MAX_PACKET_SIZE_CDC 0x40 + +//this function is used only by USB interrupt +int16_t CdcToHostFromBuffer (uint8_t intfNum) +{ + uint8_t byte_count, nTmp2; + uint8_t * pEP1; + uint8_t * pEP2; + uint8_t * pCT1; + uint8_t * pCT2; + uint8_t bWakeUp = FALSE; //TRUE for wake up after interrupt + uint8_t edbIndex; + + edbIndex = stUsbHandle[intfNum].edb_Index; + + if (CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].nCdcBytesToSendLeft == 0){ //do we have somtething to send? + if (!CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].bZeroPacketSent){ //zero packet was not yet sent + CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].bZeroPacketSent = TRUE; + + if (CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].last_ByteSend == + EP_MAX_PACKET_SIZE_CDC){ + if (CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY == + X_BUFFER){ + if (tInputEndPointDescriptorBlock[edbIndex].bEPBCTX & + EPBCNT_NAK){ + tInputEndPointDescriptorBlock[edbIndex].bEPBCTX = 0; + CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY + = Y_BUFFER; //switch buffer + } + } else { + if (tInputEndPointDescriptorBlock[edbIndex].bEPBCTY & + EPBCNT_NAK){ + tInputEndPointDescriptorBlock[edbIndex].bEPBCTY = 0; + CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY + = X_BUFFER; //switch buffer + } + } + } + + CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].nCdcBytesToSend = 0; //nothing to send + + //call event callback function + if (wUsbEventMask & kUSB_sendCompletedEvent){ + bWakeUp = USBCDC_handleSendCompleted(intfNum); + } + } //if (!bSentZeroPacket) + + return (bWakeUp); + } + + CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].bZeroPacketSent = FALSE; //zero packet will be not sent: we have data + + if (CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY == X_BUFFER){ + //this is the active EP buffer + pEP1 = (uint8_t*)stUsbHandle[intfNum].iep_X_Buffer; + pCT1 = &tInputEndPointDescriptorBlock[edbIndex].bEPBCTX; + + //second EP buffer + pEP2 = (uint8_t*)stUsbHandle[intfNum].iep_Y_Buffer; + pCT2 = &tInputEndPointDescriptorBlock[edbIndex].bEPBCTY; + } else { + //this is the active EP buffer + pEP1 = (uint8_t*)stUsbHandle[intfNum].iep_Y_Buffer; + pCT1 = &tInputEndPointDescriptorBlock[edbIndex].bEPBCTY; + + //second EP buffer + pEP2 = (uint8_t*)stUsbHandle[intfNum].iep_X_Buffer; + pCT2 = &tInputEndPointDescriptorBlock[edbIndex].bEPBCTX; + } + + //how many byte we can send over one endpoint buffer + byte_count = + (CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].nCdcBytesToSendLeft > + EP_MAX_PACKET_SIZE_CDC) ? EP_MAX_PACKET_SIZE_CDC : CdcWriteCtrl[ + INTFNUM_OFFSET(intfNum)].nCdcBytesToSendLeft; + nTmp2 = *pCT1; + + if (nTmp2 & EPBCNT_NAK){ + USB_TX_memcpy(pEP1, CdcWriteCtrl[INTFNUM_OFFSET( + intfNum)].pUsbBufferToSend, + byte_count); //copy data into IEP3 X or Y buffer + *pCT1 = byte_count; //Set counter for usb In-Transaction + CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY = + (CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY + 1) & 0x01; //switch buffer + CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].nCdcBytesToSendLeft -= byte_count; + CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].pUsbBufferToSend += byte_count; //move buffer pointer + CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].last_ByteSend = byte_count; + + //try to send data over second buffer + nTmp2 = *pCT2; + if ((CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].nCdcBytesToSendLeft > 0) && //do we have more data to send? + (nTmp2 & EPBCNT_NAK)){ //if the second buffer is free? + //how many byte we can send over one endpoint buffer + byte_count = + (CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].nCdcBytesToSendLeft > + EP_MAX_PACKET_SIZE_CDC) ? EP_MAX_PACKET_SIZE_CDC : + CdcWriteCtrl[ + INTFNUM_OFFSET(intfNum)].nCdcBytesToSendLeft; + + USB_TX_memcpy(pEP2, CdcWriteCtrl[INTFNUM_OFFSET( + intfNum)].pUsbBufferToSend, + byte_count); //copy data into IEP3 X or Y buffer + *pCT2 = byte_count; //Set counter for usb In-Transaction + CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY = + (CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY + + 1) & 0x01; //switch buffer + CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].nCdcBytesToSendLeft -= + byte_count; + CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].pUsbBufferToSend += + byte_count; //move buffer pointer + CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].last_ByteSend = byte_count; + } + } + return (bWakeUp); +} + +// +//! \endcond +// + +//***************************************************************************** +// +//! Aborts an Active Send Operation. +//! +//! \param size is the number of bytes that were sent prior to the abort action. +//! \param intfNum is the data interface for which the send should be aborted. +//! +//! Aborts an active send operation on data interface \b intfNum. Returns the +//! number of bytes that were sent prior to the abort, in \b size. +//! +//! An application may choose to call this function if sending failed, due to +//! factors such as: +//! - a surprise removal of the bus +//! - a USB suspend event +//! - any send operation that extends longer than desired (perhaps due +//! to no open COM port on the host.) +//! +//! \return \b kUSB_succeed +// +//***************************************************************************** + +uint8_t USBCDC_abortSend (uint16_t* size, uint8_t intfNum) +{ + uint8_t edbIndex; + uint16_t state; + + edbIndex = stUsbHandle[intfNum].edb_Index; + + state = usbDisableInEndpointInterrupt(edbIndex); //disable interrupts - atomic operation + + *size = + (CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].nCdcBytesToSend - + CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].nCdcBytesToSendLeft); + CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].nCdcBytesToSend = 0; + CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].nCdcBytesToSendLeft = 0; + + usbRestoreInEndpointInterrupt(state); + return (kUSB_succeed); +} + +// +//! \cond +// + +//This function copies data from OUT endpoint into user's buffer +//Arguments: +//pEP - pointer to EP to copy from +//pCT - pointer to pCT control reg +// +void CopyUsbToBuff (uint8_t* pEP, uint8_t* pCT, uint8_t intfNum) +{ + uint8_t nCount; + + //how many byte we can get from one endpoint buffer + nCount = + (CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft > + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp) ? CdcReadCtrl[ + INTFNUM_OFFSET(intfNum)].nBytesInEp : CdcReadCtrl[INTFNUM_OFFSET( + intfNum)]. + nBytesToReceiveLeft; + + USB_RX_memcpy(CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer, pEP, nCount); //copy data from OEP3 X or Y buffer + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft -= nCount; + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer += nCount; //move buffer pointer + //to read rest of data next time from this place + + if (nCount == CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp){ //all bytes are copied from receive buffer? + //switch current buffer + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY = + (CdcReadCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY + 1) & 0x01; + + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = 0; + + //clear NAK, EP ready to receive data + *pCT = 0x00; + } else { + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp -= nCount; + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCurrentEpPos = pEP + nCount; + } +} + +// +//! \endcond +// + +//***************************************************************************** +// +//! Begins a Receive Operation from the USB Host. +//! +//! \param *data is an array to contain the data received. +//! \param size is the number of bytes to be received. +//! \param intfNum is which data interface to receive from. +//! +//! Receives \b size bytes over CDC interface \b intfNum into memory starting at +//! address \b data. \b size has no inherent upper limit (beyond being a 16-bit +//! value). +//! +//! The function may return with \b kUSBCDC_receiveStarted, indicating that a +//! receive operation is underway. The operation completes when \b size bytes +//! are received. The application should ensure that the data memory buffer be +//! available during the whole of the receive operation. +//! +//! The function may also return with \b kUSBCDC_receiveCompleted. This means that +//! the receive operation was complete by the time the function returned. +//! +//! If the bus is not connected when the function is called, the function +//! returns \b kUSBCDC_busNotAvailable, and no operation is begun. If \b size is 0, +//! the function returns \b kUSBCDC_generalError. If a previous receive operation +//! is already underway for this data interface, the function returns +//! \b kUSBCDC_intfBusyError. +//! +//! USB includes low-level mechanisms that ensure valid transmission of data. +//! +//! See Sec. 7.2 of \e "Programmer's Guide: MSP430 USB API Stack for CDC/PHDC/HID/MSC" for a detailed discussion of +//! receive operations. +//! +//! \return Any of the following: +//! - \b kUSBCDC_receiveStarted: A receive operation has been +//! succesfully started. +//! - \b kUSBCDC_receiveCompleted: The receive operation is already +//! completed. +//! - \b kUSBCDC_intfBusyError: a previous receive operation is +//! underway. +//! - \b kUSBCDC_busNotAvailable: the bus is either suspended or +//! disconnected. +//! - \b kUSBCDC_generalError: \b size was zero, or other error. +// +//***************************************************************************** + +uint8_t USBCDC_receiveData (uint8_t* data, uint16_t size, uint8_t intfNum) +{ + uint8_t nTmp1; + uint8_t edbIndex; + uint16_t state; + + edbIndex = stUsbHandle[intfNum].edb_Index; + + if ((size == 0) || //read size is 0 + (data == NULL)){ + return (kUSBCDC_generalError); + } + + state = usbDisableOutEndpointInterrupt(edbIndex); + //atomic operation - disable interrupts + + //do not access USB memory if suspended (PLL off). It may produce BUS_ERROR + if ((bFunctionSuspended) || + (bEnumerationStatus != ENUMERATION_COMPLETE)){ + //data can not be read because of USB suspended + usbRestoreOutEndpointInterrupt(state); + return (kUSBCDC_busNotAvailable); + } + + if (CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer != NULL){ //receive process already started + usbRestoreOutEndpointInterrupt(state); + return (kUSBCDC_intfBusyError); + } + + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceive = size; //bytes to receive + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft = size; //left bytes to receive + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer = data; //set user receive buffer + + //read rest of data from buffer, if any + if (CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp > 0){ + //copy data from pEP-endpoint into User's buffer + CopyUsbToBuff(CdcReadCtrl[INTFNUM_OFFSET( + intfNum)].pCurrentEpPos, + CdcReadCtrl[INTFNUM_OFFSET( + intfNum) + ].pCT1, intfNum); + + if (CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft == 0){ //the Receive opereation is completed + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer = NULL; //no more receiving pending + if (wUsbEventMask & kUSB_receiveCompletedEvent){ + USBCDC_handleReceiveCompleted(intfNum); //call event handler in interrupt context + } + usbRestoreOutEndpointInterrupt(state); + return (kUSBCDC_receiveCompleted); //receive completed + } + + //check other EP buffer for data - exchange pCT1 with pCT2 + if (CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 == + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX){ + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 = + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY; + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCurrentEpPos = + (uint8_t*)stUsbHandle[intfNum].oep_Y_Buffer; + } else { + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 = + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX; + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCurrentEpPos = + (uint8_t*)stUsbHandle[intfNum].oep_X_Buffer; + } + + nTmp1 = *CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1; + //try read data from second buffer + if (nTmp1 & EPBCNT_NAK){ //if the second buffer has received data? + nTmp1 = nTmp1 & 0x7f; //clear NAK bit + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = nTmp1; //holds how many valid bytes in the EP buffer + CopyUsbToBuff(CdcReadCtrl[INTFNUM_OFFSET( + intfNum)].pCurrentEpPos, + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1, intfNum); + } + + if (CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft == 0){ //the Receive opereation is completed + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer = NULL; //no more receiving pending + if (wUsbEventMask & kUSB_receiveCompletedEvent){ + USBCDC_handleReceiveCompleted(intfNum); //call event handler in interrupt context + } + usbRestoreOutEndpointInterrupt(state); + return (kUSBCDC_receiveCompleted); //receive completed + } + } //read rest of data from buffer, if any + + //read 'fresh' data, if available + nTmp1 = 0; + if (CdcReadCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY == X_BUFFER){ //this is current buffer + if (tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX & EPBCNT_NAK){ //this buffer has a valid data packet + //this is the active EP buffer + //pEP1 + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCurrentEpPos = + (uint8_t*)stUsbHandle[intfNum].oep_X_Buffer; + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 = + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX; + + //second EP buffer + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pEP2 = + (uint8_t*)stUsbHandle[intfNum].oep_Y_Buffer; + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2 = + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY; + nTmp1 = 1; //indicate that data is available + } + } else { //Y_BUFFER + if (tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY & EPBCNT_NAK){ + //this is the active EP buffer + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCurrentEpPos = + (uint8_t*)stUsbHandle[intfNum].oep_Y_Buffer; + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 = + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY; + + //second EP buffer + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pEP2 = + (uint8_t*)stUsbHandle[intfNum].oep_X_Buffer; + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2 = + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX; + nTmp1 = 1; //indicate that data is available + } + } + + if (nTmp1){ + //how many byte we can get from one endpoint buffer + nTmp1 = *CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1; + while (nTmp1 == 0) + { + nTmp1 = *CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1; + } + + if (nTmp1 & EPBCNT_NAK){ + nTmp1 = nTmp1 & 0x7f; //clear NAK bit + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = nTmp1; //holds how many valid bytes in the EP buffer + + CopyUsbToBuff(CdcReadCtrl[INTFNUM_OFFSET( + intfNum)].pCurrentEpPos, + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1, intfNum); + + nTmp1 = *CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2; + //try read data from second buffer + if ((CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft > + 0) && //do we have more data to send? + (nTmp1 & EPBCNT_NAK)){ //if the second buffer has received data? + nTmp1 = nTmp1 & 0x7f; //clear NAK bit + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = nTmp1; //holds how many valid bytes in the EP buffer + CopyUsbToBuff(CdcReadCtrl[INTFNUM_OFFSET( + intfNum)].pEP2, + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2, intfNum); + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 = + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2; + } + } + } + + if (CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft == 0){ //the Receive opereation is completed + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer = NULL; //no more receiving pending + if (wUsbEventMask & kUSB_receiveCompletedEvent){ + USBCDC_handleReceiveCompleted(intfNum); //call event handler in interrupt context + } + usbRestoreOutEndpointInterrupt(state); + return (kUSBCDC_receiveCompleted); + } + + //interrupts enable + usbRestoreOutEndpointInterrupt(state); + return (kUSBCDC_receiveStarted); +} + +// +//! \cond +// + +//this function is used only by USB interrupt. +//It fills user receiving buffer with received data +int16_t CdcToBufferFromHost (uint8_t intfNum) +{ + uint8_t * pEP1; + uint8_t nTmp1; + uint8_t bWakeUp = FALSE; //per default we do not wake up after interrupt + + uint8_t edbIndex; + + edbIndex = stUsbHandle[intfNum].edb_Index; + + if (CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft == 0){ //do we have somtething to receive? + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer = NULL; //no more receiving pending + return (bWakeUp); + } + + //No data to receive... + if (!((tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX | + tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY) + & 0x80)){ + return (bWakeUp); + } + + if (CdcReadCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY == X_BUFFER){ //X is current buffer + //this is the active EP buffer + pEP1 = (uint8_t*)stUsbHandle[intfNum].oep_X_Buffer; + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 = + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX; + + //second EP buffer + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pEP2 = + (uint8_t*)stUsbHandle[intfNum].oep_Y_Buffer; + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2 = + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY; + } else { + //this is the active EP buffer + pEP1 = (uint8_t*)stUsbHandle[intfNum].oep_Y_Buffer; + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 = + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY; + + //second EP buffer + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pEP2 = + (uint8_t*)stUsbHandle[intfNum].oep_X_Buffer; + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2 = + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX; + } + + //how many byte we can get from one endpoint buffer + nTmp1 = *CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1; + + if (nTmp1 & EPBCNT_NAK){ + nTmp1 = nTmp1 & 0x7f; //clear NAK bit + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = nTmp1; //holds how many valid bytes in the EP buffer + + CopyUsbToBuff(pEP1, CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1, intfNum); + + nTmp1 = *CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2; + //try read data from second buffer + if ((CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft > 0) && //do we have more data to send? + (nTmp1 & EPBCNT_NAK)){ //if the second buffer has received data? + nTmp1 = nTmp1 & 0x7f; //clear NAK bit + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = nTmp1; //holds how many valid bytes in the EP buffer + CopyUsbToBuff(CdcReadCtrl[INTFNUM_OFFSET( + intfNum)].pEP2, + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2, intfNum); + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 = + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2; + } + } + + if (CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft == 0){ //the Receive opereation is completed + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer = NULL; //no more receiving pending + if (wUsbEventMask & kUSB_receiveCompletedEvent){ + bWakeUp |= USBCDC_handleReceiveCompleted(intfNum); + } + + if (CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp){ //Is not read data still available in the EP? + if (wUsbEventMask & kUSB_dataReceivedEvent){ + bWakeUp |= USBCDC_handleDataReceived(intfNum); + } + } + } + return (bWakeUp); +} + +//helper for USB interrupt handler +int16_t CdcIsReceiveInProgress (uint8_t intfNum) +{ + return (CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer != NULL); +} + +// +//! \endcond +// + +//***************************************************************************** +// +//! Aborts an Active Receive Operation. +//! +//! \param *size is the number of bytes that were received and are waiting +//! at the assigned address. +//! \param intfNum is the data interface for which the send should be +//! aborted. +//! +//! Aborts an active receive operation on CDC interface \b intfNum. Returns the +//! number of bytes that were received and transferred to the data location +//! established for this receive operation. The data moved to the buffer up to +//! that time remains valid. +//! +//! An application may choose to call this function if it decides it no longer +//! wants to receive data from the USB host. It should be noted that if a +//! continuous stream of data is being received from the host, aborting the +//! operation is akin to pressing a "pause" button; the host will be NAK'ed +//! until another receive operation is opened. +//! +//! See Sec. 7.2 of \e "Programmer's Guide: MSP430 USB API Stack for CDC/PHDC/HID/MSC" for a detailed discussion of +//! receive operations. +//! +//! \return \b kUSB_succeed +// +//***************************************************************************** + +uint8_t USBCDC_abortReceive (uint16_t* size, uint8_t intfNum) +{ + //interrupts disable + uint8_t edbIndex; + uint16_t state; + + edbIndex = stUsbHandle[intfNum].edb_Index; + state = usbDisableOutEndpointInterrupt(edbIndex); + + *size = 0; //set received bytes count to 0 + + //is receive operation underway? + if (CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer){ + //how many bytes are already received? + *size = CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceive - + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft; + + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = 0; + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer = NULL; + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft = 0; + } + + //restore interrupt status + usbRestoreOutEndpointInterrupt(state); + return (kUSB_succeed); +} + +//***************************************************************************** +// +//! Rejects the Data Received from the Host. +//! +//! This function rejects data that has been received from the host, for +//! interface inftNum, that does not have an active receive operation underway. +//! It resides in the USB endpoint buffer and blocks further data until a +//! receive operation is opened, or until rejected. When this function is +//! called, the buffer for this interface is purged, and the data lost. This +//! frees the USB path to resume communication. +//! +//! See Sec. 7.2 of \e "Programmer's Guide: MSP430 USB API Stack for CDC/PHDC/HID/MSC" for a detailed discussion of +//! receive operations. +//! +//! \return \b kUSB_succeed +// +//***************************************************************************** + +uint8_t USBCDC_rejectData (uint8_t intfNum) +{ + uint8_t edbIndex; + uint16_t state; + + edbIndex = stUsbHandle[intfNum].edb_Index; + state = usbDisableOutEndpointInterrupt(edbIndex); + + //atomic operation - disable interrupts + + //do not access USB memory if suspended (PLL off). It may produce BUS_ERROR + if (bFunctionSuspended){ + usbRestoreOutEndpointInterrupt(state); + return (kUSBCDC_busNotAvailable); + } + + //Is receive operation underway? + //- do not flush buffers if any operation still active. + if (!CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer){ + uint8_t tmp1 = tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX & + EPBCNT_NAK; + uint8_t tmp2 = tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY & + EPBCNT_NAK; + + if (tmp1 ^ tmp2){ //switch current buffer if any and only ONE of buffers + //is full + //switch current buffer + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY = + (CdcReadCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY + + 1) & 0x01; + } + + tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX = 0; //flush buffer X + tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY = 0; //flush buffer Y + CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = 0; //indicates that no more data available in the EP + } + + usbRestoreOutEndpointInterrupt(state); + return (kUSB_succeed); +} + +//***************************************************************************** +// +//! Indicates the Status of the CDC Interface. +//! +//! \param intfNum is the interface number for which status is being retrieved. +//! \param bytesSent If a send operation is underway, the number of bytes that +//! send have been transferred to the host is returned in this location. If +//! no operation is underway, this returns zero. +//! \param bytesReceived If a receive operation is underway, the number of bytes +//! that have been transferred to the assigned memory location is returned +//! in this location. If no receive operation is underway, this returns +//! zero. +//! +//! Indicates the status of the CDC interface \b intfNum. If a send operation is +//! active for this interface, the function also returns the number of bytes +//! that have been transmitted to the host. If a receive operation is active for +//! this interface, the function also returns the number of bytes that have been +//! received from the host and are waiting at the assigned address. +//! +//! Because multiple flags can be returned, the possible values can be masked +//! together - for example, \b kUSBCDC_waitingForSend + \b kUSBCDC_dataWaiting. +//! +//! \return Any combination of the following: +//! - \b kUSBCDC_waitingForSend: Indicates that a send operation is +//! open ont his interface +//! - \b kUSBCDC_waitingForReceive: Indicates that a receive operation +//! is open on this interface +//! - \b kUSBCDC_dataWaiting: Indicates that data has been received +//! from the host for this interface, waiting in the USB receive +//! buffers, lacking an open receive operation to accept it. +//! - \b kUSBCDC_busNotAvailable: Indicates that the bus is either +//! suspended or disconnected. Any operations that had previously +//! been underway are now aborted. +// +//***************************************************************************** + +uint8_t USBCDC_intfStatus (uint8_t intfNum, uint16_t* bytesSent, uint16_t* bytesReceived) +{ + uint8_t ret = 0; + uint16_t stateIn, stateOut; + uint8_t edbIndex; + + *bytesSent = 0; + *bytesReceived = 0; + + edbIndex = stUsbHandle[intfNum].edb_Index; + + stateIn = usbDisableInEndpointInterrupt(edbIndex); + stateOut = usbDisableOutEndpointInterrupt(edbIndex); + + //Is send operation underway? + if (CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].nCdcBytesToSendLeft != 0){ + ret |= kUSBCDC_waitingForSend; + *bytesSent = CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].nCdcBytesToSend - + CdcWriteCtrl[INTFNUM_OFFSET(intfNum)].nCdcBytesToSendLeft; + } + + //Is receive operation underway? + if (CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer != NULL){ + ret |= kUSBCDC_waitingForReceive; + *bytesReceived = CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceive - + CdcReadCtrl[INTFNUM_OFFSET(intfNum)]. + nBytesToReceiveLeft; + } else { //receive operation not started + //do not access USB memory if suspended (PLL off). + //It may produce BUS_ERROR + if (!bFunctionSuspended){ + if ((tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX & + EPBCNT_NAK) | //any of buffers has a valid data packet + (tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY & + EPBCNT_NAK)){ + ret |= kUSBCDC_dataWaiting; + } + } + } + + if ((bFunctionSuspended) || + (bEnumerationStatus != ENUMERATION_COMPLETE)){ + //if suspended or not enumerated - report no other tasks pending + ret = kUSBCDC_busNotAvailable; + } + + //restore interrupt status + usbRestoreInEndpointInterrupt(stateIn); + usbRestoreOutEndpointInterrupt(stateOut); + + __no_operation(); + return (ret); +} + +//***************************************************************************** +// +//! Gives the Number of Bytes in the USB Endpoint Buffer. +//! +//! \param intfNum is the data interface whose buffer is to be checked. +//! +//! Returns the number of bytes waiting in the USB endpoint buffer for +//! \b intfNum. A non-zero value generally means that no receive operation is +//! open by which these bytes can be copied to a user buffer. If the value is +//! non-zero, the application should either open a receive operation so that the +//! data can be moved out of the endpoint buffer, or the data should be rejected +//! (USBCDC_rejectData()). +//! +//! \return The number of bytes waiting in this buffer. +// +//***************************************************************************** + +uint8_t USBCDC_bytesInUSBBuffer (uint8_t intfNum) +{ + uint8_t bTmp1 = 0; + uint16_t state; + uint8_t edbIndex; + + edbIndex = stUsbHandle[intfNum].edb_Index; + + state = usbDisableOutEndpointInterrupt(edbIndex); + //atomic operation - disable interrupts + + if ((bFunctionSuspended) || + (bEnumerationStatus != ENUMERATION_COMPLETE)){ + usbRestoreOutEndpointInterrupt(state); + //if suspended or not enumerated - report 0 bytes available + return (0); + } + + if (CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp > 0){ //If a RX operation is underway, part of data may + //was read of the OEP buffer + bTmp1 = CdcReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp; + if (*CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2 & EPBCNT_NAK){ //the next buffer has a valid data packet + bTmp1 += *CdcReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2 & 0x7F; + } + } else { + if (tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX & EPBCNT_NAK){ //this buffer has a valid data packet + bTmp1 = tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX & 0x7F; + } + if (tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY & EPBCNT_NAK){ //this buffer has a valid data packet + bTmp1 += tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY & 0x7F; + } + } + + usbRestoreOutEndpointInterrupt(state); + return (bTmp1); +} + +// +//! \cond +// + +//---------------------------------------------------------------------------- +//Line Coding Structure +//dwDTERate | 4 | Data terminal rate, in bits per second +//bCharFormat | 1 | Stop bits, 0 = 1 Stop bit, 1 = 1,5 Stop bits, 2 = 2 Stop bits +//bParityType | 1 | Parity, 0 = None, 1 = Odd, 2 = Even, 3= Mark, 4 = Space +//bDataBits | 1 | Data bits (5,6,7,8,16) +//---------------------------------------------------------------------------- +uint8_t usbGetLineCoding (void) +{ + uint8_t infIndex; + + if(tSetupPacket.wIndex % 2) + { + infIndex = (tSetupPacket.wIndex-1) / 2; + } + else + { + infIndex = (tSetupPacket.wIndex) / 2; + } + + abUsbRequestReturnData[6] = + CdcControl[infIndex].bDataBits; //Data bits = 8 + abUsbRequestReturnData[5] = + CdcControl[infIndex].bParity; //No Parity + abUsbRequestReturnData[4] = + CdcControl[infIndex].bStopBits; //Stop bits = 1 + + abUsbRequestReturnData[3] = + CdcControl[infIndex].lBaudrate >> 24; + abUsbRequestReturnData[2] = + CdcControl[infIndex].lBaudrate >> 16; + abUsbRequestReturnData[1] = + CdcControl[infIndex].lBaudrate >> 8; + abUsbRequestReturnData[0] = + CdcControl[infIndex].lBaudrate; + + wBytesRemainingOnIEP0 = 0x07; //amount of data to be send over EP0 to host + usbSendDataPacketOnEP0((uint8_t*)&abUsbRequestReturnData[0]); //send data to host + + return (FALSE); +} + +//---------------------------------------------------------------------------- + +uint8_t usbSetLineCoding (void) +{ + usbReceiveDataPacketOnEP0((uint8_t*)&abUsbRequestIncomingData); //receive data over EP0 from Host + + return (FALSE); +} + +//---------------------------------------------------------------------------- + +uint8_t usbSetControlLineState (void) +{ + USBCDC_handleSetControlLineState((uint8_t)tSetupPacket.wIndex, + (uint8_t)tSetupPacket.wValue); + usbSendZeroLengthPacketOnIEP0(); //Send ZLP for status stage + + return (FALSE); +} + +//---------------------------------------------------------------------------- + +uint8_t Handler_SetLineCoding (void) +{ + uint8_t bWakeUp; + volatile uint8_t infIndex; + + if(tSetupPacket.wIndex % 2) + { + infIndex = (tSetupPacket.wIndex-1) / 2; + } + else + { + infIndex = (tSetupPacket.wIndex) / 2; + } + + //Baudrate Settings + + CdcControl[infIndex].lBaudrate = + (uint32_t)abUsbRequestIncomingData[3] << 24 | + (uint32_t)abUsbRequestIncomingData[2] << 16 | + (uint32_t) + abUsbRequestIncomingData[1] << 8 | abUsbRequestIncomingData[0]; + bWakeUp = + USBCDC_handleSetLineCoding(tSetupPacket.wIndex, + CdcControl[infIndex].lBaudrate); + + return (bWakeUp); +} + +#endif //ifdef _CDC_ + +// +//! \endcond +// + +/*----------------------------------------------------------------------------+ + | End of source file | + +----------------------------------------------------------------------------*/ +/*------------------------ Nothing Below This Line --------------------------*/ +//Released_Version_4_10_02 diff --git a/source/USB_API/USB_CDC_API/UsbCdc.h b/source/USB_API/USB_CDC_API/UsbCdc.h new file mode 100644 index 0000000..a49f52a --- /dev/null +++ b/source/USB_API/USB_CDC_API/UsbCdc.h @@ -0,0 +1,221 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +/* + * ======== UsbCdc.h ======== + */ + +#ifndef _UsbCdc_H_ +#define _UsbCdc_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +#define kUSBCDC_sendStarted 0x01 +#define kUSBCDC_sendComplete 0x02 +#define kUSBCDC_intfBusyError 0x03 +#define kUSBCDC_receiveStarted 0x04 +#define kUSBCDC_receiveCompleted 0x05 +#define kUSBCDC_receiveInProgress 0x06 +#define kUSBCDC_generalError 0x07 +#define kUSBCDC_busNotAvailable 0x08 + + +/*---------------------------------------------------------------------------- + * These functions can be used in application + +----------------------------------------------------------------------------*/ + +/* + * Sends data over interface intfNum, of size size and starting at address data. + * Returns: kUSBCDC_sendStarted + * kUSBCDC_sendComplete + * kUSBCDC_intfBusyError + */ +uint8_t USBCDC_sendData (const uint8_t* data, uint16_t size, uint8_t intfNum); + +/* + * Receives data over interface intfNum, of size size, into memory starting at address data. + */ +uint8_t USBCDC_receiveData (uint8_t* data, uint16_t size, uint8_t intfNum); + +/* + * Aborts an active receive operation on interface intfNum. + * size: the number of bytes that were received and transferred + * to the data location established for this receive operation. + */ +uint8_t USBCDC_abortReceive (uint16_t* size, uint8_t intfNum); + + +#define kUSBCDC_noDataWaiting 1 //returned by USBCDC_rejectData() if no data pending + +/* + * This function rejects payload data that has been received from the host. + */ +uint8_t USBCDC_rejectData (uint8_t intfNum); + +/* + * Aborts an active send operation on interface intfNum. Returns the number of bytes that were sent prior to the abort, in size. + */ +uint8_t USBCDC_abortSend (uint16_t* size, uint8_t intfNum); + + +#define kUSBCDC_waitingForSend 0x01 +#define kUSBCDC_waitingForReceive 0x02 +#define kUSBCDC_dataWaiting 0x04 +#define kUSBCDC_busNotAvailable 0x08 +#define kUSB_allCdcEvents 0xFF + +/* + * This function indicates the status of the interface intfNum. + * If a send operation is active for this interface, + * the function also returns the number of bytes that have been transmitted to the host. + * If a receiver operation is active for this interface, the function also returns + * the number of bytes that have been received from the host and are waiting at the assigned address. + * + * returns kUSBCDC_waitingForSend (indicates that a call to USBCDC_SendData() + * has been made, for which data transfer has not been completed) + * + * returns kUSBCDC_waitingForReceive (indicates that a receive operation + * has been initiated, but not all data has yet been received) + * + * returns kUSBCDC_dataWaiting (indicates that data has been received + * from the host, waiting in the USB receive buffers) + */ +uint8_t USBCDC_intfStatus (uint8_t intfNum, uint16_t* bytesSent, uint16_t* bytesReceived); + +/* + * Returns how many bytes are in the buffer are received and ready to be read. + */ +uint8_t USBCDC_bytesInUSBBuffer (uint8_t intfNum); + +/*---------------------------------------------------------------------------- + * Event-Handling routines + +----------------------------------------------------------------------------*/ + +/* + * This event indicates that data has been received for interface intfNum, but no data receive operation is underway. + * returns TRUE to keep CPU awake + */ +uint8_t USBCDC_handleDataReceived (uint8_t intfNum); + +/* + * This event indicates that a send operation on interface intfNum has just been completed. + * returns TRUE to keep CPU awake + */ +uint8_t USBCDC_handleSendCompleted (uint8_t intfNum); + +/* + * This event indicates that a receive operation on interface intfNum has just been completed. + * returns TRUE to keep CPU awake + */ +uint8_t USBCDC_handleReceiveCompleted (uint8_t intfNum); + +/* + * Toggle state variable for CTS in USB Stack + */ +void USBCDC_setCTS(uint8_t state); + +/* + * This event indicates that a SetLineCoding request was received from the host and new values + * for line coding paramters are available. + * + */ +uint8_t USBCDC_handleSetLineCoding (uint8_t intfNum, uint32_t lBaudrate); + +/* + * This event indicates that a SetControlLineState request was received from the host. + * Basically new RTS and DTR states have been sent. Bit 0 of lineState is DTR and Bit 1 is RTS. + * + */ +uint8_t USBCDC_handleSetControlLineState (uint8_t intfNum, uint8_t lineState); + +/*---------------------------------------------------------------------------- + * These functions is to be used ONLY by USB stack, and not by application + +----------------------------------------------------------------------------*/ + +/** + * Send a packet with the settings of the second uart back to the usb host + */ +uint8_t usbGetLineCoding(void); + +/** + * Prepare EP0 to receive a packet with the settings for the second uart + */ +uint8_t usbSetLineCoding(void); + +/** + * Function set or reset RTS + */ +uint8_t usbSetControlLineState(void); + +/** + * Readout the settings (send from usb host) for the second uart + */ +uint8_t Handler_SetLineCoding(void); + +/** + * sets up dma for CDC interface used as usb to uart bridge + */ +uint8_t USBCDC_setupDMA_Bridge(); +/** + * sends data alread present in endpoint buffer + */ +uint8_t USBCDC_Bridge_sendData (uint16_t size, uint8_t intfNum); +/** + * gets address of input endpoint X + */ +uint8_t *USBCDC_Bridge_getInEndpointBufferXAddr(uint8_t intfNum); +/** + * gets address of input endpoint Y + */ +uint8_t *USBCDC_Bridge_getInEndpointBufferYAddr(uint8_t intfNum); +/** + * gets address of output endpoint X + */ +uint8_t *USBCDC_Bridge_getOutEndpointBufferXAddr(uint8_t intfNum); +/** + * gets address of output endpoint Y + */ +uint8_t *USBCDC_Bridge_getOutEndpointBufferYAddr(uint8_t intfNum); +/** + * completes receive operation once data from endpoint has been transmitted thru uart + */ +uint8_t USBCDC_Bridge_completeReceiveData(uint8_t intfNum); + + +#ifdef __cplusplus +} +#endif +#endif //_UsbCdc_H_ +//Released_Version_4_10_02 diff --git a/source/USB_API/USB_Common/UsbIsr.h b/source/USB_API/USB_Common/UsbIsr.h new file mode 100644 index 0000000..2747532 --- /dev/null +++ b/source/USB_API/USB_Common/UsbIsr.h @@ -0,0 +1,81 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +/* + * ======== UsbIsr.h ======== + */ +#include + +#ifndef _ISR_H_ +#define _ISR_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * Handle incoming setup packet. + * returns TRUE to keep CPU awake + */ +uint8_t SetupPacketInterruptHandler(void); + +/** + * Handle VBuss on signal. + */ +void PWRVBUSonHandler(void); + +/** + * Handle VBuss off signal. + */ +void PWRVBUSoffHandler(void); + +/** + * Handle In-requests from control pipe. + */ +void IEP0InterruptHandler(void); + +/** + * Handle Out-requests from control pipe. + */ +uint8_t OEP0InterruptHandler(void); + +/*----------------------------------------------------------------------------+ + | End of header file | + +----------------------------------------------------------------------------*/ + +#ifdef __cplusplus +} +#endif +#endif /* _ISR_H_ */ + +/*------------------------ Nothing Below This Line --------------------------*/ +//Released_Version_4_10_02 diff --git a/source/USB_API/USB_Common/defMSP430USB.h b/source/USB_API/USB_Common/defMSP430USB.h new file mode 100644 index 0000000..d7231be --- /dev/null +++ b/source/USB_API/USB_Common/defMSP430USB.h @@ -0,0 +1,188 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +/* + * ======== defMSP430USB.h ======== + */ + +#include + +#ifndef _defMSP430USB_H +#define _defMSP430USB_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/*----------------------------------------------------------------------------+ + | Constant Definitions | + +----------------------------------------------------------------------------*/ +#define YES 1 +#define NO 0 + +#define TRUE 1 +#define FALSE 0 + +#define NOERR 0 +#define ERR 1 + +#define NO_ERROR 0 +#define ERROR 1 + +#define DISABLE 0 +#define ENABLE 1 + + +/*----------------------------------------------------------------------------+ + | USB Constants, Type Definition & Macro | + +----------------------------------------------------------------------------*/ + +//USB related Constant +#define MAX_ENDPOINT_NUMBER 0x07 //A maximum of 7 endpoints is available +#define EP0_MAX_PACKET_SIZE 0x08 +#define EP0_PACKET_SIZE 0x08 +#define EP_MAX_PACKET_SIZE 0x40 + +//Base addresses of transmit and receive buffers +#define OEP1_X_BUFFER_ADDRESS 0x1C00 //Input Endpoint 1 X Buffer Base-address +#define OEP1_Y_BUFFER_ADDRESS 0x1C40 //Input Endpoint 1 Y Buffer Base-address +#define IEP1_X_BUFFER_ADDRESS 0x1C80 //Output Endpoint 1 X Buffer Base-address +#define IEP1_Y_BUFFER_ADDRESS 0x1CC0 //Output Endpoint 1 Y Buffer Base-address + +#define OEP2_X_BUFFER_ADDRESS 0x1D00 //Input Endpoint 2 X Buffer Base-address +#define OEP2_Y_BUFFER_ADDRESS 0x1D40 //Input Endpoint 2 Y Buffer Base-address +#define IEP2_X_BUFFER_ADDRESS 0x1D80 //Output Endpoint 2 X Buffer Base-address +#define IEP2_Y_BUFFER_ADDRESS 0x1DC0 //Output Endpoint 2 Y Buffer Base-address + +#define OEP3_X_BUFFER_ADDRESS 0x1E00 //Input Endpoint 2 X Buffer Base-address +#define OEP3_Y_BUFFER_ADDRESS 0x1E40 //Input Endpoint 2 Y Buffer Base-address +#define IEP3_X_BUFFER_ADDRESS 0x1E80 //Output Endpoint 2 X Buffer Base-address +#define IEP3_Y_BUFFER_ADDRESS 0x1EC0 //Output Endpoint 2 Y Buffer Base-address + +#define OEP4_X_BUFFER_ADDRESS 0x1F00 //Input Endpoint 2 X Buffer Base-address +#define OEP4_Y_BUFFER_ADDRESS 0x1F40 //Input Endpoint 2 Y Buffer Base-address +#define IEP4_X_BUFFER_ADDRESS 0x1F80 //Output Endpoint 2 X Buffer Base-address +#define IEP4_Y_BUFFER_ADDRESS 0x1FC0 //Output Endpoint 2 Y Buffer Base-address + +#define OEP5_X_BUFFER_ADDRESS 0x2000 //Input Endpoint 2 X Buffer Base-address +#define OEP5_Y_BUFFER_ADDRESS 0x2040 //Input Endpoint 2 Y Buffer Base-address +#define IEP5_X_BUFFER_ADDRESS 0x2080 //Output Endpoint 2 X Buffer Base-address +#define IEP5_Y_BUFFER_ADDRESS 0x20C0 //Output Endpoint 2 Y Buffer Base-address + +#define OEP6_X_BUFFER_ADDRESS 0x2100 //Input Endpoint 2 X Buffer Base-address +#define OEP6_Y_BUFFER_ADDRESS 0x2140 //Input Endpoint 2 Y Buffer Base-address +#define IEP6_X_BUFFER_ADDRESS 0x2180 //Output Endpoint 2 X Buffer Base-address +#define IEP6_Y_BUFFER_ADDRESS 0x21C0 //Output Endpoint 2 Y Buffer Base-address + +#define OEP7_X_BUFFER_ADDRESS 0x2200 //Input Endpoint 2 X Buffer Base-address +#define OEP7_Y_BUFFER_ADDRESS 0x2240 //Input Endpoint 2 Y Buffer Base-address +#define IEP7_X_BUFFER_ADDRESS 0x2280 //Output Endpoint 2 X Buffer Base-address +#define IEP7_Y_BUFFER_ADDRESS 0x22C0 //Output Endpoint 2 Y Buffer Base-address + +#define X_BUFFER 0 +#define Y_BUFFER 1 + +//Macros for end point numbers +#define EP1 1 +#define EP2 2 +#define EP3 3 +#define EP4 4 +#define EP5 5 +#define EP6 6 +#define EP7 7 + +//addresses of pipes for endpoints +#define EP1_OUT_ADDR 0x01 //address for endpoint 1 +#define EP2_OUT_ADDR 0x02 //address for endpoint 2 +#define EP3_OUT_ADDR 0x03 //address for endpoint 3 +#define EP4_OUT_ADDR 0x04 //address for endpoint 4 +#define EP5_OUT_ADDR 0x05 //address for endpoint 5 +#define EP6_OUT_ADDR 0x06 //address for endpoint 6 +#define EP7_OUT_ADDR 0x07 //address for endpoint 7 + +//Input end points +#define EP1_IN_ADDR 0x81 //address for endpoint 1 +#define EP2_IN_ADDR 0x82 //address for endpoint 2 +#define EP3_IN_ADDR 0x83 //address for endpoint 3 +#define EP4_IN_ADDR 0x84 //address for endpoint 4 +#define EP5_IN_ADDR 0x85 //address for endpoint 5 +#define EP6_IN_ADDR 0x86 //address for endpoint 6 +#define EP7_IN_ADDR 0x87 //address for endpoint 7 + + +//EDB Data Structure +typedef struct _tEDB { + uint8_t bEPCNF; //Endpoint Configuration + uint8_t bEPBBAX; //Endpoint X Buffer Base Address + uint8_t bEPBCTX; //Endpoint X Buffer byte Count + uint8_t bSPARE0; //no used + uint8_t bSPARE1; //no used + uint8_t bEPBBAY; //Endpoint Y Buffer Base Address + uint8_t bEPBCTY; //Endpoint Y Buffer byte Count + uint8_t bEPSIZXY; //Endpoint XY Buffer Size +} tEDB, *tpEDB; + +typedef struct _tEDB0 { + uint8_t bIEPCNFG; //Input Endpoint 0 Configuration Register + uint8_t bIEPBCNT; //Input Endpoint 0 Buffer Byte Count + uint8_t bOEPCNFG; //Output Endpoint 0 Configuration Register + uint8_t bOEPBCNT; //Output Endpoint 0 Buffer Byte Count +} tEDB0, *tpEDB0; + +//EndPoint Desciptor Block Bits +#define EPCNF_USBIE 0x04 //USB Interrupt on Transaction Completion. Set By MCU + //0:No Interrupt, 1:Interrupt on completion +#define EPCNF_STALL 0x08 //USB Stall Condition Indication. Set by UBM + //0: No Stall, 1:USB Install Condition +#define EPCNF_DBUF 0x10 //Double Buffer Enable. Set by MCU + //0: Primary Buffer Only(x-buffer only), 1:Toggle Bit Selects Buffer + +#define EPCNF_TOGGLE 0x20 //USB Toggle bit. This bit reflects the toggle sequence bit of DATA0 and DATA1. + +#define EPCNF_UBME 0x80 //UBM Enable or Disable bit. Set or Clear by MCU. + //0:UBM can't use this endpoint + //1:UBM can use this endpoint +#define EPBCNT_BYTECNT_MASK 0x7F //MASK for Buffer Byte Count +#define EPBCNT_NAK 0x80 //NAK, 0:No Valid in buffer, 1:Valid packet in buffer + +//definitions for MSP430 USB-module +#define START_OF_USB_BUFFER 0x1C00 + +//input and output buffers for EP0 +#define USBIEP0BUF 0x2378 +#define USBOEP0BUF 0x2370 + +#ifdef __cplusplus +} +#endif +#endif /*_defMSP430USB_H */ +//Released_Version_4_10_02 diff --git a/source/USB_API/USB_Common/device.h b/source/USB_API/USB_Common/device.h new file mode 100644 index 0000000..0c45b43 --- /dev/null +++ b/source/USB_API/USB_Common/device.h @@ -0,0 +1,78 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +/* + * ======== device.h ======== + */ +#include + +#if defined (__MSP430F6659__) || defined (__MSP430F6658__) || \ + defined (__MSP430F5659__) || \ + defined (__MSP430F5658__) + #define __MSP430F565x_F665x +#elif defined (__MSP430F6638__) || defined (__MSP430F6637__) || \ + defined (__MSP430F6636__) || \ + defined (__MSP430F6635__) || defined (__MSP430F6634__) || \ + defined (__MSP430F6633__) || \ + defined (__MSP430F6632__) || defined (__MSP430F6631__) || \ + defined (__MSP430F6630__) || \ + defined (__MSP430F5638__) || defined (__MSP430F5637__) || \ + defined (__MSP430F5636__) || \ + defined (__MSP430F5635__) || defined (__MSP430F5634__) || \ + defined (__MSP430F5633__) || \ + defined (__MSP430F5632__) || defined (__MSP430F5631__) || \ + defined (__MSP430F5630__) + #define __MSP430F563x_F663x +#elif defined (__MSP430F5510__) || defined (__MSP430F5509__) || \ + defined (__MSP430F5508__) || \ + defined (__MSP430F5507__) || defined (__MSP430F5506__) || \ + defined (__MSP430F5505__) || \ + defined (__MSP430F5504__) || defined (__MSP430F5503__) || \ + defined (__MSP430F5502__) || \ + defined (__MSP430F5501__) || defined (__MSP430F5500__) + #define __MSP430F550x +#elif defined (__MSP430F5529__) || defined (__MSP430F5528__) || \ + defined (__MSP430F5527__) || \ + defined (__MSP430F5526__) || defined (__MSP430F5525__) || \ + defined (__MSP430F5524__) || \ + defined (__MSP430F5522__) || defined (__MSP430F5521__) || \ + defined (__MSP430F5519__) || \ + defined (__MSP430F5517__) || defined (__MSP430F5515__) || \ + defined (__MSP430F5514__) || \ + defined (__MSP430F5513__) + #define __MSP430F552x +#else + #error \ + Define a constant of format __MSP430Fxxxx__ within the projects preprocessor settings, +according to the device being used. +#endif +/*------------------------ Nothing Below This Line --------------------------*/ +//Released_Version_4_10_02 diff --git a/source/USB_API/USB_Common/types.h b/source/USB_API/USB_Common/types.h new file mode 100644 index 0000000..64f8421 --- /dev/null +++ b/source/USB_API/USB_Common/types.h @@ -0,0 +1,96 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ + + +/* +* This file is DEPRECATED. It is being included in the USB stack to +* provide backward compatibility with MSP430USB_Developers_Package_4_00_00 +* and previous versions of the stack +* +*/ + +/* + * ======== types.h ======== + */ +#ifndef _TYPES_H_ +#define _TYPES_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#ifdef __TI_COMPILER_VERSION__ +#define __no_init +#define __data16 +#endif + +/*----------------------------------------------------------------------------+ + | Include files | + +----------------------------------------------------------------------------*/ +/*----------------------------------------------------------------------------+ + | Function Prototype | + +----------------------------------------------------------------------------*/ +/*----------------------------------------------------------------------------+ + | Type Definition & Macro | + +----------------------------------------------------------------------------*/ +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef short SHORT; +typedef unsigned short USHORT; +typedef long LONG; +typedef unsigned long ULONG; +typedef void VOID; +typedef unsigned long HANDLE; +typedef char * PSTR; +typedef int BOOL; +typedef double DOUBLE; +typedef unsigned char BYTE; +typedef unsigned char* PBYTE; +typedef unsigned int WORD; +typedef unsigned long DWORD; +typedef unsigned long* PDWORD; + +/*----------------------------------------------------------------------------+ + | End of header file | + +----------------------------------------------------------------------------*/ +#ifdef __cplusplus +} +#endif +#endif /* + * _TYPES_H_ + *------------------------ Nothing Below This Line -------------------------- + */ + +//Released_Version_4_10_02 diff --git a/source/USB_API/USB_Common/usb.c b/source/USB_API/USB_Common/usb.c new file mode 100644 index 0000000..0e31f04 --- /dev/null +++ b/source/USB_API/USB_Common/usb.c @@ -0,0 +1,1896 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +/** @file usb.c + * @brief Contains APIs related to handling of Control Endpoint + */ +/* + * ======== usb.c ======== + */ +/*----------------------------------------------------------------------------+ + | Include files | + +----------------------------------------------------------------------------*/ + +// +//! \cond +// +#include +#include "driverlib.h" + +#include "../USB_Common/device.h" +#include "../USB_Common/defMSP430USB.h" +#include "../USB_Common/usb.h" //USB-specific Data Structures +#include "../USB_CDC_API/UsbCdc.h" +#include "../USB_PHDC_API/UsbPHDC.h" +#include "../USB_HID_API/UsbHidReq.h" +#include "../USB_MSC_API/UsbMscScsi.h" +#include "../USB_Common/UsbIsr.h" +#include + + +/*----------------------------------------------------------------------------+ + | Internal Constant Definition | + +----------------------------------------------------------------------------*/ +#define NO_MORE_DATA 0xFFFF +#define EPBCT_NAK 0x80 +#define EPCNF_TOGLE 0x20 + +#define DIRECTION_IN 0x80 +#define DIRECTION_OUT 0x00 + +#if defined(__TI_COMPILER_VERSION__) || defined(__GNUC__) +#define __no_init +#define __data16 +#endif + +/*----------------------------------------------------------------------------+ + | Internal Variables | + +----------------------------------------------------------------------------*/ + +static uint8_t bConfigurationNumber; //Set to 1 when USB device has been +//configured, set to 0 when unconfigured + +static uint8_t bInterfaceNumber; //interface number + +uint16_t wBytesRemainingOnIEP0; //For endpoint zero transmitter only + //Holds count of bytes remaining to be + //transmitted by endpoint 0. A value + //of 0 means that a 0-length data packet + //A value of 0xFFFF means that transfer + //is complete. + +uint16_t wBytesRemainingOnOEP0; //For endpoint zero transmitter only + //Holds count of bytes remaining to be + //received by endpoint 0. A value + //of 0 means that a 0-length data packet + //A value of 0xFFFF means that transfer + //is complete. + +static const uint8_t* pbIEP0Buffer; //A buffer pointer to input end point 0 + //Data sent back to host is copied from + //this pointed memory location + +static uint8_t* pbOEP0Buffer; //A buffer pointer to output end point 0 + //Data sent from host is copied to + //this pointed memory location + +static uint8_t bHostAskMoreDataThanAvailable = 0; + +uint8_t abUsbRequestReturnData[USB_RETURN_DATA_LENGTH]; +uint8_t abUsbRequestIncomingData[USB_RETURN_DATA_LENGTH]; + +__no_init uint8_t abramSerialStringDescriptor[34]; + +uint8_t bStatusAction; +uint8_t bFunctionSuspended = FALSE; //TRUE if function is suspended +uint8_t bEnumerationStatus = 0; //is 0 if not enumerated + +static uint8_t bRemoteWakeup; + +uint16_t wUsbEventMask; //used by USB_getEnabledEvents() and USB_setEnabledEvents() + +#ifdef _MSC_ +extern uint8_t USBMSC_reset (void); +void MscResetData (); +extern struct _MscState MscState; +#endif + +#ifdef NON_COMPOSITE_MULTIPLE_INTERFACES + +extern const void *usbConfigurationDescriptors[]; +extern const void *usbDeviceDescriptors[]; +extern const uint8_t usbConfigurationsSizes[]; +uint8_t activeInterfaceIndex = 0; + +#endif + +/*----------------------------------------------------------------------------+ + | Global Variables | + +----------------------------------------------------------------------------*/ +/*----------------------------------------------------------------------------+ + | Hardware Related Structure Definition | + +----------------------------------------------------------------------------*/ + +#ifdef __IAR_SYSTEMS_ICC__ + +#pragma location = 0x2380 +__no_init tDEVICE_REQUEST __data16 tSetupPacket; + +#pragma location = 0x0920 +__no_init tEDB0 __data16 tEndPoint0DescriptorBlock; + +#pragma location = 0x23C8 +__no_init tEDB __data16 tInputEndPointDescriptorBlock[7]; + +#pragma location = 0x2388 +__no_init tEDB __data16 tOutputEndPointDescriptorBlock[7]; + +#pragma location = 0x2378 +__no_init uint8_t __data16 abIEP0Buffer[EP0_MAX_PACKET_SIZE]; + +#pragma location = 0x2370 +__no_init uint8_t __data16 abOEP0Buffer[EP0_MAX_PACKET_SIZE]; + +#pragma location = OEP1_X_BUFFER_ADDRESS +__no_init uint8_t __data16 pbXBufferAddressEp1[EP_MAX_PACKET_SIZE]; + +#pragma location = OEP1_Y_BUFFER_ADDRESS +__no_init uint8_t __data16 pbYBufferAddressEp1[EP_MAX_PACKET_SIZE]; + +#pragma location = IEP1_X_BUFFER_ADDRESS +__no_init uint8_t __data16 pbXBufferAddressEp81[EP_MAX_PACKET_SIZE]; + +#pragma location = IEP1_Y_BUFFER_ADDRESS +__no_init uint8_t __data16 pbYBufferAddressEp81[EP_MAX_PACKET_SIZE]; + +#pragma location = OEP2_X_BUFFER_ADDRESS +__no_init uint8_t __data16 pbXBufferAddressEp2[EP_MAX_PACKET_SIZE]; + +#pragma location = OEP2_Y_BUFFER_ADDRESS +__no_init uint8_t __data16 pbYBufferAddressEp2[EP_MAX_PACKET_SIZE]; + +#pragma location = IEP2_X_BUFFER_ADDRESS +__no_init uint8_t __data16 pbXBufferAddressEp82[EP_MAX_PACKET_SIZE]; + +#pragma location = IEP2_Y_BUFFER_ADDRESS +__no_init uint8_t __data16 pbYBufferAddressEp82[EP_MAX_PACKET_SIZE]; + +#pragma location = OEP3_X_BUFFER_ADDRESS +__no_init uint8_t __data16 pbXBufferAddressEp3[EP_MAX_PACKET_SIZE]; + +#pragma location = OEP3_Y_BUFFER_ADDRESS +__no_init uint8_t __data16 pbYBufferAddressEp3[EP_MAX_PACKET_SIZE]; + +#pragma location = IEP3_X_BUFFER_ADDRESS +__no_init uint8_t __data16 pbXBufferAddressEp83[EP_MAX_PACKET_SIZE]; + +#pragma location = IEP3_Y_BUFFER_ADDRESS +__no_init uint8_t __data16 pbYBufferAddressEp83[EP_MAX_PACKET_SIZE]; + +#pragma location = OEP4_X_BUFFER_ADDRESS +__no_init uint8_t __data16 pbXBufferAddressEp4[EP_MAX_PACKET_SIZE]; + +#pragma location = OEP4_Y_BUFFER_ADDRESS +__no_init uint8_t __data16 pbYBufferAddressEp4[EP_MAX_PACKET_SIZE]; + +#pragma location = IEP4_X_BUFFER_ADDRESS +__no_init uint8_t __data16 pbXBufferAddressEp84[EP_MAX_PACKET_SIZE]; + +#pragma location = IEP4_Y_BUFFER_ADDRESS +__no_init uint8_t __data16 pbYBufferAddressEp84[EP_MAX_PACKET_SIZE]; + +#pragma location = OEP5_X_BUFFER_ADDRESS +__no_init uint8_t __data16 pbXBufferAddressEp5[EP_MAX_PACKET_SIZE]; + +#pragma location = OEP5_Y_BUFFER_ADDRESS +__no_init uint8_t __data16 pbYBufferAddressEp5[EP_MAX_PACKET_SIZE]; + +#pragma location = IEP5_X_BUFFER_ADDRESS +__no_init uint8_t __data16 pbXBufferAddressEp85[EP_MAX_PACKET_SIZE]; + +#pragma location = IEP5_Y_BUFFER_ADDRESS +__no_init uint8_t __data16 pbYBufferAddressEp85[EP_MAX_PACKET_SIZE]; + +#pragma location = OEP6_X_BUFFER_ADDRESS +__no_init uint8_t __data16 pbXBufferAddressEp6[EP_MAX_PACKET_SIZE]; + +#pragma location = OEP6_Y_BUFFER_ADDRESS +__no_init uint8_t __data16 pbYBufferAddressEp6[EP_MAX_PACKET_SIZE]; + +#pragma location = IEP6_X_BUFFER_ADDRESS +__no_init uint8_t __data16 pbXBufferAddressEp86[EP_MAX_PACKET_SIZE]; + +#pragma location = IEP6_Y_BUFFER_ADDRESS +__no_init uint8_t __data16 pbYBufferAddressEp86[EP_MAX_PACKET_SIZE]; + +#pragma location = OEP7_X_BUFFER_ADDRESS +__no_init uint8_t __data16 pbXBufferAddressEp7[EP_MAX_PACKET_SIZE]; + +#pragma location = OEP7_Y_BUFFER_ADDRESS +__no_init uint8_t __data16 pbYBufferAddressEp7[EP_MAX_PACKET_SIZE]; + +#pragma location = IEP7_X_BUFFER_ADDRESS +__no_init uint8_t __data16 pbXBufferAddressEp87[EP_MAX_PACKET_SIZE]; + +#pragma location = IEP7_Y_BUFFER_ADDRESS +__no_init uint8_t __data16 pbYBufferAddressEp87[EP_MAX_PACKET_SIZE]; + + + +#endif + +#if defined(__TI_COMPILER_VERSION__) || defined(__GNUC__) +extern __no_init tDEVICE_REQUEST tSetupPacket; +extern __no_init tEDB0 tEndPoint0DescriptorBlock; +extern __no_init tEDB tInputEndPointDescriptorBlock[7]; +extern __no_init tEDB tOutputEndPointDescriptorBlock[7]; +extern __no_init uint8_t abIEP0Buffer[EP0_MAX_PACKET_SIZE]; +extern __no_init uint8_t abOEP0Buffer[EP0_MAX_PACKET_SIZE]; +extern __no_init uint8_t pbXBufferAddressEp1[EP_MAX_PACKET_SIZE]; +extern __no_init uint8_t pbYBufferAddressEp1[EP_MAX_PACKET_SIZE]; +extern __no_init uint8_t pbXBufferAddressEp81[EP_MAX_PACKET_SIZE]; +extern __no_init uint8_t pbYBufferAddressEp81[EP_MAX_PACKET_SIZE]; +extern __no_init uint8_t pbXBufferAddressEp2[EP_MAX_PACKET_SIZE]; +extern __no_init uint8_t pbYBufferAddressEp2[EP_MAX_PACKET_SIZE]; +extern __no_init uint8_t pbXBufferAddressEp82[EP_MAX_PACKET_SIZE]; +extern __no_init uint8_t pbYBufferAddressEp82[EP_MAX_PACKET_SIZE]; +extern __no_init uint8_t pbXBufferAddressEp3[EP_MAX_PACKET_SIZE]; +extern __no_init uint8_t pbYBufferAddressEp3[EP_MAX_PACKET_SIZE]; +extern __no_init uint8_t pbXBufferAddressEp83[EP_MAX_PACKET_SIZE]; +extern __no_init uint8_t pbYBufferAddressEp83[EP_MAX_PACKET_SIZE]; + +extern __no_init uint8_t pbXBufferAddressEp4[EP_MAX_PACKET_SIZE]; +extern __no_init uint8_t pbYBufferAddressEp4[EP_MAX_PACKET_SIZE]; +extern __no_init uint8_t pbXBufferAddressEp84[EP_MAX_PACKET_SIZE]; +extern __no_init uint8_t pbYBufferAddressEp84[EP_MAX_PACKET_SIZE]; + +extern __no_init uint8_t pbXBufferAddressEp5[EP_MAX_PACKET_SIZE]; +extern __no_init uint8_t pbYBufferAddressEp5[EP_MAX_PACKET_SIZE]; +extern __no_init uint8_t pbXBufferAddressEp85[EP_MAX_PACKET_SIZE]; +extern __no_init uint8_t pbYBufferAddressEp85[EP_MAX_PACKET_SIZE]; + +#endif + +void CdcResetData (); +void HidResetData (); +void PHDCResetData(); + +void USB_InitSerialStringDescriptor (void); +void USB_initMemcpy (void); +uint16_t USB_determineFreq(void); + +/* Version string to embed in executable. May need to change for ELF compiler */ +const char *VERSION = "USB_DEVELOPERS_PACKAGE_4_10_02"; +char *USB_getVersion(void) +{ + return ((char *)&VERSION); +} + +// +//! \endcond +// + +//***************************************************************************** +// +//! Initializes the USB Module. +//! +//! +//! Initializes the USB module by configuring power and clocks, and configures +//! pins that are critical for USB. This should be called very soon after the +//! beginning of program execution. +//! +//! Note that this does not enable the USB module (that is, does not set +//! USB_EN bit). Rather, it prepares the USB module to detect the application of +//! power to VBUS, after which the application may choose to enable the module +//! and connect to USB. Calling this function is necessary to achieve expected +//! LPM3 current consumption into DVCC. +//! +//! \return \b kUSB_succeed +// +//***************************************************************************** + +uint8_t USB_init (void) +{ + uint16_t bGIE = __get_SR_register() & GIE; //save interrupt status + uint16_t MCLKFreq = USB_determineFreq(); + uint16_t DelayConstant_250us = ((MCLKFreq >> 6) + (MCLKFreq >> 7) + (MCLKFreq >> 9)); + volatile uint16_t i, j; + + char *(*fp)(void); + + /* force version string into executable */ + fp = &USB_getVersion; + fp(); + + //atomic operation - disable interrupts + __disable_interrupt(); //Disable global interrupts + + //configuration of USB module + USBKEYPID = 0x9628; //set KEY and PID to 0x9628 -> access to + //configuration registers enabled + /* If USB device is self-powered, USB_SUPPORT_SELF_POWERED = 0xc0 */ +#if (USB_SUPPORT_SELF_POWERED == 0xc0) + /* To fix USB9 enumeration issue */ + USBPWRCTL = 0; +#endif + + USBPHYCTL = PUSEL; //use DP and DM as USB terminals (not needed + //because an external PHY is connected to port + //9) + if(USB_USE_INTERNAL_3V3LDO == TRUE) + USBPWRCTL = VUSBEN + SLDOAON; //enable 3.3v and 1.8v LDO (3.3 and 1.8V) + else + USBPWRCTL = SLDOEN + USBDETEN; //enable 1.8v and VBUS voltage detection while internal 3.3v + //LDO is turned off. + + for (j = 0; j < 20; j++) { + for (i = 0; i < (DelayConstant_250us); i++) {//wait some time for LDOs (5ms delay) + _NOP(); + } + } + + USBPWRCTL |= VBONIE; //enable interrupt VBUSon + USBKEYPID = 0x9600; //access to configuration registers disabled + + //reset events mask + wUsbEventMask = 0; + + //init Serial Number +#if (USB_STR_INDEX_SERNUM != 0) + USB_InitSerialStringDescriptor(); +#endif + + //init memcpy() function: DMA or non-DMA + USB_initMemcpy(); +#ifdef _MSC_ + MscResetCtrlLun(); +#endif + +#ifdef BRIDGE_CDC_PRESENT + USBCDC_setupDMA_Bridge(); +#endif + + __bis_SR_register(bGIE); //restore interrupt status + return (kUSB_succeed); +} + +//***************************************************************************** +// +//! Initializes the USB Module. Also enables events and connects. +//! +//! +//! Initializes the USB module by configuring power and clocks, and configures +//! pins that are critical for USB. This should be called very soon after the +//! beginning of program execution. +//! +//! If connectEnable is TRUE, then this API then enables the USB module, which +//! includes activating the PLL and setting the USB_EN bit. AFter enabling the +//! USB module, this API will connect to the host if VBUS is present. +//! +//! If eventsEnable is set to TRUE then all USB events are enabled by this API. +//! +//! \param connectEnable If TRUE, Connect to host if VBUS is present by +//! pulling the D+ signal high using the PUR pin. +//! \param eventsEnable If TRUE, all USB events handlers are enabled +//! \return \b kUSB_succeed +// +//***************************************************************************** + +uint8_t USB_setup(uint8_t connectEnable, uint8_t eventsEnable) +{ + uint8_t status; + + status = USB_init(); + + if (eventsEnable) { + USB_setEnabledEvents(kUSB_allUsbEvents); + } + if (connectEnable) { + if (USB_connectionInfo() & kUSB_vbusPresent){ + if (USB_enable() == kUSB_succeed){ + USB_reset(); + USB_connect(); + } + } + } + + return (status); +} + +// +//! \cond +// + +//---------------------------------------------------------------------------- +//This function will be compiled only if +#if (USB_STR_INDEX_SERNUM != 0) +void USB_InitSerialStringDescriptor (void) +{ + uint8_t i,j,hexValue; + uint8_t* pbSerNum; + uint8_t bBytes; + + j = 1; //we start with second byte, first byte (lenght) + //will be filled later + pbSerNum = 0; + abramSerialStringDescriptor[j++] = DESC_TYPE_STRING; + + //TLV access Function Call + TLV_getInfo(TLV_TAG_DIERECORD, 0, + (uint8_t *)&bBytes, (uint16_t **)&pbSerNum); + if (bBytes == 0){ //no serial number available + //use 00 as serial number = no serial number available + abramSerialStringDescriptor[0] = 4; //length + abramSerialStringDescriptor[j++] = 0; //no serial number available + abramSerialStringDescriptor[j++] = 0; //no serial number available + } else { + for (i = 0; (i < bBytes) && (i < 8); i++,pbSerNum++) + { + hexValue = (*pbSerNum & 0xF0) >> 4; + if (hexValue < 10){ + abramSerialStringDescriptor[j++] = (hexValue + '0'); + } else { abramSerialStringDescriptor[j++] = (hexValue + 55);} + abramSerialStringDescriptor[j++] = 0x00; //needed for UNI-Code + + hexValue = (*pbSerNum & 0x0F); + if (hexValue < 10){ + abramSerialStringDescriptor[j++] = (hexValue + '0'); + } else { abramSerialStringDescriptor[j++] = (hexValue + 55);} + abramSerialStringDescriptor[j++] = 0x00; //needed for UNI-Code + } + abramSerialStringDescriptor[0] = i * 4 + 2; //calculate the length + } +} + +#endif + +// +//! \endcond +// + +//***************************************************************************** +// +//! Enables the USB Module. +//! +//! Enables the USB module, which includes activating the PLL and setting the +//! USB_EN bit. Power consumption increases as a result of this operation (see +//! device datasheet for specifics). This call should only be made after an +//! earlier call to USB_init(), and prior to any other call except than +//! USB_setEnabledEvents(), or USB_getEnabledEvents(). It is usually called just +//! prior to attempting to connect with a host after a bus connection has +//! already been detected. +//! +//! \return \b kUSB_succeed +// +//***************************************************************************** + +uint8_t USB_enable () +{ +#ifdef USE_TIMER_FOR_RESUME + USB_enable_crystal(); + return (kUSB_succeed); +#else + + volatile uint16_t i, k; + volatile uint16_t j = 0; + uint16_t status; + uint16_t MCLKFreq = USB_determineFreq(); + uint16_t DelayConstant_250us = ((MCLKFreq >> 6) + (MCLKFreq >> 7) + (MCLKFreq >> 9)); + + if (!(USBPWRCTL & USBBGVBV)){ //check USB Bandgap and VBUS valid + return (kUSB_generalError); + } + + if ((USBCNF & USB_EN) && + (USBPLLCTL & UPLLEN)){ + return (kUSB_succeed); //exit if PLL is already enalbed + } + +#if defined (__MSP430F552x) || defined (__MSP430F550x) + GPIO_setAsPeripheralModuleFunctionOutputPin(GPIO_PORT_P5, GPIO_PIN2); + GPIO_setAsPeripheralModuleFunctionOutputPin(GPIO_PORT_P5, GPIO_PIN3); +#elif defined (__MSP430F563x_F663x) || defined (__MSP430F565x_F665x) + GPIO_setAsPeripheralModuleFunctionOutputPin(GPIO_PORT_P7, GPIO_PIN2); + GPIO_setAsPeripheralModuleFunctionOutputPin(GPIO_PORT_P7, GPIO_PIN3); +#endif + USBKEYPID = 0x9628; //set KEY and PID to 0x9628 -> access to + //configuration registers enabled +#ifndef DRIVERLIB_LEGACY_MODE + if (USB_XT_FREQ_VALUE >= 24) { + status = UCS_XT2StartWithTimeout( + XT2DRIVE_3, 50000); + } + else if(USB_XT_FREQ_VALUE >= 16) { + status = UCS_XT2StartWithTimeout( + XT2DRIVE_2, 50000); + } + else if(USB_XT_FREQ_VALUE >= 8) { + status = UCS_XT2StartWithTimeout( + XT2DRIVE_1, 50000); + } + else { + status = UCS_XT2StartWithTimeout( + XT2DRIVE_0, 50000); + } +#else + if (USB_XT_FREQ_VALUE >= 24) { + status = UCS_XT2StartWithTimeout(UCS_BASE, + XT2DRIVE_3, 50000); + } + else if(USB_XT_FREQ_VALUE >= 16) { + status = UCS_XT2StartWithTimeout(UCS_BASE, + XT2DRIVE_2, 50000); + } + else if(USB_XT_FREQ_VALUE >= 8) { + status = UCS_XT2StartWithTimeout(UCS_BASE, + XT2DRIVE_1, 50000); + } + else { + status = UCS_XT2StartWithTimeout(UCS_BASE, + XT2DRIVE_0, 50000); + } +#endif + + if (status == STATUS_FAIL) { + return (kUSB_generalError); + } + + USBPLLDIVB = USB_XT_FREQ; //Settings desired frequency + + USBPLLCTL = UPFDEN + UPLLEN; //Select XT2 as Ref / Select PLL for USB / Discrim. + //on, enable PLL + + //Wait some time till PLL is settled + do + { + USBPLLIR = 0x0000; //make sure no interrupts can occur on + //PLL-module + if ((((bFunctionSuspended == TRUE) || (bFunctionSuspended == FALSE)) && (USB_DISABLE_XT_SUSPEND == 1)) || + ((USB_DISABLE_XT_SUSPEND == 0) && (bFunctionSuspended == FALSE))){ //BUG NUMBER 4879 +#ifdef __MSP430F6638 + //wait 1 ms till enable USB + for(k = 0; k < 4; k++) + { + for (i = 0; i < (DelayConstant_250us); i++){ + _NOP(); + } + } +#else + //wait 1/2 ms till enable USB + for(k = 0; k < 2; k++) + { + for (i = 0; i < (DelayConstant_250us); i++){ + _NOP(); + } + } +#endif + } + + if (j++ > 10){ + USBKEYPID = 0x9600; //access to configuration registers disabled + return (kUSB_generalError); + } + } while (USBPLLIR != 0); + + USBCNF |= USB_EN; //enable USB module + USBKEYPID = 0x9600; //access to configuration registers disabled + return (kUSB_succeed); +#endif +} + +#ifdef USE_TIMER_FOR_RESUME + +//***************************************************************************** +// +//! First phase of enabling the USB Module when USE_TIMER_FOR_RESUME is defined +//! +//! This functions is only used by USB_resume to reduce the interrupt latency +//! of the resume interrupt. +//! This function starts the XT2 crystal and then calls an event handler +//! USB_handleCrystalStartedEvent() to allow the application to get control. The +//! application can use a timer or other peripheral to "wait" for the XT2 +//! crystal to stabilize. See the crystal datasheet for typical wait times. +//! The application then informs the stack of XT2 +//! stabilization by calling USB_enable_PLL(). +//! +//! \return \b kUSB_succeed or kUSB_generalError +// +//***************************************************************************** + +uint8_t USB_enable_crystal (void) +{ + volatile uint16_t i, k; + volatile uint16_t j = 0; + + if (!(USBPWRCTL & USBBGVBV)){ //check USB Bandgap and VBUS valid + return (kUSB_generalError); + } + + if ((USBCNF & USB_EN) && + (USBPLLCTL & UPLLEN)){ + return (kUSB_succeed); //exit if PLL is already enalbed + } + +#if defined (__MSP430F552x) || defined (__MSP430F550x) + GPIO_setAsPeripheralModuleFunctionOutputPin(GPIO_PORT_P5, GPIO_PIN2); + GPIO_setAsPeripheralModuleFunctionOutputPin(GPIO_PORT_P5, GPIO_PIN3); +#elif defined (__MSP430F563x_F663x) || defined (__MSP430F565x_F665x) + GPIO_setAsPeripheralModuleFunctionOutputPin(GPIO_PORT_P7, GPIO_PIN2); + GPIO_setAsPeripheralModuleFunctionOutputPin(GPIO_PORT_P7, GPIO_PIN3); +#endif + +#ifndef DRIVERLIB_LEGACY_MODE + if (USB_XT_FREQ_VALUE >= 24) { + UCS_XT2StartWithTimeout(XT2DRIVE_3, 1); + } + else if(USB_XT_FREQ_VALUE >= 16) { + UCS_XT2StartWithTimeout(XT2DRIVE_2, 1); + } + else if(USB_XT_FREQ_VALUE >= 8) { + UCS_XT2StartWithTimeout(XT2DRIVE_1, 1); + } + else { + UCS_XT2StartWithTimeout(XT2DRIVE_0, 1); + } + +#else + if (USB_XT_FREQ_VALUE >= 24) { + UCS_XT2StartWithTimeout(UCS_BASE, XT2DRIVE_3, 1); + } + else if(USB_XT_FREQ_VALUE >= 16) { + UCS_XT2StartWithTimeout(UCS_BASE, XT2DRIVE_2, 1); + } + else if(USB_XT_FREQ_VALUE >= 8) { + UCS_XT2StartWithTimeout(UCS_BASE, XT2DRIVE_1, 1); + } + else { + UCS_XT2StartWithTimeout(UCS_BASE, XT2DRIVE_0, 1); + } + +#endif + + USB_handleCrystalStartedEvent(); + + return (kUSB_succeed); +} + +//***************************************************************************** +// +//! Second phase of enabling the USB Module when USE_TIMER_FOR_RESUME is defined +//! +//! This functions is only used by USB_resume to reduce the interrupt latency +//! of the resume interrupt. +//! This function starts the PLL and then calls an event handler +//! USB_handlePLLStartedEvent() to allow the application to get control. The +//! application can use a timer or other peripheral to "wait" for the USB PLL +//! to stabilize. See the datasheet for typical PLL wait times. +//! The application then informs the stack of XT2 +//! stabilization by calling USB_enable_final(). +//! +//! \return \b kUSB_succeed or kUSB_generalError +// +//***************************************************************************** +void USB_enable_PLL(void) +{ + USBKEYPID = 0x9628; //set KEY and PID to 0x9628 -> access to + //configuration registers enabled + USBPLLDIVB = USB_XT_FREQ; //Settings desired frequency + + USBPLLCTL = UPFDEN + UPLLEN; //Select XT2 as Ref / Select PLL for USB / Discrim. + //on, enable PLL + + USB_handlePLLStartedEvent(); +} + +//***************************************************************************** +// +//! Final phase of enabling the USB Module when USE_TIMER_FOR_RESUME is defined +//! +//! This function is only used by USB_resume to reduce the interrupt latency +//! of the resume interrupt. +//! This function gets called by the application when thye USB PLL has stabilized +//! to allow the resume process to finish. +//! +// +//***************************************************************************** +void USB_enable_final(void) +{ + USBCNF |= USB_EN; //enable USB module + USBKEYPID = 0x9600; //access to configuration registers disabled + USBIFG &= ~(RESRIFG | SUSRIFG); //clear interrupt flags + USBIE = SETUPIE | RSTRIE | SUSRIE; //enable USB specific interrupts (setup, reset, suspend) + + bFunctionSuspended = FALSE; +} + +#endif + +//***************************************************************************** +// +//! Disables the USB Module and PLL. +//! +//! +//! Disables the USB module and PLL. If USB is not enabled when this call is +//! made, no error is returned - the call simply exits with success. +//! +//! If a handleVbusOffEvent() occurs, or if USB_connectionState() begins +//! returning ST_USB_DISCONNECTED, this function should be called (following a +//! call to USB_disconnect()), in order to avoid unnecessary current draw. +//! +//! \return \b kUSB_succeed +// +//***************************************************************************** + +uint8_t USB_disable (void) +{ + USBKEYPID = 0x9628; //set KEY and PID to 0x9628 -> access to + //configuration registers enabled + USBCNF = 0; //disable USB module + USBPLLCTL &= ~UPLLEN; //disable PLL + USBKEYPID = 0x9600; //access to configuration registers disabled + bEnumerationStatus = 0x00; //device is not enumerated + bFunctionSuspended = FALSE; //device is not suspended + return (kUSB_succeed); +} + +//***************************************************************************** +// +//! Enables/Disables the Various USB Events. +//! +//! \param events is the mask for what is to be enabled/disabled. +//! - Valid values are: +//! - \b kUSB_clockFaultEvent +//! - \b kUSB_VbusOnEvent +//! - \b kUSB_VbusOffEvent +//! - \b kUSB_UsbResetEvent +//! - \b kUSB_UsbSuspendEvent +//! - \b kUSB_UsbResumeEvent +//! - \b kUSBCDC_dataReceivedEvent +//! - \b kUSBCDC_sendCompletedEvent +//! - \b kUSBCDC_receiveCompletedEvent +//! - \b kUSBHID_dataReceivedEvent +//! - \b kUSBHID_sendCompletedEvent +//! - \b kUSBHID_receiveCompletedEvent +//! - \b kUSB_allUsbEvents +//! +//! Enables/disables various USB events. Within the events byte, all bits with +//! '1' values will be enabled, and all bits with '0' values will be disabled. +//! (There are no bit-wise operations). By default (that is, prior to any call +//! to this function), all events are disabled. +//! +//! The status of event enabling can be read with the USB_getEnabledEvents() +//! function. This call can be made at any time after a call to USB_init(). +//! +//! USB_setEnabledEvents() can be thought of in a similar fashion to +//! setting/clearing interrupt enable bits. The only benefit in keeping an event +//! disabled is to save the unnecessary execution cycles incurred from running +//! an "empty" event handler. +//! +//! The mask constant \b kUSB_allUsbEvents is used to enable/disable all events +//! pertaining to core USB functions; in other words, it enables all those with +//! a \b kUSB_ prefix. +//! +//! See Sec. 10 of \e "Programmer's Guide: MSP430 USB API Stack for CDC/PHDC/HID/MSC" for more information about +//! events. +//! +//! \return \b kUSB_succeed +// +//***************************************************************************** + +uint8_t USB_setEnabledEvents (uint16_t events) +{ + wUsbEventMask = events; + return (kUSB_succeed); +} + +//***************************************************************************** +// +//! Returns Which Events are Enabled/Disabled. +//! +//! Returns which events are enabled and which are disabled. The definition of +//! events is the same as for USB_enableEvents() above. +//! +//! If the bit is set, the event is enabled. If cleared, the event is disabled. +//! By default (that is, prior to calling USB_setEnabledEvents() ), all events +//! are disabled. This call can be made at any time after a call to USB_init(). +//! +//! \return \b Events +// +//***************************************************************************** + +uint16_t USB_getEnabledEvents () +{ + return (wUsbEventMask); +} + +//***************************************************************************** +// +//! Resets the USB Module and the Internal State of the API. +//! +//! Resets the USB module and also the internal state of the API. The interrupt +//! register is cleared to make sure no interrupts are pending. If the device +//! had been enumerated, the enumeration is now lost. All open send/receive +//! operations are aborted. +//! +//! This function is most often called immediately before a call to +//! USB_connect(). It should not be called prior to USB_enable(). +//! +//! \return \b kUSB_succeed +// +//***************************************************************************** + +uint8_t USB_reset () +{ + int16_t i; + + USBKEYPID = 0x9628; //set KEY and PID to 0x9628 -> access to + //configuration registers enabled + + //reset should be on the bus after this! + bEnumerationStatus = 0x00; //Device not enumerated yet + bFunctionSuspended = FALSE; //Device is not in suspend mode + + bRemoteWakeup = DISABLE; + + bConfigurationNumber = 0x00; //device unconfigured + bInterfaceNumber = 0x00; + + //FRSTE handling: + //Clear FRSTE in the RESRIFG interrupt service routine before re-configuring USB control registers. + //Set FRSTE at the beginning of SUSRIFG, SETUP, IEPIFG.EP0 and OEPIFG.EP0 interrupt service routines. + USBCTL = 0; //Function Reset Connection disable (FRSTE) + + wBytesRemainingOnIEP0 = NO_MORE_DATA; + wBytesRemainingOnOEP0 = NO_MORE_DATA; + bStatusAction = STATUS_ACTION_NOTHING; + + //The address reset normally will be done automatically during bus function reset + USBFUNADR = 0x00; //reset address of USB device (unconfigured) + + /* Set settings for EP0 */ + //NAK both 0 endpoints and enable endpoint 0 interrupt + tEndPoint0DescriptorBlock.bIEPBCNT = EPBCNT_NAK; + tEndPoint0DescriptorBlock.bOEPBCNT = EPBCNT_NAK; + tEndPoint0DescriptorBlock.bIEPCNFG = EPCNF_USBIE | EPCNF_UBME | EPCNF_STALL; //8 byte data packet + tEndPoint0DescriptorBlock.bOEPCNFG = EPCNF_USBIE | EPCNF_UBME | EPCNF_STALL; //8 byte data packet + + USBOEPIE = USB_OUTEP_INT_EN; + USBIEPIE = USB_INEP_INT_EN; + + //loop for initialization all of used enpoints + for (i = 0; + i < (CDC_NUM_INTERFACES + HID_NUM_INTERFACES + MSC_NUM_INTERFACES + PHDC_NUM_INTERFACES); + i++) + { + uint8_t edbIndex = stUsbHandle[i].edb_Index; + + /* Set settings for IEPx */ + tInputEndPointDescriptorBlock[edbIndex].bEPCNF = EPCNF_USBIE | + EPCNF_UBME | + EPCNF_DBUF; //double buffering + tInputEndPointDescriptorBlock[edbIndex].bEPBBAX = + (uint8_t)(((stUsbHandle[i].iep_X_Buffer - + START_OF_USB_BUFFER) >> 3) & 0x00ff); + tInputEndPointDescriptorBlock[edbIndex].bEPBBAY = + (uint8_t)(((stUsbHandle[i].iep_Y_Buffer - + START_OF_USB_BUFFER) >> 3) & 0x00ff); + tInputEndPointDescriptorBlock[edbIndex].bEPBCTX = EPBCNT_NAK; + tInputEndPointDescriptorBlock[edbIndex].bEPBCTY = EPBCNT_NAK; + tInputEndPointDescriptorBlock[edbIndex].bEPSIZXY = MAX_PACKET_SIZE; + + /* Set settings for OEPx */ +#ifdef BRIDGE_CDC_PRESENT + if (i == BRIDGE_CDC_INTFNUM) { + tOutputEndPointDescriptorBlock[edbIndex].bEPCNF = EPCNF_USBIE | + EPCNF_UBME; + } + else + { + tOutputEndPointDescriptorBlock[edbIndex].bEPCNF = EPCNF_USBIE | + EPCNF_UBME | + EPCNF_DBUF ; //double buffering + } +#else + tOutputEndPointDescriptorBlock[edbIndex].bEPCNF = EPCNF_USBIE | + EPCNF_UBME | + EPCNF_DBUF ; //double buffering +#endif + + tOutputEndPointDescriptorBlock[edbIndex].bEPBBAX = + (uint8_t)(((stUsbHandle[i].oep_X_Buffer - + START_OF_USB_BUFFER) >> 3) & 0x00ff); + tOutputEndPointDescriptorBlock[edbIndex].bEPBBAY = + (uint8_t)(((stUsbHandle[i].oep_Y_Buffer - + START_OF_USB_BUFFER) >> 3) & 0x00ff); + tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX = 0x00; + tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY = 0x00; + tOutputEndPointDescriptorBlock[edbIndex].bEPSIZXY = MAX_PACKET_SIZE; + +# ifdef _CDC_ + /* Additional interrupt end point for CDC */ + if (stUsbHandle[i].dev_Class == CDC_CLASS){ + //The decriptor tool always generates the managemnet endpoint before the data endpoint + tInputEndPointDescriptorBlock[edbIndex - + 1].bEPCNF = EPCNF_USBIE | + EPCNF_UBME | EPCNF_DBUF; //double buffering + tInputEndPointDescriptorBlock[edbIndex - + 1].bEPBBAX = + (uint8_t)(((stUsbHandle[i].intepEP_X_Buffer - + START_OF_USB_BUFFER) >> 3) & 0x00ff); + tInputEndPointDescriptorBlock[edbIndex - + 1].bEPBBAY = + (uint8_t)(((stUsbHandle[i].intepEP_Y_Buffer - + START_OF_USB_BUFFER) >> 3) & 0x00ff); + tInputEndPointDescriptorBlock[edbIndex - 1].bEPBCTX = EPBCNT_NAK; + tInputEndPointDescriptorBlock[edbIndex - 1].bEPBCTY = EPBCNT_NAK; + tInputEndPointDescriptorBlock[edbIndex - + 1].bEPSIZXY = MAX_PACKET_SIZE; + } +# endif + } + +# ifdef _HID_ + HidResetData(); //reset HID specific data structures +# endif //_HID_ + +# ifdef _MSC_ + MscState.isMSCConfigured = FALSE; + USBMSC_reset(); + MscResetData(); +# endif + +# ifdef _CDC_ + CdcResetData(); //reset CDC specific data structures +# endif //_CDC_ + +# ifdef _PHDC_ + PHDCResetData(); // reset CDC specific data structures +# endif // _PHDC_ + + USBCTL = FEN; //enable function + USBIFG = 0; //make sure no interrupts are pending + + USBIE = SETUPIE | RSTRIE | SUSRIE; //enable USB specific interrupts (setup, reset, + //suspend) + USBKEYPID = 0x9600; //access to configuration registers disabled + return (kUSB_succeed); +} + +//***************************************************************************** +// +//! Makes USB Module Available to Host for Connection. +//! +//! Instructs the USB module to make itself available to the host for +//! connection, by pulling the D+ signal high using the PUR pin. This call +//! should only be made after a call to USB_enable(). +//! +//! \return \b kUSB_succeed +// +//***************************************************************************** + +uint8_t USB_connect () +{ + USBKEYPID = 0x9628; //set KEY and PID to 0x9628 -> access to + //configuration registers enabled + USBCNF |= PUR_EN; //generate rising edge on DP -> the host + //enumerates our device as full speed device + USBPWRCTL |= VBOFFIE; //enable interrupt VUSBoff + USBKEYPID = 0x9600; //access to configuration registers disabled + + return (kUSB_succeed); +} + +//***************************************************************************** +// +//! Forces a Disconnect From the USB Host. +//! +//! Forces a logical disconnect from the USB host by pulling the PUR pin low, +//! removing the pullup on the D+ signal. The USB module and PLL remain enabled. +//! If the USB is not connected when this call is made, no error is returned - +//! the call simply exits with success after ensuring PUR is low. +//! +//! \return \b kUSB_succeed +// +//***************************************************************************** + +uint8_t USB_disconnect () +{ + USBKEYPID = 0x9628; //set KEY and PID to 0x9628 -> access to + //configuration registers enabled + USBCNF &= ~PUR_EN; //disconnect pull up resistor - logical + //disconnect from HOST + USBPWRCTL &= ~VBOFFIE; //disable interrupt VUSBoff + USBKEYPID = 0x9600; //access to configuration registers disabled + bEnumerationStatus = 0; //not enumerated + bFunctionSuspended = FALSE; //device is not suspended + return (kUSB_succeed); +} + +//***************************************************************************** +// +//! Remote Wakeup of USB Host. +//! +//! Prompts a remote wakeup of the USB host. The user must ensure that the USB +//! descriptors had indicated remote wakeup capability (using the Descriptor +//! Tool); otherwise the host will ignore the request. +//! +//! If the function returns \b kUSB_generalError, it means that the host did not +//! grant the device the ability to perform a remote wakeup, when it enumerated +//! the device. +//! +//! \return \b kUSB_succeed, \b kUSBgeneralError or \b kUSB_notSuspended. +// +//***************************************************************************** + +uint8_t USB_forceRemoteWakeup () +{ + if (bFunctionSuspended == FALSE){ //device is not suspended + return (kUSB_NotSuspended); + } + if (bRemoteWakeup == ENABLE){ + volatile uint16_t i; + USBCTL |= RWUP; //USB - Device Remote Wakeup Request - this bit + //is self-cleaned + return (kUSB_succeed); + } + return (kUSB_generalError); +} + +//***************************************************************************** +// +//! Gets Connection Info. +//! +//! Returns low-level status information about the USB connection. +//! +//! Because multiple flags can be returned, the possible values can be masked +//! together - for example, \b kUSB_vbusPresent + \b kUSB_suspended. +//! +//! \return A single mask that is the all the statuses together and may +//! consist of the following: +//! - \b kUSB_purHigh +//! - \b kUSB_suspended +//! - \b kUSB_NotSuspended +//! - \b kUSB_Enumerated +//! - \b kUSB_vbusPresent +// +//***************************************************************************** + +uint8_t USB_connectionInfo () +{ + uint8_t retVal = 0; + + if (USBPWRCTL & USBBGVBV){ + retVal |= kUSB_vbusPresent; + } + + if (bEnumerationStatus == ENUMERATION_COMPLETE){ + retVal |= kUSB_Enumerated; + } + + if (USBCNF & PUR_EN){ + retVal |= kUSB_purHigh; + } + + if (bFunctionSuspended == TRUE){ + retVal |= kUSB_suspended; + } else { + retVal |= kUSB_NotSuspended; + } + return (retVal); +} + +//***************************************************************************** +// +//! Gets State of the USB Connection. +//! +//! Returns the state of the USB connection, according to the state diagram +//! in Sec. 6 of \e "Programmer's Guide: MSP430 USB API Stack for CDC/PHDC/HID/MSC". +//! +//! \return Any of the following: +//! - \b ST_USB_DISCONNECTED +//! - \b ST_USB_CONNECTED_NO_ENUM +//! - \b ST_ENUM_IN_PROGRESS +//! - \b ST_ENUM_ACTIVE +//! - \b ST_ENUM_SUSPENDED +//! - \b ST_NOENUM_SUSPENDED, +//! - \b ST_ERROR. +// +//***************************************************************************** + +uint8_t USB_connectionState () +{ + //If no VBUS present + if (!(USBPWRCTL & USBBGVBV)){ + return (ST_USB_DISCONNECTED); + } + + //If VBUS present, but PUR is low + if ((USBPWRCTL & USBBGVBV) && (!(USBCNF & PUR_EN))){ + return (ST_USB_CONNECTED_NO_ENUM); + } + + //If VBUS present, PUR is high, and enumeration is complete, and not suspended + if ((USBPWRCTL & USBBGVBV) && (USBCNF & PUR_EN) + && (bEnumerationStatus == ENUMERATION_COMPLETE) + && (!(bFunctionSuspended == TRUE))){ + return (ST_ENUM_ACTIVE); + } + + //If VBUS present, PUR is high, and enumeration is NOT complete, and suspended + if ((USBPWRCTL & USBBGVBV) && (USBCNF & PUR_EN) + && (!(bEnumerationStatus == ENUMERATION_COMPLETE)) + && (bFunctionSuspended == TRUE)){ + return (ST_NOENUM_SUSPENDED); + } + + //If VBUS present, PUR is high, and enumeration is complete, and suspended + if ((USBPWRCTL & USBBGVBV) && (USBCNF & PUR_EN) + && (bEnumerationStatus == ENUMERATION_COMPLETE) + && (bFunctionSuspended == TRUE)){ + return (ST_ENUM_SUSPENDED); + } + + //If VBUS present, PUR is high, but no enumeration yet + if ((USBPWRCTL & USBBGVBV) && (USBCNF & PUR_EN) + && (!(bEnumerationStatus == ENUMERATION_COMPLETE))){ + return (ST_ENUM_IN_PROGRESS); + } + + return (ST_ERROR); +} + +// +//! \cond +// + +//---------------------------------------------------------------------------- + +uint8_t USB_suspend (void) +{ + bFunctionSuspended = TRUE; + USBKEYPID = 0x9628; //set KEY and PID to 0x9628 -> access to configuration registers enabled + USBCTL |= FRSTE; //Function Reset Connection Enable + USBIFG &= ~SUSRIFG; //clear interrupt flag + + USBPLLCTL &= ~UPLLEN; + + if (USB_DISABLE_XT_SUSPEND){ +#ifndef DRIVERLIB_LEGACY_MODE + UCS_XT2Off(); //disable XT2 +#else + UCS_XT2Off(UCS_BASE); //disable XT2 +#endif + } + + USBIE = RESRIE; //disable USB specific interrupts (setup, suspend, reset), enable resume. + //If the reset occured during device in suspend, the resume-interrupt will come, after - + //reset interrupt + USBKEYPID = 0x9600; //access to configuration registers disabled + + return (kUSB_succeed); +} + +//---------------------------------------------------------------------------- + +uint8_t USB_resume (void) +{ + USB_enable(); //enable PLL + + USBIFG &= ~(RESRIFG | SUSRIFG); //clear interrupt flags + USBIE = SETUPIE | RSTRIE | SUSRIE; //enable USB specific interrupts (setup, reset, suspend) + + bFunctionSuspended = FALSE; + return (kUSB_succeed); +} + +//---------------------------------------------------------------------------- + +void usbStallEndpoint0 (void) +{ + tEndPoint0DescriptorBlock.bIEPCNFG |= EPCNF_STALL; + tEndPoint0DescriptorBlock.bOEPCNFG |= EPCNF_STALL; +} + +//---------------------------------------------------------------------------- + +void usbClearOEP0ByteCount (void) +{ + tEndPoint0DescriptorBlock.bOEPBCNT = 0x00; +} + +//---------------------------------------------------------------------------- + +void usbStallOEP0 (void) +{ + //in standard USB request, there is not control write request with data stage + //control write, stall output endpoint 0 + //wLength should be 0 in all cases + tEndPoint0DescriptorBlock.bOEPCNFG |= EPCNF_STALL; +} + +//---------------------------------------------------------------------------- + +void usbSendNextPacketOnIEP0 (void) +{ + uint8_t bPacketSize,bIndex; + + //First check if there are bytes remaining to be transferred + if (wBytesRemainingOnIEP0 != NO_MORE_DATA){ + if (wBytesRemainingOnIEP0 > EP0_PACKET_SIZE){ + //More bytes are remaining than will fit in one packet + //there will be More IN Stage + bPacketSize = EP0_PACKET_SIZE; + wBytesRemainingOnIEP0 -= EP0_PACKET_SIZE; + bStatusAction = STATUS_ACTION_DATA_IN; + } else if (wBytesRemainingOnIEP0 < EP0_PACKET_SIZE){ + //The remaining data will fit in one packet. + //This case will properly handle wBytesRemainingOnIEP0 == 0 + bPacketSize = (uint8_t)wBytesRemainingOnIEP0; + wBytesRemainingOnIEP0 = NO_MORE_DATA; //No more data need to be Txed + bStatusAction = STATUS_ACTION_NOTHING; + } else { + bPacketSize = EP0_PACKET_SIZE; + if (bHostAskMoreDataThanAvailable == TRUE){ + wBytesRemainingOnIEP0 = 0; + bStatusAction = STATUS_ACTION_DATA_IN; + } else { + wBytesRemainingOnIEP0 = NO_MORE_DATA; + bStatusAction = STATUS_ACTION_NOTHING; + } + } + + for (bIndex = 0; bIndex < bPacketSize; bIndex++) + { + abIEP0Buffer[bIndex] = *pbIEP0Buffer; + pbIEP0Buffer++; + } + tEndPoint0DescriptorBlock.bIEPBCNT = bPacketSize; + } else { + bStatusAction = STATUS_ACTION_NOTHING; + } +} + +//---------------------------------------------------------------------------- + +void usbSendDataPacketOnEP0 (const uint8_t* pbBuffer) +{ + uint16_t wTemp; + + pbIEP0Buffer = pbBuffer; + wTemp = tSetupPacket.wLength; + + //Limit transfer size to wLength if needed + //this prevent USB device sending 'more than require' data back to host + if (wBytesRemainingOnIEP0 >= wTemp){ + wBytesRemainingOnIEP0 = wTemp; + bHostAskMoreDataThanAvailable = FALSE; + } else { + bHostAskMoreDataThanAvailable = TRUE; + } + usbSendNextPacketOnIEP0(); +} + +//---------------------------------------------------------------------------- +void usbReceiveNextPacketOnOEP0 (void) +{ + uint8_t bIndex,bByte; + + bByte = tEndPoint0DescriptorBlock.bOEPBCNT & EPBCNT_BYTECNT_MASK; + + if (wBytesRemainingOnOEP0 >= (uint16_t)bByte){ + for (bIndex = 0; bIndex < bByte; bIndex++) + { + *pbOEP0Buffer = abOEP0Buffer[bIndex]; + pbOEP0Buffer++; + } + wBytesRemainingOnOEP0 -= (uint16_t)bByte; + + //clear the NAK bit for next packet + if (wBytesRemainingOnOEP0 > 0){ + usbClearOEP0ByteCount(); + bStatusAction = STATUS_ACTION_DATA_OUT; + } else { + usbStallOEP0(); + bStatusAction = STATUS_ACTION_NOTHING; + } + } else { + usbStallOEP0(); + bStatusAction = STATUS_ACTION_NOTHING; + } +} + +//---------------------------------------------------------------------------- + +void usbReceiveDataPacketOnEP0 (uint8_t* pbBuffer) +{ + pbOEP0Buffer = pbBuffer; + + wBytesRemainingOnOEP0 = tSetupPacket.wLength; + bStatusAction = STATUS_ACTION_DATA_OUT; + + usbClearOEP0ByteCount(); +} + +//---------------------------------------------------------------------------- + +void usbSendZeroLengthPacketOnIEP0 (void) +{ + wBytesRemainingOnIEP0 = NO_MORE_DATA; + bStatusAction = STATUS_ACTION_NOTHING; + tEndPoint0DescriptorBlock.bIEPBCNT = 0x00; +} + +//---------------------------------------------------------------------------- + +uint8_t usbClearEndpointFeature (void) +{ + uint8_t bEndpointNumber; + + //EP is from EP1 to EP7 while C language start from 0 + bEndpointNumber = (tSetupPacket.wIndex & EP_DESC_ADDR_EP_NUM); + if (bEndpointNumber == 0x00){ + usbSendZeroLengthPacketOnIEP0(); + } else { + bEndpointNumber--; + if (bEndpointNumber < MAX_ENDPOINT_NUMBER){ + if ((tSetupPacket.wIndex & EP_DESC_ADDR_DIR_IN) == + EP_DESC_ADDR_DIR_IN){ +#ifdef _MSC_ + if (!MscState.bMscResetRequired){ +#endif + tInputEndPointDescriptorBlock[bEndpointNumber].bEPCNF &= + ~(EPCNF_STALL | EPCNF_TOGGLE ); +#ifdef _MSC_ + } +#endif +# ifdef _MSC_ + if (stUsbHandle[MSC0_INTFNUM].edb_Index == bEndpointNumber){ + MscReadControl.bCurrentBufferXY = 0; //Set current buffer to X + MscState.bMcsCommandSupported = TRUE; + } +# endif + } else { +#ifdef _MSC_ + if (!MscState.bMscResetRequired){ +#endif + tOutputEndPointDescriptorBlock[bEndpointNumber].bEPCNF &= + ~(EPCNF_STALL | EPCNF_TOGGLE ); +#ifdef _MSC_ + tOutputEndPointDescriptorBlock[bEndpointNumber].bEPBCTX = 0; + tOutputEndPointDescriptorBlock[bEndpointNumber].bEPBCTY = 0; + MscState.stallEndpoint = FALSE; +#endif +#ifdef _MSC_ + } +#endif +# ifdef _MSC_ + if (stUsbHandle[MSC0_INTFNUM].edb_Index == bEndpointNumber){ + MscWriteControl.bCurrentBufferXY = 0; //Set current buffer to X + MscState.bMcsCommandSupported = TRUE; + } +# endif + } + usbSendZeroLengthPacketOnIEP0(); + } + } + + return (FALSE); +} + +//---------------------------------------------------------------------------- + +uint8_t usbGetConfiguration (void) +{ + usbClearOEP0ByteCount(); //for status stage + wBytesRemainingOnIEP0 = 1; + usbSendDataPacketOnEP0((uint8_t*)&bConfigurationNumber); + + return (FALSE); +} + +//---------------------------------------------------------------------------- + +uint8_t usbGetDeviceDescriptor (void) +{ + usbClearOEP0ByteCount(); + wBytesRemainingOnIEP0 = SIZEOF_DEVICE_DESCRIPTOR; +#ifdef NON_COMPOSITE_MULTIPLE_INTERFACES + usbSendDataPacketOnEP0((uint8_t*)usbDeviceDescriptors[activeInterfaceIndex]); +#else + usbSendDataPacketOnEP0((uint8_t*)&abromDeviceDescriptor); +#endif + return (FALSE); +} + +//---------------------------------------------------------------------------- + +uint8_t usbGetConfigurationDescriptor (void) +{ + usbClearOEP0ByteCount(); +#ifdef NON_COMPOSITE_MULTIPLE_INTERFACES + wBytesRemainingOnIEP0 = usbConfigurationsSizes[activeInterfaceIndex]; + usbSendDataPacketOnEP0((uint8_t*)usbConfigurationDescriptors[activeInterfaceIndex]); +#else + wBytesRemainingOnIEP0 = sizeof(abromConfigurationDescriptorGroup); + usbSendDataPacketOnEP0((uint8_t*)&abromConfigurationDescriptorGroup); +#endif + + return (FALSE); +} + +//---------------------------------------------------------------------------- + +uint8_t usbGetStringDescriptor (void) +{ + uint16_t bIndex; + uint8_t bVal = (uint8_t)tSetupPacket.wValue; + + usbClearOEP0ByteCount(); //for status stage + if (bVal <= MAX_STRING_DESCRIPTOR_INDEX) { +#if (USB_STR_INDEX_SERNUM != 0) + if (bVal == 0x03){ + wBytesRemainingOnIEP0 = abramSerialStringDescriptor[0]; + usbSendDataPacketOnEP0((uint8_t*)&abramSerialStringDescriptor); + } else +#endif + { + bIndex = 0x00; + while (bVal-- > 0x00) bIndex += abromStringDescriptor[bIndex]; + wBytesRemainingOnIEP0 = abromStringDescriptor[bIndex]; + usbSendDataPacketOnEP0((uint8_t*)&abromStringDescriptor[bIndex]); + } + } + else { + usbStallEndpoint0(); + } + + return (FALSE); +} + +//---------------------------------------------------------------------------- + +uint8_t usbGetInterface (void) +{ + //not fully supported, return one byte, zero + usbClearOEP0ByteCount(); //for status stage + wBytesRemainingOnIEP0 = 0x02; + abUsbRequestReturnData[0] = 0x00; //changed to report alternative setting byte + abUsbRequestReturnData[1] = bInterfaceNumber; + usbSendDataPacketOnEP0((uint8_t*)&abUsbRequestReturnData[0]); + + return (FALSE); +} + +//---------------------------------------------------------------------------- + +uint8_t usbGetDeviceStatus (void) +{ +#ifdef NON_COMPOSITE_MULTIPLE_INTERFACES + if ((((struct abromConfigurationDescriptorGroup *) + usbConfigurationDescriptors[activeInterfaceIndex])-> + abromConfigurationDescriptorGenric.mattributes & + CFG_DESC_ATTR_SELF_POWERED) == CFG_DESC_ATTR_SELF_POWERED){ + abUsbRequestReturnData[0] = DEVICE_STATUS_SELF_POWER; + } +#else + if ((abromConfigurationDescriptorGroup.abromConfigurationDescriptorGenric. + mattributes & + CFG_DESC_ATTR_SELF_POWERED) == CFG_DESC_ATTR_SELF_POWERED){ + abUsbRequestReturnData[0] = DEVICE_STATUS_SELF_POWER; + } +#endif + if (bRemoteWakeup == ENABLE){ + abUsbRequestReturnData[0] |= DEVICE_STATUS_REMOTE_WAKEUP; + } + usbClearOEP0ByteCount(); //for status stage + + //Return self power status and remote wakeup status + wBytesRemainingOnIEP0 = 2; + usbSendDataPacketOnEP0((uint8_t*)&abUsbRequestReturnData[0]); + + return (FALSE); +} + +//---------------------------------------------------------------------------- + +uint8_t usbGetInterfaceStatus (void) +{ + //check bIndexL for index number (not supported) + usbClearOEP0ByteCount(); //for status stage + + //Return two zero bytes + wBytesRemainingOnIEP0 = 2; + abUsbRequestReturnData[0] = 0x00; //changed to support multiple interfaces + abUsbRequestReturnData[1] = bInterfaceNumber; + usbSendDataPacketOnEP0((uint8_t*)&abUsbRequestReturnData[0]); + + return (FALSE); +} + +//---------------------------------------------------------------------------- + +uint8_t usbGetEndpointStatus (void) +{ + uint8_t bEndpointNumber; + + //Endpoint number is bIndexL + bEndpointNumber = tSetupPacket.wIndex & EP_DESC_ADDR_EP_NUM; + if (bEndpointNumber == 0x00){ + if ((tSetupPacket.wIndex & EP_DESC_ADDR_DIR_IN) == + EP_DESC_ADDR_DIR_IN){ + //input endpoint 0 + abUsbRequestReturnData[0] = + (uint8_t)(tEndPoint0DescriptorBlock.bIEPCNFG & EPCNF_STALL); + } else { + //output endpoint 0 + abUsbRequestReturnData[0] = + (uint8_t)(tEndPoint0DescriptorBlock.bOEPCNFG & EPCNF_STALL); + } + abUsbRequestReturnData[0] = abUsbRequestReturnData[0] >> 3; //STALL is on bit 3 + usbClearOEP0ByteCount(); //for status stage + wBytesRemainingOnIEP0 = 0x02; + usbSendDataPacketOnEP0((uint8_t*)&abUsbRequestReturnData[0]); + } else { + bEndpointNumber--; + //EP is from EP1 to EP7 while C language start from 0 + //Firmware should NOT response if specified endpoint is not supported. (charpter 8) + if (bEndpointNumber < MAX_ENDPOINT_NUMBER){ + if (tSetupPacket.wIndex & EP_DESC_ADDR_DIR_IN){ + //input endpoint + abUsbRequestReturnData[0] = + (uint8_t)(tInputEndPointDescriptorBlock[bEndpointNumber]. + bEPCNF & + EPCNF_STALL); + } else { + //output endpoint + abUsbRequestReturnData[0] = + (uint8_t)(tOutputEndPointDescriptorBlock[bEndpointNumber]. + bEPCNF & + EPCNF_STALL); + } + } //no response if endpoint is not supported. + abUsbRequestReturnData[0] = abUsbRequestReturnData[0] >> 3; //STALL is on bit 3 + usbClearOEP0ByteCount(); + wBytesRemainingOnIEP0 = 0x02; + usbSendDataPacketOnEP0((uint8_t*)&abUsbRequestReturnData[0]); + } + + return (FALSE); +} + +//---------------------------------------------------------------------------- +uint8_t usbSetAddress (void) +{ + usbStallOEP0(); //control write without data stage + + //bValueL contains device address + if (tSetupPacket.wValue < 128){ + //hardware will update the address after status stage + //therefore, firmware can set the address now. + USBFUNADR = tSetupPacket.wValue; + usbSendZeroLengthPacketOnIEP0(); + } else { + usbStallEndpoint0(); + } + + return (FALSE); +} + +//---------------------------------------------------------------------------- + +uint8_t usbSetConfiguration (void) +{ + uint8_t bWakeUp = FALSE; + + usbStallOEP0(); //control write without data stage + + //configuration number is in bValueL + //change the code if more than one configuration is supported + bConfigurationNumber = tSetupPacket.wValue; + usbSendZeroLengthPacketOnIEP0(); + + if (bConfigurationNumber == 1){ + bEnumerationStatus = ENUMERATION_COMPLETE; //set device as enumerated + //perform enumeration complete event: + bWakeUp = USB_handleEnumCompleteEvent(); + } else { + bEnumerationStatus = 0; //device is not configured == config # is zero + } + + return (bWakeUp); +} + +//---------------------------------------------------------------------------- + +uint8_t usbClearDeviceFeature (void) +{ + //bValueL contains feature selector + if (tSetupPacket.wValue == FEATURE_REMOTE_WAKEUP){ + bRemoteWakeup = DISABLE; + usbSendZeroLengthPacketOnIEP0(); + } else { + usbStallEndpoint0(); + } + + return (FALSE); +} + +//---------------------------------------------------------------------------- + +uint8_t usbSetDeviceFeature (void) +{ + //bValueL contains feature selector + if (tSetupPacket.wValue == FEATURE_REMOTE_WAKEUP){ + bRemoteWakeup = ENABLE; + usbSendZeroLengthPacketOnIEP0(); + } else { + usbStallEndpoint0(); + } + + return (FALSE); +} + +//---------------------------------------------------------------------------- + +uint8_t usbSetEndpointFeature (void) +{ + uint8_t bEndpointNumber; + + //wValue contains feature selector + //bIndexL contains endpoint number + //Endpoint number is in low byte of wIndex + if (tSetupPacket.wValue == FEATURE_ENDPOINT_STALL){ + bEndpointNumber = tSetupPacket.wIndex & EP_DESC_ADDR_EP_NUM; + if (bEndpointNumber == 0x00){ + usbSendZeroLengthPacketOnIEP0(); //do nothing for endpoint 0 + } else { + bEndpointNumber--; + //Firmware should NOT response if specified endpoint is not supported. (charpter 8) + if (bEndpointNumber < MAX_ENDPOINT_NUMBER){ + if (tSetupPacket.wIndex & EP_DESC_ADDR_DIR_IN){ + //input endpoint + tInputEndPointDescriptorBlock[bEndpointNumber].bEPCNF |= + EPCNF_STALL; + } else { + //output endpoint + tOutputEndPointDescriptorBlock[bEndpointNumber].bEPCNF |= + EPCNF_STALL; + } + usbSendZeroLengthPacketOnIEP0(); + } //no response if endpoint is not supported. + } + } else { + usbStallEndpoint0(); + } + + return (FALSE); +} + +//---------------------------------------------------------------------------- + +uint8_t usbSetInterface (void) +{ + //bValueL contains alternative setting + //bIndexL contains interface number + //change code if more than one interface is supported + usbStallOEP0(); //control write without data stage + bInterfaceNumber = tSetupPacket.wIndex; +#ifdef _MSC_ + tInputEndPointDescriptorBlock[stUsbHandle[MSC0_INTFNUM].edb_Index].bEPCNF + &= ~(EPCNF_TOGGLE); + tOutputEndPointDescriptorBlock[stUsbHandle[MSC0_INTFNUM].edb_Index].bEPCNF + &= ~(EPCNF_TOGGLE); + MscReadControl.bCurrentBufferXY = 0; //Set current buffer to X + MscWriteControl.bCurrentBufferXY = 0; //Set current buffer to X +#endif + usbSendZeroLengthPacketOnIEP0(); + + return (FALSE); +} + +//---------------------------------------------------------------------------- + +uint8_t usbInvalidRequest (void) +{ + //check if setup overwrite is set + //if set, do nothing since we might decode it wrong + //setup packet buffer could be modified by hardware if another setup packet + //was sent while we are deocding setup packet + if ((USBIFG & STPOWIFG) == 0x00){ + usbStallEndpoint0(); + } + + return (FALSE); +} + +typedef uint8_t (*tpF)(void); + +uint8_t usbDecodeAndProcessUsbRequest (void) +{ + uint8_t bMask,bResult,bTemp; + const uint8_t* pbUsbRequestList; + uint8_t bWakeUp = FALSE; + ptDEVICE_REQUEST ptSetupPacket = &tSetupPacket; + uint8_t bRequestType,bRequest; + tpF lAddrOfFunction; + + //point to beginning of the matrix + pbUsbRequestList = (uint8_t*)&tUsbRequestList[0]; + + while (1) + { + bRequestType = *pbUsbRequestList++; + bRequest = *pbUsbRequestList++; + + if (((bRequestType == 0xff) && (bRequest == 0xff)) || + (tSetupPacket.bmRequestType == + (USB_REQ_TYPE_INPUT | USB_REQ_TYPE_VENDOR | + USB_REQ_TYPE_DEVICE)) || + (tSetupPacket.bmRequestType == + (USB_REQ_TYPE_OUTPUT | USB_REQ_TYPE_VENDOR | + USB_REQ_TYPE_DEVICE))){ + pbUsbRequestList -= 2; + break; + } + + if ((bRequestType == tSetupPacket.bmRequestType) && + (bRequest == tSetupPacket.bRequest)){ + //compare the first two + bResult = 0xc0; + bMask = 0x20; + //first two bytes matched, compare the rest + for (bTemp = 2; bTemp < 8; bTemp++) + { + if (*((uint8_t*)ptSetupPacket + bTemp) == *pbUsbRequestList){ + bResult |= bMask; + } + pbUsbRequestList++; + bMask = bMask >> 1; + } + //now we have the result + if ((*pbUsbRequestList & bResult) == *pbUsbRequestList){ + pbUsbRequestList -= 8; + break; + } else { + pbUsbRequestList += (sizeof(tDEVICE_REQUEST_COMPARE) - 8); + } + } else { + pbUsbRequestList += (sizeof(tDEVICE_REQUEST_COMPARE) - 2); + } + } + + //if another setup packet comes before we have the chance to process current + //setup request, we return here without processing the request + //this check is not necessary but still kept here to reduce response(or simulation) time + + if ((USBIFG & STPOWIFG) != 0x00){ + return (bWakeUp); + } + + //now we found the match and jump to the function accordingly. + lAddrOfFunction = + ((tDEVICE_REQUEST_COMPARE*)pbUsbRequestList)->pUsbFunction; + + //call function + bWakeUp = (*lAddrOfFunction)(); + + return (bWakeUp); +} + +uint16_t usbDisableInEndpointInterrupt(uint8_t edbIndex) +{ + uint16_t state; + state = USBIEPIE & (1 << (edbIndex + 1)); + USBIEPIE &= ~(1 << (edbIndex + 1)); + return (state); +} +void usbRestoreInEndpointInterrupt(uint16_t state) +{ + USBIEPIE |= state; +} +uint16_t usbDisableOutEndpointInterrupt(uint8_t edbIndex) +{ + uint16_t state; + state = USBOEPIE & (1 << (edbIndex + 1)); + USBOEPIE &= ~(1 << (edbIndex + 1)); + return (state); +} +void usbRestoreOutEndpointInterrupt(uint16_t state) +{ + USBOEPIE |= state; +} +#ifdef NON_COMPOSITE_MULTIPLE_INTERFACES + +uint8_t USB_switchInterface(uint8_t interfaceIndex) +{ + if (interfaceIndex < NONCOMP_NUM_USB_INTERFACES) { + activeInterfaceIndex = interfaceIndex; + return (TRUE); + } + else { + return (FALSE); + } +} + +#endif + +uint16_t USB_determineFreq(void){ + uint16_t freq; // calculated MCLK freq in kHz + uint16_t currentFLLN; // value of divider N taken from UCS registers + uint8_t currentSELM; // MCLK reference taken from UCS registers + uint8_t currentFLLREFDIV; // value of divider n taken from UCS registers + uint16_t currentFLLD; // value of prescalar D taken from UCS registers + uint16_t FLLRefFreq; + + currentSELM = (UCSCTL4_L & SELM_7); // get clock selection control register + + if(currentSELM<=4) // MCLK = DCO, DCOCLKDIV, XT1, VLO, or REFO. The last three aren't supported by the API. + { + FLLRefFreq = 33; // The reference is usually 32.768 kHz. + if((UCSCTL3_L & SELREF_7) > 0x50){ // Unless it's XT2 frequency + FLLRefFreq = USB_XT_FREQ_VALUE * 1000; + } + + // determine factors N and n + currentFLLN = UCSCTL2 & 0x03FF; // get FLL multiplier register + currentFLLN++; + if(currentSELM == SELM_3) // if MCLK is sourced by DCOCLK + { + // determine D + currentFLLD = UCSCTL2 & FLLD_7; // get FLLD register + currentFLLD >>= 12; + currentFLLN <<= currentFLLD; + } + + currentFLLREFDIV = UCSCTL3_L & FLLREFDIV_7; // get FLL reference divider register + if(currentFLLREFDIV>=4) + { + currentFLLREFDIV = FLLREFDIV_5; + } + freq = currentFLLN * (FLLRefFreq >> currentFLLREFDIV); + } + else + { + freq = USB_XT_FREQ_VALUE * 1000; + } + return freq >> (UCSCTL5_L & DIVM_7); // Divide by any divider present in DIVM +} + + +// +//! \endcond +// + +/*----------------------------------------------------------------------------+ + | End of source file | + +----------------------------------------------------------------------------*/ +/*------------------------ Nothing Below This Line --------------------------*/ +//Released_Version_4_10_02 diff --git a/source/USB_API/USB_Common/usb.h b/source/USB_API/USB_Common/usb.h new file mode 100644 index 0000000..60950d0 --- /dev/null +++ b/source/USB_API/USB_Common/usb.h @@ -0,0 +1,581 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +/* + * ======== usb.h ======== + */ +#ifndef _USB_H_ +#define _USB_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/*----------------------------------------------------------------------------+ + | Constant Definition | + +----------------------------------------------------------------------------*/ +#if defined(__TI_COMPILER_VERSION__) || defined(__GNUC__) +#define __no_init +#define __data16 +#endif + +#define FALSE 0 +#define TRUE 1 + +#define USB_RETURN_DATA_LENGTH 8 +#define SIZEOF_DEVICE_REQUEST 0x08 + +//Bit definitions for DEVICE_REQUEST.bmRequestType +//Bit 7: Data direction +#define USB_REQ_TYPE_OUTPUT 0x00 //0 = Host sending data to device +#define USB_REQ_TYPE_INPUT 0x80 //1 = Device sending data to host + +//Bit 6-5: Type +#define USB_REQ_TYPE_MASK 0x60 //Mask value for bits 6-5 +#define USB_REQ_TYPE_STANDARD 0x00 //00 = Standard USB request +#define USB_REQ_TYPE_CLASS 0x20 //01 = Class specific +#define USB_REQ_TYPE_VENDOR 0x40 //10 = Vendor specific + +//Bit 4-0: Recipient +#define USB_REQ_TYPE_RECIP_MASK 0x1F //Mask value for bits 4-0 +#define USB_REQ_TYPE_DEVICE 0x00 //00000 = Device +#define USB_REQ_TYPE_INTERFACE 0x01 //00001 = Interface +#define USB_REQ_TYPE_ENDPOINT 0x02 //00010 = Endpoint +#define USB_REQ_TYPE_OTHER 0x03 //00011 = Other + +//Values for DEVICE_REQUEST.bRequest +//Standard Device Requests +#define USB_REQ_GET_STATUS 0 +#define USB_REQ_CLEAR_FEATURE 1 +#define USB_REQ_SET_FEATURE 3 +#define USB_REQ_SET_ADDRESS 5 +#define USB_REQ_GET_DESCRIPTOR 6 +#define USB_REQ_SET_DESCRIPTOR 7 +#define USB_REQ_GET_CONFIGURATION 8 +#define USB_REQ_SET_CONFIGURATION 9 +#define USB_REQ_GET_INTERFACE 10 +#define USB_REQ_SET_INTERFACE 11 +#define USB_REQ_SYNCH_FRAME 12 + +//CDC CLASS Requests +#define USB_CDC_GET_LINE_CODING 0x21 +#define USB_CDC_SET_LINE_CODING 0x20 +#define USB_CDC_SET_CONTROL_LINE_STATE 0x22 + +//HID CLASS Requests +#define USB_HID_REQ 0x81 +#define USB_REQ_GET_REPORT 0x01 +#define USB_REQ_GET_IDLE 0x02 +#define USB_REQ_SET_REPORT 0x09 +#define USB_REQ_SET_IDLE 0x0A +#define USB_REQ_SET_PROTOCOL 0x0B +#define USB_REQ_GET_PROTOCOL 0x03 + +//MSC CLASS Requests +#define USB_MSC_RESET_BULK 0xFF +#define USB_MSC_GET_MAX_LUN 0xFE + +// PHDC CLASS Requests +#define USB_PHDC_GET_STATUS 0x00 + +//HID Values for HID Report Types (tSetup.bValueH) +#define USB_REQ_HID_INPUT 0x01 +#define USB_REQ_HID_OUTPUT 0x02 +#define USB_REQ_HID_FEATURE 0x03 + +#define USB_REQ_HID_BOOT_PROTOCOL 0x00 +#define USB_REQ_HID_REPORT_PROTOCOL 0x01 + + +//Descriptor Type Values +#define DESC_TYPE_DEVICE 1 //Device Descriptor (Type 1) +#define DESC_TYPE_CONFIG 2 //Configuration Descriptor (Type 2) +#define DESC_TYPE_STRING 3 //String Descriptor (Type 3) +#define DESC_TYPE_INTERFACE 4 //Interface Descriptor (Type 4) +#define DESC_TYPE_ENDPOINT 5 //Endpoint Descriptor (Type 5) +#define DESC_TYPE_DEVICE_QUALIFIER 6 //Endpoint Descriptor (Type 6) +#define DESC_TYPE_IAD 0x0B +#define DESC_TYPE_HUB 0x29 //Hub Descriptor (Type 6) +#define DESC_TYPE_HID 0x21 //HID Descriptor +#define DESC_TYPE_REPORT 0x22 //Report Descriptor +#define DESC_TYPE_PHYSICAL 0x23 //Physical Descriptor + +//Feature Selector Values +#define FEATURE_REMOTE_WAKEUP 1 //Remote wakeup (Type 1) +#define FEATURE_ENDPOINT_STALL 0 //Endpoint stall (Type 0) + +//Device Status Values +#define DEVICE_STATUS_REMOTE_WAKEUP 0x02 +#define DEVICE_STATUS_SELF_POWER 0x01 + +//Maximum descriptor size +#define MAX_DESC_SIZE 256 + +//DEVICE_DESCRIPTOR structure +#define SIZEOF_DEVICE_DESCRIPTOR 0x12 +#define OFFSET_DEVICE_DESCRIPTOR_VID_L 0x08 +#define OFFSET_DEVICE_DESCRIPTOR_VID_H 0x09 +#define OFFSET_DEVICE_DESCRIPTOR_PID_L 0x0A +#define OFFSET_DEVICE_DESCRIPTOR_PID_H 0x0B +#define OFFSET_CONFIG_DESCRIPTOR_POWER 0x07 +#define OFFSET_CONFIG_DESCRIPTOR_CURT 0x08 + +//CONFIG_DESCRIPTOR structure +#define SIZEOF_CONFIG_DESCRIPTOR 0x09 + +//HID DESCRIPTOR structure +//#define SIZEOF_HID_DESCRIPTOR 0x09 + +//Bit definitions for CONFIG_DESCRIPTOR.bmAttributes +#define CFG_DESC_ATTR_SELF_POWERED 0x40 //Bit 6: If set, device is self powered +#define CFG_DESC_ATTR_BUS_POWERED 0x80 //Bit 7: If set, device is bus powered +#define CFG_DESC_ATTR_REMOTE_WAKE 0x20 //Bit 5: If set, device supports remote wakeup + +//INTERFACE_DESCRIPTOR structure +#define SIZEOF_INTERFACE_DESCRIPTOR 0x09 + +//ENDPOINT_DESCRIPTOR structure +#define SIZEOF_ENDPOINT_DESCRIPTOR 0x07 + +//Bit definitions for EndpointDescriptor.EndpointAddr +#define EP_DESC_ADDR_EP_NUM 0x0F //Bit 3-0: Endpoint number +#define EP_DESC_ADDR_DIR_IN 0x80 //Bit 7: Direction of endpoint, 1/0 = In/Out + +//Bit definitions for EndpointDescriptor.EndpointFlags +#define EP_DESC_ATTR_TYPE_MASK 0x03 //Mask value for bits 1-0 +#define EP_DESC_ATTR_TYPE_CONT 0x00 //Bit 1-0: 00 = Endpoint does control transfers +#define EP_DESC_ATTR_TYPE_ISOC 0x01 //Bit 1-0: 01 = Endpoint does isochronous transfers +#define EP_DESC_ATTR_TYPE_BULK 0x02 //Bit 1-0: 10 = Endpoint does bulk transfers +#define EP_DESC_ATTR_TYPE_INT 0x03 //Bit 1-0: 11 = Endpoint does interrupt transfers + +//Definition to indicate valid/invalid data +#define DATA_VALID 1 +#define DATA_INVALID 0 + +typedef enum { + STATUS_ACTION_NOTHING, + STATUS_ACTION_DATA_IN, + STATUS_ACTION_DATA_OUT +} tSTATUS_ACTION_LIST; + + +typedef struct _tDEVICE_REQUEST { + uint8_t bmRequestType; //See bit definitions below + uint8_t bRequest; //See value definitions below + uint16_t wValue; //Meaning varies with request type + uint16_t wIndex; //Meaning varies with request type + uint16_t wLength; //Number of bytes of data to transfer +} tDEVICE_REQUEST, *ptDEVICE_REQUEST; + +extern __no_init tDEVICE_REQUEST __data16 tSetupPacket; +extern __no_init uint8_t __data16 abIEP0Buffer[]; +extern __no_init uint8_t __data16 abOEP0Buffer[]; +extern __no_init uint8_t __data16 pbXBufferAddressEp1[]; +extern __no_init uint8_t __data16 pbYBufferAddressEp1[]; +extern __no_init uint8_t __data16 pbXBufferAddressEp81[]; +extern __no_init uint8_t __data16 pbYBufferAddressEp81[]; +extern __no_init uint8_t __data16 pbXBufferAddressEp2[]; +extern __no_init uint8_t __data16 pbYBufferAddressEp2[]; +extern __no_init uint8_t __data16 pbXBufferAddressEp82[]; +extern __no_init uint8_t __data16 pbYBufferAddressEp82[]; + +extern __no_init uint8_t __data16 pbXBufferAddressEp3[]; +extern __no_init uint8_t __data16 pbYBufferAddressEp3[]; +extern __no_init uint8_t __data16 pbXBufferAddressEp83[]; +extern __no_init uint8_t __data16 pbYBufferAddressEp83[]; + +extern __no_init uint8_t __data16 pbXBufferAddressEp4[]; +extern __no_init uint8_t __data16 pbYBufferAddressEp4[]; +extern __no_init uint8_t __data16 pbXBufferAddressEp84[]; +extern __no_init uint8_t __data16 pbYBufferAddressEp84[]; + +extern __no_init uint8_t __data16 pbXBufferAddressEp5[]; +extern __no_init uint8_t __data16 pbYBufferAddressEp5[]; +extern __no_init uint8_t __data16 pbXBufferAddressEp85[]; +extern __no_init uint8_t __data16 pbYBufferAddressEp85[]; + + +extern __no_init uint8_t __data16 pbXBufferAddressEp6[]; +extern __no_init uint8_t __data16 pbYBufferAddressEp6[]; +extern __no_init uint8_t __data16 pbXBufferAddressEp86[]; +extern __no_init uint8_t __data16 pbYBufferAddressEp86[]; + +extern __no_init uint8_t __data16 pbXBufferAddressEp7[]; +extern __no_init uint8_t __data16 pbYBufferAddressEp7[]; +extern __no_init uint8_t __data16 pbXBufferAddressEp87[]; +extern __no_init uint8_t __data16 pbYBufferAddressEp87[]; + +extern uint16_t wBytesRemainingOnIEP0; +extern uint16_t wBytesRemainingOnOEP0; +extern uint8_t abUsbRequestReturnData[]; +extern uint8_t abUsbRequestIncomingData[]; +extern uint8_t bEnumerationStatus; +extern uint8_t bFunctionSuspended; + +//Function return values +#define kUSB_succeed 0x00 +#define kUSB_generalError 0x01 +#define kUSB_notEnabled 0x02 +//#define kUSB_VbusNotPresent 0x03 + +//return values USB_connectionInfo(), USB_connect() +#define kUSB_vbusPresent 0x01 +#define kUSB_busActive 0x02 //frame sync packets are being received +#define kUSB_ConnectNoVBUS 0x04 +#define kUSB_suspended 0x08 +#define kUSB_NotSuspended 0x10 +#define kUSB_Enumerated 0x20 +#define kUSB_purHigh 0x40 + +//Parameters for function USB_setEnabledEvents() +#define kUSB_clockFaultEvent 0x0001 +#define kUSB_VbusOnEvent 0x0002 +#define kUSB_VbusOffEvent 0x0004 +#define kUSB_UsbResetEvent 0x0008 +#define kUSB_UsbSuspendEvent 0x0010 +#define kUSB_UsbResumeEvent 0x0020 +#define kUSB_dataReceivedEvent 0x0040 +#define kUSB_sendCompletedEvent 0x0080 +#define kUSB_receiveCompletedEvent 0x0100 +#define kUSB_allUsbEvents 0x01FF + +//USB connection states +#define ST_USB_DISCONNECTED 0x80 +#define ST_USB_CONNECTED_NO_ENUM 0x81 +#define ST_ENUM_IN_PROGRESS 0x82 +#define ST_ENUM_ACTIVE 0x83 +#define ST_ENUM_SUSPENDED 0x84 +//#define ST_FAILED_ENUM 0x85 +#define ST_ERROR 0x86 +#define ST_NOENUM_SUSPENDED 0x87 + +#define ST_PHYS_DISCONNECTED ST_USB_DISCONNECTED +#define ST_PHYS_CONNECTED_NOENUM ST_USB_CONNECTED_NO_ENUM +#define ST_PHYS_CONNECTED_NOENUM_SUSP ST_NOENUM_SUSPENDED + +#define USB_CLOCKFAULT_EVENTMASK kUSB_clockFaultEvent +#define USB_VBUSON_EVENTMASK kUSB_VbusOnEvent +#define USB_VBUSOFF_EVENTMASK kUSB_VbusOffEvent +#define USB_USBRESET_EVENTMASK kUSB_UsbResetEvent +#define USB_USBSUSPEND_EVENTMASK kUSB_UsbSuspendEvent +#define USB_USBRESUME_EVENTMASK kUSB_UsbResumeEvent +#define USB_DATARECEIVED_EVENTMASK kUSB_dataReceivedEvent +#define USB_SENDCOMPLETED_EVENTMASK kUSB_sendCompletedEvent +#define USB_RECEIVECOMPLETED_EVENTMASK kUSB_receiveCompletedEvent +#define USB_ALL_EVENTMASK kUSB_allUsbEvents + +#define SUCCESS 0 +#define FAILURE 1 + +typedef struct _tDEVICE_REQUEST_COMPARE { + uint8_t bmRequestType; //See bit definitions below + uint8_t bRequest; //See value definitions below + uint8_t bValueL; //Meaning varies with request type + uint8_t bValueH; //Meaning varies with request type + uint8_t bIndexL; //Meaning varies with request type + uint8_t bIndexH; //Meaning varies with request type + uint8_t bLengthL; //Number of bytes of data to transfer (LSByte) + uint8_t bLengthH; //Number of bytes of data to transfer (MSByte) + uint8_t bCompareMask; //MSB is bRequest, if set 1, bRequest should be matched + uint8_t (*pUsbFunction)(void); //function pointer +} tDEVICE_REQUEST_COMPARE, *ptDEVICE_REQUEST_COMPARE; + +void usbStallInEndpoint(uint8_t); +void usbStallOutEndpoint(uint8_t); +void usbStallEndpoint(uint8_t); +void usbClearOEPByteCount(uint8_t); + + +/*---------------------------------------------------------------------------- + * These functions can be used in application + +----------------------------------------------------------------------------*/ + +/* + * MSP430 USB Module Management functions + */ + +/** + * Init the USB HW interface. + */ +uint8_t USB_init(void); + +/** + * Init the USB HW interface, enable events and connect + */ +uint8_t USB_setup(uint8_t connectEnable, uint8_t eventsEnable); + +/** + * Init and start the USB PLL. + */ +uint8_t USB_enable (); + +#ifdef USE_TIMER_FOR_RESUME +/** + * First phase of enable in the case where a timer is used to stabilize crystal and PLL + */ +uint8_t USB_enable_crystal (void); + +/** + * Second phase of enable in the case where a timer is used to stabilize crystal and PLL + */ +void USB_enable_PLL(void); + +/** + * Final phase of enable in the case where a timer is used to stabilize crystal and PLL + */ +void USB_enable_final(void); + +#endif +/** + * Disables the USB module and PLL. + */ +uint8_t USB_disable(void); + +/* + * Enables/disables various USB events. + */ +uint8_t USB_setEnabledEvents (uint16_t events); + +/* + * Returns which events are enabled and which are disabled. + */ +uint16_t USB_getEnabledEvents (); + +/* + * Instruct USB module to make itself available to the PC for connection, by pulling PUR high. + */ +uint8_t USB_connect (); + +/* + * Force a disconnect from the PC by pulling PUR low. + */ +uint8_t USB_disconnect (); + +/** + * Reset USB-SIE and global variables. + */ +uint8_t USB_reset (); + +/** + * Suspend USB. + */ +uint8_t USB_suspend(void); + +/** + * Resume USB. + */ +uint8_t USB_resume(void); + +/* + * Force a remote wakeup of the USB host. + * This method can be generated only if device supports + * remote wake-up feature in some of its configurations. + * The method wakes-up the USB bus only if wake-up feature is enabled by the host. + */ +uint8_t USB_forceRemoteWakeup (); + +/* + * Returns the status of the USB connection. + */ +uint8_t USB_connectionInfo (); + +/* + * Returns the state of the USB connection. + */ +uint8_t USB_connectionState (); + +#ifdef NON_COMPOSITE_MULTIPLE_INTERFACES +/* + * Switch to a different USB configuration. Used only for non-composite devices with multiple configuratons. + */ +uint8_t USB_switchInterface(uint8_t interfaceIndex); + +#endif + +/* + * Event-Handling routines + */ + +/* + * If this function gets executed, it's a sign that the output of the USB PLL has failed. + * returns TRUE to keep CPU awake + */ +uint8_t USB_handleClockEvent (); + +/* + * If this function gets executed, it indicates that a valid voltage has just been applied to the VBUS pin. + * returns TRUE to keep CPU awake + */ +uint8_t USB_handleVbusOnEvent (); + +/* + * If this function gets executed, it indicates that a valid voltage has just been removed from the VBUS pin. + * returns TRUE to keep CPU awake + */ +uint8_t USB_handleVbusOffEvent (); + +/* + * If this function gets executed, it indicates that the USB host has issued a USB reset event to the device. + * returns TRUE to keep CPU awake + */ +uint8_t USB_handleResetEvent (); + +/* + * If this function gets executed, it indicates that the USB host has chosen to suspend this device after a period of active + * operation. + * returns TRUE to keep CPU awake + */ +uint8_t USB_handleSuspendEvent (); + +/* + * If this function gets executed, it indicates that the USB host has chosen to resume this device after a period of suspended + * operation. + * returns TRUE to keep CPU awake + */ +uint8_t USB_handleResumeEvent (); + +/* + * If this function gets executed, it indicates that the USB host has enumerated this device : + * after host assigned the address to the device. + * returns TRUE to keep CPU awake + */ +uint8_t USB_handleEnumCompleteEvent (); + +#ifdef USE_TIMER_FOR_RESUME +/* + * When this function gets executed, it indicates that a USB_resume is in progress and the USB + * stack requires the application to use a timer to wait until the XT2 crystal has + * stabilized. See crystal specific datasheet for delay times. When the crystal has + * stabilized the application needs to call the function USB_enable_PLL() to allow + * resume to continue. + */ +void USB_handleCrystalStartedEvent(void); + +/* + * When this function gets executed, it indicates that a USB_resume is in progress and the USB + * stack requires the application to use a timer to wait until the USB PLL has + * stabilized. See device specific datasheet for PLL delay times. When the PLL has + * stabilized the application needs to call the function USB_enable_final() to allow resume + * to complete. + */ +void USB_handlePLLStartedEvent(void); + +#endif + +/** + * Send stall handshake for in- and out-endpoint0 (control pipe) + */ +void usbStallEndpoint0(void); + +/** + * Clear byte counter for endpoint0 (control pipe) + */ +void usbClearOEP0ByteCount(void); + +/** + * Send stall handshake for out-endpoint0 (control pipe) + */ +void usbStallOEP0(void); + +/** + * Send further data over control pipe if needed. + * Function is called from control-in IRQ. Do not call from user application + */ +void usbSendNextPacketOnIEP0(void); + +/** + * Send data over control pipe to host. + * Number of bytes to transmit should be set with + * global varible "wBytesRemainingOnIEP0" before function is called. + */ +void usbSendDataPacketOnEP0 (const uint8_t* pbBuffer); + +/** + * Receive further data from control pipe if needed. + * Function is called from control-out IRQ. Do not call from user application + */ +void usbReceiveNextPacketOnOEP0(void); + +/** + * Receive data from control pipe. + * Number of bytes to receive should be set with + * global varible "wBytesRemainingOnOEP0" before function is called. + */ +void usbReceiveDataPacketOnEP0 (uint8_t* pbBuffer); + +/** + * Send zero length packet on control pipe. + */ +void usbSendZeroLengthPacketOnIEP0(void); + +/*Send data to host.*/ +uint8_t MscSendData (const uint8_t* data, uint16_t size); + +/** + * Decode incoming usb setup packet and call corresponding function + * usbDecodeAndProcessUsbRequest is called from IRQ. Do not call from user application + */ +uint8_t usbDecodeAndProcessUsbRequest(void); +uint8_t usbClearEndpointFeature(void); +uint8_t usbGetConfiguration(void); +uint8_t usbGetDeviceDescriptor(void); +uint8_t usbGetConfigurationDescriptor(void); +uint8_t usbGetStringDescriptor(void); +uint8_t usbGetInterface(void); +uint8_t usbGetDeviceStatus(void); +uint8_t usbGetEndpointStatus(void); +uint8_t usbGetInterfaceStatus(void); +uint8_t usbSetAddress(void); +uint8_t usbSetConfiguration(void); +uint8_t usbClearDeviceFeature(void); +uint8_t usbSetDeviceFeature(void); +uint8_t usbSetEndpointFeature(void); +uint8_t usbSetInterface(void); +uint8_t usbInvalidRequest(void); +uint16_t usbDisableInEndpointInterrupt(uint8_t edbIndex); +void usbRestoreInEndpointInterrupt(uint16_t state); +uint16_t usbDisableOutEndpointInterrupt(uint8_t edbIndex); +void usbRestoreOutEndpointInterrupt(uint16_t state); + +#define ENUMERATION_COMPLETE 0x01 + +/*----------------------------------------------------------------------------+ + | End of header file | + +----------------------------------------------------------------------------*/ +#ifdef __cplusplus +} +#endif +#endif /* + * _USB_H + *------------------------ Nothing Below This Line -------------------------- + */ +//Released_Version_4_10_02 diff --git a/source/USB_API/USB_Common/usbdma.c b/source/USB_API/USB_Common/usbdma.c new file mode 100644 index 0000000..27139a5 --- /dev/null +++ b/source/USB_API/USB_Common/usbdma.c @@ -0,0 +1,152 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ + +// +//! \cond +// + +/* + * ======== dma.c ======== + */ +#include + +#include "driverlib.h" + +#include "../USB_Common/device.h" +#include "../USB_Common/defMSP430USB.h" +#include +#include + +#ifdef __REGISTER_MODEL__ +/* for IAR */ +# if __REGISTER_MODEL__ == __REGISTER_MODEL_REG20__ +# define __DMA_ACCESS_REG__ (void __data20 *) +# else +# define __DMA_ACCESS_REG__ (uint16_t) +# endif +#else +/* for CCS */ +# define __DMA_ACCESS_REG__ (__SFR_FARPTR)(uint32_t) +#endif + +//function pointers +void *(*USB_TX_memcpy)(void * dest, const void * source, size_t count); +void *(*USB_RX_memcpy)(void * dest, const void * source, size_t count); + +void * memcpyDMA0 (void * dest, const void * source, size_t count); +void * memcpyDMA1 (void * dest, const void * source, size_t count); +void * memcpyDMA2 (void * dest, const void * source, size_t count); + +//NOTE: this functin works only with data in the area <64k (small memory model) +void * memcpyV (void * dest, const void * source, size_t count) +{ + uint16_t i; + volatile uint8_t bTmp; + + for (i = 0; i < count; i++) + { + bTmp = *((uint8_t*)source + i); + *((uint8_t*)dest + i) = bTmp; + } + return (dest); +} + +void * memcpyDMA (void * dest, const void * source, size_t count) +{ + if (count == 0){ //do nothing if zero bytes to transfer + return (dest); + } + + //DMA4 workaround - disable DMA transfers during read-modify-write CPU + //operations +#ifndef DRIVERLIB_LEGACY_MODE + DMA_disableTransferDuringReadModifyWrite(); + DMA_setSrcAddress(USB_DMA_CHAN, (uint32_t)source, DMA_DIRECTION_INCREMENT); + DMA_setDstAddress(USB_DMA_CHAN, (uint32_t)dest, DMA_DIRECTION_INCREMENT); + //DMA4 workaround - re-enable DMA transfers during read-modify-write CPU + //operations + DMA_enableTransferDuringReadModifyWrite(); + DMA_setTransferSize(USB_DMA_CHAN, count); + DMA_enableTransfers(USB_DMA_CHAN); + DMA_startTransfer(USB_DMA_CHAN); + + while (DMA_getInterruptStatus(USB_DMA_CHAN) == DMA_INT_INACTIVE); + + DMA_disableTransfers(USB_DMA_CHAN); +#else + + DMA_disableTransferDuringReadModifyWrite(DMA_BASE); + DMA_setSrcAddress(DMA_BASE, USB_DMA_CHAN, (uint32_t)source, DMA_DIRECTION_INCREMENT); + DMA_setDstAddress(DMA_BASE, USB_DMA_CHAN, (uint32_t)dest, DMA_DIRECTION_INCREMENT); + //DMA4 workaround - re-enable DMA transfers during read-modify-write CPU + //operations + DMA_enableTransferDuringReadModifyWrite(DMA_BASE); + DMA_setTransferSize(DMA_BASE, USB_DMA_CHAN, count); + DMA_enableTransfers(DMA_BASE, USB_DMA_CHAN); + DMA_startTransfer(DMA_BASE, USB_DMA_CHAN); + + while (DMA_getInterruptStatus(DMA_BASE, USB_DMA_CHAN) == DMA_INT_INACTIVE); + + DMA_disableTransfers(DMA_BASE, USB_DMA_CHAN); +#endif + + return (dest); +} + +//this function inits the DMA +void USB_initMemcpy (void) +{ + USB_TX_memcpy = memcpyV; + USB_RX_memcpy = memcpyV; + + if (USB_DMA_CHAN != 0xFF) { +#ifndef DRIVERLIB_LEGACY_MODE + DMA_init (USB_DMA_CHAN, DMA_TRANSFER_BLOCK, 0, + DMA_TRIGGERSOURCE_0, DMA_SIZE_SRCBYTE_DSTBYTE, DMA_TRIGGER_HIGH); +#else + DMA_init (DMA_BASE, USB_DMA_CHAN, DMA_TRANSFER_BLOCK, 0, + DMA_TRIGGERSOURCE_0, DMA_SIZE_SRCBYTE_DSTBYTE, DMA_TRIGGER_HIGH); +#endif + USB_TX_memcpy = memcpyDMA; + USB_RX_memcpy = memcpyDMA; + } +} + +// +//! \endcond +// + +/*----------------------------------------------------------------------------+ + | End of source file | + +----------------------------------------------------------------------------*/ +/*------------------------ Nothing Below This Line --------------------------*/ +//Released_Version_4_10_02 diff --git a/source/USB_API/USB_HID_API/UsbHid.c b/source/USB_API/USB_HID_API/UsbHid.c new file mode 100644 index 0000000..ef66679 --- /dev/null +++ b/source/USB_API/USB_HID_API/UsbHid.c @@ -0,0 +1,1176 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +/** @file UsbHid.c + * @brief Contains APIs related to HID (Human Interface Device) device class. + */ +// +//! \cond +// + +/* + * ======== UsbHid.c ======== + */ +#include "../USB_Common/device.h" +#include "../USB_Common/defMSP430USB.h" +#include "../USB_Common/usb.h" //USB-specific Data Structures +#include "UsbHid.h" +#include +#include + +#ifdef _HID_ + +//function pointers +extern void *(*USB_TX_memcpy)(void * dest, const void * source, size_t count); +extern void *(*USB_RX_memcpy)(void * dest, const void * source, size_t count); + +//Local Macros +#define INTFNUM_OFFSET(X) (X - HID0_INTFNUM) //Get the HID offset + +extern uint8_t const report_len_input[HID_NUM_INTERFACES]; + +static struct _HidWrite { + uint16_t nHidBytesToSend; //holds counter of bytes to be sent + uint16_t nHidBytesToSendLeft; //holds counter how many bytes is still to be sent + const uint8_t* pHidBufferToSend; //holds the buffer with data to be sent + uint8_t bCurrentBufferXY; //indicates which buffer is to use next for for write into IN OUT endpoint +} HidWriteCtrl[HID_NUM_INTERFACES]; + +static struct _HidRead { + uint8_t *pUserBuffer; //holds the current position of user's receiving buffer. If NULL- no receiving + //operation started + uint8_t *pCurrentEpPos; //current positon to read of received data from curent EP + uint16_t nBytesToReceive; //holds how many bytes was requested by receiveData() to receive + uint16_t nBytesToReceiveLeft; //holds how many bytes is still requested by receiveData() to receive + uint8_t * pCT1; //holds current EPBCTxx register + uint8_t * pCT2; //holds next EPBCTxx register + uint8_t * pEP2; //holds addr of the next EP buffer + uint8_t nBytesInEp; //how many received bytes still available in current EP + uint8_t bCurrentBufferXY; //indicates which buffer is used by host to transmit data via OUT endpoint +} HidReadCtrl[HID_NUM_INTERFACES]; + +extern uint16_t wUsbEventMask; + +uint8_t hidProtocol[HID_NUM_INTERFACES] = {0}; +uint8_t hidIdleRate[HID_NUM_INTERFACES] = {0}; + +/*----------------------------------------------------------------------------+ + | Global Variables | + +----------------------------------------------------------------------------*/ + +extern __no_init tEDB __data16 tInputEndPointDescriptorBlock[]; +extern __no_init tEDB __data16 tOutputEndPointDescriptorBlock[]; + + +void HidCopyUsbToBuff (uint8_t* pEP, uint8_t* pCT, uint8_t); + +/*----------------------------------------------------------------------------+ + | Functions' implementatin | + +----------------------------------------------------------------------------*/ + +//resets internal HID data structure +void HidResetData () +{ + int16_t i; + + //indicates which buffer is used by host to transmit data via OUT endpoint3 - X buffer is first + //HidReadCtrl[intfIndex].bCurrentBufferXY = X_BUFFER; + + memset(&HidReadCtrl, 0, sizeof(HidReadCtrl)); + memset(&HidWriteCtrl, 0, sizeof(HidWriteCtrl)); + for (i = 0; i < HID_NUM_INTERFACES; i++){ + hidProtocol[i] = USB_REQ_HID_REPORT_PROTOCOL; + } +} + +// +//! \endcond +// + +//***************************************************************************** +// +//! Sends a Data Report to the Host. +//! +//! \param reportData is an array containing the report. +//! \param intfNum is which HID interface the data should be transmitted +//! over. +//! +//! Sends a pre-built report \b reportData to the host, on interface +//! \b intfNum. The report must be organized to reflect the format defined +//! by the report descriptor in descriptors.c. +//! +//! When the function returns \b kUSBHID_sendComplete, the data has been written to +//! the USB transmit buffers, and will be transferred to the host in the next +//! polling frame. If the function returns \b kUSBHID_busNotAvailable, then the bus +//! has either been disconnected or the device is suspended, allowing no reports +//! to be sent. If the function returns \b kUSBHID_intfBusyError, it means the USB +//! buffer for the interface has data in it, suggesting that the host has not +//! yet fetched the previously-loaded report. +//! +//! \return Any of the following: +//! - \b kUSBHID_sendComplete +//! - \b kUSBHID_busNotAvailable +//! - \b kUSBHID_intfBusyError +// +//***************************************************************************** + +uint8_t USBHID_sendReport (const uint8_t * reportData, uint8_t intfNum) +{ + uint8_t byte_count; + uint8_t * pEP1; + uint8_t * pCT1; + + uint8_t edbIndex; + + edbIndex = stUsbHandle[intfNum].edb_Index; + + //do not access USB memory if suspended (PLL off). It may produce BUS_ERROR + if ((bFunctionSuspended) || + (bEnumerationStatus != ENUMERATION_COMPLETE)){ + return (kUSBHID_busNotAvailable); + } + + if (HidWriteCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY == X_BUFFER){ + //this is the active EP buffer + pEP1 = (uint8_t*)stUsbHandle[intfNum].iep_X_Buffer; + pCT1 = &tInputEndPointDescriptorBlock[edbIndex].bEPBCTX; + } else { + //this is the active EP buffer + pEP1 = (uint8_t*)stUsbHandle[intfNum].iep_Y_Buffer; + pCT1 = &tInputEndPointDescriptorBlock[edbIndex].bEPBCTY; + } + + byte_count = report_len_input[INTFNUM_OFFSET(intfNum)]; + + if (*pCT1 & EPBCNT_NAK){ //if this EP is empty + USB_TX_memcpy(pEP1, reportData, byte_count); //copy data into IEP X or Y buffer + *pCT1 = byte_count; //Set counter for usb In-Transaction + HidWriteCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY = + (HidWriteCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY + 1) & 0x01; //switch buffer + return (kUSBHID_sendComplete); + } + return (kUSBHID_intfBusyError); +} + +//***************************************************************************** +// +//! Receives a Report from the Host into \b reportData. +//! +//! \param reportData is an array containing the report. +//! \param intfNum is the HID interface over which the data is to be +//! received. +//! +//! Receives a report from the host into \b reportData, on interface +//! \b intfNum. It is expected that the host will organize the report in the +//! format defined by the report descriptor in descriptors.c. +//! +//! When the function returns \b kUSBHID_receiveCompleted, the data has been +//! successfully copied from the USB receive buffers into \b reportData. If the +//! function returns \b kUSBHID_busNotAvailable, then the bus has either been +//! disconnected or the device is suspended, allowing no reports to be sent. If +//! the function returns \b kUSBHID_generalError, it means the call failed for +//! unspecified reasons. +//! +//! The call is intended to be called only when it is known that a report is in +//! the USB buffer. This means it is best called in response to the API calling +//! USBHID_handleDataReceived(), which indicates that a report has been received +//! for interface \b intfNum. +//! +//! \return Any of the following: +//! - \b kUSBHID_receiveCompleted +//! - \b kUSBHID_busNotAvailable +//! - \b kUSBHID_intfBusyError +// +//***************************************************************************** + +uint8_t USBHID_receiveReport (uint8_t * reportData, uint8_t intfNum) +{ + uint8_t ret = kUSBHID_generalError; + uint8_t nTmp1 = 0; + + uint8_t edbIndex; + + edbIndex = stUsbHandle[intfNum].edb_Index; + + //do not access USB memory if suspended (PLL off). It may produce BUS_ERROR + if ((bFunctionSuspended) || + (bEnumerationStatus != ENUMERATION_COMPLETE)){ + return (kUSBHID_busNotAvailable); + } + + if (HidReadCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY == X_BUFFER){ //this is current buffer + if (tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX & EPBCNT_NAK){ //this buffer has a valid data packet + //this is the active EP buffer + //pEP1 + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCurrentEpPos = + (uint8_t*)stUsbHandle[intfNum].oep_X_Buffer; + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 = + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX; + + //second EP buffer + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pEP2 = + (uint8_t*)stUsbHandle[intfNum].oep_Y_Buffer; + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2 = + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY; + nTmp1 = 1; //indicate that data is available + } + } else { //Y_BUFFER + if (tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY & EPBCNT_NAK){ + //this is the active EP buffer + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCurrentEpPos = + (uint8_t*)stUsbHandle[intfNum].oep_Y_Buffer; + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 = + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY; + + //second EP buffer + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pEP2 = + (uint8_t*)stUsbHandle[intfNum].oep_X_Buffer; + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2 = + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX; + nTmp1 = 1; //indicate that data is available + } + } + + if (nTmp1){ + //how many byte we can get from one endpoint buffer + nTmp1 = *HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1; + + if (nTmp1 & EPBCNT_NAK){ + nTmp1 = nTmp1 & 0x7f; //clear NAK bit + HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = nTmp1; //holds how many valid bytes in the EP buffer + + USB_RX_memcpy(reportData, HidReadCtrl[INTFNUM_OFFSET( + intfNum)].pCurrentEpPos, + nTmp1); + //memcpy(reportData, HidReadCtrl.pEP1, nTmp1); + HidReadCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY = + (HidReadCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY + + 1) & 0x01; + HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = 0; + *HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 = 0; //clear NAK, EP ready to receive data + + ret = kUSBHID_receiveCompleted; + } + } + return (ret); +} + +//***************************************************************************** +// +//! Initiates Sending of a User Buffer Over HID Interface. +//! +//! \param data is an array of data to be sent. +//! \param size is the number of bytes to be sent, starting from address +//! \b data. +//! \param intfNum is which data interface the \b data should be transmitted +//! over. +//! +//! Initiates sending of a user buffer over HID interface \b intfNum, of size +//! \b size and starting at address \b data. If \b size is larger than the +//! packet size, the function handles all packetization and buffer management. +//! \b size has no inherent upper limit (beyond being a 16-bit value). +//! +//! In most cases where a send operation is successfully started, the function +//! will return \b kUSBHID_sendStarted. A send operation is said to be underway. At +//! some point, either before or after the function returns, the send operation +//! will complete, barring any events that would preclude it. (Even if the +//! operation completes before the function returns, the return code will still +//! be \b kUSBHID_sendStarted.) +//! +//! If the bus is not connected when the function is called, the function +//! returns \b kUSBHID_busNotAvailable, and no operation is begun. If \b size is 0, +//! the function returns \b kUSBHID_generalError. If a previous send operation is +//! already underway for this data interface, the function returns with +//! \b kUSBHID_intfBusyError. +//! +//! USB includes low-level mechanisms that ensure valid transmission of data. +//! +//! See Sec. 7.2 of \e "Programmer's Guide: MSP430 USB API Stack for CDC/PHDC/HID/MSC" for a detailed discussion of +//! send operations. +//! +//! \return Any of the following: +//! - \b kUSBHID_sendStarted: a send operation was successfully +//! started. +//! - \b kUSBHID_intfBusyError: a previous send operation is +//! underway. +//! - \b kUSBHID_busNotAvailable: the bus is either suspended or +//! disconnected. +//! - \b kUSBHID_generalError: \b size was zero, or other +//! errorkUSBHID_receiveCompleted. +// +//***************************************************************************** + +uint8_t USBHID_sendData (const uint8_t* data, uint16_t size, uint8_t intfNum) +{ + uint16_t state; + uint8_t edbIndex; + + edbIndex = stUsbHandle[intfNum].edb_Index; + + if (size == 0){ + return (kUSBHID_generalError); + } + + state = usbDisableInEndpointInterrupt(edbIndex); + + //atomic operation - disable interrupts + + //do not access USB memory if suspended (PLL off). It may produce BUS_ERROR + if ((bFunctionSuspended) || + (bEnumerationStatus != ENUMERATION_COMPLETE)){ + //data can not be read because of USB suspended + usbRestoreInEndpointInterrupt(state); + return (kUSBHID_busNotAvailable); + } + + if (HidWriteCtrl[INTFNUM_OFFSET(intfNum)].nHidBytesToSendLeft != 0){ + //the USB still sends previous data, we have to wait + usbRestoreInEndpointInterrupt(state); + return (kUSBHID_intfBusyError); + } + + //This function generate the USB interrupt. The data will be sent out from interrupt + + HidWriteCtrl[INTFNUM_OFFSET(intfNum)].nHidBytesToSend = size; + HidWriteCtrl[INTFNUM_OFFSET(intfNum)].nHidBytesToSendLeft = size; + HidWriteCtrl[INTFNUM_OFFSET(intfNum)].pHidBufferToSend = data; + + //trigger Endpoint Interrupt - to start send operation + USBIEPIFG |= 1 << (edbIndex + 1); //IEPIFGx; + + usbRestoreInEndpointInterrupt(state); + + return (kUSBHID_sendStarted); +} + +// +//! \cond +// + +//this function is used only by USB interrupt +int16_t HidToHostFromBuffer (uint8_t intfNum) +{ + uint8_t byte_count, nTmp2; + uint8_t * pEP1; + uint8_t * pEP2; + uint8_t * pCT1; + uint8_t * pCT2; + uint8_t bWakeUp = FALSE; //per default we do not wake up after interrupt + + uint8_t edbIndex; + + edbIndex = stUsbHandle[intfNum].edb_Index; + + if (HidWriteCtrl[INTFNUM_OFFSET(intfNum)].nHidBytesToSendLeft == 0){ //do we have somtething to send? + HidWriteCtrl[INTFNUM_OFFSET(intfNum)].nHidBytesToSend = 0; + + //call event callback function + if (wUsbEventMask & kUSB_sendCompletedEvent){ + bWakeUp = USBHID_handleSendCompleted(intfNum); + } + return (bWakeUp); + } + + if (!(tInputEndPointDescriptorBlock[edbIndex].bEPCNF & EPCNF_TOGGLE)){ + //this is the active EP buffer + pEP1 = (uint8_t*)stUsbHandle[intfNum].iep_X_Buffer; + pCT1 = &tInputEndPointDescriptorBlock[edbIndex].bEPBCTX; + + //second EP buffer + pEP2 = (uint8_t*)stUsbHandle[intfNum].iep_Y_Buffer; + pCT2 = &tInputEndPointDescriptorBlock[edbIndex].bEPBCTY; + } else { + //this is the active EP buffer + pEP1 = (uint8_t*)stUsbHandle[intfNum].iep_Y_Buffer; + pCT1 = &tInputEndPointDescriptorBlock[edbIndex].bEPBCTY; + + //second EP buffer + pEP2 = (uint8_t*)stUsbHandle[intfNum].iep_X_Buffer; + pCT2 = &tInputEndPointDescriptorBlock[edbIndex].bEPBCTX; + } + + //how many byte we can send over one endpoint buffer + //2 bytes a reserved: [0] - HID Report Descriptor, [1] - count of valid bytes + byte_count = + (HidWriteCtrl[INTFNUM_OFFSET(intfNum)].nHidBytesToSendLeft > + EP_MAX_PACKET_SIZE - + 2) ? EP_MAX_PACKET_SIZE - + 2 : HidWriteCtrl[INTFNUM_OFFSET(intfNum)].nHidBytesToSendLeft; + nTmp2 = *pCT1; + + if (nTmp2 & EPBCNT_NAK){ + USB_TX_memcpy(pEP1 + 2, HidWriteCtrl[INTFNUM_OFFSET( + intfNum)].pHidBufferToSend, + byte_count); //copy data into IEP3 X or Y buffer + pEP1[0] = 0x3F; //set HID report descriptor: 0x3F + pEP1[1] = byte_count; //set HID report descriptor + + //64 bytes will be send: we use only one HID report descriptor + *pCT1 = 0x40; //Set counter for usb In-Transaction + + HidWriteCtrl[INTFNUM_OFFSET(intfNum)].nHidBytesToSendLeft -= byte_count; + HidWriteCtrl[INTFNUM_OFFSET(intfNum)].pHidBufferToSend += byte_count; //move buffer pointer + + //try to send data over second buffer + nTmp2 = *pCT2; + if ((HidWriteCtrl[INTFNUM_OFFSET(intfNum)].nHidBytesToSendLeft > 0) && //do we have more data to send? + (nTmp2 & EPBCNT_NAK)){ //if the second buffer is free? + //how many byte we can send over one endpoint buffer + byte_count = + (HidWriteCtrl[INTFNUM_OFFSET(intfNum)].nHidBytesToSendLeft > + EP_MAX_PACKET_SIZE - + 2) ? EP_MAX_PACKET_SIZE - + 2 : HidWriteCtrl[INTFNUM_OFFSET(intfNum)].nHidBytesToSendLeft; + + USB_TX_memcpy(pEP2 + 2, HidWriteCtrl[INTFNUM_OFFSET( + intfNum)].pHidBufferToSend, + byte_count); //copy data into IEP3 X or Y buffer + pEP2[0] = 0x3F; //set HID report descriptor: 0x3F + pEP2[1] = byte_count; //set byte count of valid data + + //64 bytes will be send: we use only one HID report descriptor + *pCT2 = 0x40; //Set counter for usb In-Transaction + + HidWriteCtrl[INTFNUM_OFFSET(intfNum)].nHidBytesToSendLeft -= + byte_count; + HidWriteCtrl[INTFNUM_OFFSET(intfNum)].pHidBufferToSend += + byte_count; //move buffer pointer + } + } + return (bWakeUp); +} + +// +//! \endcond +// + +//***************************************************************************** +// +//! Aborts an Active Send Operation on Data Interface. +//! +//! \param size is the number of bytes that were sent prior to the aboert +//! action. +//! \param intfNum is the data interface for which the send should be +//! aborted. +//! +//! Aborts an active send operation on data interface \b intfNum. Returns +//! the number of bytes that were sent prior to the abort, in \b size. +//! +//! An application may choose to call this function if sending failed, due to +//! factors such as: +//! - a surprise removal of the bus +//! - a USB suspend event +//! - any send operation that extends longer than desired//! +//! +//! \return \b kUSB_succeed +// +//***************************************************************************** + +uint8_t USBHID_abortSend (uint16_t* size, uint8_t intfNum) +{ + uint8_t edbIndex; + uint16_t state; + + edbIndex = stUsbHandle[intfNum].edb_Index; + + state = usbDisableInEndpointInterrupt(edbIndex); + + *size = + (HidWriteCtrl[INTFNUM_OFFSET(intfNum)].nHidBytesToSend - + HidWriteCtrl[INTFNUM_OFFSET(intfNum)].nHidBytesToSendLeft); + HidWriteCtrl[INTFNUM_OFFSET(intfNum)].nHidBytesToSend = 0; + HidWriteCtrl[INTFNUM_OFFSET(intfNum)].nHidBytesToSendLeft = 0; + + usbRestoreInEndpointInterrupt(state); + return (kUSB_succeed); +} + +// +//! \cond +// + +//This function copies data from OUT endpoint into user's buffer +//Arguments: +//pEP - pointer to EP to copy from +//pCT - pointer to pCT control reg +// +void HidCopyUsbToBuff (uint8_t* pEP, uint8_t* pCT,uint8_t intfNum) +{ + uint8_t nCount; + + //how many byte we can get from one endpoint buffer + nCount = + (HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft > + HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp) ? HidReadCtrl[ + INTFNUM_OFFSET(intfNum)].nBytesInEp : HidReadCtrl[INTFNUM_OFFSET( + intfNum)]. + nBytesToReceiveLeft; + + USB_RX_memcpy(HidReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer, pEP, nCount); //copy data from OEPx X or Y buffer + HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft -= nCount; + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer += nCount; //move buffer pointer + //to read rest of data next time from this place + + if (nCount == HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp){ //all bytes are copied from receive buffer? + //switch current buffer + HidReadCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY = + (HidReadCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY + 1) & 0x01; + + HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = 0; + + //clear NAK, EP ready to receive data + *pCT = 0; + } else { + HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp -= nCount; + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCurrentEpPos = pEP + nCount; + } +} + +// +//! \endcond +// + +//***************************************************************************** +// +//! Receives \b size Bytes Over HID Interface. +//! +//! \param data is an array to contain the data received. +//! \param size is the number of bytes to be received. +//! \param intfNum is which data interface to receive from. +//! +//! Receives \b size bytes over HID interface \b intfNum into memory starting at +//! address \b data. \b size has no inherent upper limit (beyond being a 16-bit +//! value). +//! +//! The function may return with \b kUSBHID_receiveStarted, indicating that a +//! receive operation is underway. The operation completes when \b size bytes +//! are received. The application should ensure that the data memory buffer be +//! available during the whole of the receive operation. +//! +//! The function may also return with \b kUSBHID_receiveCompleted. This means that +//! the receive operation was complete by the time the function returned. +//! +//! If the bus is not connected when the function is called, the function +//! returns \b kUSBHID_busNotAvailable, and no operation is begun. If \b size is 0, +//! the function returns \b kUSBHID_generalError. If a previous receive operation +//! is already underway for this data interface, the function returns +//! \b kUSBHID_intfBusyError. +//! +//! USB includes low-level mechanisms that ensure valid transmission of data. +//! +//! See Sec. 7.2 of \e "Programmer's Guide: MSP430 USB API Stack for CDC/PHDC/HID/MSC" for a detailed discussion of +//! receive operations. +//! +//! \return Any of the following: +//! - \b kUSBHID_receiveStarted: A receive operation has been +//! successfully started. +//! - \b kUSBHID_receiveCompleted: The receive operation is already +//! completed. +//! - \b kUSBHID_intfBusyError: a previous receive operation is +//! underway. +//! - \b kUSBHID_ busNotAvailable: the bus is either suspended or +//! disconnected. +//! - \b kUSBHID_generalError: size was zero, or other error. +// +//***************************************************************************** + +uint8_t USBHID_receiveData (uint8_t* data, uint16_t size, uint8_t intfNum) +{ + uint8_t nTmp1; + uint16_t state; + uint8_t edbIndex; + + edbIndex = stUsbHandle[intfNum].edb_Index; + + if ((size == 0) || //read size is 0 + (data == NULL)){ + return (kUSBHID_generalError); + } + + state = usbDisableOutEndpointInterrupt(edbIndex); + + //atomic operation - disable interrupts + + //do not access USB memory if suspended (PLL off). It may produce BUS_ERROR + if ((bFunctionSuspended) || + (bEnumerationStatus != ENUMERATION_COMPLETE)){ + usbRestoreOutEndpointInterrupt(state); + return (kUSBHID_busNotAvailable); + } + + if (HidReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer != NULL){ //receive process already started + usbRestoreOutEndpointInterrupt(state); + return (kUSBHID_receiveInProgress); + } + + HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceive = size; //bytes to receive + HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft = size; //left bytes to receive + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer = data; //set user receive buffer + + //read rest of data from buffer, if any + if (HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp > 0){ + //copy data from pEP-endpoint into User's buffer + HidCopyUsbToBuff(HidReadCtrl[INTFNUM_OFFSET( + intfNum)].pCurrentEpPos, + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1,intfNum); + + if (HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft == 0){ //the Receive opereation is completed + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer = NULL; //no more receiving pending + USBHID_handleReceiveCompleted(intfNum); //call event handler in interrupt context + usbRestoreOutEndpointInterrupt(state); + return (kUSBHID_receiveCompleted); //receive completed + } + + //check other EP buffer for data - exchange pCT1 with pCT2 + if (HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 == + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX){ + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 = + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY; + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCurrentEpPos = + (uint8_t*)stUsbHandle[intfNum].oep_Y_Buffer; + } else { + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 = + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX; + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCurrentEpPos = + (uint8_t*)stUsbHandle[intfNum].oep_X_Buffer; + } + nTmp1 = *HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1; + //try read data from second buffer + if (nTmp1 & EPBCNT_NAK){ //if the second buffer has received data? + nTmp1 = nTmp1 & 0x7f; //clear NAK bit + HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = + *(HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCurrentEpPos + 1); //holds how many valid bytes in the EP buffer + if (HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp > nTmp1 - 2){ + HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = nTmp1 - 2; + } + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCurrentEpPos += 2; //here starts user data + HidCopyUsbToBuff(HidReadCtrl[INTFNUM_OFFSET( + intfNum)].pCurrentEpPos, + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1,intfNum); + } + + if (HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft == 0){ //the Receive opereation is completed + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer = NULL; //no more receiving pending + if (wUsbEventMask & kUSB_receiveCompletedEvent){ + USBHID_handleReceiveCompleted(intfNum); //call event handler in interrupt context + } + usbRestoreOutEndpointInterrupt(state); + return (kUSBHID_receiveCompleted); //receive completed + } + } //read rest of data from buffer, if any + + //read 'fresh' data, if available + nTmp1 = 0; + if (HidReadCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY == X_BUFFER){ //this is current buffer + if (tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX & EPBCNT_NAK){ //this buffer has a valid data packet + //this is the active EP buffer + //pEP1 + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCurrentEpPos = + (uint8_t*)stUsbHandle[intfNum].oep_X_Buffer; + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 = + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX; + + //second EP buffer + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pEP2 = + (uint8_t*)stUsbHandle[intfNum].oep_Y_Buffer; + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2 = + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY; + nTmp1 = 1; //indicate that data is available + } + } else { //Y_BUFFER + if (tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY & EPBCNT_NAK){ + //this is the active EP buffer + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCurrentEpPos = + (uint8_t*)stUsbHandle[intfNum].oep_Y_Buffer; + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 = + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY; + + //second EP buffer + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pEP2 = + (uint8_t*)stUsbHandle[intfNum].oep_X_Buffer; + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2 = + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX; + nTmp1 = 1; //indicate that data is available + } + } + + if (nTmp1){ + //how many byte we can get from one endpoint buffer + nTmp1 = *HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1; + + if (nTmp1 & EPBCNT_NAK){ + nTmp1 = nTmp1 & 0x7f; //clear NAK bit + HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = + *(HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCurrentEpPos + 1); //holds how many valid bytes in the EP buffer + if (HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp > nTmp1 - 2){ + HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = nTmp1 - 2; + } + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCurrentEpPos += 2; //here starts user data + HidCopyUsbToBuff(HidReadCtrl[INTFNUM_OFFSET( + intfNum)].pCurrentEpPos, + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1,intfNum); + + nTmp1 = *HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2; + //try read data from second buffer + if ((HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft > + 0) && //do we have more data to receive? + (nTmp1 & EPBCNT_NAK)){ //if the second buffer has received data? + nTmp1 = nTmp1 & 0x7f; //clear NAK bit + HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = + *(HidReadCtrl[INTFNUM_OFFSET(intfNum)].pEP2 + 1); //holds how many valid bytes in the EP buffer + if (HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp > nTmp1 - + 2){ + HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = nTmp1 - 2; + } + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pEP2 += 2; //here starts user data + HidCopyUsbToBuff(HidReadCtrl[INTFNUM_OFFSET( + intfNum)].pEP2, + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2,intfNum); + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 = + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2; + } + } + } + + if (HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft == 0){ //the Receive opereation is completed + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer = NULL; //no more receiving pending + if (wUsbEventMask & kUSB_receiveCompletedEvent){ + USBHID_handleReceiveCompleted(intfNum); //call event handler in interrupt context + } + usbRestoreOutEndpointInterrupt(state); + return (kUSBHID_receiveCompleted); + } + + //interrupts enable + usbRestoreOutEndpointInterrupt(state); + return (kUSBHID_receiveStarted); +} + +// +//! \cond +// + +//this function is used only by USB interrupt. +//It fills user receiving buffer with received data +int16_t HidToBufferFromHost (uint8_t intfNum) +{ + uint8_t * pEP1; + uint8_t nTmp1; + uint8_t bWakeUp = FALSE; //per default we do not wake up after interrupt + + uint8_t edbIndex; + + edbIndex = stUsbHandle[intfNum].edb_Index; + + if (HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft == 0){ //do we have somtething to receive? + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer = NULL; //no more receiving pending + return (bWakeUp); + } + + //No data to receive... + if (!((tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX | + tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY) + & 0x80)){ + return (bWakeUp); + } + + if (HidReadCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY == X_BUFFER){ //X is current buffer + //this is the active EP buffer + pEP1 = (uint8_t*)stUsbHandle[intfNum].oep_X_Buffer; + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 = + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX; + + //second EP buffer + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pEP2 = + (uint8_t*)stUsbHandle[intfNum].oep_Y_Buffer; + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2 = + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY; + } else { + //this is the active EP buffer + pEP1 = (uint8_t*)stUsbHandle[intfNum].oep_Y_Buffer; + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 = + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY; + + //second EP buffer + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pEP2 = + (uint8_t*)stUsbHandle[intfNum].oep_X_Buffer; + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2 = + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX; + } + + //how many byte we can get from one endpoint buffer + nTmp1 = *HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1; + + if (nTmp1 & EPBCNT_NAK){ + nTmp1 = nTmp1 & 0x7f; //clear NAK bit + HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = *(pEP1 + 1); //holds how many valid bytes in the EP buffer + if (HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp > nTmp1 - 2){ + HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = nTmp1 - 2; + } + pEP1 += 2; //here starts user data + HidCopyUsbToBuff(pEP1, HidReadCtrl[INTFNUM_OFFSET( + intfNum)].pCT1,intfNum); + + nTmp1 = *HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2; + //try read data from second buffer + if ((HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft > 0) && //do we have more data to send? + (nTmp1 & EPBCNT_NAK)){ //if the second buffer has received data? + nTmp1 = nTmp1 & 0x7f; //clear NAK bit + HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = *(pEP1 + 1); //holds how many valid bytes in the EP buffer + if (HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp > nTmp1 - 2){ + HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = nTmp1 - 2; + } + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pEP2 += 2; //here starts user data + HidCopyUsbToBuff(HidReadCtrl[INTFNUM_OFFSET( + intfNum)].pEP2, + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2,intfNum); + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 = + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2; + } + } + + if (HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft == 0){ //the Receive opereation is completed + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer = NULL; //no more receiving pending + if (wUsbEventMask & kUSB_receiveCompletedEvent){ + bWakeUp = USBHID_handleReceiveCompleted(intfNum); + } + + if (HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp){ //Is not read data still available in the EP? + if (wUsbEventMask & kUSB_dataReceivedEvent){ + bWakeUp = USBHID_handleDataReceived(intfNum); + } + } + } + return (bWakeUp); +} + +//helper for USB interrupt handler +int16_t HidIsReceiveInProgress (uint8_t intfNum) +{ + return (HidReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer != NULL); +} + +// +//! \endcond +// + +//***************************************************************************** +// +//! Aborts an Active Recieve Operation on HID Interface. +//! +//! \param size is the number of bytes that were received and are waiting at the +//! assigned address. +//! \param intfNum is the data interface for which the receive should be +//! aborted. +//! +//! Aborts an active receive operation on HID interface \b intfNum. Returns the +//! number of bytes that were received and transferred to the data location +//! established for this receive operation. The data moved to the buffer up to +//! that time remains valid. +//! +//! An application may choose to call this function if it decides it no longer +//! wants to receive data from the USB host. It should be noted that if a +//! continuous stream of data is being received from the host, aborting the +//! operation is akin to pressing a "pause" button; the host will be NAK'ed +//! until another receive operation is opened. +//! +//! See Sec. 7.2 of \e "Programmer's Guide: MSP430 USB API Stack for CDC/PHDC/HID/MSC" for a detailed discussion of +//! receive operations. +//! +//! \return \b kUSB_succeed +// +//***************************************************************************** + +uint8_t USBHID_abortReceive (uint16_t* size, uint8_t intfNum) +{ + uint16_t state; + uint8_t edbIndex; + + edbIndex = stUsbHandle[intfNum].edb_Index; + state = usbDisableOutEndpointInterrupt(edbIndex); + + *size = 0; //set received bytes count to 0 + + //is receive operation underway? + if (HidReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer){ + //how many bytes are already received? + *size = HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceive - + HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft; + + HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = 0; + HidReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer = NULL; + HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft = 0; + } + + //restore interrupt status + usbRestoreOutEndpointInterrupt(state); + return (kUSB_succeed); +} + +//***************************************************************************** +// +//! Rejects Data Received from the Host. +//! +//! This function rejects data that has been received from the host, for +//! interface \b intfNum, that does not have an active receive operation underway. +//! It resides in the USB endpoint buffer and blocks further data until a +//! receive operation is opened, or until rejected. When this function is +//! called, the buffer for this interface is purged, and the data lost. This +//! frees the USB path to resume communication. +//! +//! See Sec. 7.2 of \e "Programmer's Guide: MSP430 USB API Stack for CDC/PHDC/HID/MSC" for a detailed discussion of +//! receive operations. +//! +//! \return \b kUSB_succeed +// +//***************************************************************************** + +uint8_t USBHID_rejectData (uint8_t intfNum) +{ + uint16_t state; + uint8_t edbIndex; + + edbIndex = stUsbHandle[intfNum].edb_Index; + + state = usbDisableOutEndpointInterrupt(edbIndex); + + //interrupts disable + + //do not access USB memory if suspended (PLL off). It may produce BUS_ERROR + if (bFunctionSuspended){ + usbRestoreOutEndpointInterrupt(state); + return (kUSBHID_busNotAvailable); + } + + //Is receive operation underway? + //- do not flush buffers if any operation still active. + if (!HidReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer){ + uint8_t tmp1 = tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX & + EPBCNT_NAK; + uint8_t tmp2 = tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY & + EPBCNT_NAK; + + if (tmp1 ^ tmp2){ //switch current buffer if any and only ONE of the + //buffers is full + //switch current buffer + HidReadCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY = + (HidReadCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY + + 1) & 0x01; + } + + tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX = 0; //flush buffer X + tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY = 0; //flush buffer Y + HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = 0; //indicates that no more data available in the EP + } + + usbRestoreOutEndpointInterrupt(state); + return (kUSB_succeed); +} + +//***************************************************************************** +// +//! Indicates the Status of the HID Interface. +//! +//! \param intfNum is the interface number for which the status is being +//! retrieved. +//! \param bytesSent If a send operation is underway, the number of bytes +//! that have been transferred to the host is returned in this location. If +//! no send operation is underway, this returns zero. +//! \param bytesReceived If a receive operation is underway, the number of +//! bytes that have been transferred to the assigned memory location is +//! returned in this location. If no receive operation is underway, this +//! returns zero. +//! +//! Indicates the status of the HID interface \b intfNum. If a send operation is +//! active for this interface, the function also returns the number of bytes +//! that have been transmitted to the host. If a receive operation is active for +//! this interface, the function also returns the number of bytes that have been +//! received from the host and are waiting at the assigned address. +//! +//! Because multiple flags can be returned, the possible values can be masked +//! together - for example, \b kUSBHID_waitingForSend + \b kUSBHID_dataWaiting. +//! +//! \return Any combination of the following: +//! - \b kUSBHID_waitingForSend: Indicates that a send operation is open +//! on this interface. +//! - \b kUSBHID_waitingForReceive: Indicates that a receive operation +//! is open on this interface. +//! - \b kUSBHID_dataWaiting: Indicates that data has been received from +//! the host for this interface, waiting in the USB receive buffers, +//! lacking an open receive operation to accept it. +//! - \b kUSBHID_busNotAvailable: Indicates that the bus is either +//! suspended or disconnected. Any operations that had previously +//! been underway are now aborted. +// +//***************************************************************************** + +uint8_t USBHID_intfStatus (uint8_t intfNum, uint16_t* bytesSent, uint16_t* bytesReceived) +{ + uint8_t ret = 0; + uint16_t stateIn, stateOut; + uint8_t edbIndex; + + *bytesSent = 0; + *bytesReceived = 0; + + edbIndex = stUsbHandle[intfNum].edb_Index; + + stateIn = usbDisableInEndpointInterrupt(edbIndex); + stateOut = usbDisableOutEndpointInterrupt(edbIndex); + + //Is send operation underway? + if (HidWriteCtrl[INTFNUM_OFFSET(intfNum)].nHidBytesToSendLeft != 0){ + ret |= kUSBHID_waitingForSend; + *bytesSent = HidWriteCtrl[INTFNUM_OFFSET(intfNum)].nHidBytesToSend - + HidWriteCtrl[INTFNUM_OFFSET(intfNum)].nHidBytesToSendLeft; + } + + //Is receive operation underway? + if (HidReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer != NULL){ + ret |= kUSBHID_waitingForReceive; + *bytesReceived = HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceive - + HidReadCtrl[INTFNUM_OFFSET(intfNum)]. + nBytesToReceiveLeft; + } else { //not receive operation started + //do not access USB memory if suspended (PLL off). + //It may produce BUS_ERROR + if (!bFunctionSuspended){ + if ((tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX & + EPBCNT_NAK) | //any of buffers has a valid data packet + (tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY & + EPBCNT_NAK)){ + ret |= kUSBHID_dataWaiting; + } + } + } + + if ((bFunctionSuspended) || + (bEnumerationStatus != ENUMERATION_COMPLETE)){ + //if suspended or not enumerated - report no other tasks pending + ret = kUSBHID_busNotAvailable; + } + + //restore interrupt status + usbRestoreInEndpointInterrupt(stateIn); + usbRestoreOutEndpointInterrupt(stateOut); + + return (ret); +} + +//***************************************************************************** +// +//! Returns the Number of Bytes Waiting in the USB Endpoint Buffer. +//! +//! \param intfNum is the data interface whose buffer is to be checked. +//! +//! Returns the number of bytes waiting in the USB endpoint buffer for +//! \b intfNum. A non-zero value generally means that no receive operation is +//! open by which these bytes can be copied to a user buffer. If the value is +//! non-zero, the application should either open a receive operation so that the +//! data can be moved out of the endpoint buffer, or the data should be rejected +//! (USBHID_rejectData()). +//! +//! \return The number of bytes waiting in this buffer. +// +//***************************************************************************** + +uint8_t USBHID_bytesInUSBBuffer (uint8_t intfNum) +{ + uint8_t bTmp1 = 0; + uint8_t bTmp2; + + uint8_t edbIndex; + uint16_t state; + + + edbIndex = stUsbHandle[intfNum].edb_Index; + + //interrupts disable + state = usbDisableOutEndpointInterrupt(edbIndex); + + if ((bFunctionSuspended) || + (bEnumerationStatus != ENUMERATION_COMPLETE)){ + //if suspended or not enumerated - report 0 bytes available + usbRestoreOutEndpointInterrupt(state); + return (0); + } + + if (HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp > 0){ //If a RX operation is underway, part of data may + //was read of the OEP buffer + bTmp1 = HidReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp; + if (*HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2 & EPBCNT_NAK){ //the next buffer has a valid data packet + bTmp2 = *(HidReadCtrl[INTFNUM_OFFSET(intfNum)].pEP2 + 1); //holds how many valid bytes in the EP buffer + if (bTmp2 > + (*HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2 & 0x7F) - 2){ //check if all data received correctly + bTmp1 += + (*HidReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2 & 0x7F) - 2; + } else { + bTmp1 += bTmp2; + } + } + } else { + if (tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX & EPBCNT_NAK){ //this buffer has a valid data packet + bTmp2 = tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX & 0x7F; + bTmp1 = *((uint8_t*)stUsbHandle[intfNum].oep_X_Buffer + 1); + if (bTmp2 - 2 < bTmp1){ //check if the count (second byte) is valid + bTmp1 = bTmp2 - 2; + } + } + if (tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY & EPBCNT_NAK){ //this buffer has a valid data packet + bTmp2 = tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY & 0x7F; + if (bTmp2 - 2 > *((uint8_t*)stUsbHandle[intfNum].oep_Y_Buffer + 1)){ //check if the count (second byte) is valid + bTmp1 += *((uint8_t*)stUsbHandle[intfNum].oep_Y_Buffer + 1); + } else { + bTmp1 += bTmp2 - 2; + } + } + } + + //interrupts enable + usbRestoreOutEndpointInterrupt(state); + return (bTmp1); +} + +// +//! \cond +// + +#endif //ifdef _HID_ + +// +//! \endcond +// + +/*----------------------------------------------------------------------------+ + | End of source file | + +----------------------------------------------------------------------------*/ +/*------------------------ Nothing Below This Line --------------------------*/ +//Released_Version_4_10_02 diff --git a/source/USB_API/USB_HID_API/UsbHid.h b/source/USB_API/USB_HID_API/UsbHid.h new file mode 100644 index 0000000..e182634 --- /dev/null +++ b/source/USB_API/USB_HID_API/UsbHid.h @@ -0,0 +1,204 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +/* + * ======== UsbHid.h ======== + */ +#include + +#ifndef _UsbHid_H_ +#define _UsbHid_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +#define kUSBHID_sendStarted 0x01 +#define kUSBHID_sendComplete 0x02 +#define kUSBHID_intfBusyError 0x03 +#define kUSBHID_receiveStarted 0x04 +#define kUSBHID_receiveCompleted 0x05 +#define kUSBHID_receiveInProgress 0x06 +#define kUSBHID_generalError 0x07 +#define kUSBHID_busNotAvailable 0x08 + +#define HID_BOOT_PROTOCOL 0x00 +#define HID_REPORT_PROTOCOL 0x01 + +#define USBHID_handleGetReport USBHID_handleEP0GetReport +#define USBHID_handleSetReport USBHID_handleEP0SetReport +#define USBHID_handleSetReportDataAvailable USBHID_handleEP0SetReportDataAvailable +#define USBHID_handleSetReportDataAvailable USBHID_handleEP0SetReportDataAvailable + +/*---------------------------------------------------------------------------- + * These functions can be used in application + +----------------------------------------------------------------------------*/ + +/* + * Sends a pre-built report reportData to the host. + * Returns: kUSBHID_sendComplete + * kUSBHID_intfBusyError + * kUSBHID_busSuspended + */ +uint8_t USBHID_sendReport (const uint8_t * reportData, uint8_t intfNum); + +/* + * Receives report reportData from the host. + * Return: kUSBHID_receiveCompleted + * kUSBHID_generalError + * kUSBHID_busSuspended + */ +uint8_t USBHID_receiveReport (uint8_t * reportData, uint8_t intfNum); + +/* + * Sends data over interface intfNum, of size size and starting at address data. + * Returns: kUSBHID_sendStarted + * kUSBHID_sendComplete + * kUSBHID_intfBusyError + */ +uint8_t USBHID_sendData (const uint8_t* data, uint16_t size, uint8_t intfNum); + +/* + * Receives data over interface intfNum, of size size, into memory starting at address data. + */ +uint8_t USBHID_receiveData (uint8_t* data, uint16_t size, uint8_t intfNum); + +/* + * Aborts an active receive operation on interface intfNum. + * size: the number of bytes that were received and transferred + * to the data location established for this receive operation. + */ +uint8_t USBHID_abortReceive (uint16_t* size, uint8_t intfNum); + + +#define kUSBHID_noDataWaiting 1 //returned by USBHID_rejectData() if no data pending + +/* + * This function rejects payload data that has been received from the host. + */ +uint8_t USBHID_rejectData (uint8_t intfNum); + +/* + * Aborts an active send operation on interface intfNum. Returns the number of bytes that were sent prior to the abort, in size. + */ +uint8_t USBHID_abortSend (uint16_t* size, uint8_t intfNum); + + +#define kUSBHID_waitingForSend 0x01 +#define kUSBHID_waitingForReceive 0x02 +#define kUSBHID_dataWaiting 0x04 +#define kUSBHID_busNotAvailable 0x08 +#define kUSB_allHidEvents 0xFF +/* + * This function indicates the status of the interface intfNum. + * If a send operation is active for this interface, + * the function also returns the number of bytes that have been transmitted to the host. + * If a receiver operation is active for this interface, the function also returns + * the number of bytes that have been received from the host and are waiting at the assigned address. + * + * returns kUSBHID_waitingForSend (indicates that a call to USBHID_SendData() + * has been made, for which data transfer has not been completed) + * + * returns kUSBHID_waitingForReceive (indicates that a receive operation + * has been initiated, but not all data has yet been received) + * + * returns kUSBHID_dataWaiting (indicates that data has been received + * from the host, waiting in the USB receive buffers) + */ +uint8_t USBHID_intfStatus (uint8_t intfNum, uint16_t* bytesSent, uint16_t* bytesReceived); + +/* + * Returns how many bytes are in the buffer are received and ready to be read. + */ +uint8_t USBHID_bytesInUSBBuffer (uint8_t intfNum); + +/*---------------------------------------------------------------------------- + * Event-Handling routines + +----------------------------------------------------------------------------*/ + +/* + * This event indicates that data has been received for port port, but no data receive operation is underway. + * returns TRUE to keep CPU awake + */ +uint8_t USBHID_handleDataReceived (uint8_t intfNum); + +/* + * This event indicates that a send operation on port port has just been completed. + * returns TRUE to keep CPU awake + */ +uint8_t USBHID_handleSendCompleted (uint8_t intfNum); + +/* + * This event indicates that a receive operation on port port has just been completed. + * returns TRUE to keep CPU awake + */ +uint8_t USBHID_handleReceiveCompleted (uint8_t intfNum); + +/* + * This event indicates that a Set_Protocol request was received from the host + * The application may maintain separate reports for boot and report protocols. + * The protocol field is either HID_BOOT_PROTOCOL or + * HID_REPORT_PROTOCOL + */ +uint8_t USBHID_handleBootProtocol (uint8_t protocol, uint8_t intfnum); + +/* + * This event indicates that a Set_Report request was received from the host + * The application needs to supply a buffer to retrieve the report data that will be sent + * as part of this request. This handler is passed the reportType, reportId, the length of data + * phase as well as the interface number. + */ +uint8_t *USBHID_handleEP0SetReport (uint8_t reportType, uint8_t reportId, + uint16_t requestedLength, + uint8_t intfnum); +/* + * This event indicates that data as part of Set_Report request was received from the host + * Tha application can return TRUE to wake up the CPU. If the application supplied a buffer + * as part of USBHID_handleEP0SetReport, then this buffer will contain the Set Report data. + */ +uint8_t USBHID_handleEP0SetReportDataAvailable (uint8_t intfnum); +/* + * This event indicates that a Get_Report request was received from the host + * The application can supply a buffer of data that will be sent to the host. + * This handler is passed the reportType, reportId, the requested length as + * well as the interface number. + */ +uint8_t *USBHID_handleEP0GetReport (uint8_t reportType, uint8_t reportId, + uint16_t requestedLength, + uint8_t intfnum); + +#ifdef __cplusplus +} +#endif +#endif //_UsbHid_H_ +//Released_Version_4_10_02 diff --git a/source/USB_API/USB_HID_API/UsbHidReq.c b/source/USB_API/USB_HID_API/UsbHidReq.c new file mode 100644 index 0000000..996c36a --- /dev/null +++ b/source/USB_API/USB_HID_API/UsbHidReq.c @@ -0,0 +1,194 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ + +// +//! \cond +// + +/* + * ======== UsbHidReq.c ======== + */ +#include "../USB_Common/device.h" +#include "../USB_Common/defMSP430USB.h" +#include "../USB_Common/usb.h" //USB-specific Data Structures +#include "UsbHid.h" +#include "UsbHidReq.h" +#include + +#ifdef _HID_ + +void usbClearOEP0ByteCount (void); +void usbSendDataPacketOnEP0 (const uint8_t* pbBuffer); +void usbReceiveDataPacketOnEP0 (uint8_t* pbBuffer); + +extern const uint16_t report_desc_size[HID_NUM_INTERFACES]; +extern const uint8_t* report_desc[HID_NUM_INTERFACES]; //KLQ +extern uint8_t hidProtocol[]; +extern uint8_t hidIdleRate[]; +extern uint16_t wUsbHidEventMask; + +#ifdef NON_COMPOSITE_MULTIPLE_INTERFACES +extern const struct abromConfigurationDescriptorGroupHID abromConfigurationDescriptorGroupHID; +#endif + +//Local Macros +#define INTERFACE_OFFSET(X) (X - HID0_REPORT_INTERFACE) //Get the HID offset + +uint8_t usbGetHidDescriptor (void) +{ + usbClearOEP0ByteCount(); + wBytesRemainingOnIEP0 = 9; +#ifdef NON_COMPOSITE_MULTIPLE_INTERFACES + usbSendDataPacketOnEP0((uint8_t*)&abromConfigurationDescriptorGroupHID.stHid[ + INTERFACE_OFFSET(tSetupPacket.wIndex)].blength_hid_descriptor); +#else + usbSendDataPacketOnEP0((uint8_t*)&abromConfigurationDescriptorGroup.stHid[ + INTERFACE_OFFSET(tSetupPacket.wIndex)].blength_hid_descriptor); +#endif + return (FALSE); +} + +uint8_t usbGetReportDescriptor (void) +{ + wBytesRemainingOnIEP0 = + report_desc_size[INTERFACE_OFFSET(tSetupPacket.wIndex)]; + usbSendDataPacketOnEP0(report_desc[INTERFACE_OFFSET(tSetupPacket.wIndex)]); + + return (FALSE); +} + +//---------------------------------------------------------------------------- + +uint8_t usbSetReport (void) +{ + uint8_t *buffer; + + //tSetupPacket.wValue = USB_REQ_HID_FEATURE or USB_REQ_HID_INPUT + buffer = USBHID_handleEP0SetReport(tSetupPacket.wValue >> 8, tSetupPacket.wValue, + tSetupPacket.wLength, + tSetupPacket.wIndex); + + //What if buffer is NULL? + if (buffer == 0){ + usbReceiveDataPacketOnEP0((uint8_t*)&abUsbRequestIncomingData); + } else { + usbReceiveDataPacketOnEP0((uint8_t*)buffer); //receive data over EP0 from Host + } + + return (FALSE); +} + +//---------------------------------------------------------------------------- + +uint8_t usbGetReport (void) +{ + uint8_t *buffer; + + //tSetupPacket.wValue = USB_REQ_HID_FEATURE or USB_REQ_HID_INPUT + buffer = USBHID_handleEP0GetReport(tSetupPacket.wValue >> 8, tSetupPacket.wValue, + tSetupPacket.wLength, + tSetupPacket.wIndex); + if (buffer != 0){ + usbSendDataPacketOnEP0((uint8_t*)buffer); + } + + return (FALSE); +} + +uint8_t usbSetProtocol (void) +{ + uint8_t bWakeUp = FALSE; + + hidProtocol[INTERFACE_OFFSET(tSetupPacket.wIndex)] = + (uint8_t)tSetupPacket.wValue; + //tSetupPacket.wValue = USB_REQ_HID_BOOT_PROTOCOL or USB_REQ_HID_REPORT_PROTOCOL + bWakeUp = USBHID_handleBootProtocol((uint8_t)tSetupPacket.wValue, + tSetupPacket.wIndex); + usbSendZeroLengthPacketOnIEP0(); + + return (bWakeUp); +} + +//---------------------------------------------------------------------------- + +uint8_t usbGetProtocol (void) +{ + usbSendDataPacketOnEP0(&hidProtocol[INTERFACE_OFFSET(tSetupPacket.wIndex)]); + + return (FALSE); +} + +//---------------------------------------------------------------------------- + +uint8_t usbSetIdle (void) +{ + if (hidProtocol[INTERFACE_OFFSET(tSetupPacket.wIndex)] == + USB_REQ_HID_BOOT_PROTOCOL){ + hidIdleRate[INTERFACE_OFFSET(tSetupPacket.wIndex)] = + tSetupPacket.wValue >> 8; + usbSendZeroLengthPacketOnIEP0(); + } else { + usbInvalidRequest(); + } + + return (FALSE); +} + +//---------------------------------------------------------------------------- + +uint8_t usbGetIdle (void) +{ + if (hidProtocol[INTERFACE_OFFSET(tSetupPacket.wIndex)] == + USB_REQ_HID_BOOT_PROTOCOL){ + usbSendDataPacketOnEP0(&hidIdleRate[INTERFACE_OFFSET(tSetupPacket. + wIndex)]); + } else { + usbInvalidRequest(); + } + + return (FALSE); +} + + +//---------------------------------------------------------------------------- + +#endif //_HID_ + +// +//! \endcond +// + +/*----------------------------------------------------------------------------+ + | End of source file | + +----------------------------------------------------------------------------*/ +/*------------------------ Nothing Below This Line --------------------------*/ +//Released_Version_4_10_02 diff --git a/source/USB_API/USB_HID_API/UsbHidReq.h b/source/USB_API/USB_HID_API/UsbHidReq.h new file mode 100644 index 0000000..2b0d37e --- /dev/null +++ b/source/USB_API/USB_HID_API/UsbHidReq.h @@ -0,0 +1,85 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +/* + * ======== UsbHidReq.h ======== + */ + +#include + +#ifndef _UsbHidReq_H_ +#define _UsbHidReq_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** + * Return Hid descriptor to host over control endpoint + */ +uint8_t usbGetHidDescriptor(void); +/** + * Return HID report descriptor to host over control endpoint + */ +uint8_t usbGetReportDescriptor(void); +/** + * Receive Set_Report from host over control endpoint + */ +uint8_t usbSetReport(void); +/** + * Process Get_Report request from host over control endpoint + */ +uint8_t usbGetReport(void); +/** + * Receive Set_Idle from host over control endpoint + */ +uint8_t usbSetIdle(void); +/** + * Process Get_Idle request from host over control endpoint + */ +uint8_t usbGetIdle(void); +/** + * Receive Set_Protocol from host over control endpoint + */ +uint8_t usbSetProtocol(void); +/** + * Process Get_Protocol request from host over control endpoint + */ +uint8_t usbGetProtocol(void); + + +#ifdef __cplusplus +} +#endif +#endif //_UsbHidReq_H_ +//Released_Version_4_10_02 diff --git a/source/USB_API/USB_MSC_API/UsbMsc.h b/source/USB_API/USB_MSC_API/UsbMsc.h new file mode 100644 index 0000000..5694b11 --- /dev/null +++ b/source/USB_API/USB_MSC_API/UsbMsc.h @@ -0,0 +1,75 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +/* + * ======== UsbMsc.h ======== + */ +#include + +#ifndef _USB_MSC_H_ +#define _USB_MSC_H_ + +#include "UsbMscScsi.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/*Return values of getState() and USBMSC_poll() API */ +#define kUSBMSC_idle 0 +#define kUSBMSC_readInProgress 1 +#define kUSBMSC_writeInProgress 2 +#define kUSBMSC_cmdBeingProcessed 3 +#define kUSBMSC_okToSleep 4 +#define kUSBMSC_processBuffer 5 + +/*----------------------------------------------------------------------------+ + | Function Prototypes | + +----------------------------------------------------------------------------*/ +/*Function to handle the MSC SCSI state machine */ +uint8_t USBMSC_poll(void); + +/* MSC functions */ +int16_t MSCToHostFromBuffer (); +int16_t MSCFromHostToBuffer (); +uint8_t USBMSC_bufferProcessed(void); +uint8_t USBMSC_getState (); +uint8_t USBMSC_updateMediaInfo (uint8_t lun, struct USBMSC_mediaInfoStr *info); + +uint8_t USBMSC_handleBufferEvent(void); +uint8_t USBMSC_registerBufInfo ( uint8_t lun, uint8_t* RWbuf_x, uint8_t* RWbuf_y, uint16_t size); + +#ifdef __cplusplus +} +#endif +#endif //_USB_MSC_H_ +//Released_Version_4_10_02 diff --git a/source/USB_API/USB_MSC_API/UsbMscReq.c b/source/USB_API/USB_MSC_API/UsbMscReq.c new file mode 100644 index 0000000..092c24f --- /dev/null +++ b/source/USB_API/USB_MSC_API/UsbMscReq.c @@ -0,0 +1,97 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ + +// +//! \cond +// + +/* + * ======== UsbMscReq.c ======== + */ +#include + +#ifdef _MSC_ + +#include "../USB_Common/device.h" +#include "../USB_Common/defMSP430USB.h" +#include "../USB_Common/usb.h" //USB-specific Data Structures +#include "../USB_MSC_API/UsbMscScsi.h" +#include "../USB_MSC_API/UsbMscReq.h" +#include "../USB_MSC_API/UsbMsc.h" + +extern __no_init tEDB __data16 tInputEndPointDescriptorBlock[]; +extern __no_init tEDB __data16 tOutputEndPointDescriptorBlock[]; +extern struct _MscState MscState; + +/*----------------------------------------------------------------------------+ + | Functions | + +----------------------------------------------------------------------------*/ +uint8_t USBMSC_reset (void) +{ + Msc_ResetStateMachine(); + Msc_ResetFlags(); + Msc_ResetStruct(); + MscState.isMSCConfigured = TRUE; + + MscState.bMscResetRequired = FALSE; + tInputEndPointDescriptorBlock[stUsbHandle[MSC0_INTFNUM].edb_Index].bEPCNF + &= ~(EPCNF_STALL | EPCNF_TOGGLE ); + tOutputEndPointDescriptorBlock[stUsbHandle[MSC0_INTFNUM].edb_Index].bEPCNF + &= ~(EPCNF_STALL | EPCNF_TOGGLE ); + usbSendZeroLengthPacketOnIEP0(); //status stage for control transfer + + return (FALSE); +} + +//---------------------------------------------------------------------------- +uint8_t Get_MaxLUN (void) +{ + uint8_t maxLunNumber = MSC_MAX_LUN_NUMBER - 1; + + wBytesRemainingOnIEP0 = 1; + MscState.isMSCConfigured = TRUE; + usbSendDataPacketOnEP0((uint8_t*)&maxLunNumber); + + return (FALSE); +} + +#endif //_MSC_ + +// +//! \cond +// + +/*----------------------------------------------------------------------------+ + | End of source file | + +----------------------------------------------------------------------------*/ +/*------------------------ Nothing Below This Line --------------------------*/ +//Released_Version_4_10_02 diff --git a/source/USB_API/USB_MSC_API/UsbMscReq.h b/source/USB_API/USB_MSC_API/UsbMscReq.h new file mode 100644 index 0000000..c5acabb --- /dev/null +++ b/source/USB_API/USB_MSC_API/UsbMscReq.h @@ -0,0 +1,54 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +/* + * ======== UsbMscReq.h ======== + */ +#ifndef _USB_MSC_REQ_H_ +#define _USB_MSC_REQ_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* MSC Class defined Request.Reset State-Machine and makes endpoints ready again*/ +uint8_t USBMSC_reset(void); + +/* MSC Class defined Request.Tells the host the number of supported logical units*/ +uint8_t Get_MaxLUN(void); + +#ifdef __cplusplus +} +#endif +#endif //_USB_MSC_REQ_H_ + +//Released_Version_4_10_02 diff --git a/source/USB_API/USB_MSC_API/UsbMscScsi.c b/source/USB_API/USB_MSC_API/UsbMscScsi.c new file mode 100644 index 0000000..7119e8c --- /dev/null +++ b/source/USB_API/USB_MSC_API/UsbMscScsi.c @@ -0,0 +1,2098 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +/** @file UsbMscScsi.c + * @brief Contains APIs related to MSC (Mass Storage) SCSI handling + */ +// +//! \cond +// + +/* + * ======== UsbMscScsi.c ======== + */ +/*----------------------------------------------------------------------------+ + | Includes | + +----------------------------------------------------------------------------*/ +#include "../USB_Common/device.h" +#include "../USB_Common/defMSP430USB.h" +#include "../USB_Common/usb.h" +#include "../USB_MSC_API/UsbMscScsi.h" +#include "../USB_MSC_API/UsbMsc.h" +#include +#include + +#ifdef _MSC_ + +/*----------------------------------------------------------------------------+ + | Internal Definitions | + +----------------------------------------------------------------------------*/ +//Error codes +#define RESCODE_CURRENT_ERROR 0x70 + +#define S_NO_SENSE 0x00 +#define S_NOT_READY 0x02 +#define S_MEDIUM_ERROR 0x03 +#define S_ILLEGAL_REQUEST 0x05 +#define S_UNITATTN 0x06 +#define S_WRITE_PROTECTED 0x07 +#define S_ABORTED_COMMAND 0x0B + +#define ASC_NOT_READY 0x04 +#define ASCQ_NOT_READY 0x03 + +#define ASC_MEDIUM_NOT_PRESENT 0x3A +#define ASCQ_MEDIUM_NOT_PRESENT 0x00 + +#define ASC_INVALID_COMMAND_OP_CODE 0x20 +#define ASCQ_INVALID_COMMAND_OP_CODE 0x00 + +#define ASC_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE 0x21 +#define ASCQ_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE 0x00 + +#define ASC_INVALID_FIELD_IN_CDB 0x24 +#define ASCQ_INVALID_FIELD_IN_CDB 0x00 + +#define ASC_INVALID_PARAMETER_LIST 0x26 +#define ASCQ_INVALID_PARAMETER_LIST 0x02 + +#define ASC_ABORTED_DATAPHASE_ERROR 0x4B +#define ASCQ_ABORTED_DATAPHASE_ERROR 0x00 + +#define ASC_ILLEGAL_REQUEST 0x20 +#define ASCQ_ILLEGAL_REQUEST 0x00 + +#define ASC_UNITATTN_READY_NOTREADY 0x28 +#define ASCQ_UNITATTN_READY_NOTREADY 0x00 + +#define ASC_WRITE_PROTECTED 0X27 +#define ASCQ_WRITE_PROTECTED 0X00 + +#define ASC_WRITE_FAULT 0x03 +#define ASCQ_WRITE_FAULT 0x00 + +#define ASC_UNRECOVERED_READ 0x11 +#define ASCQ_UNRECOVERED_READ 0x00 + +#define DIRECTION_IN 0x80 +#define DIRECTION_OUT 0x00 + +#define EP_MAX_PACKET_SIZE 0x40 + +void usbStallEndpoint (uint8_t); +uint8_t Scsi_Verify_CBW (); + +extern struct config_struct USBMSC_config; + +extern void *(*USB_TX_memcpy)(void * dest, const void * source, size_t count); +extern void *(*USB_RX_memcpy)(void * dest, const void * source, size_t count); + +extern __no_init tEDB __data16 tInputEndPointDescriptorBlock[]; +extern __no_init tEDB __data16 tOutputEndPointDescriptorBlock[]; +/*----------------------------------------------------------------------------+ + | Global Variables | + +----------------------------------------------------------------------------*/ + +struct _MscWriteControl MscWriteControl; +struct _MscReadControl MscReadControl; +struct _MscControl MscControl[MSC_MAX_LUN_NUMBER] = {0}; + +/* Structure internal to stack for maintaining LBA info,buffer address etc */ +USBMSC_RWbuf_Info sRwbuf; + +__no_init CBW McsCbw; +__no_init CSW McsCsw; + +struct _MscState MscState; + +/*----------------------------------------------------------------------------+ + | Initiliazing Command data | + +----------------------------------------------------------------------------*/ +uint8_t Scsi_Standard_Inquiry_Data[256]; + +REQUEST_SENSE_RESPONSE RequestSenseResponse; + +struct _Scsi_Read_Capacity Scsi_Read_Capacity_10[MSC_MAX_LUN_NUMBER]; + +const struct _Report_Luns Report_Luns = {{0x02,0x00,0x00,0x00}, + {0x00,0x00,0x00,0x00}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00}}; + +uint8_t Scsi_Mode_Sense_6[SCSI_MODE_SENSE_6_CMD_LEN] = {0x03,0,0,0 }; //No mode sense parameter + +uint8_t Scsi_Mode_Sense_10[SCSI_MODE_SENSE_10_CMD_LEN] = {0,0x06,0,0,0,0,0,0 }; //No mode sense parameter + +uint8_t Scsi_Read_Format_Capacity[SCSI_READ_FORMAT_CAPACITY_CMD_LEN] = +{0x00,0x00,0x00,0x08,0x01,0x00,0x00,0x00,0x03,0x00,0x02,0x00}; + +/*Default values initialized for SCSI Inquiry data */ +const uint8_t bScsi_Standard_Inquiry_Data[SCSI_SCSI_INQUIRY_CMD_LEN] = { +#ifdef CDROM_SUPPORT + 0x05, //Peripheral qualifier & peripheral device type +#else + 0x00, //Peripheral qualifier & peripheral device type +#endif + 0x80, //Removable medium + 0x02, //Version of the standard (SPC-2) + 0x02, //No NormACA, No HiSup, response data format=2 + 0x1F, //No extra parameters + 0x00, //No flags + 0x00, //0x80 => BQue => Basic Task Management supported + 0x00, //No flags + /* 'T','I',' ',' ',' ',' ',' ',' ', + * 'M','a','s','s',' ','S','t','o','r','a','g','e', */ +}; + +#ifdef CDROM_SUPPORT + +/* SCSI TOC Record - Pg.459 of mmc6r02g.pdf */ +const uint8_t Scsi_Read_TOC_PMA_ATIP_F1[Scsi_Read_TOC_PMA_ATIP_F1_LEN] = { + 0x00, 0x12, // Length + 0x01, // First Track + 0x01, // Last Track + + 0x00, // Reserved + 0x14, // ADR/CTL + 0x01, // Track Number + 0x00, // Reserved + 0x00, 0x00, 0x02, 0x00, // Track Address (TIME Form) + 0x00,0x00,0x00,0x00, // Padding + 0x00,0x00,0x00,0x00 +}; + +const uint8_t Scsi_Read_TOC_PMA_ATIP_F2[Scsi_Read_TOC_PMA_ATIP_F2_LEN] = { + 0x00, 0x2E, // Length + 0x01, // First Track + 0x01, // Last Track + 0x01, // Reserved + 0x14, // ADR/CTL + 0x00, // Track Number + 0xA0, // Reserved + 0x00, 0x00, 0x00, 0x00, // Track Address (TIME Form) + 0x01,0x00,0x00,0x01, // Padding/Descriptors + 0x14,0x00,0xA1,0x00, + 0x00,0x00,0x00,0x01, + 0x00,0x00,0x01,0x14, + 0x00,0xA2,0x00,0x00, + 0x00,0x00,0x1C,0x35, + 0x30,0x01,0x14,0x00, + 0x01,0x00,0x00,0x00, + 0x00,0x00,0x02,0x00 +}; + +/* GET_CONFIGURATION Response Pg. 312 of mmc6r02g.pdf */ +const uint8_t Scsi_Get_Configuration_Descriptor[SCSI_GET_CONFIGURATION_LEN] = { + + /* Feature Header */ + 0x00,0x00,0x00,0x00 // Length +}; + +/* EVENT STATUS Response Pg. 316 of mmc6r02g.pdf */ +const uint8_t Scsi_Event_Status_Descriptor[SCSI_EVENT_STATUS_LEN] = { + + /* Feature Header */ + 0x00,0x06, // Event Descriptor Length + 0x04, // NEA/Reserved/Notification Class + 0x54, // Supported Event Classes + 0x02, // Reserved/Event Code + 0x02, + 0x00,0x00 +}; + + +/* READ_DISC_INFORMATION Response Pg. 374 of mmc6r02g.pdf */ +const uint8_t Scsi_Disc_Information_Descriptor[SCSI_READ_DISC_INFORMATION_LEN] = { + + 0x00,0x00, // Disc Information Length + 0x00, // Disc Information Type, Non-Erasable, Last Session, Finalized + 0x00, // First Track on Disc + 0x00, // Number of Sessions + 0x00, // First Track Number in Last Session + 0x00, // Last Track Number in Last Session + 0x00, // BG/Barcode/ID Disable + 0x00, // Disc Type (CD-ROM) + 0x00, // Number of Sessions (MSB) + 0x00, // First Track Number in Last Session (MSB) + 0x00, // Last Track Number in Last Sessions (MSB) + 0x00,0x00,0x00,0x00, // Disc ID + 0x00,0x00,0x00,0x00, // Last Session Lead-In Address + 0x00,0x00,0x00,0x00, // Last Lead-Out Start Address + 0x00,0x00,0x00,0x00, // Bar Code (Not Supported) + 0x00,0x00,0x00,0x00, + 0x00, // Disc Application Code (Not Supported) + 0x00,0x00,0x00 // No OPC Entries +}; + +void Scsi_Read_TocPmaAtip(uint8_t intfNum); +void Scsi_Get_Configuration(uint8_t intfNum); +void Scsi_Event_Status_Notification(uint8_t intfNum); +void Scsi_Read_Disc_Information(uint8_t intfNum); + +#endif +/*----------------------------------------------------------------------------+ + | Functions | + +----------------------------------------------------------------------------*/ +void Reset_RequestSenseResponse (void) +{ + int16_t i; + + RequestSenseResponse.ResponseCode = RESCODE_CURRENT_ERROR; + RequestSenseResponse.VALID = 0; //no data in the information field + RequestSenseResponse.Obsolete = 0x00; + RequestSenseResponse.SenseKey = S_NO_SENSE; + RequestSenseResponse.ILI = 0; + RequestSenseResponse.EOM = 0; + RequestSenseResponse.FILEMARK = 0; + RequestSenseResponse.Information[0] = 0x00; + RequestSenseResponse.Information[1] = 0x00; + RequestSenseResponse.Information[2] = 0x00; + RequestSenseResponse.Information[3] = 0x00; + RequestSenseResponse.AddSenseLen = 0x0a; + RequestSenseResponse.CmdSpecificInfo[0] = 0x00; + RequestSenseResponse.CmdSpecificInfo[1] = 0x00; + RequestSenseResponse.CmdSpecificInfo[2] = 0x00; + RequestSenseResponse.CmdSpecificInfo[3] = 0x00; + RequestSenseResponse.ASC = 0x00; + RequestSenseResponse.ASCQ = 0x00; + RequestSenseResponse.FRUC = 0x00; + RequestSenseResponse.SenseKeySpecific[0] = 0x00; + RequestSenseResponse.SenseKeySpecific[1] = 0x00; + RequestSenseResponse.SenseKeySpecific[2] = 0x00; + for (i = 0; i < 14; i++){ + RequestSenseResponse.padding[i] = 0x00; + } +} + +//---------------------------------------------------------------------------- + +uint8_t Check_CBW (uint8_t intfNum,uint8_t Dir_Dev_Exp, uint32_t Bytes_Dev_Exp) +{ + if (McsCbw.CBWCB[0] == SCSI_INQUIRY || McsCbw.CBWCB[0] == + SCSI_REQUEST_SENSE){ + return (SUCCESS); + } + + if (Dir_Dev_Exp == McsCbw.bmCBWFlags){ //all is right. Host is sending direction as expected by device + if (McsCbw.dCBWDataTransferLength < Bytes_Dev_Exp){ //Host expect less data to send or receive then device + MscState.Scsi_Status = SCSI_PHASE_ERROR; + MscState.Scsi_Residue = 0 ; + if (McsCbw.bmCBWFlags == DIRECTION_IN){ + usbStallInEndpoint(intfNum); + } else { + usbStallOutEndpoint(intfNum); + } + } else if ((McsCbw.dCBWDataTransferLength > Bytes_Dev_Exp) && + (McsCbw.CBWCB[0] != SCSI_MODE_SENSE_6) && + (McsCbw.CBWCB[0] != SCSI_MODE_SENSE_10) && + (McsCbw.CBWCB[0] != SCSI_READ_TOC_PMA_ATIP)){ + MscState.Scsi_Status = SCSI_FAILED; + MscState.Scsi_Residue = McsCbw.dCBWDataTransferLength - + Bytes_Dev_Exp; + if (McsCbw.bmCBWFlags == DIRECTION_IN){ + usbStallInEndpoint(intfNum); + } else { + usbStallOutEndpoint(intfNum); + } + } else { + return ( SUCCESS) ; + } + } else { //Direction mismatch + MscState.Scsi_Residue = McsCbw.dCBWDataTransferLength; + MscState.Scsi_Status = SCSI_FAILED; + if (McsCbw.bmCBWFlags == DIRECTION_IN){ + usbStallInEndpoint(intfNum); + } else if ((McsCbw.bmCBWFlags == DIRECTION_OUT) && + (McsCbw.CBWCB[0] == SCSI_READ_10)){ + usbStallOutEndpoint(intfNum); + } + } + + //Indicates a generic failure. Read/write failure/sense data is handled separately + if (MscState.Scsi_Status != SCSI_READWRITE_FAIL){ + RequestSenseResponse.ResponseCode = RESCODE_CURRENT_ERROR; + RequestSenseResponse.VALID = 1; + RequestSenseResponse.AddSenseLen = 0xA0; + RequestSenseResponse.SenseKey = S_ILLEGAL_REQUEST; + RequestSenseResponse.ASC = ASC_INVALID_PARAMETER_LIST; + RequestSenseResponse.ASCQ = ASCQ_INVALID_PARAMETER_LIST; + } + + return (FAILURE); +} + +//---------------------------------------------------------------------------- +uint8_t Scsi_Verify_CBW () +{ + /*(5.2.3) Devices must consider the CBW meaningful if no reserved bits + * are set, the LUN number indicates a LUN supported by the device, + * bCBWCBLength is in the range of 1 through 16, and the length and + * content of the CBWCB field are appropriate to the SubClass. + */ + if ((MscState.bMscResetRequired || McsCbw.dCBWSignature != + CBW_SIGNATURE) || //Check for correct CBW signature + ((McsCbw.bmCBWFlags != DIRECTION_IN && McsCbw.bmCBWFlags != + DIRECTION_OUT) || + (McsCbw.bCBWLUN & 0xF0) || //Upper bits have to be zero + (McsCbw.bCBWCBLength > 16))){ //maximum length is 16 + MscState.bMscResetRequired = TRUE; + usbStallEndpoint(MSC0_INTFNUM); + usbClearOEPByteCount(MSC0_INTFNUM); + MscState.Scsi_Status = SCSI_FAILED; + MscState.Scsi_Residue = 0; + return (FAILURE); + } + MscState.Scsi_Status = SCSI_PASSED; + return (SUCCESS); +} + +//---------------------------------------------------------------------------- +uint8_t Scsi_Send_CSW (uint8_t intfNum) +{ + uint8_t retval = 0; + + //Populate the CSW to be sent + McsCsw.dCSWSignature = CSW_SIGNATURE; + McsCsw.dCSWTag = McsCbw.dCBWTag; + McsCsw.bCSWStatus = MscState.Scsi_Status; + McsCsw.dCSWDataResidue = MscState.Scsi_Residue; + retval = MscSendData((uint8_t*)&McsCsw, CSW_LENGTH); //Sending CSW + MscState.Scsi_Status = SCSI_PASSED; + return (retval); +} + +//---------------------------------------------------------------------------- + +void Scsi_Inquiry (uint8_t intfNum) +{ + //int16_t index; + + //clear the inquiry array + memset(Scsi_Standard_Inquiry_Data, 256, 0); + //copy the inquiry data from flash to RAM + + memcpy(Scsi_Standard_Inquiry_Data, + bScsi_Standard_Inquiry_Data, + SCSI_SCSI_INQUIRY_CMD_LEN); + + + + //get the values from USB_Config + Scsi_Standard_Inquiry_Data[1] = USBMSC_config.LUN[McsCbw.bCBWLUN].removable; + memcpy(&Scsi_Standard_Inquiry_Data[8], + USBMSC_config.LUN[McsCbw.bCBWLUN].t10VID, + 8); + memcpy(&Scsi_Standard_Inquiry_Data[16], + USBMSC_config.LUN[McsCbw.bCBWLUN].t10PID, + 16); + memcpy(&Scsi_Standard_Inquiry_Data[32], + USBMSC_config.LUN[McsCbw.bCBWLUN].t10rev, + 4); + + if (McsCbw.dCBWDataTransferLength < SCSI_SCSI_INQUIRY_CMD_LEN){ + if (McsCbw.dCBWDataTransferLength == 0){ + MscState.Scsi_Residue = 0; + return; + } + if (SUCCESS == + MscSendData((uint8_t*)Scsi_Standard_Inquiry_Data, + McsCbw.dCBWDataTransferLength)){ + MscState.Scsi_Residue = 0; + } else { + MscState.Scsi_Status = SCSI_FAILED; + } + } else if (McsCbw.dCBWDataTransferLength > SCSI_SCSI_INQUIRY_CMD_LEN){ + Reset_RequestSenseResponse(); + + RequestSenseResponse.ResponseCode = RESCODE_CURRENT_ERROR; + RequestSenseResponse.VALID = 1; + RequestSenseResponse.SenseKey = S_ILLEGAL_REQUEST; + RequestSenseResponse.ASC = ASC_INVALID_FIELD_IN_CDB; + RequestSenseResponse.ASCQ = ASCQ_INVALID_FIELD_IN_CDB; + usbStallInEndpoint(intfNum); + MscState.Scsi_Status = SCSI_FAILED; + } else { + if (SUCCESS == + MscSendData((uint8_t*)Scsi_Standard_Inquiry_Data, + SCSI_SCSI_INQUIRY_CMD_LEN)){ + MscState.Scsi_Residue = 0; + } else { + MscState.Scsi_Status = SCSI_FAILED; + } + } +} + +//---------------------------------------------------------------------------- + +void Scsi_Read_Capacity10 (uint8_t intfNum) +{ + if (FAILURE == Check_CBW(intfNum,DIRECTION_IN,SCSI_READ_CAPACITY_CMD_LEN)){ + return; + } + MscState.Scsi_Residue = 0; + if (SUCCESS != + MscSendData( (uint8_t*)&Scsi_Read_Capacity_10[McsCbw.bCBWLUN], + SCSI_READ_CAPACITY_CMD_LEN)){ + MscState.Scsi_Status = SCSI_FAILED; + } +} + + +//---------------------------------------------------------------------------- + +void Scsi_Read10 (uint8_t intfNum) +{ + uint16_t wLBA_len; + uint16_t state; + uint8_t edbIndex; + uint32_t dLBA; + + /* Get first LBA: convert 4 bytes into uint32_t */ + dLBA = McsCbw.CBWCB[2]; + dLBA <<= 8; + dLBA += McsCbw.CBWCB[3]; + dLBA <<= 8; + dLBA += McsCbw.CBWCB[4]; + dLBA <<= 8; + dLBA += McsCbw.CBWCB[5]; + + /* Get number of requested logical blocks */ + wLBA_len = McsCbw.CBWCB[7]; + wLBA_len <<= 8; + wLBA_len += McsCbw.CBWCB[8]; + + if (FAILURE == + Check_CBW( intfNum, DIRECTION_IN, ((uint32_t)wLBA_len) * + MscControl[McsCbw.bCBWLUN].lbaSize)){ + return; + } + + edbIndex = stUsbHandle[intfNum].edb_Index; + state = usbDisableOutEndpointInterrupt(edbIndex); + + //Populating stack internal structure required for READ/WRITE + MscReadControl.lba = dLBA; //the first LBA number. + MscReadControl.lbaCount = wLBA_len; //how many LBAs to read. + MscReadControl.XorY = 0; + + sRwbuf.bufferAddr = MscControl[McsCbw.bCBWLUN].xBufferAddr; + sRwbuf.lun = McsCbw.bCBWLUN; + + //set LBA count + sRwbuf.lbCount = wLBA_len > + MscControl[McsCbw.bCBWLUN].lbaBufCapacity ? + MscControl[McsCbw.bCBWLUN].lbaBufCapacity : wLBA_len; + sRwbuf.operation = kUSBMSC_READ; + sRwbuf.lba = dLBA; + sRwbuf.returnCode = kUSBMSC_RWSuccess; + sRwbuf.XorY = 0; + sRwbuf.xBufFull = 0; + sRwbuf.xWordCnt = 0; + sRwbuf.yBufFull = 0; + sRwbuf.yWordCnt = 0; + sRwbuf.bufferProcessed = 0; + sRwbuf.firstFlag = 0; + //buffer is prepared, let user's Application fill data. + USBMSC_handleBufferEvent(); + + usbRestoreOutEndpointInterrupt(state); +} + +//---------------------------------------------------------------------------- + +void Scsi_Write10 (uint8_t intfNum) +{ + uint16_t wLBA_len; + uint8_t edbIndex; + uint16_t state; + /* Get first LBA: convert 4 bytes into uint32_t */ + uint32_t dLBA = McsCbw.CBWCB[2]; + + dLBA <<= 8; + dLBA += McsCbw.CBWCB[3]; + dLBA <<= 8; + dLBA += McsCbw.CBWCB[4]; + dLBA <<= 8; + dLBA += McsCbw.CBWCB[5]; + + /* Get number of requested logical blocks */ + wLBA_len = McsCbw.CBWCB[7]; + wLBA_len <<= 8; + wLBA_len += McsCbw.CBWCB[8]; + + if (FAILURE == + Check_CBW(intfNum,DIRECTION_OUT,((uint32_t)wLBA_len) * + MscControl[McsCbw.bCBWLUN].lbaSize)){ + return; + } + + edbIndex = stUsbHandle[intfNum].edb_Index; + state = usbDisableInEndpointInterrupt(edbIndex); + + //calculate the whole size to receive (Host to MSP430) + MscWriteControl.dwBytesToReceiveLeft = (uint32_t)wLBA_len * + MscControl[McsCbw.bCBWLUN].lbaSize; + MscWriteControl.pUserBuffer = MscControl[McsCbw.bCBWLUN].xBufferAddr; + MscWriteControl.wFreeBytesLeft = + MscControl[McsCbw.bCBWLUN].wMscUserBufferSize; + + /*Populating stack internal structure required for READ/WRITE */ + + MscWriteControl.bWriteProcessing = TRUE; //indicate that we are in WRITE phase + MscWriteControl.lba = dLBA; + MscWriteControl.wCurrentByte = 0; //reset internal variable + MscWriteControl.lbaCount = 0; //reset internal variable + MscWriteControl.XorY = 0; + + sRwbuf.lun = McsCbw.bCBWLUN; + sRwbuf.operation = 0; + sRwbuf.lba = 0; + sRwbuf.lbCount = 0; + sRwbuf.bufferAddr = MscControl[McsCbw.bCBWLUN].xBufferAddr; + sRwbuf.returnCode = 0; + sRwbuf.XorY = 0; + sRwbuf.xBufFull = 0; + sRwbuf.yBufFull = 0; + sRwbuf.bufferProcessed = 0; + sRwbuf.firstFlag = 0; + sRwbuf.xlba = 0; + sRwbuf.xlbaCount = 0; + sRwbuf.ylba = 0; + sRwbuf.ylbaCount = 0; + + usbRestoreInEndpointInterrupt(state); +} + +//---------------------------------------------------------------------------- + +void Scsi_Mode_Sense6 (uint8_t intfNum) +{ + if (FAILURE == Check_CBW(intfNum,DIRECTION_IN,SCSI_MODE_SENSE_6_CMD_LEN)){ + return; + } + /* Fix for SDOCM00077834 - Set WP bit. WP bit is BIT7 in byte 3 */ + Scsi_Mode_Sense_6[2] |= (MscControl[McsCbw.bCBWLUN].bWriteProtected << 0x7); + + MscState.Scsi_Residue = McsCbw.dCBWDataTransferLength - + SCSI_MODE_SENSE_6_CMD_LEN; + if (MscState.Scsi_Residue) { + MscState.stallAtEndofTx = TRUE; + } + if (SUCCESS != + MscSendData((uint8_t*)Scsi_Mode_Sense_6, SCSI_MODE_SENSE_6_CMD_LEN)){ + MscState.Scsi_Status = SCSI_FAILED; + } +} + +//---------------------------------------------------------------------------- + +void Scsi_Mode_Sense10 (uint8_t intfNum) +{ + if (FAILURE == Check_CBW(intfNum,DIRECTION_IN,SCSI_MODE_SENSE_10_CMD_LEN)){ + return; + } + /* Fix for SDOCM00077834 - Set WP bit. WP bit is BIT7 in byte 3 */ + Scsi_Mode_Sense_10[4] |= (MscControl[McsCbw.bCBWLUN].bWriteProtected << 0x7); + MscState.Scsi_Residue = McsCbw.dCBWDataTransferLength - + SCSI_MODE_SENSE_10_CMD_LEN; + if (MscState.Scsi_Residue) { + MscState.stallAtEndofTx = TRUE; + } + if (SUCCESS != + MscSendData((uint8_t*)Scsi_Mode_Sense_10, SCSI_MODE_SENSE_10_CMD_LEN)){ + MscState.Scsi_Status = SCSI_FAILED; + } +} + +//---------------------------------------------------------------------------- + +void Scsi_Request_Sense (uint8_t intfNum) +{ + if (FAILURE == Check_CBW(intfNum,DIRECTION_IN,SCSI_REQ_SENSE_CMD_LEN)){ + return; + } + + //If there is attention needed, setup the request sense response. The + //bUnitAttention flag is set in USBMSC_updateMediaInfo() when the volume + //is removed or inserted. Note that the response is different for the + //removed and inserted case. + if (MscState.bUnitAttention == TRUE){ + //Check if the volume was removed. + if (MscControl[McsCbw.bCBWLUN].bMediaPresent == + kUSBMSC_MEDIA_NOT_PRESENT){ + Reset_RequestSenseResponse(); + RequestSenseResponse.VALID = 1; + RequestSenseResponse.SenseKey = S_NOT_READY; + RequestSenseResponse.ASC = ASC_MEDIUM_NOT_PRESENT; + RequestSenseResponse.ASCQ = ASCQ_MEDIUM_NOT_PRESENT; + } + //Otherwise it was inserted. + else { + Reset_RequestSenseResponse(); + RequestSenseResponse.VALID = 1; + RequestSenseResponse.SenseKey = S_UNITATTN; + RequestSenseResponse.ASC = ASC_UNITATTN_READY_NOTREADY; + RequestSenseResponse.ASCQ = ASCQ_UNITATTN_READY_NOTREADY; + } + } + + if (McsCbw.dCBWDataTransferLength < SCSI_REQ_SENSE_CMD_LEN){ + if (SUCCESS == + MscSendData((uint8_t*)&RequestSenseResponse, + McsCbw.dCBWDataTransferLength)){ + MscState.Scsi_Residue = 0; + } else { + MscState.Scsi_Status = SCSI_FAILED; + } + } else if (McsCbw.dCBWDataTransferLength > SCSI_REQ_SENSE_CMD_LEN){ + RequestSenseResponse.AddSenseLen += + (McsCbw.dCBWDataTransferLength - SCSI_REQ_SENSE_CMD_LEN); + if (SUCCESS == + MscSendData((uint8_t*)&RequestSenseResponse, + McsCbw.dCBWDataTransferLength)){ + MscState.Scsi_Residue = 0; + } else { + MscState.Scsi_Status = SCSI_FAILED; + } + } else { + if (SUCCESS == + MscSendData((uint8_t*)&RequestSenseResponse,SCSI_REQ_SENSE_CMD_LEN)){ + MscState.Scsi_Residue = 0; + } else { + MscState.Scsi_Status = SCSI_FAILED; + } + } + + //Clear the bUnitAttention flag after the response was properly sent via + //MscSendData(). + if (MscState.bUnitAttention == TRUE){ + MscState.bUnitAttention = FALSE; + } +} + +//---------------------------------------------------------------------------- + +void Scsi_Test_Unit_Ready (uint8_t intfNum) +{ + if (SUCCESS != Check_CBW(intfNum,DIRECTION_OUT,0)){ + MscState.Scsi_Status = SCSI_FAILED; + } + + Reset_RequestSenseResponse(); +} + +//---------------------------------------------------------------------------- + +void Scsi_Unknown_Request (uint8_t intfNum) +{ + Reset_RequestSenseResponse(); + + RequestSenseResponse.ResponseCode = RESCODE_CURRENT_ERROR; + RequestSenseResponse.VALID = 1; + RequestSenseResponse.AddSenseLen = 0xA0; + RequestSenseResponse.SenseKey = S_ILLEGAL_REQUEST; + RequestSenseResponse.ASC = ASC_INVALID_COMMAND_OP_CODE; + RequestSenseResponse.ASCQ = ASCQ_INVALID_COMMAND_OP_CODE; + MscState.Scsi_Residue = 0; + MscState.Scsi_Status = SCSI_FAILED; + + if (McsCbw.dCBWDataTransferLength && (McsCbw.bmCBWFlags == DIRECTION_IN)){ + MscState.bMcsCommandSupported = FALSE; + usbStallInEndpoint(intfNum); + } + if (McsCbw.dCBWDataTransferLength && (McsCbw.bmCBWFlags == DIRECTION_OUT)){ + MscState.bMcsCommandSupported = FALSE; + usbStallOutEndpoint(intfNum); + } +} + +//---------------------------------------------------------------------------- + +void Scsi_Report_Luns (uint8_t intfNum) +{ + if (FAILURE == + Check_CBW( intfNum, DIRECTION_IN, SCSI_REPORT_LUNS_CMD_LEN)){ + return; + } + if (SUCCESS != + MscSendData( (uint8_t*)&Report_Luns, SCSI_REPORT_LUNS_CMD_LEN)){ + MscState.Scsi_Status = SCSI_FAILED; + } +} + +//---------------------------------------------------------------------------- + +uint8_t Scsi_Cmd_Parser (uint8_t intfNum) +{ + uint8_t ret = kUSBMSC_cmdBeingProcessed; + + //MscState.Scsi_Status = SCSI_FAILED; + MscState.Scsi_Residue = McsCbw.dCBWDataTransferLength; + + //fails the commands during UNIT ATTENTION + if ((MscState.bUnitAttention) && (McsCbw.CBWCB[0] != SCSI_INQUIRY) && + (McsCbw.CBWCB[0] != SCSI_REQUEST_SENSE)){ + MscState.Scsi_Status = SCSI_FAILED; + return (kUSB_generalError); + } + + if (!McsCbw.bCBWCBLength){ + return (kUSB_generalError); + } + + switch (McsCbw.CBWCB[0]) //SCSI Operation code + { + case SCSI_READ_10: + if (MscControl[McsCbw.bCBWLUN].xBufferAddr == NULL){ //Check for null address. + ret = kUSB_generalError; + SET_RequestsenseNotReady(); + MscState.Scsi_Status = SCSI_FAILED; + usbStallInEndpoint(intfNum); + break; + } + + if (MscControl[McsCbw.bCBWLUN].bMediaPresent == + kUSBMSC_MEDIA_NOT_PRESENT){ //Check for media present. Do this for any command that accesses + //media. + ret = kUSB_generalError; + SET_RequestsenseMediaNotPresent(); + usbStallInEndpoint(intfNum); + break; + } + Scsi_Read10(intfNum); + break; + + case SCSI_WRITE_10: + if (MscControl[McsCbw.bCBWLUN].xBufferAddr == NULL){ //Check for null address. + ret = kUSB_generalError; + SET_RequestsenseNotReady(); + MscState.Scsi_Status = SCSI_FAILED; + break; + } + + if (MscControl[McsCbw.bCBWLUN].bMediaPresent == + kUSBMSC_MEDIA_NOT_PRESENT){ //Check for media present. Do this for any command that accesses + //media. + ret = kUSB_generalError; + SET_RequestsenseMediaNotPresent(); + usbStallOutEndpoint(intfNum); + break; + } + + if (MscControl[McsCbw.bCBWLUN].bWriteProtected){ //Do this only for WRITE + ret = kUSB_generalError; + //Set REQUEST SENSE with "write protected" + Reset_RequestSenseResponse(); + RequestSenseResponse.VALID = 1; + RequestSenseResponse.SenseKey = S_WRITE_PROTECTED; + RequestSenseResponse.ASC = ASC_WRITE_PROTECTED; + RequestSenseResponse.ASCQ = ASCQ_WRITE_PROTECTED; + MscWriteControl.bWriteProcessing = FALSE; + //Send CSW with error status + MscState.Scsi_Residue = 1; + MscState.Scsi_Status = SCSI_FAILED; + usbStallOutEndpoint(intfNum); + break; + } + + Scsi_Write10(intfNum); + break; + + case START_STOP_UNIT: + case PREVENT_ALLW_MDM: + case SCSI_MODE_SELECT_10: + case SCSI_MODE_SELECT_6: + case SCSI_TEST_UNIT_READY: + if (MscControl[McsCbw.bCBWLUN].bMediaPresent == + kUSBMSC_MEDIA_NOT_PRESENT){ //Check for media present. Do this for any command that accesses + //media. + ret = kUSB_generalError; + SET_RequestsenseMediaNotPresent(); + break; + } + Scsi_Test_Unit_Ready(intfNum); + break; + + case SCSI_SET_CD_SPEED: + break; + case SCSI_INQUIRY: + Scsi_Inquiry(intfNum); + break; + + case SCSI_MODE_SENSE_6: + Scsi_Mode_Sense6(intfNum); + break; + + case SCSI_MODE_SENSE_10: + Scsi_Mode_Sense10(intfNum); + break; + + case SCSI_READ_CAPACITY_10: + if (MscControl[McsCbw.bCBWLUN].bMediaPresent == + kUSBMSC_MEDIA_NOT_PRESENT){ //Check for media present. Do this for any command that accesses media. + ret = kUSB_generalError; + SET_RequestsenseMediaNotPresent(); + usbStallInEndpoint(intfNum); + break; + } + Scsi_Read_Capacity10(intfNum); + break; + + case SCSI_REQUEST_SENSE: + Scsi_Request_Sense(intfNum); + break; + + case SCSI_REPORT_LUNS: + if (MscControl[McsCbw.bCBWLUN].bMediaPresent == + kUSBMSC_MEDIA_NOT_PRESENT){ //Check for media present. Do this for any command that accesses media. + ret = kUSB_generalError; + SET_RequestsenseMediaNotPresent(); + if (McsCbw.bmCBWFlags == DIRECTION_IN){ + usbStallInEndpoint(intfNum); + } else { + usbStallOutEndpoint(intfNum); + } + break; + } + Scsi_Report_Luns(intfNum); + break; + case SCSI_VERIFY: + /* Fix for SDOCM00078183 */ + /* NOTE: we are assuming that BYTCHK=0 and PASSing the command. */ + break; +#ifdef CDROM_SUPPORT + + case SCSI_READ_TOC_PMA_ATIP: + if (MscControl[McsCbw.bCBWLUN].bMediaPresent == + kUSBMSC_MEDIA_NOT_PRESENT){ //Check for media present. Do this for any command that accesses media. + ret = kUSB_generalError; + SET_RequestsenseMediaNotPresent(); + usbStallInEndpoint(intfNum); + break; + } + Scsi_Read_TocPmaAtip(intfNum); + break; + + case SCSI_GET_CONFIGURATION: + if (MscControl[McsCbw.bCBWLUN].bMediaPresent == + kUSBMSC_MEDIA_NOT_PRESENT){ //Check for media present. Do this for any command that accesses media. + ret = kUSB_generalError; + SET_RequestsenseMediaNotPresent(); + usbStallInEndpoint(intfNum); + break; + } + Scsi_Get_Configuration(intfNum); + break; + case SCSI_EVENT_STATUS: + if (MscControl[McsCbw.bCBWLUN].bMediaPresent == + kUSBMSC_MEDIA_NOT_PRESENT){ //Check for media present. Do this for any command that accesses media. + ret = kUSB_generalError; + SET_RequestsenseMediaNotPresent(); + usbStallInEndpoint(intfNum); + break; + } + Scsi_Event_Status_Notification(intfNum); + break; + + case SCSI_READ_DISC_INFORMATION: + + if (MscControl[McsCbw.bCBWLUN].bMediaPresent == + kUSBMSC_MEDIA_NOT_PRESENT){ //Check for media present. Do this for any command that accesses media. + ret = kUSB_generalError; + SET_RequestsenseMediaNotPresent(); + usbStallInEndpoint(intfNum); + break; + } + + Scsi_Read_Disc_Information(intfNum); + break; +#endif + default: + ret = kUSB_generalError; + Scsi_Unknown_Request(intfNum); + break; + } + return (ret); +} + +//------------------------------------------------------------------------------------------------------- +/* This function is called only from ISR(only on Input endpoint interrupt to transfer data to host) + * This function actually performs the data transfer to host Over USB */ +int16_t MSCToHostFromBuffer () +{ + //Check if there are any pending LBAs to process + uint8_t * pEP1; + uint8_t * pEP2; + uint8_t * pCT1; + uint8_t * pCT2; + uint8_t bWakeUp = FALSE; //per default we do not wake up after interrupt + uint8_t edbIndex; + uint8_t bCount; + + if (MscControl[sRwbuf.lun].yBufferAddr == NULL) { + //Check if there are any pending data to send + if (MscReadControl.dwBytesToSendLeft == 0){ + //no more data to send - clear ready busy status + MscReadControl.bReadProcessing = FALSE; + + //check if more LBA to send out pending... + if (MscReadControl.lbaCount > 0){ + sRwbuf.lba = MscReadControl.lba; //update current lba + sRwbuf.lbCount = MscControl[sRwbuf.lun].lbaBufCapacity > + MscReadControl.lbaCount ? + MscReadControl.lbaCount : MscControl[sRwbuf.lun]. + lbaBufCapacity; //update LBA count + sRwbuf.operation = kUSBMSC_READ; //start data READ phase + sRwbuf.returnCode = kUSBMSC_RWSuccess; + sRwbuf.bufferAddr = MscControl[sRwbuf.lun].xBufferAddr; + sRwbuf.XorY = 0; //only one buffer is active + //buffer is prepared, let user's Application fill data. + USBMSC_handleBufferEvent(); + } + return (TRUE); //data sent out - wake up! + } + } + else { + if ((MscReadControl.lbaCount > 0) && (sRwbuf.bufferProcessed == 1)) { + if ((sRwbuf.XorY == 0) && (sRwbuf.yBufFull == 0)){ + sRwbuf.bufferProcessed = 0; + sRwbuf.XorY = 1; + sRwbuf.bufferAddr = MscControl[sRwbuf.lun].yBufferAddr; + sRwbuf.lba = MscReadControl.lba; //update current lba + sRwbuf.lbCount = MscControl[sRwbuf.lun].lbaBufCapacity > + MscReadControl.lbaCount ? + MscReadControl.lbaCount : MscControl[sRwbuf.lun]. + lbaBufCapacity; //update LBA count + sRwbuf.operation = kUSBMSC_READ; //start data READ phase + sRwbuf.returnCode = kUSBMSC_RWSuccess; + //buffer is prepared, let user's Application fill data. + USBMSC_handleBufferEvent(); + } + else if ((sRwbuf.XorY == 1) && (sRwbuf.xBufFull == 0)){ + sRwbuf.bufferProcessed = 0; + sRwbuf.XorY = 0; + sRwbuf.bufferAddr = MscControl[sRwbuf.lun].xBufferAddr; + sRwbuf.lba = MscReadControl.lba; //update current lba + sRwbuf.lbCount = MscControl[sRwbuf.lun].lbaBufCapacity > + MscReadControl.lbaCount ? + MscReadControl.lbaCount : MscControl[sRwbuf.lun]. + lbaBufCapacity; //update LBA count + sRwbuf.operation = kUSBMSC_READ; //start data READ phase + sRwbuf.returnCode = kUSBMSC_RWSuccess; + //buffer is prepared, let user's Application fill data. + USBMSC_handleBufferEvent(); + } + } + + //Check if there are any pending data to send + if (MscReadControl.dwBytesToSendLeft == 0){ + //no more data to send - clear ready busy status + MscReadControl.bReadProcessing = FALSE; + + if (MscReadControl.XorY == 0) { + sRwbuf.xBufFull = 0; + sRwbuf.xWordCnt = 0; + if (sRwbuf.yBufFull) { + MscSendData(MscControl[sRwbuf.lun].yBufferAddr, sRwbuf.yWordCnt); + MscReadControl.XorY = 1; + } + } + else { + sRwbuf.yBufFull = 0; + sRwbuf.yWordCnt = 0; + if (sRwbuf.xBufFull) { + MscSendData(MscControl[sRwbuf.lun].xBufferAddr, sRwbuf.xWordCnt); + MscReadControl.XorY = 0; + } + } + + return (TRUE); //data sent out - wake up! + } + } + + + edbIndex = stUsbHandle[MSC0_INTFNUM].edb_Index; + + //check if the endpoint is stalled = do not send data. + if (tInputEndPointDescriptorBlock[edbIndex].bEPCNF & EPCNF_STALL){ + return (TRUE); + } + + //send one chunk of 64 bytes + //check what is current buffer: X or Y + if (MscReadControl.bCurrentBufferXY == X_BUFFER){ //X is current buffer + //this is the active EP buffer + pEP1 = (uint8_t*)stUsbHandle[MSC0_INTFNUM].iep_X_Buffer; + pCT1 = &tInputEndPointDescriptorBlock[edbIndex].bEPBCTX; + + //second EP buffer + pEP2 = (uint8_t*)stUsbHandle[MSC0_INTFNUM].iep_Y_Buffer; + pCT2 = &tInputEndPointDescriptorBlock[edbIndex].bEPBCTY; + } else { + //this is the active EP buffer + pEP1 = (uint8_t*)stUsbHandle[MSC0_INTFNUM].iep_Y_Buffer; + pCT1 = &tInputEndPointDescriptorBlock[edbIndex].bEPBCTY; + + //second EP buffer + pEP2 = (uint8_t*)stUsbHandle[MSC0_INTFNUM].iep_X_Buffer; + pCT2 = &tInputEndPointDescriptorBlock[edbIndex].bEPBCTX; + } + + //how many byte we can send over one endpoint buffer + bCount = + (MscReadControl.dwBytesToSendLeft > + EP_MAX_PACKET_SIZE) ? EP_MAX_PACKET_SIZE : MscReadControl. + dwBytesToSendLeft; + + if (*pCT1 & EPBCNT_NAK){ + USB_TX_memcpy(pEP1, MscReadControl.pUserBuffer, bCount); //copy data into IEPx X or Y buffer + *pCT1 = bCount; //Set counter for usb In-Transaction + MscReadControl.bCurrentBufferXY = + (MscReadControl.bCurrentBufferXY + 1) & 0x01; //switch buffer + MscReadControl.dwBytesToSendLeft -= bCount; + MscReadControl.pUserBuffer += bCount; //move buffer pointer + + //try to send data over second buffer + if ((MscReadControl.dwBytesToSendLeft > 0) && //do we have more data to send? + (*pCT2 & EPBCNT_NAK)){ //if the second buffer is free? + //how many byte we can send over one endpoint buffer + bCount = + (MscReadControl.dwBytesToSendLeft > + EP_MAX_PACKET_SIZE) ? EP_MAX_PACKET_SIZE : MscReadControl. + dwBytesToSendLeft; + //copy data into IEPx X or Y buffer + USB_TX_memcpy(pEP2, MscReadControl.pUserBuffer, bCount); + //Set counter for usb In-Transaction + *pCT2 = bCount; + //switch buffer + MscReadControl.bCurrentBufferXY = + (MscReadControl.bCurrentBufferXY + 1) & 0x01; + MscReadControl.dwBytesToSendLeft -= bCount; + //move buffer pointer + MscReadControl.pUserBuffer += bCount; + } + } //if(*pCT1 & EPBCNT_NAK) + return (bWakeUp); +} + +//------------------------------------------------------------------------------------------------------ + +//This function used to initialize the sending process. +//Use this by functiosn for send CSW or send LBA +//To use only by STACK itself, not by application +//Returns: SUCCESS or FAILURE +uint8_t MscSendData (const uint8_t* data, uint16_t size) +{ + uint8_t edbIndex; + uint16_t state; + + edbIndex = stUsbHandle[MSC0_INTFNUM].edb_Index; + + if (size == 0){ + return (FAILURE); + } + + state = usbDisableInEndpointInterrupt(edbIndex); + //atomic operation - disable interrupts + + //do not access USB memory if suspended (PLL off). It may produce BUS_ERROR + if ((bFunctionSuspended) || + (bEnumerationStatus != ENUMERATION_COMPLETE)){ + //data can not be read because of USB suspended + usbRestoreInEndpointInterrupt(state); + return (FAILURE); + } + + if ((MscReadControl.dwBytesToSendLeft != 0) || //data was not sent out + (MscReadControl.bReadProcessing == TRUE)){ //still processing previous data + //the USB still sends previous data, we have to wait + usbRestoreInEndpointInterrupt(state); + return (FAILURE); + } + + //This function generate the USB interrupt. The data will be sent out from interrupt + + MscReadControl.bReadProcessing = TRUE; //set reading busy status. + MscReadControl.dwBytesToSendLeft = size; + MscReadControl.pUserBuffer = (uint8_t*)data; + + //trigger Endpoint Interrupt - to start send operation + USBIEPIFG |= 1 << (edbIndex + 1); //IEPIFGx; + + usbRestoreInEndpointInterrupt(state); + + return (SUCCESS); +} + +//This function copies data from OUT endpoint into user's buffer +//This function to call only from MSCFromHostToBuffer() +//Arguments: +//pEP - pointer to EP to copy from +//pCT - pointer to EP control reg +// +void MscCopyUsbToBuff (uint8_t* pEP, uint8_t* pCT) +{ + uint8_t nCount; + + nCount = *pCT & (~EPBCNT_NAK); + + //how many bytes we can receive to avoid overflow + nCount = + (nCount > + MscWriteControl.dwBytesToReceiveLeft) ? MscWriteControl. + dwBytesToReceiveLeft : + nCount; + + USB_RX_memcpy(MscWriteControl.pUserBuffer, pEP, nCount); //copy data from OEPx X or Y buffer + MscWriteControl.dwBytesToReceiveLeft -= nCount; + MscWriteControl.pUserBuffer += nCount; //move buffer pointer + //to read rest of data next time from this place + MscWriteControl.wFreeBytesLeft -= nCount; //update counter + + MscWriteControl.wCurrentByte += nCount; + if (MscWriteControl.wCurrentByte >= MscControl[sRwbuf.lun].lbaSize){ + MscWriteControl.wCurrentByte = 0; + MscWriteControl.lbaCount++; + } + + //switch current buffer + MscWriteControl.bCurrentBufferXY = + (MscWriteControl.bCurrentBufferXY + 1) & 0x01; + + //clear NAK, EP ready to receive data + *pCT = 0x00; +} + +//------------------------------------------------------------------------------------------------------ +/* This function is called only from ISR(only on Output endpoint interrupt, to recv data from host) + * This function actually recieves the data from host Over USB */ +int16_t MSCFromHostToBuffer () +{ + uint8_t * pEP1; + uint8_t nTmp1; + uint8_t bWakeUp = FALSE; //per default we do not wake up after interrupt + uint8_t edbIndex; + + edbIndex = stUsbHandle[MSC0_INTFNUM].edb_Index; + + if (MscState.stallEndpoint == TRUE) { + tOutputEndPointDescriptorBlock[edbIndex].bEPCNF |= EPCNF_STALL; + return TRUE; + } + + if (MscState.bMscCbwReceived == TRUE){ + //previous CBW is not performed, so exit interrupt hendler + //and trigger it again later + return (TRUE); //true for wake up! + } + + if (!MscWriteControl.bWriteProcessing){ //receiving CBW + //CBW will be received here.... + //check what is current buffer: X or Y + if (MscWriteControl.bCurrentBufferXY == X_BUFFER){ //X is current buffer + //this is the active EP buffer + pEP1 = (uint8_t*)stUsbHandle[MSC0_INTFNUM].oep_X_Buffer; + MscWriteControl.pCT1 = + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX; + MscWriteControl.pCT2 = + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY; + } else { + //this is the active EP buffer + pEP1 = (uint8_t*)stUsbHandle[MSC0_INTFNUM].oep_Y_Buffer; + MscWriteControl.pCT1 = + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY; + MscWriteControl.pCT2 = + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX; + } + + //how many byte we can get from one endpoint buffer + nTmp1 = *MscWriteControl.pCT1; + + if (nTmp1 & EPBCNT_NAK){ + uint8_t nCount; + + //switch current buffer + MscWriteControl.bCurrentBufferXY = + (MscWriteControl.bCurrentBufferXY + 1) & 0x01; + + nTmp1 = nTmp1 & 0x7f; //clear NAK bit + nCount = (nTmp1 > sizeof(McsCbw)) ? sizeof(McsCbw) : nTmp1; + USB_RX_memcpy(&McsCbw, pEP1, nCount); //copy data from OEPx X or Y buffer + + //clear NAK, EP ready to receive data + *MscWriteControl.pCT1 = 0x00; + + //set flag and check the CBW from the usbmsc_poll + MscState.bMscCbwReceived = TRUE; + + //second 64b buffer will be not read out here because the CBW is <64 bytes + } + + bWakeUp = TRUE; //wake up to perform CBW + return (bWakeUp); + } + + //if we are here - LBAs will be received + if (MscControl[sRwbuf.lun].yBufferAddr == NULL) { + + /*Check if there are any pending LBAs to process */ + if (MscWriteControl.dwBytesToReceiveLeft > 0){ + //read one chunk of 64 bytes + + //check what is current buffer: X or Y + if (MscWriteControl.bCurrentBufferXY == X_BUFFER){ //X is current buffer + //this is the active EP buffer + pEP1 = (uint8_t*)stUsbHandle[MSC0_INTFNUM].oep_X_Buffer; + MscWriteControl.pCT1 = + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX; + + //second EP buffer + MscWriteControl.pEP2 = + (uint8_t*)stUsbHandle[MSC0_INTFNUM].oep_Y_Buffer; + MscWriteControl.pCT2 = + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY; + } else { + //this is the active EP buffer + pEP1 = (uint8_t*)stUsbHandle[MSC0_INTFNUM].oep_Y_Buffer; + MscWriteControl.pCT1 = + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY; + + //second EP buffer + MscWriteControl.pEP2 = + (uint8_t*)stUsbHandle[MSC0_INTFNUM].oep_X_Buffer; + MscWriteControl.pCT2 = + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX; + } + + //how many byte we can get from one endpoint buffer + nTmp1 = *MscWriteControl.pCT1; + + if ((nTmp1 & EPBCNT_NAK) && + (MscWriteControl.wFreeBytesLeft >= 64)){ + //copy data from Endpoint + MscCopyUsbToBuff(pEP1, MscWriteControl.pCT1); + + nTmp1 = *MscWriteControl.pCT2; + + //try read data from second buffer + if ((MscWriteControl.dwBytesToReceiveLeft > 0) && //do we have more data to send? + (MscWriteControl.wFreeBytesLeft >= 64) && + (nTmp1 & EPBCNT_NAK)){ //if the second buffer has received data? + //copy data from Endpoint + MscCopyUsbToBuff(MscWriteControl.pEP2, MscWriteControl.pCT2); + //MscWriteControl.pCT1 = MscWriteControl.pCT2; + } + + if ((MscWriteControl.wFreeBytesLeft == 0) || //user's buffer is full, give it to User + (MscWriteControl.dwBytesToReceiveLeft == 0)){ //or no bytes to read left - give it to User + sRwbuf.operation = kUSBMSC_WRITE; + sRwbuf.lba = MscWriteControl.lba; //copy lba number + MscWriteControl.lba += MscWriteControl.lbaCount; + sRwbuf.lbCount = MscWriteControl.lbaCount; //copy lba count + MscWriteControl.wCurrentByte = 0; + MscWriteControl.lbaCount = 0; + + //call event handler, we are ready with data + bWakeUp = USBMSC_handleBufferEvent(); + } //if (wFreeBytesLeft == 0) + } + } //if (MscWriteControl.dwBytesToReceiveLeft > 0) + else { + //perform error handling here, if required. + bWakeUp = TRUE; + } + } + else { + //if we are here - LBAs will be received + if (sRwbuf.bufferProcessed == 1) { + if (sRwbuf.XorY == 0) { + sRwbuf.xBufFull = 0; + if (sRwbuf.yBufFull) { + sRwbuf.bufferProcessed = 0; + sRwbuf.XorY = 1; + sRwbuf.bufferAddr = MscControl[McsCbw.bCBWLUN].yBufferAddr; + sRwbuf.operation = kUSBMSC_WRITE; + sRwbuf.lba = sRwbuf.ylba; //copy lba number + sRwbuf.lbCount = sRwbuf.ylbaCount; //copy lba count + + //call event handler, we are ready with data + bWakeUp = USBMSC_handleBufferEvent(); + } + } + else { + sRwbuf.yBufFull = 0; + if (sRwbuf.xBufFull) { + sRwbuf.bufferProcessed = 0; + sRwbuf.XorY = 0; + sRwbuf.bufferAddr = MscControl[McsCbw.bCBWLUN].xBufferAddr; + sRwbuf.operation = kUSBMSC_WRITE; + sRwbuf.lba = sRwbuf.xlba; //copy lba number + sRwbuf.lbCount = sRwbuf.xlbaCount; //copy lba count + + //call event handler, we are ready with data + bWakeUp = USBMSC_handleBufferEvent(); + } + } + } + + /*Check if there are any pending LBAs to process */ + if (MscWriteControl.dwBytesToReceiveLeft > 0){ + //read one chunk of 64 bytes + + if (MscWriteControl.wFreeBytesLeft == 0) { + if (MscWriteControl.XorY == 0) { + if (sRwbuf.yBufFull == 0) { + MscWriteControl.lba += MscWriteControl.lbaCount; + MscWriteControl.wCurrentByte = 0; + MscWriteControl.lbaCount = 0; + MscWriteControl.pUserBuffer = MscControl[sRwbuf.lun].yBufferAddr; + MscWriteControl.XorY = 1; + MscWriteControl.wFreeBytesLeft = + MscControl[sRwbuf.lun].wMscUserBufferSize; + } + } + else { + if (sRwbuf.xBufFull == 0) { + MscWriteControl.lba += MscWriteControl.lbaCount; + MscWriteControl.wCurrentByte = 0; + MscWriteControl.lbaCount = 0; + MscWriteControl.pUserBuffer = MscControl[sRwbuf.lun].xBufferAddr; + MscWriteControl.XorY = 0; + MscWriteControl.wFreeBytesLeft = + MscControl[sRwbuf.lun].wMscUserBufferSize; + } + } + } + + + //check what is current buffer: X or Y + if (MscWriteControl.bCurrentBufferXY == X_BUFFER){ //X is current buffer + //this is the active EP buffer + pEP1 = (uint8_t*)stUsbHandle[MSC0_INTFNUM].oep_X_Buffer; + MscWriteControl.pCT1 = + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX; + + //second EP buffer + MscWriteControl.pEP2 = + (uint8_t*)stUsbHandle[MSC0_INTFNUM].oep_Y_Buffer; + MscWriteControl.pCT2 = + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY; + } else { + //this is the active EP buffer + pEP1 = (uint8_t*)stUsbHandle[MSC0_INTFNUM].oep_Y_Buffer; + MscWriteControl.pCT1 = + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY; + + //second EP buffer + MscWriteControl.pEP2 = + (uint8_t*)stUsbHandle[MSC0_INTFNUM].oep_X_Buffer; + MscWriteControl.pCT2 = + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX; + } + + //how many byte we can get from one endpoint buffer + nTmp1 = *MscWriteControl.pCT1; + + if ((nTmp1 & EPBCNT_NAK) && + (MscWriteControl.wFreeBytesLeft >= 64)){ + //copy data from Endpoint + MscCopyUsbToBuff(pEP1, MscWriteControl.pCT1); + + nTmp1 = *MscWriteControl.pCT2; + + //try read data from second buffer + if ((MscWriteControl.dwBytesToReceiveLeft > 0) && //do we have more data to send? + (MscWriteControl.wFreeBytesLeft >= 64) && + (nTmp1 & EPBCNT_NAK)){ //if the second buffer has received data? + //copy data from Endpoint + MscCopyUsbToBuff(MscWriteControl.pEP2, MscWriteControl.pCT2); + //MscWriteControl.pCT1 = MscWriteControl.pCT2; + } + + if ((MscWriteControl.wFreeBytesLeft == 0) || //user's buffer is full, give it to User + (MscWriteControl.dwBytesToReceiveLeft == 0)){ //or no bytes to read left - give it to User + + if (sRwbuf.firstFlag == 0) { + sRwbuf.firstFlag = 1; + sRwbuf.operation = kUSBMSC_WRITE; + sRwbuf.lba = MscWriteControl.lba; //copy lba number + sRwbuf.lbCount = MscWriteControl.lbaCount; //copy lba count + + //call event handler, we are ready with data + bWakeUp = USBMSC_handleBufferEvent(); + } + if (MscWriteControl.XorY == 0) { + sRwbuf.xBufFull = 1; + sRwbuf.xlba = MscWriteControl.lba; + sRwbuf.xlbaCount = MscWriteControl.lbaCount; + } + else { + sRwbuf.yBufFull = 1; + sRwbuf.ylba = MscWriteControl.lba; + sRwbuf.ylbaCount = MscWriteControl.lbaCount; + } + return (TRUE); + } //if (wFreeBytesLeft == 0) + } + } //if (MscWriteControl.dwBytesToReceiveLeft > 0) + else { + if (sRwbuf.xBufFull ==0 && sRwbuf.yBufFull == 0) { + MscWriteControl.pUserBuffer = NULL; //no more receiving pending + MscWriteControl.bWriteProcessing = FALSE; //ready to receive next CBW + } + bWakeUp = TRUE; + } + } + return (bWakeUp); +} + +// +//! \endcond +// + +//***************************************************************************** +// +//! This function should be called by the application after it has processed a buffer request. +//! +//! \param USBMSC_Rwbuf_Info*RWBufInfo Pass the value received from USBMSC_fetchInfoStruct(). +//! +//! This function should be called by the application after it has processed a buffer request. It +//! indicates to the API that the application has fulfilled the request. +//! Prior to calling this function, the application needs to write a return code to rwInfo.returnCode. +//! This code should reflect the result of the operation. The value may come from the file system +//! software, depending on the application. See Sec. 8.3.6 of +//! \e "Programmer's Guide: MSP430 USB API Stack for CDC/PHDC/HID/MSC" for a list of valid return codes. +//! +//! \return \b kUSB_succeed +// +//***************************************************************************** + +uint8_t USBMSC_bufferProcessed () +{ + uint16_t stateIn, stateOut; + uint8_t edbIndex; + + edbIndex = stUsbHandle[MSC0_INTFNUM].edb_Index; + stateIn = usbDisableInEndpointInterrupt(edbIndex); + stateOut = usbDisableOutEndpointInterrupt(edbIndex); + + if (MscControl[sRwbuf.lun].yBufferAddr == NULL) { + /* + * Fix for SDOCM00078384 + * Reset bWriteProcessing after last buffer is processed by the application + */ + if (sRwbuf.operation == kUSBMSC_WRITE && + MscWriteControl.dwBytesToReceiveLeft == 0){ //the Receive opereation (MSC_WRITE) is completed + MscWriteControl.pUserBuffer = NULL; //no more receiving pending + MscWriteControl.bWriteProcessing = FALSE; //ready to receive next CBW + } + + if (sRwbuf.operation == kUSBMSC_WRITE && sRwbuf.returnCode == + kUSBMSC_RWSuccess){ + //initialize user buffer. + MscWriteControl.pUserBuffer = MscControl[sRwbuf.lun].xBufferAddr; + MscWriteControl.wFreeBytesLeft = + MscControl[sRwbuf.lun].wMscUserBufferSize; + sRwbuf.operation = NULL; //no operation pending... + //read out next portion of data if available. + MSCFromHostToBuffer(); + } else if (sRwbuf.operation == kUSBMSC_READ && sRwbuf.returnCode == + kUSBMSC_RWSuccess){ + uint16_t wCnt = sRwbuf.lbCount * MscControl[sRwbuf.lun].lbaSize; + + //trigger sending LBA(s) + MscSendData(sRwbuf.bufferAddr, wCnt); + + if (sRwbuf.lbCount >= MscReadControl.lbaCount){ + //all bytes sent, reset structure + MscReadControl.lbaCount = 0; + } else { + //update read structure + MscReadControl.lbaCount -= sRwbuf.lbCount; + MscReadControl.lba += sRwbuf.lbCount; + + } + sRwbuf.operation = NULL; //no operation pending... + } + } + else { + if (sRwbuf.operation == kUSBMSC_WRITE && sRwbuf.returnCode == + kUSBMSC_RWSuccess){ + //initialize user buffer. + sRwbuf.bufferProcessed = 1; + if (sRwbuf.XorY == 0) { + sRwbuf.xBufFull = 0; + } + else { + sRwbuf.yBufFull = 0; + } + sRwbuf.operation = NULL; //no operation pending... + //read out next portion of data if available. + MSCFromHostToBuffer(); + } else if (sRwbuf.operation == kUSBMSC_READ && sRwbuf.returnCode == + kUSBMSC_RWSuccess){ + uint16_t wCnt = sRwbuf.lbCount * MscControl[sRwbuf.lun].lbaSize; + + sRwbuf.bufferProcessed = 1; + + if (sRwbuf.XorY == 0) { + sRwbuf.xBufFull = 1; + sRwbuf.xWordCnt = wCnt; + } + else { + sRwbuf.yBufFull = 1; + sRwbuf.yWordCnt = wCnt; + } + + if (sRwbuf.firstFlag == 0) { + //trigger sending LBA(s) + sRwbuf.firstFlag = 1; + MscSendData(sRwbuf.bufferAddr, wCnt); + } + else { + edbIndex = stUsbHandle[MSC0_INTFNUM].edb_Index; + //trigger Endpoint Interrupt - to start send operation + USBIEPIFG |= 1 << (edbIndex + 1); //IEPIFGx; + } + + if (sRwbuf.lbCount >= MscReadControl.lbaCount){ + //all bytes sent, reset structure + MscReadControl.lbaCount = 0; + sRwbuf.operation = NULL; + } else { + //update read structure + MscReadControl.lbaCount -= sRwbuf.lbCount; + MscReadControl.lba += sRwbuf.lbCount; + } + sRwbuf.operation = NULL; //no operation pending... + } + } + + switch (sRwbuf.returnCode) + { + case kUSBMSC_RWSuccess: + MscState.Scsi_Residue = 0; + Reset_RequestSenseResponse(); + break; + //Set RequestSenseResponse if necessary? Maybe initialized values OK? + + case kUSBMSC_RWNotReady: + MscState.Scsi_Status = SCSI_FAILED; + MscState.Scsi_Residue = 1; + Reset_RequestSenseResponse(); + RequestSenseResponse.VALID = 1; + RequestSenseResponse.SenseKey = S_NOT_READY; + RequestSenseResponse.ASC = ASC_NOT_READY; + RequestSenseResponse.ASCQ = ASCQ_NOT_READY; + break; + + case kUSBMSC_RWIllegalReq: + MscState.Scsi_Status = SCSI_FAILED; + MscState.Scsi_Residue = 0; + Reset_RequestSenseResponse(); + RequestSenseResponse.VALID = 1; + RequestSenseResponse.SenseKey = S_ILLEGAL_REQUEST; + RequestSenseResponse.ASC = ASC_ILLEGAL_REQUEST; + RequestSenseResponse.ASCQ = ASCQ_ILLEGAL_REQUEST; + break; + + case kUSBMSC_RWUnitAttn: + MscState.Scsi_Status = SCSI_FAILED; + MscState.Scsi_Residue = 0; + Reset_RequestSenseResponse(); + RequestSenseResponse.VALID = 1; + RequestSenseResponse.SenseKey = S_UNITATTN; + RequestSenseResponse.ASC = ASC_UNITATTN_READY_NOTREADY; + RequestSenseResponse.ASCQ = ASCQ_UNITATTN_READY_NOTREADY; + break; + + case kUSBMSC_RWLbaOutOfRange: + MscState.Scsi_Status = SCSI_FAILED; + MscState.Scsi_Residue = 0; + Reset_RequestSenseResponse(); + RequestSenseResponse.VALID = 1; + RequestSenseResponse.SenseKey = S_ILLEGAL_REQUEST; + RequestSenseResponse.ASC = ASC_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; + RequestSenseResponse.ASCQ = ASCQ_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; + break; + + case kUSBMSC_RWMedNotPresent: + MscState.Scsi_Status = SCSI_FAILED; + MscState.Scsi_Residue = 0; + Reset_RequestSenseResponse(); + RequestSenseResponse.VALID = 1; + RequestSenseResponse.SenseKey = S_NOT_READY; + RequestSenseResponse.ASC = ASC_MEDIUM_NOT_PRESENT; + RequestSenseResponse.ASCQ = ASCQ_MEDIUM_NOT_PRESENT; + break; + + case kUSBMSC_RWDevWriteFault: + MscState.Scsi_Status = SCSI_FAILED; + MscState.Scsi_Residue = 0; + Reset_RequestSenseResponse(); + RequestSenseResponse.VALID = 1; + RequestSenseResponse.SenseKey = S_MEDIUM_ERROR; + RequestSenseResponse.ASC = ASC_WRITE_FAULT; + RequestSenseResponse.ASCQ = ASCQ_WRITE_FAULT; + break; + + case kUSBMSC_RWUnrecoveredRead: + MscState.Scsi_Status = SCSI_FAILED; + MscState.Scsi_Residue = 0; + Reset_RequestSenseResponse(); + RequestSenseResponse.VALID = 1; + RequestSenseResponse.SenseKey = S_MEDIUM_ERROR; + RequestSenseResponse.ASC = ASC_UNRECOVERED_READ; + RequestSenseResponse.ASCQ = ASCQ_UNRECOVERED_READ; + break; + + case kUSBMSC_RWWriteProtected: + MscState.Scsi_Status = SCSI_FAILED; + MscState.Scsi_Residue = 0; + Reset_RequestSenseResponse(); + RequestSenseResponse.VALID = 1; + RequestSenseResponse.SenseKey = S_WRITE_PROTECTED; + RequestSenseResponse.ASC = ASC_WRITE_PROTECTED; + RequestSenseResponse.ASCQ = ASCQ_WRITE_PROTECTED; + break; + //case breakouts for all the codes + } + + if (sRwbuf.returnCode != kUSBMSC_RWSuccess){ + sRwbuf.operation = NULL; //no operation pending... + if (McsCbw.bmCBWFlags == DIRECTION_IN){ + usbStallInEndpoint(MSC0_INTFNUM); + MscReadControl.bReadProcessing = FALSE; //ready to receive next CBW + MscReadControl.pUserBuffer = NULL; //no more receiving pending + MscReadControl.lbaCount = 0; + } else { + //we need to stall only if not all af data was transfered + if (MscWriteControl.dwBytesToReceiveLeft > 0){ + usbStallOutEndpoint(MSC0_INTFNUM); + } + MscWriteControl.bWriteProcessing = FALSE; //ready to receive next CBW + MscWriteControl.pUserBuffer = NULL; //no more receiving pending + *MscWriteControl.pCT1 = 0x00; //clear NAK, EP ready to receive next data + *MscWriteControl.pCT2 = 0x00; //clear NAK, EP ready to receive next data + } + } + + usbRestoreInEndpointInterrupt(stateIn); + usbRestoreOutEndpointInterrupt(stateOut); + return (kUSB_succeed); +} + +// +//! \cond +// + +//------------------------------------------------------------------------------------------- +void Msc_ResetFlags () +{ + MscState.bMscCbwReceived = FALSE; +} + +//------------------------------------------------------------------------------------------- +void Msc_ResetStruct () +{ + memset(&sRwbuf,0,sizeof(USBMSC_RWbuf_Info)); + memset(&McsCsw,0,sizeof(CSW)); + + MscReadControl.pUserBuffer = NULL; + MscReadControl.dwBytesToSendLeft = 0; + MscReadControl.bReadProcessing = FALSE; + + MscWriteControl.bWriteProcessing = FALSE; + MscWriteControl.pUserBuffer = NULL; + MscWriteControl.dwBytesToReceiveLeft = 0; //holds how many bytes is still requested by WRITE operation (Host to MSP430) + //we do not reset the bCurrentBufferXY, becuase the buffer doesnt changed if he MSC reseted. + //The bCurrentBufferXY should be reseted in USB_Reset() + + Reset_RequestSenseResponse(); +} + +//------------------------------------------------------------------------------------------- +void MscResetData () +{ + Msc_ResetStruct(); + + memset(&MscWriteControl, 0, sizeof(MscWriteControl)); + memset(&MscReadControl, 0, sizeof(MscReadControl)); +} + +//------------------------------------------------------------------------------------------- +void MscResetCtrlLun () +{ + int16_t i; + + for (i = 0; i < MSC_MAX_LUN_NUMBER; i++) + { + MscControl[i].bMediaPresent = 0x80; + MscControl[i].bWriteProtected = FALSE; + } +} + +//------------------------------------------------------------------------------------------- +/* This function can be called by application to get the current status of stack operation */ +uint8_t USBMSC_getState () +{ + uint8_t state; + + if (sRwbuf.operation == 0 && MscState.bMscSendCsw == FALSE){ + state = kUSBMSC_idle; + } else if (sRwbuf.operation == kUSBMSC_READ && sRwbuf.lbCount > 0){ + state = kUSBMSC_readInProgress; + } else if (sRwbuf.operation == kUSBMSC_WRITE && sRwbuf.lbCount > 0){ + state = kUSBMSC_writeInProgress; + } else if (sRwbuf.operation == 0 && MscState.bMscSendCsw == TRUE){ + state = kUSBMSC_cmdBeingProcessed; + } + return (state); +} + +// +//! \endcond +// + +//***************************************************************************** +// +//! Informs the API of the Current State of the Media on LUN \b lun. +//! +//! \param lun is the logical unit (LUN) on which the operation is taking place. Zero-based. (This version of the API +//! only supports a single LUN.) +//! \param info is a structure that communicates the most recent information about the medium. +//! +//! Informs the API of the current state of the media on LUN \b lun. It does this using an instance \b info +//! of the API-defined structure USBMSC_mediaInfoStr. The API uses the information in the most +//! recent call to this function in automatically handling certain requests from the host. +//! In LUNs that are marked as not removable in USBMSC_CONFIG, this function should be called +//! once at the beginning of execution, prior to attachment to the USB host. It then no longer needs +//! to be called. +//! +//! In LUNS that are marked as removable, the media information is dynamic. The function should +//! still be called at the beginning of execution to indicate the initial state of the media, and then it +//! should also be called every time the media changes. +//! +//! See Sec. 8.3.4 of \e "Programmer's Guide: MSP430 USB API Stack for CDC/PHDC/HID/MSC" for more about informing +//! the API of media changes. +//! +//! \return \b kUSB_succeed +// +//***************************************************************************** + +uint8_t USBMSC_updateMediaInfo ( uint8_t lun, struct USBMSC_mediaInfoStr *info) +{ + uint8_t state; + + Scsi_Read_Capacity_10[lun].lLba[0] = (uint8_t)(info->lastBlockLba >> 24); + Scsi_Read_Capacity_10[lun].lLba[1] = (uint8_t)(info->lastBlockLba >> 16); + Scsi_Read_Capacity_10[lun].lLba[2] = (uint8_t)(info->lastBlockLba >> 8); + Scsi_Read_Capacity_10[lun].lLba[3] = (uint8_t)(info->lastBlockLba); + + Scsi_Read_Capacity_10[lun].bLength[0] = (uint8_t)(info->bytesPerBlock >> 24); + Scsi_Read_Capacity_10[lun].bLength[1] = (uint8_t)(info->bytesPerBlock >> 16); + Scsi_Read_Capacity_10[lun].bLength[2] = (uint8_t)(info->bytesPerBlock >> 8); + Scsi_Read_Capacity_10[lun].bLength[3] = (uint8_t)(info->bytesPerBlock); + + MscControl[lun].lbaSize = (uint16_t)Scsi_Read_Capacity_10[lun].bLength[2] << + 8 | Scsi_Read_Capacity_10[lun].bLength[3]; + + //If the LUN was reported as not removable, then leave mediaPresent/mediaChanged as + //their initialized defaults. + if (USBMSC_config.LUN[lun].removable){ + if (((MscControl[lun].bMediaPresent == kUSBMSC_MEDIA_NOT_PRESENT)) && + (info->mediaPresent == kUSBMSC_MEDIA_PRESENT)){ //If media was inserted... + //Set Unit Attention flag. This flag is used in Scsi_Request_Sense(). + MscState.bUnitAttention = TRUE; + MscState.Scsi_Status = SCSI_FAILED; + } + + if ((MscControl[lun].bMediaPresent == kUSBMSC_MEDIA_PRESENT && + ((info->mediaPresent == kUSBMSC_MEDIA_NOT_PRESENT))) || //If media was removed... + ((info->mediaPresent == kUSBMSC_MEDIA_PRESENT) && + (info->mediaChanged))){ //Or if media still present, but has changed... + //Set Unit Attention flag. This flag is used in Scsi_Request_Sense(). + MscState.bUnitAttention = TRUE; + MscState.Scsi_Status = SCSI_FAILED; + state = USBMSC_getState(); + + if (state == kUSBMSC_readInProgress || state == + kUSBMSC_writeInProgress){ + if (McsCbw.bmCBWFlags == DIRECTION_IN){ + usbStallInEndpoint(MSC0_INTFNUM); + } else { + usbStallOutEndpoint(MSC0_INTFNUM); + } + + Msc_ResetStateMachine(); + Msc_ResetFlags(); + Msc_ResetStruct(); + MscState.isMSCConfigured = TRUE; + + Scsi_Send_CSW(MSC0_INTFNUM); + } + } + MscControl[lun].bMediaPresent = info->mediaPresent; + } + + MscControl[lun].bWriteProtected = info->writeProtected; + return (kUSB_succeed); +} + +//***************************************************************************** +// +//! Gives the API a Buffer to Use for READ/WRITE Data Transfer. +//! +//! \param lun is the Lun number. +//! \param *RWbuf_x is the address of an X-buffer. If null, then both buffers are de-activated. +//! \param *RWbuf_y is the address of an Y-buffer. (Double-buffering is not supported in this version of the API.) +//! \param size is the size, in bytes, of the buffers. +//! +//! Gives the API a buffer to use for READ/WRITE data transfer. \b size indicates the size of the +//! buffer, in bytes. +//! +//! \b NOTE: Currently, only single-buffering is supported, so \b RWbuf_y should be set to null. +//! If the application intends to allocate the buffer statically, then this function needs only to be +//! called once, prior to any READ/WRITE commands being received from the host. Most likely this +//! would happen during the application's initialization functions. +//! +//! \b NOTE: This API has to be called after the call to USBMSC_updateMediaInfo() at the beginning +//! of execution. +//! +//! However, this function optionally enables dynamic buffer management. That is, it can activate +//! and de-activate the buffer, by alternately assigning a null and valid address in \b RWbuf_x. This is +//! useful because the buffer uses a significant portion of the RAM resources (typically 512 bytes). +//! This memory is not needed when USB is not attached or suspended. +//! +//! If doing this, it's important that the application re-activate the buffer when USB becomes active +//! again, by issuing another call to the function, this time using valid buffer information. If the API +//! needs the buffer and doesn't have it, it will begin failing READ/WRITE commands from the host. +//! The re-activation can take place within USB_handleVbusOffEvent(). +//! +//! \b size must be a multiple of a block size - for FAT, a block size is typically 512 bytes. Thus +//! values of 512, 1024, 1536, etc. are valid. Non-multiples are not valid. +//! +//! The function returns \b kUSB_succeed every time. It is up to the application to ensure that the +//! buffers are valid. +//! +//! \return \b kUSB_succeed +// +//***************************************************************************** + +uint8_t USBMSC_registerBufInfo (uint8_t lun, uint8_t *RWbuf_x, uint8_t *RWbuf_y, uint16_t size) +{ + MscControl[lun].wMscUserBufferSize = 0; + MscControl[lun].xBufferAddr = NULL; + MscControl[lun].yBufferAddr = NULL; //this version supports only X buffer. + + //check if arguments are valid + if ((size < MscControl[lun].lbaSize) || + (RWbuf_x == NULL)){ //Need at least one buffer + return (kUSB_generalError); + } + + MscControl[lun].wMscUserBufferSize = size; + MscControl[lun].lbaBufCapacity = MscControl[lun].wMscUserBufferSize / + MscControl[lun].lbaSize; + MscControl[lun].xBufferAddr = RWbuf_x; + MscControl[lun].yBufferAddr = RWbuf_y; + return (kUSB_succeed); +} + +// +//! \cond +// + +//------------------------------------------------------------------------------------------- +void SET_RequestsenseNotReady () +{ + //Set REQUEST SENSE with "not ready" + Reset_RequestSenseResponse(); + RequestSenseResponse.VALID = 1; + RequestSenseResponse.SenseKey = S_NOT_READY; + RequestSenseResponse.ASC = ASC_NOT_READY; + RequestSenseResponse.ASCQ = ASCQ_NOT_READY; + //Send CSW with error status + MscState.Scsi_Status = SCSI_FAILED; +} + +//------------------------------------------------------------------------------------------- +void SET_RequestsenseMediaNotPresent () +{ + //Set REQUEST SENSE with "not ready" + Reset_RequestSenseResponse(); + RequestSenseResponse.VALID = 1; + RequestSenseResponse.SenseKey = S_NOT_READY; + RequestSenseResponse.ASC = ASC_MEDIUM_NOT_PRESENT; + RequestSenseResponse.ASCQ = ASCQ_MEDIUM_NOT_PRESENT; + //Send CSW with error status + MscState.Scsi_Status = SCSI_FAILED; +} + +//------------------------------------------------------------------------------------------- +void usbClearOEPByteCount (uint8_t intfNum) +{ + uint8_t edbIndex; + + edbIndex = stUsbHandle[intfNum].edb_Index; + tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX = 0; +} + +//------------------------------------------------------------------------------------------- +void usbStallEndpoint (uint8_t intfNum) +{ + uint8_t edbIndex; + + edbIndex = stUsbHandle[intfNum].edb_Index; + tOutputEndPointDescriptorBlock[edbIndex].bEPCNF |= EPCNF_STALL; + tInputEndPointDescriptorBlock[edbIndex].bEPCNF |= EPCNF_STALL; +} + +//------------------------------------------------------------------------------------------- +void usbStallInEndpoint (uint8_t intfNum) +{ + uint8_t edbIndex; + + edbIndex = stUsbHandle[intfNum].edb_Index; + tInputEndPointDescriptorBlock[edbIndex].bEPCNF |= EPCNF_STALL; +} + +//------------------------------------------------------------------------------------------- +void usbStallOutEndpoint (uint8_t intfNum) +{ + uint8_t edbIndex; + + edbIndex = stUsbHandle[intfNum].edb_Index; + tOutputEndPointDescriptorBlock[edbIndex].bEPCNF |= EPCNF_STALL; + MscState.stallEndpoint = TRUE; +} + +// +//! \endcond +// + +//***************************************************************************** +// +//! Returns a pointer to the \b USBMSC_Rwbuf_Info structure instance maintained within the API. +//! +//! Returns a pointer to the \b USBMSC_Rwbuf_Info structure instance maintained within the API. +//! See Sec. 8.3.6 of \e "Programmer's Guide: MSP430 USB API Stack for CDC/PHDC/HID/MSC" for information on using +//! this structure. +//! This function should be called prior to USB enumeration; that is, prior to calling USB_connect(). +//! +//! \return A pointer to an application-allocated instance of \b USBMSC_RWBuf_Info, +//! which will be used to exchange information related to buffer requests from +//! the API to the application. +// +//***************************************************************************** + +USBMSC_RWbuf_Info* USBMSC_fetchInfoStruct (void) +{ + return (&sRwbuf); +} + +// +//! \cond +// + +#ifdef CDROM_SUPPORT +//---------------------------------------------------------------------------- + +void Scsi_Read_TocPmaAtip(uint8_t intfNum) +{ + if(McsCbw.CBWCB[2] & 0x01) { + + if (SUCCESS != + MscSendData( (uint8_t*)&Scsi_Read_TOC_PMA_ATIP_F1[McsCbw.bCBWLUN], + Scsi_Read_TOC_PMA_ATIP_F1_LEN)){ + MscState.Scsi_Status = SCSI_FAILED; + } + } else { + + if (SUCCESS != + MscSendData( (uint8_t*)&Scsi_Read_TOC_PMA_ATIP_F2[McsCbw.bCBWLUN], + Scsi_Read_TOC_PMA_ATIP_F2_LEN)){ + MscState.Scsi_Status = SCSI_FAILED; + } + } +} + +void Scsi_Get_Configuration(uint8_t intfNum) { + + if (FAILURE == Check_CBW(intfNum,DIRECTION_IN,SCSI_GET_CONFIGURATION_LEN)){ + return; + } + + if (SUCCESS != + MscSendData( (uint8_t*)&Scsi_Get_Configuration_Descriptor[McsCbw.bCBWLUN], + SCSI_GET_CONFIGURATION_LEN)){ + MscState.Scsi_Status = SCSI_FAILED; + } +} + +void Scsi_Event_Status_Notification(uint8_t intfNum) { + + if (FAILURE == Check_CBW(intfNum,DIRECTION_IN,SCSI_EVENT_STATUS_LEN)){ + return; + } + if (SUCCESS != + MscSendData( (uint8_t*)&Scsi_Event_Status_Descriptor[McsCbw.bCBWLUN], + SCSI_EVENT_STATUS_LEN)){ + MscState.Scsi_Status = SCSI_FAILED; + } +} + +void Scsi_Read_Disc_Information(uint8_t intfNum) { + + + if (FAILURE == Check_CBW(intfNum,DIRECTION_IN,SCSI_READ_DISC_INFORMATION_LEN)){ + return; + } + if (SUCCESS != + MscSendData( (uint8_t*)&Scsi_Disc_Information_Descriptor[McsCbw.bCBWLUN], + SCSI_READ_DISC_INFORMATION_LEN)){ + MscState.Scsi_Status = SCSI_FAILED; + } +} + +#endif + +#endif //_MSC_ + +// +//! \endcond +// + +/*----------------------------------------------------------------------------+ + | End of source file | + +----------------------------------------------------------------------------*/ +/*------------------------ Nothing Below This Line --------------------------*/ +//Released_Version_4_10_02 diff --git a/source/USB_API/USB_MSC_API/UsbMscScsi.h b/source/USB_API/USB_MSC_API/UsbMscScsi.h new file mode 100644 index 0000000..1b7348b --- /dev/null +++ b/source/USB_API/USB_MSC_API/UsbMscScsi.h @@ -0,0 +1,326 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +/* + * ======== UsbMscScsi.h ======== + */ +#include + +#ifndef _UMSC_SCSI_H_ +#define _UMSC_SCSI_H_ + +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +/*Macros for CBW, CSW signatures */ +#define CBW_SIGNATURE 0x43425355u +#define CSW_SIGNATURE 0x53425355u + +/*CBW, CSW length in bytes */ +#define CBW_LENGTH 31 +#define CSW_LENGTH 13 + +/*SCSI Commands - Mandatory only implemented */ +#define SCSI_TEST_UNIT_READY 0x00 +#define SCSI_REQUEST_SENSE 0x03 +#define SCSI_INQUIRY 0x12 +#define SCSI_MODE_SENSE_6 0x1A +#define SCSI_MODE_SENSE_10 0x5A +#define SCSI_READ_CAPACITY_10 0x25 +#define SCSI_READ_10 0x28 +#define SCSI_WRITE_10 0x2A +#define SCSI_READ_FORMAT_CAPACITIES 0x23 +#define SCSI_MODE_SELECT_6 0x15 +#define SCSI_MODE_SELECT_10 0x55 +#define PREVENT_ALLW_MDM 0x1E +#define START_STOP_UNIT 0x1B +#define SCSI_REPORT_LUNS 0xA0 +#define SCSI_VERIFY 0x2F + +#define SCSI_READ_TOC_PMA_ATIP 0x43 +#define Scsi_Read_TOC_PMA_ATIP_F1_LEN 20 +#define Scsi_Read_TOC_PMA_ATIP_F2_LEN 48 +#define SCSI_GET_CONFIGURATION 0x46 +#define SCSI_GET_CONFIGURATION_LEN 4 +#define SCSI_EVENT_STATUS 0x4A +#define SCSI_EVENT_STATUS_LEN 8 +#define SCSI_READ_DISC_INFORMATION 0x51 +#define SCSI_SET_CD_SPEED 0xBB +#define SCSI_READ_DISC_INFORMATION_LEN 36 + +/*SCSI Status codes. Used in CSW response */ +#define SCSI_PASSED 0 +#define SCSI_FAILED 1 +#define SCSI_PHASE_ERROR 2 +#define SCSI_READWRITE_FAIL 2 + +#define kUSBMSC_RWSuccess 0 +#define kUSBMSC_RWNotReady 1 +#define kUSBMSC_RWIllegalReq 2 +#define kUSBMSC_RWUnitAttn 3 +#define kUSBMSC_RWLbaOutOfRange 4 +#define kUSBMSC_RWMedNotPresent 5 +#define kUSBMSC_RWDevWriteFault 6 +#define kUSBMSC_RWUnrecoveredRead 7 +#define kUSBMSC_RWWriteProtected 8 + + +/* Macros to indicate READ or WRITE operation */ +#define kUSBMSC_READ 1 +#define kUSBMSC_WRITE 2 + +#define kUSBMSC_MEDIA_PRESENT 0x81 +#define kUSBMSC_MEDIA_NOT_PRESENT 0x82 + +#define kUSBMSC_WRITE_PROTECTED 0x00 + +/* Defines for MSC SCSI State-Machine */ +#define MSC_READY 0x00 +#define MSC_COMMAND_TRANSPORT 0x01 +#define MSC_DATA_IN 0x02 +#define MSC_DATA_OUT 0x03 +#define MSC_STATUS_TRANSPORT 0x04 +#define MSC_DATA 0x05 +#define MSC_WAIT4RESET 0x06 + +/*Lengths of SCSI commands(in bytes) */ +#define SCSI_SCSI_INQUIRY_CMD_LEN 36 +#define SCSI_READ_CAPACITY_CMD_LEN 8 +#define SCSI_MODE_SENSE_6_CMD_LEN 4 +#define SCSI_MODE_SENSE_10_CMD_LEN 8 +#define SCSI_REQ_SENSE_CMD_LEN 18 +#define SCSI_READ_FORMAT_CAPACITY_CMD_LEN 12 +#define SCSI_REPORT_LUNS_CMD_LEN 16 + +/*----------------------------------------------------------------------------+ + | Type defines and structures | + +----------------------------------------------------------------------------*/ +/*CBW Structure */ +typedef struct { + uint32_t dCBWSignature; + uint32_t dCBWTag; + uint32_t dCBWDataTransferLength; + uint8_t bmCBWFlags; + uint8_t bCBWLUN; + uint8_t bCBWCBLength; + uint8_t CBWCB[16]; +} CBW, *pCBW; + +/*CSW structure */ +typedef struct { + uint32_t dCSWSignature; + uint32_t dCSWTag; + uint32_t dCSWDataResidue; + uint8_t bCSWStatus; +} CSW, *pCSW; + +/*Request Response union(Required for Request sense command) */ +typedef struct { + uint8_t ResponseCode : 7; + uint8_t VALID : 1; + uint8_t Obsolete; + uint8_t SenseKey : 4; + uint8_t Resv : 1; + uint8_t ILI : 1; + uint8_t EOM : 1; + uint8_t FILEMARK : 1; + uint8_t Information[4]; + uint8_t AddSenseLen; + uint8_t CmdSpecificInfo[4]; + uint8_t ASC; + uint8_t ASCQ; + uint8_t FRUC; + uint8_t SenseKeySpecific[3]; + uint8_t padding[14]; /* padding to cover case where host requests 24 bytes of sense data */ +} REQUEST_SENSE_RESPONSE; + +/*Read capacity union(Required for READ CAPACITY command)*/ +typedef struct { + uint32_t Last_LBA; + uint8_t Resv; + uint8_t Size_LBA[3]; +} SCSI_READ_CAPACITY; + +/*Structure internal to stack for holding LBA,buffer addr etc information*/ +typedef struct { + //uint8_t intfNum; + uint8_t lun; + uint8_t operation; + uint32_t lba; + uint8_t lbCount; + uint8_t *bufferAddr; + uint8_t returnCode; + uint8_t XorY; + uint8_t xBufFull; + uint16_t xWordCnt; + uint8_t yBufFull; + uint16_t yWordCnt; + uint8_t bufferProcessed; + uint8_t firstFlag; + uint32_t xlba; + uint8_t xlbaCount; + uint32_t ylba; + uint8_t ylbaCount; + +}USBMSC_RWbuf_Info; + +/*Media info structure */ +struct USBMSC_mediaInfoStr { + uint32_t lastBlockLba; + uint32_t bytesPerBlock; + uint8_t mediaPresent; + uint8_t mediaChanged; + uint8_t writeProtected; +}; + +/*Lun entry Structures */ +struct _LUN_entry_struct { + uint8_t number; + uint8_t PDT; + uint8_t removable; + char t10VID[8]; + char t10PID[16]; + char t10rev[4]; +}; + +struct config_struct { + struct _LUN_entry_struct LUN[MSC_MAX_LUN_NUMBER]; +}; + +struct _Report_Luns { + uint8_t LunListLength[4]; + uint8_t Reserved[4]; + uint8_t LunList1[8]; +}; + +struct _Scsi_Read_Capacity { + uint8_t lLba[4]; //Last logical block address + uint8_t bLength[4]; //Block length, in this case 0x200 = 512 bytes for each Logical Block +}; + +//structure for controlling WRITE phase (HOST to MSP430) +struct _MscWriteControl { + uint32_t dwBytesToReceiveLeft; //holds how many bytes is still requested by WRITE operation: + //Host to MSP430. + uint16_t wFreeBytesLeft; //free bytes left in UserBuffer + uint32_t lba; //holds the current LBA number. This is the first LBA in the UserBuffer + uint8_t *pUserBuffer; //holds the current position of user's receiving buffer. + //If NULL- no receiving operation started + uint16_t wCurrentByte; //how many bytes in current LBA are received + uint16_t lbaCount; //how many LBA we have received in current User Buffer + uint8_t * pCT1; //holds current EPBCTxx register + uint8_t * pCT2; //holds next EPBCTxx register + uint8_t * pEP2; //holds addr of the next EP buffer + uint8_t bCurrentBufferXY; //indicates which buffer is used by host to transmit data via OUT + uint8_t bWriteProcessing; //indicated if the current state is DATA WRITE phase or CBW receiwing + uint8_t XorY; +}; + +//structure for controlling READ phase (MSP430 to HOST) +struct _MscReadControl { + uint32_t dwBytesToSendLeft; //holds how many bytes is still requested by WRITE operation (Host to MSP430) + uint8_t *pUserBuffer; //holds the current position of user's receiving buffer. + //If NULL- no receiving operation started + uint32_t lba; //holds the current LBA number. This is the first LBA in the UserBuffer. + uint8_t * pCT1; //holds current EPBCTxx register + uint8_t * pCT2; //holds next EPBCTxx register + uint8_t * pEP2; //holds addr of the next EP buffer + uint16_t lbaCount; //how many LBA we have to send to Host + uint8_t bCurrentBufferXY; //indicates which buffer is used by host to transmit data via OUT + uint8_t bReadProcessing; //indicated if the current state is DATA READ phase or CSW sending + //initiated by McsDataSend() + uint8_t XorY; +}; + +//structure for common control of MSC stack +struct _MscControl { + uint16_t wMscUserBufferSize; + uint16_t lbaSize; //limitid to uint16_t, but could be increased if required. + uint8_t lbaBufCapacity; //how many LBAs (max) contains UserBuffer for read/write operation (>=1) + uint8_t *xBufferAddr; + uint8_t *yBufferAddr; + uint8_t bMediaPresent; + uint8_t bWriteProtected; +}; + +struct _MscState { + volatile uint32_t Scsi_Residue; + volatile uint8_t Scsi_Status; /*Variable to track command status */ + int16_t bMcsCommandSupported; /*Flag to indicate read/write command is recieved from host */ + int16_t bMscCbwReceived; /*Flag to inidicate whether any CBW recieved from host*/ + int16_t bMscSendCsw; + int16_t isMSCConfigured; + uint8_t bUnitAttention; + uint8_t bMscCbwFailed; + uint8_t bMscResetRequired; + uint8_t stallEndpoint; + uint8_t stallAtEndofTx; +}; + +extern struct _MscWriteControl MscWriteControl; +extern struct _MscReadControl MscReadControl; +extern struct _MscControl MscControl[]; + +/*----------------------------------------------------------------------------+ + | Extern Variables | + +----------------------------------------------------------------------------*/ + +extern CBW cbw; +extern CSW csw; +extern REQUEST_SENSE_RESPONSE RequestSenseResponse; + +/*----------------------------------------------------------------------------+ + | Function Prototypes | + +----------------------------------------------------------------------------*/ + +/*SCSI Wrapper functions */ +uint8_t Scsi_Cmd_Parser (uint8_t opcode); +uint8_t Scsi_Send_CSW (uint8_t intfNum); + +/*Function to reset MSC SCSI state machine */ +void Msc_ResetStateMachine(void); +void Msc_ResetFlags(void); +void Msc_ResetStruct(void); +void SET_RequestsenseNotReady(void); +void SET_RequestsenseMediaNotPresent(void); +void MscResetCtrlLun(void); + +USBMSC_RWbuf_Info* USBMSC_fetchInfoStruct(void); +#ifdef __cplusplus +} +#endif +#endif //_MSC_SCSI_H_ + +//Released_Version_4_10_02 diff --git a/source/USB_API/USB_MSC_API/UsbMscStateMachine.c b/source/USB_API/USB_MSC_API/UsbMscStateMachine.c new file mode 100644 index 0000000..a4ef22c --- /dev/null +++ b/source/USB_API/USB_MSC_API/UsbMscStateMachine.c @@ -0,0 +1,213 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +/** @file UsbMscStateMachine.c + * @brief Contains APIs related to MSC task Management. + */ +// +//! \cond +// + +/* + * ======== UsbMscStateMachine.c ======== + */ +/*File includes */ +#include "../USB_Common/device.h" +#include "../USB_Common/defMSP430USB.h" +#include "../USB_MSC_API/UsbMscScsi.h" +#include "../USB_MSC_API/UsbMsc.h" +#include "../USB_Common/usb.h" +#include +#include + +#ifdef _MSC_ + +/*Macros to indicate data direction */ +#define DIRECTION_IN 0x80 +#define DIRECTION_OUT 0x00 + +/*Buffer pointers passed by application */ +extern __no_init tEDB __data16 tInputEndPointDescriptorBlock[]; +extern struct _MscState MscState; + +uint8_t Scsi_Verify_CBW (); + +/*----------------------------------------------------------------------------+ + | Functions | + +----------------------------------------------------------------------------*/ +void Msc_ResetStateMachine (void) +{ + MscState.bMscSendCsw = FALSE; + MscState.Scsi_Residue = 0; + MscState.Scsi_Status = SCSI_PASSED; /*Variable to track command status */ + MscState.bMcsCommandSupported = TRUE; /*Flag to indicate read/write command is recieved from host */ + MscState.bMscCbwReceived = 0; /*Flag to inidicate whether any CBW recieved from host*/ + MscState.bMscSendCsw = FALSE; + MscState.isMSCConfigured = FALSE; + MscState.bUnitAttention = FALSE; + MscState.bMscCbwFailed = FALSE; + MscState.bMscResetRequired = FALSE; + MscState.stallEndpoint = FALSE; + MscState.stallAtEndofTx = FALSE; +} + +//---------------------------------------------------------------------------- +/*This is the core function called by application to handle the MSC SCSI state +* machine */ + +// +//! \endcond +// + +//***************************************************************************** +// +//! Checks to See if a SCSI Command has Been Received. +//! +//! Checks to see if a SCSI command has been received. If so, it handles it. If not, it returns +//! having taken no action. +//! The return values of this function are intended to be used with entry of low-power modes. If the +//! function returns \b kUSBMSC_okToSleep, then no further application action is required; that is, +//! either no SCSI command was received; one was received but immediately handled; or one was +//! received but the handling will be completed in the background by the API as it automatically +//! services USB interrupts. +//! If instead the function returns \b kUSBMSC_processBuffer, then the API is currently servicing a +//! SCSI READ or WRITE command, and the API requires the application to process a buffer. (See +//! Sec. 8.3.6 of \e "Programmer's Guide: MSP430 USB API Stack for CDC/PHDC/HID/MSC" for a discussion of buffer +//! processing.) +//! Note that even if the function returns these values, the values could potentially be outdated by +//! the time the application evaluates them. For this reason, it's important to disable interrupts prior +//! to calling this function. See Sec. 8.3.5 of \e "Programmer's Guide: MSP430 USB API Stack for CDC/PHDC/HID/MSC" +//! for more information. +//! +//! \return \b kUSBMSC_okToSleep or \b kUSBMSC_processBuffer +// +//***************************************************************************** + +uint8_t USBMSC_poll () +{ + uint16_t state; + uint8_t edbIndex; + uint8_t * pCT1; + uint8_t * pCT2; + + edbIndex = stUsbHandle[MSC0_INTFNUM].edb_Index; + pCT1 = &tInputEndPointDescriptorBlock[edbIndex].bEPBCTX; + pCT2 = &tInputEndPointDescriptorBlock[edbIndex].bEPBCTY; + + //check if currently transmitting data.. + if (MscReadControl.bReadProcessing == TRUE){ + state = usbDisableOutEndpointInterrupt(edbIndex); + //atomic operation - disable interrupts + if ((MscReadControl.dwBytesToSendLeft == 0) && + (MscReadControl.lbaCount == 0)){ + //data is no more processing - clear flags.. + MscReadControl.bReadProcessing = FALSE; + usbRestoreOutEndpointInterrupt(state); + } else { + if (!(tInputEndPointDescriptorBlock[edbIndex].bEPCNF & + EPCNF_STALL)){ //if it is not stalled - contiune communication + USBIEPIFG |= 1 << (edbIndex + 1); //trigger IN interrupt to finish data tranmition + } + usbRestoreOutEndpointInterrupt(state); + return (kUSBMSC_processBuffer); + } + } + + if (MscState.isMSCConfigured == FALSE){ + return (kUSBMSC_okToSleep); + } + + if (!MscState.bMscSendCsw){ + if (MscState.bMscCbwReceived){ + if (Scsi_Verify_CBW() == SUCCESS){ + //Successful reception of CBW + //Parse the CBW opcode and invoke the right command handler function + Scsi_Cmd_Parser(MSC0_INTFNUM); + MscState.bMscSendCsw = TRUE; + } + MscState.bMscCbwReceived = FALSE; //CBW is performed! + } else { + return (kUSBMSC_okToSleep); + } + //check if any of out pipes has pending data and trigger interrupt + + if ((MscWriteControl.pCT1 != NULL) && + ((*MscWriteControl.pCT1 & EPBCNT_NAK ) || + (*MscWriteControl.pCT2 & EPBCNT_NAK ))){ + USBOEPIFG |= 1 << (edbIndex + 1); //trigger OUT interrupt again + return (kUSBMSC_processBuffer); //do not asleep, as data is coming in + //and follow up data perform will be required. + } + } + + if (MscState.bMscSendCsw){ + if (MscState.bMcsCommandSupported == TRUE){ + //watiting till transport is finished! + if ((MscWriteControl.bWriteProcessing == FALSE) && + (MscReadControl.bReadProcessing == FALSE) && + (MscReadControl.lbaCount == 0)){ + //Send CSW + if (MscState.stallAtEndofTx == TRUE) { + if ((*pCT1 & EPBCNT_NAK) && (*pCT2 & EPBCNT_NAK)) { + MscState.stallAtEndofTx = FALSE; + usbStallInEndpoint(MSC0_INTFNUM); + } + } + else if (SUCCESS == Scsi_Send_CSW(MSC0_INTFNUM)){ + MscState.bMscSendCsw = FALSE; + return (kUSBMSC_okToSleep); + } + } + else { + MSCFromHostToBuffer(); + } + } + } + + return (kUSBMSC_processBuffer); //When MscState.bMcsCommandSupported = FALSE, bReadProcessing became true, and + //bWriteProcessing = true. +} + +// +//! \cond +// + +#endif //_MSC_ + +// +//! \endcond +// + +/*----------------------------------------------------------------------------+ + | End of source file | + +----------------------------------------------------------------------------*/ +/*------------------------ Nothing Below This Line --------------------------*/ +//Released_Version_4_10_02 diff --git a/source/USB_API/USB_MSC_API/UsbMscStateMachine.h b/source/USB_API/USB_MSC_API/UsbMscStateMachine.h new file mode 100644 index 0000000..2057402 --- /dev/null +++ b/source/USB_API/USB_MSC_API/UsbMscStateMachine.h @@ -0,0 +1,50 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +/* + * ======== UsbMscStateMachine.h ======== + */ +#ifndef _USB_MSCSTATE_H_ +#define _USB_MSCSTATE_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +//this file is obsolete. To delete in next version. + +#ifdef __cplusplus +} +#endif +#endif //_USB_MSCSTATE_H_ + +//Released_Version_4_10_02 diff --git a/source/USB_API/USB_PHDC_API/UsbPHDC.c b/source/USB_API/USB_PHDC_API/UsbPHDC.c new file mode 100644 index 0000000..f876bdc --- /dev/null +++ b/source/USB_API/USB_PHDC_API/UsbPHDC.c @@ -0,0 +1,866 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ + +// +//! \cond +// + +/* + * ======== UsbPHDC.c ======== + */ +#include + +#ifdef _PHDC_ + + +#include "../USB_Common/device.h" +#include "../USB_Common/defMSP430USB.h" +#include "../USB_Common/usb.h" //USB-specific Data Structures +#include "..\USB_PHDC_API\UsbPHDC.h" +#include + +//Local Macros +#define INTFNUM_OFFSET(X) (X - PHDC0_INTFNUM) //Get the PHDC offset + +static struct _PHDCWrite { + uint16_t nPHDCBytesToSend; //holds counter of bytes to be sent + uint16_t nPHDCBytesToSendLeft; //holds counter how many bytes is still to be sent + const uint8_t* pUsbBufferToSend; //holds the buffer with data to be sent + uint8_t bCurrentBufferXY; //is 0 if current buffer to write data is X, or 1 if current buffer is Y + uint8_t bZeroPacketSent; //= FALSE; + uint8_t last_ByteSend; +} PHDCWriteCtrl[PHDC_NUM_INTERFACES]; + +static struct _PHDCRead { + uint8_t *pUserBuffer; //holds the current position of user's receiving buffer. If NULL- no receiving + //operation started + uint8_t *pCurrentEpPos; //current positon to read of received data from curent EP + uint16_t nBytesToReceive; //holds how many bytes was requested by receiveData() to receive + uint16_t nBytesToReceiveLeft; //holds how many bytes is still requested by receiveData() to receive + uint8_t * pCT1; //holds current EPBCTxx register + uint8_t * pCT2; //holds next EPBCTxx register + uint8_t * pEP2; //holds addr of the next EP buffer + uint8_t nBytesInEp; //how many received bytes still available in current EP + uint8_t bCurrentBufferXY; //indicates which buffer is used by host to transmit data via OUT endpoint3 +} PHDCReadCtrl[PHDC_NUM_INTERFACES]; + +extern uint16_t wUsbEventMask; + +//function pointers +extern void *(*USB_TX_memcpy)(void * dest, const void * source, size_t count); +extern void *(*USB_RX_memcpy)(void * dest, const void * source, size_t count); + +#ifdef NON_COMPOSITE_MULTIPLE_INTERFACES +extern const struct abromConfigurationDescriptorGroupPHDC abromConfigurationDescriptorGroupPHDC; +#endif +/*----------------------------------------------------------------------------+ + | Global Variables | + +----------------------------------------------------------------------------*/ + +extern __no_init tEDB __data16 tInputEndPointDescriptorBlock[]; +extern __no_init tEDB __data16 tOutputEndPointDescriptorBlock[]; + + +void PHDCResetData () +{ + //indicates which buffer is used by host to transmit data via OUT endpoint3 - X buffer is first + //PHDCReadCtrl[intfIndex].bCurrentBufferXY = X_BUFFER; + + memset(&PHDCWriteCtrl, 0, sizeof(PHDCWriteCtrl)); + memset(&PHDCReadCtrl, 0, sizeof(PHDCReadCtrl)); +} + +/* + * Sends data over interface intfNum, of size size and starting at address data. + * Returns: kUSBPHDC_sendStarted + * kUSBPHDC_sendComplete + * kUSBPHDC_intfBusyError + */ +uint8_t USBPHDC_sendData (const uint8_t* data, uint16_t size, uint8_t intfNum) +{ + uint8_t edbIndex; + uint16_t state; + + edbIndex = stUsbHandle[intfNum].edb_Index; + + if (size == 0){ + return (kUSBPHDC_generalError); + } + + state = usbDisableInEndpointInterrupt(edbIndex); + //atomic operation - disable interrupts + + //do not access USB memory if suspended (PLL off). It may produce BUS_ERROR + if ((bFunctionSuspended) || + (bEnumerationStatus != ENUMERATION_COMPLETE)){ + //data can not be read because of USB suspended + usbRestoreInEndpointInterrupt(state); + return (kUSBPHDC_busNotAvailable); + } + + if (PHDCWriteCtrl[INTFNUM_OFFSET(intfNum)].nPHDCBytesToSendLeft != 0){ + //the USB still sends previous data, we have to wait + usbRestoreInEndpointInterrupt(state); + return (kUSBPHDC_intfBusyError); + } + + //This function generate the USB interrupt. The data will be sent out from interrupt + + PHDCWriteCtrl[INTFNUM_OFFSET(intfNum)].nPHDCBytesToSend = size; + PHDCWriteCtrl[INTFNUM_OFFSET(intfNum)].nPHDCBytesToSendLeft = size; + PHDCWriteCtrl[INTFNUM_OFFSET(intfNum)].pUsbBufferToSend = data; + + //trigger Endpoint Interrupt - to start send operation + USBIEPIFG |= 1 << (edbIndex + 1); //IEPIFGx; + + usbRestoreInEndpointInterrupt(state); + + return (kUSBPHDC_sendStarted); +} + +//workaround for PHDC windows driver: it doesn't give data to Application if was sent 64 byte +#define EP_MAX_PACKET_SIZE_PHDC 0x40 + +//this function is used only by USB interrupt +int16_t PHDCToHostFromBuffer (uint8_t intfNum) +{ + uint8_t byte_count, nTmp2; + uint8_t * pEP1; + uint8_t * pEP2; + uint8_t * pCT1; + uint8_t * pCT2; + uint8_t bWakeUp = FALSE; //TRUE for wake up after interrupt + uint8_t edbIndex; + + edbIndex = stUsbHandle[intfNum].edb_Index; + + if (PHDCWriteCtrl[INTFNUM_OFFSET(intfNum)].nPHDCBytesToSendLeft == 0){ //do we have somtething to send? + if (!PHDCWriteCtrl[INTFNUM_OFFSET(intfNum)].bZeroPacketSent){ //zero packet was not yet sent + PHDCWriteCtrl[INTFNUM_OFFSET(intfNum)].bZeroPacketSent = TRUE; + + if (PHDCWriteCtrl[INTFNUM_OFFSET(intfNum)].last_ByteSend == + EP_MAX_PACKET_SIZE_PHDC){ + if (PHDCWriteCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY == + X_BUFFER){ + if (tInputEndPointDescriptorBlock[edbIndex].bEPBCTX & + EPBCNT_NAK){ + tInputEndPointDescriptorBlock[edbIndex].bEPBCTX = 0; + PHDCWriteCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY + = Y_BUFFER; //switch buffer + } + } else { + if (tInputEndPointDescriptorBlock[edbIndex].bEPBCTY & + EPBCNT_NAK){ + tInputEndPointDescriptorBlock[edbIndex].bEPBCTY = 0; + PHDCWriteCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY + = X_BUFFER; //switch buffer + } + } + } + + PHDCWriteCtrl[INTFNUM_OFFSET(intfNum)].nPHDCBytesToSend = 0; //nothing to send + + //call event callback function + if (wUsbEventMask & kUSB_sendCompletedEvent){ + bWakeUp = USBPHDC_handleSendCompleted(intfNum); + } + } //if (!bSentZeroPacket) + + return (bWakeUp); + } + + PHDCWriteCtrl[INTFNUM_OFFSET(intfNum)].bZeroPacketSent = FALSE; //zero packet will be not sent: we have data + + if (PHDCWriteCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY == X_BUFFER){ + //this is the active EP buffer + pEP1 = (uint8_t*)stUsbHandle[intfNum].iep_X_Buffer; + pCT1 = &tInputEndPointDescriptorBlock[edbIndex].bEPBCTX; + + //second EP buffer + pEP2 = (uint8_t*)stUsbHandle[intfNum].iep_Y_Buffer; + pCT2 = &tInputEndPointDescriptorBlock[edbIndex].bEPBCTY; + } else { + //this is the active EP buffer + pEP1 = (uint8_t*)stUsbHandle[intfNum].iep_Y_Buffer; + pCT1 = &tInputEndPointDescriptorBlock[edbIndex].bEPBCTY; + + //second EP buffer + pEP2 = (uint8_t*)stUsbHandle[intfNum].iep_X_Buffer; + pCT2 = &tInputEndPointDescriptorBlock[edbIndex].bEPBCTX; + } + + //how many byte we can send over one endpoint buffer + byte_count = + (PHDCWriteCtrl[INTFNUM_OFFSET(intfNum)].nPHDCBytesToSendLeft > + EP_MAX_PACKET_SIZE_PHDC) ? EP_MAX_PACKET_SIZE_PHDC : PHDCWriteCtrl[ + INTFNUM_OFFSET(intfNum)].nPHDCBytesToSendLeft; + nTmp2 = *pCT1; + + if (nTmp2 & EPBCNT_NAK){ + USB_TX_memcpy(pEP1, PHDCWriteCtrl[INTFNUM_OFFSET( + intfNum)].pUsbBufferToSend, + byte_count); //copy data into IEP3 X or Y buffer + *pCT1 = byte_count; //Set counter for usb In-Transaction + PHDCWriteCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY = + (PHDCWriteCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY + + 1) & 0x01; //switch buffer + PHDCWriteCtrl[INTFNUM_OFFSET(intfNum)].nPHDCBytesToSendLeft -= + byte_count; + PHDCWriteCtrl[INTFNUM_OFFSET(intfNum)].pUsbBufferToSend += byte_count; //move buffer pointer + PHDCWriteCtrl[INTFNUM_OFFSET(intfNum)].last_ByteSend = byte_count; + + //try to send data over second buffer + nTmp2 = *pCT2; + if ((PHDCWriteCtrl[INTFNUM_OFFSET(intfNum)].nPHDCBytesToSendLeft > + 0) && //do we have more data to send? + (nTmp2 & EPBCNT_NAK)){ //if the second buffer is free? + //how many byte we can send over one endpoint buffer + byte_count = + (PHDCWriteCtrl[INTFNUM_OFFSET(intfNum)].nPHDCBytesToSendLeft > + EP_MAX_PACKET_SIZE_PHDC) ? EP_MAX_PACKET_SIZE_PHDC : + PHDCWriteCtrl[ + INTFNUM_OFFSET(intfNum)].nPHDCBytesToSendLeft; + + USB_TX_memcpy(pEP2, PHDCWriteCtrl[INTFNUM_OFFSET( + intfNum)].pUsbBufferToSend, + byte_count); //copy data into IEP3 X or Y buffer + *pCT2 = byte_count; //Set counter for usb In-Transaction + PHDCWriteCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY = + (PHDCWriteCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY + + 1) & 0x01; //switch buffer + PHDCWriteCtrl[INTFNUM_OFFSET(intfNum)].nPHDCBytesToSendLeft -= + byte_count; + PHDCWriteCtrl[INTFNUM_OFFSET(intfNum)].pUsbBufferToSend += + byte_count; //move buffer pointer + PHDCWriteCtrl[INTFNUM_OFFSET(intfNum)].last_ByteSend = byte_count; + } + } + return (bWakeUp); +} + +/* + * Aborts an active send operation on interface intfNum. + * Returns the number of bytes that were sent prior to the abort, in size. + */ +uint8_t USBPHDC_abortSend (uint16_t* size, uint8_t intfNum) +{ + uint8_t edbIndex; + uint16_t state; + + edbIndex = stUsbHandle[intfNum].edb_Index; + state = usbDisableInEndpointInterrupt(edbIndex); + + *size = + (PHDCWriteCtrl[INTFNUM_OFFSET(intfNum)].nPHDCBytesToSend - + PHDCWriteCtrl[INTFNUM_OFFSET(intfNum)].nPHDCBytesToSendLeft); + PHDCWriteCtrl[INTFNUM_OFFSET(intfNum)].nPHDCBytesToSend = 0; + PHDCWriteCtrl[INTFNUM_OFFSET(intfNum)].nPHDCBytesToSendLeft = 0; + + usbRestoreInEndpointInterrupt(state); + return (kUSB_succeed); +} + +//This function copies data from OUT endpoint into user's buffer +//Arguments: +//pEP - pointer to EP to copy from +//pCT - pointer to pCT control reg +// +void PHDCCopyUsbToBuff (uint8_t* pEP, uint8_t* pCT, uint8_t intfNum) +{ + uint8_t nCount; + + //how many byte we can get from one endpoint buffer + nCount = + (PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft > + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp) ? PHDCReadCtrl[ + INTFNUM_OFFSET(intfNum)].nBytesInEp : PHDCReadCtrl[INTFNUM_OFFSET( + intfNum)]. + nBytesToReceiveLeft; + + USB_RX_memcpy(PHDCReadCtrl[INTFNUM_OFFSET( + intfNum)].pUserBuffer, pEP, nCount); //copy data from OEP3 X or Y buffer + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft -= nCount; + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer += nCount; //move buffer pointer + //to read rest of data next time from this place + + if (nCount == PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp){ //all bytes are copied from receive buffer? + //switch current buffer + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY = + (PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY + 1) & 0x01; + + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = 0; + + //clear NAK, EP ready to receive data + *pCT = 0x00; + } else { + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp -= nCount; + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pCurrentEpPos = pEP + nCount; + } +} + +/* + * Receives data over interface intfNum, of size size, into memory starting at address data. + * Returns: + * kUSBPHDC_receiveStarted if the receiving process started. + * kUSBPHDC_receiveCompleted all requested date are received. + * kUSBPHDC_receiveInProgress previous receive opereation is in progress. The requested receive operation can be not started. + * kUSBPHDC_generalError error occurred. + */ +uint8_t USBPHDC_receiveData (uint8_t* data, uint16_t size, uint8_t intfNum) +{ + uint8_t nTmp1; + uint8_t edbIndex; + uint16_t state; + + edbIndex = stUsbHandle[intfNum].edb_Index; + + if ((size == 0) || //read size is 0 + (data == NULL)){ + return (kUSBPHDC_generalError); + } + + state = usbDisableOutEndpointInterrupt(edbIndex); + //atomic operation - disable interrupts + + //do not access USB memory if suspended (PLL off). It may produce BUS_ERROR + if ((bFunctionSuspended) || + (bEnumerationStatus != ENUMERATION_COMPLETE)){ + //data can not be read because of USB suspended + usbRestoreOutEndpointInterrupt(state); + return (kUSBPHDC_busNotAvailable); + } + + if (PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer != NULL){ //receive process already started + usbRestoreOutEndpointInterrupt(state); + return (kUSBPHDC_intfBusyError); + } + + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceive = size; //bytes to receive + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft = size; //left bytes to receive + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer = data; //set user receive buffer + + //read rest of data from buffer, if any4 + if (PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp > 0){ + //copy data from pEP-endpoint into User's buffer + PHDCCopyUsbToBuff(PHDCReadCtrl[INTFNUM_OFFSET( + intfNum)].pCurrentEpPos, + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1, intfNum); + + if (PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft == 0){ //the Receive opereation is completed + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer = NULL; //no more receiving pending + if (wUsbEventMask & kUSB_receiveCompletedEvent){ + USBPHDC_handleReceiveCompleted(intfNum); //call event handler in interrupt context + } + usbRestoreOutEndpointInterrupt(state); + return (kUSBPHDC_receiveCompleted); //receive completed + } + + //check other EP buffer for data - exchange pCT1 with pCT2 + if (PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 == + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX){ + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 = + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY; + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pCurrentEpPos = + (uint8_t*)stUsbHandle[intfNum].oep_Y_Buffer; + } else { + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 = + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX; + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pCurrentEpPos = + (uint8_t*)stUsbHandle[intfNum].oep_X_Buffer; + } + + nTmp1 = *PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1; + //try read data from second buffer + if (nTmp1 & EPBCNT_NAK){ //if the second buffer has received data? + nTmp1 = nTmp1 & 0x7f; //clear NAK bit + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = nTmp1; //holds how many valid bytes in the EP buffer + PHDCCopyUsbToBuff(PHDCReadCtrl[INTFNUM_OFFSET( + intfNum)].pCurrentEpPos, + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1, intfNum); + } + + if (PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft == 0){ //the Receive opereation is completed + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer = NULL; //no more receiving pending + if (wUsbEventMask & kUSB_receiveCompletedEvent){ + USBPHDC_handleReceiveCompleted(intfNum); //call event handler in interrupt context + } + usbRestoreOutEndpointInterrupt(state); + return (kUSBPHDC_receiveCompleted); //receive completed + } + } //read rest of data from buffer, if any + + //read 'fresh' data, if available + nTmp1 = 0; + if (PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY == X_BUFFER){ //this is current buffer + if (tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX & EPBCNT_NAK){ //this buffer has a valid data packet + //this is the active EP buffer + //pEP1 + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pCurrentEpPos = + (uint8_t*)stUsbHandle[intfNum].oep_X_Buffer; + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 = + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX; + + //second EP buffer + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pEP2 = + (uint8_t*)stUsbHandle[intfNum].oep_Y_Buffer; + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2 = + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY; + nTmp1 = 1; //indicate that data is available + } + } else { //Y_BUFFER + if (tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY & EPBCNT_NAK){ + //this is the active EP buffer + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pCurrentEpPos = + (uint8_t*)stUsbHandle[intfNum].oep_Y_Buffer; + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 = + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY; + + //second EP buffer + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pEP2 = + (uint8_t*)stUsbHandle[intfNum].oep_X_Buffer; + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2 = + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX; + nTmp1 = 1; //indicate that data is available + } + } + if (nTmp1){ + //how many byte we can get from one endpoint buffer + nTmp1 = *PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1; + while (nTmp1 == 0) + { + nTmp1 = *PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1; + } + + if (nTmp1 & EPBCNT_NAK){ + nTmp1 = nTmp1 & 0x7f; //clear NAK bit + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = nTmp1; //holds how many valid bytes in the EP buffer + + PHDCCopyUsbToBuff(PHDCReadCtrl[INTFNUM_OFFSET( + intfNum)].pCurrentEpPos, + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1, intfNum); + + nTmp1 = *PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2; + //try read data from second buffer + if ((PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft > + 0) && //do we have more data to send? + (nTmp1 & EPBCNT_NAK)){ //if the second buffer has received data? + nTmp1 = nTmp1 & 0x7f; //clear NAK bit + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = nTmp1; //holds how many valid bytes in the EP buffer + PHDCCopyUsbToBuff(PHDCReadCtrl[INTFNUM_OFFSET( + intfNum)].pEP2, + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2, intfNum); + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 = + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2; + } + } + } + + if (PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft == 0){ //the Receive opereation is completed + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer = NULL; //no more receiving pending + if (wUsbEventMask & kUSB_receiveCompletedEvent){ + USBPHDC_handleReceiveCompleted(intfNum); //call event handler in interrupt context + } + usbRestoreOutEndpointInterrupt(state); + return (kUSBPHDC_receiveCompleted); + } + + //interrupts enable + usbRestoreOutEndpointInterrupt(state); + return (kUSBPHDC_receiveStarted); +} + +//this function is used only by USB interrupt. +//It fills user receiving buffer with received data +int16_t PHDCToBufferFromHost (uint8_t intfNum) +{ + uint8_t * pEP1; + uint8_t nTmp1; + uint8_t bWakeUp = FALSE; //per default we do not wake up after interrupt + + uint8_t edbIndex; + + edbIndex = stUsbHandle[intfNum].edb_Index; + + if (PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft == 0){ //do we have somtething to receive? + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer = NULL; //no more receiving pending + return (bWakeUp); + } + + //No data to receive... + if (!((tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX | + tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY) + & 0x80)){ + return (bWakeUp); + } + + if (PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY == X_BUFFER){ //X is current buffer + //this is the active EP buffer + pEP1 = (uint8_t*)stUsbHandle[intfNum].oep_X_Buffer; + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 = + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX; + + //second EP buffer + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pEP2 = + (uint8_t*)stUsbHandle[intfNum].oep_Y_Buffer; + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2 = + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY; + } else { + //this is the active EP buffer + pEP1 = (uint8_t*)stUsbHandle[intfNum].oep_Y_Buffer; + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 = + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY; + + //second EP buffer + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pEP2 = + (uint8_t*)stUsbHandle[intfNum].oep_X_Buffer; + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2 = + &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX; + } + + //how many byte we can get from one endpoint buffer + nTmp1 = *PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1; + + if (nTmp1 & EPBCNT_NAK){ + nTmp1 = nTmp1 & 0x7f; //clear NAK bit + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = nTmp1; //holds how many valid bytes in the EP buffer + + PHDCCopyUsbToBuff(pEP1, PHDCReadCtrl[INTFNUM_OFFSET( + intfNum)].pCT1, intfNum); + + nTmp1 = *PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2; + //try read data from second buffer + if ((PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft > 0) && //do we have more data to send? + (nTmp1 & EPBCNT_NAK)){ //if the second buffer has received data? + nTmp1 = nTmp1 & 0x7f; //clear NAK bit + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = nTmp1; //holds how many valid bytes in the EP buffer + PHDCCopyUsbToBuff(PHDCReadCtrl[INTFNUM_OFFSET( + intfNum)].pEP2, + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2, intfNum); + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pCT1 = + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2; + } + } + + if (PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft == 0){ //the Receive opereation is completed + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer = NULL; //no more receiving pending + if (wUsbEventMask & kUSB_receiveCompletedEvent){ + bWakeUp = USBPHDC_handleReceiveCompleted(intfNum); + } + + if (PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp){ //Is not read data still available in the EP? + if (wUsbEventMask & kUSB_dataReceivedEvent){ + bWakeUp = USBPHDC_handleDataReceived(intfNum); + } + } + } + return (bWakeUp); +} + +//helper for USB interrupt handler +int16_t PHDCIsReceiveInProgress (uint8_t intfNum) +{ + return (PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer != NULL); +} + +/* + * Aborts an active receive operation on interface intfNum. + * Returns the number of bytes that were received and transferred + * to the data location established for this receive operation. + */ +uint8_t USBPHDC_abortReceive (uint16_t* size, uint8_t intfNum) +{ + uint16_t state; + + edbIndex = stUsbHandle[intfNum].edb_Index; + + + state = usbDisableOutEndpointInterrupt(edbIndex); + + *size = 0; //set received bytes count to 0 + + //is receive operation underway? + if (PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer){ + //how many bytes are already received? + *size = PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceive - + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft; + + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = 0; + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer = NULL; + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft = 0; + } + + //restore interrupt status + usbRestoreOutEndpointInterrupt(state); + return (kUSB_succeed); +} + +/* + * This function rejects payload data that has been received from the host. + */ +uint8_t USBPHDC_rejectData (uint8_t intfNum) +{ + uint8_t edbIndex; + uint16_t state; + + edbIndex = stUsbHandle[intfNum].edb_Index; + state = usbDisableOutEndpointInterrupt(edbIndex); + + //atomic operation - disable interrupts + + //do not access USB memory if suspended (PLL off). It may produce BUS_ERROR + if (bFunctionSuspended){ + usbRestoreOutEndpointInterrupt(state); + return (kUSBPHDC_busNotAvailable); + } + + //Is receive operation underway? + //- do not flush buffers if any operation still active. + if (!PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer){ + uint8_t tmp1 = tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX & + EPBCNT_NAK; + uint8_t tmp2 = tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY & + EPBCNT_NAK; + + if (tmp1 ^ tmp2){ //switch current buffer if any and only ONE of buffers is full + //switch current buffer + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY = + (PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].bCurrentBufferXY + + 1) & 0x01; + } + + tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX = 0; //flush buffer X + tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY = 0; //flush buffer Y + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp = 0; //indicates that no more data available in the EP + } + + usbRestoreOutEndpointInterrupt(state); + return (kUSB_succeed); +} + +/* + * This function indicates the status of the itnerface intfNum. + * If a send operation is active for this interface, + * the function also returns the number of bytes that have been transmitted to the host. + * If a receiver operation is active for this interface, the function also returns + * the number of bytes that have been received from the host and are waiting at the assigned address. + * + * returns kUSBPHDC_waitingForSend (indicates that a call to USBPHDC_SendData() + * has been made, for which data transfer has not been completed) + * + * returns kUSBPHDC_waitingForReceive (indicates that a receive operation + * has been initiated, but not all data has yet been received) + * + * returns kUSBPHDC_dataWaiting (indicates that data has been received + * from the host, waiting in the USB receive buffers) + */ +uint8_t USBPHDC_intfStatus (uint8_t intfNum, uint16_t* bytesSent, uint16_t* bytesReceived) +{ + uint8_t ret = 0; + uint16_t stateIn, stateOut; + uint8_t edbIndex; + + *bytesSent = 0; + *bytesReceived = 0; + + edbIndex = stUsbHandle[intfNum].edb_Index; + + stateIn = usbDisableInEndpointInterrupt(edbIndex); + stateOut = usbDisableOutEndpointInterrupt(edbIndex); + + //Is send operation underway? + if (PHDCWriteCtrl[INTFNUM_OFFSET(intfNum)].nPHDCBytesToSendLeft != 0){ + ret |= kUSBPHDC_waitingForSend; + *bytesSent = PHDCWriteCtrl[INTFNUM_OFFSET(intfNum)].nPHDCBytesToSend - + PHDCWriteCtrl[INTFNUM_OFFSET(intfNum)]. + nPHDCBytesToSendLeft; + } + + //Is receive operation underway? + if (PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pUserBuffer != NULL){ + ret |= kUSBPHDC_waitingForReceive; + *bytesReceived = + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceive - + PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesToReceiveLeft; + } else { //receive operation not started + //do not access USB memory if suspended (PLL off). It may produce + //BUS_ERROR + if (!bFunctionSuspended){ + if ((tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX & + EPBCNT_NAK) | //any of buffers has a valid data packet + (tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY & + EPBCNT_NAK)){ + ret |= kUSBPHDC_dataWaiting; + } + } + } + + if ((bFunctionSuspended) || + (bEnumerationStatus != ENUMERATION_COMPLETE)){ + //if suspended or not enumerated - report no other tasks pending + ret = kUSBPHDC_busNotAvailable; + } + + //restore interrupt status + usbRestoreInEndpointInterrupt(stateIn); + usbRestoreOutEndpointInterrupt(stateOut); + + __no_operation(); + return (ret); +} + +/* + * Returns how many bytes are in the buffer are received and ready to be read. + */ +uint8_t USBPHDC_bytesInUSBBuffer (uint8_t intfNum) +{ + uint8_t bTmp1 = 0; + uint16_t state; + uint8_t edbIndex; + + edbIndex = stUsbHandle[intfNum].edb_Index; + + state = usbDisableOutEndpointInterrupt(edbIndex); + //atomic operation - disable interrupts + + if ((bFunctionSuspended) || + (bEnumerationStatus != ENUMERATION_COMPLETE)){ + usbRestoreOutEndpointInterrupt(state); + //if suspended or not enumerated - report 0 bytes available + return (0); + } + + if (PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp > 0){ //If a RX operation is underway, part of data may was read of the + //OEP buffer + bTmp1 = PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].nBytesInEp; + if (*PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2 & EPBCNT_NAK){ //the next buffer has a valid data packet + bTmp1 += *PHDCReadCtrl[INTFNUM_OFFSET(intfNum)].pCT2 & 0x7F; + } + } else { + if (tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX & EPBCNT_NAK){ //this buffer has a valid data packet + bTmp1 = tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX & 0x7F; + } + if (tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY & EPBCNT_NAK){ //this buffer has a valid data packet + bTmp1 += tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY & 0x7F; + } + } + + usbRestoreOutEndpointInterrupt(state); + return (bTmp1); +} + +//---------------------------------------------------------------------------- +//Line Coding Structure +//dwDTERate | 4 | Data terminal rate, in bits per second +//bCharFormat | 1 | Stop bits, 0 = 1 Stop bit, 1 = 1,5 Stop bits, 2 = 2 Stop bits +//bParityType | 1 | Parity, 0 = None, 1 = Odd, 2 = Even, 3= Mark, 4 = Space +//bDataBits | 1 | Data bits (5,6,7,8,16) +//---------------------------------------------------------------------------- +uint8_t USBPHDC_GetDataStatusReq (void) +{ + uint8_t i; + + //Initialize response + abUsbRequestReturnData[0] = 0; + abUsbRequestReturnData[1] = 0; + + for (i = 0; i < PHDC_NUM_INTERFACES; i++) + { +#ifdef NON_COMPOSITE_MULTIPLE_INTERFACES + if (abromConfigurationDescriptorGroupPHDC.stPhdc[i].bInterfaceNumber == + tSetupPacket.wIndex){ +#else + if (abromConfigurationDescriptorGroup.stPhdc[i].bInterfaceNumber == + tSetupPacket.wIndex){ +#endif + if (PHDCWriteCtrl[i].nPHDCBytesToSendLeft){ + abUsbRequestReturnData[0] |= 1 << + (stUsbHandle[PHDC0_INTFNUM + + i].ep_Out_Addr); + } + + if (PHDCReadCtrl[i].nBytesInEp){ + abUsbRequestReturnData[0] |= 1 << + (stUsbHandle[PHDC0_INTFNUM + + i].ep_In_Addr & 0x7F); + } + break; + } + } + + /* + * edbIndex = stUsbHandle[intfNum].edb_Index; + * tInputEndPointDescriptorBlock[edbIndex].bEPCNF = 0; + * + * abromConfigurationDescriptorGroup.stPhdc[0].bEndpointAddress_intp + #ifdef PHDC_USE_INT_ENDPOINT + * // ENDPOINT #1 INPUT DESCRIPTOR, (7 bytes) + * SIZEOF_ENDPOINT_DESCRIPTOR, // bLength: Endpoint Descriptor size + * DESC_TYPE_ENDPOINT, // bDescriptorType: Endpoint + * PHDC0_INTEP_ADDR, // bEndpointAddress: + * + * for (i=0; i < PHDC_NUM_INTERFACES; i++) + * { + * for (j=0; j< abromConfigurationDescriptorGroup.stPhdc[i].bNumEndpoints; j++) + * { + * + * } + * } + * bNumEndpoints + * abromConfigurationDescriptorGroup.stPhdc[PHDC_NUM_INTERFACES] + * if(tSetupPacket.wIndex & EP_DESC_ADDR_DIR_IN) + * { + * // input endpoint + * abUsbRequestReturnData[0] = (uint8_t)(tInputEndPointDescriptorBlock[bEndpointNumber].bEPCNF & EPCNF_STALL); + * }else + * { + * // output endpoint + * abUsbRequestReturnData[0] = (uint8_t)(tOutputEndPointDescriptorBlock[bEndpointNumber].bEPCNF & EPCNF_STALL); + * } + * } // no response if endpoint is not supported. + * abUsbRequestReturnData[0] = abUsbRequestReturnData[0] >> 3; // STALL is on bit 3 + */ + wBytesRemainingOnIEP0 = 0x02; + usbSendDataPacketOnEP0((uint8_t*)&abUsbRequestReturnData[0]); + return (FALSE); +} + +#endif //ifdef _PHDC_ + +// +//! \endcond +// + +/*----------------------------------------------------------------------------+ + | End of source file | + +----------------------------------------------------------------------------*/ +/*------------------------ Nothing Below This Line --------------------------*/ +//Released_Version_4_10_02 diff --git a/source/USB_API/USB_PHDC_API/UsbPHDC.h b/source/USB_API/USB_PHDC_API/UsbPHDC.h new file mode 100644 index 0000000..d640d6d --- /dev/null +++ b/source/USB_API/USB_PHDC_API/UsbPHDC.h @@ -0,0 +1,156 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +/* + * ======== UsbPHDC.h ======== + */ +#ifndef _UsbPHDC_H_ +#define _UsbPHDC_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +#define kUSBPHDC_sendStarted 0x01 +#define kUSBPHDC_sendComplete 0x02 +#define kUSBPHDC_intfBusyError 0x03 +#define kUSBPHDC_receiveStarted 0x04 +#define kUSBPHDC_receiveCompleted 0x05 +#define kUSBPHDC_receiveInProgress 0x06 +#define kUSBPHDC_generalError 0x07 +#define kUSBPHDC_busNotAvailable 0x08 + + + +/*---------------------------------------------------------------------------- + * These functions can be used in application + +----------------------------------------------------------------------------*/ + +/* + * Sends data over interface intfNum, of size size and starting at address data. + * Returns: kUSBPHDC_sendStarted + * kUSBPHDC_sendComplete + * kUSBPHDC_intfBusyError + */ +uint8_t USBPHDC_sendData (const uint8_t* data, uint16_t size, uint8_t intfNum); + +/* + * Receives data over interface intfNum, of size size, into memory starting at address data. + */ +uint8_t USBPHDC_receiveData (uint8_t* data, uint16_t size, uint8_t intfNum); + +/* + * Aborts an active receive operation on interface intfNum. + * size: the number of bytes that were received and transferred + * to the data location established for this receive operation. + */ +uint8_t USBPHDC_abortReceive (uint16_t* size, uint8_t intfNum); + + +#define kUSBPHDC_noDataWaiting 1 //returned by USBPHDC_rejectData() if no data pending + +/* + * This function rejects payload data that has been received from the host. + */ +uint8_t USBPHDC_rejectData (uint8_t intfNum); + +/* + * Aborts an active send operation on interface intfNum. Returns the number of bytes that were sent prior to the abort, in size. + */ +uint8_t USBPHDC_abortSend (uint16_t* size, uint8_t intfNum); + + +#define kUSBPHDC_waitingForSend 0x01 +#define kUSBPHDC_waitingForReceive 0x02 +#define kUSBPHDC_dataWaiting 0x04 +#define kUSBPHDC_busNotAvailable 0x08 +#define kUSB_allPHDCEvents 0xFF + +/* + * This function indicates the status of the interface intfNum. + * If a send operation is active for this interface, + * the function also returns the number of bytes that have been transmitted to the host. + * If a receiver operation is active for this interface, the function also returns + * the number of bytes that have been received from the host and are waiting at the assigned address. + * + * returns kUSBPHDC_waitingForSend (indicates that a call to USBPHDC_SendData() + * has been made, for which data transfer has not been completed) + * + * returns kUSBPHDC_waitingForReceive (indicates that a receive operation + * has been initiated, but not all data has yet been received) + * + * returns kUSBPHDC_dataWaiting (indicates that data has been received + * from the host, waiting in the USB receive buffers) + */ +uint8_t USBPHDC_intfStatus (uint8_t intfNum, uint16_t* bytesSent, uint16_t* bytesReceived); + +/* + * This function is called when the device receives a Get_Status request + */ +uint8_t USBPHDC_GetDataStatusReq(void); + + +/* + * Returns how many bytes are in the buffer are received and ready to be read. + */ +uint8_t USBPHDC_bytesInUSBBuffer (uint8_t intfNum); + + +/*---------------------------------------------------------------------------- + * Event-Handling routines + +----------------------------------------------------------------------------*/ + +/* + * This event indicates that data has been received for interface intfNum, but no data receive operation is underway. + * returns TRUE to keep CPU awake + */ +uint8_t USBPHDC_handleDataReceived (uint8_t intfNum); + +/* + * This event indicates that a send operation on interface intfNum has just been completed. + * returns TRUE to keep CPU awake + */ +uint8_t USBPHDC_handleSendCompleted (uint8_t intfNum); + +/* + * This event indicates that a receive operation on interface intfNum has just been completed. + * returns TRUE to keep CPU awake + */ +uint8_t USBPHDC_handleReceiveCompleted (uint8_t intfNum); + + +#ifdef __cplusplus +} +#endif +#endif //_UsbPHDC_H_ +//Released_Version_4_10_02 diff --git a/source/USB_app/usbConstructs.c b/source/USB_app/usbConstructs.c new file mode 100644 index 0000000..cdbda52 --- /dev/null +++ b/source/USB_app/usbConstructs.c @@ -0,0 +1,664 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +/** @file usbConstructs.c + * @brief Contains example constructs for send/receive operations + */ +/* + * ======== usbConstructs.c ======== + */ +// +//! \cond +// + +#include "USB_API/USB_Common/device.h" + +#include "USB_config/descriptors.h" +#include "USB_API/USB_Common/usb.h" // USB-specific functions + +#ifdef _CDC_ + #include "USB_API/USB_CDC_API/UsbCdc.h" +#endif +#ifdef _HID_ + #include "USB_API/USB_HID_API/UsbHid.h" +#endif +#ifdef _PHDC_ + #include "USB_API/USB_PHDC_API/UsbPHDC.h" +#endif + +#include "usbConstructs.h" + + + +/************************************************************************************************** +These are example, user-editable construct functions for calling the API. + +In cases where fast development is the priority, it's usually best to use these sending +construct functions, rather than calling USBCDC_sendData() or USBHID_sendData() +directly. This is because they put boundaries on the "background execution" of sends, +simplfying the application. + +xxxsendDataWaitTilDone() essentially eliminates background processing altogether, always +polling after the call to send and not allowing execution to resume until it's done. This +allows simpler coding at the expense of wasted MCU cycles, and MCU execution being "locked" +to the host (also called "synchronous" operation). + +xxxsendDataInBackground() takes advantage of background processing ("asynchronous" operation) +by allowing sending to happen during application execution; while at the same time ensuring +that the sending always definitely occurs. It provides most of the simplicity of +xxxsendDataWaitTilDone() while minimizing wasted cycles. It's probably the best choice +for most applications. + +A true, asynchronous implementation would be the most cycle-efficient, but is the most +difficult to code; and can't be "contained" in an example function as these other approaches +are. Such an implementation might be advantageous in RTOS-based implementations or those +requiring the highest levels of efficiency. + +These functions take into account all the pertinent return codes, toward ensuring fully +robust operation. The send functions implement a timeout feature, using a loose "number of +retries" approach. This was done in order to avoid using additional hardware resources. A +more sophisticated approach, which the developer might want to implement, would be to use a +hardware timer. + +Please see the MSP430 CDC/HID/MSC USB API Programmer's Guide for a full description of these +functions, how they work, and how to use them. +**************************************************************************************************/ +// +//! \endcond +// + +// +//! \cond +// +#ifdef _HID_ +// +//! \endcond +// +//***************************************************************************** +// +//! Completely Sends the Data in dataBuf +//! +//! \param *dataBuf is the address of the data buffer. +//! \param size is the size of the data. +//! \param intfnum intfNum is which HID interface is being used. +//! \param ulTimeout is the (32-bit) number of polls to USBHID_intfStatus(). +//! +//! Sends the data in \b dataBuf, of size \b size, using the post-call polling method. +//! It does so over interface \b intfNum. The function doesn’t return until the +//! send has completed. Because of this, the user buffer can be edited +//! immediately after the function returns, without consequence. The +//! function assumes that size is non-zero. It assumes no previous send +//! operation is underway. +//! +//! The 32-bit number \b ulTimeout selects how many times USBHID_intfStatus() will +//! be polled while waiting for the operation to complete. If the value is zero, +//! then no timeout is employed; it will wait indefinitely. When choosing a +//! number, it is advised to consider MCLK speed, as a faster CPU will cycle +//! through the calls more quickly. The function provides the simplest coding, +//! at the expense of wasted cycles and potentially allowing MCU execution to +//! become "locked" to the host, a disadvantage if the host (or bus) is slow. +//! +//! The function also checks all valid return codes, and returns non-zero if an +//! error occurred. In many applications, the return value can simply be +//! evaluated as zero or non-zero, where nonzero means the call failed for +//! reasons of host or bus non-availability. Therefore, it may desirable for the +//! application to break from execution. Other applications may wish to handle +//! return values 1 and 2 in different ways. +//! +//! It’s recommended not to call this function from within an event handler. +//! This is because if an interface currently has an open send operation, the +//! operation will never complete during the event handler; rather, only after +//! the ISR that spawned the event returns. Thus the USBHID_intfStatus() polling +//! would loop indefinitely (or timeout). It’s better to set a flag from within +//! the event handler, and use this flag to trigger the calling of this function +//! from within main(). +//! +//! \return \b 0 if the call succeeded; all data has been sent. +//! \return \b 1 if the call timed out, either because the host is unavailable +//! or a COM port with an active application on the host wasn't opened. +//! \return \b 2 if the bus is unavailable. +// +//***************************************************************************** +uint8_t hidSendDataWaitTilDone (uint8_t* dataBuf, + uint16_t size, + uint8_t intfNum, + uint32_t ulTimeout) +{ + uint32_t sendCounter = 0; + uint16_t bytesSent, bytesReceived; + + switch (USBHID_sendData(dataBuf,size,intfNum)){ + case kUSBHID_sendStarted: + break; + case kUSBHID_busNotAvailable: + return ( 2) ; + case kUSBHID_intfBusyError: + return ( 3) ; + case kUSBHID_generalError: + return ( 4) ; + default:; + } + + /* If execution reaches this point, then the operation successfully started. Now wait til it's finished. */ + while (1){ + uint8_t ret = USBHID_intfStatus(intfNum,&bytesSent,&bytesReceived); + if (ret & kUSBHID_busNotAvailable){ /* This may happen at any time */ + return ( 2) ; + } + if (ret & kUSBHID_waitingForSend){ + if (ulTimeout && (sendCounter++ >= ulTimeout)){ /* Incr counter & try again */ + return ( 1) ; /* Timed out */ + } + } else { + return ( 0) ; /* If neither busNotAvailable nor waitingForSend, it succeeded */ + } + } +} + + + +//***************************************************************************** +// +//! Completely Sends the Data in dataBuf +//! +//! \param *dataBuf is the address of the data buffer. +//! \param size is the size of the data. +//! \param intfnum intfNum is which HID interface is being used. +//! \param ulTimeout is the (32-bit) number of polls to USBHID_intfStatus(). +//! +//! Sends the data in \b dataBuf, of size \b size, using the pre-call polling +//! method. It does so over interface \b intfNum. The send operation may still +//! be active after the function returns, and \b dataBuf should not be edited +//! until it can be verified that the operation has completed. The function +//! assumes that size is non-zero. This call assumes a previous send operation +//! might be underway. +//! +//! The 32-bit number \b ulTimeout selects how many times USBHID_intfStatus() +//! will be polled while waiting for the previous operation to complete. If the +//! value is zero, then no timeout is employed; it will wait indefinitely. When +//! choosing a number, it is advised to consider MCLK speed, as a faster CPU +//! will cycle through the calls more quickly. The function provides simple +//! coding while also taking advantage of the efficiencies of background +//! processing. If a previous send operation is underway, this function does +//! waste cycles polling, like xxxsendDataWaitTilDone(); however it's less +//! likely to do so since much of the sending presumably took place in the +//! background since the last call to xxxsendDataInBackground(). +//! +//! The function also checks all valid return codes, and returns non-zero if an +//! error occurred. In many applications, the return value can simply be +//! evaluated as zero or non-zero, where nonzero means the call failed for +//! reasons of host or bus non-availability. Therefore, it may desirable for the +//! application to break from execution. Other applications may wish to handle +//! return values 1 and 2 in different ways. +//! +//! It’s recommended not to call this function from within an event handler. +//! This is because if an interface currently has an open send operation, the +//! operation will never complete during the event handler; rather, only after +//! the ISR that spawned the event returns. Thus the USBHID_intfStatus() polling +//! would loop indefinitely (or timeout). It’s better to set a flag from within +//! the event handler, and use this flag to trigger the calling of this function +//! from within main(). +//! +//! \return \b 0 if the call succeeded; all data has been sent. +//! \return \b 1 if the call timed out, either because the host is unavailable +//! or a COM port with an active application on the host wasn't opened. +//! \return \b 2 if the bus is unavailable. +// +//***************************************************************************** +uint8_t hidSendDataInBackground (uint8_t* dataBuf, + uint16_t size, + uint8_t intfNum, + uint32_t ulTimeout) +{ + uint32_t sendCounter = 0; + uint16_t bytesSent, bytesReceived; + + while (USBHID_intfStatus(intfNum,&bytesSent, + &bytesReceived) & kUSBHID_waitingForSend){ + if (ulTimeout && ((sendCounter++) > ulTimeout)){ /* A send operation is underway; incr counter & try again */ + return ( 1) ; /* Timed out */ + } + } + + /* The interface is now clear. Call sendData(). */ + switch (USBHID_sendData(dataBuf,size,intfNum)){ + case kUSBHID_sendStarted: + return ( 0) ; + case kUSBHID_busNotAvailable: + return ( 2) ; + default: + return ( 4) ; + } +} + + + + +//***************************************************************************** +// +//! Opens a Receive Operation +//! +//! \param *dataBuf is the address of the data buffer. +//! \param size is the size of the data. +//! \param intfnum intfNum is which HID interface is being used. +//! +//! Opens a brief receive operation for any data that has already been received +//! into the USB buffer over interface \b intfNum. This call only retrieves data +//! that is already waiting in the USB buffer -- that is, data that has already +//! been received by the MCU. It assumes a previous, open receive operation +//! (began by a direct call to USBxxx_receiveData()) is NOT underway on this +//! interface; and no receive operation remains open after this call returns. +//! It doesn't check for kUSBxxx_busNotAvailable, because it doesn't matter if +//! it's not. The data in the USB buffer is copied into \b dataBuf, and the +//! function returns the number of bytes received. +//! +//! \b size is the maximum that is allowed to be received before exiting; i.e., +//! it is the size allotted to \b dataBuf. If \b size bytes are received, the +//! function ends, returning \b size. In this case, it’s possible that more +//! bytes are still in the USB buffer; it might be a good idea to open another +//! receive operation to retrieve them. For this reason, operation is simplified +//! by using large \b size values, since it helps ensure all the data is +//! retrieved at one time. +//! +//! This function is usually called when a USBHID_handleDataReceived() event +//! flags the application that data has been received into the USB buffer. +//! +//! \return The number of bytes received into \b dataBuf. +// +//***************************************************************************** +uint16_t hidReceiveDataInBuffer (uint8_t* dataBuf, uint16_t size, uint8_t intfNum) +{ + uint16_t bytesInBuf; + uint16_t rxCount = 0; + uint8_t* currentPos = dataBuf; + + while (bytesInBuf = USBHID_bytesInUSBBuffer(intfNum)){ + if ((uint16_t)(currentPos - dataBuf + bytesInBuf) <= size){ + rxCount = bytesInBuf; + USBHID_receiveData(currentPos,rxCount,intfNum); + currentPos += rxCount; + } else { + rxCount = size - (currentPos - dataBuf); + USBHID_receiveData(currentPos,rxCount,intfNum); + currentPos += rxCount; + return (currentPos - dataBuf); + } + } + + return (currentPos - dataBuf); +} + +// +//! \cond +// +#endif + +/********************************************************************************************* +Please see the MSP430 USB CDC API Programmer's Guide Sec. 9 for a full description of these +functions, how they work, and how to use them. +**********************************************************************************************/ + +#ifdef _CDC_ +// +//! \endcond +// +//***************************************************************************** +// +//! Completely Sends the Data in dataBuf +//! +//! \param *dataBuf is the address of the data buffer. +//! \param size is the size of the data. +//! \param intfnum intfNum is which interface is being used. +//! \param ulTimeout is the (32-bit) number of polls to USBCDC_intfStatus(). +//! +//! Sends the data in \b dataBuf, of size \b size, using the post-call polling method. +//! It does so over interface \b intfNum. The function doesn’t return until the +//! send has completed. Because of this, the user buffer can be edited +//! immediately after the function returns, without consequence. The +//! function assumes that size is non-zero. It assumes no previous send +//! operation is underway. +//! +//! The 32-bit number \b ulTimeout selects how many times USBCDC_intfStatus() will +//! be polled while waiting for the operation to complete. If the value is zero, +//! then no timeout is employed; it will wait indefinitely. When choosing a +//! number, it is advised to consider MCLK speed, as a faster CPU will cycle +//! through the calls more quickly. The function provides the simplest coding, +//! at the expense of wasted cycles and potentially allowing MCU execution to +//! become "locked" to the host, a disadvantage if the host (or bus) is slow. +//! +//! The function also checks all valid return codes, and returns non-zero if an +//! error occurred. In many applications, the return value can simply be +//! evaluated as zero or non-zero, where nonzero means the call failed for +//! reasons of host or bus non-availability. Therefore, it may desirable for the +//! application to break from execution. Other applications may wish to handle +//! return values 1 and 2 in different ways. +//! +//! It’s recommended not to call this function from within an event handler. +//! This is because if an interface currently has an open send operation, the +//! operation will never complete during the event handler; rather, only after +//! the ISR that spawned the event returns. Thus the USBCDC_intfStatus() polling +//! would loop indefinitely (or timeout). It’s better to set a flag from within +//! the event handler, and use this flag to trigger the calling of this function +//! from within main(). +//! +//! \return \b 0 if the call succeeded; all data has been sent. +//! \return \b 1 if the call timed out, either because the host is unavailable +//! or a COM port with an active application on the host wasn't opened. +//! \return \b 2 if the bus is unavailable. +// +//***************************************************************************** +uint8_t cdcSendDataWaitTilDone (uint8_t* dataBuf, + uint16_t size, + uint8_t intfNum, + uint32_t ulTimeout) +{ + uint32_t sendCounter = 0; + uint16_t bytesSent, bytesReceived; + + switch (USBCDC_sendData(dataBuf,size,intfNum)) + { + case kUSBCDC_sendStarted: + break; + case kUSBCDC_busNotAvailable: + return ( 2) ; + case kUSBCDC_intfBusyError: + return ( 3) ; + case kUSBCDC_generalError: + return ( 4) ; + default:; + } + + /* If execution reaches this point, then the operation successfully started. Now wait til it's finished. */ + while (1){ + uint8_t ret = USBCDC_intfStatus(intfNum,&bytesSent,&bytesReceived); + if (ret & kUSBCDC_busNotAvailable){ /* This may happen at any time */ + return ( 2) ; + } + if (ret & kUSBCDC_waitingForSend){ + if (ulTimeout && (sendCounter++ >= ulTimeout)){ /* Incr counter & try again */ + return ( 1) ; /* Timed out */ + } + } else { + return ( 0) ; /* If neither busNotAvailable nor waitingForSend, it succeeded */ + } + } +} + + + + +//***************************************************************************** +// +//! Completely Sends the Data in dataBuf +//! +//! \param *dataBuf is the address of the data buffer. +//! \param size is the size of the data. +//! \param intfnum intfNum is which interface is being used. +//! \param ulTimeout is the (32-bit) number of polls to USBCDC_intfStatus(). +//! +//! Sends the data in \b dataBuf, of size \b size, using the pre-call polling +//! method. It does so over interface \b intfNum. The send operation may still +//! be active after the function returns, and \b dataBuf should not be edited +//! until it can be verified that the operation has completed. The function +//! assumes that size is non-zero. This call assumes a previous send operation +//! might be underway. +//! +//! The 32-bit number \b ulTimeout selects how many times USBCDC_intfStatus() +//! will be polled while waiting for the previous operation to complete. If the +//! value is zero, then no timeout is employed; it will wait indefinitely. When +//! choosing a number, it is advised to consider MCLK speed, as a faster CPU +//! will cycle through the calls more quickly. The function provides simple +//! coding while also taking advantage of the efficiencies of background +//! processing. If a previous send operation is underway, this function does +//! waste cycles polling, like xxxsendDataWaitTilDone(); however it's less +//! likely to do so since much of the sending presumably took place in the +//! background since the last call to xxxsendDataInBackground(). +//! +//! The function also checks all valid return codes, and returns non-zero if an +//! error occurred. In many applications, the return value can simply be +//! evaluated as zero or non-zero, where nonzero means the call failed for +//! reasons of host or bus non-availability. Therefore, it may desirable for the +//! application to break from execution. Other applications may wish to handle +//! return values 1 and 2 in different ways. +//! +//! It’s recommended not to call this function from within an event handler. +//! This is because if an interface currently has an open send operation, the +//! operation will never complete during the event handler; rather, only after +//! the ISR that spawned the event returns. Thus the USBCDC_intfStatus() polling +//! would loop indefinitely (or timeout). It’s better to set a flag from within +//! the event handler, and use this flag to trigger the calling of this function +//! from within main(). +//! +//! \return \b 0 if the call succeeded; all data has been sent. +//! \return \b 1 if the call timed out, either because the host is unavailable +//! or a COM port with an active application on the host wasn't opened. +//! \return \b 2 if the bus is unavailable. +// +//***************************************************************************** +uint8_t cdcSendDataInBackground (uint8_t* dataBuf, + uint16_t size, + uint8_t intfNum, + uint32_t ulTimeout) +{ + uint32_t sendCounter = 0; + uint16_t bytesSent, bytesReceived; + + while (USBCDC_intfStatus(intfNum,&bytesSent, + &bytesReceived) & kUSBCDC_waitingForSend){ + if (ulTimeout && ((sendCounter++) > ulTimeout)){ /* A send operation is underway; incr counter & try again */ + return ( 1) ; /* Timed out */ + } + } + + /* The interface is now clear. Call sendData(). */ + switch (USBCDC_sendData(dataBuf,size,intfNum)){ + case kUSBCDC_sendStarted: + return ( 0) ; + case kUSBCDC_busNotAvailable: + return ( 2) ; + default: + return ( 4) ; + } +} + + + + +//***************************************************************************** +// +//! Opens a Receive Operation +//! +//! \param *dataBuf is the address of the data buffer. +//! \param size is the size of the data. +//! \param intfnum intfNum is which CDC interface is being used. +//! +//! Opens a brief receive operation for any data that has already been received +//! into the USB buffer over interface \b intfNum. This call only retrieves data +//! that is already waiting in the USB buffer -- that is, data that has already +//! been received by the MCU. It assumes a previous, open receive operation +//! (began by a direct call to USBxxx_receiveData()) is NOT underway on this +//! interface; and no receive operation remains open after this call returns. +//! It doesn't check for kUSBxxx_busNotAvailable, because it doesn't matter if +//! it's not. The data in the USB buffer is copied into \b dataBuf, and the +//! function returns the number of bytes received. +//! +//! \b size is the maximum that is allowed to be received before exiting; i.e., +//! it is the size allotted to \b dataBuf. If \b size bytes are received, the +//! function ends, returning \b size. In this case, it’s possible that more +//! bytes are still in the USB buffer; it might be a good idea to open another +//! receive operation to retrieve them. For this reason, operation is simplified +//! by using large \b size values, since it helps ensure all the data is +//! retrieved at one time. +//! +//! This function is usually called when a USBCDC_handleDataReceived() event +//! flags the application that data has been received into the USB buffer. +//! +//! \return The number of bytes received into \b dataBuf. +// +//***************************************************************************** +uint16_t cdcReceiveDataInBuffer (uint8_t* dataBuf, uint16_t size, uint8_t intfNum) +{ + uint16_t bytesInBuf; + uint16_t rxCount = 0; + uint8_t* currentPos = dataBuf; + + while (bytesInBuf = USBCDC_bytesInUSBBuffer(intfNum)){ + if ((uint16_t)(currentPos - dataBuf + bytesInBuf) <= size){ + rxCount = bytesInBuf; + USBCDC_receiveData(currentPos,rxCount,intfNum); + currentPos += rxCount; + } else { + rxCount = size - (currentPos - dataBuf); + USBCDC_receiveData(currentPos,rxCount,intfNum); + currentPos += rxCount; + return (currentPos - dataBuf); + } + } + + return (currentPos - dataBuf); +} +// +//! \cond +// + +#endif +// +//! \endcond +// + +#ifdef _PHDC_ +/* This construct implements post-call polling to ensure the sending completes before the function + * returns. It provides the simplest coding, at the expense of wasted cycles and potentially + * allowing MCU execution to become "locked" to the host, a disadvantage if the host (or bus) is + * slow. The function also checks all valid return codes, and returns non-zero if an error occurred. + * It assumes no previous send operation is underway; also assumes size is non-zero. */ +uint8_t phdcSendDataWaitTilDone (uint8_t* dataBuf, + uint16_t size, + uint8_t intfNum, + uint32_t ulTimeout) +{ + uint32_t sendCounter = 0; + uint16_t bytesSent, bytesReceived; + + switch (USBPHDC_sendData(dataBuf,size,intfNum)) + { + case kUSBPHDC_sendStarted: + break; + case kUSBPHDC_busNotAvailable: + return ( 2) ; + case kUSBPHDC_intfBusyError: + return ( 3) ; + case kUSBPHDC_generalError: + return ( 4) ; + default:; + } + + /* If execution reaches this point, then the operation successfully started. Now wait til it's finished. */ + while (1){ + uint8_t ret = USBPHDC_intfStatus(intfNum,&bytesSent,&bytesReceived); + if (ret & kUSBPHDC_busNotAvailable){ /* This may happen at any time */ + return ( 2) ; + } + if (ret & kUSBPHDC_waitingForSend){ + if (ulTimeout && (sendCounter++ >= ulTimeout)){ /* Incr counter & try again */ + return ( 1) ; /* Timed out */ + } + } else { + return ( 0) ; /* If neither busNotAvailable nor waitingForSend, it succeeded */ + } + } +} + +/* This construct implements pre-call polling to ensure the sending completes before the function + * returns. It provides simple coding while also taking advantage of the efficiencies of background + * processing. If a previous send operation is underway, this function does waste cycles polling, + * like xxxsendDataWaitTilDone(); however it's less likely to do so since much of the sending + * presumably took place in the background since the last call to xxxsendDataInBackground(). + * The function also checks all valid return codes, and returns non-zero if an error occurred. + * It assumes no previous send operation is underway; also assumes size is non-zero. + * This call assumes a previous send operation might be underway; also assumes size is non-zero. + * Returns zero if send completed; non-zero if it failed, with 1 = timeout and 2 = bus is gone. */ +uint8_t phdcSendDataInBackground (uint8_t* dataBuf, + uint16_t size, + uint8_t intfNum, + uint32_t ulTimeout) +{ + uint32_t sendCounter = 0; + uint16_t bytesSent, bytesReceived; + + while (USBPHDC_intfStatus(intfNum,&bytesSent, + &bytesReceived) & kUSBPHDC_waitingForSend){ + if (ulTimeout && ((sendCounter++) > ulTimeout)){ /* A send operation is underway; incr counter & try again */ + return ( 1) ; /* Timed out */ + } + } + + /* The interface is now clear. Call sendData(). */ + switch (USBPHDC_sendData(dataBuf,size,intfNum)){ + case kUSBPHDC_sendStarted: + return ( 0) ; + case kUSBPHDC_busNotAvailable: + return ( 2) ; + default: + return ( 4) ; + } +} + +/* This call only retrieves data that is already waiting in the USB buffer -- that is, data that has + * already been received by the MCU. It assumes a previous, open receive operation (began by a direct + * call to USBxxx_receiveData()) is NOT underway on this interface; and no receive operation remains + * open after this call returns. It doesn't check for kUSBxxx_busNotAvailable, because it doesn't + * matter if it's not. size is the maximum that is allowed to be received before exiting; i.e., it + * is the size allotted to dataBuf. Returns the number of bytes received. */ +uint16_t phdcReceiveDataInBuffer (uint8_t* dataBuf, uint16_t size, uint8_t intfNum) +{ + uint16_t bytesInBuf; + uint16_t rxCount = 0; + uint8_t* currentPos = dataBuf; + + while (bytesInBuf = USBPHDC_bytesInUSBBuffer(intfNum)){ + if ((uint16_t)(currentPos - dataBuf + bytesInBuf) <= size){ + rxCount = bytesInBuf; + USBPHDC_receiveData(currentPos,rxCount,intfNum); + currentPos += rxCount; + } else { + rxCount = size - (currentPos - dataBuf); + USBPHDC_receiveData(currentPos,rxCount,intfNum); + currentPos += rxCount; + return (currentPos - dataBuf); + } + } + + return (currentPos - dataBuf); +} + +#endif +//Released_Version_4_10_02 diff --git a/source/USB_app/usbConstructs.h b/source/USB_app/usbConstructs.h new file mode 100644 index 0000000..0d65e4c --- /dev/null +++ b/source/USB_app/usbConstructs.h @@ -0,0 +1,63 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +/* + * ======== usbConstructs.h ======== + */ +uint8_t hidSendDataWaitTilDone (uint8_t* dataBuf, + uint16_t size, + uint8_t intfNum, + uint32_t ulTimeout); +uint8_t hidSendDataInBackground (uint8_t* dataBuf, + uint16_t size, + uint8_t intfNum, + uint32_t ulTimeout); +uint16_t hidReceiveDataInBuffer(uint8_t*,uint16_t,uint8_t); + +uint8_t cdcSendDataWaitTilDone (uint8_t* dataBuf, + uint16_t size, + uint8_t intfNum, + uint32_t ulTimeout); +uint8_t cdcSendDataInBackground (uint8_t* dataBuf, + uint16_t size, + uint8_t intfNum, + uint32_t ulTimeout); +uint16_t cdcReceiveDataInBuffer(uint8_t*,uint16_t,uint8_t); +uint8_t phdcSendDataWaitTilDone (uint8_t* dataBuf, + uint16_t size, + uint8_t intfNum, + uint32_t ulTimeout); +uint8_t phdcSendDataInBackground (uint8_t* dataBuf, + uint16_t size, + uint8_t intfNum, + uint32_t ulTimeout); +uint16_t phdcReceiveDataInBuffer(uint8_t *,uint16_t,uint8_t); +//Released_Version_4_10_02 diff --git a/source/USB_app/usbEventHandling.c b/source/USB_app/usbEventHandling.c new file mode 100644 index 0000000..b98da86 --- /dev/null +++ b/source/USB_app/usbEventHandling.c @@ -0,0 +1,748 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +/** @file usbEventHandling.c + * @brief Contains required event Handler fucntions + */ +/* + * ======== usbEventHandling.c ======== + * Event-handling placeholder functions. + * All functios are called in interrupt context. + */ + +// +//! \cond +// + +#include "USB_API/USB_Common/device.h" +#include "USB_API/USB_Common/defMSP430USB.h" +#include "USB_config/descriptors.h" +#include "USB_API/USB_Common/usb.h" + +#include "peripherals.h" + +#ifdef _CDC_ +#include "USB_API/USB_CDC_API/UsbCdc.h" +#endif + +#ifdef _HID_ +#include "USB_API/USB_HID_API/UsbHid.h" +#endif + +#ifdef _MSC_ +#include "USB_API/USB_MSC_API/UsbMsc.h" +#endif + +#ifdef _PHDC_ +#include "USB_API/USB_PHDC_API/UsbPHDC.h" +#endif + +// +//! \endcond +// + +//****************************************************************************** +// +//! USB PLL has Failed +//! +//! This event signals that the output of the USB PLL has failed. This event may +//! have occurred because XT2, the source of the PLL’s reference clock, has +//! failed or is unreliable. If this event occurs, the USB connection will +//! likely be lost. It is best to handle it by calling USB_disconnect() and +//! attempting a re-connection. +//! +//! Since this event is associated with a change in state, it's a good +//! practice to return TRUE so the main loop can adapt. +// +//****************************************************************************** +uint8_t USB_handleClockEvent () +{ + //Something happened to the PLL. This might also show up in the system as an oscillator fault on XT2. + //The USB connection is probably lost. Software should ensure any faults on XT2 are resolved, + //then can attempt to call USB_enable()/USB_connect() again. + USB_disconnect(); + USB_disable(); + + return ( TRUE) ; //Since this event is associated with a change in state, it's a good practice to return TRUE + //so the main loop can adapt. +} + +//***************************************************************************** +// +//! Valid Voltage Applied to VBUS +//! +//! If this function gets executed, it indicates that a valid voltage has been +//! applied to the VBUS pin; that is, the voltage on VBUS has transitioned from +//! low to high. +//! +//! This usually means the device has been attached to an active USB host. It is +//! recommended to attempt a USB connection from this handler, as described in +//! Sec. 6.3 of \e "Programmer’s Guide: MSP430 USB API Stack for CDC/PHDC/HID/MSC." +//! events. +//! +//! Returns TRUE to wake the main loop (if LPM was entered), so that it can +//! take into account the change in state. +// +//***************************************************************************** +uint8_t USB_handleVbusOnEvent () +{ + //The standard user experience when a USB device gets physically attached to a host is for the host to + //enumerate the device. Typically this happens as follows: + //1) the device senses 5V VBUS from the host, which tells it a host is present; (usually; but could also be a powered hub w/o a + //host! See state ST_NOENUM_SUSPENDED.) + //2) the device asserts the PUR signal, which tells the host the devicde is present; + //3) the host issues a number of USB device requests, including asking for the device's USB descriptors; + //4) the host decides if it has the appropriate driver for what it sees in the descriptors; and if so, loads it. Enumeration is + //now complete. + //So -- USB_handleVbusOnEvent occurs if a VBUS-on event has been detected. We respond by doing the following. + //However, keep in mind that USB_enable() might take a few milliseconds while the crystal starts up, and that most events handle + //in + //the context of the USB interrupt handler. If this interrupt latency is unacceptable, it might be better to set a flag for + //main() to handle it. + if (USB_enable() == kUSB_succeed){ //Start the module; + USB_reset(); //Reset the internal API + USB_connect(); //Assert PUR, to tell the host we're here + } //Enumeration will now take place in the background + return (TRUE); //Meanwhile, return TRUE to wake the main loop (if LPM was entered), so +} //that it can take into account the change in state + +//***************************************************************************** +// +//! Valid Voltage Removed from VBUS +//! +//! This event indicates that a valid voltage has just been removed from the +//! VBUS pin. That is, the voltage on VBUS has transitioned from high to low. +//! +//! This generally means the device has been removed from an active USB host. It +//! might also mean the device is still physically attached to the host, but the +//! host went into a standby mode; or it was attached to a powered hub but the +//! host upstream from that hub became inactive. The API automatically responds +//! to a VBUS-off event by powering down the USB module and PLL, which is the +//! equivalent of calling USB_disable(). It then calls this handling function, +//! if enabled. +//! +//! Since this event is associated with a change in state, it's a good +//! practice to return TRUE so the main loop can adapt. +// +//***************************************************************************** +uint8_t USB_handleVbusOffEvent () +{ + //Typically there's no need to place code here -- the main loop simply shifts to ST_USB_DISCONNECTED. + + return (TRUE); //Since this event is associated with a change in state, it's a good practice to return TRUE + //so the main loop can adapt. +} + +//***************************************************************************** +// +//! USB Host Issued a Reset +//! +//! This event indicates that the USB host has issued a reset of this USB +//! device. The API handles this automatically, and no action is required by the +//! application to maintain USB operation. After handling the reset, the API +//! calls this handling function, if enabled. In most cases there is no +//! significant reason for the application to respond to bus resets. +// +//***************************************************************************** +uint8_t USB_handleResetEvent () +{ + return (TRUE); +} + +//***************************************************************************** +// +//! USB Host Suspends USB Device +//! +//! This event indicates that the USB host has chosen to suspend this USB device +//! after a period of active operation. It’s important that a bus-powered, +//! suspended USB device limit its consumption of power from VBUS during this +//! time. The API automatically shuts down USB-related circuitry inside the +//! MSP430’s USB module. However, the application may need to shut down other +//! circuitry drawing from VBUS. This handler is a good place to do this. +//! +//! See Sec.11.1.3 of \e "Programmer’s Guide: +//! MSP430 USB API Stack for CDC/PHDC/HID/MSC." for a complete discussion +//! about handling suspend. +//! +//! Returns TRUE so that the main loop can adapt. +// +//***************************************************************************** +uint8_t USB_handleSuspendEvent () +{ + //If this device draws power from the host over VBUS, then this event is the signal for software to ensure that + //no more than 2.5mA is drawn over VBUS. Code can be placed here to do this, or it can be placed in the main loop + //under ST_ENUM_SUSPENDED (but make sure this handler returns TRUE to wake the main loop, if LPM0 was entered). + + return (TRUE); //Return TRUE so that the main loop can adapt. +} + +//***************************************************************************** +// +//! USB Host has Resumed this USB Device +//! +//! This event indicates that the USB host has resumed this USB device from +//! suspend mode. If the device is bus-powered, it is no longer restricted in +//! the amount of power it can draw from VBUS. The API automatically re-enables +//! any circuitry in the MSP430’s USB module that was disabled during suspend. +//! The application can use this handler to re-enable other circuitry as well. +//! +//! Since this event is associated with a change in state, it's a good +//! practice to return TRUE so the main loop can adapt. +// +//***************************************************************************** +uint8_t USB_handleResumeEvent () +{ + //If functionality was shut off during USB_handleSuspendEvent(), it can be re-enabled here. + + return (TRUE); //Since this event is associated with a change in state, it's a good practice to return TRUE so the main loop + //can adapt. +} + +//***************************************************************************** +// +//! Device has Become Enumerated +//! +//! This event indicates that the device has just become enumerated. This +//! corresponds with a state change to ST_ENUM_ACTIVE. +//! +//! Since this event is associated with a change in state, it's a good +//! practice to return TRUE so the main loop can adapt. +// +//***************************************************************************** +uint8_t USB_handleEnumCompleteEvent () +{ + //Typically there's no need to place code here -- the main loop shifts to ST_ENUM_ACTIVE. + + return (TRUE); //Since this event is associated with a change in state, it's a good practice to return TRUE so the main loop + //can adapt. +} + +#ifdef USE_TIMER_FOR_RESUME +//***************************************************************************** +// +//! USB_resume requires a "wait" for XT2 crystal stabilization +//! +//! When this function gets executed, it indicates that a USB_resume is in +//! progress and the USB stack requires the application to use a timer to wait +//! until the XT2 crystal has stabilized. See crystal specific datasheet for +//! delay times. When the crystal has stabilized the application needs to call +//! the function USB_enable_PLL() to allow resume to continue. +// +//***************************************************************************** +void USB_handleCrystalStartedEvent(void) +{ + +} +//***************************************************************************** +// +//! USB_resume requires a "wait" for USB PLL stabilization +//! +//! When this function gets executed, it indicates that a USB_resume is in +//! progress and the USB stack requires the application to use a timer to wait +//! until the USB PLL has stabilized. See crystal specific datasheet for +//! delay times. When the PLL has stabilized the application needs to call +//! the function USB_enable_final() to allow resume to continue. +// +//***************************************************************************** +void USB_handlePLLStartedEvent(void) +{ + +} +#endif + +//***************************************************************************** +// +//! Indicates Data has been Received for CDC Interface +//! +//! \param intfNum is which HID interface is being used. +//! +//! This event indicates that data has been received for CDC interface intfNum +//! with no receive operation underway. Effectively, the API doesn’t know what +//! to do with this data and is asking for instructions. The application can +//! respond by either initiating a receive operation or rejecting the data. +//! Until one of these is performed, USB data reception cannot continue; any +//! packets received from the USB host will be NAK’ed. +//! +//! Therefore, this event should be handled quickly. A receive operation cannot +//! be started directly out of this event, since USBCDC_receiveData() cannot be +//! called from the event handlers. However, the handler can set a flag for +//! main() to begin the receive operation. After this function exits, a call to +//! USBCDC_intfStatus() for this CDC interface will return kUSBDataWaiting. +//! +//! If the application is written so that a receive operation is always begun +//! prior to data arriving from the host, this event will never occur. The +//! software designer generally has a choice of whether to use this event as +//! part of code flow (initiating receive operations after data is received), or +//! to always keep a receive operation open in case data arrives. (See Sec. 11 +//! of \e "Programmer’s Guide: MSP430 USB API Stack for CDC/PHDC/HID/MSC" for +//! more discussion.) +//! +//! Return TRUE to wake up after data was received. +// +//***************************************************************************** +#ifdef _CDC_ + +uint8_t USBCDC_handleDataReceived (uint8_t intfNum) +{ + //TO DO: You can place your code here + + return (FALSE); //return TRUE to wake up after data was received +} + +//***************************************************************************** +// +//! Send Operation on CDC Interface has Completed +//! +//! \param intfNum is which HID interface is being used. +//! +//! +//! This event indicates that a send operation on CDC interface intfNum has just +//! been completed. +//! +//! In applications sending a series of data blocks, the designer may wish +//! to use this event to trigger another send operation. This cannot be done +//! directly out of this event, since USBCDC_sendData() cannot be called +//! from the event handlers. However, the handler can set a flag for main() +//! to begin the operation. +//! +//! Returns FALSE to go asleep after interrupt (in the case the CPU slept before +//! interrupt). +// +//***************************************************************************** +uint8_t USBCDC_handleSendCompleted (uint8_t intfNum) +{ + //TO DO: You can place your code here + + // Signal I2C state machine that USB send operation has just been completed. + extern volatile unsigned char bDataSendCompleted_event[]; // data send completed event + bDataSendCompleted_event[intfNum] = TRUE; + + return (FALSE); //return FALSE to go asleep after interrupt (in the case the CPU slept before interrupt) +} + +//***************************************************************************** +// +//! Receive Operation on CDC Interface has Completed +//! +//! \param intfNum is which HID interface is being used. +//! +//! This event indicates that a receive operation on CDC interface intfNum has +//! just been completed, and the data is therefore available in the user buffer +//! assigned when the call was made to USBCDC_receiveData(). If this event +//! occurs, it means that the entire buffer is full, according to the size value +//! that was requested. +//! +//! The designer may wish to use this event to trigger another receive +//! operation. This cannot be done directly out of this event, since +//! USBCDC_receiveData() cannot be called from the event handlers. However, the +//! handler can set a flag for main() to begin the operation. +//! +//! Returns FALSE to go asleep after interrupt (in the case the CPU slept before +//! interrupt). +// +//***************************************************************************** +uint8_t USBCDC_handleReceiveCompleted (uint8_t intfNum) +{ + //TO DO: You can place your code here + + // Signal I2C state machine that USB receive operation has just completed. + extern volatile unsigned char bDataReceiveCompleted_event[]; + bDataReceiveCompleted_event[intfNum] = TRUE; + + return (FALSE); //return FALSE to go asleep after interrupt (in the case the CPU slept before interrupt) +} + +//***************************************************************************** +// +//! New Line Coding Parameters have been Received from the Host +//! +//! \param intfNum is which CDC interface is being used. +//! \param lBaudrate had COMport baud rate values such as 9600, 19200 etc +//! +//! This event indicates that a SetLineCoding request has been received from the +//! host and new values for baud rate are available. +//! +//! The application can use the new baud rate value to re-configure the Uart +//! in the case of a usb to uart bridge application. See C7 Example for +//! details. +//! +//! Returns FALSE to go asleep after interrupt (in the case the CPU slept before +//! interrupt). +// +//***************************************************************************** +uint8_t USBCDC_handleSetLineCoding (uint8_t intfNum, uint32_t lBaudrate) +{ + //TO DO: You can place your code here + BaudrateSelect(lBaudrate); + + return (FALSE); //return FALSE to go asleep after interrupt (in the case the CPU slept before interrupt) +} + +//***************************************************************************** +// +//! New Line State has been Received from the Host +//! +//! \param intfNum is which CDC interface is being used. +//! \param lineState BIT0 is DTR_PRESENT(1) or DTR_NOT_PRESENT(0) +//! BIT1 is RTS_PRESETNT(1) or RTS_NOT_PRESENT(0) +//! +//! This event indicates that a SetControlLineState request has been received +//! from the host and new values for RTS are available. +//! +//! The application can use the new RTS value to flow off the uart. See C7 +//! Example for details. +//! +//! Returns FALSE to go asleep after interrupt (in the case the CPU slept before +//! interrupt). +// +//***************************************************************************** +uint8_t USBCDC_handleSetControlLineState (uint8_t intfNum, uint8_t lineState) +{ + return FALSE; +} + +#endif //_CDC_ + +#ifdef _HID_ + +//***************************************************************************** +// +//! Data has been Received for HID Interface +//! +//! \param intfNum is which HID interface is being used. +//! +//! This event applies to HID-Datapipe only, as opposed to HID-Traditional. +//! It indicates that data has been received for HID interface intfNum with no +//! receive operation underway. Effectively, the API doesn’t know what to do +//! with this data and is asking for instructions. The application can respond +//! by either initiating a receive operation or rejecting the data. Until one of +//! these is performed, USB data reception cannot continue; any packets received +//! from the USB host will be NAK’ed. +//! +//! Therefore, this event should be handled quickly. A receive operation cannot +//! be started directly out of this event, since USBHID_receiveData() cannot be +//! called from the event handlers. However, the handler can set a flag for +//! main() to begin the receive operation. After this function exits, a call to +//! USBHID_intfStatus() for this HID interface will return kUSBDataWaiting. +//! +//! If the application is written so that a receive operation is always begun +//! prior to data arriving from the host, this event will never occur. The +//! software designer generally has a choice of whether to use this event as +//! part of code flow (initiating receive operations after data is received), or +//! to always keep a receive operation open in case data arrives. (See Sec. 11 +//! of \e "Programmer’s Guide: MSP430 USB API Stack for CDC/PHDC/HID/MSC" more +//! discussion.) +//! +//! Returns FALSE to go asleep after interrupt (in the case the CPU slept before +//! interrupt). +// +//***************************************************************************** +uint8_t USBHID_handleDataReceived (uint8_t intfNum) +{ + //TO DO: You can place your code here + + return (FALSE); //return FALSE to go asleep after interrupt (in the case the CPU slept before interrupt) +} + +//***************************************************************************** +// +//! Send Operation on Data Interface has been Completed +//! +//! \param intfNum is which HID interface is being used. +//! +//! This event applies to HID-Datapipe only, as opposed to HID-Traditional. It +//! indicates that a send operation on data interface intfNum has just been +//! completed. +//! +//! In applications sending a series of large blocks of data, the designer may +//! wish to use this event to trigger another send operation. This cannot be +//! done directly out of this event, since USBHID_sendData() cannot be called +//! from the event handlers. However, the handler can set a flag for main() to +//! begin the operation. +//! +//! Returns FALSE to go asleep after interrupt (in the case the CPU slept before +//! interrupt). +// +//***************************************************************************** +uint8_t USBHID_handleSendCompleted (uint8_t intfNum) +{ + //TO DO: You can place your code here + extern volatile unsigned char bDataSendCompleted_event[]; // data send completed event + bDataSendCompleted_event[intfNum] = TRUE; + + return (FALSE); //return FALSE to go asleep after interrupt (in the case the CPU slept before interrupt) +} + +//***************************************************************************** +// +//! Receive Operation has been Completed +//! +//! \param intfNum is which HID interface is being used. +//! +//! This event applies to HID-Datapipe only, as opposed to HID-Traditional. It +//! indicates that a receive operation on HID interface intfNum has just been +//! completed, and the data is therefore available in the user buffer assigned +//! when the call was made to USBHID_receiveData(). If this event occurs, it +//! means that the entire buffer is full, according to the size value that was +//! requested. +//! +//! The designer may wish to use this event to trigger another receive +//! operation. This cannot be done directly out of this event, since +//! USBHID_receiveData() cannot be called from the event handlers. However, the +//! handler can set a flag for main() to begin the operation. +//! +//! Returns FALSE to go asleep after interrupt (in the case the CPU slept before +//! interrupt). +// +//***************************************************************************** +uint8_t USBHID_handleReceiveCompleted (uint8_t intfNum) +{ + //TO DO: You can place your code here + extern volatile unsigned char bDataReceiveCompleted_event[]; + bDataReceiveCompleted_event[intfNum] = TRUE; + + return (FALSE); //return FALSE to go asleep after interrupt (in the case the CPU slept before interrupt) +} + +//***************************************************************************** +// +//! Set_Protocol Request Received from the Host +//! +//! \param protocol indicates HID_BOOT_PROTOCOL or HID_REPORT_PROTOCOL +//! \param intfNum is which HID interface is being used. +//! +//! This event applies to HID Traditional only. It indicates that the host has +//! requested a change in the HID protocol – from Boot to Standard or Standard +//! to Boot. An application that maintains separate reports for boot and +//! standard protocols can switch to the appropriate report upon receiving this +//! request. The protocol field is either HID_BOOT_PROTOCOL or +//! HID_REPORT_PROTOCOL. +//! +//! Returns FALSE to go asleep after interrupt (in the case the CPU slept before +//! interrupt). +// +//***************************************************************************** +uint8_t USBHID_handleBootProtocol (uint8_t protocol, uint8_t intfnum) +{ + return (FALSE); +} + +//***************************************************************************** +// +//! Set_Report request Received from the Host +//! +//! \param reportType is either USB_REQ_HID_INPUT, USB_REQ_HID_OUTPUT or +//! USB_REQ_HID_FEATURE +//! \param reportId is values defined by report descriptor +//! \param dataLength is length of report +//! \param intfNum is which HID interface is being used. +//! +//! This event indicates that a Set_Report request was received from the +//! host. The application needs to supply a buffer to retrieve the report data +//! that will be sent as part of this request. This handler is passed the +//! reportType, reportId, the length of data phase as well as the interface +//! number. +// +//***************************************************************************** +uint8_t *USBHID_handleEP0SetReport (uint8_t reportType, uint8_t reportId, + uint16_t dataLength, + uint8_t intfnum) +{ + switch (reportType) { + case USB_REQ_HID_INPUT: + //Return pointer to input Report Buffer + return (0); + case USB_REQ_HID_OUTPUT: + //Return pointer to output Report Buffer + return (0); + + case USB_REQ_HID_FEATURE: + //Return pointer to feature Report Buffer + return (0); + + default: + return (0); + } +} + +//***************************************************************************** +// +//! Data as Part of Set_Report Request was Received from the Host +//! +//! \param intfNum is which HID interface is being used. +//! +//! This event indicates that data as part of Set_Report request was received +//! from the host. If the application supplied a buffer as part of +//! USBHID_handleEP0SetReport, then this buffer will contain the Set Report data. +//! +//! Returns TRUE to wake up after data was received. +// +//***************************************************************************** +uint8_t USBHID_handleEP0SetReportDataAvailable (uint8_t intfnum) +{ + //Process received data based on currentReportType + return (TRUE); +} + +//***************************************************************************** +// +//! Get_Report Request was Received from the Host +//! +//! \param reportType is either USB_REQ_HID_INPUT, USB_REQ_HID_OUTPUT or +//! USB_REQ_HID_FEATURE +//! \param reportId is values defined by report descriptor +//! \param requestedLength is length of report +//! \param intfNum is which HID interface is being used. +//! +//! This event indicates that a Get_Report request was received from the host. +//! The application can supply a buffer of data that will be sent to the host. +//! This handler is passed the reportType, reportId, the requested length as +//! well as the interface number. +//! +//! Returns TRUE to wake up after data was received. +// +//***************************************************************************** +uint8_t *USBHID_handleEP0GetReport (uint8_t reportType, uint8_t reportId, + uint16_t requestedLength, + uint8_t intfnum) +{ + //report data should be ready in buffers for Get Report. + switch (reportType) { + case USB_REQ_HID_INPUT: + //Return pointer to input Report Buffer + return (0); + case USB_REQ_HID_OUTPUT: + //Return pointer to OUTput Report Buffer + return (0); + case USB_REQ_HID_FEATURE: + //Return pointer to FEATURE Report Buffer + return (0); + default: + return (0); + } +} + +#endif //_HID_ + +#ifdef _MSC_ +//***************************************************************************** +// +//! API Requests a Buffer +//! +//! This event occurs when the API requests a buffer. Immediately prior to this, +//! the API sets the operation field of the USBMSC_RWBuf_Info structure +//! corresponding with the request, and also clears the low-power-mode bits of +//! the MCU’s status register to ensure the CPU remains awake to process the +//! buffer after the event occurs. +//! +//! NOTE: This means the return value of this event has no effect; the CPU will <-- BECAUSE OF THIS... +//! remain awake even if this function returns FALSE. +// +//***************************************************************************** +uint8_t USBMSC_handleBufferEvent (void) +{ + return (FALSE); //return FALSE to go asleep after interrupt (in the case the CPU slept before interrupt) <-- ...LOSE COMMENT??? +} + +#endif //_MSC_ + +#ifdef _PHDC_ + +//***************************************************************************** +// +//! Data Received +//! +//! \param intfNum is which interface is being used. +//! +//! This event indicates that data has been received for interface \b intfNum, +//! but no data receive operation is underway. +//! +//! Returns TRUE to keep CPU awake, or return FALSE to go asleep after interrupt +//! (in the case the CPU slept before interrupt). +// +//***************************************************************************** +uint8_t USBPHDC_handleDataReceived (uint8_t intfNum) +{ + //TO DO: You can place your code here + + return (FALSE); //return FALSE to go asleep after interrupt (in the case the CPU slept before + //interrupt) +} + +//***************************************************************************** +// +//! Send Completed +//! +//! \param intfNum is which interface is being used. +//! +//! This event indicates that a send operation on interface \b intfNum has just +//! been completed. +//! +//! Returns TRUE to keep CPU awake, or return FALSE to go asleep after interrupt +//! (in the case the CPU slept before interrupt). +// +//***************************************************************************** +uint8_t USBPHDC_handleSendCompleted (uint8_t intfNum) +{ + //TO DO: You can place your code here + + return (FALSE); //return FALSE to go asleep after interrupt (in the case the CPU slept before + //interrupt) +} + +//***************************************************************************** +// +//! Receive Completed +//! +//! \param intfNum is which interface is being used. +//! +//! This event indicates that a receive operation on interface \b intfNum has +//! just been completed. +//! +//! Returns TRUE to keep CPU awake, or return FALSE to go asleep after interrupt +//! (in the case the CPU slept before interrupt). +// +//***************************************************************************** +uint8_t USBPHDC_handleReceiveCompleted (uint8_t intfNum) +{ + //TO DO: You can place your code here + + return (FALSE); //return FALSE to go asleep after interrupt (in the case the CPU slept before + //interrupt) +} + +#endif //_PHDC_ + +/*----------------------------------------------------------------------------+ + | End of source file | + +----------------------------------------------------------------------------*/ +/*------------------------ Nothing Below This Line --------------------------*/ +//Released_Version_4_10_02 diff --git a/source/USB_config/MSP430_CDC.inf b/source/USB_config/MSP430_CDC.inf new file mode 100644 index 0000000..f247371 --- /dev/null +++ b/source/USB_config/MSP430_CDC.inf @@ -0,0 +1,124 @@ +; --COPYRIGHT--,BSD +; Copyright (c) 2012, Texas Instruments Incorporated +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions +; are met: +; +; * Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; +; * Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; +; * Neither the name of Texas Instruments Incorporated nor the names of +; its contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 'AS IS' +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; --/COPYRIGHT-- +; MSP430 Virtual COM Port Installation file for Win2000/XP/Vista/7 +; +; Port drivers setup +; +; Supported operating systems: +; Windows 32-bit and 64-bit +[Version] + +Signature="$Windows NT$" +; CatalogFile=MSP430_CDC.cat +; For information on CatalogFile, please see +; http://msdn.microsoft.com/en-us/library/windows/hardware/ff547502(v=vs.85).aspx +Class=Ports +ClassGuid={4D36E978-E325-11CE-BFC1-08002BE10318} +Provider=%TI% +DriverVer=09/06/2010, 1.02 + +[Manufacturer] +%TI%=DeviceList, NTamd64 + +[DestinationDirs] +FakeModemCopyFileSection=12 +DefaultDestDir=12 + +[SourceDisksNames] + +[SourceDisksFiles] + +;You can modify next string and place your VID and PID +[DeviceList] +%DESCRIPTION0%=TIUSB, USB\Vid_2047&Pid_030b + +[DeviceList.NTamd64] +%DESCRIPTION0%=TIUSB.NTamd64, USB\Vid_2047&Pid_030b + + ;------------------------------------------------------------------------------ +; Windows 32-bit Sections +;------------------------------------------------------------------------------ + +[TIUSB.nt] +include=mdmcpq.inf +CopyFiles=FakeModemCopyFileSection +AddReg=TIUSB.nt.AddReg + +[TIUSB.nt.AddReg] +HKR,,NTMPDriver,,*ntkern +HKR,,NTMPDriver,,usbser.sys +HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider" +HKR,,PortSubClass,1,01 + +[TIUSB.nt.Services] +AddService=usbser, 0x00000002, DriverService + +[TIUSB.nt.HW] +include=mdmcpq.inf + +[DriverService] +DisplayName=%DESCRIPTION% +ServiceType=1 +StartType=3 +ErrorControl=1 +ServiceBinary=%12%\usbser.sys +LoadOrderGroup=Base + +;------------------------------------------------------------------------------ +; Windows 64-bit Sections +;------------------------------------------------------------------------------ + +[TIUSB.NTamd64] +include=mdmcpq.inf +CopyFiles=FakeModemCopyFileSection +AddReg=TIUSB.NTamd64.AddReg + +[TIUSB.NTamd64.AddReg] +HKR,,NTMPDriver,,*ntkern +HKR,,NTMPDriver,,usbser.sys +HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider" +HKR,,PortSubClass,1,01 + +[TIUSB.NTamd64.Services] +AddService=usbser, 0x00000002, DriverService + +[TIUSB.NTamd64.HW] +include=mdmcpq.inf + +;------------------------------------------------------------------------------ +; String Definitions +;------------------------------------------------------------------------------ + +[Strings] +TI="Texas Instruments" +DESCRIPTION="MSP BSL USB Tool" +DESCRIPTION0="MSP BSL USB Tool" diff --git a/source/USB_config/MSP430_CDC.zip b/source/USB_config/MSP430_CDC.zip new file mode 100644 index 0000000..c18b4ec Binary files /dev/null and b/source/USB_config/MSP430_CDC.zip differ diff --git a/USB_config/UsbIsr.c b/source/USB_config/UsbIsr.c similarity index 53% rename from USB_config/UsbIsr.c rename to source/USB_config/UsbIsr.c index cdf10a9..a6a1075 100644 --- a/USB_config/UsbIsr.c +++ b/source/USB_config/UsbIsr.c @@ -1,386 +1,352 @@ -// (c)2010 by Texas Instruments Incorporated, All Rights Reserved. -/*-----------------------------------------------------------------------------+ -| | -| Texas Instruments | -| | -| This is an automatically generated script by MSP430 USB Descriptor Tool | -| | -| Descriptor Tool Version: 3.0.10 | -| Date: 2011/10/13 11:03:28 | -| | -| UsbIsr.c | -|-----------------------------------------------------------------------------*/ - -/*-----------------------------------------------------------------------------+ -| Include files | -|-----------------------------------------------------------------------------*/ -#include -#include // Basic Type declarations -#include -#include "descriptors.h" -#include //USB-specific Data Structures -#include -#include -#include -#include -#include - -#include "../uart.h" - -/*----------------------------------------------------------------------------+ -| External Variables | -+----------------------------------------------------------------------------*/ -extern BYTE bFunctionSuspended; -extern __no_init tEDB0 __data16 tEndPoint0DescriptorBlock; -extern __no_init tEDB __data16 tInputEndPointDescriptorBlock[]; -extern __no_init tEDB __data16 tOutputEndPointDescriptorBlock[]; -extern volatile BYTE bHostAsksUSBData; -extern volatile BYTE bTransferInProgress; -extern volatile BYTE bSecondUartTxDataCounter[]; -extern volatile PBYTE pbSecondUartTxData; -extern BYTE bStatusAction; -extern WORD wUsbEventMask; -BOOL CdcToHostFromBuffer(BYTE); -BOOL CdcToBufferFromHost(BYTE); -BOOL CdcIsReceiveInProgress(BYTE); -BOOL HidToHostFromBuffer(BYTE); -BOOL HidToBufferFromHost(BYTE); -BOOL HidIsReceiveInProgress(BYTE); -/*----------------------------------------------------------------------------+ -| General Subroutines | -+----------------------------------------------------------------------------*/ -#pragma vector=USB_UBM_VECTOR -__interrupt VOID iUsbInterruptHandler(VOID) -{ - BYTE bWakeUp = FALSE; - //Check if the setup interrupt is pending. - //We need to check it before other interrupts, - //to work around that the Setup Int has lower priority then Input Endpoint 0 - if (USBIFG & SETUPIFG) - { - bWakeUp = SetupPacketInterruptHandler(); - USBIFG &= ~SETUPIFG; // clear the interrupt bit - } - switch (__even_in_range(USBVECINT & 0x3f, USBVECINT_OUTPUT_ENDPOINT7)) - { - case USBVECINT_NONE: - break; - case USBVECINT_PWR_DROP: - __no_operation(); - break; - case USBVECINT_PLL_LOCK: - break; - case USBVECINT_PLL_SIGNAL: - break; - case USBVECINT_PLL_RANGE: - if (wUsbEventMask & kUSB_clockFaultEvent) - { - bWakeUp = USB_handleClockEvent(); - } - break; - case USBVECINT_PWR_VBUSOn: - PWRVBUSonHandler(); - if (wUsbEventMask & kUSB_VbusOnEvent) - { - bWakeUp = USB_handleVbusOnEvent(); - } - break; - case USBVECINT_PWR_VBUSOff: - PWRVBUSoffHandler(); - if (wUsbEventMask & kUSB_VbusOffEvent) - { - bWakeUp = USB_handleVbusOffEvent(); - } - break; - case USBVECINT_USB_TIMESTAMP: - break; - case USBVECINT_INPUT_ENDPOINT0: - IEP0InterruptHandler(); - break; - case USBVECINT_OUTPUT_ENDPOINT0: - OEP0InterruptHandler(); - break; - case USBVECINT_RSTR: - USB_reset(); - if (wUsbEventMask & kUSB_UsbResetEvent) - { - bWakeUp = USB_handleResetEvent(); - } - break; - case USBVECINT_SUSR: - USB_suspend(); - if (wUsbEventMask & kUSB_UsbSuspendEvent) - { - bWakeUp = USB_handleSuspendEvent(); - } - break; - case USBVECINT_RESR: - USB_resume(); - if (wUsbEventMask & kUSB_UsbResumeEvent) - { - bWakeUp = USB_handleResumeEvent(); - } - //-- after resume we will wake up! Independ what event handler says. - bWakeUp = TRUE; - break; - case USBVECINT_SETUP_PACKET_RECEIVED: - // NAK both IEP and OEP enpoints - tEndPoint0DescriptorBlock.bIEPBCNT = EPBCNT_NAK; - tEndPoint0DescriptorBlock.bOEPBCNT = EPBCNT_NAK; - SetupPacketInterruptHandler(); - break; - case USBVECINT_STPOW_PACKET_RECEIVED: - break; - case USBVECINT_INPUT_ENDPOINT1: - break; - case USBVECINT_INPUT_ENDPOINT2: - //send saved bytes from buffer... -// bWakeUp = CdcToHostFromBuffer(CDC0_INTFNUM); - - #ifdef UART0_INTFNUM - bWakeUp = UartToCdc(UART0_INTFNUM, CDC0_INTFNUM); - #else - //send saved bytes from buffer... - bWakeUp = CdcToHostFromBuffer(CDC0_INTFNUM); - #endif - - - break; - case USBVECINT_INPUT_ENDPOINT3: - break; - case USBVECINT_INPUT_ENDPOINT4: - //send saved bytes from buffer... -// bWakeUp = CdcToHostFromBuffer(CDC1_INTFNUM); -#if CDC_NUM_INTERFACES >= 2 - #ifdef UART1_INTFNUM - bWakeUp = UartToCdc(UART1_INTFNUM, CDC1_INTFNUM); - #else - //send saved bytes from buffer... - bWakeUp = CdcToHostFromBuffer(CDC1_INTFNUM); - #endif -#endif - - - break; - case USBVECINT_INPUT_ENDPOINT5: - break; - case USBVECINT_INPUT_ENDPOINT6: - break; - case USBVECINT_INPUT_ENDPOINT7: - break; - case USBVECINT_OUTPUT_ENDPOINT1: - break; - case USBVECINT_OUTPUT_ENDPOINT2: - //call callback function if no receive operation is underway -/* - if (!CdcIsReceiveInProgress(CDC0_INTFNUM)) - { - if (wUsbEventMask & kUSB_dataReceivedEvent) - { - bWakeUp = USBCDC_handleDataReceived(CDC0_INTFNUM); - } - } - else - { - //complete receive opereation - copy data to user buffer - bWakeUp = CdcToBufferFromHost(CDC0_INTFNUM); - } -*/ - - #ifdef UART0_INTFNUM - bWakeUp = CdcToUart(CDC0_INTFNUM, UART0_INTFNUM); - #else - //call callback function if no receive operation is underway - if (!CdcIsReceiveInProgress(CDC0_INTFNUM)) - { - if (wUsbEventMask & kUSB_dataReceivedEvent) - { - bWakeUp = USBCDC_handleDataReceived(CDC0_INTFNUM); - } - } - else - { - //complete receive opereation - copy data to user buffer - bWakeUp = CdcToBufferFromHost(CDC0_INTFNUM); - } - #endif - - - break; - case USBVECINT_OUTPUT_ENDPOINT3: - break; - case USBVECINT_OUTPUT_ENDPOINT4: - //call callback function if no receive operation is underway -/* - if (!CdcIsReceiveInProgress(CDC1_INTFNUM)) - { - if (wUsbEventMask & kUSB_dataReceivedEvent) - { - bWakeUp = USBCDC_handleDataReceived(CDC1_INTFNUM); - } - } - else - { - //complete receive opereation - copy data to user buffer - bWakeUp = CdcToBufferFromHost(CDC1_INTFNUM); - } -*/ - -#if CDC_NUM_INTERFACES >= 2 - #ifdef UART1_INTFNUM - bWakeUp = CdcToUart(CDC1_INTFNUM, UART1_INTFNUM); - #else - //call callback function if no receive operation is underway - if (!CdcIsReceiveInProgress(CDC1_INTFNUM)) - { - if (wUsbEventMask & kUSB_dataReceivedEvent) - { - bWakeUp = USBCDC_handleDataReceived(CDC1_INTFNUM); - } - } - else - { - //complete receive opereation - copy data to user buffer - bWakeUp = CdcToBufferFromHost(CDC1_INTFNUM); - } - #endif -#endif - - break; - case USBVECINT_OUTPUT_ENDPOINT5: - break; - case USBVECINT_OUTPUT_ENDPOINT6: - break; - case USBVECINT_OUTPUT_ENDPOINT7: - break; - default: - break; - } - if (bWakeUp) - { - __bic_SR_register_on_exit(LPM3_bits); // Exit LPM0-3 - __no_operation(); // Required for debugger - } -} - -/*----------------------------------------------------------------------------+ -| Interrupt Sub-routines | -+----------------------------------------------------------------------------*/ -BYTE SetupPacketInterruptHandler(VOID) -{ - BYTE bTemp; - BYTE bWakeUp = FALSE; - USBCTL |= FRSTE; // Function Reset Connection Enable - set enable after first setup packet was received - usbProcessNewSetupPacket: - // copy the MSB of bmRequestType to DIR bit of USBCTL - if((tSetupPacket.bmRequestType & USB_REQ_TYPE_INPUT) == USB_REQ_TYPE_INPUT) - { - USBCTL |= DIR; - } - else - { - USBCTL &= ~DIR; - } - bStatusAction = STATUS_ACTION_NOTHING; - // clear out return data buffer - for(bTemp=0; bTemp access to configuration registers enabled - bEnumerationStatus = 0x00; // device is not enumerated - bFunctionSuspended = FALSE; // device is not suspended - USBCNF = 0; // disable USB module - USBPLLCTL &= ~UPLLEN; // disable PLL - USBPWRCTL &= ~(VBOFFIE + VBOFFIFG + SLDOEN); // disable interrupt VBUSoff - USBKEYPID = 0x9600; // access to configuration registers disabled - } -} - -//---------------------------------------------------------------------------- -VOID PWRVBUSonHandler(VOID) -{ - volatile unsigned int i; - for (i =0; i < USB_MCLK_FREQ/1000*1/10; i++); // waiting till voltage will be stable (1ms delay) - USBKEYPID = 0x9628; // set KEY and PID to 0x9628 -> access to configuration registers enabled - USBPWRCTL |= VBOFFIE; // enable interrupt VBUSoff - USBPWRCTL &= ~ (VBONIFG + VBOFFIFG); // clean int flag (bouncing) - USBKEYPID = 0x9600; // access to configuration registers disabled -} - -//---------------------------------------------------------------------------- -VOID IEP0InterruptHandler(VOID) -{ - USBCTL |= FRSTE; // Function Reset Connection Enable - tEndPoint0DescriptorBlock.bOEPBCNT = 0x00; - if(bStatusAction == STATUS_ACTION_DATA_IN) - { - usbSendNextPacketOnIEP0(); - } - else - { - tEndPoint0DescriptorBlock.bIEPCNFG |= EPCNF_STALL; // no more data - } -} - -//---------------------------------------------------------------------------- -VOID OEP0InterruptHandler(VOID) -{ - USBCTL |= FRSTE; // Function Reset Connection Enable - tEndPoint0DescriptorBlock.bIEPBCNT = 0x00; - if(bStatusAction == STATUS_ACTION_DATA_OUT) - { - usbReceiveNextPacketOnOEP0(); - if(bStatusAction == STATUS_ACTION_NOTHING) - { -# ifdef _CDC_ - if(tSetupPacket.bRequest == USB_CDC_SET_LINE_CODING) - { - switch(tSetupPacket.wIndex) - { - case 0: - case 1: - Handler_SetLineCoding0(); - break; - case 2: - case 3: - Handler_SetLineCoding1(); - break; - case 4: - case 5: - Handler_SetLineCoding2(); - break; - } - } -# endif - } - } - else - { - tEndPoint0DescriptorBlock.bOEPCNFG |= EPCNF_STALL; // no more data - } -} - -/*----------------------------------------------------------------------------+ -| End of source file | -+----------------------------------------------------------------------------*/ -/*------------------------ Nothing Below This Line --------------------------*/ +/* --COPYRIGHT--,BSD + * Copyright (c) 2013, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 'AS IS' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ + +/*-----------------------------------------------------------------------------+ +| Include files | +|-----------------------------------------------------------------------------*/ +#include + // Basic Type declarations +#include +#include "descriptors.h" +#include //USB-specific Data Structures +#include +#include + +#include +/*----------------------------------------------------------------------------+ +| External Variables | ++----------------------------------------------------------------------------*/ +extern uint8_t bFunctionSuspended; +extern __no_init tEDB0 __data16 tEndPoint0DescriptorBlock; +extern __no_init tEDB __data16 tInputEndPointDescriptorBlock[]; +extern __no_init tEDB __data16 tOutputEndPointDescriptorBlock[]; +extern volatile uint8_t bHostAsksUSBData; +extern volatile uint8_t bTransferInProgress; +extern volatile uint8_t bSecondUartTxDataCounter[]; +extern volatile uint8_t* pbSecondUartTxData; +extern uint8_t bStatusAction; +extern uint16_t wUsbEventMask; +int16_t CdcToHostFromBuffer(uint8_t); +int16_t CdcToBufferFromHost(uint8_t); +int16_t CdcIsReceiveInProgress(uint8_t); +int16_t HidToHostFromBuffer(uint8_t); +int16_t HidToBufferFromHost(uint8_t); +int16_t HidIsReceiveInProgress(uint8_t); +extern uint16_t wUsbHidEventMask; +int16_t PHDCToHostFromBuffer(uint8_t); +int16_t PHDCToBufferFromHost(uint8_t); +int16_t PHDCIsReceiveInProgress(uint8_t); +uint16_t USB_determineFreq(void); +/*----------------------------------------------------------------------------+ +| General Subroutines | ++----------------------------------------------------------------------------*/ +#if defined(__TI_COMPILER_VERSION__) || (__IAR_SYSTEMS_ICC__) +#pragma vector=USB_UBM_VECTOR +__interrupt void iUsbInterruptHandler(void) +#elif defined(__GNUC__) && (__MSP430__) +void __attribute__ ((interrupt(USB_UBM_VECTOR))) iUsbInterruptHandler(void) +#endif +{ + uint8_t bWakeUp = FALSE; + //Check if the setup interrupt is pending. + //We need to check it before other interrupts, + //to work around that the Setup Int has lower priority then Input Endpoint 0 + if (USBIFG & SETUPIFG) + { + bWakeUp = SetupPacketInterruptHandler(); +#ifdef USB10_WORKAROUND + tEndPoint0DescriptorBlock.bIEPCNFG &= ~EPCNF_UBME; // Clear ME to gate off SETUPIFG clear event + tEndPoint0DescriptorBlock.bOEPCNFG &= ~EPCNF_UBME; // Clear ME to gate off SETUPIFG clear event +#endif + USBIFG &= ~SETUPIFG; // clear the interrupt bit +#ifdef USB10_WORKAROUND + tEndPoint0DescriptorBlock.bIEPCNFG |= EPCNF_UBME; // Set ME to continue with normal operation + tEndPoint0DescriptorBlock.bOEPCNFG |= EPCNF_UBME; // Set ME to continue with normal operation +#endif + } + switch (__even_in_range(USBVECINT & 0x3f, USBVECINT_OUTPUT_ENDPOINT7)) + { + case USBVECINT_NONE: + break; + case USBVECINT_PWR_DROP: + __no_operation(); + break; + case USBVECINT_PLL_LOCK: + break; + case USBVECINT_PLL_SIGNAL: + break; + case USBVECINT_PLL_RANGE: + if (wUsbEventMask & kUSB_clockFaultEvent) + { + bWakeUp = USB_handleClockEvent(); + } + break; + case USBVECINT_PWR_VBUSOn: + PWRVBUSonHandler(); + if (wUsbEventMask & kUSB_VbusOnEvent) + { + bWakeUp = USB_handleVbusOnEvent(); + } + break; + case USBVECINT_PWR_VBUSOff: + PWRVBUSoffHandler(); + if (wUsbEventMask & kUSB_VbusOffEvent) + { + bWakeUp = USB_handleVbusOffEvent(); + } + break; + case USBVECINT_USB_TIMESTAMP: + break; + case USBVECINT_INPUT_ENDPOINT0: + IEP0InterruptHandler(); + break; + case USBVECINT_OUTPUT_ENDPOINT0: + OEP0InterruptHandler(); + break; + case USBVECINT_RSTR: + USB_reset(); + if (wUsbEventMask & kUSB_UsbResetEvent) + { + bWakeUp = USB_handleResetEvent(); + } + break; + case USBVECINT_SUSR: + USB_suspend(); + if (wUsbEventMask & kUSB_UsbSuspendEvent) + { + bWakeUp = USB_handleSuspendEvent(); + } + break; + case USBVECINT_RESR: + USB_resume(); + if (wUsbEventMask & kUSB_UsbResumeEvent) + { + bWakeUp = USB_handleResumeEvent(); + } + //-- after resume we will wake up! Independ what event handler says. + bWakeUp = TRUE; + break; + case USBVECINT_SETUP_PACKET_RECEIVED: + // NAK both IEP and OEP enpoints + tEndPoint0DescriptorBlock.bIEPBCNT = EPBCNT_NAK; + tEndPoint0DescriptorBlock.bOEPBCNT = EPBCNT_NAK; + SetupPacketInterruptHandler(); + break; + case USBVECINT_STPOW_PACKET_RECEIVED: + break; + case USBVECINT_INPUT_ENDPOINT1: + break; + case USBVECINT_INPUT_ENDPOINT2: + //send saved bytes from buffer... + bWakeUp = CdcToHostFromBuffer(CDC0_INTFNUM); + break; + case USBVECINT_INPUT_ENDPOINT3: + break; + case USBVECINT_INPUT_ENDPOINT4: + break; + case USBVECINT_INPUT_ENDPOINT5: + break; + case USBVECINT_INPUT_ENDPOINT6: + break; + case USBVECINT_INPUT_ENDPOINT7: + break; + case USBVECINT_OUTPUT_ENDPOINT1: + break; + case USBVECINT_OUTPUT_ENDPOINT2: + //call callback function if no receive operation is underway + if (!CdcIsReceiveInProgress(CDC0_INTFNUM) && USBCDC_bytesInUSBBuffer(CDC0_INTFNUM)) + { + if (wUsbEventMask & kUSB_dataReceivedEvent) + { + bWakeUp = USBCDC_handleDataReceived(CDC0_INTFNUM); + } + } + else + { + //complete receive opereation - copy data to user buffer + bWakeUp = CdcToBufferFromHost(CDC0_INTFNUM); + } + break; + case USBVECINT_OUTPUT_ENDPOINT3: + break; + case USBVECINT_OUTPUT_ENDPOINT4: + break; + case USBVECINT_OUTPUT_ENDPOINT5: + break; + case USBVECINT_OUTPUT_ENDPOINT6: + break; + case USBVECINT_OUTPUT_ENDPOINT7: + break; + default: + break; + } + if (bWakeUp) + { + __bic_SR_register_on_exit(LPM3_bits); // Exit LPM0-3 + __no_operation(); // Required for debugger + } +} + +/*----------------------------------------------------------------------------+ +| Interrupt Sub-routines | ++----------------------------------------------------------------------------*/ +uint8_t SetupPacketInterruptHandler(void) +{ + uint8_t bTemp; + uint8_t bWakeUp = FALSE; + USBCTL |= FRSTE; // Function Reset Connection Enable - set enable after first setup packet was received + usbProcessNewSetupPacket: + // copy the MSB of bmRequestType to DIR bit of USBCTL + if((tSetupPacket.bmRequestType & USB_REQ_TYPE_INPUT) == USB_REQ_TYPE_INPUT) + { + USBCTL |= DIR; + } + else + { + USBCTL &= ~DIR; + } + bStatusAction = STATUS_ACTION_NOTHING; + // clear out return data buffer + for(bTemp=0; bTemp> 6) + (MCLKFreq >> 7) + (MCLKFreq >> 9)); + volatile uint16_t i, j; + + //wait 1 ms till enable USB + for(j = 0; j < 4; j++) + { + for (i = 0; i < (DelayConstant_250us); i++){ + _NOP(); + } + } + if (!(USBPWRCTL & USBBGVBV)) + { + USBKEYPID = 0x9628; // set KEY and PID to 0x9628 -> access to configuration registers enabled + bEnumerationStatus = 0x00; // device is not enumerated + bFunctionSuspended = FALSE; // device is not suspended + USBCNF = 0; // disable USB module + USBPLLCTL &= ~UPLLEN; // disable PLL + USBPWRCTL &= ~(VBOFFIE + VBOFFIFG + SLDOEN); // disable interrupt VBUSoff + USBKEYPID = 0x9600; // access to configuration registers disabled + } +} + +//---------------------------------------------------------------------------- +void PWRVBUSonHandler(void) +{ + uint16_t MCLKFreq = USB_determineFreq(); + uint16_t DelayConstant_250us = ((MCLKFreq >> 6) + (MCLKFreq >> 7) + (MCLKFreq >> 9)); + volatile uint16_t i, j; + + //wait 1 ms till enable USB + for(j = 0; j < 4; j++) + { + for (i = 0; i < (DelayConstant_250us); i++){ + _NOP(); + } + } + USBKEYPID = 0x9628; // set KEY and PID to 0x9628 -> access to configuration registers enabled + USBPWRCTL |= VBOFFIE; // enable interrupt VBUSoff + USBPWRCTL &= ~ (VBONIFG + VBOFFIFG); // clean int flag (bouncing) + USBKEYPID = 0x9600; // access to configuration registers disabled +} + +//---------------------------------------------------------------------------- +void IEP0InterruptHandler(void) +{ + USBCTL |= FRSTE; // Function Reset Connection Enable + tEndPoint0DescriptorBlock.bOEPBCNT = 0x00; + if(bStatusAction == STATUS_ACTION_DATA_IN) + { + usbSendNextPacketOnIEP0(); + } + else + { + tEndPoint0DescriptorBlock.bIEPCNFG |= EPCNF_STALL; // no more data + } +} + +//---------------------------------------------------------------------------- +uint8_t OEP0InterruptHandler(void) +{ + uint8_t bWakeUp = FALSE; + USBCTL |= FRSTE; // Function Reset Connection Enable + tEndPoint0DescriptorBlock.bIEPBCNT = 0x00; + if(bStatusAction == STATUS_ACTION_DATA_OUT) + { + usbReceiveNextPacketOnOEP0(); + if(bStatusAction == STATUS_ACTION_NOTHING) + { +# ifdef _CDC_ + if(tSetupPacket.bRequest == USB_CDC_SET_LINE_CODING) + { + bWakeUp = Handler_SetLineCoding(); + } +# endif +#ifdef _HID_ + if (tSetupPacket.bRequest == USB_REQ_SET_REPORT) { + bWakeUp = USBHID_handleEP0SetReportDataAvailable(tSetupPacket.wIndex); + } +#endif + } + } + else + { + tEndPoint0DescriptorBlock.bOEPCNFG |= EPCNF_STALL; // no more data + } + return (bWakeUp); +} + + + +/*----------------------------------------------------------------------------+ +| End of source file | ++----------------------------------------------------------------------------*/ +/*------------------------ Nothing Below This Line --------------------------*/ diff --git a/USB_config/descriptors.c b/source/USB_config/descriptors.c similarity index 62% rename from USB_config/descriptors.c rename to source/USB_config/descriptors.c index d8f0604..3aaca71 100644 --- a/USB_config/descriptors.c +++ b/source/USB_config/descriptors.c @@ -1,368 +1,372 @@ -// (c)2010 by Texas Instruments Incorporated, All Rights Reserved. -/*-----------------------------------------------------------------------------+ -| | -| Texas Instruments | -| | -| This is an automatically generated script by MSP430 USB Descriptor Tool | -| | -| Descriptor Tool Version: 3.0.10 | -| Date: 2011/10/25 21:16:05 | -| | -| Descriptor.c | -|-----------------------------------------------------------------------------*/ - -/*-----------------------------------------------------------------------------+ -| Include files | -|-----------------------------------------------------------------------------*/ -#include -#include // Basic Type declarations -#include -#include // USB-specific Data Structures -#include "descriptors.h" -#include -#include - -/*-----------------------------------------------------------------------------+ -| Device Descriptor | -|-----------------------------------------------------------------------------*/ -BYTE const abromDeviceDescriptor[SIZEOF_DEVICE_DESCRIPTOR] = { - SIZEOF_DEVICE_DESCRIPTOR, // Length of this descriptor - DESC_TYPE_DEVICE, // Type code of this descriptor - 0x00, 0x02, // Release of USB spec - 0x02, // Device's base class code - 0x00, // Device's sub class code - 0x00, // Device's protocol type code - EP0_PACKET_SIZE, // End point 0's packet size - USB_VID&0xFF, USB_VID>>8, // Vendor ID for device, TI=0x0451 - // You can order your own VID at www.usb.org - USB_PID&0xFF, USB_PID>>8, // Product ID for device, - // this ID is to only with this example - VER_FW_L, VER_FW_H, // Revision level of device - 1, // Index of manufacturer name string desc - 2, // Index of product name string desc - USB_STR_INDEX_SERNUM, // Index of serial number string desc - 1 // Number of configurations supported -}; - -/*-----------------------------------------------------------------------------+ -| Configuration Descriptor | -|-----------------------------------------------------------------------------*/ -const struct abromConfigurationDescriptorGroup abromConfigurationDescriptorGroup= -{ - /* Generic part */ - { - // CONFIGURATION DESCRIPTOR (9 bytes) - SIZEOF_CONFIG_DESCRIPTOR, // bLength - DESC_TYPE_CONFIG, // bDescriptorType - DESCRIPTOR_TOTAL_LENGTH, 0x00, // wTotalLength - USB_NUM_INTERFACES, // bNumInterfaces - USB_CONFIG_VALUE, // bConfigurationvalue - CONFIG_STRING_INDEX, // iConfiguration Description offset - USB_SUPPORT_SELF_POWERED | USB_SUPPORT_REM_WAKE, // bmAttributes, bus power, remote wakeup - USB_MAX_POWER // Max. Power Consumption - }, - - /******************************************************* start of CDC*************************************/ - - { - /* start CDC[0] */ - { - - //INTERFACE DESCRIPTOR (9 bytes) - 0x09, // bLength: Interface Descriptor size - DESC_TYPE_INTERFACE, // bDescriptorType: Interface - CDC0_COMM_INTERFACE, // bInterfaceNumber - 0x00, // bAlternateSetting: Alternate setting - 0x01, // bNumEndpoints: Three endpoints used - 0x02, // bInterfaceClass: Communication Interface Class - 0x02, // bInterfaceSubClass: Abstract Control Model - 0x01, // bInterfaceProtocol: Common AT commands - INTF_STRING_INDEX + 0, // iInterface: - - //Header Functional Descriptor - 0x05, // bLength: Endpoint Descriptor size - 0x24, // bDescriptorType: CS_INTERFACE - 0x00, // bDescriptorSubtype: Header Func Desc - 0x10, // bcdCDC: spec release number - 0x01, - - //Call Managment Functional Descriptor - 0x05, // bFunctionLength - 0x24, // bDescriptorType: CS_INTERFACE - 0x01, // bDescriptorSubtype: Call Management Func Desc - 0x00, // bmCapabilities: D0+D1 - CDC0_DATA_INTERFACE, // bDataInterface: 0 - - //ACM Functional Descriptor - 0x04, // bFunctionLength - 0x24, // bDescriptorType: CS_INTERFACE - 0x02, // bDescriptorSubtype: Abstract Control Management desc - 0x02, // bmCapabilities - - // Union Functional Descriptor - 0x05, // Size, in bytes - 0x24, // bDescriptorType: CS_INTERFACE - 0x06, // bDescriptorSubtype: Union Functional Desc - CDC0_COMM_INTERFACE, // bMasterInterface -- the controlling intf for the union - CDC0_DATA_INTERFACE, // bSlaveInterface -- the controlled intf for the union - - //EndPoint Descriptor for Interrupt endpoint - SIZEOF_ENDPOINT_DESCRIPTOR, // bLength: Endpoint Descriptor size - DESC_TYPE_ENDPOINT, // bDescriptorType: Endpoint - CDC0_INTEP_ADDR, // bEndpointAddress: (IN2) - EP_DESC_ATTR_TYPE_INT, // bmAttributes: Interrupt - 0x40, 0x00, // wMaxPacketSize, 64 bytes - 0xFF, // bInterval - - //DATA INTERFACE DESCRIPTOR (9 bytes) - 0x09, // bLength: Interface Descriptor size - DESC_TYPE_INTERFACE, // bDescriptorType: Interface - CDC0_DATA_INTERFACE, // bInterfaceNumber - 0x00, // bAlternateSetting: Alternate setting - 0x02, // bNumEndpoints: Three endpoints used - 0x0A, // bInterfaceClass: Data Interface Class - 0x00, // bInterfaceSubClass: - 0x00, // bInterfaceProtocol: No class specific protocol required - 0x00, // iInterface: - - //EndPoint Descriptor for Output endpoint - SIZEOF_ENDPOINT_DESCRIPTOR, // bLength: Endpoint Descriptor size - DESC_TYPE_ENDPOINT, // bDescriptorType: Endpoint - CDC0_OUTEP_ADDR, // bEndpointAddress: (OUT3) - EP_DESC_ATTR_TYPE_BULK, // bmAttributes: Bulk - 0x40, 0x00, // wMaxPacketSize, 64 bytes - 0xFF, // bInterval: ignored for Bulk transfer - - //EndPoint Descriptor for Input endpoint - SIZEOF_ENDPOINT_DESCRIPTOR, // bLength: Endpoint Descriptor size - DESC_TYPE_ENDPOINT, // bDescriptorType: Endpoint - CDC0_INEP_ADDR, // bEndpointAddress: (IN3) - EP_DESC_ATTR_TYPE_BULK, // bmAttributes: Bulk - 0x40, 0x00, // wMaxPacketSize, 64 bytes - 0xFF // bInterval: ignored for bulk transfer - } - - /* end CDC[0]*/ - - } - /******************************************************* end of CDC**************************************/ - -}; -/*-----------------------------------------------------------------------------+ -| String Descriptor | -|-----------------------------------------------------------------------------*/ -BYTE const abromStringDescriptor[] = { - - // String index0, language support - 4, // Length of language descriptor ID - 3, // LANGID tag - 0x09, 0x04, // 0x0409 for English - - // String index1, Manufacturer - 36, // Length of this string descriptor - 3, // bDescriptorType - 'T',0x00,'e',0x00,'x',0x00,'a',0x00,'s',0x00,' ',0x00, - 'I',0x00,'n',0x00,'s',0x00,'t',0x00,'r',0x00,'u',0x00, - 'm',0x00,'e',0x00,'n',0x00,'t',0x00,'s',0x00, - - // String index2, Product - 34, // Length of this string descriptor - 3, // bDescriptorType - 'M',0x00,'S',0x00,'P',0x00,' ',0x00,'B',0x00,'S',0x00, - 'L',0x00,' ',0x00,'U',0x00,'S',0x00,'B',0x00,' ',0x00, - 'T',0x00,'o',0x00,'o',0x00,'l',0x00, - - // String index3, Serial Number - 4, // Length of this string descriptor - 3, // bDescriptorType - '0',0x00, - - // String index4, Configuration String - 22, // Length of this string descriptor - 3, // bDescriptorType - 'M',0x00,'S',0x00,'P',0x00,'4',0x00,'3',0x00,'0',0x00, - ' ',0x00,'U',0x00,'S',0x00,'B',0x00, - - // String index5, Interface String - 34, // Length of this string descriptor - 3, // bDescriptorType - 'M',0x00,'S',0x00,'P',0x00,' ',0x00,'B',0x00,'S',0x00, - 'L',0x00,' ',0x00,'U',0x00,'S',0x00,'B',0x00,' ',0x00, - 'T',0x00,'o',0x00,'o',0x00,'l',0x00 -}; - -/**** Populating the endpoint information handle here ****/ - -const struct tUsbHandle stUsbHandle[]= -{ - { - CDC0_INEP_ADDR, - CDC0_OUTEP_ADDR, - 1, - CDC_CLASS, - IEP1_X_BUFFER_ADDRESS, - IEP1_Y_BUFFER_ADDRESS, - OEP2_X_BUFFER_ADDRESS, - OEP2_Y_BUFFER_ADDRESS, - IEP2_X_BUFFER_ADDRESS, - IEP2_Y_BUFFER_ADDRESS - } -}; -//-------------DEVICE REQUEST LIST--------------------------------------------- - -const tDEVICE_REQUEST_COMPARE tUsbRequestList[] = -{ - - //---- CDC 0 Class Requests -----// - // GET LINE CODING - USB_REQ_TYPE_INPUT | USB_REQ_TYPE_CLASS | USB_REQ_TYPE_INTERFACE, - USB_CDC_GET_LINE_CODING, - 0x00,0x00, // always zero - CDC0_COMM_INTERFACE,0x00, // CDC interface is 0 - 0x07,0x00, // Size of Structure (data length) - 0xff,&usbGetLineCoding0, - - // SET LINE CODING - USB_REQ_TYPE_OUTPUT | USB_REQ_TYPE_CLASS | USB_REQ_TYPE_INTERFACE, - USB_CDC_SET_LINE_CODING, - 0x00,0x00, // always zero - CDC0_COMM_INTERFACE,0x00, // CDC interface is 0 - 0x07,0x00, // Size of Structure (data length) - 0xff,&usbSetLineCoding0, - - // SET CONTROL LINE STATE - USB_REQ_TYPE_OUTPUT | USB_REQ_TYPE_CLASS | USB_REQ_TYPE_INTERFACE, - USB_CDC_SET_CONTROL_LINE_STATE, - 0xff,0xff, // Contains data - CDC0_COMM_INTERFACE,0x00, // CDC interface is 0 - 0x00,0x00, // No further data - 0xcf,&usbSetControlLineState0, - - //---- USB Standard Requests -----// - // clear device feature - USB_REQ_TYPE_OUTPUT | USB_REQ_TYPE_STANDARD | USB_REQ_TYPE_DEVICE, - USB_REQ_CLEAR_FEATURE, - FEATURE_REMOTE_WAKEUP,0x00, // feature selector - 0x00,0x00, - 0x00,0x00, - 0xff,&usbClearDeviceFeature, - - // clear endpoint feature - USB_REQ_TYPE_OUTPUT | USB_REQ_TYPE_STANDARD | USB_REQ_TYPE_ENDPOINT, - USB_REQ_CLEAR_FEATURE, - FEATURE_ENDPOINT_STALL,0x00, - 0xff,0x00, - 0x00,0x00, - 0xf7,&usbClearEndpointFeature, - - // get configuration - USB_REQ_TYPE_INPUT | USB_REQ_TYPE_STANDARD | USB_REQ_TYPE_DEVICE, - USB_REQ_GET_CONFIGURATION, - 0x00,0x00, - 0x00,0x00, - 0x01,0x00, - 0xff,&usbGetConfiguration, - - // get device descriptor - USB_REQ_TYPE_INPUT | USB_REQ_TYPE_STANDARD | USB_REQ_TYPE_DEVICE, - USB_REQ_GET_DESCRIPTOR, - 0xff,DESC_TYPE_DEVICE, // bValueL is index and bValueH is type - 0xff,0xff, - 0xff,0xff, - 0xd0,&usbGetDeviceDescriptor, - - // get configuration descriptor - USB_REQ_TYPE_INPUT | USB_REQ_TYPE_STANDARD | USB_REQ_TYPE_DEVICE, - USB_REQ_GET_DESCRIPTOR, - 0xff,DESC_TYPE_CONFIG, // bValueL is index and bValueH is type - 0xff,0xff, - 0xff,0xff, - 0xd0,&usbGetConfigurationDescriptor, - - // get string descriptor - USB_REQ_TYPE_INPUT | USB_REQ_TYPE_STANDARD | USB_REQ_TYPE_DEVICE, - USB_REQ_GET_DESCRIPTOR, - 0xff,DESC_TYPE_STRING, // bValueL is index and bValueH is type - 0xff,0xff, - 0xff,0xff, - 0xd0,&usbGetStringDescriptor, - - // get interface - USB_REQ_TYPE_INPUT | USB_REQ_TYPE_STANDARD | USB_REQ_TYPE_INTERFACE, - USB_REQ_GET_INTERFACE, - 0x00,0x00, - 0xff,0xff, - 0x01,0x00, - 0xf3,&usbGetInterface, - - // get device status - USB_REQ_TYPE_INPUT | USB_REQ_TYPE_STANDARD | USB_REQ_TYPE_DEVICE, - USB_REQ_GET_STATUS, - 0x00,0x00, - 0x00,0x00, - 0x02,0x00, - 0xff,&usbGetDeviceStatus, - // get interface status - USB_REQ_TYPE_INPUT | USB_REQ_TYPE_STANDARD | USB_REQ_TYPE_INTERFACE, - USB_REQ_GET_STATUS, - 0x00,0x00, - 0xff,0x00, - 0x02,0x00, - 0xf7,&usbGetInterfaceStatus, - // get endpoint status - USB_REQ_TYPE_INPUT | USB_REQ_TYPE_STANDARD | USB_REQ_TYPE_ENDPOINT, - USB_REQ_GET_STATUS, - 0x00,0x00, - 0xff,0x00, - 0x02,0x00, - 0xf7,&usbGetEndpointStatus, - - // set address - USB_REQ_TYPE_OUTPUT | USB_REQ_TYPE_STANDARD | USB_REQ_TYPE_DEVICE, - USB_REQ_SET_ADDRESS, - 0xff,0x00, - 0x00,0x00, - 0x00,0x00, - 0xdf,&usbSetAddress, - - // set configuration - USB_REQ_TYPE_OUTPUT | USB_REQ_TYPE_STANDARD | USB_REQ_TYPE_DEVICE, - USB_REQ_SET_CONFIGURATION, - 0xff,0x00, - 0x00,0x00, - 0x00,0x00, - 0xdf,&usbSetConfiguration, - - // set device feature - USB_REQ_TYPE_OUTPUT | USB_REQ_TYPE_STANDARD | USB_REQ_TYPE_DEVICE, - USB_REQ_SET_FEATURE, - 0xff,0x00, // feature selector - 0x00,0x00, - 0x00,0x00, - 0xdf,&usbSetDeviceFeature, - - // set endpoint feature - USB_REQ_TYPE_OUTPUT | USB_REQ_TYPE_STANDARD | USB_REQ_TYPE_ENDPOINT, - USB_REQ_SET_FEATURE, - 0xff,0x00, // feature selector - 0xff,0x00, // endpoint number <= 127 - 0x00,0x00, - 0xd7,&usbSetEndpointFeature, - - // set interface - USB_REQ_TYPE_OUTPUT | USB_REQ_TYPE_STANDARD | USB_REQ_TYPE_INTERFACE, - USB_REQ_SET_INTERFACE, - 0xff,0x00, // feature selector - 0xff,0x00, // interface number - 0x00,0x00, - 0xd7,&usbSetInterface, - - // end of usb descriptor -- this one will be matched to any USB request - // since bCompareMask is 0x00. - 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, - 0x00,&usbInvalidRequest // end of list -}; - -/*-----------------------------------------------------------------------------+ -| END OF Descriptor.c FILE | -|-----------------------------------------------------------------------------*/ +/* --COPYRIGHT--,BSD + * Copyright (c) 2013, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 'AS IS' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ + +/*-----------------------------------------------------------------------------+ +| Include files | +|-----------------------------------------------------------------------------*/ +#include +#include +#include // USB-specific Data Structures +#include "descriptors.h" +#include +#include + +/*-----------------------------------------------------------------------------+ +| Device Descriptor | +|-----------------------------------------------------------------------------*/ +uint8_t const abromDeviceDescriptor[SIZEOF_DEVICE_DESCRIPTOR] = { + SIZEOF_DEVICE_DESCRIPTOR, // Length of this descriptor + DESC_TYPE_DEVICE, // Type code of this descriptor + 0x00, 0x02, // Release of USB spec + 0x02, // Device's base class code + 0x00, // Device's sub class code + 0x00, // Device's protocol type code + EP0_PACKET_SIZE, // End point 0's packet size + USB_VID&0xFF, USB_VID>>8, // Vendor ID for device, TI=0x0451 + // You can order your own VID at www.usb.org + USB_PID&0xFF, USB_PID>>8, // Product ID for device, + // this ID is to only with this example + VER_FW_L, VER_FW_H, // Revision level of device + 1, // Index of manufacturer name string desc + 2, // Index of product name string desc + USB_STR_INDEX_SERNUM, // Index of serial number string desc + 1 // Number of configurations supported +}; + +/*-----------------------------------------------------------------------------+ +| Configuration Descriptor | +|-----------------------------------------------------------------------------*/ +const struct abromConfigurationDescriptorGroup abromConfigurationDescriptorGroup= +{ + /* Generic part */ + { + // CONFIGURATION DESCRIPTOR (9 bytes) + SIZEOF_CONFIG_DESCRIPTOR, // bLength + DESC_TYPE_CONFIG, // bDescriptorType + DESCRIPTOR_TOTAL_LENGTH, 0x00, // wTotalLength + USB_NUM_INTERFACES, // bNumInterfaces + USB_CONFIG_VALUE, // bConfigurationvalue + CONFIG_STRING_INDEX, // iConfiguration Description offset + USB_SUPPORT_SELF_POWERED | USB_SUPPORT_REM_WAKE, // bmAttributes, bus power, remote wakeup + USB_MAX_POWER // Max. Power Consumption + }, + + /******************************************************* start of CDC*************************************/ + + { + /* start CDC[0] */ + { + + //INTERFACE DESCRIPTOR (9 bytes) + 0x09, // bLength: Interface Descriptor size + DESC_TYPE_INTERFACE, // bDescriptorType: Interface + CDC0_COMM_INTERFACE, // bInterfaceNumber + 0x00, // bAlternateSetting: Alternate setting + 0x01, // bNumEndpoints: Three endpoints used + 0x02, // bInterfaceClass: Communication Interface Class + 0x02, // bInterfaceSubClass: Abstract Control Model + 0x01, // bInterfaceProtocol: Common AT commands + INTF_STRING_INDEX + 0, // iInterface: + + //Header Functional Descriptor + 0x05, // bLength: Endpoint Descriptor size + 0x24, // bDescriptorType: CS_INTERFACE + 0x00, // bDescriptorSubtype: Header Func Desc + 0x10, // bcdCDC: spec release number + 0x01, + + //Call Managment Functional Descriptor + 0x05, // bFunctionLength + 0x24, // bDescriptorType: CS_INTERFACE + 0x01, // bDescriptorSubtype: Call Management Func Desc + 0x00, // bmCapabilities: D0+D1 + CDC0_DATA_INTERFACE, // bDataInterface: 0 + + //ACM Functional Descriptor + 0x04, // bFunctionLength + 0x24, // bDescriptorType: CS_INTERFACE + 0x02, // bDescriptorSubtype: Abstract Control Management desc + 0x02, // bmCapabilities + + // Union Functional Descriptor + 0x05, // Size, in bytes + 0x24, // bDescriptorType: CS_INTERFACE + 0x06, // bDescriptorSubtype: Union Functional Desc + CDC0_COMM_INTERFACE, // bMasterInterface -- the controlling intf for the union + CDC0_DATA_INTERFACE, // bSlaveInterface -- the controlled intf for the union + + //EndPoint Descriptor for Interrupt endpoint + SIZEOF_ENDPOINT_DESCRIPTOR, // bLength: Endpoint Descriptor size + DESC_TYPE_ENDPOINT, // bDescriptorType: Endpoint + CDC0_INTEP_ADDR, // bEndpointAddress: (IN2) + EP_DESC_ATTR_TYPE_INT, // bmAttributes: Interrupt + 0x40, 0x00, // wMaxPacketSize, 64 bytes + 0xFF, // bInterval + + //DATA INTERFACE DESCRIPTOR (9 bytes) + 0x09, // bLength: Interface Descriptor size + DESC_TYPE_INTERFACE, // bDescriptorType: Interface + CDC0_DATA_INTERFACE, // bInterfaceNumber + 0x00, // bAlternateSetting: Alternate setting + 0x02, // bNumEndpoints: Three endpoints used + 0x0A, // bInterfaceClass: Data Interface Class + 0x00, // bInterfaceSubClass: + 0x00, // bInterfaceProtocol: No class specific protocol required + 0x00, // iInterface: + + //EndPoint Descriptor for Output endpoint + SIZEOF_ENDPOINT_DESCRIPTOR, // bLength: Endpoint Descriptor size + DESC_TYPE_ENDPOINT, // bDescriptorType: Endpoint + CDC0_OUTEP_ADDR, // bEndpointAddress: (OUT3) + EP_DESC_ATTR_TYPE_BULK, // bmAttributes: Bulk + 0x40, 0x00, // wMaxPacketSize, 64 bytes + 0xFF, // bInterval: ignored for Bulk transfer + + //EndPoint Descriptor for Input endpoint + SIZEOF_ENDPOINT_DESCRIPTOR, // bLength: Endpoint Descriptor size + DESC_TYPE_ENDPOINT, // bDescriptorType: Endpoint + CDC0_INEP_ADDR, // bEndpointAddress: (IN3) + EP_DESC_ATTR_TYPE_BULK, // bmAttributes: Bulk + 0x40, 0x00, // wMaxPacketSize, 64 bytes + 0xFF // bInterval: ignored for bulk transfer + } + + /* end CDC[0]*/ + + } + /******************************************************* end of CDC**************************************/ + +}; +/*-----------------------------------------------------------------------------+ +| String Descriptor | +|-----------------------------------------------------------------------------*/ +uint8_t const abromStringDescriptor[] = { + + // String index0, language support + 4, // Length of language descriptor ID + 3, // LANGID tag + 0x09, 0x04, // 0x0409 for English + + // String index1, Manufacturer + 36, // Length of this string descriptor + 3, // bDescriptorType + 'T',0x00,'e',0x00,'x',0x00,'a',0x00,'s',0x00,' ',0x00, + 'I',0x00,'n',0x00,'s',0x00,'t',0x00,'r',0x00,'u',0x00, + 'm',0x00,'e',0x00,'n',0x00,'t',0x00,'s',0x00, + + // String index2, Product + 34, // Length of this string descriptor + 3, // bDescriptorType + 'M',0x00,'S',0x00,'P',0x00,' ',0x00,'B',0x00,'S',0x00, + 'L',0x00,' ',0x00,'U',0x00,'S',0x00,'B',0x00,' ',0x00, + 'T',0x00,'o',0x00,'o',0x00,'l',0x00, + + // String index3, Serial Number + 4, // Length of this string descriptor + 3, // bDescriptorType + '0',0x00, + + // String index4, Configuration String + 22, // Length of this string descriptor + 3, // bDescriptorType + 'M',0x00,'S',0x00,'P',0x00,'4',0x00,'3',0x00,'0',0x00, + ' ',0x00,'U',0x00,'S',0x00,'B',0x00, + + // String index5, Interface String + 34, // Length of this string descriptor + 3, // bDescriptorType + 'M',0x00,'S',0x00,'P',0x00,' ',0x00,'B',0x00,'S',0x00, + 'L',0x00,' ',0x00,'U',0x00,'S',0x00,'B',0x00,' ',0x00, + 'T',0x00,'o',0x00,'o',0x00,'l',0x00 +}; + +/**** Populating the endpoint information handle here ****/ + +const struct tUsbHandle stUsbHandle[]= +{ + { + CDC0_INEP_ADDR, + CDC0_OUTEP_ADDR, + 1, + CDC_CLASS, + IEP1_X_BUFFER_ADDRESS, + IEP1_Y_BUFFER_ADDRESS, + OEP2_X_BUFFER_ADDRESS, + OEP2_Y_BUFFER_ADDRESS, + IEP2_X_BUFFER_ADDRESS, + IEP2_Y_BUFFER_ADDRESS + } +}; +//-------------DEVICE REQUEST LIST--------------------------------------------- + +const tDEVICE_REQUEST_COMPARE tUsbRequestList[] = +{ + +//---- CDC 0 Class Requests -----// + // GET LINE CODING + USB_REQ_TYPE_INPUT | USB_REQ_TYPE_CLASS | USB_REQ_TYPE_INTERFACE, + USB_CDC_GET_LINE_CODING, + 0x00,0x00, // always zero + CDC0_COMM_INTERFACE,0x00, // CDC interface is 0 + 0x07,0x00, // Size of Structure (data length) + 0xff,&usbGetLineCoding, +// SET LINE CODING + USB_REQ_TYPE_OUTPUT | USB_REQ_TYPE_CLASS | USB_REQ_TYPE_INTERFACE, + USB_CDC_SET_LINE_CODING, + 0x00,0x00, // always zero + CDC0_COMM_INTERFACE,0x00, // CDC interface is 0 + 0x07,0x00, // Size of Structure (data length) + 0xff,&usbSetLineCoding, + // SET CONTROL LINE STATE + USB_REQ_TYPE_OUTPUT | USB_REQ_TYPE_CLASS | USB_REQ_TYPE_INTERFACE, + USB_CDC_SET_CONTROL_LINE_STATE, + 0xff,0xff, // Contains data + CDC0_COMM_INTERFACE,0x00, // CDC interface is 0 + 0x00,0x00, // No further data + 0xcf,&usbSetControlLineState, + +//---- USB Standard Requests -----// + // clear device feature + USB_REQ_TYPE_OUTPUT | USB_REQ_TYPE_STANDARD | USB_REQ_TYPE_DEVICE, + USB_REQ_CLEAR_FEATURE, + FEATURE_REMOTE_WAKEUP,0x00, // feature selector + 0x00,0x00, + 0x00,0x00, + 0xff,&usbClearDeviceFeature, + +// clear endpoint feature + USB_REQ_TYPE_OUTPUT | USB_REQ_TYPE_STANDARD | USB_REQ_TYPE_ENDPOINT, + USB_REQ_CLEAR_FEATURE, +FEATURE_ENDPOINT_STALL,0x00, + 0xff,0x00, + 0x00,0x00, + 0xf7,&usbClearEndpointFeature, +// get configuration + USB_REQ_TYPE_INPUT | USB_REQ_TYPE_STANDARD | USB_REQ_TYPE_DEVICE, + USB_REQ_GET_CONFIGURATION, + 0x00,0x00, + 0x00,0x00, + 0x01,0x00, + 0xff,&usbGetConfiguration, +// get device descriptor + USB_REQ_TYPE_INPUT | USB_REQ_TYPE_STANDARD | USB_REQ_TYPE_DEVICE, + USB_REQ_GET_DESCRIPTOR, + 0xff,DESC_TYPE_DEVICE, // bValueL is index and bValueH is type + 0xff,0xff, + 0xff,0xff, + 0xd0,&usbGetDeviceDescriptor, +// get configuration descriptor + USB_REQ_TYPE_INPUT | USB_REQ_TYPE_STANDARD | USB_REQ_TYPE_DEVICE, + USB_REQ_GET_DESCRIPTOR, + 0xff,DESC_TYPE_CONFIG, // bValueL is index and bValueH is type + 0xff,0xff, + 0xff,0xff, + 0xd0,&usbGetConfigurationDescriptor, +// get string descriptor + USB_REQ_TYPE_INPUT | USB_REQ_TYPE_STANDARD | USB_REQ_TYPE_DEVICE, + USB_REQ_GET_DESCRIPTOR, + 0xff,DESC_TYPE_STRING, // bValueL is index and bValueH is type + 0xff,0xff, + 0xff,0xff, + 0xd0,&usbGetStringDescriptor, +// get interface + USB_REQ_TYPE_INPUT | USB_REQ_TYPE_STANDARD | USB_REQ_TYPE_INTERFACE, + USB_REQ_GET_INTERFACE, + 0x00,0x00, + 0xff,0xff, + 0x01,0x00, + 0xf3,&usbGetInterface, + // get device status + USB_REQ_TYPE_INPUT | USB_REQ_TYPE_STANDARD | USB_REQ_TYPE_DEVICE, + USB_REQ_GET_STATUS, + 0x00,0x00, + 0x00,0x00, + 0x02,0x00, + 0xff,&usbGetDeviceStatus, // get interface status + USB_REQ_TYPE_INPUT | USB_REQ_TYPE_STANDARD | USB_REQ_TYPE_INTERFACE, + USB_REQ_GET_STATUS, + 0x00,0x00, + 0xff,0x00, + 0x02,0x00, + 0xf7,&usbGetInterfaceStatus, + // get endpoint status + USB_REQ_TYPE_INPUT | USB_REQ_TYPE_STANDARD | USB_REQ_TYPE_ENDPOINT, + USB_REQ_GET_STATUS, + 0x00,0x00, + 0xff,0x00, + 0x02,0x00, + 0xf7,&usbGetEndpointStatus, + // set address + USB_REQ_TYPE_OUTPUT | USB_REQ_TYPE_STANDARD | USB_REQ_TYPE_DEVICE, + USB_REQ_SET_ADDRESS, + 0xff,0x00, + 0x00,0x00, + 0x00,0x00, + 0xdf,&usbSetAddress, + // set configuration + USB_REQ_TYPE_OUTPUT | USB_REQ_TYPE_STANDARD | USB_REQ_TYPE_DEVICE, + USB_REQ_SET_CONFIGURATION, + 0xff,0x00, + 0x00,0x00, + 0x00,0x00, + 0xdf,&usbSetConfiguration, + // set device feature + USB_REQ_TYPE_OUTPUT | USB_REQ_TYPE_STANDARD | USB_REQ_TYPE_DEVICE, + USB_REQ_SET_FEATURE, + 0xff,0x00, // feature selector + 0x00,0x00, + 0x00,0x00, + 0xdf,&usbSetDeviceFeature, + // set endpoint feature + USB_REQ_TYPE_OUTPUT | USB_REQ_TYPE_STANDARD | USB_REQ_TYPE_ENDPOINT, + USB_REQ_SET_FEATURE, + 0xff,0x00, // feature selector + 0xff,0x00, // endpoint number <= 127 + 0x00,0x00, + 0xd7,&usbSetEndpointFeature, + // set interface + USB_REQ_TYPE_OUTPUT | USB_REQ_TYPE_STANDARD | USB_REQ_TYPE_INTERFACE, + USB_REQ_SET_INTERFACE, + 0xff,0x00, // feature selector + 0xff,0x00, // interface number + 0x00,0x00, + 0xd7,&usbSetInterface, + + // end of usb descriptor -- this one will be matched to any USB request + // since bCompareMask is 0x00. + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0x00,&usbInvalidRequest // end of list +}; + +/*-----------------------------------------------------------------------------+ +| END OF Descriptor.c FILE | +|-----------------------------------------------------------------------------*/ diff --git a/source/USB_config/descriptors.dat b/source/USB_config/descriptors.dat new file mode 100644 index 0000000..9ab6ebe Binary files /dev/null and b/source/USB_config/descriptors.dat differ diff --git a/source/USB_config/descriptors.h b/source/USB_config/descriptors.h new file mode 100644 index 0000000..cb3952c --- /dev/null +++ b/source/USB_config/descriptors.h @@ -0,0 +1,377 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2013, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 'AS IS' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ + +#include +#include "USB_API/USB_Common/usb.h" + +#ifndef _DESCRIPTORS_H_ +#define _DESCRIPTORS_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/*-----------------------------------------------------------------------------+ +| Include files | +|-----------------------------------------------------------------------------*/ + +//*********************************************************************************************** +// CDC or HID - Define both for composite support +//*********************************************************************************************** +#define _CDC_ // Needed for CDC inteface +//*********************************************************************************************** +// CONFIGURATION CONSTANTS +//*********************************************************************************************** +// These constants configure the API stack and help define the USB descriptors. +// Refer to Sec. 6 of the MSP430 USB CDC API Programmer's Guide for descriptions of these constants. + +// Configuration Constants that can change +// #define that relates to Device Descriptor +#define USB_VID 0x2047 // Vendor ID (VID) +#define USB_PID 0x030b // Product ID (PID) +/*----------------------------------------------------------------------------+ +| Firmware Version | +| How to detect version number of the FW running on MSP430? | +| on Windows Open ControlPanel->Systems->Hardware->DeviceManager->Ports-> | +| Msp430->ApplicationUART->Details | ++----------------------------------------------------------------------------*/ +#define VER_FW_H 0x02 // Device release number, in binary-coded decimal +#define VER_FW_L 0x00 // Device release number, in binary-coded decimal +// If a serial number is to be reported, set this to the index within the string descriptor +//of the dummy serial number string. It will then be automatically handled by the API. +// If no serial number is to be reported, set this to 0. +#define USB_STR_INDEX_SERNUM 3 + #define PHDC_ENDPOINTS_NUMBER 2 // bulk in, bulk out + + +#define DESCRIPTOR_TOTAL_LENGTH 67 // wTotalLength, This is the sum of configuration descriptor length + CDC descriptor length + HID descriptor length +#define USB_NUM_INTERFACES 2 // Number of implemented interfaces. + +#define CDC0_COMM_INTERFACE 0 // Comm interface number of CDC0 +#define CDC0_DATA_INTERFACE 1 // Data interface number of CDC0 +#define CDC0_INTEP_ADDR 0x81 // Interrupt Endpoint Address of CDC0 +#define CDC0_OUTEP_ADDR 0x02 // Output Endpoint Address of CDC0 +#define CDC0_INEP_ADDR 0x82 // Input Endpoint Address of CDC0 + +#define CDC_NUM_INTERFACES 1 // Total Number of CDCs implemented. should set to 0 if there are no CDCs implemented. +#define HID_NUM_INTERFACES 0 // Total Number of HIDs implemented. should set to 0 if there are no HIDs implemented. +#define MSC_NUM_INTERFACES 0 // Total Number of MSCs implemented. should set to 0 if there are no MSCs implemented. +#define PHDC_NUM_INTERFACES 0 // Total Number of PHDCs implemented. should set to 0 if there are no PHDCs implemented. +// Interface numbers for the implemented CDSs and HIDs, This is to use in the Application(main.c) and in the interupt file(UsbIsr.c). +#define CDC0_INTFNUM 0 +#define MSC_MAX_LUN_NUMBER 1 // Maximum number of LUNs supported + +#define PUTWORD(x) ((x)&0xFF),((x)>>8) + +#define USB_OUTEP_INT_EN BIT0 | BIT2 +#define USB_INEP_INT_EN BIT0 | BIT1 | BIT2 + +#define USB_USE_INTERNAL_3V3LDO TRUE +// MCLK frequency of MCU, in Hz +// For running higher frequencies the Vcore voltage adjustment may required. +// Please refer to Data Sheet of the MSP430 device you use +#define USB_MCLK_FREQ 20000000 // MCLK frequency of MCU, in Hz +#define USB_PLL_XT 2 // Defines which XT is used by the PLL (1=XT1, 2=XT2) +#define USB_XT_FREQ_VALUE 4.0 // Indicates the freq of the crystal on the oscillator indicated by USB_PLL_XT +#define USB_XT_FREQ USBPLL_SETCLK_4_0 // Indicates the freq of the crystal on the oscillator indicated by USB_PLL_XT +#define USB_DISABLE_XT_SUSPEND 1 // If non-zero, then USB_suspend() will disable the oscillator + // that is designated by USB_PLL_XT; if zero, USB_suspend won't + // affect the oscillator +#define USB_DMA_CHAN 0x00 // Set to 0xFF if no DMA channel will be used 0..7 for selected DMA channel + + + +// Controls whether the remote wakeup feature is supported by this device. +// A value of 0x20 indicates that is it supported (this value is the mask for +// the bmAttributes field in the configuration descriptor). +// A value of zero indicates remote wakeup is not supported. +// Other values are undefined, as they will interfere with bmAttributes. +#define USB_SUPPORT_REM_WAKE 0x00 + +// Controls whether the application is self-powered to any degree. Should be +// set to 0x40, unless the USB device is fully supplied by the bus. +#define USB_SUPPORT_SELF_POWERED 0x80 + +// Controls what the device reports to the host regarding how much power it will +// consume from VBUS. Expressed in 2mA units; that is, the number of mA +// communicated is twice the value of this field. +#define USB_MAX_POWER 0x32 +//Configuration constants that can not change ( Fixed Values) +#define CDC_CLASS 2 +#define HID_CLASS 3 +#define MSC_CLASS 4 +#define PHDC_CLASS 5 + + #define MAX_PACKET_SIZE 0x40 // Max size of the USB packets. + +//*********************************************************************************************** +// DESCRIPTOR CONSTANTS +//*********************************************************************************************** +#define SIZEOF_DEVICE_DESCRIPTOR 0x12 +#define MAX_STRING_DESCRIPTOR_INDEX 5 +//#define SIZEOF_REPORT_DESCRIPTOR 36 +//#define USBHID_REPORT_LENGTH 64 // length of whole HID report (including Report ID) +#define CONFIG_STRING_INDEX 4 +#define INTF_STRING_INDEX 5 +#define USB_CONFIG_VALUE 0x01 +//*********************************************************************************************** +// OUTWARD DECLARATIONS +//*********************************************************************************************** + +//Calculates the endpoint descriptor block number from given address +#define EDB(addr) ((addr&0x07)-1) + +/* Structure for generic part of configuration descriptor */ +struct abromConfigurationDescriptorGenric +{ + uint8_t sizeof_config_descriptor; // bLength + uint8_t desc_type_config; // bDescriptorType: 2 + uint8_t sizeof_configuration_descriptor1; // wTotalLength + uint8_t sizeof_configuration_descriptor2; + uint8_t usb_num_configurations; // bNumInterfaces + uint8_t bconfigurationvalue; // bConfigurationValue + uint8_t config_string_index; // iConfiguration Description offset + uint8_t mattributes; // bmAttributes, bus power, remote wakeup + uint8_t usb_max_power; // Max. Power Consumption at 2mA unit +}; + +/************************************************CDC Descriptor**************************/ +struct abromConfigurationDescriptorCdc +{ +// interface descriptor (9 bytes) + uint8_t blength_intf; // blength: interface descriptor size + uint8_t desc_type_interface; // bdescriptortype: interface + uint8_t interface_number_cdc; // binterfacenumber + uint8_t balternatesetting; // balternatesetting: alternate setting + uint8_t bnumendpoints; // bnumendpoints: three endpoints used + uint8_t binterfaceclass; // binterfaceclass: communication interface class + uint8_t binterfacesubclass; // binterfacesubclass: abstract control model + uint8_t binterfaceprotocol; // binterfaceprotocol: common at commands + uint8_t intf_string_index; // interface: +//header functional descriptor + uint8_t blength_header; // blength: endpoint descriptor size + uint8_t bdescriptortype_header; // bdescriptortype: cs_interface + uint8_t bdescriptorsubtype_header; // bdescriptorsubtype: header func desc + uint8_t bcdcdc1; + uint8_t bcdcdc2; // bcdcdc: spec release number + +//call managment functional descriptor + uint8_t bfunctionlength; // bfunctionlength + uint8_t bdescriptortype_c; // bdescriptortype: cs_interface + uint8_t bdescriptorsubtype_c; // bdescriptorsubtype: call management func desc + uint8_t bmcapabilities; // bmcapabilities: d0+d1 + uint8_t intf_number_cdc; // bdatainterface: 0 + +//acm functional descriptor + uint8_t bfunctionlength_acm; // bfunctionlength + uint8_t bdescriptortype_acm; // bdescriptortype: cs_interface + uint8_t bdescriptorsubtype_acm; // bdescriptorsubtype: abstract control management desc + uint8_t bmcapabilities_acm; // bmcapabilities + +// Union Functional Descriptor + uint8_t bLength_ufd; // Size, in bytes + uint8_t bdescriptortype_ufd; // bDescriptorType: CS_INTERFACE + uint8_t bdescriptorsubtype_ufd; // bDescriptorSubtype: Union Functional Desc + uint8_t bmasterinterface_ufd; // bMasterInterface -- the controlling intf for the union + uint8_t bslaveinterface_ufd; // bSlaveInterface -- the controlled intf for the union + +//Interrupt end point related fields + uint8_t sizeof_epintep_descriptor; // blength: endpoint descriptor size + uint8_t desc_type_epintep; // bdescriptortype: endpoint + uint8_t cdc_intep_addr; // bendpointaddress: (in2) + uint8_t epintep_desc_attr_type_int; // bmattributes: interrupt + uint8_t epintep_wmaxpacketsize1; + uint8_t epintep_wmaxpacketsize; // wmaxpacketsize, 64 bytes + uint8_t epintep_binterval; // binterval + +// Data interface descriptor (9 bytes) + uint8_t blength_slaveintf; // blength: interface descriptor size + uint8_t desc_type_slaveinterface; // bdescriptortype: interface + uint8_t interface_number_slavecdc; // binterfacenumber + uint8_t balternatesetting_slave; // balternatesetting: alternate setting + uint8_t bnumendpoints_slave; // bnumendpoints: three endpoints used + uint8_t binterfaceclass_slave; // binterfaceclass: data interface class + uint8_t binterfacesubclass_slave; // binterfacesubclass: abstract control model + uint8_t binterfaceprotocol_slave; // binterfaceprotocol: common at commands + uint8_t intf_string_index_slave; // interface: + +// Bulk out end point related fields + uint8_t sizeof_outep_descriptor; // blength: endpoint descriptor size + uint8_t desc_type_outep; // bdescriptortype: endpoint + uint8_t cdc_outep_addr; // bendpointaddress: (out3) + uint8_t outep_desc_attr_type_bulk; // bmattributes: bulk + uint8_t outep_wmaxpacketsize1; + uint8_t outep_wmaxpacketsize2; // wmaxpacketsize, 64 bytes + uint8_t outep_binterval; // binterval: ignored for bulk transfer + +// Bulk in related fields + uint8_t sizeof_inep_descriptor; // blength: endpoint descriptor size + uint8_t desc_type_inep; // bdescriptortype: endpoint + uint8_t cdc_inep_addr; // bendpointaddress: (in3) + uint8_t inep_desc_attr_type_bulk; // bmattributes: bulk + uint8_t inep_wmaxpacketsize1; + uint8_t inep_wmaxpacketsize2; // wmaxpacketsize, 64 bytes + uint8_t inep_binterval; // binterval: ignored for bulk transfer +} ; + +/**************************************HID descriptor structure *************************/ +struct abromConfigurationDescriptorHid +{ +//INTERFACE DESCRIPTOR (9 bytes) + uint8_t sizeof_interface_descriptor; // Desc Length + uint8_t desc_type_interface; // DescriptorType + uint8_t interface_number_hid; // Interface number + uint8_t balternatesetting; // Any alternate settings if supported + uint8_t bnumendpoints; // Number of end points required + uint8_t binterfaceclass; // Class ID + uint8_t binterfacesubclass; // Sub class ID + uint8_t binterfaceprotocol; // Protocol + uint8_t intf_string_index; // String Index + +//hid descriptor (9 bytes) + uint8_t blength_hid_descriptor; // HID Desc length + uint8_t hid_descriptor_type; // HID Desc Type + uint8_t hidrevno1; // Rev no + uint8_t hidrevno2; // Rev no - 2nd part + uint8_t tcountry; // Country code + uint8_t numhidclasses; // Number of HID classes to follow + uint8_t report_descriptor_type; // Report desc type + uint8_t tlength; // Total length of report descriptor + uint8_t size_rep_desc; + +//input end point descriptor (7 bytes) + uint8_t size_inp_endpoint_descriptor; // End point desc size + uint8_t desc_type_inp_endpoint; // Desc type + uint8_t hid_inep_addr; // Input end point address + uint8_t ep_desc_attr_type_inp_int; // Type of end point + uint8_t inp_wmaxpacketsize1; // Max packet size + uint8_t inp_wmaxpacketsize2; + uint8_t inp_binterval; // bInterval in ms + + // Output end point descriptor; (7 bytes) + uint8_t size_out_endpoint_descriptor; // Output endpoint desc size + uint8_t desc_type_out_endpoint; // Desc type + uint8_t hid_outep_addr; // Output end point address + uint8_t ep_desc_attr_type_out_int; // End point type + uint8_t out_wmaxpacketsize1; // Max packet size + uint8_t out_wmaxpacketsize2; + uint8_t out_binterval; // bInterval in ms +}; + +/**************************************MSC descriptor structure *************************/ +struct abromConfigurationDescriptorMsc +{ +// INTERFACE DESCRIPTOR (9 bytes) + uint8_t sizeof_interface_descriptor; // Desc Length + uint8_t desc_type_interface; // DescriptorType + uint8_t interface_number_hid; // Interface number + uint8_t balternatesetting; // Any alternate settings if supported + uint8_t bnumendpoints; // Number of end points required + uint8_t binterfaceclass; // Class ID + uint8_t binterfacesubclass; // Sub class ID + uint8_t binterfaceprotocol; // Protocol + uint8_t intf_string_index; // String Index + +// input end point descriptor (7 bytes) + uint8_t size_inp_endpoint_descriptor; // End point desc size + uint8_t desc_type_inp_endpoint; // Desc type + uint8_t hid_inep_addr; // Input end point address + uint8_t ep_desc_attr_type_inp_int; // Type of end point + uint8_t inp_wmaxpacketsize1; // Max packet size + uint8_t inp_wmaxpacketsize2; + uint8_t inp_binterval; // bInterval in ms + +// Output end point descriptor; (7 bytes) + uint8_t size_out_endpoint_descriptor; // Output endpoint desc size + uint8_t desc_type_out_endpoint; // Desc type + uint8_t hid_outep_addr; // Output end point address + uint8_t ep_desc_attr_type_out_int; // End point type + uint8_t out_wmaxpacketsize1; // Max packet size + uint8_t out_wmaxpacketsize2; + uint8_t out_binterval; // bInterval in ms +}; + +/* Global structure having Generic,CDC,HID, MSC structures */ +struct abromConfigurationDescriptorGroup +{ + /* Generic part of config descriptor */ + const struct abromConfigurationDescriptorGenric abromConfigurationDescriptorGenric; +#ifdef _MSC_ + /* MSC descriptor structure */ + const struct abromConfigurationDescriptorMsc stMsc[MSC_NUM_INTERFACES]; +#endif +#ifdef _CDC_ + /* CDC descriptor structure */ + const struct abromConfigurationDescriptorCdc stCdc[CDC_NUM_INTERFACES]; +#endif +#ifdef _HID_ + /* HID descriptor structure */ + const struct abromConfigurationDescriptorHid stHid[HID_NUM_INTERFACES]; +#endif +#ifdef _PHDC_ +/* PDC descriptor structure */ + const struct abromConfigurationDescriptorPhdc stPhdc[PHDC_NUM_INTERFACES]; +#endif +}; + +extern const struct abromConfigurationDescriptorGroup abromConfigurationDescriptorGroup; +extern uint8_t const abromDeviceDescriptor[SIZEOF_DEVICE_DESCRIPTOR]; +extern uint8_t const abromStringDescriptor[]; +//extern uint8_t const abromReportDescriptor[SIZEOF_REPORT_DESCRIPTOR]; + +/* Handle Structure - Will be populated in descriptors.c based on number of CDC,HID interfaces */ +struct tUsbHandle +{ + uint8_t ep_In_Addr; // Input EP Addr + uint8_t ep_Out_Addr; // Output EP Addr + uint8_t edb_Index; // The EDB index + uint8_t dev_Class; // Device Class- 2 for CDC, 3 for HID + uint16_t intepEP_X_Buffer; // Interupt X Buffer Addr + uint16_t intepEP_Y_Buffer; // Interupt Y Buffer Addr + uint16_t oep_X_Buffer; // Output X buffer Addr + uint16_t oep_Y_Buffer; // Output Y buffer Addr + uint16_t iep_X_Buffer; // Input X Buffer Addr + uint16_t iep_Y_Buffer; // Input Y Buffer Addr +}; + +extern const struct tUsbHandle stUsbHandle[CDC_NUM_INTERFACES + HID_NUM_INTERFACES + MSC_NUM_INTERFACES + PHDC_NUM_INTERFACES]; +extern const tDEVICE_REQUEST_COMPARE tUsbRequestList[]; + +#ifdef __cplusplus +} +#endif + +#endif + +/*------------------------ Nothing Below This Line --------------------------*/ + diff --git a/source/USB_config/readme.h b/source/USB_config/readme.h new file mode 100644 index 0000000..3c4425c --- /dev/null +++ b/source/USB_config/readme.h @@ -0,0 +1,34 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//This is just a crumb file to create the USB_config directory +//This directory needs to get populated by running the DescriptorTool +//Released_Version_4_10_02 diff --git a/source/driverlib/MSP430F5xx_6xx/adc10_a.c b/source/driverlib/MSP430F5xx_6xx/adc10_a.c new file mode 100644 index 0000000..fe705c3 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/adc10_a.c @@ -0,0 +1,827 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// adc10_a.c - Driver for the adc10_a Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup adc10_a_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_ADC10_A__ +#include "adc10_a.h" + +#include + +//***************************************************************************** +// +//! \brief Initializes the ADC10_A Module. +//! +//! This function initializes the ADC module to allow for analog-to-digital +//! conversions. Specifically this function sets up the sample-and-hold signal +//! and clock sources for the ADC core to use for conversions. Upon successful +//! completion of the initialization all of the ADC control registers will be +//! reset, excluding the memory controls and reference module bits, the given +//! parameters will be set, and the ADC core will be turned on (Note, that the +//! ADC core only draws power during conversions and remains off when not +//! converting).Note that sample/hold signal sources are device dependent. Note +//! that if re-initializing the ADC after starting a conversion with the +//! startConversion() function, the disableConversion() must be called BEFORE +//! this function can be called. +//! +//! \param baseAddress is the base address of the ADC10_A module. +//! \param sampleHoldSignalSourceSelect is the signal that will trigger a +//! sample-and-hold for an input signal to be converted. This parameter +//! is device specific and sources should be found in the device's +//! datasheet +//! Valid values are: +//! - \b ADC10_A_SAMPLEHOLDSOURCE_SC +//! - \b ADC10_A_SAMPLEHOLDSOURCE_1 +//! - \b ADC10_A_SAMPLEHOLDSOURCE_2 +//! - \b ADC10_A_SAMPLEHOLDSOURCE_3 +//! \n Modified bits are \b ADC10SHSx of \b ADC10CTL1 register. +//! \param clockSourceSelect selects the clock that will be used by the ADC10_A +//! core and the sampling timer if a sampling pulse mode is enabled. +//! Valid values are: +//! - \b ADC10_A_CLOCKSOURCE_ADC10OSC [Default] - MODOSC 5 MHz +//! oscillator from the UCS +//! - \b ADC10_A_CLOCKSOURCE_ACLK - The Auxiliary Clock +//! - \b ADC10_A_CLOCKSOURCE_MCLK - The Master Clock +//! - \b ADC10_A_CLOCKSOURCE_SMCLK - The Sub-Master Clock +//! \n Modified bits are \b ADC10SSELx of \b ADC10CTL1 register. +//! \param clockSourceDivider selects the amount that the clock will be +//! divided. +//! Valid values are: +//! - \b ADC10_A_CLOCKDIVIDER_1 [Default] +//! - \b ADC10_A_CLOCKDIVIDER_2 +//! - \b ADC10_A_CLOCKDIVIDER_3 +//! - \b ADC10_A_CLOCKDIVIDER_4 +//! - \b ADC10_A_CLOCKDIVIDER_5 +//! - \b ADC10_A_CLOCKDIVIDER_6 +//! - \b ADC10_A_CLOCKDIVIDER_7 +//! - \b ADC10_A_CLOCKDIVIDER_8 +//! - \b ADC10_A_CLOCKDIVIDER_12 +//! - \b ADC10_A_CLOCKDIVIDER_16 +//! - \b ADC10_A_CLOCKDIVIDER_20 +//! - \b ADC10_A_CLOCKDIVIDER_24 +//! - \b ADC10_A_CLOCKDIVIDER_28 +//! - \b ADC10_A_CLOCKDIVIDER_32 +//! - \b ADC10_A_CLOCKDIVIDER_64 +//! - \b ADC10_A_CLOCKDIVIDER_128 +//! - \b ADC10_A_CLOCKDIVIDER_192 +//! - \b ADC10_A_CLOCKDIVIDER_256 +//! - \b ADC10_A_CLOCKDIVIDER_320 +//! - \b ADC10_A_CLOCKDIVIDER_384 +//! - \b ADC10_A_CLOCKDIVIDER_448 +//! - \b ADC10_A_CLOCKDIVIDER_512 +//! \n Modified bits are \b ADC10DIVx of \b ADC10CTL1 register; bits \b +//! ADC10PDIVx of \b ADC10CTL2 register. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the initialization process. +// +//***************************************************************************** +bool ADC10_A_init(uint16_t baseAddress, + uint16_t sampleHoldSignalSourceSelect, + uint8_t clockSourceSelect, + uint16_t clockSourceDivider) +{ + //Make sure the ENC bit is cleared before initializing the ADC10_A + assert( !(HWREG16(baseAddress + OFS_ADC10CTL0) & ADC10ENC) ); + + assert(sampleHoldSignalSourceSelect <= ADC10_A_SAMPLEHOLDSOURCE_3); + assert(clockSourceSelect <= ADC10_A_CLOCKSOURCE_SMCLK); + assert(clockSourceDivider <= ADC10_A_CLOCKDIVIDER_512); + + bool retVal = STATUS_SUCCESS; + + //Turn OFF ADC10_A Module & Clear Interrupt Registers + HWREG16(baseAddress + OFS_ADC10CTL0) &= ~(ADC10ON + ADC10ENC + ADC10SC); + HWREG16(baseAddress + OFS_ADC10IE) &= 0x0000; //Reset ALL interrupt enables + HWREG16(baseAddress + OFS_ADC10IFG) &= 0x0000; //Reset ALL interrupt flags + + //Set ADC10_A Control 1 + HWREG16(baseAddress + OFS_ADC10CTL1) = + sampleHoldSignalSourceSelect //Setup the Sample-and-Hold Source + + (clockSourceDivider & ADC10DIV_7) //Set Clock Divider + + clockSourceSelect; //Setup Clock Source + + //Set ADC10_A Control 2 + HWREG16(baseAddress + OFS_ADC10CTL2) = + (clockSourceDivider & ADC10PDIV_3) //Set Clock Pre-Divider + + ADC10RES; //Default resolution to 10-bits + + return retVal; +} + +//***************************************************************************** +// +//! \brief Enables the ADC10_A block. +//! +//! This will enable operation of the ADC10_A block. +//! +//! \param baseAddress is the base address of the ADC10_A module. +//! +//! Modified bits are \b ADC10ON of \b ADC10CTL0 register. +//! +//! \return None +// +//***************************************************************************** +void ADC10_A_enable(uint16_t baseAddress) +{ + //Reset the ADC10ON bit to enable the ADC10_A Module + HWREG16(baseAddress + OFS_ADC10CTL0) |= ADC10ON; +} + +//***************************************************************************** +// +//! \brief Disables the ADC10_A block. +//! +//! This will disable operation of the ADC10_A block. +//! +//! \param baseAddress is the base address of the ADC10_A module. +//! +//! Modified bits are \b ADC10ON of \b ADC10CTL0 register. +//! +//! \return None +// +//***************************************************************************** +void ADC10_A_disable(uint16_t baseAddress) +{ + //Set the ADC10ON bit to disable the ADC10_A Module + HWREG16(baseAddress + OFS_ADC10CTL0) &= ~ADC10ON; +} + +//***************************************************************************** +// +//! \brief Sets up and enables the Sampling Timer Pulse Mode. +//! +//! This function sets up the sampling timer pulse mode which allows the +//! sample/hold signal to trigger a sampling timer to sample-and-hold an input +//! signal for a specified number of clock cycles without having to hold the +//! sample/hold signal for the entire period of sampling. Note that if a +//! conversion has been started with the startConversion() function, then a +//! call to disableConversions() is required before this function may be +//! called. +//! +//! \param baseAddress is the base address of the ADC10_A module. +//! \param clockCycleHoldCount sets the amount of clock cycles to sample-and- +//! hold for the memory buffer. +//! Valid values are: +//! - \b ADC10_A_CYCLEHOLD_4_CYCLES [Default] +//! - \b ADC10_A_CYCLEHOLD_8_CYCLES +//! - \b ADC10_A_CYCLEHOLD_16_CYCLES +//! - \b ADC10_A_CYCLEHOLD_32_CYCLES +//! - \b ADC10_A_CYCLEHOLD_64_CYCLES +//! - \b ADC10_A_CYCLEHOLD_96_CYCLES +//! - \b ADC10_A_CYCLEHOLD_128_CYCLES +//! - \b ADC10_A_CYCLEHOLD_192_CYCLES +//! - \b ADC10_A_CYCLEHOLD_256_CYCLES +//! - \b ADC10_A_CYCLEHOLD_384_CYCLES +//! - \b ADC10_A_CYCLEHOLD_512_CYCLES +//! - \b ADC10_A_CYCLEHOLD_768_CYCLES +//! - \b ADC10_A_CYCLEHOLD_1024_CYCLES +//! \n Modified bits are \b ADC10SHTx of \b ADC10CTL0 register. +//! \param multipleSamplesEnabled allows multiple conversions to start without +//! a trigger signal from the sample/hold signal +//! Valid values are: +//! - \b ADC10_A_MULTIPLESAMPLESDISABLE - a timer trigger will be needed +//! to start every ADC conversion. +//! - \b ADC10_A_MULTIPLESAMPLESENABLE - during a sequenced and/or +//! repeated conversion mode, after the first conversion, no +//! sample/hold signal is necessary to start subsequent samples. +//! \n Modified bits are \b ADC10MSC of \b ADC10CTL0 register. +//! +//! \return None +// +//***************************************************************************** +void ADC10_A_setupSamplingTimer(uint16_t baseAddress, + uint16_t clockCycleHoldCount, + uint16_t multipleSamplesEnabled) +{ + //Make sure the ENC bit is cleared before setting up sampling pulse mode + assert( !(HWREG16(baseAddress + OFS_ADC10CTL0) & ADC10ENC) ); + + assert(clockCycleHoldCount <= ADC10_A_CYCLEHOLD_1024_CYCLES); + + HWREG16(baseAddress + OFS_ADC10CTL1) |= ADC10SHP; + + //Reset and Set CB Control 0 Bits + HWREG16(baseAddress + OFS_ADC10CTL0) &= ~(ADC10SHT_15 + ADC10MSC); + HWREG16(baseAddress + OFS_ADC10CTL0) |= clockCycleHoldCount + + multipleSamplesEnabled; +} + +//***************************************************************************** +// +//! \brief Disables Sampling Timer Pulse Mode. +//! +//! Disables the Sampling Timer Pulse Mode. Note that if a conversion has been +//! started with the startConversion() function, then a call to +//! disableConversions() is required before this function may be called. +//! +//! \param baseAddress is the base address of the ADC10_A module. +//! +//! \return None +// +//***************************************************************************** +void ADC10_A_disableSamplingTimer(uint16_t baseAddress) +{ + //Make sure the ENC bit is cleared before disabling sampling pulse mode + assert( ~(HWREG16(baseAddress + OFS_ADC10CTL0) & ADC10ENC) ); + + HWREG16(baseAddress + OFS_ADC10CTL1) &= ~(ADC10SHP); +} + +//***************************************************************************** +// +//! \brief Configures the controls of the selected memory buffer. +//! +//! Maps an input signal conversion into the memory buffer, as well as the +//! positive and negative reference voltages for each conversion being stored +//! into the memory buffer. If the internal reference is used for the positive +//! reference voltage, the internal REF module has to control the voltage +//! level. Note that if a conversion has been started with the +//! startConversion() function, then a call to disableConversions() is required +//! before this function may be called. +//! +//! \param baseAddress is the base address of the ADC10_A module. +//! \param inputSourceSelect is the input that will store the converted data +//! into the specified memory buffer. +//! Valid values are: +//! - \b ADC10_A_INPUT_A0 [Default] +//! - \b ADC10_A_INPUT_A1 +//! - \b ADC10_A_INPUT_A2 +//! - \b ADC10_A_INPUT_A3 +//! - \b ADC10_A_INPUT_A4 +//! - \b ADC10_A_INPUT_A5 +//! - \b ADC10_A_INPUT_A6 +//! - \b ADC10_A_INPUT_A7 +//! - \b ADC10_A_INPUT_A8 +//! - \b ADC10_A_INPUT_A9 +//! - \b ADC10_A_INPUT_TEMPSENSOR +//! - \b ADC10_A_INPUT_BATTERYMONITOR +//! - \b ADC10_A_INPUT_A12 +//! - \b ADC10_A_INPUT_A13 +//! - \b ADC10_A_INPUT_A14 +//! - \b ADC10_A_INPUT_A15 +//! \n Modified bits are \b ADC10INCHx of \b ADC10MCTL0 register. +//! \param positiveRefVoltageSourceSelect is the reference voltage source to +//! set as the upper limit for the conversion that is to be stored in +//! the specified memory buffer. +//! Valid values are: +//! - \b ADC10_A_VREFPOS_AVCC [Default] +//! - \b ADC10_A_VREFPOS_EXT +//! - \b ADC10_A_VREFPOS_INT +//! \n Modified bits are \b ADC10SREF of \b ADC10MCTL0 register. +//! \param negativeRefVoltageSourceSelect is the reference voltage source to +//! set as the lower limit for the conversion that is to be stored in +//! the specified memory buffer. +//! Valid values are: +//! - \b ADC10_A_VREFNEG_AVSS +//! - \b ADC10_A_VREFNEG_EXT +//! \n Modified bits are \b ADC10SREF of \b ADC10CTL0 register. +//! +//! \return None +// +//***************************************************************************** +void ADC10_A_memoryConfigure(uint16_t baseAddress, + uint8_t inputSourceSelect, + uint8_t positiveRefVoltageSourceSelect, + uint8_t negativeRefVoltageSourceSelect) +{ + //Make sure the ENC bit is cleared before configuring a Memory Buffer Control + assert( !(HWREG16(baseAddress + OFS_ADC10CTL0) & ADC10ENC) ); + + assert(inputSourceSelect <= ADC10_A_INPUT_A15); + assert(positiveRefVoltageSourceSelect <= ADC10_A_VREFPOS_INT); + assert(negativeRefVoltageSourceSelect <= ADC10_A_VREFNEG_EXT); + + //Reset and Set the Memory Buffer Control Bits + HWREG8(baseAddress + OFS_ADC10MCTL0) = inputSourceSelect + + positiveRefVoltageSourceSelect + + negativeRefVoltageSourceSelect; +} + +//***************************************************************************** +// +//! \brief Enables selected ADC10_A interrupt sources. +//! +//! Enables the indicated ADC10_A interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. Does not clear interrupt flags. +//! +//! \param baseAddress is the base address of the ADC10_A module. +//! \param interruptMask is the bit mask of the memory buffer interrupt sources +//! to be enabled. +//! Mask value is the logical OR of any of the following: +//! - \b ADC10_A_TIMEOVERFLOW_INT - Interrupts when a new conversion is +//! starting before the previous one has finished +//! - \b ADC10_A_OVERFLOW_INT - Interrupts when a new conversion is +//! about to overwrite the previous one +//! - \b ADC10_A_ABOVETHRESHOLD_INT - Interrupts when the input signal +//! has gone above the high threshold of the window comparator +//! - \b ADC10_A_BELOWTHRESHOLD_INT - Interrupts when the input signal +//! has gone below the low threshold of the low window comparator +//! - \b ADC10_A_INSIDEWINDOW_INT - Interrupts when the input signal is +//! in between the high and low thresholds of the window comparator +//! - \b ADC10_A_COMPLETED_INT - Interrupt for new conversion data in +//! the memory buffer +//! +//! Modified bits of \b ADC10IE register. +//! +//! \return None +// +//***************************************************************************** +void ADC10_A_enableInterrupt(uint16_t baseAddress, + uint8_t interruptMask) +{ + HWREG16(baseAddress + OFS_ADC10IE) |= interruptMask; +} + +//***************************************************************************** +// +//! \brief Disables selected ADC10_A interrupt sources. +//! +//! Disables the indicated ADC10_A interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! \param baseAddress is the base address of the ADC10_A module. +//! \param interruptMask is the bit mask of the memory buffer interrupt sources +//! to be disabled. +//! Mask value is the logical OR of any of the following: +//! - \b ADC10_A_TIMEOVERFLOW_INT - Interrupts when a new conversion is +//! starting before the previous one has finished +//! - \b ADC10_A_OVERFLOW_INT - Interrupts when a new conversion is +//! about to overwrite the previous one +//! - \b ADC10_A_ABOVETHRESHOLD_INT - Interrupts when the input signal +//! has gone above the high threshold of the window comparator +//! - \b ADC10_A_BELOWTHRESHOLD_INT - Interrupts when the input signal +//! has gone below the low threshold of the low window comparator +//! - \b ADC10_A_INSIDEWINDOW_INT - Interrupts when the input signal is +//! in between the high and low thresholds of the window comparator +//! - \b ADC10_A_COMPLETED_INT - Interrupt for new conversion data in +//! the memory buffer +//! +//! Modified bits of \b ADC10IE register. +//! +//! \return None +// +//***************************************************************************** +void ADC10_A_disableInterrupt(uint16_t baseAddress, + uint8_t interruptMask) +{ + HWREG16(baseAddress + OFS_ADC10IE) &= ~(interruptMask); +} + +//***************************************************************************** +// +//! \brief Clears ADC10_A selected interrupt flags. +//! +//! The selected ADC10_A interrupt flags are cleared, so that it no longer +//! asserts. The memory buffer interrupt flags are only cleared when the memory +//! buffer is accessed. +//! +//! \param baseAddress is the base address of the ADC10_A module. +//! \param interruptFlagMask is a bit mask of the interrupt flags to be +//! cleared. +//! Mask value is the logical OR of any of the following: +//! - \b ADC10_A_TIMEOVERFLOW_INTFLAG - Interrupts flag when a new +//! conversion is starting before the previous one has finished +//! - \b ADC10_A_OVERFLOW_INTFLAG - Interrupts flag when a new +//! conversion is about to overwrite the previous one +//! - \b ADC10_A_ABOVETHRESHOLD_INTFLAG - Interrupts flag when the input +//! signal has gone above the high threshold of the window comparator +//! - \b ADC10_A_BELOWTHRESHOLD_INTFLAG - Interrupts flag when the input +//! signal has gone below the low threshold of the low window +//! comparator +//! - \b ADC10_A_INSIDEWINDOW_INTFLAG - Interrupts flag when the input +//! signal is in between the high and low thresholds of the window +//! comparator +//! - \b ADC10_A_COMPLETED_INTFLAG - Interrupt flag for new conversion +//! data in the memory buffer +//! +//! Modified bits of \b ADC10IFG register. +//! +//! \return None +// +//***************************************************************************** +void ADC10_A_clearInterrupt(uint16_t baseAddress, + uint8_t interruptFlagMask) +{ + HWREG16(baseAddress + OFS_ADC10IFG) &= ~(interruptFlagMask); +} + +//***************************************************************************** +// +//! \brief Returns the status of the selected memory interrupt flags. +//! +//! Returns the status of the selected interrupt flags. +//! +//! \param baseAddress is the base address of the ADC10_A module. +//! \param interruptFlagMask is a bit mask of the interrupt flags status to be +//! returned. +//! Mask value is the logical OR of any of the following: +//! - \b ADC10_A_TIMEOVERFLOW_INTFLAG - Interrupts flag when a new +//! conversion is starting before the previous one has finished +//! - \b ADC10_A_OVERFLOW_INTFLAG - Interrupts flag when a new +//! conversion is about to overwrite the previous one +//! - \b ADC10_A_ABOVETHRESHOLD_INTFLAG - Interrupts flag when the input +//! signal has gone above the high threshold of the window comparator +//! - \b ADC10_A_BELOWTHRESHOLD_INTFLAG - Interrupts flag when the input +//! signal has gone below the low threshold of the low window +//! comparator +//! - \b ADC10_A_INSIDEWINDOW_INTFLAG - Interrupts flag when the input +//! signal is in between the high and low thresholds of the window +//! comparator +//! - \b ADC10_A_COMPLETED_INTFLAG - Interrupt flag for new conversion +//! data in the memory buffer +//! +//! \return The current interrupt flag status for the corresponding mask. +// +//***************************************************************************** +uint8_t ADC10_A_getInterruptStatus(uint16_t baseAddress, + uint8_t interruptFlagMask) +{ + return HWREG16(baseAddress + OFS_ADC10IFG) & interruptFlagMask; +} + +//***************************************************************************** +// +//! \brief Enables/Starts an Analog-to-Digital Conversion. +//! +//! This function enables/starts the conversion process of the ADC. If the +//! sample/hold signal source chosen during initialization was ADC10OSC, then +//! the conversion is started immediately, otherwise the chosen sample/hold +//! signal source starts the conversion by a rising edge of the signal. Keep in +//! mind when selecting conversion modes, that for sequenced and/or repeated +//! modes, to keep the sample/hold-and-convert process continuing without a +//! trigger from the sample/hold signal source, the multiple samples must be +//! enabled using the ADC10_A_setupSamplingTimer() function. Also note that +//! when a sequence conversion mode is selected, the first input channel is the +//! one mapped to the memory buffer, the next input channel selected for +//! conversion is one less than the input channel just converted (i.e. A1 comes +//! after A2), until A0 is reached, and if in repeating mode, then the next +//! input channel will again be the one mapped to the memory buffer. Note that +//! after this function is called, the ADC10_A_stopConversions() has to be +//! called to re-initialize the ADC, reconfigure a memory buffer control, +//! enable/disable the sampling timer, or to change the internal reference +//! voltage. +//! +//! \param baseAddress is the base address of the ADC10_A module. +//! \param conversionSequenceModeSelect determines the ADC operating mode. +//! Valid values are: +//! - \b ADC10_A_SINGLECHANNEL [Default] - one-time conversion of a +//! single channel into a single memory buffer +//! - \b ADC10_A_SEQOFCHANNELS - one time conversion of multiple +//! channels into the specified starting memory buffer and each +//! subsequent memory buffer up until the conversion is stored in a +//! memory buffer dedicated as the end-of-sequence by the memory's +//! control register +//! - \b ADC10_A_REPEATED_SINGLECHANNEL - repeated conversions of one +//! channel into a single memory buffer +//! - \b ADC10_A_REPEATED_SEQOFCHANNELS - repeated conversions of +//! multiple channels into the specified starting memory buffer and +//! each subsequent memory buffer up until the conversion is stored +//! in a memory buffer dedicated as the end-of-sequence by the +//! memory's control register +//! \n Modified bits are \b ADC10CONSEQx of \b ADC10CTL1 register. +//! +//! \return None +// +//***************************************************************************** +void ADC10_A_startConversion(uint16_t baseAddress, + uint8_t conversionSequenceModeSelect) +{ + assert(conversionSequenceModeSelect <= ADC10_A_REPEATED_SEQOFCHANNELS); + + //Reset the ENC bit to set the conversion mode sequence + HWREG16(baseAddress + OFS_ADC10CTL0) &= ~(ADC10ENC); + + HWREG16(baseAddress + OFS_ADC10CTL1) |= conversionSequenceModeSelect; + HWREG16(baseAddress + OFS_ADC10CTL0) |= ADC10ENC + ADC10SC; +} + +//***************************************************************************** +// +//! \brief Disables the ADC from converting any more signals. +//! +//! Disables the ADC from converting any more signals. If there is a conversion +//! in progress, this function can stop it immediately if the preempt parameter +//! is set as ADC10_A_PREEMPTCONVERSION, by changing the conversion mode to +//! single-channel, single-conversion and disabling conversions. If the +//! conversion mode is set as single-channel, single-conversion and this +//! function is called without preemption, then the ADC core conversion status +//! is polled until the conversion is complete before disabling conversions to +//! prevent unpredictable data. If the ADC10_A_startConversion() has been +//! called, then this function has to be called to re-initialize the ADC, +//! reconfigure a memory buffer control, enable/disable the sampling pulse +//! mode, or change the internal reference voltage. +//! +//! \param baseAddress is the base address of the ADC10_A module. +//! \param preempt specifies if the current conversion should be pre-empted +//! before the end of the conversion +//! Valid values are: +//! - \b ADC10_A_COMPLETECONVERSION - Allows the ADC10_A to end the +//! current conversion before disabling conversions. +//! - \b ADC10_A_PREEMPTCONVERSION - Stops the ADC10_A immediately, with +//! unpredictable results of the current conversion. Cannot be used +//! with repeated conversion. +//! +//! Modified bits of \b ADC10CTL1 register and bits of \b ADC10CTL0 register. +//! +//! \return None +// +//***************************************************************************** +void ADC10_A_disableConversions(uint16_t baseAddress, bool preempt) +{ + if (ADC10_A_PREEMPTCONVERSION == preempt) + HWREG16(baseAddress + OFS_ADC10CTL1) &= ~(ADC10CONSEQ_3); + //Reset conversion sequence mode to single-channel, single-conversion + else if ( ~(HWREG16(baseAddress + OFS_ADC10CTL1) & ADC10CONSEQ_3) ) { + //To prevent preemoption of a single-channel, single-conversion we must + //wait for the ADC core to finish the conversion. + while (HWREG16(baseAddress + OFS_ADC10CTL1) & ADC10BUSY) ; + } + + HWREG16(baseAddress + OFS_ADC10CTL0) &= ~(ADC10ENC); +} + +//***************************************************************************** +// +//! \brief Returns the raw contents of the specified memory buffer. +//! +//! Returns the raw contents of the specified memory buffer. The format of the +//! content depends on the read-back format of the data: if the data is in +//! signed 2's complement format then the contents in the memory buffer will be +//! left-justified with the least-significant bits as 0's, whereas if the data +//! is in unsigned format then the contents in the memory buffer will be right- +//! justified with the most-significant bits as 0's. +//! +//! \param baseAddress is the base address of the ADC10_A module. +//! +//! \return A Signed Integer of the contents of the specified memory buffer. +// +//***************************************************************************** +int16_t ADC10_A_getResults(uint16_t baseAddress) +{ + return HWREG16(baseAddress + OFS_ADC10MEM0); +} + +//***************************************************************************** +// +//! \brief Use to change the resolution of the converted data. +//! +//! This function can be used to change the resolution of the converted data +//! from the default of 12-bits. +//! +//! \param baseAddress is the base address of the ADC10_A module. +//! \param resolutionSelect determines the resolution of the converted data. +//! Valid values are: +//! - \b ADC10_A_RESOLUTION_8BIT +//! - \b ADC10_A_RESOLUTION_10BIT [Default] +//! \n Modified bits are \b ADC10RES of \b ADC10CTL2 register. +//! +//! \return None +// +//***************************************************************************** +void ADC10_A_setResolution(uint16_t baseAddress, + uint8_t resolutionSelect) +{ + assert(resolutionSelect <= ADC10_A_RESOLUTION_10BIT); + + HWREG16(baseAddress + OFS_ADC10CTL2) &= ~(ADC10RES); + HWREG16(baseAddress + OFS_ADC10CTL2) |= resolutionSelect; +} + +//***************************************************************************** +// +//! \brief Use to invert or un-invert the sample/hold signal +//! +//! This function can be used to invert or un-invert the sample/hold signal. +//! Note that if a conversion has been started with the startConversion() +//! function, then a call to disableConversions() is required before this +//! function may be called. +//! +//! \param baseAddress is the base address of the ADC10_A module. +//! \param invertedSignal set if the sample/hold signal should be inverted +//! Valid values are: +//! - \b ADC10_A_NONINVERTEDSIGNAL [Default] - a sample-and-hold of an +//! input signal for conversion will be started on a rising edge of +//! the sample/hold signal. +//! - \b ADC10_A_INVERTEDSIGNAL - a sample-and-hold of an input signal +//! for conversion will be started on a falling edge of the +//! sample/hold signal. +//! \n Modified bits are \b ADC10ISSH of \b ADC10CTL1 register. +//! +//! \return None +// +//***************************************************************************** +void ADC10_A_setSampleHoldSignalInversion(uint16_t baseAddress, + uint16_t invertedSignal) +{ + //Make sure the ENC bit is cleared before using this function + assert( !(HWREG16(baseAddress + OFS_ADC10CTL0) & ADC10ENC) ); + + HWREG16(baseAddress + OFS_ADC10CTL1) &= ~(ADC10ISSH); + HWREG16(baseAddress + OFS_ADC10CTL1) |= invertedSignal; +} + +//***************************************************************************** +// +//! \brief Use to set the read-back format of the converted data +//! +//! Sets the format of the converted data: how it will be stored into the +//! memory buffer, and how it should be read back. The format can be set as +//! right-justified (default), which indicates that the number will be +//! unsigned, or left-justified, which indicates that the number will be signed +//! in 2's complement format. This change affects all memory buffers for +//! subsequent conversions. +//! +//! \param baseAddress is the base address of the ADC10_A module. +//! \param readBackFormat is the specified format to store the conversions in +//! the memory buffer. +//! Valid values are: +//! - \b ADC10_A_UNSIGNED_BINARY [Default] +//! - \b ADC10_A_SIGNED_2SCOMPLEMENT +//! \n Modified bits are \b ADC10DF of \b ADC10CTL2 register. +//! +//! \return None +// +//***************************************************************************** +void ADC10_A_setDataReadBackFormat(uint16_t baseAddress, + uint16_t readBackFormat) +{ + assert(readBackFormat <= ADC10_A_SIGNED_2SCOMPLEMENT); + + HWREG16(baseAddress + OFS_ADC10CTL2) &= ~(ADC10DF); + HWREG16(baseAddress + OFS_ADC10CTL2) |= readBackFormat; +} + +//***************************************************************************** +// +//! \brief Enables the reference buffer's burst ability. +//! +//! Enables the reference buffer's burst ability, allowing the reference buffer +//! to turn off while the ADC is not converting, and automatically turning on +//! when the ADC needs the generated reference voltage for a conversion. +//! +//! \param baseAddress is the base address of the ADC10_A module. +//! +//! \return None +// +//***************************************************************************** +void ADC10_A_enableReferenceBurst(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_ADC10CTL2) |= ADC10REFBURST; +} + +//***************************************************************************** +// +//! \brief Disables the reference buffer's burst ability. +//! +//! Disables the reference buffer's burst ability, forcing the reference buffer +//! to remain on continuously. +//! +//! \param baseAddress is the base address of the ADC10_A module. +//! +//! \return None +// +//***************************************************************************** +void ADC10_A_disableReferenceBurst(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_ADC10CTL2) &= ~(ADC10REFBURST); +} + +//***************************************************************************** +// +//! \brief Use to set the reference buffer's sampling rate. +//! +//! Sets the reference buffer's sampling rate to the selected sampling rate. +//! The default sampling rate is maximum of 200-ksps, and can be reduced to a +//! maximum of 50-ksps to conserve power. +//! +//! \param baseAddress is the base address of the ADC10_A module. +//! \param samplingRateSelect is the specified maximum sampling rate. +//! Valid values are: +//! - \b ADC10_A_MAXSAMPLINGRATE_200KSPS [Default] +//! - \b ADC10_A_MAXSAMPLINGRATE_50KSPS +//! \n Modified bits are \b ADC10SR of \b ADC10CTL2 register. +//! +//! \return None +// +//***************************************************************************** +void ADC10_A_setReferenceBufferSamplingRate(uint16_t baseAddress, + uint16_t samplingRateSelect) +{ + assert(samplingRateSelect <= ADC10_A_MAXSAMPLINGRATE_50KSPS); + + HWREG16(baseAddress + OFS_ADC10CTL2) &= ~(ADC10SR); + HWREG16(baseAddress + OFS_ADC10CTL2) |= samplingRateSelect; +} + +//***************************************************************************** +// +//! \brief Sets the high and low threshold for the window comparator feature. +//! +//! Sets the high and low threshold for the window comparator feature. Use the +//! ADC10HIIE, ADC10INIE, ADC10LOIE interrupts to utilize this feature. +//! +//! \param baseAddress is the base address of the ADC10_A module. +//! \param highThreshold is the upper bound that could trip an interrupt for +//! the window comparator. +//! \param lowThreshold is the lower bound that could trip on interrupt for the +//! window comparator. +//! +//! \return None +// +//***************************************************************************** +void ADC10_A_setWindowComp(uint16_t baseAddress, + uint16_t highThreshold, + uint16_t lowThreshold) +{ + HWREG16(baseAddress + OFS_ADC10HI) = highThreshold; + HWREG16(baseAddress + OFS_ADC10LO) = lowThreshold; +} + +//***************************************************************************** +// +//! \brief Returns the address of the memory buffer for the DMA module. +//! +//! Returns the address of the memory buffer. This can be used in conjunction +//! with the DMA to store the converted data directly to memory. +//! +//! \param baseAddress is the base address of the ADC10_A module. +//! +//! \return The memory address of the memory buffer +// +//***************************************************************************** +uint32_t ADC10_A_getMemoryAddressForDMA(uint16_t baseAddress) +{ + return baseAddress + OFS_ADC10MEM0; +} + +//***************************************************************************** +// +//! \brief Returns the busy status of the ADC10_A core. +//! +//! Returns the status of the ADC core if there is a conversion currently +//! taking place. +//! +//! \param baseAddress is the base address of the ADC10_A module. +//! +//! \return One of the following: +//! - \b ADC10_A_BUSY +//! - \b ADC10_A_NOTBUSY +//! \n indicating if there is a conversion currently taking place +// +//***************************************************************************** +uint16_t ADC10_A_isBusy(uint16_t baseAddress) +{ + return HWREG16(baseAddress + OFS_ADC10CTL1) & ADC10BUSY; +} + +#endif +//***************************************************************************** +// +//! Close the doxygen group for adc10_a_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/adc10_a.h b/source/driverlib/MSP430F5xx_6xx/adc10_a.h new file mode 100644 index 0000000..d59a9b9 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/adc10_a.h @@ -0,0 +1,352 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// adc10_a.h - Driver for the ADC10_A Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_ADC10_A_H__ +#define __MSP430WARE_ADC10_A_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_ADC10_A__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the clockSourceSelect +// parameter for functions: ADC10_A_init(). +// +//***************************************************************************** +#define ADC10_A_CLOCKSOURCE_ADC10OSC (ADC10SSEL_0) +#define ADC10_A_CLOCKSOURCE_ACLK (ADC10SSEL_1) +#define ADC10_A_CLOCKSOURCE_MCLK (ADC10SSEL_2) +#define ADC10_A_CLOCKSOURCE_SMCLK (ADC10SSEL_3) + +//***************************************************************************** +// +// The following are values that can be passed to the clockSourceDivider +// parameter for functions: ADC10_A_init(). +// +//***************************************************************************** +#define ADC10_A_CLOCKDIVIDER_1 (ADC10DIV_0 + ADC10PDIV_0) +#define ADC10_A_CLOCKDIVIDER_2 (ADC10DIV_1 + ADC10PDIV_0) +#define ADC10_A_CLOCKDIVIDER_3 (ADC10DIV_2 + ADC10PDIV_0) +#define ADC10_A_CLOCKDIVIDER_4 (ADC10DIV_3 + ADC10PDIV_0) +#define ADC10_A_CLOCKDIVIDER_5 (ADC10DIV_4 + ADC10PDIV_0) +#define ADC10_A_CLOCKDIVIDER_6 (ADC10DIV_5 + ADC10PDIV_0) +#define ADC10_A_CLOCKDIVIDER_7 (ADC10DIV_6 + ADC10PDIV_0) +#define ADC10_A_CLOCKDIVIDER_8 (ADC10DIV_7 + ADC10PDIV_0) +#define ADC10_A_CLOCKDIVIDER_12 (ADC10DIV_2 + ADC10PDIV_1) +#define ADC10_A_CLOCKDIVIDER_16 (ADC10DIV_3 + ADC10PDIV_1) +#define ADC10_A_CLOCKDIVIDER_20 (ADC10DIV_4 + ADC10PDIV_1) +#define ADC10_A_CLOCKDIVIDER_24 (ADC10DIV_5 + ADC10PDIV_1) +#define ADC10_A_CLOCKDIVIDER_28 (ADC10DIV_6 + ADC10PDIV_1) +#define ADC10_A_CLOCKDIVIDER_32 (ADC10DIV_7 + ADC10PDIV_1) +#define ADC10_A_CLOCKDIVIDER_64 (ADC10DIV_0 + ADC10PDIV_2) +#define ADC10_A_CLOCKDIVIDER_128 (ADC10DIV_1 + ADC10PDIV_2) +#define ADC10_A_CLOCKDIVIDER_192 (ADC10DIV_2 + ADC10PDIV_2) +#define ADC10_A_CLOCKDIVIDER_256 (ADC10DIV_3 + ADC10PDIV_2) +#define ADC10_A_CLOCKDIVIDER_320 (ADC10DIV_4 + ADC10PDIV_2) +#define ADC10_A_CLOCKDIVIDER_384 (ADC10DIV_5 + ADC10PDIV_2) +#define ADC10_A_CLOCKDIVIDER_448 (ADC10DIV_6 + ADC10PDIV_2) +#define ADC10_A_CLOCKDIVIDER_512 (ADC10DIV_7 + ADC10PDIV_2) + +//***************************************************************************** +// +// The following are values that can be passed to the +// sampleHoldSignalSourceSelect parameter for functions: ADC10_A_init(). +// +//***************************************************************************** +#define ADC10_A_SAMPLEHOLDSOURCE_SC (ADC10SHS_0) +#define ADC10_A_SAMPLEHOLDSOURCE_1 (ADC10SHS_1) +#define ADC10_A_SAMPLEHOLDSOURCE_2 (ADC10SHS_2) +#define ADC10_A_SAMPLEHOLDSOURCE_3 (ADC10SHS_3) + +//***************************************************************************** +// +// The following are values that can be passed to the multipleSamplesEnabled +// parameter for functions: ADC10_A_setupSamplingTimer(). +// +//***************************************************************************** +#define ADC10_A_MULTIPLESAMPLESDISABLE (!(ADC10MSC)) +#define ADC10_A_MULTIPLESAMPLESENABLE (ADC10MSC) + +//***************************************************************************** +// +// The following are values that can be passed to the clockCycleHoldCount +// parameter for functions: ADC10_A_setupSamplingTimer(). +// +//***************************************************************************** +#define ADC10_A_CYCLEHOLD_4_CYCLES (ADC10SHT_0) +#define ADC10_A_CYCLEHOLD_8_CYCLES (ADC10SHT_1) +#define ADC10_A_CYCLEHOLD_16_CYCLES (ADC10SHT_2) +#define ADC10_A_CYCLEHOLD_32_CYCLES (ADC10SHT_3) +#define ADC10_A_CYCLEHOLD_64_CYCLES (ADC10SHT_4) +#define ADC10_A_CYCLEHOLD_96_CYCLES (ADC10SHT_5) +#define ADC10_A_CYCLEHOLD_128_CYCLES (ADC10SHT_6) +#define ADC10_A_CYCLEHOLD_192_CYCLES (ADC10SHT_7) +#define ADC10_A_CYCLEHOLD_256_CYCLES (ADC10SHT_8) +#define ADC10_A_CYCLEHOLD_384_CYCLES (ADC10SHT_9) +#define ADC10_A_CYCLEHOLD_512_CYCLES (ADC10SHT_10) +#define ADC10_A_CYCLEHOLD_768_CYCLES (ADC10SHT_11) +#define ADC10_A_CYCLEHOLD_1024_CYCLES (ADC10SHT_12) + +//***************************************************************************** +// +// The following are values that can be passed to the +// positiveRefVoltageSourceSelect parameter for functions: +// ADC10_A_memoryConfigure(). +// +//***************************************************************************** +#define ADC10_A_VREFPOS_AVCC (!(ADC10SREF0 + ADC10SREF1)) +#define ADC10_A_VREFPOS_EXT (ADC10SREF1) +#define ADC10_A_VREFPOS_INT (ADC10SREF0) + +//***************************************************************************** +// +// The following are values that can be passed to the inputSourceSelect +// parameter for functions: ADC10_A_memoryConfigure(). +// +//***************************************************************************** +#define ADC10_A_INPUT_A0 (ADC10INCH_0) +#define ADC10_A_INPUT_A1 (ADC10INCH_1) +#define ADC10_A_INPUT_A2 (ADC10INCH_2) +#define ADC10_A_INPUT_A3 (ADC10INCH_3) +#define ADC10_A_INPUT_A4 (ADC10INCH_4) +#define ADC10_A_INPUT_A5 (ADC10INCH_5) +#define ADC10_A_INPUT_A6 (ADC10INCH_6) +#define ADC10_A_INPUT_A7 (ADC10INCH_7) +#define ADC10_A_INPUT_A8 (ADC10INCH_8) +#define ADC10_A_INPUT_A9 (ADC10INCH_9) +#define ADC10_A_INPUT_TEMPSENSOR (ADC10INCH_10) +#define ADC10_A_INPUT_BATTERYMONITOR (ADC10INCH_11) +#define ADC10_A_INPUT_A12 (ADC10INCH_12) +#define ADC10_A_INPUT_A13 (ADC10INCH_13) +#define ADC10_A_INPUT_A14 (ADC10INCH_14) +#define ADC10_A_INPUT_A15 (ADC10INCH_15) + +//***************************************************************************** +// +// The following are values that can be passed to the +// negativeRefVoltageSourceSelect parameter for functions: +// ADC10_A_memoryConfigure(). +// +//***************************************************************************** +#define ADC10_A_VREFNEG_AVSS (!(ADC10SREF2)) +#define ADC10_A_VREFNEG_EXT (ADC10SREF2) + +//***************************************************************************** +// +// The following are values that can be passed to the interruptMask parameter +// for functions: ADC10_A_enableInterrupt(), and ADC10_A_disableInterrupt(). +// +//***************************************************************************** +#define ADC10_A_TIMEOVERFLOW_INT (ADC10TOVIE) +#define ADC10_A_OVERFLOW_INT (ADC10OVIE) +#define ADC10_A_ABOVETHRESHOLD_INT (ADC10HIIE) +#define ADC10_A_BELOWTHRESHOLD_INT (ADC10LOIE) +#define ADC10_A_INSIDEWINDOW_INT (ADC10INIE) +#define ADC10_A_COMPLETED_INT (ADC10IE0) + +//***************************************************************************** +// +// The following are values that can be passed to the interruptFlagMask +// parameter for functions: ADC10_A_clearInterrupt(), and +// ADC10_A_getInterruptStatus(). +// +//***************************************************************************** +#define ADC10_A_TIMEOVERFLOW_INTFLAG (ADC10TOVIFG) +#define ADC10_A_OVERFLOW_INTFLAG (ADC10OVIFG) +#define ADC10_A_ABOVETHRESHOLD_INTFLAG (ADC10HIIFG) +#define ADC10_A_BELOWTHRESHOLD_INTFLAG (ADC10LOIFG) +#define ADC10_A_INSIDEWINDOW_INTFLAG (ADC10INIFG) +#define ADC10_A_COMPLETED_INTFLAG (ADC10IFG0) + +//***************************************************************************** +// +// The following are values that can be passed to the +// conversionSequenceModeSelect parameter for functions: +// ADC10_A_startConversion(). +// +//***************************************************************************** +#define ADC10_A_SINGLECHANNEL (ADC10CONSEQ_0) +#define ADC10_A_SEQOFCHANNELS (ADC10CONSEQ_1) +#define ADC10_A_REPEATED_SINGLECHANNEL (ADC10CONSEQ_2) +#define ADC10_A_REPEATED_SEQOFCHANNELS (ADC10CONSEQ_3) + +//***************************************************************************** +// +// The following are values that can be passed to the preempt parameter for +// functions: ADC10_A_disableConversions(). +// +//***************************************************************************** +#define ADC10_A_COMPLETECONVERSION false +#define ADC10_A_PREEMPTCONVERSION true + +//***************************************************************************** +// +// The following are values that can be passed to the resolutionSelect +// parameter for functions: ADC10_A_setResolution(). +// +//***************************************************************************** +#define ADC10_A_RESOLUTION_8BIT (!(ADC10RES)) +#define ADC10_A_RESOLUTION_10BIT (ADC10RES) + +//***************************************************************************** +// +// The following are values that can be passed to the invertedSignal parameter +// for functions: ADC10_A_setSampleHoldSignalInversion(). +// +//***************************************************************************** +#define ADC10_A_NONINVERTEDSIGNAL (!(ADC10ISSH)) +#define ADC10_A_INVERTEDSIGNAL (ADC10ISSH) + +//***************************************************************************** +// +// The following are values that can be passed to the readBackFormat parameter +// for functions: ADC10_A_setDataReadBackFormat(). +// +//***************************************************************************** +#define ADC10_A_UNSIGNED_BINARY (!(ADC10DF)) +#define ADC10_A_SIGNED_2SCOMPLEMENT (ADC10DF) + +//***************************************************************************** +// +// The following are values that can be passed to the samplingRateSelect +// parameter for functions: ADC10_A_setReferenceBufferSamplingRate(). +// +//***************************************************************************** +#define ADC10_A_MAXSAMPLINGRATE_200KSPS (!(ADC10SR)) +#define ADC10_A_MAXSAMPLINGRATE_50KSPS (ADC10SR) + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the ADC10_A_isBusy() function. +// +//***************************************************************************** +#define ADC10_A_BUSY ADC10BUSY +#define ADC10_A_NOTBUSY 0x00 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern bool ADC10_A_init(uint16_t baseAddress, + uint16_t sampleHoldSignalSourceSelect, + uint8_t clockSourceSelect, + uint16_t clockSourceDivider); + +extern void ADC10_A_enable(uint16_t baseAddress); + +extern void ADC10_A_disable(uint16_t baseAddress); + +extern void ADC10_A_setupSamplingTimer(uint16_t baseAddress, + uint16_t clockCycleHoldCount, + uint16_t multipleSamplesEnabled); + +extern void ADC10_A_disableSamplingTimer(uint16_t baseAddress); + +extern void ADC10_A_memoryConfigure(uint16_t baseAddress, + uint8_t inputSourceSelect, + uint8_t positiveRefVoltageSourceSelect, + uint8_t negativeRefVoltageSourceSelect); + +extern void ADC10_A_enableInterrupt(uint16_t baseAddress, + uint8_t interruptMask); + +extern void ADC10_A_disableInterrupt(uint16_t baseAddress, + uint8_t interruptMask); + +extern void ADC10_A_clearInterrupt(uint16_t baseAddress, + uint8_t interruptFlagMask); + +extern uint8_t ADC10_A_getInterruptStatus(uint16_t baseAddress, + uint8_t interruptFlagMask); + +extern void ADC10_A_startConversion(uint16_t baseAddress, + uint8_t conversionSequenceModeSelect); + +extern void ADC10_A_disableConversions(uint16_t baseAddress, + bool preempt); + +extern int16_t ADC10_A_getResults(uint16_t baseAddress); + +extern void ADC10_A_setResolution(uint16_t baseAddress, + uint8_t resolutionSelect); + +extern void ADC10_A_setSampleHoldSignalInversion(uint16_t baseAddress, + uint16_t invertedSignal); + +extern void ADC10_A_setDataReadBackFormat(uint16_t baseAddress, + uint16_t readBackFormat); + +extern void ADC10_A_enableReferenceBurst(uint16_t baseAddress); + +extern void ADC10_A_disableReferenceBurst(uint16_t baseAddress); + +extern void ADC10_A_setReferenceBufferSamplingRate(uint16_t baseAddress, + uint16_t samplingRateSelect); + +extern void ADC10_A_setWindowComp(uint16_t baseAddress, + uint16_t highThreshold, + uint16_t lowThreshold); + +extern uint32_t ADC10_A_getMemoryAddressForDMA(uint16_t baseAddress); + +extern uint16_t ADC10_A_isBusy(uint16_t baseAddress); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_ADC10_A_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/adc12_a.c b/source/driverlib/MSP430F5xx_6xx/adc12_a.c new file mode 100644 index 0000000..bd12c6f --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/adc12_a.c @@ -0,0 +1,1033 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// adc12_a.c - Driver for the adc12_a Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup adc12_a_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_ADC12_PLUS__ +#include "adc12_a.h" + +#include + +//***************************************************************************** +// +//! \brief Initializes the ADC12_A Module. +//! +//! This function initializes the ADC module to allow for analog-to-digital +//! conversions. Specifically this function sets up the sample-and-hold signal +//! and clock sources for the ADC core to use for conversions. Upon successful +//! completion of the initialization all of the ADC control registers will be +//! reset, excluding the memory controls and reference module bits, the given +//! parameters will be set, and the ADC core will be turned on (Note, that the +//! ADC core only draws power during conversions and remains off when not +//! converting).Note that sample/hold signal sources are device dependent. Note +//! that if re-initializing the ADC after starting a conversion with the +//! startConversion() function, the disableConversion() must be called BEFORE +//! this function can be called. +//! +//! \param baseAddress is the base address of the ADC12_A module. +//! \param sampleHoldSignalSourceSelect is the signal that will trigger a +//! sample-and-hold for an input signal to be converted. This parameter +//! is device specific and sources should be found in the device's +//! datasheet. +//! Valid values are: +//! - \b ADC12_A_SAMPLEHOLDSOURCE_SC [Default] +//! - \b ADC12_A_SAMPLEHOLDSOURCE_1 +//! - \b ADC12_A_SAMPLEHOLDSOURCE_2 +//! - \b ADC12_A_SAMPLEHOLDSOURCE_3 - This parameter is device specific +//! and sources should be found in the device's datasheet. +//! \n Modified bits are \b ADC12SHSx of \b ADC12CTL1 register. +//! \param clockSourceSelect selects the clock that will be used by the ADC12_A +//! core, and the sampling timer if a sampling pulse mode is enabled. +//! Valid values are: +//! - \b ADC12_A_CLOCKSOURCE_ADC12OSC [Default] - MODOSC 5 MHz +//! oscillator from the UCS +//! - \b ADC12_A_CLOCKSOURCE_ACLK - The Auxiliary Clock +//! - \b ADC12_A_CLOCKSOURCE_MCLK - The Master Clock +//! - \b ADC12_A_CLOCKSOURCE_SMCLK - The Sub-Master Clock +//! \n Modified bits are \b ADC12SSELx of \b ADC12CTL1 register. +//! \param clockSourceDivider selects the amount that the clock will be +//! divided. +//! Valid values are: +//! - \b ADC12_A_CLOCKDIVIDER_1 [Default] +//! - \b ADC12_A_CLOCKDIVIDER_2 +//! - \b ADC12_A_CLOCKDIVIDER_3 +//! - \b ADC12_A_CLOCKDIVIDER_4 +//! - \b ADC12_A_CLOCKDIVIDER_5 +//! - \b ADC12_A_CLOCKDIVIDER_6 +//! - \b ADC12_A_CLOCKDIVIDER_7 +//! - \b ADC12_A_CLOCKDIVIDER_8 +//! - \b ADC12_A_CLOCKDIVIDER_12 +//! - \b ADC12_A_CLOCKDIVIDER_16 +//! - \b ADC12_A_CLOCKDIVIDER_20 +//! - \b ADC12_A_CLOCKDIVIDER_24 +//! - \b ADC12_A_CLOCKDIVIDER_28 +//! - \b ADC12_A_CLOCKDIVIDER_32 +//! \n Modified bits are \b ADC12PDIV of \b ADC12CTL2 register; bits \b +//! ADC12DIVx of \b ADC12CTL1 register. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the initialization process. +// +//***************************************************************************** +bool ADC12_A_init(uint16_t baseAddress, + uint16_t sampleHoldSignalSourceSelect, + uint8_t clockSourceSelect, + uint16_t clockSourceDivider) +{ + assert(sampleHoldSignalSourceSelect <= ADC12_A_SAMPLEHOLDSOURCE_3); + assert(clockSourceSelect <= ADC12_A_CLOCKSOURCE_SMCLK); + assert(clockSourceDivider <= ADC12_A_CLOCKDIVIDER_32); + + //Make sure the ENC bit is cleared before initializing the ADC12_A + HWREG8(baseAddress + OFS_ADC12CTL0_L) &= ~ADC12ENC; + + bool retVal = STATUS_SUCCESS; + + //Turn OFF ADC12_A Module & Clear Interrupt Registers + HWREG16(baseAddress + OFS_ADC12CTL0) &= ~(ADC12ON + ADC12OVIE + ADC12TOVIE + + ADC12ENC + ADC12SC); + HWREG16(baseAddress + OFS_ADC12IE) &= 0x0000; //Reset ALL interrupt enables + HWREG16(baseAddress + OFS_ADC12IFG) &= 0x0000; //Reset ALL interrupt flags + + //Set ADC12_A Control 1 + HWREG16(baseAddress + OFS_ADC12CTL1) = + sampleHoldSignalSourceSelect //Setup the Sample-and-Hold Source + + (clockSourceDivider & ADC12DIV_7) //Set Clock Divider + + clockSourceSelect; //Setup Clock Source + + //Set ADC12_A Control 2 + HWREG16(baseAddress + OFS_ADC12CTL2) = + (clockSourceDivider & ADC12PDIV) //Set Clock Pre-Divider + + ADC12RES_2; //Default resolution to 12-bits + + return retVal; +} + +//***************************************************************************** +// +//! \brief Enables the ADC12_A block. +//! +//! This will enable operation of the ADC12_A block. +//! +//! \param baseAddress is the base address of the ADC12_A module. +//! +//! Modified bits are \b ADC12ON of \b ADC12CTL0 register. +//! +//! \return None +// +//***************************************************************************** +void ADC12_A_enable(uint16_t baseAddress) +{ + //Enable the ADC12_A Module + HWREG8(baseAddress + OFS_ADC12CTL0_L) |= ADC12ON; +} + +//***************************************************************************** +// +//! \brief Disables the ADC12_A block. +//! +//! This will disable operation of the ADC12_A block. +//! +//! \param baseAddress is the base address of the ADC12_A module. +//! +//! Modified bits are \b ADC12ON of \b ADC12CTL0 register. +//! +//! \return None +// +//***************************************************************************** +void ADC12_A_disable(uint16_t baseAddress) +{ + //Disable ADC12_A module + HWREG8(baseAddress + OFS_ADC12CTL0_L) &= ~ADC12ON; +} + +//***************************************************************************** +// +//! \brief Sets up and enables the Sampling Timer Pulse Mode. +//! +//! This function sets up the sampling timer pulse mode which allows the +//! sample/hold signal to trigger a sampling timer to sample-and-hold an input +//! signal for a specified number of clock cycles without having to hold the +//! sample/hold signal for the entire period of sampling. Note that if a +//! conversion has been started with the startConversion() function, then a +//! call to disableConversions() is required before this function may be +//! called. +//! +//! \param baseAddress is the base address of the ADC12_A module. +//! \param clockCycleHoldCountLowMem sets the amount of clock cycles to sample- +//! and-hold for the higher memory buffers 0-7. +//! Valid values are: +//! - \b ADC12_A_CYCLEHOLD_4_CYCLES [Default] +//! - \b ADC12_A_CYCLEHOLD_8_CYCLES +//! - \b ADC12_A_CYCLEHOLD_16_CYCLES +//! - \b ADC12_A_CYCLEHOLD_32_CYCLES +//! - \b ADC12_A_CYCLEHOLD_64_CYCLES +//! - \b ADC12_A_CYCLEHOLD_96_CYCLES +//! - \b ADC12_A_CYCLEHOLD_128_CYCLES +//! - \b ADC12_A_CYCLEHOLD_192_CYCLES +//! - \b ADC12_A_CYCLEHOLD_256_CYCLES +//! - \b ADC12_A_CYCLEHOLD_384_CYCLES +//! - \b ADC12_A_CYCLEHOLD_512_CYCLES +//! - \b ADC12_A_CYCLEHOLD_768_CYCLES +//! - \b ADC12_A_CYCLEHOLD_1024_CYCLES +//! \n Modified bits are \b ADC12SHT0x of \b ADC12CTL0 register. +//! \param clockCycleHoldCountHighMem sets the amount of clock cycles to +//! sample-and-hold for the higher memory buffers 8-15. +//! Valid values are: +//! - \b ADC12_A_CYCLEHOLD_4_CYCLES [Default] +//! - \b ADC12_A_CYCLEHOLD_8_CYCLES +//! - \b ADC12_A_CYCLEHOLD_16_CYCLES +//! - \b ADC12_A_CYCLEHOLD_32_CYCLES +//! - \b ADC12_A_CYCLEHOLD_64_CYCLES +//! - \b ADC12_A_CYCLEHOLD_96_CYCLES +//! - \b ADC12_A_CYCLEHOLD_128_CYCLES +//! - \b ADC12_A_CYCLEHOLD_192_CYCLES +//! - \b ADC12_A_CYCLEHOLD_256_CYCLES +//! - \b ADC12_A_CYCLEHOLD_384_CYCLES +//! - \b ADC12_A_CYCLEHOLD_512_CYCLES +//! - \b ADC12_A_CYCLEHOLD_768_CYCLES +//! - \b ADC12_A_CYCLEHOLD_1024_CYCLES +//! \n Modified bits are \b ADC12SHT1x of \b ADC12CTL0 register. +//! \param multipleSamplesEnabled allows multiple conversions to start without +//! a trigger signal from the sample/hold signal +//! Valid values are: +//! - \b ADC12_A_MULTIPLESAMPLESDISABLE [Default] - a timer trigger will +//! be needed to start every ADC conversion. +//! - \b ADC12_A_MULTIPLESAMPLESENABLE - during a sequenced and/or +//! repeated conversion mode, after the first conversion, no +//! sample/hold signal is necessary to start subsequent sample/hold +//! and convert processes. +//! \n Modified bits are \b ADC12MSC of \b ADC12CTL0 register. +//! +//! \return None +// +//***************************************************************************** +void ADC12_A_setupSamplingTimer(uint16_t baseAddress, + uint16_t clockCycleHoldCountLowMem, + uint16_t clockCycleHoldCountHighMem, + uint16_t multipleSamplesEnabled) +{ + //Make sure the ENC bit is cleared before setting up sampling pulse mode + assert( !(HWREG8(baseAddress + OFS_ADC12CTL0_L) & ADC12ENC) ); + + assert(clockCycleHoldCountLowMem <= ADC12_A_CYCLEHOLD_1024_CYCLES); + assert(clockCycleHoldCountHighMem <= ADC12_A_CYCLEHOLD_1024_CYCLES); + + HWREG16(baseAddress + OFS_ADC12CTL1) |= ADC12SHP; + + //Reset clock cycle hold counts and msc bit before setting them + HWREG16(baseAddress + OFS_ADC12CTL0) &= + ~(ADC12SHT0_15 + ADC12SHT1_15 + ADC12MSC); + + //Set clock cycle hold counts and msc bit + HWREG16(baseAddress + OFS_ADC12CTL0) |= clockCycleHoldCountLowMem + + (clockCycleHoldCountHighMem << 4) + + multipleSamplesEnabled; +} + +//***************************************************************************** +// +//! \brief Disables Sampling Timer Pulse Mode. +//! +//! Disables the Sampling Timer Pulse Mode. Note that if a conversion has been +//! started with the startConversion() function, then a call to +//! disableConversions() is required before this function may be called. +//! +//! \param baseAddress is the base address of the ADC12_A module. +//! +//! Modified bits are \b ADC12SHP of \b ADC12CTL0 register. +//! +//! \return None +// +//***************************************************************************** +void ADC12_A_disableSamplingTimer(uint16_t baseAddress) +{ + //Make sure the ENC bit is cleared before disabling sampling pulse mode + assert( !(HWREG8(baseAddress + OFS_ADC12CTL0_L) & ADC12ENC) ); + + HWREG16(baseAddress + OFS_ADC12CTL1) &= ~(ADC12SHP); +} + +//***************************************************************************** +// +//! \brief DEPRECATED - Configures the controls of the selected memory buffer. +//! +//! Maps an input signal conversion into the selected memory buffer, as well as +//! the positive and negative reference voltages for each conversion being +//! stored into this memory buffer. If the internal reference is used for the +//! positive reference voltage, the internal REF module must be used to control +//! the voltage level. Note that if a conversion has been started with the +//! startConversion() function, then a call to disableConversions() is required +//! before this function may be called. +//! +//! \param baseAddress is the base address of the ADC12_A module. +//! \param memoryBufferControlIndex is the selected memory buffer to set the +//! configuration for. +//! Valid values are: +//! - \b ADC12_A_MEMORY_0 [Default] +//! - \b ADC12_A_MEMORY_1 +//! - \b ADC12_A_MEMORY_2 +//! - \b ADC12_A_MEMORY_3 +//! - \b ADC12_A_MEMORY_4 +//! - \b ADC12_A_MEMORY_5 +//! - \b ADC12_A_MEMORY_6 +//! - \b ADC12_A_MEMORY_7 +//! - \b ADC12_A_MEMORY_8 +//! - \b ADC12_A_MEMORY_9 +//! - \b ADC12_A_MEMORY_10 +//! - \b ADC12_A_MEMORY_11 +//! - \b ADC12_A_MEMORY_12 +//! - \b ADC12_A_MEMORY_13 +//! - \b ADC12_A_MEMORY_14 +//! - \b ADC12_A_MEMORY_15 +//! \param inputSourceSelect is the input that will store the converted data +//! into the specified memory buffer. +//! Valid values are: +//! - \b ADC12_A_INPUT_A0 [Default] +//! - \b ADC12_A_INPUT_A1 +//! - \b ADC12_A_INPUT_A2 +//! - \b ADC12_A_INPUT_A3 +//! - \b ADC12_A_INPUT_A4 +//! - \b ADC12_A_INPUT_A5 +//! - \b ADC12_A_INPUT_A6 +//! - \b ADC12_A_INPUT_A7 +//! - \b ADC12_A_INPUT_A8 +//! - \b ADC12_A_INPUT_A9 +//! - \b ADC12_A_INPUT_TEMPSENSOR +//! - \b ADC12_A_INPUT_BATTERYMONITOR +//! - \b ADC12_A_INPUT_A12 +//! - \b ADC12_A_INPUT_A13 +//! - \b ADC12_A_INPUT_A14 +//! - \b ADC12_A_INPUT_A15 +//! \n Modified bits are \b ADC12INCHx of \b ADC12MCTLx register. +//! \param positiveRefVoltageSourceSelect is the reference voltage source to +//! set as the upper limit for the conversion stored in the specified +//! memory. +//! Valid values are: +//! - \b ADC12_A_VREFPOS_AVCC [Default] +//! - \b ADC12_A_VREFPOS_EXT +//! - \b ADC12_A_VREFPOS_INT +//! \n Modified bits are \b ADC12SREF of \b ADC12MCTLx register. +//! \param negativeRefVoltageSourceSelect is the reference voltage source to +//! set as the lower limit for the conversion stored in the specified +//! memory. +//! Valid values are: +//! - \b ADC12_A_VREFNEG_AVSS [Default] +//! - \b ADC12_A_VREFNEG_EXT +//! \n Modified bits are \b ADC12SREF of \b ADC12MCTLx register. +//! \param endOfSequence indicates that the specified memory buffer will be the +//! end of the sequence if a sequenced conversion mode is selected +//! Valid values are: +//! - \b ADC12_A_NOTENDOFSEQUENCE [Default] - The specified memory +//! buffer will NOT be the end of the sequence OR a sequenced +//! conversion mode is not selected. +//! - \b ADC12_A_ENDOFSEQUENCE - The specified memory buffer will be the +//! end of the sequence. +//! \n Modified bits are \b ADC12EOS of \b ADC12MCTLx register. +//! +//! \return None +// +//***************************************************************************** +void ADC12_A_memoryConfigure(uint16_t baseAddress, + uint8_t memoryBufferControlIndex, + uint8_t inputSourceSelect, + uint8_t positiveRefVoltageSourceSelect, + uint8_t negativeRefVoltageSourceSelect, + uint8_t endOfSequence) +{ + ADC12_A_configureMemoryParam param = { 0 }; + + param.memoryBufferControlIndex = memoryBufferControlIndex; + param.inputSourceSelect = inputSourceSelect; + param.positiveRefVoltageSourceSelect = positiveRefVoltageSourceSelect; + param.negativeRefVoltageSourceSelect = negativeRefVoltageSourceSelect; + param.endOfSequence = endOfSequence; + + ADC12_A_configureMemory(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Configures the controls of the selected memory buffer. +//! +//! Maps an input signal conversion into the selected memory buffer, as well as +//! the positive and negative reference voltages for each conversion being +//! stored into this memory buffer. If the internal reference is used for the +//! positive reference voltage, the internal REF module must be used to control +//! the voltage level. Note that if a conversion has been started with the +//! startConversion() function, then a call to disableConversions() is required +//! before this function may be called. +//! +//! \param baseAddress is the base address of the ADC12_A module. +//! \param param is the pointer to struct for memory configuration. +//! +//! \return None +// +//***************************************************************************** +void ADC12_A_configureMemory(uint16_t baseAddress, + ADC12_A_configureMemoryParam *param) +{ + assert(param != 0); + + //Make sure the ENC bit is cleared before configuring a Memory Buffer Control + assert(!(HWREG8(baseAddress + OFS_ADC12CTL0_L) & ADC12ENC) ); + + assert(param->memoryBufferControlIndex <= ADC12_A_MEMORY_15); + assert(param->inputSourceSelect <= ADC12_A_INPUT_A15); + assert(param->positiveRefVoltageSourceSelect <= ADC12_A_VREFPOS_INT); + assert(param->negativeRefVoltageSourceSelect <= ADC12_A_VREFNEG_EXT); + + //Set the offset in respect to ADC12MCTL0 + uint16_t memoryBufferControlOffset = + (OFS_ADC12MCTL0 + param->memoryBufferControlIndex); + + //Reset the memory buffer control and Set the input source + HWREG8(baseAddress + memoryBufferControlOffset) = + param->inputSourceSelect //Set Input Source + + param->positiveRefVoltageSourceSelect //Set Vref+ + + param->negativeRefVoltageSourceSelect //Set Vref- + + param->endOfSequence; //Set End of Sequence +} //***************************************************************************** +// +//! \brief Enables selected ADC12_A interrupt sources. +//! +//! Enables the indicated ADC12_A interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt, disabled sources have +//! no effect on the processor. Does not clear interrupt flags. +//! +//! \param baseAddress is the base address of the ADC12_A module. +//! \param interruptMask +//! Mask value is the logical OR of any of the following: +//! - \b ADC12_A_IE0 +//! - \b ADC12_A_IE1 +//! - \b ADC12_A_IE2 +//! - \b ADC12_A_IE3 +//! - \b ADC12_A_IE4 +//! - \b ADC12_A_IE5 +//! - \b ADC12_A_IE6 +//! - \b ADC12_A_IE7 +//! - \b ADC12_A_IE8 +//! - \b ADC12_A_IE9 +//! - \b ADC12_A_IE10 +//! - \b ADC12_A_IE11 +//! - \b ADC12_A_IE12 +//! - \b ADC12_A_IE13 +//! - \b ADC12_A_IE14 +//! - \b ADC12_A_IE15 +//! - \b ADC12_A_OVERFLOW_IE +//! - \b ADC12_A_CONVERSION_TIME_OVERFLOW_IE +//! +//! Modified bits of \b ADC12IE register and bits of \b ADC12CTL0 register. +//! +//! \return None +// +//***************************************************************************** +void ADC12_A_enableInterrupt(uint16_t baseAddress, + uint32_t interruptMask) +{ + assert(interruptMask <= (ADC12IE0 + + ADC12IE1 + + ADC12IE2 + + ADC12IE3 + + ADC12IE4 + + ADC12IE5 + + ADC12IE6 + + ADC12IE7 + + ADC12IE8 + + ADC12IE9 + + ADC12IE10 + + ADC12IE11 + + ADC12IE12 + + ADC12IE13 + + ADC12IE14 + + ADC12IE15 + + ADC12OVIE0 + + ADC12TOVIE0 + )); + + if (interruptMask & ADC12_A_CONVERSION_TIME_OVERFLOW_IE) { + HWREG16(baseAddress + OFS_ADC12CTL0) |= ADC12TOVIE; + interruptMask &= ~ADC12TOVIE0; + } + if (interruptMask & ADC12_A_OVERFLOW_IE) { + HWREG16(baseAddress + OFS_ADC12CTL0) |= ADC12OVIE; + interruptMask &= ~ADC12OVIE0; + } + + HWREG16(baseAddress + OFS_ADC12IE) |= interruptMask; +} + +//***************************************************************************** +// +//! \brief Disables selected ADC12_A interrupt sources. +//! +//! Disables the indicated ADC12_A interrupt sources. Only the sources that +//! are enabled can be reflected to the processor interrupt, disabled sources +//! have no effect on the processor. +//! +//! \param baseAddress is the base address of the ADC12_A module. +//! \param interruptMask +//! Mask value is the logical OR of any of the following: +//! - \b ADC12_A_IE0 +//! - \b ADC12_A_IE1 +//! - \b ADC12_A_IE2 +//! - \b ADC12_A_IE3 +//! - \b ADC12_A_IE4 +//! - \b ADC12_A_IE5 +//! - \b ADC12_A_IE6 +//! - \b ADC12_A_IE7 +//! - \b ADC12_A_IE8 +//! - \b ADC12_A_IE9 +//! - \b ADC12_A_IE10 +//! - \b ADC12_A_IE11 +//! - \b ADC12_A_IE12 +//! - \b ADC12_A_IE13 +//! - \b ADC12_A_IE14 +//! - \b ADC12_A_IE15 +//! - \b ADC12_A_OVERFLOW_IE +//! - \b ADC12_A_CONVERSION_TIME_OVERFLOW_IE +//! +//! Modified bits of \b ADC12IE register and bits of \b ADC12CTL0 register. +//! +//! \return None +// +//***************************************************************************** +void ADC12_A_disableInterrupt(uint16_t baseAddress, + uint32_t interruptMask) +{ + assert(interruptMask <= (ADC12IE0 + + ADC12IE1 + + ADC12IE2 + + ADC12IE3 + + ADC12IE4 + + ADC12IE5 + + ADC12IE6 + + ADC12IE7 + + ADC12IE8 + + ADC12IE9 + + ADC12IE10 + + ADC12IE11 + + ADC12IE12 + + ADC12IE13 + + ADC12IE14 + + ADC12IE15 + + ADC12OVIE0 + + ADC12TOVIE0 + )); + + if (interruptMask & ADC12_A_CONVERSION_TIME_OVERFLOW_IE) { + HWREG16(baseAddress + OFS_ADC12CTL0) &= ~(ADC12TOVIE); + interruptMask &= ~ADC12TOVIE0; + } + if (interruptMask & ADC12_A_OVERFLOW_IE) { + HWREG16(baseAddress + OFS_ADC12CTL0) &= ~(ADC12OVIE); + interruptMask &= ~ADC12OVIE0; + } + + HWREG16(baseAddress + OFS_ADC12IE) &= ~(interruptMask); +} + +//***************************************************************************** +// +//! \brief Clears ADC12_A selected interrupt flags. +//! +//! The selected ADC12_A interrupt flags are cleared, so that it no longer +//! asserts. The memory buffer interrupt flags are only cleared when the memory +//! buffer is accessed. Note that the overflow interrupts do not have an +//! interrupt flag to clear; they must be accessed directly from the interrupt +//! vector. +//! +//! \param baseAddress is the base address of the ADC12_A module. +//! \param memoryInterruptFlagMask is a bit mask of the interrupt flags to be +//! cleared. +//! Mask value is the logical OR of any of the following: +//! - \b ADC12_A_IFG0 +//! - \b ADC12_A_IFG1 +//! - \b ADC12_A_IFG2 +//! - \b ADC12_A_IFG3 +//! - \b ADC12_A_IFG4 +//! - \b ADC12_A_IFG5 +//! - \b ADC12_A_IFG6 +//! - \b ADC12_A_IFG7 +//! - \b ADC12_A_IFG8 +//! - \b ADC12_A_IFG9 +//! - \b ADC12_A_IFG10 +//! - \b ADC12_A_IFG11 +//! - \b ADC12_A_IFG12 +//! - \b ADC12_A_IFG13 +//! - \b ADC12_A_IFG14 +//! - \b ADC12_A_IFG15 +//! +//! Modified bits of \b ADC12IFG register. +//! +//! \return None +// +//***************************************************************************** +void ADC12_A_clearInterrupt(uint16_t baseAddress, + uint16_t memoryInterruptFlagMask) +{ + HWREG16(baseAddress + OFS_ADC12IFG) &= ~(memoryInterruptFlagMask); +} + +//***************************************************************************** +// +//! \brief Returns the status of the selected memory interrupt flags. +//! +//! Returns the status of the selected memory interrupt flags. Note that the +//! overflow interrupts do not have an interrupt flag to clear; they must be +//! accessed directly from the interrupt vector. +//! +//! \param baseAddress is the base address of the ADC12_A module. +//! \param memoryInterruptFlagMask is a bit mask of the interrupt flags status +//! to be returned. +//! Mask value is the logical OR of any of the following: +//! - \b ADC12_A_IFG0 +//! - \b ADC12_A_IFG1 +//! - \b ADC12_A_IFG2 +//! - \b ADC12_A_IFG3 +//! - \b ADC12_A_IFG4 +//! - \b ADC12_A_IFG5 +//! - \b ADC12_A_IFG6 +//! - \b ADC12_A_IFG7 +//! - \b ADC12_A_IFG8 +//! - \b ADC12_A_IFG9 +//! - \b ADC12_A_IFG10 +//! - \b ADC12_A_IFG11 +//! - \b ADC12_A_IFG12 +//! - \b ADC12_A_IFG13 +//! - \b ADC12_A_IFG14 +//! - \b ADC12_A_IFG15 +//! +//! \return The current interrupt flag status for the corresponding mask. +// +//***************************************************************************** +uint8_t ADC12_A_getInterruptStatus(uint16_t baseAddress, + uint16_t memoryInterruptFlagMask) +{ + return HWREG16(baseAddress + OFS_ADC12IFG) & memoryInterruptFlagMask; +} + +//***************************************************************************** +// +//! \brief Enables/Starts an Analog-to-Digital Conversion. +//! +//! This function enables/starts the conversion process of the ADC. If the +//! sample/hold signal source chosen during initialization was ADC12OSC, then +//! the conversion is started immediately, otherwise the chosen sample/hold +//! signal source starts the conversion by a rising edge of the signal. Keep in +//! mind when selecting conversion modes, that for sequenced and/or repeated +//! modes, to keep the sample/hold-and-convert process continuing without a +//! trigger from the sample/hold signal source, the multiple samples must be +//! enabled using the ADC12_A_setupSamplingTimer() function. Note that after +//! this function is called, the ADC12_A_disableConversions() has to be called +//! to re-initialize the ADC, reconfigure a memory buffer control, +//! enable/disable the sampling timer, or to change the internal reference +//! voltage. +//! +//! \param baseAddress is the base address of the ADC12_A module. +//! \param startingMemoryBufferIndex is the memory buffer that will hold the +//! first or only conversion. +//! Valid values are: +//! - \b ADC12_A_MEMORY_0 [Default] +//! - \b ADC12_A_MEMORY_1 +//! - \b ADC12_A_MEMORY_2 +//! - \b ADC12_A_MEMORY_3 +//! - \b ADC12_A_MEMORY_4 +//! - \b ADC12_A_MEMORY_5 +//! - \b ADC12_A_MEMORY_6 +//! - \b ADC12_A_MEMORY_7 +//! - \b ADC12_A_MEMORY_8 +//! - \b ADC12_A_MEMORY_9 +//! - \b ADC12_A_MEMORY_10 +//! - \b ADC12_A_MEMORY_11 +//! - \b ADC12_A_MEMORY_12 +//! - \b ADC12_A_MEMORY_13 +//! - \b ADC12_A_MEMORY_14 +//! - \b ADC12_A_MEMORY_15 +//! \n Modified bits are \b ADC12STARTADDx of \b ADC12CTL1 register. +//! \param conversionSequenceModeSelect determines the ADC operating mode. +//! Valid values are: +//! - \b ADC12_A_SINGLECHANNEL [Default] - one-time conversion of a +//! single channel into a single memory buffer. +//! - \b ADC12_A_SEQOFCHANNELS - one time conversion of multiple +//! channels into the specified starting memory buffer and each +//! subsequent memory buffer up until the conversion is stored in a +//! memory buffer dedicated as the end-of-sequence by the memory's +//! control register. +//! - \b ADC12_A_REPEATED_SINGLECHANNEL - repeated conversions of one +//! channel into a single memory buffer. +//! - \b ADC12_A_REPEATED_SEQOFCHANNELS - repeated conversions of +//! multiple channels into the specified starting memory buffer and +//! each subsequent memory buffer up until the conversion is stored +//! in a memory buffer dedicated as the end-of-sequence by the +//! memory's control register. +//! \n Modified bits are \b ADC12CONSEQx of \b ADC12CTL1 register. +//! +//! Modified bits of \b ADC12CTL1 register and bits of \b ADC12CTL0 register. +//! +//! \return None +// +//***************************************************************************** +void ADC12_A_startConversion(uint16_t baseAddress, + uint16_t startingMemoryBufferIndex, + uint8_t conversionSequenceModeSelect) +{ + assert(startingMemoryBufferIndex <= ADC12_A_MEMORY_15); + assert(conversionSequenceModeSelect <= ADC12_A_REPEATED_SEQOFCHANNELS); + + //Reset the ENC bit to set the starting memory address and conversion mode + //sequence + HWREG8(baseAddress + OFS_ADC12CTL0_L) &= ~(ADC12ENC); + //Reset the bits about to be set + HWREG16(baseAddress + OFS_ADC12CTL1) &= ~(ADC12CSTARTADD_15 + ADC12CONSEQ_3); + + HWREG8(baseAddress + OFS_ADC12CTL1_H) |= (startingMemoryBufferIndex << 4); + HWREG8(baseAddress + OFS_ADC12CTL1_L) |= conversionSequenceModeSelect; + HWREG8(baseAddress + OFS_ADC12CTL0_L) |= ADC12ENC + ADC12SC; +} + +//***************************************************************************** +// +//! \brief Disables the ADC from converting any more signals. +//! +//! Disables the ADC from converting any more signals. If there is a conversion +//! in progress, this function can stop it immediately if the preempt parameter +//! is set as TRUE, by changing the conversion mode to single-channel, single- +//! conversion and disabling conversions. If the conversion mode is set as +//! single-channel, single-conversion and this function is called without +//! preemption, then the ADC core conversion status is polled until the +//! conversion is complete before disabling conversions to prevent +//! unpredictable data. If the ADC12_A_startConversion() has been called, then +//! this function has to be called to re-initialize the ADC, reconfigure a +//! memory buffer control, enable/disable the sampling pulse mode, or change +//! the internal reference voltage. +//! +//! \param baseAddress is the base address of the ADC12_A module. +//! \param preempt specifies if the current conversion should be pre-empted +//! before the end of the conversion. +//! Valid values are: +//! - \b ADC12_A_COMPLETECONVERSION - Allows the ADC12_A to end the +//! current conversion before disabling conversions. +//! - \b ADC12_A_PREEMPTCONVERSION - Stops the ADC12_A immediately, with +//! unpredictable results of the current conversion. +//! +//! Modified bits of \b ADC12CTL1 register and bits of \b ADC12CTL0 register. +//! +//! \return None +// +//***************************************************************************** +void ADC12_A_disableConversions(uint16_t baseAddress, bool preempt) +{ + if (ADC12_A_PREEMPTCONVERSION == preempt) + HWREG8(baseAddress + OFS_ADC12CTL1_L) &= ~(ADC12CONSEQ_3); + //Reset conversion sequence mode to single-channel, single-conversion + else if (~(HWREG8(baseAddress + OFS_ADC12CTL1_L) & ADC12CONSEQ_3)) { + //To prevent preemoption of a single-channel, single-conversion we must + //wait for the ADC core to finish the conversion. + while (ADC12_A_isBusy(baseAddress)) ; + } + + HWREG8(baseAddress + OFS_ADC12CTL0_L) &= ~(ADC12ENC); +} + +//***************************************************************************** +// +//! \brief A Signed Integer of the contents of the specified memory buffer +//! +//! Returns the raw contents of the specified memory buffer. The format of the +//! content depends on the read-back format of the data: if the data is in +//! signed 2's complement format then the contents in the memory buffer will be +//! left-justified with the least-significant bits as 0's, whereas if the data +//! is in unsigned format then the contents in the memory buffer will be right- +//! justified with the most-significant bits as 0's. +//! +//! \param baseAddress is the base address of the ADC12_A module. +//! \param memoryBufferIndex is the specified Memory Buffer to read. +//! Valid values are: +//! - \b ADC12_A_MEMORY_0 [Default] +//! - \b ADC12_A_MEMORY_1 +//! - \b ADC12_A_MEMORY_2 +//! - \b ADC12_A_MEMORY_3 +//! - \b ADC12_A_MEMORY_4 +//! - \b ADC12_A_MEMORY_5 +//! - \b ADC12_A_MEMORY_6 +//! - \b ADC12_A_MEMORY_7 +//! - \b ADC12_A_MEMORY_8 +//! - \b ADC12_A_MEMORY_9 +//! - \b ADC12_A_MEMORY_10 +//! - \b ADC12_A_MEMORY_11 +//! - \b ADC12_A_MEMORY_12 +//! - \b ADC12_A_MEMORY_13 +//! - \b ADC12_A_MEMORY_14 +//! - \b ADC12_A_MEMORY_15 +//! +//! \return A signed integer of the contents of the specified memory buffer +// +//***************************************************************************** +uint16_t ADC12_A_getResults(uint16_t baseAddress, uint8_t memoryBufferIndex) +{ + assert(memoryBufferIndex <= ADC12_A_MEMORY_15); + + return HWREG16(baseAddress + (0x20 + (memoryBufferIndex * 2))); + //(0x20 + (memoryBufferIndex * 2)) == offset of ADC12MEMx +} + +//***************************************************************************** +// +//! \brief Use to change the resolution of the converted data. +//! +//! This function can be used to change the resolution of the converted data +//! from the default of 12-bits. +//! +//! \param baseAddress is the base address of the ADC12_A module. +//! \param resolutionSelect determines the resolution of the converted data. +//! Valid values are: +//! - \b ADC12_A_RESOLUTION_8BIT +//! - \b ADC12_A_RESOLUTION_10BIT +//! - \b ADC12_A_RESOLUTION_12BIT [Default] +//! \n Modified bits are \b ADC12RESx of \b ADC12CTL2 register. +//! +//! \return None +// +//***************************************************************************** +void ADC12_A_setResolution(uint16_t baseAddress, + uint8_t resolutionSelect) +{ + assert(resolutionSelect <= ADC12_A_RESOLUTION_12BIT); + + HWREG8(baseAddress + OFS_ADC12CTL2_L) &= ~(ADC12RES_3); + HWREG8(baseAddress + OFS_ADC12CTL2_L) |= resolutionSelect; +} + +//***************************************************************************** +// +//! \brief Use to invert or un-invert the sample/hold signal. +//! +//! This function can be used to invert or un-invert the sample/hold signal. +//! Note that if a conversion has been started with the startConversion() +//! function, then a call to disableConversions() is required before this +//! function may be called. +//! +//! \param baseAddress is the base address of the ADC12_A module. +//! \param invertedSignal set if the sample/hold signal should be inverted +//! Valid values are: +//! - \b ADC12_A_NONINVERTEDSIGNAL [Default] - a sample-and-hold of an +//! input signal for conversion will be started on a rising edge of +//! the sample/hold signal. +//! - \b ADC12_A_INVERTEDSIGNAL - a sample-and-hold of an input signal +//! for conversion will be started on a falling edge of the +//! sample/hold signal. +//! \n Modified bits are \b ADC12ISSH of \b ADC12CTL1 register. +//! +//! \return None +// +//***************************************************************************** +void ADC12_A_setSampleHoldSignalInversion(uint16_t baseAddress, + uint16_t invertedSignal) +{ + //Make sure the ENC bit is cleared before using this function + assert( !(HWREG8(baseAddress + OFS_ADC12CTL0_L) & ADC12ENC) ); + + HWREG16(baseAddress + OFS_ADC12CTL1) &= ~(ADC12ISSH); + HWREG16(baseAddress + OFS_ADC12CTL1) |= invertedSignal; +} + +//***************************************************************************** +// +//! \brief Use to set the read-back format of the converted data. +//! +//! Sets the format of the converted data: how it will be stored into the +//! memory buffer, and how it should be read back. The format can be set as +//! right-justified (default), which indicates that the number will be +//! unsigned, or left-justified, which indicates that the number will be signed +//! in 2's complement format. This change affects all memory buffers for +//! subsequent conversions. +//! +//! \param baseAddress is the base address of the ADC12_A module. +//! \param readBackFormat is the specified format to store the conversions in +//! the memory buffer. +//! Valid values are: +//! - \b ADC12_A_UNSIGNED_BINARY [Default] +//! - \b ADC12_A_SIGNED_2SCOMPLEMENT +//! \n Modified bits are \b ADC12DF of \b ADC12CTL2 register. +//! +//! \return None +// +//***************************************************************************** +void ADC12_A_setDataReadBackFormat(uint16_t baseAddress, + uint8_t readBackFormat) +{ + assert(readBackFormat <= ADC12_A_SIGNED_2SCOMPLEMENT); + + HWREG8(baseAddress + OFS_ADC12CTL2_L) &= ~(ADC12DF); + HWREG8(baseAddress + OFS_ADC12CTL2_L) |= readBackFormat; +} + +//***************************************************************************** +// +//! \brief Enables the reference buffer's burst ability. +//! +//! Enables the reference buffer's burst ability, allowing the reference buffer +//! to turn off while the ADC is not converting, and automatically turning on +//! when the ADC needs the generated reference voltage for a conversion. +//! +//! \param baseAddress is the base address of the ADC12_A module. +//! +//! \return None +// +//***************************************************************************** +void ADC12_A_enableReferenceBurst(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_ADC12CTL2_L) |= ADC12REFBURST; +} + +//***************************************************************************** +// +//! \brief Disables the reference buffer's burst ability. +//! +//! Disables the reference buffer's burst ability, forcing the reference buffer +//! to remain on continuously. +//! +//! \param baseAddress is the base address of the ADC12_A module. +//! +//! \return None +// +//***************************************************************************** +void ADC12_A_disableReferenceBurst(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_ADC12CTL2_L) &= ~(ADC12REFBURST); +} + +//***************************************************************************** +// +//! \brief Use to set the reference buffer's sampling rate. +//! +//! Sets the reference buffer's sampling rate to the selected sampling rate. +//! The default sampling rate is maximum of 200-ksps, and can be reduced to a +//! maximum of 50-ksps to conserve power. +//! +//! \param baseAddress is the base address of the ADC12_A module. +//! \param samplingRateSelect is the specified maximum sampling rate. +//! Valid values are: +//! - \b ADC12_A_MAXSAMPLINGRATE_200KSPS [Default] +//! - \b ADC12_A_MAXSAMPLINGRATE_50KSPS +//! \n Modified bits are \b ADC12SR of \b ADC12CTL2 register. +//! +//! \return None +// +//***************************************************************************** +void ADC12_A_setReferenceBufferSamplingRate(uint16_t baseAddress, + uint8_t samplingRateSelect) +{ + assert(samplingRateSelect <= ADC12_A_MAXSAMPLINGRATE_50KSPS); + + HWREG8(baseAddress + OFS_ADC12CTL2_L) &= ~(ADC12SR); + HWREG8(baseAddress + OFS_ADC12CTL2_L) |= samplingRateSelect; +} + +//***************************************************************************** +// +//! \brief Returns the address of the specified memory buffer for the DMA +//! module. +//! +//! Returns the address of the specified memory buffer. This can be used in +//! conjunction with the DMA to store the converted data directly to memory. +//! +//! \param baseAddress is the base address of the ADC12_A module. +//! \param memoryIndex is the memory buffer to return the address of. +//! Valid values are: +//! - \b ADC12_A_MEMORY_0 [Default] +//! - \b ADC12_A_MEMORY_1 +//! - \b ADC12_A_MEMORY_2 +//! - \b ADC12_A_MEMORY_3 +//! - \b ADC12_A_MEMORY_4 +//! - \b ADC12_A_MEMORY_5 +//! - \b ADC12_A_MEMORY_6 +//! - \b ADC12_A_MEMORY_7 +//! - \b ADC12_A_MEMORY_8 +//! - \b ADC12_A_MEMORY_9 +//! - \b ADC12_A_MEMORY_10 +//! - \b ADC12_A_MEMORY_11 +//! - \b ADC12_A_MEMORY_12 +//! - \b ADC12_A_MEMORY_13 +//! - \b ADC12_A_MEMORY_14 +//! - \b ADC12_A_MEMORY_15 +//! +//! \return address of the specified memory buffer +// +//***************************************************************************** +uint32_t ADC12_A_getMemoryAddressForDMA(uint16_t baseAddress, + uint8_t memoryIndex) +{ + return baseAddress + (0x20 + (memoryIndex * 2)); +} + +//***************************************************************************** +// +//! \brief Returns the busy status of the ADC12_A core. +//! +//! Returns the status of the ADC core if there is a conversion currently +//! taking place. +//! +//! \param baseAddress is the base address of the ADC12_A module. +//! +//! \return One of the following: +//! - \b ADC12_A_NOTBUSY +//! - \b ADC12_A_BUSY +//! \n indicating if a conversion is taking place +// +//***************************************************************************** +uint16_t ADC12_A_isBusy(uint16_t baseAddress) +{ + return HWREG8(baseAddress + OFS_ADC12CTL1_L) & ADC12BUSY; +} + + +#endif +//***************************************************************************** +// +//! Close the doxygen group for adc12_a_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/adc12_a.h b/source/driverlib/MSP430F5xx_6xx/adc12_a.h new file mode 100644 index 0000000..fc7e51c --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/adc12_a.h @@ -0,0 +1,436 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// adc12_a.h - Driver for the ADC12_A Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_ADC12_A_H__ +#define __MSP430WARE_ADC12_A_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_ADC12_PLUS__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//****************************************************************************** +// +// The following is a struct that is passed to ADC12_A_configureMemory() +// +//****************************************************************************** +typedef struct ADC12_A_configureMemoryParam { + uint8_t memoryBufferControlIndex; + uint8_t inputSourceSelect; + uint8_t positiveRefVoltageSourceSelect; + uint8_t negativeRefVoltageSourceSelect; + uint8_t endOfSequence; +} ADC12_A_configureMemoryParam; + +//***************************************************************************** +// +// The following are values that can be passed to the clockSourceSelect +// parameter for functions: ADC12_A_init(). +// +//***************************************************************************** +#define ADC12_A_CLOCKSOURCE_ADC12OSC (ADC12SSEL_0) +#define ADC12_A_CLOCKSOURCE_ACLK (ADC12SSEL_1) +#define ADC12_A_CLOCKSOURCE_MCLK (ADC12SSEL_2) +#define ADC12_A_CLOCKSOURCE_SMCLK (ADC12SSEL_3) + +//***************************************************************************** +// +// The following are values that can be passed to the clockSourceDivider +// parameter for functions: ADC12_A_init(). +// +//***************************************************************************** +#define ADC12_A_CLOCKDIVIDER_1 (ADC12DIV_0) +#define ADC12_A_CLOCKDIVIDER_2 (ADC12DIV_1) +#define ADC12_A_CLOCKDIVIDER_3 (ADC12DIV_2) +#define ADC12_A_CLOCKDIVIDER_4 (ADC12DIV_3) +#define ADC12_A_CLOCKDIVIDER_5 (ADC12DIV_4) +#define ADC12_A_CLOCKDIVIDER_6 (ADC12DIV_5) +#define ADC12_A_CLOCKDIVIDER_7 (ADC12DIV_6) +#define ADC12_A_CLOCKDIVIDER_8 (ADC12DIV_7) +#define ADC12_A_CLOCKDIVIDER_12 (ADC12DIV_2 + ADC12PDIV) +#define ADC12_A_CLOCKDIVIDER_16 (ADC12DIV_3 + ADC12PDIV) +#define ADC12_A_CLOCKDIVIDER_20 (ADC12DIV_4 + ADC12PDIV) +#define ADC12_A_CLOCKDIVIDER_24 (ADC12DIV_5 + ADC12PDIV) +#define ADC12_A_CLOCKDIVIDER_28 (ADC12DIV_6 + ADC12PDIV) +#define ADC12_A_CLOCKDIVIDER_32 (ADC12DIV_7 + ADC12PDIV) + +//***************************************************************************** +// +// The following are values that can be passed to the +// sampleHoldSignalSourceSelect parameter for functions: ADC12_A_init(). +// +//***************************************************************************** +#define ADC12_A_SAMPLEHOLDSOURCE_SC (ADC12SHS_0) +#define ADC12_A_SAMPLEHOLDSOURCE_1 (ADC12SHS_1) +#define ADC12_A_SAMPLEHOLDSOURCE_2 (ADC12SHS_2) +#define ADC12_A_SAMPLEHOLDSOURCE_3 (ADC12SHS_3) + +//***************************************************************************** +// +// The following are values that can be passed to the clockCycleHoldCountLowMem +// parameter for functions: ADC12_A_setupSamplingTimer(); the +// clockCycleHoldCountHighMem parameter for functions: +// ADC12_A_setupSamplingTimer(). +// +//***************************************************************************** +#define ADC12_A_CYCLEHOLD_4_CYCLES (ADC12SHT0_0) +#define ADC12_A_CYCLEHOLD_8_CYCLES (ADC12SHT0_1) +#define ADC12_A_CYCLEHOLD_16_CYCLES (ADC12SHT0_2) +#define ADC12_A_CYCLEHOLD_32_CYCLES (ADC12SHT0_3) +#define ADC12_A_CYCLEHOLD_64_CYCLES (ADC12SHT0_4) +#define ADC12_A_CYCLEHOLD_96_CYCLES (ADC12SHT0_5) +#define ADC12_A_CYCLEHOLD_128_CYCLES (ADC12SHT0_6) +#define ADC12_A_CYCLEHOLD_192_CYCLES (ADC12SHT0_7) +#define ADC12_A_CYCLEHOLD_256_CYCLES (ADC12SHT0_8) +#define ADC12_A_CYCLEHOLD_384_CYCLES (ADC12SHT0_9) +#define ADC12_A_CYCLEHOLD_512_CYCLES (ADC12SHT0_10) +#define ADC12_A_CYCLEHOLD_768_CYCLES (ADC12SHT0_11) +#define ADC12_A_CYCLEHOLD_1024_CYCLES (ADC12SHT0_12) + +//***************************************************************************** +// +// The following are values that can be passed to the multipleSamplesEnabled +// parameter for functions: ADC12_A_setupSamplingTimer(). +// +//***************************************************************************** +#define ADC12_A_MULTIPLESAMPLESDISABLE (!(ADC12MSC)) +#define ADC12_A_MULTIPLESAMPLESENABLE (ADC12MSC) + +//***************************************************************************** +// +// The following are values that can be passed to the +// positiveRefVoltageSourceSelect parameter for functions: +// ADC12_A_memoryConfigure(). +// +//***************************************************************************** +#define ADC12_A_VREFPOS_AVCC (!(ADC12SREF0 + ADC12SREF1)) +#define ADC12_A_VREFPOS_EXT (ADC12SREF1) +#define ADC12_A_VREFPOS_INT (ADC12SREF0) + +//***************************************************************************** +// +// The following are values that can be passed to the +// negativeRefVoltageSourceSelect parameter for functions: +// ADC12_A_memoryConfigure(). +// +//***************************************************************************** +#define ADC12_A_VREFNEG_AVSS (!(ADC12SREF2)) +#define ADC12_A_VREFNEG_EXT (ADC12SREF2) + +//***************************************************************************** +// +// The following are values that can be passed to the endOfSequence parameter +// for functions: ADC12_A_memoryConfigure(). +// +//***************************************************************************** +#define ADC12_A_NOTENDOFSEQUENCE (!(ADC12EOS)) +#define ADC12_A_ENDOFSEQUENCE (ADC12EOS) + +//***************************************************************************** +// +// The following are values that can be passed to the inputSourceSelect +// parameter for functions: ADC12_A_memoryConfigure(). +// +//***************************************************************************** +#define ADC12_A_INPUT_A0 (ADC12INCH_0) +#define ADC12_A_INPUT_A1 (ADC12INCH_1) +#define ADC12_A_INPUT_A2 (ADC12INCH_2) +#define ADC12_A_INPUT_A3 (ADC12INCH_3) +#define ADC12_A_INPUT_A4 (ADC12INCH_4) +#define ADC12_A_INPUT_A5 (ADC12INCH_5) +#define ADC12_A_INPUT_A6 (ADC12INCH_6) +#define ADC12_A_INPUT_A7 (ADC12INCH_7) +#define ADC12_A_INPUT_A8 (ADC12INCH_8) +#define ADC12_A_INPUT_A9 (ADC12INCH_9) +#define ADC12_A_INPUT_TEMPSENSOR (ADC12INCH_10) +#define ADC12_A_INPUT_BATTERYMONITOR (ADC12INCH_11) +#define ADC12_A_INPUT_A12 (ADC12INCH_12) +#define ADC12_A_INPUT_A13 (ADC12INCH_13) +#define ADC12_A_INPUT_A14 (ADC12INCH_14) +#define ADC12_A_INPUT_A15 (ADC12INCH_15) + +//***************************************************************************** +// +// The following are values that can be passed to the startingMemoryBufferIndex +// parameter for functions: ADC12_A_startConversion(); the memoryIndex +// parameter for functions: ADC12_A_getMemoryAddressForDMA(); the +// memoryBufferControlIndex parameter for functions: ADC12_A_memoryConfigure(); +// the memoryBufferIndex parameter for functions: ADC12_A_getResults(). +// +//***************************************************************************** +#define ADC12_A_MEMORY_0 (0x0) +#define ADC12_A_MEMORY_1 (0x1) +#define ADC12_A_MEMORY_2 (0x2) +#define ADC12_A_MEMORY_3 (0x3) +#define ADC12_A_MEMORY_4 (0x4) +#define ADC12_A_MEMORY_5 (0x5) +#define ADC12_A_MEMORY_6 (0x6) +#define ADC12_A_MEMORY_7 (0x7) +#define ADC12_A_MEMORY_8 (0x8) +#define ADC12_A_MEMORY_9 (0x9) +#define ADC12_A_MEMORY_10 (0xA) +#define ADC12_A_MEMORY_11 (0xB) +#define ADC12_A_MEMORY_12 (0xC) +#define ADC12_A_MEMORY_13 (0xD) +#define ADC12_A_MEMORY_14 (0xE) +#define ADC12_A_MEMORY_15 (0xF) + +//***************************************************************************** +// +// The following are values that can be passed to the memoryInterruptFlagMask +// parameter for functions: ADC12_A_clearInterrupt(), and +// ADC12_A_getInterruptStatus(). +// +//***************************************************************************** +#define ADC12_A_IFG0 (ADC12IFG0) +#define ADC12_A_IFG1 (ADC12IFG1) +#define ADC12_A_IFG2 (ADC12IFG2) +#define ADC12_A_IFG3 (ADC12IFG3) +#define ADC12_A_IFG4 (ADC12IFG4) +#define ADC12_A_IFG5 (ADC12IFG5) +#define ADC12_A_IFG6 (ADC12IFG6) +#define ADC12_A_IFG7 (ADC12IFG7) +#define ADC12_A_IFG8 (ADC12IFG8) +#define ADC12_A_IFG9 (ADC12IFG9) +#define ADC12_A_IFG10 (ADC12IFG10) +#define ADC12_A_IFG11 (ADC12IFG11) +#define ADC12_A_IFG12 (ADC12IFG12) +#define ADC12_A_IFG13 (ADC12IFG13) +#define ADC12_A_IFG14 (ADC12IFG14) +#define ADC12_A_IFG15 (ADC12IFG15) + +//***************************************************************************** +// +// The following are values that can be passed to the +// conversionSequenceModeSelect parameter for functions: +// ADC12_A_startConversion(). +// +//***************************************************************************** +#define ADC12_A_SINGLECHANNEL (ADC12CONSEQ_0) +#define ADC12_A_SEQOFCHANNELS (ADC12CONSEQ_1) +#define ADC12_A_REPEATED_SINGLECHANNEL (ADC12CONSEQ_2) +#define ADC12_A_REPEATED_SEQOFCHANNELS (ADC12CONSEQ_3) + +//***************************************************************************** +// +// The following are values that can be passed to the preempt parameter for +// functions: ADC12_A_disableConversions(). +// +//***************************************************************************** +#define ADC12_A_COMPLETECONVERSION false +#define ADC12_A_PREEMPTCONVERSION true + +//***************************************************************************** +// +// The following are values that can be passed to the resolutionSelect +// parameter for functions: ADC12_A_setResolution(). +// +//***************************************************************************** +#define ADC12_A_RESOLUTION_8BIT (ADC12RES_0) +#define ADC12_A_RESOLUTION_10BIT (ADC12RES_1) +#define ADC12_A_RESOLUTION_12BIT (ADC12RES_2) + +//***************************************************************************** +// +// The following are values that can be passed to the invertedSignal parameter +// for functions: ADC12_A_setSampleHoldSignalInversion(). +// +//***************************************************************************** +#define ADC12_A_NONINVERTEDSIGNAL (!(ADC12ISSH)) +#define ADC12_A_INVERTEDSIGNAL (ADC12ISSH) + +//***************************************************************************** +// +// The following are values that can be passed to the readBackFormat parameter +// for functions: ADC12_A_setDataReadBackFormat(). +// +//***************************************************************************** +#define ADC12_A_UNSIGNED_BINARY (!(ADC12DF)) +#define ADC12_A_SIGNED_2SCOMPLEMENT (ADC12DF) + +//***************************************************************************** +// +// The following are values that can be passed to the samplingRateSelect +// parameter for functions: ADC12_A_setReferenceBufferSamplingRate(). +// +//***************************************************************************** +#define ADC12_A_MAXSAMPLINGRATE_200KSPS (!(ADC12SR)) +#define ADC12_A_MAXSAMPLINGRATE_50KSPS (ADC12SR) + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the ADC12_A_isBusy() function. +// +//***************************************************************************** +#define ADC12_A_NOTBUSY 0x00 +#define ADC12_A_BUSY ADC12BUSY + +//***************************************************************************** +// +// The following are values that can be passed to the interruptMask parameter +// for functions: ADC12_A_enableInterrupt(), and ADC12_A_disableInterrupt(). +// +//***************************************************************************** +#define ADC12_A_IE0 (ADC12IE0) +#define ADC12_A_IE1 (ADC12IE1) +#define ADC12_A_IE2 (ADC12IE2) +#define ADC12_A_IE3 (ADC12IE3) +#define ADC12_A_IE4 (ADC12IE4) +#define ADC12_A_IE5 (ADC12IE5) +#define ADC12_A_IE6 (ADC12IE6) +#define ADC12_A_IE7 (ADC12IE7) +#define ADC12_A_IE8 (ADC12IE8) +#define ADC12_A_IE9 (ADC12IE9) +#define ADC12_A_IE10 (ADC12IE10) +#define ADC12_A_IE11 (ADC12IE11) +#define ADC12_A_IE12 (ADC12IE12) +#define ADC12_A_IE13 (ADC12IE13) +#define ADC12_A_IE14 (ADC12IE14) +#define ADC12_A_IE15 (ADC12IE15) +#define ADC12_A_OVERFLOW_IE ((uint32_t)ADC12OVIE << 16) +#define ADC12_A_CONVERSION_TIME_OVERFLOW_IE ((uint32_t)ADC12TOVIE << 16) + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern bool ADC12_A_init(uint16_t baseAddress, + uint16_t sampleHoldSignalSourceSelect, + uint8_t clockSourceSelect, + uint16_t clockSourceDivider); + +extern void ADC12_A_enable(uint16_t baseAddress); + +extern void ADC12_A_disable(uint16_t baseAddress); + +extern void ADC12_A_setupSamplingTimer(uint16_t baseAddress, + uint16_t clockCycleHoldCountLowMem, + uint16_t clockCycleHoldCountHighMem, + uint16_t multipleSamplesEnabled); + +extern void ADC12_A_disableSamplingTimer(uint16_t baseAddress); + +extern void ADC12_A_configureMemory(uint16_t baseAddress, + ADC12_A_configureMemoryParam *param); + +extern void ADC12_A_enableInterrupt(uint16_t baseAddress, + uint32_t interruptMask); + +extern void ADC12_A_disableInterrupt(uint16_t baseAddress, + uint32_t interruptMask); + +extern void ADC12_A_clearInterrupt(uint16_t baseAddress, + uint16_t memoryInterruptFlagMask); + +extern uint8_t ADC12_A_getInterruptStatus(uint16_t baseAddress, + uint16_t memoryInterruptFlagMask); + +extern void ADC12_A_startConversion(uint16_t baseAddress, + uint16_t startingMemoryBufferIndex, + uint8_t conversionSequenceModeSelect); + +extern void ADC12_A_disableConversions(uint16_t baseAddress, + bool preempt); + +extern uint16_t ADC12_A_getResults(uint16_t baseAddress, + uint8_t memoryBufferIndex); + +extern void ADC12_A_setResolution(uint16_t baseAddress, + uint8_t resolutionSelect); + +extern void ADC12_A_setSampleHoldSignalInversion(uint16_t baseAddress, + uint16_t invertedSignal); + +extern void ADC12_A_setDataReadBackFormat(uint16_t baseAddress, + uint8_t readBackFormat); + +extern void ADC12_A_enableReferenceBurst(uint16_t baseAddress); + +extern void ADC12_A_disableReferenceBurst(uint16_t baseAddress); + +extern void ADC12_A_setReferenceBufferSamplingRate(uint16_t baseAddress, + uint8_t samplingRateSelect); + +extern uint32_t ADC12_A_getMemoryAddressForDMA(uint16_t baseAddress, + uint8_t memoryIndex); + +extern uint16_t ADC12_A_isBusy(uint16_t baseAddress); + +//***************************************************************************** +// +// The following values are deprecated values. Please refer to the documenation +// for the correct values to use. +// +//***************************************************************************** +#define ADC12TOVIE0 ADC12_A_OVERFLOW_IE +#define ADC12OVIE0 ADC12_A_CONVERSION_TIME_OVERFLOW_IE + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +extern void ADC12_A_memoryConfigure(uint16_t baseAddress, + uint8_t memoryBufferControlIndex, + uint8_t inputSourceSelect, + uint8_t positiveRefVoltageSourceSelect, + uint8_t negativeRefVoltageSourceSelect, + uint8_t endOfSequence); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_ADC12_A_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/aes.c b/source/driverlib/MSP430F5xx_6xx/aes.c new file mode 100644 index 0000000..3a55270 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/aes.c @@ -0,0 +1,644 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// aes.c - Driver for the aes Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup aes_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_AES__ +#include "aes.h" + +#include + +//***************************************************************************** +// +//! \brief Loads a 128 bit cipher key to AES module. +//! +//! This function loads a 128 bit cipher key to AES module. +//! +//! \param baseAddress is the base address of the AES module. +//! \param CipherKey is a pointer to an uint8_t array with a length of 16 bytes +//! that contains a 128 bit cipher key. +//! +//! \return STATUS_SUCCESS +// +//***************************************************************************** +uint8_t AES_setCipherKey(uint16_t baseAddress, + const uint8_t * CipherKey + ) +{ + uint8_t i = 0; + uint16_t tempVariable = 0; + + // Wait until AES accelerator is busy + while (AESBUSY == (HWREG16(baseAddress + OFS_AESASTAT) & AESBUSY) ) ; + + for (i = 0; i < 16; i = i + 2) { + tempVariable = (uint16_t)(CipherKey[i]); + tempVariable = tempVariable | ((uint16_t)(CipherKey[i + 1]) << 8); + HWREG16(baseAddress + OFS_AESAKEY) = tempVariable; + } + + // Wait until key is written + while (0x00 == (HWREG16(baseAddress + OFS_AESASTAT) & AESKEYWR )) ; + + return STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! \brief Encrypts a block of data using the AES module. +//! +//! The cipher key that is used for encryption should be loaded in advance by +//! using function \b AES_setCipherKey() +//! +//! \param baseAddress is the base address of the AES module. +//! \param Data is a pointer to an uint8_t array with a length of 16 bytes that +//! contains data to be encrypted. +//! \param encryptedData is a pointer to an uint8_t array with a length of 16 +//! bytes in that the encrypted data will be written. +//! +//! \return STATUS_SUCCESS +// +//***************************************************************************** +uint8_t AES_encryptData(uint16_t baseAddress, + const uint8_t * Data, + uint8_t * encryptedData) +{ + uint8_t i; + uint16_t tempData = 0; + uint16_t tempVariable = 0; + + // Set module to encrypt mode + HWREG16(baseAddress + OFS_AESACTL0) &= ~AESOP_3; + + + // Write data to encrypt to module + for (i = 0; i < 16; i = i + 2) { + + tempVariable = (uint16_t)(Data[i]); + tempVariable = tempVariable | ((uint16_t)(Data[i + 1]) << 8); + HWREG16(baseAddress + OFS_AESADIN) = tempVariable; + } + + // Key that is already written shall be used + // Encryption is initialized by setting AESKEYWR to 1 + HWREG16(baseAddress + OFS_AESASTAT) |= AESKEYWR; + + // Wait unit finished ~167 MCLK + while (AESBUSY == (HWREG16(baseAddress + OFS_AESASTAT) & AESBUSY) ) ; + + // Write encrypted data back to variable + for (i = 0; i < 16; i = i + 2) { + tempData = HWREG16(baseAddress + OFS_AESADOUT); + *(encryptedData + i) = (uint8_t)tempData; + *(encryptedData + i + 1) = (uint8_t)(tempData >> 8); + + } + + return STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! \brief Decrypts a block of data using the AES module. +//! +//! This function requires a pre-generated decryption key. A key can be loaded +//! and pre-generated by using function \b AES_startSetDecipherKey() or \b +//! AES_setDecipherKey(). The decryption takes 167 MCLK. +//! +//! \param baseAddress is the base address of the AES module. +//! \param Data is a pointer to an uint8_t array with a length of 16 bytes that +//! contains encrypted data to be decrypted. +//! \param decryptedData is a pointer to an uint8_t array with a length of 16 +//! bytes in that the decrypted data will be written. +//! +//! \return STATUS_SUCCESS +// +//***************************************************************************** +uint8_t AES_decryptData(uint16_t baseAddress, + const uint8_t * Data, + uint8_t * decryptedData) +{ + uint8_t i; + uint16_t tempData = 0; + uint16_t tempVariable = 0; + + // Set module to decrypt mode + HWREG16(baseAddress + OFS_AESACTL0) |= (AESOP_3); + + // Write data to decrypt to module + for (i = 0; i < 16; i = i + 2) { + tempVariable = (uint16_t)(Data[i + 1] << 8); + tempVariable = tempVariable | ((uint16_t)(Data[i])); + HWREG16(baseAddress + OFS_AESADIN) = tempVariable; + } + + // Key that is already written shall be used + // Now decryption starts + HWREG16(baseAddress + OFS_AESASTAT) |= AESKEYWR; + + // Wait unit finished ~167 MCLK + while (AESBUSY == (HWREG16(baseAddress + OFS_AESASTAT) & AESBUSY )) ; + + // Write encrypted data back to variable + for (i = 0; i < 16; i = i + 2) { + tempData = HWREG16(baseAddress + OFS_AESADOUT); + *(decryptedData + i ) = (uint8_t)tempData; + *(decryptedData + i + 1) = (uint8_t)(tempData >> 8); + } + + return STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! \brief Sets the decipher key The API +//! +//! The API \b AES_startSetDecipherKey() or \b AES_setDecipherKey() must be +//! invoked before invoking \b AES_setDecipherKey(). +//! +//! \param baseAddress is the base address of the AES module. +//! \param CipherKey is a pointer to an uint8_t array with a length of 16 bytes +//! that contains the initial AES key. +//! +//! \return STATUS_SUCCESS +// +//***************************************************************************** +uint8_t AES_setDecipherKey(uint16_t baseAddress, + const uint8_t * CipherKey) +{ + uint8_t i; + uint16_t tempVariable = 0; + + // Set module to decrypt mode + HWREG16(baseAddress + OFS_AESACTL0) &= ~(AESOP0); + HWREG16(baseAddress + OFS_AESACTL0) |= AESOP1; + + // Write cipher key to key register + for (i = 0; i < 16; i = i + 2) { + tempVariable = (uint16_t)(CipherKey[i]); + tempVariable = tempVariable | ((uint16_t)(CipherKey[i + 1]) << 8); + HWREG16(baseAddress + OFS_AESAKEY) = tempVariable; + } + + // Wait until key is processed ~52 MCLK + while ((HWREG16(baseAddress + OFS_AESASTAT) & AESBUSY) == AESBUSY) ; + + return STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! \brief Clears the AES ready interrupt flag. +//! +//! This function clears the AES ready interrupt flag. This flag is +//! automatically cleared when AESADOUT is read, or when AESAKEY or AESADIN is +//! written. This function should be used when the flag needs to be reset and +//! it has not been automatically cleared by one of the previous actions. +//! +//! \param baseAddress is the base address of the AES module. +//! +//! Modified bits are \b AESRDYIFG of \b AESACTL0 register. +//! +//! \return None +// +//***************************************************************************** +void AES_clearInterruptFlag(uint16_t baseAddress ) +{ + HWREG8(baseAddress + OFS_AESACTL0) &= ~AESRDYIFG; +} + +//***************************************************************************** +// +//! \brief Gets the AES ready interrupt flag status. +//! +//! This function checks the AES ready interrupt flag. This flag is +//! automatically cleared when AESADOUT is read, or when AESAKEY or AESADIN is +//! written. This function can be used to confirm that this has been done. +//! +//! \param baseAddress is the base address of the AES module. +//! +//! \return uint32_t - AES_READY_INTERRUPT or 0x00. +// +//***************************************************************************** +uint32_t AES_getInterruptFlagStatus(uint16_t baseAddress) +{ + return (HWREG8(baseAddress + OFS_AESACTL0) & AESRDYIFG) << 0x04; +} + +//***************************************************************************** +// +//! \brief Enables AES ready interrupt. +//! +//! Enables AES ready interrupt. This interrupt is reset by a PUC, but not +//! reset by AES_reset. Does not clear interrupt flags. +//! +//! \param baseAddress is the base address of the AES module. +//! +//! Modified bits are \b AESRDYIE of \b AESACTL0 register. +//! +//! \return None +// +//***************************************************************************** +void AES_enableInterrupt(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_AESACTL0) |= AESRDYIE; +} + +//***************************************************************************** +// +//! \brief Disables AES ready interrupt. +//! +//! Disables AES ready interrupt. This interrupt is reset by a PUC, but not +//! reset by AES_reset. +//! +//! \param baseAddress is the base address of the AES module. +//! +//! Modified bits are \b AESRDYIE of \b AESACTL0 register. +//! +//! \return None +// +//***************************************************************************** +void AES_disableInterrupt(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_AESACTL0) &= ~AESRDYIE; +} + +//***************************************************************************** +// +//! \brief Resets AES Module immediately. +//! +//! This function performs a software reset on the AES Module, note that this +//! does not affect the AES ready interrupt. +//! +//! \param baseAddress is the base address of the AES module. +//! +//! Modified bits are \b AESSWRST of \b AESACTL0 register. +//! +//! \return None +// +//***************************************************************************** +void AES_reset(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_AESACTL0) |= AESSWRST; +} + +//***************************************************************************** +// +//! \brief Starts an encryption process on the AES module. +//! +//! This is the non-blocking equivalent of AES_encryptData(). The cipher key +//! that is used for decryption should be loaded in advance by using function +//! \b AES_setCipherKey(). It is recommended to use interrupt to check for +//! procedure completion then using AES_getDataOut() API to retrieve the +//! encrypted data. +//! +//! \param baseAddress is the base address of the AES module. +//! \param Data is a pointer to an uint8_t array with a length of 16 bytes that +//! contains data to be encrypted. +//! \param encryptedData is a pointer to an uint8_t array with a length of 16 +//! bytes in that the encrypted data will be written. +//! +//! \return STATUS_SUCCESS +// +//***************************************************************************** +uint8_t AES_startEncryptData(uint16_t baseAddress, + const uint8_t * Data, + uint8_t * encryptedData) +{ + uint8_t i; + uint16_t tempVariable = 0; + + // Set module to encrypt mode + HWREG16(baseAddress + OFS_AESACTL0) &= ~AESOP_3; + + + // Write data to encrypt to module + for (i = 0; i < 16; i = i + 2) { + tempVariable = (uint16_t)(Data[i]); + tempVariable = tempVariable | ((uint16_t)(Data[i + 1]) << 8); + HWREG16(baseAddress + OFS_AESADIN) = tempVariable; + } + + // Key that is already written shall be used + // Encryption is initialized by setting AESKEYWR to 1 + HWREG16(baseAddress + OFS_AESASTAT) |= AESKEYWR; + + return STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! \brief Decrypts a block of data using the AES module. +//! +//! This is the non-blocking equivalent of AES_decryptData(). This function +//! requires a pre-generated decryption key. A key can be loaded and pre- +//! generated by using function \b AES_setDecipherKey() or \b +//! AES_startSetDecipherKey(). The decryption takes 167 MCLK. It is recommended +//! to use interrupt to check for procedure completion then using +//! AES_getDataOut() API to retrieve the decrypted data. +//! +//! \param baseAddress is the base address of the AES module. +//! \param Data is a pointer to an uint8_t array with a length of 16 bytes that +//! contains encrypted data to be decrypted. +//! +//! \return STATUS_SUCCESS +// +//***************************************************************************** +uint8_t AES_startDecryptData(uint16_t baseAddress, + const uint8_t * Data) +{ + uint8_t i; + uint16_t tempVariable = 0; + + // Set module to decrypt mode + HWREG16(baseAddress + OFS_AESACTL0) |= (AESOP_3); + + // Write data to decrypt to module + for (i = 0; i < 16; i = i + 2) { + tempVariable = (uint16_t)(Data[i + 1] << 8); + tempVariable = tempVariable | ((uint16_t)(Data[i])); + HWREG16(baseAddress + OFS_AESADIN) = tempVariable; + } + + // Key that is already written shall be used + // Now decryption starts + HWREG16(baseAddress + OFS_AESASTAT) |= AESKEYWR; + + return STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! \brief Loads the decipher key. +//! +//! This is the non-blocking equivalent of AES_setDecipherKey(). The API \b +//! AES_startSetDecipherKey() or \b AES_setDecipherKey() must be invoked before +//! invoking \b AES_startSetDecipherKey(). +//! +//! \param baseAddress is the base address of the AES module. +//! \param CipherKey is a pointer to an uint8_t array with a length of 16 bytes +//! that contains the initial AES key. +//! +//! \return STATUS_SUCCESS +// +//***************************************************************************** +uint8_t AES_startSetDecipherKey(uint16_t baseAddress, + const uint8_t * CipherKey) +{ + uint8_t i; + uint16_t tempVariable = 0; + + HWREG16(baseAddress + OFS_AESACTL0) &= ~(AESOP0); + HWREG16(baseAddress + OFS_AESACTL0) |= AESOP1; + + // Write cipher key to key register + for (i = 0; i < 16; i = i + 2) { + tempVariable = (uint16_t)(CipherKey[i]); + tempVariable = tempVariable | ((uint16_t)(CipherKey[i + 1]) << 8); + HWREG16(baseAddress + OFS_AESAKEY) = tempVariable; + } + + return STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! \brief Reads back the output data from AES module. +//! +//! This function is meant to use after an encryption or decryption process +//! that was started and finished by initiating an interrupt by use of the \b +//! AES_startEncryptData() or \b AES_startDecryptData() functions. +//! +//! \param baseAddress is the base address of the AES module. +//! \param OutputData is a pointer to an uint8_t array with a length of 16 +//! bytes in which the output data of the AES module is available. If +//! AES module is busy returns NULL. +//! +//! \return STATUS_SUCCESS if AES is not busy, STATUS_FAIL if it is busy +// +//***************************************************************************** +uint8_t AES_getDataOut(uint16_t baseAddress, + uint8_t *OutputData + ) +{ + uint8_t i; + uint16_t tempData = 0; + + // If module is busy, exit and return failure + if ( AESBUSY == (HWREG16(baseAddress + OFS_AESASTAT) & AESBUSY)) + return STATUS_FAIL; + + // Write encrypted data back to variable + for (i = 0; i < 16; i = i + 2) { + tempData = HWREG16(baseAddress + OFS_AESADOUT); + *(OutputData + i) = (uint8_t)tempData; + *(OutputData + i + 1) = (uint8_t)(tempData >> 8); + } + + return STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! \brief Gets the AES module busy status. +//! +//! Gets the AES module busy status. If a key or data are written while the AES +//! module is busy, an error flag will be thrown. +//! +//! \param baseAddress is the base address of the AES module. +//! +//! \return One of the following: +//! - \b AES_BUSY +//! - \b AES_NOT_BUSY +//! \n indicating if encryption/decryption/key generation is taking +//! place +// +//***************************************************************************** +uint8_t AES_isBusy(uint16_t baseAddress) +{ + return HWREG16(baseAddress + OFS_AESASTAT) & AESBUSY; +} + +//***************************************************************************** +// +//! \brief Clears the AES error flag. +//! +//! Clears the AES error flag that results from a key or data being written +//! while the AES module is busy. Modified bit is AESERRFG of AESACTL0 +//! register. +//! +//! \param baseAddress is the base address of the AES module. +//! +//! Modified bits are \b AESERRFG of \b AESACTL0 register. +//! +//! \return None +// +//***************************************************************************** +void AES_clearErrorFlag(uint16_t baseAddress ) +{ + HWREG8(baseAddress + OFS_AESACTL0) &= ~AESERRFG; +} + +//***************************************************************************** +// +//! \brief Gets the AES error flag status. +//! +//! Checks the AES error flag that results from a key or data being written +//! while the AES module is busy. If the flag is set, it needs to be cleared +//! using AES_clearErrorFlag. +//! +//! \param baseAddress is the base address of the AES module. +//! +//! \return One of the following: +//! - \b AES_ERROR_OCCURRED +//! - \b AES_NO_ERROR +//! \n indicating if AESAKEY or AESADIN were written while an AES +//! operation was in progress +// +//***************************************************************************** +uint32_t AES_getErrorFlagStatus(uint16_t baseAddress) +{ + return HWREG8(baseAddress + OFS_AESACTL0) & AESERRFG; +} + +//***************************************************************************** +// +//! \brief DEPRECATED Starts an decryption process on the AES module. +//! +//! This is the non-blocking equivalent of AES_decryptDataUsingEncryptionKey(). +//! This function can be used to decrypt data by using the same key as used for +//! a previous performed encryption. The decryption takes 214 MCLK. +//! +//! \param baseAddress is the base address of the AES module. +//! \param Data is a pointer to an uint8_t array with a length of 16 bytes that +//! contains encrypted data to be decrypted. +//! +//! \return STATUS_SUCCESS +// +//***************************************************************************** +uint8_t AES_startDecryptDataUsingEncryptionKey( + uint16_t baseAddress, + const uint8_t * Data) +{ + uint8_t i; + uint16_t tempVariable = 0; + + // Set module to decrypt mode + HWREG16(baseAddress + OFS_AESACTL0) &= ~(AESOP1); + HWREG16(baseAddress + OFS_AESACTL0) |= AESOP0; + + // Write data to decrypt to module + for (i = 0; i < 16; i = i + 2) { + tempVariable = (uint16_t)(Data[i + 1] << 8); + tempVariable = tempVariable | ((uint16_t)(Data[i])); + HWREG16(baseAddress + OFS_AESADIN) = tempVariable; + } + + // Key that is already written shall be used + // Now decryption starts + HWREG16(baseAddress + OFS_AESASTAT) |= AESKEYWR; + + return STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! \brief DEPRECATED Decrypts a block of data using the AES module. +//! +//! This function can be used to decrypt data by using the same key as used for +//! a previous performed encryption. The decryption takes 214 MCLK. +//! +//! \param baseAddress is the base address of the AES module. +//! \param Data is a pointer to an uint8_t array with a length of 16 bytes that +//! contains encrypted data to be decrypted. +//! \param decryptedData is a pointer to an uint8_t array with a length of 16 +//! bytes in that the decrypted data will be written. +//! +//! \return STATUS_SUCCESS +// +//***************************************************************************** +uint8_t AES_decryptDataUsingEncryptionKey(uint16_t baseAddress, + const uint8_t * Data, + uint8_t * decryptedData) +{ + uint8_t i; + uint16_t tempData = 0; + uint16_t tempVariable = 0; + + // Set module to decrypt mode + HWREG16(baseAddress + OFS_AESACTL0) &= ~(AESOP1); + HWREG16(baseAddress + OFS_AESACTL0) |= AESOP0; + + // Write data to decrypt to module + for (i = 0; i < 16; i = i + 2) { + tempVariable = (uint16_t)(Data[i + 1] << 8); + tempVariable = tempVariable | ((uint16_t)(Data[i])); + HWREG16(baseAddress + OFS_AESADIN) = tempVariable; + } + + // Key that is already written shall be used + // Now decryption starts + HWREG16(baseAddress + OFS_AESASTAT) |= AESKEYWR; + + // Wait unit finished ~214 MCLK + while (AESBUSY == (HWREG16(baseAddress + OFS_AESASTAT) & AESBUSY) ) ; + + // Write encrypted data back to variable + for (i = 0; i < 16; i = i + 2) { + tempData = HWREG16(baseAddress + OFS_AESADOUT); + *(decryptedData + i ) = (uint8_t)tempData; + *(decryptedData + i + 1) = (uint8_t)(tempData >> 8); + } + + return STATUS_SUCCESS; +} + +#endif +//***************************************************************************** +// +//! Close the doxygen group for aes_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/aes.h b/source/driverlib/MSP430F5xx_6xx/aes.h new file mode 100644 index 0000000..3a13595 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/aes.h @@ -0,0 +1,147 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// aes.h - Driver for the AES Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_AES_H__ +#define __MSP430WARE_AES_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_AES__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the AES_isBusy() function. +// +//***************************************************************************** +#define AES_BUSY AESBUSY +#define AES_NOT_BUSY 0x00 + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the AES_getErrorFlagStatus() function. +// +//***************************************************************************** +#define AES_ERROR_OCCURRED AESERRFG +#define AES_NO_ERROR 0x00 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern uint8_t AES_setCipherKey(uint16_t baseAddress, + const uint8_t *CipherKey); + +extern uint8_t AES_encryptData(uint16_t baseAddress, + const uint8_t *Data, + uint8_t *encryptedData); + +extern uint8_t AES_decryptData(uint16_t baseAddress, + const uint8_t *Data, + uint8_t *decryptedData); + +extern uint8_t AES_setDecipherKey(uint16_t baseAddress, + const uint8_t *CipherKey); + +extern void AES_clearInterruptFlag(uint16_t baseAddress); + +extern uint32_t AES_getInterruptFlagStatus(uint16_t baseAddress); + +extern void AES_enableInterrupt(uint16_t baseAddress); + +extern void AES_disableInterrupt(uint16_t baseAddress); + +extern void AES_reset(uint16_t baseAddress); + +extern uint8_t AES_startEncryptData(uint16_t baseAddress, + const uint8_t *Data, + uint8_t *encryptedData); + +extern uint8_t AES_startDecryptData(uint16_t baseAddress, + const uint8_t *Data); + +extern uint8_t AES_startSetDecipherKey(uint16_t baseAddress, + const uint8_t *CipherKey); + +extern uint8_t AES_getDataOut(uint16_t baseAddress, + uint8_t *OutputData); + +extern uint8_t AES_isBusy(uint16_t baseAddress); + +extern void AES_clearErrorFlag(uint16_t baseAddress); + +extern uint32_t AES_getErrorFlagStatus(uint16_t baseAddress); + +extern uint8_t AES_startDecryptDataUsingEncryptionKey(uint16_t baseAddress, + const uint8_t *Data); + +extern uint8_t AES_decryptDataUsingEncryptionKey(uint16_t baseAddress, + const uint8_t *Data, + uint8_t *decryptedData); + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +#define AES_startGenerateFirstRoundKey AES_startSetDecipherKey +#define AES_generateFirstRoundKey AES_setDecipherKey + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_AES_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/bak_batt.c b/source/driverlib/MSP430F5xx_6xx/bak_batt.c new file mode 100644 index 0000000..2448346 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/bak_batt.c @@ -0,0 +1,259 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// bak_batt.c - Driver for the bak_batt Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup bak_batt_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_BATTERY_CHARGER__ +#include "bak_batt.h" + +#include + +//***************************************************************************** +// +//! \brief Unlocks any pending backup input pins and RTC_B interrupts to be +//! serviced. +//! +//! This function unlocks the ability to view and service any pending backup +//! input pin interrupts, as well as pending RTC_B interrupts. The backup sub- +//! system can only be unlocked when the backup domain has settled, so this +//! function returns the status of the unlock bit after it has been to be +//! verified by user code. Please note, the backup sub-system should only be +//! unlocked after modifying the RTC_B registers. +//! +//! \param baseAddress is the base address of the BAK_BATT module. +//! +//! \return One of the following: +//! - \b BAK_BATT_UNLOCKFAILURE backup system has not yet settled +//! - \b BAK_BATT_UNLOCKSUCCESS successfully unlocked +//! \n indicating if the backup system has been successfully unlocked +// +//***************************************************************************** +uint16_t BAK_BATT_unlockBackupSubSystem(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_BAKCTL) &= ~(LOCKBAK); + return HWREG8(baseAddress + OFS_BAKCTL) & LOCKBAK; +} + +//***************************************************************************** +// +//! \brief Enables the backup supply to be measured by the ADC battery monitor +//! input. +//! +//! This function enables the backup supply signal to be monitored by the ADC +//! battery supply monitor input, to allow a measurement of the voltage from +//! the backup battery. +//! +//! \param baseAddress is the base address of the BAK_BATT module. +//! +//! \return None +// +//***************************************************************************** +void BAK_BATT_enableBackupSupplyToADC(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_BAKCTL) |= BAKADC; +} + +//***************************************************************************** +// +//! \brief Disables the backup supply input to the ADC module. +//! +//! This function disables the ability to monitor the backup supply voltage +//! from the ADC battery monitor input. +//! +//! \param baseAddress is the base address of the BAK_BATT module. +//! +//! \return None +// +//***************************************************************************** +void BAK_BATT_disableBackupSupplyToADC(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_BAKCTL) &= ~(BAKADC); +} + +//***************************************************************************** +// +//! \brief Manually switches to backup supply. +//! +//! This function uses software to manually switch to the backup battery +//! supply. Once this bit is set, it will be automatically reset by a POR and +//! the system returns to an automatic switch to backup supply. +//! +//! \param baseAddress is the base address of the BAK_BATT module. +//! +//! \return None +// +//***************************************************************************** +void BAK_BATT_manuallySwitchToBackupSupply(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_BAKCTL) |= BAKSW; +} + +//***************************************************************************** +// +//! \brief Disables backup battery system. +//! +//! This function disables the battery backup system from being used. The +//! battery backup system is re-enabled after a power cycle. +//! +//! \param baseAddress is the base address of the BAK_BATT module. +//! +//! \return None +// +//***************************************************************************** +void BAK_BATT_disable(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_BAKCTL) |= BAKDIS; +} + +//***************************************************************************** +// +//! \brief Initializes and enables the backup battery charger. +//! +//! This function initializes the backup battery charger with the selected +//! settings. +//! +//! \param baseAddress is the base address of the BAK_BATT module. +//! \param chargerEndVoltage is the maximum voltage to charge the backup +//! battery to. +//! Valid values are: +//! - \b BAK_BATT_CHARGERENDVOLTAGE_VCC - charges backup battery up to +//! Vcc +//! - \b BAK_BATT_CHARGERENDVOLTAGE2_7V - charges backup battery up to +//! 2.7V OR up to Vcc if Vcc is less than 2.7V. +//! \n Modified bits are \b BAKCHVx of \b BAKCHCTL register. +//! \param chargeCurrent is the maximum current to charge the backup battery +//! at. +//! Valid values are: +//! - \b BAK_BATT_CHARGECURRENT_5KOHM +//! - \b BAK_BATT_CHARGECURRENT_10KOHM +//! - \b BAK_BATT_CHARGECURRENT_20KOHM +//! \n Modified bits are \b BAKCHCx of \b BAKCHCTL register. +//! +//! \return None +// +//***************************************************************************** +void BAK_BATT_chargerInitAndEnable(uint16_t baseAddress, + uint8_t chargerEndVoltage, + uint8_t chargeCurrent) +{ + HWREG16(baseAddress + + OFS_BAKCHCTL) = CHPWD + chargerEndVoltage + chargeCurrent + CHEN; +} + +//***************************************************************************** +// +//! \brief Disables and resets backup battery charger settings. +//! +//! This function clears all backup battery charger settings and disables it. +//! To re-enable the charger, a call to BAK_BATT_chargerInitAndEnable() is +//! required. +//! +//! \param baseAddress is the base address of the BAK_BATT module. +//! +//! \return None +// +//***************************************************************************** +void BAK_BATT_disableCharger(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_BAKCHCTL) = CHPWD; +} + +//***************************************************************************** +// +//! \brief Sets data into the selected backup RAM space. +//! +//! This function sets the given 16-bit data into the selected backup RAM +//! space. +//! +//! \param baseAddress is the base address of the BAK_BATT module. +//! \param backupRAMSelect is the backup RAM space to set data into. +//! Valid values are: +//! - \b BAK_BATT_RAMSELECT_0 +//! - \b BAK_BATT_RAMSELECT_1 +//! - \b BAK_BATT_RAMSELECT_2 +//! - \b BAK_BATT_RAMSELECT_3 +//! \param data is the data to set into the selected backup RAM space. +//! +//! \return None +// +//***************************************************************************** +void BAK_BATT_setBackupRAMData(uint16_t baseAddress, + uint8_t backupRAMSelect, + uint16_t data) +{ + HWREG16(baseAddress + backupRAMSelect) = data; +} + +//***************************************************************************** +// +//! \brief Returns the data from the selected backup RAM space. +//! +//! This function returns the 16-bit data currently residing in the selected +//! backup RAM space. +//! +//! \param baseAddress is the base address of the BAK_BATT module. +//! \param backupRAMSelect is the backup RAM space to read out from. +//! Valid values are: +//! - \b BAK_BATT_RAMSELECT_0 +//! - \b BAK_BATT_RAMSELECT_1 +//! - \b BAK_BATT_RAMSELECT_2 +//! - \b BAK_BATT_RAMSELECT_3 +//! +//! \return Data residing in the selected backup RAM space. +// +//***************************************************************************** +uint16_t BAK_BATT_getBackupRAMData(uint16_t baseAddress, + uint8_t backupRAMSelect) +{ + return HWREG16(baseAddress + backupRAMSelect); +} + +#endif +//***************************************************************************** +// +//! Close the doxygen group for bak_batt_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/bak_batt.h b/source/driverlib/MSP430F5xx_6xx/bak_batt.h new file mode 100644 index 0000000..6e38f40 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/bak_batt.h @@ -0,0 +1,133 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// bak_batt.h - Driver for the BAK_BATT Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_BAK_BATT_H__ +#define __MSP430WARE_BAK_BATT_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_BATTERY_CHARGER__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the BAK_BATT_unlockBackupSubSystem() function. +// +//***************************************************************************** +#define BAK_BATT_UNLOCKFAILURE (LOCKBAK) +#define BAK_BATT_UNLOCKSUCCESS (0x0) + +//***************************************************************************** +// +// The following are values that can be passed to the chargerEndVoltage +// parameter for functions: BAK_BATT_chargerInitAndEnable(). +// +//***************************************************************************** +#define BAK_BATT_CHARGERENDVOLTAGE_VCC (BAKCHV0) +#define BAK_BATT_CHARGERENDVOLTAGE2_7V (BAKCHV1) + +//***************************************************************************** +// +// The following are values that can be passed to the chargeCurrent parameter +// for functions: BAK_BATT_chargerInitAndEnable(). +// +//***************************************************************************** +#define BAK_BATT_CHARGECURRENT_5KOHM (BAKCHC0) +#define BAK_BATT_CHARGECURRENT_10KOHM (BAKCHC1) +#define BAK_BATT_CHARGECURRENT_20KOHM (BAKCHC0 + BAKCHC1) + +//***************************************************************************** +// +// The following are values that can be passed to the backupRAMSelect parameter +// for functions: BAK_BATT_setBackupRAMData(), and BAK_BATT_getBackupRAMData(). +// +//***************************************************************************** +#define BAK_BATT_RAMSELECT_0 (0x0000) +#define BAK_BATT_RAMSELECT_1 (0x0002) +#define BAK_BATT_RAMSELECT_2 (0x0004) +#define BAK_BATT_RAMSELECT_3 (0x0006) + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern uint16_t BAK_BATT_unlockBackupSubSystem(uint16_t baseAddress); + +extern void BAK_BATT_enableBackupSupplyToADC(uint16_t baseAddress); + +extern void BAK_BATT_disableBackupSupplyToADC(uint16_t baseAddress); + +extern void BAK_BATT_manuallySwitchToBackupSupply(uint16_t baseAddress); + +extern void BAK_BATT_disable(uint16_t baseAddress); + +extern void BAK_BATT_chargerInitAndEnable(uint16_t baseAddress, + uint8_t chargerEndVoltage, + uint8_t chargeCurrent); + +extern void BAK_BATT_disableCharger(uint16_t baseAddress); + +extern void BAK_BATT_setBackupRAMData(uint16_t baseAddress, + uint8_t backupRAMSelect, + uint16_t data); + +extern uint16_t BAK_BATT_getBackupRAMData(uint16_t baseAddress, + uint8_t backupRAMSelect); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_BAK_BATT_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/comp_b.c b/source/driverlib/MSP430F5xx_6xx/comp_b.c new file mode 100644 index 0000000..881438e --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/comp_b.c @@ -0,0 +1,686 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// comp_b.c - Driver for the comp_b Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup comp_b_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_COMPB__ +#include "comp_b.h" + +#include + +//***************************************************************************** +// +//! \brief DEPRECATED - Initializes the COMP_B Module. +//! +//! Upon successful initialization of the COMP_B module, this function will +//! have reset all necessary register bits and set the given options in the +//! registers. To actually use the COMP_B module, the COMP_B_enable() function +//! must be explicitly called before use. If a Reference Voltage is set to a +//! terminal, the Voltage should be set using the COMP_B_setReferenceVoltage() +//! function. +//! +//! \param baseAddress is the base address of the COMP_B module. +//! \param positiveTerminalInput selects the input to the positive terminal. +//! Valid values are: +//! - \b COMP_B_INPUT0 [Default] +//! - \b COMP_B_INPUT1 +//! - \b COMP_B_INPUT2 +//! - \b COMP_B_INPUT3 +//! - \b COMP_B_INPUT4 +//! - \b COMP_B_INPUT5 +//! - \b COMP_B_INPUT6 +//! - \b COMP_B_INPUT7 +//! - \b COMP_B_INPUT8 +//! - \b COMP_B_INPUT9 +//! - \b COMP_B_INPUT10 +//! - \b COMP_B_INPUT11 +//! - \b COMP_B_INPUT12 +//! - \b COMP_B_INPUT13 +//! - \b COMP_B_INPUT14 +//! - \b COMP_B_INPUT15 +//! - \b COMP_B_VREF +//! \n Modified bits are \b CBIPEN and \b CBIPSEL of \b CBCTL0 register; +//! bits \b CBRSEL of \b CBCTL2 register; bits \b CBPDx of \b CBCTL3 +//! register. +//! \param negativeTerminalInput selects the input to the negative terminal. +//! Valid values are: +//! - \b COMP_B_INPUT0 [Default] +//! - \b COMP_B_INPUT1 +//! - \b COMP_B_INPUT2 +//! - \b COMP_B_INPUT3 +//! - \b COMP_B_INPUT4 +//! - \b COMP_B_INPUT5 +//! - \b COMP_B_INPUT6 +//! - \b COMP_B_INPUT7 +//! - \b COMP_B_INPUT8 +//! - \b COMP_B_INPUT9 +//! - \b COMP_B_INPUT10 +//! - \b COMP_B_INPUT11 +//! - \b COMP_B_INPUT12 +//! - \b COMP_B_INPUT13 +//! - \b COMP_B_INPUT14 +//! - \b COMP_B_INPUT15 +//! - \b COMP_B_VREF +//! \n Modified bits are \b CBIMEN and \b CBIMSEL of \b CBCTL0 register; +//! bits \b CBRSEL of \b CBCTL2 register; bits \b CBPDx of \b CBCTL3 +//! register. +//! \param powerModeSelect selects the power mode at which the COMP_B module +//! will operate at. +//! Valid values are: +//! - \b COMP_B_POWERMODE_HIGHSPEED [Default] +//! - \b COMP_B_POWERMODE_NORMALMODE +//! - \b COMP_B_POWERMODE_ULTRALOWPOWER +//! \n Modified bits are \b CBWRMD of \b CBCTL1 register. +//! \param outputFilterEnableAndDelayLevel controls the output filter delay +//! state, which is either off or enabled with a specified delay level. +//! This parameter is device specific and delay levels should be found +//! in the device's datasheet. +//! Valid values are: +//! - \b COMP_B_FILTEROUTPUT_OFF [Default] +//! - \b COMP_B_FILTEROUTPUT_DLYLVL1 +//! - \b COMP_B_FILTEROUTPUT_DLYLVL2 +//! - \b COMP_B_FILTEROUTPUT_DLYLVL3 +//! - \b COMP_B_FILTEROUTPUT_DLYLVL4 +//! \n Modified bits are \b CBFDLY and \b CBF of \b CBCTL1 register. +//! \param invertedOutputPolarity controls if the output will be inverted or +//! not +//! Valid values are: +//! - \b COMP_B_NORMALOUTPUTPOLARITY [Default] +//! - \b COMP_B_INVERTEDOUTPUTPOLARITY +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the initialization process. +// +//***************************************************************************** +bool COMP_B_init(uint16_t baseAddress, + uint8_t positiveTerminalInput, + uint8_t negativeTerminalInput, + uint16_t powerModeSelect, + uint8_t outputFilterEnableAndDelayLevel, + uint16_t invertedOutputPolarity) +{ + COMP_B_initializeParam param = { 0 }; + + param.positiveTerminalInput = positiveTerminalInput; + param.negativeTerminalInput = negativeTerminalInput; + param.powerModeSelect = powerModeSelect; + param.outputFilterEnableAndDelayLevel = outputFilterEnableAndDelayLevel; + param.invertedOutputPolarity = invertedOutputPolarity; + + return COMP_B_initialize(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Initializes the COMP_B Module. +//! +//! Upon successful initialization of the COMP_B module, this function will +//! have reset all necessary register bits and set the given options in the +//! registers. To actually use the COMP_B module, the COMP_B_enable() function +//! must be explicitly called before use. If a Reference Voltage is set to a +//! terminal, the Voltage should be set using the COMP_B_setReferenceVoltage() +//! function. +//! +//! \param baseAddress is the base address of the COMP_B module. +//! \param param is the pointer to struct for initialization. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the initialization process. +// +//***************************************************************************** +bool COMP_B_initialize(uint16_t baseAddress, COMP_B_initializeParam *param) +{ + assert(param != 0); + assert(param->positiveTerminalInput <= COMP_B_VREF); + assert(param->negativeTerminalInput <= COMP_B_VREF); + assert(param->positiveTerminalInput != param->negativeTerminalInput); + assert(param->powerModeSelect <= COMP_B_POWERMODE_ULTRALOWPOWER); + assert(param->outputFilterEnableAndDelayLevel <= COMP_B_FILTEROUTPUT_DLYLVL4); + + bool retVal = STATUS_SUCCESS; + + //Reset COMPB Control 1 & Interrupt Registers for initialization (OFS_CBCTL3 + //is not reset because it controls the input buffers of the analog signals + //and may cause parasitic effects if an analog signal is still attached and + //the buffer is re-enabled + HWREG16(baseAddress + OFS_CBCTL0) &= 0x0000; + HWREG16(baseAddress + OFS_CBINT) &= 0x0000; + + //Set the Positive Terminal + if (COMP_B_VREF != param->positiveTerminalInput) { + //Enable Positive Terminal Input Mux and Set it to the appropriate input + HWREG16(baseAddress + OFS_CBCTL0) |= CBIPEN + param->positiveTerminalInput; + + //Disable the input buffer + HWREG16(baseAddress + OFS_CBCTL3) |= (1 << param->positiveTerminalInput); + } else + //Reset and Set COMPB Control 2 Register + HWREG16(baseAddress + OFS_CBCTL2) &= ~(CBRSEL); //Set Vref to go to (+)terminal + + //Set the Negative Terminal + if (COMP_B_VREF != param->negativeTerminalInput) { + //Enable Negative Terminal Input Mux and Set it to the appropriate input + HWREG16(baseAddress + OFS_CBCTL0) |= CBIMEN + (param->negativeTerminalInput << 8); + + //Disable the input buffer + HWREG16(baseAddress + OFS_CBCTL3) |= (1 << param->negativeTerminalInput); + } else + //Reset and Set COMPB Control 2 Register + HWREG16(baseAddress + OFS_CBCTL2) |= CBRSEL; //Set Vref to go to (-) terminal + + //Reset and Set COMPB Control 1 Register + HWREG16(baseAddress + OFS_CBCTL1) = + param->powerModeSelect //Set the power mode + + param->outputFilterEnableAndDelayLevel //Set the filter enable bit and delay + + param->invertedOutputPolarity; //Set the polarity of the output + + return retVal; +} + +//***************************************************************************** +// +//! \brief DEPRECATED - Generates a Reference Voltage to the terminal selected +//! during initialization. +//! +//! Use this function to generate a voltage to serve as a reference to the +//! terminal selected at initialization. The voltage is determined by the +//! equation: Vbase * (Numerator / 32). If the upper and lower limit voltage +//! numerators are equal, then a static reference is defined, whereas they are +//! different then a hysteresis effect is generated. +//! +//! \param baseAddress is the base address of the COMP_B module. +//! \param supplyVoltageReferenceBase decides the source and max amount of +//! Voltage that can be used as a reference. +//! Valid values are: +//! - \b COMP_B_VREFBASE_VCC +//! - \b COMP_B_VREFBASE1_5V +//! - \b COMP_B_VREFBASE2_0V +//! - \b COMP_B_VREFBASE2_5V +//! \n Modified bits are \b CBREFL of \b CBCTL2 register. +//! \param lowerLimitSupplyVoltageFractionOf32 is the numerator of the equation +//! to generate the reference voltage for the lower limit reference +//! voltage. +//! \n Modified bits are \b CBREF0 of \b CBCTL2 register. +//! \param upperLimitSupplyVoltageFractionOf32 is the numerator of the equation +//! to generate the reference voltage for the upper limit reference +//! voltage. +//! \n Modified bits are \b CBREF1 of \b CBCTL2 register. +//! \param referenceAccuracy is the reference accuracy setting of the COMP_B. +//! Clocked is for low power/low accuracy. +//! Valid values are: +//! - \b COMP_B_ACCURACY_STATIC +//! - \b COMP_B_ACCURACY_CLOCKED +//! \n Modified bits are \b CDREFACC of \b CDCTL2 register. +//! +//! \return None +// +//***************************************************************************** +void COMP_B_setReferenceVoltage(uint16_t baseAddress, + uint16_t supplyVoltageReferenceBase, + uint16_t lowerLimitSupplyVoltageFractionOf32, + uint16_t upperLimitSupplyVoltageFractionOf32, + uint16_t referenceAccuracy) +{ + COMP_B_configureReferenceVoltageParam param = { 0 }; + + param.supplyVoltageReferenceBase = supplyVoltageReferenceBase; + param.lowerLimitSupplyVoltageFractionOf32 = lowerLimitSupplyVoltageFractionOf32; + param.upperLimitSupplyVoltageFractionOf32 = upperLimitSupplyVoltageFractionOf32; + param.referenceAccuracy = referenceAccuracy; + + COMP_B_configureReferenceVoltage(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Generates a Reference Voltage to the terminal selected during +//! initialization. +//! +//! Use this function to generate a voltage to serve as a reference to the +//! terminal selected at initialization. The voltage is determined by the +//! equation: Vbase * (Numerator / 32). If the upper and lower limit voltage +//! numerators are equal, then a static reference is defined, whereas they are +//! different then a hysteresis effect is generated. +//! +//! \param baseAddress is the base address of the COMP_B module. +//! \param param is the pointer to struct for reference voltage configuration. +//! +//! \return None +// +//***************************************************************************** +void COMP_B_configureReferenceVoltage(uint16_t baseAddress, + COMP_B_configureReferenceVoltageParam *param) +{ + assert(param != 0); + assert(param->supplyVoltageReferenceBase <= COMP_B_VREFBASE2_5V); + assert(param->upperLimitSupplyVoltageFractionOf32 <= 32); + assert(param->lowerLimitSupplyVoltageFractionOf32 <= 32); + assert(param->upperLimitSupplyVoltageFractionOf32 + >= param->lowerLimitSupplyVoltageFractionOf32); + + HWREG16(baseAddress + OFS_CBCTL1) &= ~(CBMRVS); //Set to VREF0 + + //Reset COMPB Control 2 Bits (Except for CBRSEL which is set in Comp_Init() ) + HWREG16(baseAddress + OFS_CBCTL2) &= CBRSEL; + + //Set Voltage Source (Vcc | Vref, resistor ladder or not) + if (COMP_B_VREFBASE_VCC == param->supplyVoltageReferenceBase) + HWREG16(baseAddress + OFS_CBCTL2) |= CBRS_1; //Vcc with resistor ladder + else if (param->lowerLimitSupplyVoltageFractionOf32 == 32) { + //If the lower limit is 32, then the upper limit has to be 32 due to the + //assertion that upper must be >= to the lower limit. If the numerator is + //equal to 32, then the equation would be 32/32 == 1, therefore no resistor + //ladder is needed + HWREG16(baseAddress + OFS_CBCTL2) |= CBRS_3; //Vref, no resistor ladder + } else + HWREG16(baseAddress + OFS_CBCTL2) |= CBRS_2; //Vref with resistor ladder + + //Set COMPD Control 2 Register + HWREG16(baseAddress + OFS_CBCTL2) |= + param->supplyVoltageReferenceBase //Set Supply Voltage Base + + ((param->upperLimitSupplyVoltageFractionOf32 - 1) << 8) //Set Supply Voltage Num. + + (param->lowerLimitSupplyVoltageFractionOf32 - 1); + + HWREG16(baseAddress + OFS_CBCTL2) &= ~(CBREFACC); + HWREG16(baseAddress + OFS_CBCTL2) |= param->referenceAccuracy; +} //***************************************************************************** +// +//! \brief Enables selected COMP_B interrupt sources. +//! +//! Enables the indicated COMP_B interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. Does not clear interrupt flags. +//! +//! \param baseAddress is the base address of the COMP_B module. +//! \param interruptMask is the bit mask of the interrupt sources to be +//! enabled. +//! Mask value is the logical OR of any of the following: +//! - \b COMP_B_OUTPUT_INT - Output interrupt +//! - \b COMP_B_OUTPUTINVERTED_INT - Output interrupt inverted polarity +//! \n Modified bits of \b CBINT register. +//! +//! \return None +// +//***************************************************************************** +void COMP_B_enableInterrupt(uint16_t baseAddress, + uint16_t interruptMask) +{ + //Set the Interrupt enable bit + HWREG16(baseAddress + OFS_CBINT) |= interruptMask; +} + +//***************************************************************************** +// +//! \brief Disables selected COMP_B interrupt sources. +//! +//! Disables the indicated COMP_B interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! \param baseAddress is the base address of the COMP_B module. +//! \param interruptMask is the bit mask of the interrupt sources to be +//! disabled. +//! Mask value is the logical OR of any of the following: +//! - \b COMP_B_OUTPUT_INT - Output interrupt +//! - \b COMP_B_OUTPUTINVERTED_INT - Output interrupt inverted polarity +//! \n Modified bits of \b CBINT register. +//! +//! \return None +// +//***************************************************************************** +void COMP_B_disableInterrupt(uint16_t baseAddress, + uint16_t interruptMask) +{ + HWREG16(baseAddress + OFS_CBINT) &= ~(interruptMask); +} + +//***************************************************************************** +// +//! \brief Clears COMP_B interrupt flags. +//! +//! The COMP_B interrupt source is cleared, so that it no longer asserts. The +//! highest interrupt flag is automatically cleared when an interrupt vector +//! generator is used. +//! +//! \param baseAddress is the base address of the COMP_B module. +//! \param interruptFlagMask is a bit mask of the interrupt sources to be +//! cleared. +//! Mask value is the logical OR of any of the following: +//! - \b COMP_B_OUTPUT_FLAG - Output interrupt +//! - \b COMP_B_OUTPUTINVERTED_FLAG - Output interrupt inverted polarity +//! \n Modified bits of \b CBINT register. +//! +//! \return None +// +//***************************************************************************** +void COMP_B_clearInterrupt(uint16_t baseAddress, + uint16_t interruptFlagMask) +{ + HWREG16(baseAddress + OFS_CBINT) &= ~(interruptFlagMask); +} + +//***************************************************************************** +// +//! \brief Gets the current COMP_B interrupt status. +//! +//! This returns the interrupt status for the COMP_B module based on which flag +//! is passed. +//! +//! \param baseAddress is the base address of the COMP_B module. +//! \param interruptFlagMask is the masked interrupt flag status to be +//! returned. +//! Mask value is the logical OR of any of the following: +//! - \b COMP_B_OUTPUT_FLAG - Output interrupt +//! - \b COMP_B_OUTPUTINVERTED_FLAG - Output interrupt inverted polarity +//! +//! \return Logical OR of any of the following: +//! - \b COMP_B_OUTPUT_FLAG Output interrupt +//! - \b COMP_B_OUTPUTINVERTED_FLAG Output interrupt inverted polarity +//! \n indicating the status of the masked interrupts +// +//***************************************************************************** +uint8_t COMP_B_getInterruptStatus(uint16_t baseAddress, + uint16_t interruptFlagMask) +{ + return HWREG16(baseAddress + OFS_CBINT) & interruptFlagMask; +} + +//***************************************************************************** +// +//! \brief Explicitly sets the edge direction that would trigger an interrupt. +//! +//! This function will set which direction the output will have to go, whether +//! rising or falling, to generate an interrupt based on a non-inverted +//! interrupt. +//! +//! \param baseAddress is the base address of the COMP_B module. +//! \param edgeDirection determines which direction the edge would have to go +//! to generate an interrupt based on the non-inverted interrupt flag. +//! Valid values are: +//! - \b COMP_B_FALLINGEDGE [Default] - sets the bit to generate an +//! interrupt when the output of the COMP_B falls from HIGH to LOW if +//! the normal interrupt bit is set(and LOW to HIGH if the inverted +//! interrupt enable bit is set). +//! - \b COMP_B_RISINGEDGE - sets the bit to generate an interrupt when +//! the output of the COMP_B rises from LOW to HIGH if the normal +//! interrupt bit is set(and HIGH to LOW if the inverted interrupt +//! enable bit is set). +//! \n Modified bits are \b CBIES of \b CBCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void COMP_B_interruptSetEdgeDirection(uint16_t baseAddress, + uint16_t edgeDirection) +{ + assert(edgeDirection <= COMP_B_RISINGEDGE); + + //Set the edge direction that will trigger an interrupt + if (COMP_B_RISINGEDGE == edgeDirection) + HWREG16(baseAddress + OFS_CBCTL1) |= CBIES; + else if (COMP_B_FALLINGEDGE == edgeDirection) + HWREG16(baseAddress + OFS_CBCTL1) &= ~(CBIES); +} + +//***************************************************************************** +// +//! \brief Toggles the edge direction that would trigger an interrupt. +//! +//! This function will toggle which direction the output will have to go, +//! whether rising or falling, to generate an interrupt based on a non-inverted +//! interrupt. If the direction was rising, it is now falling, if it was +//! falling, it is now rising. +//! +//! \param baseAddress is the base address of the COMP_B module. +//! +//! \return None +// +//***************************************************************************** +void COMP_B_interruptToggleEdgeDirection(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_CBCTL1) ^= CBIES; +} + +//***************************************************************************** +// +//! \brief Turns on the COMP_B module. +//! +//! This function sets the bit that enables the operation of the COMP_B module. +//! +//! \param baseAddress is the base address of the COMP_B module. +//! +//! \return None +// +//***************************************************************************** +void COMP_B_enable(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_CBCTL1) |= CBON; +} + +//***************************************************************************** +// +//! \brief Turns off the COMP_B module. +//! +//! This function clears the CBON bit disabling the operation of the COMP_B +//! module, saving from excess power consumption. +//! +//! \param baseAddress is the base address of the COMP_B module. +//! +//! \return None +// +//***************************************************************************** +void COMP_B_disable(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_CBCTL1) &= ~(CBON); +} + +//***************************************************************************** +// +//! \brief Shorts the two input pins chosen during initialization. +//! +//! This function sets the bit that shorts the devices attached to the input +//! pins chosen from the initialization of the COMP_B. +//! +//! \param baseAddress is the base address of the COMP_B module. +//! +//! \return None +// +//***************************************************************************** +void COMP_B_shortInputs(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_CBCTL1) |= CBSHORT; +} + +//***************************************************************************** +// +//! \brief Disables the short of the two input pins chosen during +//! initialization. +//! +//! This function clears the bit that shorts the devices attached to the input +//! pins chosen from the initialization of the COMP_B. +//! +//! \param baseAddress is the base address of the COMP_B module. +//! +//! \return None +// +//***************************************************************************** +void COMP_B_unshortInputs(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_CBCTL1) &= ~(CBSHORT); +} + +//***************************************************************************** +// +//! \brief Disables the input buffer of the selected input port to effectively +//! allow for analog signals. +//! +//! This function sets the bit to disable the buffer for the specified input +//! port to allow for analog signals from any of the COMP_B input pins. This +//! bit is automatically set when the input is initialized to be used with the +//! COMP_B module. This function should be used whenever an analog input is +//! connected to one of these pins to prevent parasitic voltage from causing +//! unexpected results. +//! +//! \param baseAddress is the base address of the COMP_B module. +//! \param inputPort is the port in which the input buffer will be disabled. +//! Valid values are: +//! - \b COMP_B_INPUT0 [Default] +//! - \b COMP_B_INPUT1 +//! - \b COMP_B_INPUT2 +//! - \b COMP_B_INPUT3 +//! - \b COMP_B_INPUT4 +//! - \b COMP_B_INPUT5 +//! - \b COMP_B_INPUT6 +//! - \b COMP_B_INPUT7 +//! - \b COMP_B_INPUT8 +//! - \b COMP_B_INPUT9 +//! - \b COMP_B_INPUT10 +//! - \b COMP_B_INPUT11 +//! - \b COMP_B_INPUT12 +//! - \b COMP_B_INPUT13 +//! - \b COMP_B_INPUT14 +//! - \b COMP_B_INPUT15 +//! - \b COMP_B_VREF +//! \n Modified bits are \b CBPDx of \b CBCTL3 register. +//! +//! \return None +// +//***************************************************************************** +void COMP_B_disableInputBuffer(uint16_t baseAddress, + uint8_t inputPort) +{ + assert(inputPort <= COMP_B_INPUT15); + + HWREG16(baseAddress + OFS_CBCTL3) |= (1 << inputPort); +} + +//***************************************************************************** +// +//! \brief Enables the input buffer of the selected input port to allow for +//! digital signals. +//! +//! This function clears the bit to enable the buffer for the specified input +//! port to allow for digital signals from any of the COMP_B input pins. This +//! should not be reset if there is an analog signal connected to the specified +//! input pin to prevent from unexpected results. +//! +//! \param baseAddress is the base address of the COMP_B module. +//! \param inputPort is the port in which the input buffer will be enabled. +//! Valid values are: +//! - \b COMP_B_INPUT0 [Default] +//! - \b COMP_B_INPUT1 +//! - \b COMP_B_INPUT2 +//! - \b COMP_B_INPUT3 +//! - \b COMP_B_INPUT4 +//! - \b COMP_B_INPUT5 +//! - \b COMP_B_INPUT6 +//! - \b COMP_B_INPUT7 +//! - \b COMP_B_INPUT8 +//! - \b COMP_B_INPUT9 +//! - \b COMP_B_INPUT10 +//! - \b COMP_B_INPUT11 +//! - \b COMP_B_INPUT12 +//! - \b COMP_B_INPUT13 +//! - \b COMP_B_INPUT14 +//! - \b COMP_B_INPUT15 +//! - \b COMP_B_VREF +//! \n Modified bits are \b CBPDx of \b CBCTL3 register. +//! +//! \return None +// +//***************************************************************************** +void COMP_B_enableInputBuffer(uint16_t baseAddress, uint8_t inputPort) +{ + assert(inputPort <= COMP_B_INPUT15); + + HWREG16(baseAddress + OFS_CBCTL3) &= ~(1 << inputPort); +} + +//***************************************************************************** +// +//! \brief Toggles the bit that swaps which terminals the inputs go to, while +//! also inverting the output of the COMP_B. +//! +//! This function toggles the bit that controls which input goes to which +//! terminal. After initialization, this bit is set to 0, after toggling it +//! once the inputs are routed to the opposite terminal and the output is +//! inverted. +//! +//! \param baseAddress is the base address of the COMP_B module. +//! +//! \return None +// +//***************************************************************************** +void COMP_B_IOSwap(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_CBCTL1) ^= CBEX; //Toggle CBEX bit +} + +//***************************************************************************** +// +//! \brief Returns the output value of the COMP_B module. +//! +//! Returns the output value of the COMP_B module. +//! +//! \param baseAddress is the base address of the COMP_B module. +//! +//! \return One of the following: +//! - \b COMP_B_LOW +//! - \b COMP_B_HIGH +//! \n indicating the output value of the COMP_B module +// +//***************************************************************************** +uint16_t COMP_B_outputValue(uint16_t baseAddress) +{ + return HWREG16(baseAddress + OFS_CBCTL1) & CBOUT; + +} + + +#endif +//***************************************************************************** +// +//! Close the doxygen group for comp_b_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/comp_b.h b/source/driverlib/MSP430F5xx_6xx/comp_b.h new file mode 100644 index 0000000..d608b05 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/comp_b.h @@ -0,0 +1,271 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// comp_b.h - Driver for the COMP_B Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_COMP_B_H__ +#define __MSP430WARE_COMP_B_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_COMPB__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//****************************************************************************** +// +// The following is a struct that is passed to COMP_B_initialize() +// +//****************************************************************************** +typedef struct COMP_B_initializeParam { + uint8_t positiveTerminalInput; + uint8_t negativeTerminalInput; + uint16_t powerModeSelect; + uint8_t outputFilterEnableAndDelayLevel; + uint16_t invertedOutputPolarity; +} COMP_B_initializeParam; + +//****************************************************************************** +// +// The following is a struct that is passed to COMP_B_configureReferenceVoltage() +// +//****************************************************************************** +typedef struct COMP_B_configureReferenceVoltageParam { + uint16_t supplyVoltageReferenceBase; + uint16_t lowerLimitSupplyVoltageFractionOf32; + uint16_t upperLimitSupplyVoltageFractionOf32; + uint16_t referenceAccuracy; +} COMP_B_configureReferenceVoltageParam; + +//***************************************************************************** +// +// The following are values that can be passed to the powerModeSelect parameter +// for functions: COMP_B_init(). +// +//***************************************************************************** +#define COMP_B_POWERMODE_HIGHSPEED (CBPWRMD_0) +#define COMP_B_POWERMODE_NORMALMODE (CBPWRMD_1) +#define COMP_B_POWERMODE_ULTRALOWPOWER (CBPWRMD_2) + +//***************************************************************************** +// +// The following are values that can be passed to the positiveTerminalInput +// parameter for functions: COMP_B_init(); the inputPort parameter for +// functions: COMP_B_disableInputBuffer(), and COMP_B_enableInputBuffer(); the +// negativeTerminalInput parameter for functions: COMP_B_init(). +// +//***************************************************************************** +#define COMP_B_INPUT0 (CBIPSEL_0) +#define COMP_B_INPUT1 (CBIPSEL_1) +#define COMP_B_INPUT2 (CBIPSEL_2) +#define COMP_B_INPUT3 (CBIPSEL_3) +#define COMP_B_INPUT4 (CBIPSEL_4) +#define COMP_B_INPUT5 (CBIPSEL_5) +#define COMP_B_INPUT6 (CBIPSEL_6) +#define COMP_B_INPUT7 (CBIPSEL_7) +#define COMP_B_INPUT8 (CBIPSEL_8) +#define COMP_B_INPUT9 (CBIPSEL_9) +#define COMP_B_INPUT10 (CBIPSEL_10) +#define COMP_B_INPUT11 (CBIPSEL_11) +#define COMP_B_INPUT12 (CBIPSEL_12) +#define COMP_B_INPUT13 (CBIPSEL_13) +#define COMP_B_INPUT14 (CBIPSEL_14) +#define COMP_B_INPUT15 (CBIPSEL_15) +#define COMP_B_VREF (0x10) + +//***************************************************************************** +// +// The following are values that can be passed to the +// outputFilterEnableAndDelayLevel parameter for functions: COMP_B_init(). +// +//***************************************************************************** +#define COMP_B_FILTEROUTPUT_OFF 0x00 +#define COMP_B_FILTEROUTPUT_DLYLVL1 (CBF + CBFDLY_0) +#define COMP_B_FILTEROUTPUT_DLYLVL2 (CBF + CBFDLY_1) +#define COMP_B_FILTEROUTPUT_DLYLVL3 (CBF + CBFDLY_2) +#define COMP_B_FILTEROUTPUT_DLYLVL4 (CBF + CBFDLY_3) + +//***************************************************************************** +// +// The following are values that can be passed to the invertedOutputPolarity +// parameter for functions: COMP_B_init(). +// +//***************************************************************************** +#define COMP_B_NORMALOUTPUTPOLARITY (!(CBOUTPOL)) +#define COMP_B_INVERTEDOUTPUTPOLARITY (CBOUTPOL) + +//***************************************************************************** +// +// The following are values that can be passed to the referenceAccuracy +// parameter for functions: COMP_B_setReferenceVoltage(). +// +//***************************************************************************** +#define COMP_B_ACCURACY_STATIC (!CBREFACC) +#define COMP_B_ACCURACY_CLOCKED (CBREFACC) + +//***************************************************************************** +// +// The following are values that can be passed to the +// supplyVoltageReferenceBase parameter for functions: +// COMP_B_setReferenceVoltage(). +// +//***************************************************************************** +#define COMP_B_VREFBASE_VCC (CBREFL_0) +#define COMP_B_VREFBASE1_5V (CBREFL_1) +#define COMP_B_VREFBASE2_0V (CBREFL_2) +#define COMP_B_VREFBASE2_5V (CBREFL_3) + +//***************************************************************************** +// +// The following are values that can be passed to the interruptMask parameter +// for functions: COMP_B_enableInterrupt(), and COMP_B_disableInterrupt(). +// +//***************************************************************************** +#define COMP_B_OUTPUT_INT CBIE +#define COMP_B_OUTPUTINVERTED_INT CBIIE + +//***************************************************************************** +// +// The following are values that can be passed to the interruptFlagMask +// parameter for functions: COMP_B_clearInterrupt(), and +// COMP_B_getInterruptStatus() as well as returned by the +// COMP_B_getInterruptStatus() function. +// +//***************************************************************************** +#define COMP_B_OUTPUT_FLAG CBIFG +#define COMP_B_OUTPUTINVERTED_FLAG CBIIFG + +//***************************************************************************** +// +// The following are values that can be passed to the edgeDirection parameter +// for functions: COMP_B_interruptSetEdgeDirection(). +// +//***************************************************************************** +#define COMP_B_FALLINGEDGE (!(CBIES)) +#define COMP_B_RISINGEDGE (CBIES) + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the COMP_B_outputValue() function. +// +//***************************************************************************** +#define COMP_B_LOW (0x0) +#define COMP_B_HIGH (CBOUT) + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern bool COMP_B_initialize(uint16_t baseAddress, + COMP_B_initializeParam *param); + +extern void COMP_B_configureReferenceVoltage(uint16_t baseAddress, + COMP_B_configureReferenceVoltageParam *param); + +extern void COMP_B_enableInterrupt(uint16_t baseAddress, + uint16_t interruptMask); + +extern void COMP_B_disableInterrupt(uint16_t baseAddress, + uint16_t interruptMask); + +extern void COMP_B_clearInterrupt(uint16_t baseAddress, + uint16_t interruptFlagMask); + +extern uint8_t COMP_B_getInterruptStatus(uint16_t baseAddress, + uint16_t interruptFlagMask); + +extern void COMP_B_interruptSetEdgeDirection(uint16_t baseAddress, + uint16_t edgeDirection); + +extern void COMP_B_interruptToggleEdgeDirection(uint16_t baseAddress); + +extern void COMP_B_enable(uint16_t baseAddress); + +extern void COMP_B_disable(uint16_t baseAddress); + +extern void COMP_B_shortInputs(uint16_t baseAddress); + +extern void COMP_B_unshortInputs(uint16_t baseAddress); + +extern void COMP_B_disableInputBuffer(uint16_t baseAddress, + uint8_t inputPort); + +extern void COMP_B_enableInputBuffer(uint16_t baseAddress, + uint8_t inputPort); + +extern void COMP_B_IOSwap(uint16_t baseAddress); + +extern uint16_t COMP_B_outputValue(uint16_t baseAddress); + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +extern bool COMP_B_init(uint16_t baseAddress, + uint8_t positiveTerminalInput, + uint8_t negativeTerminalInput, + uint16_t powerModeSelect, + uint8_t outputFilterEnableAndDelayLevel, + uint16_t invertedOutputPolarity); + +extern void COMP_B_setReferenceVoltage(uint16_t baseAddress, + uint16_t supplyVoltageReferenceBase, + uint16_t lowerLimitSupplyVoltageFractionOf32, + uint16_t upperLimitSupplyVoltageFractionOf32, + uint16_t referenceAccuracy); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_COMP_B_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/crc.c b/source/driverlib/MSP430F5xx_6xx/crc.c new file mode 100644 index 0000000..51e7065 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/crc.c @@ -0,0 +1,220 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// crc.c - Driver for the crc Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup crc_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_CRC__ +#include "crc.h" + +#include + +//***************************************************************************** +// +//! \brief Sets the seed for the CRC. +//! +//! This function sets the seed for the CRC to begin generating a signature +//! with the given seed and all passed data. Using this function resets the CRC +//! signature. +//! +//! \param baseAddress is the base address of the CRC module. +//! \param seed is the seed for the CRC to start generating a signature from. +//! \n Modified bits are \b CRCINIRES of \b CRCINIRES register. +//! +//! \return None +// +//***************************************************************************** +void CRC_setSeed(uint16_t baseAddress, + uint16_t seed) +{ + HWREG16(baseAddress + OFS_CRCINIRES) = seed; +} + +//***************************************************************************** +// +//! \brief Sets the 16 bit data to add into the CRC module to generate a new +//! signature. +//! +//! This function sets the given data into the CRC module to generate the new +//! signature from the current signature and new data. +//! +//! \param baseAddress is the base address of the CRC module. +//! \param dataIn is the data to be added, through the CRC module, to the +//! signature. +//! \n Modified bits are \b CRCDI of \b CRCDI register. +//! +//! \return None +// +//***************************************************************************** +void CRC_set16BitData(uint16_t baseAddress, + uint16_t dataIn) +{ + HWREG16(baseAddress + OFS_CRCDI) = dataIn; +} + +//***************************************************************************** +// +//! \brief Sets the 8 bit data to add into the CRC module to generate a new +//! signature. +//! +//! This function sets the given data into the CRC module to generate the new +//! signature from the current signature and new data. +//! +//! \param baseAddress is the base address of the CRC module. +//! \param dataIn is the data to be added, through the CRC module, to the +//! signature. +//! \n Modified bits are \b CRCDI of \b CRCDI register. +//! +//! \return None +// +//***************************************************************************** +void CRC_set8BitData(uint16_t baseAddress, + uint8_t dataIn) +{ + HWREG8(baseAddress + OFS_CRCDI_L) = dataIn; +} + +//***************************************************************************** +// +//! \brief Translates the 16 bit data by reversing the bits in each byte and +//! then sets this data to add into the CRC module to generate a new signature. +//! +//! This function first reverses the bits in each byte of the data and then +//! generates the new signature from the current signature and new translated +//! data. +//! +//! \param baseAddress is the base address of the CRC module. +//! \param dataIn is the data to be added, through the CRC module, to the +//! signature. +//! \n Modified bits are \b CRCDIRB of \b CRCDIRB register. +//! +//! \return None +// +//***************************************************************************** +void CRC_set16BitDataReversed(uint16_t baseAddress, + uint16_t dataIn) +{ + HWREG16(baseAddress + OFS_CRCDIRB) = dataIn; +} + +//***************************************************************************** +// +//! \brief Translates the 8 bit data by reversing the bits in each byte and +//! then sets this data to add into the CRC module to generate a new signature. +//! +//! This function first reverses the bits in each byte of the data and then +//! generates the new signature from the current signature and new translated +//! data. +//! +//! \param baseAddress is the base address of the CRC module. +//! \param dataIn is the data to be added, through the CRC module, to the +//! signature. +//! \n Modified bits are \b CRCDIRB of \b CRCDIRB register. +//! +//! \return None +// +//***************************************************************************** +void CRC_set8BitDataReversed(uint16_t baseAddress, + uint8_t dataIn) +{ + HWREG8(baseAddress + OFS_CRCDIRB_L) = dataIn; +} + +//***************************************************************************** +// +//! \brief Returns the value currently in the Data register. +//! +//! This function returns the value currently in the data register. If set in +//! byte bits reversed format, then the translated data would be returned. +//! +//! \param baseAddress is the base address of the CRC module. +//! +//! \return The value currently in the data register +// +//***************************************************************************** +uint16_t CRC_getData(uint16_t baseAddress) +{ + return HWREG16(baseAddress + OFS_CRCDI); +} + +//***************************************************************************** +// +//! \brief Returns the value pf the Signature Result. +//! +//! This function returns the value of the signature result generated by the +//! CRC. +//! +//! \param baseAddress is the base address of the CRC module. +//! +//! \return The value currently in the data register +// +//***************************************************************************** +uint16_t CRC_getResult(uint16_t baseAddress) +{ + return HWREG16(baseAddress + OFS_CRCINIRES); +} + +//***************************************************************************** +// +//! \brief Returns the bit-wise reversed format of the Signature Result. +//! +//! This function returns the bit-wise reversed format of the Signature Result. +//! +//! \param baseAddress is the base address of the CRC module. +//! +//! \return The bit-wise reversed format of the Signature Result +// +//***************************************************************************** +uint16_t CRC_getResultBitsReversed(uint16_t baseAddress) +{ + return HWREG16(baseAddress + OFS_CRCRESR); +} + +#endif +//***************************************************************************** +// +//! Close the doxygen group for crc_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/crc.h b/source/driverlib/MSP430F5xx_6xx/crc.h new file mode 100644 index 0000000..1861bf7 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/crc.h @@ -0,0 +1,106 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// crc.h - Driver for the CRC Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_CRC_H__ +#define __MSP430WARE_CRC_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_CRC__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void CRC_setSeed(uint16_t baseAddress, + uint16_t seed); + +extern void CRC_set16BitData(uint16_t baseAddress, + uint16_t dataIn); + +extern void CRC_set8BitData(uint16_t baseAddress, + uint8_t dataIn); + +extern void CRC_set16BitDataReversed(uint16_t baseAddress, + uint16_t dataIn); + +extern void CRC_set8BitDataReversed(uint16_t baseAddress, + uint8_t dataIn); + +extern uint16_t CRC_getData(uint16_t baseAddress); + +extern uint16_t CRC_getResult(uint16_t baseAddress); + +extern uint16_t CRC_getResultBitsReversed(uint16_t baseAddress); + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +#define CRC_setDataByteBitsReversed CRC_set16BitDataReversed + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +#define CRC_setData CRC_set16BitData + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_CRC_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/dac12_a.c b/source/driverlib/MSP430F5xx_6xx/dac12_a.c new file mode 100644 index 0000000..961e1d2 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/dac12_a.c @@ -0,0 +1,763 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// dac12_a.c - Driver for the dac12_a Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup dac12_a_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_DAC12_2__ +#include "dac12_a.h" + +#include + +//***************************************************************************** +// +//! \brief DEPRECATED - Initializes the DAC12_A module with the specified +//! settings. +//! +//! This function initializes the DAC12_A module with the specified settings. +//! Upon successful completion of the initialization of this module the control +//! registers and interrupts of this module are all reset, and the specified +//! variables will be set. Please note, that if conversions are enabled with +//! the enableConversions() function, then disableConversions() must be called +//! before re-initializing the DAC12_A module with this function. +//! +//! \param baseAddress is the base address of the DAC12_A module. +//! \param submoduleSelect decides which DAC12_A sub-module to configure. +//! Valid values are: +//! - \b DAC12_A_SUBMODULE_0 +//! - \b DAC12_A_SUBMODULE_1 +//! \param outputSelect selects the output pin that the selected DAC12_A module +//! will output to. +//! Valid values are: +//! - \b DAC12_A_OUTPUT_1 [Default] +//! - \b DAC12_A_OUTPUT_2 +//! \n Modified bits are \b DAC12OPS of \b DAC12_xCTL0 register. +//! \param positiveReferenceVoltage is the upper limit voltage that the data +//! can be converted in to. +//! Valid values are: +//! - \b DAC12_A_VREF_AVCC [Default] +//! - \b DAC12_A_VREF_INT +//! - \b DAC12_A_VREF_EXT +//! \n Modified bits are \b DAC12SREFx of \b DAC12_xCTL0 register. +//! \param outputVoltageMultiplier is the multiplier of the Vout voltage. +//! Valid values are: +//! - \b DAC12_A_VREFx1 [Default] +//! - \b DAC12_A_VREFx2 +//! - \b DAC12_A_VREFx3 +//! \n Modified bits are \b DAC12IR of \b DAC12_xCTL0 register; bits \b +//! DAC12OG of \b DAC12_xCTL1 register. +//! \param amplifierSetting is the setting of the settling speed and current of +//! the Vref+ and the Vout buffer. +//! Valid values are: +//! - \b DAC12_A_AMP_OFF_PINOUTHIGHZ [Default] - Initialize the DAC12_A +//! Module with settings, but do not turn it on. +//! - \b DAC12_A_AMP_OFF_PINOUTLOW - Initialize the DAC12_A Module with +//! settings, and allow it to take control of the selected output pin +//! to pull it low (Note: this takes control away port mapping +//! module). +//! - \b DAC12_A_AMP_LOWIN_LOWOUT - Select a slow settling speed and +//! current for Vref+ input buffer and for Vout output buffer. +//! - \b DAC12_A_AMP_LOWIN_MEDOUT - Select a slow settling speed and +//! current for Vref+ input buffer and a medium settling speed and +//! current for Vout output buffer. +//! - \b DAC12_A_AMP_LOWIN_HIGHOUT - Select a slow settling speed and +//! current for Vref+ input buffer and a high settling speed and +//! current for Vout output buffer. +//! - \b DAC12_A_AMP_MEDIN_MEDOUT - Select a medium settling speed and +//! current for Vref+ input buffer and for Vout output buffer. +//! - \b DAC12_A_AMP_MEDIN_HIGHOUT - Select a medium settling speed and +//! current for Vref+ input buffer and a high settling speed and +//! current for Vout output buffer. +//! - \b DAC12_A_AMP_HIGHIN_HIGHOUT - Select a high settling speed and +//! current for Vref+ input buffer and for Vout output buffer. +//! \n Modified bits are \b DAC12AMPx of \b DAC12_xCTL0 register. +//! \param conversionTriggerSelect selects the trigger that will start a +//! conversion. +//! Valid values are: +//! - \b DAC12_A_TRIGGER_ENCBYPASS [Default] - Automatically converts +//! data as soon as it is written into the data buffer. (Note: Do not +//! use this selection if grouping DAC's). +//! - \b DAC12_A_TRIGGER_ENC - Requires a call to enableConversions() to +//! allow a conversion, but starts a conversion as soon as data is +//! written to the data buffer (Note: with DAC12_A module's grouped, +//! data has to be set in BOTH DAC12_A data buffers to start a +//! conversion). +//! - \b DAC12_A_TRIGGER_TA - Requires a call to enableConversions() to +//! allow a conversion, and a rising edge of Timer_A's Out1 (TA1) to +//! start a conversion. +//! - \b DAC12_A_TRIGGER_TB - Requires a call to enableConversions() to +//! allow a conversion, and a rising edge of Timer_B's Out2 (TB2) to +//! start a conversion. +//! \n Modified bits are \b DAC12LSELx of \b DAC12_xCTL0 register. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the initialization process. +// +//***************************************************************************** +bool DAC12_A_init(uint16_t baseAddress, + uint8_t submoduleSelect, + uint16_t outputSelect, + uint16_t positiveReferenceVoltage, + uint16_t outputVoltageMultiplier, + uint8_t amplifierSetting, + uint16_t conversionTriggerSelect) +{ + DAC12_A_initializeParam param = { 0 }; + + param.submoduleSelect = submoduleSelect; + param.outputSelect = outputSelect; + param.positiveReferenceVoltage = positiveReferenceVoltage; + param.outputVoltageMultiplier = outputVoltageMultiplier; + param.amplifierSetting = amplifierSetting; + param.conversionTriggerSelect = conversionTriggerSelect; + + return DAC12_A_initialize(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Initializes the DAC12_A module with the specified settings. +//! +//! This function initializes the DAC12_A module with the specified settings. +//! Upon successful completion of the initialization of this module the control +//! registers and interrupts of this module are all reset, and the specified +//! variables will be set. Please note, that if conversions are enabled with +//! the enableConversions() function, then disableConversions() must be called +//! before re-initializing the DAC12_A module with this function. +//! +//! \param baseAddress is the base address of the DAC12_A module. +//! \param param is the pointer to struct for initialization. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the initialization process. +// +//***************************************************************************** +bool DAC12_A_initialize(uint16_t baseAddress, DAC12_A_initializeParam *param) +{ + assert(param != 0); + assert(param->submoduleSelect <= DAC12_A_SUBMODULE_1); + assert(param->outputSelect <= DAC12_A_OUTPUT_2); + assert(param->positiveReferenceVoltage <= DAC12_A_VREF_EXT); + assert(param->outputVoltageMultiplier <= DAC12_A_VREFx3); + assert(param->amplifierSetting <= DAC12_A_AMP_HIGHIN_HIGHOUT); + assert(param->conversionTriggerSelect <= DAC12_A_TRIGGER_TB); + + baseAddress += param->submoduleSelect; //Add 0x10 to base address IF + //DAC12_A_1 is selected. + bool retVal = STATUS_SUCCESS; + + HWREG16(baseAddress + OFS_DAC12_0CTL1) &= ~(DAC12OG + DAC12DFJ); + + //Reset and Set DAC12_A Control 0 Bits + HWREG16(baseAddress + OFS_DAC12_0CTL0) = param->outputSelect + + param->positiveReferenceVoltage + + param->amplifierSetting + + param->conversionTriggerSelect; + + if (DAC12_A_VREFx1 == param->outputVoltageMultiplier) + HWREG16(baseAddress + OFS_DAC12_0CTL0) |= DAC12IR; + else if (DAC12_A_VREFx2 == param->outputVoltageMultiplier) + HWREG16(baseAddress + OFS_DAC12_0CTL1) |= DAC12OG; + //else if(DAC12_A_VREFx3 == outputVoltageMultiplier) + //Both DAC12IR and DAC12OG values == 0 + + return retVal; +} //***************************************************************************** +// +//! \brief Sets the amplifier settings for the Vref+ and Vout buffers. +//! +//! This function sets the amplifier settings of the DAC12_A module for the +//! Vref+ and Vout buffers without re-initializing the DAC12_A module. This can +//! be used to disable the control of the pin by the DAC12_A module. +//! +//! \param baseAddress is the base address of the DAC12_A module. +//! \param submoduleSelect decides which DAC12_A sub-module to configure. +//! Valid values are: +//! - \b DAC12_A_SUBMODULE_0 +//! - \b DAC12_A_SUBMODULE_1 +//! \param amplifierSetting is the setting of the settling speed and current of +//! the Vref+ and the Vout buffer. +//! Valid values are: +//! - \b DAC12_A_AMP_OFF_PINOUTHIGHZ [Default] - Initialize the DAC12_A +//! Module with settings, but do not turn it on. +//! - \b DAC12_A_AMP_OFF_PINOUTLOW - Initialize the DAC12_A Module with +//! settings, and allow it to take control of the selected output pin +//! to pull it low (Note: this takes control away port mapping +//! module). +//! - \b DAC12_A_AMP_LOWIN_LOWOUT - Select a slow settling speed and +//! current for Vref+ input buffer and for Vout output buffer. +//! - \b DAC12_A_AMP_LOWIN_MEDOUT - Select a slow settling speed and +//! current for Vref+ input buffer and a medium settling speed and +//! current for Vout output buffer. +//! - \b DAC12_A_AMP_LOWIN_HIGHOUT - Select a slow settling speed and +//! current for Vref+ input buffer and a high settling speed and +//! current for Vout output buffer. +//! - \b DAC12_A_AMP_MEDIN_MEDOUT - Select a medium settling speed and +//! current for Vref+ input buffer and for Vout output buffer. +//! - \b DAC12_A_AMP_MEDIN_HIGHOUT - Select a medium settling speed and +//! current for Vref+ input buffer and a high settling speed and +//! current for Vout output buffer. +//! - \b DAC12_A_AMP_HIGHIN_HIGHOUT - Select a high settling speed and +//! current for Vref+ input buffer and for Vout output buffer. +//! +//! \return None +// +//***************************************************************************** +void DAC12_A_setAmplifierSetting(uint16_t baseAddress, + uint8_t submoduleSelect, + uint8_t amplifierSetting) +{ + assert(submoduleSelect <= DAC12_A_SUBMODULE_1); + assert(amplifierSetting <= DAC12_A_AMP_HIGHIN_HIGHOUT); + + //Reset amplifier setting to set it + HWREG16(baseAddress + submoduleSelect + OFS_DAC12_0CTL0) &= ~(DAC12AMP_7); + HWREG16(baseAddress + submoduleSelect + OFS_DAC12_0CTL0) |= amplifierSetting; +} + +//***************************************************************************** +// +//! \brief Clears the amplifier settings to disable the DAC12_A module. +//! +//! This function clears the amplifier settings for the selected DAC12_A module +//! to disable the DAC12_A module. +//! +//! \param baseAddress is the base address of the DAC12_A module. +//! \param submoduleSelect decides which DAC12_A sub-module to configure. +//! Valid values are: +//! - \b DAC12_A_SUBMODULE_0 +//! - \b DAC12_A_SUBMODULE_1 +//! +//! Modified bits are \b DAC12AMP_7 of \b DAC12_xCTL0 register. +//! +//! \return None +// +//***************************************************************************** +void DAC12_A_disable(uint16_t baseAddress, + uint8_t submoduleSelect) +{ + assert(submoduleSelect <= DAC12_A_SUBMODULE_1); + //Reset amplifier setting to turn DAC12_A off completely + HWREG16(baseAddress + submoduleSelect + OFS_DAC12_0CTL0) &= ~(DAC12AMP_7); +} + +//***************************************************************************** +// +//! \brief Enables grouping of two DAC12_A modules in a dual DAC12_A system. +//! +//! This function enables grouping two DAC12_A modules in a dual DAC12_A +//! system. Both DAC12_A modules will work in sync, converting data at the same +//! time. To convert data, the same trigger should be set for both DAC12_A +//! modules during initialization (which should not be +//! DAC12_A_TRIGGER_ENCBYPASS), the enableConversions() function needs to be +//! called with both DAC12_A modules, and data needs to be set for both DAC12_A +//! modules separately. +//! +//! \param baseAddress is the base address of the DAC12_A module. +//! +//! Modified bits are \b DAC12GRP of \b DAC12_xCTL0 register. +//! +//! \return None +// +//***************************************************************************** +void DAC12_A_enableGrouping(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_DAC12_0CTL0) |= DAC12GRP; +} + +//***************************************************************************** +// +//! \brief Disables grouping of two DAC12_A modules in a dual DAC12_A system. +//! +//! This function disables grouping of two DAC12_A modules in a dual DAC12_A +//! system. +//! +//! \param baseAddress is the base address of the DAC12_A module. +//! +//! \return None +// +//***************************************************************************** +void DAC12_A_disableGrouping(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_DAC12_0CTL0) &= ~(DAC12GRP); +} + +//***************************************************************************** +// +//! \brief Enables the DAC12_A module interrupt source. +//! +//! This function to enable the DAC12_A module interrupt, which throws an +//! interrupt when the data buffer is available for new data to be set. Only +//! the sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. Note that an interrupt is +//! not thrown when DAC12_A_TRIGGER_AUTO has been set for the parameter +//! conversionTriggerSelect in initialization. Does not clear interrupt flags. +//! +//! \param baseAddress is the base address of the DAC12_A module. +//! \param submoduleSelect decides which DAC12_A sub-module to configure. +//! Valid values are: +//! - \b DAC12_A_SUBMODULE_0 +//! - \b DAC12_A_SUBMODULE_1 +//! +//! \return None +// +//***************************************************************************** +void DAC12_A_enableInterrupt(uint16_t baseAddress, + uint8_t submoduleSelect) +{ + assert(submoduleSelect <= DAC12_A_SUBMODULE_1); + + HWREG16(baseAddress + submoduleSelect + OFS_DAC12_0CTL0) |= DAC12IE; +} + +//***************************************************************************** +// +//! \brief Disables the DAC12_A module interrupt source. +//! +//! Enables the DAC12_A module interrupt source. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! \param baseAddress is the base address of the DAC12_A module. +//! \param submoduleSelect decides which DAC12_A sub-module to configure. +//! Valid values are: +//! - \b DAC12_A_SUBMODULE_0 +//! - \b DAC12_A_SUBMODULE_1 +//! +//! \return None +// +//***************************************************************************** +void DAC12_A_disableInterrupt(uint16_t baseAddress, + uint8_t submoduleSelect) +{ + assert(submoduleSelect <= DAC12_A_SUBMODULE_1); + + HWREG16(baseAddress + submoduleSelect + OFS_DAC12_0CTL0) &= ~(DAC12IE); +} + +//***************************************************************************** +// +//! \brief Returns the status of the DAC12_A module interrupt flag. +//! +//! This function returns the status of the DAC12_A module interrupt flag. Note +//! that an interrupt is not thrown when DAC12_A_TRIGGER_AUTO has been set for +//! the conversionTriggerSelect parameter in initialization. +//! +//! \param baseAddress is the base address of the DAC12_A module. +//! \param submoduleSelect decides which DAC12_A sub-module to configure. +//! Valid values are: +//! - \b DAC12_A_SUBMODULE_0 +//! - \b DAC12_A_SUBMODULE_1 +//! +//! \return One of the following: +//! - \b DAC12_A_INT_ACTIVE +//! - \b DAC12_A_INT_INACTIVE +//! \n indicating the status for the selected DAC12_A module +// +//***************************************************************************** +uint16_t DAC12_A_getInterruptStatus(uint16_t baseAddress, + uint8_t submoduleSelect) +{ + assert(submoduleSelect <= DAC12_A_SUBMODULE_1); + + return HWREG16(baseAddress + submoduleSelect + OFS_DAC12_0CTL0) & DAC12IFG; +} + +//***************************************************************************** +// +//! \brief Clears the DAC12_A module interrupt flag. +//! +//! The DAC12_A module interrupt flag is cleared, so that it no longer asserts. +//! Note that an interrupt is not thrown when DAC12_A_TRIGGER_AUTO has been set +//! for the parameter conversionTriggerSelect in initialization. +//! +//! \param baseAddress is the base address of the DAC12_A module. +//! \param submoduleSelect decides which DAC12_A sub-module to configure. +//! Valid values are: +//! - \b DAC12_A_SUBMODULE_0 +//! - \b DAC12_A_SUBMODULE_1 +//! +//! Modified bits are \b DAC12IFG of \b DAC12_xCTL0 register. +//! +//! \return None +// +//***************************************************************************** +void DAC12_A_clearInterrupt(uint16_t baseAddress, + uint8_t submoduleSelect) +{ + assert(submoduleSelect <= DAC12_A_SUBMODULE_1); + + HWREG16(baseAddress + submoduleSelect + OFS_DAC12_0CTL0) &= ~(DAC12IFG); +} + +//***************************************************************************** +// +//! \brief Calibrates the output offset. +//! +//! This function disables the calibration lock, starts the calibration, whats +//! for the calibration to complete, and then re-locks the calibration lock. +//! Please note, this function should be called after initializing the dac12 +//! module, and before using it. +//! +//! \param baseAddress is the base address of the DAC12_A module. +//! \param submoduleSelect decides which DAC12_A sub-module to configure. +//! Valid values are: +//! - \b DAC12_A_SUBMODULE_0 +//! - \b DAC12_A_SUBMODULE_1 +//! +//! Modified bits are \b DAC12CALON of \b DAC12_xCTL0 register; bits \b DAC12PW +//! of \b DAC12_xCALCTL register. +//! +//! \return None +// +//***************************************************************************** +void DAC12_A_calibrateOutput(uint16_t baseAddress, + uint8_t submoduleSelect) +{ + assert(submoduleSelect <= DAC12_A_SUBMODULE_1); + + //Unlock Calibration + HWREG16(baseAddress + submoduleSelect + OFS_DAC12_0CALCTL) = DAC12PW; + + //Start Calibration + HWREG16(baseAddress + submoduleSelect + OFS_DAC12_0CTL0) |= DAC12CALON; + + //Wait for Calibration to Finish + while (HWREG16(baseAddress + submoduleSelect + OFS_DAC12_0CTL0) & DAC12CALON) ; + + //Lock Calibration + HWREG16(baseAddress + submoduleSelect + + OFS_DAC12_0CALCTL) = DAC12PW + DAC12LOCK; +} + +//***************************************************************************** +// +//! \brief Returns the calibrated offset of the output buffer. +//! +//! This function returns the calibrated offset of the output buffer. The +//! output buffer offset is used to obtain accurate results from the output +//! pin. This function should only be used while the calibration lock is +//! enabled. Only the lower byte of the word of the register is returned, and +//! the value is between -128 and +127. +//! +//! \param baseAddress is the base address of the DAC12_A module. +//! \param submoduleSelect decides which DAC12_A sub-module to configure. +//! Valid values are: +//! - \b DAC12_A_SUBMODULE_0 +//! - \b DAC12_A_SUBMODULE_1 +//! +//! \return The calibrated offset of the output buffer. +// +//***************************************************************************** +uint16_t DAC12_A_getCalibrationData(uint16_t baseAddress, + uint8_t submoduleSelect) +{ + assert(submoduleSelect <= DAC12_A_SUBMODULE_1); + + return (uint16_t)(HWREG16(baseAddress + submoduleSelect + OFS_DAC12_0CALDAT)); +} + +//***************************************************************************** +// +//! \brief Returns the calibrated offset of the output buffer. +//! +//! This function is used to manually set the calibration offset value. The +//! calibration is automatically unlocked and re-locked to be able to allow for +//! the offset value to be set. +//! +//! \param baseAddress is the base address of the DAC12_A module. +//! \param submoduleSelect decides which DAC12_A sub-module to configure. +//! Valid values are: +//! - \b DAC12_A_SUBMODULE_0 +//! - \b DAC12_A_SUBMODULE_1 +//! \param calibrationOffsetValue calibration offset value +//! +//! Modified bits are \b DAC12LOCK of \b DAC12_xCALDAT register; bits \b +//! DAC12PW of \b DAC12_xCTL0 register; bits \b DAC12PW of \b DAC12_xCALCTL +//! register. +//! +//! \return None +// +//***************************************************************************** +void DAC12_A_setCalibrationOffset(uint16_t baseAddress, + uint8_t submoduleSelect, + uint16_t calibrationOffsetValue) +{ + assert(submoduleSelect <= DAC12_A_SUBMODULE_1); + + //Unlock Calibration + HWREG16(baseAddress + submoduleSelect + OFS_DAC12_0CALCTL) = DAC12PW; + + //Set Calibration Offset + HWREG16(baseAddress + submoduleSelect + OFS_DAC12_0CALDAT) = + calibrationOffsetValue; + + //Lock Calibration + HWREG16(baseAddress + submoduleSelect + + OFS_DAC12_0CALCTL) = DAC12PW + DAC12LOCK; +} + +//***************************************************************************** +// +//! \brief Enables triggers to start conversions. +//! +//! This function is used to allow triggers to start a conversion. Note that +//! this function does not need to be used if DAC12_A_TRIGGER_AUTO was set for +//! the conversionTriggerSelect parameter during initialization. If DAC +//! grouping is enabled, this has to be called for both DAC's. +//! +//! \param baseAddress is the base address of the DAC12_A module. +//! \param submoduleSelect decides which DAC12_A sub-module to configure. +//! Valid values are: +//! - \b DAC12_A_SUBMODULE_0 +//! - \b DAC12_A_SUBMODULE_1 +//! +//! Modified bits are \b DAC12ENC of \b DAC12_xCTL0 register. +//! +//! \return None +// +//***************************************************************************** +void DAC12_A_enableConversions(uint16_t baseAddress, + uint8_t submoduleSelect) +{ + assert(submoduleSelect <= DAC12_A_SUBMODULE_1); + + HWREG16(baseAddress + submoduleSelect + OFS_DAC12_0CTL0) |= DAC12ENC; +} + +//***************************************************************************** +// +//! \brief Sets the given data into the buffer to be converted. +//! +//! This function is used to set the given data into the data buffer of the +//! DAC12_A module. The data given should be in the format set (12-bit +//! Unsigned, Right-justified by default). Note if DAC12_A_TRIGGER_AUTO was set +//! for the conversionTriggerSelect during initialization then using this +//! function will set the data and automatically trigger a conversion. If any +//! other trigger was set during initialization, then the +//! DAC12_A_enableConversions() function needs to be called before a conversion +//! can be started. If grouping DAC's and DAC12_A_TRIGGER_ENC was set during +//! initialization, then both data buffers must be set before a conversion will +//! be started. +//! +//! \param baseAddress is the base address of the DAC12_A module. +//! \param submoduleSelect decides which DAC12_A sub-module to configure. +//! Valid values are: +//! - \b DAC12_A_SUBMODULE_0 +//! - \b DAC12_A_SUBMODULE_1 +//! \param data is the data to be set into the DAC12_A data buffer to be +//! converted. +//! \n Modified bits are \b DAC12_DATA of \b DAC12_xDAT register. +//! +//! Modified bits of \b DAC12_xDAT register. +//! +//! \return None +// +//***************************************************************************** +void DAC12_A_setData(uint16_t baseAddress, + uint8_t submoduleSelect, + uint16_t data) +{ + assert(submoduleSelect <= DAC12_A_SUBMODULE_1); + + HWREG16(baseAddress + submoduleSelect + OFS_DAC12_0DAT) = data; +} + +//***************************************************************************** +// +//! \brief Disables triggers to start conversions. +//! +//! This function is used to disallow triggers to start a conversion. Note that +//! this function does not have any affect if DAC12_A_TRIGGER_AUTO was set for +//! the conversionTriggerSelect parameter during initialization. +//! +//! \param baseAddress is the base address of the DAC12_A module. +//! \param submoduleSelect decides which DAC12_A sub-module to configure. +//! Valid values are: +//! - \b DAC12_A_SUBMODULE_0 +//! - \b DAC12_A_SUBMODULE_1 +//! +//! Modified bits are \b DAC12ENC of \b DAC12_xCTL0 register. +//! +//! \return None +// +//***************************************************************************** +void DAC12_A_disableConversions(uint16_t baseAddress, + uint8_t submoduleSelect) +{ + assert(submoduleSelect <= DAC12_A_SUBMODULE_1); + + HWREG16(baseAddress + submoduleSelect + OFS_DAC12_0CTL0) &= ~(DAC12ENC); +} + +//***************************************************************************** +// +//! \brief Sets the resolution to be used by the DAC12_A module. +//! +//! This function sets the resolution of the data to be converted. +//! +//! \param baseAddress is the base address of the DAC12_A module. +//! \param submoduleSelect decides which DAC12_A sub-module to configure. +//! Valid values are: +//! - \b DAC12_A_SUBMODULE_0 +//! - \b DAC12_A_SUBMODULE_1 +//! \param resolutionSelect is the resolution to use for conversions. +//! Valid values are: +//! - \b DAC12_A_RESOLUTION_8BIT +//! - \b DAC12_A_RESOLUTION_12BIT [Default] +//! \n Modified bits are \b DAC12RES of \b DAC12_xCTL0 register. +//! +//! Modified bits are \b DAC12ENC and \b DAC12RES of \b DAC12_xCTL0 register. +//! +//! \return None +// +//***************************************************************************** +void DAC12_A_setResolution(uint16_t baseAddress, + uint8_t submoduleSelect, + uint16_t resolutionSelect) +{ + assert(submoduleSelect <= DAC12_A_SUBMODULE_1); + assert(resolutionSelect <= DAC12_A_RESOLUTION_12BIT); + + //Store the ENC bit status + uint16_t conversionsEnabledStatus = + ( HWREG16(baseAddress + OFS_DAC12_0CTL0) & (DAC12ENC) ); + + baseAddress += submoduleSelect; //Add 0x10 to base address IF + //DAC12_A_1 is selected. + + if (DAC12_A_RESOLUTION_8BIT == resolutionSelect) + HWREG16(baseAddress + OFS_DAC12_0CTL0) |= DAC12RES; + else if (DAC12_A_RESOLUTION_12BIT == resolutionSelect) + HWREG16(baseAddress + OFS_DAC12_0CTL0) &= ~(DAC12RES); + + //Restore the ENC bit status + HWREG16(baseAddress + OFS_DAC12_0CTL0) |= conversionsEnabledStatus; +} + +//***************************************************************************** +// +//! \brief Sets the input data format for the DAC12_A module. +//! +//! This function sets the input format for the binary data to be converted. +//! +//! \param baseAddress is the base address of the DAC12_A module. +//! \param submoduleSelect decides which DAC12_A sub-module to configure. +//! Valid values are: +//! - \b DAC12_A_SUBMODULE_0 +//! - \b DAC12_A_SUBMODULE_1 +//! \param inputJustification is the justification of the data to be converted. +//! Valid values are: +//! - \b DAC12_A_JUSTIFICATION_RIGHT [Default] +//! - \b DAC12_A_JUSTIFICATION_LEFT +//! \n Modified bits are \b DAC12DFJ of \b DAC12_xCTL1 register. +//! \param inputSign is the sign of the data to be converted. +//! Valid values are: +//! - \b DAC12_A_UNSIGNED_BINARY [Default] +//! - \b DAC12_A_SIGNED_2SCOMPLEMENT +//! \n Modified bits are \b DAC12DF of \b DAC12_xCTL0 register. +//! +//! \return None +// +//***************************************************************************** +void DAC12_A_setInputDataFormat(uint16_t baseAddress, + uint8_t submoduleSelect, + uint8_t inputJustification, + uint8_t inputSign) +{ + assert(submoduleSelect <= DAC12_A_SUBMODULE_1); + assert(inputJustification <= DAC12_A_JUSTIFICATION_LEFT); + assert(inputSign <= DAC12_A_SIGNED_2SCOMPLEMENT); + + //Store the ENC bit status + uint16_t conversionsEnabledStatus = + ( HWREG16(baseAddress + OFS_DAC12_0CTL0) & (DAC12ENC) ); + + baseAddress += submoduleSelect; //Add 0x10 to base address IF + //DAC12_A_1 is selected. + + if (DAC12_A_JUSTIFICATION_LEFT == inputJustification) + HWREG16(baseAddress + OFS_DAC12_0CTL1) |= DAC12DFJ; + else if (DAC12_A_JUSTIFICATION_RIGHT == inputJustification) + HWREG16(baseAddress + OFS_DAC12_0CTL1) &= ~(DAC12DFJ); + + if (DAC12_A_SIGNED_2SCOMPLEMENT == inputSign) + HWREG16(baseAddress + OFS_DAC12_0CTL0) |= DAC12DF; + else if (DAC12_A_UNSIGNED_BINARY == inputSign) + HWREG16(baseAddress + OFS_DAC12_0CTL0) &= ~(DAC12DF); + + //Restore the ENC bit status + HWREG16(baseAddress + OFS_DAC12_0CTL0) |= conversionsEnabledStatus; +} + +//***************************************************************************** +// +//! \brief Returns the address of the specified DAC12_A data buffer for the DMA +//! module. +//! +//! Returns the address of the specified memory buffer. This can be used in +//! conjunction with the DMA to obtain the data directly from memory. +//! +//! \param baseAddress is the base address of the DAC12_A module. +//! \param submoduleSelect decides which DAC12_A sub-module to configure. +//! Valid values are: +//! - \b DAC12_A_SUBMODULE_0 +//! - \b DAC12_A_SUBMODULE_1 +//! +//! \return The address of the specified memory buffer +// +//***************************************************************************** +uint32_t DAC12_A_getDataBufferMemoryAddressForDMA(uint16_t baseAddress, + uint8_t submoduleSelect) +{ + assert(submoduleSelect <= DAC12_A_SUBMODULE_1); + return baseAddress + submoduleSelect + OFS_DAC12_0DAT; +} + + +#endif +//***************************************************************************** +// +//! Close the doxygen group for dac12_a_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/dac12_a.h b/source/driverlib/MSP430F5xx_6xx/dac12_a.h new file mode 100644 index 0000000..649310f --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/dac12_a.h @@ -0,0 +1,263 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// dac12_a.h - Driver for the DAC12_A Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_DAC12_A_H__ +#define __MSP430WARE_DAC12_A_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_DAC12_2__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//****************************************************************************** +// +// The following is a struct that is passed to DAC12_A_initialize() +// +//****************************************************************************** +typedef struct DAC12_A_initializeParam { + uint8_t submoduleSelect; + uint16_t outputSelect; + uint16_t positiveReferenceVoltage; + uint16_t outputVoltageMultiplier; + uint8_t amplifierSetting; + uint16_t conversionTriggerSelect; +} DAC12_A_initializeParam; + +//***************************************************************************** +// +// The following are values that can be passed to the positiveReferenceVoltage +// parameter for functions: DAC12_A_init(). +// +//***************************************************************************** +#define DAC12_A_VREF_AVCC (DAC12SREF_1) +#define DAC12_A_VREF_INT (DAC12SREF_0) +#define DAC12_A_VREF_EXT (DAC12SREF_2) + +//***************************************************************************** +// +// The following are values that can be passed to the amplifierSetting +// parameter for functions: DAC12_A_init(), and DAC12_A_setAmplifierSetting(). +// +//***************************************************************************** +#define DAC12_A_AMP_OFF_PINOUTHIGHZ (DAC12AMP_0) +#define DAC12_A_AMP_OFF_PINOUTLOW (DAC12AMP_1) +#define DAC12_A_AMP_LOWIN_LOWOUT (DAC12AMP_2) +#define DAC12_A_AMP_LOWIN_MEDOUT (DAC12AMP_3) +#define DAC12_A_AMP_LOWIN_HIGHOUT (DAC12AMP_4) +#define DAC12_A_AMP_MEDIN_MEDOUT (DAC12AMP_5) +#define DAC12_A_AMP_MEDIN_HIGHOUT (DAC12AMP_6) +#define DAC12_A_AMP_HIGHIN_HIGHOUT (DAC12AMP_7) + +//***************************************************************************** +// +// The following are values that can be passed to the outputSelect parameter +// for functions: DAC12_A_init(). +// +//***************************************************************************** +#define DAC12_A_OUTPUT_1 (!(DAC12OPS)) +#define DAC12_A_OUTPUT_2 (DAC12OPS) + +//***************************************************************************** +// +// The following are values that can be passed to the submoduleSelect parameter +// for functions: DAC12_A_init(), DAC12_A_setAmplifierSetting(), +// DAC12_A_disable(), DAC12_A_enableInterrupt(), DAC12_A_disableInterrupt(), +// DAC12_A_getInterruptStatus(), DAC12_A_clearInterrupt(), +// DAC12_A_calibrateOutput(), DAC12_A_getCalibrationData(), +// DAC12_A_setCalibrationOffset(), DAC12_A_enableConversions(), +// DAC12_A_setData(), DAC12_A_disableConversions(), DAC12_A_setResolution(), +// DAC12_A_setInputDataFormat(), and +// DAC12_A_getDataBufferMemoryAddressForDMA(). +// +//***************************************************************************** +#define DAC12_A_SUBMODULE_0 (0x00) +#define DAC12_A_SUBMODULE_1 (0x10) + +//***************************************************************************** +// +// The following are values that can be passed to the outputVoltageMultiplier +// parameter for functions: DAC12_A_init(). +// +//***************************************************************************** +#define DAC12_A_VREFx1 (DAC12IR) +#define DAC12_A_VREFx2 (DAC12OG) +#define DAC12_A_VREFx3 (0x0) + +//***************************************************************************** +// +// The following are values that can be passed to the conversionTriggerSelect +// parameter for functions: DAC12_A_init(). +// +//***************************************************************************** +#define DAC12_A_TRIGGER_ENCBYPASS (DAC12LSEL_0) +#define DAC12_A_TRIGGER_ENC (DAC12LSEL_1) +#define DAC12_A_TRIGGER_TA (DAC12LSEL_2) +#define DAC12_A_TRIGGER_TB (DAC12LSEL_3) + +//***************************************************************************** +// +// The following are values that can be passed to the resolutionSelect +// parameter for functions: DAC12_A_setResolution(). +// +//***************************************************************************** +#define DAC12_A_RESOLUTION_8BIT (DAC12RES) +#define DAC12_A_RESOLUTION_12BIT (!(DAC12RES)) + +//***************************************************************************** +// +// The following are values that can be passed to the inputJustification +// parameter for functions: DAC12_A_setInputDataFormat(). +// +//***************************************************************************** +#define DAC12_A_JUSTIFICATION_RIGHT (!(DAC12DFJ)) +#define DAC12_A_JUSTIFICATION_LEFT (DAC12DFJ) + +//***************************************************************************** +// +// The following are values that can be passed to the inputSign parameter for +// functions: DAC12_A_setInputDataFormat(). +// +//***************************************************************************** +#define DAC12_A_UNSIGNED_BINARY (!(DAC12DF)) +#define DAC12_A_SIGNED_2SCOMPLEMENT (DAC12DF) + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the DAC12_A_getInterruptStatus() function. +// +//***************************************************************************** +#define DAC12_A_INT_ACTIVE (DAC12IFG) +#define DAC12_A_INT_INACTIVE (0x00) + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern bool DAC12_A_initialize(uint16_t baseAddress, + DAC12_A_initializeParam *param); + +extern void DAC12_A_setAmplifierSetting(uint16_t baseAddress, + uint8_t submoduleSelect, + uint8_t amplifierSetting); + +extern void DAC12_A_disable(uint16_t baseAddress, + uint8_t submoduleSelect); + +extern void DAC12_A_enableGrouping(uint16_t baseAddress); + +extern void DAC12_A_disableGrouping(uint16_t baseAddress); + +extern void DAC12_A_enableInterrupt(uint16_t baseAddress, + uint8_t submoduleSelect); + +extern void DAC12_A_disableInterrupt(uint16_t baseAddress, + uint8_t submoduleSelect); + +extern uint16_t DAC12_A_getInterruptStatus(uint16_t baseAddress, + uint8_t submoduleSelect); + +extern void DAC12_A_clearInterrupt(uint16_t baseAddress, + uint8_t submoduleSelect); + +extern void DAC12_A_calibrateOutput(uint16_t baseAddress, + uint8_t submoduleSelect); + +extern uint16_t DAC12_A_getCalibrationData(uint16_t baseAddress, + uint8_t submoduleSelect); + +extern void DAC12_A_setCalibrationOffset(uint16_t baseAddress, + uint8_t submoduleSelect, + uint16_t calibrationOffsetValue); + +extern void DAC12_A_enableConversions(uint16_t baseAddress, + uint8_t submoduleSelect); + +extern void DAC12_A_setData(uint16_t baseAddress, + uint8_t submoduleSelect, + uint16_t data); + +extern void DAC12_A_disableConversions(uint16_t baseAddress, + uint8_t submoduleSelect); + +extern void DAC12_A_setResolution(uint16_t baseAddress, + uint8_t submoduleSelect, + uint16_t resolutionSelect); + +extern void DAC12_A_setInputDataFormat(uint16_t baseAddress, + uint8_t submoduleSelect, + uint8_t inputJustification, + uint8_t inputSign); + +extern uint32_t DAC12_A_getDataBufferMemoryAddressForDMA(uint16_t baseAddress, + uint8_t submoduleSelect); + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +extern bool DAC12_A_init(uint16_t baseAddress, + uint8_t submoduleSelect, + uint16_t outputSelect, + uint16_t positiveReferenceVoltage, + uint16_t outputVoltageMultiplier, + uint8_t amplifierSetting, + uint16_t conversionTriggerSelect); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_DAC12_A_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/deprecated/CCS/msp430f5xx_6xxgeneric.h b/source/driverlib/MSP430F5xx_6xx/deprecated/CCS/msp430f5xx_6xxgeneric.h new file mode 100644 index 0000000..3a7db7f --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/deprecated/CCS/msp430f5xx_6xxgeneric.h @@ -0,0 +1,9977 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +/* ============================================================================ */ +/* Copyright (c) 2013, Texas Instruments Incorporated */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* * Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* * Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in the */ +/* documentation and/or other materials provided with the distribution. */ +/* */ +/* * Neither the name of Texas Instruments Incorporated nor the names of */ +/* its contributors may be used to endorse or promote products derived */ +/* from this software without specific prior written permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ +/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */ +/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */ +/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */ +/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */ +/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */ +/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */ +/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ +/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */ +/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ============================================================================ */ + +/******************************************************************** +* +* Standard register and bit definitions for the Texas Instruments +* MSP430 microcontroller. +* +* This file supports assembler and C development for +* MSP430F5XX_F6XXGENERIC device. +* +* Texas Instruments, Version 1.0 +* +* Rev. 1.0, Setup +* +* +********************************************************************/ + +#ifndef __msp430F5XX_F6XXGENERIC +#define __msp430F5XX_F6XXGENERIC + +//#define __MSP430_HEADER_VERSION__ 1125 + +#ifdef __cplusplus +extern "C" { +#endif + + +/*----------------------------------------------------------------------------*/ +/* PERIPHERAL FILE MAP */ +/*----------------------------------------------------------------------------*/ + +#ifndef SFR_8BIT +/* External references resolved by a device-specific linker command file */ +#define SFR_8BIT(address) extern volatile unsigned char address +#define SFR_16BIT(address) extern volatile unsigned int address +//#define SFR_20BIT(address) extern volatile unsigned int address +typedef void (* __SFR_FARPTR)(); +#define SFR_20BIT(address) extern __SFR_FARPTR address +#define SFR_32BIT(address) extern volatile unsigned long address + +#endif + + +/************************************************************ +* STANDARD BITS +************************************************************/ + +#define BIT0 (0x0001) +#define BIT1 (0x0002) +#define BIT2 (0x0004) +#define BIT3 (0x0008) +#define BIT4 (0x0010) +#define BIT5 (0x0020) +#define BIT6 (0x0040) +#define BIT7 (0x0080) +#define BIT8 (0x0100) +#define BIT9 (0x0200) +#define BITA (0x0400) +#define BITB (0x0800) +#define BITC (0x1000) +#define BITD (0x2000) +#define BITE (0x4000) +#define BITF (0x8000) + +/************************************************************ +* STATUS REGISTER BITS +************************************************************/ + +#define C (0x0001) +#define Z (0x0002) +#define N (0x0004) +#define V (0x0100) +#define GIE (0x0008) +#define CPUOFF (0x0010) +#define OSCOFF (0x0020) +#define SCG0 (0x0040) +#define SCG1 (0x0080) + +/* Low Power Modes coded with Bits 4-7 in SR */ + +#ifdef __ASM_HEADER__ /* Begin #defines for assembler */ +#define LPM0 (CPUOFF) +#define LPM1 (SCG0+CPUOFF) +#define LPM2 (SCG1+CPUOFF) +#define LPM3 (SCG1+SCG0+CPUOFF) +#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF) +/* End #defines for assembler */ + +#else /* Begin #defines for C */ +#define LPM0_bits (CPUOFF) +#define LPM1_bits (SCG0+CPUOFF) +#define LPM2_bits (SCG1+CPUOFF) +#define LPM3_bits (SCG1+SCG0+CPUOFF) +#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF) + +#include "in430.h" +#include + +#if __MSP430_HEADER_VERSION__ < 1107 + #define LPM0 _bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */ + #define LPM0_EXIT _bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */ + #define LPM1 _bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */ + #define LPM1_EXIT _bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */ + #define LPM2 _bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */ + #define LPM2_EXIT _bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */ + #define LPM3 _bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */ + #define LPM3_EXIT _bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */ + #define LPM4 _bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */ + #define LPM4_EXIT _bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */ +#else + #define LPM0 __bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */ + #define LPM0_EXIT __bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */ + #define LPM1 __bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */ + #define LPM1_EXIT __bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */ + #define LPM2 __bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */ + #define LPM2_EXIT __bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */ + #define LPM3 __bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */ + #define LPM3_EXIT __bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */ + #define LPM4 __bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */ + #define LPM4_EXIT __bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */ +#endif + +#endif /* End #defines for C */ + +/************************************************************ +* CPU +************************************************************/ +#define __MSP430_HAS_MSP430XV2_CPU__ /* Definition to show that it has MSP430XV2 CPU */ + +#if defined(__MSP430_HAS_T0A2__) || defined(__MSP430_HAS_T1A2__) || defined(__MSP430_HAS_T2A2__) || defined(__MSP430_HAS_T3A2__) \ + || defined(__MSP430_HAS_T0A3__) || defined(__MSP430_HAS_T1A3__) || defined(__MSP430_HAS_T2A3__) || defined(__MSP430_HAS_T3A3__) \ + || defined(__MSP430_HAS_T0A5__) || defined(__MSP430_HAS_T1A5__) || defined(__MSP430_HAS_T2A5__) || defined(__MSP430_HAS_T3A5__) \ + || defined(__MSP430_HAS_T0A7__) || defined(__MSP430_HAS_T1A7__) || defined(__MSP430_HAS_T2A7__) || defined(__MSP430_HAS_T3A7__) + #define __MSP430_HAS_TxA7__ +#endif +#if defined(__MSP430_HAS_T0B3__) || defined(__MSP430_HAS_T0B5__) || defined(__MSP430_HAS_T0B7__) \ + || defined(__MSP430_HAS_T1B3__) || defined(__MSP430_HAS_T1B5__) || defined(__MSP430_HAS_T1B7__) + #define __MSP430_HAS_TxB7__ +#endif +#if defined(__MSP430_HAS_T0D3__) || defined(__MSP430_HAS_T0D5__) || defined(__MSP430_HAS_T0D7__) \ + || defined(__MSP430_HAS_T1D3__) || defined(__MSP430_HAS_T1D5__) || defined(__MSP430_HAS_T1D7__) + #define __MSP430_HAS_TxD7__ +#endif +#if defined(__MSP430_HAS_USCI_A0__) || defined(__MSP430_HAS_USCI_A1__) || defined(__MSP430_HAS_USCI_A2__) || defined(__MSP430_HAS_USCI_A3__) + #define __MSP430_HAS_USCI_Ax__ +#endif +#if defined(__MSP430_HAS_USCI_B0__) || defined(__MSP430_HAS_USCI_B1__) || defined(__MSP430_HAS_USCI_B2__) || defined(__MSP430_HAS_USCI_B3__) + #define __MSP430_HAS_USCI_Bx__ +#endif +#if defined(__MSP430_HAS_EUSCI_A0__) || defined(__MSP430_HAS_EUSCI_A1__) || defined(__MSP430_HAS_EUSCI_A2__) || defined(__MSP430_HAS_EUSCI_A3__) + #define __MSP430_HAS_EUSCI_Ax__ +#endif +#if defined(__MSP430_HAS_EUSCI_B0__) || defined(__MSP430_HAS_EUSCI_B1__) || defined(__MSP430_HAS_EUSCI_B2__) || defined(__MSP430_HAS_EUSCI_B3__) + #define __MSP430_HAS_EUSCI_Bx__ +#endif +#ifdef __MSP430_HAS_EUSCI_B0__ + #define __MSP430_HAS_EUSCI_Bx__ +#endif + +/************************************************************ +* ADC10_A +************************************************************/ +#ifdef __MSP430_HAS_ADC10_A__ /* Definition to show that Module is available */ + +#define OFS_ADC10CTL0 (0x0000) /* ADC10 Control 0 */ +#define OFS_ADC10CTL0_L OFS_ADC10CTL0 +#define OFS_ADC10CTL0_H OFS_ADC10CTL0+1 +#define OFS_ADC10CTL1 (0x0002) /* ADC10 Control 1 */ +#define OFS_ADC10CTL1_L OFS_ADC10CTL1 +#define OFS_ADC10CTL1_H OFS_ADC10CTL1+1 +#define OFS_ADC10CTL2 (0x0004) /* ADC10 Control 2 */ +#define OFS_ADC10CTL2_L OFS_ADC10CTL2 +#define OFS_ADC10CTL2_H OFS_ADC10CTL2+1 +#define OFS_ADC10LO (0x0006) /* ADC10 Window Comparator High Threshold */ +#define OFS_ADC10LO_L OFS_ADC10LO +#define OFS_ADC10LO_H OFS_ADC10LO+1 +#define OFS_ADC10HI (0x0008) /* ADC10 Window Comparator High Threshold */ +#define OFS_ADC10HI_L OFS_ADC10HI +#define OFS_ADC10HI_H OFS_ADC10HI+1 +#define OFS_ADC10MCTL0 (0x000A) /* ADC10 Memory Control 0 */ +#define OFS_ADC10MCTL0_L OFS_ADC10MCTL0 +#define OFS_ADC10MCTL0_H OFS_ADC10MCTL0+1 +#define OFS_ADC10MEM0 (0x0012) /* ADC10 Conversion Memory 0 */ +#define OFS_ADC10MEM0_L OFS_ADC10MEM0 +#define OFS_ADC10MEM0_H OFS_ADC10MEM0+1 +#define OFS_ADC10IE (0x001A) /* ADC10 Interrupt Enable */ +#define OFS_ADC10IE_L OFS_ADC10IE +#define OFS_ADC10IE_H OFS_ADC10IE+1 +#define OFS_ADC10IFG (0x001C) /* ADC10 Interrupt Flag */ +#define OFS_ADC10IFG_L OFS_ADC10IFG +#define OFS_ADC10IFG_H OFS_ADC10IFG+1 +#define OFS_ADC10IV (0x001E) /* ADC10 Interrupt Vector Word */ +#define OFS_ADC10IV_L OFS_ADC10IV +#define OFS_ADC10IV_H OFS_ADC10IV+1 + +/* ADC10CTL0 Control Bits */ +#define ADC10SC (0x0001) /* ADC10 Start Conversion */ +#define ADC10ENC (0x0002) /* ADC10 Enable Conversion */ +#define ADC10ON (0x0010) /* ADC10 On/enable */ +#define ADC10MSC (0x0080) /* ADC10 Multiple SampleConversion */ +#define ADC10SHT0 (0x0100) /* ADC10 Sample Hold Select Bit: 0 */ +#define ADC10SHT1 (0x0200) /* ADC10 Sample Hold Select Bit: 1 */ +#define ADC10SHT2 (0x0400) /* ADC10 Sample Hold Select Bit: 2 */ +#define ADC10SHT3 (0x0800) /* ADC10 Sample Hold Select Bit: 3 */ + +/* ADC10CTL0 Control Bits */ +#define ADC10SC_L (0x0001) /* ADC10 Start Conversion */ +#define ADC10ENC_L (0x0002) /* ADC10 Enable Conversion */ +#define ADC10ON_L (0x0010) /* ADC10 On/enable */ +#define ADC10MSC_L (0x0080) /* ADC10 Multiple SampleConversion */ + +/* ADC10CTL0 Control Bits */ +#define ADC10SHT0_H (0x0001) /* ADC10 Sample Hold Select Bit: 0 */ +#define ADC10SHT1_H (0x0002) /* ADC10 Sample Hold Select Bit: 1 */ +#define ADC10SHT2_H (0x0004) /* ADC10 Sample Hold Select Bit: 2 */ +#define ADC10SHT3_H (0x0008) /* ADC10 Sample Hold Select Bit: 3 */ + +#define ADC10SHT_0 (0*0x100u) /* ADC10 Sample Hold Select 0 */ +#define ADC10SHT_1 (1*0x100u) /* ADC10 Sample Hold Select 1 */ +#define ADC10SHT_2 (2*0x100u) /* ADC10 Sample Hold Select 2 */ +#define ADC10SHT_3 (3*0x100u) /* ADC10 Sample Hold Select 3 */ +#define ADC10SHT_4 (4*0x100u) /* ADC10 Sample Hold Select 4 */ +#define ADC10SHT_5 (5*0x100u) /* ADC10 Sample Hold Select 5 */ +#define ADC10SHT_6 (6*0x100u) /* ADC10 Sample Hold Select 6 */ +#define ADC10SHT_7 (7*0x100u) /* ADC10 Sample Hold Select 7 */ +#define ADC10SHT_8 (8*0x100u) /* ADC10 Sample Hold Select 8 */ +#define ADC10SHT_9 (9*0x100u) /* ADC10 Sample Hold Select 9 */ +#define ADC10SHT_10 (10*0x100u) /* ADC10 Sample Hold Select 10 */ +#define ADC10SHT_11 (11*0x100u) /* ADC10 Sample Hold Select 11 */ +#define ADC10SHT_12 (12*0x100u) /* ADC10 Sample Hold Select 12 */ +#define ADC10SHT_13 (13*0x100u) /* ADC10 Sample Hold Select 13 */ +#define ADC10SHT_14 (14*0x100u) /* ADC10 Sample Hold Select 14 */ +#define ADC10SHT_15 (15*0x100u) /* ADC10 Sample Hold Select 15 */ + +/* ADC10CTL1 Control Bits */ +#define ADC10BUSY (0x0001) /* ADC10 Busy */ +#define ADC10CONSEQ0 (0x0002) /* ADC10 Conversion Sequence Select 0 */ +#define ADC10CONSEQ1 (0x0004) /* ADC10 Conversion Sequence Select 1 */ +#define ADC10SSEL0 (0x0008) /* ADC10 Clock Source Select 0 */ +#define ADC10SSEL1 (0x0010) /* ADC10 Clock Source Select 1 */ +#define ADC10DIV0 (0x0020) /* ADC10 Clock Divider Select 0 */ +#define ADC10DIV1 (0x0040) /* ADC10 Clock Divider Select 1 */ +#define ADC10DIV2 (0x0080) /* ADC10 Clock Divider Select 2 */ +#define ADC10ISSH (0x0100) /* ADC10 Invert Sample Hold Signal */ +#define ADC10SHP (0x0200) /* ADC10 Sample/Hold Pulse Mode */ +#define ADC10SHS0 (0x0400) /* ADC10 Sample/Hold Source 0 */ +#define ADC10SHS1 (0x0800) /* ADC10 Sample/Hold Source 1 */ + +/* ADC10CTL1 Control Bits */ +#define ADC10BUSY_L (0x0001) /* ADC10 Busy */ +#define ADC10CONSEQ0_L (0x0002) /* ADC10 Conversion Sequence Select 0 */ +#define ADC10CONSEQ1_L (0x0004) /* ADC10 Conversion Sequence Select 1 */ +#define ADC10SSEL0_L (0x0008) /* ADC10 Clock Source Select 0 */ +#define ADC10SSEL1_L (0x0010) /* ADC10 Clock Source Select 1 */ +#define ADC10DIV0_L (0x0020) /* ADC10 Clock Divider Select 0 */ +#define ADC10DIV1_L (0x0040) /* ADC10 Clock Divider Select 1 */ +#define ADC10DIV2_L (0x0080) /* ADC10 Clock Divider Select 2 */ + +/* ADC10CTL1 Control Bits */ +#define ADC10ISSH_H (0x0001) /* ADC10 Invert Sample Hold Signal */ +#define ADC10SHP_H (0x0002) /* ADC10 Sample/Hold Pulse Mode */ +#define ADC10SHS0_H (0x0004) /* ADC10 Sample/Hold Source 0 */ +#define ADC10SHS1_H (0x0008) /* ADC10 Sample/Hold Source 1 */ + +#define ADC10CONSEQ_0 (0*2u) /* ADC10 Conversion Sequence Select: 0 */ +#define ADC10CONSEQ_1 (1*2u) /* ADC10 Conversion Sequence Select: 1 */ +#define ADC10CONSEQ_2 (2*2u) /* ADC10 Conversion Sequence Select: 2 */ +#define ADC10CONSEQ_3 (3*2u) /* ADC10 Conversion Sequence Select: 3 */ + +#define ADC10SSEL_0 (0*8u) /* ADC10 Clock Source Select: 0 */ +#define ADC10SSEL_1 (1*8u) /* ADC10 Clock Source Select: 1 */ +#define ADC10SSEL_2 (2*8u) /* ADC10 Clock Source Select: 2 */ +#define ADC10SSEL_3 (3*8u) /* ADC10 Clock Source Select: 3 */ + +#define ADC10DIV_0 (0*0x20u) /* ADC10 Clock Divider Select: 0 */ +#define ADC10DIV_1 (1*0x20u) /* ADC10 Clock Divider Select: 1 */ +#define ADC10DIV_2 (2*0x20u) /* ADC10 Clock Divider Select: 2 */ +#define ADC10DIV_3 (3*0x20u) /* ADC10 Clock Divider Select: 3 */ +#define ADC10DIV_4 (4*0x20u) /* ADC10 Clock Divider Select: 4 */ +#define ADC10DIV_5 (5*0x20u) /* ADC10 Clock Divider Select: 5 */ +#define ADC10DIV_6 (6*0x20u) /* ADC10 Clock Divider Select: 6 */ +#define ADC10DIV_7 (7*0x20u) /* ADC10 Clock Divider Select: 7 */ + +#define ADC10SHS_0 (0*0x400u) /* ADC10 Sample/Hold Source: 0 */ +#define ADC10SHS_1 (1*0x400u) /* ADC10 Sample/Hold Source: 1 */ +#define ADC10SHS_2 (2*0x400u) /* ADC10 Sample/Hold Source: 2 */ +#define ADC10SHS_3 (3*0x400u) /* ADC10 Sample/Hold Source: 3 */ + +/* ADC10CTL2 Control Bits */ +#define ADC10REFBURST (0x0001) /* ADC10 Reference Burst */ +#define ADC10SR (0x0004) /* ADC10 Sampling Rate */ +#define ADC10DF (0x0008) /* ADC10 Data Format */ +#define ADC10RES (0x0010) /* ADC10 Resolution Bit */ +#define ADC10PDIV0 (0x0100) /* ADC10 predivider Bit: 0 */ +#define ADC10PDIV1 (0x0200) /* ADC10 predivider Bit: 1 */ + +/* ADC10CTL2 Control Bits */ +#define ADC10REFBURST_L (0x0001) /* ADC10 Reference Burst */ +#define ADC10SR_L (0x0004) /* ADC10 Sampling Rate */ +#define ADC10DF_L (0x0008) /* ADC10 Data Format */ +#define ADC10RES_L (0x0010) /* ADC10 Resolution Bit */ + +/* ADC10CTL2 Control Bits */ +#define ADC10PDIV0_H (0x0001) /* ADC10 predivider Bit: 0 */ +#define ADC10PDIV1_H (0x0002) /* ADC10 predivider Bit: 1 */ + +#define ADC10PDIV_0 (0x0000) /* ADC10 predivider /1 */ +#define ADC10PDIV_1 (0x0100) /* ADC10 predivider /2 */ +#define ADC10PDIV_2 (0x0200) /* ADC10 predivider /64 */ +#define ADC10PDIV_3 (0x0300) /* ADC10 predivider reserved */ + +#define ADC10PDIV__1 (0x0000) /* ADC10 predivider /1 */ +#define ADC10PDIV__4 (0x0100) /* ADC10 predivider /2 */ +#define ADC10PDIV__64 (0x0200) /* ADC10 predivider /64 */ + +/* ADC10MCTL0 Control Bits */ +#define ADC10INCH0 (0x0001) /* ADC10 Input Channel Select Bit 0 */ +#define ADC10INCH1 (0x0002) /* ADC10 Input Channel Select Bit 1 */ +#define ADC10INCH2 (0x0004) /* ADC10 Input Channel Select Bit 2 */ +#define ADC10INCH3 (0x0008) /* ADC10 Input Channel Select Bit 3 */ +#define ADC10SREF0 (0x0010) /* ADC10 Select Reference Bit 0 */ +#define ADC10SREF1 (0x0020) /* ADC10 Select Reference Bit 1 */ +#define ADC10SREF2 (0x0040) /* ADC10 Select Reference Bit 2 */ + +/* ADC10MCTL0 Control Bits */ +#define ADC10INCH0_L (0x0001) /* ADC10 Input Channel Select Bit 0 */ +#define ADC10INCH1_L (0x0002) /* ADC10 Input Channel Select Bit 1 */ +#define ADC10INCH2_L (0x0004) /* ADC10 Input Channel Select Bit 2 */ +#define ADC10INCH3_L (0x0008) /* ADC10 Input Channel Select Bit 3 */ +#define ADC10SREF0_L (0x0010) /* ADC10 Select Reference Bit 0 */ +#define ADC10SREF1_L (0x0020) /* ADC10 Select Reference Bit 1 */ +#define ADC10SREF2_L (0x0040) /* ADC10 Select Reference Bit 2 */ + +#define ADC10INCH_0 (0) /* ADC10 Input Channel 0 */ +#define ADC10INCH_1 (1) /* ADC10 Input Channel 1 */ +#define ADC10INCH_2 (2) /* ADC10 Input Channel 2 */ +#define ADC10INCH_3 (3) /* ADC10 Input Channel 3 */ +#define ADC10INCH_4 (4) /* ADC10 Input Channel 4 */ +#define ADC10INCH_5 (5) /* ADC10 Input Channel 5 */ +#define ADC10INCH_6 (6) /* ADC10 Input Channel 6 */ +#define ADC10INCH_7 (7) /* ADC10 Input Channel 7 */ +#define ADC10INCH_8 (8) /* ADC10 Input Channel 8 */ +#define ADC10INCH_9 (9) /* ADC10 Input Channel 9 */ +#define ADC10INCH_10 (10) /* ADC10 Input Channel 10 */ +#define ADC10INCH_11 (11) /* ADC10 Input Channel 11 */ +#define ADC10INCH_12 (12) /* ADC10 Input Channel 12 */ +#define ADC10INCH_13 (13) /* ADC10 Input Channel 13 */ +#define ADC10INCH_14 (14) /* ADC10 Input Channel 14 */ +#define ADC10INCH_15 (15) /* ADC10 Input Channel 15 */ + +#define ADC10SREF_0 (0*0x10u) /* ADC10 Select Reference 0 */ +#define ADC10SREF_1 (1*0x10u) /* ADC10 Select Reference 1 */ +#define ADC10SREF_2 (2*0x10u) /* ADC10 Select Reference 2 */ +#define ADC10SREF_3 (3*0x10u) /* ADC10 Select Reference 3 */ +#define ADC10SREF_4 (4*0x10u) /* ADC10 Select Reference 4 */ +#define ADC10SREF_5 (5*0x10u) /* ADC10 Select Reference 5 */ +#define ADC10SREF_6 (6*0x10u) /* ADC10 Select Reference 6 */ +#define ADC10SREF_7 (7*0x10u) /* ADC10 Select Reference 7 */ + +/* ADC10IE Interrupt Enable Bits */ +#define ADC10IE0 (0x0001) /* ADC10_A Interrupt enable */ +#define ADC10INIE (0x0002) /* ADC10_A Interrupt enable for the inside of window of the Window comparator */ +#define ADC10LOIE (0x0004) /* ADC10_A Interrupt enable for lower threshold of the Window comparator */ +#define ADC10HIIE (0x0008) /* ADC10_A Interrupt enable for upper threshold of the Window comparator */ +#define ADC10OVIE (0x0010) /* ADC10_A ADC10MEM overflow Interrupt enable */ +#define ADC10TOVIE (0x0020) /* ADC10_A conversion-time-overflow Interrupt enable */ + +/* ADC10IE Interrupt Enable Bits */ +#define ADC10IE0_L (0x0001) /* ADC10_A Interrupt enable */ +#define ADC10INIE_L (0x0002) /* ADC10_A Interrupt enable for the inside of window of the Window comparator */ +#define ADC10LOIE_L (0x0004) /* ADC10_A Interrupt enable for lower threshold of the Window comparator */ +#define ADC10HIIE_L (0x0008) /* ADC10_A Interrupt enable for upper threshold of the Window comparator */ +#define ADC10OVIE_L (0x0010) /* ADC10_A ADC10MEM overflow Interrupt enable */ +#define ADC10TOVIE_L (0x0020) /* ADC10_A conversion-time-overflow Interrupt enable */ + +/* ADC10IFG Interrupt Flag Bits */ +#define ADC10IFG0 (0x0001) /* ADC10_A Interrupt Flag */ +#define ADC10INIFG (0x0002) /* ADC10_A Interrupt Flag for the inside of window of the Window comparator */ +#define ADC10LOIFG (0x0004) /* ADC10_A Interrupt Flag for lower threshold of the Window comparator */ +#define ADC10HIIFG (0x0008) /* ADC10_A Interrupt Flag for upper threshold of the Window comparator */ +#define ADC10OVIFG (0x0010) /* ADC10_A ADC10MEM overflow Interrupt Flag */ +#define ADC10TOVIFG (0x0020) /* ADC10_A conversion-time-overflow Interrupt Flag */ + +/* ADC10IFG Interrupt Flag Bits */ +#define ADC10IFG0_L (0x0001) /* ADC10_A Interrupt Flag */ +#define ADC10INIFG_L (0x0002) /* ADC10_A Interrupt Flag for the inside of window of the Window comparator */ +#define ADC10LOIFG_L (0x0004) /* ADC10_A Interrupt Flag for lower threshold of the Window comparator */ +#define ADC10HIIFG_L (0x0008) /* ADC10_A Interrupt Flag for upper threshold of the Window comparator */ +#define ADC10OVIFG_L (0x0010) /* ADC10_A ADC10MEM overflow Interrupt Flag */ +#define ADC10TOVIFG_L (0x0020) /* ADC10_A conversion-time-overflow Interrupt Flag */ + +/* ADC10IV Definitions */ +#define ADC10IV_NONE (0x0000) /* No Interrupt pending */ +#define ADC10IV_ADC10OVIFG (0x0002) /* ADC10OVIFG */ +#define ADC10IV_ADC10TOVIFG (0x0004) /* ADC10TOVIFG */ +#define ADC10IV_ADC10HIIFG (0x0006) /* ADC10HIIFG */ +#define ADC10IV_ADC10LOIFG (0x0008) /* ADC10LOIFG */ +#define ADC10IV_ADC10INIFG (0x000A) /* ADC10INIFG */ +#define ADC10IV_ADC10IFG (0x000C) /* ADC10IFG */ + +#endif +/************************************************************ +* ADC12 PLUS +************************************************************/ +#ifdef __MSP430_HAS_ADC12_PLUS__ /* Definition to show that Module is available */ + +#define OFS_ADC12CTL0 (0x0000) /* ADC12+ Control 0 */ +#define OFS_ADC12CTL0_L OFS_ADC12CTL0 +#define OFS_ADC12CTL0_H OFS_ADC12CTL0+1 +#define OFS_ADC12CTL1 (0x0002) /* ADC12+ Control 1 */ +#define OFS_ADC12CTL1_L OFS_ADC12CTL1 +#define OFS_ADC12CTL1_H OFS_ADC12CTL1+1 +#define OFS_ADC12CTL2 (0x0004) /* ADC12+ Control 2 */ +#define OFS_ADC12CTL2_L OFS_ADC12CTL2 +#define OFS_ADC12CTL2_H OFS_ADC12CTL2+1 +#define OFS_ADC12IFG (0x000A) /* ADC12+ Interrupt Flag */ +#define OFS_ADC12IFG_L OFS_ADC12IFG +#define OFS_ADC12IFG_H OFS_ADC12IFG+1 +#define OFS_ADC12IE (0x000C) /* ADC12+ Interrupt Enable */ +#define OFS_ADC12IE_L OFS_ADC12IE +#define OFS_ADC12IE_H OFS_ADC12IE+1 +#define OFS_ADC12IV (0x000E) /* ADC12+ Interrupt Vector Word */ +#define OFS_ADC12IV_L OFS_ADC12IV +#define OFS_ADC12IV_H OFS_ADC12IV+1 + +#define OFS_ADC12MEM0 (0x0020) /* ADC12 Conversion Memory 0 */ +#define OFS_ADC12MEM0_L OFS_ADC12MEM0 +#define OFS_ADC12MEM0_H OFS_ADC12MEM0+1 +#define OFS_ADC12MEM1 (0x0022) /* ADC12 Conversion Memory 1 */ +#define OFS_ADC12MEM1_L OFS_ADC12MEM1 +#define OFS_ADC12MEM1_H OFS_ADC12MEM1+1 +#define OFS_ADC12MEM2 (0x0024) /* ADC12 Conversion Memory 2 */ +#define OFS_ADC12MEM2_L OFS_ADC12MEM2 +#define OFS_ADC12MEM2_H OFS_ADC12MEM2+1 +#define OFS_ADC12MEM3 (0x0026) /* ADC12 Conversion Memory 3 */ +#define OFS_ADC12MEM3_L OFS_ADC12MEM3 +#define OFS_ADC12MEM3_H OFS_ADC12MEM3+1 +#define OFS_ADC12MEM4 (0x0028) /* ADC12 Conversion Memory 4 */ +#define OFS_ADC12MEM4_L OFS_ADC12MEM4 +#define OFS_ADC12MEM4_H OFS_ADC12MEM4+1 +#define OFS_ADC12MEM5 (0x002A) /* ADC12 Conversion Memory 5 */ +#define OFS_ADC12MEM5_L OFS_ADC12MEM5 +#define OFS_ADC12MEM5_H OFS_ADC12MEM5+1 +#define OFS_ADC12MEM6 (0x002C) /* ADC12 Conversion Memory 6 */ +#define OFS_ADC12MEM6_L OFS_ADC12MEM6 +#define OFS_ADC12MEM6_H OFS_ADC12MEM6+1 +#define OFS_ADC12MEM7 (0x002E) /* ADC12 Conversion Memory 7 */ +#define OFS_ADC12MEM7_L OFS_ADC12MEM7 +#define OFS_ADC12MEM7_H OFS_ADC12MEM7+1 +#define OFS_ADC12MEM8 (0x0030) /* ADC12 Conversion Memory 8 */ +#define OFS_ADC12MEM8_L OFS_ADC12MEM8 +#define OFS_ADC12MEM8_H OFS_ADC12MEM8+1 +#define OFS_ADC12MEM9 (0x0032) /* ADC12 Conversion Memory 9 */ +#define OFS_ADC12MEM9_L OFS_ADC12MEM9 +#define OFS_ADC12MEM9_H OFS_ADC12MEM9+1 +#define OFS_ADC12MEM10 (0x0034) /* ADC12 Conversion Memory 10 */ +#define OFS_ADC12MEM10_L OFS_ADC12MEM10 +#define OFS_ADC12MEM10_H OFS_ADC12MEM10+1 +#define OFS_ADC12MEM11 (0x0036) /* ADC12 Conversion Memory 11 */ +#define OFS_ADC12MEM11_L OFS_ADC12MEM11 +#define OFS_ADC12MEM11_H OFS_ADC12MEM11+1 +#define OFS_ADC12MEM12 (0x0038) /* ADC12 Conversion Memory 12 */ +#define OFS_ADC12MEM12_L OFS_ADC12MEM12 +#define OFS_ADC12MEM12_H OFS_ADC12MEM12+1 +#define OFS_ADC12MEM13 (0x003A) /* ADC12 Conversion Memory 13 */ +#define OFS_ADC12MEM13_L OFS_ADC12MEM13 +#define OFS_ADC12MEM13_H OFS_ADC12MEM13+1 +#define OFS_ADC12MEM14 (0x003C) /* ADC12 Conversion Memory 14 */ +#define OFS_ADC12MEM14_L OFS_ADC12MEM14 +#define OFS_ADC12MEM14_H OFS_ADC12MEM14+1 +#define OFS_ADC12MEM15 (0x003E) /* ADC12 Conversion Memory 15 */ +#define OFS_ADC12MEM15_L OFS_ADC12MEM15 +#define OFS_ADC12MEM15_H OFS_ADC12MEM15+1 +#define ADC12MEM_ ADC12MEM /* ADC12 Conversion Memory */ +#ifdef __ASM_HEADER__ +#define ADC12MEM ADC12MEM0 /* ADC12 Conversion Memory (for assembler) */ +#else +#define ADC12MEM ((int*) &ADC12MEM0) /* ADC12 Conversion Memory (for C) */ +#endif + +#define OFS_ADC12MCTL0 (0x0010) /* ADC12 Memory Control 0 */ +#define OFS_ADC12MCTL1 (0x0011) /* ADC12 Memory Control 1 */ +#define OFS_ADC12MCTL2 (0x0012) /* ADC12 Memory Control 2 */ +#define OFS_ADC12MCTL3 (0x0013) /* ADC12 Memory Control 3 */ +#define OFS_ADC12MCTL4 (0x0014) /* ADC12 Memory Control 4 */ +#define OFS_ADC12MCTL5 (0x0015) /* ADC12 Memory Control 5 */ +#define OFS_ADC12MCTL6 (0x0016) /* ADC12 Memory Control 6 */ +#define OFS_ADC12MCTL7 (0x0017) /* ADC12 Memory Control 7 */ +#define OFS_ADC12MCTL8 (0x0018) /* ADC12 Memory Control 8 */ +#define OFS_ADC12MCTL9 (0x0019) /* ADC12 Memory Control 9 */ +#define OFS_ADC12MCTL10 (0x001A) /* ADC12 Memory Control 10 */ +#define OFS_ADC12MCTL11 (0x001B) /* ADC12 Memory Control 11 */ +#define OFS_ADC12MCTL12 (0x001C) /* ADC12 Memory Control 12 */ +#define OFS_ADC12MCTL13 (0x001D) /* ADC12 Memory Control 13 */ +#define OFS_ADC12MCTL14 (0x001E) /* ADC12 Memory Control 14 */ +#define OFS_ADC12MCTL15 (0x001F) /* ADC12 Memory Control 15 */ +#define ADC12MCTL_ ADC12MCTL /* ADC12 Memory Control */ +#ifdef __ASM_HEADER__ +#define ADC12MCTL ADC12MCTL0 /* ADC12 Memory Control (for assembler) */ +#else +#define ADC12MCTL ((char*) &ADC12MCTL0) /* ADC12 Memory Control (for C) */ +#endif + +/* ADC12CTL0 Control Bits */ +#define ADC12SC (0x0001) /* ADC12 Start Conversion */ +#define ADC12ENC (0x0002) /* ADC12 Enable Conversion */ +#define ADC12TOVIE (0x0004) /* ADC12 Timer Overflow interrupt enable */ +#define ADC12OVIE (0x0008) /* ADC12 Overflow interrupt enable */ +#define ADC12ON (0x0010) /* ADC12 On/enable */ +#define ADC12REFON (0x0020) /* ADC12 Reference on */ +#define ADC12REF2_5V (0x0040) /* ADC12 Ref 0:1.5V / 1:2.5V */ +#define ADC12MSC (0x0080) /* ADC12 Multiple SampleConversion */ +#define ADC12SHT00 (0x0100) /* ADC12 Sample Hold 0 Select Bit: 0 */ +#define ADC12SHT01 (0x0200) /* ADC12 Sample Hold 0 Select Bit: 1 */ +#define ADC12SHT02 (0x0400) /* ADC12 Sample Hold 0 Select Bit: 2 */ +#define ADC12SHT03 (0x0800) /* ADC12 Sample Hold 0 Select Bit: 3 */ +#define ADC12SHT10 (0x1000) /* ADC12 Sample Hold 1 Select Bit: 0 */ +#define ADC12SHT11 (0x2000) /* ADC12 Sample Hold 1 Select Bit: 1 */ +#define ADC12SHT12 (0x4000) /* ADC12 Sample Hold 1 Select Bit: 2 */ +#define ADC12SHT13 (0x8000) /* ADC12 Sample Hold 1 Select Bit: 3 */ + +/* ADC12CTL0 Control Bits */ +#define ADC12SC_L (0x0001) /* ADC12 Start Conversion */ +#define ADC12ENC_L (0x0002) /* ADC12 Enable Conversion */ +#define ADC12TOVIE_L (0x0004) /* ADC12 Timer Overflow interrupt enable */ +#define ADC12OVIE_L (0x0008) /* ADC12 Overflow interrupt enable */ +#define ADC12ON_L (0x0010) /* ADC12 On/enable */ +#define ADC12REFON_L (0x0020) /* ADC12 Reference on */ +#define ADC12REF2_5V_L (0x0040) /* ADC12 Ref 0:1.5V / 1:2.5V */ +#define ADC12MSC_L (0x0080) /* ADC12 Multiple SampleConversion */ + +/* ADC12CTL0 Control Bits */ +#define ADC12SHT00_H (0x0001) /* ADC12 Sample Hold 0 Select Bit: 0 */ +#define ADC12SHT01_H (0x0002) /* ADC12 Sample Hold 0 Select Bit: 1 */ +#define ADC12SHT02_H (0x0004) /* ADC12 Sample Hold 0 Select Bit: 2 */ +#define ADC12SHT03_H (0x0008) /* ADC12 Sample Hold 0 Select Bit: 3 */ +#define ADC12SHT10_H (0x0010) /* ADC12 Sample Hold 1 Select Bit: 0 */ +#define ADC12SHT11_H (0x0020) /* ADC12 Sample Hold 1 Select Bit: 1 */ +#define ADC12SHT12_H (0x0040) /* ADC12 Sample Hold 1 Select Bit: 2 */ +#define ADC12SHT13_H (0x0080) /* ADC12 Sample Hold 1 Select Bit: 3 */ + +#define ADC12SHT0_0 (0*0x100u) /* ADC12 Sample Hold 0 Select Bit: 0 */ +#define ADC12SHT0_1 (1*0x100u) /* ADC12 Sample Hold 0 Select Bit: 1 */ +#define ADC12SHT0_2 (2*0x100u) /* ADC12 Sample Hold 0 Select Bit: 2 */ +#define ADC12SHT0_3 (3*0x100u) /* ADC12 Sample Hold 0 Select Bit: 3 */ +#define ADC12SHT0_4 (4*0x100u) /* ADC12 Sample Hold 0 Select Bit: 4 */ +#define ADC12SHT0_5 (5*0x100u) /* ADC12 Sample Hold 0 Select Bit: 5 */ +#define ADC12SHT0_6 (6*0x100u) /* ADC12 Sample Hold 0 Select Bit: 6 */ +#define ADC12SHT0_7 (7*0x100u) /* ADC12 Sample Hold 0 Select Bit: 7 */ +#define ADC12SHT0_8 (8*0x100u) /* ADC12 Sample Hold 0 Select Bit: 8 */ +#define ADC12SHT0_9 (9*0x100u) /* ADC12 Sample Hold 0 Select Bit: 9 */ +#define ADC12SHT0_10 (10*0x100u) /* ADC12 Sample Hold 0 Select Bit: 10 */ +#define ADC12SHT0_11 (11*0x100u) /* ADC12 Sample Hold 0 Select Bit: 11 */ +#define ADC12SHT0_12 (12*0x100u) /* ADC12 Sample Hold 0 Select Bit: 12 */ +#define ADC12SHT0_13 (13*0x100u) /* ADC12 Sample Hold 0 Select Bit: 13 */ +#define ADC12SHT0_14 (14*0x100u) /* ADC12 Sample Hold 0 Select Bit: 14 */ +#define ADC12SHT0_15 (15*0x100u) /* ADC12 Sample Hold 0 Select Bit: 15 */ + +#define ADC12SHT1_0 (0*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 0 */ +#define ADC12SHT1_1 (1*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 1 */ +#define ADC12SHT1_2 (2*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 2 */ +#define ADC12SHT1_3 (3*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 3 */ +#define ADC12SHT1_4 (4*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 4 */ +#define ADC12SHT1_5 (5*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 5 */ +#define ADC12SHT1_6 (6*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 6 */ +#define ADC12SHT1_7 (7*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 7 */ +#define ADC12SHT1_8 (8*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 8 */ +#define ADC12SHT1_9 (9*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 9 */ +#define ADC12SHT1_10 (10*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 10 */ +#define ADC12SHT1_11 (11*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 11 */ +#define ADC12SHT1_12 (12*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 12 */ +#define ADC12SHT1_13 (13*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 13 */ +#define ADC12SHT1_14 (14*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 14 */ +#define ADC12SHT1_15 (15*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 15 */ + +/* ADC12CTL1 Control Bits */ +#define ADC12BUSY (0x0001) /* ADC12 Busy */ +#define ADC12CONSEQ0 (0x0002) /* ADC12 Conversion Sequence Select Bit: 0 */ +#define ADC12CONSEQ1 (0x0004) /* ADC12 Conversion Sequence Select Bit: 1 */ +#define ADC12SSEL0 (0x0008) /* ADC12 Clock Source Select Bit: 0 */ +#define ADC12SSEL1 (0x0010) /* ADC12 Clock Source Select Bit: 1 */ +#define ADC12DIV0 (0x0020) /* ADC12 Clock Divider Select Bit: 0 */ +#define ADC12DIV1 (0x0040) /* ADC12 Clock Divider Select Bit: 1 */ +#define ADC12DIV2 (0x0080) /* ADC12 Clock Divider Select Bit: 2 */ +#define ADC12ISSH (0x0100) /* ADC12 Invert Sample Hold Signal */ +#define ADC12SHP (0x0200) /* ADC12 Sample/Hold Pulse Mode */ +#define ADC12SHS0 (0x0400) /* ADC12 Sample/Hold Source Bit: 0 */ +#define ADC12SHS1 (0x0800) /* ADC12 Sample/Hold Source Bit: 1 */ +#define ADC12CSTARTADD0 (0x1000) /* ADC12 Conversion Start Address Bit: 0 */ +#define ADC12CSTARTADD1 (0x2000) /* ADC12 Conversion Start Address Bit: 1 */ +#define ADC12CSTARTADD2 (0x4000) /* ADC12 Conversion Start Address Bit: 2 */ +#define ADC12CSTARTADD3 (0x8000) /* ADC12 Conversion Start Address Bit: 3 */ + +/* ADC12CTL1 Control Bits */ +#define ADC12BUSY_L (0x0001) /* ADC12 Busy */ +#define ADC12CONSEQ0_L (0x0002) /* ADC12 Conversion Sequence Select Bit: 0 */ +#define ADC12CONSEQ1_L (0x0004) /* ADC12 Conversion Sequence Select Bit: 1 */ +#define ADC12SSEL0_L (0x0008) /* ADC12 Clock Source Select Bit: 0 */ +#define ADC12SSEL1_L (0x0010) /* ADC12 Clock Source Select Bit: 1 */ +#define ADC12DIV0_L (0x0020) /* ADC12 Clock Divider Select Bit: 0 */ +#define ADC12DIV1_L (0x0040) /* ADC12 Clock Divider Select Bit: 1 */ +#define ADC12DIV2_L (0x0080) /* ADC12 Clock Divider Select Bit: 2 */ + +/* ADC12CTL1 Control Bits */ +#define ADC12ISSH_H (0x0001) /* ADC12 Invert Sample Hold Signal */ +#define ADC12SHP_H (0x0002) /* ADC12 Sample/Hold Pulse Mode */ +#define ADC12SHS0_H (0x0004) /* ADC12 Sample/Hold Source Bit: 0 */ +#define ADC12SHS1_H (0x0008) /* ADC12 Sample/Hold Source Bit: 1 */ +#define ADC12CSTARTADD0_H (0x0010) /* ADC12 Conversion Start Address Bit: 0 */ +#define ADC12CSTARTADD1_H (0x0020) /* ADC12 Conversion Start Address Bit: 1 */ +#define ADC12CSTARTADD2_H (0x0040) /* ADC12 Conversion Start Address Bit: 2 */ +#define ADC12CSTARTADD3_H (0x0080) /* ADC12 Conversion Start Address Bit: 3 */ + +#define ADC12CONSEQ_0 (0*2u) /* ADC12 Conversion Sequence Select: 0 */ +#define ADC12CONSEQ_1 (1*2u) /* ADC12 Conversion Sequence Select: 1 */ +#define ADC12CONSEQ_2 (2*2u) /* ADC12 Conversion Sequence Select: 2 */ +#define ADC12CONSEQ_3 (3*2u) /* ADC12 Conversion Sequence Select: 3 */ + +#define ADC12SSEL_0 (0*8u) /* ADC12 Clock Source Select: 0 */ +#define ADC12SSEL_1 (1*8u) /* ADC12 Clock Source Select: 1 */ +#define ADC12SSEL_2 (2*8u) /* ADC12 Clock Source Select: 2 */ +#define ADC12SSEL_3 (3*8u) /* ADC12 Clock Source Select: 3 */ + +#define ADC12DIV_0 (0*0x20u) /* ADC12 Clock Divider Select: 0 */ +#define ADC12DIV_1 (1*0x20u) /* ADC12 Clock Divider Select: 1 */ +#define ADC12DIV_2 (2*0x20u) /* ADC12 Clock Divider Select: 2 */ +#define ADC12DIV_3 (3*0x20u) /* ADC12 Clock Divider Select: 3 */ +#define ADC12DIV_4 (4*0x20u) /* ADC12 Clock Divider Select: 4 */ +#define ADC12DIV_5 (5*0x20u) /* ADC12 Clock Divider Select: 5 */ +#define ADC12DIV_6 (6*0x20u) /* ADC12 Clock Divider Select: 6 */ +#define ADC12DIV_7 (7*0x20u) /* ADC12 Clock Divider Select: 7 */ + +#define ADC12SHS_0 (0*0x400u) /* ADC12 Sample/Hold Source: 0 */ +#define ADC12SHS_1 (1*0x400u) /* ADC12 Sample/Hold Source: 1 */ +#define ADC12SHS_2 (2*0x400u) /* ADC12 Sample/Hold Source: 2 */ +#define ADC12SHS_3 (3*0x400u) /* ADC12 Sample/Hold Source: 3 */ + +#define ADC12CSTARTADD_0 (0*0x1000u) /* ADC12 Conversion Start Address: 0 */ +#define ADC12CSTARTADD_1 (1*0x1000u) /* ADC12 Conversion Start Address: 1 */ +#define ADC12CSTARTADD_2 (2*0x1000u) /* ADC12 Conversion Start Address: 2 */ +#define ADC12CSTARTADD_3 (3*0x1000u) /* ADC12 Conversion Start Address: 3 */ +#define ADC12CSTARTADD_4 (4*0x1000u) /* ADC12 Conversion Start Address: 4 */ +#define ADC12CSTARTADD_5 (5*0x1000u) /* ADC12 Conversion Start Address: 5 */ +#define ADC12CSTARTADD_6 (6*0x1000u) /* ADC12 Conversion Start Address: 6 */ +#define ADC12CSTARTADD_7 (7*0x1000u) /* ADC12 Conversion Start Address: 7 */ +#define ADC12CSTARTADD_8 (8*0x1000u) /* ADC12 Conversion Start Address: 8 */ +#define ADC12CSTARTADD_9 (9*0x1000u) /* ADC12 Conversion Start Address: 9 */ +#define ADC12CSTARTADD_10 (10*0x1000u) /* ADC12 Conversion Start Address: 10 */ +#define ADC12CSTARTADD_11 (11*0x1000u) /* ADC12 Conversion Start Address: 11 */ +#define ADC12CSTARTADD_12 (12*0x1000u) /* ADC12 Conversion Start Address: 12 */ +#define ADC12CSTARTADD_13 (13*0x1000u) /* ADC12 Conversion Start Address: 13 */ +#define ADC12CSTARTADD_14 (14*0x1000u) /* ADC12 Conversion Start Address: 14 */ +#define ADC12CSTARTADD_15 (15*0x1000u) /* ADC12 Conversion Start Address: 15 */ + +/* ADC12CTL2 Control Bits */ +#define ADC12REFBURST (0x0001) /* ADC12+ Reference Burst */ +#define ADC12REFOUT (0x0002) /* ADC12+ Reference Out */ +#define ADC12SR (0x0004) /* ADC12+ Sampling Rate */ +#define ADC12DF (0x0008) /* ADC12+ Data Format */ +#define ADC12RES0 (0x0010) /* ADC12+ Resolution Bit: 0 */ +#define ADC12RES1 (0x0020) /* ADC12+ Resolution Bit: 1 */ +#define ADC12TCOFF (0x0080) /* ADC12+ Temperature Sensor Off */ +#define ADC12PDIV (0x0100) /* ADC12+ predivider 0:/1 1:/4 */ + +/* ADC12CTL2 Control Bits */ +#define ADC12REFBURST_L (0x0001) /* ADC12+ Reference Burst */ +#define ADC12REFOUT_L (0x0002) /* ADC12+ Reference Out */ +#define ADC12SR_L (0x0004) /* ADC12+ Sampling Rate */ +#define ADC12DF_L (0x0008) /* ADC12+ Data Format */ +#define ADC12RES0_L (0x0010) /* ADC12+ Resolution Bit: 0 */ +#define ADC12RES1_L (0x0020) /* ADC12+ Resolution Bit: 1 */ +#define ADC12TCOFF_L (0x0080) /* ADC12+ Temperature Sensor Off */ + +/* ADC12CTL2 Control Bits */ +#define ADC12PDIV_H (0x0001) /* ADC12+ predivider 0:/1 1:/4 */ + +#define ADC12RES_0 (0x0000) /* ADC12+ Resolution : 8 Bit */ +#define ADC12RES_1 (0x0010) /* ADC12+ Resolution : 10 Bit */ +#define ADC12RES_2 (0x0020) /* ADC12+ Resolution : 12 Bit */ +#define ADC12RES_3 (0x0030) /* ADC12+ Resolution : reserved */ + +/* ADC12MCTLx Control Bits */ +#define ADC12INCH0 (0x0001) /* ADC12 Input Channel Select Bit 0 */ +#define ADC12INCH1 (0x0002) /* ADC12 Input Channel Select Bit 1 */ +#define ADC12INCH2 (0x0004) /* ADC12 Input Channel Select Bit 2 */ +#define ADC12INCH3 (0x0008) /* ADC12 Input Channel Select Bit 3 */ +#define ADC12SREF0 (0x0010) /* ADC12 Select Reference Bit 0 */ +#define ADC12SREF1 (0x0020) /* ADC12 Select Reference Bit 1 */ +#define ADC12SREF2 (0x0040) /* ADC12 Select Reference Bit 2 */ +#define ADC12EOS (0x0080) /* ADC12 End of Sequence */ + +#define ADC12INCH_0 (0x0000) /* ADC12 Input Channel 0 */ +#define ADC12INCH_1 (0x0001) /* ADC12 Input Channel 1 */ +#define ADC12INCH_2 (0x0002) /* ADC12 Input Channel 2 */ +#define ADC12INCH_3 (0x0003) /* ADC12 Input Channel 3 */ +#define ADC12INCH_4 (0x0004) /* ADC12 Input Channel 4 */ +#define ADC12INCH_5 (0x0005) /* ADC12 Input Channel 5 */ +#define ADC12INCH_6 (0x0006) /* ADC12 Input Channel 6 */ +#define ADC12INCH_7 (0x0007) /* ADC12 Input Channel 7 */ +#define ADC12INCH_8 (0x0008) /* ADC12 Input Channel 8 */ +#define ADC12INCH_9 (0x0009) /* ADC12 Input Channel 9 */ +#define ADC12INCH_10 (0x000A) /* ADC12 Input Channel 10 */ +#define ADC12INCH_11 (0x000B) /* ADC12 Input Channel 11 */ +#define ADC12INCH_12 (0x000C) /* ADC12 Input Channel 12 */ +#define ADC12INCH_13 (0x000D) /* ADC12 Input Channel 13 */ +#define ADC12INCH_14 (0x000E) /* ADC12 Input Channel 14 */ +#define ADC12INCH_15 (0x000F) /* ADC12 Input Channel 15 */ + +#define ADC12SREF_0 (0*0x10u) /* ADC12 Select Reference 0 */ +#define ADC12SREF_1 (1*0x10u) /* ADC12 Select Reference 1 */ +#define ADC12SREF_2 (2*0x10u) /* ADC12 Select Reference 2 */ +#define ADC12SREF_3 (3*0x10u) /* ADC12 Select Reference 3 */ +#define ADC12SREF_4 (4*0x10u) /* ADC12 Select Reference 4 */ +#define ADC12SREF_5 (5*0x10u) /* ADC12 Select Reference 5 */ +#define ADC12SREF_6 (6*0x10u) /* ADC12 Select Reference 6 */ +#define ADC12SREF_7 (7*0x10u) /* ADC12 Select Reference 7 */ + +#define ADC12IE0 (0x0001) /* ADC12 Memory 0 Interrupt Enable */ +#define ADC12IE1 (0x0002) /* ADC12 Memory 1 Interrupt Enable */ +#define ADC12IE2 (0x0004) /* ADC12 Memory 2 Interrupt Enable */ +#define ADC12IE3 (0x0008) /* ADC12 Memory 3 Interrupt Enable */ +#define ADC12IE4 (0x0010) /* ADC12 Memory 4 Interrupt Enable */ +#define ADC12IE5 (0x0020) /* ADC12 Memory 5 Interrupt Enable */ +#define ADC12IE6 (0x0040) /* ADC12 Memory 6 Interrupt Enable */ +#define ADC12IE7 (0x0080) /* ADC12 Memory 7 Interrupt Enable */ +#define ADC12IE8 (0x0100) /* ADC12 Memory 8 Interrupt Enable */ +#define ADC12IE9 (0x0200) /* ADC12 Memory 9 Interrupt Enable */ +#define ADC12IE10 (0x0400) /* ADC12 Memory 10 Interrupt Enable */ +#define ADC12IE11 (0x0800) /* ADC12 Memory 11 Interrupt Enable */ +#define ADC12IE12 (0x1000) /* ADC12 Memory 12 Interrupt Enable */ +#define ADC12IE13 (0x2000) /* ADC12 Memory 13 Interrupt Enable */ +#define ADC12IE14 (0x4000) /* ADC12 Memory 14 Interrupt Enable */ +#define ADC12IE15 (0x8000) /* ADC12 Memory 15 Interrupt Enable */ + +#define ADC12IE0_L (0x0001) /* ADC12 Memory 0 Interrupt Enable */ +#define ADC12IE1_L (0x0002) /* ADC12 Memory 1 Interrupt Enable */ +#define ADC12IE2_L (0x0004) /* ADC12 Memory 2 Interrupt Enable */ +#define ADC12IE3_L (0x0008) /* ADC12 Memory 3 Interrupt Enable */ +#define ADC12IE4_L (0x0010) /* ADC12 Memory 4 Interrupt Enable */ +#define ADC12IE5_L (0x0020) /* ADC12 Memory 5 Interrupt Enable */ +#define ADC12IE6_L (0x0040) /* ADC12 Memory 6 Interrupt Enable */ +#define ADC12IE7_L (0x0080) /* ADC12 Memory 7 Interrupt Enable */ + +#define ADC12IE8_H (0x0001) /* ADC12 Memory 8 Interrupt Enable */ +#define ADC12IE9_H (0x0002) /* ADC12 Memory 9 Interrupt Enable */ +#define ADC12IE10_H (0x0004) /* ADC12 Memory 10 Interrupt Enable */ +#define ADC12IE11_H (0x0008) /* ADC12 Memory 11 Interrupt Enable */ +#define ADC12IE12_H (0x0010) /* ADC12 Memory 12 Interrupt Enable */ +#define ADC12IE13_H (0x0020) /* ADC12 Memory 13 Interrupt Enable */ +#define ADC12IE14_H (0x0040) /* ADC12 Memory 14 Interrupt Enable */ +#define ADC12IE15_H (0x0080) /* ADC12 Memory 15 Interrupt Enable */ + +#define ADC12IFG0 (0x0001) /* ADC12 Memory 0 Interrupt Flag */ +#define ADC12IFG1 (0x0002) /* ADC12 Memory 1 Interrupt Flag */ +#define ADC12IFG2 (0x0004) /* ADC12 Memory 2 Interrupt Flag */ +#define ADC12IFG3 (0x0008) /* ADC12 Memory 3 Interrupt Flag */ +#define ADC12IFG4 (0x0010) /* ADC12 Memory 4 Interrupt Flag */ +#define ADC12IFG5 (0x0020) /* ADC12 Memory 5 Interrupt Flag */ +#define ADC12IFG6 (0x0040) /* ADC12 Memory 6 Interrupt Flag */ +#define ADC12IFG7 (0x0080) /* ADC12 Memory 7 Interrupt Flag */ +#define ADC12IFG8 (0x0100) /* ADC12 Memory 8 Interrupt Flag */ +#define ADC12IFG9 (0x0200) /* ADC12 Memory 9 Interrupt Flag */ +#define ADC12IFG10 (0x0400) /* ADC12 Memory 10 Interrupt Flag */ +#define ADC12IFG11 (0x0800) /* ADC12 Memory 11 Interrupt Flag */ +#define ADC12IFG12 (0x1000) /* ADC12 Memory 12 Interrupt Flag */ +#define ADC12IFG13 (0x2000) /* ADC12 Memory 13 Interrupt Flag */ +#define ADC12IFG14 (0x4000) /* ADC12 Memory 14 Interrupt Flag */ +#define ADC12IFG15 (0x8000) /* ADC12 Memory 15 Interrupt Flag */ + +#define ADC12IFG0_L (0x0001) /* ADC12 Memory 0 Interrupt Flag */ +#define ADC12IFG1_L (0x0002) /* ADC12 Memory 1 Interrupt Flag */ +#define ADC12IFG2_L (0x0004) /* ADC12 Memory 2 Interrupt Flag */ +#define ADC12IFG3_L (0x0008) /* ADC12 Memory 3 Interrupt Flag */ +#define ADC12IFG4_L (0x0010) /* ADC12 Memory 4 Interrupt Flag */ +#define ADC12IFG5_L (0x0020) /* ADC12 Memory 5 Interrupt Flag */ +#define ADC12IFG6_L (0x0040) /* ADC12 Memory 6 Interrupt Flag */ +#define ADC12IFG7_L (0x0080) /* ADC12 Memory 7 Interrupt Flag */ + +#define ADC12IFG8_H (0x0001) /* ADC12 Memory 8 Interrupt Flag */ +#define ADC12IFG9_H (0x0002) /* ADC12 Memory 9 Interrupt Flag */ +#define ADC12IFG10_H (0x0004) /* ADC12 Memory 10 Interrupt Flag */ +#define ADC12IFG11_H (0x0008) /* ADC12 Memory 11 Interrupt Flag */ +#define ADC12IFG12_H (0x0010) /* ADC12 Memory 12 Interrupt Flag */ +#define ADC12IFG13_H (0x0020) /* ADC12 Memory 13 Interrupt Flag */ +#define ADC12IFG14_H (0x0040) /* ADC12 Memory 14 Interrupt Flag */ +#define ADC12IFG15_H (0x0080) /* ADC12 Memory 15 Interrupt Flag */ + +/* ADC12IV Definitions */ +#define ADC12IV_NONE (0x0000) /* No Interrupt pending */ +#define ADC12IV_ADC12OVIFG (0x0002) /* ADC12OVIFG */ +#define ADC12IV_ADC12TOVIFG (0x0004) /* ADC12TOVIFG */ +#define ADC12IV_ADC12IFG0 (0x0006) /* ADC12IFG0 */ +#define ADC12IV_ADC12IFG1 (0x0008) /* ADC12IFG1 */ +#define ADC12IV_ADC12IFG2 (0x000A) /* ADC12IFG2 */ +#define ADC12IV_ADC12IFG3 (0x000C) /* ADC12IFG3 */ +#define ADC12IV_ADC12IFG4 (0x000E) /* ADC12IFG4 */ +#define ADC12IV_ADC12IFG5 (0x0010) /* ADC12IFG5 */ +#define ADC12IV_ADC12IFG6 (0x0012) /* ADC12IFG6 */ +#define ADC12IV_ADC12IFG7 (0x0014) /* ADC12IFG7 */ +#define ADC12IV_ADC12IFG8 (0x0016) /* ADC12IFG8 */ +#define ADC12IV_ADC12IFG9 (0x0018) /* ADC12IFG9 */ +#define ADC12IV_ADC12IFG10 (0x001A) /* ADC12IFG10 */ +#define ADC12IV_ADC12IFG11 (0x001C) /* ADC12IFG11 */ +#define ADC12IV_ADC12IFG12 (0x001E) /* ADC12IFG12 */ +#define ADC12IV_ADC12IFG13 (0x0020) /* ADC12IFG13 */ +#define ADC12IV_ADC12IFG14 (0x0022) /* ADC12IFG14 */ +#define ADC12IV_ADC12IFG15 (0x0024) /* ADC12IFG15 */ + +#endif +/************************************************************ +* AES Accelerator +************************************************************/ +#ifdef __MSP430_HAS_AES__ /* Definition to show that Module is available */ + +#define OFS_AESACTL0 (0x0000) /* AES accelerator control register 0 */ +#define OFS_AESACTL0_L OFS_AESACTL0 +#define OFS_AESACTL0_H OFS_AESACTL0+1 +#define OFS_AESASTAT (0x0004) /* AES accelerator status register */ +#define OFS_AESASTAT_L OFS_AESASTAT +#define OFS_AESASTAT_H OFS_AESASTAT+1 +#define OFS_AESAKEY (0x0006) /* AES accelerator key register */ +#define OFS_AESAKEY_L OFS_AESAKEY +#define OFS_AESAKEY_H OFS_AESAKEY+1 +#define OFS_AESADIN (0x0008) /* AES accelerator data in register */ +#define OFS_AESADIN_L OFS_AESADIN +#define OFS_AESADIN_H OFS_AESADIN+1 +#define OFS_AESADOUT (0x000A) /* AES accelerator data out register */ +#define OFS_AESADOUT_L OFS_AESADOUT +#define OFS_AESADOUT_H OFS_AESADOUT+1 + +/* AESACTL0 Control Bits */ +#define AESOP0 (0x0001) /* AES Operation Bit: 0 */ +#define AESOP1 (0x0002) /* AES Operation Bit: 1 */ +#define AESSWRST (0x0080) /* AES Software Reset */ +#define AESRDYIFG (0x0100) /* AES ready interrupt flag */ +#define AESERRFG (0x0800) /* AES Error Flag */ +#define AESRDYIE (0x1000) /* AES ready interrupt enable*/ + +/* AESACTL0 Control Bits */ +#define AESOP0_L (0x0001) /* AES Operation Bit: 0 */ +#define AESOP1_L (0x0002) /* AES Operation Bit: 1 */ +#define AESSWRST_L (0x0080) /* AES Software Reset */ + +/* AESACTL0 Control Bits */ +#define AESRDYIFG_H (0x0001) /* AES ready interrupt flag */ +#define AESERRFG_H (0x0008) /* AES Error Flag */ +#define AESRDYIE_H (0x0010) /* AES ready interrupt enable*/ + +#define AESOP_0 (0x0000) /* AES Operation: Encrypt */ +#define AESOP_1 (0x0001) /* AES Operation: Decrypt (same Key) */ +#define AESOP_2 (0x0002) /* AES Operation: Decrypt (frist round Key) */ +#define AESOP_3 (0x0003) /* AES Operation: Generate first round Key */ + +/* AESASTAT Control Bits */ +#define AESBUSY (0x0001) /* AES Busy */ +#define AESKEYWR (0x0002) /* AES All 16 bytes written to AESAKEY */ +#define AESDINWR (0x0004) /* AES All 16 bytes written to AESADIN */ +#define AESDOUTRD (0x0008) /* AES All 16 bytes read from AESADOUT */ +#define AESKEYCNT0 (0x0010) /* AES Bytes written via AESAKEY Bit: 0 */ +#define AESKEYCNT1 (0x0020) /* AES Bytes written via AESAKEY Bit: 1 */ +#define AESKEYCNT2 (0x0040) /* AES Bytes written via AESAKEY Bit: 2 */ +#define AESKEYCNT3 (0x0080) /* AES Bytes written via AESAKEY Bit: 3 */ +#define AESDINCNT0 (0x0100) /* AES Bytes written via AESADIN Bit: 0 */ +#define AESDINCNT1 (0x0200) /* AES Bytes written via AESADIN Bit: 1 */ +#define AESDINCNT2 (0x0400) /* AES Bytes written via AESADIN Bit: 2 */ +#define AESDINCNT3 (0x0800) /* AES Bytes written via AESADIN Bit: 3 */ +#define AESDOUTCNT0 (0x1000) /* AES Bytes read via AESADOUT Bit: 0 */ +#define AESDOUTCNT1 (0x2000) /* AES Bytes read via AESADOUT Bit: 1 */ +#define AESDOUTCNT2 (0x4000) /* AES Bytes read via AESADOUT Bit: 2 */ +#define AESDOUTCNT3 (0x8000) /* AES Bytes read via AESADOUT Bit: 3 */ + +/* AESASTAT Control Bits */ +#define AESBUSY_L (0x0001) /* AES Busy */ +#define AESKEYWR_L (0x0002) /* AES All 16 bytes written to AESAKEY */ +#define AESDINWR_L (0x0004) /* AES All 16 bytes written to AESADIN */ +#define AESDOUTRD_L (0x0008) /* AES All 16 bytes read from AESADOUT */ +#define AESKEYCNT0_L (0x0010) /* AES Bytes written via AESAKEY Bit: 0 */ +#define AESKEYCNT1_L (0x0020) /* AES Bytes written via AESAKEY Bit: 1 */ +#define AESKEYCNT2_L (0x0040) /* AES Bytes written via AESAKEY Bit: 2 */ +#define AESKEYCNT3_L (0x0080) /* AES Bytes written via AESAKEY Bit: 3 */ + +/* AESASTAT Control Bits */ +#define AESDINCNT0_H (0x0001) /* AES Bytes written via AESADIN Bit: 0 */ +#define AESDINCNT1_H (0x0002) /* AES Bytes written via AESADIN Bit: 1 */ +#define AESDINCNT2_H (0x0004) /* AES Bytes written via AESADIN Bit: 2 */ +#define AESDINCNT3_H (0x0008) /* AES Bytes written via AESADIN Bit: 3 */ +#define AESDOUTCNT0_H (0x0010) /* AES Bytes read via AESADOUT Bit: 0 */ +#define AESDOUTCNT1_H (0x0020) /* AES Bytes read via AESADOUT Bit: 1 */ +#define AESDOUTCNT2_H (0x0040) /* AES Bytes read via AESADOUT Bit: 2 */ +#define AESDOUTCNT3_H (0x0080) /* AES Bytes read via AESADOUT Bit: 3 */ + +#endif +/************************************************************* +* Backup RAM Module +*************************************************************/ +#ifdef __MSP430_HAS_BACKUP_RAM__ /* Definition to show that Module is available */ + +#define OFS_BAKMEM0 (0x0000) /* Battery Backup Memory 0 */ +#define OFS_BAKMEM0_L OFS_BAKMEM0 +#define OFS_BAKMEM0_H OFS_BAKMEM0+1 +#define OFS_BAKMEM1 (0x0002) /* Battery Backup Memory 1 */ +#define OFS_BAKMEM1_L OFS_BAKMEM1 +#define OFS_BAKMEM1_H OFS_BAKMEM1+1 +#define OFS_BAKMEM2 (0x0004) /* Battery Backup Memory 2 */ +#define OFS_BAKMEM2_L OFS_BAKMEM2 +#define OFS_BAKMEM2_H OFS_BAKMEM2+1 +#define OFS_BAKMEM3 (0x0006) /* Battery Backup Memory 3 */ +#define OFS_BAKMEM3_L OFS_BAKMEM3 +#define OFS_BAKMEM3_H OFS_BAKMEM3+1 + +#endif +/************************************************************* +* Battery Charger Module +*************************************************************/ +#ifdef __MSP430_HAS_BATTERY_CHARGER__ /* Definition to show that Module is available */ + +#define OFS_BAKCTL (0x0000) /* Battery Backup Control */ +#define OFS_BAKCTL_L OFS_BAKCTL +#define OFS_BAKCTL_H OFS_BAKCTL+1 +#define OFS_BAKCHCTL (0x0002) /* Battery Charger Control */ +#define OFS_BAKCHCTL_L OFS_BAKCHCTL +#define OFS_BAKCHCTL_H OFS_BAKCHCTL+1 + +/* BAKCTL Control Bits */ +#define LOCKBAK (0x0001) /* Lock backup sub-system */ +#define BAKSW (0x0002) /* Manual switch to battery backup supply */ +#define BAKADC (0x0004) /* Battery backup supply to ADC. */ +#define BAKDIS (0x0008) /* Disable backup supply switching. */ + +/* BAKCTL Control Bits */ +#define LOCKBAK_L (0x0001) /* Lock backup sub-system */ +#define BAKSW_L (0x0002) /* Manual switch to battery backup supply */ +#define BAKADC_L (0x0004) /* Battery backup supply to ADC. */ +#define BAKDIS_L (0x0008) /* Disable backup supply switching. */ + +/* BAKCHCTL Control Bits */ +#define CHEN (0x0001) /* Charger enable */ +#define CHC0 (0x0002) /* Charger charge current Bit 0 */ +#define CHC1 (0x0004) /* Charger charge current Bit 1 */ +#define CHV0 (0x0010) /* Charger end voltage Bit 0 */ +#define CHV1 (0x0020) /* Charger end voltage Bit 1 */ + +/* BAKCHCTL Control Bits */ +#define CHEN_L (0x0001) /* Charger enable */ +#define CHC0_L (0x0002) /* Charger charge current Bit 0 */ +#define CHC1_L (0x0004) /* Charger charge current Bit 1 */ +#define CHV0_L (0x0010) /* Charger end voltage Bit 0 */ +#define CHV1_L (0x0020) /* Charger end voltage Bit 1 */ + +#define CHPWD (0x6900) /* Charger write password. */ + +#endif +/************************************************************ +* Comparator B +************************************************************/ +#ifdef __MSP430_HAS_COMPB__ /* Definition to show that Module is available */ + +#define OFS_CBCTL0 (0x0000) /* Comparator B Control Register 0 */ +#define OFS_CBCTL0_L OFS_CBCTL0 +#define OFS_CBCTL0_H OFS_CBCTL0+1 +#define OFS_CBCTL1 (0x0002) /* Comparator B Control Register 1 */ +#define OFS_CBCTL1_L OFS_CBCTL1 +#define OFS_CBCTL1_H OFS_CBCTL1+1 +#define OFS_CBCTL2 (0x0004) /* Comparator B Control Register 2 */ +#define OFS_CBCTL2_L OFS_CBCTL2 +#define OFS_CBCTL2_H OFS_CBCTL2+1 +#define OFS_CBCTL3 (0x0006) /* Comparator B Control Register 3 */ +#define OFS_CBCTL3_L OFS_CBCTL3 +#define OFS_CBCTL3_H OFS_CBCTL3+1 +#define OFS_CBINT (0x000C) /* Comparator B Interrupt Register */ +#define OFS_CBINT_L OFS_CBINT +#define OFS_CBINT_H OFS_CBINT+1 +#define OFS_CBIV (0x000E) /* Comparator B Interrupt Vector Word */ + +/* CBCTL0 Control Bits */ +#define CBIPSEL0 (0x0001) /* Comp. B Pos. Channel Input Select 0 */ +#define CBIPSEL1 (0x0002) /* Comp. B Pos. Channel Input Select 1 */ +#define CBIPSEL2 (0x0004) /* Comp. B Pos. Channel Input Select 2 */ +#define CBIPSEL3 (0x0008) /* Comp. B Pos. Channel Input Select 3 */ +//#define RESERVED (0x0010) /* Comp. B */ +//#define RESERVED (0x0020) /* Comp. B */ +//#define RESERVED (0x0040) /* Comp. B */ +#define CBIPEN (0x0080) /* Comp. B Pos. Channel Input Enable */ +#define CBIMSEL0 (0x0100) /* Comp. B Neg. Channel Input Select 0 */ +#define CBIMSEL1 (0x0200) /* Comp. B Neg. Channel Input Select 1 */ +#define CBIMSEL2 (0x0400) /* Comp. B Neg. Channel Input Select 2 */ +#define CBIMSEL3 (0x0800) /* Comp. B Neg. Channel Input Select 3 */ +//#define RESERVED (0x1000) /* Comp. B */ +//#define RESERVED (0x2000) /* Comp. B */ +//#define RESERVED (0x4000) /* Comp. B */ +#define CBIMEN (0x8000) /* Comp. B Neg. Channel Input Enable */ + +/* CBCTL0 Control Bits */ +#define CBIPSEL0_L (0x0001) /* Comp. B Pos. Channel Input Select 0 */ +#define CBIPSEL1_L (0x0002) /* Comp. B Pos. Channel Input Select 1 */ +#define CBIPSEL2_L (0x0004) /* Comp. B Pos. Channel Input Select 2 */ +#define CBIPSEL3_L (0x0008) /* Comp. B Pos. Channel Input Select 3 */ +//#define RESERVED (0x0010) /* Comp. B */ +//#define RESERVED (0x0020) /* Comp. B */ +//#define RESERVED (0x0040) /* Comp. B */ +#define CBIPEN_L (0x0080) /* Comp. B Pos. Channel Input Enable */ +//#define RESERVED (0x1000) /* Comp. B */ +//#define RESERVED (0x2000) /* Comp. B */ +//#define RESERVED (0x4000) /* Comp. B */ + +/* CBCTL0 Control Bits */ +//#define RESERVED (0x0010) /* Comp. B */ +//#define RESERVED (0x0020) /* Comp. B */ +//#define RESERVED (0x0040) /* Comp. B */ +#define CBIMSEL0_H (0x0001) /* Comp. B Neg. Channel Input Select 0 */ +#define CBIMSEL1_H (0x0002) /* Comp. B Neg. Channel Input Select 1 */ +#define CBIMSEL2_H (0x0004) /* Comp. B Neg. Channel Input Select 2 */ +#define CBIMSEL3_H (0x0008) /* Comp. B Neg. Channel Input Select 3 */ +//#define RESERVED (0x1000) /* Comp. B */ +//#define RESERVED (0x2000) /* Comp. B */ +//#define RESERVED (0x4000) /* Comp. B */ +#define CBIMEN_H (0x0080) /* Comp. B Neg. Channel Input Enable */ + +#define CBIPSEL_0 (0x0000) /* Comp. B V+ terminal Input Select: Channel 0 */ +#define CBIPSEL_1 (0x0001) /* Comp. B V+ terminal Input Select: Channel 1 */ +#define CBIPSEL_2 (0x0002) /* Comp. B V+ terminal Input Select: Channel 2 */ +#define CBIPSEL_3 (0x0003) /* Comp. B V+ terminal Input Select: Channel 3 */ +#define CBIPSEL_4 (0x0004) /* Comp. B V+ terminal Input Select: Channel 4 */ +#define CBIPSEL_5 (0x0005) /* Comp. B V+ terminal Input Select: Channel 5 */ +#define CBIPSEL_6 (0x0006) /* Comp. B V+ terminal Input Select: Channel 6 */ +#define CBIPSEL_7 (0x0007) /* Comp. B V+ terminal Input Select: Channel 7 */ +#define CBIPSEL_8 (0x0008) /* Comp. B V+ terminal Input Select: Channel 8 */ +#define CBIPSEL_9 (0x0009) /* Comp. B V+ terminal Input Select: Channel 9 */ +#define CBIPSEL_10 (0x000A) /* Comp. B V+ terminal Input Select: Channel 10 */ +#define CBIPSEL_11 (0x000B) /* Comp. B V+ terminal Input Select: Channel 11 */ +#define CBIPSEL_12 (0x000C) /* Comp. B V+ terminal Input Select: Channel 12 */ +#define CBIPSEL_13 (0x000D) /* Comp. B V+ terminal Input Select: Channel 13 */ +#define CBIPSEL_14 (0x000E) /* Comp. B V+ terminal Input Select: Channel 14 */ +#define CBIPSEL_15 (0x000F) /* Comp. B V+ terminal Input Select: Channel 15 */ + +#define CBIMSEL_0 (0x0000) /* Comp. B V- Terminal Input Select: Channel 0 */ +#define CBIMSEL_1 (0x0100) /* Comp. B V- Terminal Input Select: Channel 1 */ +#define CBIMSEL_2 (0x0200) /* Comp. B V- Terminal Input Select: Channel 2 */ +#define CBIMSEL_3 (0x0300) /* Comp. B V- Terminal Input Select: Channel 3 */ +#define CBIMSEL_4 (0x0400) /* Comp. B V- Terminal Input Select: Channel 4 */ +#define CBIMSEL_5 (0x0500) /* Comp. B V- Terminal Input Select: Channel 5 */ +#define CBIMSEL_6 (0x0600) /* Comp. B V- Terminal Input Select: Channel 6 */ +#define CBIMSEL_7 (0x0700) /* Comp. B V- Terminal Input Select: Channel 7 */ +#define CBIMSEL_8 (0x0800) /* Comp. B V- terminal Input Select: Channel 8 */ +#define CBIMSEL_9 (0x0900) /* Comp. B V- terminal Input Select: Channel 9 */ +#define CBIMSEL_10 (0x0A00) /* Comp. B V- terminal Input Select: Channel 10 */ +#define CBIMSEL_11 (0x0B00) /* Comp. B V- terminal Input Select: Channel 11 */ +#define CBIMSEL_12 (0x0C00) /* Comp. B V- terminal Input Select: Channel 12 */ +#define CBIMSEL_13 (0x0D00) /* Comp. B V- terminal Input Select: Channel 13 */ +#define CBIMSEL_14 (0x0E00) /* Comp. B V- terminal Input Select: Channel 14 */ +#define CBIMSEL_15 (0x0F00) /* Comp. B V- terminal Input Select: Channel 15 */ + +/* CBCTL1 Control Bits */ +#define CBOUT (0x0001) /* Comp. B Output */ +#define CBOUTPOL (0x0002) /* Comp. B Output Polarity */ +#define CBF (0x0004) /* Comp. B Enable Output Filter */ +#define CBIES (0x0008) /* Comp. B Interrupt Edge Select */ +#define CBSHORT (0x0010) /* Comp. B Input Short */ +#define CBEX (0x0020) /* Comp. B Exchange Inputs */ +#define CBFDLY0 (0x0040) /* Comp. B Filter delay Bit 0 */ +#define CBFDLY1 (0x0080) /* Comp. B Filter delay Bit 1 */ +#define CBPWRMD0 (0x0100) /* Comp. B Power Mode Bit 0 */ +#define CBPWRMD1 (0x0200) /* Comp. B Power Mode Bit 1 */ +#define CBON (0x0400) /* Comp. B enable */ +#define CBMRVL (0x0800) /* Comp. B CBMRV Level */ +#define CBMRVS (0x1000) /* Comp. B Output selects between VREF0 or VREF1*/ +//#define RESERVED (0x2000) /* Comp. B */ +//#define RESERVED (0x4000) /* Comp. B */ +//#define RESERVED (0x8000) /* Comp. B */ + +/* CBCTL1 Control Bits */ +#define CBOUT_L (0x0001) /* Comp. B Output */ +#define CBOUTPOL_L (0x0002) /* Comp. B Output Polarity */ +#define CBF_L (0x0004) /* Comp. B Enable Output Filter */ +#define CBIES_L (0x0008) /* Comp. B Interrupt Edge Select */ +#define CBSHORT_L (0x0010) /* Comp. B Input Short */ +#define CBEX_L (0x0020) /* Comp. B Exchange Inputs */ +#define CBFDLY0_L (0x0040) /* Comp. B Filter delay Bit 0 */ +#define CBFDLY1_L (0x0080) /* Comp. B Filter delay Bit 1 */ +//#define RESERVED (0x2000) /* Comp. B */ +//#define RESERVED (0x4000) /* Comp. B */ +//#define RESERVED (0x8000) /* Comp. B */ + +/* CBCTL1 Control Bits */ +#define CBPWRMD0_H (0x0001) /* Comp. B Power Mode Bit 0 */ +#define CBPWRMD1_H (0x0002) /* Comp. B Power Mode Bit 1 */ +#define CBON_H (0x0004) /* Comp. B enable */ +#define CBMRVL_H (0x0008) /* Comp. B CBMRV Level */ +#define CBMRVS_H (0x0010) /* Comp. B Output selects between VREF0 or VREF1*/ +//#define RESERVED (0x2000) /* Comp. B */ +//#define RESERVED (0x4000) /* Comp. B */ +//#define RESERVED (0x8000) /* Comp. B */ + +#define CBFDLY_0 (0x0000) /* Comp. B Filter delay 0 : 450ns */ +#define CBFDLY_1 (0x0040) /* Comp. B Filter delay 1 : 900ns */ +#define CBFDLY_2 (0x0080) /* Comp. B Filter delay 2 : 1800ns */ +#define CBFDLY_3 (0x00C0) /* Comp. B Filter delay 3 : 3600ns */ + +#define CBPWRMD_0 (0x0000) /* Comp. B Power Mode 0 : High speed */ +#define CBPWRMD_1 (0x0100) /* Comp. B Power Mode 1 : Normal */ +#define CBPWRMD_2 (0x0200) /* Comp. B Power Mode 2 : Ultra-Low*/ +#define CBPWRMD_3 (0x0300) /* Comp. B Power Mode 3 : Reserved */ + +/* CBCTL2 Control Bits */ +#define CBREF00 (0x0001) /* Comp. B Reference 0 Resistor Select Bit : 0 */ +#define CBREF01 (0x0002) /* Comp. B Reference 0 Resistor Select Bit : 1 */ +#define CBREF02 (0x0004) /* Comp. B Reference 0 Resistor Select Bit : 2 */ +#define CBREF03 (0x0008) /* Comp. B Reference 0 Resistor Select Bit : 3 */ +#define CBREF04 (0x0010) /* Comp. B Reference 0 Resistor Select Bit : 4 */ +#define CBRSEL (0x0020) /* Comp. B Reference select */ +#define CBRS0 (0x0040) /* Comp. B Reference Source Bit : 0 */ +#define CBRS1 (0x0080) /* Comp. B Reference Source Bit : 1 */ +#define CBREF10 (0x0100) /* Comp. B Reference 1 Resistor Select Bit : 0 */ +#define CBREF11 (0x0200) /* Comp. B Reference 1 Resistor Select Bit : 1 */ +#define CBREF12 (0x0400) /* Comp. B Reference 1 Resistor Select Bit : 2 */ +#define CBREF13 (0x0800) /* Comp. B Reference 1 Resistor Select Bit : 3 */ +#define CBREF14 (0x1000) /* Comp. B Reference 1 Resistor Select Bit : 4 */ +#define CBREFL0 (0x2000) /* Comp. B Reference voltage level Bit : 0 */ +#define CBREFL1 (0x4000) /* Comp. B Reference voltage level Bit : 1 */ +#define CBREFACC (0x8000) /* Comp. B Reference Accuracy */ + +/* CBCTL2 Control Bits */ +#define CBREF00_L (0x0001) /* Comp. B Reference 0 Resistor Select Bit : 0 */ +#define CBREF01_L (0x0002) /* Comp. B Reference 0 Resistor Select Bit : 1 */ +#define CBREF02_L (0x0004) /* Comp. B Reference 0 Resistor Select Bit : 2 */ +#define CBREF03_L (0x0008) /* Comp. B Reference 0 Resistor Select Bit : 3 */ +#define CBREF04_L (0x0010) /* Comp. B Reference 0 Resistor Select Bit : 4 */ +#define CBRSEL_L (0x0020) /* Comp. B Reference select */ +#define CBRS0_L (0x0040) /* Comp. B Reference Source Bit : 0 */ +#define CBRS1_L (0x0080) /* Comp. B Reference Source Bit : 1 */ + +/* CBCTL2 Control Bits */ +#define CBREF10_H (0x0001) /* Comp. B Reference 1 Resistor Select Bit : 0 */ +#define CBREF11_H (0x0002) /* Comp. B Reference 1 Resistor Select Bit : 1 */ +#define CBREF12_H (0x0004) /* Comp. B Reference 1 Resistor Select Bit : 2 */ +#define CBREF13_H (0x0008) /* Comp. B Reference 1 Resistor Select Bit : 3 */ +#define CBREF14_H (0x0010) /* Comp. B Reference 1 Resistor Select Bit : 4 */ +#define CBREFL0_H (0x0020) /* Comp. B Reference voltage level Bit : 0 */ +#define CBREFL1_H (0x0040) /* Comp. B Reference voltage level Bit : 1 */ +#define CBREFACC_H (0x0080) /* Comp. B Reference Accuracy */ + +#define CBREF0_0 (0x0000) /* Comp. B Int. Ref.0 Select 0 : 1/32 */ +#define CBREF0_1 (0x0001) /* Comp. B Int. Ref.0 Select 1 : 2/32 */ +#define CBREF0_2 (0x0002) /* Comp. B Int. Ref.0 Select 2 : 3/32 */ +#define CBREF0_3 (0x0003) /* Comp. B Int. Ref.0 Select 3 : 4/32 */ +#define CBREF0_4 (0x0004) /* Comp. B Int. Ref.0 Select 4 : 5/32 */ +#define CBREF0_5 (0x0005) /* Comp. B Int. Ref.0 Select 5 : 6/32 */ +#define CBREF0_6 (0x0006) /* Comp. B Int. Ref.0 Select 6 : 7/32 */ +#define CBREF0_7 (0x0007) /* Comp. B Int. Ref.0 Select 7 : 8/32 */ +#define CBREF0_8 (0x0008) /* Comp. B Int. Ref.0 Select 0 : 9/32 */ +#define CBREF0_9 (0x0009) /* Comp. B Int. Ref.0 Select 1 : 10/32 */ +#define CBREF0_10 (0x000A) /* Comp. B Int. Ref.0 Select 2 : 11/32 */ +#define CBREF0_11 (0x000B) /* Comp. B Int. Ref.0 Select 3 : 12/32 */ +#define CBREF0_12 (0x000C) /* Comp. B Int. Ref.0 Select 4 : 13/32 */ +#define CBREF0_13 (0x000D) /* Comp. B Int. Ref.0 Select 5 : 14/32 */ +#define CBREF0_14 (0x000E) /* Comp. B Int. Ref.0 Select 6 : 15/32 */ +#define CBREF0_15 (0x000F) /* Comp. B Int. Ref.0 Select 7 : 16/32 */ +#define CBREF0_16 (0x0010) /* Comp. B Int. Ref.0 Select 0 : 17/32 */ +#define CBREF0_17 (0x0011) /* Comp. B Int. Ref.0 Select 1 : 18/32 */ +#define CBREF0_18 (0x0012) /* Comp. B Int. Ref.0 Select 2 : 19/32 */ +#define CBREF0_19 (0x0013) /* Comp. B Int. Ref.0 Select 3 : 20/32 */ +#define CBREF0_20 (0x0014) /* Comp. B Int. Ref.0 Select 4 : 21/32 */ +#define CBREF0_21 (0x0015) /* Comp. B Int. Ref.0 Select 5 : 22/32 */ +#define CBREF0_22 (0x0016) /* Comp. B Int. Ref.0 Select 6 : 23/32 */ +#define CBREF0_23 (0x0017) /* Comp. B Int. Ref.0 Select 7 : 24/32 */ +#define CBREF0_24 (0x0018) /* Comp. B Int. Ref.0 Select 0 : 25/32 */ +#define CBREF0_25 (0x0019) /* Comp. B Int. Ref.0 Select 1 : 26/32 */ +#define CBREF0_26 (0x001A) /* Comp. B Int. Ref.0 Select 2 : 27/32 */ +#define CBREF0_27 (0x001B) /* Comp. B Int. Ref.0 Select 3 : 28/32 */ +#define CBREF0_28 (0x001C) /* Comp. B Int. Ref.0 Select 4 : 29/32 */ +#define CBREF0_29 (0x001D) /* Comp. B Int. Ref.0 Select 5 : 30/32 */ +#define CBREF0_30 (0x001E) /* Comp. B Int. Ref.0 Select 6 : 31/32 */ +#define CBREF0_31 (0x001F) /* Comp. B Int. Ref.0 Select 7 : 32/32 */ + +#define CBRS_0 (0x0000) /* Comp. B Reference Source 0 : Off */ +#define CBRS_1 (0x0040) /* Comp. B Reference Source 1 : Vcc */ +#define CBRS_2 (0x0080) /* Comp. B Reference Source 2 : Shared Ref. */ +#define CBRS_3 (0x00C0) /* Comp. B Reference Source 3 : Shared Ref. / Off */ + +#define CBREF1_0 (0x0000) /* Comp. B Int. Ref.1 Select 0 : 1/32 */ +#define CBREF1_1 (0x0100) /* Comp. B Int. Ref.1 Select 1 : 2/32 */ +#define CBREF1_2 (0x0200) /* Comp. B Int. Ref.1 Select 2 : 3/32 */ +#define CBREF1_3 (0x0300) /* Comp. B Int. Ref.1 Select 3 : 4/32 */ +#define CBREF1_4 (0x0400) /* Comp. B Int. Ref.1 Select 4 : 5/32 */ +#define CBREF1_5 (0x0500) /* Comp. B Int. Ref.1 Select 5 : 6/32 */ +#define CBREF1_6 (0x0600) /* Comp. B Int. Ref.1 Select 6 : 7/32 */ +#define CBREF1_7 (0x0700) /* Comp. B Int. Ref.1 Select 7 : 8/32 */ +#define CBREF1_8 (0x0800) /* Comp. B Int. Ref.1 Select 0 : 9/32 */ +#define CBREF1_9 (0x0900) /* Comp. B Int. Ref.1 Select 1 : 10/32 */ +#define CBREF1_10 (0x0A00) /* Comp. B Int. Ref.1 Select 2 : 11/32 */ +#define CBREF1_11 (0x0B00) /* Comp. B Int. Ref.1 Select 3 : 12/32 */ +#define CBREF1_12 (0x0C00) /* Comp. B Int. Ref.1 Select 4 : 13/32 */ +#define CBREF1_13 (0x0D00) /* Comp. B Int. Ref.1 Select 5 : 14/32 */ +#define CBREF1_14 (0x0E00) /* Comp. B Int. Ref.1 Select 6 : 15/32 */ +#define CBREF1_15 (0x0F00) /* Comp. B Int. Ref.1 Select 7 : 16/32 */ +#define CBREF1_16 (0x1000) /* Comp. B Int. Ref.1 Select 0 : 17/32 */ +#define CBREF1_17 (0x1100) /* Comp. B Int. Ref.1 Select 1 : 18/32 */ +#define CBREF1_18 (0x1200) /* Comp. B Int. Ref.1 Select 2 : 19/32 */ +#define CBREF1_19 (0x1300) /* Comp. B Int. Ref.1 Select 3 : 20/32 */ +#define CBREF1_20 (0x1400) /* Comp. B Int. Ref.1 Select 4 : 21/32 */ +#define CBREF1_21 (0x1500) /* Comp. B Int. Ref.1 Select 5 : 22/32 */ +#define CBREF1_22 (0x1600) /* Comp. B Int. Ref.1 Select 6 : 23/32 */ +#define CBREF1_23 (0x1700) /* Comp. B Int. Ref.1 Select 7 : 24/32 */ +#define CBREF1_24 (0x1800) /* Comp. B Int. Ref.1 Select 0 : 25/32 */ +#define CBREF1_25 (0x1900) /* Comp. B Int. Ref.1 Select 1 : 26/32 */ +#define CBREF1_26 (0x1A00) /* Comp. B Int. Ref.1 Select 2 : 27/32 */ +#define CBREF1_27 (0x1B00) /* Comp. B Int. Ref.1 Select 3 : 28/32 */ +#define CBREF1_28 (0x1C00) /* Comp. B Int. Ref.1 Select 4 : 29/32 */ +#define CBREF1_29 (0x1D00) /* Comp. B Int. Ref.1 Select 5 : 30/32 */ +#define CBREF1_30 (0x1E00) /* Comp. B Int. Ref.1 Select 6 : 31/32 */ +#define CBREF1_31 (0x1F00) /* Comp. B Int. Ref.1 Select 7 : 32/32 */ + +#define CBREFL_0 (0x0000) /* Comp. B Reference voltage level 0 : None */ +#define CBREFL_1 (0x2000) /* Comp. B Reference voltage level 1 : 1.5V */ +#define CBREFL_2 (0x4000) /* Comp. B Reference voltage level 2 : 2.0V */ +#define CBREFL_3 (0x6000) /* Comp. B Reference voltage level 3 : 2.5V */ + +#define CBPD0 (0x0001) /* Comp. B Disable Input Buffer of Port Register .0 */ +#define CBPD1 (0x0002) /* Comp. B Disable Input Buffer of Port Register .1 */ +#define CBPD2 (0x0004) /* Comp. B Disable Input Buffer of Port Register .2 */ +#define CBPD3 (0x0008) /* Comp. B Disable Input Buffer of Port Register .3 */ +#define CBPD4 (0x0010) /* Comp. B Disable Input Buffer of Port Register .4 */ +#define CBPD5 (0x0020) /* Comp. B Disable Input Buffer of Port Register .5 */ +#define CBPD6 (0x0040) /* Comp. B Disable Input Buffer of Port Register .6 */ +#define CBPD7 (0x0080) /* Comp. B Disable Input Buffer of Port Register .7 */ +#define CBPD8 (0x0100) /* Comp. B Disable Input Buffer of Port Register .8 */ +#define CBPD9 (0x0200) /* Comp. B Disable Input Buffer of Port Register .9 */ +#define CBPD10 (0x0400) /* Comp. B Disable Input Buffer of Port Register .10 */ +#define CBPD11 (0x0800) /* Comp. B Disable Input Buffer of Port Register .11 */ +#define CBPD12 (0x1000) /* Comp. B Disable Input Buffer of Port Register .12 */ +#define CBPD13 (0x2000) /* Comp. B Disable Input Buffer of Port Register .13 */ +#define CBPD14 (0x4000) /* Comp. B Disable Input Buffer of Port Register .14 */ +#define CBPD15 (0x8000) /* Comp. B Disable Input Buffer of Port Register .15 */ + +#define CBPD0_L (0x0001) /* Comp. B Disable Input Buffer of Port Register .0 */ +#define CBPD1_L (0x0002) /* Comp. B Disable Input Buffer of Port Register .1 */ +#define CBPD2_L (0x0004) /* Comp. B Disable Input Buffer of Port Register .2 */ +#define CBPD3_L (0x0008) /* Comp. B Disable Input Buffer of Port Register .3 */ +#define CBPD4_L (0x0010) /* Comp. B Disable Input Buffer of Port Register .4 */ +#define CBPD5_L (0x0020) /* Comp. B Disable Input Buffer of Port Register .5 */ +#define CBPD6_L (0x0040) /* Comp. B Disable Input Buffer of Port Register .6 */ +#define CBPD7_L (0x0080) /* Comp. B Disable Input Buffer of Port Register .7 */ + +#define CBPD8_H (0x0001) /* Comp. B Disable Input Buffer of Port Register .8 */ +#define CBPD9_H (0x0002) /* Comp. B Disable Input Buffer of Port Register .9 */ +#define CBPD10_H (0x0004) /* Comp. B Disable Input Buffer of Port Register .10 */ +#define CBPD11_H (0x0008) /* Comp. B Disable Input Buffer of Port Register .11 */ +#define CBPD12_H (0x0010) /* Comp. B Disable Input Buffer of Port Register .12 */ +#define CBPD13_H (0x0020) /* Comp. B Disable Input Buffer of Port Register .13 */ +#define CBPD14_H (0x0040) /* Comp. B Disable Input Buffer of Port Register .14 */ +#define CBPD15_H (0x0080) /* Comp. B Disable Input Buffer of Port Register .15 */ + +/* CBINT Control Bits */ +#define CBIFG (0x0001) /* Comp. B Interrupt Flag */ +#define CBIIFG (0x0002) /* Comp. B Interrupt Flag Inverted Polarity */ +//#define RESERVED (0x0004) /* Comp. B */ +//#define RESERVED (0x0008) /* Comp. B */ +//#define RESERVED (0x0010) /* Comp. B */ +//#define RESERVED (0x0020) /* Comp. B */ +//#define RESERVED (0x0040) /* Comp. B */ +//#define RESERVED (0x0080) /* Comp. B */ +#define CBIE (0x0100) /* Comp. B Interrupt Enable */ +#define CBIIE (0x0200) /* Comp. B Interrupt Enable Inverted Polarity */ +//#define RESERVED (0x0400) /* Comp. B */ +//#define RESERVED (0x0800) /* Comp. B */ +//#define RESERVED (0x1000) /* Comp. B */ +//#define RESERVED (0x2000) /* Comp. B */ +//#define RESERVED (0x4000) /* Comp. B */ +//#define RESERVED (0x8000) /* Comp. B */ + +/* CBINT Control Bits */ +#define CBIFG_L (0x0001) /* Comp. B Interrupt Flag */ +#define CBIIFG_L (0x0002) /* Comp. B Interrupt Flag Inverted Polarity */ +//#define RESERVED (0x0004) /* Comp. B */ +//#define RESERVED (0x0008) /* Comp. B */ +//#define RESERVED (0x0010) /* Comp. B */ +//#define RESERVED (0x0020) /* Comp. B */ +//#define RESERVED (0x0040) /* Comp. B */ +//#define RESERVED (0x0080) /* Comp. B */ +//#define RESERVED (0x0400) /* Comp. B */ +//#define RESERVED (0x0800) /* Comp. B */ +//#define RESERVED (0x1000) /* Comp. B */ +//#define RESERVED (0x2000) /* Comp. B */ +//#define RESERVED (0x4000) /* Comp. B */ +//#define RESERVED (0x8000) /* Comp. B */ + +/* CBINT Control Bits */ +//#define RESERVED (0x0004) /* Comp. B */ +//#define RESERVED (0x0008) /* Comp. B */ +//#define RESERVED (0x0010) /* Comp. B */ +//#define RESERVED (0x0020) /* Comp. B */ +//#define RESERVED (0x0040) /* Comp. B */ +//#define RESERVED (0x0080) /* Comp. B */ +#define CBIE_H (0x0001) /* Comp. B Interrupt Enable */ +#define CBIIE_H (0x0002) /* Comp. B Interrupt Enable Inverted Polarity */ +//#define RESERVED (0x0400) /* Comp. B */ +//#define RESERVED (0x0800) /* Comp. B */ +//#define RESERVED (0x1000) /* Comp. B */ +//#define RESERVED (0x2000) /* Comp. B */ +//#define RESERVED (0x4000) /* Comp. B */ +//#define RESERVED (0x8000) /* Comp. B */ + +/* CBIV Definitions */ +#define CBIV_NONE (0x0000) /* No Interrupt pending */ +#define CBIV_CBIFG (0x0002) /* CBIFG */ +#define CBIV_CBIIFG (0x0004) /* CBIIFG */ + +#endif +/************************************************************ +* CC1101 Radio Interface +************************************************************/ +#ifdef __MSP430_HAS_CC1101__ /* Definition to show that Module is available */ + +#define OFS_RF1AIFCTL0 (0x0000) /* Radio interface control register 0 */ +#define OFS_RF1AIFCTL0_L OFS_RF1AIFCTL0 +#define OFS_RF1AIFCTL0_H OFS_RF1AIFCTL0+1 +#define OFS_RF1AIFCTL1 (0x0002) /* Radio interface control register 1 */ +#define OFS_RF1AIFCTL1_L OFS_RF1AIFCTL1 +#define OFS_RF1AIFCTL1_H OFS_RF1AIFCTL1+1 +#define RF1AIFIFG RF1AIFCTL1_L /* Radio interface interrupt flag register */ +#define RF1AIFIE RF1AIFCTL1_H /* Radio interface interrupt enable register */ +#define OFS_RF1AIFCTL2 (0x0004) /* (Radio interface control register 2) */ +#define OFS_RF1AIFCTL2_L OFS_RF1AIFCTL2 +#define OFS_RF1AIFCTL2_H OFS_RF1AIFCTL2+1 +#define OFS_RF1AIFERR (0x0006) /* Radio interface error flag register */ +#define OFS_RF1AIFERR_L OFS_RF1AIFERR +#define OFS_RF1AIFERR_H OFS_RF1AIFERR+1 +#define OFS_RF1AIFERRV (0x000C) /* Radio interface error vector word register */ +#define OFS_RF1AIFERRV_L OFS_RF1AIFERRV +#define OFS_RF1AIFERRV_H OFS_RF1AIFERRV+1 +#define OFS_RF1AIFIV (0x000E) /* Radio interface interrupt vector word register */ +#define OFS_RF1AIFIV_L OFS_RF1AIFIV +#define OFS_RF1AIFIV_H OFS_RF1AIFIV+1 +#define OFS_RF1AINSTRW (0x0010) /* Radio instruction word register */ +#define OFS_RF1AINSTRW_L OFS_RF1AINSTRW +#define OFS_RF1AINSTRW_H OFS_RF1AINSTRW+1 +#define RF1ADINB RF1AINSTRW_L /* Radio instruction byte register */ +#define RF1AINSTRB RF1AINSTRW_H /* Radio byte data in register */ +#define OFS_RF1AINSTR1W (0x0012) /* Radio instruction 1-byte register with autoread */ +#define OFS_RF1AINSTR1W_L OFS_RF1AINSTR1W +#define OFS_RF1AINSTR1W_H OFS_RF1AINSTR1W+1 +#define RF1AINSTR1B RF1AINSTR1W_H /* Radio instruction 1-byte register with autoread */ +#define OFS_RF1AINSTR2W (0x0014) /* Radio instruction 2-byte register with autoread */ +#define OFS_RF1AINSTR2W_L OFS_RF1AINSTR2W +#define OFS_RF1AINSTR2W_H OFS_RF1AINSTR2W+1 +#define RF1AINSTR2B RF1AINSTR1W_H /* Radio instruction 2-byte register with autoread */ +#define OFS_RF1ADINW (0x0016) /* Radio word data in register */ +#define OFS_RF1ADINW_L OFS_RF1ADINW +#define OFS_RF1ADINW_H OFS_RF1ADINW+1 + +#define OFS_RF1ASTAT0W (0x0020) /* Radio status word register without auto-read */ +#define OFS_RF1ASTAT0W_L OFS_RF1ASTAT0W +#define OFS_RF1ASTAT0W_H OFS_RF1ASTAT0W+1 +#define RF1ADOUT0B RF1ASTAT0W_L /* Radio byte data out register without auto-read */ +#define RF1ASTAT0B RF1ASTAT0W_H /* Radio status byte register without auto-read */ +#define RF1ASTATW RF1ASTAT0W /* Radio status word register without auto-read */ +#define RF1ADOUTB RF1ASTAT0W_L /* Radio byte data out register without auto-read */ +#define RF1ASTATB RF1ASTAT0W_H /* Radio status byte register without auto-read */ +#define OFS_RF1ASTAT1W (0x0022) /* Radio status word register with 1-byte auto-read */ +#define OFS_RF1ASTAT1W_L OFS_RF1ASTAT1W +#define OFS_RF1ASTAT1W_H OFS_RF1ASTAT1W+1 +#define RF1ADOUT1B RF1ASTAT1W_L /* Radio byte data out register with 1-byte auto-read */ +#define RF1ASTAT1B RF1ASTAT1W_H /* Radio status byte register with 1-byte auto-read */ +#define OFS_RF1ASTAT2W (0x0024) /* Radio status word register with 2-byte auto-read */ +#define OFS_RF1ASTAT2W_L OFS_RF1ASTAT2W +#define OFS_RF1ASTAT2W_H OFS_RF1ASTAT2W+1 +#define RF1ADOUT2B RF1ASTAT2W_L /* Radio byte data out register with 2-byte auto-read */ +#define RF1ASTAT2B RF1ASTAT2W_H /* Radio status byte register with 2-byte auto-read */ +#define OFS_RF1ADOUT0W (0x0028) /* Radio core word data out register without auto-read */ +#define OFS_RF1ADOUT0W_L OFS_RF1ADOUT0W +#define OFS_RF1ADOUT0W_H OFS_RF1ADOUT0W+1 +#define RF1ADOUTW RF1ADOUT0W /* Radio core word data out register without auto-read */ +#define RF1ADOUTW_L RF1ADOUT0W_L /* Radio core word data out register without auto-read */ +#define RF1ADOUTW_H RF1ADOUT0W_H /* Radio core word data out register without auto-read */ +#define OFS_RF1ADOUT1W (0x002A) /* Radio core word data out register with 1-byte auto-read */ +#define OFS_RF1ADOUT1W_L OFS_RF1ADOUT1W +#define OFS_RF1ADOUT1W_H OFS_RF1ADOUT1W+1 +#define OFS_RF1ADOUT2W (0x002C) /* Radio core word data out register with 2-byte auto-read */ +#define OFS_RF1ADOUT2W_L OFS_RF1ADOUT2W +#define OFS_RF1ADOUT2W_H OFS_RF1ADOUT2W+1 +#define OFS_RF1AIN (0x0030) /* Radio core signal input register */ +#define OFS_RF1AIN_L OFS_RF1AIN +#define OFS_RF1AIN_H OFS_RF1AIN+1 +#define OFS_RF1AIFG (0x0032) /* Radio core interrupt flag register */ +#define OFS_RF1AIFG_L OFS_RF1AIFG +#define OFS_RF1AIFG_H OFS_RF1AIFG+1 +#define OFS_RF1AIES (0x0034) /* Radio core interrupt edge select register */ +#define OFS_RF1AIES_L OFS_RF1AIES +#define OFS_RF1AIES_H OFS_RF1AIES+1 +#define OFS_RF1AIE (0x0036) /* Radio core interrupt enable register */ +#define OFS_RF1AIE_L OFS_RF1AIE +#define OFS_RF1AIE_H OFS_RF1AIE+1 +#define OFS_RF1AIV (0x0038) /* Radio core interrupt vector word register */ +#define OFS_RF1AIV_L OFS_RF1AIV +#define OFS_RF1AIV_H OFS_RF1AIV+1 +#define OFS_RF1ARXFIFO (0x003C) /* Direct receive FIFO access register */ +#define OFS_RF1ARXFIFO_L OFS_RF1ARXFIFO +#define OFS_RF1ARXFIFO_H OFS_RF1ARXFIFO+1 +#define OFS_RF1ATXFIFO (0x003E) /* Direct transmit FIFO access register */ +#define OFS_RF1ATXFIFO_L OFS_RF1ATXFIFO +#define OFS_RF1ATXFIFO_H OFS_RF1ATXFIFO+1 + +/* RF1AIFCTL0 Control Bits */ +#define RFFIFOEN (0x0001) /* CC1101 Direct FIFO access enable */ +#define RFENDIAN (0x0002) /* CC1101 Disable endianness conversion */ + +/* RF1AIFCTL0 Control Bits */ +#define RFFIFOEN_L (0x0001) /* CC1101 Direct FIFO access enable */ +#define RFENDIAN_L (0x0002) /* CC1101 Disable endianness conversion */ + +/* RF1AIFCTL1 Control Bits */ +#define RFRXIFG (0x0001) /* Radio interface direct FIFO access receive interrupt flag */ +#define RFTXIFG (0x0002) /* Radio interface direct FIFO access transmit interrupt flag */ +#define RFERRIFG (0x0004) /* Radio interface error interrupt flag */ +#define RFINSTRIFG (0x0010) /* Radio interface instruction interrupt flag */ +#define RFDINIFG (0x0020) /* Radio interface data in interrupt flag */ +#define RFSTATIFG (0x0040) /* Radio interface status interrupt flag */ +#define RFDOUTIFG (0x0080) /* Radio interface data out interrupt flag */ +#define RFRXIE (0x0100) /* Radio interface direct FIFO access receive interrupt enable */ +#define RFTXIE (0x0200) /* Radio interface direct FIFO access transmit interrupt enable */ +#define RFERRIE (0x0400) /* Radio interface error interrupt enable */ +#define RFINSTRIE (0x1000) /* Radio interface instruction interrupt enable */ +#define RFDINIE (0x2000) /* Radio interface data in interrupt enable */ +#define RFSTATIE (0x4000) /* Radio interface status interrupt enable */ +#define RFDOUTIE (0x8000) /* Radio interface data out interrupt enable */ + +/* RF1AIFCTL1 Control Bits */ +#define RFRXIFG_L (0x0001) /* Radio interface direct FIFO access receive interrupt flag */ +#define RFTXIFG_L (0x0002) /* Radio interface direct FIFO access transmit interrupt flag */ +#define RFERRIFG_L (0x0004) /* Radio interface error interrupt flag */ +#define RFINSTRIFG_L (0x0010) /* Radio interface instruction interrupt flag */ +#define RFDINIFG_L (0x0020) /* Radio interface data in interrupt flag */ +#define RFSTATIFG_L (0x0040) /* Radio interface status interrupt flag */ +#define RFDOUTIFG_L (0x0080) /* Radio interface data out interrupt flag */ + +/* RF1AIFCTL1 Control Bits */ +#define RFRXIE_H (0x0001) /* Radio interface direct FIFO access receive interrupt enable */ +#define RFTXIE_H (0x0002) /* Radio interface direct FIFO access transmit interrupt enable */ +#define RFERRIE_H (0x0004) /* Radio interface error interrupt enable */ +#define RFINSTRIE_H (0x0010) /* Radio interface instruction interrupt enable */ +#define RFDINIE_H (0x0020) /* Radio interface data in interrupt enable */ +#define RFSTATIE_H (0x0040) /* Radio interface status interrupt enable */ +#define RFDOUTIE_H (0x0080) /* Radio interface data out interrupt enable */ + +/* RF1AIFERR Control Bits */ +#define LVERR (0x0001) /* Low Core Voltage Error Flag */ +#define OPERR (0x0002) /* Operand Error Flag */ +#define OUTERR (0x0004) /* Output data not available Error Flag */ +#define OPOVERR (0x0008) /* Operand Overwrite Error Flag */ + +/* RF1AIFERR Control Bits */ +#define LVERR_L (0x0001) /* Low Core Voltage Error Flag */ +#define OPERR_L (0x0002) /* Operand Error Flag */ +#define OUTERR_L (0x0004) /* Output data not available Error Flag */ +#define OPOVERR_L (0x0008) /* Operand Overwrite Error Flag */ + +/* RF1AIFERRV Definitions */ +#define RF1AIFERRV_NONE (0x0000) /* No Error pending */ +#define RF1AIFERRV_LVERR (0x0002) /* Low core voltage error */ +#define RF1AIFERRV_OPERR (0x0004) /* Operand Error */ +#define RF1AIFERRV_OUTERR (0x0006) /* Output data not available Error */ +#define RF1AIFERRV_OPOVERR (0x0008) /* Operand Overwrite Error */ + +/* RF1AIFIV Definitions */ +#define RF1AIFIV_NONE (0x0000) /* No Interrupt pending */ +#define RF1AIFIV_RFERRIFG (0x0002) /* Radio interface error */ +#define RF1AIFIV_RFDOUTIFG (0x0004) /* Radio i/f data out */ +#define RF1AIFIV_RFSTATIFG (0x0006) /* Radio i/f status out */ +#define RF1AIFIV_RFDINIFG (0x0008) /* Radio i/f data in */ +#define RF1AIFIV_RFINSTRIFG (0x000A) /* Radio i/f instruction in */ + +/* RF1AIV Definitions */ +#define RF1AIV_NONE (0x0000) /* No Interrupt pending */ +#define RF1AIV_RFIFG0 (0x0002) /* RFIFG0 */ +#define RF1AIV_RFIFG1 (0x0004) /* RFIFG1 */ +#define RF1AIV_RFIFG2 (0x0006) /* RFIFG2 */ +#define RF1AIV_RFIFG3 (0x0008) /* RFIFG3 */ +#define RF1AIV_RFIFG4 (0x000A) /* RFIFG4 */ +#define RF1AIV_RFIFG5 (0x000C) /* RFIFG5 */ +#define RF1AIV_RFIFG6 (0x000E) /* RFIFG6 */ +#define RF1AIV_RFIFG7 (0x0010) /* RFIFG7 */ +#define RF1AIV_RFIFG8 (0x0012) /* RFIFG8 */ +#define RF1AIV_RFIFG9 (0x0014) /* RFIFG9 */ +#define RF1AIV_RFIFG10 (0x0016) /* RFIFG10 */ +#define RF1AIV_RFIFG11 (0x0018) /* RFIFG11 */ +#define RF1AIV_RFIFG12 (0x001A) /* RFIFG12 */ +#define RF1AIV_RFIFG13 (0x001C) /* RFIFG13 */ +#define RF1AIV_RFIFG14 (0x001E) /* RFIFG14 */ +#define RF1AIV_RFIFG15 (0x0020) /* RFIFG15 */ + +// Radio Core Registers +#define IOCFG2 0x00 /* IOCFG2 - GDO2 output pin configuration */ +#define IOCFG1 0x01 /* IOCFG1 - GDO1 output pin configuration */ +#define IOCFG0 0x02 /* IOCFG1 - GDO0 output pin configuration */ +#define FIFOTHR 0x03 /* FIFOTHR - RX FIFO and TX FIFO thresholds */ +#define SYNC1 0x04 /* SYNC1 - Sync word, high byte */ +#define SYNC0 0x05 /* SYNC0 - Sync word, low byte */ +#define PKTLEN 0x06 /* PKTLEN - Packet length */ +#define PKTCTRL1 0x07 /* PKTCTRL1 - Packet automation control */ +#define PKTCTRL0 0x08 /* PKTCTRL0 - Packet automation control */ +#define ADDR 0x09 /* ADDR - Device address */ +#define CHANNR 0x0A /* CHANNR - Channel number */ +#define FSCTRL1 0x0B /* FSCTRL1 - Frequency synthesizer control */ +#define FSCTRL0 0x0C /* FSCTRL0 - Frequency synthesizer control */ +#define FREQ2 0x0D /* FREQ2 - Frequency control word, high byte */ +#define FREQ1 0x0E /* FREQ1 - Frequency control word, middle byte */ +#define FREQ0 0x0F /* FREQ0 - Frequency control word, low byte */ +#define MDMCFG4 0x10 /* MDMCFG4 - Modem configuration */ +#define MDMCFG3 0x11 /* MDMCFG3 - Modem configuration */ +#define MDMCFG2 0x12 /* MDMCFG2 - Modem configuration */ +#define MDMCFG1 0x13 /* MDMCFG1 - Modem configuration */ +#define MDMCFG0 0x14 /* MDMCFG0 - Modem configuration */ +#define DEVIATN 0x15 /* DEVIATN - Modem deviation setting */ +#define MCSM2 0x16 /* MCSM2 - Main Radio Control State Machine configuration */ +#define MCSM1 0x17 /* MCSM1 - Main Radio Control State Machine configuration */ +#define MCSM0 0x18 /* MCSM0 - Main Radio Control State Machine configuration */ +#define FOCCFG 0x19 /* FOCCFG - Frequency Offset Compensation configuration */ +#define BSCFG 0x1A /* BSCFG - Bit Synchronization configuration */ +#define AGCCTRL2 0x1B /* AGCCTRL2 - AGC control */ +#define AGCCTRL1 0x1C /* AGCCTRL1 - AGC control */ +#define AGCCTRL0 0x1D /* AGCCTRL0 - AGC control */ +#define WOREVT1 0x1E /* WOREVT1 - High byte Event0 timeout */ +#define WOREVT0 0x1F /* WOREVT0 - Low byte Event0 timeout */ +#define WORCTRL 0x20 /* WORCTRL - Wake On Radio control */ +#define FREND1 0x21 /* FREND1 - Front end RX configuration */ +#define FREND0 0x22 /* FREDN0 - Front end TX configuration */ +#define FSCAL3 0x23 /* FSCAL3 - Frequency synthesizer calibration */ +#define FSCAL2 0x24 /* FSCAL2 - Frequency synthesizer calibration */ +#define FSCAL1 0x25 /* FSCAL1 - Frequency synthesizer calibration */ +#define FSCAL0 0x26 /* FSCAL0 - Frequency synthesizer calibration */ +//#define RCCTRL1 0x27 /* RCCTRL1 - RC oscillator configuration */ +//#define RCCTRL0 0x28 /* RCCTRL0 - RC oscillator configuration */ +#define FSTEST 0x29 /* FSTEST - Frequency synthesizer calibration control */ +#define PTEST 0x2A /* PTEST - Production test */ +#define AGCTEST 0x2B /* AGCTEST - AGC test */ +#define TEST2 0x2C /* TEST2 - Various test settings */ +#define TEST1 0x2D /* TEST1 - Various test settings */ +#define TEST0 0x2E /* TEST0 - Various test settings */ + +/* status registers */ +#define PARTNUM 0x30 /* PARTNUM - Chip ID */ +#define VERSION 0x31 /* VERSION - Chip ID */ +#define FREQEST 0x32 /* FREQEST – Frequency Offset Estimate from demodulator */ +#define LQI 0x33 /* LQI – Demodulator estimate for Link Quality */ +#define RSSI 0x34 /* RSSI – Received signal strength indication */ +#define MARCSTATE 0x35 /* MARCSTATE – Main Radio Control State Machine state */ +#define WORTIME1 0x36 /* WORTIME1 – High byte of WOR time */ +#define WORTIME0 0x37 /* WORTIME0 – Low byte of WOR time */ +#define PKTSTATUS 0x38 /* PKTSTATUS – Current GDOx status and packet status */ +#define VCO_VC_DAC 0x39 /* VCO_VC_DAC – Current setting from PLL calibration module */ +#define TXBYTES 0x3A /* TXBYTES – Underflow and number of bytes */ +#define RXBYTES 0x3B /* RXBYTES – Overflow and number of bytes */ + +/* burst write registers */ +#define PATABLE 0x3E /* PATABLE - PA control settings table */ +#define TXFIFO 0x3F /* TXFIFO - Transmit FIFO */ +#define RXFIFO 0x3F /* RXFIFO - Receive FIFO */ + +/* Radio Core Instructions */ +/* command strobes */ +#define RF_SRES 0x30 /* SRES - Reset chip. */ +#define RF_SFSTXON 0x31 /* SFSTXON - Enable and calibrate frequency synthesizer. */ +#define RF_SXOFF 0x32 /* SXOFF - Turn off crystal oscillator. */ +#define RF_SCAL 0x33 /* SCAL - Calibrate frequency synthesizer and turn it off. */ +#define RF_SRX 0x34 /* SRX - Enable RX. Perform calibration if enabled. */ +#define RF_STX 0x35 /* STX - Enable TX. If in RX state, only enable TX if CCA passes. */ +#define RF_SIDLE 0x36 /* SIDLE - Exit RX / TX, turn off frequency synthesizer. */ +//#define RF_SRSVD 0x37 /* SRVSD - Reserved. Do not use. */ +#define RF_SWOR 0x38 /* SWOR - Start automatic RX polling sequence (Wake-on-Radio) */ +#define RF_SPWD 0x39 /* SPWD - Enter power down mode when CSn goes high. */ +#define RF_SFRX 0x3A /* SFRX - Flush the RX FIFO buffer. */ +#define RF_SFTX 0x3B /* SFTX - Flush the TX FIFO buffer. */ +#define RF_SWORRST 0x3C /* SWORRST - Reset real time clock. */ +#define RF_SNOP 0x3D /* SNOP - No operation. Returns status byte. */ + +#define RF_RXSTAT 0x80 /* Used in combination with strobe commands delivers number of availabe bytes in RX FIFO with return status */ +#define RF_TXSTAT 0x00 /* Used in combination with strobe commands delivers number of availabe bytes in TX FIFO with return status */ + +/* other radio instr */ +#define RF_SNGLREGRD 0x80 +#define RF_SNGLREGWR 0x00 +#define RF_REGRD 0xC0 +#define RF_REGWR 0x40 +#define RF_STATREGRD 0xC0 /* Read single radio core status register */ +#define RF_SNGLPATABRD (RF_SNGLREGRD+PATABLE) +#define RF_SNGLPATABWR (RF_SNGLREGWR+PATABLE) +#define RF_PATABRD (RF_REGRD+PATABLE) +#define RF_PATABWR (RF_REGWR+PATABLE) +#define RF_SNGLRXRD (RF_SNGLREGRD+RXFIFO) +#define RF_SNGLTXWR (RF_SNGLREGWR+TXFIFO) +#define RF_RXFIFORD (RF_REGRD+RXFIFO) +#define RF_TXFIFOWR (RF_REGWR+TXFIFO) + +#endif +/************************************************************* +* CRC Module +*************************************************************/ +#ifdef __MSP430_HAS_CRC__ /* Definition to show that Module is available */ + +#define OFS_CRCDI (0x0000) /* CRC Data In Register */ +#define OFS_CRCDI_L OFS_CRCDI +#define OFS_CRCDI_H OFS_CRCDI+1 +#define OFS_CRCDIRB (0x0002) /* CRC data in reverse byte Register */ +#define OFS_CRCDIRB_L OFS_CRCDIRB +#define OFS_CRCDIRB_H OFS_CRCDIRB+1 +#define OFS_CRCINIRES (0x0004) /* CRC Initialisation Register and Result Register */ +#define OFS_CRCINIRES_L OFS_CRCINIRES +#define OFS_CRCINIRES_H OFS_CRCINIRES+1 +#define OFS_CRCRESR (0x0006) /* CRC reverse result Register */ +#define OFS_CRCRESR_L OFS_CRCRESR +#define OFS_CRCRESR_H OFS_CRCRESR+1 + +#endif +/************************************************************ +* DAC12 +************************************************************/ +#ifdef __MSP430_HAS_DAC12_2__ /* Definition to show that Module is available */ + +#define OFS_DAC12_0CTL0 (0x0000) /* DAC12_0 Control Register 0 */ +#define OFS_DAC12_0CTL1 (0x0002) /* DAC12_0 Control Register 1 */ +#define OFS_DAC12_0DAT (0x0004) /* DAC12_0 Data */ +#define OFS_DAC12_0CALCTL (0x0006) /* DAC12_0 Calibration Control Register */ +#define OFS_DAC12_0CALDAT (0x0008) /* DAC12_0 Calibration Data Register */ +#define OFS_DAC12_1CTL0 (0x0010) /* DAC12_1 Control Register 0 */ +#define OFS_DAC12_1CTL1 (0x0012) /* DAC12_1 Control Register 1 */ +#define OFS_DAC12_1DAT (0x0014) /* DAC12_1 Data */ +#define OFS_DAC12_1CALCTL (0x0016) /* DAC12_1 Calibration Control Register */ +#define OFS_DAC12_1CALDAT (0x0018) /* DAC12_1 Calibration Data Register */ +#define OFS_DAC12_IV (0x001E) /* DAC12 Interrupt Vector Word */ + +/* DAC12_xCTL0 Control Bits */ +#define DAC12GRP (0x0001) /* DAC12 group */ +#define DAC12ENC (0x0002) /* DAC12 enable conversion */ +#define DAC12IFG (0x0004) /* DAC12 interrupt flag */ +#define DAC12IE (0x0008) /* DAC12 interrupt enable */ +#define DAC12DF (0x0010) /* DAC12 data format */ +#define DAC12AMP0 (0x0020) /* DAC12 amplifier bit 0 */ +#define DAC12AMP1 (0x0040) /* DAC12 amplifier bit 1 */ +#define DAC12AMP2 (0x0080) /* DAC12 amplifier bit 2 */ +#define DAC12IR (0x0100) /* DAC12 input reference and output range */ +#define DAC12CALON (0x0200) /* DAC12 calibration */ +#define DAC12LSEL0 (0x0400) /* DAC12 load select bit 0 */ +#define DAC12LSEL1 (0x0800) /* DAC12 load select bit 1 */ +#define DAC12RES (0x1000) /* DAC12 resolution */ +#define DAC12SREF0 (0x2000) /* DAC12 reference bit 0 */ +#define DAC12SREF1 (0x4000) /* DAC12 reference bit 1 */ +#define DAC12OPS (0x8000) /* DAC12 Operation Amp. */ + +#define DAC12AMP_0 (0*0x0020u) /* DAC12 amplifier 0: off, 3-state */ +#define DAC12AMP_1 (1*0x0020u) /* DAC12 amplifier 1: off, off */ +#define DAC12AMP_2 (2*0x0020u) /* DAC12 amplifier 2: low, low */ +#define DAC12AMP_3 (3*0x0020u) /* DAC12 amplifier 3: low, medium */ +#define DAC12AMP_4 (4*0x0020u) /* DAC12 amplifier 4: low, high */ +#define DAC12AMP_5 (5*0x0020u) /* DAC12 amplifier 5: medium, medium */ +#define DAC12AMP_6 (6*0x0020u) /* DAC12 amplifier 6: medium, high */ +#define DAC12AMP_7 (7*0x0020u) /* DAC12 amplifier 7: high, high */ + +#define DAC12LSEL_0 (0*0x0400u) /* DAC12 load select 0: direct */ +#define DAC12LSEL_1 (1*0x0400u) /* DAC12 load select 1: latched with DAT */ +#define DAC12LSEL_2 (2*0x0400u) /* DAC12 load select 2: latched with pos. Timer_A3.OUT1 */ +#define DAC12LSEL_3 (3*0x0400u) /* DAC12 load select 3: latched with pos. Timer_B7.OUT1 */ + +#define DAC12SREF_0 (0*0x2000u) /* DAC12 reference 0: Vref+ */ +#define DAC12SREF_1 (1*0x2000u) /* DAC12 reference 1: Vref+ */ +#define DAC12SREF_2 (2*0x2000u) /* DAC12 reference 2: Veref+ */ +#define DAC12SREF_3 (3*0x2000u) /* DAC12 reference 3: Veref+ */ + +/* DAC12_xCTL1 Control Bits */ +#define DAC12DFJ (0x0001) /* DAC12 Data Format Justification */ +#define DAC12OG (0x0002) /* DAC12 output buffer gain: 0: 3x gain / 1: 2x gain */ + +/* DAC12_xCALCTL Control Bits */ +#define DAC12LOCK (0x0001) /* DAC12 Calibration Lock */ + +#define DAC12PW (0xA500) /* DAC12 Calibration Register write Password */ + +/* DACIV Definitions */ +#define DACIV_NONE (0x0000) /* No Interrupt pending */ +#define DACIV_DAC12IFG_0 (0x0002) /* DAC12IFG_0 */ +#define DACIV_DAC12IFG_1 (0x0004) /* DAC12IFG_1 */ + +#endif +/************************************************************ +* DMA_X +************************************************************/ +#ifdef __MSP430_HAS_DMAX_3__ /* Definition to show that Module is available */ + +#define OFS_DMACTL0 (0x0000) /* DMA Module Control 0 */ +#define OFS_DMACTL0_L OFS_DMACTL0 +#define OFS_DMACTL0_H OFS_DMACTL0+1 +#define OFS_DMACTL1 (0x0002) /* DMA Module Control 1 */ +#define OFS_DMACTL1_L OFS_DMACTL1 +#define OFS_DMACTL1_H OFS_DMACTL1+1 +#define OFS_DMACTL2 (0x0004) /* DMA Module Control 2 */ +#define OFS_DMACTL2_L OFS_DMACTL2 +#define OFS_DMACTL2_H OFS_DMACTL2+1 +#define OFS_DMACTL3 (0x0006) /* DMA Module Control 3 */ +#define OFS_DMACTL3_L OFS_DMACTL3 +#define OFS_DMACTL3_H OFS_DMACTL3+1 +#define OFS_DMACTL4 (0x0008) /* DMA Module Control 4 */ +#define OFS_DMACTL4_L OFS_DMACTL4 +#define OFS_DMACTL4_H OFS_DMACTL4+1 +#define OFS_DMAIV (0x000E) /* DMA Interrupt Vector Word */ +#define OFS_DMAIV_L OFS_DMAIV +#define OFS_DMAIV_H OFS_DMAIV+1 + +#define OFS_DMA0CTL (0x0010) /* DMA Channel 0 Control */ +#define OFS_DMA0CTL_L OFS_DMA0CTL +#define OFS_DMA0CTL_H OFS_DMA0CTL+1 +#define OFS_DMA0SA (0x0012) /* DMA Channel 0 Source Address */ +#define OFS_DMA0DA (0x0016) /* DMA Channel 0 Destination Address */ +#define OFS_DMA0SZ (0x001A) /* DMA Channel 0 Transfer Size */ + +#define OFS_DMA1CTL (0x0020) /* DMA Channel 1 Control */ +#define OFS_DMA1CTL_L OFS_DMA1CTL +#define OFS_DMA1CTL_H OFS_DMA1CTL+1 +#define OFS_DMA1SA (0x0022) /* DMA Channel 1 Source Address */ +#define OFS_DMA1DA (0x0026) /* DMA Channel 1 Destination Address */ +#define OFS_DMA1SZ (0x002A) /* DMA Channel 1 Transfer Size */ + +#define OFS_DMA2CTL (0x0030) /* DMA Channel 2 Control */ +#define OFS_DMA2CTL_L OFS_DMA2CTL +#define OFS_DMA2CTL_H OFS_DMA2CTL+1 +#define OFS_DMA2SA (0x0032) /* DMA Channel 2 Source Address */ +#define OFS_DMA2DA (0x0036) /* DMA Channel 2 Destination Address */ +#define OFS_DMA2SZ (0x003A) /* DMA Channel 2 Transfer Size */ + +/* DMACTL0 Control Bits */ +#define DMA0TSEL0 (0x0001) /* DMA channel 0 transfer select bit 0 */ +#define DMA0TSEL1 (0x0002) /* DMA channel 0 transfer select bit 1 */ +#define DMA0TSEL2 (0x0004) /* DMA channel 0 transfer select bit 2 */ +#define DMA0TSEL3 (0x0008) /* DMA channel 0 transfer select bit 3 */ +#define DMA0TSEL4 (0x0010) /* DMA channel 0 transfer select bit 4 */ +#define DMA1TSEL0 (0x0100) /* DMA channel 1 transfer select bit 0 */ +#define DMA1TSEL1 (0x0200) /* DMA channel 1 transfer select bit 1 */ +#define DMA1TSEL2 (0x0400) /* DMA channel 1 transfer select bit 2 */ +#define DMA1TSEL3 (0x0800) /* DMA channel 1 transfer select bit 3 */ +#define DMA1TSEL4 (0x1000) /* DMA channel 1 transfer select bit 4 */ + +/* DMACTL0 Control Bits */ +#define DMA0TSEL0_L (0x0001) /* DMA channel 0 transfer select bit 0 */ +#define DMA0TSEL1_L (0x0002) /* DMA channel 0 transfer select bit 1 */ +#define DMA0TSEL2_L (0x0004) /* DMA channel 0 transfer select bit 2 */ +#define DMA0TSEL3_L (0x0008) /* DMA channel 0 transfer select bit 3 */ +#define DMA0TSEL4_L (0x0010) /* DMA channel 0 transfer select bit 4 */ + +/* DMACTL0 Control Bits */ +#define DMA1TSEL0_H (0x0001) /* DMA channel 1 transfer select bit 0 */ +#define DMA1TSEL1_H (0x0002) /* DMA channel 1 transfer select bit 1 */ +#define DMA1TSEL2_H (0x0004) /* DMA channel 1 transfer select bit 2 */ +#define DMA1TSEL3_H (0x0008) /* DMA channel 1 transfer select bit 3 */ +#define DMA1TSEL4_H (0x0010) /* DMA channel 1 transfer select bit 4 */ + +/* DMACTL01 Control Bits */ +#define DMA2TSEL0 (0x0001) /* DMA channel 2 transfer select bit 0 */ +#define DMA2TSEL1 (0x0002) /* DMA channel 2 transfer select bit 1 */ +#define DMA2TSEL2 (0x0004) /* DMA channel 2 transfer select bit 2 */ +#define DMA2TSEL3 (0x0008) /* DMA channel 2 transfer select bit 3 */ +#define DMA2TSEL4 (0x0010) /* DMA channel 2 transfer select bit 4 */ + +/* DMACTL01 Control Bits */ +#define DMA2TSEL0_L (0x0001) /* DMA channel 2 transfer select bit 0 */ +#define DMA2TSEL1_L (0x0002) /* DMA channel 2 transfer select bit 1 */ +#define DMA2TSEL2_L (0x0004) /* DMA channel 2 transfer select bit 2 */ +#define DMA2TSEL3_L (0x0008) /* DMA channel 2 transfer select bit 3 */ +#define DMA2TSEL4_L (0x0010) /* DMA channel 2 transfer select bit 4 */ + +/* DMACTL4 Control Bits */ +#define ENNMI (0x0001) /* Enable NMI interruption of DMA */ +#define ROUNDROBIN (0x0002) /* Round-Robin DMA channel priorities */ +#define DMARMWDIS (0x0004) /* Inhibited DMA transfers during read-modify-write CPU operations */ + +/* DMACTL4 Control Bits */ +#define ENNMI_L (0x0001) /* Enable NMI interruption of DMA */ +#define ROUNDROBIN_L (0x0002) /* Round-Robin DMA channel priorities */ +#define DMARMWDIS_L (0x0004) /* Inhibited DMA transfers during read-modify-write CPU operations */ + +/* DMAxCTL Control Bits */ +#define DMAREQ (0x0001) /* Initiate DMA transfer with DMATSEL */ +#define DMAABORT (0x0002) /* DMA transfer aborted by NMI */ +#define DMAIE (0x0004) /* DMA interrupt enable */ +#define DMAIFG (0x0008) /* DMA interrupt flag */ +#define DMAEN (0x0010) /* DMA enable */ +#define DMALEVEL (0x0020) /* DMA level sensitive trigger select */ +#define DMASRCBYTE (0x0040) /* DMA source byte */ +#define DMADSTBYTE (0x0080) /* DMA destination byte */ +#define DMASRCINCR0 (0x0100) /* DMA source increment bit 0 */ +#define DMASRCINCR1 (0x0200) /* DMA source increment bit 1 */ +#define DMADSTINCR0 (0x0400) /* DMA destination increment bit 0 */ +#define DMADSTINCR1 (0x0800) /* DMA destination increment bit 1 */ +#define DMADT0 (0x1000) /* DMA transfer mode bit 0 */ +#define DMADT1 (0x2000) /* DMA transfer mode bit 1 */ +#define DMADT2 (0x4000) /* DMA transfer mode bit 2 */ + +/* DMAxCTL Control Bits */ +#define DMAREQ_L (0x0001) /* Initiate DMA transfer with DMATSEL */ +#define DMAABORT_L (0x0002) /* DMA transfer aborted by NMI */ +#define DMAIE_L (0x0004) /* DMA interrupt enable */ +#define DMAIFG_L (0x0008) /* DMA interrupt flag */ +#define DMAEN_L (0x0010) /* DMA enable */ +#define DMALEVEL_L (0x0020) /* DMA level sensitive trigger select */ +#define DMASRCBYTE_L (0x0040) /* DMA source byte */ +#define DMADSTBYTE_L (0x0080) /* DMA destination byte */ + +/* DMAxCTL Control Bits */ +#define DMASRCINCR0_H (0x0001) /* DMA source increment bit 0 */ +#define DMASRCINCR1_H (0x0002) /* DMA source increment bit 1 */ +#define DMADSTINCR0_H (0x0004) /* DMA destination increment bit 0 */ +#define DMADSTINCR1_H (0x0008) /* DMA destination increment bit 1 */ +#define DMADT0_H (0x0010) /* DMA transfer mode bit 0 */ +#define DMADT1_H (0x0020) /* DMA transfer mode bit 1 */ +#define DMADT2_H (0x0040) /* DMA transfer mode bit 2 */ + +#define DMASWDW (0*0x0040u) /* DMA transfer: source word to destination word */ +#define DMASBDW (1*0x0040u) /* DMA transfer: source byte to destination word */ +#define DMASWDB (2*0x0040u) /* DMA transfer: source word to destination byte */ +#define DMASBDB (3*0x0040u) /* DMA transfer: source byte to destination byte */ + +#define DMASRCINCR_0 (0*0x0100u) /* DMA source increment 0: source address unchanged */ +#define DMASRCINCR_1 (1*0x0100u) /* DMA source increment 1: source address unchanged */ +#define DMASRCINCR_2 (2*0x0100u) /* DMA source increment 2: source address decremented */ +#define DMASRCINCR_3 (3*0x0100u) /* DMA source increment 3: source address incremented */ + +#define DMADSTINCR_0 (0*0x0400u) /* DMA destination increment 0: destination address unchanged */ +#define DMADSTINCR_1 (1*0x0400u) /* DMA destination increment 1: destination address unchanged */ +#define DMADSTINCR_2 (2*0x0400u) /* DMA destination increment 2: destination address decremented */ +#define DMADSTINCR_3 (3*0x0400u) /* DMA destination increment 3: destination address incremented */ + +#define DMADT_0 (0*0x1000u) /* DMA transfer mode 0: Single transfer */ +#define DMADT_1 (1*0x1000u) /* DMA transfer mode 1: Block transfer */ +#define DMADT_2 (2*0x1000u) /* DMA transfer mode 2: Burst-Block transfer */ +#define DMADT_3 (3*0x1000u) /* DMA transfer mode 3: Burst-Block transfer */ +#define DMADT_4 (4*0x1000u) /* DMA transfer mode 4: Repeated Single transfer */ +#define DMADT_5 (5*0x1000u) /* DMA transfer mode 5: Repeated Block transfer */ +#define DMADT_6 (6*0x1000u) /* DMA transfer mode 6: Repeated Burst-Block transfer */ +#define DMADT_7 (7*0x1000u) /* DMA transfer mode 7: Repeated Burst-Block transfer */ + +/* DMAIV Definitions */ +#define DMAIV_NONE (0x0000) /* No Interrupt pending */ +#define DMAIV_DMA0IFG (0x0002) /* DMA0IFG*/ +#define DMAIV_DMA1IFG (0x0004) /* DMA1IFG*/ +#define DMAIV_DMA2IFG (0x0006) /* DMA2IFG*/ + +#endif +/************************************************************ +* DMA_X +************************************************************/ +#ifdef __MSP430_HAS_DMAX_6__ /* Definition to show that Module is available */ + +#define OFS_DMACTL0 (0x0000) /* DMA Module Control 0 */ +#define OFS_DMACTL0_L OFS_DMACTL0 +#define OFS_DMACTL0_H OFS_DMACTL0+1 +#define OFS_DMACTL1 (0x0002) /* DMA Module Control 1 */ +#define OFS_DMACTL1_L OFS_DMACTL1 +#define OFS_DMACTL1_H OFS_DMACTL1+1 +#define OFS_DMACTL2 (0x0004) /* DMA Module Control 2 */ +#define OFS_DMACTL2_L OFS_DMACTL2 +#define OFS_DMACTL2_H OFS_DMACTL2+1 +#define OFS_DMACTL3 (0x0006) /* DMA Module Control 3 */ +#define OFS_DMACTL3_L OFS_DMACTL3 +#define OFS_DMACTL3_H OFS_DMACTL3+1 +#define OFS_DMACTL4 (0x0008) /* DMA Module Control 4 */ +#define OFS_DMACTL4_L OFS_DMACTL4 +#define OFS_DMACTL4_H OFS_DMACTL4+1 +#define OFS_DMAIV (0x000E) /* DMA Interrupt Vector Word */ +#define OFS_DMAIV_L OFS_DMAIV +#define OFS_DMAIV_H OFS_DMAIV+1 + +#define OFS_DMA0CTL (0x0010) /* DMA Channel 0 Control */ +#define OFS_DMA0CTL_L OFS_DMA0CTL +#define OFS_DMA0CTL_H OFS_DMA0CTL+1 +#define OFS_DMA0SA (0x0012) /* DMA Channel 0 Source Address */ +#define OFS_DMA0DA (0x0016) /* DMA Channel 0 Destination Address */ +#define OFS_DMA0SZ (0x001A) /* DMA Channel 0 Transfer Size */ + +#define OFS_DMA1CTL (0x0020) /* DMA Channel 1 Control */ +#define OFS_DMA1CTL_L OFS_DMA1CTL +#define OFS_DMA1CTL_H OFS_DMA1CTL+1 +#define OFS_DMA1SA (0x0022) /* DMA Channel 1 Source Address */ +#define OFS_DMA1DA (0x0026) /* DMA Channel 1 Destination Address */ +#define OFS_DMA1SZ (0x002A) /* DMA Channel 1 Transfer Size */ + +#define OFS_DMA2CTL (0x0030) /* DMA Channel 2 Control */ +#define OFS_DMA2CTL_L OFS_DMA2CTL +#define OFS_DMA2CTL_H OFS_DMA2CTL+1 +#define OFS_DMA2SA (0x0032) /* DMA Channel 2 Source Address */ +#define OFS_DMA2DA (0x0036) /* DMA Channel 2 Destination Address */ +#define OFS_DMA2SZ (0x003A) /* DMA Channel 2 Transfer Size */ + +#define OFS_DMA3CTL (0x0040) /* DMA Channel 3 Control */ +#define OFS_DMA3CTL_L OFS_DMA3CTL +#define OFS_DMA3CTL_H OFS_DMA3CTL+1 +#define OFS_DMA3SA (0x0042) /* DMA Channel 3 Source Address */ +#define OFS_DMA3DA (0x0046) /* DMA Channel 3 Destination Address */ +#define OFS_DMA3SZ (0x004A) /* DMA Channel 3 Transfer Size */ + +#define OFS_DMA4CTL (0x0050) /* DMA Channel 4 Control */ +#define OFS_DMA4CTL_L OFS_DMA4CTL +#define OFS_DMA4CTL_H OFS_DMA4CTL+1 +#define OFS_DMA4SA (0x0052) /* DMA Channel 4 Source Address */ +#define OFS_DMA4DA (0x0056) /* DMA Channel 4 Destination Address */ +#define OFS_DMA4SZ (0x005A) /* DMA Channel 4 Transfer Size */ + +#define OFS_DMA5CTL (0x0060) /* DMA Channel 5 Control */ +#define OFS_DMA5CTL_L OFS_DMA5CTL +#define OFS_DMA5CTL_H OFS_DMA5CTL+1 +#define OFS_DMA5SA (0x0062) /* DMA Channel 5 Source Address */ +#define OFS_DMA5DA (0x0066) /* DMA Channel 5 Destination Address */ +#define OFS_DMA5SZ (0x006A) /* DMA Channel 5 Transfer Size */ + +/* DMACTL0 Control Bits */ +#define DMA0TSEL0 (0x0001) /* DMA channel 0 transfer select bit 0 */ +#define DMA0TSEL1 (0x0002) /* DMA channel 0 transfer select bit 1 */ +#define DMA0TSEL2 (0x0004) /* DMA channel 0 transfer select bit 2 */ +#define DMA0TSEL3 (0x0008) /* DMA channel 0 transfer select bit 3 */ +#define DMA0TSEL4 (0x0010) /* DMA channel 0 transfer select bit 4 */ +#define DMA1TSEL0 (0x0100) /* DMA channel 1 transfer select bit 0 */ +#define DMA1TSEL1 (0x0200) /* DMA channel 1 transfer select bit 1 */ +#define DMA1TSEL2 (0x0400) /* DMA channel 1 transfer select bit 2 */ +#define DMA1TSEL3 (0x0800) /* DMA channel 1 transfer select bit 3 */ +#define DMA1TSEL4 (0x1000) /* DMA channel 1 transfer select bit 4 */ + +/* DMACTL0 Control Bits */ +#define DMA0TSEL0_L (0x0001) /* DMA channel 0 transfer select bit 0 */ +#define DMA0TSEL1_L (0x0002) /* DMA channel 0 transfer select bit 1 */ +#define DMA0TSEL2_L (0x0004) /* DMA channel 0 transfer select bit 2 */ +#define DMA0TSEL3_L (0x0008) /* DMA channel 0 transfer select bit 3 */ +#define DMA0TSEL4_L (0x0010) /* DMA channel 0 transfer select bit 4 */ + +/* DMACTL0 Control Bits */ +#define DMA1TSEL0_H (0x0001) /* DMA channel 1 transfer select bit 0 */ +#define DMA1TSEL1_H (0x0002) /* DMA channel 1 transfer select bit 1 */ +#define DMA1TSEL2_H (0x0004) /* DMA channel 1 transfer select bit 2 */ +#define DMA1TSEL3_H (0x0008) /* DMA channel 1 transfer select bit 3 */ +#define DMA1TSEL4_H (0x0010) /* DMA channel 1 transfer select bit 4 */ + +/* DMACTL01 Control Bits */ +#define DMA2TSEL0 (0x0001) /* DMA channel 2 transfer select bit 0 */ +#define DMA2TSEL1 (0x0002) /* DMA channel 2 transfer select bit 1 */ +#define DMA2TSEL2 (0x0004) /* DMA channel 2 transfer select bit 2 */ +#define DMA2TSEL3 (0x0008) /* DMA channel 2 transfer select bit 3 */ +#define DMA2TSEL4 (0x0010) /* DMA channel 2 transfer select bit 4 */ +#define DMA3TSEL0 (0x0100) /* DMA channel 3 transfer select bit 0 */ +#define DMA3TSEL1 (0x0200) /* DMA channel 3 transfer select bit 1 */ +#define DMA3TSEL2 (0x0400) /* DMA channel 3 transfer select bit 2 */ +#define DMA3TSEL3 (0x0800) /* DMA channel 3 transfer select bit 3 */ +#define DMA3TSEL4 (0x1000) /* DMA channel 3 transfer select bit 4 */ + +/* DMACTL01 Control Bits */ +#define DMA2TSEL0_L (0x0001) /* DMA channel 2 transfer select bit 0 */ +#define DMA2TSEL1_L (0x0002) /* DMA channel 2 transfer select bit 1 */ +#define DMA2TSEL2_L (0x0004) /* DMA channel 2 transfer select bit 2 */ +#define DMA2TSEL3_L (0x0008) /* DMA channel 2 transfer select bit 3 */ +#define DMA2TSEL4_L (0x0010) /* DMA channel 2 transfer select bit 4 */ + +/* DMACTL01 Control Bits */ +#define DMA3TSEL0_H (0x0001) /* DMA channel 3 transfer select bit 0 */ +#define DMA3TSEL1_H (0x0002) /* DMA channel 3 transfer select bit 1 */ +#define DMA3TSEL2_H (0x0004) /* DMA channel 3 transfer select bit 2 */ +#define DMA3TSEL3_H (0x0008) /* DMA channel 3 transfer select bit 3 */ +#define DMA3TSEL4_H (0x0010) /* DMA channel 3 transfer select bit 4 */ + +/* DMACTL0 Control Bits */ +#define DMA4TSEL0 (0x0001) /* DMA channel 4 transfer select bit 0 */ +#define DMA4TSEL1 (0x0002) /* DMA channel 4 transfer select bit 1 */ +#define DMA4TSEL2 (0x0004) /* DMA channel 4 transfer select bit 2 */ +#define DMA4TSEL3 (0x0008) /* DMA channel 4 transfer select bit 3 */ +#define DMA4TSEL4 (0x0010) /* DMA channel 4 transfer select bit 4 */ +#define DMA5TSEL0 (0x0100) /* DMA channel 5 transfer select bit 0 */ +#define DMA5TSEL1 (0x0200) /* DMA channel 5 transfer select bit 1 */ +#define DMA5TSEL2 (0x0400) /* DMA channel 5 transfer select bit 2 */ +#define DMA5TSEL3 (0x0800) /* DMA channel 5 transfer select bit 3 */ +#define DMA5TSEL4 (0x1000) /* DMA channel 5 transfer select bit 4 */ + +/* DMACTL0 Control Bits */ +#define DMA4TSEL0_L (0x0001) /* DMA channel 4 transfer select bit 0 */ +#define DMA4TSEL1_L (0x0002) /* DMA channel 4 transfer select bit 1 */ +#define DMA4TSEL2_L (0x0004) /* DMA channel 4 transfer select bit 2 */ +#define DMA4TSEL3_L (0x0008) /* DMA channel 4 transfer select bit 3 */ +#define DMA4TSEL4_L (0x0010) /* DMA channel 4 transfer select bit 4 */ + +/* DMACTL0 Control Bits */ +#define DMA5TSEL0_H (0x0001) /* DMA channel 5 transfer select bit 0 */ +#define DMA5TSEL1_H (0x0002) /* DMA channel 5 transfer select bit 1 */ +#define DMA5TSEL2_H (0x0004) /* DMA channel 5 transfer select bit 2 */ +#define DMA5TSEL3_H (0x0008) /* DMA channel 5 transfer select bit 3 */ +#define DMA5TSEL4_H (0x0010) /* DMA channel 5 transfer select bit 4 */ + +/* DMACTL4 Control Bits */ +#define ENNMI (0x0001) /* Enable NMI interruption of DMA */ +#define ROUNDROBIN (0x0002) /* Round-Robin DMA channel priorities */ +#define DMARMWDIS (0x0004) /* Inhibited DMA transfers during read-modify-write CPU operations */ + +/* DMACTL4 Control Bits */ +#define ENNMI_L (0x0001) /* Enable NMI interruption of DMA */ +#define ROUNDROBIN_L (0x0002) /* Round-Robin DMA channel priorities */ +#define DMARMWDIS_L (0x0004) /* Inhibited DMA transfers during read-modify-write CPU operations */ + +/* DMAxCTL Control Bits */ +#define DMAREQ (0x0001) /* Initiate DMA transfer with DMATSEL */ +#define DMAABORT (0x0002) /* DMA transfer aborted by NMI */ +#define DMAIE (0x0004) /* DMA interrupt enable */ +#define DMAIFG (0x0008) /* DMA interrupt flag */ +#define DMAEN (0x0010) /* DMA enable */ +#define DMALEVEL (0x0020) /* DMA level sensitive trigger select */ +#define DMASRCBYTE (0x0040) /* DMA source byte */ +#define DMADSTBYTE (0x0080) /* DMA destination byte */ +#define DMASRCINCR0 (0x0100) /* DMA source increment bit 0 */ +#define DMASRCINCR1 (0x0200) /* DMA source increment bit 1 */ +#define DMADSTINCR0 (0x0400) /* DMA destination increment bit 0 */ +#define DMADSTINCR1 (0x0800) /* DMA destination increment bit 1 */ +#define DMADT0 (0x1000) /* DMA transfer mode bit 0 */ +#define DMADT1 (0x2000) /* DMA transfer mode bit 1 */ +#define DMADT2 (0x4000) /* DMA transfer mode bit 2 */ + +/* DMAxCTL Control Bits */ +#define DMAREQ_L (0x0001) /* Initiate DMA transfer with DMATSEL */ +#define DMAABORT_L (0x0002) /* DMA transfer aborted by NMI */ +#define DMAIE_L (0x0004) /* DMA interrupt enable */ +#define DMAIFG_L (0x0008) /* DMA interrupt flag */ +#define DMAEN_L (0x0010) /* DMA enable */ +#define DMALEVEL_L (0x0020) /* DMA level sensitive trigger select */ +#define DMASRCBYTE_L (0x0040) /* DMA source byte */ +#define DMADSTBYTE_L (0x0080) /* DMA destination byte */ + +/* DMAxCTL Control Bits */ +#define DMASRCINCR0_H (0x0001) /* DMA source increment bit 0 */ +#define DMASRCINCR1_H (0x0002) /* DMA source increment bit 1 */ +#define DMADSTINCR0_H (0x0004) /* DMA destination increment bit 0 */ +#define DMADSTINCR1_H (0x0008) /* DMA destination increment bit 1 */ +#define DMADT0_H (0x0010) /* DMA transfer mode bit 0 */ +#define DMADT1_H (0x0020) /* DMA transfer mode bit 1 */ +#define DMADT2_H (0x0040) /* DMA transfer mode bit 2 */ + +#define DMASWDW (0*0x0040u) /* DMA transfer: source word to destination word */ +#define DMASBDW (1*0x0040u) /* DMA transfer: source byte to destination word */ +#define DMASWDB (2*0x0040u) /* DMA transfer: source word to destination byte */ +#define DMASBDB (3*0x0040u) /* DMA transfer: source byte to destination byte */ + +#define DMASRCINCR_0 (0*0x0100u) /* DMA source increment 0: source address unchanged */ +#define DMASRCINCR_1 (1*0x0100u) /* DMA source increment 1: source address unchanged */ +#define DMASRCINCR_2 (2*0x0100u) /* DMA source increment 2: source address decremented */ +#define DMASRCINCR_3 (3*0x0100u) /* DMA source increment 3: source address incremented */ + +#define DMADSTINCR_0 (0*0x0400u) /* DMA destination increment 0: destination address unchanged */ +#define DMADSTINCR_1 (1*0x0400u) /* DMA destination increment 1: destination address unchanged */ +#define DMADSTINCR_2 (2*0x0400u) /* DMA destination increment 2: destination address decremented */ +#define DMADSTINCR_3 (3*0x0400u) /* DMA destination increment 3: destination address incremented */ + +#define DMADT_0 (0*0x1000u) /* DMA transfer mode 0: Single transfer */ +#define DMADT_1 (1*0x1000u) /* DMA transfer mode 1: Block transfer */ +#define DMADT_2 (2*0x1000u) /* DMA transfer mode 2: Burst-Block transfer */ +#define DMADT_3 (3*0x1000u) /* DMA transfer mode 3: Burst-Block transfer */ +#define DMADT_4 (4*0x1000u) /* DMA transfer mode 4: Repeated Single transfer */ +#define DMADT_5 (5*0x1000u) /* DMA transfer mode 5: Repeated Block transfer */ +#define DMADT_6 (6*0x1000u) /* DMA transfer mode 6: Repeated Burst-Block transfer */ +#define DMADT_7 (7*0x1000u) /* DMA transfer mode 7: Repeated Burst-Block transfer */ + +/* DMAIV Definitions */ +#define DMAIV_NONE (0x0000) /* No Interrupt pending */ +#define DMAIV_DMA0IFG (0x0002) /* DMA0IFG*/ +#define DMAIV_DMA1IFG (0x0004) /* DMA1IFG*/ +#define DMAIV_DMA2IFG (0x0006) /* DMA2IFG*/ +#define DMAIV_DMA3IFG (0x0008) /* DMA3IFG*/ +#define DMAIV_DMA4IFG (0x000A) /* DMA4IFG*/ +#define DMAIV_DMA5IFG (0x000C) /* DMA5IFG*/ + +#endif +/************************************************************* +* Flash Memory +*************************************************************/ +#ifdef __MSP430_HAS_FLASH__ /* Definition to show that Module is available */ + +#define OFS_FCTL1 (0x0000) /* FLASH Control 1 */ +#define OFS_FCTL1_L OFS_FCTL1 +#define OFS_FCTL1_H OFS_FCTL1+1 +//#define FCTL2_O (0x0002) /* FLASH Control 2 */ +#define OFS_FCTL3 (0x0004) /* FLASH Control 3 */ +#define OFS_FCTL3_L OFS_FCTL3 +#define OFS_FCTL3_H OFS_FCTL3+1 +#define OFS_FCTL4 (0x0006) /* FLASH Control 4 */ +#define OFS_FCTL4_L OFS_FCTL4 +#define OFS_FCTL4_H OFS_FCTL4+1 + +#define FRPW (0x9600) /* Flash password returned by read */ +#define FWPW (0xA500) /* Flash password for write */ +#define FXPW (0x3300) /* for use with XOR instruction */ +#define FRKEY (0x9600) /* (legacy definition) Flash key returned by read */ +#define FWKEY (0xA500) /* (legacy definition) Flash key for write */ +#define FXKEY (0x3300) /* (legacy definition) for use with XOR instruction */ + +/* FCTL1 Control Bits */ +//#define RESERVED (0x0001) /* Reserved */ +#define ERASE (0x0002) /* Enable bit for Flash segment erase */ +#define MERAS (0x0004) /* Enable bit for Flash mass erase */ +//#define RESERVED (0x0008) /* Reserved */ +//#define RESERVED (0x0010) /* Reserved */ +#define SWRT (0x0020) /* Smart Write enable */ +#define WRT (0x0040) /* Enable bit for Flash write */ +#define BLKWRT (0x0080) /* Enable bit for Flash segment write */ + +/* FCTL1 Control Bits */ +//#define RESERVED (0x0001) /* Reserved */ +#define ERASE_L (0x0002) /* Enable bit for Flash segment erase */ +#define MERAS_L (0x0004) /* Enable bit for Flash mass erase */ +//#define RESERVED (0x0008) /* Reserved */ +//#define RESERVED (0x0010) /* Reserved */ +#define SWRT_L (0x0020) /* Smart Write enable */ +#define WRT_L (0x0040) /* Enable bit for Flash write */ +#define BLKWRT_L (0x0080) /* Enable bit for Flash segment write */ + +/* FCTL3 Control Bits */ +#define BUSY (0x0001) /* Flash busy: 1 */ +#define KEYV (0x0002) /* Flash Key violation flag */ +#define ACCVIFG (0x0004) /* Flash Access violation flag */ +#define WAIT (0x0008) /* Wait flag for segment write */ +#define LOCK (0x0010) /* Lock bit: 1 - Flash is locked (read only) */ +#define EMEX (0x0020) /* Flash Emergency Exit */ +#define LOCKA (0x0040) /* Segment A Lock bit: read = 1 - Segment is locked (read only) */ +//#define RESERVED (0x0080) /* Reserved */ + +/* FCTL3 Control Bits */ +#define BUSY_L (0x0001) /* Flash busy: 1 */ +#define KEYV_L (0x0002) /* Flash Key violation flag */ +#define ACCVIFG_L (0x0004) /* Flash Access violation flag */ +#define WAIT_L (0x0008) /* Wait flag for segment write */ +#define LOCK_L (0x0010) /* Lock bit: 1 - Flash is locked (read only) */ +#define EMEX_L (0x0020) /* Flash Emergency Exit */ +#define LOCKA_L (0x0040) /* Segment A Lock bit: read = 1 - Segment is locked (read only) */ +//#define RESERVED (0x0080) /* Reserved */ + +/* FCTL4 Control Bits */ +#define VPE (0x0001) /* Voltage Changed during Program Error Flag */ +#define MGR0 (0x0010) /* Marginal read 0 mode. */ +#define MGR1 (0x0020) /* Marginal read 1 mode. */ +#define LOCKINFO (0x0080) /* Lock INFO Memory bit: read = 1 - Segment is locked (read only) */ + +/* FCTL4 Control Bits */ +#define VPE_L (0x0001) /* Voltage Changed during Program Error Flag */ +#define MGR0_L (0x0010) /* Marginal read 0 mode. */ +#define MGR1_L (0x0020) /* Marginal read 1 mode. */ +#define LOCKINFO_L (0x0080) /* Lock INFO Memory bit: read = 1 - Segment is locked (read only) */ + +#endif +/************************************************************ +* LCD_B +************************************************************/ +#ifdef __MSP430_HAS_LCD_B__ /* Definition to show that Module is available */ + +#define OFS_LCDBCTL0 (0x0000) /* LCD_B Control Register 0 */ +#define OFS_LCDBCTL0_L OFS_LCDBCTL0 +#define OFS_LCDBCTL0_H OFS_LCDBCTL0+1 +#define OFS_LCDBCTL1 (0x0002) /* LCD_B Control Register 1 */ +#define OFS_LCDBCTL1_L OFS_LCDBCTL1 +#define OFS_LCDBCTL1_H OFS_LCDBCTL1+1 +#define OFS_LCDBBLKCTL (0x0004) /* LCD_B blinking control register */ +#define OFS_LCDBBLKCTL_L OFS_LCDBBLKCTL +#define OFS_LCDBBLKCTL_H OFS_LCDBBLKCTL+1 +#define OFS_LCDBMEMCTL (0x0006) /* LCD_B memory control register */ +#define OFS_LCDBMEMCTL_L OFS_LCDBMEMCTL +#define OFS_LCDBMEMCTL_H OFS_LCDBMEMCTL+1 +#define OFS_LCDBVCTL (0x0008) /* LCD_B Voltage Control Register */ +#define OFS_LCDBVCTL_L OFS_LCDBVCTL +#define OFS_LCDBVCTL_H OFS_LCDBVCTL+1 +#define OFS_LCDBPCTL0 (0x000A) /* LCD_B Port Control Register 0 */ +#define OFS_LCDBPCTL0_L OFS_LCDBPCTL0 +#define OFS_LCDBPCTL0_H OFS_LCDBPCTL0+1 +#define OFS_LCDBPCTL1 (0x000C) /* LCD_B Port Control Register 1 */ +#define OFS_LCDBPCTL1_L OFS_LCDBPCTL1 +#define OFS_LCDBPCTL1_H OFS_LCDBPCTL1+1 +#define OFS_LCDBPCTL2 (0x000E) /* LCD_B Port Control Register 2 */ +#define OFS_LCDBPCTL2_L OFS_LCDBPCTL2 +#define OFS_LCDBPCTL2_H OFS_LCDBPCTL2+1 +#define OFS_LCDBPCTL3 (0x0010) /* LCD_B Port Control Register 3 */ +#define OFS_LCDBPCTL3_L OFS_LCDBPCTL3 +#define OFS_LCDBPCTL3_H OFS_LCDBPCTL3+1 +#define OFS_LCDBCPCTL (0x0012) /* LCD_B Charge Pump Control Register 3 */ +#define OFS_LCDBCPCTL_L OFS_LCDBCPCTL +#define OFS_LCDBCPCTL_H OFS_LCDBCPCTL+1 +#define OFS_LCDBIV (0x001E) /* LCD_B Interrupt Vector Register */ + +// LCDBCTL0 +#define LCDON (0x0001) /* LCD_B LCD On */ +#define LCDSON (0x0004) /* LCD_B LCD Segments On */ +#define LCDMX0 (0x0008) /* LCD_B Mux Rate Bit: 0 */ +#define LCDMX1 (0x0010) /* LCD_B Mux Rate Bit: 1 */ +//#define RESERVED (0x0020) /* LCD_B RESERVED */ +//#define RESERVED (0x0040) /* LCD_B RESERVED */ +#define LCDSSEL (0x0080) /* LCD_B Clock Select */ +#define LCDPRE0 (0x0100) /* LCD_B LCD frequency pre-scaler Bit: 0 */ +#define LCDPRE1 (0x0200) /* LCD_B LCD frequency pre-scaler Bit: 1 */ +#define LCDPRE2 (0x0400) /* LCD_B LCD frequency pre-scaler Bit: 2 */ +#define LCDDIV0 (0x0800) /* LCD_B LCD frequency divider Bit: 0 */ +#define LCDDIV1 (0x1000) /* LCD_B LCD frequency divider Bit: 1 */ +#define LCDDIV2 (0x2000) /* LCD_B LCD frequency divider Bit: 2 */ +#define LCDDIV3 (0x4000) /* LCD_B LCD frequency divider Bit: 3 */ +#define LCDDIV4 (0x8000) /* LCD_B LCD frequency divider Bit: 4 */ + +// LCDBCTL0 +#define LCDON_L (0x0001) /* LCD_B LCD On */ +#define LCDSON_L (0x0004) /* LCD_B LCD Segments On */ +#define LCDMX0_L (0x0008) /* LCD_B Mux Rate Bit: 0 */ +#define LCDMX1_L (0x0010) /* LCD_B Mux Rate Bit: 1 */ +//#define RESERVED (0x0020) /* LCD_B RESERVED */ +//#define RESERVED (0x0040) /* LCD_B RESERVED */ +#define LCDSSEL_L (0x0080) /* LCD_B Clock Select */ + +// LCDBCTL0 +//#define RESERVED (0x0020) /* LCD_B RESERVED */ +//#define RESERVED (0x0040) /* LCD_B RESERVED */ +#define LCDPRE0_H (0x0001) /* LCD_B LCD frequency pre-scaler Bit: 0 */ +#define LCDPRE1_H (0x0002) /* LCD_B LCD frequency pre-scaler Bit: 1 */ +#define LCDPRE2_H (0x0004) /* LCD_B LCD frequency pre-scaler Bit: 2 */ +#define LCDDIV0_H (0x0008) /* LCD_B LCD frequency divider Bit: 0 */ +#define LCDDIV1_H (0x0010) /* LCD_B LCD frequency divider Bit: 1 */ +#define LCDDIV2_H (0x0020) /* LCD_B LCD frequency divider Bit: 2 */ +#define LCDDIV3_H (0x0040) /* LCD_B LCD frequency divider Bit: 3 */ +#define LCDDIV4_H (0x0080) /* LCD_B LCD frequency divider Bit: 4 */ + +#define LCDPRE_0 (0x0000) /* LCD_B LCD frequency pre-scaler: /1 */ +#define LCDPRE_1 (0x0100) /* LCD_B LCD frequency pre-scaler: /2 */ +#define LCDPRE_2 (0x0200) /* LCD_B LCD frequency pre-scaler: /4 */ +#define LCDPRE_3 (0x0300) /* LCD_B LCD frequency pre-scaler: /8 */ +#define LCDPRE_4 (0x0400) /* LCD_B LCD frequency pre-scaler: /16 */ +#define LCDPRE_5 (0x0500) /* LCD_B LCD frequency pre-scaler: /32 */ +#define LCDPRE__1 (0x0000) /* LCD_B LCD frequency pre-scaler: /1 */ +#define LCDPRE__2 (0x0100) /* LCD_B LCD frequency pre-scaler: /2 */ +#define LCDPRE__4 (0x0200) /* LCD_B LCD frequency pre-scaler: /4 */ +#define LCDPRE__8 (0x0300) /* LCD_B LCD frequency pre-scaler: /8 */ +#define LCDPRE__16 (0x0400) /* LCD_B LCD frequency pre-scaler: /16 */ +#define LCDPRE__32 (0x0500) /* LCD_B LCD frequency pre-scaler: /32 */ + +#define LCDDIV_0 (0x0000) /* LCD_B LCD frequency divider: /1 */ +#define LCDDIV_1 (0x0800) /* LCD_B LCD frequency divider: /2 */ +#define LCDDIV_2 (0x1000) /* LCD_B LCD frequency divider: /3 */ +#define LCDDIV_3 (0x1800) /* LCD_B LCD frequency divider: /4 */ +#define LCDDIV_4 (0x2000) /* LCD_B LCD frequency divider: /5 */ +#define LCDDIV_5 (0x2800) /* LCD_B LCD frequency divider: /6 */ +#define LCDDIV_6 (0x3000) /* LCD_B LCD frequency divider: /7 */ +#define LCDDIV_7 (0x3800) /* LCD_B LCD frequency divider: /8 */ +#define LCDDIV_8 (0x4000) /* LCD_B LCD frequency divider: /9 */ +#define LCDDIV_9 (0x4800) /* LCD_B LCD frequency divider: /10 */ +#define LCDDIV_10 (0x5000) /* LCD_B LCD frequency divider: /11 */ +#define LCDDIV_11 (0x5800) /* LCD_B LCD frequency divider: /12 */ +#define LCDDIV_12 (0x6000) /* LCD_B LCD frequency divider: /13 */ +#define LCDDIV_13 (0x6800) /* LCD_B LCD frequency divider: /14 */ +#define LCDDIV_14 (0x7000) /* LCD_B LCD frequency divider: /15 */ +#define LCDDIV_15 (0x7800) /* LCD_B LCD frequency divider: /16 */ +#define LCDDIV_16 (0x8000) /* LCD_B LCD frequency divider: /17 */ +#define LCDDIV_17 (0x8800) /* LCD_B LCD frequency divider: /18 */ +#define LCDDIV_18 (0x9000) /* LCD_B LCD frequency divider: /19 */ +#define LCDDIV_19 (0x9800) /* LCD_B LCD frequency divider: /20 */ +#define LCDDIV_20 (0xA000) /* LCD_B LCD frequency divider: /21 */ +#define LCDDIV_21 (0xA800) /* LCD_B LCD frequency divider: /22 */ +#define LCDDIV_22 (0xB000) /* LCD_B LCD frequency divider: /23 */ +#define LCDDIV_23 (0xB800) /* LCD_B LCD frequency divider: /24 */ +#define LCDDIV_24 (0xC000) /* LCD_B LCD frequency divider: /25 */ +#define LCDDIV_25 (0xC800) /* LCD_B LCD frequency divider: /26 */ +#define LCDDIV_26 (0xD000) /* LCD_B LCD frequency divider: /27 */ +#define LCDDIV_27 (0xD800) /* LCD_B LCD frequency divider: /28 */ +#define LCDDIV_28 (0xE000) /* LCD_B LCD frequency divider: /29 */ +#define LCDDIV_29 (0xE800) /* LCD_B LCD frequency divider: /30 */ +#define LCDDIV_30 (0xF000) /* LCD_B LCD frequency divider: /31 */ +#define LCDDIV_31 (0xF800) /* LCD_B LCD frequency divider: /32 */ +#define LCDDIV__1 (0x0000) /* LCD_B LCD frequency divider: /1 */ +#define LCDDIV__2 (0x0800) /* LCD_B LCD frequency divider: /2 */ +#define LCDDIV__3 (0x1000) /* LCD_B LCD frequency divider: /3 */ +#define LCDDIV__4 (0x1800) /* LCD_B LCD frequency divider: /4 */ +#define LCDDIV__5 (0x2000) /* LCD_B LCD frequency divider: /5 */ +#define LCDDIV__6 (0x2800) /* LCD_B LCD frequency divider: /6 */ +#define LCDDIV__7 (0x3000) /* LCD_B LCD frequency divider: /7 */ +#define LCDDIV__8 (0x3800) /* LCD_B LCD frequency divider: /8 */ +#define LCDDIV__9 (0x4000) /* LCD_B LCD frequency divider: /9 */ +#define LCDDIV__10 (0x4800) /* LCD_B LCD frequency divider: /10 */ +#define LCDDIV__11 (0x5000) /* LCD_B LCD frequency divider: /11 */ +#define LCDDIV__12 (0x5800) /* LCD_B LCD frequency divider: /12 */ +#define LCDDIV__13 (0x6000) /* LCD_B LCD frequency divider: /13 */ +#define LCDDIV__14 (0x6800) /* LCD_B LCD frequency divider: /14 */ +#define LCDDIV__15 (0x7000) /* LCD_B LCD frequency divider: /15 */ +#define LCDDIV__16 (0x7800) /* LCD_B LCD frequency divider: /16 */ +#define LCDDIV__17 (0x8000) /* LCD_B LCD frequency divider: /17 */ +#define LCDDIV__18 (0x8800) /* LCD_B LCD frequency divider: /18 */ +#define LCDDIV__19 (0x9000) /* LCD_B LCD frequency divider: /19 */ +#define LCDDIV__20 (0x9800) /* LCD_B LCD frequency divider: /20 */ +#define LCDDIV__21 (0xA000) /* LCD_B LCD frequency divider: /21 */ +#define LCDDIV__22 (0xA800) /* LCD_B LCD frequency divider: /22 */ +#define LCDDIV__23 (0xB000) /* LCD_B LCD frequency divider: /23 */ +#define LCDDIV__24 (0xB800) /* LCD_B LCD frequency divider: /24 */ +#define LCDDIV__25 (0xC000) /* LCD_B LCD frequency divider: /25 */ +#define LCDDIV__26 (0xC800) /* LCD_B LCD frequency divider: /26 */ +#define LCDDIV__27 (0xD000) /* LCD_B LCD frequency divider: /27 */ +#define LCDDIV__28 (0xD800) /* LCD_B LCD frequency divider: /28 */ +#define LCDDIV__29 (0xE000) /* LCD_B LCD frequency divider: /29 */ +#define LCDDIV__30 (0xE800) /* LCD_B LCD frequency divider: /30 */ +#define LCDDIV__31 (0xF000) /* LCD_B LCD frequency divider: /31 */ +#define LCDDIV__32 (0xF800) /* LCD_B LCD frequency divider: /32 */ + +/* Display modes coded with Bits 2-4 */ +#define LCDSTATIC (LCDSON) +#define LCD2MUX (LCDMX0+LCDSON) +#define LCD3MUX (LCDMX1+LCDSON) +#define LCD4MUX (LCDMX1+LCDMX0+LCDSON) + +// LCDBCTL1 +#define LCDFRMIFG (0x0001) /* LCD_B LCD frame interrupt flag */ +#define LCDBLKOFFIFG (0x0002) /* LCD_B LCD blinking off interrupt flag, */ +#define LCDBLKONIFG (0x0004) /* LCD_B LCD blinking on interrupt flag, */ +#define LCDNOCAPIFG (0x0008) /* LCD_B No cpacitance connected interrupt flag */ +#define LCDFRMIE (0x0100) /* LCD_B LCD frame interrupt enable */ +#define LCDBLKOFFIE (0x0200) /* LCD_B LCD blinking off interrupt flag, */ +#define LCDBLKONIE (0x0400) /* LCD_B LCD blinking on interrupt flag, */ +#define LCDNOCAPIE (0x0800) /* LCD_B No cpacitance connected interrupt enable */ + +// LCDBCTL1 +#define LCDFRMIFG_L (0x0001) /* LCD_B LCD frame interrupt flag */ +#define LCDBLKOFFIFG_L (0x0002) /* LCD_B LCD blinking off interrupt flag, */ +#define LCDBLKONIFG_L (0x0004) /* LCD_B LCD blinking on interrupt flag, */ +#define LCDNOCAPIFG_L (0x0008) /* LCD_B No cpacitance connected interrupt flag */ + +// LCDBCTL1 +#define LCDFRMIE_H (0x0001) /* LCD_B LCD frame interrupt enable */ +#define LCDBLKOFFIE_H (0x0002) /* LCD_B LCD blinking off interrupt flag, */ +#define LCDBLKONIE_H (0x0004) /* LCD_B LCD blinking on interrupt flag, */ +#define LCDNOCAPIE_H (0x0008) /* LCD_B No cpacitance connected interrupt enable */ + +// LCDBBLKCTL +#define LCDBLKMOD0 (0x0001) /* LCD_B Blinking mode Bit: 0 */ +#define LCDBLKMOD1 (0x0002) /* LCD_B Blinking mode Bit: 1 */ +#define LCDBLKPRE0 (0x0004) /* LCD_B Clock pre-scaler for blinking frequency Bit: 0 */ +#define LCDBLKPRE1 (0x0008) /* LCD_B Clock pre-scaler for blinking frequency Bit: 1 */ +#define LCDBLKPRE2 (0x0010) /* LCD_B Clock pre-scaler for blinking frequency Bit: 2 */ +#define LCDBLKDIV0 (0x0020) /* LCD_B Clock divider for blinking frequency Bit: 0 */ +#define LCDBLKDIV1 (0x0040) /* LCD_B Clock divider for blinking frequency Bit: 1 */ +#define LCDBLKDIV2 (0x0080) /* LCD_B Clock divider for blinking frequency Bit: 2 */ + +// LCDBBLKCTL +#define LCDBLKMOD0_L (0x0001) /* LCD_B Blinking mode Bit: 0 */ +#define LCDBLKMOD1_L (0x0002) /* LCD_B Blinking mode Bit: 1 */ +#define LCDBLKPRE0_L (0x0004) /* LCD_B Clock pre-scaler for blinking frequency Bit: 0 */ +#define LCDBLKPRE1_L (0x0008) /* LCD_B Clock pre-scaler for blinking frequency Bit: 1 */ +#define LCDBLKPRE2_L (0x0010) /* LCD_B Clock pre-scaler for blinking frequency Bit: 2 */ +#define LCDBLKDIV0_L (0x0020) /* LCD_B Clock divider for blinking frequency Bit: 0 */ +#define LCDBLKDIV1_L (0x0040) /* LCD_B Clock divider for blinking frequency Bit: 1 */ +#define LCDBLKDIV2_L (0x0080) /* LCD_B Clock divider for blinking frequency Bit: 2 */ + +#define LCDBLKMOD_0 (0x0000) /* LCD_B Blinking mode: Off */ +#define LCDBLKMOD_1 (0x0001) /* LCD_B Blinking mode: Individual */ +#define LCDBLKMOD_2 (0x0002) /* LCD_B Blinking mode: All */ +#define LCDBLKMOD_3 (0x0003) /* LCD_B Blinking mode: Switching */ + +// LCDBMEMCTL +#define LCDDISP (0x0001) /* LCD_B LCD memory registers for display */ +#define LCDCLRM (0x0002) /* LCD_B Clear LCD memory */ +#define LCDCLRBM (0x0004) /* LCD_B Clear LCD blinking memory */ + +// LCDBMEMCTL +#define LCDDISP_L (0x0001) /* LCD_B LCD memory registers for display */ +#define LCDCLRM_L (0x0002) /* LCD_B Clear LCD memory */ +#define LCDCLRBM_L (0x0004) /* LCD_B Clear LCD blinking memory */ + +// LCDBVCTL +#define LCD2B (0x0001) /* Selects 1/2 bias. */ +#define VLCDREF0 (0x0002) /* Selects reference voltage for regulated charge pump: 0 */ +#define VLCDREF1 (0x0004) /* Selects reference voltage for regulated charge pump: 1 */ +#define LCDCPEN (0x0008) /* LCD Voltage Charge Pump Enable. */ +#define VLCDEXT (0x0010) /* Select external source for VLCD. */ +#define LCDEXTBIAS (0x0020) /* V2 - V4 voltage select. */ +#define R03EXT (0x0040) /* Selects external connections for LCD mid voltages. */ +#define LCDREXT (0x0080) /* Selects external connection for lowest LCD voltage. */ +#define VLCD0 (0x0200) /* VLCD select: 0 */ +#define VLCD1 (0x0400) /* VLCD select: 1 */ +#define VLCD2 (0x0800) /* VLCD select: 2 */ +#define VLCD3 (0x1000) /* VLCD select: 3 */ + +// LCDBVCTL +#define LCD2B_L (0x0001) /* Selects 1/2 bias. */ +#define VLCDREF0_L (0x0002) /* Selects reference voltage for regulated charge pump: 0 */ +#define VLCDREF1_L (0x0004) /* Selects reference voltage for regulated charge pump: 1 */ +#define LCDCPEN_L (0x0008) /* LCD Voltage Charge Pump Enable. */ +#define VLCDEXT_L (0x0010) /* Select external source for VLCD. */ +#define LCDEXTBIAS_L (0x0020) /* V2 - V4 voltage select. */ +#define R03EXT_L (0x0040) /* Selects external connections for LCD mid voltages. */ +#define LCDREXT_L (0x0080) /* Selects external connection for lowest LCD voltage. */ + +// LCDBVCTL +#define VLCD0_H (0x0002) /* VLCD select: 0 */ +#define VLCD1_H (0x0004) /* VLCD select: 1 */ +#define VLCD2_H (0x0008) /* VLCD select: 2 */ +#define VLCD3_H (0x0010) /* VLCD select: 3 */ + +/* Reference voltage source select for the regulated charge pump */ +#define VLCDREF_0 (0<<1) /* Internal */ +#define VLCDREF_1 (1<<1) /* External */ +#define VLCDREF_2 (2<<1) /* Reserved */ +#define VLCDREF_3 (3<<1) /* Reserved */ + +/* Charge pump voltage selections */ +#define VLCD_0 (0<<9) /* Charge pump disabled */ +#define VLCD_1 (1<<9) /* VLCD = 2.60V */ +#define VLCD_2 (2<<9) /* VLCD = 2.66V */ +#define VLCD_3 (3<<9) /* VLCD = 2.72V */ +#define VLCD_4 (4<<9) /* VLCD = 2.78V */ +#define VLCD_5 (5<<9) /* VLCD = 2.84V */ +#define VLCD_6 (6<<9) /* VLCD = 2.90V */ +#define VLCD_7 (7<<9) /* VLCD = 2.96V */ +#define VLCD_8 (8<<9) /* VLCD = 3.02V */ +#define VLCD_9 (9<<9) /* VLCD = 3.08V */ +#define VLCD_10 (10<<9) /* VLCD = 3.14V */ +#define VLCD_11 (11<<9) /* VLCD = 3.20V */ +#define VLCD_12 (12<<9) /* VLCD = 3.26V */ +#define VLCD_13 (13<<9) /* VLCD = 3.32V */ +#define VLCD_14 (14<<9) /* VLCD = 3.38V */ +#define VLCD_15 (15<<9) /* VLCD = 3.44V */ + +#define VLCD_DISABLED (0<<9) /* Charge pump disabled */ +#define VLCD_2_60 (1<<9) /* VLCD = 2.60V */ +#define VLCD_2_66 (2<<9) /* VLCD = 2.66V */ +#define VLCD_2_72 (3<<9) /* VLCD = 2.72V */ +#define VLCD_2_78 (4<<9) /* VLCD = 2.78V */ +#define VLCD_2_84 (5<<9) /* VLCD = 2.84V */ +#define VLCD_2_90 (6<<9) /* VLCD = 2.90V */ +#define VLCD_2_96 (7<<9) /* VLCD = 2.96V */ +#define VLCD_3_02 (8<<9) /* VLCD = 3.02V */ +#define VLCD_3_08 (9<<9) /* VLCD = 3.08V */ +#define VLCD_3_14 (10<<9) /* VLCD = 3.14V */ +#define VLCD_3_20 (11<<9) /* VLCD = 3.20V */ +#define VLCD_3_26 (12<<9) /* VLCD = 3.26V */ +#define VLCD_3_32 (13<<9) /* VLCD = 3.32V */ +#define VLCD_3_38 (14<<9) /* VLCD = 3.38V */ +#define VLCD_3_44 (15<<9) /* VLCD = 3.44V */ + +// LCDBPCTL0 +#define LCDS0 (0x0001) /* LCD Segment 0 enable. */ +#define LCDS1 (0x0002) /* LCD Segment 1 enable. */ +#define LCDS2 (0x0004) /* LCD Segment 2 enable. */ +#define LCDS3 (0x0008) /* LCD Segment 3 enable. */ +#define LCDS4 (0x0010) /* LCD Segment 4 enable. */ +#define LCDS5 (0x0020) /* LCD Segment 5 enable. */ +#define LCDS6 (0x0040) /* LCD Segment 6 enable. */ +#define LCDS7 (0x0080) /* LCD Segment 7 enable. */ +#define LCDS8 (0x0100) /* LCD Segment 8 enable. */ +#define LCDS9 (0x0200) /* LCD Segment 9 enable. */ +#define LCDS10 (0x0400) /* LCD Segment 10 enable. */ +#define LCDS11 (0x0800) /* LCD Segment 11 enable. */ +#define LCDS12 (0x1000) /* LCD Segment 12 enable. */ +#define LCDS13 (0x2000) /* LCD Segment 13 enable. */ +#define LCDS14 (0x4000) /* LCD Segment 14 enable. */ +#define LCDS15 (0x8000) /* LCD Segment 15 enable. */ + +// LCDBPCTL0 +#define LCDS0_L (0x0001) /* LCD Segment 0 enable. */ +#define LCDS1_L (0x0002) /* LCD Segment 1 enable. */ +#define LCDS2_L (0x0004) /* LCD Segment 2 enable. */ +#define LCDS3_L (0x0008) /* LCD Segment 3 enable. */ +#define LCDS4_L (0x0010) /* LCD Segment 4 enable. */ +#define LCDS5_L (0x0020) /* LCD Segment 5 enable. */ +#define LCDS6_L (0x0040) /* LCD Segment 6 enable. */ +#define LCDS7_L (0x0080) /* LCD Segment 7 enable. */ + +// LCDBPCTL0 +#define LCDS8_H (0x0001) /* LCD Segment 8 enable. */ +#define LCDS9_H (0x0002) /* LCD Segment 9 enable. */ +#define LCDS10_H (0x0004) /* LCD Segment 10 enable. */ +#define LCDS11_H (0x0008) /* LCD Segment 11 enable. */ +#define LCDS12_H (0x0010) /* LCD Segment 12 enable. */ +#define LCDS13_H (0x0020) /* LCD Segment 13 enable. */ +#define LCDS14_H (0x0040) /* LCD Segment 14 enable. */ +#define LCDS15_H (0x0080) /* LCD Segment 15 enable. */ + +// LCDBPCTL1 +#define LCDS16 (0x0001) /* LCD Segment 16 enable. */ +#define LCDS17 (0x0002) /* LCD Segment 17 enable. */ +#define LCDS18 (0x0004) /* LCD Segment 18 enable. */ +#define LCDS19 (0x0008) /* LCD Segment 19 enable. */ +#define LCDS20 (0x0010) /* LCD Segment 20 enable. */ +#define LCDS21 (0x0020) /* LCD Segment 21 enable. */ +#define LCDS22 (0x0040) /* LCD Segment 22 enable. */ +#define LCDS23 (0x0080) /* LCD Segment 23 enable. */ +#define LCDS24 (0x0100) /* LCD Segment 24 enable. */ +#define LCDS25 (0x0200) /* LCD Segment 25 enable. */ +#define LCDS26 (0x0400) /* LCD Segment 26 enable. */ +#define LCDS27 (0x0800) /* LCD Segment 27 enable. */ +#define LCDS28 (0x1000) /* LCD Segment 28 enable. */ +#define LCDS29 (0x2000) /* LCD Segment 29 enable. */ +#define LCDS30 (0x4000) /* LCD Segment 30 enable. */ +#define LCDS31 (0x8000) /* LCD Segment 31 enable. */ + +// LCDBPCTL1 +#define LCDS16_L (0x0001) /* LCD Segment 16 enable. */ +#define LCDS17_L (0x0002) /* LCD Segment 17 enable. */ +#define LCDS18_L (0x0004) /* LCD Segment 18 enable. */ +#define LCDS19_L (0x0008) /* LCD Segment 19 enable. */ +#define LCDS20_L (0x0010) /* LCD Segment 20 enable. */ +#define LCDS21_L (0x0020) /* LCD Segment 21 enable. */ +#define LCDS22_L (0x0040) /* LCD Segment 22 enable. */ +#define LCDS23_L (0x0080) /* LCD Segment 23 enable. */ + +// LCDBPCTL1 +#define LCDS24_H (0x0001) /* LCD Segment 24 enable. */ +#define LCDS25_H (0x0002) /* LCD Segment 25 enable. */ +#define LCDS26_H (0x0004) /* LCD Segment 26 enable. */ +#define LCDS27_H (0x0008) /* LCD Segment 27 enable. */ +#define LCDS28_H (0x0010) /* LCD Segment 28 enable. */ +#define LCDS29_H (0x0020) /* LCD Segment 29 enable. */ +#define LCDS30_H (0x0040) /* LCD Segment 30 enable. */ +#define LCDS31_H (0x0080) /* LCD Segment 31 enable. */ + +// LCDBPCTL2 +#define LCDS32 (0x0001) /* LCD Segment 32 enable. */ +#define LCDS33 (0x0002) /* LCD Segment 33 enable. */ +#define LCDS34 (0x0004) /* LCD Segment 34 enable. */ +#define LCDS35 (0x0008) /* LCD Segment 35 enable. */ +#define LCDS36 (0x0010) /* LCD Segment 36 enable. */ +#define LCDS37 (0x0020) /* LCD Segment 37 enable. */ +#define LCDS38 (0x0040) /* LCD Segment 38 enable. */ +#define LCDS39 (0x0080) /* LCD Segment 39 enable. */ +#define LCDS40 (0x0100) /* LCD Segment 40 enable. */ +#define LCDS41 (0x0200) /* LCD Segment 41 enable. */ +#define LCDS42 (0x0400) /* LCD Segment 42 enable. */ +#define LCDS43 (0x0800) /* LCD Segment 43 enable. */ +#define LCDS44 (0x1000) /* LCD Segment 44 enable. */ +#define LCDS45 (0x2000) /* LCD Segment 45 enable. */ +#define LCDS46 (0x4000) /* LCD Segment 46 enable. */ +#define LCDS47 (0x8000) /* LCD Segment 47 enable. */ + +// LCDBPCTL2 +#define LCDS32_L (0x0001) /* LCD Segment 32 enable. */ +#define LCDS33_L (0x0002) /* LCD Segment 33 enable. */ +#define LCDS34_L (0x0004) /* LCD Segment 34 enable. */ +#define LCDS35_L (0x0008) /* LCD Segment 35 enable. */ +#define LCDS36_L (0x0010) /* LCD Segment 36 enable. */ +#define LCDS37_L (0x0020) /* LCD Segment 37 enable. */ +#define LCDS38_L (0x0040) /* LCD Segment 38 enable. */ +#define LCDS39_L (0x0080) /* LCD Segment 39 enable. */ + +// LCDBPCTL2 +#define LCDS40_H (0x0001) /* LCD Segment 40 enable. */ +#define LCDS41_H (0x0002) /* LCD Segment 41 enable. */ +#define LCDS42_H (0x0004) /* LCD Segment 42 enable. */ +#define LCDS43_H (0x0008) /* LCD Segment 43 enable. */ +#define LCDS44_H (0x0010) /* LCD Segment 44 enable. */ +#define LCDS45_H (0x0020) /* LCD Segment 45 enable. */ +#define LCDS46_H (0x0040) /* LCD Segment 46 enable. */ +#define LCDS47_H (0x0080) /* LCD Segment 47 enable. */ + +// LCDBPCTL3 +#define LCDS48 (0x0001) /* LCD Segment 48 enable. */ +#define LCDS49 (0x0002) /* LCD Segment 49 enable. */ +#define LCDS50 (0x0004) /* LCD Segment 50 enable. */ + +// LCDBPCTL3 +#define LCDS48_L (0x0001) /* LCD Segment 48 enable. */ +#define LCDS49_L (0x0002) /* LCD Segment 49 enable. */ +#define LCDS50_L (0x0004) /* LCD Segment 50 enable. */ + +// LCDBCPCTL +#define LCDCPDIS0 (0x0001) /* LCD charge pump disable */ +#define LCDCPDIS1 (0x0002) /* LCD charge pump disable */ +#define LCDCPDIS2 (0x0004) /* LCD charge pump disable */ +#define LCDCPDIS3 (0x0008) /* LCD charge pump disable */ +#define LCDCPDIS4 (0x0010) /* LCD charge pump disable */ +#define LCDCPDIS5 (0x0020) /* LCD charge pump disable */ +#define LCDCPDIS6 (0x0040) /* LCD charge pump disable */ +#define LCDCPDIS7 (0x0080) /* LCD charge pump disable */ +#define LCDCPCLKSYNC (0x8000) /* LCD charge pump clock synchronization */ + +// LCDBCPCTL +#define LCDCPDIS0_L (0x0001) /* LCD charge pump disable */ +#define LCDCPDIS1_L (0x0002) /* LCD charge pump disable */ +#define LCDCPDIS2_L (0x0004) /* LCD charge pump disable */ +#define LCDCPDIS3_L (0x0008) /* LCD charge pump disable */ +#define LCDCPDIS4_L (0x0010) /* LCD charge pump disable */ +#define LCDCPDIS5_L (0x0020) /* LCD charge pump disable */ +#define LCDCPDIS6_L (0x0040) /* LCD charge pump disable */ +#define LCDCPDIS7_L (0x0080) /* LCD charge pump disable */ + +// LCDBCPCTL +#define LCDCPCLKSYNC_H (0x0080) /* LCD charge pump clock synchronization */ + +#define OFS_LCDM1 (0x0020) /* LCD Memory 1 */ +#define LCDMEM_ LCDM1 /* LCD Memory */ +#ifdef __ASM_HEADER__ +#define LCDMEM LCDM1 /* LCD Memory (for assembler) */ +#else +#define LCDMEM ((char*) &LCDM1) /* LCD Memory (for C) */ +#endif +#define OFS_LCDM2 (0x0021) /* LCD Memory 2 */ +#define OFS_LCDM3 (0x0022) /* LCD Memory 3 */ +#define OFS_LCDM4 (0x0023) /* LCD Memory 4 */ +#define OFS_LCDM5 (0x0024) /* LCD Memory 5 */ +#define OFS_LCDM6 (0x0025) /* LCD Memory 6 */ +#define OFS_LCDM7 (0x0026) /* LCD Memory 7 */ +#define OFS_LCDM8 (0x0027) /* LCD Memory 8 */ +#define OFS_LCDM9 (0x0028) /* LCD Memory 9 */ +#define OFS_LCDM10 (0x0029) /* LCD Memory 10 */ +#define OFS_LCDM11 (0x002A) /* LCD Memory 11 */ +#define OFS_LCDM12 (0x002B) /* LCD Memory 12 */ +#define OFS_LCDM13 (0x002C) /* LCD Memory 13 */ +#define OFS_LCDM14 (0x002D) /* LCD Memory 14 */ +#define OFS_LCDM15 (0x002E) /* LCD Memory 15 */ +#define OFS_LCDM16 (0x002F) /* LCD Memory 16 */ +#define OFS_LCDM17 (0x0030) /* LCD Memory 17 */ +#define OFS_LCDM18 (0x0031) /* LCD Memory 18 */ +#define OFS_LCDM19 (0x0032) /* LCD Memory 19 */ +#define OFS_LCDM20 (0x0033) /* LCD Memory 20 */ +#define OFS_LCDM21 (0x0034) /* LCD Memory 21 */ +#define OFS_LCDM22 (0x0035) /* LCD Memory 22 */ +#define OFS_LCDM23 (0x0036) /* LCD Memory 23 */ +#define OFS_LCDM24 (0x0037) /* LCD Memory 24 */ + +#define OFS_LCDBM1 (0x0040) /* LCD Blinking Memory 1 */ +#define LCDBMEM_ LCDBM1 /* LCD Blinking Memory */ +#ifdef __ASM_HEADER__ +#define LCDBMEM (LCDBM1) /* LCD Blinking Memory (for assembler) */ +#else +#define LCDBMEM ((char*) &LCDBM1) /* LCD Blinking Memory (for C) */ +#endif +#define OFS_LCDBM2 (0x0041) /* LCD Blinking Memory 2 */ +#define OFS_LCDBM3 (0x0042) /* LCD Blinking Memory 3 */ +#define OFS_LCDBM4 (0x0043) /* LCD Blinking Memory 4 */ +#define OFS_LCDBM5 (0x0044) /* LCD Blinking Memory 5 */ +#define OFS_LCDBM6 (0x0045) /* LCD Blinking Memory 6 */ +#define OFS_LCDBM7 (0x0046) /* LCD Blinking Memory 7 */ +#define OFS_LCDBM8 (0x0047) /* LCD Blinking Memory 8 */ +#define OFS_LCDBM9 (0x0048) /* LCD Blinking Memory 9 */ +#define OFS_LCDBM10 (0x0049) /* LCD Blinking Memory 10 */ +#define OFS_LCDBM11 (0x004A) /* LCD Blinking Memory 11 */ +#define OFS_LCDBM12 (0x004B) /* LCD Blinking Memory 12 */ +#define OFS_LCDBM13 (0x004C) /* LCD Blinking Memory 13 */ +#define OFS_LCDBM14 (0x004D) /* LCD Blinking Memory 14 */ +#define OFS_LCDBM15 (0x004E) /* LCD Blinking Memory 15 */ +#define OFS_LCDBM16 (0x004F) /* LCD Blinking Memory 16 */ +#define OFS_LCDBM17 (0x0050) /* LCD Blinking Memory 17 */ +#define OFS_LCDBM18 (0x0051) /* LCD Blinking Memory 18 */ +#define OFS_LCDBM19 (0x0052) /* LCD Blinking Memory 19 */ +#define OFS_LCDBM20 (0x0053) /* LCD Blinking Memory 20 */ +#define OFS_LCDBM21 (0x0054) /* LCD Blinking Memory 21 */ +#define OFS_LCDBM22 (0x0055) /* LCD Blinking Memory 22 */ +#define OFS_LCDBM23 (0x0056) /* LCD Blinking Memory 23 */ +#define OFS_LCDBM24 (0x0057) /* LCD Blinking Memory 24 */ + +/* LCDBIV Definitions */ +#define LCDBIV_NONE (0x0000) /* No Interrupt pending */ +#define LCDBIV_LCDNOCAPIFG (0x0002) /* No capacitor connected */ +#define LCDBIV_LCDBLKOFFIFG (0x0004) /* Blink, segments off */ +#define LCDBIV_LCDBLKONIFG (0x0006) /* Blink, segments on */ +#define LCDBIV_LCDFRMIFG (0x0008) /* Frame interrupt */ + +#endif +/************************************************************ +* LCD_C +************************************************************/ +#ifdef __MSP430_HAS_LCD_C__ /* Definition to show that Module is available */ + +#define OFS_LCDCCTL0 (0x0000) /* LCD_C Control Register 0 */ +#define OFS_LCDCCTL0_L OFS_LCDCCTL0 +#define OFS_LCDCCTL0_H OFS_LCDCCTL0+1 +#define OFS_LCDCCTL1 (0x0002) /* LCD_C Control Register 1 */ +#define OFS_LCDCCTL1_L OFS_LCDCCTL1 +#define OFS_LCDCCTL1_H OFS_LCDCCTL1+1 +#define OFS_LCDCBLKCTL (0x0004) /* LCD_C blinking control register */ +#define OFS_LCDCBLKCTL_L OFS_LCDCBLKCTL +#define OFS_LCDCBLKCTL_H OFS_LCDCBLKCTL+1 +#define OFS_LCDCMEMCTL (0x0006) /* LCD_C memory control register */ +#define OFS_LCDCMEMCTL_L OFS_LCDCMEMCTL +#define OFS_LCDCMEMCTL_H OFS_LCDCMEMCTL+1 +#define OFS_LCDCVCTL (0x0008) /* LCD_C Voltage Control Register */ +#define OFS_LCDCVCTL_L OFS_LCDCVCTL +#define OFS_LCDCVCTL_H OFS_LCDCVCTL+1 +#define OFS_LCDCPCTL0 (0x000A) /* LCD_C Port Control Register 0 */ +#define OFS_LCDCPCTL0_L OFS_LCDCPCTL0 +#define OFS_LCDCPCTL0_H OFS_LCDCPCTL0+1 +#define OFS_LCDCPCTL1 (0x000C) /* LCD_C Port Control Register 1 */ +#define OFS_LCDCPCTL1_L OFS_LCDCPCTL1 +#define OFS_LCDCPCTL1_H OFS_LCDCPCTL1+1 +#define OFS_LCDCPCTL2 (0x000E) /* LCD_C Port Control Register 2 */ +#define OFS_LCDCPCTL2_L OFS_LCDCPCTL2 +#define OFS_LCDCPCTL2_H OFS_LCDCPCTL2+1 +#define OFS_LCDCCPCTL (0x0012) /* LCD_C Charge Pump Control Register 3 */ +#define OFS_LCDCCPCTL_L OFS_LCDCCPCTL +#define OFS_LCDCCPCTL_H OFS_LCDCCPCTL+1 +#define OFS_LCDCIV (0x001E) /* LCD_C Interrupt Vector Register */ + +// LCDCCTL0 +#define LCDON (0x0001) /* LCD_C LCD On */ +#define LCDLP (0x0002) /* LCD_C Low Power Waveform */ +#define LCDSON (0x0004) /* LCD_C LCD Segments On */ +#define LCDMX0 (0x0008) /* LCD_C Mux Rate Bit: 0 */ +#define LCDMX1 (0x0010) /* LCD_C Mux Rate Bit: 1 */ +#define LCDMX2 (0x0020) /* LCD_C Mux Rate Bit: 2 */ +//#define RESERVED (0x0040) /* LCD_C RESERVED */ +#define LCDSSEL (0x0080) /* LCD_C Clock Select */ +#define LCDPRE0 (0x0100) /* LCD_C LCD frequency pre-scaler Bit: 0 */ +#define LCDPRE1 (0x0200) /* LCD_C LCD frequency pre-scaler Bit: 1 */ +#define LCDPRE2 (0x0400) /* LCD_C LCD frequency pre-scaler Bit: 2 */ +#define LCDDIV0 (0x0800) /* LCD_C LCD frequency divider Bit: 0 */ +#define LCDDIV1 (0x1000) /* LCD_C LCD frequency divider Bit: 1 */ +#define LCDDIV2 (0x2000) /* LCD_C LCD frequency divider Bit: 2 */ +#define LCDDIV3 (0x4000) /* LCD_C LCD frequency divider Bit: 3 */ +#define LCDDIV4 (0x8000) /* LCD_C LCD frequency divider Bit: 4 */ + +// LCDCCTL0 +#define LCDON_L (0x0001) /* LCD_C LCD On */ +#define LCDLP_L (0x0002) /* LCD_C Low Power Waveform */ +#define LCDSON_L (0x0004) /* LCD_C LCD Segments On */ +#define LCDMX0_L (0x0008) /* LCD_C Mux Rate Bit: 0 */ +#define LCDMX1_L (0x0010) /* LCD_C Mux Rate Bit: 1 */ +#define LCDMX2_L (0x0020) /* LCD_C Mux Rate Bit: 2 */ +//#define RESERVED (0x0040) /* LCD_C RESERVED */ +#define LCDSSEL_L (0x0080) /* LCD_C Clock Select */ + +// LCDCCTL0 +//#define RESERVED (0x0040) /* LCD_C RESERVED */ +#define LCDPRE0_H (0x0001) /* LCD_C LCD frequency pre-scaler Bit: 0 */ +#define LCDPRE1_H (0x0002) /* LCD_C LCD frequency pre-scaler Bit: 1 */ +#define LCDPRE2_H (0x0004) /* LCD_C LCD frequency pre-scaler Bit: 2 */ +#define LCDDIV0_H (0x0008) /* LCD_C LCD frequency divider Bit: 0 */ +#define LCDDIV1_H (0x0010) /* LCD_C LCD frequency divider Bit: 1 */ +#define LCDDIV2_H (0x0020) /* LCD_C LCD frequency divider Bit: 2 */ +#define LCDDIV3_H (0x0040) /* LCD_C LCD frequency divider Bit: 3 */ +#define LCDDIV4_H (0x0080) /* LCD_C LCD frequency divider Bit: 4 */ + +#define LCDPRE_0 (0x0000) /* LCD_C LCD frequency pre-scaler: /1 */ +#define LCDPRE_1 (0x0100) /* LCD_C LCD frequency pre-scaler: /2 */ +#define LCDPRE_2 (0x0200) /* LCD_C LCD frequency pre-scaler: /4 */ +#define LCDPRE_3 (0x0300) /* LCD_C LCD frequency pre-scaler: /8 */ +#define LCDPRE_4 (0x0400) /* LCD_C LCD frequency pre-scaler: /16 */ +#define LCDPRE_5 (0x0500) /* LCD_C LCD frequency pre-scaler: /32 */ +#define LCDPRE__1 (0x0000) /* LCD_C LCD frequency pre-scaler: /1 */ +#define LCDPRE__2 (0x0100) /* LCD_C LCD frequency pre-scaler: /2 */ +#define LCDPRE__4 (0x0200) /* LCD_C LCD frequency pre-scaler: /4 */ +#define LCDPRE__8 (0x0300) /* LCD_C LCD frequency pre-scaler: /8 */ +#define LCDPRE__16 (0x0400) /* LCD_C LCD frequency pre-scaler: /16 */ +#define LCDPRE__32 (0x0500) /* LCD_C LCD frequency pre-scaler: /32 */ + +#define LCDDIV_0 (0x0000) /* LCD_C LCD frequency divider: /1 */ +#define LCDDIV_1 (0x0800) /* LCD_C LCD frequency divider: /2 */ +#define LCDDIV_2 (0x1000) /* LCD_C LCD frequency divider: /3 */ +#define LCDDIV_3 (0x1800) /* LCD_C LCD frequency divider: /4 */ +#define LCDDIV_4 (0x2000) /* LCD_C LCD frequency divider: /5 */ +#define LCDDIV_5 (0x2800) /* LCD_C LCD frequency divider: /6 */ +#define LCDDIV_6 (0x3000) /* LCD_C LCD frequency divider: /7 */ +#define LCDDIV_7 (0x3800) /* LCD_C LCD frequency divider: /8 */ +#define LCDDIV_8 (0x4000) /* LCD_C LCD frequency divider: /9 */ +#define LCDDIV_9 (0x4800) /* LCD_C LCD frequency divider: /10 */ +#define LCDDIV_10 (0x5000) /* LCD_C LCD frequency divider: /11 */ +#define LCDDIV_11 (0x5800) /* LCD_C LCD frequency divider: /12 */ +#define LCDDIV_12 (0x6000) /* LCD_C LCD frequency divider: /13 */ +#define LCDDIV_13 (0x6800) /* LCD_C LCD frequency divider: /14 */ +#define LCDDIV_14 (0x7000) /* LCD_C LCD frequency divider: /15 */ +#define LCDDIV_15 (0x7800) /* LCD_C LCD frequency divider: /16 */ +#define LCDDIV_16 (0x8000) /* LCD_C LCD frequency divider: /17 */ +#define LCDDIV_17 (0x8800) /* LCD_C LCD frequency divider: /18 */ +#define LCDDIV_18 (0x9000) /* LCD_C LCD frequency divider: /19 */ +#define LCDDIV_19 (0x9800) /* LCD_C LCD frequency divider: /20 */ +#define LCDDIV_20 (0xA000) /* LCD_C LCD frequency divider: /21 */ +#define LCDDIV_21 (0xA800) /* LCD_C LCD frequency divider: /22 */ +#define LCDDIV_22 (0xB000) /* LCD_C LCD frequency divider: /23 */ +#define LCDDIV_23 (0xB800) /* LCD_C LCD frequency divider: /24 */ +#define LCDDIV_24 (0xC000) /* LCD_C LCD frequency divider: /25 */ +#define LCDDIV_25 (0xC800) /* LCD_C LCD frequency divider: /26 */ +#define LCDDIV_26 (0xD000) /* LCD_C LCD frequency divider: /27 */ +#define LCDDIV_27 (0xD800) /* LCD_C LCD frequency divider: /28 */ +#define LCDDIV_28 (0xE000) /* LCD_C LCD frequency divider: /29 */ +#define LCDDIV_29 (0xE800) /* LCD_C LCD frequency divider: /30 */ +#define LCDDIV_30 (0xF000) /* LCD_C LCD frequency divider: /31 */ +#define LCDDIV_31 (0xF800) /* LCD_C LCD frequency divider: /32 */ +#define LCDDIV__1 (0x0000) /* LCD_C LCD frequency divider: /1 */ +#define LCDDIV__2 (0x0800) /* LCD_C LCD frequency divider: /2 */ +#define LCDDIV__3 (0x1000) /* LCD_C LCD frequency divider: /3 */ +#define LCDDIV__4 (0x1800) /* LCD_C LCD frequency divider: /4 */ +#define LCDDIV__5 (0x2000) /* LCD_C LCD frequency divider: /5 */ +#define LCDDIV__6 (0x2800) /* LCD_C LCD frequency divider: /6 */ +#define LCDDIV__7 (0x3000) /* LCD_C LCD frequency divider: /7 */ +#define LCDDIV__8 (0x3800) /* LCD_C LCD frequency divider: /8 */ +#define LCDDIV__9 (0x4000) /* LCD_C LCD frequency divider: /9 */ +#define LCDDIV__10 (0x4800) /* LCD_C LCD frequency divider: /10 */ +#define LCDDIV__11 (0x5000) /* LCD_C LCD frequency divider: /11 */ +#define LCDDIV__12 (0x5800) /* LCD_C LCD frequency divider: /12 */ +#define LCDDIV__13 (0x6000) /* LCD_C LCD frequency divider: /13 */ +#define LCDDIV__14 (0x6800) /* LCD_C LCD frequency divider: /14 */ +#define LCDDIV__15 (0x7000) /* LCD_C LCD frequency divider: /15 */ +#define LCDDIV__16 (0x7800) /* LCD_C LCD frequency divider: /16 */ +#define LCDDIV__17 (0x8000) /* LCD_C LCD frequency divider: /17 */ +#define LCDDIV__18 (0x8800) /* LCD_C LCD frequency divider: /18 */ +#define LCDDIV__19 (0x9000) /* LCD_C LCD frequency divider: /19 */ +#define LCDDIV__20 (0x9800) /* LCD_C LCD frequency divider: /20 */ +#define LCDDIV__21 (0xA000) /* LCD_C LCD frequency divider: /21 */ +#define LCDDIV__22 (0xA800) /* LCD_C LCD frequency divider: /22 */ +#define LCDDIV__23 (0xB000) /* LCD_C LCD frequency divider: /23 */ +#define LCDDIV__24 (0xB800) /* LCD_C LCD frequency divider: /24 */ +#define LCDDIV__25 (0xC000) /* LCD_C LCD frequency divider: /25 */ +#define LCDDIV__26 (0xC800) /* LCD_C LCD frequency divider: /26 */ +#define LCDDIV__27 (0xD000) /* LCD_C LCD frequency divider: /27 */ +#define LCDDIV__28 (0xD800) /* LCD_C LCD frequency divider: /28 */ +#define LCDDIV__29 (0xE000) /* LCD_C LCD frequency divider: /29 */ +#define LCDDIV__30 (0xE800) /* LCD_C LCD frequency divider: /30 */ +#define LCDDIV__31 (0xF000) /* LCD_C LCD frequency divider: /31 */ +#define LCDDIV__32 (0xF800) /* LCD_C LCD frequency divider: /32 */ + +/* Display modes coded with Bits 2-4 */ +#define LCDSTATIC (LCDSON) +#define LCD2MUX (LCDMX0+LCDSON) +#define LCD3MUX (LCDMX1+LCDSON) +#define LCD4MUX (LCDMX1+LCDMX0+LCDSON) +#define LCD5MUX (LCDMX2+LCDSON) +#define LCD6MUX (LCDMX2+LCDMX0+LCDSON) +#define LCD7MUX (LCDMX2+LCDMX1+LCDSON) +#define LCD8MUX (LCDMX2+LCDMX1+LCDMX0+LCDSON) + +// LCDCCTL1 +#define LCDFRMIFG (0x0001) /* LCD_C LCD frame interrupt flag */ +#define LCDBLKOFFIFG (0x0002) /* LCD_C LCD blinking off interrupt flag, */ +#define LCDBLKONIFG (0x0004) /* LCD_C LCD blinking on interrupt flag, */ +#define LCDNOCAPIFG (0x0008) /* LCD_C No cpacitance connected interrupt flag */ +#define LCDFRMIE (0x0100) /* LCD_C LCD frame interrupt enable */ +#define LCDBLKOFFIE (0x0200) /* LCD_C LCD blinking off interrupt flag, */ +#define LCDBLKONIE (0x0400) /* LCD_C LCD blinking on interrupt flag, */ +#define LCDNOCAPIE (0x0800) /* LCD_C No cpacitance connected interrupt enable */ + +// LCDCCTL1 +#define LCDFRMIFG_L (0x0001) /* LCD_C LCD frame interrupt flag */ +#define LCDBLKOFFIFG_L (0x0002) /* LCD_C LCD blinking off interrupt flag, */ +#define LCDBLKONIFG_L (0x0004) /* LCD_C LCD blinking on interrupt flag, */ +#define LCDNOCAPIFG_L (0x0008) /* LCD_C No cpacitance connected interrupt flag */ + +// LCDCCTL1 +#define LCDFRMIE_H (0x0001) /* LCD_C LCD frame interrupt enable */ +#define LCDBLKOFFIE_H (0x0002) /* LCD_C LCD blinking off interrupt flag, */ +#define LCDBLKONIE_H (0x0004) /* LCD_C LCD blinking on interrupt flag, */ +#define LCDNOCAPIE_H (0x0008) /* LCD_C No cpacitance connected interrupt enable */ + +// LCDCBLKCTL +#define LCDBLKMOD0 (0x0001) /* LCD_C Blinking mode Bit: 0 */ +#define LCDBLKMOD1 (0x0002) /* LCD_C Blinking mode Bit: 1 */ +#define LCDBLKPRE0 (0x0004) /* LCD_C Clock pre-scaler for blinking frequency Bit: 0 */ +#define LCDBLKPRE1 (0x0008) /* LCD_C Clock pre-scaler for blinking frequency Bit: 1 */ +#define LCDBLKPRE2 (0x0010) /* LCD_C Clock pre-scaler for blinking frequency Bit: 2 */ +#define LCDBLKDIV0 (0x0020) /* LCD_C Clock divider for blinking frequency Bit: 0 */ +#define LCDBLKDIV1 (0x0040) /* LCD_C Clock divider for blinking frequency Bit: 1 */ +#define LCDBLKDIV2 (0x0080) /* LCD_C Clock divider for blinking frequency Bit: 2 */ + +// LCDCBLKCTL +#define LCDBLKMOD0_L (0x0001) /* LCD_C Blinking mode Bit: 0 */ +#define LCDBLKMOD1_L (0x0002) /* LCD_C Blinking mode Bit: 1 */ +#define LCDBLKPRE0_L (0x0004) /* LCD_C Clock pre-scaler for blinking frequency Bit: 0 */ +#define LCDBLKPRE1_L (0x0008) /* LCD_C Clock pre-scaler for blinking frequency Bit: 1 */ +#define LCDBLKPRE2_L (0x0010) /* LCD_C Clock pre-scaler for blinking frequency Bit: 2 */ +#define LCDBLKDIV0_L (0x0020) /* LCD_C Clock divider for blinking frequency Bit: 0 */ +#define LCDBLKDIV1_L (0x0040) /* LCD_C Clock divider for blinking frequency Bit: 1 */ +#define LCDBLKDIV2_L (0x0080) /* LCD_C Clock divider for blinking frequency Bit: 2 */ + +#define LCDBLKMOD_0 (0x0000) /* LCD_C Blinking mode: Off */ +#define LCDBLKMOD_1 (0x0001) /* LCD_C Blinking mode: Individual */ +#define LCDBLKMOD_2 (0x0002) /* LCD_C Blinking mode: All */ +#define LCDBLKMOD_3 (0x0003) /* LCD_C Blinking mode: Switching */ + +// LCDCMEMCTL +#define LCDDISP (0x0001) /* LCD_C LCD memory registers for display */ +#define LCDCLRM (0x0002) /* LCD_C Clear LCD memory */ +#define LCDCLRBM (0x0004) /* LCD_C Clear LCD blinking memory */ + +// LCDCMEMCTL +#define LCDDISP_L (0x0001) /* LCD_C LCD memory registers for display */ +#define LCDCLRM_L (0x0002) /* LCD_C Clear LCD memory */ +#define LCDCLRBM_L (0x0004) /* LCD_C Clear LCD blinking memory */ + +// LCDCVCTL +#define LCD2B (0x0001) /* Selects 1/2 bias. */ +#define VLCDREF0 (0x0002) /* Selects reference voltage for regulated charge pump: 0 */ +#define VLCDREF1 (0x0004) /* Selects reference voltage for regulated charge pump: 1 */ +#define LCDCPEN (0x0008) /* LCD Voltage Charge Pump Enable. */ +#define VLCDEXT (0x0010) /* Select external source for VLCD. */ +#define LCDEXTBIAS (0x0020) /* V2 - V4 voltage select. */ +#define R03EXT (0x0040) /* Selects external connections for LCD mid voltages. */ +#define LCDREXT (0x0080) /* Selects external connection for lowest LCD voltage. */ +#define VLCD0 (0x0200) /* VLCD select: 0 */ +#define VLCD1 (0x0400) /* VLCD select: 1 */ +#define VLCD2 (0x0800) /* VLCD select: 2 */ +#define VLCD3 (0x1000) /* VLCD select: 3 */ +#define VLCD4 (0x2000) /* VLCD select: 4 */ +#define VLCD5 (0x4000) /* VLCD select: 5 */ + +// LCDCVCTL +#define LCD2B_L (0x0001) /* Selects 1/2 bias. */ +#define VLCDREF0_L (0x0002) /* Selects reference voltage for regulated charge pump: 0 */ +#define VLCDREF1_L (0x0004) /* Selects reference voltage for regulated charge pump: 1 */ +#define LCDCPEN_L (0x0008) /* LCD Voltage Charge Pump Enable. */ +#define VLCDEXT_L (0x0010) /* Select external source for VLCD. */ +#define LCDEXTBIAS_L (0x0020) /* V2 - V4 voltage select. */ +#define R03EXT_L (0x0040) /* Selects external connections for LCD mid voltages. */ +#define LCDREXT_L (0x0080) /* Selects external connection for lowest LCD voltage. */ + +// LCDCVCTL +#define VLCD0_H (0x0002) /* VLCD select: 0 */ +#define VLCD1_H (0x0004) /* VLCD select: 1 */ +#define VLCD2_H (0x0008) /* VLCD select: 2 */ +#define VLCD3_H (0x0010) /* VLCD select: 3 */ +#define VLCD4_H (0x0020) /* VLCD select: 4 */ +#define VLCD5_H (0x0040) /* VLCD select: 5 */ + +/* Reference voltage source select for the regulated charge pump */ +#define VLCDREF_0 (0x0000) /* Internal */ +#define VLCDREF_1 (0x0002) /* External */ +#define VLCDREF_2 (0x0004) /* Reserved */ +#define VLCDREF_3 (0x0006) /* Reserved */ + +/* Charge pump voltage selections */ +#define VLCD_0 (0x0000) /* Charge pump disabled */ +#define VLCD_1 (0x0200) /* VLCD = 2.60V */ +#define VLCD_2 (0x0400) /* VLCD = 2.66V */ +#define VLCD_3 (0x0600) /* VLCD = 2.72V */ +#define VLCD_4 (0x0800) /* VLCD = 2.78V */ +#define VLCD_5 (0x0A00) /* VLCD = 2.84V */ +#define VLCD_6 (0x0C00) /* VLCD = 2.90V */ +#define VLCD_7 (0x0E00) /* VLCD = 2.96V */ +#define VLCD_8 (0x1000) /* VLCD = 3.02V */ +#define VLCD_9 (0x1200) /* VLCD = 3.08V */ +#define VLCD_10 (0x1400) /* VLCD = 3.14V */ +#define VLCD_11 (0x1600) /* VLCD = 3.20V */ +#define VLCD_12 (0x1800) /* VLCD = 3.26V */ +#define VLCD_13 (0x1A00) /* VLCD = 3.32V */ +#define VLCD_14 (0x1C00) /* VLCD = 3.38V */ +#define VLCD_15 (0x1E00) /* VLCD = 3.44V */ + +#define VLCD_DISABLED (0x0000) /* Charge pump disabled */ +#define VLCD_2_60 (0x0200) /* VLCD = 2.60V */ +#define VLCD_2_66 (0x0400) /* VLCD = 2.66V */ +#define VLCD_2_72 (0x0600) /* VLCD = 2.72V */ +#define VLCD_2_78 (0x0800) /* VLCD = 2.78V */ +#define VLCD_2_84 (0x0A00) /* VLCD = 2.84V */ +#define VLCD_2_90 (0x0C00) /* VLCD = 2.90V */ +#define VLCD_2_96 (0x0E00) /* VLCD = 2.96V */ +#define VLCD_3_02 (0x1000) /* VLCD = 3.02V */ +#define VLCD_3_08 (0x1200) /* VLCD = 3.08V */ +#define VLCD_3_14 (0x1400) /* VLCD = 3.14V */ +#define VLCD_3_20 (0x1600) /* VLCD = 3.20V */ +#define VLCD_3_26 (0x1800) /* VLCD = 3.26V */ +#define VLCD_3_32 (0x1A00) /* VLCD = 3.32V */ +#define VLCD_3_38 (0x1C00) /* VLCD = 3.38V */ +#define VLCD_3_44 (0x1E00) /* VLCD = 3.44V */ + +// LCDCPCTL0 +#define LCDS0 (0x0001) /* LCD Segment 0 enable. */ +#define LCDS1 (0x0002) /* LCD Segment 1 enable. */ +#define LCDS2 (0x0004) /* LCD Segment 2 enable. */ +#define LCDS3 (0x0008) /* LCD Segment 3 enable. */ +#define LCDS4 (0x0010) /* LCD Segment 4 enable. */ +#define LCDS5 (0x0020) /* LCD Segment 5 enable. */ +#define LCDS6 (0x0040) /* LCD Segment 6 enable. */ +#define LCDS7 (0x0080) /* LCD Segment 7 enable. */ +#define LCDS8 (0x0100) /* LCD Segment 8 enable. */ +#define LCDS9 (0x0200) /* LCD Segment 9 enable. */ +#define LCDS10 (0x0400) /* LCD Segment 10 enable. */ +#define LCDS11 (0x0800) /* LCD Segment 11 enable. */ +#define LCDS12 (0x1000) /* LCD Segment 12 enable. */ +#define LCDS13 (0x2000) /* LCD Segment 13 enable. */ +#define LCDS14 (0x4000) /* LCD Segment 14 enable. */ +#define LCDS15 (0x8000) /* LCD Segment 15 enable. */ + +// LCDCPCTL0 +#define LCDS0_L (0x0001) /* LCD Segment 0 enable. */ +#define LCDS1_L (0x0002) /* LCD Segment 1 enable. */ +#define LCDS2_L (0x0004) /* LCD Segment 2 enable. */ +#define LCDS3_L (0x0008) /* LCD Segment 3 enable. */ +#define LCDS4_L (0x0010) /* LCD Segment 4 enable. */ +#define LCDS5_L (0x0020) /* LCD Segment 5 enable. */ +#define LCDS6_L (0x0040) /* LCD Segment 6 enable. */ +#define LCDS7_L (0x0080) /* LCD Segment 7 enable. */ + +// LCDCPCTL0 +#define LCDS8_H (0x0001) /* LCD Segment 8 enable. */ +#define LCDS9_H (0x0002) /* LCD Segment 9 enable. */ +#define LCDS10_H (0x0004) /* LCD Segment 10 enable. */ +#define LCDS11_H (0x0008) /* LCD Segment 11 enable. */ +#define LCDS12_H (0x0010) /* LCD Segment 12 enable. */ +#define LCDS13_H (0x0020) /* LCD Segment 13 enable. */ +#define LCDS14_H (0x0040) /* LCD Segment 14 enable. */ +#define LCDS15_H (0x0080) /* LCD Segment 15 enable. */ + +// LCDCPCTL1 +#define LCDS16 (0x0001) /* LCD Segment 16 enable. */ +#define LCDS17 (0x0002) /* LCD Segment 17 enable. */ +#define LCDS18 (0x0004) /* LCD Segment 18 enable. */ +#define LCDS19 (0x0008) /* LCD Segment 19 enable. */ +#define LCDS20 (0x0010) /* LCD Segment 20 enable. */ +#define LCDS21 (0x0020) /* LCD Segment 21 enable. */ +#define LCDS22 (0x0040) /* LCD Segment 22 enable. */ +#define LCDS23 (0x0080) /* LCD Segment 23 enable. */ +#define LCDS24 (0x0100) /* LCD Segment 24 enable. */ +#define LCDS25 (0x0200) /* LCD Segment 25 enable. */ +#define LCDS26 (0x0400) /* LCD Segment 26 enable. */ +#define LCDS27 (0x0800) /* LCD Segment 27 enable. */ +#define LCDS28 (0x1000) /* LCD Segment 28 enable. */ +#define LCDS29 (0x2000) /* LCD Segment 29 enable. */ +#define LCDS30 (0x4000) /* LCD Segment 30 enable. */ +#define LCDS31 (0x8000) /* LCD Segment 31 enable. */ + +// LCDCPCTL1 +#define LCDS16_L (0x0001) /* LCD Segment 16 enable. */ +#define LCDS17_L (0x0002) /* LCD Segment 17 enable. */ +#define LCDS18_L (0x0004) /* LCD Segment 18 enable. */ +#define LCDS19_L (0x0008) /* LCD Segment 19 enable. */ +#define LCDS20_L (0x0010) /* LCD Segment 20 enable. */ +#define LCDS21_L (0x0020) /* LCD Segment 21 enable. */ +#define LCDS22_L (0x0040) /* LCD Segment 22 enable. */ +#define LCDS23_L (0x0080) /* LCD Segment 23 enable. */ + +// LCDCPCTL1 +#define LCDS24_H (0x0001) /* LCD Segment 24 enable. */ +#define LCDS25_H (0x0002) /* LCD Segment 25 enable. */ +#define LCDS26_H (0x0004) /* LCD Segment 26 enable. */ +#define LCDS27_H (0x0008) /* LCD Segment 27 enable. */ +#define LCDS28_H (0x0010) /* LCD Segment 28 enable. */ +#define LCDS29_H (0x0020) /* LCD Segment 29 enable. */ +#define LCDS30_H (0x0040) /* LCD Segment 30 enable. */ +#define LCDS31_H (0x0080) /* LCD Segment 31 enable. */ + +// LCDCPCTL2 +#define LCDS32 (0x0001) /* LCD Segment 32 enable. */ +#define LCDS33 (0x0002) /* LCD Segment 33 enable. */ +#define LCDS34 (0x0004) /* LCD Segment 34 enable. */ +#define LCDS35 (0x0008) /* LCD Segment 35 enable. */ +#define LCDS36 (0x0010) /* LCD Segment 36 enable. */ +#define LCDS37 (0x0020) /* LCD Segment 37 enable. */ +#define LCDS38 (0x0040) /* LCD Segment 38 enable. */ +#define LCDS39 (0x0080) /* LCD Segment 39 enable. */ +#define LCDS40 (0x0100) /* LCD Segment 40 enable. */ +#define LCDS41 (0x0200) /* LCD Segment 41 enable. */ +#define LCDS42 (0x0400) /* LCD Segment 42 enable. */ +#define LCDS43 (0x0800) /* LCD Segment 43 enable. */ +#define LCDS44 (0x1000) /* LCD Segment 44 enable. */ +#define LCDS45 (0x2000) /* LCD Segment 45 enable. */ +#define LCDS46 (0x4000) /* LCD Segment 46 enable. */ +#define LCDS47 (0x8000) /* LCD Segment 47 enable. */ + +// LCDCPCTL2 +#define LCDS32_L (0x0001) /* LCD Segment 32 enable. */ +#define LCDS33_L (0x0002) /* LCD Segment 33 enable. */ +#define LCDS34_L (0x0004) /* LCD Segment 34 enable. */ +#define LCDS35_L (0x0008) /* LCD Segment 35 enable. */ +#define LCDS36_L (0x0010) /* LCD Segment 36 enable. */ +#define LCDS37_L (0x0020) /* LCD Segment 37 enable. */ +#define LCDS38_L (0x0040) /* LCD Segment 38 enable. */ +#define LCDS39_L (0x0080) /* LCD Segment 39 enable. */ + +// LCDCPCTL2 +#define LCDS40_H (0x0001) /* LCD Segment 40 enable. */ +#define LCDS41_H (0x0002) /* LCD Segment 41 enable. */ +#define LCDS42_H (0x0004) /* LCD Segment 42 enable. */ +#define LCDS43_H (0x0008) /* LCD Segment 43 enable. */ +#define LCDS44_H (0x0010) /* LCD Segment 44 enable. */ +#define LCDS45_H (0x0020) /* LCD Segment 45 enable. */ +#define LCDS46_H (0x0040) /* LCD Segment 46 enable. */ +#define LCDS47_H (0x0080) /* LCD Segment 47 enable. */ + +// LCDCCPCTL +#define LCDCPDIS0 (0x0001) /* LCD charge pump disable */ +#define LCDCPDIS1 (0x0002) /* LCD charge pump disable */ +#define LCDCPDIS2 (0x0004) /* LCD charge pump disable */ +#define LCDCPDIS3 (0x0008) /* LCD charge pump disable */ +#define LCDCPDIS4 (0x0010) /* LCD charge pump disable */ +#define LCDCPDIS5 (0x0020) /* LCD charge pump disable */ +#define LCDCPDIS6 (0x0040) /* LCD charge pump disable */ +#define LCDCPDIS7 (0x0080) /* LCD charge pump disable */ +#define LCDCPCLKSYNC (0x8000) /* LCD charge pump clock synchronization */ + +// LCDCCPCTL +#define LCDCPDIS0_L (0x0001) /* LCD charge pump disable */ +#define LCDCPDIS1_L (0x0002) /* LCD charge pump disable */ +#define LCDCPDIS2_L (0x0004) /* LCD charge pump disable */ +#define LCDCPDIS3_L (0x0008) /* LCD charge pump disable */ +#define LCDCPDIS4_L (0x0010) /* LCD charge pump disable */ +#define LCDCPDIS5_L (0x0020) /* LCD charge pump disable */ +#define LCDCPDIS6_L (0x0040) /* LCD charge pump disable */ +#define LCDCPDIS7_L (0x0080) /* LCD charge pump disable */ + +// LCDCCPCTL +#define LCDCPCLKSYNC_H (0x0080) /* LCD charge pump clock synchronization */ + +#define OFS_LCDM1 (0x0020) /* LCD Memory 1 */ +#define LCDMEM_ LCDM1 /* LCD Memory */ +#ifdef __ASM_HEADER__ +#define LCDMEM LCDM1 /* LCD Memory (for assembler) */ +#else +#define LCDMEM ((char*) &LCDM1) /* LCD Memory (for C) */ +#endif +#define OFS_LCDM2 (0x0021) /* LCD Memory 2 */ +#define OFS_LCDM3 (0x0022) /* LCD Memory 3 */ +#define OFS_LCDM4 (0x0023) /* LCD Memory 4 */ +#define OFS_LCDM5 (0x0024) /* LCD Memory 5 */ +#define OFS_LCDM6 (0x0025) /* LCD Memory 6 */ +#define OFS_LCDM7 (0x0026) /* LCD Memory 7 */ +#define OFS_LCDM8 (0x0027) /* LCD Memory 8 */ +#define OFS_LCDM9 (0x0028) /* LCD Memory 9 */ +#define OFS_LCDM10 (0x0029) /* LCD Memory 10 */ +#define OFS_LCDM11 (0x002A) /* LCD Memory 11 */ +#define OFS_LCDM12 (0x002B) /* LCD Memory 12 */ +#define OFS_LCDM13 (0x002C) /* LCD Memory 13 */ +#define OFS_LCDM14 (0x002D) /* LCD Memory 14 */ +#define OFS_LCDM15 (0x002E) /* LCD Memory 15 */ +#define OFS_LCDM16 (0x002F) /* LCD Memory 16 */ +#define OFS_LCDM17 (0x0030) /* LCD Memory 17 */ +#define OFS_LCDM18 (0x0031) /* LCD Memory 18 */ +#define OFS_LCDM19 (0x0032) /* LCD Memory 19 */ +#define OFS_LCDM20 (0x0033) /* LCD Memory 20 */ +#define OFS_LCDM21 (0x0034) /* LCD Memory 21 */ +#define OFS_LCDM22 (0x0035) /* LCD Memory 22 */ +#define OFS_LCDM23 (0x0036) /* LCD Memory 23 */ +#define OFS_LCDM24 (0x0037) /* LCD Memory 24 */ +#define OFS_LCDM25 (0x0038) /* LCD Memory 25 */ +#define OFS_LCDM26 (0x0039) /* LCD Memory 26 */ +#define OFS_LCDM27 (0x003A) /* LCD Memory 27 */ +#define OFS_LCDM28 (0x003B) /* LCD Memory 28 */ +#define OFS_LCDM29 (0x003C) /* LCD Memory 29 */ +#define OFS_LCDM30 (0x003D) /* LCD Memory 30 */ +#define OFS_LCDM31 (0x003E) /* LCD Memory 31 */ +#define OFS_LCDM32 (0x003F) /* LCD Memory 32 */ +#define OFS_LCDM33 (0x0040) /* LCD Memory 33 */ +#define OFS_LCDM34 (0x0041) /* LCD Memory 34 */ +#define OFS_LCDM35 (0x0042) /* LCD Memory 35 */ +#define OFS_LCDM36 (0x0043) /* LCD Memory 36 */ +#define OFS_LCDM37 (0x0044) /* LCD Memory 37 */ +#define OFS_LCDM38 (0x0045) /* LCD Memory 38 */ +#define OFS_LCDM39 (0x0046) /* LCD Memory 39 */ +#define OFS_LCDM40 (0x0047) /* LCD Memory 40 */ + +#define OFS_LCDBM1 (0x0040) /* LCD Blinking Memory 1 */ +#define LCDBMEM_ LCDBM1 /* LCD Blinking Memory */ +#ifdef __ASM_HEADER__ +#define LCDBMEM (LCDBM1) /* LCD Blinking Memory (for assembler) */ +#else +#define LCDBMEM ((char*) &LCDBM1) /* LCD Blinking Memory (for C) */ +#endif +#define OFS_LCDBM2 (0x0041) /* LCD Blinking Memory 2 */ +#define OFS_LCDBM3 (0x0042) /* LCD Blinking Memory 3 */ +#define OFS_LCDBM4 (0x0043) /* LCD Blinking Memory 4 */ +#define OFS_LCDBM5 (0x0044) /* LCD Blinking Memory 5 */ +#define OFS_LCDBM6 (0x0045) /* LCD Blinking Memory 6 */ +#define OFS_LCDBM7 (0x0046) /* LCD Blinking Memory 7 */ +#define OFS_LCDBM8 (0x0047) /* LCD Blinking Memory 8 */ +#define OFS_LCDBM9 (0x0048) /* LCD Blinking Memory 9 */ +#define OFS_LCDBM10 (0x0049) /* LCD Blinking Memory 10 */ +#define OFS_LCDBM11 (0x004A) /* LCD Blinking Memory 11 */ +#define OFS_LCDBM12 (0x004B) /* LCD Blinking Memory 12 */ +#define OFS_LCDBM13 (0x004C) /* LCD Blinking Memory 13 */ +#define OFS_LCDBM14 (0x004D) /* LCD Blinking Memory 14 */ +#define OFS_LCDBM15 (0x004E) /* LCD Blinking Memory 15 */ +#define OFS_LCDBM16 (0x004F) /* LCD Blinking Memory 16 */ +#define OFS_LCDBM17 (0x0050) /* LCD Blinking Memory 17 */ +#define OFS_LCDBM18 (0x0051) /* LCD Blinking Memory 18 */ +#define OFS_LCDBM19 (0x0052) /* LCD Blinking Memory 19 */ +#define OFS_LCDBM20 (0x0053) /* LCD Blinking Memory 20 */ + +/* LCDCIV Definitions */ +#define LCDCIV_NONE (0x0000) /* No Interrupt pending */ +#define LCDCIV_LCDNOCAPIFG (0x0002) /* No capacitor connected */ +#define LCDCIV_LCDCLKOFFIFG (0x0004) /* Blink, segments off */ +#define LCDCIV_LCDCLKONIFG (0x0006) /* Blink, segments on */ +#define LCDCIV_LCDFRMIFG (0x0008) /* Frame interrupt */ + +#endif +/************************************************************ +* HARDWARE MULTIPLIER 32Bit +************************************************************/ +#ifdef __MSP430_HAS_MPY32__ /* Definition to show that Module is available */ + +#define OFS_MPY (0x0000) /* Multiply Unsigned/Operand 1 */ +#define OFS_MPY_L OFS_MPY +#define OFS_MPY_H OFS_MPY+1 +#define OFS_MPYS (0x0002) /* Multiply Signed/Operand 1 */ +#define OFS_MPYS_L OFS_MPYS +#define OFS_MPYS_H OFS_MPYS+1 +#define OFS_MAC (0x0004) /* Multiply Unsigned and Accumulate/Operand 1 */ +#define OFS_MAC_L OFS_MAC +#define OFS_MAC_H OFS_MAC+1 +#define OFS_MACS (0x0006) /* Multiply Signed and Accumulate/Operand 1 */ +#define OFS_MACS_L OFS_MACS +#define OFS_MACS_H OFS_MACS+1 +#define OFS_OP2 (0x0008) /* Operand 2 */ +#define OFS_OP2_L OFS_OP2 +#define OFS_OP2_H OFS_OP2+1 +#define OFS_RESLO (0x000A) /* Result Low Word */ +#define OFS_RESLO_L OFS_RESLO +#define OFS_RESLO_H OFS_RESLO+1 +#define OFS_RESHI (0x000C) /* Result High Word */ +#define OFS_RESHI_L OFS_RESHI +#define OFS_RESHI_H OFS_RESHI+1 +#define OFS_SUMEXT (0x000E) /* Sum Extend */ +#define OFS_SUMEXT_L OFS_SUMEXT +#define OFS_SUMEXT_H OFS_SUMEXT+1 +#define OFS_MPY32CTL0 (0x002C) +#define OFS_MPY32CTL0_L OFS_MPY32CTL0 +#define OFS_MPY32CTL0_H OFS_MPY32CTL0+1 + +#define OFS_MPY32L (0x0010) /* 32-bit operand 1 - multiply - low word */ +#define OFS_MPY32L_L OFS_MPY32L +#define OFS_MPY32L_H OFS_MPY32L+1 +#define OFS_MPY32H (0x0012) /* 32-bit operand 1 - multiply - high word */ +#define OFS_MPY32H_L OFS_MPY32H +#define OFS_MPY32H_H OFS_MPY32H+1 +#define OFS_MPYS32L (0x0014) /* 32-bit operand 1 - signed multiply - low word */ +#define OFS_MPYS32L_L OFS_MPYS32L +#define OFS_MPYS32L_H OFS_MPYS32L+1 +#define OFS_MPYS32H (0x0016) /* 32-bit operand 1 - signed multiply - high word */ +#define OFS_MPYS32H_L OFS_MPYS32H +#define OFS_MPYS32H_H OFS_MPYS32H+1 +#define OFS_MAC32L (0x0018) /* 32-bit operand 1 - multiply accumulate - low word */ +#define OFS_MAC32L_L OFS_MAC32L +#define OFS_MAC32L_H OFS_MAC32L+1 +#define OFS_MAC32H (0x001A) /* 32-bit operand 1 - multiply accumulate - high word */ +#define OFS_MAC32H_L OFS_MAC32H +#define OFS_MAC32H_H OFS_MAC32H+1 +#define OFS_MACS32L (0x001C) /* 32-bit operand 1 - signed multiply accumulate - low word */ +#define OFS_MACS32L_L OFS_MACS32L +#define OFS_MACS32L_H OFS_MACS32L+1 +#define OFS_MACS32H (0x001E) /* 32-bit operand 1 - signed multiply accumulate - high word */ +#define OFS_MACS32H_L OFS_MACS32H +#define OFS_MACS32H_H OFS_MACS32H+1 +#define OFS_OP2L (0x0020) /* 32-bit operand 2 - low word */ +#define OFS_OP2L_L OFS_OP2L +#define OFS_OP2L_H OFS_OP2L+1 +#define OFS_OP2H (0x0022) /* 32-bit operand 2 - high word */ +#define OFS_OP2H_L OFS_OP2H +#define OFS_OP2H_H OFS_OP2H+1 +#define OFS_RES0 (0x0024) /* 32x32-bit result 0 - least significant word */ +#define OFS_RES0_L OFS_RES0 +#define OFS_RES0_H OFS_RES0+1 +#define OFS_RES1 (0x0026) /* 32x32-bit result 1 */ +#define OFS_RES1_L OFS_RES1 +#define OFS_RES1_H OFS_RES1+1 +#define OFS_RES2 (0x0028) /* 32x32-bit result 2 */ +#define OFS_RES2_L OFS_RES2 +#define OFS_RES2_H OFS_RES2+1 +#define OFS_RES3 (0x002A) /* 32x32-bit result 3 - most significant word */ +#define OFS_RES3_L OFS_RES3 +#define OFS_RES3_H OFS_RES3+1 +#define OFS_SUMEXT (0x000E) +#define OFS_SUMEXT_L OFS_SUMEXT +#define OFS_SUMEXT_H OFS_SUMEXT+1 +#define OFS_MPY32CTL0 (0x002C) /* MPY32 Control Register 0 */ +#define OFS_MPY32CTL0_L OFS_MPY32CTL0 +#define OFS_MPY32CTL0_H OFS_MPY32CTL0+1 + +#define MPY_B MPY_L /* Multiply Unsigned/Operand 1 (Byte Access) */ +#define MPYS_B MPYS_L /* Multiply Signed/Operand 1 (Byte Access) */ +#define MAC_B MAC_L /* Multiply Unsigned and Accumulate/Operand 1 (Byte Access) */ +#define MACS_B MACS_L /* Multiply Signed and Accumulate/Operand 1 (Byte Access) */ +#define OP2_B OP2_L /* Operand 2 (Byte Access) */ +#define MPY32L_B MPY32L_L /* 32-bit operand 1 - multiply - low word (Byte Access) */ +#define MPY32H_B MPY32H_L /* 32-bit operand 1 - multiply - high word (Byte Access) */ +#define MPYS32L_B MPYS32L_L /* 32-bit operand 1 - signed multiply - low word (Byte Access) */ +#define MPYS32H_B MPYS32H_L /* 32-bit operand 1 - signed multiply - high word (Byte Access) */ +#define MAC32L_B MAC32L_L /* 32-bit operand 1 - multiply accumulate - low word (Byte Access) */ +#define MAC32H_B MAC32H_L /* 32-bit operand 1 - multiply accumulate - high word (Byte Access) */ +#define MACS32L_B MACS32L_L /* 32-bit operand 1 - signed multiply accumulate - low word (Byte Access) */ +#define MACS32H_B MACS32H_L /* 32-bit operand 1 - signed multiply accumulate - high word (Byte Access) */ +#define OP2L_B OP2L_L /* 32-bit operand 2 - low word (Byte Access) */ +#define OP2H_B OP2H_L /* 32-bit operand 2 - high word (Byte Access) */ + +/* MPY32CTL0 Control Bits */ +#define MPYC (0x0001) /* Carry of the multiplier */ +//#define RESERVED (0x0002) /* Reserved */ +#define MPYFRAC (0x0004) /* Fractional mode */ +#define MPYSAT (0x0008) /* Saturation mode */ +#define MPYM0 (0x0010) /* Multiplier mode Bit:0 */ +#define MPYM1 (0x0020) /* Multiplier mode Bit:1 */ +#define OP1_32 (0x0040) /* Bit-width of operand 1 0:16Bit / 1:32Bit */ +#define OP2_32 (0x0080) /* Bit-width of operand 2 0:16Bit / 1:32Bit */ +#define MPYDLYWRTEN (0x0100) /* Delayed write enable */ +#define MPYDLY32 (0x0200) /* Delayed write mode */ + +/* MPY32CTL0 Control Bits */ +#define MPYC_L (0x0001) /* Carry of the multiplier */ +//#define RESERVED (0x0002) /* Reserved */ +#define MPYFRAC_L (0x0004) /* Fractional mode */ +#define MPYSAT_L (0x0008) /* Saturation mode */ +#define MPYM0_L (0x0010) /* Multiplier mode Bit:0 */ +#define MPYM1_L (0x0020) /* Multiplier mode Bit:1 */ +#define OP1_32_L (0x0040) /* Bit-width of operand 1 0:16Bit / 1:32Bit */ +#define OP2_32_L (0x0080) /* Bit-width of operand 2 0:16Bit / 1:32Bit */ + +/* MPY32CTL0 Control Bits */ +//#define RESERVED (0x0002) /* Reserved */ +#define MPYDLYWRTEN_H (0x0001) /* Delayed write enable */ +#define MPYDLY32_H (0x0002) /* Delayed write mode */ + +#define MPYM_0 (0x0000) /* Multiplier mode: MPY */ +#define MPYM_1 (0x0010) /* Multiplier mode: MPYS */ +#define MPYM_2 (0x0020) /* Multiplier mode: MAC */ +#define MPYM_3 (0x0030) /* Multiplier mode: MACS */ +#define MPYM__MPY (0x0000) /* Multiplier mode: MPY */ +#define MPYM__MPYS (0x0010) /* Multiplier mode: MPYS */ +#define MPYM__MAC (0x0020) /* Multiplier mode: MAC */ +#define MPYM__MACS (0x0030) /* Multiplier mode: MACS */ + +#endif +/************************************************************ +* DIGITAL I/O Port1/2 Pull up / Pull down Resistors +************************************************************/ +#ifdef __MSP430_HAS_PORT1_R__ /* Definition to show that Module is available */ +#ifdef __MSP430_HAS_PORT2_R__ /* Definition to show that Module is available */ +#ifdef __MSP430_HAS_PORTA_R__ /* Definition to show that Module is available */ + +#define OFS_PAIN (0x0000) /* Port A Input */ +#define OFS_PAIN_L OFS_PAIN +#define OFS_PAIN_H OFS_PAIN+1 +#define OFS_PAOUT (0x0002) /* Port A Output */ +#define OFS_PAOUT_L OFS_PAOUT +#define OFS_PAOUT_H OFS_PAOUT+1 +#define OFS_PADIR (0x0004) /* Port A Direction */ +#define OFS_PADIR_L OFS_PADIR +#define OFS_PADIR_H OFS_PADIR+1 +#define OFS_PAREN (0x0006) /* Port A Resistor Enable */ +#define OFS_PAREN_L OFS_PAREN +#define OFS_PAREN_H OFS_PAREN+1 +#define OFS_PADS (0x0008) /* Port A Drive Strenght */ +#define OFS_PADS_L OFS_PADS +#define OFS_PADS_H OFS_PADS+1 +#define OFS_PASEL (0x000A) /* Port A Selection */ +#define OFS_PASEL_L OFS_PASEL +#define OFS_PASEL_H OFS_PASEL+1 +#define OFS_PAIES (0x0018) /* Port A Interrupt Edge Select */ +#define OFS_PAIES_L OFS_PAIES +#define OFS_PAIES_H OFS_PAIES+1 +#define OFS_PAIE (0x001A) /* Port A Interrupt Enable */ +#define OFS_PAIE_L OFS_PAIE +#define OFS_PAIE_H OFS_PAIE+1 +#define OFS_PAIFG (0x001C) /* Port A Interrupt Flag */ +#define OFS_PAIFG_L OFS_PAIFG +#define OFS_PAIFG_H OFS_PAIFG+1 + + +#define OFS_P1IN (0x0000) +#define OFS_P1OUT (0x0002) +#define OFS_P1DIR (0x0004) +#define OFS_P1REN (0x0006) +#define OFS_P1DS (0x0008) +#define OFS_P1SEL (0x000A) +#define OFS_P1IV (0x000E) /* Port 1 Interrupt Vector Word */ +#define OFS_P1IES (0x0018) +#define OFS_P1IE (0x001A) +#define OFS_P1IFG (0x001C) +#define OFS_P2IN (0x0001) +#define OFS_P2OUT (0x0003) +#define OFS_P2DIR (0x0005) +#define OFS_P2REN (0x0007) +#define OFS_P2DS (0x0009) +#define OFS_P2SEL (0x000B) +#define OFS_P2IV (0x001E) /* Port 2 Interrupt Vector Word */ +#define OFS_P2IES (0x0019) +#define OFS_P2IE (0x001B) +#define OFS_P2IFG (0x001d) +#define P1IN (PAIN_L) /* Port 1 Input */ +#define P1OUT (PAOUT_L) /* Port 1 Output */ +#define P1DIR (PADIR_L) /* Port 1 Direction */ +#define P1REN (PAREN_L) /* Port 1 Resistor Enable */ +#define P1DS (PADS_L) /* Port 1 Drive Strenght */ +#define P1SEL (PASEL_L) /* Port 1 Selection */ +#define P1IES (PAIES_L) /* Port 1 Interrupt Edge Select */ +#define P1IE (PAIE_L) /* Port 1 Interrupt Enable */ +#define P1IFG (PAIFG_L) /* Port 1 Interrupt Flag */ + +//Definitions for P1IV +#define P1IV_NONE (0x0000) /* No Interrupt pending */ +#define P1IV_P1IFG0 (0x0002) /* P1IV P1IFG.0 */ +#define P1IV_P1IFG1 (0x0004) /* P1IV P1IFG.1 */ +#define P1IV_P1IFG2 (0x0006) /* P1IV P1IFG.2 */ +#define P1IV_P1IFG3 (0x0008) /* P1IV P1IFG.3 */ +#define P1IV_P1IFG4 (0x000A) /* P1IV P1IFG.4 */ +#define P1IV_P1IFG5 (0x000C) /* P1IV P1IFG.5 */ +#define P1IV_P1IFG6 (0x000E) /* P1IV P1IFG.6 */ +#define P1IV_P1IFG7 (0x0010) /* P1IV P1IFG.7 */ + +#define P2IN (PAIN_H) /* Port 2 Input */ +#define P2OUT (PAOUT_H) /* Port 2 Output */ +#define P2DIR (PADIR_H) /* Port 2 Direction */ +#define P2REN (PAREN_H) /* Port 2 Resistor Enable */ +#define P2DS (PADS_H) /* Port 2 Drive Strenght */ +#define P2SEL (PASEL_H) /* Port 2 Selection */ +#define P2IES (PAIES_H) /* Port 2 Interrupt Edge Select */ +#define P2IE (PAIE_H) /* Port 2 Interrupt Enable */ +#define P2IFG (PAIFG_H) /* Port 2 Interrupt Flag */ + +//Definitions for P2IV +#define P2IV_NONE (0x0000) /* No Interrupt pending */ +#define P2IV_P2IFG0 (0x0002) /* P2IV P2IFG.0 */ +#define P2IV_P2IFG1 (0x0004) /* P2IV P2IFG.1 */ +#define P2IV_P2IFG2 (0x0006) /* P2IV P2IFG.2 */ +#define P2IV_P2IFG3 (0x0008) /* P2IV P2IFG.3 */ +#define P2IV_P2IFG4 (0x000A) /* P2IV P2IFG.4 */ +#define P2IV_P2IFG5 (0x000C) /* P2IV P2IFG.5 */ +#define P2IV_P2IFG6 (0x000E) /* P2IV P2IFG.6 */ +#define P2IV_P2IFG7 (0x0010) /* P2IV P2IFG.7 */ + + +#endif +#endif +#endif +/************************************************************ +* DIGITAL I/O Port3/4 Pull up / Pull down Resistors +************************************************************/ +#ifdef __MSP430_HAS_PORT3_R__ /* Definition to show that Module is available */ +#ifdef __MSP430_HAS_PORT4_R__ /* Definition to show that Module is available */ +#ifdef __MSP430_HAS_PORTB_R__ /* Definition to show that Module is available */ + +#define OFS_PBIN (0x0000) /* Port B Input */ +#define OFS_PBIN_L OFS_PBIN +#define OFS_PBIN_H OFS_PBIN+1 +#define OFS_PBOUT (0x0002) /* Port B Output */ +#define OFS_PBOUT_L OFS_PBOUT +#define OFS_PBOUT_H OFS_PBOUT+1 +#define OFS_PBDIR (0x0004) /* Port B Direction */ +#define OFS_PBDIR_L OFS_PBDIR +#define OFS_PBDIR_H OFS_PBDIR+1 +#define OFS_PBREN (0x0006) /* Port B Resistor Enable */ +#define OFS_PBREN_L OFS_PBREN +#define OFS_PBREN_H OFS_PBREN+1 +#define OFS_PBDS (0x0008) /* Port B Drive Strenght */ +#define OFS_PBDS_L OFS_PBDS +#define OFS_PBDS_H OFS_PBDS+1 +#define OFS_PBSEL (0x000A) /* Port B Selection */ +#define OFS_PBSEL_L OFS_PBSEL +#define OFS_PBSEL_H OFS_PBSEL+1 +#define OFS_PBIES (0x0018) /* Port B Interrupt Edge Select */ +#define OFS_PBIES_L OFS_PBIES +#define OFS_PBIES_H OFS_PBIES+1 +#define OFS_PBIE (0x001A) /* Port B Interrupt Enable */ +#define OFS_PBIE_L OFS_PBIE +#define OFS_PBIE_H OFS_PBIE+1 +#define OFS_PBIFG (0x001C) /* Port B Interrupt Flag */ +#define OFS_PBIFG_L OFS_PBIFG +#define OFS_PBIFG_H OFS_PBIFG+1 + + +#define OFS_P3IN (0x0000) +#define OFS_P3OUT (0x0002) +#define OFS_P3DIR (0x0004) +#define OFS_P3REN (0x0006) +#define OFS_P3DS (0x0008) +#define OFS_P3SEL (0x000A) +#define OFS_P3IV (0x000E) /* Port 3 Interrupt Vector Word */ +#define OFS_P3IES (0x0018) +#define OFS_P3IE (0x001A) +#define OFS_P3IFG (0x001C) +#define OFS_P4IN (0x0001) +#define OFS_P4OUT (0x0003) +#define OFS_P4DIR (0x0005) +#define OFS_P4REN (0x0007) +#define OFS_P4DS (0x0009) +#define OFS_P4SEL (0x000B) +#define OFS_P4IV (0x001E) /* Port 4 Interrupt Vector Word */ +#define OFS_P4IES (0x0019) +#define OFS_P4IE (0x001B) +#define OFS_P4IFG (0x001d) +#define P3IN (PBIN_L) /* Port 3 Input */ +#define P3OUT (PBOUT_L) /* Port 3 Output */ +#define P3DIR (PBDIR_L) /* Port 3 Direction */ +#define P3REN (PBREN_L) /* Port 3 Resistor Enable */ +#define P3DS (PBDS_L) /* Port 3 Drive Strenght */ +#define P3SEL (PBSEL_L) /* Port 3 Selection */ +#define P3IES (PBIES_L) /* Port 3 Interrupt Edge Select */ +#define P3IE (PBIE_L) /* Port 3 Interrupt Enable */ +#define P3IFG (PBIFG_L) /* Port 3 Interrupt Flag */ + +//Definitions for P3IV +#define P3IV_NONE (0x0000) /* No Interrupt pending */ +#define P3IV_P3IFG0 (0x0002) /* P3IV P3IFG.0 */ +#define P3IV_P3IFG1 (0x0004) /* P3IV P3IFG.1 */ +#define P3IV_P3IFG2 (0x0006) /* P3IV P3IFG.2 */ +#define P3IV_P3IFG3 (0x0008) /* P3IV P3IFG.3 */ +#define P3IV_P3IFG4 (0x000A) /* P3IV P3IFG.4 */ +#define P3IV_P3IFG5 (0x000C) /* P3IV P3IFG.5 */ +#define P3IV_P3IFG6 (0x000E) /* P3IV P3IFG.6 */ +#define P3IV_P3IFG7 (0x0010) /* P3IV P3IFG.7 */ + +#define P4IN (PBIN_H) /* Port 4 Input */ +#define P4OUT (PBOUT_H) /* Port 4 Output */ +#define P4DIR (PBDIR_H) /* Port 4 Direction */ +#define P4REN (PBREN_H) /* Port 4 Resistor Enable */ +#define P4DS (PBDS_H) /* Port 4 Drive Strenght */ +#define P4SEL (PBSEL_H) /* Port 4 Selection */ +#define P4IES (PBIES_H) /* Port 4 Interrupt Edge Select */ +#define P4IE (PBIE_H) /* Port 4 Interrupt Enable */ +#define P4IFG (PBIFG_H) /* Port 4 Interrupt Flag */ + +//Definitions for P4IV +#define P4IV_NONE (0x0000) /* No Interrupt pending */ +#define P4IV_P4IFG0 (0x0002) /* P4IV P4IFG.0 */ +#define P4IV_P4IFG1 (0x0004) /* P4IV P4IFG.1 */ +#define P4IV_P4IFG2 (0x0006) /* P4IV P4IFG.2 */ +#define P4IV_P4IFG3 (0x0008) /* P4IV P4IFG.3 */ +#define P4IV_P4IFG4 (0x000A) /* P4IV P4IFG.4 */ +#define P4IV_P4IFG5 (0x000C) /* P4IV P4IFG.5 */ +#define P4IV_P4IFG6 (0x000E) /* P4IV P4IFG.6 */ +#define P4IV_P4IFG7 (0x0010) /* P4IV P4IFG.7 */ + + +#endif +#endif +#endif +/************************************************************ +* DIGITAL I/O Port5/6 Pull up / Pull down Resistors +************************************************************/ +#ifdef __MSP430_HAS_PORT5_R__ /* Definition to show that Module is available */ +#ifdef __MSP430_HAS_PORT6_R__ /* Definition to show that Module is available */ +#ifdef __MSP430_HAS_PORTC_R__ /* Definition to show that Module is available */ + +#define OFS_PCIN (0x0000) /* Port C Input */ +#define OFS_PCIN_L OFS_PCIN +#define OFS_PCIN_H OFS_PCIN+1 +#define OFS_PCOUT (0x0002) /* Port C Output */ +#define OFS_PCOUT_L OFS_PCOUT +#define OFS_PCOUT_H OFS_PCOUT+1 +#define OFS_PCDIR (0x0004) /* Port C Direction */ +#define OFS_PCDIR_L OFS_PCDIR +#define OFS_PCDIR_H OFS_PCDIR+1 +#define OFS_PCREN (0x0006) /* Port C Resistor Enable */ +#define OFS_PCREN_L OFS_PCREN +#define OFS_PCREN_H OFS_PCREN+1 +#define OFS_PCDS (0x0008) /* Port C Drive Strenght */ +#define OFS_PCDS_L OFS_PCDS +#define OFS_PCDS_H OFS_PCDS+1 +#define OFS_PCSEL (0x000A) /* Port C Selection */ +#define OFS_PCSEL_L OFS_PCSEL +#define OFS_PCSEL_H OFS_PCSEL+1 +#define OFS_PCIES (0x0018) /* Port C Interrupt Edge Select */ +#define OFS_PCIES_L OFS_PCIES +#define OFS_PCIES_H OFS_PCIES+1 +#define OFS_PCIE (0x001A) /* Port C Interrupt Enable */ +#define OFS_PCIE_L OFS_PCIE +#define OFS_PCIE_H OFS_PCIE+1 +#define OFS_PCIFG (0x001C) /* Port C Interrupt Flag */ +#define OFS_PCIFG_L OFS_PCIFG +#define OFS_PCIFG_H OFS_PCIFG+1 + + +#define OFS_P5IN (0x0000) +#define OFS_P5OUT (0x0002) +#define OFS_P5DIR (0x0004) +#define OFS_P5REN (0x0006) +#define OFS_P5DS (0x0008) +#define OFS_P5SEL (0x000A) +#define OFS_P5IV (0x000E) /* Port 5 Interrupt Vector Word */ +#define OFS_P5IES (0x0018) +#define OFS_P5IE (0x001A) +#define OFS_P5IFG (0x001C) +#define OFS_P6IN (0x0001) +#define OFS_P6OUT (0x0003) +#define OFS_P6DIR (0x0005) +#define OFS_P6REN (0x0007) +#define OFS_P6DS (0x0009) +#define OFS_P6SEL (0x000B) +#define OFS_P6IV (0x001E) /* Port 6 Interrupt Vector Word */ +#define OFS_P6IES (0x0019) +#define OFS_P6IE (0x001B) +#define OFS_P6IFG (0x001d) +#define P5IN (PCIN_L) /* Port 5 Input */ +#define P5OUT (PCOUT_L) /* Port 5 Output */ +#define P5DIR (PCDIR_L) /* Port 5 Direction */ +#define P5REN (PCREN_L) /* Port 5 Resistor Enable */ +#define P5DS (PCDS_L) /* Port 5 Drive Strenght */ +#define P5SEL (PCSEL_L) /* Port 5 Selection */ +#define P5IES (PCIES_L) /* Port 5 Interrupt Edge Select */ +#define P5IE (PCIE_L) /* Port 5 Interrupt Enable */ +#define P5IFG (PCIFG_L) /* Port 5 Interrupt Flag */ + +//Definitions for P5IV +#define P5IV_NONE (0x0000) /* No Interrupt pending */ +#define P5IV_P5IFG0 (0x0002) /* P5IV P5IFG.0 */ +#define P5IV_P5IFG1 (0x0004) /* P5IV P5IFG.1 */ +#define P5IV_P5IFG2 (0x0006) /* P5IV P5IFG.2 */ +#define P5IV_P5IFG3 (0x0008) /* P5IV P5IFG.3 */ +#define P5IV_P5IFG4 (0x000A) /* P5IV P5IFG.4 */ +#define P5IV_P5IFG5 (0x000C) /* P5IV P5IFG.5 */ +#define P5IV_P5IFG6 (0x000E) /* P5IV P5IFG.6 */ +#define P5IV_P5IFG7 (0x0010) /* P5IV P5IFG.7 */ + +#define P6IN (PCIN_H) /* Port 6 Input */ +#define P6OUT (PCOUT_H) /* Port 6 Output */ +#define P6DIR (PCDIR_H) /* Port 6 Direction */ +#define P6REN (PCREN_H) /* Port 6 Resistor Enable */ +#define P6DS (PCDS_H) /* Port 6 Drive Strenght */ +#define P6SEL (PCSEL_H) /* Port 6 Selection */ +#define P6IES (PCIES_H) /* Port 6 Interrupt Edge Select */ +#define P6IE (PCIE_H) /* Port 6 Interrupt Enable */ +#define P6IFG (PCIFG_H) /* Port 6 Interrupt Flag */ + +//Definitions for P6IV +#define P6IV_NONE (0x0000) /* No Interrupt pending */ +#define P6IV_P6IFG0 (0x0002) /* P6IV P6IFG.0 */ +#define P6IV_P6IFG1 (0x0004) /* P6IV P6IFG.1 */ +#define P6IV_P6IFG2 (0x0006) /* P6IV P6IFG.2 */ +#define P6IV_P6IFG3 (0x0008) /* P6IV P6IFG.3 */ +#define P6IV_P6IFG4 (0x000A) /* P6IV P6IFG.4 */ +#define P6IV_P6IFG5 (0x000C) /* P6IV P6IFG.5 */ +#define P6IV_P6IFG6 (0x000E) /* P6IV P6IFG.6 */ +#define P6IV_P6IFG7 (0x0010) /* P6IV P6IFG.7 */ + + +#endif +#endif +#endif +/************************************************************ +* DIGITAL I/O Port7/8 Pull up / Pull down Resistors +************************************************************/ +#ifdef __MSP430_HAS_PORT7_R__ /* Definition to show that Module is available */ +#ifdef __MSP430_HAS_PORT8_R__ /* Definition to show that Module is available */ +#ifdef __MSP430_HAS_PORTD_R__ /* Definition to show that Module is available */ + +#define OFS_PDIN (0x0000) /* Port D Input */ +#define OFS_PDIN_L OFS_PDIN +#define OFS_PDIN_H OFS_PDIN+1 +#define OFS_PDOUT (0x0002) /* Port D Output */ +#define OFS_PDOUT_L OFS_PDOUT +#define OFS_PDOUT_H OFS_PDOUT+1 +#define OFS_PDDIR (0x0004) /* Port D Direction */ +#define OFS_PDDIR_L OFS_PDDIR +#define OFS_PDDIR_H OFS_PDDIR+1 +#define OFS_PDREN (0x0006) /* Port D Resistor Enable */ +#define OFS_PDREN_L OFS_PDREN +#define OFS_PDREN_H OFS_PDREN+1 +#define OFS_PDDS (0x0008) /* Port D Drive Strenght */ +#define OFS_PDDS_L OFS_PDDS +#define OFS_PDDS_H OFS_PDDS+1 +#define OFS_PDSEL (0x000A) /* Port D Selection */ +#define OFS_PDSEL_L OFS_PDSEL +#define OFS_PDSEL_H OFS_PDSEL+1 +#define OFS_PDIES (0x0018) /* Port D Interrupt Edge Select */ +#define OFS_PDIES_L OFS_PDIES +#define OFS_PDIES_H OFS_PDIES+1 +#define OFS_PDIE (0x001A) /* Port D Interrupt Enable */ +#define OFS_PDIE_L OFS_PDIE +#define OFS_PDIE_H OFS_PDIE+1 +#define OFS_PDIFG (0x001C) /* Port D Interrupt Flag */ +#define OFS_PDIFG_L OFS_PDIFG +#define OFS_PDIFG_H OFS_PDIFG+1 + + +#define OFS_P7IN (0x0000) +#define OFS_P7OUT (0x0002) +#define OFS_P7DIR (0x0004) +#define OFS_P7REN (0x0006) +#define OFS_P7DS (0x0008) +#define OFS_P7SEL (0x000A) +#define OFS_P7IV (0x000E) /* Port 7 Interrupt Vector Word */ +#define OFS_P7IES (0x0018) +#define OFS_P7IE (0x001A) +#define OFS_P7IFG (0x001C) +#define OFS_P8IN (0x0001) +#define OFS_P8OUT (0x0003) +#define OFS_P8DIR (0x0005) +#define OFS_P8REN (0x0007) +#define OFS_P8DS (0x0009) +#define OFS_P8SEL (0x000B) +#define OFS_P8IV (0x001E) /* Port 8 Interrupt Vector Word */ +#define OFS_P8IES (0x0019) +#define OFS_P8IE (0x001B) +#define OFS_P8IFG (0x001d) +#define P7IN (PDIN_L) /* Port 7 Input */ +#define P7OUT (PDOUT_L) /* Port 7 Output */ +#define P7DIR (PDDIR_L) /* Port 7 Direction */ +#define P7REN (PDREN_L) /* Port 7 Resistor Enable */ +#define P7DS (PDDS_L) /* Port 7 Drive Strenght */ +#define P7SEL (PDSEL_L) /* Port 7 Selection */ +#define P7IES (PDIES_L) /* Port 7 Interrupt Edge Select */ +#define P7IE (PDIE_L) /* Port 7 Interrupt Enable */ +#define P7IFG (PDIFG_L) /* Port 7 Interrupt Flag */ + +//Definitions for P7IV +#define P7IV_NONE (0x0000) /* No Interrupt pending */ +#define P7IV_P7IFG0 (0x0002) /* P7IV P7IFG.0 */ +#define P7IV_P7IFG1 (0x0004) /* P7IV P7IFG.1 */ +#define P7IV_P7IFG2 (0x0006) /* P7IV P7IFG.2 */ +#define P7IV_P7IFG3 (0x0008) /* P7IV P7IFG.3 */ +#define P7IV_P7IFG4 (0x000A) /* P7IV P7IFG.4 */ +#define P7IV_P7IFG5 (0x000C) /* P7IV P7IFG.5 */ +#define P7IV_P7IFG6 (0x000E) /* P7IV P7IFG.6 */ +#define P7IV_P7IFG7 (0x0010) /* P7IV P7IFG.7 */ + +#define P8IN (PDIN_H) /* Port 8 Input */ +#define P8OUT (PDOUT_H) /* Port 8 Output */ +#define P8DIR (PDDIR_H) /* Port 8 Direction */ +#define P8REN (PDREN_H) /* Port 8 Resistor Enable */ +#define P8DS (PDDS_H) /* Port 8 Drive Strenght */ +#define P8SEL (PDSEL_H) /* Port 8 Selection */ +#define P8IES (PDIES_H) /* Port 8 Interrupt Edge Select */ +#define P8IE (PDIE_H) /* Port 8 Interrupt Enable */ +#define P8IFG (PDIFG_H) /* Port 8 Interrupt Flag */ + +//Definitions for P8IV +#define P8IV_NONE (0x0000) /* No Interrupt pending */ +#define P8IV_P8IFG0 (0x0002) /* P8IV P8IFG.0 */ +#define P8IV_P8IFG1 (0x0004) /* P8IV P8IFG.1 */ +#define P8IV_P8IFG2 (0x0006) /* P8IV P8IFG.2 */ +#define P8IV_P8IFG3 (0x0008) /* P8IV P8IFG.3 */ +#define P8IV_P8IFG4 (0x000A) /* P8IV P8IFG.4 */ +#define P8IV_P8IFG5 (0x000C) /* P8IV P8IFG.5 */ +#define P8IV_P8IFG6 (0x000E) /* P8IV P8IFG.6 */ +#define P8IV_P8IFG7 (0x0010) /* P8IV P8IFG.7 */ + + +#endif +#endif +#endif +/************************************************************ +* DIGITAL I/O Port9/10 Pull up / Pull down Resistors +************************************************************/ +#ifdef __MSP430_HAS_PORT9_R__ /* Definition to show that Module is available */ +#ifdef __MSP430_HAS_PORT10_R__ /* Definition to show that Module is available */ +#ifdef __MSP430_HAS_PORTE_R__ /* Definition to show that Module is available */ + +#define OFS_PEIN (0x0000) /* Port E Input */ +#define OFS_PEIN_L OFS_PEIN +#define OFS_PEIN_H OFS_PEIN+1 +#define OFS_PEOUT (0x0002) /* Port E Output */ +#define OFS_PEOUT_L OFS_PEOUT +#define OFS_PEOUT_H OFS_PEOUT+1 +#define OFS_PEDIR (0x0004) /* Port E Direction */ +#define OFS_PEDIR_L OFS_PEDIR +#define OFS_PEDIR_H OFS_PEDIR+1 +#define OFS_PEREN (0x0006) /* Port E Resistor Enable */ +#define OFS_PEREN_L OFS_PEREN +#define OFS_PEREN_H OFS_PEREN+1 +#define OFS_PEDS (0x0008) /* Port E Drive Strenght */ +#define OFS_PEDS_L OFS_PEDS +#define OFS_PEDS_H OFS_PEDS+1 +#define OFS_PESEL (0x000A) /* Port E Selection */ +#define OFS_PESEL_L OFS_PESEL +#define OFS_PESEL_H OFS_PESEL+1 +#define OFS_PEIES (0x0018) /* Port E Interrupt Edge Select */ +#define OFS_PEIES_L OFS_PEIES +#define OFS_PEIES_H OFS_PEIES+1 +#define OFS_PEIE (0x001A) /* Port E Interrupt Enable */ +#define OFS_PEIE_L OFS_PEIE +#define OFS_PEIE_H OFS_PEIE+1 +#define OFS_PEIFG (0x001C) /* Port E Interrupt Flag */ +#define OFS_PEIFG_L OFS_PEIFG +#define OFS_PEIFG_H OFS_PEIFG+1 + + +#define OFS_P9IN (0x0000) +#define OFS_P9OUT (0x0002) +#define OFS_P9DIR (0x0004) +#define OFS_P9REN (0x0006) +#define OFS_P9DS (0x0008) +#define OFS_P9SEL (0x000A) +#define OFS_P9IV (0x000E) /* Port 9 Interrupt Vector Word */ +#define OFS_P9IES (0x0018) +#define OFS_P9IE (0x001A) +#define OFS_P9IFG (0x001C) +#define OFS_P10IN (0x0001) +#define OFS_P10OUT (0x0003) +#define OFS_P10DIR (0x0005) +#define OFS_P10REN (0x0007) +#define OFS_P10DS (0x0009) +#define OFS_P10SEL (0x000B) +#define OFS_P10IV (0x001E) /* Port 10 Interrupt Vector Word */ +#define OFS_P10IES (0x0019) +#define OFS_P10IE (0x001B) +#define OFS_P10IFG (0x001d) +#define P9IN (PEIN_L) /* Port 9 Input */ +#define P9OUT (PEOUT_L) /* Port 9 Output */ +#define P9DIR (PEDIR_L) /* Port 9 Direction */ +#define P9REN (PEREN_L) /* Port 9 Resistor Enable */ +#define P9DS (PEDS_L) /* Port 9 Drive Strenght */ +#define P9SEL (PESEL_L) /* Port 9 Selection */ +#define P9IES (PEIES_L) /* Port 9 Interrupt Edge Select */ +#define P9IE (PEIE_L) /* Port 9 Interrupt Enable */ +#define P9IFG (PEIFG_L) /* Port 9 Interrupt Flag */ + +//Definitions for P9IV +#define P9IV_NONE (0x0000) /* No Interrupt pending */ +#define P9IV_P9IFG0 (0x0002) /* P9IV P9IFG.0 */ +#define P9IV_P9IFG1 (0x0004) /* P9IV P9IFG.1 */ +#define P9IV_P9IFG2 (0x0006) /* P9IV P9IFG.2 */ +#define P9IV_P9IFG3 (0x0008) /* P9IV P9IFG.3 */ +#define P9IV_P9IFG4 (0x000A) /* P9IV P9IFG.4 */ +#define P9IV_P9IFG5 (0x000C) /* P9IV P9IFG.5 */ +#define P9IV_P9IFG6 (0x000E) /* P9IV P9IFG.6 */ +#define P9IV_P9IFG7 (0x0010) /* P9IV P9IFG.7 */ + +#define P10IN (PEIN_H) /* Port 10 Input */ +#define P10OUT (PEOUT_H) /* Port 10 Output */ +#define P10DIR (PEDIR_H) /* Port 10 Direction */ +#define P10REN (PEREN_H) /* Port 10 Resistor Enable */ +#define P10DS (PEDS_H) /* Port 10 Drive Strenght */ +#define P10SEL (PESEL_H) /* Port 10 Selection */ +#define P10IES (PEIES_H) /* Port 10 Interrupt Edge Select */ +#define P10IE (PEIE_H) /* Port 10 Interrupt Enable */ +#define P10IFG (PEIFG_H) /* Port 10 Interrupt Flag */ + +//Definitions for P10IV +#define P10IV_NONE (0x0000) /* No Interrupt pending */ +#define P10IV_P10IFG0 (0x0002) /* P10IV P10IFG.0 */ +#define P10IV_P10IFG1 (0x0004) /* P10IV P10IFG.1 */ +#define P10IV_P10IFG2 (0x0006) /* P10IV P10IFG.2 */ +#define P10IV_P10IFG3 (0x0008) /* P10IV P10IFG.3 */ +#define P10IV_P10IFG4 (0x000A) /* P10IV P10IFG.4 */ +#define P10IV_P10IFG5 (0x000C) /* P10IV P10IFG.5 */ +#define P10IV_P10IFG6 (0x000E) /* P10IV P10IFG.6 */ +#define P10IV_P10IFG7 (0x0010) /* P10IV P10IFG.7 */ + + +#endif +#endif +#endif +/************************************************************ +* DIGITAL I/O Port11 Pull up / Pull down Resistors +************************************************************/ +#ifdef __MSP430_HAS_PORT11_R__ /* Definition to show that Module is available */ +#ifdef __MSP430_HAS_PORTF_R__ /* Definition to show that Module is available */ + +#define OFS_PFIN (0x0000) /* Port F Input */ +#define OFS_PFIN_L OFS_PFIN +#define OFS_PFIN_H OFS_PFIN+1 +#define OFS_PFOUT (0x0002) /* Port F Output */ +#define OFS_PFOUT_L OFS_PFOUT +#define OFS_PFOUT_H OFS_PFOUT+1 +#define OFS_PFDIR (0x0004) /* Port F Direction */ +#define OFS_PFDIR_L OFS_PFDIR +#define OFS_PFDIR_H OFS_PFDIR+1 +#define OFS_PFREN (0x0006) /* Port F Resistor Enable */ +#define OFS_PFREN_L OFS_PFREN +#define OFS_PFREN_H OFS_PFREN+1 +#define OFS_PFDS (0x0008) /* Port F Drive Strenght */ +#define OFS_PFDS_L OFS_PFDS +#define OFS_PFDS_H OFS_PFDS+1 +#define OFS_PFSEL (0x000A) /* Port F Selection */ +#define OFS_PFSEL_L OFS_PFSEL +#define OFS_PFSEL_H OFS_PFSEL+1 +#define OFS_PFIES (0x0018) /* Port F Interrupt Edge Select */ +#define OFS_PFIES_L OFS_PFIES +#define OFS_PFIES_H OFS_PFIES+1 +#define OFS_PFIE (0x001A) /* Port F Interrupt Enable */ +#define OFS_PFIE_L OFS_PFIE +#define OFS_PFIE_H OFS_PFIE+1 +#define OFS_PFIFG (0x001C) /* Port F Interrupt Flag */ +#define OFS_PFIFG_L OFS_PFIFG +#define OFS_PFIFG_H OFS_PFIFG+1 + + +#define OFS_P11IN (0x0000) +#define OFS_P11OUT (0x0002) +#define OFS_P11DIR (0x0004) +#define OFS_P11REN (0x0006) +#define OFS_P11DS (0x0008) +#define OFS_P11SEL (0x000A) +#define OFS_P11IV (0x000E) /* Port 11 Interrupt Vector Word */ +#define OFS_P11IES (0x0018) +#define OFS_P11IE (0x001A) +#define OFS_P11IFG (0x001C) +#define P11IN (PFIN_L) /* Port 11 Input */ +#define P11OUT (PFOUT_L) /* Port 11 Output */ +#define P11DIR (PFDIR_L) /* Port 11 Direction */ +#define P11REN (PFREN_L) /* Port 11 Resistor Enable */ +#define P11DS (PFDS_L) /* Port 11 Drive Strenght */ +#define P11SEL (PFSEL_L) /* Port 11 Selection */ + +#define P11IES (PFIES_L) /* Port 11 Interrupt Edge Select */ +#define P11IE (PFIE_L) /* Port 11 Interrupt Enable */ +#define P11IFG (PFIFG_L) /* Port 11 Interrupt Flag */ + +//Definitions for P11IV +#define P11IV_NONE (0x0000) /* No Interrupt pending */ +#define P11IV_P11IFG0 (0x0002) /* P11IV P11IFG.0 */ +#define P11IV_P11IFG1 (0x0004) /* P11IV P11IFG.1 */ +#define P11IV_P11IFG2 (0x0006) /* P11IV P11IFG.2 */ +#define P11IV_P11IFG3 (0x0008) /* P11IV P11IFG.3 */ +#define P11IV_P11IFG4 (0x000A) /* P11IV P11IFG.4 */ +#define P11IV_P11IFG5 (0x000C) /* P11IV P11IFG.5 */ +#define P11IV_P11IFG6 (0x000E) /* P11IV P11IFG.6 */ +#define P11IV_P11IFG7 (0x0010) /* P11IV P11IFG.7 */ + + +#endif +#endif +/************************************************************ +* DIGITAL I/O PortJ Pull up / Pull down Resistors +************************************************************/ +#ifdef __MSP430_HAS_PORTJ_R__ /* Definition to show that Module is available */ + +#define OFS_PJIN (0x0000) /* Port J Input */ +#define OFS_PJIN_L OFS_PJIN +#define OFS_PJIN_H OFS_PJIN+1 +#define OFS_PJOUT (0x0002) /* Port J Output */ +#define OFS_PJOUT_L OFS_PJOUT +#define OFS_PJOUT_H OFS_PJOUT+1 +#define OFS_PJDIR (0x0004) /* Port J Direction */ +#define OFS_PJDIR_L OFS_PJDIR +#define OFS_PJDIR_H OFS_PJDIR+1 +#define OFS_PJREN (0x0006) /* Port J Resistor Enable */ +#define OFS_PJREN_L OFS_PJREN +#define OFS_PJREN_H OFS_PJREN+1 +#define OFS_PJDS (0x0008) /* Port J Drive Strenght */ +#define OFS_PJDS_L OFS_PJDS +#define OFS_PJDS_H OFS_PJDS+1 +#define OFS_PJSEL (0x000A) /* Port J Selection */ +#define OFS_PJSEL_L OFS_PJSEL +#define OFS_PJSEL_H OFS_PJSEL+1 + +#endif +/************************************************************ +* PORT MAPPING CONTROLLER +************************************************************/ +#ifdef __MSP430_HAS_PORT_MAPPING__ /* Definition to show that Module is available */ + +#define OFS_PMAPKEYID (0x0000) /* Port Mapping Key register */ +#define OFS_PMAPKEYID_L OFS_PMAPKEYID +#define OFS_PMAPKEYID_H OFS_PMAPKEYID+1 +#define OFS_PMAPCTL (0x0002) /* Port Mapping control register */ +#define OFS_PMAPCTL_L OFS_PMAPCTL +#define OFS_PMAPCTL_H OFS_PMAPCTL+1 + +#define PMAPKEY (0x2D52) /* Port Mapping Key */ +#define PMAPPWD PMAPKEYID /* Legacy Definition: Mapping Key register */ +#define PMAPPW (0x2D52) /* Legacy Definition: Port Mapping Password */ + +/* PMAPCTL Control Bits */ +#define PMAPLOCKED (0x0001) /* Port Mapping Lock bit. Read only */ +#define PMAPRECFG (0x0002) /* Port Mapping re-configuration control bit */ + +/* PMAPCTL Control Bits */ +#define PMAPLOCKED_L (0x0001) /* Port Mapping Lock bit. Read only */ +#define PMAPRECFG_L (0x0002) /* Port Mapping re-configuration control bit */ + +#endif +/************************************************************ +* PORT 2 MAPPING CONTROLLER +************************************************************/ +#ifdef __MSP430_HAS_PORT2_MAPPING__ /* Definition to show that Module is available */ + +#define OFS_P2MAP01 (0x0000) /* Port P2.0/1 mapping register */ +#define OFS_P2MAP01_L OFS_P2MAP01 +#define OFS_P2MAP01_H OFS_P2MAP01+1 +#define OFS_P2MAP23 (0x0002) /* Port P2.2/3 mapping register */ +#define OFS_P2MAP23_L OFS_P2MAP23 +#define OFS_P2MAP23_H OFS_P2MAP23+1 +#define OFS_P2MAP45 (0x0004) /* Port P2.4/5 mapping register */ +#define OFS_P2MAP45_L OFS_P2MAP45 +#define OFS_P2MAP45_H OFS_P2MAP45+1 +#define OFS_P2MAP67 (0x0006) /* Port P2.6/7 mapping register */ +#define OFS_P2MAP67_L OFS_P2MAP67 +#define OFS_P2MAP67_H OFS_P2MAP67+1 +#define OFS_P2MAP0 (0x0000) +#define OFS_P2MAP1 (0x0001) +#define OFS_P2MAP2 (0x0002) +#define OFS_P2MAP3 (0x0003) +#define OFS_P2MAP4 (0x0004) +#define OFS_P2MAP5 (0x0005) +#define OFS_P2MAP6 (0x0006) +#define OFS_P2MAP7 (0x0007) + +#define P2MAP0 P2MAP01_L /* Port P2.0 mapping register */ +#define P2MAP1 P2MAP01_H /* Port P2.1 mapping register */ +#define P2MAP2 P2MAP23_L /* Port P2.2 mapping register */ +#define P2MAP3 P2MAP23_H /* Port P2.3 mapping register */ +#define P2MAP4 P2MAP45_L /* Port P2.4 mapping register */ +#define P2MAP5 P2MAP45_H /* Port P2.5 mapping register */ +#define P2MAP6 P2MAP67_L /* Port P2.6 mapping register */ +#define P2MAP7 P2MAP67_H /* Port P2.7 mapping register */ + +#endif +/************************************************************ +* PMM - Power Management System +************************************************************/ +#ifdef __MSP430_HAS_PMM__ /* Definition to show that Module is available */ + +#define OFS_PMMCTL0 (0x0000) /* PMM Control 0 */ +#define OFS_PMMCTL0_L OFS_PMMCTL0 +#define OFS_PMMCTL0_H OFS_PMMCTL0+1 +#define OFS_PMMCTL1 (0x0002) /* PMM Control 1 */ +#define OFS_PMMCTL1_L OFS_PMMCTL1 +#define OFS_PMMCTL1_H OFS_PMMCTL1+1 +#define OFS_SVSMHCTL (0x0004) /* SVS and SVM high side control register */ +#define OFS_SVSMHCTL_L OFS_SVSMHCTL +#define OFS_SVSMHCTL_H OFS_SVSMHCTL+1 +#define OFS_SVSMLCTL (0x0006) /* SVS and SVM low side control register */ +#define OFS_SVSMLCTL_L OFS_SVSMLCTL +#define OFS_SVSMLCTL_H OFS_SVSMLCTL+1 +#define OFS_SVSMIO (0x0008) /* SVSIN and SVSOUT control register */ +#define OFS_SVSMIO_L OFS_SVSMIO +#define OFS_SVSMIO_H OFS_SVSMIO+1 +#define OFS_PMMIFG (0x000C) /* PMM Interrupt Flag */ +#define OFS_PMMIFG_L OFS_PMMIFG +#define OFS_PMMIFG_H OFS_PMMIFG+1 +#define OFS_PMMRIE (0x000E) /* PMM and RESET Interrupt Enable */ +#define OFS_PMMRIE_L OFS_PMMRIE +#define OFS_PMMRIE_H OFS_PMMRIE+1 + +#define PMMPW (0xA500) /* PMM Register Write Password */ +#define PMMPW_H (0xA5) /* PMM Register Write Password for high word access */ + +/* PMMCTL0 Control Bits */ +#define PMMCOREV0 (0x0001) /* PMM Core Voltage Bit: 0 */ +#define PMMCOREV1 (0x0002) /* PMM Core Voltage Bit: 1 */ +#define PMMSWBOR (0x0004) /* PMM Software BOR */ +#define PMMSWPOR (0x0008) /* PMM Software POR */ +#define PMMREGOFF (0x0010) /* PMM Turn Regulator off */ +#define PMMHPMRE (0x0080) /* PMM Global High Power Module Request Enable */ + +/* PMMCTL0 Control Bits */ +#define PMMCOREV0_L (0x0001) /* PMM Core Voltage Bit: 0 */ +#define PMMCOREV1_L (0x0002) /* PMM Core Voltage Bit: 1 */ +#define PMMSWBOR_L (0x0004) /* PMM Software BOR */ +#define PMMSWPOR_L (0x0008) /* PMM Software POR */ +#define PMMREGOFF_L (0x0010) /* PMM Turn Regulator off */ +#define PMMHPMRE_L (0x0080) /* PMM Global High Power Module Request Enable */ + +#define PMMCOREV_0 (0x0000) /* PMM Core Voltage 0 (1.35V) */ +#define PMMCOREV_1 (0x0001) /* PMM Core Voltage 1 (1.55V) */ +#define PMMCOREV_2 (0x0002) /* PMM Core Voltage 2 (1.75V) */ +#define PMMCOREV_3 (0x0003) /* PMM Core Voltage 3 (1.85V) */ + +/* PMMCTL1 Control Bits */ +#define PMMREFMD (0x0001) /* PMM Reference Mode */ +#define PMMCMD0 (0x0010) /* PMM Voltage Regulator Current Mode Bit: 0 */ +#define PMMCMD1 (0x0020) /* PMM Voltage Regulator Current Mode Bit: 1 */ + +/* PMMCTL1 Control Bits */ +#define PMMREFMD_L (0x0001) /* PMM Reference Mode */ +#define PMMCMD0_L (0x0010) /* PMM Voltage Regulator Current Mode Bit: 0 */ +#define PMMCMD1_L (0x0020) /* PMM Voltage Regulator Current Mode Bit: 1 */ + +/* SVSMHCTL Control Bits */ +#define SVSMHRRL0 (0x0001) /* SVS and SVM high side Reset Release Voltage Level Bit: 0 */ +#define SVSMHRRL1 (0x0002) /* SVS and SVM high side Reset Release Voltage Level Bit: 1 */ +#define SVSMHRRL2 (0x0004) /* SVS and SVM high side Reset Release Voltage Level Bit: 2 */ +#define SVSMHDLYST (0x0008) /* SVS and SVM high side delay status */ +#define SVSHMD (0x0010) /* SVS high side mode */ +#define SVSMHEVM (0x0040) /* SVS and SVM high side event mask */ +#define SVSMHACE (0x0080) /* SVS and SVM high side auto control enable */ +#define SVSHRVL0 (0x0100) /* SVS high side reset voltage level Bit: 0 */ +#define SVSHRVL1 (0x0200) /* SVS high side reset voltage level Bit: 1 */ +#define SVSHE (0x0400) /* SVS high side enable */ +#define SVSHFP (0x0800) /* SVS high side full performace mode */ +#define SVMHOVPE (0x1000) /* SVM high side over-voltage enable */ +#define SVMHE (0x4000) /* SVM high side enable */ +#define SVMHFP (0x8000) /* SVM high side full performace mode */ + +/* SVSMHCTL Control Bits */ +#define SVSMHRRL0_L (0x0001) /* SVS and SVM high side Reset Release Voltage Level Bit: 0 */ +#define SVSMHRRL1_L (0x0002) /* SVS and SVM high side Reset Release Voltage Level Bit: 1 */ +#define SVSMHRRL2_L (0x0004) /* SVS and SVM high side Reset Release Voltage Level Bit: 2 */ +#define SVSMHDLYST_L (0x0008) /* SVS and SVM high side delay status */ +#define SVSHMD_L (0x0010) /* SVS high side mode */ +#define SVSMHEVM_L (0x0040) /* SVS and SVM high side event mask */ +#define SVSMHACE_L (0x0080) /* SVS and SVM high side auto control enable */ + +/* SVSMHCTL Control Bits */ +#define SVSHRVL0_H (0x0001) /* SVS high side reset voltage level Bit: 0 */ +#define SVSHRVL1_H (0x0002) /* SVS high side reset voltage level Bit: 1 */ +#define SVSHE_H (0x0004) /* SVS high side enable */ +#define SVSHFP_H (0x0008) /* SVS high side full performace mode */ +#define SVMHOVPE_H (0x0010) /* SVM high side over-voltage enable */ +#define SVMHE_H (0x0040) /* SVM high side enable */ +#define SVMHFP_H (0x0080) /* SVM high side full performace mode */ + +#define SVSMHRRL_0 (0x0000) /* SVS and SVM high side Reset Release Voltage Level 0 */ +#define SVSMHRRL_1 (0x0001) /* SVS and SVM high side Reset Release Voltage Level 1 */ +#define SVSMHRRL_2 (0x0002) /* SVS and SVM high side Reset Release Voltage Level 2 */ +#define SVSMHRRL_3 (0x0003) /* SVS and SVM high side Reset Release Voltage Level 3 */ +#define SVSMHRRL_4 (0x0004) /* SVS and SVM high side Reset Release Voltage Level 4 */ +#define SVSMHRRL_5 (0x0005) /* SVS and SVM high side Reset Release Voltage Level 5 */ +#define SVSMHRRL_6 (0x0006) /* SVS and SVM high side Reset Release Voltage Level 6 */ +#define SVSMHRRL_7 (0x0007) /* SVS and SVM high side Reset Release Voltage Level 7 */ + +#define SVSHRVL_0 (0x0000) /* SVS high side Reset Release Voltage Level 0 */ +#define SVSHRVL_1 (0x0100) /* SVS high side Reset Release Voltage Level 1 */ +#define SVSHRVL_2 (0x0200) /* SVS high side Reset Release Voltage Level 2 */ +#define SVSHRVL_3 (0x0300) /* SVS high side Reset Release Voltage Level 3 */ + +/* SVSMLCTL Control Bits */ +#define SVSMLRRL0 (0x0001) /* SVS and SVM low side Reset Release Voltage Level Bit: 0 */ +#define SVSMLRRL1 (0x0002) /* SVS and SVM low side Reset Release Voltage Level Bit: 1 */ +#define SVSMLRRL2 (0x0004) /* SVS and SVM low side Reset Release Voltage Level Bit: 2 */ +#define SVSMLDLYST (0x0008) /* SVS and SVM low side delay status */ +#define SVSLMD (0x0010) /* SVS low side mode */ +#define SVSMLEVM (0x0040) /* SVS and SVM low side event mask */ +#define SVSMLACE (0x0080) /* SVS and SVM low side auto control enable */ +#define SVSLRVL0 (0x0100) /* SVS low side reset voltage level Bit: 0 */ +#define SVSLRVL1 (0x0200) /* SVS low side reset voltage level Bit: 1 */ +#define SVSLE (0x0400) /* SVS low side enable */ +#define SVSLFP (0x0800) /* SVS low side full performace mode */ +#define SVMLOVPE (0x1000) /* SVM low side over-voltage enable */ +#define SVMLE (0x4000) /* SVM low side enable */ +#define SVMLFP (0x8000) /* SVM low side full performace mode */ + +/* SVSMLCTL Control Bits */ +#define SVSMLRRL0_L (0x0001) /* SVS and SVM low side Reset Release Voltage Level Bit: 0 */ +#define SVSMLRRL1_L (0x0002) /* SVS and SVM low side Reset Release Voltage Level Bit: 1 */ +#define SVSMLRRL2_L (0x0004) /* SVS and SVM low side Reset Release Voltage Level Bit: 2 */ +#define SVSMLDLYST_L (0x0008) /* SVS and SVM low side delay status */ +#define SVSLMD_L (0x0010) /* SVS low side mode */ +#define SVSMLEVM_L (0x0040) /* SVS and SVM low side event mask */ +#define SVSMLACE_L (0x0080) /* SVS and SVM low side auto control enable */ + +/* SVSMLCTL Control Bits */ +#define SVSLRVL0_H (0x0001) /* SVS low side reset voltage level Bit: 0 */ +#define SVSLRVL1_H (0x0002) /* SVS low side reset voltage level Bit: 1 */ +#define SVSLE_H (0x0004) /* SVS low side enable */ +#define SVSLFP_H (0x0008) /* SVS low side full performace mode */ +#define SVMLOVPE_H (0x0010) /* SVM low side over-voltage enable */ +#define SVMLE_H (0x0040) /* SVM low side enable */ +#define SVMLFP_H (0x0080) /* SVM low side full performace mode */ + +#define SVSMLRRL_0 (0x0000) /* SVS and SVM low side Reset Release Voltage Level 0 */ +#define SVSMLRRL_1 (0x0001) /* SVS and SVM low side Reset Release Voltage Level 1 */ +#define SVSMLRRL_2 (0x0002) /* SVS and SVM low side Reset Release Voltage Level 2 */ +#define SVSMLRRL_3 (0x0003) /* SVS and SVM low side Reset Release Voltage Level 3 */ +#define SVSMLRRL_4 (0x0004) /* SVS and SVM low side Reset Release Voltage Level 4 */ +#define SVSMLRRL_5 (0x0005) /* SVS and SVM low side Reset Release Voltage Level 5 */ +#define SVSMLRRL_6 (0x0006) /* SVS and SVM low side Reset Release Voltage Level 6 */ +#define SVSMLRRL_7 (0x0007) /* SVS and SVM low side Reset Release Voltage Level 7 */ + +#define SVSLRVL_0 (0x0000) /* SVS low side Reset Release Voltage Level 0 */ +#define SVSLRVL_1 (0x0100) /* SVS low side Reset Release Voltage Level 1 */ +#define SVSLRVL_2 (0x0200) /* SVS low side Reset Release Voltage Level 2 */ +#define SVSLRVL_3 (0x0300) /* SVS low side Reset Release Voltage Level 3 */ + +/* SVSMIO Control Bits */ +#define SVMLOE (0x0008) /* SVM low side output enable */ +#define SVMLVLROE (0x0010) /* SVM low side voltage level reached output enable */ +#define SVMOUTPOL (0x0020) /* SVMOUT pin polarity */ +#define SVMHOE (0x0800) /* SVM high side output enable */ +#define SVMHVLROE (0x1000) /* SVM high side voltage level reached output enable */ + +/* SVSMIO Control Bits */ +#define SVMLOE_L (0x0008) /* SVM low side output enable */ +#define SVMLVLROE_L (0x0010) /* SVM low side voltage level reached output enable */ +#define SVMOUTPOL_L (0x0020) /* SVMOUT pin polarity */ + +/* SVSMIO Control Bits */ +#define SVMHOE_H (0x0008) /* SVM high side output enable */ +#define SVMHVLROE_H (0x0010) /* SVM high side voltage level reached output enable */ + +/* PMMIFG Control Bits */ +#define SVSMLDLYIFG (0x0001) /* SVS and SVM low side Delay expired interrupt flag */ +#define SVMLIFG (0x0002) /* SVM low side interrupt flag */ +#define SVMLVLRIFG (0x0004) /* SVM low side Voltage Level Reached interrupt flag */ +#define SVSMHDLYIFG (0x0010) /* SVS and SVM high side Delay expired interrupt flag */ +#define SVMHIFG (0x0020) /* SVM high side interrupt flag */ +#define SVMHVLRIFG (0x0040) /* SVM high side Voltage Level Reached interrupt flag */ +#define PMMBORIFG (0x0100) /* PMM Software BOR interrupt flag */ +#define PMMRSTIFG (0x0200) /* PMM RESET pin interrupt flag */ +#define PMMPORIFG (0x0400) /* PMM Software POR interrupt flag */ +#define SVSHIFG (0x1000) /* SVS low side interrupt flag */ +#define SVSLIFG (0x2000) /* SVS high side interrupt flag */ +#define PMMLPM5IFG (0x8000) /* LPM5 indication Flag */ + +/* PMMIFG Control Bits */ +#define SVSMLDLYIFG_L (0x0001) /* SVS and SVM low side Delay expired interrupt flag */ +#define SVMLIFG_L (0x0002) /* SVM low side interrupt flag */ +#define SVMLVLRIFG_L (0x0004) /* SVM low side Voltage Level Reached interrupt flag */ +#define SVSMHDLYIFG_L (0x0010) /* SVS and SVM high side Delay expired interrupt flag */ +#define SVMHIFG_L (0x0020) /* SVM high side interrupt flag */ +#define SVMHVLRIFG_L (0x0040) /* SVM high side Voltage Level Reached interrupt flag */ + +/* PMMIFG Control Bits */ +#define PMMBORIFG_H (0x0001) /* PMM Software BOR interrupt flag */ +#define PMMRSTIFG_H (0x0002) /* PMM RESET pin interrupt flag */ +#define PMMPORIFG_H (0x0004) /* PMM Software POR interrupt flag */ +#define SVSHIFG_H (0x0010) /* SVS low side interrupt flag */ +#define SVSLIFG_H (0x0020) /* SVS high side interrupt flag */ +#define PMMLPM5IFG_H (0x0080) /* LPM5 indication Flag */ + +#define PMMRSTLPM5IFG PMMLPM5IFG /* LPM5 indication Flag */ + +/* PMMIE and RESET Control Bits */ +#define SVSMLDLYIE (0x0001) /* SVS and SVM low side Delay expired interrupt enable */ +#define SVMLIE (0x0002) /* SVM low side interrupt enable */ +#define SVMLVLRIE (0x0004) /* SVM low side Voltage Level Reached interrupt enable */ +#define SVSMHDLYIE (0x0010) /* SVS and SVM high side Delay expired interrupt enable */ +#define SVMHIE (0x0020) /* SVM high side interrupt enable */ +#define SVMHVLRIE (0x0040) /* SVM high side Voltage Level Reached interrupt enable */ +#define SVSLPE (0x0100) /* SVS low side POR enable */ +#define SVMLVLRPE (0x0200) /* SVM low side Voltage Level reached POR enable */ +#define SVSHPE (0x1000) /* SVS high side POR enable */ +#define SVMHVLRPE (0x2000) /* SVM high side Voltage Level reached POR enable */ + +/* PMMIE and RESET Control Bits */ +#define SVSMLDLYIE_L (0x0001) /* SVS and SVM low side Delay expired interrupt enable */ +#define SVMLIE_L (0x0002) /* SVM low side interrupt enable */ +#define SVMLVLRIE_L (0x0004) /* SVM low side Voltage Level Reached interrupt enable */ +#define SVSMHDLYIE_L (0x0010) /* SVS and SVM high side Delay expired interrupt enable */ +#define SVMHIE_L (0x0020) /* SVM high side interrupt enable */ +#define SVMHVLRIE_L (0x0040) /* SVM high side Voltage Level Reached interrupt enable */ + +/* PMMIE and RESET Control Bits */ +#define SVSLPE_H (0x0001) /* SVS low side POR enable */ +#define SVMLVLRPE_H (0x0002) /* SVM low side Voltage Level reached POR enable */ +#define SVSHPE_H (0x0010) /* SVS high side POR enable */ +#define SVMHVLRPE_H (0x0020) /* SVM high side Voltage Level reached POR enable */ + +#endif +/************************************************************ +* Port U +************************************************************/ +#ifdef __MSP430_HAS_PU__ /* Definition to show that Module is available */ + +/* ========================================================================= */ +/* Port U and LDO Control Registers */ +/* ========================================================================= */ +#define OFS_LDOKEYPID (0x0000) /* LDO Controller peripheral ID and key register */ +#define OFS_LDOKEYPID_L OFS_LDOKEYPID +#define OFS_LDOKEYPID_H OFS_LDOKEYPID+1 +#define OFS_PUCTL (0x0004) /* PU Control register */ +#define OFS_PUCTL_L OFS_PUCTL +#define OFS_PUCTL_H OFS_PUCTL+1 +#define OFS_LDOPWRCTL (0x0008) /* LDO Power control register */ +#define OFS_LDOPWRCTL_L OFS_LDOPWRCTL +#define OFS_LDOPWRCTL_H OFS_LDOPWRCTL+1 + +#define LDOKEY (0x9628) /* LDO Control Register key */ +#define LDOKEYID LDOKEYPID /* Legacy Definiton */ + +/* PUCTL Control Bits */ +#define PUOUT0 (0x0001) /* PU - PU Output Signal Bit 0 */ +#define PUOUT1 (0x0002) /* PU - PU Output Signal Bit 1 */ +#define PUIN0 (0x0004) /* PU - PU0/DP Input Data */ +#define PUIN1 (0x0008) /* PU - PU1/DM Input Data */ +#define PUOPE (0x0020) /* PU - Port Output Enable */ +#define PUIPE (0x0100) /* PU - PHY Single Ended Input enable */ + +/* PUCTL Control Bits */ +#define PUOUT0_L (0x0001) /* PU - PU Output Signal Bit 0 */ +#define PUOUT1_L (0x0002) /* PU - PU Output Signal Bit 1 */ +#define PUIN0_L (0x0004) /* PU - PU0/DP Input Data */ +#define PUIN1_L (0x0008) /* PU - PU1/DM Input Data */ +#define PUOPE_L (0x0020) /* PU - Port Output Enable */ + +/* PUCTL Control Bits */ +#define PUIPE_H (0x0001) /* PU - PHY Single Ended Input enable */ + +#define PUDIR (0x0020) /* Legacy Definiton */ +#define PSEIEN (0x0100) /* Legacy Definiton */ + +/* LDOPWRCTL Control Bits */ +#define LDOOVLIFG (0x0001) /* PU - LDOO Overload Interrupt Flag */ +#define LDOONIFG (0x0002) /* PU - LDOI "Coming ON" Interrupt Flag */ +#define LDOOFFIFG (0x0004) /* PU - LDOI "Going OFF" Interrupt Flag */ +#define LDOBGVBV (0x0008) /* PU - LDO Bandgap and LDOI valid */ +#define OVLAOFF (0x0020) /* PU - LDO overload auto off enable */ +#define LDOOVLIE (0x0100) /* PU - Overload indication Interrupt Enable */ +#define LDOONIE (0x0200) /* PU - LDOI "Coming ON" Interrupt Enable */ +#define LDOOFFIE (0x0400) /* PU - LDOI "Going OFF" Interrupt Enable */ +#define LDOEN (0x0800) /* PU - LDO Enable (3.3V) */ + +/* LDOPWRCTL Control Bits */ +#define LDOOVLIFG_L (0x0001) /* PU - LDOO Overload Interrupt Flag */ +#define LDOONIFG_L (0x0002) /* PU - LDOI "Coming ON" Interrupt Flag */ +#define LDOOFFIFG_L (0x0004) /* PU - LDOI "Going OFF" Interrupt Flag */ +#define LDOBGVBV_L (0x0008) /* PU - LDO Bandgap and LDOI valid */ +#define OVLAOFF_L (0x0020) /* PU - LDO overload auto off enable */ + +/* LDOPWRCTL Control Bits */ +#define LDOOVLIE_H (0x0001) /* PU - Overload indication Interrupt Enable */ +#define LDOONIE_H (0x0002) /* PU - LDOI "Coming ON" Interrupt Enable */ +#define LDOOFFIE_H (0x0004) /* PU - LDOI "Going OFF" Interrupt Enable */ +#define LDOEN_H (0x0008) /* PU - LDO Enable (3.3V) */ +#define LDOOEN LDOEN /* Deprecated support for LDO Enable (3.3V) */ +#define LDOOEN_H LDOEN_H /* Deprecated support for LDO Enable (3.3V) */ + +#define VUOVLIFG (0x0001) /* PU - Legacy Definiton: LDOO Overload Interrupt Flag */ +#define VBONIFG (0x0002) /* PU - Legacy Definiton: LDOI "Coming ON" Interrupt Flag */ +#define VBOFFIFG (0x0004) /* PU - Legacy Definiton: LDOI "Going OFF" Interrupt Flag */ +#define VUOVLIE (0x0100) /* PU - Legacy Definiton: Overload indication Interrupt Enable */ +#define VBONIE (0x0200) /* PU - Legacy Definiton: LDOI "Coming ON" Interrupt Enable */ +#define VBOFFIE (0x0400) /* PU - Legacy Definiton: LDOI "Going OFF" Interrupt Enable */ + + +#endif +/************************************************************* +* RAM Control Module +*************************************************************/ +#ifdef __MSP430_HAS_RC__ /* Definition to show that Module is available */ + +#define OFS_RCCTL0 (0x0000) /* Ram Controller Control Register */ +#define OFS_RCCTL0_L OFS_RCCTL0 +#define OFS_RCCTL0_H OFS_RCCTL0+1 + +/* RCCTL0 Control Bits */ +#define RCRS0OFF (0x0001) /* RAM Controller RAM Sector 0 Off */ +#define RCRS1OFF (0x0002) /* RAM Controller RAM Sector 1 Off */ +#define RCRS2OFF (0x0004) /* RAM Controller RAM Sector 2 Off */ +#define RCRS3OFF (0x0008) /* RAM Controller RAM Sector 3 Off */ +#define RCRS4OFF (0x0010) /* RAM Controller RAM Sector 4 Off */ +#define RCRS5OFF (0x0020) /* RAM Controller RAM Sector 5 Off */ +#define RCRS6OFF (0x0040) /* RAM Controller RAM Sector 6 Off */ +#define RCRS7OFF (0x0080) /* RAM Controller RAM Sector 7 (USB) Off */ + +/* RCCTL0 Control Bits */ +#define RCRS0OFF_L (0x0001) /* RAM Controller RAM Sector 0 Off */ +#define RCRS1OFF_L (0x0002) /* RAM Controller RAM Sector 1 Off */ +#define RCRS2OFF_L (0x0004) /* RAM Controller RAM Sector 2 Off */ +#define RCRS3OFF_L (0x0008) /* RAM Controller RAM Sector 3 Off */ +#define RCRS4OFF_L (0x0010) /* RAM Controller RAM Sector 4 Off */ +#define RCRS5OFF_L (0x0020) /* RAM Controller RAM Sector 5 Off */ +#define RCRS6OFF_L (0x0040) /* RAM Controller RAM Sector 6 Off */ +#define RCRS7OFF_L (0x0080) /* RAM Controller RAM Sector 7 (USB) Off */ + +#define RCKEY (0x5A00) + +#endif +/************************************************************ +* Shared Reference +************************************************************/ +#ifdef __MSP430_HAS_REF__ /* Definition to show that Module is available */ + +#define OFS_REFCTL0 (0x0000) /* REF Shared Reference control register 0 */ +#define OFS_REFCTL0_L OFS_REFCTL0 +#define OFS_REFCTL0_H OFS_REFCTL0+1 + +/* REFCTL0 Control Bits */ +#define REFON (0x0001) /* REF Reference On */ +#define REFOUT (0x0002) /* REF Reference output Buffer On */ +//#define RESERVED (0x0004) /* Reserved */ +#define REFTCOFF (0x0008) /* REF Temp.Sensor off */ +#define REFVSEL0 (0x0010) /* REF Reference Voltage Level Select Bit:0 */ +#define REFVSEL1 (0x0020) /* REF Reference Voltage Level Select Bit:1 */ +//#define RESERVED (0x0040) /* Reserved */ +#define REFMSTR (0x0080) /* REF Master Control */ +#define REFGENACT (0x0100) /* REF Reference generator active */ +#define REFBGACT (0x0200) /* REF Reference bandgap active */ +#define REFGENBUSY (0x0400) /* REF Reference generator busy */ +#define BGMODE (0x0800) /* REF Bandgap mode */ +//#define RESERVED (0x1000) /* Reserved */ +//#define RESERVED (0x2000) /* Reserved */ +//#define RESERVED (0x4000) /* Reserved */ +//#define RESERVED (0x8000) /* Reserved */ + +/* REFCTL0 Control Bits */ +#define REFON_L (0x0001) /* REF Reference On */ +#define REFOUT_L (0x0002) /* REF Reference output Buffer On */ +//#define RESERVED (0x0004) /* Reserved */ +#define REFTCOFF_L (0x0008) /* REF Temp.Sensor off */ +#define REFVSEL0_L (0x0010) /* REF Reference Voltage Level Select Bit:0 */ +#define REFVSEL1_L (0x0020) /* REF Reference Voltage Level Select Bit:1 */ +//#define RESERVED (0x0040) /* Reserved */ +#define REFMSTR_L (0x0080) /* REF Master Control */ +//#define RESERVED (0x1000) /* Reserved */ +//#define RESERVED (0x2000) /* Reserved */ +//#define RESERVED (0x4000) /* Reserved */ +//#define RESERVED (0x8000) /* Reserved */ + +/* REFCTL0 Control Bits */ +//#define RESERVED (0x0004) /* Reserved */ +//#define RESERVED (0x0040) /* Reserved */ +#define REFGENACT_H (0x0001) /* REF Reference generator active */ +#define REFBGACT_H (0x0002) /* REF Reference bandgap active */ +#define REFGENBUSY_H (0x0004) /* REF Reference generator busy */ +#define BGMODE_H (0x0008) /* REF Bandgap mode */ +//#define RESERVED (0x1000) /* Reserved */ +//#define RESERVED (0x2000) /* Reserved */ +//#define RESERVED (0x4000) /* Reserved */ +//#define RESERVED (0x8000) /* Reserved */ + +#define REFVSEL_0 (0x0000) /* REF Reference Voltage Level Select 1.5V */ +#define REFVSEL_1 (0x0010) /* REF Reference Voltage Level Select 2.0V */ +#define REFVSEL_2 (0x0020) /* REF Reference Voltage Level Select 2.5V */ +#define REFVSEL_3 (0x0030) /* REF Reference Voltage Level Select 2.5V */ + +#endif +/************************************************************ +* Shared Reference +************************************************************/ +#ifdef __MSP430_HAS_REF__ /* Definition to show that Module is available */ + +#define OFS_REFCTL0 (0x0000) /* REF Shared Reference control register 0 */ +#define OFS_REFCTL0_L OFS_REFCTL0 +#define OFS_REFCTL0_H OFS_REFCTL0+1 + +/* REFCTL0 Control Bits */ +#define REFON (0x0001) /* REF Reference On */ +//#define RESERVED (0x0002) /* Reserved */ +//#define RESERVED (0x0004) /* Reserved */ +#define REFTCOFF (0x0008) /* REF Temp.Sensor off */ +#define REFVSEL0 (0x0010) /* REF Reference Voltage Level Select Bit:0 */ +#define REFVSEL1 (0x0020) /* REF Reference Voltage Level Select Bit:1 */ +//#define RESERVED (0x0040) /* Reserved */ +//#define RESERVED (0x0080) /* Reserved */ +#define REFGENACT (0x0100) /* REF Reference generator active */ +#define REFBGACT (0x0200) /* REF Reference bandgap active */ +#define REFGENBUSY (0x0400) /* REF Reference generator busy */ +#define BGMODE (0x0800) /* REF Bandgap mode */ +//#define RESERVED (0x1000) /* Reserved */ +//#define RESERVED (0x2000) /* Reserved */ +//#define RESERVED (0x4000) /* Reserved */ +//#define RESERVED (0x8000) /* Reserved */ + +/* REFCTL0 Control Bits */ +#define REFON_L (0x0001) /* REF Reference On */ +//#define RESERVED (0x0002) /* Reserved */ +//#define RESERVED (0x0004) /* Reserved */ +#define REFTCOFF_L (0x0008) /* REF Temp.Sensor off */ +#define REFVSEL0_L (0x0010) /* REF Reference Voltage Level Select Bit:0 */ +#define REFVSEL1_L (0x0020) /* REF Reference Voltage Level Select Bit:1 */ +//#define RESERVED (0x0040) /* Reserved */ +//#define RESERVED (0x0080) /* Reserved */ +//#define RESERVED (0x1000) /* Reserved */ +//#define RESERVED (0x2000) /* Reserved */ +//#define RESERVED (0x4000) /* Reserved */ +//#define RESERVED (0x8000) /* Reserved */ + +/* REFCTL0 Control Bits */ +//#define RESERVED (0x0002) /* Reserved */ +//#define RESERVED (0x0004) /* Reserved */ +//#define RESERVED (0x0040) /* Reserved */ +//#define RESERVED (0x0080) /* Reserved */ +#define REFGENACT_H (0x0001) /* REF Reference generator active */ +#define REFBGACT_H (0x0002) /* REF Reference bandgap active */ +#define REFGENBUSY_H (0x0004) /* REF Reference generator busy */ +#define BGMODE_H (0x0008) /* REF Bandgap mode */ +//#define RESERVED (0x1000) /* Reserved */ +//#define RESERVED (0x2000) /* Reserved */ +//#define RESERVED (0x4000) /* Reserved */ +//#define RESERVED (0x8000) /* Reserved */ + +#define REFVSEL_0 (0x0000) /* REF Reference Voltage Level Select 1.5V */ +#define REFVSEL_1 (0x0010) /* REF Reference Voltage Level Select 2.0V */ +#define REFVSEL_2 (0x0020) /* REF Reference Voltage Level Select 2.5V */ +#define REFVSEL_3 (0x0030) /* REF Reference Voltage Level Select 2.5V */ + +#endif +/************************************************************ +* Real Time Clock +************************************************************/ +#ifdef __MSP430_HAS_RTC__ /* Definition to show that Module is available */ + +#define OFS_RTCCTL01 (0x0000) /* Real Timer Control 0/1 */ +#define OFS_RTCCTL01_L OFS_RTCCTL01 +#define OFS_RTCCTL01_H OFS_RTCCTL01+1 +#define OFS_RTCCTL23 (0x0002) /* Real Timer Control 2/3 */ +#define OFS_RTCCTL23_L OFS_RTCCTL23 +#define OFS_RTCCTL23_H OFS_RTCCTL23+1 +#define OFS_RTCPS0CTL (0x0008) /* Real Timer Prescale Timer 0 Control */ +#define OFS_RTCPS0CTL_L OFS_RTCPS0CTL +#define OFS_RTCPS0CTL_H OFS_RTCPS0CTL+1 +#define OFS_RTCPS1CTL (0x000A) /* Real Timer Prescale Timer 1 Control */ +#define OFS_RTCPS1CTL_L OFS_RTCPS1CTL +#define OFS_RTCPS1CTL_H OFS_RTCPS1CTL+1 +#define OFS_RTCPS (0x000C) /* Real Timer Prescale Timer Control */ +#define OFS_RTCPS_L OFS_RTCPS +#define OFS_RTCPS_H OFS_RTCPS+1 +#define OFS_RTCIV (0x000E) /* Real Time Clock Interrupt Vector */ +#define OFS_RTCTIM0 (0x0010) /* Real Time Clock Time 0 */ +#define OFS_RTCTIM0_L OFS_RTCTIM0 +#define OFS_RTCTIM0_H OFS_RTCTIM0+1 +#define OFS_RTCTIM1 (0x0012) /* Real Time Clock Time 1 */ +#define OFS_RTCTIM1_L OFS_RTCTIM1 +#define OFS_RTCTIM1_H OFS_RTCTIM1+1 +#define OFS_RTCDATE (0x0014) /* Real Time Clock Date */ +#define OFS_RTCDATE_L OFS_RTCDATE +#define OFS_RTCDATE_H OFS_RTCDATE+1 +#define OFS_RTCYEAR (0x0016) /* Real Time Clock Year */ +#define OFS_RTCYEAR_L OFS_RTCYEAR +#define OFS_RTCYEAR_H OFS_RTCYEAR+1 +#define OFS_RTCAMINHR (0x0018) /* Real Time Clock Alarm Min/Hour */ +#define OFS_RTCAMINHR_L OFS_RTCAMINHR +#define OFS_RTCAMINHR_H OFS_RTCAMINHR+1 +#define OFS_RTCADOWDAY (0x001A) /* Real Time Clock Alarm day of week/day */ +#define OFS_RTCADOWDAY_L OFS_RTCADOWDAY +#define OFS_RTCADOWDAY_H OFS_RTCADOWDAY+1 +#define OFS_RTCSEC (0x0010) +#define OFS_RTCMIN (0x0011) +#define OFS_RTCHOUR (0x0012) +#define OFS_RTCDOW (0x0013) +#define OFS_RTCDAY (0x0014) +#define OFS_RTCMON (0x0015) +#define OFS_RTCAMIN (0x0018) +#define OFS_RTCAHOUR (0x0019) +#define OFS_RTCADOW (0x001A) +#define OFS_RTCADAY (0x001B) + +#define RTCCTL0 RTCCTL01_L /* Real Time Clock Control 0 */ +#define RTCCTL1 RTCCTL01_H /* Real Time Clock Control 1 */ +#define RTCCTL2 RTCCTL23_L /* Real Time Clock Control 2 */ +#define RTCCTL3 RTCCTL23_H /* Real Time Clock Control 3 */ +#define RTCNT12 RTCTIM0 +#define RTCNT34 RTCTIM1 +#define RTCNT1 RTCTIM0_L +#define RTCNT2 RTCTIM0_H +#define RTCNT3 RTCTIM1_L +#define RTCNT4 RTCTIM1_H +#define RTCSEC RTCTIM0_L +#define RTCMIN RTCTIM0_H +#define RTCHOUR RTCTIM1_L +#define RTCDOW RTCTIM1_H +#define RTCDAY RTCDATE_L +#define RTCMON RTCDATE_H +#define RTCYEARL RTCYEAR_L +#define RTCYEARH RTCYEAR_H +#define RT0PS RTCPS_L +#define RT1PS RTCPS_H +#define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */ +#define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */ +#define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */ +#define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */ + +/* RTCCTL01 Control Bits */ +#define RTCBCD (0x8000) /* RTC BCD 0:Binary / 1:BCD */ +#define RTCHOLD (0x4000) /* RTC Hold */ +#define RTCMODE (0x2000) /* RTC Mode 0:Counter / 1: Calendar */ +#define RTCRDY (0x1000) /* RTC Ready */ +#define RTCSSEL1 (0x0800) /* RTC Source Select 1 */ +#define RTCSSEL0 (0x0400) /* RTC Source Select 0 */ +#define RTCTEV1 (0x0200) /* RTC Time Event 1 */ +#define RTCTEV0 (0x0100) /* RTC Time Event 0 */ +//#define Reserved (0x0080) +#define RTCTEVIE (0x0040) /* RTC Time Event Interrupt Enable Flag */ +#define RTCAIE (0x0020) /* RTC Alarm Interrupt Enable Flag */ +#define RTCRDYIE (0x0010) /* RTC Ready Interrupt Enable Flag */ +//#define Reserved (0x0008) +#define RTCTEVIFG (0x0004) /* RTC Time Event Interrupt Flag */ +#define RTCAIFG (0x0002) /* RTC Alarm Interrupt Flag */ +#define RTCRDYIFG (0x0001) /* RTC Ready Interrupt Flag */ + +/* RTCCTL01 Control Bits */ +//#define Reserved (0x0080) +#define RTCTEVIE_L (0x0040) /* RTC Time Event Interrupt Enable Flag */ +#define RTCAIE_L (0x0020) /* RTC Alarm Interrupt Enable Flag */ +#define RTCRDYIE_L (0x0010) /* RTC Ready Interrupt Enable Flag */ +//#define Reserved (0x0008) +#define RTCTEVIFG_L (0x0004) /* RTC Time Event Interrupt Flag */ +#define RTCAIFG_L (0x0002) /* RTC Alarm Interrupt Flag */ +#define RTCRDYIFG_L (0x0001) /* RTC Ready Interrupt Flag */ + +/* RTCCTL01 Control Bits */ +#define RTCBCD_H (0x0080) /* RTC BCD 0:Binary / 1:BCD */ +#define RTCHOLD_H (0x0040) /* RTC Hold */ +#define RTCMODE_H (0x0020) /* RTC Mode 0:Counter / 1: Calendar */ +#define RTCRDY_H (0x0010) /* RTC Ready */ +#define RTCSSEL1_H (0x0008) /* RTC Source Select 1 */ +#define RTCSSEL0_H (0x0004) /* RTC Source Select 0 */ +#define RTCTEV1_H (0x0002) /* RTC Time Event 1 */ +#define RTCTEV0_H (0x0001) /* RTC Time Event 0 */ +//#define Reserved (0x0080) +//#define Reserved (0x0008) + +#define RTCSSEL_0 (0x0000) /* RTC Source Select ACLK */ +#define RTCSSEL_1 (0x0400) /* RTC Source Select SMCLK */ +#define RTCSSEL_2 (0x0800) /* RTC Source Select RT1PS */ +#define RTCSSEL_3 (0x0C00) /* RTC Source Select RT1PS */ +#define RTCSSEL__ACLK (0x0000) /* RTC Source Select ACLK */ +#define RTCSSEL__SMCLK (0x0400) /* RTC Source Select SMCLK */ +#define RTCSSEL__RT1PS (0x0800) /* RTC Source Select RT1PS */ +#define RTCTEV_0 (0x0000) /* RTC Time Event: 0 (Min. changed) */ +#define RTCTEV_1 (0x0100) /* RTC Time Event: 1 (Hour changed) */ +#define RTCTEV_2 (0x0200) /* RTC Time Event: 2 (12:00 changed) */ +#define RTCTEV_3 (0x0300) /* RTC Time Event: 3 (00:00 changed) */ +#define RTCTEV__MIN (0x0000) /* RTC Time Event: 0 (Min. changed) */ +#define RTCTEV__HOUR (0x0100) /* RTC Time Event: 1 (Hour changed) */ +#define RTCTEV__0000 (0x0200) /* RTC Time Event: 2 (00:00 changed) */ +#define RTCTEV__1200 (0x0300) /* RTC Time Event: 3 (12:00 changed) */ + +/* RTCCTL23 Control Bits */ +#define RTCCALF1 (0x0200) /* RTC Calibration Frequency Bit 1 */ +#define RTCCALF0 (0x0100) /* RTC Calibration Frequency Bit 0 */ +#define RTCCALS (0x0080) /* RTC Calibration Sign */ +//#define Reserved (0x0040) +#define RTCCAL5 (0x0020) /* RTC Calibration Bit 5 */ +#define RTCCAL4 (0x0010) /* RTC Calibration Bit 4 */ +#define RTCCAL3 (0x0008) /* RTC Calibration Bit 3 */ +#define RTCCAL2 (0x0004) /* RTC Calibration Bit 2 */ +#define RTCCAL1 (0x0002) /* RTC Calibration Bit 1 */ +#define RTCCAL0 (0x0001) /* RTC Calibration Bit 0 */ + +/* RTCCTL23 Control Bits */ +#define RTCCALS_L (0x0080) /* RTC Calibration Sign */ +//#define Reserved (0x0040) +#define RTCCAL5_L (0x0020) /* RTC Calibration Bit 5 */ +#define RTCCAL4_L (0x0010) /* RTC Calibration Bit 4 */ +#define RTCCAL3_L (0x0008) /* RTC Calibration Bit 3 */ +#define RTCCAL2_L (0x0004) /* RTC Calibration Bit 2 */ +#define RTCCAL1_L (0x0002) /* RTC Calibration Bit 1 */ +#define RTCCAL0_L (0x0001) /* RTC Calibration Bit 0 */ + +/* RTCCTL23 Control Bits */ +#define RTCCALF1_H (0x0002) /* RTC Calibration Frequency Bit 1 */ +#define RTCCALF0_H (0x0001) /* RTC Calibration Frequency Bit 0 */ +//#define Reserved (0x0040) + +#define RTCCALF_0 (0x0000) /* RTC Calibration Frequency: No Output */ +#define RTCCALF_1 (0x0100) /* RTC Calibration Frequency: 512 Hz */ +#define RTCCALF_2 (0x0200) /* RTC Calibration Frequency: 256 Hz */ +#define RTCCALF_3 (0x0300) /* RTC Calibration Frequency: 1 Hz */ + +#define RTCAE (0x80) /* Real Time Clock Alarm enable */ + +/* RTCPS0CTL Control Bits */ +//#define Reserved (0x8000) +#define RT0SSEL (0x4000) /* RTC Prescale Timer 0 Source Select 0:ACLK / 1:SMCLK */ +#define RT0PSDIV2 (0x2000) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */ +#define RT0PSDIV1 (0x1000) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */ +#define RT0PSDIV0 (0x0800) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */ +//#define Reserved (0x0400) +//#define Reserved (0x0200) +#define RT0PSHOLD (0x0100) /* RTC Prescale Timer 0 Hold */ +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) +#define RT0IP2 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */ +#define RT0IP1 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */ +#define RT0IP0 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */ +#define RT0PSIE (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */ +#define RT0PSIFG (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */ + +/* RTCPS0CTL Control Bits */ +//#define Reserved (0x8000) +//#define Reserved (0x0400) +//#define Reserved (0x0200) +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) +#define RT0IP2_L (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */ +#define RT0IP1_L (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */ +#define RT0IP0_L (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */ +#define RT0PSIE_L (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */ +#define RT0PSIFG_L (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */ + +/* RTCPS0CTL Control Bits */ +//#define Reserved (0x8000) +#define RT0SSEL_H (0x0040) /* RTC Prescale Timer 0 Source Select 0:ACLK / 1:SMCLK */ +#define RT0PSDIV2_H (0x0020) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */ +#define RT0PSDIV1_H (0x0010) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */ +#define RT0PSDIV0_H (0x0008) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */ +//#define Reserved (0x0400) +//#define Reserved (0x0200) +#define RT0PSHOLD_H (0x0001) /* RTC Prescale Timer 0 Hold */ +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) + +#define RT0IP_0 (0x0000) /* RTC Prescale Timer 0 Interrupt Interval /2 */ +#define RT0IP_1 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval /4 */ +#define RT0IP_2 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval /8 */ +#define RT0IP_3 (0x000C) /* RTC Prescale Timer 0 Interrupt Interval /16 */ +#define RT0IP_4 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval /32 */ +#define RT0IP_5 (0x0014) /* RTC Prescale Timer 0 Interrupt Interval /64 */ +#define RT0IP_6 (0x0018) /* RTC Prescale Timer 0 Interrupt Interval /128 */ +#define RT0IP_7 (0x001C) /* RTC Prescale Timer 0 Interrupt Interval /256 */ + +#define RT0PSDIV_0 (0x0000) /* RTC Prescale Timer 0 Clock Divide /2 */ +#define RT0PSDIV_1 (0x0800) /* RTC Prescale Timer 0 Clock Divide /4 */ +#define RT0PSDIV_2 (0x1000) /* RTC Prescale Timer 0 Clock Divide /8 */ +#define RT0PSDIV_3 (0x1800) /* RTC Prescale Timer 0 Clock Divide /16 */ +#define RT0PSDIV_4 (0x2000) /* RTC Prescale Timer 0 Clock Divide /32 */ +#define RT0PSDIV_5 (0x2800) /* RTC Prescale Timer 0 Clock Divide /64 */ +#define RT0PSDIV_6 (0x3000) /* RTC Prescale Timer 0 Clock Divide /128 */ +#define RT0PSDIV_7 (0x3800) /* RTC Prescale Timer 0 Clock Divide /256 */ + +/* RTCPS1CTL Control Bits */ +#define RT1SSEL1 (0x8000) /* RTC Prescale Timer 1 Source Select Bit 1 */ +#define RT1SSEL0 (0x4000) /* RTC Prescale Timer 1 Source Select Bit 0 */ +#define RT1PSDIV2 (0x2000) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */ +#define RT1PSDIV1 (0x1000) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */ +#define RT1PSDIV0 (0x0800) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */ +//#define Reserved (0x0400) +//#define Reserved (0x0200) +#define RT1PSHOLD (0x0100) /* RTC Prescale Timer 1 Hold */ +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) +#define RT1IP2 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */ +#define RT1IP1 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */ +#define RT1IP0 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */ +#define RT1PSIE (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */ +#define RT1PSIFG (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */ + +/* RTCPS1CTL Control Bits */ +//#define Reserved (0x0400) +//#define Reserved (0x0200) +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) +#define RT1IP2_L (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */ +#define RT1IP1_L (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */ +#define RT1IP0_L (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */ +#define RT1PSIE_L (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */ +#define RT1PSIFG_L (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */ + +/* RTCPS1CTL Control Bits */ +#define RT1SSEL1_H (0x0080) /* RTC Prescale Timer 1 Source Select Bit 1 */ +#define RT1SSEL0_H (0x0040) /* RTC Prescale Timer 1 Source Select Bit 0 */ +#define RT1PSDIV2_H (0x0020) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */ +#define RT1PSDIV1_H (0x0010) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */ +#define RT1PSDIV0_H (0x0008) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */ +//#define Reserved (0x0400) +//#define Reserved (0x0200) +#define RT1PSHOLD_H (0x0001) /* RTC Prescale Timer 1 Hold */ +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) + +#define RT1IP_0 (0x0000) /* RTC Prescale Timer 1 Interrupt Interval /2 */ +#define RT1IP_1 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval /4 */ +#define RT1IP_2 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval /8 */ +#define RT1IP_3 (0x000C) /* RTC Prescale Timer 1 Interrupt Interval /16 */ +#define RT1IP_4 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval /32 */ +#define RT1IP_5 (0x0014) /* RTC Prescale Timer 1 Interrupt Interval /64 */ +#define RT1IP_6 (0x0018) /* RTC Prescale Timer 1 Interrupt Interval /128 */ +#define RT1IP_7 (0x001C) /* RTC Prescale Timer 1 Interrupt Interval /256 */ + +#define RT1PSDIV_0 (0x0000) /* RTC Prescale Timer 1 Clock Divide /2 */ +#define RT1PSDIV_1 (0x0800) /* RTC Prescale Timer 1 Clock Divide /4 */ +#define RT1PSDIV_2 (0x1000) /* RTC Prescale Timer 1 Clock Divide /8 */ +#define RT1PSDIV_3 (0x1800) /* RTC Prescale Timer 1 Clock Divide /16 */ +#define RT1PSDIV_4 (0x2000) /* RTC Prescale Timer 1 Clock Divide /32 */ +#define RT1PSDIV_5 (0x2800) /* RTC Prescale Timer 1 Clock Divide /64 */ +#define RT1PSDIV_6 (0x3000) /* RTC Prescale Timer 1 Clock Divide /128 */ +#define RT1PSDIV_7 (0x3800) /* RTC Prescale Timer 1 Clock Divide /256 */ + +#define RT1SSEL_0 (0x0000) /* RTC Prescale Timer Source Select ACLK */ +#define RT1SSEL_1 (0x4000) /* RTC Prescale Timer Source Select SMCLK */ +#define RT1SSEL_2 (0x8000) /* RTC Prescale Timer Source Select RT0PS */ +#define RT1SSEL_3 (0xC000) /* RTC Prescale Timer Source Select RT0PS */ + +/* RTC Definitions */ +#define RTCIV_NONE (0x0000) /* No Interrupt pending */ +#define RTCIV_RTCRDYIFG (0x0002) /* RTC ready: RTCRDYIFG */ +#define RTCIV_RTCTEVIFG (0x0004) /* RTC interval timer: RTCTEVIFG */ +#define RTCIV_RTCAIFG (0x0006) /* RTC user alarm: RTCAIFG */ +#define RTCIV_RT0PSIFG (0x0008) /* RTC prescaler 0: RT0PSIFG */ +#define RTCIV_RT1PSIFG (0x000A) /* RTC prescaler 1: RT1PSIFG */ + +/* Legacy Definitions */ +#define RTC_NONE (0x0000) /* No Interrupt pending */ +#define RTC_RTCRDYIFG (0x0002) /* RTC ready: RTCRDYIFG */ +#define RTC_RTCTEVIFG (0x0004) /* RTC interval timer: RTCTEVIFG */ +#define RTC_RTCAIFG (0x0006) /* RTC user alarm: RTCAIFG */ +#define RTC_RT0PSIFG (0x0008) /* RTC prescaler 0: RT0PSIFG */ +#define RTC_RT1PSIFG (0x000A) /* RTC prescaler 1: RT1PSIFG */ + +#endif +/************************************************************ +* Real Time Clock +************************************************************/ +#ifdef __MSP430_HAS_RTC_B__ /* Definition to show that Module is available */ + +#define OFS_RTCCTL01 (0x0000) /* Real Timer Control 0/1 */ +#define OFS_RTCCTL01_L OFS_RTCCTL01 +#define OFS_RTCCTL01_H OFS_RTCCTL01+1 +#define OFS_RTCCTL23 (0x0002) /* Real Timer Control 2/3 */ +#define OFS_RTCCTL23_L OFS_RTCCTL23 +#define OFS_RTCCTL23_H OFS_RTCCTL23+1 +#define OFS_RTCPS0CTL (0x0008) /* Real Timer Prescale Timer 0 Control */ +#define OFS_RTCPS0CTL_L OFS_RTCPS0CTL +#define OFS_RTCPS0CTL_H OFS_RTCPS0CTL+1 +#define OFS_RTCPS1CTL (0x000A) /* Real Timer Prescale Timer 1 Control */ +#define OFS_RTCPS1CTL_L OFS_RTCPS1CTL +#define OFS_RTCPS1CTL_H OFS_RTCPS1CTL+1 +#define OFS_RTCPS (0x000C) /* Real Timer Prescale Timer Control */ +#define OFS_RTCPS_L OFS_RTCPS +#define OFS_RTCPS_H OFS_RTCPS+1 +#define OFS_RTCIV (0x000E) /* Real Time Clock Interrupt Vector */ +#define OFS_RTCTIM0 (0x0010) /* Real Time Clock Time 0 */ +#define OFS_RTCTIM0_L OFS_RTCTIM0 +#define OFS_RTCTIM0_H OFS_RTCTIM0+1 +#define OFS_RTCTIM1 (0x0012) /* Real Time Clock Time 1 */ +#define OFS_RTCTIM1_L OFS_RTCTIM1 +#define OFS_RTCTIM1_H OFS_RTCTIM1+1 +#define OFS_RTCDATE (0x0014) /* Real Time Clock Date */ +#define OFS_RTCDATE_L OFS_RTCDATE +#define OFS_RTCDATE_H OFS_RTCDATE+1 +#define OFS_RTCYEAR (0x0016) /* Real Time Clock Year */ +#define OFS_RTCYEAR_L OFS_RTCYEAR +#define OFS_RTCYEAR_H OFS_RTCYEAR+1 +#define OFS_RTCAMINHR (0x0018) /* Real Time Clock Alarm Min/Hour */ +#define OFS_RTCAMINHR_L OFS_RTCAMINHR +#define OFS_RTCAMINHR_H OFS_RTCAMINHR+1 +#define OFS_RTCADOWDAY (0x001A) /* Real Time Clock Alarm day of week/day */ +#define OFS_RTCADOWDAY_L OFS_RTCADOWDAY +#define OFS_RTCADOWDAY_H OFS_RTCADOWDAY+1 +#define OFS_BIN2BCD (0x001C) /* Real Time Binary-to-BCD conversion register */ +#define OFS_BCD2BIN (0x001E) /* Real Time BCD-to-binary conversion register */ +#define OFS_RTCSEC (0x0010) +#define OFS_RTCMIN (0x0011) +#define OFS_RTCHOUR (0x0012) +#define OFS_RTCDOW (0x0013) +#define OFS_RTCDAY (0x0014) +#define OFS_RTCMON (0x0015) +#define OFS_RTCAMIN (0x0018) +#define OFS_RTCAHOUR (0x0019) +#define OFS_RTCADOW (0x001A) +#define OFS_RTCADAY (0x001B) + +#define RTCCTL0 RTCCTL01_L /* Real Time Clock Control 0 */ +#define RTCCTL1 RTCCTL01_H /* Real Time Clock Control 1 */ +#define RTCCTL2 RTCCTL23_L /* Real Time Clock Control 2 */ +#define RTCCTL3 RTCCTL23_H /* Real Time Clock Control 3 */ +#define RTCNT12 RTCTIM0 +#define RTCNT34 RTCTIM1 +#define RTCNT1 RTCTIM0_L +#define RTCNT2 RTCTIM0_H +#define RTCNT3 RTCTIM1_L +#define RTCNT4 RTCTIM1_H +#define RTCSEC RTCTIM0_L +#define RTCMIN RTCTIM0_H +#define RTCHOUR RTCTIM1_L +#define RTCDOW RTCTIM1_H +#define RTCDAY RTCDATE_L +#define RTCMON RTCDATE_H +#define RTCYEARL RTCYEAR_L +#define RTCYEARH RTCYEAR_H +#define RT0PS RTCPS_L +#define RT1PS RTCPS_H +#define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */ +#define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */ +#define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */ +#define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */ + +/* RTCCTL01 Control Bits */ +#define RTCBCD (0x8000) /* RTC BCD 0:Binary / 1:BCD */ +#define RTCHOLD (0x4000) /* RTC Hold */ +//#define RESERVED (0x2000) /* RESERVED */ +#define RTCRDY (0x1000) /* RTC Ready */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +#define RTCTEV1 (0x0200) /* RTC Time Event 1 */ +#define RTCTEV0 (0x0100) /* RTC Time Event 0 */ +#define RTCOFIE (0x0080) /* RTC 32kHz cyrstal oscillator fault interrupt enable */ +#define RTCTEVIE (0x0040) /* RTC Time Event Interrupt Enable Flag */ +#define RTCAIE (0x0020) /* RTC Alarm Interrupt Enable Flag */ +#define RTCRDYIE (0x0010) /* RTC Ready Interrupt Enable Flag */ +#define RTCOFIFG (0x0008) /* RTC 32kHz cyrstal oscillator fault interrupt flag */ +#define RTCTEVIFG (0x0004) /* RTC Time Event Interrupt Flag */ +#define RTCAIFG (0x0002) /* RTC Alarm Interrupt Flag */ +#define RTCRDYIFG (0x0001) /* RTC Ready Interrupt Flag */ + +/* RTCCTL01 Control Bits */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +#define RTCOFIE_L (0x0080) /* RTC 32kHz cyrstal oscillator fault interrupt enable */ +#define RTCTEVIE_L (0x0040) /* RTC Time Event Interrupt Enable Flag */ +#define RTCAIE_L (0x0020) /* RTC Alarm Interrupt Enable Flag */ +#define RTCRDYIE_L (0x0010) /* RTC Ready Interrupt Enable Flag */ +#define RTCOFIFG_L (0x0008) /* RTC 32kHz cyrstal oscillator fault interrupt flag */ +#define RTCTEVIFG_L (0x0004) /* RTC Time Event Interrupt Flag */ +#define RTCAIFG_L (0x0002) /* RTC Alarm Interrupt Flag */ +#define RTCRDYIFG_L (0x0001) /* RTC Ready Interrupt Flag */ + +/* RTCCTL01 Control Bits */ +#define RTCBCD_H (0x0080) /* RTC BCD 0:Binary / 1:BCD */ +#define RTCHOLD_H (0x0040) /* RTC Hold */ +//#define RESERVED (0x2000) /* RESERVED */ +#define RTCRDY_H (0x0010) /* RTC Ready */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +#define RTCTEV1_H (0x0002) /* RTC Time Event 1 */ +#define RTCTEV0_H (0x0001) /* RTC Time Event 0 */ + +#define RTCTEV_0 (0x0000) /* RTC Time Event: 0 (Min. changed) */ +#define RTCTEV_1 (0x0100) /* RTC Time Event: 1 (Hour changed) */ +#define RTCTEV_2 (0x0200) /* RTC Time Event: 2 (12:00 changed) */ +#define RTCTEV_3 (0x0300) /* RTC Time Event: 3 (00:00 changed) */ +#define RTCTEV__MIN (0x0000) /* RTC Time Event: 0 (Min. changed) */ +#define RTCTEV__HOUR (0x0100) /* RTC Time Event: 1 (Hour changed) */ +#define RTCTEV__0000 (0x0200) /* RTC Time Event: 2 (00:00 changed) */ +#define RTCTEV__1200 (0x0300) /* RTC Time Event: 3 (12:00 changed) */ + +/* RTCCTL23 Control Bits */ +#define RTCCALF1 (0x0200) /* RTC Calibration Frequency Bit 1 */ +#define RTCCALF0 (0x0100) /* RTC Calibration Frequency Bit 0 */ +#define RTCCALS (0x0080) /* RTC Calibration Sign */ +//#define Reserved (0x0040) +#define RTCCAL5 (0x0020) /* RTC Calibration Bit 5 */ +#define RTCCAL4 (0x0010) /* RTC Calibration Bit 4 */ +#define RTCCAL3 (0x0008) /* RTC Calibration Bit 3 */ +#define RTCCAL2 (0x0004) /* RTC Calibration Bit 2 */ +#define RTCCAL1 (0x0002) /* RTC Calibration Bit 1 */ +#define RTCCAL0 (0x0001) /* RTC Calibration Bit 0 */ + +/* RTCCTL23 Control Bits */ +#define RTCCALS_L (0x0080) /* RTC Calibration Sign */ +//#define Reserved (0x0040) +#define RTCCAL5_L (0x0020) /* RTC Calibration Bit 5 */ +#define RTCCAL4_L (0x0010) /* RTC Calibration Bit 4 */ +#define RTCCAL3_L (0x0008) /* RTC Calibration Bit 3 */ +#define RTCCAL2_L (0x0004) /* RTC Calibration Bit 2 */ +#define RTCCAL1_L (0x0002) /* RTC Calibration Bit 1 */ +#define RTCCAL0_L (0x0001) /* RTC Calibration Bit 0 */ + +/* RTCCTL23 Control Bits */ +#define RTCCALF1_H (0x0002) /* RTC Calibration Frequency Bit 1 */ +#define RTCCALF0_H (0x0001) /* RTC Calibration Frequency Bit 0 */ +//#define Reserved (0x0040) + +#define RTCCALF_0 (0x0000) /* RTC Calibration Frequency: No Output */ +#define RTCCALF_1 (0x0100) /* RTC Calibration Frequency: 512 Hz */ +#define RTCCALF_2 (0x0200) /* RTC Calibration Frequency: 256 Hz */ +#define RTCCALF_3 (0x0300) /* RTC Calibration Frequency: 1 Hz */ + +#define RTCAE (0x80) /* Real Time Clock Alarm enable */ + +/* RTCPS0CTL Control Bits */ +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) +#define RT0IP2 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */ +#define RT0IP1 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */ +#define RT0IP0 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */ +#define RT0PSIE (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */ +#define RT0PSIFG (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */ + +/* RTCPS0CTL Control Bits */ +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) +#define RT0IP2_L (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */ +#define RT0IP1_L (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */ +#define RT0IP0_L (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */ +#define RT0PSIE_L (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */ +#define RT0PSIFG_L (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */ + +#define RT0IP_0 (0x0000) /* RTC Prescale Timer 0 Interrupt Interval /2 */ +#define RT0IP_1 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval /4 */ +#define RT0IP_2 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval /8 */ +#define RT0IP_3 (0x000C) /* RTC Prescale Timer 0 Interrupt Interval /16 */ +#define RT0IP_4 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval /32 */ +#define RT0IP_5 (0x0014) /* RTC Prescale Timer 0 Interrupt Interval /64 */ +#define RT0IP_6 (0x0018) /* RTC Prescale Timer 0 Interrupt Interval /128 */ +#define RT0IP_7 (0x001C) /* RTC Prescale Timer 0 Interrupt Interval /256 */ + +#define RT0IP__2 (0x0000) /* RTC Prescale Timer 0 Interrupt Interval /2 */ +#define RT0IP__4 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval /4 */ +#define RT0IP__8 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval /8 */ +#define RT0IP__16 (0x000C) /* RTC Prescale Timer 0 Interrupt Interval /16 */ +#define RT0IP__32 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval /32 */ +#define RT0IP__64 (0x0014) /* RTC Prescale Timer 0 Interrupt Interval /64 */ +#define RT0IP__128 (0x0018) /* RTC Prescale Timer 0 Interrupt Interval /128 */ +#define RT0IP__256 (0x001C) /* RTC Prescale Timer 0 Interrupt Interval /256 */ + +/* RTCPS1CTL Control Bits */ +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) +#define RT1IP2 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */ +#define RT1IP1 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */ +#define RT1IP0 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */ +#define RT1PSIE (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */ +#define RT1PSIFG (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */ + +/* RTCPS1CTL Control Bits */ +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) +#define RT1IP2_L (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */ +#define RT1IP1_L (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */ +#define RT1IP0_L (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */ +#define RT1PSIE_L (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */ +#define RT1PSIFG_L (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */ + +#define RT1IP_0 (0x0000) /* RTC Prescale Timer 1 Interrupt Interval /2 */ +#define RT1IP_1 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval /4 */ +#define RT1IP_2 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval /8 */ +#define RT1IP_3 (0x000C) /* RTC Prescale Timer 1 Interrupt Interval /16 */ +#define RT1IP_4 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval /32 */ +#define RT1IP_5 (0x0014) /* RTC Prescale Timer 1 Interrupt Interval /64 */ +#define RT1IP_6 (0x0018) /* RTC Prescale Timer 1 Interrupt Interval /128 */ +#define RT1IP_7 (0x001C) /* RTC Prescale Timer 1 Interrupt Interval /256 */ + +#define RT1IP__2 (0x0000) /* RTC Prescale Timer 1 Interrupt Interval /2 */ +#define RT1IP__4 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval /4 */ +#define RT1IP__8 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval /8 */ +#define RT1IP__16 (0x000C) /* RTC Prescale Timer 1 Interrupt Interval /16 */ +#define RT1IP__32 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval /32 */ +#define RT1IP__64 (0x0014) /* RTC Prescale Timer 1 Interrupt Interval /64 */ +#define RT1IP__128 (0x0018) /* RTC Prescale Timer 1 Interrupt Interval /128 */ +#define RT1IP__256 (0x001C) /* RTC Prescale Timer 1 Interrupt Interval /256 */ + +/* RTC Definitions */ +#define RTCIV_NONE (0x0000) /* No Interrupt pending */ +#define RTCIV_RTCRDYIFG (0x0002) /* RTC ready: RTCRDYIFG */ +#define RTCIV_RTCTEVIFG (0x0004) /* RTC interval timer: RTCTEVIFG */ +#define RTCIV_RTCAIFG (0x0006) /* RTC user alarm: RTCAIFG */ +#define RTCIV_RT0PSIFG (0x0008) /* RTC prescaler 0: RT0PSIFG */ +#define RTCIV_RT1PSIFG (0x000A) /* RTC prescaler 1: RT1PSIFG */ +#define RTCIV_RTCOFIFG (0x000C) /* RTC Oscillator fault */ + +/* Legacy Definitions */ +#define RTC_NONE (0x0000) /* No Interrupt pending */ +#define RTC_RTCRDYIFG (0x0002) /* RTC ready: RTCRDYIFG */ +#define RTC_RTCTEVIFG (0x0004) /* RTC interval timer: RTCTEVIFG */ +#define RTC_RTCAIFG (0x0006) /* RTC user alarm: RTCAIFG */ +#define RTC_RT0PSIFG (0x0008) /* RTC prescaler 0: RT0PSIFG */ +#define RTC_RT1PSIFG (0x000A) /* RTC prescaler 1: RT1PSIFG */ +#define RTC_RTCOFIFG (0x000C) /* RTC Oscillator fault */ + +#endif +/************************************************************ +* Real Time Clock +************************************************************/ +#ifdef __MSP430_HAS_RTC_C__ /* Definition to show that Module is available */ + +#define OFS_RTCCTL0 (0x0000) /* Real Timer Clock Control 0/Key */ +#define OFS_RTCCTL0_L OFS_RTCCTL0 +#define OFS_RTCCTL0_H OFS_RTCCTL0+1 +#define OFS_RTCCTL13 (0x0002) /* Real Timer Clock Control 1/3 */ +#define OFS_RTCCTL13_L OFS_RTCCTL13 +#define OFS_RTCCTL13_H OFS_RTCCTL13+1 +#define RTCCTL1 RTCCTL13_L +#define RTCCTL3 RTCCTL13_H +#define OFS_RTCOCAL (0x0004) /* Real Timer Clock Offset Calibartion */ +#define OFS_RTCOCAL_L OFS_RTCOCAL +#define OFS_RTCOCAL_H OFS_RTCOCAL+1 +#define OFS_RTCTCMP (0x0006) /* Real Timer Temperature Compensation */ +#define OFS_RTCTCMP_L OFS_RTCTCMP +#define OFS_RTCTCMP_H OFS_RTCTCMP+1 +#define OFS_RTCPS0CTL (0x0008) /* Real Timer Prescale Timer 0 Control */ +#define OFS_RTCPS0CTL_L OFS_RTCPS0CTL +#define OFS_RTCPS0CTL_H OFS_RTCPS0CTL+1 +#define OFS_RTCPS1CTL (0x000A) /* Real Timer Prescale Timer 1 Control */ +#define OFS_RTCPS1CTL_L OFS_RTCPS1CTL +#define OFS_RTCPS1CTL_H OFS_RTCPS1CTL+1 +#define OFS_RTCPS (0x000C) /* Real Timer Prescale Timer Control */ +#define OFS_RTCPS_L OFS_RTCPS +#define OFS_RTCPS_H OFS_RTCPS+1 +#define OFS_RTCIV (0x000E) /* Real Time Clock Interrupt Vector */ +#define OFS_RTCTIM0 (0x0010) /* Real Time Clock Time 0 */ +#define OFS_RTCTIM0_L OFS_RTCTIM0 +#define OFS_RTCTIM0_H OFS_RTCTIM0+1 +#define OFS_RTCTIM1 (0x0012) /* Real Time Clock Time 1 */ +#define OFS_RTCTIM1_L OFS_RTCTIM1 +#define OFS_RTCTIM1_H OFS_RTCTIM1+1 +#define OFS_RTCDATE (0x0014) /* Real Time Clock Date */ +#define OFS_RTCDATE_L OFS_RTCDATE +#define OFS_RTCDATE_H OFS_RTCDATE+1 +#define OFS_RTCYEAR (0x0016) /* Real Time Clock Year */ +#define OFS_RTCYEAR_L OFS_RTCYEAR +#define OFS_RTCYEAR_H OFS_RTCYEAR+1 +#define OFS_RTCAMINHR (0x0018) /* Real Time Clock Alarm Min/Hour */ +#define OFS_RTCAMINHR_L OFS_RTCAMINHR +#define OFS_RTCAMINHR_H OFS_RTCAMINHR+1 +#define OFS_RTCADOWDAY (0x001A) /* Real Time Clock Alarm day of week/day */ +#define OFS_RTCADOWDAY_L OFS_RTCADOWDAY +#define OFS_RTCADOWDAY_H OFS_RTCADOWDAY+1 +#define OFS_BIN2BCD (0x001C) /* Real Time Binary-to-BCD conversion register */ +#define OFS_BCD2BIN (0x001E) /* Real Time BCD-to-binary conversion register */ +#define OFS_RTCSEC (0x0010) +#define OFS_RTCMIN (0x0011) +#define OFS_RTCHOUR (0x0012) +#define OFS_RTCDOW (0x0013) +#define OFS_RTCDAY (0x0014) +#define OFS_RTCMON (0x0015) +#define OFS_RTCAMIN (0x0018) +#define OFS_RTCAHOUR (0x0019) +#define OFS_RTCADOW (0x001A) +#define OFS_RTCADAY (0x001B) + +#define RTCSEC RTCTIM0_L +#define RTCMIN RTCTIM0_H +#define RTCHOUR RTCTIM1_L +#define RTCDOW RTCTIM1_H +#define RTCDAY RTCDATE_L +#define RTCMON RTCDATE_H +#define RTCYEARL RTCYEAR_L +#define RT0PS RTCPS_L +#define RT1PS RTCPS_H +#define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */ +#define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */ +#define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */ +#define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */ + +/* RTCCTL0 Control Bits */ +#define RTCOFIE (0x0080) /* RTC 32kHz cyrstal oscillator fault interrupt enable */ +#define RTCTEVIE (0x0040) /* RTC Time Event Interrupt Enable Flag */ +#define RTCAIE (0x0020) /* RTC Alarm Interrupt Enable Flag */ +#define RTCRDYIE (0x0010) /* RTC Ready Interrupt Enable Flag */ +#define RTCOFIFG (0x0008) /* RTC 32kHz cyrstal oscillator fault interrupt flag */ +#define RTCTEVIFG (0x0004) /* RTC Time Event Interrupt Flag */ +#define RTCAIFG (0x0002) /* RTC Alarm Interrupt Flag */ +#define RTCRDYIFG (0x0001) /* RTC Ready Interrupt Flag */ + +/* RTCCTL0 Control Bits */ +#define RTCOFIE_L (0x0080) /* RTC 32kHz cyrstal oscillator fault interrupt enable */ +#define RTCTEVIE_L (0x0040) /* RTC Time Event Interrupt Enable Flag */ +#define RTCAIE_L (0x0020) /* RTC Alarm Interrupt Enable Flag */ +#define RTCRDYIE_L (0x0010) /* RTC Ready Interrupt Enable Flag */ +#define RTCOFIFG_L (0x0008) /* RTC 32kHz cyrstal oscillator fault interrupt flag */ +#define RTCTEVIFG_L (0x0004) /* RTC Time Event Interrupt Flag */ +#define RTCAIFG_L (0x0002) /* RTC Alarm Interrupt Flag */ +#define RTCRDYIFG_L (0x0001) /* RTC Ready Interrupt Flag */ + +#define RTCKEY (0xA500) /* RTC Key for RTC write access */ +#define RTCKEY_H (0xA5) /* RTC Key for RTC write access (high word) */ + +/* RTCCTL13 Control Bits */ +#define RTCCALF1 (0x0200) /* RTC Calibration Frequency Bit 1 */ +#define RTCCALF0 (0x0100) /* RTC Calibration Frequency Bit 0 */ +#define RTCBCD (0x0080) /* RTC BCD 0:Binary / 1:BCD */ +#define RTCHOLD (0x0040) /* RTC Hold */ +#define RTCMODE (0x0020) /* RTC Mode 0:Counter / 1: Calendar */ +#define RTCRDY (0x0010) /* RTC Ready */ +#define RTCSSEL1 (0x0008) /* RTC Source Select 1 */ +#define RTCSSEL0 (0x0004) /* RTC Source Select 0 */ +#define RTCTEV1 (0x0002) /* RTC Time Event 1 */ +#define RTCTEV0 (0x0001) /* RTC Time Event 0 */ + +/* RTCCTL13 Control Bits */ +#define RTCBCD_L (0x0080) /* RTC BCD 0:Binary / 1:BCD */ +#define RTCHOLD_L (0x0040) /* RTC Hold */ +#define RTCMODE_L (0x0020) /* RTC Mode 0:Counter / 1: Calendar */ +#define RTCRDY_L (0x0010) /* RTC Ready */ +#define RTCSSEL1_L (0x0008) /* RTC Source Select 1 */ +#define RTCSSEL0_L (0x0004) /* RTC Source Select 0 */ +#define RTCTEV1_L (0x0002) /* RTC Time Event 1 */ +#define RTCTEV0_L (0x0001) /* RTC Time Event 0 */ + +/* RTCCTL13 Control Bits */ +#define RTCCALF1_H (0x0002) /* RTC Calibration Frequency Bit 1 */ +#define RTCCALF0_H (0x0001) /* RTC Calibration Frequency Bit 0 */ + +#define RTCSSEL_0 (0x0000) /* RTC Source Select ACLK */ +#define RTCSSEL_1 (0x0004) /* RTC Source Select SMCLK */ +#define RTCSSEL_2 (0x0008) /* RTC Source Select RT1PS */ +#define RTCSSEL_3 (0x000C) /* RTC Source Select RT1PS */ +#define RTCSSEL__ACLK (0x0000) /* RTC Source Select ACLK */ +#define RTCSSEL__SMCLK (0x0004) /* RTC Source Select SMCLK */ +#define RTCSSEL__RT1PS (0x0008) /* RTC Source Select RT1PS */ + +#define RTCTEV_0 (0x0000) /* RTC Time Event: 0 (Min. changed) */ +#define RTCTEV_1 (0x0001) /* RTC Time Event: 1 (Hour changed) */ +#define RTCTEV_2 (0x0002) /* RTC Time Event: 2 (12:00 changed) */ +#define RTCTEV_3 (0x0003) /* RTC Time Event: 3 (00:00 changed) */ +#define RTCTEV__MIN (0x0000) /* RTC Time Event: 0 (Min. changed) */ +#define RTCTEV__HOUR (0x0001) /* RTC Time Event: 1 (Hour changed) */ +#define RTCTEV__0000 (0x0002) /* RTC Time Event: 2 (00:00 changed) */ +#define RTCTEV__1200 (0x0003) /* RTC Time Event: 3 (12:00 changed) */ + +#define RTCCALF_0 (0x0000) /* RTC Calibration Frequency: No Output */ +#define RTCCALF_1 (0x0100) /* RTC Calibration Frequency: 512 Hz */ +#define RTCCALF_2 (0x0200) /* RTC Calibration Frequency: 256 Hz */ +#define RTCCALF_3 (0x0300) /* RTC Calibration Frequency: 1 Hz */ + +/* RTCOCAL Control Bits */ +#define RTCOCALS (0x8000) /* RTC Offset Calibration Sign */ +#define RTCOCAL7 (0x0080) /* RTC Offset Calibration Bit 7 */ +#define RTCOCAL6 (0x0040) /* RTC Offset Calibration Bit 6 */ +#define RTCOCAL5 (0x0020) /* RTC Offset Calibration Bit 5 */ +#define RTCOCAL4 (0x0010) /* RTC Offset Calibration Bit 4 */ +#define RTCOCAL3 (0x0008) /* RTC Offset Calibration Bit 3 */ +#define RTCOCAL2 (0x0004) /* RTC Offset Calibration Bit 2 */ +#define RTCOCAL1 (0x0002) /* RTC Offset Calibration Bit 1 */ +#define RTCOCAL0 (0x0001) /* RTC Offset Calibration Bit 0 */ + +/* RTCOCAL Control Bits */ +#define RTCOCAL7_L (0x0080) /* RTC Offset Calibration Bit 7 */ +#define RTCOCAL6_L (0x0040) /* RTC Offset Calibration Bit 6 */ +#define RTCOCAL5_L (0x0020) /* RTC Offset Calibration Bit 5 */ +#define RTCOCAL4_L (0x0010) /* RTC Offset Calibration Bit 4 */ +#define RTCOCAL3_L (0x0008) /* RTC Offset Calibration Bit 3 */ +#define RTCOCAL2_L (0x0004) /* RTC Offset Calibration Bit 2 */ +#define RTCOCAL1_L (0x0002) /* RTC Offset Calibration Bit 1 */ +#define RTCOCAL0_L (0x0001) /* RTC Offset Calibration Bit 0 */ + +/* RTCOCAL Control Bits */ +#define RTCOCALS_H (0x0080) /* RTC Offset Calibration Sign */ + +/* RTCTCMP Control Bits */ +#define RTCTCMPS (0x8000) /* RTC Temperature Compensation Sign */ +#define RTCTCRDY (0x4000) /* RTC Temperature compensation ready */ +#define RTCTCOK (0x2000) /* RTC Temperature compensation write OK */ +#define RTCTCMP7 (0x0080) /* RTC Temperature Compensation Bit 7 */ +#define RTCTCMP6 (0x0040) /* RTC Temperature Compensation Bit 6 */ +#define RTCTCMP5 (0x0020) /* RTC Temperature Compensation Bit 5 */ +#define RTCTCMP4 (0x0010) /* RTC Temperature Compensation Bit 4 */ +#define RTCTCMP3 (0x0008) /* RTC Temperature Compensation Bit 3 */ +#define RTCTCMP2 (0x0004) /* RTC Temperature Compensation Bit 2 */ +#define RTCTCMP1 (0x0002) /* RTC Temperature Compensation Bit 1 */ +#define RTCTCMP0 (0x0001) /* RTC Temperature Compensation Bit 0 */ + +/* RTCTCMP Control Bits */ +#define RTCTCMP7_L (0x0080) /* RTC Temperature Compensation Bit 7 */ +#define RTCTCMP6_L (0x0040) /* RTC Temperature Compensation Bit 6 */ +#define RTCTCMP5_L (0x0020) /* RTC Temperature Compensation Bit 5 */ +#define RTCTCMP4_L (0x0010) /* RTC Temperature Compensation Bit 4 */ +#define RTCTCMP3_L (0x0008) /* RTC Temperature Compensation Bit 3 */ +#define RTCTCMP2_L (0x0004) /* RTC Temperature Compensation Bit 2 */ +#define RTCTCMP1_L (0x0002) /* RTC Temperature Compensation Bit 1 */ +#define RTCTCMP0_L (0x0001) /* RTC Temperature Compensation Bit 0 */ + +/* RTCTCMP Control Bits */ +#define RTCTCMPS_H (0x0080) /* RTC Temperature Compensation Sign */ +#define RTCTCRDY_H (0x0040) /* RTC Temperature compensation ready */ +#define RTCTCOK_H (0x0020) /* RTC Temperature compensation write OK */ + +#define RTCAE (0x80) /* Real Time Clock Alarm enable */ + +/* RTCPS0CTL Control Bits */ +//#define Reserved (0x8000) +//#define Reserved (0x4000) +#define RT0PSDIV2 (0x2000) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */ +#define RT0PSDIV1 (0x1000) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */ +#define RT0PSDIV0 (0x0800) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */ +//#define Reserved (0x0400) +//#define Reserved (0x0200) +#define RT0PSHOLD (0x0100) /* RTC Prescale Timer 0 Hold */ +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) +#define RT0IP2 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */ +#define RT0IP1 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */ +#define RT0IP0 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */ +#define RT0PSIE (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */ +#define RT0PSIFG (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */ + +/* RTCPS0CTL Control Bits */ +//#define Reserved (0x8000) +//#define Reserved (0x4000) +//#define Reserved (0x0400) +//#define Reserved (0x0200) +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) +#define RT0IP2_L (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */ +#define RT0IP1_L (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */ +#define RT0IP0_L (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */ +#define RT0PSIE_L (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */ +#define RT0PSIFG_L (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */ + +/* RTCPS0CTL Control Bits */ +//#define Reserved (0x8000) +//#define Reserved (0x4000) +#define RT0PSDIV2_H (0x0020) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */ +#define RT0PSDIV1_H (0x0010) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */ +#define RT0PSDIV0_H (0x0008) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */ +//#define Reserved (0x0400) +//#define Reserved (0x0200) +#define RT0PSHOLD_H (0x0001) /* RTC Prescale Timer 0 Hold */ +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) + +#define RT0IP_0 (0x0000) /* RTC Prescale Timer 0 Interrupt Interval /2 */ +#define RT0IP_1 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval /4 */ +#define RT0IP_2 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval /8 */ +#define RT0IP_3 (0x000C) /* RTC Prescale Timer 0 Interrupt Interval /16 */ +#define RT0IP_4 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval /32 */ +#define RT0IP_5 (0x0014) /* RTC Prescale Timer 0 Interrupt Interval /64 */ +#define RT0IP_6 (0x0018) /* RTC Prescale Timer 0 Interrupt Interval /128 */ +#define RT0IP_7 (0x001C) /* RTC Prescale Timer 0 Interrupt Interval /256 */ + +/* RTCPS1CTL Control Bits */ +#define RT1SSEL1 (0x8000) /* RTC Prescale Timer 1 Source Select Bit 1 */ +#define RT1SSEL0 (0x4000) /* RTC Prescale Timer 1 Source Select Bit 0 */ +#define RT1PSDIV2 (0x2000) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */ +#define RT1PSDIV1 (0x1000) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */ +#define RT1PSDIV0 (0x0800) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */ +//#define Reserved (0x0400) +//#define Reserved (0x0200) +#define RT1PSHOLD (0x0100) /* RTC Prescale Timer 1 Hold */ +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) +#define RT1IP2 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */ +#define RT1IP1 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */ +#define RT1IP0 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */ +#define RT1PSIE (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */ +#define RT1PSIFG (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */ + +/* RTCPS1CTL Control Bits */ +//#define Reserved (0x0400) +//#define Reserved (0x0200) +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) +#define RT1IP2_L (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */ +#define RT1IP1_L (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */ +#define RT1IP0_L (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */ +#define RT1PSIE_L (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */ +#define RT1PSIFG_L (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */ + +/* RTCPS1CTL Control Bits */ +#define RT1SSEL1_H (0x0080) /* RTC Prescale Timer 1 Source Select Bit 1 */ +#define RT1SSEL0_H (0x0040) /* RTC Prescale Timer 1 Source Select Bit 0 */ +#define RT1PSDIV2_H (0x0020) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */ +#define RT1PSDIV1_H (0x0010) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */ +#define RT1PSDIV0_H (0x0008) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */ +//#define Reserved (0x0400) +//#define Reserved (0x0200) +#define RT1PSHOLD_H (0x0001) /* RTC Prescale Timer 1 Hold */ +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) + +#define RT1IP_0 (0x0000) /* RTC Prescale Timer 1 Interrupt Interval /2 */ +#define RT1IP_1 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval /4 */ +#define RT1IP_2 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval /8 */ +#define RT1IP_3 (0x000C) /* RTC Prescale Timer 1 Interrupt Interval /16 */ +#define RT1IP_4 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval /32 */ +#define RT1IP_5 (0x0014) /* RTC Prescale Timer 1 Interrupt Interval /64 */ +#define RT1IP_6 (0x0018) /* RTC Prescale Timer 1 Interrupt Interval /128 */ +#define RT1IP_7 (0x001C) /* RTC Prescale Timer 1 Interrupt Interval /256 */ + +/* RTC Definitions */ +#define RTCIV_NONE (0x0000) /* No Interrupt pending */ +#define RTCIV_RTCOFIFG (0x0002) /* RTC Osc fault: RTCOFIFG */ +#define RTCIV_RTCRDYIFG (0x0004) /* RTC ready: RTCRDYIFG */ +#define RTCIV_RTCTEVIFG (0x0006) /* RTC interval timer: RTCTEVIFG */ +#define RTCIV_RTCAIFG (0x0008) /* RTC user alarm: RTCAIFG */ +#define RTCIV_RT0PSIFG (0x000A) /* RTC prescaler 0: RT0PSIFG */ +#define RTCIV_RT1PSIFG (0x000C) /* RTC prescaler 1: RT1PSIFG */ + +/* Legacy Definitions */ +#define RTC_NONE (0x0000) /* No Interrupt pending */ +#define RTC_RTCOFIFG (0x0002) /* RTC Osc fault: RTCOFIFG */ +#define RTC_RTCRDYIFG (0x0004) /* RTC ready: RTCRDYIFG */ +#define RTC_RTCTEVIFG (0x0006) /* RTC interval timer: RTCTEVIFG */ +#define RTC_RTCAIFG (0x0008) /* RTC user alarm: RTCAIFG */ +#define RTC_RT0PSIFG (0x000A) /* RTC prescaler 0: RT0PSIFG */ +#define RTC_RT1PSIFG (0x000C) /* RTC prescaler 1: RT1PSIFG */ + +#endif +/************************************************************ +* Real Time Clock +************************************************************/ +#ifdef __MSP430_HAS_RTC_CE__ /* Definition to show that Module is available */ + +#define OFS_RTCCTL0 (0x0000) /* Real Timer Clock Control 0/Key */ +#define OFS_RTCCTL0_L OFS_RTCCTL0 +#define OFS_RTCCTL0_H OFS_RTCCTL0+1 +#define OFS_RTCCTL13 (0x0002) /* Real Timer Clock Control 1/3 */ +#define OFS_RTCCTL13_L OFS_RTCCTL13 +#define OFS_RTCCTL13_H OFS_RTCCTL13+1 +#define RTCCTL1 RTCCTL13_L +#define RTCCTL3 RTCCTL13_H +#define OFS_RTCOCAL (0x0004) /* Real Timer Clock Offset Calibartion */ +#define OFS_RTCOCAL_L OFS_RTCOCAL +#define OFS_RTCOCAL_H OFS_RTCOCAL+1 +#define OFS_RTCTCMP (0x0006) /* Real Timer Temperature Compensation */ +#define OFS_RTCTCMP_L OFS_RTCTCMP +#define OFS_RTCTCMP_H OFS_RTCTCMP+1 +#define OFS_RTCPS0CTL (0x0008) /* Real Timer Prescale Timer 0 Control */ +#define OFS_RTCPS0CTL_L OFS_RTCPS0CTL +#define OFS_RTCPS0CTL_H OFS_RTCPS0CTL+1 +#define OFS_RTCPS1CTL (0x000A) /* Real Timer Prescale Timer 1 Control */ +#define OFS_RTCPS1CTL_L OFS_RTCPS1CTL +#define OFS_RTCPS1CTL_H OFS_RTCPS1CTL+1 +#define OFS_RTCPS (0x000C) /* Real Timer Prescale Timer Control */ +#define OFS_RTCPS_L OFS_RTCPS +#define OFS_RTCPS_H OFS_RTCPS+1 +#define OFS_RTCIV (0x000E) /* Real Time Clock Interrupt Vector */ +#define OFS_RTCTIM0 (0x0010) /* Real Time Clock Time 0 */ +#define OFS_RTCTIM0_L OFS_RTCTIM0 +#define OFS_RTCTIM0_H OFS_RTCTIM0+1 +#define OFS_RTCTIM1 (0x0012) /* Real Time Clock Time 1 */ +#define OFS_RTCTIM1_L OFS_RTCTIM1 +#define OFS_RTCTIM1_H OFS_RTCTIM1+1 +#define OFS_RTCDATE (0x0014) /* Real Time Clock Date */ +#define OFS_RTCDATE_L OFS_RTCDATE +#define OFS_RTCDATE_H OFS_RTCDATE+1 +#define OFS_RTCYEAR (0x0016) /* Real Time Clock Year */ +#define OFS_RTCYEAR_L OFS_RTCYEAR +#define OFS_RTCYEAR_H OFS_RTCYEAR+1 +#define OFS_RTCAMINHR (0x0018) /* Real Time Clock Alarm Min/Hour */ +#define OFS_RTCAMINHR_L OFS_RTCAMINHR +#define OFS_RTCAMINHR_H OFS_RTCAMINHR+1 +#define OFS_RTCADOWDAY (0x001A) /* Real Time Clock Alarm day of week/day */ +#define OFS_RTCADOWDAY_L OFS_RTCADOWDAY +#define OFS_RTCADOWDAY_H OFS_RTCADOWDAY+1 +#define OFS_BIN2BCD (0x001C) /* Real Time Binary-to-BCD conversion register */ +#define OFS_BCD2BIN (0x001E) /* Real Time BCD-to-binary conversion register */ +#define OFS_RTCSEC (0x0010) +#define OFS_RTCMIN (0x0011) +#define OFS_RTCHOUR (0x0012) +#define OFS_RTCDOW (0x0013) +#define OFS_RTCDAY (0x0014) +#define OFS_RTCMON (0x0015) +#define OFS_RTCAMIN (0x0018) +#define OFS_RTCAHOUR (0x0019) +#define OFS_RTCADOW (0x001A) +#define OFS_RTCADAY (0x001B) + +#define OFS_RTCTCCTL0 (0x0020) /* Real-Time Clock Time Capture Control Register 0 */ +#define OFS_RTCTCCTL1 (0x0021) /* Real-Time Clock Time Capture Control Register 1 */ +#define OFS_RTCCAP0CTL (0x0022) /* Tamper Detect Pin 0 Control Register */ +#define OFS_RTCCAP1CTL (0x0023) /* Tamper Detect Pin 1 Control Register */ +#define OFS_RTCSECBAK0 (0x0030) /* Real-Time Clock Seconds Backup Register 0 */ +#define OFS_RTCMINBAK0 (0x0031) /* Real-Time Clock Minutes Backup Register 0 */ +#define OFS_RTCHOURBAK0 (0x0032) /* Real-Time Clock Hours Backup Register 0 */ +#define OFS_RTCDAYBAK0 (0x0033) /* Real-Time Clock Days Backup Register 0 */ +#define OFS_RTCMONBAK0 (0x0034) /* Real-Time Clock Months Backup Register 0 */ +#define OFS_RTCYEARBAK0 (0x0036) /* Real-Time Clock year Backup Register 0 */ +#define OFS_RTCSECBAK1 (0x0038) /* Real-Time Clock Seconds Backup Register 1 */ +#define OFS_RTCMINBAK1 (0x0039) /* Real-Time Clock Minutes Backup Register 1 */ +#define OFS_RTCHOURBAK1 (0x003A) /* Real-Time Clock Hours Backup Register 1 */ +#define OFS_RTCDAYBAK1 (0x003B) /* Real-Time Clock Days Backup Register 1 */ +#define OFS_RTCMONBAK1 (0x003C) /* Real-Time Clock Months Backup Register 1 */ +#define OFS_RTCYEARBAK1 (0x003E) /* Real-Time Clock Year Backup Register 1 */ + +#define RTCSEC RTCTIM0_L +#define RTCMIN RTCTIM0_H +#define RTCHOUR RTCTIM1_L +#define RTCDOW RTCTIM1_H +#define RTCDAY RTCDATE_L +#define RTCMON RTCDATE_H +#define RTCYEARL RTCYEAR_L +#define RT0PS RTCPS_L +#define RT1PS RTCPS_H +#define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */ +#define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */ +#define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */ +#define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */ + +/* RTCCTL0 Control Bits */ +#define RTCOFIE (0x0080) /* RTC 32kHz cyrstal oscillator fault interrupt enable */ +#define RTCTEVIE (0x0040) /* RTC Time Event Interrupt Enable Flag */ +#define RTCAIE (0x0020) /* RTC Alarm Interrupt Enable Flag */ +#define RTCRDYIE (0x0010) /* RTC Ready Interrupt Enable Flag */ +#define RTCOFIFG (0x0008) /* RTC 32kHz cyrstal oscillator fault interrupt flag */ +#define RTCTEVIFG (0x0004) /* RTC Time Event Interrupt Flag */ +#define RTCAIFG (0x0002) /* RTC Alarm Interrupt Flag */ +#define RTCRDYIFG (0x0001) /* RTC Ready Interrupt Flag */ + +/* RTCCTL0 Control Bits */ +#define RTCOFIE_L (0x0080) /* RTC 32kHz cyrstal oscillator fault interrupt enable */ +#define RTCTEVIE_L (0x0040) /* RTC Time Event Interrupt Enable Flag */ +#define RTCAIE_L (0x0020) /* RTC Alarm Interrupt Enable Flag */ +#define RTCRDYIE_L (0x0010) /* RTC Ready Interrupt Enable Flag */ +#define RTCOFIFG_L (0x0008) /* RTC 32kHz cyrstal oscillator fault interrupt flag */ +#define RTCTEVIFG_L (0x0004) /* RTC Time Event Interrupt Flag */ +#define RTCAIFG_L (0x0002) /* RTC Alarm Interrupt Flag */ +#define RTCRDYIFG_L (0x0001) /* RTC Ready Interrupt Flag */ + +#define RTCKEY (0xA500) /* RTC Key for RTC write access */ +#define RTCKEY_H (0xA5) /* RTC Key for RTC write access (high word) */ + +/* RTCCTL13 Control Bits */ +#define RTCCALF1 (0x0200) /* RTC Calibration Frequency Bit 1 */ +#define RTCCALF0 (0x0100) /* RTC Calibration Frequency Bit 0 */ +#define RTCBCD (0x0080) /* RTC BCD 0:Binary / 1:BCD */ +#define RTCHOLD (0x0040) /* RTC Hold */ +#define RTCMODE (0x0020) /* RTC Mode 0:Counter / 1: Calendar */ +#define RTCRDY (0x0010) /* RTC Ready */ +#define RTCSSEL1 (0x0008) /* RTC Source Select 1 */ +#define RTCSSEL0 (0x0004) /* RTC Source Select 0 */ +#define RTCTEV1 (0x0002) /* RTC Time Event 1 */ +#define RTCTEV0 (0x0001) /* RTC Time Event 0 */ + +/* RTCCTL13 Control Bits */ +#define RTCBCD_L (0x0080) /* RTC BCD 0:Binary / 1:BCD */ +#define RTCHOLD_L (0x0040) /* RTC Hold */ +#define RTCMODE_L (0x0020) /* RTC Mode 0:Counter / 1: Calendar */ +#define RTCRDY_L (0x0010) /* RTC Ready */ +#define RTCSSEL1_L (0x0008) /* RTC Source Select 1 */ +#define RTCSSEL0_L (0x0004) /* RTC Source Select 0 */ +#define RTCTEV1_L (0x0002) /* RTC Time Event 1 */ +#define RTCTEV0_L (0x0001) /* RTC Time Event 0 */ + +/* RTCCTL13 Control Bits */ +#define RTCCALF1_H (0x0002) /* RTC Calibration Frequency Bit 1 */ +#define RTCCALF0_H (0x0001) /* RTC Calibration Frequency Bit 0 */ + +#define RTCSSEL_0 (0x0000) /* RTC Source Select ACLK */ +#define RTCSSEL_1 (0x0004) /* RTC Source Select SMCLK */ +#define RTCSSEL_2 (0x0008) /* RTC Source Select RT1PS */ +#define RTCSSEL_3 (0x000C) /* RTC Source Select RT1PS */ +#define RTCSSEL__ACLK (0x0000) /* RTC Source Select ACLK */ +#define RTCSSEL__SMCLK (0x0004) /* RTC Source Select SMCLK */ +#define RTCSSEL__RT1PS (0x0008) /* RTC Source Select RT1PS */ + +#define RTCTEV_0 (0x0000) /* RTC Time Event: 0 (Min. changed) */ +#define RTCTEV_1 (0x0001) /* RTC Time Event: 1 (Hour changed) */ +#define RTCTEV_2 (0x0002) /* RTC Time Event: 2 (12:00 changed) */ +#define RTCTEV_3 (0x0003) /* RTC Time Event: 3 (00:00 changed) */ +#define RTCTEV__MIN (0x0000) /* RTC Time Event: 0 (Min. changed) */ +#define RTCTEV__HOUR (0x0001) /* RTC Time Event: 1 (Hour changed) */ +#define RTCTEV__0000 (0x0002) /* RTC Time Event: 2 (00:00 changed) */ +#define RTCTEV__1200 (0x0003) /* RTC Time Event: 3 (12:00 changed) */ + +#define RTCCALF_0 (0x0000) /* RTC Calibration Frequency: No Output */ +#define RTCCALF_1 (0x0100) /* RTC Calibration Frequency: 512 Hz */ +#define RTCCALF_2 (0x0200) /* RTC Calibration Frequency: 256 Hz */ +#define RTCCALF_3 (0x0300) /* RTC Calibration Frequency: 1 Hz */ + +/* RTCOCAL Control Bits */ +#define RTCOCALS (0x8000) /* RTC Offset Calibration Sign */ +#define RTCOCAL7 (0x0080) /* RTC Offset Calibration Bit 7 */ +#define RTCOCAL6 (0x0040) /* RTC Offset Calibration Bit 6 */ +#define RTCOCAL5 (0x0020) /* RTC Offset Calibration Bit 5 */ +#define RTCOCAL4 (0x0010) /* RTC Offset Calibration Bit 4 */ +#define RTCOCAL3 (0x0008) /* RTC Offset Calibration Bit 3 */ +#define RTCOCAL2 (0x0004) /* RTC Offset Calibration Bit 2 */ +#define RTCOCAL1 (0x0002) /* RTC Offset Calibration Bit 1 */ +#define RTCOCAL0 (0x0001) /* RTC Offset Calibration Bit 0 */ + +/* RTCOCAL Control Bits */ +#define RTCOCAL7_L (0x0080) /* RTC Offset Calibration Bit 7 */ +#define RTCOCAL6_L (0x0040) /* RTC Offset Calibration Bit 6 */ +#define RTCOCAL5_L (0x0020) /* RTC Offset Calibration Bit 5 */ +#define RTCOCAL4_L (0x0010) /* RTC Offset Calibration Bit 4 */ +#define RTCOCAL3_L (0x0008) /* RTC Offset Calibration Bit 3 */ +#define RTCOCAL2_L (0x0004) /* RTC Offset Calibration Bit 2 */ +#define RTCOCAL1_L (0x0002) /* RTC Offset Calibration Bit 1 */ +#define RTCOCAL0_L (0x0001) /* RTC Offset Calibration Bit 0 */ + +/* RTCOCAL Control Bits */ +#define RTCOCALS_H (0x0080) /* RTC Offset Calibration Sign */ + +/* RTCTCMP Control Bits */ +#define RTCTCMPS (0x8000) /* RTC Temperature Compensation Sign */ +#define RTCTCRDY (0x4000) /* RTC Temperature compensation ready */ +#define RTCTCOK (0x2000) /* RTC Temperature compensation write OK */ +#define RTCTCMP7 (0x0080) /* RTC Temperature Compensation Bit 7 */ +#define RTCTCMP6 (0x0040) /* RTC Temperature Compensation Bit 6 */ +#define RTCTCMP5 (0x0020) /* RTC Temperature Compensation Bit 5 */ +#define RTCTCMP4 (0x0010) /* RTC Temperature Compensation Bit 4 */ +#define RTCTCMP3 (0x0008) /* RTC Temperature Compensation Bit 3 */ +#define RTCTCMP2 (0x0004) /* RTC Temperature Compensation Bit 2 */ +#define RTCTCMP1 (0x0002) /* RTC Temperature Compensation Bit 1 */ +#define RTCTCMP0 (0x0001) /* RTC Temperature Compensation Bit 0 */ + +/* RTCTCMP Control Bits */ +#define RTCTCMP7_L (0x0080) /* RTC Temperature Compensation Bit 7 */ +#define RTCTCMP6_L (0x0040) /* RTC Temperature Compensation Bit 6 */ +#define RTCTCMP5_L (0x0020) /* RTC Temperature Compensation Bit 5 */ +#define RTCTCMP4_L (0x0010) /* RTC Temperature Compensation Bit 4 */ +#define RTCTCMP3_L (0x0008) /* RTC Temperature Compensation Bit 3 */ +#define RTCTCMP2_L (0x0004) /* RTC Temperature Compensation Bit 2 */ +#define RTCTCMP1_L (0x0002) /* RTC Temperature Compensation Bit 1 */ +#define RTCTCMP0_L (0x0001) /* RTC Temperature Compensation Bit 0 */ + +/* RTCTCMP Control Bits */ +#define RTCTCMPS_H (0x0080) /* RTC Temperature Compensation Sign */ +#define RTCTCRDY_H (0x0040) /* RTC Temperature compensation ready */ +#define RTCTCOK_H (0x0020) /* RTC Temperature compensation write OK */ + +#define RTCAE (0x80) /* Real Time Clock Alarm enable */ + +/* RTCPS0CTL Control Bits */ +//#define Reserved (0x8000) +//#define Reserved (0x4000) +#define RT0PSDIV2 (0x2000) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */ +#define RT0PSDIV1 (0x1000) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */ +#define RT0PSDIV0 (0x0800) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */ +//#define Reserved (0x0400) +//#define Reserved (0x0200) +#define RT0PSHOLD (0x0100) /* RTC Prescale Timer 0 Hold */ +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) +#define RT0IP2 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */ +#define RT0IP1 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */ +#define RT0IP0 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */ +#define RT0PSIE (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */ +#define RT0PSIFG (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */ + +/* RTCPS0CTL Control Bits */ +//#define Reserved (0x8000) +//#define Reserved (0x4000) +//#define Reserved (0x0400) +//#define Reserved (0x0200) +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) +#define RT0IP2_L (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */ +#define RT0IP1_L (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */ +#define RT0IP0_L (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */ +#define RT0PSIE_L (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */ +#define RT0PSIFG_L (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */ + +/* RTCPS0CTL Control Bits */ +//#define Reserved (0x8000) +//#define Reserved (0x4000) +#define RT0PSDIV2_H (0x0020) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */ +#define RT0PSDIV1_H (0x0010) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */ +#define RT0PSDIV0_H (0x0008) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */ +//#define Reserved (0x0400) +//#define Reserved (0x0200) +#define RT0PSHOLD_H (0x0001) /* RTC Prescale Timer 0 Hold */ +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) + +#define RT0IP_0 (0x0000) /* RTC Prescale Timer 0 Interrupt Interval /2 */ +#define RT0IP_1 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval /4 */ +#define RT0IP_2 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval /8 */ +#define RT0IP_3 (0x000C) /* RTC Prescale Timer 0 Interrupt Interval /16 */ +#define RT0IP_4 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval /32 */ +#define RT0IP_5 (0x0014) /* RTC Prescale Timer 0 Interrupt Interval /64 */ +#define RT0IP_6 (0x0018) /* RTC Prescale Timer 0 Interrupt Interval /128 */ +#define RT0IP_7 (0x001C) /* RTC Prescale Timer 0 Interrupt Interval /256 */ + +/* RTCPS1CTL Control Bits */ +#define RT1SSEL1 (0x8000) /* RTC Prescale Timer 1 Source Select Bit 1 */ +#define RT1SSEL0 (0x4000) /* RTC Prescale Timer 1 Source Select Bit 0 */ +#define RT1PSDIV2 (0x2000) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */ +#define RT1PSDIV1 (0x1000) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */ +#define RT1PSDIV0 (0x0800) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */ +//#define Reserved (0x0400) +//#define Reserved (0x0200) +#define RT1PSHOLD (0x0100) /* RTC Prescale Timer 1 Hold */ +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) +#define RT1IP2 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */ +#define RT1IP1 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */ +#define RT1IP0 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */ +#define RT1PSIE (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */ +#define RT1PSIFG (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */ + +/* RTCPS1CTL Control Bits */ +//#define Reserved (0x0400) +//#define Reserved (0x0200) +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) +#define RT1IP2_L (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */ +#define RT1IP1_L (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */ +#define RT1IP0_L (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */ +#define RT1PSIE_L (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */ +#define RT1PSIFG_L (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */ + +/* RTCPS1CTL Control Bits */ +#define RT1SSEL1_H (0x0080) /* RTC Prescale Timer 1 Source Select Bit 1 */ +#define RT1SSEL0_H (0x0040) /* RTC Prescale Timer 1 Source Select Bit 0 */ +#define RT1PSDIV2_H (0x0020) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */ +#define RT1PSDIV1_H (0x0010) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */ +#define RT1PSDIV0_H (0x0008) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */ +//#define Reserved (0x0400) +//#define Reserved (0x0200) +#define RT1PSHOLD_H (0x0001) /* RTC Prescale Timer 1 Hold */ +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) + +#define RT1IP_0 (0x0000) /* RTC Prescale Timer 1 Interrupt Interval /2 */ +#define RT1IP_1 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval /4 */ +#define RT1IP_2 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval /8 */ +#define RT1IP_3 (0x000C) /* RTC Prescale Timer 1 Interrupt Interval /16 */ +#define RT1IP_4 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval /32 */ +#define RT1IP_5 (0x0014) /* RTC Prescale Timer 1 Interrupt Interval /64 */ +#define RT1IP_6 (0x0018) /* RTC Prescale Timer 1 Interrupt Interval /128 */ +#define RT1IP_7 (0x001C) /* RTC Prescale Timer 1 Interrupt Interval /256 */ + +/* RTCTCCTL0 Control Bits */ +#define TCEN (0x0001) /* RTC Enable for RTC Tamper Detection with Time Stamp */ +#define AUX3RST (0x0002) /* RTC Indication of power cycle on AUXVCC3 */ + +/* RTCTCCTL1 Control Bits */ +#define RTCCAPIFG (0x0001) /* RTC Tamper Event Interrupt Flag */ +#define RTCCAPIE (0x0002) /* RTC Tamper Event Interrupt Enable */ + +/* RTCCAPxCTL Control Bits */ +#define CAPEV (0x0001) /* RTC Tamper Event Flag */ +#define CAPES (0x0004) /* RTC Event Edge Select */ +#define RTCREN (0x0008) /* RTC RTCCAPx pin pullup/pulldown resistor enable */ +#define RTCCAPIN (0x0010) /* RTC RTCCAPx input */ +#define RTCCAPDIR (0x0020) /* RTC RTCCAPx Pin direction */ +#define RTCCAPOUT (0x0040) /* RTC RTCCAPx Output */ + +/* RTCIV Definitions */ +#define RTCIV_NONE (0x0000) /* No Interrupt pending */ +#define RTCIV_RTCOFIFG (0x0002) /* RTC Osc fault: RTCOFIFG */ +#define RTCIV_RTCCAPIFG (0x0004) /* RTC RTC Tamper Event: RTCCAPIFG */ +#define RTCIV_RTCRDYIFG (0x0006) /* RTC ready: RTCRDYIFG */ +#define RTCIV_RTCTEVIFG (0x0008) /* RTC interval timer: RTCTEVIFG */ +#define RTCIV_RTCAIFG (0x000A) /* RTC user alarm: RTCAIFG */ +#define RTCIV_RT0PSIFG (0x000C) /* RTC prescaler 0: RT0PSIFG */ +#define RTCIV_RT1PSIFG (0x000E) /* RTC prescaler 1: RT1PSIFG */ + +/* Legacy RTCIV Definitions */ +#define RTC_NONE (0x0000) /* No Interrupt pending */ +#define RTC_RTCOFIFG (0x0002) /* RTC Osc fault: RTCOFIFG */ +#define RTC_RTCRDYIFG (0x0006) /* RTC ready: RTCRDYIFG */ +#define RTC_RTCTEVIFG (0x0008) /* RTC interval timer: RTCTEVIFG */ +#define RTC_RTCAIFG (0x000A) /* RTC user alarm: RTCAIFG */ +#define RTC_RT0PSIFG (0x000C) /* RTC prescaler 0: RT0PSIFG */ +#define RTC_RT1PSIFG (0x000E) /* RTC prescaler 1: RT1PSIFG */ + +#endif +/************************************************************ +* SD24_B - Sigma Delta 24 Bit +************************************************************/ +#ifdef __MSP430_HAS_SD24_B__ /* Definition to show that Module is available */ + +#define OFS_SD24BCTL0 (0x0000) /* SD24B Control Register 0 */ +#define OFS_SD24BCTL0_L OFS_SD24BCTL0 +#define OFS_SD24BCTL0_H OFS_SD24BCTL0+1 +#define OFS_SD24BCTL1 (0x0002) /* SD24B Control Register 1 */ +#define OFS_SD24BCTL1_L OFS_SD24BCTL1 +#define OFS_SD24BCTL1_H OFS_SD24BCTL1+1 +#define OFS_SD24BTRGCTL (0x0004) /* SD24B Trigger Control Register */ +#define OFS_SD24BTRGCTL_L OFS_SD24BTRGCTL +#define OFS_SD24BTRGCTL_H OFS_SD24BTRGCTL+1 +#define OFS_SD24BTRGOSR (0x0006) /* SD24B Trigger OSR Control Register */ +#define OFS_SD24BTRGOSR_L OFS_SD24BTRGOSR +#define OFS_SD24BTRGOSR_H OFS_SD24BTRGOSR+1 +#define OFS_SD24BTRGPRE (0x0008) /* SD24B Trigger Preload Register */ +#define OFS_SD24BTRGPRE_L OFS_SD24BTRGPRE +#define OFS_SD24BTRGPRE_H OFS_SD24BTRGPRE+1 +#define OFS_SD24BIFG (0x000A) /* SD24B Interrupt Flag Register */ +#define OFS_SD24BIFG_L OFS_SD24BIFG +#define OFS_SD24BIFG_H OFS_SD24BIFG+1 +#define OFS_SD24BIE (0x000C) /* SD24B Interrupt Enable Register */ +#define OFS_SD24BIE_L OFS_SD24BIE +#define OFS_SD24BIE_H OFS_SD24BIE+1 +#define OFS_SD24BIV (0x000E) /* SD24B Interrupt Vector Register */ +#define OFS_SD24BIV_L OFS_SD24BIV +#define OFS_SD24BIV_H OFS_SD24BIV+1 + +#define OFS_SD24BCCTL0 (0x0010) /* SD24B Channel 0 Control Register */ +#define OFS_SD24BCCTL0_L OFS_SD24BCCTL0 +#define OFS_SD24BCCTL0_H OFS_SD24BCCTL0+1 +#define OFS_SD24BINCTL0 (0x0012) /* SD24B Channel 0 Input Control Register */ +#define OFS_SD24BINCTL0_L OFS_SD24BINCTL0 +#define OFS_SD24BINCTL0_H OFS_SD24BINCTL0+1 +#define OFS_SD24BOSR0 (0x0014) /* SD24B Channel 0 OSR Control Register */ +#define OFS_SD24BOSR0_L OFS_SD24BOSR0 +#define OFS_SD24BOSR0_H OFS_SD24BOSR0+1 +#define OFS_SD24BPRE0 (0x0016) /* SD24B Channel 0 Preload Register */ +#define OFS_SD24BPRE0_L OFS_SD24BPRE0 +#define OFS_SD24BPRE0_H OFS_SD24BPRE0+1 + +#define OFS_SD24BMEML0 (0x0050) /* SD24B Channel 0 Conversion Memory Low word */ +#define OFS_SD24BMEML0_L OFS_SD24BMEML0 +#define OFS_SD24BMEML0_H OFS_SD24BMEML0+1 +#define OFS_SD24BMEMH0 (0x0052) /* SD24B Channel 0 Conversion Memory High Word */ +#define OFS_SD24BMEMH0_L OFS_SD24BMEMH0 +#define OFS_SD24BMEMH0_H OFS_SD24BMEMH0+1 + +/* SD24BCTL0 */ +#define SD24OV32 (0x0002) /* SD24B Overflow Control */ +#define SD24REFS (0x0004) /* SD24B Reference Select */ +#define SD24SSEL0 (0x0010) /* SD24B Clock Source Select 0 */ +#define SD24SSEL1 (0x0020) /* SD24B Clock Source Select 1 */ +#define SD24M4 (0x0040) /* SD24B Modulator clock to Manchester decoder clock ratio */ +#define SD24CLKOS (0x0080) /* SD24B Clock Output Select */ +#define SD24PDIV0 (0x0100) /* SD24B Frequency pre-scaler Bit 0 */ +#define SD24PDIV1 (0x0200) /* SD24B Frequency pre-scaler Bit 1 */ +#define SD24PDIV2 (0x0400) /* SD24B Frequency pre-scaler Bit 2 */ +#define SD24DIV0 (0x0800) /* SD24B Frequency Divider Bit 0 */ +#define SD24DIV1 (0x1000) /* SD24B Frequency Divider Bit 1 */ +#define SD24DIV2 (0x2000) /* SD24B Frequency Divider Bit 2 */ +#define SD24DIV3 (0x4000) /* SD24B Frequency Divider Bit 3 */ +#define SD24DIV4 (0x8000) /* SD24B Frequency Divider Bit 4 */ + +#define SD24OV32_L (0x0002) /* SD24B Overflow Control */ +#define SD24REFS_L (0x0004) /* SD24B Reference Select */ +#define SD24SSEL0_L (0x0010) /* SD24B Clock Source Select 0 */ +#define SD24SSEL1_L (0x0020) /* SD24B Clock Source Select 1 */ +#define SD24M4_L (0x0040) /* SD24B Modulator clock to Manchester decoder clock ratio */ +#define SD24CLKOS_L (0x0080) /* SD24B Clock Output Select */ + +#define SD24PDIV0_H (0x0001) /* SD24B Frequency pre-scaler Bit 0 */ +#define SD24PDIV1_H (0x0002) /* SD24B Frequency pre-scaler Bit 1 */ +#define SD24PDIV2_H (0x0004) /* SD24B Frequency pre-scaler Bit 2 */ +#define SD24DIV0_H (0x0008) /* SD24B Frequency Divider Bit 0 */ +#define SD24DIV1_H (0x0010) /* SD24B Frequency Divider Bit 1 */ +#define SD24DIV2_H (0x0020) /* SD24B Frequency Divider Bit 2 */ +#define SD24DIV3_H (0x0040) /* SD24B Frequency Divider Bit 3 */ +#define SD24DIV4_H (0x0080) /* SD24B Frequency Divider Bit 4 */ + +#define SD24SSEL_0 (0x0000) /* SD24B Clock Source Select MCLK */ +#define SD24SSEL_1 (0x0010) /* SD24B Clock Source Select SMCLK */ +#define SD24SSEL_2 (0x0020) /* SD24B Clock Source Select ACLK */ +#define SD24SSEL_3 (0x0030) /* SD24B Clock Source Select TACLK */ +#define SD24SSEL__MCLK (0x0000) /* SD24B Clock Source Select MCLK */ +#define SD24SSEL__SMCLK (0x0010) /* SD24B Clock Source Select SMCLK */ +#define SD24SSEL__ACLK (0x0020) /* SD24B Clock Source Select ACLK */ +#define SD24SSEL__SD24CLK (0x0030) /* SD24B Clock Source Select SD24CLK */ + +#define SD24PDIV_0 (0x0000) /* SD24B Frequency pre-scaler /1 */ +#define SD24PDIV_1 (0x0100) /* SD24B Frequency pre-scaler /2 */ +#define SD24PDIV_2 (0x0200) /* SD24B Frequency pre-scaler /4 */ +#define SD24PDIV_3 (0x0300) /* SD24B Frequency pre-scaler /8 */ +#define SD24PDIV_4 (0x0400) /* SD24B Frequency pre-scaler /16 */ +#define SD24PDIV_5 (0x0500) /* SD24B Frequency pre-scaler /32 */ +#define SD24PDIV_6 (0x0600) /* SD24B Frequency pre-scaler /64 */ +#define SD24PDIV_7 (0x0700) /* SD24B Frequency pre-scaler /128 */ + +/* SD24BCTL1 */ +#define SD24GRP0SC (0x0001) /* SD24B Group 0 Start Conversion */ +#define SD24GRP1SC (0x0002) /* SD24B Group 1 Start Conversion */ +#define SD24GRP2SC (0x0004) /* SD24B Group 2 Start Conversion */ +#define SD24GRP3SC (0x0008) /* SD24B Group 3 Start Conversion */ +#define SD24DMA0 (0x0100) /* SD24B DMA Trigger Select Bit 0 */ +#define SD24DMA1 (0x0200) /* SD24B DMA Trigger Select Bit 1 */ +#define SD24DMA2 (0x0400) /* SD24B DMA Trigger Select Bit 2 */ +#define SD24DMA3 (0x0800) /* SD24B DMA Trigger Select Bit 3 */ + +#define SD24GRP0SC_L (0x0001) /* SD24B Group 0 Start Conversion */ +#define SD24GRP1SC_L (0x0002) /* SD24B Group 1 Start Conversion */ +#define SD24GRP2SC_L (0x0004) /* SD24B Group 2 Start Conversion */ +#define SD24GRP3SC_L (0x0008) /* SD24B Group 3 Start Conversion */ + +#define SD24DMA0_H (0x0001) /* SD24B DMA Trigger Select Bit 0 */ +#define SD24DMA1_H (0x0002) /* SD24B DMA Trigger Select Bit 1 */ +#define SD24DMA2_H (0x0004) /* SD24B DMA Trigger Select Bit 2 */ +#define SD24DMA3_H (0x0008) /* SD24B DMA Trigger Select Bit 3 */ + +#define SD24DMA_0 (0x0000) /* SD24B DMA Trigger: 0 */ +#define SD24DMA_1 (0x0100) /* SD24B DMA Trigger: 1 */ +#define SD24DMA_2 (0x0200) /* SD24B DMA Trigger: 2 */ +#define SD24DMA_3 (0x0300) /* SD24B DMA Trigger: 3 */ +#define SD24DMA_4 (0x0400) /* SD24B DMA Trigger: 4 */ +#define SD24DMA_5 (0x0500) /* SD24B DMA Trigger: 5 */ +#define SD24DMA_6 (0x0600) /* SD24B DMA Trigger: 6 */ +#define SD24DMA_7 (0x0700) /* SD24B DMA Trigger: 7 */ +#define SD24DMA_8 (0x0800) /* SD24B DMA Trigger: 8 */ + +/* SD24BTRGCTL */ +#define SD24SC (0x0001) /* SD24B Start Conversion */ +#define SD24SCS0 (0x0002) /* SD24B Start Conversion Select Bit 0 */ +#define SD24SCS1 (0x0004) /* SD24B Start Conversion Select Bit 1 */ +#define SD24SCS2 (0x0008) /* SD24B Start Conversion Select Bit 2 */ +#define SD24SNGL (0x0100) /* SD24B Single Trigger Mode */ +#define SD24TRGIFG (0x0400) /* SD24B Trigger Interrupt Flag */ +#define SD24TRGIE (0x0800) /* SD24B Trigger Interrupt Enable */ + +#define SD24SC_L (0x0001) /* SD24B Start Conversion */ +#define SD24SCS0_L (0x0002) /* SD24B Start Conversion Select Bit 0 */ +#define SD24SCS1_L (0x0004) /* SD24B Start Conversion Select Bit 1 */ +#define SD24SCS2_L (0x0008) /* SD24B Start Conversion Select Bit 2 */ + +#define SD24SNGL_H (0x0001) /* SD24B Single Trigger Mode */ +#define SD24TRGIFG_H (0x0004) /* SD24B Trigger Interrupt Flag */ +#define SD24TRGIE_H (0x0008) /* SD24B Trigger Interrupt Enable */ + +#define SD24SCS_0 (0x0000) /* SD24B Start Conversion Select: 0 */ +#define SD24SCS_1 (0x0002) /* SD24B Start Conversion Select: 1 */ +#define SD24SCS_2 (0x0004) /* SD24B Start Conversion Select: 2 */ +#define SD24SCS_3 (0x0006) /* SD24B Start Conversion Select: 3 */ +#define SD24SCS_4 (0x0008) /* SD24B Start Conversion Select: 4 */ +#define SD24SCS_5 (0x000A) /* SD24B Start Conversion Select: 5 */ +#define SD24SCS_6 (0x000C) /* SD24B Start Conversion Select: 6 */ +#define SD24SCS_7 (0x000E) /* SD24B Start Conversion Select: 7 */ +#define SD24SCS__SD24SC (0x0000) /* SD24B Start Conversion Select: SD24SC */ +#define SD24SCS__EXT1 (0x0002) /* SD24B Start Conversion Select: EXT1 */ +#define SD24SCS__EXT2 (0x0004) /* SD24B Start Conversion Select: EXT2 */ +#define SD24SCS__EXT3 (0x0006) /* SD24B Start Conversion Select: EXT3 */ +#define SD24SCS__GROUP0 (0x0008) /* SD24B Start Conversion Select: GROUP0 */ +#define SD24SCS__GROUP1 (0x000A) /* SD24B Start Conversion Select: GROUP1 */ +#define SD24SCS__GROUP2 (0x000C) /* SD24B Start Conversion Select: GROUP2 */ +#define SD24SCS__GROUP3 (0x000E) /* SD24B Start Conversion Select: GROUP3 */ + +/* SD24BIFG */ +#define SD24IFG0 (0x0001) /* SD24B Channel 0 Interrupt Flag */ +#define SD24OVIFG0 (0x0100) /* SD24B Channel 0 Overflow Interrupt Flag */ + +#define SD24IFG0_L (0x0001) /* SD24B Channel 0 Interrupt Flag */ + +#define SD24OVIFG0_H (0x0001) /* SD24B Channel 0 Overflow Interrupt Flag */ + +/* SD24BIE */ +#define SD24IE0 (0x0001) /* SD24B Channel 0 Interrupt Enable */ +#define SD24OVIE0 (0x0100) /* SD24B Channel 0 Overflow Interrupt Enable */ + +#define SD24IE0_L (0x0001) /* SD24B Channel 0 Interrupt Enable */ + +#define SD24OVIE0_H (0x0001) /* SD24B Channel 0 Overflow Interrupt Enable */ + +/* SD24BIV Definitions */ +#define SD24BIV_NONE (0x0000) /* No Interrupt pending */ +#define SD24BIV_SD24OVIFG (0x0002) /* SD24OVIFG */ +#define SD24BIV_SD24TRGIFG (0x0004) /* SD24TRGIFG */ +#define SD24BIV_SD24IFG0 (0x0006) /* SD24IFG0 */ + +/* SD24BCCTLx */ +#define SD24DF0 (0x0010) /* SD24B Data Format Bit: 0 */ +#define SD24DF1 (0x0020) /* SD24B Data Format Bit: 1 */ +#define SD24ALGN (0x0040) /* SD24B Data Alignment */ +#define SD24CAL (0x0200) /* SD24B Calibration */ +#define SD24DFS0 (0x0400) /* SD24B Digital Filter Bit: 0 */ +#define SD24DFS1 (0x0800) /* SD24B Digital Filter Bit: 1 */ +#define SD24DI (0x1000) /* SD24B Digital Bitstream Input */ +#define SD24MC0 (0x2000) /* SD24B Manchaster Encoding Bit: 0 */ +#define SD24MC1 (0x4000) /* SD24B Manchaster Encoding Bit: 1 */ + +#define SD24DF0_L (0x0010) /* SD24B Data Format Bit: 0 */ +#define SD24DF1_L (0x0020) /* SD24B Data Format Bit: 1 */ +#define SD24ALGN_L (0x0040) /* SD24B Data Alignment */ + +#define SD24CAL_H (0x0002) /* SD24B Calibration */ +#define SD24DFS0_H (0x0004) /* SD24B Digital Filter Bit: 0 */ +#define SD24DFS1_H (0x0008) /* SD24B Digital Filter Bit: 1 */ +#define SD24DI_H (0x0010) /* SD24B Digital Bitstream Input */ +#define SD24MC0_H (0x0020) /* SD24B Manchaster Encoding Bit: 0 */ +#define SD24MC1_H (0x0040) /* SD24B Manchaster Encoding Bit: 1 */ + +#define SD24DF_0 (0x0000) /* SD24B Data Format: Offset Binary */ +#define SD24DF_1 (0x0010) /* SD24B Data Format: 2's complement */ + +#define SD24DFS_0 (0x0000) /* SD24B Digital Filter 0 */ +#define SD24DFS_1 (0x0400) /* SD24B Digital Filter 1 */ +#define SD24DFS_2 (0x0800) /* SD24B Digital Filter 2 */ +#define SD24DFS_3 (0x0C00) /* SD24B Digital Filter 3 */ + +#define SD24MC_0 (0x0000) /* SD24B Manchaster Encoding 0 */ +#define SD24MC_1 (0x2000) /* SD24B Manchaster Encoding 1 */ +#define SD24MC_2 (0x4000) /* SD24B Manchaster Encoding 2 */ +#define SD24MC_3 (0x6000) /* SD24B Manchaster Encoding 3 */ + +/* SD24BINCTLx */ +#define SD24GAIN0 (0x0008) /* SD24B Input Pre-Amplifier Gain Select 0 */ +#define SD24GAIN1 (0x0010) /* SD24B Input Pre-Amplifier Gain Select 1 */ +#define SD24GAIN2 (0x0020) /* SD24B Input Pre-Amplifier Gain Select 2 */ +#define SD24INTDLY0 (0x0040) /* SD24B Interrupt Delay after 1.Conversion 0 */ +#define SD24INTDLY1 (0x0080) /* SD24B Interrupt Delay after 1.Conversion 1 */ + +#define SD24GAIN0_L (0x0008) /* SD24B Input Pre-Amplifier Gain Select 0 */ +#define SD24GAIN1_L (0x0010) /* SD24B Input Pre-Amplifier Gain Select 1 */ +#define SD24GAIN2_L (0x0020) /* SD24B Input Pre-Amplifier Gain Select 2 */ +#define SD24INTDLY0_L (0x0040) /* SD24B Interrupt Delay after 1.Conversion 0 */ +#define SD24INTDLY1_L (0x0080) /* SD24B Interrupt Delay after 1.Conversion 1 */ + +#define SD24GAIN_1 (0x0000) /* SD24B Input Pre-Amplifier Gain Select *1 */ +#define SD24GAIN_2 (0x0008) /* SD24B Input Pre-Amplifier Gain Select *2 */ +#define SD24GAIN_4 (0x0010) /* SD24B Input Pre-Amplifier Gain Select *4 */ +#define SD24GAIN_8 (0x0018) /* SD24B Input Pre-Amplifier Gain Select *8 */ +#define SD24GAIN_16 (0x0020) /* SD24B Input Pre-Amplifier Gain Select *16 */ +#define SD24GAIN_32 (0x0028) /* SD24B Input Pre-Amplifier Gain Select *32 */ +#define SD24GAIN_64 (0x0030) /* SD24B Input Pre-Amplifier Gain Select *64 */ +#define SD24GAIN_128 (0x0038) /* SD24B Input Pre-Amplifier Gain Select *128 */ + +#define SD24INTDLY_0 (0x0000) /* SD24B Interrupt Delay: Int. after 4.Conversion */ +#define SD24INTDLY_1 (0x0040) /* SD24B Interrupt Delay: Int. after 3.Conversion */ +#define SD24INTDLY_2 (0x0080) /* SD24B Interrupt Delay: Int. after 2.Conversion */ +#define SD24INTDLY_3 (0x00C0) /* SD24B Interrupt Delay: Int. after 1.Conversion */ + +/* SD24BOSRx */ +#define OSR0 (0x0001) /* SD24B Oversampling Rate Bit: 0 */ +#define OSR1 (0x0002) /* SD24B Oversampling Rate Bit: 1 */ +#define OSR2 (0x0004) /* SD24B Oversampling Rate Bit: 2 */ +#define OSR3 (0x0008) /* SD24B Oversampling Rate Bit: 3 */ +#define OSR4 (0x0010) /* SD24B Oversampling Rate Bit: 4 */ +#define OSR5 (0x0020) /* SD24B Oversampling Rate Bit: 5 */ +#define OSR6 (0x0040) /* SD24B Oversampling Rate Bit: 6 */ +#define OSR7 (0x0080) /* SD24B Oversampling Rate Bit: 7 */ +#define OSR8 (0x0100) /* SD24B Oversampling Rate Bit: 8 */ +#define OSR9 (0x0200) /* SD24B Oversampling Rate Bit: 9 */ +#define OSR10 (0x0400) /* SD24B Oversampling Rate Bit: 10 */ + +#define OSR0_L (0x0001) /* SD24B Oversampling Rate Bit: 0 */ +#define OSR1_L (0x0002) /* SD24B Oversampling Rate Bit: 1 */ +#define OSR2_L (0x0004) /* SD24B Oversampling Rate Bit: 2 */ +#define OSR3_L (0x0008) /* SD24B Oversampling Rate Bit: 3 */ +#define OSR4_L (0x0010) /* SD24B Oversampling Rate Bit: 4 */ +#define OSR5_L (0x0020) /* SD24B Oversampling Rate Bit: 5 */ +#define OSR6_L (0x0040) /* SD24B Oversampling Rate Bit: 6 */ +#define OSR7_L (0x0080) /* SD24B Oversampling Rate Bit: 7 */ + +#define OSR8_H (0x0001) /* SD24B Oversampling Rate Bit: 8 */ +#define OSR9_H (0x0002) /* SD24B Oversampling Rate Bit: 9 */ +#define OSR10_H (0x0004) /* SD24B Oversampling Rate Bit: 10 */ + +/* SD24BTRGOSR */ + +#define OSR__32 (32-1) /* SD24B Oversampling Rate: 32 */ +#define OSR__64 (64-1) /* SD24B Oversampling Rate: 64 */ +#define OSR__128 (128-1) /* SD24B Oversampling Rate: 128 */ +#define OSR__256 (256-1) /* SD24B Oversampling Rate: 256 */ +#define OSR__512 (512-1) /* SD24B Oversampling Rate: 512 */ +#define OSR__1024 (1024-1) /* SD24B Oversampling Rate: 1024 */ + + +#endif +/************************************************************ +* SFR - Special Function Register Module +************************************************************/ +#ifdef __MSP430_HAS_SFR__ /* Definition to show that Module is available */ + +#define OFS_SFRIE1 (0x0000) /* Interrupt Enable 1 */ +#define OFS_SFRIE1_L OFS_SFRIE1 +#define OFS_SFRIE1_H OFS_SFRIE1+1 + +/* SFRIE1 Control Bits */ +#define WDTIE (0x0001) /* WDT Interrupt Enable */ +#define OFIE (0x0002) /* Osc Fault Enable */ +//#define Reserved (0x0004) +#define VMAIE (0x0008) /* Vacant Memory Interrupt Enable */ +#define NMIIE (0x0010) /* NMI Interrupt Enable */ +#ifndef ACCVIE +#define ACCVIE (0x0020) /* Flash Access Violation Interrupt Enable */ +#endif +#define JMBINIE (0x0040) /* JTAG Mail Box input Interrupt Enable */ +#define JMBOUTIE (0x0080) /* JTAG Mail Box output Interrupt Enable */ + +#define WDTIE_L (0x0001) /* WDT Interrupt Enable */ +#define OFIE_L (0x0002) /* Osc Fault Enable */ +//#define Reserved (0x0004) +#define VMAIE_L (0x0008) /* Vacant Memory Interrupt Enable */ +#define NMIIE_L (0x0010) /* NMI Interrupt Enable */ +#ifndef ACCVIE +#define ACCVIE_L (0x0020) /* Flash Access Violation Interrupt Enable */ +#endif +#define JMBINIE_L (0x0040) /* JTAG Mail Box input Interrupt Enable */ +#define JMBOUTIE_L (0x0080) /* JTAG Mail Box output Interrupt Enable */ + +#define OFS_SFRIFG1 (0x0002) /* Interrupt Flag 1 */ +#define OFS_SFRIFG1_L OFS_SFRIFG1 +#define OFS_SFRIFG1_H OFS_SFRIFG1+1 +/* SFRIFG1 Control Bits */ +#define WDTIFG (0x0001) /* WDT Interrupt Flag */ +#define OFIFG (0x0002) /* Osc Fault Flag */ +//#define Reserved (0x0004) +#define VMAIFG (0x0008) /* Vacant Memory Interrupt Flag */ +#define NMIIFG (0x0010) /* NMI Interrupt Flag */ +//#define Reserved (0x0020) +#define JMBINIFG (0x0040) /* JTAG Mail Box input Interrupt Flag */ +#define JMBOUTIFG (0x0080) /* JTAG Mail Box output Interrupt Flag */ + +#define WDTIFG_L (0x0001) /* WDT Interrupt Flag */ +#define OFIFG_L (0x0002) /* Osc Fault Flag */ +//#define Reserved (0x0004) +#define VMAIFG_L (0x0008) /* Vacant Memory Interrupt Flag */ +#define NMIIFG_L (0x0010) /* NMI Interrupt Flag */ +//#define Reserved (0x0020) +#define JMBINIFG_L (0x0040) /* JTAG Mail Box input Interrupt Flag */ +#define JMBOUTIFG_L (0x0080) /* JTAG Mail Box output Interrupt Flag */ + +#define OFS_SFRRPCR (0x0004) /* RESET Pin Control Register */ +#define OFS_SFRRPCR_L OFS_SFRRPCR +#define OFS_SFRRPCR_H OFS_SFRRPCR+1 +/* SFRRPCR Control Bits */ +#define SYSNMI (0x0001) /* NMI select */ +#define SYSNMIIES (0x0002) /* NMI edge select */ +#define SYSRSTUP (0x0004) /* RESET Pin pull down/up select */ +#define SYSRSTRE (0x0008) /* RESET Pin Resistor enable */ + +#define SYSNMI_L (0x0001) /* NMI select */ +#define SYSNMIIES_L (0x0002) /* NMI edge select */ +#define SYSRSTUP_L (0x0004) /* RESET Pin pull down/up select */ +#define SYSRSTRE_L (0x0008) /* RESET Pin Resistor enable */ + +#endif +/************************************************************ +* SYS - System Module +************************************************************/ +#ifdef __MSP430_HAS_SYS__ /* Definition to show that Module is available */ + +#define OFS_SYSCTL (0x0000) /* System control */ +#define OFS_SYSCTL_L OFS_SYSCTL +#define OFS_SYSCTL_H OFS_SYSCTL+1 +#define OFS_SYSBSLC (0x0002) /* Boot strap configuration area */ +#define OFS_SYSBSLC_L OFS_SYSBSLC +#define OFS_SYSBSLC_H OFS_SYSBSLC+1 +#define OFS_SYSJMBC (0x0006) /* JTAG mailbox control */ +#define OFS_SYSJMBC_L OFS_SYSJMBC +#define OFS_SYSJMBC_H OFS_SYSJMBC+1 +#define OFS_SYSJMBI0 (0x0008) /* JTAG mailbox input 0 */ +#define OFS_SYSJMBI0_L OFS_SYSJMBI0 +#define OFS_SYSJMBI0_H OFS_SYSJMBI0+1 +#define OFS_SYSJMBI1 (0x000A) /* JTAG mailbox input 1 */ +#define OFS_SYSJMBI1_L OFS_SYSJMBI1 +#define OFS_SYSJMBI1_H OFS_SYSJMBI1+1 +#define OFS_SYSJMBO0 (0x000C) /* JTAG mailbox output 0 */ +#define OFS_SYSJMBO0_L OFS_SYSJMBO0 +#define OFS_SYSJMBO0_H OFS_SYSJMBO0+1 +#define OFS_SYSJMBO1 (0x000E) /* JTAG mailbox output 1 */ +#define OFS_SYSJMBO1_L OFS_SYSJMBO1 +#define OFS_SYSJMBO1_H OFS_SYSJMBO1+1 + +#define OFS_SYSBERRIV (0x0018) /* Bus Error vector generator */ +#define OFS_SYSBERRIV_L OFS_SYSBERRIV +#define OFS_SYSBERRIV_H OFS_SYSBERRIV+1 +#define OFS_SYSUNIV (0x001A) /* User NMI vector generator */ +#define OFS_SYSUNIV_L OFS_SYSUNIV +#define OFS_SYSUNIV_H OFS_SYSUNIV+1 +#define OFS_SYSSNIV (0x001C) /* System NMI vector generator */ +#define OFS_SYSSNIV_L OFS_SYSSNIV +#define OFS_SYSSNIV_H OFS_SYSSNIV+1 +#define OFS_SYSRSTIV (0x001E) /* Reset vector generator */ +#define OFS_SYSRSTIV_L OFS_SYSRSTIV +#define OFS_SYSRSTIV_H OFS_SYSRSTIV+1 + +/* SYSCTL Control Bits */ +#define SYSRIVECT (0x0001) /* SYS - RAM based interrupt vectors */ +//#define RESERVED (0x0002) /* SYS - Reserved */ +#define SYSPMMPE (0x0004) /* SYS - PMM access protect */ +//#define RESERVED (0x0008) /* SYS - Reserved */ +#define SYSBSLIND (0x0010) /* SYS - TCK/RST indication detected */ +#define SYSJTAGPIN (0x0020) /* SYS - Dedicated JTAG pins enabled */ +//#define RESERVED (0x0040) /* SYS - Reserved */ +//#define RESERVED (0x0080) /* SYS - Reserved */ +//#define RESERVED (0x0100) /* SYS - Reserved */ +//#define RESERVED (0x0200) /* SYS - Reserved */ +//#define RESERVED (0x0400) /* SYS - Reserved */ +//#define RESERVED (0x0800) /* SYS - Reserved */ +//#define RESERVED (0x1000) /* SYS - Reserved */ +//#define RESERVED (0x2000) /* SYS - Reserved */ +//#define RESERVED (0x4000) /* SYS - Reserved */ +//#define RESERVED (0x8000) /* SYS - Reserved */ + +/* SYSCTL Control Bits */ +#define SYSRIVECT_L (0x0001) /* SYS - RAM based interrupt vectors */ +//#define RESERVED (0x0002) /* SYS - Reserved */ +#define SYSPMMPE_L (0x0004) /* SYS - PMM access protect */ +//#define RESERVED (0x0008) /* SYS - Reserved */ +#define SYSBSLIND_L (0x0010) /* SYS - TCK/RST indication detected */ +#define SYSJTAGPIN_L (0x0020) /* SYS - Dedicated JTAG pins enabled */ +//#define RESERVED (0x0040) /* SYS - Reserved */ +//#define RESERVED (0x0080) /* SYS - Reserved */ +//#define RESERVED (0x0100) /* SYS - Reserved */ +//#define RESERVED (0x0200) /* SYS - Reserved */ +//#define RESERVED (0x0400) /* SYS - Reserved */ +//#define RESERVED (0x0800) /* SYS - Reserved */ +//#define RESERVED (0x1000) /* SYS - Reserved */ +//#define RESERVED (0x2000) /* SYS - Reserved */ +//#define RESERVED (0x4000) /* SYS - Reserved */ +//#define RESERVED (0x8000) /* SYS - Reserved */ + +/* SYSBSLC Control Bits */ +#define SYSBSLSIZE0 (0x0001) /* SYS - BSL Protection Size 0 */ +#define SYSBSLSIZE1 (0x0002) /* SYS - BSL Protection Size 1 */ +#define SYSBSLR (0x0004) /* SYS - RAM assigned to BSL */ +//#define RESERVED (0x0008) /* SYS - Reserved */ +//#define RESERVED (0x0010) /* SYS - Reserved */ +//#define RESERVED (0x0020) /* SYS - Reserved */ +//#define RESERVED (0x0040) /* SYS - Reserved */ +//#define RESERVED (0x0080) /* SYS - Reserved */ +//#define RESERVED (0x0100) /* SYS - Reserved */ +//#define RESERVED (0x0200) /* SYS - Reserved */ +//#define RESERVED (0x0400) /* SYS - Reserved */ +//#define RESERVED (0x0800) /* SYS - Reserved */ +//#define RESERVED (0x1000) /* SYS - Reserved */ +//#define RESERVED (0x2000) /* SYS - Reserved */ +#define SYSBSLOFF (0x4000) /* SYS - BSL Memory disabled */ +#define SYSBSLPE (0x8000) /* SYS - BSL Memory protection enabled */ + +/* SYSBSLC Control Bits */ +#define SYSBSLSIZE0_L (0x0001) /* SYS - BSL Protection Size 0 */ +#define SYSBSLSIZE1_L (0x0002) /* SYS - BSL Protection Size 1 */ +#define SYSBSLR_L (0x0004) /* SYS - RAM assigned to BSL */ +//#define RESERVED (0x0008) /* SYS - Reserved */ +//#define RESERVED (0x0010) /* SYS - Reserved */ +//#define RESERVED (0x0020) /* SYS - Reserved */ +//#define RESERVED (0x0040) /* SYS - Reserved */ +//#define RESERVED (0x0080) /* SYS - Reserved */ +//#define RESERVED (0x0100) /* SYS - Reserved */ +//#define RESERVED (0x0200) /* SYS - Reserved */ +//#define RESERVED (0x0400) /* SYS - Reserved */ +//#define RESERVED (0x0800) /* SYS - Reserved */ +//#define RESERVED (0x1000) /* SYS - Reserved */ +//#define RESERVED (0x2000) /* SYS - Reserved */ + +/* SYSBSLC Control Bits */ +//#define RESERVED (0x0008) /* SYS - Reserved */ +//#define RESERVED (0x0010) /* SYS - Reserved */ +//#define RESERVED (0x0020) /* SYS - Reserved */ +//#define RESERVED (0x0040) /* SYS - Reserved */ +//#define RESERVED (0x0080) /* SYS - Reserved */ +//#define RESERVED (0x0100) /* SYS - Reserved */ +//#define RESERVED (0x0200) /* SYS - Reserved */ +//#define RESERVED (0x0400) /* SYS - Reserved */ +//#define RESERVED (0x0800) /* SYS - Reserved */ +//#define RESERVED (0x1000) /* SYS - Reserved */ +//#define RESERVED (0x2000) /* SYS - Reserved */ +#define SYSBSLOFF_H (0x0040) /* SYS - BSL Memory disabled */ +#define SYSBSLPE_H (0x0080) /* SYS - BSL Memory protection enabled */ + +/* SYSJMBC Control Bits */ +#define JMBIN0FG (0x0001) /* SYS - Incoming JTAG Mailbox 0 Flag */ +#define JMBIN1FG (0x0002) /* SYS - Incoming JTAG Mailbox 1 Flag */ +#define JMBOUT0FG (0x0004) /* SYS - Outgoing JTAG Mailbox 0 Flag */ +#define JMBOUT1FG (0x0008) /* SYS - Outgoing JTAG Mailbox 1 Flag */ +#define JMBMODE (0x0010) /* SYS - JMB 16/32 Bit Mode */ +//#define RESERVED (0x0020) /* SYS - Reserved */ +#define JMBCLR0OFF (0x0040) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */ +#define JMBCLR1OFF (0x0080) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */ +//#define RESERVED (0x0100) /* SYS - Reserved */ +//#define RESERVED (0x0200) /* SYS - Reserved */ +//#define RESERVED (0x0400) /* SYS - Reserved */ +//#define RESERVED (0x0800) /* SYS - Reserved */ +//#define RESERVED (0x1000) /* SYS - Reserved */ +//#define RESERVED (0x2000) /* SYS - Reserved */ +//#define RESERVED (0x4000) /* SYS - Reserved */ +//#define RESERVED (0x8000) /* SYS - Reserved */ + +/* SYSJMBC Control Bits */ +#define JMBIN0FG_L (0x0001) /* SYS - Incoming JTAG Mailbox 0 Flag */ +#define JMBIN1FG_L (0x0002) /* SYS - Incoming JTAG Mailbox 1 Flag */ +#define JMBOUT0FG_L (0x0004) /* SYS - Outgoing JTAG Mailbox 0 Flag */ +#define JMBOUT1FG_L (0x0008) /* SYS - Outgoing JTAG Mailbox 1 Flag */ +#define JMBMODE_L (0x0010) /* SYS - JMB 16/32 Bit Mode */ +//#define RESERVED (0x0020) /* SYS - Reserved */ +#define JMBCLR0OFF_L (0x0040) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */ +#define JMBCLR1OFF_L (0x0080) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */ +//#define RESERVED (0x0100) /* SYS - Reserved */ +//#define RESERVED (0x0200) /* SYS - Reserved */ +//#define RESERVED (0x0400) /* SYS - Reserved */ +//#define RESERVED (0x0800) /* SYS - Reserved */ +//#define RESERVED (0x1000) /* SYS - Reserved */ +//#define RESERVED (0x2000) /* SYS - Reserved */ +//#define RESERVED (0x4000) /* SYS - Reserved */ +//#define RESERVED (0x8000) /* SYS - Reserved */ + + +#endif +/************************************************************ +* Timerx_A7 +************************************************************/ +#ifdef __MSP430_HAS_TxA7__ /* Definition to show that Module is available */ + +#define OFS_TAxCTL (0x0000) /* Timerx_A7 Control */ +#define OFS_TAxCCTL0 (0x0002) /* Timerx_A7 Capture/Compare Control 0 */ +#define OFS_TAxCCTL1 (0x0004) /* Timerx_A7 Capture/Compare Control 1 */ +#define OFS_TAxCCTL2 (0x0006) /* Timerx_A7 Capture/Compare Control 2 */ +#define OFS_TAxCCTL3 (0x0008) /* Timerx_A7 Capture/Compare Control 3 */ +#define OFS_TAxCCTL4 (0x000A) /* Timerx_A7 Capture/Compare Control 4 */ +#define OFS_TAxCCTL5 (0x000C) /* Timerx_A7 Capture/Compare Control 5 */ +#define OFS_TAxCCTL6 (0x000E) /* Timerx_A7 Capture/Compare Control 6 */ +#define OFS_TAxR (0x0010) /* Timerx_A7 */ +#define OFS_TAxCCR0 (0x0012) /* Timerx_A7 Capture/Compare 0 */ +#define OFS_TAxCCR1 (0x0014) /* Timerx_A7 Capture/Compare 1 */ +#define OFS_TAxCCR2 (0x0016) /* Timerx_A7 Capture/Compare 2 */ +#define OFS_TAxCCR3 (0x0018) /* Timerx_A7 Capture/Compare 3 */ +#define OFS_TAxCCR4 (0x001A) /* Timerx_A7 Capture/Compare 4 */ +#define OFS_TAxCCR5 (0x001C) /* Timerx_A7 Capture/Compare 5 */ +#define OFS_TAxCCR6 (0x001E) /* Timerx_A7 Capture/Compare 6 */ +#define OFS_TAxIV (0x002E) /* Timerx_A7 Interrupt Vector Word */ +#define OFS_TAxEX0 (0x0020) /* Timerx_A7 Expansion Register 0 */ + +/* Bits are already defined within the Timer0_Ax */ + +/* TAxIV Definitions */ +#define TAxIV_NONE (0x0000) /* No Interrupt pending */ +#define TAxIV_TACCR1 (0x0002) /* TAxCCR1_CCIFG */ +#define TAxIV_TACCR2 (0x0004) /* TAxCCR2_CCIFG */ +#define TAxIV_TACCR3 (0x0006) /* TAxCCR3_CCIFG */ +#define TAxIV_TACCR4 (0x0008) /* TAxCCR4_CCIFG */ +#define TAxIV_TACCR5 (0x000A) /* TAxCCR5_CCIFG */ +#define TAxIV_TACCR6 (0x000C) /* TAxCCR6_CCIFG */ +#define TAxIV_TAIFG (0x000E) /* TAxIFG */ + +/* Legacy Defines */ +#define TAxIV_TAxCCR1 (0x0002) /* TAxCCR1_CCIFG */ +#define TAxIV_TAxCCR2 (0x0004) /* TAxCCR2_CCIFG */ +#define TAxIV_TAxCCR3 (0x0006) /* TAxCCR3_CCIFG */ +#define TAxIV_TAxCCR4 (0x0008) /* TAxCCR4_CCIFG */ +#define TAxIV_TAxCCR5 (0x000A) /* TAxCCR5_CCIFG */ +#define TAxIV_TAxCCR6 (0x000C) /* TAxCCR6_CCIFG */ +#define TAxIV_TAxIFG (0x000E) /* TAxIFG */ + +/* TAxCTL Control Bits */ +#define TASSEL1 (0x0200) /* Timer A clock source select 1 */ +#define TASSEL0 (0x0100) /* Timer A clock source select 0 */ +#define ID1 (0x0080) /* Timer A clock input divider 1 */ +#define ID0 (0x0040) /* Timer A clock input divider 0 */ +#define MC1 (0x0020) /* Timer A mode control 1 */ +#define MC0 (0x0010) /* Timer A mode control 0 */ +#define TACLR (0x0004) /* Timer A counter clear */ +#define TAIE (0x0002) /* Timer A counter interrupt enable */ +#define TAIFG (0x0001) /* Timer A counter interrupt flag */ + +#define MC_0 (0*0x10u) /* Timer A mode control: 0 - Stop */ +#define MC_1 (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */ +#define MC_2 (2*0x10u) /* Timer A mode control: 2 - Continuous up */ +#define MC_3 (3*0x10u) /* Timer A mode control: 3 - Up/Down */ +#define ID_0 (0*0x40u) /* Timer A input divider: 0 - /1 */ +#define ID_1 (1*0x40u) /* Timer A input divider: 1 - /2 */ +#define ID_2 (2*0x40u) /* Timer A input divider: 2 - /4 */ +#define ID_3 (3*0x40u) /* Timer A input divider: 3 - /8 */ +#define TASSEL_0 (0*0x100u) /* Timer A clock source select: 0 - TACLK */ +#define TASSEL_1 (1*0x100u) /* Timer A clock source select: 1 - ACLK */ +#define TASSEL_2 (2*0x100u) /* Timer A clock source select: 2 - SMCLK */ +#define TASSEL_3 (3*0x100u) /* Timer A clock source select: 3 - INCLK */ +#define MC__STOP (0*0x10u) /* Timer A mode control: 0 - Stop */ +#define MC__UP (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */ +#define MC__CONTINUOUS (2*0x10u) /* Timer A mode control: 2 - Continuous up */ +#define MC__CONTINOUS (2*0x10u) /* Legacy define */ +#define MC__UPDOWN (3*0x10u) /* Timer A mode control: 3 - Up/Down */ +#define ID__1 (0*0x40u) /* Timer A input divider: 0 - /1 */ +#define ID__2 (1*0x40u) /* Timer A input divider: 1 - /2 */ +#define ID__4 (2*0x40u) /* Timer A input divider: 2 - /4 */ +#define ID__8 (3*0x40u) /* Timer A input divider: 3 - /8 */ +#define TASSEL__TACLK (0*0x100u) /* Timer A clock source select: 0 - TACLK */ +#define TASSEL__ACLK (1*0x100u) /* Timer A clock source select: 1 - ACLK */ +#define TASSEL__SMCLK (2*0x100u) /* Timer A clock source select: 2 - SMCLK */ +#define TASSEL__INCLK (3*0x100u) /* Timer A clock source select: 3 - INCLK */ + +/* TAxCCTLx Control Bits */ +#define CM1 (0x8000) /* Capture mode 1 */ +#define CM0 (0x4000) /* Capture mode 0 */ +#define CCIS1 (0x2000) /* Capture input select 1 */ +#define CCIS0 (0x1000) /* Capture input select 0 */ +#define SCS (0x0800) /* Capture sychronize */ +#define SCCI (0x0400) /* Latched capture signal (read) */ +#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */ +#define OUTMOD2 (0x0080) /* Output mode 2 */ +#define OUTMOD1 (0x0040) /* Output mode 1 */ +#define OUTMOD0 (0x0020) /* Output mode 0 */ +#define CCIE (0x0010) /* Capture/compare interrupt enable */ +#define CCI (0x0008) /* Capture input signal (read) */ +#define OUT (0x0004) /* PWM Output signal if output mode 0 */ +#define COV (0x0002) /* Capture/compare overflow flag */ +#define CCIFG (0x0001) /* Capture/compare interrupt flag */ + +#define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */ +#define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */ +#define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */ +#define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */ +#define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */ +#define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */ +#define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */ +#define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */ +#define CCIS_0 (0*0x1000u) /* Capture input select: 0 - CCIxA */ +#define CCIS_1 (1*0x1000u) /* Capture input select: 1 - CCIxB */ +#define CCIS_2 (2*0x1000u) /* Capture input select: 2 - GND */ +#define CCIS_3 (3*0x1000u) /* Capture input select: 3 - Vcc */ +#define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */ +#define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */ +#define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */ +#define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */ + +/* TAxEX0 Control Bits */ +#define TAIDEX0 (0x0001) /* Timer A Input divider expansion Bit: 0 */ +#define TAIDEX1 (0x0002) /* Timer A Input divider expansion Bit: 1 */ +#define TAIDEX2 (0x0004) /* Timer A Input divider expansion Bit: 2 */ + +#define TAIDEX_0 (0*0x0001u) /* Timer A Input divider expansion : /1 */ +#define TAIDEX_1 (1*0x0001u) /* Timer A Input divider expansion : /2 */ +#define TAIDEX_2 (2*0x0001u) /* Timer A Input divider expansion : /3 */ +#define TAIDEX_3 (3*0x0001u) /* Timer A Input divider expansion : /4 */ +#define TAIDEX_4 (4*0x0001u) /* Timer A Input divider expansion : /5 */ +#define TAIDEX_5 (5*0x0001u) /* Timer A Input divider expansion : /6 */ +#define TAIDEX_6 (6*0x0001u) /* Timer A Input divider expansion : /7 */ +#define TAIDEX_7 (7*0x0001u) /* Timer A Input divider expansion : /8 */ + +#endif +/************************************************************ +* Timerx_B7 +************************************************************/ +#ifdef __MSP430_HAS_TxB7__ /* Definition to show that Module is available */ + +#define OFS_TBxCTL (0x0000) /* Timerx_B7 Control */ +#define OFS_TBxCCTL0 (0x0002) /* Timerx_B7 Capture/Compare Control 0 */ +#define OFS_TBxCCTL1 (0x0004) /* Timerx_B7 Capture/Compare Control 1 */ +#define OFS_TBxCCTL2 (0x0006) /* Timerx_B7 Capture/Compare Control 2 */ +#define OFS_TBxCCTL3 (0x0008) /* Timerx_B7 Capture/Compare Control 3 */ +#define OFS_TBxCCTL4 (0x000A) /* Timerx_B7 Capture/Compare Control 4 */ +#define OFS_TBxCCTL5 (0x000C) /* Timerx_B7 Capture/Compare Control 5 */ +#define OFS_TBxCCTL6 (0x000E) /* Timerx_B7 Capture/Compare Control 6 */ +#define OFS_TBxR (0x0010) /* Timerx_B7 */ +#define OFS_TBxCCR0 (0x0012) /* Timerx_B7 Capture/Compare 0 */ +#define OFS_TBxCCR1 (0x0014) /* Timerx_B7 Capture/Compare 1 */ +#define OFS_TBxCCR2 (0x0016) /* Timerx_B7 Capture/Compare 2 */ +#define OFS_TBxCCR3 (0x0018) /* Timerx_B7 Capture/Compare 3 */ +#define OFS_TBxCCR4 (0x001A) /* Timerx_B7 Capture/Compare 4 */ +#define OFS_TBxCCR5 (0x001C) /* Timerx_B7 Capture/Compare 5 */ +#define OFS_TBxCCR6 (0x001E) /* Timerx_B7 Capture/Compare 6 */ +#define OFS_TBxIV (0x002E) /* Timerx_B7 Interrupt Vector Word */ +#define OFS_TBxEX0 (0x0020) /* Timerx_B7 Expansion Register 0 */ + +/* Bits are already defined within the Timer0_Ax */ + +/* TBxIV Definitions */ +#define TBxIV_NONE (0x0000) /* No Interrupt pending */ +#define TBxIV_TBCCR1 (0x0002) /* TBxCCR1_CCIFG */ +#define TBxIV_TBCCR2 (0x0004) /* TBxCCR2_CCIFG */ +#define TBxIV_TBCCR3 (0x0006) /* TBxCCR3_CCIFG */ +#define TBxIV_TBCCR4 (0x0008) /* TBxCCR4_CCIFG */ +#define TBxIV_TBCCR5 (0x000A) /* TBxCCR5_CCIFG */ +#define TBxIV_TBCCR6 (0x000C) /* TBxCCR6_CCIFG */ +#define TBxIV_TBIFG (0x000E) /* TBxIFG */ + +/* Legacy Defines */ +#define TBxIV_TBxCCR1 (0x0002) /* TBxCCR1_CCIFG */ +#define TBxIV_TBxCCR2 (0x0004) /* TBxCCR2_CCIFG */ +#define TBxIV_TBxCCR3 (0x0006) /* TBxCCR3_CCIFG */ +#define TBxIV_TBxCCR4 (0x0008) /* TBxCCR4_CCIFG */ +#define TBxIV_TBxCCR5 (0x000A) /* TBxCCR5_CCIFG */ +#define TBxIV_TBxCCR6 (0x000C) /* TBxCCR6_CCIFG */ +#define TBxIV_TBxIFG (0x000E) /* TBxIFG */ + +/* TBxCTL Control Bits */ +#define TBCLGRP1 (0x4000) /* Timer_B7 Compare latch load group 1 */ +#define TBCLGRP0 (0x2000) /* Timer_B7 Compare latch load group 0 */ +#define CNTL1 (0x1000) /* Counter lenght 1 */ +#define CNTL0 (0x0800) /* Counter lenght 0 */ +#define TBSSEL1 (0x0200) /* Clock source 1 */ +#define TBSSEL0 (0x0100) /* Clock source 0 */ +#define TBCLR (0x0004) /* Timer_B7 counter clear */ +#define TBIE (0x0002) /* Timer_B7 interrupt enable */ +#define TBIFG (0x0001) /* Timer_B7 interrupt flag */ + +#define SHR1 (0x4000) /* Timer_B7 Compare latch load group 1 */ +#define SHR0 (0x2000) /* Timer_B7 Compare latch load group 0 */ + +#define TBSSEL_0 (0*0x0100u) /* Clock Source: TBCLK */ +#define TBSSEL_1 (1*0x0100u) /* Clock Source: ACLK */ +#define TBSSEL_2 (2*0x0100u) /* Clock Source: SMCLK */ +#define TBSSEL_3 (3*0x0100u) /* Clock Source: INCLK */ +#define CNTL_0 (0*0x0800u) /* Counter lenght: 16 bit */ +#define CNTL_1 (1*0x0800u) /* Counter lenght: 12 bit */ +#define CNTL_2 (2*0x0800u) /* Counter lenght: 10 bit */ +#define CNTL_3 (3*0x0800u) /* Counter lenght: 8 bit */ +#define SHR_0 (0*0x2000u) /* Timer_B7 Group: 0 - individually */ +#define SHR_1 (1*0x2000u) /* Timer_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */ +#define SHR_2 (2*0x2000u) /* Timer_B7 Group: 2 - 2 groups (1-3, 4-6)*/ +#define SHR_3 (3*0x2000u) /* Timer_B7 Group: 3 - 1 group (all) */ +#define TBCLGRP_0 (0*0x2000u) /* Timer_B7 Group: 0 - individually */ +#define TBCLGRP_1 (1*0x2000u) /* Timer_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */ +#define TBCLGRP_2 (2*0x2000u) /* Timer_B7 Group: 2 - 2 groups (1-3, 4-6)*/ +#define TBCLGRP_3 (3*0x2000u) /* Timer_B7 Group: 3 - 1 group (all) */ +#define TBSSEL__TBCLK (0*0x100u) /* Timer0_B7 clock source select: 0 - TBCLK */ +#define TBSSEL__TACLK (0*0x100u) /* Timer0_B7 clock source select: 0 - TBCLK (legacy) */ +#define TBSSEL__ACLK (1*0x100u) /* Timer_B7 clock source select: 1 - ACLK */ +#define TBSSEL__SMCLK (2*0x100u) /* Timer_B7 clock source select: 2 - SMCLK */ +#define TBSSEL__INCLK (3*0x100u) /* Timer_B7 clock source select: 3 - INCLK */ +#define CNTL__16 (0*0x0800u) /* Counter lenght: 16 bit */ +#define CNTL__12 (1*0x0800u) /* Counter lenght: 12 bit */ +#define CNTL__10 (2*0x0800u) /* Counter lenght: 10 bit */ +#define CNTL__8 (3*0x0800u) /* Counter lenght: 8 bit */ + +/* Additional Timer B Control Register bits are defined in Timer A */ +/* TBxCCTLx Control Bits */ +#define CLLD1 (0x0400) /* Compare latch load source 1 */ +#define CLLD0 (0x0200) /* Compare latch load source 0 */ + +#define SLSHR1 (0x0400) /* Compare latch load source 1 */ +#define SLSHR0 (0x0200) /* Compare latch load source 0 */ + +#define SLSHR_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */ +#define SLSHR_1 (1*0x0200u) /* Compare latch load sourec : 1 - TBR counts to 0 */ +#define SLSHR_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */ +#define SLSHR_3 (3*0x0200u) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */ + +#define CLLD_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */ +#define CLLD_1 (1*0x0200u) /* Compare latch load sourec : 1 - TBR counts to 0 */ +#define CLLD_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */ +#define CLLD_3 (3*0x0200u) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */ + +/* TBxEX0 Control Bits */ +#define TBIDEX0 (0x0001) /* Timer_B7 Input divider expansion Bit: 0 */ +#define TBIDEX1 (0x0002) /* Timer_B7 Input divider expansion Bit: 1 */ +#define TBIDEX2 (0x0004) /* Timer_B7 Input divider expansion Bit: 2 */ + +#define TBIDEX_0 (0*0x0001u) /* Timer_B7 Input divider expansion : /1 */ +#define TBIDEX_1 (1*0x0001u) /* Timer_B7 Input divider expansion : /2 */ +#define TBIDEX_2 (2*0x0001u) /* Timer_B7 Input divider expansion : /3 */ +#define TBIDEX_3 (3*0x0001u) /* Timer_B7 Input divider expansion : /4 */ +#define TBIDEX_4 (4*0x0001u) /* Timer_B7 Input divider expansion : /5 */ +#define TBIDEX_5 (5*0x0001u) /* Timer_B7 Input divider expansion : /6 */ +#define TBIDEX_6 (6*0x0001u) /* Timer_B7 Input divider expansion : /7 */ +#define TBIDEX_7 (7*0x0001u) /* Timer_B7 Input divider expansion : /8 */ +#define TBIDEX__1 (0*0x0001u) /* Timer_B7 Input divider expansion : /1 */ +#define TBIDEX__2 (1*0x0001u) /* Timer_B7 Input divider expansion : /2 */ +#define TBIDEX__3 (2*0x0001u) /* Timer_B7 Input divider expansion : /3 */ +#define TBIDEX__4 (3*0x0001u) /* Timer_B7 Input divider expansion : /4 */ +#define TBIDEX__5 (4*0x0001u) /* Timer_B7 Input divider expansion : /5 */ +#define TBIDEX__6 (5*0x0001u) /* Timer_B7 Input divider expansion : /6 */ +#define TBIDEX__7 (6*0x0001u) /* Timer_B7 Input divider expansion : /7 */ +#define TBIDEX__8 (7*0x0001u) /* Timer_B7 Input divider expansion : /8 */ + + +#define ID1 (0x0080) /* Timer B clock input divider 1 */ +#define ID0 (0x0040) /* Timer B clock input divider 0 */ +#define MC1 (0x0020) /* Timer B mode control 1 */ +#define MC0 (0x0010) /* Timer B mode control 0 */ +#define MC__STOP (0*0x10u) /* Timer B mode control: 0 - Stop */ +#define MC__UP (1*0x10u) /* Timer B mode control: 1 - Up to CCR0 */ +#define MC__CONTINUOUS (2*0x10u) /* Timer B mode control: 2 - Continuous up */ +#define MC__CONTINOUS (2*0x10u) /* Legacy define */ +#define MC__UPDOWN (3*0x10u) /* Timer B mode control: 3 - Up/Down */ +#define CM1 (0x8000) /* Capture mode 1 */ +#define CM0 (0x4000) /* Capture mode 0 */ +#define MC_0 (0*0x10u) /* Timer B mode control: 0 - Stop */ +#define MC_1 (1*0x10u) /* Timer B mode control: 1 - Up to CCR0 */ +#define MC_2 (2*0x10u) /* Timer B mode control: 2 - Continuous up */ +#define MC_3 (3*0x10u) /* Timer B mode control: 3 - Up/Down */ +#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */ +#define CCIE (0x0010) /* Capture/compare interrupt enable */ +#define CCIFG (0x0001) /* Capture/compare interrupt flag */ +#define CCIS_0 (0*0x1000u) +#define CCIS_1 (1*0x1000u) +#define CCIS_2 (2*0x1000u) +#define CCIS_3 (3*0x1000u) +#define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */ +#define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */ +#define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */ +#define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */ +#define OUT (0x0004) /* PWM Output signal if output mode 0 */ +#define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */ +#define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */ +#define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */ +#define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */ +#define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */ +#define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */ +#define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */ +#define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */ +#define SCCI (0x0400) /* Latched capture signal (read) */ +#define SCS (0x0800) /* Capture sychronize */ +#define CCI (0x0008) /* Capture input signal (read) */ +#define ID__1 (0*0x40u) /* Timer B input divider: 0 - /1 */ +#define ID__2 (1*0x40u) /* Timer B input divider: 1 - /2 */ +#define ID__4 (2*0x40u) /* Timer B input divider: 2 - /4 */ +#define ID__8 (3*0x40u) /* Timer B input divider: 3 - /8 */ +#define ID_0 (0*0x40u) /* Timer B input divider: 0 - /1 */ +#define ID_1 (1*0x40u) /* Timer B input divider: 1 - /2 */ +#define ID_2 (2*0x40u) /* Timer B input divider: 2 - /4 */ +#define ID_3 (3*0x40u) /* Timer B input divider: 3 - /8 */ + +#endif +/************************************************************ +* Timerx_D7 +************************************************************/ +#ifdef __MSP430_HAS_TxD7__ /* Definition to show that Module is available */ + +#define OFS_TDxCTL0 (0x0000) /* Timerx_D7 Control 0 */ +#define OFS_TDxCTL1 (0x0002) /* Timerx_D7 Control 1 */ +#define OFS_TDxCTL2 (0x0004) /* Timerx_D7 Control 2 */ +#define OFS_TDxR (0x0006) /* Timerx_D7 Counter */ +#define OFS_TDxCCTL0 (0x0008) /* Timerx_D7 Capture/Compare Control 0 */ +#define OFS_TDxCCR0 (0x000A) /* Timerx_D7 Capture/Compare 0 */ +#define OFS_TDxCL0 (0x000C) /* Timerx_D7 Capture/Compare Latch 0 */ +#define OFS_TDxCCTL1 (0x000E) /* Timerx_D7 Capture/Compare Control 1 */ +#define OFS_TDxCCR1 (0x0010) /* Timerx_D7 Capture/Compare 1 */ +#define OFS_TDxCL1 (0x0012) /* Timerx_D7 Capture/Compare Latch 1 */ +#define OFS_TDxCCTL2 (0x0014) /* Timerx_D7 Capture/Compare Control 2 */ +#define OFS_TDxCCR2 (0x0016) /* Timerx_D7 Capture/Compare 2 */ +#define OFS_TDxCL2 (0x0018) /* Timerx_D7 Capture/Compare Latch 2 */ +#define OFS_TDxCCTL3 (0x001A) /* Timerx_D7 Capture/Compare Control 3 */ +#define OFS_TDxCCR3 (0x001C) /* Timerx_D7 Capture/Compare 3 */ +#define OFS_TDxCL3 (0x001E) /* Timerx_D7 Capture/Compare Latch 3 */ +#define OFS_TDxCCTL4 (0x0020) /* Timerx_D7 Capture/Compare Control 4 */ +#define OFS_TDxCCR4 (0x0022) /* Timerx_D7 Capture/Compare 4 */ +#define OFS_TDxCL4 (0x0024) /* Timerx_D7 Capture/Compare Latch 4 */ +#define OFS_TDxCCTL5 (0x0026) /* Timerx_D7 Capture/Compare Control 5 */ +#define OFS_TDxCCR5 (0x0028) /* Timerx_D7 Capture/Compare 5 */ +#define OFS_TDxCL5 (0x002A) /* Timerx_D7 Capture/Compare Latch 5 */ +#define OFS_TDxCCTL6 (0x002C) /* Timerx_D7 Capture/Compare Control 6 */ +#define OFS_TDxCCR6 (0x002E) /* Timerx_D7 Capture/Compare 6 */ +#define OFS_TDxCL6 (0x0030) /* Timerx_D7 Capture/Compare Latch 6 */ +#define OFS_TDxHCTL0 (0x0038) /* Timerx_D7 High-resolution Control Register 0 */ +#define OFS_TDxHCTL1 (0x003A) /* Timerx_D7 High-resolution Control Register 1 */ +#define OFS_TDxHINT (0x003C) /* Timerx_D7 High-resolution Interrupt Register */ +#define OFS_TDxIV (0x003E) /* Timerx_D7 Interrupt Vector Word */ + +/* Bits are already defined within the Timer0_Dx */ + +/* TDxIV Definitions */ +#define TDxIV_NONE (0x0000) /* No Interrupt pending */ +#define TDxIV_TDCCR1 (0x0002) /* TDxCCR1_CCIFG */ +#define TDxIV_TDCCR2 (0x0004) /* TDxCCR2_CCIFG */ +#define TDxIV_TDCCR3 (0x0006) /* TDxCCR3_CCIFG */ +#define TDxIV_TDCCR4 (0x0008) /* TDxCCR4_CCIFG */ +#define TDxIV_TDCCR5 (0x000A) /* TDxCCR5_CCIFG */ +#define TDxIV_TDCCR6 (0x000C) /* TDxCCR6_CCIFG */ +#define TDxIV_RES_14 (0x000E) /* Reserverd */ +#define TDxIV_TDIFG (0x0010) /* TDxIFG */ +#define TDxIV_TDHFLIFG (0x0012) /* TDHFLIFG Clock fail low */ +#define TDxIV_TDHFHIFG (0x0014) /* TDHFLIFG Clock fail high */ +#define TDxIV_TDHLKIFG (0x0016) /* TDHLKIE Clock lock*/ +#define TDxIV_TDHUNLKIFG (0x0018) /* TDHUNLKIE Clock unlock */ + +/* Legacy Defines */ +#define TDxIV_TDxCCR1 (0x0002) /* TDxCCR1_CCIFG */ +#define TDxIV_TDxCCR2 (0x0004) /* TDxCCR2_CCIFG */ +#define TDxIV_TDxCCR3 (0x0006) /* TDxCCR3_CCIFG */ +#define TDxIV_TDxCCR4 (0x0008) /* TDxCCR4_CCIFG */ +#define TDxIV_TDxCCR5 (0x000A) /* TDxCCR5_CCIFG */ +#define TDxIV_TDxCCR6 (0x000C) /* TDxCCR6_CCIFG */ +#define TDxIV_TDxIFG (0x0010) /* TDxIFG */ + +/* TDxCTL0 Control Bits */ +#define TDCLGRP1 (0x4000) /* Timer_D7 Compare latch load group 1 */ +#define TDCLGRP0 (0x2000) /* Timer_D7 Compare latch load group 0 */ +#define CNTL1 (0x1000) /* Counter lenght 1 */ +#define CNTL0 (0x0800) /* Counter lenght 0 */ +#define TDSSEL1 (0x0200) /* Clock source 1 */ +#define TDSSEL0 (0x0100) /* Clock source 0 */ +#define TDCLR (0x0004) /* Timer_D7 counter clear */ +#define TDIE (0x0002) /* Timer_D7 interrupt enable */ +#define TDIFG (0x0001) /* Timer_D7 interrupt flag */ + +#define SHR1 (0x4000) /* Timer_D7 Compare latch load group 1 */ +#define SHR0 (0x2000) /* Timer_D7 Compare latch load group 0 */ + +#define TDSSEL_0 (0*0x0100u) /* Clock Source: TDCLK */ +#define TDSSEL_1 (1*0x0100u) /* Clock Source: ACLK */ +#define TDSSEL_2 (2*0x0100u) /* Clock Source: SMCLK */ +#define TDSSEL_3 (3*0x0100u) /* Clock Source: INCLK */ +#define CNTL_0 (0*0x0800u) /* Counter lenght: 16 bit */ +#define CNTL_1 (1*0x0800u) /* Counter lenght: 12 bit */ +#define CNTL_2 (2*0x0800u) /* Counter lenght: 10 bit */ +#define CNTL_3 (3*0x0800u) /* Counter lenght: 8 bit */ +#define SHR_0 (0*0x2000u) /* Timer_D7 Group: 0 - individually */ +#define SHR_1 (1*0x2000u) /* Timer_D7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */ +#define SHR_2 (2*0x2000u) /* Timer_D7 Group: 2 - 2 groups (1-3, 4-6)*/ +#define SHR_3 (3*0x2000u) /* Timer_D7 Group: 3 - 1 group (all) */ +#define TDCLGRP_0 (0*0x2000u) /* Timer_D7 Group: 0 - individually */ +#define TDCLGRP_1 (1*0x2000u) /* Timer_D7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */ +#define TDCLGRP_2 (2*0x2000u) /* Timer_D7 Group: 2 - 2 groups (1-3, 4-6)*/ +#define TDCLGRP_3 (3*0x2000u) /* Timer_D7 Group: 3 - 1 group (all) */ +#define TDSSEL__TACLK (0*0x0100u) /* Timer_D7 clock source select: 0 - TACLK */ +#define TDSSEL__ACLK (1*0x0100u) /* Timer_D7 clock source select: 1 - ACLK */ +#define TDSSEL__SMCLK (2*0x0100u) /* Timer_D7 clock source select: 2 - SMCLK */ +#define TDSSEL__INCLK (3*0x0100u) /* Timer_D7 clock source select: 3 - INCLK */ +#define CNTL__16 (0*0x0800u) /* Counter lenght: 16 bit */ +#define CNTL__12 (1*0x0800u) /* Counter lenght: 12 bit */ +#define CNTL__10 (2*0x0800u) /* Counter lenght: 10 bit */ +#define CNTL__8 (3*0x0800u) /* Counter lenght: 8 bit */ + +/* Additional Timer B Control Register bits are defined in Timer A */ + +/* TDxCTL1 Control Bits */ +#define TDCLKM0 (0x0001) /* Timer_D7 Clocking Mode Bit: 0 */ +#define TDCLKM1 (0x0002) /* Timer_D7 Clocking Mode Bit: 1 */ +#define TD2CMB (0x0010) /* Timer_D7 TD0CCR Combination in TD2 */ +#define TD4CMB (0x0020) /* Timer_D7 TD0CCR Combination in TD4 */ +#define TD6CMB (0x0040) /* Timer_D7 TD0CCR Combination in TD6 */ +#define TDIDEX0 (0x0100) /* Timer_D7 Input divider expansion Bit: 0 */ +#define TDIDEX1 (0x0200) /* Timer_D7 Input divider expansion Bit: 1 */ +#define TDIDEX2 (0x0400) /* Timer_D7 Input divider expansion Bit: 2 */ + +#define TDCLKM_0 (0x0000) /* Timer_D7 Clocking Mode: External */ +#define TDCLKM_1 (0x0001) /* Timer_D7 Clocking Mode: High-Res. local clock */ +#define TDCLKM_2 (0x0002) /* Timer_D7 Clocking Mode: Aux Clock */ +#define TDCLKM__EXT (0x0000) /* Timer_D7 Clocking Mode: External */ +#define TDCLKM__HIGHRES (0x0001) /* Timer_D7 Clocking Mode: High-Res. local clock */ +#define TDCLKM__AUX (0x0002) /* Timer_D7 Clocking Mode: Aux Clock */ + +#define TDIDEX_0 (0*0x0100u) /* Timer0_D3 Input divider expansion : /1 */ +#define TDIDEX_1 (1*0x0100u) /* Timer0_D3 Input divider expansion : /2 */ +#define TDIDEX_2 (2*0x0100u) /* Timer0_D3 Input divider expansion : /3 */ +#define TDIDEX_3 (3*0x0100u) /* Timer0_D3 Input divider expansion : /4 */ +#define TDIDEX_4 (4*0x0100u) /* Timer0_D3 Input divider expansion : /5 */ +#define TDIDEX_5 (5*0x0100u) /* Timer0_D3 Input divider expansion : /6 */ +#define TDIDEX_6 (6*0x0100u) /* Timer0_D3 Input divider expansion : /7 */ +#define TDIDEX_7 (7*0x0100u) /* Timer0_D3 Input divider expansion : /8 */ +#define TDIDEX__1 (0*0x0100u) /* Timer0_D3 Input divider expansion : /1 */ +#define TDIDEX__2 (1*0x0100u) /* Timer0_D3 Input divider expansion : /2 */ +#define TDIDEX__3 (2*0x0100u) /* Timer0_D3 Input divider expansion : /3 */ +#define TDIDEX__4 (3*0x0100u) /* Timer0_D3 Input divider expansion : /4 */ +#define TDIDEX__5 (4*0x0100u) /* Timer0_D3 Input divider expansion : /5 */ +#define TDIDEX__6 (5*0x0100u) /* Timer0_D3 Input divider expansion : /6 */ +#define TDIDEX__7 (6*0x0100u) /* Timer0_D3 Input divider expansion : /7 */ +#define TDIDEX__8 (7*0x0100u) /* Timer0_D3 Input divider expansion : /8 */ + +/* TDxCTL2 Control Bits */ +#define TDCAPM0 (0x0001) /* Timer_D7 Capture Mode of Channel 0 */ +#define TDCAPM1 (0x0002) /* Timer_D7 Capture Mode of Channel 1 */ +#define TDCAPM2 (0x0004) /* Timer_D7 Capture Mode of Channel 2 */ +#define TDCAPM3 (0x0008) /* Timer_D7 Capture Mode of Channel 3 */ +#define TDCAPM4 (0x0010) /* Timer_D7 Capture Mode of Channel 4 */ +#define TDCAPM5 (0x0020) /* Timer_D7 Capture Mode of Channel 5 */ +#define TDCAPM6 (0x0040) /* Timer_D7 Capture Mode of Channel 6 */ + +/* TDxCCTLx Control Bits */ +#define CLLD1 (0x0400) /* Compare latch load source 1 */ +#define CLLD0 (0x0200) /* Compare latch load source 0 */ + +#define SLSHR1 (0x0400) /* Compare latch load source 1 */ +#define SLSHR0 (0x0200) /* Compare latch load source 0 */ + +#define SLSHR_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */ +#define SLSHR_1 (1*0x0200u) /* Compare latch load sourec : 1 - TDR counts to 0 */ +#define SLSHR_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */ +#define SLSHR_3 (3*0x0200u) /* Compare latch load sourec : 3 - TDR counts to TDCTL0 */ + +#define CLLD_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */ +#define CLLD_1 (1*0x0200u) /* Compare latch load sourec : 1 - TDR counts to 0 */ +#define CLLD_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */ +#define CLLD_3 (3*0x0200u) /* Compare latch load sourec : 3 - TDR counts to TDCTL0 */ + +/* TDxHCTL0 Control Bits */ +#define TDHEN (0x0001) /* Timer_D7 High-Resolution Enable */ +#define TDHREGEN (0x0002) /* Timer_D7 High-Resolution Regulatied Mode */ +#define TDHEAEN (0x0004) /* Timer_D7 High-Resolution clock error accum. enable */ +#define TDHRON (0x0008) /* Timer_D7 High-Resolution Generator forced on*/ +#define TDHM0 (0x0010) /* Timer_D7 High-Resoltuion Clock Mult. Bit: 0 */ +#define TDHM1 (0x0020) /* Timer_D7 High-Resoltuion Clock Mult. Bit: 1 */ +#define TDHD0 (0x0040) /* Timer_D7 High-Resolution clock divider Bit: 0 */ +#define TDHD1 (0x0080) /* Timer_D7 High-Resolution clock divider Bit: 1 */ +#define TDHFW (0x0100) /* Timer_D7 High-resolution generator fast wakeup enable */ + +#define TDHCALEN TDHREGEN /* Timer_D7 Lagacy Definition */ + +#define TDHM_0 (0x0000) /* Timer_D7 High-Resoltuion Clock Mult.: 8x TimerD clock */ +#define TDHM_1 (0x0010) /* Timer_D7 High-Resoltuion Clock Mult.: 16x TimerD clock */ +#define TDHM__8 (0x0000) /* Timer_D7 High-Resoltuion Clock Mult.: 8x TimerD clock */ +#define TDHM__16 (0x0010) /* Timer_D7 High-Resoltuion Clock Mult.: 16x TimerD clock */ +#define TDHD_0 (0x0000) /* Timer_D7 High-Resolution clock divider: /1 */ +#define TDHD_1 (0x0040) /* Timer_D7 High-Resolution clock divider: /2 */ +#define TDHD_2 (0x0080) /* Timer_D7 High-Resolution clock divider: /4 */ +#define TDHD_3 (0x00C0) /* Timer_D7 High-Resolution clock divider: /8 */ +#define TDHD__1 (0x0000) /* Timer_D7 High-Resolution clock divider: /1 */ +#define TDHD__2 (0x0040) /* Timer_D7 High-Resolution clock divider: /2 */ +#define TDHD__4 (0x0080) /* Timer_D7 High-Resolution clock divider: /4 */ +#define TDHD__8 (0x00C0) /* Timer_D7 High-Resolution clock divider: /8 */ + +/* TDxHCTL1 Control Bits */ +#define TDHCLKTRIM0 (0x0002) /* Timer_D7 High-Resolution Clock Trim Bit: 0 */ +#define TDHCLKTRIM1 (0x0004) /* Timer_D7 High-Resolution Clock Trim Bit: 1 */ +#define TDHCLKTRIM2 (0x0008) /* Timer_D7 High-Resolution Clock Trim Bit: 2 */ +#define TDHCLKTRIM3 (0x0010) /* Timer_D7 High-Resolution Clock Trim Bit: 3 */ +#define TDHCLKTRIM4 (0x0020) /* Timer_D7 High-Resolution Clock Trim Bit: 4 */ +#define TDHCLKTRIM5 (0x0040) /* Timer_D7 High-Resolution Clock Trim Bit: 5 */ +#define TDHCLKTRIM6 (0x0080) /* Timer_D7 High-Resolution Clock Trim Bit: 6 */ +#define TDHCLKSR0 (0x0100) /* Timer_D7 High-Resolution Clock Sub-Range Bit: 0 */ +#define TDHCLKSR1 (0x0200) /* Timer_D7 High-Resolution Clock Sub-Range Bit: 1 */ +#define TDHCLKSR2 (0x0400) /* Timer_D7 High-Resolution Clock Sub-Range Bit: 2 */ +#define TDHCLKSR3 (0x0800) /* Timer_D7 High-Resolution Clock Sub-Range Bit: 3 */ +#define TDHCLKSR4 (0x1000) /* Timer_D7 High-Resolution Clock Sub-Range Bit: 4 */ +#define TDHCLKR0 (0x2000) /* Timer_D7 High-Resolution Clock Range Bit: 0 */ +#define TDHCLKR1 (0x4000) /* Timer_D7 High-Resolution Clock Range Bit: 1 */ +#define TDHCLKCR (0x8000) /* Timer_D7 High-Resolution Coarse Clock Range */ + +/* TDxHINT Control Bits */ +#define TDHFLIFG (0x0001) /* Timer_D7 High-Res. fail low Interrupt Flag */ +#define TDHFHIFG (0x0002) /* Timer_D7 High-Res. fail high Interrupt Flag */ +#define TDHLKIFG (0x0004) /* Timer_D7 High-Res. frequency lock Interrupt Flag */ +#define TDHUNLKIFG (0x0008) /* Timer_D7 High-Res. frequency unlock Interrupt Flag */ +#define TDHFLIE (0x0100) /* Timer_D7 High-Res. fail low Interrupt Enable */ +#define TDHFHIE (0x0200) /* Timer_D7 High-Res. fail high Interrupt Enable */ +#define TDHLKIE (0x0400) /* Timer_D7 High-Res. frequency lock Interrupt Enable */ +#define TDHUNLKIE (0x0800) /* Timer_D7 High-Res. frequency unlock Interrupt Enable */ + +#define ID1 (0x0080) /* Timer D clock input divider 1 */ +#define ID0 (0x0040) /* Timer D clock input divider 0 */ +#define MC1 (0x0020) /* Timer D mode control 1 */ +#define MC0 (0x0010) /* Timer D mode control 0 */ +#define MC__STOP (0*0x10u) /* Timer D mode control: 0 - Stop */ +#define MC__UP (1*0x10u) /* Timer D mode control: 1 - Up to CCR0 */ +#define MC__CONTINUOUS (2*0x10u) /* Timer D mode control: 2 - Continuous up */ +#define MC__CONTINOUS (2*0x10u) /* Legacy define */ +#define MC__UPDOWN (3*0x10u) /* Timer D mode control: 3 - Up/Down */ +#define CM1 (0x8000) /* Capture mode 1 */ +#define CM0 (0x4000) /* Capture mode 0 */ +#define MC_0 (0*0x10u) /* Timer D mode control: 0 - Stop */ +#define MC_1 (1*0x10u) /* Timer D mode control: 1 - Up to CCR0 */ +#define MC_2 (2*0x10u) /* Timer D mode control: 2 - Continuous up */ +#define MC_3 (3*0x10u) /* Timer D mode control: 3 - Up/Down */ +#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */ +#define CCIE (0x0010) /* Capture/compare interrupt enable */ +#define CCIFG (0x0001) /* Capture/compare interrupt flag */ +#define CCIS_0 (0*0x1000u) +#define CCIS_1 (1*0x1000u) +#define CCIS_2 (2*0x1000u) +#define CCIS_3 (3*0x1000u) +#define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */ +#define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */ +#define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */ +#define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */ +#define OUT (0x0004) /* PWM Output signal if output mode 0 */ +#define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */ +#define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */ +#define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */ +#define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */ +#define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */ +#define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */ +#define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */ +#define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */ +#define SCCI (0x0400) /* Latched capture signal (read) */ +#define SCS (0x0800) /* Capture sychronize */ +#define CCI (0x0008) /* Capture input signal (read) */ +#define ID__1 (0*0x40u) /* Timer D input divider: 0 - /1 */ +#define ID__2 (1*0x40u) /* Timer D input divider: 1 - /2 */ +#define ID__4 (2*0x40u) /* Timer D input divider: 2 - /4 */ +#define ID__8 (3*0x40u) /* Timer D input divider: 3 - /8 */ +#define ID_0 (0*0x40u) /* Timer D input divider: 0 - /1 */ +#define ID_1 (1*0x40u) /* Timer D input divider: 1 - /2 */ +#define ID_2 (2*0x40u) /* Timer D input divider: 2 - /4 */ +#define ID_3 (3*0x40u) /* Timer D input divider: 3 - /8 */ + +#endif +/************************************************************ +* Timer Event Control 0 +************************************************************/ +#ifdef __MSP430_HAS_TEV0__ /* Definition to show that Module is available */ + +#define OFS_TEC0XCTL0 (0x0000) /* Timer Event Control 0 External Control 0 */ +#define OFS_TEC0XCTL0_L OFS_TEC0XCTL0 +#define OFS_TEC0XCTL0_H OFS_TEC0XCTL0+1 +#define OFS_TEC0XCTL1 (0x0002) /* Timer Event Control 0 External Control 1 */ +#define OFS_TEC0XCTL1_L OFS_TEC0XCTL1 +#define OFS_TEC0XCTL1_H OFS_TEC0XCTL1+1 +#define OFS_TEC0XCTL2 (0x0004) /* Timer Event Control 0 External Control 2 */ +#define OFS_TEC0XCTL2_L OFS_TEC0XCTL2 +#define OFS_TEC0XCTL2_H OFS_TEC0XCTL2+1 +#define OFS_TEC0STA (0x0006) /* Timer Event Control 0 Status */ +#define OFS_TEC0STA_L OFS_TEC0STA +#define OFS_TEC0STA_H OFS_TEC0STA+1 +#define OFS_TEC0XINT (0x0008) /* Timer Event Control 0 External Interrupt */ +#define OFS_TEC0XINT_L OFS_TEC0XINT +#define OFS_TEC0XINT_H OFS_TEC0XINT+1 +#define OFS_TEC0IV (0x000A) /* Timer Event Control 0 Interrupt Vector */ +#define OFS_TEC0IV_L OFS_TEC0IV +#define OFS_TEC0IV_H OFS_TEC0IV+1 + +/* TECxXCTL0 Control Bits */ +#define TECXFLTHLD0 (0x0001) /* TEV Ext. fault signal hold for CE0 */ +#define TECXFLTHLD1 (0x0002) /* TEV Ext. fault signal hold for CE1 */ +#define TECXFLTHLD2 (0x0004) /* TEV Ext. fault signal hold for CE2 */ +#define TECXFLTHLD3 (0x0008) /* TEV Ext. fault signal hold for CE3 */ +#define TECXFLTHLD4 (0x0010) /* TEV Ext. fault signal hold for CE4 */ +#define TECXFLTHLD5 (0x0020) /* TEV Ext. fault signal hold for CE5 */ +#define TECXFLTHLD6 (0x0040) /* TEV Ext. fault signal hold for CE6 */ +#define TECXFLTEN0 (0x0100) /* TEV Ext. fault signal enable for CE0 */ +#define TECXFLTEN1 (0x0200) /* TEV Ext. fault signal enable for CE1 */ +#define TECXFLTEN2 (0x0400) /* TEV Ext. fault signal enable for CE2 */ +#define TECXFLTEN3 (0x0800) /* TEV Ext. fault signal enable for CE3 */ +#define TECXFLTEN4 (0x1000) /* TEV Ext. fault signal enable for CE4 */ +#define TECXFLTEN5 (0x2000) /* TEV Ext. fault signal enable for CE5 */ +#define TECXFLTEN6 (0x4000) /* TEV Ext. fault signal enable for CE6 */ + +/* TECxXCTL0 Control Bits */ +#define TECXFLTHLD0_L (0x0001) /* TEV Ext. fault signal hold for CE0 */ +#define TECXFLTHLD1_L (0x0002) /* TEV Ext. fault signal hold for CE1 */ +#define TECXFLTHLD2_L (0x0004) /* TEV Ext. fault signal hold for CE2 */ +#define TECXFLTHLD3_L (0x0008) /* TEV Ext. fault signal hold for CE3 */ +#define TECXFLTHLD4_L (0x0010) /* TEV Ext. fault signal hold for CE4 */ +#define TECXFLTHLD5_L (0x0020) /* TEV Ext. fault signal hold for CE5 */ +#define TECXFLTHLD6_L (0x0040) /* TEV Ext. fault signal hold for CE6 */ + +/* TECxXCTL0 Control Bits */ +#define TECXFLTEN0_H (0x0001) /* TEV Ext. fault signal enable for CE0 */ +#define TECXFLTEN1_H (0x0002) /* TEV Ext. fault signal enable for CE1 */ +#define TECXFLTEN2_H (0x0004) /* TEV Ext. fault signal enable for CE2 */ +#define TECXFLTEN3_H (0x0008) /* TEV Ext. fault signal enable for CE3 */ +#define TECXFLTEN4_H (0x0010) /* TEV Ext. fault signal enable for CE4 */ +#define TECXFLTEN5_H (0x0020) /* TEV Ext. fault signal enable for CE5 */ +#define TECXFLTEN6_H (0x0040) /* TEV Ext. fault signal enable for CE6 */ + +/* TECxXCTL1 Control Bits */ +#define TECXFLTPOL0 (0x0001) /* TEV Polarity Bit of ext. fault 0 */ +#define TECXFLTPOL1 (0x0002) /* TEV Polarity Bit of ext. fault 1 */ +#define TECXFLTPOL2 (0x0004) /* TEV Polarity Bit of ext. fault 2 */ +#define TECXFLTPOL3 (0x0008) /* TEV Polarity Bit of ext. fault 3 */ +#define TECXFLTPOL4 (0x0010) /* TEV Polarity Bit of ext. fault 4 */ +#define TECXFLTPOL5 (0x0020) /* TEV Polarity Bit of ext. fault 5 */ +#define TECXFLTPOL6 (0x0040) /* TEV Polarity Bit of ext. fault 6 */ +#define TECXFLTLVS0 (0x0100) /* TEV Signal Type of Ext. fault 0 */ +#define TECXFLTLVS1 (0x0200) /* TEV Signal Type of Ext. fault 1 */ +#define TECXFLTLVS2 (0x0400) /* TEV Signal Type of Ext. fault 2 */ +#define TECXFLTLVS3 (0x0800) /* TEV Signal Type of Ext. fault 3 */ +#define TECXFLTLVS4 (0x1000) /* TEV Signal Type of Ext. fault 4 */ +#define TECXFLTLVS5 (0x2000) /* TEV Signal Type of Ext. fault 5 */ +#define TECXFLTLVS6 (0x4000) /* TEV Signal Type of Ext. fault 6 */ + +/* TECxXCTL1 Control Bits */ +#define TECXFLTPOL0_L (0x0001) /* TEV Polarity Bit of ext. fault 0 */ +#define TECXFLTPOL1_L (0x0002) /* TEV Polarity Bit of ext. fault 1 */ +#define TECXFLTPOL2_L (0x0004) /* TEV Polarity Bit of ext. fault 2 */ +#define TECXFLTPOL3_L (0x0008) /* TEV Polarity Bit of ext. fault 3 */ +#define TECXFLTPOL4_L (0x0010) /* TEV Polarity Bit of ext. fault 4 */ +#define TECXFLTPOL5_L (0x0020) /* TEV Polarity Bit of ext. fault 5 */ +#define TECXFLTPOL6_L (0x0040) /* TEV Polarity Bit of ext. fault 6 */ + +/* TECxXCTL1 Control Bits */ +#define TECXFLTLVS0_H (0x0001) /* TEV Signal Type of Ext. fault 0 */ +#define TECXFLTLVS1_H (0x0002) /* TEV Signal Type of Ext. fault 1 */ +#define TECXFLTLVS2_H (0x0004) /* TEV Signal Type of Ext. fault 2 */ +#define TECXFLTLVS3_H (0x0008) /* TEV Signal Type of Ext. fault 3 */ +#define TECXFLTLVS4_H (0x0010) /* TEV Signal Type of Ext. fault 4 */ +#define TECXFLTLVS5_H (0x0020) /* TEV Signal Type of Ext. fault 5 */ +#define TECXFLTLVS6_H (0x0040) /* TEV Signal Type of Ext. fault 6 */ + +/* TECxXCTL2 Control Bits */ +#define TECCLKSEL0 (0x0001) /* TEV Aux. Clock Select Bit: 0 */ +#define TECCLKSEL1 (0x0002) /* TEV Aux. Clock Select Bit: 1 */ +#define TECAXCLREN (0x0004) /* TEV Auxilary clear signal control */ +#define TECEXCLREN (0x0008) /* TEV Ext. clear signal control */ +#define TECEXCLRHLD (0x0010) /* TEV External clear signal hold bit */ +#define TECEXCLRPOL (0x0020) /* TEV Polarity Bit of ext. clear */ +#define TECEXCLRLVS (0x0040) /* TEV Signal Type of Ext. clear */ + +/* TECxXCTL2 Control Bits */ +#define TECCLKSEL0_L (0x0001) /* TEV Aux. Clock Select Bit: 0 */ +#define TECCLKSEL1_L (0x0002) /* TEV Aux. Clock Select Bit: 1 */ +#define TECAXCLREN_L (0x0004) /* TEV Auxilary clear signal control */ +#define TECEXCLREN_L (0x0008) /* TEV Ext. clear signal control */ +#define TECEXCLRHLD_L (0x0010) /* TEV External clear signal hold bit */ +#define TECEXCLRPOL_L (0x0020) /* TEV Polarity Bit of ext. clear */ +#define TECEXCLRLVS_L (0x0040) /* TEV Signal Type of Ext. clear */ + +#define TECCLKSEL_0 (0x0000) /* TEV Aux. Clock Select: CLK0 */ +#define TECCLKSEL_1 (0x0001) /* TEV Aux. Clock Select: CLK1 */ +#define TECCLKSEL_2 (0x0002) /* TEV Aux. Clock Select: CLK2 */ +#define TECCLKSEL_3 (0x0003) /* TEV Aux. Clock Select: CLK3 */ + +/* TECxSTA Control Bits */ +#define TECXFLT0STA (0x0001) /* TEV External fault status flag for CE0 */ +#define TECXFLT1STA (0x0002) /* TEV External fault status flag for CE1 */ +#define TECXFLT2STA (0x0004) /* TEV External fault status flag for CE2 */ +#define TECXFLT3STA (0x0008) /* TEV External fault status flag for CE3 */ +#define TECXFLT4STA (0x0010) /* TEV External fault status flag for CE4 */ +#define TECXFLT5STA (0x0020) /* TEV External fault status flag for CE5 */ +#define TECXFLT6STA (0x0040) /* TEV External fault status flag for CE6 */ +#define TECXCLRSTA (0x0100) /* TEC External clear status flag */ + +/* TECxSTA Control Bits */ +#define TECXFLT0STA_L (0x0001) /* TEV External fault status flag for CE0 */ +#define TECXFLT1STA_L (0x0002) /* TEV External fault status flag for CE1 */ +#define TECXFLT2STA_L (0x0004) /* TEV External fault status flag for CE2 */ +#define TECXFLT3STA_L (0x0008) /* TEV External fault status flag for CE3 */ +#define TECXFLT4STA_L (0x0010) /* TEV External fault status flag for CE4 */ +#define TECXFLT5STA_L (0x0020) /* TEV External fault status flag for CE5 */ +#define TECXFLT6STA_L (0x0040) /* TEV External fault status flag for CE6 */ + +/* TECxSTA Control Bits */ +#define TECXCLRSTA_H (0x0001) /* TEC External clear status flag */ + +/* TECxXINT Control Bits */ +#define TECAXCLRIFG (0x0001) /* TEC Aux. Clear Interrupt Flag */ +#define TECEXCLRIFG (0x0002) /* TEC External Clear Interrupt Flag */ +#define TECXFLTIFG (0x0004) /* TEC External Fault Interrupt Flag */ +#define TECAXCLRIE (0x0100) /* TEC Aux. Clear Interrupt Enable */ +#define TECEXCLRIE (0x0200) /* TEC External Clear Interrupt Enable */ +#define TECXFLTIE (0x0400) /* TEC External Fault Interrupt Enable */ + +/* TECxXINT Control Bits */ +#define TECAXCLRIFG_L (0x0001) /* TEC Aux. Clear Interrupt Flag */ +#define TECEXCLRIFG_L (0x0002) /* TEC External Clear Interrupt Flag */ +#define TECXFLTIFG_L (0x0004) /* TEC External Fault Interrupt Flag */ + +/* TECxXINT Control Bits */ +#define TECAXCLRIE_H (0x0001) /* TEC Aux. Clear Interrupt Enable */ +#define TECEXCLRIE_H (0x0002) /* TEC External Clear Interrupt Enable */ +#define TECXFLTIE_H (0x0004) /* TEC External Fault Interrupt Enable */ + +/* TEC0IV Definitions */ +#define TEC0IV_NONE (0x0000) /* No Interrupt pending */ +#define TEC0IV_TECXFLTIFG (0x0002) /* TEC0XFLTIFG */ +#define TEC0IV_TECEXCLRIFG (0x0004) /* TEC0EXCLRIFG */ +#define TEC0IV_TECAXCLRIFG (0x0006) /* TEC0AXCLRIFG */ + +#endif +/************************************************************ +* Timer Event Control x +************************************************************/ +#ifdef __MSP430_HAS_TEVx__ /* Definition to show that Module is available */ + +#define OFS_TECxXCTL0 (0x0000) /* Timer Event Control x External Control 0 */ +#define OFS_TECxXCTL0_L OFS_TECxXCTL0 +#define OFS_TECxXCTL0_H OFS_TECxXCTL0+1 +#define OFS_TECxXCTL1 (0x0002) /* Timer Event Control x External Control 1 */ +#define OFS_TECxXCTL1_L OFS_TECxXCTL1 +#define OFS_TECxXCTL1_H OFS_TECxXCTL1+1 +#define OFS_TECxXCTL2 (0x0004) /* Timer Event Control x External Control 2 */ +#define OFS_TECxXCTL2_L OFS_TECxXCTL2 +#define OFS_TECxXCTL2_H OFS_TECxXCTL2+1 +#define OFS_TECxSTA (0x0006) /* Timer Event Control x Status */ +#define OFS_TECxSTA_L OFS_TECxSTA +#define OFS_TECxSTA_H OFS_TECxSTA+1 +#define OFS_TECxXINT (0x0008) /* Timer Event Control x External Interrupt */ +#define OFS_TECxXINT_L OFS_TECxXINT +#define OFS_TECxXINT_H OFS_TECxXINT+1 +#define OFS_TECxIV (0x000A) /* Timer Event Control x Interrupt Vector */ +#define OFS_TECxIV_L OFS_TECxIV +#define OFS_TECxIV_H OFS_TECxIV+1 + +/* TECIV Definitions */ +#define TECxIV_NONE (0x0000) /* No Interrupt pending */ +#define TECxIV_TECXFLTIFG (0x0002) /* TECxXFLTIFG */ +#define TECxIV_TECEXCLRIFG (0x0004) /* TECxEXCLRIFG */ +#define TECxIV_TECAXCLRIFG (0x0006) /* TECxAXCLRIFG */ + + +#endif + +/************************************************************ +* UNIFIED CLOCK SYSTEM +************************************************************/ +#ifdef __MSP430_HAS_UCS__ /* Definition to show that Module is available */ + +#define OFS_UCSCTL0 (0x0000) /* UCS Control Register 0 */ +#define OFS_UCSCTL0_L OFS_UCSCTL0 +#define OFS_UCSCTL0_H OFS_UCSCTL0+1 +#define OFS_UCSCTL1 (0x0002) /* UCS Control Register 1 */ +#define OFS_UCSCTL1_L OFS_UCSCTL1 +#define OFS_UCSCTL1_H OFS_UCSCTL1+1 +#define OFS_UCSCTL2 (0x0004) /* UCS Control Register 2 */ +#define OFS_UCSCTL2_L OFS_UCSCTL2 +#define OFS_UCSCTL2_H OFS_UCSCTL2+1 +#define OFS_UCSCTL3 (0x0006) /* UCS Control Register 3 */ +#define OFS_UCSCTL3_L OFS_UCSCTL3 +#define OFS_UCSCTL3_H OFS_UCSCTL3+1 +#define OFS_UCSCTL4 (0x0008) /* UCS Control Register 4 */ +#define OFS_UCSCTL4_L OFS_UCSCTL4 +#define OFS_UCSCTL4_H OFS_UCSCTL4+1 +#define OFS_UCSCTL5 (0x000A) /* UCS Control Register 5 */ +#define OFS_UCSCTL5_L OFS_UCSCTL5 +#define OFS_UCSCTL5_H OFS_UCSCTL5+1 +#define OFS_UCSCTL6 (0x000C) /* UCS Control Register 6 */ +#define OFS_UCSCTL6_L OFS_UCSCTL6 +#define OFS_UCSCTL6_H OFS_UCSCTL6+1 +#define OFS_UCSCTL7 (0x000E) /* UCS Control Register 7 */ +#define OFS_UCSCTL7_L OFS_UCSCTL7 +#define OFS_UCSCTL7_H OFS_UCSCTL7+1 +#define OFS_UCSCTL8 (0x0010) /* UCS Control Register 8 */ +#define OFS_UCSCTL8_L OFS_UCSCTL8 +#define OFS_UCSCTL8_H OFS_UCSCTL8+1 + +/* UCSCTL0 Control Bits */ +//#define RESERVED (0x0001) /* RESERVED */ +//#define RESERVED (0x0002) /* RESERVED */ +//#define RESERVED (0x0004) /* RESERVED */ +#define MOD0 (0x0008) /* Modulation Bit Counter Bit : 0 */ +#define MOD1 (0x0010) /* Modulation Bit Counter Bit : 1 */ +#define MOD2 (0x0020) /* Modulation Bit Counter Bit : 2 */ +#define MOD3 (0x0040) /* Modulation Bit Counter Bit : 3 */ +#define MOD4 (0x0080) /* Modulation Bit Counter Bit : 4 */ +#define DCO0 (0x0100) /* DCO TAP Bit : 0 */ +#define DCO1 (0x0200) /* DCO TAP Bit : 1 */ +#define DCO2 (0x0400) /* DCO TAP Bit : 2 */ +#define DCO3 (0x0800) /* DCO TAP Bit : 3 */ +#define DCO4 (0x1000) /* DCO TAP Bit : 4 */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL0 Control Bits */ +//#define RESERVED (0x0001) /* RESERVED */ +//#define RESERVED (0x0002) /* RESERVED */ +//#define RESERVED (0x0004) /* RESERVED */ +#define MOD0_L (0x0008) /* Modulation Bit Counter Bit : 0 */ +#define MOD1_L (0x0010) /* Modulation Bit Counter Bit : 1 */ +#define MOD2_L (0x0020) /* Modulation Bit Counter Bit : 2 */ +#define MOD3_L (0x0040) /* Modulation Bit Counter Bit : 3 */ +#define MOD4_L (0x0080) /* Modulation Bit Counter Bit : 4 */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL0 Control Bits */ +//#define RESERVED (0x0001) /* RESERVED */ +//#define RESERVED (0x0002) /* RESERVED */ +//#define RESERVED (0x0004) /* RESERVED */ +#define DCO0_H (0x0001) /* DCO TAP Bit : 0 */ +#define DCO1_H (0x0002) /* DCO TAP Bit : 1 */ +#define DCO2_H (0x0004) /* DCO TAP Bit : 2 */ +#define DCO3_H (0x0008) /* DCO TAP Bit : 3 */ +#define DCO4_H (0x0010) /* DCO TAP Bit : 4 */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL1 Control Bits */ +#define DISMOD (0x0001) /* Disable Modulation */ +//#define RESERVED (0x0002) /* RESERVED */ +//#define RESERVED (0x0004) /* RESERVED */ +//#define RESERVED (0x0008) /* RESERVED */ +#define DCORSEL0 (0x0010) /* DCO Freq. Range Select Bit : 0 */ +#define DCORSEL1 (0x0020) /* DCO Freq. Range Select Bit : 1 */ +#define DCORSEL2 (0x0040) /* DCO Freq. Range Select Bit : 2 */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0100) /* RESERVED */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL1 Control Bits */ +#define DISMOD_L (0x0001) /* Disable Modulation */ +//#define RESERVED (0x0002) /* RESERVED */ +//#define RESERVED (0x0004) /* RESERVED */ +//#define RESERVED (0x0008) /* RESERVED */ +#define DCORSEL0_L (0x0010) /* DCO Freq. Range Select Bit : 0 */ +#define DCORSEL1_L (0x0020) /* DCO Freq. Range Select Bit : 1 */ +#define DCORSEL2_L (0x0040) /* DCO Freq. Range Select Bit : 2 */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0100) /* RESERVED */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +#define DCORSEL_0 (0x0000) /* DCO RSEL 0 */ +#define DCORSEL_1 (0x0010) /* DCO RSEL 1 */ +#define DCORSEL_2 (0x0020) /* DCO RSEL 2 */ +#define DCORSEL_3 (0x0030) /* DCO RSEL 3 */ +#define DCORSEL_4 (0x0040) /* DCO RSEL 4 */ +#define DCORSEL_5 (0x0050) /* DCO RSEL 5 */ +#define DCORSEL_6 (0x0060) /* DCO RSEL 6 */ +#define DCORSEL_7 (0x0070) /* DCO RSEL 7 */ + +/* UCSCTL2 Control Bits */ +#define FLLN0 (0x0001) /* FLL Multipier Bit : 0 */ +#define FLLN1 (0x0002) /* FLL Multipier Bit : 1 */ +#define FLLN2 (0x0004) /* FLL Multipier Bit : 2 */ +#define FLLN3 (0x0008) /* FLL Multipier Bit : 3 */ +#define FLLN4 (0x0010) /* FLL Multipier Bit : 4 */ +#define FLLN5 (0x0020) /* FLL Multipier Bit : 5 */ +#define FLLN6 (0x0040) /* FLL Multipier Bit : 6 */ +#define FLLN7 (0x0080) /* FLL Multipier Bit : 7 */ +#define FLLN8 (0x0100) /* FLL Multipier Bit : 8 */ +#define FLLN9 (0x0200) /* FLL Multipier Bit : 9 */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +#define FLLD0 (0x1000) /* Loop Divider Bit : 0 */ +#define FLLD1 (0x2000) /* Loop Divider Bit : 1 */ +#define FLLD2 (0x4000) /* Loop Divider Bit : 1 */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL2 Control Bits */ +#define FLLN0_L (0x0001) /* FLL Multipier Bit : 0 */ +#define FLLN1_L (0x0002) /* FLL Multipier Bit : 1 */ +#define FLLN2_L (0x0004) /* FLL Multipier Bit : 2 */ +#define FLLN3_L (0x0008) /* FLL Multipier Bit : 3 */ +#define FLLN4_L (0x0010) /* FLL Multipier Bit : 4 */ +#define FLLN5_L (0x0020) /* FLL Multipier Bit : 5 */ +#define FLLN6_L (0x0040) /* FLL Multipier Bit : 6 */ +#define FLLN7_L (0x0080) /* FLL Multipier Bit : 7 */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL2 Control Bits */ +#define FLLN8_H (0x0001) /* FLL Multipier Bit : 8 */ +#define FLLN9_H (0x0002) /* FLL Multipier Bit : 9 */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +#define FLLD0_H (0x0010) /* Loop Divider Bit : 0 */ +#define FLLD1_H (0x0020) /* Loop Divider Bit : 1 */ +#define FLLD2_H (0x0040) /* Loop Divider Bit : 1 */ +//#define RESERVED (0x8000) /* RESERVED */ + +#define FLLD_0 (0x0000) /* Multiply Selected Loop Freq. 1 */ +#define FLLD_1 (0x1000) /* Multiply Selected Loop Freq. 2 */ +#define FLLD_2 (0x2000) /* Multiply Selected Loop Freq. 4 */ +#define FLLD_3 (0x3000) /* Multiply Selected Loop Freq. 8 */ +#define FLLD_4 (0x4000) /* Multiply Selected Loop Freq. 16 */ +#define FLLD_5 (0x5000) /* Multiply Selected Loop Freq. 32 */ +#define FLLD_6 (0x6000) /* Multiply Selected Loop Freq. 32 */ +#define FLLD_7 (0x7000) /* Multiply Selected Loop Freq. 32 */ +#define FLLD__1 (0x0000) /* Multiply Selected Loop Freq. By 1 */ +#define FLLD__2 (0x1000) /* Multiply Selected Loop Freq. By 2 */ +#define FLLD__4 (0x2000) /* Multiply Selected Loop Freq. By 4 */ +#define FLLD__8 (0x3000) /* Multiply Selected Loop Freq. By 8 */ +#define FLLD__16 (0x4000) /* Multiply Selected Loop Freq. By 16 */ +#define FLLD__32 (0x5000) /* Multiply Selected Loop Freq. By 32 */ + +/* UCSCTL3 Control Bits */ +#define FLLREFDIV0 (0x0001) /* Reference Divider Bit : 0 */ +#define FLLREFDIV1 (0x0002) /* Reference Divider Bit : 1 */ +#define FLLREFDIV2 (0x0004) /* Reference Divider Bit : 2 */ +//#define RESERVED (0x0008) /* RESERVED */ +#define SELREF0 (0x0010) /* FLL Reference Clock Select Bit : 0 */ +#define SELREF1 (0x0020) /* FLL Reference Clock Select Bit : 1 */ +#define SELREF2 (0x0040) /* FLL Reference Clock Select Bit : 2 */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0100) /* RESERVED */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL3 Control Bits */ +#define FLLREFDIV0_L (0x0001) /* Reference Divider Bit : 0 */ +#define FLLREFDIV1_L (0x0002) /* Reference Divider Bit : 1 */ +#define FLLREFDIV2_L (0x0004) /* Reference Divider Bit : 2 */ +//#define RESERVED (0x0008) /* RESERVED */ +#define SELREF0_L (0x0010) /* FLL Reference Clock Select Bit : 0 */ +#define SELREF1_L (0x0020) /* FLL Reference Clock Select Bit : 1 */ +#define SELREF2_L (0x0040) /* FLL Reference Clock Select Bit : 2 */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0100) /* RESERVED */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +#define FLLREFDIV_0 (0x0000) /* Reference Divider: f(LFCLK)/1 */ +#define FLLREFDIV_1 (0x0001) /* Reference Divider: f(LFCLK)/2 */ +#define FLLREFDIV_2 (0x0002) /* Reference Divider: f(LFCLK)/4 */ +#define FLLREFDIV_3 (0x0003) /* Reference Divider: f(LFCLK)/8 */ +#define FLLREFDIV_4 (0x0004) /* Reference Divider: f(LFCLK)/12 */ +#define FLLREFDIV_5 (0x0005) /* Reference Divider: f(LFCLK)/16 */ +#define FLLREFDIV_6 (0x0006) /* Reference Divider: f(LFCLK)/16 */ +#define FLLREFDIV_7 (0x0007) /* Reference Divider: f(LFCLK)/16 */ +#define FLLREFDIV__1 (0x0000) /* Reference Divider: f(LFCLK)/1 */ +#define FLLREFDIV__2 (0x0001) /* Reference Divider: f(LFCLK)/2 */ +#define FLLREFDIV__4 (0x0002) /* Reference Divider: f(LFCLK)/4 */ +#define FLLREFDIV__8 (0x0003) /* Reference Divider: f(LFCLK)/8 */ +#define FLLREFDIV__12 (0x0004) /* Reference Divider: f(LFCLK)/12 */ +#define FLLREFDIV__16 (0x0005) /* Reference Divider: f(LFCLK)/16 */ +#define SELREF_0 (0x0000) /* FLL Reference Clock Select 0 */ +#define SELREF_1 (0x0010) /* FLL Reference Clock Select 1 */ +#define SELREF_2 (0x0020) /* FLL Reference Clock Select 2 */ +#define SELREF_3 (0x0030) /* FLL Reference Clock Select 3 */ +#define SELREF_4 (0x0040) /* FLL Reference Clock Select 4 */ +#define SELREF_5 (0x0050) /* FLL Reference Clock Select 5 */ +#define SELREF_6 (0x0060) /* FLL Reference Clock Select 6 */ +#define SELREF_7 (0x0070) /* FLL Reference Clock Select 7 */ +#define SELREF__XT1CLK (0x0000) /* Multiply Selected Loop Freq. By XT1CLK */ +#define SELREF__REFOCLK (0x0020) /* Multiply Selected Loop Freq. By REFOCLK */ +#define SELREF__XT2CLK (0x0050) /* Multiply Selected Loop Freq. By XT2CLK */ + +/* UCSCTL4 Control Bits */ +#define SELM0 (0x0001) /* MCLK Source Select Bit: 0 */ +#define SELM1 (0x0002) /* MCLK Source Select Bit: 1 */ +#define SELM2 (0x0004) /* MCLK Source Select Bit: 2 */ +//#define RESERVED (0x0008) /* RESERVED */ +#define SELS0 (0x0010) /* SMCLK Source Select Bit: 0 */ +#define SELS1 (0x0020) /* SMCLK Source Select Bit: 1 */ +#define SELS2 (0x0040) /* SMCLK Source Select Bit: 2 */ +//#define RESERVED (0x0080) /* RESERVED */ +#define SELA0 (0x0100) /* ACLK Source Select Bit: 0 */ +#define SELA1 (0x0200) /* ACLK Source Select Bit: 1 */ +#define SELA2 (0x0400) /* ACLK Source Select Bit: 2 */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL4 Control Bits */ +#define SELM0_L (0x0001) /* MCLK Source Select Bit: 0 */ +#define SELM1_L (0x0002) /* MCLK Source Select Bit: 1 */ +#define SELM2_L (0x0004) /* MCLK Source Select Bit: 2 */ +//#define RESERVED (0x0008) /* RESERVED */ +#define SELS0_L (0x0010) /* SMCLK Source Select Bit: 0 */ +#define SELS1_L (0x0020) /* SMCLK Source Select Bit: 1 */ +#define SELS2_L (0x0040) /* SMCLK Source Select Bit: 2 */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL4 Control Bits */ +//#define RESERVED (0x0008) /* RESERVED */ +//#define RESERVED (0x0080) /* RESERVED */ +#define SELA0_H (0x0001) /* ACLK Source Select Bit: 0 */ +#define SELA1_H (0x0002) /* ACLK Source Select Bit: 1 */ +#define SELA2_H (0x0004) /* ACLK Source Select Bit: 2 */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +#define SELM_0 (0x0000) /* MCLK Source Select 0 */ +#define SELM_1 (0x0001) /* MCLK Source Select 1 */ +#define SELM_2 (0x0002) /* MCLK Source Select 2 */ +#define SELM_3 (0x0003) /* MCLK Source Select 3 */ +#define SELM_4 (0x0004) /* MCLK Source Select 4 */ +#define SELM_5 (0x0005) /* MCLK Source Select 5 */ +#define SELM_6 (0x0006) /* MCLK Source Select 6 */ +#define SELM_7 (0x0007) /* MCLK Source Select 7 */ +#define SELM__XT1CLK (0x0000) /* MCLK Source Select XT1CLK */ +#define SELM__VLOCLK (0x0001) /* MCLK Source Select VLOCLK */ +#define SELM__REFOCLK (0x0002) /* MCLK Source Select REFOCLK */ +#define SELM__DCOCLK (0x0003) /* MCLK Source Select DCOCLK */ +#define SELM__DCOCLKDIV (0x0004) /* MCLK Source Select DCOCLKDIV */ +#define SELM__XT2CLK (0x0005) /* MCLK Source Select XT2CLK */ + +#define SELS_0 (0x0000) /* SMCLK Source Select 0 */ +#define SELS_1 (0x0010) /* SMCLK Source Select 1 */ +#define SELS_2 (0x0020) /* SMCLK Source Select 2 */ +#define SELS_3 (0x0030) /* SMCLK Source Select 3 */ +#define SELS_4 (0x0040) /* SMCLK Source Select 4 */ +#define SELS_5 (0x0050) /* SMCLK Source Select 5 */ +#define SELS_6 (0x0060) /* SMCLK Source Select 6 */ +#define SELS_7 (0x0070) /* SMCLK Source Select 7 */ +#define SELS__XT1CLK (0x0000) /* SMCLK Source Select XT1CLK */ +#define SELS__VLOCLK (0x0010) /* SMCLK Source Select VLOCLK */ +#define SELS__REFOCLK (0x0020) /* SMCLK Source Select REFOCLK */ +#define SELS__DCOCLK (0x0030) /* SMCLK Source Select DCOCLK */ +#define SELS__DCOCLKDIV (0x0040) /* SMCLK Source Select DCOCLKDIV */ +#define SELS__XT2CLK (0x0050) /* SMCLK Source Select XT2CLK */ + +#define SELA_0 (0x0000) /* ACLK Source Select 0 */ +#define SELA_1 (0x0100) /* ACLK Source Select 1 */ +#define SELA_2 (0x0200) /* ACLK Source Select 2 */ +#define SELA_3 (0x0300) /* ACLK Source Select 3 */ +#define SELA_4 (0x0400) /* ACLK Source Select 4 */ +#define SELA_5 (0x0500) /* ACLK Source Select 5 */ +#define SELA_6 (0x0600) /* ACLK Source Select 6 */ +#define SELA_7 (0x0700) /* ACLK Source Select 7 */ +#define SELA__XT1CLK (0x0000) /* ACLK Source Select XT1CLK */ +#define SELA__VLOCLK (0x0100) /* ACLK Source Select VLOCLK */ +#define SELA__REFOCLK (0x0200) /* ACLK Source Select REFOCLK */ +#define SELA__DCOCLK (0x0300) /* ACLK Source Select DCOCLK */ +#define SELA__DCOCLKDIV (0x0400) /* ACLK Source Select DCOCLKDIV */ +#define SELA__XT2CLK (0x0500) /* ACLK Source Select XT2CLK */ + +/* UCSCTL5 Control Bits */ +#define DIVM0 (0x0001) /* MCLK Divider Bit: 0 */ +#define DIVM1 (0x0002) /* MCLK Divider Bit: 1 */ +#define DIVM2 (0x0004) /* MCLK Divider Bit: 2 */ +//#define RESERVED (0x0008) /* RESERVED */ +#define DIVS0 (0x0010) /* SMCLK Divider Bit: 0 */ +#define DIVS1 (0x0020) /* SMCLK Divider Bit: 1 */ +#define DIVS2 (0x0040) /* SMCLK Divider Bit: 2 */ +//#define RESERVED (0x0080) /* RESERVED */ +#define DIVA0 (0x0100) /* ACLK Divider Bit: 0 */ +#define DIVA1 (0x0200) /* ACLK Divider Bit: 1 */ +#define DIVA2 (0x0400) /* ACLK Divider Bit: 2 */ +//#define RESERVED (0x0800) /* RESERVED */ +#define DIVPA0 (0x1000) /* ACLK from Pin Divider Bit: 0 */ +#define DIVPA1 (0x2000) /* ACLK from Pin Divider Bit: 1 */ +#define DIVPA2 (0x4000) /* ACLK from Pin Divider Bit: 2 */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL5 Control Bits */ +#define DIVM0_L (0x0001) /* MCLK Divider Bit: 0 */ +#define DIVM1_L (0x0002) /* MCLK Divider Bit: 1 */ +#define DIVM2_L (0x0004) /* MCLK Divider Bit: 2 */ +//#define RESERVED (0x0008) /* RESERVED */ +#define DIVS0_L (0x0010) /* SMCLK Divider Bit: 0 */ +#define DIVS1_L (0x0020) /* SMCLK Divider Bit: 1 */ +#define DIVS2_L (0x0040) /* SMCLK Divider Bit: 2 */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL5 Control Bits */ +//#define RESERVED (0x0008) /* RESERVED */ +//#define RESERVED (0x0080) /* RESERVED */ +#define DIVA0_H (0x0001) /* ACLK Divider Bit: 0 */ +#define DIVA1_H (0x0002) /* ACLK Divider Bit: 1 */ +#define DIVA2_H (0x0004) /* ACLK Divider Bit: 2 */ +//#define RESERVED (0x0800) /* RESERVED */ +#define DIVPA0_H (0x0010) /* ACLK from Pin Divider Bit: 0 */ +#define DIVPA1_H (0x0020) /* ACLK from Pin Divider Bit: 1 */ +#define DIVPA2_H (0x0040) /* ACLK from Pin Divider Bit: 2 */ +//#define RESERVED (0x8000) /* RESERVED */ + +#define DIVM_0 (0x0000) /* MCLK Source Divider 0 */ +#define DIVM_1 (0x0001) /* MCLK Source Divider 1 */ +#define DIVM_2 (0x0002) /* MCLK Source Divider 2 */ +#define DIVM_3 (0x0003) /* MCLK Source Divider 3 */ +#define DIVM_4 (0x0004) /* MCLK Source Divider 4 */ +#define DIVM_5 (0x0005) /* MCLK Source Divider 5 */ +#define DIVM_6 (0x0006) /* MCLK Source Divider 6 */ +#define DIVM_7 (0x0007) /* MCLK Source Divider 7 */ +#define DIVM__1 (0x0000) /* MCLK Source Divider f(MCLK)/1 */ +#define DIVM__2 (0x0001) /* MCLK Source Divider f(MCLK)/2 */ +#define DIVM__4 (0x0002) /* MCLK Source Divider f(MCLK)/4 */ +#define DIVM__8 (0x0003) /* MCLK Source Divider f(MCLK)/8 */ +#define DIVM__16 (0x0004) /* MCLK Source Divider f(MCLK)/16 */ +#define DIVM__32 (0x0005) /* MCLK Source Divider f(MCLK)/32 */ + +#define DIVS_0 (0x0000) /* SMCLK Source Divider 0 */ +#define DIVS_1 (0x0010) /* SMCLK Source Divider 1 */ +#define DIVS_2 (0x0020) /* SMCLK Source Divider 2 */ +#define DIVS_3 (0x0030) /* SMCLK Source Divider 3 */ +#define DIVS_4 (0x0040) /* SMCLK Source Divider 4 */ +#define DIVS_5 (0x0050) /* SMCLK Source Divider 5 */ +#define DIVS_6 (0x0060) /* SMCLK Source Divider 6 */ +#define DIVS_7 (0x0070) /* SMCLK Source Divider 7 */ +#define DIVS__1 (0x0000) /* SMCLK Source Divider f(SMCLK)/1 */ +#define DIVS__2 (0x0010) /* SMCLK Source Divider f(SMCLK)/2 */ +#define DIVS__4 (0x0020) /* SMCLK Source Divider f(SMCLK)/4 */ +#define DIVS__8 (0x0030) /* SMCLK Source Divider f(SMCLK)/8 */ +#define DIVS__16 (0x0040) /* SMCLK Source Divider f(SMCLK)/16 */ +#define DIVS__32 (0x0050) /* SMCLK Source Divider f(SMCLK)/32 */ + +#define DIVA_0 (0x0000) /* ACLK Source Divider 0 */ +#define DIVA_1 (0x0100) /* ACLK Source Divider 1 */ +#define DIVA_2 (0x0200) /* ACLK Source Divider 2 */ +#define DIVA_3 (0x0300) /* ACLK Source Divider 3 */ +#define DIVA_4 (0x0400) /* ACLK Source Divider 4 */ +#define DIVA_5 (0x0500) /* ACLK Source Divider 5 */ +#define DIVA_6 (0x0600) /* ACLK Source Divider 6 */ +#define DIVA_7 (0x0700) /* ACLK Source Divider 7 */ +#define DIVA__1 (0x0000) /* ACLK Source Divider f(ACLK)/1 */ +#define DIVA__2 (0x0100) /* ACLK Source Divider f(ACLK)/2 */ +#define DIVA__4 (0x0200) /* ACLK Source Divider f(ACLK)/4 */ +#define DIVA__8 (0x0300) /* ACLK Source Divider f(ACLK)/8 */ +#define DIVA__16 (0x0400) /* ACLK Source Divider f(ACLK)/16 */ +#define DIVA__32 (0x0500) /* ACLK Source Divider f(ACLK)/32 */ + +#define DIVPA_0 (0x0000) /* ACLK from Pin Source Divider 0 */ +#define DIVPA_1 (0x1000) /* ACLK from Pin Source Divider 1 */ +#define DIVPA_2 (0x2000) /* ACLK from Pin Source Divider 2 */ +#define DIVPA_3 (0x3000) /* ACLK from Pin Source Divider 3 */ +#define DIVPA_4 (0x4000) /* ACLK from Pin Source Divider 4 */ +#define DIVPA_5 (0x5000) /* ACLK from Pin Source Divider 5 */ +#define DIVPA_6 (0x6000) /* ACLK from Pin Source Divider 6 */ +#define DIVPA_7 (0x7000) /* ACLK from Pin Source Divider 7 */ +#define DIVPA__1 (0x0000) /* ACLK from Pin Source Divider f(ACLK)/1 */ +#define DIVPA__2 (0x1000) /* ACLK from Pin Source Divider f(ACLK)/2 */ +#define DIVPA__4 (0x2000) /* ACLK from Pin Source Divider f(ACLK)/4 */ +#define DIVPA__8 (0x3000) /* ACLK from Pin Source Divider f(ACLK)/8 */ +#define DIVPA__16 (0x4000) /* ACLK from Pin Source Divider f(ACLK)/16 */ +#define DIVPA__32 (0x5000) /* ACLK from Pin Source Divider f(ACLK)/32 */ + +/* UCSCTL6 Control Bits */ +#define XT1OFF (0x0001) /* High Frequency Oscillator 1 (XT1) disable */ +#define SMCLKOFF (0x0002) /* SMCLK Off */ +#define XCAP0 (0x0004) /* XIN/XOUT Cap Bit: 0 */ +#define XCAP1 (0x0008) /* XIN/XOUT Cap Bit: 1 */ +#define XT1BYPASS (0x0010) /* XT1 bypass mode : 0: internal 1:sourced from external pin */ +#define XTS (0x0020) /* 1: Selects high-freq. oscillator */ +#define XT1DRIVE0 (0x0040) /* XT1 Drive Level mode Bit 0 */ +#define XT1DRIVE1 (0x0080) /* XT1 Drive Level mode Bit 1 */ +#define XT2OFF (0x0100) /* High Frequency Oscillator 2 (XT2) disable */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +#define XT2BYPASS (0x1000) /* XT2 bypass mode : 0: internal 1:sourced from external pin */ +//#define RESERVED (0x2000) /* RESERVED */ +#define XT2DRIVE0 (0x4000) /* XT2 Drive Level mode Bit 0 */ +#define XT2DRIVE1 (0x8000) /* XT2 Drive Level mode Bit 1 */ + +/* UCSCTL6 Control Bits */ +#define XT1OFF_L (0x0001) /* High Frequency Oscillator 1 (XT1) disable */ +#define SMCLKOFF_L (0x0002) /* SMCLK Off */ +#define XCAP0_L (0x0004) /* XIN/XOUT Cap Bit: 0 */ +#define XCAP1_L (0x0008) /* XIN/XOUT Cap Bit: 1 */ +#define XT1BYPASS_L (0x0010) /* XT1 bypass mode : 0: internal 1:sourced from external pin */ +#define XTS_L (0x0020) /* 1: Selects high-freq. oscillator */ +#define XT1DRIVE0_L (0x0040) /* XT1 Drive Level mode Bit 0 */ +#define XT1DRIVE1_L (0x0080) /* XT1 Drive Level mode Bit 1 */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ + +/* UCSCTL6 Control Bits */ +#define XT2OFF_H (0x0001) /* High Frequency Oscillator 2 (XT2) disable */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +#define XT2BYPASS_H (0x0010) /* XT2 bypass mode : 0: internal 1:sourced from external pin */ +//#define RESERVED (0x2000) /* RESERVED */ +#define XT2DRIVE0_H (0x0040) /* XT2 Drive Level mode Bit 0 */ +#define XT2DRIVE1_H (0x0080) /* XT2 Drive Level mode Bit 1 */ + +#define XCAP_0 (0x0000) /* XIN/XOUT Cap 0 */ +#define XCAP_1 (0x0004) /* XIN/XOUT Cap 1 */ +#define XCAP_2 (0x0008) /* XIN/XOUT Cap 2 */ +#define XCAP_3 (0x000C) /* XIN/XOUT Cap 3 */ +#define XT1DRIVE_0 (0x0000) /* XT1 Drive Level mode: 0 */ +#define XT1DRIVE_1 (0x0040) /* XT1 Drive Level mode: 1 */ +#define XT1DRIVE_2 (0x0080) /* XT1 Drive Level mode: 2 */ +#define XT1DRIVE_3 (0x00C0) /* XT1 Drive Level mode: 3 */ +#define XT2DRIVE_0 (0x0000) /* XT2 Drive Level mode: 0 */ +#define XT2DRIVE_1 (0x4000) /* XT2 Drive Level mode: 1 */ +#define XT2DRIVE_2 (0x8000) /* XT2 Drive Level mode: 2 */ +#define XT2DRIVE_3 (0xC000) /* XT2 Drive Level mode: 3 */ + +/* UCSCTL7 Control Bits */ +#define DCOFFG (0x0001) /* DCO Fault Flag */ +#define XT1LFOFFG (0x0002) /* XT1 Low Frequency Oscillator Fault Flag */ +#define XT1HFOFFG (0x0004) /* XT1 High Frequency Oscillator 1 Fault Flag */ +#define XT2OFFG (0x0008) /* High Frequency Oscillator 2 Fault Flag */ +//#define RESERVED (0x0010) /* RESERVED */ +//#define RESERVED (0x0020) /* RESERVED */ +//#define RESERVED (0x0040) /* RESERVED */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0100) /* RESERVED */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL7 Control Bits */ +#define DCOFFG_L (0x0001) /* DCO Fault Flag */ +#define XT1LFOFFG_L (0x0002) /* XT1 Low Frequency Oscillator Fault Flag */ +#define XT1HFOFFG_L (0x0004) /* XT1 High Frequency Oscillator 1 Fault Flag */ +#define XT2OFFG_L (0x0008) /* High Frequency Oscillator 2 Fault Flag */ +//#define RESERVED (0x0010) /* RESERVED */ +//#define RESERVED (0x0020) /* RESERVED */ +//#define RESERVED (0x0040) /* RESERVED */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0100) /* RESERVED */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL8 Control Bits */ +#define ACLKREQEN (0x0001) /* ACLK Clock Request Enable */ +#define MCLKREQEN (0x0002) /* MCLK Clock Request Enable */ +#define SMCLKREQEN (0x0004) /* SMCLK Clock Request Enable */ +#define MODOSCREQEN (0x0008) /* MODOSC Clock Request Enable */ +//#define RESERVED (0x0010) /* RESERVED */ +//#define RESERVED (0x0020) /* RESERVED */ +//#define RESERVED (0x0040) /* RESERVED */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0100) /* RESERVED */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL8 Control Bits */ +#define ACLKREQEN_L (0x0001) /* ACLK Clock Request Enable */ +#define MCLKREQEN_L (0x0002) /* MCLK Clock Request Enable */ +#define SMCLKREQEN_L (0x0004) /* SMCLK Clock Request Enable */ +#define MODOSCREQEN_L (0x0008) /* MODOSC Clock Request Enable */ +//#define RESERVED (0x0010) /* RESERVED */ +//#define RESERVED (0x0020) /* RESERVED */ +//#define RESERVED (0x0040) /* RESERVED */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0100) /* RESERVED */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +#endif +/************************************************************ +* UNIFIED CLOCK SYSTEM FOR Radio Devices +************************************************************/ +#ifdef __MSP430_HAS_UCS_RF__ /* Definition to show that Module is available */ + +#define OFS_UCSCTL0 (0x0000) /* UCS Control Register 0 */ +#define OFS_UCSCTL0_L OFS_UCSCTL0 +#define OFS_UCSCTL0_H OFS_UCSCTL0+1 +#define OFS_UCSCTL1 (0x0002) /* UCS Control Register 1 */ +#define OFS_UCSCTL1_L OFS_UCSCTL1 +#define OFS_UCSCTL1_H OFS_UCSCTL1+1 +#define OFS_UCSCTL2 (0x0004) /* UCS Control Register 2 */ +#define OFS_UCSCTL2_L OFS_UCSCTL2 +#define OFS_UCSCTL2_H OFS_UCSCTL2+1 +#define OFS_UCSCTL3 (0x0006) /* UCS Control Register 3 */ +#define OFS_UCSCTL3_L OFS_UCSCTL3 +#define OFS_UCSCTL3_H OFS_UCSCTL3+1 +#define OFS_UCSCTL4 (0x0008) /* UCS Control Register 4 */ +#define OFS_UCSCTL4_L OFS_UCSCTL4 +#define OFS_UCSCTL4_H OFS_UCSCTL4+1 +#define OFS_UCSCTL5 (0x000A) /* UCS Control Register 5 */ +#define OFS_UCSCTL5_L OFS_UCSCTL5 +#define OFS_UCSCTL5_H OFS_UCSCTL5+1 +#define OFS_UCSCTL6 (0x000C) /* UCS Control Register 6 */ +#define OFS_UCSCTL6_L OFS_UCSCTL6 +#define OFS_UCSCTL6_H OFS_UCSCTL6+1 +#define OFS_UCSCTL7 (0x000E) /* UCS Control Register 7 */ +#define OFS_UCSCTL7_L OFS_UCSCTL7 +#define OFS_UCSCTL7_H OFS_UCSCTL7+1 +#define OFS_UCSCTL8 (0x0010) /* UCS Control Register 8 */ +#define OFS_UCSCTL8_L OFS_UCSCTL8 +#define OFS_UCSCTL8_H OFS_UCSCTL8+1 + +/* UCSCTL0 Control Bits */ +//#define RESERVED (0x0001) /* RESERVED */ +//#define RESERVED (0x0002) /* RESERVED */ +//#define RESERVED (0x0004) /* RESERVED */ +#define MOD0 (0x0008) /* Modulation Bit Counter Bit : 0 */ +#define MOD1 (0x0010) /* Modulation Bit Counter Bit : 1 */ +#define MOD2 (0x0020) /* Modulation Bit Counter Bit : 2 */ +#define MOD3 (0x0040) /* Modulation Bit Counter Bit : 3 */ +#define MOD4 (0x0080) /* Modulation Bit Counter Bit : 4 */ +#define DCO0 (0x0100) /* DCO TAP Bit : 0 */ +#define DCO1 (0x0200) /* DCO TAP Bit : 1 */ +#define DCO2 (0x0400) /* DCO TAP Bit : 2 */ +#define DCO3 (0x0800) /* DCO TAP Bit : 3 */ +#define DCO4 (0x1000) /* DCO TAP Bit : 4 */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL0 Control Bits */ +//#define RESERVED (0x0001) /* RESERVED */ +//#define RESERVED (0x0002) /* RESERVED */ +//#define RESERVED (0x0004) /* RESERVED */ +#define MOD0_L (0x0008) /* Modulation Bit Counter Bit : 0 */ +#define MOD1_L (0x0010) /* Modulation Bit Counter Bit : 1 */ +#define MOD2_L (0x0020) /* Modulation Bit Counter Bit : 2 */ +#define MOD3_L (0x0040) /* Modulation Bit Counter Bit : 3 */ +#define MOD4_L (0x0080) /* Modulation Bit Counter Bit : 4 */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL0 Control Bits */ +//#define RESERVED (0x0001) /* RESERVED */ +//#define RESERVED (0x0002) /* RESERVED */ +//#define RESERVED (0x0004) /* RESERVED */ +#define DCO0_H (0x0001) /* DCO TAP Bit : 0 */ +#define DCO1_H (0x0002) /* DCO TAP Bit : 1 */ +#define DCO2_H (0x0004) /* DCO TAP Bit : 2 */ +#define DCO3_H (0x0008) /* DCO TAP Bit : 3 */ +#define DCO4_H (0x0010) /* DCO TAP Bit : 4 */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL1 Control Bits */ +#define DISMOD (0x0001) /* Disable Modulation */ +//#define RESERVED (0x0002) /* RESERVED */ +//#define RESERVED (0x0004) /* RESERVED */ +//#define RESERVED (0x0008) /* RESERVED */ +#define DCORSEL0 (0x0010) /* DCO Freq. Range Select Bit : 0 */ +#define DCORSEL1 (0x0020) /* DCO Freq. Range Select Bit : 1 */ +#define DCORSEL2 (0x0040) /* DCO Freq. Range Select Bit : 2 */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0100) /* RESERVED */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL1 Control Bits */ +#define DISMOD_L (0x0001) /* Disable Modulation */ +//#define RESERVED (0x0002) /* RESERVED */ +//#define RESERVED (0x0004) /* RESERVED */ +//#define RESERVED (0x0008) /* RESERVED */ +#define DCORSEL0_L (0x0010) /* DCO Freq. Range Select Bit : 0 */ +#define DCORSEL1_L (0x0020) /* DCO Freq. Range Select Bit : 1 */ +#define DCORSEL2_L (0x0040) /* DCO Freq. Range Select Bit : 2 */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0100) /* RESERVED */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +#define DCORSEL_0 (0x0000) /* DCO RSEL 0 */ +#define DCORSEL_1 (0x0010) /* DCO RSEL 1 */ +#define DCORSEL_2 (0x0020) /* DCO RSEL 2 */ +#define DCORSEL_3 (0x0030) /* DCO RSEL 3 */ +#define DCORSEL_4 (0x0040) /* DCO RSEL 4 */ +#define DCORSEL_5 (0x0050) /* DCO RSEL 5 */ +#define DCORSEL_6 (0x0060) /* DCO RSEL 6 */ +#define DCORSEL_7 (0x0070) /* DCO RSEL 7 */ + +/* UCSCTL2 Control Bits */ +#define FLLN0 (0x0001) /* FLL Multipier Bit : 0 */ +#define FLLN1 (0x0002) /* FLL Multipier Bit : 1 */ +#define FLLN2 (0x0004) /* FLL Multipier Bit : 2 */ +#define FLLN3 (0x0008) /* FLL Multipier Bit : 3 */ +#define FLLN4 (0x0010) /* FLL Multipier Bit : 4 */ +#define FLLN5 (0x0020) /* FLL Multipier Bit : 5 */ +#define FLLN6 (0x0040) /* FLL Multipier Bit : 6 */ +#define FLLN7 (0x0080) /* FLL Multipier Bit : 7 */ +#define FLLN8 (0x0100) /* FLL Multipier Bit : 8 */ +#define FLLN9 (0x0200) /* FLL Multipier Bit : 9 */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +#define FLLD0 (0x1000) /* Loop Divider Bit : 0 */ +#define FLLD1 (0x2000) /* Loop Divider Bit : 1 */ +#define FLLD2 (0x4000) /* Loop Divider Bit : 1 */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL2 Control Bits */ +#define FLLN0_L (0x0001) /* FLL Multipier Bit : 0 */ +#define FLLN1_L (0x0002) /* FLL Multipier Bit : 1 */ +#define FLLN2_L (0x0004) /* FLL Multipier Bit : 2 */ +#define FLLN3_L (0x0008) /* FLL Multipier Bit : 3 */ +#define FLLN4_L (0x0010) /* FLL Multipier Bit : 4 */ +#define FLLN5_L (0x0020) /* FLL Multipier Bit : 5 */ +#define FLLN6_L (0x0040) /* FLL Multipier Bit : 6 */ +#define FLLN7_L (0x0080) /* FLL Multipier Bit : 7 */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL2 Control Bits */ +#define FLLN8_H (0x0001) /* FLL Multipier Bit : 8 */ +#define FLLN9_H (0x0002) /* FLL Multipier Bit : 9 */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +#define FLLD0_H (0x0010) /* Loop Divider Bit : 0 */ +#define FLLD1_H (0x0020) /* Loop Divider Bit : 1 */ +#define FLLD2_H (0x0040) /* Loop Divider Bit : 1 */ +//#define RESERVED (0x8000) /* RESERVED */ + +#define FLLD_0 (0x0000) /* Multiply Selected Loop Freq. 1 */ +#define FLLD_1 (0x1000) /* Multiply Selected Loop Freq. 2 */ +#define FLLD_2 (0x2000) /* Multiply Selected Loop Freq. 4 */ +#define FLLD_3 (0x3000) /* Multiply Selected Loop Freq. 8 */ +#define FLLD_4 (0x4000) /* Multiply Selected Loop Freq. 16 */ +#define FLLD_5 (0x5000) /* Multiply Selected Loop Freq. 32 */ +#define FLLD_6 (0x6000) /* Multiply Selected Loop Freq. 32 */ +#define FLLD_7 (0x7000) /* Multiply Selected Loop Freq. 32 */ +#define FLLD__1 (0x0000) /* Multiply Selected Loop Freq. By 1 */ +#define FLLD__2 (0x1000) /* Multiply Selected Loop Freq. By 2 */ +#define FLLD__4 (0x2000) /* Multiply Selected Loop Freq. By 4 */ +#define FLLD__8 (0x3000) /* Multiply Selected Loop Freq. By 8 */ +#define FLLD__16 (0x4000) /* Multiply Selected Loop Freq. By 16 */ +#define FLLD__32 (0x5000) /* Multiply Selected Loop Freq. By 32 */ + +/* UCSCTL3 Control Bits */ +#define FLLREFDIV0 (0x0001) /* Reference Divider Bit : 0 */ +#define FLLREFDIV1 (0x0002) /* Reference Divider Bit : 1 */ +#define FLLREFDIV2 (0x0004) /* Reference Divider Bit : 2 */ +//#define RESERVED (0x0008) /* RESERVED */ +#define SELREF0 (0x0010) /* FLL Reference Clock Select Bit : 0 */ +#define SELREF1 (0x0020) /* FLL Reference Clock Select Bit : 1 */ +#define SELREF2 (0x0040) /* FLL Reference Clock Select Bit : 2 */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0100) /* RESERVED */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL3 Control Bits */ +#define FLLREFDIV0_L (0x0001) /* Reference Divider Bit : 0 */ +#define FLLREFDIV1_L (0x0002) /* Reference Divider Bit : 1 */ +#define FLLREFDIV2_L (0x0004) /* Reference Divider Bit : 2 */ +//#define RESERVED (0x0008) /* RESERVED */ +#define SELREF0_L (0x0010) /* FLL Reference Clock Select Bit : 0 */ +#define SELREF1_L (0x0020) /* FLL Reference Clock Select Bit : 1 */ +#define SELREF2_L (0x0040) /* FLL Reference Clock Select Bit : 2 */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0100) /* RESERVED */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +#define FLLREFDIV_0 (0x0000) /* Reference Divider: f(LFCLK)/1 */ +#define FLLREFDIV_1 (0x0001) /* Reference Divider: f(LFCLK)/2 */ +#define FLLREFDIV_2 (0x0002) /* Reference Divider: f(LFCLK)/4 */ +#define FLLREFDIV_3 (0x0003) /* Reference Divider: f(LFCLK)/8 */ +#define FLLREFDIV_4 (0x0004) /* Reference Divider: f(LFCLK)/12 */ +#define FLLREFDIV_5 (0x0005) /* Reference Divider: f(LFCLK)/16 */ +#define FLLREFDIV_6 (0x0006) /* Reference Divider: f(LFCLK)/16 */ +#define FLLREFDIV_7 (0x0007) /* Reference Divider: f(LFCLK)/16 */ +#define FLLREFDIV__1 (0x0000) /* Reference Divider: f(LFCLK)/1 */ +#define FLLREFDIV__2 (0x0001) /* Reference Divider: f(LFCLK)/2 */ +#define FLLREFDIV__4 (0x0002) /* Reference Divider: f(LFCLK)/4 */ +#define FLLREFDIV__8 (0x0003) /* Reference Divider: f(LFCLK)/8 */ +#define FLLREFDIV__12 (0x0004) /* Reference Divider: f(LFCLK)/12 */ +#define FLLREFDIV__16 (0x0005) /* Reference Divider: f(LFCLK)/16 */ +#define SELREF_0 (0x0000) /* FLL Reference Clock Select 0 */ +#define SELREF_1 (0x0010) /* FLL Reference Clock Select 1 */ +#define SELREF_2 (0x0020) /* FLL Reference Clock Select 2 */ +#define SELREF_3 (0x0030) /* FLL Reference Clock Select 3 */ +#define SELREF_4 (0x0040) /* FLL Reference Clock Select 4 */ +#define SELREF_5 (0x0050) /* FLL Reference Clock Select 5 */ +#define SELREF_6 (0x0060) /* FLL Reference Clock Select 6 */ +#define SELREF_7 (0x0070) /* FLL Reference Clock Select 7 */ +#define SELREF__XT1CLK (0x0000) /* Multiply Selected Loop Freq. By XT1CLK */ +#define SELREF__REFOCLK (0x0020) /* Multiply Selected Loop Freq. By REFOCLK */ +#define SELREF__XT2CLK (0x0050) /* Multiply Selected Loop Freq. By XT2CLK */ + +/* UCSCTL4 Control Bits */ +#define SELM0 (0x0001) /* MCLK Source Select Bit: 0 */ +#define SELM1 (0x0002) /* MCLK Source Select Bit: 1 */ +#define SELM2 (0x0004) /* MCLK Source Select Bit: 2 */ +//#define RESERVED (0x0008) /* RESERVED */ +#define SELS0 (0x0010) /* SMCLK Source Select Bit: 0 */ +#define SELS1 (0x0020) /* SMCLK Source Select Bit: 1 */ +#define SELS2 (0x0040) /* SMCLK Source Select Bit: 2 */ +//#define RESERVED (0x0080) /* RESERVED */ +#define SELA0 (0x0100) /* ACLK Source Select Bit: 0 */ +#define SELA1 (0x0200) /* ACLK Source Select Bit: 1 */ +#define SELA2 (0x0400) /* ACLK Source Select Bit: 2 */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL4 Control Bits */ +#define SELM0_L (0x0001) /* MCLK Source Select Bit: 0 */ +#define SELM1_L (0x0002) /* MCLK Source Select Bit: 1 */ +#define SELM2_L (0x0004) /* MCLK Source Select Bit: 2 */ +//#define RESERVED (0x0008) /* RESERVED */ +#define SELS0_L (0x0010) /* SMCLK Source Select Bit: 0 */ +#define SELS1_L (0x0020) /* SMCLK Source Select Bit: 1 */ +#define SELS2_L (0x0040) /* SMCLK Source Select Bit: 2 */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL4 Control Bits */ +//#define RESERVED (0x0008) /* RESERVED */ +//#define RESERVED (0x0080) /* RESERVED */ +#define SELA0_H (0x0001) /* ACLK Source Select Bit: 0 */ +#define SELA1_H (0x0002) /* ACLK Source Select Bit: 1 */ +#define SELA2_H (0x0004) /* ACLK Source Select Bit: 2 */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +#define SELM_0 (0x0000) /* MCLK Source Select 0 */ +#define SELM_1 (0x0001) /* MCLK Source Select 1 */ +#define SELM_2 (0x0002) /* MCLK Source Select 2 */ +#define SELM_3 (0x0003) /* MCLK Source Select 3 */ +#define SELM_4 (0x0004) /* MCLK Source Select 4 */ +#define SELM_5 (0x0005) /* MCLK Source Select 5 */ +#define SELM_6 (0x0006) /* MCLK Source Select 6 */ +#define SELM_7 (0x0007) /* MCLK Source Select 7 */ +#define SELM__XT1CLK (0x0000) /* MCLK Source Select XT1CLK */ +#define SELM__VLOCLK (0x0001) /* MCLK Source Select VLOCLK */ +#define SELM__REFOCLK (0x0002) /* MCLK Source Select REFOCLK */ +#define SELM__DCOCLK (0x0003) /* MCLK Source Select DCOCLK */ +#define SELM__DCOCLKDIV (0x0004) /* MCLK Source Select DCOCLKDIV */ +#define SELM__XT2CLK (0x0005) /* MCLK Source Select XT2CLK */ + +#define SELS_0 (0x0000) /* SMCLK Source Select 0 */ +#define SELS_1 (0x0010) /* SMCLK Source Select 1 */ +#define SELS_2 (0x0020) /* SMCLK Source Select 2 */ +#define SELS_3 (0x0030) /* SMCLK Source Select 3 */ +#define SELS_4 (0x0040) /* SMCLK Source Select 4 */ +#define SELS_5 (0x0050) /* SMCLK Source Select 5 */ +#define SELS_6 (0x0060) /* SMCLK Source Select 6 */ +#define SELS_7 (0x0070) /* SMCLK Source Select 7 */ +#define SELS__XT1CLK (0x0000) /* SMCLK Source Select XT1CLK */ +#define SELS__VLOCLK (0x0010) /* SMCLK Source Select VLOCLK */ +#define SELS__REFOCLK (0x0020) /* SMCLK Source Select REFOCLK */ +#define SELS__DCOCLK (0x0030) /* SMCLK Source Select DCOCLK */ +#define SELS__DCOCLKDIV (0x0040) /* SMCLK Source Select DCOCLKDIV */ +#define SELS__XT2CLK (0x0050) /* SMCLK Source Select XT2CLK */ + +#define SELA_0 (0x0000) /* ACLK Source Select 0 */ +#define SELA_1 (0x0100) /* ACLK Source Select 1 */ +#define SELA_2 (0x0200) /* ACLK Source Select 2 */ +#define SELA_3 (0x0300) /* ACLK Source Select 3 */ +#define SELA_4 (0x0400) /* ACLK Source Select 4 */ +#define SELA_5 (0x0500) /* ACLK Source Select 5 */ +#define SELA_6 (0x0600) /* ACLK Source Select 6 */ +#define SELA_7 (0x0700) /* ACLK Source Select 7 */ +#define SELA__XT1CLK (0x0000) /* ACLK Source Select XT1CLK */ +#define SELA__VLOCLK (0x0100) /* ACLK Source Select VLOCLK */ +#define SELA__REFOCLK (0x0200) /* ACLK Source Select REFOCLK */ +#define SELA__DCOCLK (0x0300) /* ACLK Source Select DCOCLK */ +#define SELA__DCOCLKDIV (0x0400) /* ACLK Source Select DCOCLKDIV */ +#define SELA__XT2CLK (0x0500) /* ACLK Source Select XT2CLK */ + +/* UCSCTL5 Control Bits */ +#define DIVM0 (0x0001) /* MCLK Divider Bit: 0 */ +#define DIVM1 (0x0002) /* MCLK Divider Bit: 1 */ +#define DIVM2 (0x0004) /* MCLK Divider Bit: 2 */ +//#define RESERVED (0x0008) /* RESERVED */ +#define DIVS0 (0x0010) /* SMCLK Divider Bit: 0 */ +#define DIVS1 (0x0020) /* SMCLK Divider Bit: 1 */ +#define DIVS2 (0x0040) /* SMCLK Divider Bit: 2 */ +//#define RESERVED (0x0080) /* RESERVED */ +#define DIVA0 (0x0100) /* ACLK Divider Bit: 0 */ +#define DIVA1 (0x0200) /* ACLK Divider Bit: 1 */ +#define DIVA2 (0x0400) /* ACLK Divider Bit: 2 */ +//#define RESERVED (0x0800) /* RESERVED */ +#define DIVPA0 (0x1000) /* ACLK from Pin Divider Bit: 0 */ +#define DIVPA1 (0x2000) /* ACLK from Pin Divider Bit: 1 */ +#define DIVPA2 (0x4000) /* ACLK from Pin Divider Bit: 2 */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL5 Control Bits */ +#define DIVM0_L (0x0001) /* MCLK Divider Bit: 0 */ +#define DIVM1_L (0x0002) /* MCLK Divider Bit: 1 */ +#define DIVM2_L (0x0004) /* MCLK Divider Bit: 2 */ +//#define RESERVED (0x0008) /* RESERVED */ +#define DIVS0_L (0x0010) /* SMCLK Divider Bit: 0 */ +#define DIVS1_L (0x0020) /* SMCLK Divider Bit: 1 */ +#define DIVS2_L (0x0040) /* SMCLK Divider Bit: 2 */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL5 Control Bits */ +//#define RESERVED (0x0008) /* RESERVED */ +//#define RESERVED (0x0080) /* RESERVED */ +#define DIVA0_H (0x0001) /* ACLK Divider Bit: 0 */ +#define DIVA1_H (0x0002) /* ACLK Divider Bit: 1 */ +#define DIVA2_H (0x0004) /* ACLK Divider Bit: 2 */ +//#define RESERVED (0x0800) /* RESERVED */ +#define DIVPA0_H (0x0010) /* ACLK from Pin Divider Bit: 0 */ +#define DIVPA1_H (0x0020) /* ACLK from Pin Divider Bit: 1 */ +#define DIVPA2_H (0x0040) /* ACLK from Pin Divider Bit: 2 */ +//#define RESERVED (0x8000) /* RESERVED */ + +#define DIVM_0 (0x0000) /* MCLK Source Divider 0 */ +#define DIVM_1 (0x0001) /* MCLK Source Divider 1 */ +#define DIVM_2 (0x0002) /* MCLK Source Divider 2 */ +#define DIVM_3 (0x0003) /* MCLK Source Divider 3 */ +#define DIVM_4 (0x0004) /* MCLK Source Divider 4 */ +#define DIVM_5 (0x0005) /* MCLK Source Divider 5 */ +#define DIVM_6 (0x0006) /* MCLK Source Divider 6 */ +#define DIVM_7 (0x0007) /* MCLK Source Divider 7 */ +#define DIVM__1 (0x0000) /* MCLK Source Divider f(MCLK)/1 */ +#define DIVM__2 (0x0001) /* MCLK Source Divider f(MCLK)/2 */ +#define DIVM__4 (0x0002) /* MCLK Source Divider f(MCLK)/4 */ +#define DIVM__8 (0x0003) /* MCLK Source Divider f(MCLK)/8 */ +#define DIVM__16 (0x0004) /* MCLK Source Divider f(MCLK)/16 */ +#define DIVM__32 (0x0005) /* MCLK Source Divider f(MCLK)/32 */ + +#define DIVS_0 (0x0000) /* SMCLK Source Divider 0 */ +#define DIVS_1 (0x0010) /* SMCLK Source Divider 1 */ +#define DIVS_2 (0x0020) /* SMCLK Source Divider 2 */ +#define DIVS_3 (0x0030) /* SMCLK Source Divider 3 */ +#define DIVS_4 (0x0040) /* SMCLK Source Divider 4 */ +#define DIVS_5 (0x0050) /* SMCLK Source Divider 5 */ +#define DIVS_6 (0x0060) /* SMCLK Source Divider 6 */ +#define DIVS_7 (0x0070) /* SMCLK Source Divider 7 */ +#define DIVS__1 (0x0000) /* SMCLK Source Divider f(SMCLK)/1 */ +#define DIVS__2 (0x0010) /* SMCLK Source Divider f(SMCLK)/2 */ +#define DIVS__4 (0x0020) /* SMCLK Source Divider f(SMCLK)/4 */ +#define DIVS__8 (0x0030) /* SMCLK Source Divider f(SMCLK)/8 */ +#define DIVS__16 (0x0040) /* SMCLK Source Divider f(SMCLK)/16 */ +#define DIVS__32 (0x0050) /* SMCLK Source Divider f(SMCLK)/32 */ + +#define DIVA_0 (0x0000) /* ACLK Source Divider 0 */ +#define DIVA_1 (0x0100) /* ACLK Source Divider 1 */ +#define DIVA_2 (0x0200) /* ACLK Source Divider 2 */ +#define DIVA_3 (0x0300) /* ACLK Source Divider 3 */ +#define DIVA_4 (0x0400) /* ACLK Source Divider 4 */ +#define DIVA_5 (0x0500) /* ACLK Source Divider 5 */ +#define DIVA_6 (0x0600) /* ACLK Source Divider 6 */ +#define DIVA_7 (0x0700) /* ACLK Source Divider 7 */ +#define DIVA__1 (0x0000) /* ACLK Source Divider f(ACLK)/1 */ +#define DIVA__2 (0x0100) /* ACLK Source Divider f(ACLK)/2 */ +#define DIVA__4 (0x0200) /* ACLK Source Divider f(ACLK)/4 */ +#define DIVA__8 (0x0300) /* ACLK Source Divider f(ACLK)/8 */ +#define DIVA__16 (0x0400) /* ACLK Source Divider f(ACLK)/16 */ +#define DIVA__32 (0x0500) /* ACLK Source Divider f(ACLK)/32 */ + +#define DIVPA_0 (0x0000) /* ACLK from Pin Source Divider 0 */ +#define DIVPA_1 (0x1000) /* ACLK from Pin Source Divider 1 */ +#define DIVPA_2 (0x2000) /* ACLK from Pin Source Divider 2 */ +#define DIVPA_3 (0x3000) /* ACLK from Pin Source Divider 3 */ +#define DIVPA_4 (0x4000) /* ACLK from Pin Source Divider 4 */ +#define DIVPA_5 (0x5000) /* ACLK from Pin Source Divider 5 */ +#define DIVPA_6 (0x6000) /* ACLK from Pin Source Divider 6 */ +#define DIVPA_7 (0x7000) /* ACLK from Pin Source Divider 7 */ +#define DIVPA__1 (0x0000) /* ACLK from Pin Source Divider f(ACLK)/1 */ +#define DIVPA__2 (0x1000) /* ACLK from Pin Source Divider f(ACLK)/2 */ +#define DIVPA__4 (0x2000) /* ACLK from Pin Source Divider f(ACLK)/4 */ +#define DIVPA__8 (0x3000) /* ACLK from Pin Source Divider f(ACLK)/8 */ +#define DIVPA__16 (0x4000) /* ACLK from Pin Source Divider f(ACLK)/16 */ +#define DIVPA__32 (0x5000) /* ACLK from Pin Source Divider f(ACLK)/32 */ + +/* UCSCTL6 Control Bits */ +#define XT1OFF (0x0001) /* High Frequency Oscillator 1 (XT1) disable */ +#define SMCLKOFF (0x0002) /* SMCLK Off */ +#define XCAP0 (0x0004) /* XIN/XOUT Cap Bit: 0 */ +#define XCAP1 (0x0008) /* XIN/XOUT Cap Bit: 1 */ +#define XT1BYPASS (0x0010) /* XT1 bypass mode : 0: internal 1:sourced from external pin */ +#define XTS (0x0020) /* 1: Selects high-freq. oscillator */ +#define XT1DRIVE0 (0x0040) /* XT1 Drive Level mode Bit 0 */ +#define XT1DRIVE1 (0x0080) /* XT1 Drive Level mode Bit 1 */ +#define XT2OFF (0x0100) /* High Frequency Oscillator 2 (XT2) disable */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL6 Control Bits */ +#define XT1OFF_L (0x0001) /* High Frequency Oscillator 1 (XT1) disable */ +#define SMCLKOFF_L (0x0002) /* SMCLK Off */ +#define XCAP0_L (0x0004) /* XIN/XOUT Cap Bit: 0 */ +#define XCAP1_L (0x0008) /* XIN/XOUT Cap Bit: 1 */ +#define XT1BYPASS_L (0x0010) /* XT1 bypass mode : 0: internal 1:sourced from external pin */ +#define XTS_L (0x0020) /* 1: Selects high-freq. oscillator */ +#define XT1DRIVE0_L (0x0040) /* XT1 Drive Level mode Bit 0 */ +#define XT1DRIVE1_L (0x0080) /* XT1 Drive Level mode Bit 1 */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL6 Control Bits */ +#define XT2OFF_H (0x0001) /* High Frequency Oscillator 2 (XT2) disable */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +#define XCAP_0 (0x0000) /* XIN/XOUT Cap 0 */ +#define XCAP_1 (0x0004) /* XIN/XOUT Cap 1 */ +#define XCAP_2 (0x0008) /* XIN/XOUT Cap 2 */ +#define XCAP_3 (0x000C) /* XIN/XOUT Cap 3 */ +#define XT1DRIVE_0 (0x0000) /* XT1 Drive Level mode: 0 */ +#define XT1DRIVE_1 (0x0040) /* XT1 Drive Level mode: 1 */ +#define XT1DRIVE_2 (0x0080) /* XT1 Drive Level mode: 2 */ +#define XT1DRIVE_3 (0x00C0) /* XT1 Drive Level mode: 3 */ + +/* UCSCTL7 Control Bits */ +#define DCOFFG (0x0001) /* DCO Fault Flag */ +#define XT1LFOFFG (0x0002) /* XT1 Low Frequency Oscillator Fault Flag */ +#define XT1HFOFFG (0x0004) /* XT1 High Frequency Oscillator 1 Fault Flag */ +#define XT2OFFG (0x0008) /* High Frequency Oscillator 2 Fault Flag */ +//#define RESERVED (0x0010) /* RESERVED */ +//#define RESERVED (0x0020) /* RESERVED */ +//#define RESERVED (0x0040) /* RESERVED */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0100) /* RESERVED */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL7 Control Bits */ +#define DCOFFG_L (0x0001) /* DCO Fault Flag */ +#define XT1LFOFFG_L (0x0002) /* XT1 Low Frequency Oscillator Fault Flag */ +#define XT1HFOFFG_L (0x0004) /* XT1 High Frequency Oscillator 1 Fault Flag */ +#define XT2OFFG_L (0x0008) /* High Frequency Oscillator 2 Fault Flag */ +//#define RESERVED (0x0010) /* RESERVED */ +//#define RESERVED (0x0020) /* RESERVED */ +//#define RESERVED (0x0040) /* RESERVED */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0100) /* RESERVED */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL8 Control Bits */ +#define ACLKREQEN (0x0001) /* ACLK Clock Request Enable */ +#define MCLKREQEN (0x0002) /* MCLK Clock Request Enable */ +#define SMCLKREQEN (0x0004) /* SMCLK Clock Request Enable */ +#define MODOSCREQEN (0x0008) /* MODOSC Clock Request Enable */ +//#define RESERVED (0x0010) /* RESERVED */ +//#define RESERVED (0x0020) /* RESERVED */ +//#define RESERVED (0x0040) /* RESERVED */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0100) /* RESERVED */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL8 Control Bits */ +#define ACLKREQEN_L (0x0001) /* ACLK Clock Request Enable */ +#define MCLKREQEN_L (0x0002) /* MCLK Clock Request Enable */ +#define SMCLKREQEN_L (0x0004) /* SMCLK Clock Request Enable */ +#define MODOSCREQEN_L (0x0008) /* MODOSC Clock Request Enable */ +//#define RESERVED (0x0010) /* RESERVED */ +//#define RESERVED (0x0020) /* RESERVED */ +//#define RESERVED (0x0040) /* RESERVED */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0100) /* RESERVED */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +#endif +/************************************************************ +* USB +************************************************************/ +#ifdef __MSP430_HAS_USB__ /* Definition to show that Module is available */ + +/* ========================================================================= */ +/* USB Configuration Registers */ +/* ========================================================================= */ +#define OFS_USBKEYID (0x0000) /* USB Controller key register */ +#define OFS_USBKEYID_L OFS_USBKEYID +#define OFS_USBKEYID_H OFS_USBKEYID+1 +#define OFS_USBCNF (0x0002) /* USB Module configuration register */ +#define OFS_USBCNF_L OFS_USBCNF +#define OFS_USBCNF_H OFS_USBCNF+1 +#define OFS_USBPHYCTL (0x0004) /* USB PHY control register */ +#define OFS_USBPHYCTL_L OFS_USBPHYCTL +#define OFS_USBPHYCTL_H OFS_USBPHYCTL+1 +#define OFS_USBPWRCTL (0x0008) /* USB Power control register */ +#define OFS_USBPWRCTL_L OFS_USBPWRCTL +#define OFS_USBPWRCTL_H OFS_USBPWRCTL+1 +#define OFS_USBPLLCTL (0x0010) /* USB PLL control register */ +#define OFS_USBPLLCTL_L OFS_USBPLLCTL +#define OFS_USBPLLCTL_H OFS_USBPLLCTL+1 +#define OFS_USBPLLDIVB (0x0012) /* USB PLL Clock Divider Buffer control register */ +#define OFS_USBPLLDIVB_L OFS_USBPLLDIVB +#define OFS_USBPLLDIVB_H OFS_USBPLLDIVB+1 +#define OFS_USBPLLIR (0x0014) /* USB PLL Interrupt control register */ +#define OFS_USBPLLIR_L OFS_USBPLLIR +#define OFS_USBPLLIR_H OFS_USBPLLIR+1 + +#define USBKEYPID USBKEYID /* Legacy Definition: USB Controller key register */ +#define USBKEY (0x9628) /* USB Control Register key */ + +/* USBCNF Control Bits */ +#define USB_EN (0x0001) /* USB - Module enable */ +#define PUR_EN (0x0002) /* USB - PUR pin enable */ +#define PUR_IN (0x0004) /* USB - PUR pin input value */ +#define BLKRDY (0x0008) /* USB - Block ready signal for DMA */ +#define FNTEN (0x0010) /* USB - Frame Number receive Trigger enable for DMA */ +//#define RESERVED (0x0020) /* USB - */ +//#define RESERVED (0x0040) /* USB - */ +//#define RESERVED (0x0080) /* USB - */ +//#define RESERVED (0x0100) /* USB - */ +//#define RESERVED (0x0200) /* USB - */ +//#define RESERVED (0x0400) /* USB - */ +//#define RESERVED (0x0800) /* USB - */ +//#define RESERVED (0x1000) /* USB - */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +/* USBCNF Control Bits */ +#define USB_EN_L (0x0001) /* USB - Module enable */ +#define PUR_EN_L (0x0002) /* USB - PUR pin enable */ +#define PUR_IN_L (0x0004) /* USB - PUR pin input value */ +#define BLKRDY_L (0x0008) /* USB - Block ready signal for DMA */ +#define FNTEN_L (0x0010) /* USB - Frame Number receive Trigger enable for DMA */ +//#define RESERVED (0x0020) /* USB - */ +//#define RESERVED (0x0040) /* USB - */ +//#define RESERVED (0x0080) /* USB - */ +//#define RESERVED (0x0100) /* USB - */ +//#define RESERVED (0x0200) /* USB - */ +//#define RESERVED (0x0400) /* USB - */ +//#define RESERVED (0x0800) /* USB - */ +//#define RESERVED (0x1000) /* USB - */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +/* USBPHYCTL Control Bits */ +#define PUOUT0 (0x0001) /* USB - USB Port Output Signal Bit 0 */ +#define PUOUT1 (0x0002) /* USB - USB Port Output Signal Bit 1 */ +#define PUIN0 (0x0004) /* USB - PU0/DP Input Data */ +#define PUIN1 (0x0008) /* USB - PU1/DM Input Data */ +//#define RESERVED (0x0010) /* USB - */ +#define PUOPE (0x0020) /* USB - USB Port Output Enable */ +//#define RESERVED (0x0040) /* USB - */ +#define PUSEL (0x0080) /* USB - USB Port Function Select */ +#define PUIPE (0x0100) /* USB - PHY Single Ended Input enable */ +//#define RESERVED (0x0200) /* USB - */ +//#define RESERVED (0x0100) /* USB - */ +//#define RESERVED (0x0200) /* USB - */ +//#define RESERVED (0x0400) /* USB - */ +//#define RESERVED (0x0800) /* USB - */ +//#define RESERVED (0x1000) /* USB - */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +/* USBPHYCTL Control Bits */ +#define PUOUT0_L (0x0001) /* USB - USB Port Output Signal Bit 0 */ +#define PUOUT1_L (0x0002) /* USB - USB Port Output Signal Bit 1 */ +#define PUIN0_L (0x0004) /* USB - PU0/DP Input Data */ +#define PUIN1_L (0x0008) /* USB - PU1/DM Input Data */ +//#define RESERVED (0x0010) /* USB - */ +#define PUOPE_L (0x0020) /* USB - USB Port Output Enable */ +//#define RESERVED (0x0040) /* USB - */ +#define PUSEL_L (0x0080) /* USB - USB Port Function Select */ +//#define RESERVED (0x0200) /* USB - */ +//#define RESERVED (0x0100) /* USB - */ +//#define RESERVED (0x0200) /* USB - */ +//#define RESERVED (0x0400) /* USB - */ +//#define RESERVED (0x0800) /* USB - */ +//#define RESERVED (0x1000) /* USB - */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +/* USBPHYCTL Control Bits */ +//#define RESERVED (0x0010) /* USB - */ +//#define RESERVED (0x0040) /* USB - */ +#define PUIPE_H (0x0001) /* USB - PHY Single Ended Input enable */ +//#define RESERVED (0x0200) /* USB - */ +//#define RESERVED (0x0100) /* USB - */ +//#define RESERVED (0x0200) /* USB - */ +//#define RESERVED (0x0400) /* USB - */ +//#define RESERVED (0x0800) /* USB - */ +//#define RESERVED (0x1000) /* USB - */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +#define PUDIR (0x0020) /* USB - Legacy Definition: USB Port Output Enable */ +#define PSEIEN (0x0100) /* USB - Legacy Definition: PHY Single Ended Input enable */ + +/* USBPWRCTL Control Bits */ +#define VUOVLIFG (0x0001) /* USB - VUSB Overload Interrupt Flag */ +#define VBONIFG (0x0002) /* USB - VBUS "Coming ON" Interrupt Flag */ +#define VBOFFIFG (0x0004) /* USB - VBUS "Going OFF" Interrupt Flag */ +#define USBBGVBV (0x0008) /* USB - USB Bandgap and VBUS valid */ +#define USBDETEN (0x0010) /* USB - VBUS on/off events enable */ +#define OVLAOFF (0x0020) /* USB - LDO overload auto off enable */ +#define SLDOAON (0x0040) /* USB - Secondary LDO auto on enable */ +//#define RESERVED (0x0080) /* USB - */ +#define VUOVLIE (0x0100) /* USB - Overload indication Interrupt Enable */ +#define VBONIE (0x0200) /* USB - VBUS "Coming ON" Interrupt Enable */ +#define VBOFFIE (0x0400) /* USB - VBUS "Going OFF" Interrupt Enable */ +#define VUSBEN (0x0800) /* USB - LDO Enable (3.3V) */ +#define SLDOEN (0x1000) /* USB - Secondary LDO Enable (1.8V) */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +/* USBPWRCTL Control Bits */ +#define VUOVLIFG_L (0x0001) /* USB - VUSB Overload Interrupt Flag */ +#define VBONIFG_L (0x0002) /* USB - VBUS "Coming ON" Interrupt Flag */ +#define VBOFFIFG_L (0x0004) /* USB - VBUS "Going OFF" Interrupt Flag */ +#define USBBGVBV_L (0x0008) /* USB - USB Bandgap and VBUS valid */ +#define USBDETEN_L (0x0010) /* USB - VBUS on/off events enable */ +#define OVLAOFF_L (0x0020) /* USB - LDO overload auto off enable */ +#define SLDOAON_L (0x0040) /* USB - Secondary LDO auto on enable */ +//#define RESERVED (0x0080) /* USB - */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +/* USBPWRCTL Control Bits */ +//#define RESERVED (0x0080) /* USB - */ +#define VUOVLIE_H (0x0001) /* USB - Overload indication Interrupt Enable */ +#define VBONIE_H (0x0002) /* USB - VBUS "Coming ON" Interrupt Enable */ +#define VBOFFIE_H (0x0004) /* USB - VBUS "Going OFF" Interrupt Enable */ +#define VUSBEN_H (0x0008) /* USB - LDO Enable (3.3V) */ +#define SLDOEN_H (0x0010) /* USB - Secondary LDO Enable (1.8V) */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +/* USBPLLCTL Control Bits */ +//#define RESERVED (0x0001) /* USB - */ +//#define RESERVED (0x0002) /* USB - */ +//#define RESERVED (0x0004) /* USB - */ +//#define RESERVED (0x0008) /* USB - */ +//#define RESERVED (0x0010) /* USB - */ +//#define RESERVED (0x0020) /* USB - */ +#define UCLKSEL0 (0x0040) /* USB - Module Clock Select Bit 0 */ +#define UCLKSEL1 (0x0080) /* USB - Module Clock Select Bit 1 */ +#define UPLLEN (0x0100) /* USB - PLL enable */ +#define UPFDEN (0x0200) /* USB - Phase Freq. Discriminator enable */ +//#define RESERVED (0x0400) /* USB - */ +//#define RESERVED (0x0800) /* USB - */ +//#define RESERVED (0x1000) /* USB - */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +/* USBPLLCTL Control Bits */ +//#define RESERVED (0x0001) /* USB - */ +//#define RESERVED (0x0002) /* USB - */ +//#define RESERVED (0x0004) /* USB - */ +//#define RESERVED (0x0008) /* USB - */ +//#define RESERVED (0x0010) /* USB - */ +//#define RESERVED (0x0020) /* USB - */ +#define UCLKSEL0_L (0x0040) /* USB - Module Clock Select Bit 0 */ +#define UCLKSEL1_L (0x0080) /* USB - Module Clock Select Bit 1 */ +//#define RESERVED (0x0400) /* USB - */ +//#define RESERVED (0x0800) /* USB - */ +//#define RESERVED (0x1000) /* USB - */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +/* USBPLLCTL Control Bits */ +//#define RESERVED (0x0001) /* USB - */ +//#define RESERVED (0x0002) /* USB - */ +//#define RESERVED (0x0004) /* USB - */ +//#define RESERVED (0x0008) /* USB - */ +//#define RESERVED (0x0010) /* USB - */ +//#define RESERVED (0x0020) /* USB - */ +#define UPLLEN_H (0x0001) /* USB - PLL enable */ +#define UPFDEN_H (0x0002) /* USB - Phase Freq. Discriminator enable */ +//#define RESERVED (0x0400) /* USB - */ +//#define RESERVED (0x0800) /* USB - */ +//#define RESERVED (0x1000) /* USB - */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +#define UCLKSEL_0 (0x0000) /* USB - Module Clock Select: 0 */ +#define UCLKSEL_1 (0x0040) /* USB - Module Clock Select: 1 */ +#define UCLKSEL_2 (0x0080) /* USB - Module Clock Select: 2 */ +#define UCLKSEL_3 (0x00C0) /* USB - Module Clock Select: 3 (Reserved) */ + +#define UCLKSEL__PLLCLK (0x0000) /* USB - Module Clock Select: PLLCLK */ +#define UCLKSEL__XT1CLK (0x0040) /* USB - Module Clock Select: XT1CLK */ +#define UCLKSEL__XT2CLK (0x0080) /* USB - Module Clock Select: XT2CLK */ + +/* USBPLLDIVB Control Bits */ +#define UPMB0 (0x0001) /* USB - PLL feedback divider buffer Bit 0 */ +#define UPMB1 (0x0002) /* USB - PLL feedback divider buffer Bit 1 */ +#define UPMB2 (0x0004) /* USB - PLL feedback divider buffer Bit 2 */ +#define UPMB3 (0x0008) /* USB - PLL feedback divider buffer Bit 3 */ +#define UPMB4 (0x0010) /* USB - PLL feedback divider buffer Bit 4 */ +#define UPMB5 (0x0020) /* USB - PLL feedback divider buffer Bit 5 */ +//#define RESERVED (0x0040) /* USB - */ +//#define RESERVED (0x0080) /* USB - */ +#define UPQB0 (0x0100) /* USB - PLL prescale divider buffer Bit 0 */ +#define UPQB1 (0x0200) /* USB - PLL prescale divider buffer Bit 1 */ +#define UPQB2 (0x0400) /* USB - PLL prescale divider buffer Bit 2 */ +//#define RESERVED (0x0800) /* USB - */ +//#define RESERVED (0x1000) /* USB - */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +/* USBPLLDIVB Control Bits */ +#define UPMB0_L (0x0001) /* USB - PLL feedback divider buffer Bit 0 */ +#define UPMB1_L (0x0002) /* USB - PLL feedback divider buffer Bit 1 */ +#define UPMB2_L (0x0004) /* USB - PLL feedback divider buffer Bit 2 */ +#define UPMB3_L (0x0008) /* USB - PLL feedback divider buffer Bit 3 */ +#define UPMB4_L (0x0010) /* USB - PLL feedback divider buffer Bit 4 */ +#define UPMB5_L (0x0020) /* USB - PLL feedback divider buffer Bit 5 */ +//#define RESERVED (0x0040) /* USB - */ +//#define RESERVED (0x0080) /* USB - */ +//#define RESERVED (0x0800) /* USB - */ +//#define RESERVED (0x1000) /* USB - */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +/* USBPLLDIVB Control Bits */ +//#define RESERVED (0x0040) /* USB - */ +//#define RESERVED (0x0080) /* USB - */ +#define UPQB0_H (0x0001) /* USB - PLL prescale divider buffer Bit 0 */ +#define UPQB1_H (0x0002) /* USB - PLL prescale divider buffer Bit 1 */ +#define UPQB2_H (0x0004) /* USB - PLL prescale divider buffer Bit 2 */ +//#define RESERVED (0x0800) /* USB - */ +//#define RESERVED (0x1000) /* USB - */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +#define USBPLL_SETCLK_1_5 (UPMB0*31 | UPQB0*0) /* USB - PLL Set for 1.5 MHz input clock */ +#define USBPLL_SETCLK_1_6 (UPMB0*29 | UPQB0*0) /* USB - PLL Set for 1.6 MHz input clock */ +#define USBPLL_SETCLK_1_7778 (UPMB0*26 | UPQB0*0) /* USB - PLL Set for 1.7778 MHz input clock */ +#define USBPLL_SETCLK_1_8432 (UPMB0*25 | UPQB0*0) /* USB - PLL Set for 1.8432 MHz input clock */ +#define USBPLL_SETCLK_1_8461 (UPMB0*25 | UPQB0*0) /* USB - PLL Set for 1.8461 MHz input clock */ +#define USBPLL_SETCLK_1_92 (UPMB0*24 | UPQB0*0) /* USB - PLL Set for 1.92 MHz input clock */ +#define USBPLL_SETCLK_2_0 (UPMB0*23 | UPQB0*0) /* USB - PLL Set for 2.0 MHz input clock */ +#define USBPLL_SETCLK_2_4 (UPMB0*19 | UPQB0*0) /* USB - PLL Set for 2.4 MHz input clock */ +#define USBPLL_SETCLK_2_6667 (UPMB0*17 | UPQB0*0) /* USB - PLL Set for 2.6667 MHz input clock */ +#define USBPLL_SETCLK_3_0 (UPMB0*15 | UPQB0*0) /* USB - PLL Set for 3.0 MHz input clock */ +#define USBPLL_SETCLK_3_2 (UPMB0*29 | UPQB0*1) /* USB - PLL Set for 3.2 MHz input clock */ +#define USBPLL_SETCLK_3_5556 (UPMB0*26 | UPQB0*1) /* USB - PLL Set for 3.5556 MHz input clock */ +#define USBPLL_SETCLK_3_579545 (UPMB0*26 | UPQB0*1) /* USB - PLL Set for 3.579546 MHz input clock */ +#define USBPLL_SETCLK_3_84 (UPMB0*24 | UPQB0*1) /* USB - PLL Set for 3.84 MHz input clock */ +#define USBPLL_SETCLK_4_0 (UPMB0*23 | UPQB0*1) /* USB - PLL Set for 4.0 MHz input clock */ +#define USBPLL_SETCLK_4_1739 (UPMB0*22 | UPQB0*1) /* USB - PLL Set for 4.1739 MHz input clock */ +#define USBPLL_SETCLK_4_1943 (UPMB0*22 | UPQB0*1) /* USB - PLL Set for 4.1943 MHz input clock */ +#define USBPLL_SETCLK_4_332 (UPMB0*21 | UPQB0*1) /* USB - PLL Set for 4.332 MHz input clock */ +#define USBPLL_SETCLK_4_3636 (UPMB0*21 | UPQB0*1) /* USB - PLL Set for 4.3636 MHz input clock */ +#define USBPLL_SETCLK_4_5 (UPMB0*31 | UPQB0*2) /* USB - PLL Set for 4.5 MHz input clock */ +#define USBPLL_SETCLK_4_8 (UPMB0*19 | UPQB0*1) /* USB - PLL Set for 4.8 MHz input clock */ +#define USBPLL_SETCLK_5_33 (UPMB0*17 | UPQB0*1) /* USB - PLL Set for 5.33 MHz input clock */ +#define USBPLL_SETCLK_5_76 (UPMB0*24 | UPQB0*2) /* USB - PLL Set for 5.76 MHz input clock */ +#define USBPLL_SETCLK_6_0 (UPMB0*23 | UPQB0*2) /* USB - PLL Set for 6.0 MHz input clock */ +#define USBPLL_SETCLK_6_4 (UPMB0*29 | UPQB0*3) /* USB - PLL Set for 6.4 MHz input clock */ +#define USBPLL_SETCLK_7_2 (UPMB0*19 | UPQB0*2) /* USB - PLL Set for 7.2 MHz input clock */ +#define USBPLL_SETCLK_7_68 (UPMB0*24 | UPQB0*3) /* USB - PLL Set for 7.68 MHz input clock */ +#define USBPLL_SETCLK_8_0 (UPMB0*17 | UPQB0*2) /* USB - PLL Set for 8.0 MHz input clock */ +#define USBPLL_SETCLK_9_0 (UPMB0*15 | UPQB0*2) /* USB - PLL Set for 9.0 MHz input clock */ +#define USBPLL_SETCLK_9_6 (UPMB0*19 | UPQB0*3) /* USB - PLL Set for 9.6 MHz input clock */ +#define USBPLL_SETCLK_10_66 (UPMB0*17 | UPQB0*3) /* USB - PLL Set for 10.66 MHz input clock */ +#define USBPLL_SETCLK_12_0 (UPMB0*15 | UPQB0*3) /* USB - PLL Set for 12.0 MHz input clock */ +#define USBPLL_SETCLK_12_8 (UPMB0*29 | UPQB0*5) /* USB - PLL Set for 12.8 MHz input clock */ +#define USBPLL_SETCLK_14_4 (UPMB0*19 | UPQB0*4) /* USB - PLL Set for 14.4 MHz input clock */ +#define USBPLL_SETCLK_16_0 (UPMB0*17 | UPQB0*4) /* USB - PLL Set for 16.0 MHz input clock */ +#define USBPLL_SETCLK_16_9344 (UPMB0*16 | UPQB0*4) /* USB - PLL Set for 16.9344 MHz input clock */ +#define USBPLL_SETCLK_16_94118 (UPMB0*16 | UPQB0*4) /* USB - PLL Set for 16.94118 MHz input clock */ +#define USBPLL_SETCLK_18_0 (UPMB0*15 | UPQB0*4) /* USB - PLL Set for 18.0 MHz input clock */ +#define USBPLL_SETCLK_19_2 (UPMB0*19 | UPQB0*5) /* USB - PLL Set for 19.2 MHz input clock */ +#define USBPLL_SETCLK_24_0 (UPMB0*15 | UPQB0*5) /* USB - PLL Set for 24.0 MHz input clock */ +#define USBPLL_SETCLK_25_6 (UPMB0*29 | UPQB0*7) /* USB - PLL Set for 25.6 MHz input clock */ +#define USBPLL_SETCLK_26_0 (UPMB0*23 | UPQB0*6) /* USB - PLL Set for 26.0 MHz input clock */ +#define USBPLL_SETCLK_32_0 (UPMB0*23 | UPQB0*7) /* USB - PLL Set for 32.0 MHz input clock */ + +/* USBPLLIR Control Bits */ +#define USBOOLIFG (0x0001) /* USB - PLL out of lock Interrupt Flag */ +#define USBLOSIFG (0x0002) /* USB - PLL loss of signal Interrupt Flag */ +#define USBOORIFG (0x0004) /* USB - PLL out of range Interrupt Flag */ +//#define RESERVED (0x0008) /* USB - */ +//#define RESERVED (0x0010) /* USB - */ +//#define RESERVED (0x0020) /* USB - */ +//#define RESERVED (0x0040) /* USB - */ +//#define RESERVED (0x0080) /* USB - */ +#define USBOOLIE (0x0100) /* USB - PLL out of lock Interrupt enable */ +#define USBLOSIE (0x0200) /* USB - PLL loss of signal Interrupt enable */ +#define USBOORIE (0x0400) /* USB - PLL out of range Interrupt enable */ +//#define RESERVED (0x0800) /* USB - */ +//#define RESERVED (0x1000) /* USB - */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +/* USBPLLIR Control Bits */ +#define USBOOLIFG_L (0x0001) /* USB - PLL out of lock Interrupt Flag */ +#define USBLOSIFG_L (0x0002) /* USB - PLL loss of signal Interrupt Flag */ +#define USBOORIFG_L (0x0004) /* USB - PLL out of range Interrupt Flag */ +//#define RESERVED (0x0008) /* USB - */ +//#define RESERVED (0x0010) /* USB - */ +//#define RESERVED (0x0020) /* USB - */ +//#define RESERVED (0x0040) /* USB - */ +//#define RESERVED (0x0080) /* USB - */ +//#define RESERVED (0x0800) /* USB - */ +//#define RESERVED (0x1000) /* USB - */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +/* USBPLLIR Control Bits */ +//#define RESERVED (0x0008) /* USB - */ +//#define RESERVED (0x0010) /* USB - */ +//#define RESERVED (0x0020) /* USB - */ +//#define RESERVED (0x0040) /* USB - */ +//#define RESERVED (0x0080) /* USB - */ +#define USBOOLIE_H (0x0001) /* USB - PLL out of lock Interrupt enable */ +#define USBLOSIE_H (0x0002) /* USB - PLL loss of signal Interrupt enable */ +#define USBOORIE_H (0x0004) /* USB - PLL out of range Interrupt enable */ +//#define RESERVED (0x0800) /* USB - */ +//#define RESERVED (0x1000) /* USB - */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +/* ========================================================================= */ +/* USB Control Registers */ +/* ========================================================================= */ +#define OFS_USBIEPCNF_0 (0x0020) /* USB Input endpoint_0: Configuration */ +#define OFS_USBIEPCNT_0 (0x0021) /* USB Input endpoint_0: Byte Count */ +#define OFS_USBOEPCNF_0 (0x0022) /* USB Output endpoint_0: Configuration */ +#define OFS_USBOEPCNT_0 (0x0023) /* USB Output endpoint_0: byte count */ +#define OFS_USBIEPIE (0x002E) /* USB Input endpoint interrupt enable flags */ +#define OFS_USBOEPIE (0x002F) /* USB Output endpoint interrupt enable flags */ +#define OFS_USBIEPIFG (0x0030) /* USB Input endpoint interrupt flags */ +#define OFS_USBOEPIFG (0x0031) /* USB Output endpoint interrupt flags */ +#define OFS_USBVECINT (0x0032) /* USB Vector interrupt register */ +#define OFS_USBVECINT_L OFS_USBVECINT +#define OFS_USBVECINT_H OFS_USBVECINT+1 +#define OFS_USBMAINT (0x0036) /* USB maintenance register */ +#define OFS_USBMAINT_L OFS_USBMAINT +#define OFS_USBMAINT_H OFS_USBMAINT+1 +#define OFS_USBTSREG (0x0038) /* USB Time Stamp register */ +#define OFS_USBTSREG_L OFS_USBTSREG +#define OFS_USBTSREG_H OFS_USBTSREG+1 +#define OFS_USBFN (0x003A) /* USB Frame number */ +#define OFS_USBFN_L OFS_USBFN +#define OFS_USBFN_H OFS_USBFN+1 +#define OFS_USBCTL (0x003C) /* USB control register */ +#define OFS_USBIE (0x003D) /* USB interrupt enable register */ +#define OFS_USBIFG (0x003E) /* USB interrupt flag register */ +#define OFS_USBFUNADR (0x003F) /* USB Function address register */ + +#define USBIV USBVECINT /* USB Vector interrupt register (alternate define) */ + +/* USBIEPCNF_0 Control Bits */ +/* USBOEPCNF_0 Control Bits */ +//#define RESERVED (0x0001) /* USB - */ +//#define RESERVED (0x0001) /* USB - */ +#define USBIIE (0x0004) /* USB - Transaction Interrupt indication enable */ +#define STALL (0x0008) /* USB - Stall Condition */ +//#define RESERVED (0x0010) /* USB - */ +#define TOGGLE (0x0020) /* USB - Toggle Bit */ +//#define RESERVED (0x0040) /* USB - */ +#define UBME (0x0080) /* USB - UBM In-Endpoint Enable */ + +/* USBIEPBCNT_0 Control Bits */ +/* USBOEPBCNT_0 Control Bits */ +#define CNT0 (0x0001) /* USB - Byte Count Bit 0 */ +#define CNT1 (0x0001) /* USB - Byte Count Bit 1 */ +#define CNT2 (0x0004) /* USB - Byte Count Bit 2 */ +#define CNT3 (0x0008) /* USB - Byte Count Bit 3 */ +//#define RESERVED (0x0010) /* USB - */ +//#define RESERVED (0x0020) /* USB - */ +//#define RESERVED (0x0040) /* USB - */ +#define NAK (0x0080) /* USB - No Acknowledge Status Bit */ + +/* USBMAINT Control Bits */ +#define UTIFG (0x0001) /* USB - Timer Interrupt Flag */ +#define UTIE (0x0002) /* USB - Timer Interrupt Enable */ +//#define RESERVED (0x0004) /* USB - */ +//#define RESERVED (0x0008) /* USB - */ +//#define RESERVED (0x0010) /* USB - */ +//#define RESERVED (0x0020) /* USB - */ +//#define RESERVED (0x0040) /* USB - */ +//#define RESERVED (0x0080) /* USB - */ +#define TSGEN (0x0100) /* USB - Time Stamp Generator Enable */ +#define TSESEL0 (0x0200) /* USB - Time Stamp Event Select Bit 0 */ +#define TSESEL1 (0x0400) /* USB - Time Stamp Event Select Bit 1 */ +#define TSE3 (0x0800) /* USB - Time Stamp Event #3 Bit */ +//#define RESERVED (0x1000) /* USB - */ +#define UTSEL0 (0x2000) /* USB - Timer Select Bit 0 */ +#define UTSEL1 (0x4000) /* USB - Timer Select Bit 1 */ +#define UTSEL2 (0x8000) /* USB - Timer Select Bit 2 */ + +/* USBMAINT Control Bits */ +#define UTIFG_L (0x0001) /* USB - Timer Interrupt Flag */ +#define UTIE_L (0x0002) /* USB - Timer Interrupt Enable */ +//#define RESERVED (0x0004) /* USB - */ +//#define RESERVED (0x0008) /* USB - */ +//#define RESERVED (0x0010) /* USB - */ +//#define RESERVED (0x0020) /* USB - */ +//#define RESERVED (0x0040) /* USB - */ +//#define RESERVED (0x0080) /* USB - */ +//#define RESERVED (0x1000) /* USB - */ + +/* USBMAINT Control Bits */ +//#define RESERVED (0x0004) /* USB - */ +//#define RESERVED (0x0008) /* USB - */ +//#define RESERVED (0x0010) /* USB - */ +//#define RESERVED (0x0020) /* USB - */ +//#define RESERVED (0x0040) /* USB - */ +//#define RESERVED (0x0080) /* USB - */ +#define TSGEN_H (0x0001) /* USB - Time Stamp Generator Enable */ +#define TSESEL0_H (0x0002) /* USB - Time Stamp Event Select Bit 0 */ +#define TSESEL1_H (0x0004) /* USB - Time Stamp Event Select Bit 1 */ +#define TSE3_H (0x0008) /* USB - Time Stamp Event #3 Bit */ +//#define RESERVED (0x1000) /* USB - */ +#define UTSEL0_H (0x0020) /* USB - Timer Select Bit 0 */ +#define UTSEL1_H (0x0040) /* USB - Timer Select Bit 1 */ +#define UTSEL2_H (0x0080) /* USB - Timer Select Bit 2 */ + +#define TSESEL_0 (0x0000) /* USB - Time Stamp Event Select: 0 */ +#define TSESEL_1 (0x0200) /* USB - Time Stamp Event Select: 1 */ +#define TSESEL_2 (0x0400) /* USB - Time Stamp Event Select: 2 */ +#define TSESEL_3 (0x0600) /* USB - Time Stamp Event Select: 3 */ + +#define UTSEL_0 (0x0000) /* USB - Timer Select: 0 */ +#define UTSEL_1 (0x2000) /* USB - Timer Select: 1 */ +#define UTSEL_2 (0x4000) /* USB - Timer Select: 2 */ +#define UTSEL_3 (0x6000) /* USB - Timer Select: 3 */ +#define UTSEL_4 (0x8000) /* USB - Timer Select: 4 */ +#define UTSEL_5 (0xA000) /* USB - Timer Select: 5 */ +#define UTSEL_6 (0xC000) /* USB - Timer Select: 6 */ +#define UTSEL_7 (0xE000) /* USB - Timer Select: 7 */ + +/* USBCTL Control Bits */ +#define DIR (0x0001) /* USB - Data Response Bit */ +//#define RESERVED (0x0002) /* USB - */ +//#define RESERVED (0x0004) /* USB - */ +//#define RESERVED (0x0008) /* USB - */ +#define FRSTE (0x0010) /* USB - Function Reset Connection Enable */ +#define RWUP (0x0020) /* USB - Device Remote Wakeup Request */ +#define FEN (0x0040) /* USB - Function Enable Bit */ +//#define RESERVED (0x0080) /* USB - */ + +/* USBIE Control Bits */ +#define STPOWIE (0x0001) /* USB - Setup Overwrite Interrupt Enable */ +//#define RESERVED (0x0002) /* USB - */ +#define SETUPIE (0x0004) /* USB - Setup Interrupt Enable */ +//#define RESERVED (0x0008) /* USB - */ +//#define RESERVED (0x0010) /* USB - */ +#define RESRIE (0x0020) /* USB - Function Resume Request Interrupt Enable */ +#define SUSRIE (0x0040) /* USB - Function Suspend Request Interrupt Enable */ +#define RSTRIE (0x0080) /* USB - Function Reset Request Interrupt Enable */ + +/* USBIFG Control Bits */ +#define STPOWIFG (0x0001) /* USB - Setup Overwrite Interrupt Flag */ +//#define RESERVED (0x0002) /* USB - */ +#define SETUPIFG (0x0004) /* USB - Setup Interrupt Flag */ +//#define RESERVED (0x0008) /* USB - */ +//#define RESERVED (0x0010) /* USB - */ +#define RESRIFG (0x0020) /* USB - Function Resume Request Interrupt Flag */ +#define SUSRIFG (0x0040) /* USB - Function Suspend Request Interrupt Flag */ +#define RSTRIFG (0x0080) /* USB - Function Reset Request Interrupt Flag */ + +//values of USBVECINT when USB-interrupt occured +#define USBVECINT_NONE 0x00 +#define USBVECINT_PWR_DROP 0x02 +#define USBVECINT_PLL_LOCK 0x04 +#define USBVECINT_PLL_SIGNAL 0x06 +#define USBVECINT_PLL_RANGE 0x08 +#define USBVECINT_PWR_VBUSOn 0x0A +#define USBVECINT_PWR_VBUSOff 0x0C +#define USBVECINT_USB_TIMESTAMP 0x10 +#define USBVECINT_INPUT_ENDPOINT0 0x12 +#define USBVECINT_OUTPUT_ENDPOINT0 0x14 +#define USBVECINT_RSTR 0x16 +#define USBVECINT_SUSR 0x18 +#define USBVECINT_RESR 0x1A +#define USBVECINT_SETUP_PACKET_RECEIVED 0x20 +#define USBVECINT_STPOW_PACKET_RECEIVED 0x22 +#define USBVECINT_INPUT_ENDPOINT1 0x24 +#define USBVECINT_INPUT_ENDPOINT2 0x26 +#define USBVECINT_INPUT_ENDPOINT3 0x28 +#define USBVECINT_INPUT_ENDPOINT4 0x2A +#define USBVECINT_INPUT_ENDPOINT5 0x2C +#define USBVECINT_INPUT_ENDPOINT6 0x2E +#define USBVECINT_INPUT_ENDPOINT7 0x30 +#define USBVECINT_OUTPUT_ENDPOINT1 0x32 +#define USBVECINT_OUTPUT_ENDPOINT2 0x34 +#define USBVECINT_OUTPUT_ENDPOINT3 0x36 +#define USBVECINT_OUTPUT_ENDPOINT4 0x38 +#define USBVECINT_OUTPUT_ENDPOINT5 0x3A +#define USBVECINT_OUTPUT_ENDPOINT6 0x3C +#define USBVECINT_OUTPUT_ENDPOINT7 0x3E + + +/* ========================================================================= */ +/* USB Operation Registers */ +/* ========================================================================= */ + +#define OFS_USBIEPSIZXY_7 (0x23FF) /* Input Endpoint_7: X/Y-buffer size */ +#define OFS_USBIEPBCTY_7 (0x23FE) /* Input Endpoint_7: Y-byte count */ +#define OFS_USBIEPBBAY_7 (0x23FD) /* Input Endpoint_7: Y-buffer base addr. */ +//#define Spare_O (0x23FC) /* Not used */ +//#define Spare_O (0x23FB) /* Not used */ +#define OFS_USBIEPBCTX_7 (0x23FA) /* Input Endpoint_7: X-byte count */ +#define OFS_USBIEPBBAX_7 (0x23F9) /* Input Endpoint_7: X-buffer base addr. */ +#define OFS_USBIEPCNF_7 (0x23F8) /* Input Endpoint_7: Configuration */ +#define OFS_USBIEPSIZXY_6 (0x23F7) /* Input Endpoint_6: X/Y-buffer size */ +#define OFS_USBIEPBCTY_6 (0x23F6) /* Input Endpoint_6: Y-byte count */ +#define OFS_USBIEPBBAY_6 (0x23F5) /* Input Endpoint_6: Y-buffer base addr. */ +//#define Spare_O (0x23F4) /* Not used */ +//#define Spare_O (0x23F3) /* Not used */ +#define OFS_USBIEPBCTX_6 (0x23F2) /* Input Endpoint_6: X-byte count */ +#define OFS_USBIEPBBAX_6 (0x23F1) /* Input Endpoint_6: X-buffer base addr. */ +#define OFS_USBIEPCNF_6 (0x23F0) /* Input Endpoint_6: Configuration */ +#define OFS_USBIEPSIZXY_5 (0x23EF) /* Input Endpoint_5: X/Y-buffer size */ +#define OFS_USBIEPBCTY_5 (0x23EE) /* Input Endpoint_5: Y-byte count */ +#define OFS_USBIEPBBAY_5 (0x23ED) /* Input Endpoint_5: Y-buffer base addr. */ +//#define Spare_O (0x23EC) /* Not used */ +//#define Spare_O (0x23EB) /* Not used */ +#define OFS_USBIEPBCTX_5 (0x23EA) /* Input Endpoint_5: X-byte count */ +#define OFS_USBIEPBBAX_5 (0x23E9) /* Input Endpoint_5: X-buffer base addr. */ +#define OFS_USBIEPCNF_5 (0x23E8) /* Input Endpoint_5: Configuration */ +#define OFS_USBIEPSIZXY_4 (0x23E7) /* Input Endpoint_4: X/Y-buffer size */ +#define OFS_USBIEPBCTY_4 (0x23E6) /* Input Endpoint_4: Y-byte count */ +#define OFS_USBIEPBBAY_4 (0x23E5) /* Input Endpoint_4: Y-buffer base addr. */ +//#define Spare_O (0x23E4) /* Not used */ +//#define Spare_O (0x23E3) /* Not used */ +#define OFS_USBIEPBCTX_4 (0x23E2) /* Input Endpoint_4: X-byte count */ +#define OFS_USBIEPBBAX_4 (0x23E1) /* Input Endpoint_4: X-buffer base addr. */ +#define OFS_USBIEPCNF_4 (0x23E0) /* Input Endpoint_4: Configuration */ +#define OFS_USBIEPSIZXY_3 (0x23DF) /* Input Endpoint_3: X/Y-buffer size */ +#define OFS_USBIEPBCTY_3 (0x23DE) /* Input Endpoint_3: Y-byte count */ +#define OFS_USBIEPBBAY_3 (0x23DD) /* Input Endpoint_3: Y-buffer base addr. */ +//#define Spare_O (0x23DC) /* Not used */ +//#define Spare_O (0x23DB) /* Not used */ +#define OFS_USBIEPBCTX_3 (0x23DA) /* Input Endpoint_3: X-byte count */ +#define OFS_USBIEPBBAX_3 (0x23D9) /* Input Endpoint_3: X-buffer base addr. */ +#define OFS_USBIEPCNF_3 (0x23D8) /* Input Endpoint_3: Configuration */ +#define OFS_USBIEPSIZXY_2 (0x23D7) /* Input Endpoint_2: X/Y-buffer size */ +#define OFS_USBIEPBCTY_2 (0x23D6) /* Input Endpoint_2: Y-byte count */ +#define OFS_USBIEPBBAY_2 (0x23D5) /* Input Endpoint_2: Y-buffer base addr. */ +//#define Spare_O (0x23D4) /* Not used */ +//#define Spare_O (0x23D3) /* Not used */ +#define OFS_USBIEPBCTX_2 (0x23D2) /* Input Endpoint_2: X-byte count */ +#define OFS_USBIEPBBAX_2 (0x23D1) /* Input Endpoint_2: X-buffer base addr. */ +#define OFS_USBIEPCNF_2 (0x23D0) /* Input Endpoint_2: Configuration */ +#define OFS_USBIEPSIZXY_1 (0x23CF) /* Input Endpoint_1: X/Y-buffer size */ +#define OFS_USBIEPBCTY_1 (0x23CE) /* Input Endpoint_1: Y-byte count */ +#define OFS_USBIEPBBAY_1 (0x23CD) /* Input Endpoint_1: Y-buffer base addr. */ +//#define Spare_O (0x23CC) /* Not used */ +//#define Spare_O (0x23CB) /* Not used */ +#define OFS_USBIEPBCTX_1 (0x23CA) /* Input Endpoint_1: X-byte count */ +#define OFS_USBIEPBBAX_1 (0x23C9) /* Input Endpoint_1: X-buffer base addr. */ +#define OFS_USBIEPCNF_1 (0x23C8) /* Input Endpoint_1: Configuration */ +//#define (0x23C7)_O /* */ +//#define RESERVED_O (0x1C00) /* */ +//#define (0x23C0)_O /* */ +#define OFS_USBOEPSIZXY_7 (0x23BF) /* Output Endpoint_7: X/Y-buffer size */ +#define OFS_USBOEPBCTY_7 (0x23BE) /* Output Endpoint_7: Y-byte count */ +#define OFS_USBOEPBBAY_7 (0x23BD) /* Output Endpoint_7: Y-buffer base addr. */ +//#define Spare_O (0x23BC) /* Not used */ +//#define Spare_O (0x23BB) /* Not used */ +#define OFS_USBOEPBCTX_7 (0x23BA) /* Output Endpoint_7: X-byte count */ +#define OFS_USBOEPBBAX_7 (0x23B9) /* Output Endpoint_7: X-buffer base addr. */ +#define OFS_USBOEPCNF_7 (0x23B8) /* Output Endpoint_7: Configuration */ +#define OFS_USBOEPSIZXY_6 (0x23B7) /* Output Endpoint_6: X/Y-buffer size */ +#define OFS_USBOEPBCTY_6 (0x23B6) /* Output Endpoint_6: Y-byte count */ +#define OFS_USBOEPBBAY_6 (0x23B5) /* Output Endpoint_6: Y-buffer base addr. */ +//#define Spare_O (0x23B4) /* Not used */ +//#define Spare_O (0x23B3) /* Not used */ +#define OFS_USBOEPBCTX_6 (0x23B2) /* Output Endpoint_6: X-byte count */ +#define OFS_USBOEPBBAX_6 (0x23B1) /* Output Endpoint_6: X-buffer base addr. */ +#define OFS_USBOEPCNF_6 (0x23B0) /* Output Endpoint_6: Configuration */ +#define OFS_USBOEPSIZXY_5 (0x23AF) /* Output Endpoint_5: X/Y-buffer size */ +#define OFS_USBOEPBCTY_5 (0x23AE) /* Output Endpoint_5: Y-byte count */ +#define OFS_USBOEPBBAY_5 (0x23AD) /* Output Endpoint_5: Y-buffer base addr. */ +//#define Spare_O (0x23AC) /* Not used */ +//#define Spare_O (0x23AB) /* Not used */ +#define OFS_USBOEPBCTX_5 (0x23AA) /* Output Endpoint_5: X-byte count */ +#define OFS_USBOEPBBAX_5 (0x23A9) /* Output Endpoint_5: X-buffer base addr. */ +#define OFS_USBOEPCNF_5 (0x23A8) /* Output Endpoint_5: Configuration */ +#define OFS_USBOEPSIZXY_4 (0x23A7) /* Output Endpoint_4: X/Y-buffer size */ +#define OFS_USBOEPBCTY_4 (0x23A6) /* Output Endpoint_4: Y-byte count */ +#define OFS_USBOEPBBAY_4 (0x23A5) /* Output Endpoint_4: Y-buffer base addr. */ +//#define Spare_O (0x23A4) /* Not used */ +//#define Spare_O (0x23A3) /* Not used */ +#define OFS_USBOEPBCTX_4 (0x23A2) /* Output Endpoint_4: X-byte count */ +#define OFS_USBOEPBBAX_4 (0x23A1) /* Output Endpoint_4: X-buffer base addr. */ +#define OFS_USBOEPCNF_4 (0x23A0) /* Output Endpoint_4: Configuration */ +#define OFS_USBOEPSIZXY_3 (0x239F) /* Output Endpoint_3: X/Y-buffer size */ +#define OFS_USBOEPBCTY_3 (0x239E) /* Output Endpoint_3: Y-byte count */ +#define OFS_USBOEPBBAY_3 (0x239D) /* Output Endpoint_3: Y-buffer base addr. */ +//#define Spare_O (0x239C) /* Not used */ +//#define Spare_O (0x239B) /* Not used */ +#define OFS_USBOEPBCTX_3 (0x239A) /* Output Endpoint_3: X-byte count */ +#define OFS_USBOEPBBAX_3 (0x2399) /* Output Endpoint_3: X-buffer base addr. */ +#define OFS_USBOEPCNF_3 (0x2398) /* Output Endpoint_3: Configuration */ +#define OFS_USBOEPSIZXY_2 (0x2397) /* Output Endpoint_2: X/Y-buffer size */ +#define OFS_USBOEPBCTY_2 (0x2396) /* Output Endpoint_2: Y-byte count */ +#define OFS_USBOEPBBAY_2 (0x2395) /* Output Endpoint_2: Y-buffer base addr. */ +//#define Spare_O (0x2394) /* Not used */ +//#define Spare_O (0x2393) /* Not used */ +#define OFS_USBOEPBCTX_2 (0x2392) /* Output Endpoint_2: X-byte count */ +#define OFS_USBOEPBBAX_2 (0x2391) /* Output Endpoint_2: X-buffer base addr. */ +#define OFS_USBOEPCNF_2 (0x2390) /* Output Endpoint_2: Configuration */ +#define OFS_USBOEPSIZXY_1 (0x238F) /* Output Endpoint_1: X/Y-buffer size */ +#define OFS_USBOEPBCTY_1 (0x238E) /* Output Endpoint_1: Y-byte count */ +#define OFS_USBOEPBBAY_1 (0x238D) /* Output Endpoint_1: Y-buffer base addr. */ +//#define Spare_O (0x238C) /* Not used */ +//#define Spare_O (0x238B) /* Not used */ +#define OFS_USBOEPBCTX_1 (0x238A) /* Output Endpoint_1: X-byte count */ +#define OFS_USBOEPBBAX_1 (0x2389) /* Output Endpoint_1: X-buffer base addr. */ +#define OFS_USBOEPCNF_1 (0x2388) /* Output Endpoint_1: Configuration */ +#define OFS_USBSUBLK (0x2380) /* Setup Packet Block */ +#define OFS_USBIEP0BUF (0x2378) /* Input endpoint_0 buffer */ +#define OFS_USBOEP0BUF (0x2370) /* Output endpoint_0 buffer */ +#define OFS_USBTOPBUFF (0x236F) /* Top of buffer space */ +// (1904 Bytes) /* Buffer space */ +#define OFS_USBSTABUFF (0x1C00) /* Start of buffer space */ + +/* USBIEPCNF_n Control Bits */ +/* USBOEPCNF_n Control Bits */ +//#define RESERVED (0x0001) /* USB - */ +//#define RESERVED (0x0001) /* USB - */ +#define DBUF (0x0010) /* USB - Double Buffer Enable */ +//#define RESERVED (0x0040) /* USB - */ + +/* USBIEPBCNT_n Control Bits */ +/* USBOEPBCNT_n Control Bits */ +#define CNT4 (0x0010) /* USB - Byte Count Bit 3 */ +#define CNT5 (0x0020) /* USB - Byte Count Bit 3 */ +#define CNT6 (0x0040) /* USB - Byte Count Bit 3 */ +#endif +/************************************************************ +* USCI Ax +************************************************************/ +#ifdef __MSP430_HAS_USCI_Ax__ /* Definition to show that Module is available */ + +#define OFS_UCAxCTLW0 (0x0000) /* USCI Ax Control Word Register 0 */ +#define OFS_UCAxCTLW0_L OFS_UCAxCTLW0 +#define OFS_UCAxCTLW0_H OFS_UCAxCTLW0+1 +#define OFS_UCAxCTL0 (0x0001) +#define OFS_UCAxCTL1 (0x0000) +#define UCAxCTL1 UCAxCTLW0_L /* USCI Ax Control Register 1 */ +#define UCAxCTL0 UCAxCTLW0_H /* USCI Ax Control Register 0 */ +#define OFS_UCAxBRW (0x0006) /* USCI Ax Baud Word Rate 0 */ +#define OFS_UCAxBRW_L OFS_UCAxBRW +#define OFS_UCAxBRW_H OFS_UCAxBRW+1 +#define OFS_UCAxBR0 (0x0006) +#define OFS_UCAxBR1 (0x0007) +#define UCAxBR0 UCAxBRW_L /* USCI Ax Baud Rate 0 */ +#define UCAxBR1 UCAxBRW_H /* USCI Ax Baud Rate 1 */ +#define OFS_UCAxMCTL (0x0008) /* USCI Ax Modulation Control */ +#define OFS_UCAxSTAT (0x000A) /* USCI Ax Status Register */ +#define OFS_UCAxRXBUF (0x000C) /* USCI Ax Receive Buffer */ +#define OFS_UCAxTXBUF (0x000E) /* USCI Ax Transmit Buffer */ +#define OFS_UCAxABCTL (0x0010) /* USCI Ax LIN Control */ +#define OFS_UCAxIRCTL (0x0012) /* USCI Ax IrDA Transmit Control */ +#define OFS_UCAxIRCTL_L OFS_UCAxIRCTL +#define OFS_UCAxIRCTL_H OFS_UCAxIRCTL+1 +#define OFS_UCAxIRTCTL (0x0012) +#define OFS_UCAxIRRCTL (0x0013) +#define UCAxIRTCTL UCAxIRCTL_L /* USCI Ax IrDA Transmit Control */ +#define UCAxIRRCTL UCAxIRCTL_H /* USCI Ax IrDA Receive Control */ +#define OFS_UCAxICTL (0x001C) /* USCI Ax Interrupt Enable Register */ +#define OFS_UCAxICTL_L OFS_UCAxICTL +#define OFS_UCAxICTL_H OFS_UCAxICTL+1 +#define OFS_UCAxIE (0x001C) +#define OFS_UCAxIFG (0x001D) +#define UCAxIE UCAxICTL_L /* USCI Ax Interrupt Enable Register */ +#define UCAxIFG UCAxICTL_H /* USCI Ax Interrupt Flags Register */ +#define OFS_UCAxIV (0x001E) /* USCI Ax Interrupt Vector Register */ + +#define OFS_UCAxCTLW0__SPI (0x0000) +#define OFS_UCAxCTLW0__SPI_L OFS_UCAxCTLW0__SPI +#define OFS_UCAxCTLW0__SPI_H OFS_UCAxCTLW0__SPI+1 +#define OFS_UCAxCTL0__SPI (0x0001) +#define OFS_UCAxCTL1__SPI (0x0000) +#define OFS_UCAxBRW__SPI (0x0006) +#define OFS_UCAxBRW__SPI_L OFS_UCAxBRW__SPI +#define OFS_UCAxBRW__SPI_H OFS_UCAxBRW__SPI+1 +#define OFS_UCAxBR0__SPI (0x0006) +#define OFS_UCAxBR1__SPI (0x0007) +#define OFS_UCAxMCTL__SPI (0x0008) +#define OFS_UCAxSTAT__SPI (0x000A) +#define OFS_UCAxRXBUF__SPI (0x000C) +#define OFS_UCAxTXBUF__SPI (0x000E) +#define OFS_UCAxICTL__SPI (0x001C) +#define OFS_UCAxICTL__SPI_L OFS_UCAxICTL__SPI +#define OFS_UCAxICTL__SPI_H OFS_UCAxICTL__SPI+1 +#define OFS_UCAxIE__SPI (0x001C) +#define OFS_UCAxIFG__SPI (0x001D) +#define OFS_UCAxIV__SPI (0x001E) + +#endif +/************************************************************ +* USCI Bx +************************************************************/ +#ifdef __MSP430_HAS_USCI_Bx__ /* Definition to show that Module is available */ + +#define OFS_UCBxCTLW0__SPI (0x0000) +#define OFS_UCBxCTLW0__SPI_L OFS_UCBxCTLW0__SPI +#define OFS_UCBxCTLW0__SPI_H OFS_UCBxCTLW0__SPI+1 +#define OFS_UCBxCTL0__SPI (0x0001) +#define OFS_UCBxCTL1__SPI (0x0000) +#define OFS_UCBxBRW__SPI (0x0006) +#define OFS_UCBxBRW__SPI_L OFS_UCBxBRW__SPI +#define OFS_UCBxBRW__SPI_H OFS_UCBxBRW__SPI+1 +#define OFS_UCBxBR0__SPI (0x0006) +#define OFS_UCBxBR1__SPI (0x0007) +#define OFS_UCBxSTAT__SPI (0x000A) +#define OFS_UCBxRXBUF__SPI (0x000C) +#define OFS_UCBxTXBUF__SPI (0x000E) +#define OFS_UCBxICTL__SPI (0x001C) +#define OFS_UCBxICTL__SPI_L OFS_UCBxICTL__SPI +#define OFS_UCBxICTL__SPI_H OFS_UCBxICTL__SPI+1 +#define OFS_UCBxIE__SPI (0x001C) +#define OFS_UCBxIFG__SPI (0x001D) +#define OFS_UCBxIV__SPI (0x001E) + +#define OFS_UCBxCTLW0 (0x0000) /* USCI Bx Control Word Register 0 */ +#define OFS_UCBxCTLW0_L OFS_UCBxCTLW0 +#define OFS_UCBxCTLW0_H OFS_UCBxCTLW0+1 +#define OFS_UCBxCTL0 (0x0001) +#define OFS_UCBxCTL1 (0x0000) +#define UCBxCTL1 UCBxCTLW0_L /* USCI Bx Control Register 1 */ +#define UCBxCTL0 UCBxCTLW0_H /* USCI Bx Control Register 0 */ +#define OFS_UCBxBRW (0x0006) /* USCI Bx Baud Word Rate 0 */ +#define OFS_UCBxBRW_L OFS_UCBxBRW +#define OFS_UCBxBRW_H OFS_UCBxBRW+1 +#define OFS_UCBxBR0 (0x0006) +#define OFS_UCBxBR1 (0x0007) +#define UCBxBR0 UCBxBRW_L /* USCI Bx Baud Rate 0 */ +#define UCBxBR1 UCBxBRW_H /* USCI Bx Baud Rate 1 */ +#define OFS_UCBxSTAT (0x000A) /* USCI Bx Status Register */ +#define OFS_UCBxRXBUF (0x000C) /* USCI Bx Receive Buffer */ +#define OFS_UCBxTXBUF (0x000E) /* USCI Bx Transmit Buffer */ +#define OFS_UCBxI2COA (0x0010) /* USCI Bx I2C Own Address */ +#define OFS_UCBxI2COA_L OFS_UCBxI2COA +#define OFS_UCBxI2COA_H OFS_UCBxI2COA+1 +#define OFS_UCBxI2CSA (0x0012) /* USCI Bx I2C Slave Address */ +#define OFS_UCBxI2CSA_L OFS_UCBxI2CSA +#define OFS_UCBxI2CSA_H OFS_UCBxI2CSA+1 +#define OFS_UCBxICTL (0x001C) /* USCI Bx Interrupt Enable Register */ +#define OFS_UCBxICTL_L OFS_UCBxICTL +#define OFS_UCBxICTL_H OFS_UCBxICTL+1 +#define OFS_UCBxIE (0x001C) +#define OFS_UCBxIFG (0x001D) +#define UCBxIE UCBxICTL_L /* USCI Bx Interrupt Enable Register */ +#define UCBxIFG UCBxICTL_H /* USCI Bx Interrupt Flags Register */ +#define OFS_UCBxIV (0x001E) /* USCI Bx Interrupt Vector Register */ + +#endif +#if (defined(__MSP430_HAS_USCI_Ax__) || defined(__MSP430_HAS_USCI_Bx__)) + +// UCAxCTL0 UART-Mode Control Bits +#define UCPEN (0x80) /* Async. Mode: Parity enable */ +#define UCPAR (0x40) /* Async. Mode: Parity 0:odd / 1:even */ +#define UCMSB (0x20) /* Async. Mode: MSB first 0:LSB / 1:MSB */ +#define UC7BIT (0x10) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */ +#define UCSPB (0x08) /* Async. Mode: Stop Bits 0:one / 1: two */ +#define UCMODE1 (0x04) /* Async. Mode: USCI Mode 1 */ +#define UCMODE0 (0x02) /* Async. Mode: USCI Mode 0 */ +#define UCSYNC (0x01) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */ + +// UCxxCTL0 SPI-Mode Control Bits +#define UCCKPH (0x80) /* Sync. Mode: Clock Phase */ +#define UCCKPL (0x40) /* Sync. Mode: Clock Polarity */ +#define UCMST (0x08) /* Sync. Mode: Master Select */ + +// UCBxCTL0 I2C-Mode Control Bits +#define UCA10 (0x80) /* 10-bit Address Mode */ +#define UCSLA10 (0x40) /* 10-bit Slave Address Mode */ +#define UCMM (0x20) /* Multi-Master Environment */ +//#define res (0x10) /* reserved */ +#define UCMODE_0 (0x00) /* Sync. Mode: USCI Mode: 0 */ +#define UCMODE_1 (0x02) /* Sync. Mode: USCI Mode: 1 */ +#define UCMODE_2 (0x04) /* Sync. Mode: USCI Mode: 2 */ +#define UCMODE_3 (0x06) /* Sync. Mode: USCI Mode: 3 */ + +// UCAxCTL1 UART-Mode Control Bits +#define UCSSEL1 (0x80) /* USCI 0 Clock Source Select 1 */ +#define UCSSEL0 (0x40) /* USCI 0 Clock Source Select 0 */ +#define UCRXEIE (0x20) /* RX Error interrupt enable */ +#define UCBRKIE (0x10) /* Break interrupt enable */ +#define UCDORM (0x08) /* Dormant (Sleep) Mode */ +#define UCTXADDR (0x04) /* Send next Data as Address */ +#define UCTXBRK (0x02) /* Send next Data as Break */ +#define UCSWRST (0x01) /* USCI Software Reset */ + +// UCxxCTL1 SPI-Mode Control Bits +//#define res (0x20) /* reserved */ +//#define res (0x10) /* reserved */ +//#define res (0x08) /* reserved */ +//#define res (0x04) /* reserved */ +//#define res (0x02) /* reserved */ + +// UCBxCTL1 I2C-Mode Control Bits +//#define res (0x20) /* reserved */ +#define UCTR (0x10) /* Transmit/Receive Select/Flag */ +#define UCTXNACK (0x08) /* Transmit NACK */ +#define UCTXSTP (0x04) /* Transmit STOP */ +#define UCTXSTT (0x02) /* Transmit START */ +#define UCSSEL_0 (0x00) /* USCI 0 Clock Source: 0 */ +#define UCSSEL_1 (0x40) /* USCI 0 Clock Source: 1 */ +#define UCSSEL_2 (0x80) /* USCI 0 Clock Source: 2 */ +#define UCSSEL_3 (0xC0) /* USCI 0 Clock Source: 3 */ +#define UCSSEL__UCLK (0x00) /* USCI 0 Clock Source: UCLK */ +#define UCSSEL__ACLK (0x40) /* USCI 0 Clock Source: ACLK */ +#define UCSSEL__SMCLK (0x80) /* USCI 0 Clock Source: SMCLK */ + +/* UCAxMCTL Control Bits */ +#define UCBRF3 (0x80) /* USCI First Stage Modulation Select 3 */ +#define UCBRF2 (0x40) /* USCI First Stage Modulation Select 2 */ +#define UCBRF1 (0x20) /* USCI First Stage Modulation Select 1 */ +#define UCBRF0 (0x10) /* USCI First Stage Modulation Select 0 */ +#define UCBRS2 (0x08) /* USCI Second Stage Modulation Select 2 */ +#define UCBRS1 (0x04) /* USCI Second Stage Modulation Select 1 */ +#define UCBRS0 (0x02) /* USCI Second Stage Modulation Select 0 */ +#define UCOS16 (0x01) /* USCI 16-times Oversampling enable */ + +#define UCBRF_0 (0x00) /* USCI First Stage Modulation: 0 */ +#define UCBRF_1 (0x10) /* USCI First Stage Modulation: 1 */ +#define UCBRF_2 (0x20) /* USCI First Stage Modulation: 2 */ +#define UCBRF_3 (0x30) /* USCI First Stage Modulation: 3 */ +#define UCBRF_4 (0x40) /* USCI First Stage Modulation: 4 */ +#define UCBRF_5 (0x50) /* USCI First Stage Modulation: 5 */ +#define UCBRF_6 (0x60) /* USCI First Stage Modulation: 6 */ +#define UCBRF_7 (0x70) /* USCI First Stage Modulation: 7 */ +#define UCBRF_8 (0x80) /* USCI First Stage Modulation: 8 */ +#define UCBRF_9 (0x90) /* USCI First Stage Modulation: 9 */ +#define UCBRF_10 (0xA0) /* USCI First Stage Modulation: A */ +#define UCBRF_11 (0xB0) /* USCI First Stage Modulation: B */ +#define UCBRF_12 (0xC0) /* USCI First Stage Modulation: C */ +#define UCBRF_13 (0xD0) /* USCI First Stage Modulation: D */ +#define UCBRF_14 (0xE0) /* USCI First Stage Modulation: E */ +#define UCBRF_15 (0xF0) /* USCI First Stage Modulation: F */ + +#define UCBRS_0 (0x00) /* USCI Second Stage Modulation: 0 */ +#define UCBRS_1 (0x02) /* USCI Second Stage Modulation: 1 */ +#define UCBRS_2 (0x04) /* USCI Second Stage Modulation: 2 */ +#define UCBRS_3 (0x06) /* USCI Second Stage Modulation: 3 */ +#define UCBRS_4 (0x08) /* USCI Second Stage Modulation: 4 */ +#define UCBRS_5 (0x0A) /* USCI Second Stage Modulation: 5 */ +#define UCBRS_6 (0x0C) /* USCI Second Stage Modulation: 6 */ +#define UCBRS_7 (0x0E) /* USCI Second Stage Modulation: 7 */ + +/* UCAxSTAT Control Bits */ +#define UCLISTEN (0x80) /* USCI Listen mode */ +#define UCFE (0x40) /* USCI Frame Error Flag */ +#define UCOE (0x20) /* USCI Overrun Error Flag */ +#define UCPE (0x10) /* USCI Parity Error Flag */ +#define UCBRK (0x08) /* USCI Break received */ +#define UCRXERR (0x04) /* USCI RX Error Flag */ +#define UCADDR (0x02) /* USCI Address received Flag */ +#define UCBUSY (0x01) /* USCI Busy Flag */ +#define UCIDLE (0x02) /* USCI Idle line detected Flag */ + +/* UCBxSTAT Control Bits */ +#define UCSCLLOW (0x40) /* SCL low */ +#define UCGC (0x20) /* General Call address received Flag */ +#define UCBBUSY (0x10) /* Bus Busy Flag */ + +/* UCAxIRTCTL Control Bits */ +#define UCIRTXPL5 (0x80) /* IRDA Transmit Pulse Length 5 */ +#define UCIRTXPL4 (0x40) /* IRDA Transmit Pulse Length 4 */ +#define UCIRTXPL3 (0x20) /* IRDA Transmit Pulse Length 3 */ +#define UCIRTXPL2 (0x10) /* IRDA Transmit Pulse Length 2 */ +#define UCIRTXPL1 (0x08) /* IRDA Transmit Pulse Length 1 */ +#define UCIRTXPL0 (0x04) /* IRDA Transmit Pulse Length 0 */ +#define UCIRTXCLK (0x02) /* IRDA Transmit Pulse Clock Select */ +#define UCIREN (0x01) /* IRDA Encoder/Decoder enable */ + +/* UCAxIRRCTL Control Bits */ +#define UCIRRXFL5 (0x80) /* IRDA Receive Filter Length 5 */ +#define UCIRRXFL4 (0x40) /* IRDA Receive Filter Length 4 */ +#define UCIRRXFL3 (0x20) /* IRDA Receive Filter Length 3 */ +#define UCIRRXFL2 (0x10) /* IRDA Receive Filter Length 2 */ +#define UCIRRXFL1 (0x08) /* IRDA Receive Filter Length 1 */ +#define UCIRRXFL0 (0x04) /* IRDA Receive Filter Length 0 */ +#define UCIRRXPL (0x02) /* IRDA Receive Input Polarity */ +#define UCIRRXFE (0x01) /* IRDA Receive Filter enable */ + +/* UCAxABCTL Control Bits */ +//#define res (0x80) /* reserved */ +//#define res (0x40) /* reserved */ +#define UCDELIM1 (0x20) /* Break Sync Delimiter 1 */ +#define UCDELIM0 (0x10) /* Break Sync Delimiter 0 */ +#define UCSTOE (0x08) /* Sync-Field Timeout error */ +#define UCBTOE (0x04) /* Break Timeout error */ +//#define res (0x02) /* reserved */ +#define UCABDEN (0x01) /* Auto Baud Rate detect enable */ + +/* UCBxI2COA Control Bits */ +#define UCGCEN (0x8000) /* I2C General Call enable */ +#define UCOA9 (0x0200) /* I2C Own Address 9 */ +#define UCOA8 (0x0100) /* I2C Own Address 8 */ +#define UCOA7 (0x0080) /* I2C Own Address 7 */ +#define UCOA6 (0x0040) /* I2C Own Address 6 */ +#define UCOA5 (0x0020) /* I2C Own Address 5 */ +#define UCOA4 (0x0010) /* I2C Own Address 4 */ +#define UCOA3 (0x0008) /* I2C Own Address 3 */ +#define UCOA2 (0x0004) /* I2C Own Address 2 */ +#define UCOA1 (0x0002) /* I2C Own Address 1 */ +#define UCOA0 (0x0001) /* I2C Own Address 0 */ + +/* UCBxI2COA Control Bits */ +#define UCOA7_L (0x0080) /* I2C Own Address 7 */ +#define UCOA6_L (0x0040) /* I2C Own Address 6 */ +#define UCOA5_L (0x0020) /* I2C Own Address 5 */ +#define UCOA4_L (0x0010) /* I2C Own Address 4 */ +#define UCOA3_L (0x0008) /* I2C Own Address 3 */ +#define UCOA2_L (0x0004) /* I2C Own Address 2 */ +#define UCOA1_L (0x0002) /* I2C Own Address 1 */ +#define UCOA0_L (0x0001) /* I2C Own Address 0 */ + +/* UCBxI2COA Control Bits */ +#define UCGCEN_H (0x0080) /* I2C General Call enable */ +#define UCOA9_H (0x0002) /* I2C Own Address 9 */ +#define UCOA8_H (0x0001) /* I2C Own Address 8 */ + +/* UCBxI2CSA Control Bits */ +#define UCSA9 (0x0200) /* I2C Slave Address 9 */ +#define UCSA8 (0x0100) /* I2C Slave Address 8 */ +#define UCSA7 (0x0080) /* I2C Slave Address 7 */ +#define UCSA6 (0x0040) /* I2C Slave Address 6 */ +#define UCSA5 (0x0020) /* I2C Slave Address 5 */ +#define UCSA4 (0x0010) /* I2C Slave Address 4 */ +#define UCSA3 (0x0008) /* I2C Slave Address 3 */ +#define UCSA2 (0x0004) /* I2C Slave Address 2 */ +#define UCSA1 (0x0002) /* I2C Slave Address 1 */ +#define UCSA0 (0x0001) /* I2C Slave Address 0 */ + +/* UCBxI2CSA Control Bits */ +#define UCSA7_L (0x0080) /* I2C Slave Address 7 */ +#define UCSA6_L (0x0040) /* I2C Slave Address 6 */ +#define UCSA5_L (0x0020) /* I2C Slave Address 5 */ +#define UCSA4_L (0x0010) /* I2C Slave Address 4 */ +#define UCSA3_L (0x0008) /* I2C Slave Address 3 */ +#define UCSA2_L (0x0004) /* I2C Slave Address 2 */ +#define UCSA1_L (0x0002) /* I2C Slave Address 1 */ +#define UCSA0_L (0x0001) /* I2C Slave Address 0 */ + +/* UCBxI2CSA Control Bits */ +#define UCSA9_H (0x0002) /* I2C Slave Address 9 */ +#define UCSA8_H (0x0001) /* I2C Slave Address 8 */ + +/* UCAxIE Control Bits */ +#define UCTXIE (0x0002) /* USCI Transmit Interrupt Enable */ +#define UCRXIE (0x0001) /* USCI Receive Interrupt Enable */ + +/* UCAxIE Control Bits */ +#define UCTXIE_L (0x0002) /* USCI Transmit Interrupt Enable */ +#define UCRXIE_L (0x0001) /* USCI Receive Interrupt Enable */ + +/* UCBxIE Control Bits */ +#define UCNACKIE (0x0020) /* NACK Condition interrupt enable */ +#define UCALIE (0x0010) /* Arbitration Lost interrupt enable */ +#define UCSTPIE (0x0008) /* STOP Condition interrupt enable */ +#define UCSTTIE (0x0004) /* START Condition interrupt enable */ +#define UCTXIE (0x0002) /* USCI Transmit Interrupt Enable */ +#define UCRXIE (0x0001) /* USCI Receive Interrupt Enable */ + +/* UCBxIE Control Bits */ +#define UCNACKIE_L (0x0020) /* NACK Condition interrupt enable */ +#define UCALIE_L (0x0010) /* Arbitration Lost interrupt enable */ +#define UCSTPIE_L (0x0008) /* STOP Condition interrupt enable */ +#define UCSTTIE_L (0x0004) /* START Condition interrupt enable */ +#define UCTXIE_L (0x0002) /* USCI Transmit Interrupt Enable */ +#define UCRXIE_L (0x0001) /* USCI Receive Interrupt Enable */ + +/* UCAxIFG Control Bits */ +#define UCTXIFG (0x0002) /* USCI Transmit Interrupt Flag */ +#define UCRXIFG (0x0001) /* USCI Receive Interrupt Flag */ + +/* UCAxIFG Control Bits */ +#define UCTXIFG_L (0x0002) /* USCI Transmit Interrupt Flag */ +#define UCRXIFG_L (0x0001) /* USCI Receive Interrupt Flag */ + +/* UCBxIFG Control Bits */ +#define UCNACKIFG (0x0020) /* NAK Condition interrupt Flag */ +#define UCALIFG (0x0010) /* Arbitration Lost interrupt Flag */ +#define UCSTPIFG (0x0008) /* STOP Condition interrupt Flag */ +#define UCSTTIFG (0x0004) /* START Condition interrupt Flag */ +#define UCTXIFG (0x0002) /* USCI Transmit Interrupt Flag */ +#define UCRXIFG (0x0001) /* USCI Receive Interrupt Flag */ + +/* UCBxIFG Control Bits */ +#define UCNACKIFG_L (0x0020) /* NAK Condition interrupt Flag */ +#define UCALIFG_L (0x0010) /* Arbitration Lost interrupt Flag */ +#define UCSTPIFG_L (0x0008) /* STOP Condition interrupt Flag */ +#define UCSTTIFG_L (0x0004) /* START Condition interrupt Flag */ +#define UCTXIFG_L (0x0002) /* USCI Transmit Interrupt Flag */ +#define UCRXIFG_L (0x0001) /* USCI Receive Interrupt Flag */ + +/* USCI Definitions */ +#define USCI_NONE (0x0000) /* No Interrupt pending */ +#define USCI_UCRXIFG (0x0002) /* USCI UCRXIFG */ +#define USCI_UCTXIFG (0x0004) /* USCI UCTXIFG */ +#define USCI_I2C_UCALIFG (0x0002) /* USCI I2C Mode: UCALIFG */ +#define USCI_I2C_UCNACKIFG (0x0004) /* USCI I2C Mode: UCNACKIFG */ +#define USCI_I2C_UCSTTIFG (0x0006) /* USCI I2C Mode: UCSTTIFG*/ +#define USCI_I2C_UCSTPIFG (0x0008) /* USCI I2C Mode: UCSTPIFG*/ +#define USCI_I2C_UCRXIFG (0x000A) /* USCI I2C Mode: UCRXIFG */ +#define USCI_I2C_UCTXIFG (0x000C) /* USCI I2C Mode: UCTXIFG */ + +#endif +/************************************************************ +* USCI Ax +************************************************************/ +#ifdef __MSP430_HAS_EUSCI_Ax__ /* Definition to show that Module is available */ + +#define OFS_UCAxCTLW0 (0x0000) /* USCI Ax Control Word Register 0 */ +#define OFS_UCAxCTLW0_L OFS_UCAxCTLW0 +#define OFS_UCAxCTLW0_H OFS_UCAxCTLW0+1 +#define OFS_UCAxCTL0 (0x0001) +#define OFS_UCAxCTL1 (0x0000) +#define UCAxCTL1 UCAxCTLW0_L /* USCI Ax Control Register 1 */ +#define UCAxCTL0 UCAxCTLW0_H /* USCI Ax Control Register 0 */ +#define OFS_UCAxCTLW1 (0x0002) /* USCI Ax Control Word Register 1 */ +#define OFS_UCAxCTLW1_L OFS_UCAxCTLW1 +#define OFS_UCAxCTLW1_H OFS_UCAxCTLW1+1 +#define OFS_UCAxBRW (0x0006) /* USCI Ax Baud Word Rate 0 */ +#define OFS_UCAxBRW_L OFS_UCAxBRW +#define OFS_UCAxBRW_H OFS_UCAxBRW+1 +#define OFS_UCAxBR0 (0x0006) +#define OFS_UCAxBR1 (0x0007) +#define UCAxBR0 UCAxBRW_L /* USCI Ax Baud Rate 0 */ +#define UCAxBR1 UCAxBRW_H /* USCI Ax Baud Rate 1 */ +#define OFS_UCAxMCTLW (0x0008) /* USCI Ax Modulation Control */ +#define OFS_UCAxMCTLW_L OFS_UCAxMCTLW +#define OFS_UCAxMCTLW_H OFS_UCAxMCTLW+1 +#define OFS_UCAxSTATW (0x000A) /* USCI Ax Status Register */ +#define OFS_UCAxRXBUF (0x000C) /* USCI Ax Receive Buffer */ +#define OFS_UCAxRXBUF_L OFS_UCAxRXBUF +#define OFS_UCAxRXBUF_H OFS_UCAxRXBUF+1 +#define OFS_UCAxTXBUF (0x000E) /* USCI Ax Transmit Buffer */ +#define OFS_UCAxTXBUF_L OFS_UCAxTXBUF +#define OFS_UCAxTXBUF_H OFS_UCAxTXBUF+1 +#define OFS_UCAxABCTL (0x0010) /* USCI Ax LIN Control */ +#define OFS_UCAxIRCTL (0x0012) /* USCI Ax IrDA Transmit Control */ +#define OFS_UCAxIRCTL_L OFS_UCAxIRCTL +#define OFS_UCAxIRCTL_H OFS_UCAxIRCTL+1 +#define OFS_UCAxIRTCTL (0x0012) +#define OFS_UCAxIRRCTL (0x0013) +#define UCAxIRTCTL UCAxIRCTL_L /* USCI Ax IrDA Transmit Control */ +#define UCAxIRRCTL UCAxIRCTL_H /* USCI Ax IrDA Receive Control */ +#define OFS_UCAxIE (0x001A) /* USCI Ax Interrupt Enable Register */ +#define OFS_UCAxIE_L OFS_UCAxIE +#define OFS_UCAxIE_H OFS_UCAxIE+1 +#define OFS_UCAxIFG (0x001C) /* USCI Ax Interrupt Flags Register */ +#define OFS_UCAxIFG_L OFS_UCAxIFG +#define OFS_UCAxIFG_H OFS_UCAxIFG+1 +#define OFS_UCAxIE__UART (0x001A) +#define OFS_UCAxIE__UART_L OFS_UCAxIE__UART +#define OFS_UCAxIE__UART_H OFS_UCAxIE__UART+1 +#define OFS_UCAxIFG__UART (0x001C) +#define OFS_UCAxIFG__UART_L OFS_UCAxIFG__UART +#define OFS_UCAxIFG__UART_H OFS_UCAxIFG__UART+1 +#define OFS_UCAxIV (0x001E) /* USCI Ax Interrupt Vector Register */ + +#define OFS_UCAxCTLW0__SPI (0x0000) +#define OFS_UCAxCTLW0__SPI_L OFS_UCAxCTLW0__SPI +#define OFS_UCAxCTLW0__SPI_H OFS_UCAxCTLW0__SPI+1 +#define OFS_UCAxCTL0__SPI (0x0001) +#define OFS_UCAxCTL1__SPI (0x0000) +#define OFS_UCAxBRW__SPI (0x0006) +#define OFS_UCAxBRW__SPI_L OFS_UCAxBRW__SPI +#define OFS_UCAxBRW__SPI_H OFS_UCAxBRW__SPI+1 +#define OFS_UCAxBR0__SPI (0x0006) +#define OFS_UCAxBR1__SPI (0x0007) +#define OFS_UCAxSTATW__SPI (0x000A) +#define OFS_UCAxRXBUF__SPI (0x000C) +#define OFS_UCAxRXBUF__SPI_L OFS_UCAxRXBUF__SPI +#define OFS_UCAxRXBUF__SPI_H OFS_UCAxRXBUF__SPI+1 +#define OFS_UCAxTXBUF__SPI (0x000E) +#define OFS_UCAxTXBUF__SPI_L OFS_UCAxTXBUF__SPI +#define OFS_UCAxTXBUF__SPI_H OFS_UCAxTXBUF__SPI+1 +#define OFS_UCAxIE__SPI (0x001A) +#define OFS_UCAxIFG__SPI (0x001C) +#define OFS_UCAxIV__SPI (0x001E) + +#endif +/************************************************************ +* USCI Bx +************************************************************/ +#ifdef __MSP430_HAS_EUSCI_Bx__ /* Definition to show that Module is available */ + +#define OFS_UCBxCTLW0__SPI (0x0000) +#define OFS_UCBxCTLW0__SPI_L OFS_UCBxCTLW0__SPI +#define OFS_UCBxCTLW0__SPI_H OFS_UCBxCTLW0__SPI+1 +#define OFS_UCBxCTL0__SPI (0x0001) +#define OFS_UCBxCTL1__SPI (0x0000) +#define OFS_UCBxBRW__SPI (0x0006) +#define OFS_UCBxBRW__SPI_L OFS_UCBxBRW__SPI +#define OFS_UCBxBRW__SPI_H OFS_UCBxBRW__SPI+1 +#define OFS_UCBxBR0__SPI (0x0006) +#define OFS_UCBxBR1__SPI (0x0007) +#define OFS_UCBxSTATW__SPI (0x0008) +#define OFS_UCBxSTATW__SPI_L OFS_UCBxSTATW__SPI +#define OFS_UCBxSTATW__SPI_H OFS_UCBxSTATW__SPI+1 +#define OFS_UCBxRXBUF__SPI (0x000C) +#define OFS_UCBxRXBUF__SPI_L OFS_UCBxRXBUF__SPI +#define OFS_UCBxRXBUF__SPI_H OFS_UCBxRXBUF__SPI+1 +#define OFS_UCBxTXBUF__SPI (0x000E) +#define OFS_UCBxTXBUF__SPI_L OFS_UCBxTXBUF__SPI +#define OFS_UCBxTXBUF__SPI_H OFS_UCBxTXBUF__SPI+1 +#define OFS_UCBxIE__SPI (0x002A) +#define OFS_UCBxIE__SPI_L OFS_UCBxIE__SPI +#define OFS_UCBxIE__SPI_H OFS_UCBxIE__SPI+1 +#define OFS_UCBxIFG__SPI (0x002C) +#define OFS_UCBxIFG__SPI_L OFS_UCBxIFG__SPI +#define OFS_UCBxIFG__SPI_H OFS_UCBxIFG__SPI+1 +#define OFS_UCBxIV__SPI (0x002E) + +#define OFS_UCBxCTLW0 (0x0000) /* USCI Bx Control Word Register 0 */ +#define OFS_UCBxCTLW0_L OFS_UCBxCTLW0 +#define OFS_UCBxCTLW0_H OFS_UCBxCTLW0+1 +#define OFS_UCBxCTL0 (0x0001) +#define OFS_UCBxCTL1 (0x0000) +#define UCBxCTL1 UCBxCTLW0_L /* USCI Bx Control Register 1 */ +#define UCBxCTL0 UCBxCTLW0_H /* USCI Bx Control Register 0 */ +#define OFS_UCBxCTLW1 (0x0002) /* USCI Bx Control Word Register 1 */ +#define OFS_UCBxCTLW1_L OFS_UCBxCTLW1 +#define OFS_UCBxCTLW1_H OFS_UCBxCTLW1+1 +#define OFS_UCBxBRW (0x0006) /* USCI Bx Baud Word Rate 0 */ +#define OFS_UCBxBRW_L OFS_UCBxBRW +#define OFS_UCBxBRW_H OFS_UCBxBRW+1 +#define OFS_UCBxBR0 (0x0006) +#define OFS_UCBxBR1 (0x0007) +#define UCBxBR0 UCBxBRW_L /* USCI Bx Baud Rate 0 */ +#define UCBxBR1 UCBxBRW_H /* USCI Bx Baud Rate 1 */ +#define OFS_UCBxSTATW (0x0008) /* USCI Bx Status Word Register */ +#define OFS_UCBxSTATW_L OFS_UCBxSTATW +#define OFS_UCBxSTATW_H OFS_UCBxSTATW+1 +#define OFS_UCBxSTATW__I2C (0x0008) +#define OFS_UCBxSTAT__I2C (0x0008) +#define OFS_UCBxBCNT__I2C (0x0009) +#define UCBxSTAT UCBxSTATW_L /* USCI Bx Status Register */ +#define UCBxBCNT UCBxSTATW_H /* USCI Bx Byte Counter Register */ +#define OFS_UCBxTBCNT (0x000A) /* USCI Bx Byte Counter Threshold Register */ +#define OFS_UCBxTBCNT_L OFS_UCBxTBCNT +#define OFS_UCBxTBCNT_H OFS_UCBxTBCNT+1 +#define OFS_UCBxRXBUF (0x000C) /* USCI Bx Receive Buffer */ +#define OFS_UCBxRXBUF_L OFS_UCBxRXBUF +#define OFS_UCBxRXBUF_H OFS_UCBxRXBUF+1 +#define OFS_UCBxTXBUF (0x000E) /* USCI Bx Transmit Buffer */ +#define OFS_UCBxTXBUF_L OFS_UCBxTXBUF +#define OFS_UCBxTXBUF_H OFS_UCBxTXBUF+1 +#define OFS_UCBxI2COA0 (0x0014) /* USCI Bx I2C Own Address 0 */ +#define OFS_UCBxI2COA0_L OFS_UCBxI2COA0 +#define OFS_UCBxI2COA0_H OFS_UCBxI2COA0+1 +#define OFS_UCBxI2COA1 (0x0016) /* USCI Bx I2C Own Address 1 */ +#define OFS_UCBxI2COA1_L OFS_UCBxI2COA1 +#define OFS_UCBxI2COA1_H OFS_UCBxI2COA1+1 +#define OFS_UCBxI2COA2 (0x0018) /* USCI Bx I2C Own Address 2 */ +#define OFS_UCBxI2COA2_L OFS_UCBxI2COA2 +#define OFS_UCBxI2COA2_H OFS_UCBxI2COA2+1 +#define OFS_UCBxI2COA3 (0x001A) /* USCI Bx I2C Own Address 3 */ +#define OFS_UCBxI2COA3_L OFS_UCBxI2COA3 +#define OFS_UCBxI2COA3_H OFS_UCBxI2COA3+1 +#define OFS_UCBxADDRX (0x001C) /* USCI Bx Received Address Register */ +#define OFS_UCBxADDRX_L OFS_UCBxADDRX +#define OFS_UCBxADDRX_H OFS_UCBxADDRX+1 +#define OFS_UCBxADDMASK (0x001E) /* USCI Bx Address Mask Register */ +#define OFS_UCBxADDMASK_L OFS_UCBxADDMASK +#define OFS_UCBxADDMASK_H OFS_UCBxADDMASK+1 +#define OFS_UCBxI2CSA (0x0020) /* USCI Bx I2C Slave Address */ +#define OFS_UCBxI2CSA_L OFS_UCBxI2CSA +#define OFS_UCBxI2CSA_H OFS_UCBxI2CSA+1 +#define OFS_UCBxIE (0x002A) /* USCI Bx Interrupt Enable Register */ +#define OFS_UCBxIE_L OFS_UCBxIE +#define OFS_UCBxIE_H OFS_UCBxIE+1 +#define OFS_UCBxIFG (0x002C) /* USCI Bx Interrupt Flags Register */ +#define OFS_UCBxIFG_L OFS_UCBxIFG +#define OFS_UCBxIFG_H OFS_UCBxIFG+1 +#define OFS_UCBxIE__I2C (0x002A) +#define OFS_UCBxIE__I2C_L OFS_UCBxIE__I2C +#define OFS_UCBxIE__I2C_H OFS_UCBxIE__I2C+1 +#define OFS_UCBxIFG__I2C (0x002C) +#define OFS_UCBxIFG__I2C_L OFS_UCBxIFG__I2C +#define OFS_UCBxIFG__I2C_H OFS_UCBxIFG__I2C+1 +#define OFS_UCBxIV (0x002E) /* USCI Bx Interrupt Vector Register */ + +#endif +#if (defined(__MSP430_HAS_EUSCI_Ax__) || defined(__MSP430_HAS_EUSCI_Bx__)) + +// UCAxCTLW0 UART-Mode Control Bits +#define UCPEN (0x8000) /* Async. Mode: Parity enable */ +#define UCPAR (0x4000) /* Async. Mode: Parity 0:odd / 1:even */ +#define UCMSB (0x2000) /* Async. Mode: MSB first 0:LSB / 1:MSB */ +#define UC7BIT (0x1000) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */ +#define UCSPB (0x0800) /* Async. Mode: Stop Bits 0:one / 1: two */ +#define UCMODE1 (0x0400) /* Async. Mode: USCI Mode 1 */ +#define UCMODE0 (0x0200) /* Async. Mode: USCI Mode 0 */ +#define UCSYNC (0x0100) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */ +#define UCSSEL1 (0x0080) /* USCI 0 Clock Source Select 1 */ +#define UCSSEL0 (0x0040) /* USCI 0 Clock Source Select 0 */ +#define UCRXEIE (0x0020) /* RX Error interrupt enable */ +#define UCBRKIE (0x0010) /* Break interrupt enable */ +#define UCDORM (0x0008) /* Dormant (Sleep) Mode */ +#define UCTXADDR (0x0004) /* Send next Data as Address */ +#define UCTXBRK (0x0002) /* Send next Data as Break */ +#define UCSWRST (0x0001) /* USCI Software Reset */ + +// UCAxCTLW0 UART-Mode Control Bits +#define UCSSEL1_L (0x0080) /* USCI 0 Clock Source Select 1 */ +#define UCSSEL0_L (0x0040) /* USCI 0 Clock Source Select 0 */ +#define UCRXEIE_L (0x0020) /* RX Error interrupt enable */ +#define UCBRKIE_L (0x0010) /* Break interrupt enable */ +#define UCDORM_L (0x0008) /* Dormant (Sleep) Mode */ +#define UCTXADDR_L (0x0004) /* Send next Data as Address */ +#define UCTXBRK_L (0x0002) /* Send next Data as Break */ +#define UCSWRST_L (0x0001) /* USCI Software Reset */ + +// UCAxCTLW0 UART-Mode Control Bits +#define UCPEN_H (0x0080) /* Async. Mode: Parity enable */ +#define UCPAR_H (0x0040) /* Async. Mode: Parity 0:odd / 1:even */ +#define UCMSB_H (0x0020) /* Async. Mode: MSB first 0:LSB / 1:MSB */ +#define UC7BIT_H (0x0010) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */ +#define UCSPB_H (0x0008) /* Async. Mode: Stop Bits 0:one / 1: two */ +#define UCMODE1_H (0x0004) /* Async. Mode: USCI Mode 1 */ +#define UCMODE0_H (0x0002) /* Async. Mode: USCI Mode 0 */ +#define UCSYNC_H (0x0001) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */ + +// UCxxCTLW0 SPI-Mode Control Bits +#define UCCKPH (0x8000) /* Sync. Mode: Clock Phase */ +#define UCCKPL (0x4000) /* Sync. Mode: Clock Polarity */ +#define UCMST (0x0800) /* Sync. Mode: Master Select */ +//#define res (0x0020) /* reserved */ +//#define res (0x0010) /* reserved */ +//#define res (0x0008) /* reserved */ +//#define res (0x0004) /* reserved */ +#define UCSTEM (0x0002) /* USCI STE Mode */ + +// UCBxCTLW0 I2C-Mode Control Bits +#define UCA10 (0x8000) /* 10-bit Address Mode */ +#define UCSLA10 (0x4000) /* 10-bit Slave Address Mode */ +#define UCMM (0x2000) /* Multi-Master Environment */ +//#define res (0x1000) /* reserved */ +//#define res (0x0100) /* reserved */ +#define UCTXACK (0x0020) /* Transmit ACK */ +#define UCTR (0x0010) /* Transmit/Receive Select/Flag */ +#define UCTXNACK (0x0008) /* Transmit NACK */ +#define UCTXSTP (0x0004) /* Transmit STOP */ +#define UCTXSTT (0x0002) /* Transmit START */ + +// UCBxCTLW0 I2C-Mode Control Bits +//#define res (0x1000) /* reserved */ +//#define res (0x0100) /* reserved */ +#define UCTXACK_L (0x0020) /* Transmit ACK */ +#define UCTR_L (0x0010) /* Transmit/Receive Select/Flag */ +#define UCTXNACK_L (0x0008) /* Transmit NACK */ +#define UCTXSTP_L (0x0004) /* Transmit STOP */ +#define UCTXSTT_L (0x0002) /* Transmit START */ + +// UCBxCTLW0 I2C-Mode Control Bits +#define UCA10_H (0x0080) /* 10-bit Address Mode */ +#define UCSLA10_H (0x0040) /* 10-bit Slave Address Mode */ +#define UCMM_H (0x0020) /* Multi-Master Environment */ +//#define res (0x1000) /* reserved */ +//#define res (0x0100) /* reserved */ + +#define UCMODE_0 (0x0000) /* Sync. Mode: USCI Mode: 0 */ +#define UCMODE_1 (0x0200) /* Sync. Mode: USCI Mode: 1 */ +#define UCMODE_2 (0x0400) /* Sync. Mode: USCI Mode: 2 */ +#define UCMODE_3 (0x0600) /* Sync. Mode: USCI Mode: 3 */ + +#define UCSSEL_0 (0x0000) /* USCI 0 Clock Source: 0 */ +#define UCSSEL_1 (0x0040) /* USCI 0 Clock Source: 1 */ +#define UCSSEL_2 (0x0080) /* USCI 0 Clock Source: 2 */ +#define UCSSEL_3 (0x00C0) /* USCI 0 Clock Source: 3 */ +#define UCSSEL__UCLK (0x0000) /* USCI 0 Clock Source: UCLK */ +#define UCSSEL__ACLK (0x0040) /* USCI 0 Clock Source: ACLK */ +#define UCSSEL__SMCLK (0x0080) /* USCI 0 Clock Source: SMCLK */ + +// UCAxCTLW1 UART-Mode Control Bits +#define UCGLIT1 (0x0002) /* USCI Deglitch Time Bit 1 */ +#define UCGLIT0 (0x0001) /* USCI Deglitch Time Bit 0 */ + +// UCAxCTLW1 UART-Mode Control Bits +#define UCGLIT1_L (0x0002) /* USCI Deglitch Time Bit 1 */ +#define UCGLIT0_L (0x0001) /* USCI Deglitch Time Bit 0 */ + +// UCBxCTLW1 I2C-Mode Control Bits +#define UCETXINT (0x0100) /* USCI Early UCTXIFG0 */ +#define UCCLTO1 (0x0080) /* USCI Clock low timeout Bit: 1 */ +#define UCCLTO0 (0x0040) /* USCI Clock low timeout Bit: 0 */ +#define UCSTPNACK (0x0020) /* USCI Acknowledge Stop last byte */ +#define UCSWACK (0x0010) /* USCI Software controlled ACK */ +#define UCASTP1 (0x0008) /* USCI Automatic Stop condition generation Bit: 1 */ +#define UCASTP0 (0x0004) /* USCI Automatic Stop condition generation Bit: 0 */ +#define UCGLIT1 (0x0002) /* USCI Deglitch time Bit: 1 */ +#define UCGLIT0 (0x0001) /* USCI Deglitch time Bit: 0 */ + +// UCBxCTLW1 I2C-Mode Control Bits +#define UCCLTO1_L (0x0080) /* USCI Clock low timeout Bit: 1 */ +#define UCCLTO0_L (0x0040) /* USCI Clock low timeout Bit: 0 */ +#define UCSTPNACK_L (0x0020) /* USCI Acknowledge Stop last byte */ +#define UCSWACK_L (0x0010) /* USCI Software controlled ACK */ +#define UCASTP1_L (0x0008) /* USCI Automatic Stop condition generation Bit: 1 */ +#define UCASTP0_L (0x0004) /* USCI Automatic Stop condition generation Bit: 0 */ +#define UCGLIT1_L (0x0002) /* USCI Deglitch time Bit: 1 */ +#define UCGLIT0_L (0x0001) /* USCI Deglitch time Bit: 0 */ + +// UCBxCTLW1 I2C-Mode Control Bits +#define UCETXINT_H (0x0001) /* USCI Early UCTXIFG0 */ + +#define UCGLIT_0 (0x0000) /* USCI Deglitch time: 0 */ +#define UCGLIT_1 (0x0001) /* USCI Deglitch time: 1 */ +#define UCGLIT_2 (0x0002) /* USCI Deglitch time: 2 */ +#define UCGLIT_3 (0x0003) /* USCI Deglitch time: 3 */ + +#define UCASTP_0 (0x0000) /* USCI Automatic Stop condition generation: 0 */ +#define UCASTP_1 (0x0004) /* USCI Automatic Stop condition generation: 1 */ +#define UCASTP_2 (0x0008) /* USCI Automatic Stop condition generation: 2 */ +#define UCASTP_3 (0x000C) /* USCI Automatic Stop condition generation: 3 */ + +#define UCCLTO_0 (0x0000) /* USCI Clock low timeout: 0 */ +#define UCCLTO_1 (0x0040) /* USCI Clock low timeout: 1 */ +#define UCCLTO_2 (0x0080) /* USCI Clock low timeout: 2 */ +#define UCCLTO_3 (0x00C0) /* USCI Clock low timeout: 3 */ + +/* UCAxMCTLW Control Bits */ +#define UCBRS7 (0x8000) /* USCI Second Stage Modulation Select 7 */ +#define UCBRS6 (0x4000) /* USCI Second Stage Modulation Select 6 */ +#define UCBRS5 (0x2000) /* USCI Second Stage Modulation Select 5 */ +#define UCBRS4 (0x1000) /* USCI Second Stage Modulation Select 4 */ +#define UCBRS3 (0x0800) /* USCI Second Stage Modulation Select 3 */ +#define UCBRS2 (0x0400) /* USCI Second Stage Modulation Select 2 */ +#define UCBRS1 (0x0200) /* USCI Second Stage Modulation Select 1 */ +#define UCBRS0 (0x0100) /* USCI Second Stage Modulation Select 0 */ +#define UCBRF3 (0x0080) /* USCI First Stage Modulation Select 3 */ +#define UCBRF2 (0x0040) /* USCI First Stage Modulation Select 2 */ +#define UCBRF1 (0x0020) /* USCI First Stage Modulation Select 1 */ +#define UCBRF0 (0x0010) /* USCI First Stage Modulation Select 0 */ +#define UCOS16 (0x0001) /* USCI 16-times Oversampling enable */ + +/* UCAxMCTLW Control Bits */ +#define UCBRF3_L (0x0080) /* USCI First Stage Modulation Select 3 */ +#define UCBRF2_L (0x0040) /* USCI First Stage Modulation Select 2 */ +#define UCBRF1_L (0x0020) /* USCI First Stage Modulation Select 1 */ +#define UCBRF0_L (0x0010) /* USCI First Stage Modulation Select 0 */ +#define UCOS16_L (0x0001) /* USCI 16-times Oversampling enable */ + +/* UCAxMCTLW Control Bits */ +#define UCBRS7_H (0x0080) /* USCI Second Stage Modulation Select 7 */ +#define UCBRS6_H (0x0040) /* USCI Second Stage Modulation Select 6 */ +#define UCBRS5_H (0x0020) /* USCI Second Stage Modulation Select 5 */ +#define UCBRS4_H (0x0010) /* USCI Second Stage Modulation Select 4 */ +#define UCBRS3_H (0x0008) /* USCI Second Stage Modulation Select 3 */ +#define UCBRS2_H (0x0004) /* USCI Second Stage Modulation Select 2 */ +#define UCBRS1_H (0x0002) /* USCI Second Stage Modulation Select 1 */ +#define UCBRS0_H (0x0001) /* USCI Second Stage Modulation Select 0 */ + +#define UCBRF_0 (0x00) /* USCI First Stage Modulation: 0 */ +#define UCBRF_1 (0x10) /* USCI First Stage Modulation: 1 */ +#define UCBRF_2 (0x20) /* USCI First Stage Modulation: 2 */ +#define UCBRF_3 (0x30) /* USCI First Stage Modulation: 3 */ +#define UCBRF_4 (0x40) /* USCI First Stage Modulation: 4 */ +#define UCBRF_5 (0x50) /* USCI First Stage Modulation: 5 */ +#define UCBRF_6 (0x60) /* USCI First Stage Modulation: 6 */ +#define UCBRF_7 (0x70) /* USCI First Stage Modulation: 7 */ +#define UCBRF_8 (0x80) /* USCI First Stage Modulation: 8 */ +#define UCBRF_9 (0x90) /* USCI First Stage Modulation: 9 */ +#define UCBRF_10 (0xA0) /* USCI First Stage Modulation: A */ +#define UCBRF_11 (0xB0) /* USCI First Stage Modulation: B */ +#define UCBRF_12 (0xC0) /* USCI First Stage Modulation: C */ +#define UCBRF_13 (0xD0) /* USCI First Stage Modulation: D */ +#define UCBRF_14 (0xE0) /* USCI First Stage Modulation: E */ +#define UCBRF_15 (0xF0) /* USCI First Stage Modulation: F */ + +/* UCAxSTATW Control Bits */ +#define UCLISTEN (0x0080) /* USCI Listen mode */ +#define UCFE (0x0040) /* USCI Frame Error Flag */ +#define UCOE (0x0020) /* USCI Overrun Error Flag */ +#define UCPE (0x0010) /* USCI Parity Error Flag */ +#define UCBRK (0x0008) /* USCI Break received */ +#define UCRXERR (0x0004) /* USCI RX Error Flag */ +#define UCADDR (0x0002) /* USCI Address received Flag */ +#define UCBUSY (0x0001) /* USCI Busy Flag */ +#define UCIDLE (0x0002) /* USCI Idle line detected Flag */ + +/* UCBxSTATW I2C Control Bits */ +#define UCBCNT7 (0x8000) /* USCI Byte Counter Bit 7 */ +#define UCBCNT6 (0x4000) /* USCI Byte Counter Bit 6 */ +#define UCBCNT5 (0x2000) /* USCI Byte Counter Bit 5 */ +#define UCBCNT4 (0x1000) /* USCI Byte Counter Bit 4 */ +#define UCBCNT3 (0x0800) /* USCI Byte Counter Bit 3 */ +#define UCBCNT2 (0x0400) /* USCI Byte Counter Bit 2 */ +#define UCBCNT1 (0x0200) /* USCI Byte Counter Bit 1 */ +#define UCBCNT0 (0x0100) /* USCI Byte Counter Bit 0 */ +#define UCSCLLOW (0x0040) /* SCL low */ +#define UCGC (0x0020) /* General Call address received Flag */ +#define UCBBUSY (0x0010) /* Bus Busy Flag */ + +/* UCBxTBCNT I2C Control Bits */ +#define UCTBCNT7 (0x0080) /* USCI Byte Counter Bit 7 */ +#define UCTBCNT6 (0x0040) /* USCI Byte Counter Bit 6 */ +#define UCTBCNT5 (0x0020) /* USCI Byte Counter Bit 5 */ +#define UCTBCNT4 (0x0010) /* USCI Byte Counter Bit 4 */ +#define UCTBCNT3 (0x0008) /* USCI Byte Counter Bit 3 */ +#define UCTBCNT2 (0x0004) /* USCI Byte Counter Bit 2 */ +#define UCTBCNT1 (0x0002) /* USCI Byte Counter Bit 1 */ +#define UCTBCNT0 (0x0001) /* USCI Byte Counter Bit 0 */ + +/* UCAxIRCTL Control Bits */ +#define UCIRRXFL5 (0x8000) /* IRDA Receive Filter Length 5 */ +#define UCIRRXFL4 (0x4000) /* IRDA Receive Filter Length 4 */ +#define UCIRRXFL3 (0x2000) /* IRDA Receive Filter Length 3 */ +#define UCIRRXFL2 (0x1000) /* IRDA Receive Filter Length 2 */ +#define UCIRRXFL1 (0x0800) /* IRDA Receive Filter Length 1 */ +#define UCIRRXFL0 (0x0400) /* IRDA Receive Filter Length 0 */ +#define UCIRRXPL (0x0200) /* IRDA Receive Input Polarity */ +#define UCIRRXFE (0x0100) /* IRDA Receive Filter enable */ +#define UCIRTXPL5 (0x0080) /* IRDA Transmit Pulse Length 5 */ +#define UCIRTXPL4 (0x0040) /* IRDA Transmit Pulse Length 4 */ +#define UCIRTXPL3 (0x0020) /* IRDA Transmit Pulse Length 3 */ +#define UCIRTXPL2 (0x0010) /* IRDA Transmit Pulse Length 2 */ +#define UCIRTXPL1 (0x0008) /* IRDA Transmit Pulse Length 1 */ +#define UCIRTXPL0 (0x0004) /* IRDA Transmit Pulse Length 0 */ +#define UCIRTXCLK (0x0002) /* IRDA Transmit Pulse Clock Select */ +#define UCIREN (0x0001) /* IRDA Encoder/Decoder enable */ + +/* UCAxIRCTL Control Bits */ +#define UCIRTXPL5_L (0x0080) /* IRDA Transmit Pulse Length 5 */ +#define UCIRTXPL4_L (0x0040) /* IRDA Transmit Pulse Length 4 */ +#define UCIRTXPL3_L (0x0020) /* IRDA Transmit Pulse Length 3 */ +#define UCIRTXPL2_L (0x0010) /* IRDA Transmit Pulse Length 2 */ +#define UCIRTXPL1_L (0x0008) /* IRDA Transmit Pulse Length 1 */ +#define UCIRTXPL0_L (0x0004) /* IRDA Transmit Pulse Length 0 */ +#define UCIRTXCLK_L (0x0002) /* IRDA Transmit Pulse Clock Select */ +#define UCIREN_L (0x0001) /* IRDA Encoder/Decoder enable */ + +/* UCAxIRCTL Control Bits */ +#define UCIRRXFL5_H (0x0080) /* IRDA Receive Filter Length 5 */ +#define UCIRRXFL4_H (0x0040) /* IRDA Receive Filter Length 4 */ +#define UCIRRXFL3_H (0x0020) /* IRDA Receive Filter Length 3 */ +#define UCIRRXFL2_H (0x0010) /* IRDA Receive Filter Length 2 */ +#define UCIRRXFL1_H (0x0008) /* IRDA Receive Filter Length 1 */ +#define UCIRRXFL0_H (0x0004) /* IRDA Receive Filter Length 0 */ +#define UCIRRXPL_H (0x0002) /* IRDA Receive Input Polarity */ +#define UCIRRXFE_H (0x0001) /* IRDA Receive Filter enable */ + +/* UCAxABCTL Control Bits */ +//#define res (0x80) /* reserved */ +//#define res (0x40) /* reserved */ +#define UCDELIM1 (0x20) /* Break Sync Delimiter 1 */ +#define UCDELIM0 (0x10) /* Break Sync Delimiter 0 */ +#define UCSTOE (0x08) /* Sync-Field Timeout error */ +#define UCBTOE (0x04) /* Break Timeout error */ +//#define res (0x02) /* reserved */ +#define UCABDEN (0x01) /* Auto Baud Rate detect enable */ + +/* UCBxI2COA0 Control Bits */ +#define UCGCEN (0x8000) /* I2C General Call enable */ +#define UCOAEN (0x0400) /* I2C Own Address enable */ +#define UCOA9 (0x0200) /* I2C Own Address Bit 9 */ +#define UCOA8 (0x0100) /* I2C Own Address Bit 8 */ +#define UCOA7 (0x0080) /* I2C Own Address Bit 7 */ +#define UCOA6 (0x0040) /* I2C Own Address Bit 6 */ +#define UCOA5 (0x0020) /* I2C Own Address Bit 5 */ +#define UCOA4 (0x0010) /* I2C Own Address Bit 4 */ +#define UCOA3 (0x0008) /* I2C Own Address Bit 3 */ +#define UCOA2 (0x0004) /* I2C Own Address Bit 2 */ +#define UCOA1 (0x0002) /* I2C Own Address Bit 1 */ +#define UCOA0 (0x0001) /* I2C Own Address Bit 0 */ + +/* UCBxI2COA0 Control Bits */ +#define UCOA7_L (0x0080) /* I2C Own Address Bit 7 */ +#define UCOA6_L (0x0040) /* I2C Own Address Bit 6 */ +#define UCOA5_L (0x0020) /* I2C Own Address Bit 5 */ +#define UCOA4_L (0x0010) /* I2C Own Address Bit 4 */ +#define UCOA3_L (0x0008) /* I2C Own Address Bit 3 */ +#define UCOA2_L (0x0004) /* I2C Own Address Bit 2 */ +#define UCOA1_L (0x0002) /* I2C Own Address Bit 1 */ +#define UCOA0_L (0x0001) /* I2C Own Address Bit 0 */ + +/* UCBxI2COA0 Control Bits */ +#define UCGCEN_H (0x0080) /* I2C General Call enable */ +#define UCOAEN_H (0x0004) /* I2C Own Address enable */ +#define UCOA9_H (0x0002) /* I2C Own Address Bit 9 */ +#define UCOA8_H (0x0001) /* I2C Own Address Bit 8 */ + +/* UCBxI2COAx Control Bits */ +#define UCOAEN (0x0400) /* I2C Own Address enable */ +#define UCOA9 (0x0200) /* I2C Own Address Bit 9 */ +#define UCOA8 (0x0100) /* I2C Own Address Bit 8 */ +#define UCOA7 (0x0080) /* I2C Own Address Bit 7 */ +#define UCOA6 (0x0040) /* I2C Own Address Bit 6 */ +#define UCOA5 (0x0020) /* I2C Own Address Bit 5 */ +#define UCOA4 (0x0010) /* I2C Own Address Bit 4 */ +#define UCOA3 (0x0008) /* I2C Own Address Bit 3 */ +#define UCOA2 (0x0004) /* I2C Own Address Bit 2 */ +#define UCOA1 (0x0002) /* I2C Own Address Bit 1 */ +#define UCOA0 (0x0001) /* I2C Own Address Bit 0 */ + +/* UCBxI2COAx Control Bits */ +#define UCOA7_L (0x0080) /* I2C Own Address Bit 7 */ +#define UCOA6_L (0x0040) /* I2C Own Address Bit 6 */ +#define UCOA5_L (0x0020) /* I2C Own Address Bit 5 */ +#define UCOA4_L (0x0010) /* I2C Own Address Bit 4 */ +#define UCOA3_L (0x0008) /* I2C Own Address Bit 3 */ +#define UCOA2_L (0x0004) /* I2C Own Address Bit 2 */ +#define UCOA1_L (0x0002) /* I2C Own Address Bit 1 */ +#define UCOA0_L (0x0001) /* I2C Own Address Bit 0 */ + +/* UCBxI2COAx Control Bits */ +#define UCOAEN_H (0x0004) /* I2C Own Address enable */ +#define UCOA9_H (0x0002) /* I2C Own Address Bit 9 */ +#define UCOA8_H (0x0001) /* I2C Own Address Bit 8 */ + +/* UCBxADDRX Control Bits */ +#define UCADDRX9 (0x0200) /* I2C Receive Address Bit 9 */ +#define UCADDRX8 (0x0100) /* I2C Receive Address Bit 8 */ +#define UCADDRX7 (0x0080) /* I2C Receive Address Bit 7 */ +#define UCADDRX6 (0x0040) /* I2C Receive Address Bit 6 */ +#define UCADDRX5 (0x0020) /* I2C Receive Address Bit 5 */ +#define UCADDRX4 (0x0010) /* I2C Receive Address Bit 4 */ +#define UCADDRX3 (0x0008) /* I2C Receive Address Bit 3 */ +#define UCADDRX2 (0x0004) /* I2C Receive Address Bit 2 */ +#define UCADDRX1 (0x0002) /* I2C Receive Address Bit 1 */ +#define UCADDRX0 (0x0001) /* I2C Receive Address Bit 0 */ + +/* UCBxADDRX Control Bits */ +#define UCADDRX7_L (0x0080) /* I2C Receive Address Bit 7 */ +#define UCADDRX6_L (0x0040) /* I2C Receive Address Bit 6 */ +#define UCADDRX5_L (0x0020) /* I2C Receive Address Bit 5 */ +#define UCADDRX4_L (0x0010) /* I2C Receive Address Bit 4 */ +#define UCADDRX3_L (0x0008) /* I2C Receive Address Bit 3 */ +#define UCADDRX2_L (0x0004) /* I2C Receive Address Bit 2 */ +#define UCADDRX1_L (0x0002) /* I2C Receive Address Bit 1 */ +#define UCADDRX0_L (0x0001) /* I2C Receive Address Bit 0 */ + +/* UCBxADDRX Control Bits */ +#define UCADDRX9_H (0x0002) /* I2C Receive Address Bit 9 */ +#define UCADDRX8_H (0x0001) /* I2C Receive Address Bit 8 */ + +/* UCBxADDMASK Control Bits */ +#define UCADDMASK9 (0x0200) /* I2C Address Mask Bit 9 */ +#define UCADDMASK8 (0x0100) /* I2C Address Mask Bit 8 */ +#define UCADDMASK7 (0x0080) /* I2C Address Mask Bit 7 */ +#define UCADDMASK6 (0x0040) /* I2C Address Mask Bit 6 */ +#define UCADDMASK5 (0x0020) /* I2C Address Mask Bit 5 */ +#define UCADDMASK4 (0x0010) /* I2C Address Mask Bit 4 */ +#define UCADDMASK3 (0x0008) /* I2C Address Mask Bit 3 */ +#define UCADDMASK2 (0x0004) /* I2C Address Mask Bit 2 */ +#define UCADDMASK1 (0x0002) /* I2C Address Mask Bit 1 */ +#define UCADDMASK0 (0x0001) /* I2C Address Mask Bit 0 */ + +/* UCBxADDMASK Control Bits */ +#define UCADDMASK7_L (0x0080) /* I2C Address Mask Bit 7 */ +#define UCADDMASK6_L (0x0040) /* I2C Address Mask Bit 6 */ +#define UCADDMASK5_L (0x0020) /* I2C Address Mask Bit 5 */ +#define UCADDMASK4_L (0x0010) /* I2C Address Mask Bit 4 */ +#define UCADDMASK3_L (0x0008) /* I2C Address Mask Bit 3 */ +#define UCADDMASK2_L (0x0004) /* I2C Address Mask Bit 2 */ +#define UCADDMASK1_L (0x0002) /* I2C Address Mask Bit 1 */ +#define UCADDMASK0_L (0x0001) /* I2C Address Mask Bit 0 */ + +/* UCBxADDMASK Control Bits */ +#define UCADDMASK9_H (0x0002) /* I2C Address Mask Bit 9 */ +#define UCADDMASK8_H (0x0001) /* I2C Address Mask Bit 8 */ + +/* UCBxI2CSA Control Bits */ +#define UCSA9 (0x0200) /* I2C Slave Address Bit 9 */ +#define UCSA8 (0x0100) /* I2C Slave Address Bit 8 */ +#define UCSA7 (0x0080) /* I2C Slave Address Bit 7 */ +#define UCSA6 (0x0040) /* I2C Slave Address Bit 6 */ +#define UCSA5 (0x0020) /* I2C Slave Address Bit 5 */ +#define UCSA4 (0x0010) /* I2C Slave Address Bit 4 */ +#define UCSA3 (0x0008) /* I2C Slave Address Bit 3 */ +#define UCSA2 (0x0004) /* I2C Slave Address Bit 2 */ +#define UCSA1 (0x0002) /* I2C Slave Address Bit 1 */ +#define UCSA0 (0x0001) /* I2C Slave Address Bit 0 */ + +/* UCBxI2CSA Control Bits */ +#define UCSA7_L (0x0080) /* I2C Slave Address Bit 7 */ +#define UCSA6_L (0x0040) /* I2C Slave Address Bit 6 */ +#define UCSA5_L (0x0020) /* I2C Slave Address Bit 5 */ +#define UCSA4_L (0x0010) /* I2C Slave Address Bit 4 */ +#define UCSA3_L (0x0008) /* I2C Slave Address Bit 3 */ +#define UCSA2_L (0x0004) /* I2C Slave Address Bit 2 */ +#define UCSA1_L (0x0002) /* I2C Slave Address Bit 1 */ +#define UCSA0_L (0x0001) /* I2C Slave Address Bit 0 */ + +/* UCBxI2CSA Control Bits */ +#define UCSA9_H (0x0002) /* I2C Slave Address Bit 9 */ +#define UCSA8_H (0x0001) /* I2C Slave Address Bit 8 */ + +/* UCAxIE UART Control Bits */ +#define UCTXCPTIE (0x0008) /* UART Transmit Complete Interrupt Enable */ +#define UCSTTIE (0x0004) /* UART Start Bit Interrupt Enalble */ +#define UCTXIE (0x0002) /* UART Transmit Interrupt Enable */ +#define UCRXIE (0x0001) /* UART Receive Interrupt Enable */ + +/* UCAxIE/UCBxIE SPI Control Bits */ + +/* UCBxIE I2C Control Bits */ +#define UCBIT9IE (0x4000) /* I2C Bit 9 Position Interrupt Enable 3 */ +#define UCTXIE3 (0x2000) /* I2C Transmit Interrupt Enable 3 */ +#define UCRXIE3 (0x1000) /* I2C Receive Interrupt Enable 3 */ +#define UCTXIE2 (0x0800) /* I2C Transmit Interrupt Enable 2 */ +#define UCRXIE2 (0x0400) /* I2C Receive Interrupt Enable 2 */ +#define UCTXIE1 (0x0200) /* I2C Transmit Interrupt Enable 1 */ +#define UCRXIE1 (0x0100) /* I2C Receive Interrupt Enable 1 */ +#define UCCLTOIE (0x0080) /* I2C Clock Low Timeout interrupt enable */ +#define UCBCNTIE (0x0040) /* I2C Automatic stop assertion interrupt enable */ +#define UCNACKIE (0x0020) /* I2C NACK Condition interrupt enable */ +#define UCALIE (0x0010) /* I2C Arbitration Lost interrupt enable */ +#define UCSTPIE (0x0008) /* I2C STOP Condition interrupt enable */ +#define UCSTTIE (0x0004) /* I2C START Condition interrupt enable */ +#define UCTXIE0 (0x0002) /* I2C Transmit Interrupt Enable 0 */ +#define UCRXIE0 (0x0001) /* I2C Receive Interrupt Enable 0 */ + +/* UCAxIFG UART Control Bits */ +#define UCTXCPTIFG (0x0008) /* UART Transmit Complete Interrupt Flag */ +#define UCSTTIFG (0x0004) /* UART Start Bit Interrupt Flag */ +#define UCTXIFG (0x0002) /* UART Transmit Interrupt Flag */ +#define UCRXIFG (0x0001) /* UART Receive Interrupt Flag */ + +/* UCAxIFG/UCBxIFG SPI Control Bits */ +#define UCTXIFG (0x0002) /* SPI Transmit Interrupt Flag */ +#define UCRXIFG (0x0001) /* SPI Receive Interrupt Flag */ + +/* UCBxIFG Control Bits */ +#define UCBIT9IFG (0x4000) /* I2C Bit 9 Possition Interrupt Flag 3 */ +#define UCTXIFG3 (0x2000) /* I2C Transmit Interrupt Flag 3 */ +#define UCRXIFG3 (0x1000) /* I2C Receive Interrupt Flag 3 */ +#define UCTXIFG2 (0x0800) /* I2C Transmit Interrupt Flag 2 */ +#define UCRXIFG2 (0x0400) /* I2C Receive Interrupt Flag 2 */ +#define UCTXIFG1 (0x0200) /* I2C Transmit Interrupt Flag 1 */ +#define UCRXIFG1 (0x0100) /* I2C Receive Interrupt Flag 1 */ +#define UCCLTOIFG (0x0080) /* I2C Clock low Timeout interrupt Flag */ +#define UCBCNTIFG (0x0040) /* I2C Byte counter interrupt flag */ +#define UCNACKIFG (0x0020) /* I2C NACK Condition interrupt Flag */ +#define UCALIFG (0x0010) /* I2C Arbitration Lost interrupt Flag */ +#define UCSTPIFG (0x0008) /* I2C STOP Condition interrupt Flag */ +#define UCSTTIFG (0x0004) /* I2C START Condition interrupt Flag */ +#define UCTXIFG0 (0x0002) /* I2C Transmit Interrupt Flag 0 */ +#define UCRXIFG0 (0x0001) /* I2C Receive Interrupt Flag 0 */ + +/* USCI UART Definitions */ +#define USCI_NONE (0x0000) /* No Interrupt pending */ +#define USCI_UART_UCRXIFG (0x0002) /* USCI UCRXIFG */ +#define USCI_UART_UCTXIFG (0x0004) /* USCI UCTXIFG */ +#define USCI_UART_UCSTTIFG (0x0006) /* USCI UCSTTIFG */ +#define USCI_UART_UCTXCPTIFG (0x0008) /* USCI UCTXCPTIFG */ + +/* USCI SPI Definitions */ +#define USCI_SPI_UCRXIFG (0x0002) /* USCI UCRXIFG */ +#define USCI_SPI_UCTXIFG (0x0004) /* USCI UCTXIFG */ + +/* USCI I2C Definitions */ +#define USCI_I2C_UCALIFG (0x0002) /* USCI I2C Mode: UCALIFG */ +#define USCI_I2C_UCNACKIFG (0x0004) /* USCI I2C Mode: UCNACKIFG */ +#define USCI_I2C_UCSTTIFG (0x0006) /* USCI I2C Mode: UCSTTIFG*/ +#define USCI_I2C_UCSTPIFG (0x0008) /* USCI I2C Mode: UCSTPIFG*/ +#define USCI_I2C_UCRXIFG3 (0x000A) /* USCI I2C Mode: UCRXIFG3 */ +#define USCI_I2C_UCTXIFG3 (0x000C) /* USCI I2C Mode: UCTXIFG3 */ +#define USCI_I2C_UCRXIFG2 (0x000E) /* USCI I2C Mode: UCRXIFG2 */ +#define USCI_I2C_UCTXIFG2 (0x0010) /* USCI I2C Mode: UCTXIFG2 */ +#define USCI_I2C_UCRXIFG1 (0x0012) /* USCI I2C Mode: UCRXIFG1 */ +#define USCI_I2C_UCTXIFG1 (0x0014) /* USCI I2C Mode: UCTXIFG1 */ +#define USCI_I2C_UCRXIFG0 (0x0016) /* USCI I2C Mode: UCRXIFG0 */ +#define USCI_I2C_UCTXIFG0 (0x0018) /* USCI I2C Mode: UCTXIFG0 */ +#define USCI_I2C_UCBCNTIFG (0x001A) /* USCI I2C Mode: UCBCNTIFG */ +#define USCI_I2C_UCCLTOIFG (0x001C) /* USCI I2C Mode: UCCLTOIFG */ +#define USCI_I2C_UCBIT9IFG (0x001E) /* USCI I2C Mode: UCBIT9IFG */ + +#endif +/************************************************************ +* WATCHDOG TIMER A +************************************************************/ +#ifdef __MSP430_HAS_WDT_A__ /* Definition to show that Module is available */ + +#define OFS_WDTCTL (0x000C) /* Watchdog Timer Control */ +#define OFS_WDTCTL_L OFS_WDTCTL +#define OFS_WDTCTL_H OFS_WDTCTL+1 +/* The bit names have been prefixed with "WDT" */ +/* WDTCTL Control Bits */ +#define WDTIS0 (0x0001) /* WDT - Timer Interval Select 0 */ +#define WDTIS1 (0x0002) /* WDT - Timer Interval Select 1 */ +#define WDTIS2 (0x0004) /* WDT - Timer Interval Select 2 */ +#define WDTCNTCL (0x0008) /* WDT - Timer Clear */ +#define WDTTMSEL (0x0010) /* WDT - Timer Mode Select */ +#define WDTSSEL0 (0x0020) /* WDT - Timer Clock Source Select 0 */ +#define WDTSSEL1 (0x0040) /* WDT - Timer Clock Source Select 1 */ +#define WDTHOLD (0x0080) /* WDT - Timer hold */ + +/* WDTCTL Control Bits */ +#define WDTIS0_L (0x0001) /* WDT - Timer Interval Select 0 */ +#define WDTIS1_L (0x0002) /* WDT - Timer Interval Select 1 */ +#define WDTIS2_L (0x0004) /* WDT - Timer Interval Select 2 */ +#define WDTCNTCL_L (0x0008) /* WDT - Timer Clear */ +#define WDTTMSEL_L (0x0010) /* WDT - Timer Mode Select */ +#define WDTSSEL0_L (0x0020) /* WDT - Timer Clock Source Select 0 */ +#define WDTSSEL1_L (0x0040) /* WDT - Timer Clock Source Select 1 */ +#define WDTHOLD_L (0x0080) /* WDT - Timer hold */ + +#define WDTPW (0x5A00) + +#define WDTIS_0 (0*0x0001u) /* WDT - Timer Interval Select: /2G */ +#define WDTIS_1 (1*0x0001u) /* WDT - Timer Interval Select: /128M */ +#define WDTIS_2 (2*0x0001u) /* WDT - Timer Interval Select: /8192k */ +#define WDTIS_3 (3*0x0001u) /* WDT - Timer Interval Select: /512k */ +#define WDTIS_4 (4*0x0001u) /* WDT - Timer Interval Select: /32k */ +#define WDTIS_5 (5*0x0001u) /* WDT - Timer Interval Select: /8192 */ +#define WDTIS_6 (6*0x0001u) /* WDT - Timer Interval Select: /512 */ +#define WDTIS_7 (7*0x0001u) /* WDT - Timer Interval Select: /64 */ +#define WDTIS__2G (0*0x0001u) /* WDT - Timer Interval Select: /2G */ +#define WDTIS__128M (1*0x0001u) /* WDT - Timer Interval Select: /128M */ +#define WDTIS__8192K (2*0x0001u) /* WDT - Timer Interval Select: /8192k */ +#define WDTIS__512K (3*0x0001u) /* WDT - Timer Interval Select: /512k */ +#define WDTIS__32K (4*0x0001u) /* WDT - Timer Interval Select: /32k */ +#define WDTIS__8192 (5*0x0001u) /* WDT - Timer Interval Select: /8192 */ +#define WDTIS__512 (6*0x0001u) /* WDT - Timer Interval Select: /512 */ +#define WDTIS__64 (7*0x0001u) /* WDT - Timer Interval Select: /64 */ + +#define WDTSSEL_0 (0*0x0020u) /* WDT - Timer Clock Source Select: SMCLK */ +#define WDTSSEL_1 (1*0x0020u) /* WDT - Timer Clock Source Select: ACLK */ +#define WDTSSEL_2 (2*0x0020u) /* WDT - Timer Clock Source Select: VLO_CLK */ +#define WDTSSEL_3 (3*0x0020u) /* WDT - Timer Clock Source Select: reserved */ +#define WDTSSEL__SMCLK (0*0x0020u) /* WDT - Timer Clock Source Select: SMCLK */ +#define WDTSSEL__ACLK (1*0x0020u) /* WDT - Timer Clock Source Select: ACLK */ +#define WDTSSEL__VLO (2*0x0020u) /* WDT - Timer Clock Source Select: VLO_CLK */ + +/* WDT-interval times [1ms] coded with Bits 0-2 */ +/* WDT is clocked by fSMCLK (assumed 1MHz) */ +#define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2) /* 32ms interval (default) */ +#define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */ +#define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */ +#define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */ +/* WDT is clocked by fACLK (assumed 32KHz) */ +#define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0) /* 1000ms " */ +#define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS0) /* 250ms " */ +#define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1) /* 16ms " */ +#define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1+WDTIS0) /* 1.9ms " */ +/* Watchdog mode -> reset after expired time */ +/* WDT is clocked by fSMCLK (assumed 1MHz) */ +#define WDT_MRST_32 (WDTPW+WDTCNTCL+WDTIS2) /* 32ms interval (default) */ +#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */ +#define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */ +#define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */ +/* WDT is clocked by fACLK (assumed 32KHz) */ +#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2) /* 1000ms " */ +#define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS0) /* 250ms " */ +#define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1) /* 16ms " */ +#define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1+WDTIS0) /* 1.9ms " */ + +#endif + +/************************************************************ +* TLV Descriptors +************************************************************/ +#define __MSP430_HAS_TLV__ /* Definition to show that Module is available */ +#define TLV_BASE __MSP430_BASEADDRESS_TLV__ + +#define TLV_START (0x1A08) /* Start Address of the TLV structure */ +#define TLV_END (0x1AFF) /* End Address of the TLV structure */ + +#define TLV_LDTAG (0x01) /* Legacy descriptor (1xx, 2xx, 4xx families) */ +#define TLV_PDTAG (0x02) /* Peripheral discovery descriptor */ +#define TLV_Reserved3 (0x03) /* Future usage */ +#define TLV_Reserved4 (0x04) /* Future usage */ +#define TLV_BLANK (0x05) /* Blank descriptor */ +#define TLV_Reserved6 (0x06) /* Future usage */ +#define TLV_Reserved7 (0x07) /* Serial Number */ +#define TLV_DIERECORD (0x08) /* Die Record */ +#define TLV_ADCCAL (0x11) /* ADC12 calibration */ +#define TLV_ADC12CAL (0x11) /* ADC12 calibration */ +#define TLV_REFCAL (0x12) /* REF calibration */ +#define TLV_ADC10CAL (0x13) /* ADC10 calibration */ +#define TLV_TIMERDCAL (0x15) /* TIMER_D calibration */ +#define TLV_TAGEXT (0xFE) /* Tag extender */ +#define TLV_TAGEND (0xFF) /* Tag End of Table */ + +/************************************************************ +* Interrupt Vectors (offset from 0xFF80) +************************************************************/ + +#pragma diag_suppress 1107 +#define VECTOR_NAME(name) name##_ptr +#define EMIT_PRAGMA(x) _Pragma(#x) +#define CREATE_VECTOR(name) void * const VECTOR_NAME(name) = (void *)(long)&name +#define PLACE_VECTOR(vector,section) EMIT_PRAGMA(DATA_SECTION(vector,section)) +#define PLACE_INTERRUPT(func) EMIT_PRAGMA(CODE_SECTION(func,".text:_isr")) +#define ISR_VECTOR(func,offset) CREATE_VECTOR(func); \ + PLACE_VECTOR(VECTOR_NAME(func), offset) \ + PLACE_INTERRUPT(func) + + +/************************************************************ +* End of Modules +************************************************************/ + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif /* #ifndef __msp430F5XX_F6XXGENERIC */ + diff --git a/source/driverlib/MSP430F5xx_6xx/deprecated/IAR/msp430f5xx_6xxgeneric.h b/source/driverlib/MSP430F5xx_6xx/deprecated/IAR/msp430f5xx_6xxgeneric.h new file mode 100644 index 0000000..5dbbb35 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/deprecated/IAR/msp430f5xx_6xxgeneric.h @@ -0,0 +1,10007 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +/******************************************************************** +* +* Standard register and bit definitions for the Texas Instruments +* MSP430 microcontroller. +* +* This file supports assembler and C development for +* MSP430F5XX_F6XXGENERIC device. +* +* Texas Instruments, Version 1.0 +* +* Rev. 1.0, Setup +* +* +********************************************************************/ + +#ifndef __msp430F5XX_F6XXGENERIC +#define __msp430F5XX_F6XXGENERIC + +//#define __MSP430_HEADER_VERSION__ 1125 + +#ifdef __IAR_SYSTEMS_ICC__ +#ifndef _SYSTEM_BUILD +#pragma system_include +#endif +#endif + +#if (((__TID__ >> 8) & 0x7F) != 0x2b) /* 0x2b = 43 dec */ +#error msp430f5xx_6xxgeneric.h file for use with ICC430/A430 only +#endif + + +#ifdef __IAR_SYSTEMS_ICC__ +#include "in430.h" +#pragma language=extended + +#define DEFC(name, address) __no_init volatile unsigned char name @ address; +#define DEFW(name, address) __no_init volatile unsigned short name @ address; + +#define DEFCW(name, address) __no_init union \ +{ \ + struct \ + { \ + volatile unsigned char name##_L; \ + volatile unsigned char name##_H; \ + }; \ + volatile unsigned short name; \ +} @ address; + +#define READ_ONLY_DEFCW(name, address) __no_init union \ +{ \ + struct \ + { \ + volatile READ_ONLY unsigned char name##_L; \ + volatile READ_ONLY unsigned char name##_H; \ + }; \ + volatile READ_ONLY unsigned short name; \ +} @ address; + + +#if __REGISTER_MODEL__ == __REGISTER_MODEL_REG20__ +#define __ACCESS_20BIT_REG__ void __data20 * volatile +#else +#define __ACCESS_20BIT_REG__ volatile unsigned short /* only short access from C is allowed in small memory model */ +#endif + +#define DEFA(name, address) __no_init union \ +{ \ + struct \ + { \ + volatile unsigned char name##_L; \ + volatile unsigned char name##_H; \ + }; \ + struct \ + { \ + volatile unsigned short name##L; \ + volatile unsigned short name##H; \ + }; \ + __ACCESS_20BIT_REG__ name; \ +} @ address; + +#endif /* __IAR_SYSTEMS_ICC__ */ + + +#ifdef __IAR_SYSTEMS_ASM__ +#define DEFC(name, address) sfrb name = address; +#define DEFW(name, address) sfrw name = address; + +#define DEFCW(name, address) sfrbw name, name##_L, name##_H, address; +sfrbw macro name, name_L, name_H, address; +sfrb name_L = address; +sfrb name_H = address+1; +sfrw name = address; + endm + +#define READ_ONLY_DEFCW(name, address) const_sfrbw name, name##_L, name##_H, address; +const_sfrbw macro name, name_L, name_H, address; +const sfrb name_L = address; +const sfrb name_H = address+1; +const sfrw name = address; + endm + +#define DEFA(name, address) sfrba name, name##L, name##H, name##_L, name##_H, address; +sfrba macro name, nameL, nameH, name_L, name_H, address; +sfrb name_L = address; +sfrb name_H = address+1; +sfrw nameL = address; +sfrw nameH = address+2; +sfrl name = address; + endm + +#endif /* __IAR_SYSTEMS_ASM__*/ + +#ifdef __cplusplus +#define READ_ONLY +#else +#define READ_ONLY const +#endif + +/************************************************************ +* STANDARD BITS +************************************************************/ + +#define BIT0 (0x0001u) +#define BIT1 (0x0002u) +#define BIT2 (0x0004u) +#define BIT3 (0x0008u) +#define BIT4 (0x0010u) +#define BIT5 (0x0020u) +#define BIT6 (0x0040u) +#define BIT7 (0x0080u) +#define BIT8 (0x0100u) +#define BIT9 (0x0200u) +#define BITA (0x0400u) +#define BITB (0x0800u) +#define BITC (0x1000u) +#define BITD (0x2000u) +#define BITE (0x4000u) +#define BITF (0x8000u) + +/************************************************************ +* STATUS REGISTER BITS +************************************************************/ + +#define C (0x0001u) +#define Z (0x0002u) +#define N (0x0004u) +#define V (0x0100u) +#define GIE (0x0008u) +#define CPUOFF (0x0010u) +#define OSCOFF (0x0020u) +#define SCG0 (0x0040u) +#define SCG1 (0x0080u) + +/* Low Power Modes coded with Bits 4-7 in SR */ + +#ifndef __IAR_SYSTEMS_ICC__ /* Begin #defines for assembler */ +#define LPM0 (CPUOFF) +#define LPM1 (SCG0+CPUOFF) +#define LPM2 (SCG1+CPUOFF) +#define LPM3 (SCG1+SCG0+CPUOFF) +#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF) +/* End #defines for assembler */ + +#else /* Begin #defines for C */ +#define LPM0_bits (CPUOFF) +#define LPM1_bits (SCG0+CPUOFF) +#define LPM2_bits (SCG1+CPUOFF) +#define LPM3_bits (SCG1+SCG0+CPUOFF) +#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF) + +#include "in430.h" + +#if __MSP430_HEADER_VERSION__ < 1107 +#define LPM0 _BIS_SR(LPM0_bits) /* Enter Low Power Mode 0 */ +#define LPM0_EXIT _BIC_SR_IRQ(LPM0_bits) /* Exit Low Power Mode 0 */ +#define LPM1 _BIS_SR(LPM1_bits) /* Enter Low Power Mode 1 */ +#define LPM1_EXIT _BIC_SR_IRQ(LPM1_bits) /* Exit Low Power Mode 1 */ +#define LPM2 _BIS_SR(LPM2_bits) /* Enter Low Power Mode 2 */ +#define LPM2_EXIT _BIC_SR_IRQ(LPM2_bits) /* Exit Low Power Mode 2 */ +#define LPM3 _BIS_SR(LPM3_bits) /* Enter Low Power Mode 3 */ +#define LPM3_EXIT _BIC_SR_IRQ(LPM3_bits) /* Exit Low Power Mode 3 */ +#define LPM4 _BIS_SR(LPM4_bits) /* Enter Low Power Mode 4 */ +#define LPM4_EXIT _BIC_SR_IRQ(LPM4_bits) /* Exit Low Power Mode 4 */ +#else +#define LPM0 __bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */ +#define LPM0_EXIT __bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */ +#define LPM1 __bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */ +#define LPM1_EXIT __bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */ +#define LPM2 __bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */ +#define LPM2_EXIT __bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */ +#define LPM3 __bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */ +#define LPM3_EXIT __bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */ +#define LPM4 __bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */ +#define LPM4_EXIT __bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */ +#endif +#endif /* End #defines for C */ + +/************************************************************ +* CPU +************************************************************/ +#define __MSP430_HAS_MSP430XV2_CPU__ /* Definition to show that it has MSP430XV2 CPU */ + +#if defined(__MSP430_HAS_T0A2__) || defined(__MSP430_HAS_T1A2__) || defined(__MSP430_HAS_T2A2__) || defined(__MSP430_HAS_T3A2__) \ + || defined(__MSP430_HAS_T0A3__) || defined(__MSP430_HAS_T1A3__) || defined(__MSP430_HAS_T2A3__) || defined(__MSP430_HAS_T3A3__) \ + || defined(__MSP430_HAS_T0A5__) || defined(__MSP430_HAS_T1A5__) || defined(__MSP430_HAS_T2A5__) || defined(__MSP430_HAS_T3A5__) \ + || defined(__MSP430_HAS_T0A7__) || defined(__MSP430_HAS_T1A7__) || defined(__MSP430_HAS_T2A7__) || defined(__MSP430_HAS_T3A7__) + #define __MSP430_HAS_TxA7__ +#endif +#if defined(__MSP430_HAS_T0B3__) || defined(__MSP430_HAS_T0B5__) || defined(__MSP430_HAS_T0B7__) \ + || defined(__MSP430_HAS_T1B3__) || defined(__MSP430_HAS_T1B5__) || defined(__MSP430_HAS_T1B7__) + #define __MSP430_HAS_TxB7__ +#endif +#if defined(__MSP430_HAS_T0D3__) || defined(__MSP430_HAS_T0D5__) || defined(__MSP430_HAS_T0D7__) \ + || defined(__MSP430_HAS_T1D3__) || defined(__MSP430_HAS_T1D5__) || defined(__MSP430_HAS_T1D7__) + #define __MSP430_HAS_TxD7__ +#endif +#if defined(__MSP430_HAS_USCI_A0__) || defined(__MSP430_HAS_USCI_A1__) || defined(__MSP430_HAS_USCI_A2__) || defined(__MSP430_HAS_USCI_A3__) + #define __MSP430_HAS_USCI_Ax__ +#endif +#if defined(__MSP430_HAS_USCI_B0__) || defined(__MSP430_HAS_USCI_B1__) || defined(__MSP430_HAS_USCI_B2__) || defined(__MSP430_HAS_USCI_B3__) + #define __MSP430_HAS_USCI_Bx__ +#endif +#if defined(__MSP430_HAS_EUSCI_A0__) || defined(__MSP430_HAS_EUSCI_A1__) || defined(__MSP430_HAS_EUSCI_A2__) || defined(__MSP430_HAS_EUSCI_A3__) + #define __MSP430_HAS_EUSCI_Ax__ +#endif +#if defined(__MSP430_HAS_EUSCI_B0__) || defined(__MSP430_HAS_EUSCI_B1__) || defined(__MSP430_HAS_EUSCI_B2__) || defined(__MSP430_HAS_EUSCI_B3__) + #define __MSP430_HAS_EUSCI_Bx__ +#endif +#ifdef __MSP430_HAS_EUSCI_B0__ + #define __MSP430_HAS_EUSCI_Bx__ +#endif + +/************************************************************ +* ADC10_A +************************************************************/ +#ifdef __MSP430_HAS_ADC10_A__ /* Definition to show that Module is available */ + +#define OFS_ADC10CTL0 (0x0000u) /* ADC10 Control 0 */ +#define OFS_ADC10CTL0_L OFS_ADC10CTL0 +#define OFS_ADC10CTL0_H OFS_ADC10CTL0+1 +#define OFS_ADC10CTL1 (0x0002u) /* ADC10 Control 1 */ +#define OFS_ADC10CTL1_L OFS_ADC10CTL1 +#define OFS_ADC10CTL1_H OFS_ADC10CTL1+1 +#define OFS_ADC10CTL2 (0x0004u) /* ADC10 Control 2 */ +#define OFS_ADC10CTL2_L OFS_ADC10CTL2 +#define OFS_ADC10CTL2_H OFS_ADC10CTL2+1 +#define OFS_ADC10LO (0x0006u) /* ADC10 Window Comparator High Threshold */ +#define OFS_ADC10LO_L OFS_ADC10LO +#define OFS_ADC10LO_H OFS_ADC10LO+1 +#define OFS_ADC10HI (0x0008u) /* ADC10 Window Comparator High Threshold */ +#define OFS_ADC10HI_L OFS_ADC10HI +#define OFS_ADC10HI_H OFS_ADC10HI+1 +#define OFS_ADC10MCTL0 (0x000Au) /* ADC10 Memory Control 0 */ +#define OFS_ADC10MCTL0_L OFS_ADC10MCTL0 +#define OFS_ADC10MCTL0_H OFS_ADC10MCTL0+1 +#define OFS_ADC10MEM0 (0x0012u) /* ADC10 Conversion Memory 0 */ +#define OFS_ADC10MEM0_L OFS_ADC10MEM0 +#define OFS_ADC10MEM0_H OFS_ADC10MEM0+1 +#define OFS_ADC10IE (0x001Au) /* ADC10 Interrupt Enable */ +#define OFS_ADC10IE_L OFS_ADC10IE +#define OFS_ADC10IE_H OFS_ADC10IE+1 +#define OFS_ADC10IFG (0x001Cu) /* ADC10 Interrupt Flag */ +#define OFS_ADC10IFG_L OFS_ADC10IFG +#define OFS_ADC10IFG_H OFS_ADC10IFG+1 +#define OFS_ADC10IV (0x001Eu) /* ADC10 Interrupt Vector Word */ +#define OFS_ADC10IV_L OFS_ADC10IV +#define OFS_ADC10IV_H OFS_ADC10IV+1 + +/* ADC10CTL0 Control Bits */ +#define ADC10SC (0x0001u) /* ADC10 Start Conversion */ +#define ADC10ENC (0x0002u) /* ADC10 Enable Conversion */ +#define ADC10ON (0x0010u) /* ADC10 On/enable */ +#define ADC10MSC (0x0080u) /* ADC10 Multiple SampleConversion */ +#define ADC10SHT0 (0x0100u) /* ADC10 Sample Hold Select Bit: 0 */ +#define ADC10SHT1 (0x0200u) /* ADC10 Sample Hold Select Bit: 1 */ +#define ADC10SHT2 (0x0400u) /* ADC10 Sample Hold Select Bit: 2 */ +#define ADC10SHT3 (0x0800u) /* ADC10 Sample Hold Select Bit: 3 */ + +/* ADC10CTL0 Control Bits */ +#define ADC10SC_L (0x0001u) /* ADC10 Start Conversion */ +#define ADC10ENC_L (0x0002u) /* ADC10 Enable Conversion */ +#define ADC10ON_L (0x0010u) /* ADC10 On/enable */ +#define ADC10MSC_L (0x0080u) /* ADC10 Multiple SampleConversion */ + +/* ADC10CTL0 Control Bits */ +#define ADC10SHT0_H (0x0001u) /* ADC10 Sample Hold Select Bit: 0 */ +#define ADC10SHT1_H (0x0002u) /* ADC10 Sample Hold Select Bit: 1 */ +#define ADC10SHT2_H (0x0004u) /* ADC10 Sample Hold Select Bit: 2 */ +#define ADC10SHT3_H (0x0008u) /* ADC10 Sample Hold Select Bit: 3 */ + +#define ADC10SHT_0 (0*0x100u) /* ADC10 Sample Hold Select 0 */ +#define ADC10SHT_1 (1*0x100u) /* ADC10 Sample Hold Select 1 */ +#define ADC10SHT_2 (2*0x100u) /* ADC10 Sample Hold Select 2 */ +#define ADC10SHT_3 (3*0x100u) /* ADC10 Sample Hold Select 3 */ +#define ADC10SHT_4 (4*0x100u) /* ADC10 Sample Hold Select 4 */ +#define ADC10SHT_5 (5*0x100u) /* ADC10 Sample Hold Select 5 */ +#define ADC10SHT_6 (6*0x100u) /* ADC10 Sample Hold Select 6 */ +#define ADC10SHT_7 (7*0x100u) /* ADC10 Sample Hold Select 7 */ +#define ADC10SHT_8 (8*0x100u) /* ADC10 Sample Hold Select 8 */ +#define ADC10SHT_9 (9*0x100u) /* ADC10 Sample Hold Select 9 */ +#define ADC10SHT_10 (10*0x100u) /* ADC10 Sample Hold Select 10 */ +#define ADC10SHT_11 (11*0x100u) /* ADC10 Sample Hold Select 11 */ +#define ADC10SHT_12 (12*0x100u) /* ADC10 Sample Hold Select 12 */ +#define ADC10SHT_13 (13*0x100u) /* ADC10 Sample Hold Select 13 */ +#define ADC10SHT_14 (14*0x100u) /* ADC10 Sample Hold Select 14 */ +#define ADC10SHT_15 (15*0x100u) /* ADC10 Sample Hold Select 15 */ + +/* ADC10CTL1 Control Bits */ +#define ADC10BUSY (0x0001u) /* ADC10 Busy */ +#define ADC10CONSEQ0 (0x0002u) /* ADC10 Conversion Sequence Select 0 */ +#define ADC10CONSEQ1 (0x0004u) /* ADC10 Conversion Sequence Select 1 */ +#define ADC10SSEL0 (0x0008u) /* ADC10 Clock Source Select 0 */ +#define ADC10SSEL1 (0x0010u) /* ADC10 Clock Source Select 1 */ +#define ADC10DIV0 (0x0020u) /* ADC10 Clock Divider Select 0 */ +#define ADC10DIV1 (0x0040u) /* ADC10 Clock Divider Select 1 */ +#define ADC10DIV2 (0x0080u) /* ADC10 Clock Divider Select 2 */ +#define ADC10ISSH (0x0100u) /* ADC10 Invert Sample Hold Signal */ +#define ADC10SHP (0x0200u) /* ADC10 Sample/Hold Pulse Mode */ +#define ADC10SHS0 (0x0400u) /* ADC10 Sample/Hold Source 0 */ +#define ADC10SHS1 (0x0800u) /* ADC10 Sample/Hold Source 1 */ + +/* ADC10CTL1 Control Bits */ +#define ADC10BUSY_L (0x0001u) /* ADC10 Busy */ +#define ADC10CONSEQ0_L (0x0002u) /* ADC10 Conversion Sequence Select 0 */ +#define ADC10CONSEQ1_L (0x0004u) /* ADC10 Conversion Sequence Select 1 */ +#define ADC10SSEL0_L (0x0008u) /* ADC10 Clock Source Select 0 */ +#define ADC10SSEL1_L (0x0010u) /* ADC10 Clock Source Select 1 */ +#define ADC10DIV0_L (0x0020u) /* ADC10 Clock Divider Select 0 */ +#define ADC10DIV1_L (0x0040u) /* ADC10 Clock Divider Select 1 */ +#define ADC10DIV2_L (0x0080u) /* ADC10 Clock Divider Select 2 */ + +/* ADC10CTL1 Control Bits */ +#define ADC10ISSH_H (0x0001u) /* ADC10 Invert Sample Hold Signal */ +#define ADC10SHP_H (0x0002u) /* ADC10 Sample/Hold Pulse Mode */ +#define ADC10SHS0_H (0x0004u) /* ADC10 Sample/Hold Source 0 */ +#define ADC10SHS1_H (0x0008u) /* ADC10 Sample/Hold Source 1 */ + +#define ADC10CONSEQ_0 (0*2u) /* ADC10 Conversion Sequence Select: 0 */ +#define ADC10CONSEQ_1 (1*2u) /* ADC10 Conversion Sequence Select: 1 */ +#define ADC10CONSEQ_2 (2*2u) /* ADC10 Conversion Sequence Select: 2 */ +#define ADC10CONSEQ_3 (3*2u) /* ADC10 Conversion Sequence Select: 3 */ + +#define ADC10SSEL_0 (0*8u) /* ADC10 Clock Source Select: 0 */ +#define ADC10SSEL_1 (1*8u) /* ADC10 Clock Source Select: 1 */ +#define ADC10SSEL_2 (2*8u) /* ADC10 Clock Source Select: 2 */ +#define ADC10SSEL_3 (3*8u) /* ADC10 Clock Source Select: 3 */ + +#define ADC10DIV_0 (0*0x20u) /* ADC10 Clock Divider Select: 0 */ +#define ADC10DIV_1 (1*0x20u) /* ADC10 Clock Divider Select: 1 */ +#define ADC10DIV_2 (2*0x20u) /* ADC10 Clock Divider Select: 2 */ +#define ADC10DIV_3 (3*0x20u) /* ADC10 Clock Divider Select: 3 */ +#define ADC10DIV_4 (4*0x20u) /* ADC10 Clock Divider Select: 4 */ +#define ADC10DIV_5 (5*0x20u) /* ADC10 Clock Divider Select: 5 */ +#define ADC10DIV_6 (6*0x20u) /* ADC10 Clock Divider Select: 6 */ +#define ADC10DIV_7 (7*0x20u) /* ADC10 Clock Divider Select: 7 */ + +#define ADC10SHS_0 (0*0x400u) /* ADC10 Sample/Hold Source: 0 */ +#define ADC10SHS_1 (1*0x400u) /* ADC10 Sample/Hold Source: 1 */ +#define ADC10SHS_2 (2*0x400u) /* ADC10 Sample/Hold Source: 2 */ +#define ADC10SHS_3 (3*0x400u) /* ADC10 Sample/Hold Source: 3 */ + +/* ADC10CTL2 Control Bits */ +#define ADC10REFBURST (0x0001u) /* ADC10 Reference Burst */ +#define ADC10SR (0x0004u) /* ADC10 Sampling Rate */ +#define ADC10DF (0x0008u) /* ADC10 Data Format */ +#define ADC10RES (0x0010u) /* ADC10 Resolution Bit */ +#define ADC10PDIV0 (0x0100u) /* ADC10 predivider Bit: 0 */ +#define ADC10PDIV1 (0x0200u) /* ADC10 predivider Bit: 1 */ + +/* ADC10CTL2 Control Bits */ +#define ADC10REFBURST_L (0x0001u) /* ADC10 Reference Burst */ +#define ADC10SR_L (0x0004u) /* ADC10 Sampling Rate */ +#define ADC10DF_L (0x0008u) /* ADC10 Data Format */ +#define ADC10RES_L (0x0010u) /* ADC10 Resolution Bit */ + +/* ADC10CTL2 Control Bits */ +#define ADC10PDIV0_H (0x0001u) /* ADC10 predivider Bit: 0 */ +#define ADC10PDIV1_H (0x0002u) /* ADC10 predivider Bit: 1 */ + +#define ADC10PDIV_0 (0x0000u) /* ADC10 predivider /1 */ +#define ADC10PDIV_1 (0x0100u) /* ADC10 predivider /2 */ +#define ADC10PDIV_2 (0x0200u) /* ADC10 predivider /64 */ +#define ADC10PDIV_3 (0x0300u) /* ADC10 predivider reserved */ + +#define ADC10PDIV__1 (0x0000u) /* ADC10 predivider /1 */ +#define ADC10PDIV__4 (0x0100u) /* ADC10 predivider /2 */ +#define ADC10PDIV__64 (0x0200u) /* ADC10 predivider /64 */ + +/* ADC10MCTL0 Control Bits */ +#define ADC10INCH0 (0x0001u) /* ADC10 Input Channel Select Bit 0 */ +#define ADC10INCH1 (0x0002u) /* ADC10 Input Channel Select Bit 1 */ +#define ADC10INCH2 (0x0004u) /* ADC10 Input Channel Select Bit 2 */ +#define ADC10INCH3 (0x0008u) /* ADC10 Input Channel Select Bit 3 */ +#define ADC10SREF0 (0x0010u) /* ADC10 Select Reference Bit 0 */ +#define ADC10SREF1 (0x0020u) /* ADC10 Select Reference Bit 1 */ +#define ADC10SREF2 (0x0040u) /* ADC10 Select Reference Bit 2 */ + +/* ADC10MCTL0 Control Bits */ +#define ADC10INCH0_L (0x0001u) /* ADC10 Input Channel Select Bit 0 */ +#define ADC10INCH1_L (0x0002u) /* ADC10 Input Channel Select Bit 1 */ +#define ADC10INCH2_L (0x0004u) /* ADC10 Input Channel Select Bit 2 */ +#define ADC10INCH3_L (0x0008u) /* ADC10 Input Channel Select Bit 3 */ +#define ADC10SREF0_L (0x0010u) /* ADC10 Select Reference Bit 0 */ +#define ADC10SREF1_L (0x0020u) /* ADC10 Select Reference Bit 1 */ +#define ADC10SREF2_L (0x0040u) /* ADC10 Select Reference Bit 2 */ + +#define ADC10INCH_0 (0) /* ADC10 Input Channel 0 */ +#define ADC10INCH_1 (1) /* ADC10 Input Channel 1 */ +#define ADC10INCH_2 (2) /* ADC10 Input Channel 2 */ +#define ADC10INCH_3 (3) /* ADC10 Input Channel 3 */ +#define ADC10INCH_4 (4) /* ADC10 Input Channel 4 */ +#define ADC10INCH_5 (5) /* ADC10 Input Channel 5 */ +#define ADC10INCH_6 (6) /* ADC10 Input Channel 6 */ +#define ADC10INCH_7 (7) /* ADC10 Input Channel 7 */ +#define ADC10INCH_8 (8) /* ADC10 Input Channel 8 */ +#define ADC10INCH_9 (9) /* ADC10 Input Channel 9 */ +#define ADC10INCH_10 (10) /* ADC10 Input Channel 10 */ +#define ADC10INCH_11 (11) /* ADC10 Input Channel 11 */ +#define ADC10INCH_12 (12) /* ADC10 Input Channel 12 */ +#define ADC10INCH_13 (13) /* ADC10 Input Channel 13 */ +#define ADC10INCH_14 (14) /* ADC10 Input Channel 14 */ +#define ADC10INCH_15 (15) /* ADC10 Input Channel 15 */ + +#define ADC10SREF_0 (0*0x10u) /* ADC10 Select Reference 0 */ +#define ADC10SREF_1 (1*0x10u) /* ADC10 Select Reference 1 */ +#define ADC10SREF_2 (2*0x10u) /* ADC10 Select Reference 2 */ +#define ADC10SREF_3 (3*0x10u) /* ADC10 Select Reference 3 */ +#define ADC10SREF_4 (4*0x10u) /* ADC10 Select Reference 4 */ +#define ADC10SREF_5 (5*0x10u) /* ADC10 Select Reference 5 */ +#define ADC10SREF_6 (6*0x10u) /* ADC10 Select Reference 6 */ +#define ADC10SREF_7 (7*0x10u) /* ADC10 Select Reference 7 */ + +/* ADC10IE Interrupt Enable Bits */ +#define ADC10IE0 (0x0001u) /* ADC10_A Interrupt enable */ +#define ADC10INIE (0x0002u) /* ADC10_A Interrupt enable for the inside of window of the Window comparator */ +#define ADC10LOIE (0x0004u) /* ADC10_A Interrupt enable for lower threshold of the Window comparator */ +#define ADC10HIIE (0x0008u) /* ADC10_A Interrupt enable for upper threshold of the Window comparator */ +#define ADC10OVIE (0x0010u) /* ADC10_A ADC10MEM overflow Interrupt enable */ +#define ADC10TOVIE (0x0020u) /* ADC10_A conversion-time-overflow Interrupt enable */ + +/* ADC10IE Interrupt Enable Bits */ +#define ADC10IE0_L (0x0001u) /* ADC10_A Interrupt enable */ +#define ADC10INIE_L (0x0002u) /* ADC10_A Interrupt enable for the inside of window of the Window comparator */ +#define ADC10LOIE_L (0x0004u) /* ADC10_A Interrupt enable for lower threshold of the Window comparator */ +#define ADC10HIIE_L (0x0008u) /* ADC10_A Interrupt enable for upper threshold of the Window comparator */ +#define ADC10OVIE_L (0x0010u) /* ADC10_A ADC10MEM overflow Interrupt enable */ +#define ADC10TOVIE_L (0x0020u) /* ADC10_A conversion-time-overflow Interrupt enable */ + +/* ADC10IFG Interrupt Flag Bits */ +#define ADC10IFG0 (0x0001u) /* ADC10_A Interrupt Flag */ +#define ADC10INIFG (0x0002u) /* ADC10_A Interrupt Flag for the inside of window of the Window comparator */ +#define ADC10LOIFG (0x0004u) /* ADC10_A Interrupt Flag for lower threshold of the Window comparator */ +#define ADC10HIIFG (0x0008u) /* ADC10_A Interrupt Flag for upper threshold of the Window comparator */ +#define ADC10OVIFG (0x0010u) /* ADC10_A ADC10MEM overflow Interrupt Flag */ +#define ADC10TOVIFG (0x0020u) /* ADC10_A conversion-time-overflow Interrupt Flag */ + +/* ADC10IFG Interrupt Flag Bits */ +#define ADC10IFG0_L (0x0001u) /* ADC10_A Interrupt Flag */ +#define ADC10INIFG_L (0x0002u) /* ADC10_A Interrupt Flag for the inside of window of the Window comparator */ +#define ADC10LOIFG_L (0x0004u) /* ADC10_A Interrupt Flag for lower threshold of the Window comparator */ +#define ADC10HIIFG_L (0x0008u) /* ADC10_A Interrupt Flag for upper threshold of the Window comparator */ +#define ADC10OVIFG_L (0x0010u) /* ADC10_A ADC10MEM overflow Interrupt Flag */ +#define ADC10TOVIFG_L (0x0020u) /* ADC10_A conversion-time-overflow Interrupt Flag */ + +/* ADC10IV Definitions */ +#define ADC10IV_NONE (0x0000u) /* No Interrupt pending */ +#define ADC10IV_ADC10OVIFG (0x0002u) /* ADC10OVIFG */ +#define ADC10IV_ADC10TOVIFG (0x0004u) /* ADC10TOVIFG */ +#define ADC10IV_ADC10HIIFG (0x0006u) /* ADC10HIIFG */ +#define ADC10IV_ADC10LOIFG (0x0008u) /* ADC10LOIFG */ +#define ADC10IV_ADC10INIFG (0x000Au) /* ADC10INIFG */ +#define ADC10IV_ADC10IFG (0x000Cu) /* ADC10IFG */ + +#endif +/************************************************************ +* ADC12 PLUS +************************************************************/ +#ifdef __MSP430_HAS_ADC12_PLUS__ /* Definition to show that Module is available */ + +#define OFS_ADC12CTL0 (0x0000u) /* ADC12+ Control 0 */ +#define OFS_ADC12CTL0_L OFS_ADC12CTL0 +#define OFS_ADC12CTL0_H OFS_ADC12CTL0+1 +#define OFS_ADC12CTL1 (0x0002u) /* ADC12+ Control 1 */ +#define OFS_ADC12CTL1_L OFS_ADC12CTL1 +#define OFS_ADC12CTL1_H OFS_ADC12CTL1+1 +#define OFS_ADC12CTL2 (0x0004u) /* ADC12+ Control 2 */ +#define OFS_ADC12CTL2_L OFS_ADC12CTL2 +#define OFS_ADC12CTL2_H OFS_ADC12CTL2+1 +#define OFS_ADC12IFG (0x000Au) /* ADC12+ Interrupt Flag */ +#define OFS_ADC12IFG_L OFS_ADC12IFG +#define OFS_ADC12IFG_H OFS_ADC12IFG+1 +#define OFS_ADC12IE (0x000Cu) /* ADC12+ Interrupt Enable */ +#define OFS_ADC12IE_L OFS_ADC12IE +#define OFS_ADC12IE_H OFS_ADC12IE+1 +#define OFS_ADC12IV (0x000Eu) /* ADC12+ Interrupt Vector Word */ +#define OFS_ADC12IV_L OFS_ADC12IV +#define OFS_ADC12IV_H OFS_ADC12IV+1 + +#define OFS_ADC12MEM0 (0x0020u) /* ADC12 Conversion Memory 0 */ +#define OFS_ADC12MEM0_L OFS_ADC12MEM0 +#define OFS_ADC12MEM0_H OFS_ADC12MEM0+1 +#define OFS_ADC12MEM1 (0x0022u) /* ADC12 Conversion Memory 1 */ +#define OFS_ADC12MEM1_L OFS_ADC12MEM1 +#define OFS_ADC12MEM1_H OFS_ADC12MEM1+1 +#define OFS_ADC12MEM2 (0x0024u) /* ADC12 Conversion Memory 2 */ +#define OFS_ADC12MEM2_L OFS_ADC12MEM2 +#define OFS_ADC12MEM2_H OFS_ADC12MEM2+1 +#define OFS_ADC12MEM3 (0x0026u) /* ADC12 Conversion Memory 3 */ +#define OFS_ADC12MEM3_L OFS_ADC12MEM3 +#define OFS_ADC12MEM3_H OFS_ADC12MEM3+1 +#define OFS_ADC12MEM4 (0x0028u) /* ADC12 Conversion Memory 4 */ +#define OFS_ADC12MEM4_L OFS_ADC12MEM4 +#define OFS_ADC12MEM4_H OFS_ADC12MEM4+1 +#define OFS_ADC12MEM5 (0x002Au) /* ADC12 Conversion Memory 5 */ +#define OFS_ADC12MEM5_L OFS_ADC12MEM5 +#define OFS_ADC12MEM5_H OFS_ADC12MEM5+1 +#define OFS_ADC12MEM6 (0x002Cu) /* ADC12 Conversion Memory 6 */ +#define OFS_ADC12MEM6_L OFS_ADC12MEM6 +#define OFS_ADC12MEM6_H OFS_ADC12MEM6+1 +#define OFS_ADC12MEM7 (0x002Eu) /* ADC12 Conversion Memory 7 */ +#define OFS_ADC12MEM7_L OFS_ADC12MEM7 +#define OFS_ADC12MEM7_H OFS_ADC12MEM7+1 +#define OFS_ADC12MEM8 (0x0030u) /* ADC12 Conversion Memory 8 */ +#define OFS_ADC12MEM8_L OFS_ADC12MEM8 +#define OFS_ADC12MEM8_H OFS_ADC12MEM8+1 +#define OFS_ADC12MEM9 (0x0032u) /* ADC12 Conversion Memory 9 */ +#define OFS_ADC12MEM9_L OFS_ADC12MEM9 +#define OFS_ADC12MEM9_H OFS_ADC12MEM9+1 +#define OFS_ADC12MEM10 (0x0034u) /* ADC12 Conversion Memory 10 */ +#define OFS_ADC12MEM10_L OFS_ADC12MEM10 +#define OFS_ADC12MEM10_H OFS_ADC12MEM10+1 +#define OFS_ADC12MEM11 (0x0036u) /* ADC12 Conversion Memory 11 */ +#define OFS_ADC12MEM11_L OFS_ADC12MEM11 +#define OFS_ADC12MEM11_H OFS_ADC12MEM11+1 +#define OFS_ADC12MEM12 (0x0038u) /* ADC12 Conversion Memory 12 */ +#define OFS_ADC12MEM12_L OFS_ADC12MEM12 +#define OFS_ADC12MEM12_H OFS_ADC12MEM12+1 +#define OFS_ADC12MEM13 (0x003Au) /* ADC12 Conversion Memory 13 */ +#define OFS_ADC12MEM13_L OFS_ADC12MEM13 +#define OFS_ADC12MEM13_H OFS_ADC12MEM13+1 +#define OFS_ADC12MEM14 (0x003Cu) /* ADC12 Conversion Memory 14 */ +#define OFS_ADC12MEM14_L OFS_ADC12MEM14 +#define OFS_ADC12MEM14_H OFS_ADC12MEM14+1 +#define OFS_ADC12MEM15 (0x003Eu) /* ADC12 Conversion Memory 15 */ +#define OFS_ADC12MEM15_L OFS_ADC12MEM15 +#define OFS_ADC12MEM15_H OFS_ADC12MEM15+1 +#define ADC12MEM_ ADC12MEM /* ADC12 Conversion Memory */ +#ifndef __IAR_SYSTEMS_ICC__ +#define ADC12MEM ADC12MEM0 /* ADC12 Conversion Memory (for assembler) */ +#else +#define ADC12MEM ((int*) &ADC12MEM0) /* ADC12 Conversion Memory (for C) */ +#endif + +#define OFS_ADC12MCTL0 (0x0010u) /* ADC12 Memory Control 0 */ +#define OFS_ADC12MCTL1 (0x0011u) /* ADC12 Memory Control 1 */ +#define OFS_ADC12MCTL2 (0x0012u) /* ADC12 Memory Control 2 */ +#define OFS_ADC12MCTL3 (0x0013u) /* ADC12 Memory Control 3 */ +#define OFS_ADC12MCTL4 (0x0014u) /* ADC12 Memory Control 4 */ +#define OFS_ADC12MCTL5 (0x0015u) /* ADC12 Memory Control 5 */ +#define OFS_ADC12MCTL6 (0x0016u) /* ADC12 Memory Control 6 */ +#define OFS_ADC12MCTL7 (0x0017u) /* ADC12 Memory Control 7 */ +#define OFS_ADC12MCTL8 (0x0018u) /* ADC12 Memory Control 8 */ +#define OFS_ADC12MCTL9 (0x0019u) /* ADC12 Memory Control 9 */ +#define OFS_ADC12MCTL10 (0x001Au) /* ADC12 Memory Control 10 */ +#define OFS_ADC12MCTL11 (0x001Bu) /* ADC12 Memory Control 11 */ +#define OFS_ADC12MCTL12 (0x001Cu) /* ADC12 Memory Control 12 */ +#define OFS_ADC12MCTL13 (0x001Du) /* ADC12 Memory Control 13 */ +#define OFS_ADC12MCTL14 (0x001Eu) /* ADC12 Memory Control 14 */ +#define OFS_ADC12MCTL15 (0x001Fu) /* ADC12 Memory Control 15 */ +#define ADC12MCTL_ ADC12MCTL /* ADC12 Memory Control */ +#ifndef __IAR_SYSTEMS_ICC__ +#define ADC12MCTL ADC12MCTL0 /* ADC12 Memory Control (for assembler) */ +#else +#define ADC12MCTL ((char*) &ADC12MCTL0) /* ADC12 Memory Control (for C) */ +#endif + +/* ADC12CTL0 Control Bits */ +#define ADC12SC (0x0001u) /* ADC12 Start Conversion */ +#define ADC12ENC (0x0002u) /* ADC12 Enable Conversion */ +#define ADC12TOVIE (0x0004u) /* ADC12 Timer Overflow interrupt enable */ +#define ADC12OVIE (0x0008u) /* ADC12 Overflow interrupt enable */ +#define ADC12ON (0x0010u) /* ADC12 On/enable */ +#define ADC12REFON (0x0020u) /* ADC12 Reference on */ +#define ADC12REF2_5V (0x0040u) /* ADC12 Ref 0:1.5V / 1:2.5V */ +#define ADC12MSC (0x0080u) /* ADC12 Multiple SampleConversion */ +#define ADC12SHT00 (0x0100u) /* ADC12 Sample Hold 0 Select Bit: 0 */ +#define ADC12SHT01 (0x0200u) /* ADC12 Sample Hold 0 Select Bit: 1 */ +#define ADC12SHT02 (0x0400u) /* ADC12 Sample Hold 0 Select Bit: 2 */ +#define ADC12SHT03 (0x0800u) /* ADC12 Sample Hold 0 Select Bit: 3 */ +#define ADC12SHT10 (0x1000u) /* ADC12 Sample Hold 1 Select Bit: 0 */ +#define ADC12SHT11 (0x2000u) /* ADC12 Sample Hold 1 Select Bit: 1 */ +#define ADC12SHT12 (0x4000u) /* ADC12 Sample Hold 1 Select Bit: 2 */ +#define ADC12SHT13 (0x8000u) /* ADC12 Sample Hold 1 Select Bit: 3 */ + +/* ADC12CTL0 Control Bits */ +#define ADC12SC_L (0x0001u) /* ADC12 Start Conversion */ +#define ADC12ENC_L (0x0002u) /* ADC12 Enable Conversion */ +#define ADC12TOVIE_L (0x0004u) /* ADC12 Timer Overflow interrupt enable */ +#define ADC12OVIE_L (0x0008u) /* ADC12 Overflow interrupt enable */ +#define ADC12ON_L (0x0010u) /* ADC12 On/enable */ +#define ADC12REFON_L (0x0020u) /* ADC12 Reference on */ +#define ADC12REF2_5V_L (0x0040u) /* ADC12 Ref 0:1.5V / 1:2.5V */ +#define ADC12MSC_L (0x0080u) /* ADC12 Multiple SampleConversion */ + +/* ADC12CTL0 Control Bits */ +#define ADC12SHT00_H (0x0001u) /* ADC12 Sample Hold 0 Select Bit: 0 */ +#define ADC12SHT01_H (0x0002u) /* ADC12 Sample Hold 0 Select Bit: 1 */ +#define ADC12SHT02_H (0x0004u) /* ADC12 Sample Hold 0 Select Bit: 2 */ +#define ADC12SHT03_H (0x0008u) /* ADC12 Sample Hold 0 Select Bit: 3 */ +#define ADC12SHT10_H (0x0010u) /* ADC12 Sample Hold 1 Select Bit: 0 */ +#define ADC12SHT11_H (0x0020u) /* ADC12 Sample Hold 1 Select Bit: 1 */ +#define ADC12SHT12_H (0x0040u) /* ADC12 Sample Hold 1 Select Bit: 2 */ +#define ADC12SHT13_H (0x0080u) /* ADC12 Sample Hold 1 Select Bit: 3 */ + +#define ADC12SHT0_0 (0*0x100u) /* ADC12 Sample Hold 0 Select Bit: 0 */ +#define ADC12SHT0_1 (1*0x100u) /* ADC12 Sample Hold 0 Select Bit: 1 */ +#define ADC12SHT0_2 (2*0x100u) /* ADC12 Sample Hold 0 Select Bit: 2 */ +#define ADC12SHT0_3 (3*0x100u) /* ADC12 Sample Hold 0 Select Bit: 3 */ +#define ADC12SHT0_4 (4*0x100u) /* ADC12 Sample Hold 0 Select Bit: 4 */ +#define ADC12SHT0_5 (5*0x100u) /* ADC12 Sample Hold 0 Select Bit: 5 */ +#define ADC12SHT0_6 (6*0x100u) /* ADC12 Sample Hold 0 Select Bit: 6 */ +#define ADC12SHT0_7 (7*0x100u) /* ADC12 Sample Hold 0 Select Bit: 7 */ +#define ADC12SHT0_8 (8*0x100u) /* ADC12 Sample Hold 0 Select Bit: 8 */ +#define ADC12SHT0_9 (9*0x100u) /* ADC12 Sample Hold 0 Select Bit: 9 */ +#define ADC12SHT0_10 (10*0x100u) /* ADC12 Sample Hold 0 Select Bit: 10 */ +#define ADC12SHT0_11 (11*0x100u) /* ADC12 Sample Hold 0 Select Bit: 11 */ +#define ADC12SHT0_12 (12*0x100u) /* ADC12 Sample Hold 0 Select Bit: 12 */ +#define ADC12SHT0_13 (13*0x100u) /* ADC12 Sample Hold 0 Select Bit: 13 */ +#define ADC12SHT0_14 (14*0x100u) /* ADC12 Sample Hold 0 Select Bit: 14 */ +#define ADC12SHT0_15 (15*0x100u) /* ADC12 Sample Hold 0 Select Bit: 15 */ + +#define ADC12SHT1_0 (0*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 0 */ +#define ADC12SHT1_1 (1*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 1 */ +#define ADC12SHT1_2 (2*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 2 */ +#define ADC12SHT1_3 (3*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 3 */ +#define ADC12SHT1_4 (4*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 4 */ +#define ADC12SHT1_5 (5*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 5 */ +#define ADC12SHT1_6 (6*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 6 */ +#define ADC12SHT1_7 (7*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 7 */ +#define ADC12SHT1_8 (8*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 8 */ +#define ADC12SHT1_9 (9*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 9 */ +#define ADC12SHT1_10 (10*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 10 */ +#define ADC12SHT1_11 (11*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 11 */ +#define ADC12SHT1_12 (12*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 12 */ +#define ADC12SHT1_13 (13*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 13 */ +#define ADC12SHT1_14 (14*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 14 */ +#define ADC12SHT1_15 (15*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 15 */ + +/* ADC12CTL1 Control Bits */ +#define ADC12BUSY (0x0001u) /* ADC12 Busy */ +#define ADC12CONSEQ0 (0x0002u) /* ADC12 Conversion Sequence Select Bit: 0 */ +#define ADC12CONSEQ1 (0x0004u) /* ADC12 Conversion Sequence Select Bit: 1 */ +#define ADC12SSEL0 (0x0008u) /* ADC12 Clock Source Select Bit: 0 */ +#define ADC12SSEL1 (0x0010u) /* ADC12 Clock Source Select Bit: 1 */ +#define ADC12DIV0 (0x0020u) /* ADC12 Clock Divider Select Bit: 0 */ +#define ADC12DIV1 (0x0040u) /* ADC12 Clock Divider Select Bit: 1 */ +#define ADC12DIV2 (0x0080u) /* ADC12 Clock Divider Select Bit: 2 */ +#define ADC12ISSH (0x0100u) /* ADC12 Invert Sample Hold Signal */ +#define ADC12SHP (0x0200u) /* ADC12 Sample/Hold Pulse Mode */ +#define ADC12SHS0 (0x0400u) /* ADC12 Sample/Hold Source Bit: 0 */ +#define ADC12SHS1 (0x0800u) /* ADC12 Sample/Hold Source Bit: 1 */ +#define ADC12CSTARTADD0 (0x1000u) /* ADC12 Conversion Start Address Bit: 0 */ +#define ADC12CSTARTADD1 (0x2000u) /* ADC12 Conversion Start Address Bit: 1 */ +#define ADC12CSTARTADD2 (0x4000u) /* ADC12 Conversion Start Address Bit: 2 */ +#define ADC12CSTARTADD3 (0x8000u) /* ADC12 Conversion Start Address Bit: 3 */ + +/* ADC12CTL1 Control Bits */ +#define ADC12BUSY_L (0x0001u) /* ADC12 Busy */ +#define ADC12CONSEQ0_L (0x0002u) /* ADC12 Conversion Sequence Select Bit: 0 */ +#define ADC12CONSEQ1_L (0x0004u) /* ADC12 Conversion Sequence Select Bit: 1 */ +#define ADC12SSEL0_L (0x0008u) /* ADC12 Clock Source Select Bit: 0 */ +#define ADC12SSEL1_L (0x0010u) /* ADC12 Clock Source Select Bit: 1 */ +#define ADC12DIV0_L (0x0020u) /* ADC12 Clock Divider Select Bit: 0 */ +#define ADC12DIV1_L (0x0040u) /* ADC12 Clock Divider Select Bit: 1 */ +#define ADC12DIV2_L (0x0080u) /* ADC12 Clock Divider Select Bit: 2 */ + +/* ADC12CTL1 Control Bits */ +#define ADC12ISSH_H (0x0001u) /* ADC12 Invert Sample Hold Signal */ +#define ADC12SHP_H (0x0002u) /* ADC12 Sample/Hold Pulse Mode */ +#define ADC12SHS0_H (0x0004u) /* ADC12 Sample/Hold Source Bit: 0 */ +#define ADC12SHS1_H (0x0008u) /* ADC12 Sample/Hold Source Bit: 1 */ +#define ADC12CSTARTADD0_H (0x0010u) /* ADC12 Conversion Start Address Bit: 0 */ +#define ADC12CSTARTADD1_H (0x0020u) /* ADC12 Conversion Start Address Bit: 1 */ +#define ADC12CSTARTADD2_H (0x0040u) /* ADC12 Conversion Start Address Bit: 2 */ +#define ADC12CSTARTADD3_H (0x0080u) /* ADC12 Conversion Start Address Bit: 3 */ + +#define ADC12CONSEQ_0 (0*2u) /* ADC12 Conversion Sequence Select: 0 */ +#define ADC12CONSEQ_1 (1*2u) /* ADC12 Conversion Sequence Select: 1 */ +#define ADC12CONSEQ_2 (2*2u) /* ADC12 Conversion Sequence Select: 2 */ +#define ADC12CONSEQ_3 (3*2u) /* ADC12 Conversion Sequence Select: 3 */ + +#define ADC12SSEL_0 (0*8u) /* ADC12 Clock Source Select: 0 */ +#define ADC12SSEL_1 (1*8u) /* ADC12 Clock Source Select: 1 */ +#define ADC12SSEL_2 (2*8u) /* ADC12 Clock Source Select: 2 */ +#define ADC12SSEL_3 (3*8u) /* ADC12 Clock Source Select: 3 */ + +#define ADC12DIV_0 (0*0x20u) /* ADC12 Clock Divider Select: 0 */ +#define ADC12DIV_1 (1*0x20u) /* ADC12 Clock Divider Select: 1 */ +#define ADC12DIV_2 (2*0x20u) /* ADC12 Clock Divider Select: 2 */ +#define ADC12DIV_3 (3*0x20u) /* ADC12 Clock Divider Select: 3 */ +#define ADC12DIV_4 (4*0x20u) /* ADC12 Clock Divider Select: 4 */ +#define ADC12DIV_5 (5*0x20u) /* ADC12 Clock Divider Select: 5 */ +#define ADC12DIV_6 (6*0x20u) /* ADC12 Clock Divider Select: 6 */ +#define ADC12DIV_7 (7*0x20u) /* ADC12 Clock Divider Select: 7 */ + +#define ADC12SHS_0 (0*0x400u) /* ADC12 Sample/Hold Source: 0 */ +#define ADC12SHS_1 (1*0x400u) /* ADC12 Sample/Hold Source: 1 */ +#define ADC12SHS_2 (2*0x400u) /* ADC12 Sample/Hold Source: 2 */ +#define ADC12SHS_3 (3*0x400u) /* ADC12 Sample/Hold Source: 3 */ + +#define ADC12CSTARTADD_0 (0*0x1000u) /* ADC12 Conversion Start Address: 0 */ +#define ADC12CSTARTADD_1 (1*0x1000u) /* ADC12 Conversion Start Address: 1 */ +#define ADC12CSTARTADD_2 (2*0x1000u) /* ADC12 Conversion Start Address: 2 */ +#define ADC12CSTARTADD_3 (3*0x1000u) /* ADC12 Conversion Start Address: 3 */ +#define ADC12CSTARTADD_4 (4*0x1000u) /* ADC12 Conversion Start Address: 4 */ +#define ADC12CSTARTADD_5 (5*0x1000u) /* ADC12 Conversion Start Address: 5 */ +#define ADC12CSTARTADD_6 (6*0x1000u) /* ADC12 Conversion Start Address: 6 */ +#define ADC12CSTARTADD_7 (7*0x1000u) /* ADC12 Conversion Start Address: 7 */ +#define ADC12CSTARTADD_8 (8*0x1000u) /* ADC12 Conversion Start Address: 8 */ +#define ADC12CSTARTADD_9 (9*0x1000u) /* ADC12 Conversion Start Address: 9 */ +#define ADC12CSTARTADD_10 (10*0x1000u) /* ADC12 Conversion Start Address: 10 */ +#define ADC12CSTARTADD_11 (11*0x1000u) /* ADC12 Conversion Start Address: 11 */ +#define ADC12CSTARTADD_12 (12*0x1000u) /* ADC12 Conversion Start Address: 12 */ +#define ADC12CSTARTADD_13 (13*0x1000u) /* ADC12 Conversion Start Address: 13 */ +#define ADC12CSTARTADD_14 (14*0x1000u) /* ADC12 Conversion Start Address: 14 */ +#define ADC12CSTARTADD_15 (15*0x1000u) /* ADC12 Conversion Start Address: 15 */ + +/* ADC12CTL2 Control Bits */ +#define ADC12REFBURST (0x0001u) /* ADC12+ Reference Burst */ +#define ADC12REFOUT (0x0002u) /* ADC12+ Reference Out */ +#define ADC12SR (0x0004u) /* ADC12+ Sampling Rate */ +#define ADC12DF (0x0008u) /* ADC12+ Data Format */ +#define ADC12RES0 (0x0010u) /* ADC12+ Resolution Bit: 0 */ +#define ADC12RES1 (0x0020u) /* ADC12+ Resolution Bit: 1 */ +#define ADC12TCOFF (0x0080u) /* ADC12+ Temperature Sensor Off */ +#define ADC12PDIV (0x0100u) /* ADC12+ predivider 0:/1 1:/4 */ + +/* ADC12CTL2 Control Bits */ +#define ADC12REFBURST_L (0x0001u) /* ADC12+ Reference Burst */ +#define ADC12REFOUT_L (0x0002u) /* ADC12+ Reference Out */ +#define ADC12SR_L (0x0004u) /* ADC12+ Sampling Rate */ +#define ADC12DF_L (0x0008u) /* ADC12+ Data Format */ +#define ADC12RES0_L (0x0010u) /* ADC12+ Resolution Bit: 0 */ +#define ADC12RES1_L (0x0020u) /* ADC12+ Resolution Bit: 1 */ +#define ADC12TCOFF_L (0x0080u) /* ADC12+ Temperature Sensor Off */ + +/* ADC12CTL2 Control Bits */ +#define ADC12PDIV_H (0x0001u) /* ADC12+ predivider 0:/1 1:/4 */ + +#define ADC12RES_0 (0x0000u) /* ADC12+ Resolution : 8 Bit */ +#define ADC12RES_1 (0x0010u) /* ADC12+ Resolution : 10 Bit */ +#define ADC12RES_2 (0x0020u) /* ADC12+ Resolution : 12 Bit */ +#define ADC12RES_3 (0x0030u) /* ADC12+ Resolution : reserved */ + +/* ADC12MCTLx Control Bits */ +#define ADC12INCH0 (0x0001u) /* ADC12 Input Channel Select Bit 0 */ +#define ADC12INCH1 (0x0002u) /* ADC12 Input Channel Select Bit 1 */ +#define ADC12INCH2 (0x0004u) /* ADC12 Input Channel Select Bit 2 */ +#define ADC12INCH3 (0x0008u) /* ADC12 Input Channel Select Bit 3 */ +#define ADC12SREF0 (0x0010u) /* ADC12 Select Reference Bit 0 */ +#define ADC12SREF1 (0x0020u) /* ADC12 Select Reference Bit 1 */ +#define ADC12SREF2 (0x0040u) /* ADC12 Select Reference Bit 2 */ +#define ADC12EOS (0x0080u) /* ADC12 End of Sequence */ + +#define ADC12INCH_0 (0x0000u) /* ADC12 Input Channel 0 */ +#define ADC12INCH_1 (0x0001u) /* ADC12 Input Channel 1 */ +#define ADC12INCH_2 (0x0002u) /* ADC12 Input Channel 2 */ +#define ADC12INCH_3 (0x0003u) /* ADC12 Input Channel 3 */ +#define ADC12INCH_4 (0x0004u) /* ADC12 Input Channel 4 */ +#define ADC12INCH_5 (0x0005u) /* ADC12 Input Channel 5 */ +#define ADC12INCH_6 (0x0006u) /* ADC12 Input Channel 6 */ +#define ADC12INCH_7 (0x0007u) /* ADC12 Input Channel 7 */ +#define ADC12INCH_8 (0x0008u) /* ADC12 Input Channel 8 */ +#define ADC12INCH_9 (0x0009u) /* ADC12 Input Channel 9 */ +#define ADC12INCH_10 (0x000Au) /* ADC12 Input Channel 10 */ +#define ADC12INCH_11 (0x000Bu) /* ADC12 Input Channel 11 */ +#define ADC12INCH_12 (0x000Cu) /* ADC12 Input Channel 12 */ +#define ADC12INCH_13 (0x000Du) /* ADC12 Input Channel 13 */ +#define ADC12INCH_14 (0x000Eu) /* ADC12 Input Channel 14 */ +#define ADC12INCH_15 (0x000Fu) /* ADC12 Input Channel 15 */ + +#define ADC12SREF_0 (0*0x10u) /* ADC12 Select Reference 0 */ +#define ADC12SREF_1 (1*0x10u) /* ADC12 Select Reference 1 */ +#define ADC12SREF_2 (2*0x10u) /* ADC12 Select Reference 2 */ +#define ADC12SREF_3 (3*0x10u) /* ADC12 Select Reference 3 */ +#define ADC12SREF_4 (4*0x10u) /* ADC12 Select Reference 4 */ +#define ADC12SREF_5 (5*0x10u) /* ADC12 Select Reference 5 */ +#define ADC12SREF_6 (6*0x10u) /* ADC12 Select Reference 6 */ +#define ADC12SREF_7 (7*0x10u) /* ADC12 Select Reference 7 */ + +#define ADC12IE0 (0x0001u) /* ADC12 Memory 0 Interrupt Enable */ +#define ADC12IE1 (0x0002u) /* ADC12 Memory 1 Interrupt Enable */ +#define ADC12IE2 (0x0004u) /* ADC12 Memory 2 Interrupt Enable */ +#define ADC12IE3 (0x0008u) /* ADC12 Memory 3 Interrupt Enable */ +#define ADC12IE4 (0x0010u) /* ADC12 Memory 4 Interrupt Enable */ +#define ADC12IE5 (0x0020u) /* ADC12 Memory 5 Interrupt Enable */ +#define ADC12IE6 (0x0040u) /* ADC12 Memory 6 Interrupt Enable */ +#define ADC12IE7 (0x0080u) /* ADC12 Memory 7 Interrupt Enable */ +#define ADC12IE8 (0x0100u) /* ADC12 Memory 8 Interrupt Enable */ +#define ADC12IE9 (0x0200u) /* ADC12 Memory 9 Interrupt Enable */ +#define ADC12IE10 (0x0400u) /* ADC12 Memory 10 Interrupt Enable */ +#define ADC12IE11 (0x0800u) /* ADC12 Memory 11 Interrupt Enable */ +#define ADC12IE12 (0x1000u) /* ADC12 Memory 12 Interrupt Enable */ +#define ADC12IE13 (0x2000u) /* ADC12 Memory 13 Interrupt Enable */ +#define ADC12IE14 (0x4000u) /* ADC12 Memory 14 Interrupt Enable */ +#define ADC12IE15 (0x8000u) /* ADC12 Memory 15 Interrupt Enable */ + +#define ADC12IE0_L (0x0001u) /* ADC12 Memory 0 Interrupt Enable */ +#define ADC12IE1_L (0x0002u) /* ADC12 Memory 1 Interrupt Enable */ +#define ADC12IE2_L (0x0004u) /* ADC12 Memory 2 Interrupt Enable */ +#define ADC12IE3_L (0x0008u) /* ADC12 Memory 3 Interrupt Enable */ +#define ADC12IE4_L (0x0010u) /* ADC12 Memory 4 Interrupt Enable */ +#define ADC12IE5_L (0x0020u) /* ADC12 Memory 5 Interrupt Enable */ +#define ADC12IE6_L (0x0040u) /* ADC12 Memory 6 Interrupt Enable */ +#define ADC12IE7_L (0x0080u) /* ADC12 Memory 7 Interrupt Enable */ + +#define ADC12IE8_H (0x0001u) /* ADC12 Memory 8 Interrupt Enable */ +#define ADC12IE9_H (0x0002u) /* ADC12 Memory 9 Interrupt Enable */ +#define ADC12IE10_H (0x0004u) /* ADC12 Memory 10 Interrupt Enable */ +#define ADC12IE11_H (0x0008u) /* ADC12 Memory 11 Interrupt Enable */ +#define ADC12IE12_H (0x0010u) /* ADC12 Memory 12 Interrupt Enable */ +#define ADC12IE13_H (0x0020u) /* ADC12 Memory 13 Interrupt Enable */ +#define ADC12IE14_H (0x0040u) /* ADC12 Memory 14 Interrupt Enable */ +#define ADC12IE15_H (0x0080u) /* ADC12 Memory 15 Interrupt Enable */ + +#define ADC12IFG0 (0x0001u) /* ADC12 Memory 0 Interrupt Flag */ +#define ADC12IFG1 (0x0002u) /* ADC12 Memory 1 Interrupt Flag */ +#define ADC12IFG2 (0x0004u) /* ADC12 Memory 2 Interrupt Flag */ +#define ADC12IFG3 (0x0008u) /* ADC12 Memory 3 Interrupt Flag */ +#define ADC12IFG4 (0x0010u) /* ADC12 Memory 4 Interrupt Flag */ +#define ADC12IFG5 (0x0020u) /* ADC12 Memory 5 Interrupt Flag */ +#define ADC12IFG6 (0x0040u) /* ADC12 Memory 6 Interrupt Flag */ +#define ADC12IFG7 (0x0080u) /* ADC12 Memory 7 Interrupt Flag */ +#define ADC12IFG8 (0x0100u) /* ADC12 Memory 8 Interrupt Flag */ +#define ADC12IFG9 (0x0200u) /* ADC12 Memory 9 Interrupt Flag */ +#define ADC12IFG10 (0x0400u) /* ADC12 Memory 10 Interrupt Flag */ +#define ADC12IFG11 (0x0800u) /* ADC12 Memory 11 Interrupt Flag */ +#define ADC12IFG12 (0x1000u) /* ADC12 Memory 12 Interrupt Flag */ +#define ADC12IFG13 (0x2000u) /* ADC12 Memory 13 Interrupt Flag */ +#define ADC12IFG14 (0x4000u) /* ADC12 Memory 14 Interrupt Flag */ +#define ADC12IFG15 (0x8000u) /* ADC12 Memory 15 Interrupt Flag */ + +#define ADC12IFG0_L (0x0001u) /* ADC12 Memory 0 Interrupt Flag */ +#define ADC12IFG1_L (0x0002u) /* ADC12 Memory 1 Interrupt Flag */ +#define ADC12IFG2_L (0x0004u) /* ADC12 Memory 2 Interrupt Flag */ +#define ADC12IFG3_L (0x0008u) /* ADC12 Memory 3 Interrupt Flag */ +#define ADC12IFG4_L (0x0010u) /* ADC12 Memory 4 Interrupt Flag */ +#define ADC12IFG5_L (0x0020u) /* ADC12 Memory 5 Interrupt Flag */ +#define ADC12IFG6_L (0x0040u) /* ADC12 Memory 6 Interrupt Flag */ +#define ADC12IFG7_L (0x0080u) /* ADC12 Memory 7 Interrupt Flag */ + +#define ADC12IFG8_H (0x0001u) /* ADC12 Memory 8 Interrupt Flag */ +#define ADC12IFG9_H (0x0002u) /* ADC12 Memory 9 Interrupt Flag */ +#define ADC12IFG10_H (0x0004u) /* ADC12 Memory 10 Interrupt Flag */ +#define ADC12IFG11_H (0x0008u) /* ADC12 Memory 11 Interrupt Flag */ +#define ADC12IFG12_H (0x0010u) /* ADC12 Memory 12 Interrupt Flag */ +#define ADC12IFG13_H (0x0020u) /* ADC12 Memory 13 Interrupt Flag */ +#define ADC12IFG14_H (0x0040u) /* ADC12 Memory 14 Interrupt Flag */ +#define ADC12IFG15_H (0x0080u) /* ADC12 Memory 15 Interrupt Flag */ + +/* ADC12IV Definitions */ +#define ADC12IV_NONE (0x0000u) /* No Interrupt pending */ +#define ADC12IV_ADC12OVIFG (0x0002u) /* ADC12OVIFG */ +#define ADC12IV_ADC12TOVIFG (0x0004u) /* ADC12TOVIFG */ +#define ADC12IV_ADC12IFG0 (0x0006u) /* ADC12IFG0 */ +#define ADC12IV_ADC12IFG1 (0x0008u) /* ADC12IFG1 */ +#define ADC12IV_ADC12IFG2 (0x000Au) /* ADC12IFG2 */ +#define ADC12IV_ADC12IFG3 (0x000Cu) /* ADC12IFG3 */ +#define ADC12IV_ADC12IFG4 (0x000Eu) /* ADC12IFG4 */ +#define ADC12IV_ADC12IFG5 (0x0010u) /* ADC12IFG5 */ +#define ADC12IV_ADC12IFG6 (0x0012u) /* ADC12IFG6 */ +#define ADC12IV_ADC12IFG7 (0x0014u) /* ADC12IFG7 */ +#define ADC12IV_ADC12IFG8 (0x0016u) /* ADC12IFG8 */ +#define ADC12IV_ADC12IFG9 (0x0018u) /* ADC12IFG9 */ +#define ADC12IV_ADC12IFG10 (0x001Au) /* ADC12IFG10 */ +#define ADC12IV_ADC12IFG11 (0x001Cu) /* ADC12IFG11 */ +#define ADC12IV_ADC12IFG12 (0x001Eu) /* ADC12IFG12 */ +#define ADC12IV_ADC12IFG13 (0x0020u) /* ADC12IFG13 */ +#define ADC12IV_ADC12IFG14 (0x0022u) /* ADC12IFG14 */ +#define ADC12IV_ADC12IFG15 (0x0024u) /* ADC12IFG15 */ + +#endif +/************************************************************ +* AES Accelerator +************************************************************/ +#ifdef __MSP430_HAS_AES__ /* Definition to show that Module is available */ + +#define OFS_AESACTL0 (0x0000u) /* AES accelerator control register 0 */ +#define OFS_AESACTL0_L OFS_AESACTL0 +#define OFS_AESACTL0_H OFS_AESACTL0+1 +#define OFS_AESASTAT (0x0004u) /* AES accelerator status register */ +#define OFS_AESASTAT_L OFS_AESASTAT +#define OFS_AESASTAT_H OFS_AESASTAT+1 +#define OFS_AESAKEY (0x0006u) /* AES accelerator key register */ +#define OFS_AESAKEY_L OFS_AESAKEY +#define OFS_AESAKEY_H OFS_AESAKEY+1 +#define OFS_AESADIN (0x0008u) /* AES accelerator data in register */ +#define OFS_AESADIN_L OFS_AESADIN +#define OFS_AESADIN_H OFS_AESADIN+1 +#define OFS_AESADOUT (0x000Au) /* AES accelerator data out register */ +#define OFS_AESADOUT_L OFS_AESADOUT +#define OFS_AESADOUT_H OFS_AESADOUT+1 + +/* AESACTL0 Control Bits */ +#define AESOP0 (0x0001u) /* AES Operation Bit: 0 */ +#define AESOP1 (0x0002u) /* AES Operation Bit: 1 */ +#define AESSWRST (0x0080u) /* AES Software Reset */ +#define AESRDYIFG (0x0100u) /* AES ready interrupt flag */ +#define AESERRFG (0x0800u) /* AES Error Flag */ +#define AESRDYIE (0x1000u) /* AES ready interrupt enable*/ + +/* AESACTL0 Control Bits */ +#define AESOP0_L (0x0001u) /* AES Operation Bit: 0 */ +#define AESOP1_L (0x0002u) /* AES Operation Bit: 1 */ +#define AESSWRST_L (0x0080u) /* AES Software Reset */ + +/* AESACTL0 Control Bits */ +#define AESRDYIFG_H (0x0001u) /* AES ready interrupt flag */ +#define AESERRFG_H (0x0008u) /* AES Error Flag */ +#define AESRDYIE_H (0x0010u) /* AES ready interrupt enable*/ + +#define AESOP_0 (0x0000u) /* AES Operation: Encrypt */ +#define AESOP_1 (0x0001u) /* AES Operation: Decrypt (same Key) */ +#define AESOP_2 (0x0002u) /* AES Operation: Decrypt (frist round Key) */ +#define AESOP_3 (0x0003u) /* AES Operation: Generate first round Key */ + +/* AESASTAT Control Bits */ +#define AESBUSY (0x0001u) /* AES Busy */ +#define AESKEYWR (0x0002u) /* AES All 16 bytes written to AESAKEY */ +#define AESDINWR (0x0004u) /* AES All 16 bytes written to AESADIN */ +#define AESDOUTRD (0x0008u) /* AES All 16 bytes read from AESADOUT */ +#define AESKEYCNT0 (0x0010u) /* AES Bytes written via AESAKEY Bit: 0 */ +#define AESKEYCNT1 (0x0020u) /* AES Bytes written via AESAKEY Bit: 1 */ +#define AESKEYCNT2 (0x0040u) /* AES Bytes written via AESAKEY Bit: 2 */ +#define AESKEYCNT3 (0x0080u) /* AES Bytes written via AESAKEY Bit: 3 */ +#define AESDINCNT0 (0x0100u) /* AES Bytes written via AESADIN Bit: 0 */ +#define AESDINCNT1 (0x0200u) /* AES Bytes written via AESADIN Bit: 1 */ +#define AESDINCNT2 (0x0400u) /* AES Bytes written via AESADIN Bit: 2 */ +#define AESDINCNT3 (0x0800u) /* AES Bytes written via AESADIN Bit: 3 */ +#define AESDOUTCNT0 (0x1000u) /* AES Bytes read via AESADOUT Bit: 0 */ +#define AESDOUTCNT1 (0x2000u) /* AES Bytes read via AESADOUT Bit: 1 */ +#define AESDOUTCNT2 (0x4000u) /* AES Bytes read via AESADOUT Bit: 2 */ +#define AESDOUTCNT3 (0x8000u) /* AES Bytes read via AESADOUT Bit: 3 */ + +/* AESASTAT Control Bits */ +#define AESBUSY_L (0x0001u) /* AES Busy */ +#define AESKEYWR_L (0x0002u) /* AES All 16 bytes written to AESAKEY */ +#define AESDINWR_L (0x0004u) /* AES All 16 bytes written to AESADIN */ +#define AESDOUTRD_L (0x0008u) /* AES All 16 bytes read from AESADOUT */ +#define AESKEYCNT0_L (0x0010u) /* AES Bytes written via AESAKEY Bit: 0 */ +#define AESKEYCNT1_L (0x0020u) /* AES Bytes written via AESAKEY Bit: 1 */ +#define AESKEYCNT2_L (0x0040u) /* AES Bytes written via AESAKEY Bit: 2 */ +#define AESKEYCNT3_L (0x0080u) /* AES Bytes written via AESAKEY Bit: 3 */ + +/* AESASTAT Control Bits */ +#define AESDINCNT0_H (0x0001u) /* AES Bytes written via AESADIN Bit: 0 */ +#define AESDINCNT1_H (0x0002u) /* AES Bytes written via AESADIN Bit: 1 */ +#define AESDINCNT2_H (0x0004u) /* AES Bytes written via AESADIN Bit: 2 */ +#define AESDINCNT3_H (0x0008u) /* AES Bytes written via AESADIN Bit: 3 */ +#define AESDOUTCNT0_H (0x0010u) /* AES Bytes read via AESADOUT Bit: 0 */ +#define AESDOUTCNT1_H (0x0020u) /* AES Bytes read via AESADOUT Bit: 1 */ +#define AESDOUTCNT2_H (0x0040u) /* AES Bytes read via AESADOUT Bit: 2 */ +#define AESDOUTCNT3_H (0x0080u) /* AES Bytes read via AESADOUT Bit: 3 */ + +#endif +/************************************************************* +* Backup RAM Module +*************************************************************/ +#ifdef __MSP430_HAS_BACKUP_RAM__ /* Definition to show that Module is available */ + +#define OFS_BAKMEM0 (0x0000u) /* Battery Backup Memory 0 */ +#define OFS_BAKMEM0_L OFS_BAKMEM0 +#define OFS_BAKMEM0_H OFS_BAKMEM0+1 +#define OFS_BAKMEM1 (0x0002u) /* Battery Backup Memory 1 */ +#define OFS_BAKMEM1_L OFS_BAKMEM1 +#define OFS_BAKMEM1_H OFS_BAKMEM1+1 +#define OFS_BAKMEM2 (0x0004u) /* Battery Backup Memory 2 */ +#define OFS_BAKMEM2_L OFS_BAKMEM2 +#define OFS_BAKMEM2_H OFS_BAKMEM2+1 +#define OFS_BAKMEM3 (0x0006u) /* Battery Backup Memory 3 */ +#define OFS_BAKMEM3_L OFS_BAKMEM3 +#define OFS_BAKMEM3_H OFS_BAKMEM3+1 + +#endif +/************************************************************* +* Battery Charger Module +*************************************************************/ +#ifdef __MSP430_HAS_BATTERY_CHARGER__ /* Definition to show that Module is available */ + +#define OFS_BAKCTL (0x0000u) /* Battery Backup Control */ +#define OFS_BAKCTL_L OFS_BAKCTL +#define OFS_BAKCTL_H OFS_BAKCTL+1 +#define OFS_BAKCHCTL (0x0002u) /* Battery Charger Control */ +#define OFS_BAKCHCTL_L OFS_BAKCHCTL +#define OFS_BAKCHCTL_H OFS_BAKCHCTL+1 + +/* BAKCTL Control Bits */ +#define LOCKBAK (0x0001u) /* Lock backup sub-system */ +#define BAKSW (0x0002u) /* Manual switch to battery backup supply */ +#define BAKADC (0x0004u) /* Battery backup supply to ADC. */ +#define BAKDIS (0x0008u) /* Disable backup supply switching. */ + +/* BAKCTL Control Bits */ +#define LOCKBAK_L (0x0001u) /* Lock backup sub-system */ +#define BAKSW_L (0x0002u) /* Manual switch to battery backup supply */ +#define BAKADC_L (0x0004u) /* Battery backup supply to ADC. */ +#define BAKDIS_L (0x0008u) /* Disable backup supply switching. */ + +/* BAKCHCTL Control Bits */ +#define CHEN (0x0001u) /* Charger enable */ +#define CHC0 (0x0002u) /* Charger charge current Bit 0 */ +#define CHC1 (0x0004u) /* Charger charge current Bit 1 */ +#define CHV0 (0x0010u) /* Charger end voltage Bit 0 */ +#define CHV1 (0x0020u) /* Charger end voltage Bit 1 */ + +/* BAKCHCTL Control Bits */ +#define CHEN_L (0x0001u) /* Charger enable */ +#define CHC0_L (0x0002u) /* Charger charge current Bit 0 */ +#define CHC1_L (0x0004u) /* Charger charge current Bit 1 */ +#define CHV0_L (0x0010u) /* Charger end voltage Bit 0 */ +#define CHV1_L (0x0020u) /* Charger end voltage Bit 1 */ + +#define CHPWD (0x6900u) /* Charger write password. */ + +#endif +/************************************************************ +* Comparator B +************************************************************/ +#ifdef __MSP430_HAS_COMPB__ /* Definition to show that Module is available */ + +#define OFS_CBCTL0 (0x0000u) /* Comparator B Control Register 0 */ +#define OFS_CBCTL0_L OFS_CBCTL0 +#define OFS_CBCTL0_H OFS_CBCTL0+1 +#define OFS_CBCTL1 (0x0002u) /* Comparator B Control Register 1 */ +#define OFS_CBCTL1_L OFS_CBCTL1 +#define OFS_CBCTL1_H OFS_CBCTL1+1 +#define OFS_CBCTL2 (0x0004u) /* Comparator B Control Register 2 */ +#define OFS_CBCTL2_L OFS_CBCTL2 +#define OFS_CBCTL2_H OFS_CBCTL2+1 +#define OFS_CBCTL3 (0x0006u) /* Comparator B Control Register 3 */ +#define OFS_CBCTL3_L OFS_CBCTL3 +#define OFS_CBCTL3_H OFS_CBCTL3+1 +#define OFS_CBINT (0x000Cu) /* Comparator B Interrupt Register */ +#define OFS_CBINT_L OFS_CBINT +#define OFS_CBINT_H OFS_CBINT+1 +#define OFS_CBIV (0x000Eu) /* Comparator B Interrupt Vector Word */ + +/* CBCTL0 Control Bits */ +#define CBIPSEL0 (0x0001u) /* Comp. B Pos. Channel Input Select 0 */ +#define CBIPSEL1 (0x0002u) /* Comp. B Pos. Channel Input Select 1 */ +#define CBIPSEL2 (0x0004u) /* Comp. B Pos. Channel Input Select 2 */ +#define CBIPSEL3 (0x0008u) /* Comp. B Pos. Channel Input Select 3 */ +//#define RESERVED (0x0010u) /* Comp. B */ +//#define RESERVED (0x0020u) /* Comp. B */ +//#define RESERVED (0x0040u) /* Comp. B */ +#define CBIPEN (0x0080u) /* Comp. B Pos. Channel Input Enable */ +#define CBIMSEL0 (0x0100u) /* Comp. B Neg. Channel Input Select 0 */ +#define CBIMSEL1 (0x0200u) /* Comp. B Neg. Channel Input Select 1 */ +#define CBIMSEL2 (0x0400u) /* Comp. B Neg. Channel Input Select 2 */ +#define CBIMSEL3 (0x0800u) /* Comp. B Neg. Channel Input Select 3 */ +//#define RESERVED (0x1000u) /* Comp. B */ +//#define RESERVED (0x2000u) /* Comp. B */ +//#define RESERVED (0x4000u) /* Comp. B */ +#define CBIMEN (0x8000u) /* Comp. B Neg. Channel Input Enable */ + +/* CBCTL0 Control Bits */ +#define CBIPSEL0_L (0x0001u) /* Comp. B Pos. Channel Input Select 0 */ +#define CBIPSEL1_L (0x0002u) /* Comp. B Pos. Channel Input Select 1 */ +#define CBIPSEL2_L (0x0004u) /* Comp. B Pos. Channel Input Select 2 */ +#define CBIPSEL3_L (0x0008u) /* Comp. B Pos. Channel Input Select 3 */ +//#define RESERVED (0x0010u) /* Comp. B */ +//#define RESERVED (0x0020u) /* Comp. B */ +//#define RESERVED (0x0040u) /* Comp. B */ +#define CBIPEN_L (0x0080u) /* Comp. B Pos. Channel Input Enable */ +//#define RESERVED (0x1000u) /* Comp. B */ +//#define RESERVED (0x2000u) /* Comp. B */ +//#define RESERVED (0x4000u) /* Comp. B */ + +/* CBCTL0 Control Bits */ +//#define RESERVED (0x0010u) /* Comp. B */ +//#define RESERVED (0x0020u) /* Comp. B */ +//#define RESERVED (0x0040u) /* Comp. B */ +#define CBIMSEL0_H (0x0001u) /* Comp. B Neg. Channel Input Select 0 */ +#define CBIMSEL1_H (0x0002u) /* Comp. B Neg. Channel Input Select 1 */ +#define CBIMSEL2_H (0x0004u) /* Comp. B Neg. Channel Input Select 2 */ +#define CBIMSEL3_H (0x0008u) /* Comp. B Neg. Channel Input Select 3 */ +//#define RESERVED (0x1000u) /* Comp. B */ +//#define RESERVED (0x2000u) /* Comp. B */ +//#define RESERVED (0x4000u) /* Comp. B */ +#define CBIMEN_H (0x0080u) /* Comp. B Neg. Channel Input Enable */ + +#define CBIPSEL_0 (0x0000u) /* Comp. B V+ terminal Input Select: Channel 0 */ +#define CBIPSEL_1 (0x0001u) /* Comp. B V+ terminal Input Select: Channel 1 */ +#define CBIPSEL_2 (0x0002u) /* Comp. B V+ terminal Input Select: Channel 2 */ +#define CBIPSEL_3 (0x0003u) /* Comp. B V+ terminal Input Select: Channel 3 */ +#define CBIPSEL_4 (0x0004u) /* Comp. B V+ terminal Input Select: Channel 4 */ +#define CBIPSEL_5 (0x0005u) /* Comp. B V+ terminal Input Select: Channel 5 */ +#define CBIPSEL_6 (0x0006u) /* Comp. B V+ terminal Input Select: Channel 6 */ +#define CBIPSEL_7 (0x0007u) /* Comp. B V+ terminal Input Select: Channel 7 */ +#define CBIPSEL_8 (0x0008u) /* Comp. B V+ terminal Input Select: Channel 8 */ +#define CBIPSEL_9 (0x0009u) /* Comp. B V+ terminal Input Select: Channel 9 */ +#define CBIPSEL_10 (0x000Au) /* Comp. B V+ terminal Input Select: Channel 10 */ +#define CBIPSEL_11 (0x000Bu) /* Comp. B V+ terminal Input Select: Channel 11 */ +#define CBIPSEL_12 (0x000Cu) /* Comp. B V+ terminal Input Select: Channel 12 */ +#define CBIPSEL_13 (0x000Du) /* Comp. B V+ terminal Input Select: Channel 13 */ +#define CBIPSEL_14 (0x000Eu) /* Comp. B V+ terminal Input Select: Channel 14 */ +#define CBIPSEL_15 (0x000Fu) /* Comp. B V+ terminal Input Select: Channel 15 */ + +#define CBIMSEL_0 (0x0000u) /* Comp. B V- Terminal Input Select: Channel 0 */ +#define CBIMSEL_1 (0x0100u) /* Comp. B V- Terminal Input Select: Channel 1 */ +#define CBIMSEL_2 (0x0200u) /* Comp. B V- Terminal Input Select: Channel 2 */ +#define CBIMSEL_3 (0x0300u) /* Comp. B V- Terminal Input Select: Channel 3 */ +#define CBIMSEL_4 (0x0400u) /* Comp. B V- Terminal Input Select: Channel 4 */ +#define CBIMSEL_5 (0x0500u) /* Comp. B V- Terminal Input Select: Channel 5 */ +#define CBIMSEL_6 (0x0600u) /* Comp. B V- Terminal Input Select: Channel 6 */ +#define CBIMSEL_7 (0x0700u) /* Comp. B V- Terminal Input Select: Channel 7 */ +#define CBIMSEL_8 (0x0800u) /* Comp. B V- terminal Input Select: Channel 8 */ +#define CBIMSEL_9 (0x0900u) /* Comp. B V- terminal Input Select: Channel 9 */ +#define CBIMSEL_10 (0x0A00u) /* Comp. B V- terminal Input Select: Channel 10 */ +#define CBIMSEL_11 (0x0B00u) /* Comp. B V- terminal Input Select: Channel 11 */ +#define CBIMSEL_12 (0x0C00u) /* Comp. B V- terminal Input Select: Channel 12 */ +#define CBIMSEL_13 (0x0D00u) /* Comp. B V- terminal Input Select: Channel 13 */ +#define CBIMSEL_14 (0x0E00u) /* Comp. B V- terminal Input Select: Channel 14 */ +#define CBIMSEL_15 (0x0F00u) /* Comp. B V- terminal Input Select: Channel 15 */ + +/* CBCTL1 Control Bits */ +#define CBOUT (0x0001u) /* Comp. B Output */ +#define CBOUTPOL (0x0002u) /* Comp. B Output Polarity */ +#define CBF (0x0004u) /* Comp. B Enable Output Filter */ +#define CBIES (0x0008u) /* Comp. B Interrupt Edge Select */ +#define CBSHORT (0x0010u) /* Comp. B Input Short */ +#define CBEX (0x0020u) /* Comp. B Exchange Inputs */ +#define CBFDLY0 (0x0040u) /* Comp. B Filter delay Bit 0 */ +#define CBFDLY1 (0x0080u) /* Comp. B Filter delay Bit 1 */ +#define CBPWRMD0 (0x0100u) /* Comp. B Power Mode Bit 0 */ +#define CBPWRMD1 (0x0200u) /* Comp. B Power Mode Bit 1 */ +#define CBON (0x0400u) /* Comp. B enable */ +#define CBMRVL (0x0800u) /* Comp. B CBMRV Level */ +#define CBMRVS (0x1000u) /* Comp. B Output selects between VREF0 or VREF1*/ +//#define RESERVED (0x2000u) /* Comp. B */ +//#define RESERVED (0x4000u) /* Comp. B */ +//#define RESERVED (0x8000u) /* Comp. B */ + +/* CBCTL1 Control Bits */ +#define CBOUT_L (0x0001u) /* Comp. B Output */ +#define CBOUTPOL_L (0x0002u) /* Comp. B Output Polarity */ +#define CBF_L (0x0004u) /* Comp. B Enable Output Filter */ +#define CBIES_L (0x0008u) /* Comp. B Interrupt Edge Select */ +#define CBSHORT_L (0x0010u) /* Comp. B Input Short */ +#define CBEX_L (0x0020u) /* Comp. B Exchange Inputs */ +#define CBFDLY0_L (0x0040u) /* Comp. B Filter delay Bit 0 */ +#define CBFDLY1_L (0x0080u) /* Comp. B Filter delay Bit 1 */ +//#define RESERVED (0x2000u) /* Comp. B */ +//#define RESERVED (0x4000u) /* Comp. B */ +//#define RESERVED (0x8000u) /* Comp. B */ + +/* CBCTL1 Control Bits */ +#define CBPWRMD0_H (0x0001u) /* Comp. B Power Mode Bit 0 */ +#define CBPWRMD1_H (0x0002u) /* Comp. B Power Mode Bit 1 */ +#define CBON_H (0x0004u) /* Comp. B enable */ +#define CBMRVL_H (0x0008u) /* Comp. B CBMRV Level */ +#define CBMRVS_H (0x0010u) /* Comp. B Output selects between VREF0 or VREF1*/ +//#define RESERVED (0x2000u) /* Comp. B */ +//#define RESERVED (0x4000u) /* Comp. B */ +//#define RESERVED (0x8000u) /* Comp. B */ + +#define CBFDLY_0 (0x0000u) /* Comp. B Filter delay 0 : 450ns */ +#define CBFDLY_1 (0x0040u) /* Comp. B Filter delay 1 : 900ns */ +#define CBFDLY_2 (0x0080u) /* Comp. B Filter delay 2 : 1800ns */ +#define CBFDLY_3 (0x00C0u) /* Comp. B Filter delay 3 : 3600ns */ + +#define CBPWRMD_0 (0x0000u) /* Comp. B Power Mode 0 : High speed */ +#define CBPWRMD_1 (0x0100u) /* Comp. B Power Mode 1 : Normal */ +#define CBPWRMD_2 (0x0200u) /* Comp. B Power Mode 2 : Ultra-Low*/ +#define CBPWRMD_3 (0x0300u) /* Comp. B Power Mode 3 : Reserved */ + +/* CBCTL2 Control Bits */ +#define CBREF00 (0x0001u) /* Comp. B Reference 0 Resistor Select Bit : 0 */ +#define CBREF01 (0x0002u) /* Comp. B Reference 0 Resistor Select Bit : 1 */ +#define CBREF02 (0x0004u) /* Comp. B Reference 0 Resistor Select Bit : 2 */ +#define CBREF03 (0x0008u) /* Comp. B Reference 0 Resistor Select Bit : 3 */ +#define CBREF04 (0x0010u) /* Comp. B Reference 0 Resistor Select Bit : 4 */ +#define CBRSEL (0x0020u) /* Comp. B Reference select */ +#define CBRS0 (0x0040u) /* Comp. B Reference Source Bit : 0 */ +#define CBRS1 (0x0080u) /* Comp. B Reference Source Bit : 1 */ +#define CBREF10 (0x0100u) /* Comp. B Reference 1 Resistor Select Bit : 0 */ +#define CBREF11 (0x0200u) /* Comp. B Reference 1 Resistor Select Bit : 1 */ +#define CBREF12 (0x0400u) /* Comp. B Reference 1 Resistor Select Bit : 2 */ +#define CBREF13 (0x0800u) /* Comp. B Reference 1 Resistor Select Bit : 3 */ +#define CBREF14 (0x1000u) /* Comp. B Reference 1 Resistor Select Bit : 4 */ +#define CBREFL0 (0x2000u) /* Comp. B Reference voltage level Bit : 0 */ +#define CBREFL1 (0x4000u) /* Comp. B Reference voltage level Bit : 1 */ +#define CBREFACC (0x8000u) /* Comp. B Reference Accuracy */ + +/* CBCTL2 Control Bits */ +#define CBREF00_L (0x0001u) /* Comp. B Reference 0 Resistor Select Bit : 0 */ +#define CBREF01_L (0x0002u) /* Comp. B Reference 0 Resistor Select Bit : 1 */ +#define CBREF02_L (0x0004u) /* Comp. B Reference 0 Resistor Select Bit : 2 */ +#define CBREF03_L (0x0008u) /* Comp. B Reference 0 Resistor Select Bit : 3 */ +#define CBREF04_L (0x0010u) /* Comp. B Reference 0 Resistor Select Bit : 4 */ +#define CBRSEL_L (0x0020u) /* Comp. B Reference select */ +#define CBRS0_L (0x0040u) /* Comp. B Reference Source Bit : 0 */ +#define CBRS1_L (0x0080u) /* Comp. B Reference Source Bit : 1 */ + +/* CBCTL2 Control Bits */ +#define CBREF10_H (0x0001u) /* Comp. B Reference 1 Resistor Select Bit : 0 */ +#define CBREF11_H (0x0002u) /* Comp. B Reference 1 Resistor Select Bit : 1 */ +#define CBREF12_H (0x0004u) /* Comp. B Reference 1 Resistor Select Bit : 2 */ +#define CBREF13_H (0x0008u) /* Comp. B Reference 1 Resistor Select Bit : 3 */ +#define CBREF14_H (0x0010u) /* Comp. B Reference 1 Resistor Select Bit : 4 */ +#define CBREFL0_H (0x0020u) /* Comp. B Reference voltage level Bit : 0 */ +#define CBREFL1_H (0x0040u) /* Comp. B Reference voltage level Bit : 1 */ +#define CBREFACC_H (0x0080u) /* Comp. B Reference Accuracy */ + +#define CBREF0_0 (0x0000u) /* Comp. B Int. Ref.0 Select 0 : 1/32 */ +#define CBREF0_1 (0x0001u) /* Comp. B Int. Ref.0 Select 1 : 2/32 */ +#define CBREF0_2 (0x0002u) /* Comp. B Int. Ref.0 Select 2 : 3/32 */ +#define CBREF0_3 (0x0003u) /* Comp. B Int. Ref.0 Select 3 : 4/32 */ +#define CBREF0_4 (0x0004u) /* Comp. B Int. Ref.0 Select 4 : 5/32 */ +#define CBREF0_5 (0x0005u) /* Comp. B Int. Ref.0 Select 5 : 6/32 */ +#define CBREF0_6 (0x0006u) /* Comp. B Int. Ref.0 Select 6 : 7/32 */ +#define CBREF0_7 (0x0007u) /* Comp. B Int. Ref.0 Select 7 : 8/32 */ +#define CBREF0_8 (0x0008u) /* Comp. B Int. Ref.0 Select 0 : 9/32 */ +#define CBREF0_9 (0x0009u) /* Comp. B Int. Ref.0 Select 1 : 10/32 */ +#define CBREF0_10 (0x000Au) /* Comp. B Int. Ref.0 Select 2 : 11/32 */ +#define CBREF0_11 (0x000Bu) /* Comp. B Int. Ref.0 Select 3 : 12/32 */ +#define CBREF0_12 (0x000Cu) /* Comp. B Int. Ref.0 Select 4 : 13/32 */ +#define CBREF0_13 (0x000Du) /* Comp. B Int. Ref.0 Select 5 : 14/32 */ +#define CBREF0_14 (0x000Eu) /* Comp. B Int. Ref.0 Select 6 : 15/32 */ +#define CBREF0_15 (0x000Fu) /* Comp. B Int. Ref.0 Select 7 : 16/32 */ +#define CBREF0_16 (0x0010u) /* Comp. B Int. Ref.0 Select 0 : 17/32 */ +#define CBREF0_17 (0x0011u) /* Comp. B Int. Ref.0 Select 1 : 18/32 */ +#define CBREF0_18 (0x0012u) /* Comp. B Int. Ref.0 Select 2 : 19/32 */ +#define CBREF0_19 (0x0013u) /* Comp. B Int. Ref.0 Select 3 : 20/32 */ +#define CBREF0_20 (0x0014u) /* Comp. B Int. Ref.0 Select 4 : 21/32 */ +#define CBREF0_21 (0x0015u) /* Comp. B Int. Ref.0 Select 5 : 22/32 */ +#define CBREF0_22 (0x0016u) /* Comp. B Int. Ref.0 Select 6 : 23/32 */ +#define CBREF0_23 (0x0017u) /* Comp. B Int. Ref.0 Select 7 : 24/32 */ +#define CBREF0_24 (0x0018u) /* Comp. B Int. Ref.0 Select 0 : 25/32 */ +#define CBREF0_25 (0x0019u) /* Comp. B Int. Ref.0 Select 1 : 26/32 */ +#define CBREF0_26 (0x001Au) /* Comp. B Int. Ref.0 Select 2 : 27/32 */ +#define CBREF0_27 (0x001Bu) /* Comp. B Int. Ref.0 Select 3 : 28/32 */ +#define CBREF0_28 (0x001Cu) /* Comp. B Int. Ref.0 Select 4 : 29/32 */ +#define CBREF0_29 (0x001Du) /* Comp. B Int. Ref.0 Select 5 : 30/32 */ +#define CBREF0_30 (0x001Eu) /* Comp. B Int. Ref.0 Select 6 : 31/32 */ +#define CBREF0_31 (0x001Fu) /* Comp. B Int. Ref.0 Select 7 : 32/32 */ + +#define CBRS_0 (0x0000u) /* Comp. B Reference Source 0 : Off */ +#define CBRS_1 (0x0040u) /* Comp. B Reference Source 1 : Vcc */ +#define CBRS_2 (0x0080u) /* Comp. B Reference Source 2 : Shared Ref. */ +#define CBRS_3 (0x00C0u) /* Comp. B Reference Source 3 : Shared Ref. / Off */ + +#define CBREF1_0 (0x0000u) /* Comp. B Int. Ref.1 Select 0 : 1/32 */ +#define CBREF1_1 (0x0100u) /* Comp. B Int. Ref.1 Select 1 : 2/32 */ +#define CBREF1_2 (0x0200u) /* Comp. B Int. Ref.1 Select 2 : 3/32 */ +#define CBREF1_3 (0x0300u) /* Comp. B Int. Ref.1 Select 3 : 4/32 */ +#define CBREF1_4 (0x0400u) /* Comp. B Int. Ref.1 Select 4 : 5/32 */ +#define CBREF1_5 (0x0500u) /* Comp. B Int. Ref.1 Select 5 : 6/32 */ +#define CBREF1_6 (0x0600u) /* Comp. B Int. Ref.1 Select 6 : 7/32 */ +#define CBREF1_7 (0x0700u) /* Comp. B Int. Ref.1 Select 7 : 8/32 */ +#define CBREF1_8 (0x0800u) /* Comp. B Int. Ref.1 Select 0 : 9/32 */ +#define CBREF1_9 (0x0900u) /* Comp. B Int. Ref.1 Select 1 : 10/32 */ +#define CBREF1_10 (0x0A00u) /* Comp. B Int. Ref.1 Select 2 : 11/32 */ +#define CBREF1_11 (0x0B00u) /* Comp. B Int. Ref.1 Select 3 : 12/32 */ +#define CBREF1_12 (0x0C00u) /* Comp. B Int. Ref.1 Select 4 : 13/32 */ +#define CBREF1_13 (0x0D00u) /* Comp. B Int. Ref.1 Select 5 : 14/32 */ +#define CBREF1_14 (0x0E00u) /* Comp. B Int. Ref.1 Select 6 : 15/32 */ +#define CBREF1_15 (0x0F00u) /* Comp. B Int. Ref.1 Select 7 : 16/32 */ +#define CBREF1_16 (0x1000u) /* Comp. B Int. Ref.1 Select 0 : 17/32 */ +#define CBREF1_17 (0x1100u) /* Comp. B Int. Ref.1 Select 1 : 18/32 */ +#define CBREF1_18 (0x1200u) /* Comp. B Int. Ref.1 Select 2 : 19/32 */ +#define CBREF1_19 (0x1300u) /* Comp. B Int. Ref.1 Select 3 : 20/32 */ +#define CBREF1_20 (0x1400u) /* Comp. B Int. Ref.1 Select 4 : 21/32 */ +#define CBREF1_21 (0x1500u) /* Comp. B Int. Ref.1 Select 5 : 22/32 */ +#define CBREF1_22 (0x1600u) /* Comp. B Int. Ref.1 Select 6 : 23/32 */ +#define CBREF1_23 (0x1700u) /* Comp. B Int. Ref.1 Select 7 : 24/32 */ +#define CBREF1_24 (0x1800u) /* Comp. B Int. Ref.1 Select 0 : 25/32 */ +#define CBREF1_25 (0x1900u) /* Comp. B Int. Ref.1 Select 1 : 26/32 */ +#define CBREF1_26 (0x1A00u) /* Comp. B Int. Ref.1 Select 2 : 27/32 */ +#define CBREF1_27 (0x1B00u) /* Comp. B Int. Ref.1 Select 3 : 28/32 */ +#define CBREF1_28 (0x1C00u) /* Comp. B Int. Ref.1 Select 4 : 29/32 */ +#define CBREF1_29 (0x1D00u) /* Comp. B Int. Ref.1 Select 5 : 30/32 */ +#define CBREF1_30 (0x1E00u) /* Comp. B Int. Ref.1 Select 6 : 31/32 */ +#define CBREF1_31 (0x1F00u) /* Comp. B Int. Ref.1 Select 7 : 32/32 */ + +#define CBREFL_0 (0x0000u) /* Comp. B Reference voltage level 0 : None */ +#define CBREFL_1 (0x2000u) /* Comp. B Reference voltage level 1 : 1.5V */ +#define CBREFL_2 (0x4000u) /* Comp. B Reference voltage level 2 : 2.0V */ +#define CBREFL_3 (0x6000u) /* Comp. B Reference voltage level 3 : 2.5V */ + +#define CBPD0 (0x0001u) /* Comp. B Disable Input Buffer of Port Register .0 */ +#define CBPD1 (0x0002u) /* Comp. B Disable Input Buffer of Port Register .1 */ +#define CBPD2 (0x0004u) /* Comp. B Disable Input Buffer of Port Register .2 */ +#define CBPD3 (0x0008u) /* Comp. B Disable Input Buffer of Port Register .3 */ +#define CBPD4 (0x0010u) /* Comp. B Disable Input Buffer of Port Register .4 */ +#define CBPD5 (0x0020u) /* Comp. B Disable Input Buffer of Port Register .5 */ +#define CBPD6 (0x0040u) /* Comp. B Disable Input Buffer of Port Register .6 */ +#define CBPD7 (0x0080u) /* Comp. B Disable Input Buffer of Port Register .7 */ +#define CBPD8 (0x0100u) /* Comp. B Disable Input Buffer of Port Register .8 */ +#define CBPD9 (0x0200u) /* Comp. B Disable Input Buffer of Port Register .9 */ +#define CBPD10 (0x0400u) /* Comp. B Disable Input Buffer of Port Register .10 */ +#define CBPD11 (0x0800u) /* Comp. B Disable Input Buffer of Port Register .11 */ +#define CBPD12 (0x1000u) /* Comp. B Disable Input Buffer of Port Register .12 */ +#define CBPD13 (0x2000u) /* Comp. B Disable Input Buffer of Port Register .13 */ +#define CBPD14 (0x4000u) /* Comp. B Disable Input Buffer of Port Register .14 */ +#define CBPD15 (0x8000u) /* Comp. B Disable Input Buffer of Port Register .15 */ + +#define CBPD0_L (0x0001u) /* Comp. B Disable Input Buffer of Port Register .0 */ +#define CBPD1_L (0x0002u) /* Comp. B Disable Input Buffer of Port Register .1 */ +#define CBPD2_L (0x0004u) /* Comp. B Disable Input Buffer of Port Register .2 */ +#define CBPD3_L (0x0008u) /* Comp. B Disable Input Buffer of Port Register .3 */ +#define CBPD4_L (0x0010u) /* Comp. B Disable Input Buffer of Port Register .4 */ +#define CBPD5_L (0x0020u) /* Comp. B Disable Input Buffer of Port Register .5 */ +#define CBPD6_L (0x0040u) /* Comp. B Disable Input Buffer of Port Register .6 */ +#define CBPD7_L (0x0080u) /* Comp. B Disable Input Buffer of Port Register .7 */ + +#define CBPD8_H (0x0001u) /* Comp. B Disable Input Buffer of Port Register .8 */ +#define CBPD9_H (0x0002u) /* Comp. B Disable Input Buffer of Port Register .9 */ +#define CBPD10_H (0x0004u) /* Comp. B Disable Input Buffer of Port Register .10 */ +#define CBPD11_H (0x0008u) /* Comp. B Disable Input Buffer of Port Register .11 */ +#define CBPD12_H (0x0010u) /* Comp. B Disable Input Buffer of Port Register .12 */ +#define CBPD13_H (0x0020u) /* Comp. B Disable Input Buffer of Port Register .13 */ +#define CBPD14_H (0x0040u) /* Comp. B Disable Input Buffer of Port Register .14 */ +#define CBPD15_H (0x0080u) /* Comp. B Disable Input Buffer of Port Register .15 */ + +/* CBINT Control Bits */ +#define CBIFG (0x0001u) /* Comp. B Interrupt Flag */ +#define CBIIFG (0x0002u) /* Comp. B Interrupt Flag Inverted Polarity */ +//#define RESERVED (0x0004u) /* Comp. B */ +//#define RESERVED (0x0008u) /* Comp. B */ +//#define RESERVED (0x0010u) /* Comp. B */ +//#define RESERVED (0x0020u) /* Comp. B */ +//#define RESERVED (0x0040u) /* Comp. B */ +//#define RESERVED (0x0080u) /* Comp. B */ +#define CBIE (0x0100u) /* Comp. B Interrupt Enable */ +#define CBIIE (0x0200u) /* Comp. B Interrupt Enable Inverted Polarity */ +//#define RESERVED (0x0400u) /* Comp. B */ +//#define RESERVED (0x0800u) /* Comp. B */ +//#define RESERVED (0x1000u) /* Comp. B */ +//#define RESERVED (0x2000u) /* Comp. B */ +//#define RESERVED (0x4000u) /* Comp. B */ +//#define RESERVED (0x8000u) /* Comp. B */ + +/* CBINT Control Bits */ +#define CBIFG_L (0x0001u) /* Comp. B Interrupt Flag */ +#define CBIIFG_L (0x0002u) /* Comp. B Interrupt Flag Inverted Polarity */ +//#define RESERVED (0x0004u) /* Comp. B */ +//#define RESERVED (0x0008u) /* Comp. B */ +//#define RESERVED (0x0010u) /* Comp. B */ +//#define RESERVED (0x0020u) /* Comp. B */ +//#define RESERVED (0x0040u) /* Comp. B */ +//#define RESERVED (0x0080u) /* Comp. B */ +//#define RESERVED (0x0400u) /* Comp. B */ +//#define RESERVED (0x0800u) /* Comp. B */ +//#define RESERVED (0x1000u) /* Comp. B */ +//#define RESERVED (0x2000u) /* Comp. B */ +//#define RESERVED (0x4000u) /* Comp. B */ +//#define RESERVED (0x8000u) /* Comp. B */ + +/* CBINT Control Bits */ +//#define RESERVED (0x0004u) /* Comp. B */ +//#define RESERVED (0x0008u) /* Comp. B */ +//#define RESERVED (0x0010u) /* Comp. B */ +//#define RESERVED (0x0020u) /* Comp. B */ +//#define RESERVED (0x0040u) /* Comp. B */ +//#define RESERVED (0x0080u) /* Comp. B */ +#define CBIE_H (0x0001u) /* Comp. B Interrupt Enable */ +#define CBIIE_H (0x0002u) /* Comp. B Interrupt Enable Inverted Polarity */ +//#define RESERVED (0x0400u) /* Comp. B */ +//#define RESERVED (0x0800u) /* Comp. B */ +//#define RESERVED (0x1000u) /* Comp. B */ +//#define RESERVED (0x2000u) /* Comp. B */ +//#define RESERVED (0x4000u) /* Comp. B */ +//#define RESERVED (0x8000u) /* Comp. B */ + +/* CBIV Definitions */ +#define CBIV_NONE (0x0000u) /* No Interrupt pending */ +#define CBIV_CBIFG (0x0002u) /* CBIFG */ +#define CBIV_CBIIFG (0x0004u) /* CBIIFG */ + +#endif +/************************************************************ +* CC1101 Radio Interface +************************************************************/ +#ifdef __MSP430_HAS_CC1101__ /* Definition to show that Module is available */ + +#define OFS_RF1AIFCTL0 (0x0000u) /* Radio interface control register 0 */ +#define OFS_RF1AIFCTL0_L OFS_RF1AIFCTL0 +#define OFS_RF1AIFCTL0_H OFS_RF1AIFCTL0+1 +#define OFS_RF1AIFCTL1 (0x0002u) /* Radio interface control register 1 */ +#define OFS_RF1AIFCTL1_L OFS_RF1AIFCTL1 +#define OFS_RF1AIFCTL1_H OFS_RF1AIFCTL1+1 +#define RF1AIFIFG RF1AIFCTL1_L /* Radio interface interrupt flag register */ +#define RF1AIFIE RF1AIFCTL1_H /* Radio interface interrupt enable register */ +#define OFS_RF1AIFCTL2 (0x0004u) /* (Radio interface control register 2) */ +#define OFS_RF1AIFCTL2_L OFS_RF1AIFCTL2 +#define OFS_RF1AIFCTL2_H OFS_RF1AIFCTL2+1 +#define OFS_RF1AIFERR (0x0006u) /* Radio interface error flag register */ +#define OFS_RF1AIFERR_L OFS_RF1AIFERR +#define OFS_RF1AIFERR_H OFS_RF1AIFERR+1 +#define OFS_RF1AIFERRV (0x000Cu) /* Radio interface error vector word register */ +#define OFS_RF1AIFERRV_L OFS_RF1AIFERRV +#define OFS_RF1AIFERRV_H OFS_RF1AIFERRV+1 +#define OFS_RF1AIFIV (0x000Eu) /* Radio interface interrupt vector word register */ +#define OFS_RF1AIFIV_L OFS_RF1AIFIV +#define OFS_RF1AIFIV_H OFS_RF1AIFIV+1 +#define OFS_RF1AINSTRW (0x0010u) /* Radio instruction word register */ +#define OFS_RF1AINSTRW_L OFS_RF1AINSTRW +#define OFS_RF1AINSTRW_H OFS_RF1AINSTRW+1 +#define RF1ADINB RF1AINSTRW_L /* Radio instruction byte register */ +#define RF1AINSTRB RF1AINSTRW_H /* Radio byte data in register */ +#define OFS_RF1AINSTR1W (0x0012u) /* Radio instruction 1-byte register with autoread */ +#define OFS_RF1AINSTR1W_L OFS_RF1AINSTR1W +#define OFS_RF1AINSTR1W_H OFS_RF1AINSTR1W+1 +#define RF1AINSTR1B RF1AINSTR1W_H /* Radio instruction 1-byte register with autoread */ +#define OFS_RF1AINSTR2W (0x0014u) /* Radio instruction 2-byte register with autoread */ +#define OFS_RF1AINSTR2W_L OFS_RF1AINSTR2W +#define OFS_RF1AINSTR2W_H OFS_RF1AINSTR2W+1 +#define RF1AINSTR2B RF1AINSTR1W_H /* Radio instruction 2-byte register with autoread */ +#define OFS_RF1ADINW (0x0016u) /* Radio word data in register */ +#define OFS_RF1ADINW_L OFS_RF1ADINW +#define OFS_RF1ADINW_H OFS_RF1ADINW+1 + +#define OFS_RF1ASTAT0W (0x0020u) /* Radio status word register without auto-read */ +#define OFS_RF1ASTAT0W_L OFS_RF1ASTAT0W +#define OFS_RF1ASTAT0W_H OFS_RF1ASTAT0W+1 +#define RF1ADOUT0B RF1ASTAT0W_L /* Radio byte data out register without auto-read */ +#define RF1ASTAT0B RF1ASTAT0W_H /* Radio status byte register without auto-read */ +#define RF1ASTATW RF1ASTAT0W /* Radio status word register without auto-read */ +#define RF1ADOUTB RF1ASTAT0W_L /* Radio byte data out register without auto-read */ +#define RF1ASTATB RF1ASTAT0W_H /* Radio status byte register without auto-read */ +#define OFS_RF1ASTAT1W (0x0022u) /* Radio status word register with 1-byte auto-read */ +#define OFS_RF1ASTAT1W_L OFS_RF1ASTAT1W +#define OFS_RF1ASTAT1W_H OFS_RF1ASTAT1W+1 +#define RF1ADOUT1B RF1ASTAT1W_L /* Radio byte data out register with 1-byte auto-read */ +#define RF1ASTAT1B RF1ASTAT1W_H /* Radio status byte register with 1-byte auto-read */ +#define OFS_RF1ASTAT2W (0x0024u) /* Radio status word register with 2-byte auto-read */ +#define OFS_RF1ASTAT2W_L OFS_RF1ASTAT2W +#define OFS_RF1ASTAT2W_H OFS_RF1ASTAT2W+1 +#define RF1ADOUT2B RF1ASTAT2W_L /* Radio byte data out register with 2-byte auto-read */ +#define RF1ASTAT2B RF1ASTAT2W_H /* Radio status byte register with 2-byte auto-read */ +#define OFS_RF1ADOUT0W (0x0028u) /* Radio core word data out register without auto-read */ +#define OFS_RF1ADOUT0W_L OFS_RF1ADOUT0W +#define OFS_RF1ADOUT0W_H OFS_RF1ADOUT0W+1 +#define RF1ADOUTW RF1ADOUT0W /* Radio core word data out register without auto-read */ +#define RF1ADOUTW_L RF1ADOUT0W_L /* Radio core word data out register without auto-read */ +#define RF1ADOUTW_H RF1ADOUT0W_H /* Radio core word data out register without auto-read */ +#define OFS_RF1ADOUT1W (0x002Au) /* Radio core word data out register with 1-byte auto-read */ +#define OFS_RF1ADOUT1W_L OFS_RF1ADOUT1W +#define OFS_RF1ADOUT1W_H OFS_RF1ADOUT1W+1 +#define OFS_RF1ADOUT2W (0x002Cu) /* Radio core word data out register with 2-byte auto-read */ +#define OFS_RF1ADOUT2W_L OFS_RF1ADOUT2W +#define OFS_RF1ADOUT2W_H OFS_RF1ADOUT2W+1 +#define OFS_RF1AIN (0x0030u) /* Radio core signal input register */ +#define OFS_RF1AIN_L OFS_RF1AIN +#define OFS_RF1AIN_H OFS_RF1AIN+1 +#define OFS_RF1AIFG (0x0032u) /* Radio core interrupt flag register */ +#define OFS_RF1AIFG_L OFS_RF1AIFG +#define OFS_RF1AIFG_H OFS_RF1AIFG+1 +#define OFS_RF1AIES (0x0034u) /* Radio core interrupt edge select register */ +#define OFS_RF1AIES_L OFS_RF1AIES +#define OFS_RF1AIES_H OFS_RF1AIES+1 +#define OFS_RF1AIE (0x0036u) /* Radio core interrupt enable register */ +#define OFS_RF1AIE_L OFS_RF1AIE +#define OFS_RF1AIE_H OFS_RF1AIE+1 +#define OFS_RF1AIV (0x0038u) /* Radio core interrupt vector word register */ +#define OFS_RF1AIV_L OFS_RF1AIV +#define OFS_RF1AIV_H OFS_RF1AIV+1 +#define OFS_RF1ARXFIFO (0x003Cu) /* Direct receive FIFO access register */ +#define OFS_RF1ARXFIFO_L OFS_RF1ARXFIFO +#define OFS_RF1ARXFIFO_H OFS_RF1ARXFIFO+1 +#define OFS_RF1ATXFIFO (0x003Eu) /* Direct transmit FIFO access register */ +#define OFS_RF1ATXFIFO_L OFS_RF1ATXFIFO +#define OFS_RF1ATXFIFO_H OFS_RF1ATXFIFO+1 + +/* RF1AIFCTL0 Control Bits */ +#define RFFIFOEN (0x0001u) /* CC1101 Direct FIFO access enable */ +#define RFENDIAN (0x0002u) /* CC1101 Disable endianness conversion */ + +/* RF1AIFCTL0 Control Bits */ +#define RFFIFOEN_L (0x0001u) /* CC1101 Direct FIFO access enable */ +#define RFENDIAN_L (0x0002u) /* CC1101 Disable endianness conversion */ + +/* RF1AIFCTL1 Control Bits */ +#define RFRXIFG (0x0001u) /* Radio interface direct FIFO access receive interrupt flag */ +#define RFTXIFG (0x0002u) /* Radio interface direct FIFO access transmit interrupt flag */ +#define RFERRIFG (0x0004u) /* Radio interface error interrupt flag */ +#define RFINSTRIFG (0x0010u) /* Radio interface instruction interrupt flag */ +#define RFDINIFG (0x0020u) /* Radio interface data in interrupt flag */ +#define RFSTATIFG (0x0040u) /* Radio interface status interrupt flag */ +#define RFDOUTIFG (0x0080u) /* Radio interface data out interrupt flag */ +#define RFRXIE (0x0100u) /* Radio interface direct FIFO access receive interrupt enable */ +#define RFTXIE (0x0200u) /* Radio interface direct FIFO access transmit interrupt enable */ +#define RFERRIE (0x0400u) /* Radio interface error interrupt enable */ +#define RFINSTRIE (0x1000u) /* Radio interface instruction interrupt enable */ +#define RFDINIE (0x2000u) /* Radio interface data in interrupt enable */ +#define RFSTATIE (0x4000u) /* Radio interface status interrupt enable */ +#define RFDOUTIE (0x8000u) /* Radio interface data out interrupt enable */ + +/* RF1AIFCTL1 Control Bits */ +#define RFRXIFG_L (0x0001u) /* Radio interface direct FIFO access receive interrupt flag */ +#define RFTXIFG_L (0x0002u) /* Radio interface direct FIFO access transmit interrupt flag */ +#define RFERRIFG_L (0x0004u) /* Radio interface error interrupt flag */ +#define RFINSTRIFG_L (0x0010u) /* Radio interface instruction interrupt flag */ +#define RFDINIFG_L (0x0020u) /* Radio interface data in interrupt flag */ +#define RFSTATIFG_L (0x0040u) /* Radio interface status interrupt flag */ +#define RFDOUTIFG_L (0x0080u) /* Radio interface data out interrupt flag */ + +/* RF1AIFCTL1 Control Bits */ +#define RFRXIE_H (0x0001u) /* Radio interface direct FIFO access receive interrupt enable */ +#define RFTXIE_H (0x0002u) /* Radio interface direct FIFO access transmit interrupt enable */ +#define RFERRIE_H (0x0004u) /* Radio interface error interrupt enable */ +#define RFINSTRIE_H (0x0010u) /* Radio interface instruction interrupt enable */ +#define RFDINIE_H (0x0020u) /* Radio interface data in interrupt enable */ +#define RFSTATIE_H (0x0040u) /* Radio interface status interrupt enable */ +#define RFDOUTIE_H (0x0080u) /* Radio interface data out interrupt enable */ + +/* RF1AIFERR Control Bits */ +#define LVERR (0x0001u) /* Low Core Voltage Error Flag */ +#define OPERR (0x0002u) /* Operand Error Flag */ +#define OUTERR (0x0004u) /* Output data not available Error Flag */ +#define OPOVERR (0x0008u) /* Operand Overwrite Error Flag */ + +/* RF1AIFERR Control Bits */ +#define LVERR_L (0x0001u) /* Low Core Voltage Error Flag */ +#define OPERR_L (0x0002u) /* Operand Error Flag */ +#define OUTERR_L (0x0004u) /* Output data not available Error Flag */ +#define OPOVERR_L (0x0008u) /* Operand Overwrite Error Flag */ + +/* RF1AIFERRV Definitions */ +#define RF1AIFERRV_NONE (0x0000u) /* No Error pending */ +#define RF1AIFERRV_LVERR (0x0002u) /* Low core voltage error */ +#define RF1AIFERRV_OPERR (0x0004u) /* Operand Error */ +#define RF1AIFERRV_OUTERR (0x0006u) /* Output data not available Error */ +#define RF1AIFERRV_OPOVERR (0x0008u) /* Operand Overwrite Error */ + +/* RF1AIFIV Definitions */ +#define RF1AIFIV_NONE (0x0000u) /* No Interrupt pending */ +#define RF1AIFIV_RFERRIFG (0x0002u) /* Radio interface error */ +#define RF1AIFIV_RFDOUTIFG (0x0004u) /* Radio i/f data out */ +#define RF1AIFIV_RFSTATIFG (0x0006u) /* Radio i/f status out */ +#define RF1AIFIV_RFDINIFG (0x0008u) /* Radio i/f data in */ +#define RF1AIFIV_RFINSTRIFG (0x000Au) /* Radio i/f instruction in */ + +/* RF1AIV Definitions */ +#define RF1AIV_NONE (0x0000u) /* No Interrupt pending */ +#define RF1AIV_RFIFG0 (0x0002u) /* RFIFG0 */ +#define RF1AIV_RFIFG1 (0x0004u) /* RFIFG1 */ +#define RF1AIV_RFIFG2 (0x0006u) /* RFIFG2 */ +#define RF1AIV_RFIFG3 (0x0008u) /* RFIFG3 */ +#define RF1AIV_RFIFG4 (0x000Au) /* RFIFG4 */ +#define RF1AIV_RFIFG5 (0x000Cu) /* RFIFG5 */ +#define RF1AIV_RFIFG6 (0x000Eu) /* RFIFG6 */ +#define RF1AIV_RFIFG7 (0x0010u) /* RFIFG7 */ +#define RF1AIV_RFIFG8 (0x0012u) /* RFIFG8 */ +#define RF1AIV_RFIFG9 (0x0014u) /* RFIFG9 */ +#define RF1AIV_RFIFG10 (0x0016u) /* RFIFG10 */ +#define RF1AIV_RFIFG11 (0x0018u) /* RFIFG11 */ +#define RF1AIV_RFIFG12 (0x001Au) /* RFIFG12 */ +#define RF1AIV_RFIFG13 (0x001Cu) /* RFIFG13 */ +#define RF1AIV_RFIFG14 (0x001Eu) /* RFIFG14 */ +#define RF1AIV_RFIFG15 (0x0020u) /* RFIFG15 */ + +// Radio Core Registers +#define IOCFG2 0x00 /* IOCFG2 - GDO2 output pin configuration */ +#define IOCFG1 0x01 /* IOCFG1 - GDO1 output pin configuration */ +#define IOCFG0 0x02 /* IOCFG1 - GDO0 output pin configuration */ +#define FIFOTHR 0x03 /* FIFOTHR - RX FIFO and TX FIFO thresholds */ +#define SYNC1 0x04 /* SYNC1 - Sync word, high byte */ +#define SYNC0 0x05 /* SYNC0 - Sync word, low byte */ +#define PKTLEN 0x06 /* PKTLEN - Packet length */ +#define PKTCTRL1 0x07 /* PKTCTRL1 - Packet automation control */ +#define PKTCTRL0 0x08 /* PKTCTRL0 - Packet automation control */ +#define ADDR 0x09 /* ADDR - Device address */ +#define CHANNR 0x0A /* CHANNR - Channel number */ +#define FSCTRL1 0x0B /* FSCTRL1 - Frequency synthesizer control */ +#define FSCTRL0 0x0C /* FSCTRL0 - Frequency synthesizer control */ +#define FREQ2 0x0D /* FREQ2 - Frequency control word, high byte */ +#define FREQ1 0x0E /* FREQ1 - Frequency control word, middle byte */ +#define FREQ0 0x0F /* FREQ0 - Frequency control word, low byte */ +#define MDMCFG4 0x10 /* MDMCFG4 - Modem configuration */ +#define MDMCFG3 0x11 /* MDMCFG3 - Modem configuration */ +#define MDMCFG2 0x12 /* MDMCFG2 - Modem configuration */ +#define MDMCFG1 0x13 /* MDMCFG1 - Modem configuration */ +#define MDMCFG0 0x14 /* MDMCFG0 - Modem configuration */ +#define DEVIATN 0x15 /* DEVIATN - Modem deviation setting */ +#define MCSM2 0x16 /* MCSM2 - Main Radio Control State Machine configuration */ +#define MCSM1 0x17 /* MCSM1 - Main Radio Control State Machine configuration */ +#define MCSM0 0x18 /* MCSM0 - Main Radio Control State Machine configuration */ +#define FOCCFG 0x19 /* FOCCFG - Frequency Offset Compensation configuration */ +#define BSCFG 0x1A /* BSCFG - Bit Synchronization configuration */ +#define AGCCTRL2 0x1B /* AGCCTRL2 - AGC control */ +#define AGCCTRL1 0x1C /* AGCCTRL1 - AGC control */ +#define AGCCTRL0 0x1D /* AGCCTRL0 - AGC control */ +#define WOREVT1 0x1E /* WOREVT1 - High byte Event0 timeout */ +#define WOREVT0 0x1F /* WOREVT0 - Low byte Event0 timeout */ +#define WORCTRL 0x20 /* WORCTRL - Wake On Radio control */ +#define FREND1 0x21 /* FREND1 - Front end RX configuration */ +#define FREND0 0x22 /* FREDN0 - Front end TX configuration */ +#define FSCAL3 0x23 /* FSCAL3 - Frequency synthesizer calibration */ +#define FSCAL2 0x24 /* FSCAL2 - Frequency synthesizer calibration */ +#define FSCAL1 0x25 /* FSCAL1 - Frequency synthesizer calibration */ +#define FSCAL0 0x26 /* FSCAL0 - Frequency synthesizer calibration */ +//#define RCCTRL1 0x27 /* RCCTRL1 - RC oscillator configuration */ +//#define RCCTRL0 0x28 /* RCCTRL0 - RC oscillator configuration */ +#define FSTEST 0x29 /* FSTEST - Frequency synthesizer calibration control */ +#define PTEST 0x2A /* PTEST - Production test */ +#define AGCTEST 0x2B /* AGCTEST - AGC test */ +#define TEST2 0x2C /* TEST2 - Various test settings */ +#define TEST1 0x2D /* TEST1 - Various test settings */ +#define TEST0 0x2E /* TEST0 - Various test settings */ + +/* status registers */ +#define PARTNUM 0x30 /* PARTNUM - Chip ID */ +#define VERSION 0x31 /* VERSION - Chip ID */ +#define FREQEST 0x32 /* FREQEST – Frequency Offset Estimate from demodulator */ +#define LQI 0x33 /* LQI – Demodulator estimate for Link Quality */ +#define RSSI 0x34 /* RSSI – Received signal strength indication */ +#define MARCSTATE 0x35 /* MARCSTATE – Main Radio Control State Machine state */ +#define WORTIME1 0x36 /* WORTIME1 – High byte of WOR time */ +#define WORTIME0 0x37 /* WORTIME0 – Low byte of WOR time */ +#define PKTSTATUS 0x38 /* PKTSTATUS – Current GDOx status and packet status */ +#define VCO_VC_DAC 0x39 /* VCO_VC_DAC – Current setting from PLL calibration module */ +#define TXBYTES 0x3A /* TXBYTES – Underflow and number of bytes */ +#define RXBYTES 0x3B /* RXBYTES – Overflow and number of bytes */ + +/* burst write registers */ +#define PATABLE 0x3E /* PATABLE - PA control settings table */ +#define TXFIFO 0x3F /* TXFIFO - Transmit FIFO */ +#define RXFIFO 0x3F /* RXFIFO - Receive FIFO */ + +/* Radio Core Instructions */ +/* command strobes */ +#define RF_SRES 0x30 /* SRES - Reset chip. */ +#define RF_SFSTXON 0x31 /* SFSTXON - Enable and calibrate frequency synthesizer. */ +#define RF_SXOFF 0x32 /* SXOFF - Turn off crystal oscillator. */ +#define RF_SCAL 0x33 /* SCAL - Calibrate frequency synthesizer and turn it off. */ +#define RF_SRX 0x34 /* SRX - Enable RX. Perform calibration if enabled. */ +#define RF_STX 0x35 /* STX - Enable TX. If in RX state, only enable TX if CCA passes. */ +#define RF_SIDLE 0x36 /* SIDLE - Exit RX / TX, turn off frequency synthesizer. */ +//#define RF_SRSVD 0x37 /* SRVSD - Reserved. Do not use. */ +#define RF_SWOR 0x38 /* SWOR - Start automatic RX polling sequence (Wake-on-Radio) */ +#define RF_SPWD 0x39 /* SPWD - Enter power down mode when CSn goes high. */ +#define RF_SFRX 0x3A /* SFRX - Flush the RX FIFO buffer. */ +#define RF_SFTX 0x3B /* SFTX - Flush the TX FIFO buffer. */ +#define RF_SWORRST 0x3C /* SWORRST - Reset real time clock. */ +#define RF_SNOP 0x3D /* SNOP - No operation. Returns status byte. */ + +#define RF_RXSTAT 0x80 /* Used in combination with strobe commands delivers number of availabe bytes in RX FIFO with return status */ +#define RF_TXSTAT 0x00 /* Used in combination with strobe commands delivers number of availabe bytes in TX FIFO with return status */ + +/* other radio instr */ +#define RF_SNGLREGRD 0x80 +#define RF_SNGLREGWR 0x00 +#define RF_REGRD 0xC0 +#define RF_REGWR 0x40 +#define RF_STATREGRD 0xC0 /* Read single radio core status register */ +#define RF_SNGLPATABRD (RF_SNGLREGRD+PATABLE) +#define RF_SNGLPATABWR (RF_SNGLREGWR+PATABLE) +#define RF_PATABRD (RF_REGRD+PATABLE) +#define RF_PATABWR (RF_REGWR+PATABLE) +#define RF_SNGLRXRD (RF_SNGLREGRD+RXFIFO) +#define RF_SNGLTXWR (RF_SNGLREGWR+TXFIFO) +#define RF_RXFIFORD (RF_REGRD+RXFIFO) +#define RF_TXFIFOWR (RF_REGWR+TXFIFO) + +#endif +/************************************************************* +* CRC Module +*************************************************************/ +#ifdef __MSP430_HAS_CRC__ /* Definition to show that Module is available */ + +#define OFS_CRCDI (0x0000u) /* CRC Data In Register */ +#define OFS_CRCDI_L OFS_CRCDI +#define OFS_CRCDI_H OFS_CRCDI+1 +#define OFS_CRCDIRB (0x0002u) /* CRC data in reverse byte Register */ +#define OFS_CRCDIRB_L OFS_CRCDIRB +#define OFS_CRCDIRB_H OFS_CRCDIRB+1 +#define OFS_CRCINIRES (0x0004u) /* CRC Initialisation Register and Result Register */ +#define OFS_CRCINIRES_L OFS_CRCINIRES +#define OFS_CRCINIRES_H OFS_CRCINIRES+1 +#define OFS_CRCRESR (0x0006u) /* CRC reverse result Register */ +#define OFS_CRCRESR_L OFS_CRCRESR +#define OFS_CRCRESR_H OFS_CRCRESR+1 + +#endif +/************************************************************ +* DAC12 +************************************************************/ +#ifdef __MSP430_HAS_DAC12_2__ /* Definition to show that Module is available */ + +#define OFS_DAC12_0CTL0 (0x0000u) /* DAC12_0 Control Register 0 */ +#define OFS_DAC12_0CTL1 (0x0002u) /* DAC12_0 Control Register 1 */ +#define OFS_DAC12_0DAT (0x0004u) /* DAC12_0 Data */ +#define OFS_DAC12_0CALCTL (0x0006u) /* DAC12_0 Calibration Control Register */ +#define OFS_DAC12_0CALDAT (0x0008u) /* DAC12_0 Calibration Data Register */ +#define OFS_DAC12_1CTL0 (0x0010u) /* DAC12_1 Control Register 0 */ +#define OFS_DAC12_1CTL1 (0x0012u) /* DAC12_1 Control Register 1 */ +#define OFS_DAC12_1DAT (0x0014u) /* DAC12_1 Data */ +#define OFS_DAC12_1CALCTL (0x0016u) /* DAC12_1 Calibration Control Register */ +#define OFS_DAC12_1CALDAT (0x0018u) /* DAC12_1 Calibration Data Register */ +#define OFS_DAC12_IV (0x001Eu) /* DAC12 Interrupt Vector Word */ + +/* DAC12_xCTL0 Control Bits */ +#define DAC12GRP (0x0001u) /* DAC12 group */ +#define DAC12ENC (0x0002u) /* DAC12 enable conversion */ +#define DAC12IFG (0x0004u) /* DAC12 interrupt flag */ +#define DAC12IE (0x0008u) /* DAC12 interrupt enable */ +#define DAC12DF (0x0010u) /* DAC12 data format */ +#define DAC12AMP0 (0x0020u) /* DAC12 amplifier bit 0 */ +#define DAC12AMP1 (0x0040u) /* DAC12 amplifier bit 1 */ +#define DAC12AMP2 (0x0080u) /* DAC12 amplifier bit 2 */ +#define DAC12IR (0x0100u) /* DAC12 input reference and output range */ +#define DAC12CALON (0x0200u) /* DAC12 calibration */ +#define DAC12LSEL0 (0x0400u) /* DAC12 load select bit 0 */ +#define DAC12LSEL1 (0x0800u) /* DAC12 load select bit 1 */ +#define DAC12RES (0x1000u) /* DAC12 resolution */ +#define DAC12SREF0 (0x2000u) /* DAC12 reference bit 0 */ +#define DAC12SREF1 (0x4000u) /* DAC12 reference bit 1 */ +#define DAC12OPS (0x8000u) /* DAC12 Operation Amp. */ + +#define DAC12AMP_0 (0*0x0020u) /* DAC12 amplifier 0: off, 3-state */ +#define DAC12AMP_1 (1*0x0020u) /* DAC12 amplifier 1: off, off */ +#define DAC12AMP_2 (2*0x0020u) /* DAC12 amplifier 2: low, low */ +#define DAC12AMP_3 (3*0x0020u) /* DAC12 amplifier 3: low, medium */ +#define DAC12AMP_4 (4*0x0020u) /* DAC12 amplifier 4: low, high */ +#define DAC12AMP_5 (5*0x0020u) /* DAC12 amplifier 5: medium, medium */ +#define DAC12AMP_6 (6*0x0020u) /* DAC12 amplifier 6: medium, high */ +#define DAC12AMP_7 (7*0x0020u) /* DAC12 amplifier 7: high, high */ + +#define DAC12LSEL_0 (0*0x0400u) /* DAC12 load select 0: direct */ +#define DAC12LSEL_1 (1*0x0400u) /* DAC12 load select 1: latched with DAT */ +#define DAC12LSEL_2 (2*0x0400u) /* DAC12 load select 2: latched with pos. Timer_A3.OUT1 */ +#define DAC12LSEL_3 (3*0x0400u) /* DAC12 load select 3: latched with pos. Timer_B7.OUT1 */ + +#define DAC12SREF_0 (0*0x2000u) /* DAC12 reference 0: Vref+ */ +#define DAC12SREF_1 (1*0x2000u) /* DAC12 reference 1: Vref+ */ +#define DAC12SREF_2 (2*0x2000u) /* DAC12 reference 2: Veref+ */ +#define DAC12SREF_3 (3*0x2000u) /* DAC12 reference 3: Veref+ */ + +/* DAC12_xCTL1 Control Bits */ +#define DAC12DFJ (0x0001u) /* DAC12 Data Format Justification */ +#define DAC12OG (0x0002u) /* DAC12 output buffer gain: 0: 3x gain / 1: 2x gain */ + +/* DAC12_xCALCTL Control Bits */ +#define DAC12LOCK (0x0001u) /* DAC12 Calibration Lock */ + +#define DAC12PW (0xA500u) /* DAC12 Calibration Register write Password */ + +/* DACIV Definitions */ +#define DACIV_NONE (0x0000u) /* No Interrupt pending */ +#define DACIV_DAC12IFG_0 (0x0002u) /* DAC12IFG_0 */ +#define DACIV_DAC12IFG_1 (0x0004u) /* DAC12IFG_1 */ + +#endif +/************************************************************ +* DMA_X +************************************************************/ +#ifdef __MSP430_HAS_DMAX_3__ /* Definition to show that Module is available */ + +#define OFS_DMACTL0 (0x0000u) /* DMA Module Control 0 */ +#define OFS_DMACTL0_L OFS_DMACTL0 +#define OFS_DMACTL0_H OFS_DMACTL0+1 +#define OFS_DMACTL1 (0x0002u) /* DMA Module Control 1 */ +#define OFS_DMACTL1_L OFS_DMACTL1 +#define OFS_DMACTL1_H OFS_DMACTL1+1 +#define OFS_DMACTL2 (0x0004u) /* DMA Module Control 2 */ +#define OFS_DMACTL2_L OFS_DMACTL2 +#define OFS_DMACTL2_H OFS_DMACTL2+1 +#define OFS_DMACTL3 (0x0006u) /* DMA Module Control 3 */ +#define OFS_DMACTL3_L OFS_DMACTL3 +#define OFS_DMACTL3_H OFS_DMACTL3+1 +#define OFS_DMACTL4 (0x0008u) /* DMA Module Control 4 */ +#define OFS_DMACTL4_L OFS_DMACTL4 +#define OFS_DMACTL4_H OFS_DMACTL4+1 +#define OFS_DMAIV (0x000Eu) /* DMA Interrupt Vector Word */ +#define OFS_DMAIV_L OFS_DMAIV +#define OFS_DMAIV_H OFS_DMAIV+1 + +#define OFS_DMA0CTL (0x0010u) /* DMA Channel 0 Control */ +#define OFS_DMA0CTL_L OFS_DMA0CTL +#define OFS_DMA0CTL_H OFS_DMA0CTL+1 +#define OFS_DMA0SA (0x0012u) /* DMA Channel 0 Source Address */ +#define OFS_DMA0DA (0x0016u) /* DMA Channel 0 Destination Address */ +#define OFS_DMA0SZ (0x001Au) /* DMA Channel 0 Transfer Size */ + +#define OFS_DMA1CTL (0x0020u) /* DMA Channel 1 Control */ +#define OFS_DMA1CTL_L OFS_DMA1CTL +#define OFS_DMA1CTL_H OFS_DMA1CTL+1 +#define OFS_DMA1SA (0x0022u) /* DMA Channel 1 Source Address */ +#define OFS_DMA1DA (0x0026u) /* DMA Channel 1 Destination Address */ +#define OFS_DMA1SZ (0x002Au) /* DMA Channel 1 Transfer Size */ + +#define OFS_DMA2CTL (0x0030u) /* DMA Channel 2 Control */ +#define OFS_DMA2CTL_L OFS_DMA2CTL +#define OFS_DMA2CTL_H OFS_DMA2CTL+1 +#define OFS_DMA2SA (0x0032u) /* DMA Channel 2 Source Address */ +#define OFS_DMA2DA (0x0036u) /* DMA Channel 2 Destination Address */ +#define OFS_DMA2SZ (0x003Au) /* DMA Channel 2 Transfer Size */ + +/* DMACTL0 Control Bits */ +#define DMA0TSEL0 (0x0001u) /* DMA channel 0 transfer select bit 0 */ +#define DMA0TSEL1 (0x0002u) /* DMA channel 0 transfer select bit 1 */ +#define DMA0TSEL2 (0x0004u) /* DMA channel 0 transfer select bit 2 */ +#define DMA0TSEL3 (0x0008u) /* DMA channel 0 transfer select bit 3 */ +#define DMA0TSEL4 (0x0010u) /* DMA channel 0 transfer select bit 4 */ +#define DMA1TSEL0 (0x0100u) /* DMA channel 1 transfer select bit 0 */ +#define DMA1TSEL1 (0x0200u) /* DMA channel 1 transfer select bit 1 */ +#define DMA1TSEL2 (0x0400u) /* DMA channel 1 transfer select bit 2 */ +#define DMA1TSEL3 (0x0800u) /* DMA channel 1 transfer select bit 3 */ +#define DMA1TSEL4 (0x1000u) /* DMA channel 1 transfer select bit 4 */ + +/* DMACTL0 Control Bits */ +#define DMA0TSEL0_L (0x0001u) /* DMA channel 0 transfer select bit 0 */ +#define DMA0TSEL1_L (0x0002u) /* DMA channel 0 transfer select bit 1 */ +#define DMA0TSEL2_L (0x0004u) /* DMA channel 0 transfer select bit 2 */ +#define DMA0TSEL3_L (0x0008u) /* DMA channel 0 transfer select bit 3 */ +#define DMA0TSEL4_L (0x0010u) /* DMA channel 0 transfer select bit 4 */ + +/* DMACTL0 Control Bits */ +#define DMA1TSEL0_H (0x0001u) /* DMA channel 1 transfer select bit 0 */ +#define DMA1TSEL1_H (0x0002u) /* DMA channel 1 transfer select bit 1 */ +#define DMA1TSEL2_H (0x0004u) /* DMA channel 1 transfer select bit 2 */ +#define DMA1TSEL3_H (0x0008u) /* DMA channel 1 transfer select bit 3 */ +#define DMA1TSEL4_H (0x0010u) /* DMA channel 1 transfer select bit 4 */ + +/* DMACTL01 Control Bits */ +#define DMA2TSEL0 (0x0001u) /* DMA channel 2 transfer select bit 0 */ +#define DMA2TSEL1 (0x0002u) /* DMA channel 2 transfer select bit 1 */ +#define DMA2TSEL2 (0x0004u) /* DMA channel 2 transfer select bit 2 */ +#define DMA2TSEL3 (0x0008u) /* DMA channel 2 transfer select bit 3 */ +#define DMA2TSEL4 (0x0010u) /* DMA channel 2 transfer select bit 4 */ + +/* DMACTL01 Control Bits */ +#define DMA2TSEL0_L (0x0001u) /* DMA channel 2 transfer select bit 0 */ +#define DMA2TSEL1_L (0x0002u) /* DMA channel 2 transfer select bit 1 */ +#define DMA2TSEL2_L (0x0004u) /* DMA channel 2 transfer select bit 2 */ +#define DMA2TSEL3_L (0x0008u) /* DMA channel 2 transfer select bit 3 */ +#define DMA2TSEL4_L (0x0010u) /* DMA channel 2 transfer select bit 4 */ + +/* DMACTL4 Control Bits */ +#define ENNMI (0x0001u) /* Enable NMI interruption of DMA */ +#define ROUNDROBIN (0x0002u) /* Round-Robin DMA channel priorities */ +#define DMARMWDIS (0x0004u) /* Inhibited DMA transfers during read-modify-write CPU operations */ + +/* DMACTL4 Control Bits */ +#define ENNMI_L (0x0001u) /* Enable NMI interruption of DMA */ +#define ROUNDROBIN_L (0x0002u) /* Round-Robin DMA channel priorities */ +#define DMARMWDIS_L (0x0004u) /* Inhibited DMA transfers during read-modify-write CPU operations */ + +/* DMAxCTL Control Bits */ +#define DMAREQ (0x0001u) /* Initiate DMA transfer with DMATSEL */ +#define DMAABORT (0x0002u) /* DMA transfer aborted by NMI */ +#define DMAIE (0x0004u) /* DMA interrupt enable */ +#define DMAIFG (0x0008u) /* DMA interrupt flag */ +#define DMAEN (0x0010u) /* DMA enable */ +#define DMALEVEL (0x0020u) /* DMA level sensitive trigger select */ +#define DMASRCBYTE (0x0040u) /* DMA source byte */ +#define DMADSTBYTE (0x0080u) /* DMA destination byte */ +#define DMASRCINCR0 (0x0100u) /* DMA source increment bit 0 */ +#define DMASRCINCR1 (0x0200u) /* DMA source increment bit 1 */ +#define DMADSTINCR0 (0x0400u) /* DMA destination increment bit 0 */ +#define DMADSTINCR1 (0x0800u) /* DMA destination increment bit 1 */ +#define DMADT0 (0x1000u) /* DMA transfer mode bit 0 */ +#define DMADT1 (0x2000u) /* DMA transfer mode bit 1 */ +#define DMADT2 (0x4000u) /* DMA transfer mode bit 2 */ + +/* DMAxCTL Control Bits */ +#define DMAREQ_L (0x0001u) /* Initiate DMA transfer with DMATSEL */ +#define DMAABORT_L (0x0002u) /* DMA transfer aborted by NMI */ +#define DMAIE_L (0x0004u) /* DMA interrupt enable */ +#define DMAIFG_L (0x0008u) /* DMA interrupt flag */ +#define DMAEN_L (0x0010u) /* DMA enable */ +#define DMALEVEL_L (0x0020u) /* DMA level sensitive trigger select */ +#define DMASRCBYTE_L (0x0040u) /* DMA source byte */ +#define DMADSTBYTE_L (0x0080u) /* DMA destination byte */ + +/* DMAxCTL Control Bits */ +#define DMASRCINCR0_H (0x0001u) /* DMA source increment bit 0 */ +#define DMASRCINCR1_H (0x0002u) /* DMA source increment bit 1 */ +#define DMADSTINCR0_H (0x0004u) /* DMA destination increment bit 0 */ +#define DMADSTINCR1_H (0x0008u) /* DMA destination increment bit 1 */ +#define DMADT0_H (0x0010u) /* DMA transfer mode bit 0 */ +#define DMADT1_H (0x0020u) /* DMA transfer mode bit 1 */ +#define DMADT2_H (0x0040u) /* DMA transfer mode bit 2 */ + +#define DMASWDW (0*0x0040u) /* DMA transfer: source word to destination word */ +#define DMASBDW (1*0x0040u) /* DMA transfer: source byte to destination word */ +#define DMASWDB (2*0x0040u) /* DMA transfer: source word to destination byte */ +#define DMASBDB (3*0x0040u) /* DMA transfer: source byte to destination byte */ + +#define DMASRCINCR_0 (0*0x0100u) /* DMA source increment 0: source address unchanged */ +#define DMASRCINCR_1 (1*0x0100u) /* DMA source increment 1: source address unchanged */ +#define DMASRCINCR_2 (2*0x0100u) /* DMA source increment 2: source address decremented */ +#define DMASRCINCR_3 (3*0x0100u) /* DMA source increment 3: source address incremented */ + +#define DMADSTINCR_0 (0*0x0400u) /* DMA destination increment 0: destination address unchanged */ +#define DMADSTINCR_1 (1*0x0400u) /* DMA destination increment 1: destination address unchanged */ +#define DMADSTINCR_2 (2*0x0400u) /* DMA destination increment 2: destination address decremented */ +#define DMADSTINCR_3 (3*0x0400u) /* DMA destination increment 3: destination address incremented */ + +#define DMADT_0 (0*0x1000u) /* DMA transfer mode 0: Single transfer */ +#define DMADT_1 (1*0x1000u) /* DMA transfer mode 1: Block transfer */ +#define DMADT_2 (2*0x1000u) /* DMA transfer mode 2: Burst-Block transfer */ +#define DMADT_3 (3*0x1000u) /* DMA transfer mode 3: Burst-Block transfer */ +#define DMADT_4 (4*0x1000u) /* DMA transfer mode 4: Repeated Single transfer */ +#define DMADT_5 (5*0x1000u) /* DMA transfer mode 5: Repeated Block transfer */ +#define DMADT_6 (6*0x1000u) /* DMA transfer mode 6: Repeated Burst-Block transfer */ +#define DMADT_7 (7*0x1000u) /* DMA transfer mode 7: Repeated Burst-Block transfer */ + +/* DMAIV Definitions */ +#define DMAIV_NONE (0x0000u) /* No Interrupt pending */ +#define DMAIV_DMA0IFG (0x0002u) /* DMA0IFG*/ +#define DMAIV_DMA1IFG (0x0004u) /* DMA1IFG*/ +#define DMAIV_DMA2IFG (0x0006u) /* DMA2IFG*/ + +#endif +/************************************************************ +* DMA_X +************************************************************/ +#ifdef __MSP430_HAS_DMAX_6__ /* Definition to show that Module is available */ + +#define OFS_DMACTL0 (0x0000u) /* DMA Module Control 0 */ +#define OFS_DMACTL0_L OFS_DMACTL0 +#define OFS_DMACTL0_H OFS_DMACTL0+1 +#define OFS_DMACTL1 (0x0002u) /* DMA Module Control 1 */ +#define OFS_DMACTL1_L OFS_DMACTL1 +#define OFS_DMACTL1_H OFS_DMACTL1+1 +#define OFS_DMACTL2 (0x0004u) /* DMA Module Control 2 */ +#define OFS_DMACTL2_L OFS_DMACTL2 +#define OFS_DMACTL2_H OFS_DMACTL2+1 +#define OFS_DMACTL3 (0x0006u) /* DMA Module Control 3 */ +#define OFS_DMACTL3_L OFS_DMACTL3 +#define OFS_DMACTL3_H OFS_DMACTL3+1 +#define OFS_DMACTL4 (0x0008u) /* DMA Module Control 4 */ +#define OFS_DMACTL4_L OFS_DMACTL4 +#define OFS_DMACTL4_H OFS_DMACTL4+1 +#define OFS_DMAIV (0x000Eu) /* DMA Interrupt Vector Word */ +#define OFS_DMAIV_L OFS_DMAIV +#define OFS_DMAIV_H OFS_DMAIV+1 + +#define OFS_DMA0CTL (0x0010u) /* DMA Channel 0 Control */ +#define OFS_DMA0CTL_L OFS_DMA0CTL +#define OFS_DMA0CTL_H OFS_DMA0CTL+1 +#define OFS_DMA0SA (0x0012u) /* DMA Channel 0 Source Address */ +#define OFS_DMA0DA (0x0016u) /* DMA Channel 0 Destination Address */ +#define OFS_DMA0SZ (0x001Au) /* DMA Channel 0 Transfer Size */ + +#define OFS_DMA1CTL (0x0020u) /* DMA Channel 1 Control */ +#define OFS_DMA1CTL_L OFS_DMA1CTL +#define OFS_DMA1CTL_H OFS_DMA1CTL+1 +#define OFS_DMA1SA (0x0022u) /* DMA Channel 1 Source Address */ +#define OFS_DMA1DA (0x0026u) /* DMA Channel 1 Destination Address */ +#define OFS_DMA1SZ (0x002Au) /* DMA Channel 1 Transfer Size */ + +#define OFS_DMA2CTL (0x0030u) /* DMA Channel 2 Control */ +#define OFS_DMA2CTL_L OFS_DMA2CTL +#define OFS_DMA2CTL_H OFS_DMA2CTL+1 +#define OFS_DMA2SA (0x0032u) /* DMA Channel 2 Source Address */ +#define OFS_DMA2DA (0x0036u) /* DMA Channel 2 Destination Address */ +#define OFS_DMA2SZ (0x003Au) /* DMA Channel 2 Transfer Size */ + +#define OFS_DMA3CTL (0x0040u) /* DMA Channel 3 Control */ +#define OFS_DMA3CTL_L OFS_DMA3CTL +#define OFS_DMA3CTL_H OFS_DMA3CTL+1 +#define OFS_DMA3SA (0x0042u) /* DMA Channel 3 Source Address */ +#define OFS_DMA3DA (0x0046u) /* DMA Channel 3 Destination Address */ +#define OFS_DMA3SZ (0x004Au) /* DMA Channel 3 Transfer Size */ + +#define OFS_DMA4CTL (0x0050u) /* DMA Channel 4 Control */ +#define OFS_DMA4CTL_L OFS_DMA4CTL +#define OFS_DMA4CTL_H OFS_DMA4CTL+1 +#define OFS_DMA4SA (0x0052u) /* DMA Channel 4 Source Address */ +#define OFS_DMA4DA (0x0056u) /* DMA Channel 4 Destination Address */ +#define OFS_DMA4SZ (0x005Au) /* DMA Channel 4 Transfer Size */ + +#define OFS_DMA5CTL (0x0060u) /* DMA Channel 5 Control */ +#define OFS_DMA5CTL_L OFS_DMA5CTL +#define OFS_DMA5CTL_H OFS_DMA5CTL+1 +#define OFS_DMA5SA (0x0062u) /* DMA Channel 5 Source Address */ +#define OFS_DMA5DA (0x0066u) /* DMA Channel 5 Destination Address */ +#define OFS_DMA5SZ (0x006Au) /* DMA Channel 5 Transfer Size */ + +/* DMACTL0 Control Bits */ +#define DMA0TSEL0 (0x0001u) /* DMA channel 0 transfer select bit 0 */ +#define DMA0TSEL1 (0x0002u) /* DMA channel 0 transfer select bit 1 */ +#define DMA0TSEL2 (0x0004u) /* DMA channel 0 transfer select bit 2 */ +#define DMA0TSEL3 (0x0008u) /* DMA channel 0 transfer select bit 3 */ +#define DMA0TSEL4 (0x0010u) /* DMA channel 0 transfer select bit 4 */ +#define DMA1TSEL0 (0x0100u) /* DMA channel 1 transfer select bit 0 */ +#define DMA1TSEL1 (0x0200u) /* DMA channel 1 transfer select bit 1 */ +#define DMA1TSEL2 (0x0400u) /* DMA channel 1 transfer select bit 2 */ +#define DMA1TSEL3 (0x0800u) /* DMA channel 1 transfer select bit 3 */ +#define DMA1TSEL4 (0x1000u) /* DMA channel 1 transfer select bit 4 */ + +/* DMACTL0 Control Bits */ +#define DMA0TSEL0_L (0x0001u) /* DMA channel 0 transfer select bit 0 */ +#define DMA0TSEL1_L (0x0002u) /* DMA channel 0 transfer select bit 1 */ +#define DMA0TSEL2_L (0x0004u) /* DMA channel 0 transfer select bit 2 */ +#define DMA0TSEL3_L (0x0008u) /* DMA channel 0 transfer select bit 3 */ +#define DMA0TSEL4_L (0x0010u) /* DMA channel 0 transfer select bit 4 */ + +/* DMACTL0 Control Bits */ +#define DMA1TSEL0_H (0x0001u) /* DMA channel 1 transfer select bit 0 */ +#define DMA1TSEL1_H (0x0002u) /* DMA channel 1 transfer select bit 1 */ +#define DMA1TSEL2_H (0x0004u) /* DMA channel 1 transfer select bit 2 */ +#define DMA1TSEL3_H (0x0008u) /* DMA channel 1 transfer select bit 3 */ +#define DMA1TSEL4_H (0x0010u) /* DMA channel 1 transfer select bit 4 */ + +/* DMACTL01 Control Bits */ +#define DMA2TSEL0 (0x0001u) /* DMA channel 2 transfer select bit 0 */ +#define DMA2TSEL1 (0x0002u) /* DMA channel 2 transfer select bit 1 */ +#define DMA2TSEL2 (0x0004u) /* DMA channel 2 transfer select bit 2 */ +#define DMA2TSEL3 (0x0008u) /* DMA channel 2 transfer select bit 3 */ +#define DMA2TSEL4 (0x0010u) /* DMA channel 2 transfer select bit 4 */ +#define DMA3TSEL0 (0x0100u) /* DMA channel 3 transfer select bit 0 */ +#define DMA3TSEL1 (0x0200u) /* DMA channel 3 transfer select bit 1 */ +#define DMA3TSEL2 (0x0400u) /* DMA channel 3 transfer select bit 2 */ +#define DMA3TSEL3 (0x0800u) /* DMA channel 3 transfer select bit 3 */ +#define DMA3TSEL4 (0x1000u) /* DMA channel 3 transfer select bit 4 */ + +/* DMACTL01 Control Bits */ +#define DMA2TSEL0_L (0x0001u) /* DMA channel 2 transfer select bit 0 */ +#define DMA2TSEL1_L (0x0002u) /* DMA channel 2 transfer select bit 1 */ +#define DMA2TSEL2_L (0x0004u) /* DMA channel 2 transfer select bit 2 */ +#define DMA2TSEL3_L (0x0008u) /* DMA channel 2 transfer select bit 3 */ +#define DMA2TSEL4_L (0x0010u) /* DMA channel 2 transfer select bit 4 */ + +/* DMACTL01 Control Bits */ +#define DMA3TSEL0_H (0x0001u) /* DMA channel 3 transfer select bit 0 */ +#define DMA3TSEL1_H (0x0002u) /* DMA channel 3 transfer select bit 1 */ +#define DMA3TSEL2_H (0x0004u) /* DMA channel 3 transfer select bit 2 */ +#define DMA3TSEL3_H (0x0008u) /* DMA channel 3 transfer select bit 3 */ +#define DMA3TSEL4_H (0x0010u) /* DMA channel 3 transfer select bit 4 */ + +/* DMACTL0 Control Bits */ +#define DMA4TSEL0 (0x0001u) /* DMA channel 4 transfer select bit 0 */ +#define DMA4TSEL1 (0x0002u) /* DMA channel 4 transfer select bit 1 */ +#define DMA4TSEL2 (0x0004u) /* DMA channel 4 transfer select bit 2 */ +#define DMA4TSEL3 (0x0008u) /* DMA channel 4 transfer select bit 3 */ +#define DMA4TSEL4 (0x0010u) /* DMA channel 4 transfer select bit 4 */ +#define DMA5TSEL0 (0x0100u) /* DMA channel 5 transfer select bit 0 */ +#define DMA5TSEL1 (0x0200u) /* DMA channel 5 transfer select bit 1 */ +#define DMA5TSEL2 (0x0400u) /* DMA channel 5 transfer select bit 2 */ +#define DMA5TSEL3 (0x0800u) /* DMA channel 5 transfer select bit 3 */ +#define DMA5TSEL4 (0x1000u) /* DMA channel 5 transfer select bit 4 */ + +/* DMACTL0 Control Bits */ +#define DMA4TSEL0_L (0x0001u) /* DMA channel 4 transfer select bit 0 */ +#define DMA4TSEL1_L (0x0002u) /* DMA channel 4 transfer select bit 1 */ +#define DMA4TSEL2_L (0x0004u) /* DMA channel 4 transfer select bit 2 */ +#define DMA4TSEL3_L (0x0008u) /* DMA channel 4 transfer select bit 3 */ +#define DMA4TSEL4_L (0x0010u) /* DMA channel 4 transfer select bit 4 */ + +/* DMACTL0 Control Bits */ +#define DMA5TSEL0_H (0x0001u) /* DMA channel 5 transfer select bit 0 */ +#define DMA5TSEL1_H (0x0002u) /* DMA channel 5 transfer select bit 1 */ +#define DMA5TSEL2_H (0x0004u) /* DMA channel 5 transfer select bit 2 */ +#define DMA5TSEL3_H (0x0008u) /* DMA channel 5 transfer select bit 3 */ +#define DMA5TSEL4_H (0x0010u) /* DMA channel 5 transfer select bit 4 */ + +/* DMACTL4 Control Bits */ +#define ENNMI (0x0001u) /* Enable NMI interruption of DMA */ +#define ROUNDROBIN (0x0002u) /* Round-Robin DMA channel priorities */ +#define DMARMWDIS (0x0004u) /* Inhibited DMA transfers during read-modify-write CPU operations */ + +/* DMACTL4 Control Bits */ +#define ENNMI_L (0x0001u) /* Enable NMI interruption of DMA */ +#define ROUNDROBIN_L (0x0002u) /* Round-Robin DMA channel priorities */ +#define DMARMWDIS_L (0x0004u) /* Inhibited DMA transfers during read-modify-write CPU operations */ + +/* DMAxCTL Control Bits */ +#define DMAREQ (0x0001u) /* Initiate DMA transfer with DMATSEL */ +#define DMAABORT (0x0002u) /* DMA transfer aborted by NMI */ +#define DMAIE (0x0004u) /* DMA interrupt enable */ +#define DMAIFG (0x0008u) /* DMA interrupt flag */ +#define DMAEN (0x0010u) /* DMA enable */ +#define DMALEVEL (0x0020u) /* DMA level sensitive trigger select */ +#define DMASRCBYTE (0x0040u) /* DMA source byte */ +#define DMADSTBYTE (0x0080u) /* DMA destination byte */ +#define DMASRCINCR0 (0x0100u) /* DMA source increment bit 0 */ +#define DMASRCINCR1 (0x0200u) /* DMA source increment bit 1 */ +#define DMADSTINCR0 (0x0400u) /* DMA destination increment bit 0 */ +#define DMADSTINCR1 (0x0800u) /* DMA destination increment bit 1 */ +#define DMADT0 (0x1000u) /* DMA transfer mode bit 0 */ +#define DMADT1 (0x2000u) /* DMA transfer mode bit 1 */ +#define DMADT2 (0x4000u) /* DMA transfer mode bit 2 */ + +/* DMAxCTL Control Bits */ +#define DMAREQ_L (0x0001u) /* Initiate DMA transfer with DMATSEL */ +#define DMAABORT_L (0x0002u) /* DMA transfer aborted by NMI */ +#define DMAIE_L (0x0004u) /* DMA interrupt enable */ +#define DMAIFG_L (0x0008u) /* DMA interrupt flag */ +#define DMAEN_L (0x0010u) /* DMA enable */ +#define DMALEVEL_L (0x0020u) /* DMA level sensitive trigger select */ +#define DMASRCBYTE_L (0x0040u) /* DMA source byte */ +#define DMADSTBYTE_L (0x0080u) /* DMA destination byte */ + +/* DMAxCTL Control Bits */ +#define DMASRCINCR0_H (0x0001u) /* DMA source increment bit 0 */ +#define DMASRCINCR1_H (0x0002u) /* DMA source increment bit 1 */ +#define DMADSTINCR0_H (0x0004u) /* DMA destination increment bit 0 */ +#define DMADSTINCR1_H (0x0008u) /* DMA destination increment bit 1 */ +#define DMADT0_H (0x0010u) /* DMA transfer mode bit 0 */ +#define DMADT1_H (0x0020u) /* DMA transfer mode bit 1 */ +#define DMADT2_H (0x0040u) /* DMA transfer mode bit 2 */ + +#define DMASWDW (0*0x0040u) /* DMA transfer: source word to destination word */ +#define DMASBDW (1*0x0040u) /* DMA transfer: source byte to destination word */ +#define DMASWDB (2*0x0040u) /* DMA transfer: source word to destination byte */ +#define DMASBDB (3*0x0040u) /* DMA transfer: source byte to destination byte */ + +#define DMASRCINCR_0 (0*0x0100u) /* DMA source increment 0: source address unchanged */ +#define DMASRCINCR_1 (1*0x0100u) /* DMA source increment 1: source address unchanged */ +#define DMASRCINCR_2 (2*0x0100u) /* DMA source increment 2: source address decremented */ +#define DMASRCINCR_3 (3*0x0100u) /* DMA source increment 3: source address incremented */ + +#define DMADSTINCR_0 (0*0x0400u) /* DMA destination increment 0: destination address unchanged */ +#define DMADSTINCR_1 (1*0x0400u) /* DMA destination increment 1: destination address unchanged */ +#define DMADSTINCR_2 (2*0x0400u) /* DMA destination increment 2: destination address decremented */ +#define DMADSTINCR_3 (3*0x0400u) /* DMA destination increment 3: destination address incremented */ + +#define DMADT_0 (0*0x1000u) /* DMA transfer mode 0: Single transfer */ +#define DMADT_1 (1*0x1000u) /* DMA transfer mode 1: Block transfer */ +#define DMADT_2 (2*0x1000u) /* DMA transfer mode 2: Burst-Block transfer */ +#define DMADT_3 (3*0x1000u) /* DMA transfer mode 3: Burst-Block transfer */ +#define DMADT_4 (4*0x1000u) /* DMA transfer mode 4: Repeated Single transfer */ +#define DMADT_5 (5*0x1000u) /* DMA transfer mode 5: Repeated Block transfer */ +#define DMADT_6 (6*0x1000u) /* DMA transfer mode 6: Repeated Burst-Block transfer */ +#define DMADT_7 (7*0x1000u) /* DMA transfer mode 7: Repeated Burst-Block transfer */ + +/* DMAIV Definitions */ +#define DMAIV_NONE (0x0000u) /* No Interrupt pending */ +#define DMAIV_DMA0IFG (0x0002u) /* DMA0IFG*/ +#define DMAIV_DMA1IFG (0x0004u) /* DMA1IFG*/ +#define DMAIV_DMA2IFG (0x0006u) /* DMA2IFG*/ +#define DMAIV_DMA3IFG (0x0008u) /* DMA3IFG*/ +#define DMAIV_DMA4IFG (0x000Au) /* DMA4IFG*/ +#define DMAIV_DMA5IFG (0x000Cu) /* DMA5IFG*/ + +#endif +/************************************************************* +* Flash Memory +*************************************************************/ +#ifdef __MSP430_HAS_FLASH__ /* Definition to show that Module is available */ + +#define OFS_FCTL1 (0x0000u) /* FLASH Control 1 */ +#define OFS_FCTL1_L OFS_FCTL1 +#define OFS_FCTL1_H OFS_FCTL1+1 +//#define FCTL2_O (0x0002u) /* FLASH Control 2 */ +#define OFS_FCTL3 (0x0004u) /* FLASH Control 3 */ +#define OFS_FCTL3_L OFS_FCTL3 +#define OFS_FCTL3_H OFS_FCTL3+1 +#define OFS_FCTL4 (0x0006u) /* FLASH Control 4 */ +#define OFS_FCTL4_L OFS_FCTL4 +#define OFS_FCTL4_H OFS_FCTL4+1 + +#define FRPW (0x9600u) /* Flash password returned by read */ +#define FWPW (0xA500u) /* Flash password for write */ +#define FXPW (0x3300u) /* for use with XOR instruction */ +#define FRKEY (0x9600u) /* (legacy definition) Flash key returned by read */ +#define FWKEY (0xA500u) /* (legacy definition) Flash key for write */ +#define FXKEY (0x3300u) /* (legacy definition) for use with XOR instruction */ + +/* FCTL1 Control Bits */ +//#define RESERVED (0x0001u) /* Reserved */ +#define ERASE (0x0002u) /* Enable bit for Flash segment erase */ +#define MERAS (0x0004u) /* Enable bit for Flash mass erase */ +//#define RESERVED (0x0008u) /* Reserved */ +//#define RESERVED (0x0010u) /* Reserved */ +#define SWRT (0x0020u) /* Smart Write enable */ +#define WRT (0x0040u) /* Enable bit for Flash write */ +#define BLKWRT (0x0080u) /* Enable bit for Flash segment write */ + +/* FCTL1 Control Bits */ +//#define RESERVED (0x0001u) /* Reserved */ +#define ERASE_L (0x0002u) /* Enable bit for Flash segment erase */ +#define MERAS_L (0x0004u) /* Enable bit for Flash mass erase */ +//#define RESERVED (0x0008u) /* Reserved */ +//#define RESERVED (0x0010u) /* Reserved */ +#define SWRT_L (0x0020u) /* Smart Write enable */ +#define WRT_L (0x0040u) /* Enable bit for Flash write */ +#define BLKWRT_L (0x0080u) /* Enable bit for Flash segment write */ + +/* FCTL3 Control Bits */ +#define BUSY (0x0001u) /* Flash busy: 1 */ +#define KEYV (0x0002u) /* Flash Key violation flag */ +#define ACCVIFG (0x0004u) /* Flash Access violation flag */ +#define WAIT (0x0008u) /* Wait flag for segment write */ +#define LOCK (0x0010u) /* Lock bit: 1 - Flash is locked (read only) */ +#define EMEX (0x0020u) /* Flash Emergency Exit */ +#define LOCKA (0x0040u) /* Segment A Lock bit: read = 1 - Segment is locked (read only) */ +//#define RESERVED (0x0080u) /* Reserved */ + +/* FCTL3 Control Bits */ +#define BUSY_L (0x0001u) /* Flash busy: 1 */ +#define KEYV_L (0x0002u) /* Flash Key violation flag */ +#define ACCVIFG_L (0x0004u) /* Flash Access violation flag */ +#define WAIT_L (0x0008u) /* Wait flag for segment write */ +#define LOCK_L (0x0010u) /* Lock bit: 1 - Flash is locked (read only) */ +#define EMEX_L (0x0020u) /* Flash Emergency Exit */ +#define LOCKA_L (0x0040u) /* Segment A Lock bit: read = 1 - Segment is locked (read only) */ +//#define RESERVED (0x0080u) /* Reserved */ + +/* FCTL4 Control Bits */ +#define VPE (0x0001u) /* Voltage Changed during Program Error Flag */ +#define MGR0 (0x0010u) /* Marginal read 0 mode. */ +#define MGR1 (0x0020u) /* Marginal read 1 mode. */ +#define LOCKINFO (0x0080u) /* Lock INFO Memory bit: read = 1 - Segment is locked (read only) */ + +/* FCTL4 Control Bits */ +#define VPE_L (0x0001u) /* Voltage Changed during Program Error Flag */ +#define MGR0_L (0x0010u) /* Marginal read 0 mode. */ +#define MGR1_L (0x0020u) /* Marginal read 1 mode. */ +#define LOCKINFO_L (0x0080u) /* Lock INFO Memory bit: read = 1 - Segment is locked (read only) */ + +#endif +/************************************************************ +* LCD_B +************************************************************/ +#ifdef __MSP430_HAS_LCD_B__ /* Definition to show that Module is available */ + +#define OFS_LCDBCTL0 (0x0000u) /* LCD_B Control Register 0 */ +#define OFS_LCDBCTL0_L OFS_LCDBCTL0 +#define OFS_LCDBCTL0_H OFS_LCDBCTL0+1 +#define OFS_LCDBCTL1 (0x0002u) /* LCD_B Control Register 1 */ +#define OFS_LCDBCTL1_L OFS_LCDBCTL1 +#define OFS_LCDBCTL1_H OFS_LCDBCTL1+1 +#define OFS_LCDBBLKCTL (0x0004u) /* LCD_B blinking control register */ +#define OFS_LCDBBLKCTL_L OFS_LCDBBLKCTL +#define OFS_LCDBBLKCTL_H OFS_LCDBBLKCTL+1 +#define OFS_LCDBMEMCTL (0x0006u) /* LCD_B memory control register */ +#define OFS_LCDBMEMCTL_L OFS_LCDBMEMCTL +#define OFS_LCDBMEMCTL_H OFS_LCDBMEMCTL+1 +#define OFS_LCDBVCTL (0x0008u) /* LCD_B Voltage Control Register */ +#define OFS_LCDBVCTL_L OFS_LCDBVCTL +#define OFS_LCDBVCTL_H OFS_LCDBVCTL+1 +#define OFS_LCDBPCTL0 (0x000Au) /* LCD_B Port Control Register 0 */ +#define OFS_LCDBPCTL0_L OFS_LCDBPCTL0 +#define OFS_LCDBPCTL0_H OFS_LCDBPCTL0+1 +#define OFS_LCDBPCTL1 (0x000Cu) /* LCD_B Port Control Register 1 */ +#define OFS_LCDBPCTL1_L OFS_LCDBPCTL1 +#define OFS_LCDBPCTL1_H OFS_LCDBPCTL1+1 +#define OFS_LCDBPCTL2 (0x000Eu) /* LCD_B Port Control Register 2 */ +#define OFS_LCDBPCTL2_L OFS_LCDBPCTL2 +#define OFS_LCDBPCTL2_H OFS_LCDBPCTL2+1 +#define OFS_LCDBPCTL3 (0x0010u) /* LCD_B Port Control Register 3 */ +#define OFS_LCDBPCTL3_L OFS_LCDBPCTL3 +#define OFS_LCDBPCTL3_H OFS_LCDBPCTL3+1 +#define OFS_LCDBCPCTL (0x0012u) /* LCD_B Charge Pump Control Register 3 */ +#define OFS_LCDBCPCTL_L OFS_LCDBCPCTL +#define OFS_LCDBCPCTL_H OFS_LCDBCPCTL+1 +#define OFS_LCDBIV (0x001Eu) /* LCD_B Interrupt Vector Register */ + +// LCDBCTL0 +#define LCDON (0x0001u) /* LCD_B LCD On */ +#define LCDSON (0x0004u) /* LCD_B LCD Segments On */ +#define LCDMX0 (0x0008u) /* LCD_B Mux Rate Bit: 0 */ +#define LCDMX1 (0x0010u) /* LCD_B Mux Rate Bit: 1 */ +//#define RESERVED (0x0020u) /* LCD_B RESERVED */ +//#define RESERVED (0x0040u) /* LCD_B RESERVED */ +#define LCDSSEL (0x0080u) /* LCD_B Clock Select */ +#define LCDPRE0 (0x0100u) /* LCD_B LCD frequency pre-scaler Bit: 0 */ +#define LCDPRE1 (0x0200u) /* LCD_B LCD frequency pre-scaler Bit: 1 */ +#define LCDPRE2 (0x0400u) /* LCD_B LCD frequency pre-scaler Bit: 2 */ +#define LCDDIV0 (0x0800u) /* LCD_B LCD frequency divider Bit: 0 */ +#define LCDDIV1 (0x1000u) /* LCD_B LCD frequency divider Bit: 1 */ +#define LCDDIV2 (0x2000u) /* LCD_B LCD frequency divider Bit: 2 */ +#define LCDDIV3 (0x4000u) /* LCD_B LCD frequency divider Bit: 3 */ +#define LCDDIV4 (0x8000u) /* LCD_B LCD frequency divider Bit: 4 */ + +// LCDBCTL0 +#define LCDON_L (0x0001u) /* LCD_B LCD On */ +#define LCDSON_L (0x0004u) /* LCD_B LCD Segments On */ +#define LCDMX0_L (0x0008u) /* LCD_B Mux Rate Bit: 0 */ +#define LCDMX1_L (0x0010u) /* LCD_B Mux Rate Bit: 1 */ +//#define RESERVED (0x0020u) /* LCD_B RESERVED */ +//#define RESERVED (0x0040u) /* LCD_B RESERVED */ +#define LCDSSEL_L (0x0080u) /* LCD_B Clock Select */ + +// LCDBCTL0 +//#define RESERVED (0x0020u) /* LCD_B RESERVED */ +//#define RESERVED (0x0040u) /* LCD_B RESERVED */ +#define LCDPRE0_H (0x0001u) /* LCD_B LCD frequency pre-scaler Bit: 0 */ +#define LCDPRE1_H (0x0002u) /* LCD_B LCD frequency pre-scaler Bit: 1 */ +#define LCDPRE2_H (0x0004u) /* LCD_B LCD frequency pre-scaler Bit: 2 */ +#define LCDDIV0_H (0x0008u) /* LCD_B LCD frequency divider Bit: 0 */ +#define LCDDIV1_H (0x0010u) /* LCD_B LCD frequency divider Bit: 1 */ +#define LCDDIV2_H (0x0020u) /* LCD_B LCD frequency divider Bit: 2 */ +#define LCDDIV3_H (0x0040u) /* LCD_B LCD frequency divider Bit: 3 */ +#define LCDDIV4_H (0x0080u) /* LCD_B LCD frequency divider Bit: 4 */ + +#define LCDPRE_0 (0x0000u) /* LCD_B LCD frequency pre-scaler: /1 */ +#define LCDPRE_1 (0x0100u) /* LCD_B LCD frequency pre-scaler: /2 */ +#define LCDPRE_2 (0x0200u) /* LCD_B LCD frequency pre-scaler: /4 */ +#define LCDPRE_3 (0x0300u) /* LCD_B LCD frequency pre-scaler: /8 */ +#define LCDPRE_4 (0x0400u) /* LCD_B LCD frequency pre-scaler: /16 */ +#define LCDPRE_5 (0x0500u) /* LCD_B LCD frequency pre-scaler: /32 */ +#define LCDPRE__1 (0x0000u) /* LCD_B LCD frequency pre-scaler: /1 */ +#define LCDPRE__2 (0x0100u) /* LCD_B LCD frequency pre-scaler: /2 */ +#define LCDPRE__4 (0x0200u) /* LCD_B LCD frequency pre-scaler: /4 */ +#define LCDPRE__8 (0x0300u) /* LCD_B LCD frequency pre-scaler: /8 */ +#define LCDPRE__16 (0x0400u) /* LCD_B LCD frequency pre-scaler: /16 */ +#define LCDPRE__32 (0x0500u) /* LCD_B LCD frequency pre-scaler: /32 */ + +#define LCDDIV_0 (0x0000u) /* LCD_B LCD frequency divider: /1 */ +#define LCDDIV_1 (0x0800u) /* LCD_B LCD frequency divider: /2 */ +#define LCDDIV_2 (0x1000u) /* LCD_B LCD frequency divider: /3 */ +#define LCDDIV_3 (0x1800u) /* LCD_B LCD frequency divider: /4 */ +#define LCDDIV_4 (0x2000u) /* LCD_B LCD frequency divider: /5 */ +#define LCDDIV_5 (0x2800u) /* LCD_B LCD frequency divider: /6 */ +#define LCDDIV_6 (0x3000u) /* LCD_B LCD frequency divider: /7 */ +#define LCDDIV_7 (0x3800u) /* LCD_B LCD frequency divider: /8 */ +#define LCDDIV_8 (0x4000u) /* LCD_B LCD frequency divider: /9 */ +#define LCDDIV_9 (0x4800u) /* LCD_B LCD frequency divider: /10 */ +#define LCDDIV_10 (0x5000u) /* LCD_B LCD frequency divider: /11 */ +#define LCDDIV_11 (0x5800u) /* LCD_B LCD frequency divider: /12 */ +#define LCDDIV_12 (0x6000u) /* LCD_B LCD frequency divider: /13 */ +#define LCDDIV_13 (0x6800u) /* LCD_B LCD frequency divider: /14 */ +#define LCDDIV_14 (0x7000u) /* LCD_B LCD frequency divider: /15 */ +#define LCDDIV_15 (0x7800u) /* LCD_B LCD frequency divider: /16 */ +#define LCDDIV_16 (0x8000u) /* LCD_B LCD frequency divider: /17 */ +#define LCDDIV_17 (0x8800u) /* LCD_B LCD frequency divider: /18 */ +#define LCDDIV_18 (0x9000u) /* LCD_B LCD frequency divider: /19 */ +#define LCDDIV_19 (0x9800u) /* LCD_B LCD frequency divider: /20 */ +#define LCDDIV_20 (0xA000u) /* LCD_B LCD frequency divider: /21 */ +#define LCDDIV_21 (0xA800u) /* LCD_B LCD frequency divider: /22 */ +#define LCDDIV_22 (0xB000u) /* LCD_B LCD frequency divider: /23 */ +#define LCDDIV_23 (0xB800u) /* LCD_B LCD frequency divider: /24 */ +#define LCDDIV_24 (0xC000u) /* LCD_B LCD frequency divider: /25 */ +#define LCDDIV_25 (0xC800u) /* LCD_B LCD frequency divider: /26 */ +#define LCDDIV_26 (0xD000u) /* LCD_B LCD frequency divider: /27 */ +#define LCDDIV_27 (0xD800u) /* LCD_B LCD frequency divider: /28 */ +#define LCDDIV_28 (0xE000u) /* LCD_B LCD frequency divider: /29 */ +#define LCDDIV_29 (0xE800u) /* LCD_B LCD frequency divider: /30 */ +#define LCDDIV_30 (0xF000u) /* LCD_B LCD frequency divider: /31 */ +#define LCDDIV_31 (0xF800u) /* LCD_B LCD frequency divider: /32 */ +#define LCDDIV__1 (0x0000u) /* LCD_B LCD frequency divider: /1 */ +#define LCDDIV__2 (0x0800u) /* LCD_B LCD frequency divider: /2 */ +#define LCDDIV__3 (0x1000u) /* LCD_B LCD frequency divider: /3 */ +#define LCDDIV__4 (0x1800u) /* LCD_B LCD frequency divider: /4 */ +#define LCDDIV__5 (0x2000u) /* LCD_B LCD frequency divider: /5 */ +#define LCDDIV__6 (0x2800u) /* LCD_B LCD frequency divider: /6 */ +#define LCDDIV__7 (0x3000u) /* LCD_B LCD frequency divider: /7 */ +#define LCDDIV__8 (0x3800u) /* LCD_B LCD frequency divider: /8 */ +#define LCDDIV__9 (0x4000u) /* LCD_B LCD frequency divider: /9 */ +#define LCDDIV__10 (0x4800u) /* LCD_B LCD frequency divider: /10 */ +#define LCDDIV__11 (0x5000u) /* LCD_B LCD frequency divider: /11 */ +#define LCDDIV__12 (0x5800u) /* LCD_B LCD frequency divider: /12 */ +#define LCDDIV__13 (0x6000u) /* LCD_B LCD frequency divider: /13 */ +#define LCDDIV__14 (0x6800u) /* LCD_B LCD frequency divider: /14 */ +#define LCDDIV__15 (0x7000u) /* LCD_B LCD frequency divider: /15 */ +#define LCDDIV__16 (0x7800u) /* LCD_B LCD frequency divider: /16 */ +#define LCDDIV__17 (0x8000u) /* LCD_B LCD frequency divider: /17 */ +#define LCDDIV__18 (0x8800u) /* LCD_B LCD frequency divider: /18 */ +#define LCDDIV__19 (0x9000u) /* LCD_B LCD frequency divider: /19 */ +#define LCDDIV__20 (0x9800u) /* LCD_B LCD frequency divider: /20 */ +#define LCDDIV__21 (0xA000u) /* LCD_B LCD frequency divider: /21 */ +#define LCDDIV__22 (0xA800u) /* LCD_B LCD frequency divider: /22 */ +#define LCDDIV__23 (0xB000u) /* LCD_B LCD frequency divider: /23 */ +#define LCDDIV__24 (0xB800u) /* LCD_B LCD frequency divider: /24 */ +#define LCDDIV__25 (0xC000u) /* LCD_B LCD frequency divider: /25 */ +#define LCDDIV__26 (0xC800u) /* LCD_B LCD frequency divider: /26 */ +#define LCDDIV__27 (0xD000u) /* LCD_B LCD frequency divider: /27 */ +#define LCDDIV__28 (0xD800u) /* LCD_B LCD frequency divider: /28 */ +#define LCDDIV__29 (0xE000u) /* LCD_B LCD frequency divider: /29 */ +#define LCDDIV__30 (0xE800u) /* LCD_B LCD frequency divider: /30 */ +#define LCDDIV__31 (0xF000u) /* LCD_B LCD frequency divider: /31 */ +#define LCDDIV__32 (0xF800u) /* LCD_B LCD frequency divider: /32 */ + +/* Display modes coded with Bits 2-4 */ +#define LCDSTATIC (LCDSON) +#define LCD2MUX (LCDMX0+LCDSON) +#define LCD3MUX (LCDMX1+LCDSON) +#define LCD4MUX (LCDMX1+LCDMX0+LCDSON) + +// LCDBCTL1 +#define LCDFRMIFG (0x0001u) /* LCD_B LCD frame interrupt flag */ +#define LCDBLKOFFIFG (0x0002u) /* LCD_B LCD blinking off interrupt flag, */ +#define LCDBLKONIFG (0x0004u) /* LCD_B LCD blinking on interrupt flag, */ +#define LCDNOCAPIFG (0x0008u) /* LCD_B No cpacitance connected interrupt flag */ +#define LCDFRMIE (0x0100u) /* LCD_B LCD frame interrupt enable */ +#define LCDBLKOFFIE (0x0200u) /* LCD_B LCD blinking off interrupt flag, */ +#define LCDBLKONIE (0x0400u) /* LCD_B LCD blinking on interrupt flag, */ +#define LCDNOCAPIE (0x0800u) /* LCD_B No cpacitance connected interrupt enable */ + +// LCDBCTL1 +#define LCDFRMIFG_L (0x0001u) /* LCD_B LCD frame interrupt flag */ +#define LCDBLKOFFIFG_L (0x0002u) /* LCD_B LCD blinking off interrupt flag, */ +#define LCDBLKONIFG_L (0x0004u) /* LCD_B LCD blinking on interrupt flag, */ +#define LCDNOCAPIFG_L (0x0008u) /* LCD_B No cpacitance connected interrupt flag */ + +// LCDBCTL1 +#define LCDFRMIE_H (0x0001u) /* LCD_B LCD frame interrupt enable */ +#define LCDBLKOFFIE_H (0x0002u) /* LCD_B LCD blinking off interrupt flag, */ +#define LCDBLKONIE_H (0x0004u) /* LCD_B LCD blinking on interrupt flag, */ +#define LCDNOCAPIE_H (0x0008u) /* LCD_B No cpacitance connected interrupt enable */ + +// LCDBBLKCTL +#define LCDBLKMOD0 (0x0001u) /* LCD_B Blinking mode Bit: 0 */ +#define LCDBLKMOD1 (0x0002u) /* LCD_B Blinking mode Bit: 1 */ +#define LCDBLKPRE0 (0x0004u) /* LCD_B Clock pre-scaler for blinking frequency Bit: 0 */ +#define LCDBLKPRE1 (0x0008u) /* LCD_B Clock pre-scaler for blinking frequency Bit: 1 */ +#define LCDBLKPRE2 (0x0010u) /* LCD_B Clock pre-scaler for blinking frequency Bit: 2 */ +#define LCDBLKDIV0 (0x0020u) /* LCD_B Clock divider for blinking frequency Bit: 0 */ +#define LCDBLKDIV1 (0x0040u) /* LCD_B Clock divider for blinking frequency Bit: 1 */ +#define LCDBLKDIV2 (0x0080u) /* LCD_B Clock divider for blinking frequency Bit: 2 */ + +// LCDBBLKCTL +#define LCDBLKMOD0_L (0x0001u) /* LCD_B Blinking mode Bit: 0 */ +#define LCDBLKMOD1_L (0x0002u) /* LCD_B Blinking mode Bit: 1 */ +#define LCDBLKPRE0_L (0x0004u) /* LCD_B Clock pre-scaler for blinking frequency Bit: 0 */ +#define LCDBLKPRE1_L (0x0008u) /* LCD_B Clock pre-scaler for blinking frequency Bit: 1 */ +#define LCDBLKPRE2_L (0x0010u) /* LCD_B Clock pre-scaler for blinking frequency Bit: 2 */ +#define LCDBLKDIV0_L (0x0020u) /* LCD_B Clock divider for blinking frequency Bit: 0 */ +#define LCDBLKDIV1_L (0x0040u) /* LCD_B Clock divider for blinking frequency Bit: 1 */ +#define LCDBLKDIV2_L (0x0080u) /* LCD_B Clock divider for blinking frequency Bit: 2 */ + +#define LCDBLKMOD_0 (0x0000u) /* LCD_B Blinking mode: Off */ +#define LCDBLKMOD_1 (0x0001u) /* LCD_B Blinking mode: Individual */ +#define LCDBLKMOD_2 (0x0002u) /* LCD_B Blinking mode: All */ +#define LCDBLKMOD_3 (0x0003u) /* LCD_B Blinking mode: Switching */ + +// LCDBMEMCTL +#define LCDDISP (0x0001u) /* LCD_B LCD memory registers for display */ +#define LCDCLRM (0x0002u) /* LCD_B Clear LCD memory */ +#define LCDCLRBM (0x0004u) /* LCD_B Clear LCD blinking memory */ + +// LCDBMEMCTL +#define LCDDISP_L (0x0001u) /* LCD_B LCD memory registers for display */ +#define LCDCLRM_L (0x0002u) /* LCD_B Clear LCD memory */ +#define LCDCLRBM_L (0x0004u) /* LCD_B Clear LCD blinking memory */ + +// LCDBVCTL +#define LCD2B (0x0001u) /* Selects 1/2 bias. */ +#define VLCDREF0 (0x0002u) /* Selects reference voltage for regulated charge pump: 0 */ +#define VLCDREF1 (0x0004u) /* Selects reference voltage for regulated charge pump: 1 */ +#define LCDCPEN (0x0008u) /* LCD Voltage Charge Pump Enable. */ +#define VLCDEXT (0x0010u) /* Select external source for VLCD. */ +#define LCDEXTBIAS (0x0020u) /* V2 - V4 voltage select. */ +#define R03EXT (0x0040u) /* Selects external connections for LCD mid voltages. */ +#define LCDREXT (0x0080u) /* Selects external connection for lowest LCD voltage. */ +#define VLCD0 (0x0200u) /* VLCD select: 0 */ +#define VLCD1 (0x0400u) /* VLCD select: 1 */ +#define VLCD2 (0x0800u) /* VLCD select: 2 */ +#define VLCD3 (0x1000u) /* VLCD select: 3 */ + +// LCDBVCTL +#define LCD2B_L (0x0001u) /* Selects 1/2 bias. */ +#define VLCDREF0_L (0x0002u) /* Selects reference voltage for regulated charge pump: 0 */ +#define VLCDREF1_L (0x0004u) /* Selects reference voltage for regulated charge pump: 1 */ +#define LCDCPEN_L (0x0008u) /* LCD Voltage Charge Pump Enable. */ +#define VLCDEXT_L (0x0010u) /* Select external source for VLCD. */ +#define LCDEXTBIAS_L (0x0020u) /* V2 - V4 voltage select. */ +#define R03EXT_L (0x0040u) /* Selects external connections for LCD mid voltages. */ +#define LCDREXT_L (0x0080u) /* Selects external connection for lowest LCD voltage. */ + +// LCDBVCTL +#define VLCD0_H (0x0002u) /* VLCD select: 0 */ +#define VLCD1_H (0x0004u) /* VLCD select: 1 */ +#define VLCD2_H (0x0008u) /* VLCD select: 2 */ +#define VLCD3_H (0x0010u) /* VLCD select: 3 */ + +/* Reference voltage source select for the regulated charge pump */ +#define VLCDREF_0 (0<<1) /* Internal */ +#define VLCDREF_1 (1<<1) /* External */ +#define VLCDREF_2 (2<<1) /* Reserved */ +#define VLCDREF_3 (3<<1) /* Reserved */ + +/* Charge pump voltage selections */ +#define VLCD_0 (0<<9) /* Charge pump disabled */ +#define VLCD_1 (1<<9) /* VLCD = 2.60V */ +#define VLCD_2 (2<<9) /* VLCD = 2.66V */ +#define VLCD_3 (3<<9) /* VLCD = 2.72V */ +#define VLCD_4 (4<<9) /* VLCD = 2.78V */ +#define VLCD_5 (5<<9) /* VLCD = 2.84V */ +#define VLCD_6 (6<<9) /* VLCD = 2.90V */ +#define VLCD_7 (7<<9) /* VLCD = 2.96V */ +#define VLCD_8 (8<<9) /* VLCD = 3.02V */ +#define VLCD_9 (9<<9) /* VLCD = 3.08V */ +#define VLCD_10 (10<<9) /* VLCD = 3.14V */ +#define VLCD_11 (11<<9) /* VLCD = 3.20V */ +#define VLCD_12 (12<<9) /* VLCD = 3.26V */ +#define VLCD_13 (13<<9) /* VLCD = 3.32V */ +#define VLCD_14 (14<<9) /* VLCD = 3.38V */ +#define VLCD_15 (15<<9) /* VLCD = 3.44V */ + +#define VLCD_DISABLED (0<<9) /* Charge pump disabled */ +#define VLCD_2_60 (1<<9) /* VLCD = 2.60V */ +#define VLCD_2_66 (2<<9) /* VLCD = 2.66V */ +#define VLCD_2_72 (3<<9) /* VLCD = 2.72V */ +#define VLCD_2_78 (4<<9) /* VLCD = 2.78V */ +#define VLCD_2_84 (5<<9) /* VLCD = 2.84V */ +#define VLCD_2_90 (6<<9) /* VLCD = 2.90V */ +#define VLCD_2_96 (7<<9) /* VLCD = 2.96V */ +#define VLCD_3_02 (8<<9) /* VLCD = 3.02V */ +#define VLCD_3_08 (9<<9) /* VLCD = 3.08V */ +#define VLCD_3_14 (10<<9) /* VLCD = 3.14V */ +#define VLCD_3_20 (11<<9) /* VLCD = 3.20V */ +#define VLCD_3_26 (12<<9) /* VLCD = 3.26V */ +#define VLCD_3_32 (13<<9) /* VLCD = 3.32V */ +#define VLCD_3_38 (14<<9) /* VLCD = 3.38V */ +#define VLCD_3_44 (15<<9) /* VLCD = 3.44V */ + +// LCDBPCTL0 +#define LCDS0 (0x0001u) /* LCD Segment 0 enable. */ +#define LCDS1 (0x0002u) /* LCD Segment 1 enable. */ +#define LCDS2 (0x0004u) /* LCD Segment 2 enable. */ +#define LCDS3 (0x0008u) /* LCD Segment 3 enable. */ +#define LCDS4 (0x0010u) /* LCD Segment 4 enable. */ +#define LCDS5 (0x0020u) /* LCD Segment 5 enable. */ +#define LCDS6 (0x0040u) /* LCD Segment 6 enable. */ +#define LCDS7 (0x0080u) /* LCD Segment 7 enable. */ +#define LCDS8 (0x0100u) /* LCD Segment 8 enable. */ +#define LCDS9 (0x0200u) /* LCD Segment 9 enable. */ +#define LCDS10 (0x0400u) /* LCD Segment 10 enable. */ +#define LCDS11 (0x0800u) /* LCD Segment 11 enable. */ +#define LCDS12 (0x1000u) /* LCD Segment 12 enable. */ +#define LCDS13 (0x2000u) /* LCD Segment 13 enable. */ +#define LCDS14 (0x4000u) /* LCD Segment 14 enable. */ +#define LCDS15 (0x8000u) /* LCD Segment 15 enable. */ + +// LCDBPCTL0 +#define LCDS0_L (0x0001u) /* LCD Segment 0 enable. */ +#define LCDS1_L (0x0002u) /* LCD Segment 1 enable. */ +#define LCDS2_L (0x0004u) /* LCD Segment 2 enable. */ +#define LCDS3_L (0x0008u) /* LCD Segment 3 enable. */ +#define LCDS4_L (0x0010u) /* LCD Segment 4 enable. */ +#define LCDS5_L (0x0020u) /* LCD Segment 5 enable. */ +#define LCDS6_L (0x0040u) /* LCD Segment 6 enable. */ +#define LCDS7_L (0x0080u) /* LCD Segment 7 enable. */ + +// LCDBPCTL0 +#define LCDS8_H (0x0001u) /* LCD Segment 8 enable. */ +#define LCDS9_H (0x0002u) /* LCD Segment 9 enable. */ +#define LCDS10_H (0x0004u) /* LCD Segment 10 enable. */ +#define LCDS11_H (0x0008u) /* LCD Segment 11 enable. */ +#define LCDS12_H (0x0010u) /* LCD Segment 12 enable. */ +#define LCDS13_H (0x0020u) /* LCD Segment 13 enable. */ +#define LCDS14_H (0x0040u) /* LCD Segment 14 enable. */ +#define LCDS15_H (0x0080u) /* LCD Segment 15 enable. */ + +// LCDBPCTL1 +#define LCDS16 (0x0001u) /* LCD Segment 16 enable. */ +#define LCDS17 (0x0002u) /* LCD Segment 17 enable. */ +#define LCDS18 (0x0004u) /* LCD Segment 18 enable. */ +#define LCDS19 (0x0008u) /* LCD Segment 19 enable. */ +#define LCDS20 (0x0010u) /* LCD Segment 20 enable. */ +#define LCDS21 (0x0020u) /* LCD Segment 21 enable. */ +#define LCDS22 (0x0040u) /* LCD Segment 22 enable. */ +#define LCDS23 (0x0080u) /* LCD Segment 23 enable. */ +#define LCDS24 (0x0100u) /* LCD Segment 24 enable. */ +#define LCDS25 (0x0200u) /* LCD Segment 25 enable. */ +#define LCDS26 (0x0400u) /* LCD Segment 26 enable. */ +#define LCDS27 (0x0800u) /* LCD Segment 27 enable. */ +#define LCDS28 (0x1000u) /* LCD Segment 28 enable. */ +#define LCDS29 (0x2000u) /* LCD Segment 29 enable. */ +#define LCDS30 (0x4000u) /* LCD Segment 30 enable. */ +#define LCDS31 (0x8000u) /* LCD Segment 31 enable. */ + +// LCDBPCTL1 +#define LCDS16_L (0x0001u) /* LCD Segment 16 enable. */ +#define LCDS17_L (0x0002u) /* LCD Segment 17 enable. */ +#define LCDS18_L (0x0004u) /* LCD Segment 18 enable. */ +#define LCDS19_L (0x0008u) /* LCD Segment 19 enable. */ +#define LCDS20_L (0x0010u) /* LCD Segment 20 enable. */ +#define LCDS21_L (0x0020u) /* LCD Segment 21 enable. */ +#define LCDS22_L (0x0040u) /* LCD Segment 22 enable. */ +#define LCDS23_L (0x0080u) /* LCD Segment 23 enable. */ + +// LCDBPCTL1 +#define LCDS24_H (0x0001u) /* LCD Segment 24 enable. */ +#define LCDS25_H (0x0002u) /* LCD Segment 25 enable. */ +#define LCDS26_H (0x0004u) /* LCD Segment 26 enable. */ +#define LCDS27_H (0x0008u) /* LCD Segment 27 enable. */ +#define LCDS28_H (0x0010u) /* LCD Segment 28 enable. */ +#define LCDS29_H (0x0020u) /* LCD Segment 29 enable. */ +#define LCDS30_H (0x0040u) /* LCD Segment 30 enable. */ +#define LCDS31_H (0x0080u) /* LCD Segment 31 enable. */ + +// LCDBPCTL2 +#define LCDS32 (0x0001u) /* LCD Segment 32 enable. */ +#define LCDS33 (0x0002u) /* LCD Segment 33 enable. */ +#define LCDS34 (0x0004u) /* LCD Segment 34 enable. */ +#define LCDS35 (0x0008u) /* LCD Segment 35 enable. */ +#define LCDS36 (0x0010u) /* LCD Segment 36 enable. */ +#define LCDS37 (0x0020u) /* LCD Segment 37 enable. */ +#define LCDS38 (0x0040u) /* LCD Segment 38 enable. */ +#define LCDS39 (0x0080u) /* LCD Segment 39 enable. */ +#define LCDS40 (0x0100u) /* LCD Segment 40 enable. */ +#define LCDS41 (0x0200u) /* LCD Segment 41 enable. */ +#define LCDS42 (0x0400u) /* LCD Segment 42 enable. */ +#define LCDS43 (0x0800u) /* LCD Segment 43 enable. */ +#define LCDS44 (0x1000u) /* LCD Segment 44 enable. */ +#define LCDS45 (0x2000u) /* LCD Segment 45 enable. */ +#define LCDS46 (0x4000u) /* LCD Segment 46 enable. */ +#define LCDS47 (0x8000u) /* LCD Segment 47 enable. */ + +// LCDBPCTL2 +#define LCDS32_L (0x0001u) /* LCD Segment 32 enable. */ +#define LCDS33_L (0x0002u) /* LCD Segment 33 enable. */ +#define LCDS34_L (0x0004u) /* LCD Segment 34 enable. */ +#define LCDS35_L (0x0008u) /* LCD Segment 35 enable. */ +#define LCDS36_L (0x0010u) /* LCD Segment 36 enable. */ +#define LCDS37_L (0x0020u) /* LCD Segment 37 enable. */ +#define LCDS38_L (0x0040u) /* LCD Segment 38 enable. */ +#define LCDS39_L (0x0080u) /* LCD Segment 39 enable. */ + +// LCDBPCTL2 +#define LCDS40_H (0x0001u) /* LCD Segment 40 enable. */ +#define LCDS41_H (0x0002u) /* LCD Segment 41 enable. */ +#define LCDS42_H (0x0004u) /* LCD Segment 42 enable. */ +#define LCDS43_H (0x0008u) /* LCD Segment 43 enable. */ +#define LCDS44_H (0x0010u) /* LCD Segment 44 enable. */ +#define LCDS45_H (0x0020u) /* LCD Segment 45 enable. */ +#define LCDS46_H (0x0040u) /* LCD Segment 46 enable. */ +#define LCDS47_H (0x0080u) /* LCD Segment 47 enable. */ + +// LCDBPCTL3 +#define LCDS48 (0x0001u) /* LCD Segment 48 enable. */ +#define LCDS49 (0x0002u) /* LCD Segment 49 enable. */ +#define LCDS50 (0x0004u) /* LCD Segment 50 enable. */ + +// LCDBPCTL3 +#define LCDS48_L (0x0001u) /* LCD Segment 48 enable. */ +#define LCDS49_L (0x0002u) /* LCD Segment 49 enable. */ +#define LCDS50_L (0x0004u) /* LCD Segment 50 enable. */ + +// LCDBCPCTL +#define LCDCPDIS0 (0x0001u) /* LCD charge pump disable */ +#define LCDCPDIS1 (0x0002u) /* LCD charge pump disable */ +#define LCDCPDIS2 (0x0004u) /* LCD charge pump disable */ +#define LCDCPDIS3 (0x0008u) /* LCD charge pump disable */ +#define LCDCPDIS4 (0x0010u) /* LCD charge pump disable */ +#define LCDCPDIS5 (0x0020u) /* LCD charge pump disable */ +#define LCDCPDIS6 (0x0040u) /* LCD charge pump disable */ +#define LCDCPDIS7 (0x0080u) /* LCD charge pump disable */ +#define LCDCPCLKSYNC (0x8000u) /* LCD charge pump clock synchronization */ + +// LCDBCPCTL +#define LCDCPDIS0_L (0x0001u) /* LCD charge pump disable */ +#define LCDCPDIS1_L (0x0002u) /* LCD charge pump disable */ +#define LCDCPDIS2_L (0x0004u) /* LCD charge pump disable */ +#define LCDCPDIS3_L (0x0008u) /* LCD charge pump disable */ +#define LCDCPDIS4_L (0x0010u) /* LCD charge pump disable */ +#define LCDCPDIS5_L (0x0020u) /* LCD charge pump disable */ +#define LCDCPDIS6_L (0x0040u) /* LCD charge pump disable */ +#define LCDCPDIS7_L (0x0080u) /* LCD charge pump disable */ + +// LCDBCPCTL +#define LCDCPCLKSYNC_H (0x0080u) /* LCD charge pump clock synchronization */ + +#define OFS_LCDM1 (0x0020u) /* LCD Memory 1 */ +#define LCDMEM_ LCDM1 /* LCD Memory */ +#ifndef __IAR_SYSTEMS_ICC__ +#define LCDMEM LCDM1 /* LCD Memory (for assembler) */ +#else +#define LCDMEM ((char*) &LCDM1) /* LCD Memory (for C) */ +#endif +#define OFS_LCDM2 (0x0021u) /* LCD Memory 2 */ +#define OFS_LCDM3 (0x0022u) /* LCD Memory 3 */ +#define OFS_LCDM4 (0x0023u) /* LCD Memory 4 */ +#define OFS_LCDM5 (0x0024u) /* LCD Memory 5 */ +#define OFS_LCDM6 (0x0025u) /* LCD Memory 6 */ +#define OFS_LCDM7 (0x0026u) /* LCD Memory 7 */ +#define OFS_LCDM8 (0x0027u) /* LCD Memory 8 */ +#define OFS_LCDM9 (0x0028u) /* LCD Memory 9 */ +#define OFS_LCDM10 (0x0029u) /* LCD Memory 10 */ +#define OFS_LCDM11 (0x002Au) /* LCD Memory 11 */ +#define OFS_LCDM12 (0x002Bu) /* LCD Memory 12 */ +#define OFS_LCDM13 (0x002Cu) /* LCD Memory 13 */ +#define OFS_LCDM14 (0x002Du) /* LCD Memory 14 */ +#define OFS_LCDM15 (0x002Eu) /* LCD Memory 15 */ +#define OFS_LCDM16 (0x002Fu) /* LCD Memory 16 */ +#define OFS_LCDM17 (0x0030u) /* LCD Memory 17 */ +#define OFS_LCDM18 (0x0031u) /* LCD Memory 18 */ +#define OFS_LCDM19 (0x0032u) /* LCD Memory 19 */ +#define OFS_LCDM20 (0x0033u) /* LCD Memory 20 */ +#define OFS_LCDM21 (0x0034u) /* LCD Memory 21 */ +#define OFS_LCDM22 (0x0035u) /* LCD Memory 22 */ +#define OFS_LCDM23 (0x0036u) /* LCD Memory 23 */ +#define OFS_LCDM24 (0x0037u) /* LCD Memory 24 */ + +#define OFS_LCDBM1 (0x0040u) /* LCD Blinking Memory 1 */ +#define LCDBMEM_ LCDBM1 /* LCD Blinking Memory */ +#ifndef __IAR_SYSTEMS_ICC__ +#define LCDBMEM (LCDBM1) /* LCD Blinking Memory (for assembler) */ +#else +#define LCDBMEM ((char*) &LCDBM1) /* LCD Blinking Memory (for C) */ +#endif +#define OFS_LCDBM2 (0x0041u) /* LCD Blinking Memory 2 */ +#define OFS_LCDBM3 (0x0042u) /* LCD Blinking Memory 3 */ +#define OFS_LCDBM4 (0x0043u) /* LCD Blinking Memory 4 */ +#define OFS_LCDBM5 (0x0044u) /* LCD Blinking Memory 5 */ +#define OFS_LCDBM6 (0x0045u) /* LCD Blinking Memory 6 */ +#define OFS_LCDBM7 (0x0046u) /* LCD Blinking Memory 7 */ +#define OFS_LCDBM8 (0x0047u) /* LCD Blinking Memory 8 */ +#define OFS_LCDBM9 (0x0048u) /* LCD Blinking Memory 9 */ +#define OFS_LCDBM10 (0x0049u) /* LCD Blinking Memory 10 */ +#define OFS_LCDBM11 (0x004Au) /* LCD Blinking Memory 11 */ +#define OFS_LCDBM12 (0x004Bu) /* LCD Blinking Memory 12 */ +#define OFS_LCDBM13 (0x004Cu) /* LCD Blinking Memory 13 */ +#define OFS_LCDBM14 (0x004Du) /* LCD Blinking Memory 14 */ +#define OFS_LCDBM15 (0x004Eu) /* LCD Blinking Memory 15 */ +#define OFS_LCDBM16 (0x004Fu) /* LCD Blinking Memory 16 */ +#define OFS_LCDBM17 (0x0050u) /* LCD Blinking Memory 17 */ +#define OFS_LCDBM18 (0x0051u) /* LCD Blinking Memory 18 */ +#define OFS_LCDBM19 (0x0052u) /* LCD Blinking Memory 19 */ +#define OFS_LCDBM20 (0x0053u) /* LCD Blinking Memory 20 */ +#define OFS_LCDBM21 (0x0054u) /* LCD Blinking Memory 21 */ +#define OFS_LCDBM22 (0x0055u) /* LCD Blinking Memory 22 */ +#define OFS_LCDBM23 (0x0056u) /* LCD Blinking Memory 23 */ +#define OFS_LCDBM24 (0x0057u) /* LCD Blinking Memory 24 */ + +/* LCDBIV Definitions */ +#define LCDBIV_NONE (0x0000u) /* No Interrupt pending */ +#define LCDBIV_LCDNOCAPIFG (0x0002u) /* No capacitor connected */ +#define LCDBIV_LCDBLKOFFIFG (0x0004u) /* Blink, segments off */ +#define LCDBIV_LCDBLKONIFG (0x0006u) /* Blink, segments on */ +#define LCDBIV_LCDFRMIFG (0x0008u) /* Frame interrupt */ + +#endif +/************************************************************ +* LCD_C +************************************************************/ +#ifdef __MSP430_HAS_LCD_C__ /* Definition to show that Module is available */ + +#define OFS_LCDCCTL0 (0x0000u) /* LCD_C Control Register 0 */ +#define OFS_LCDCCTL0_L OFS_LCDCCTL0 +#define OFS_LCDCCTL0_H OFS_LCDCCTL0+1 +#define OFS_LCDCCTL1 (0x0002u) /* LCD_C Control Register 1 */ +#define OFS_LCDCCTL1_L OFS_LCDCCTL1 +#define OFS_LCDCCTL1_H OFS_LCDCCTL1+1 +#define OFS_LCDCBLKCTL (0x0004u) /* LCD_C blinking control register */ +#define OFS_LCDCBLKCTL_L OFS_LCDCBLKCTL +#define OFS_LCDCBLKCTL_H OFS_LCDCBLKCTL+1 +#define OFS_LCDCMEMCTL (0x0006u) /* LCD_C memory control register */ +#define OFS_LCDCMEMCTL_L OFS_LCDCMEMCTL +#define OFS_LCDCMEMCTL_H OFS_LCDCMEMCTL+1 +#define OFS_LCDCVCTL (0x0008u) /* LCD_C Voltage Control Register */ +#define OFS_LCDCVCTL_L OFS_LCDCVCTL +#define OFS_LCDCVCTL_H OFS_LCDCVCTL+1 +#define OFS_LCDCPCTL0 (0x000Au) /* LCD_C Port Control Register 0 */ +#define OFS_LCDCPCTL0_L OFS_LCDCPCTL0 +#define OFS_LCDCPCTL0_H OFS_LCDCPCTL0+1 +#define OFS_LCDCPCTL1 (0x000Cu) /* LCD_C Port Control Register 1 */ +#define OFS_LCDCPCTL1_L OFS_LCDCPCTL1 +#define OFS_LCDCPCTL1_H OFS_LCDCPCTL1+1 +#define OFS_LCDCPCTL2 (0x000Eu) /* LCD_C Port Control Register 2 */ +#define OFS_LCDCPCTL2_L OFS_LCDCPCTL2 +#define OFS_LCDCPCTL2_H OFS_LCDCPCTL2+1 +#define OFS_LCDCCPCTL (0x0012u) /* LCD_C Charge Pump Control Register 3 */ +#define OFS_LCDCCPCTL_L OFS_LCDCCPCTL +#define OFS_LCDCCPCTL_H OFS_LCDCCPCTL+1 +#define OFS_LCDCIV (0x001Eu) /* LCD_C Interrupt Vector Register */ + +// LCDCCTL0 +#define LCDON (0x0001u) /* LCD_C LCD On */ +#define LCDLP (0x0002u) /* LCD_C Low Power Waveform */ +#define LCDSON (0x0004u) /* LCD_C LCD Segments On */ +#define LCDMX0 (0x0008u) /* LCD_C Mux Rate Bit: 0 */ +#define LCDMX1 (0x0010u) /* LCD_C Mux Rate Bit: 1 */ +#define LCDMX2 (0x0020u) /* LCD_C Mux Rate Bit: 2 */ +//#define RESERVED (0x0040u) /* LCD_C RESERVED */ +#define LCDSSEL (0x0080u) /* LCD_C Clock Select */ +#define LCDPRE0 (0x0100u) /* LCD_C LCD frequency pre-scaler Bit: 0 */ +#define LCDPRE1 (0x0200u) /* LCD_C LCD frequency pre-scaler Bit: 1 */ +#define LCDPRE2 (0x0400u) /* LCD_C LCD frequency pre-scaler Bit: 2 */ +#define LCDDIV0 (0x0800u) /* LCD_C LCD frequency divider Bit: 0 */ +#define LCDDIV1 (0x1000u) /* LCD_C LCD frequency divider Bit: 1 */ +#define LCDDIV2 (0x2000u) /* LCD_C LCD frequency divider Bit: 2 */ +#define LCDDIV3 (0x4000u) /* LCD_C LCD frequency divider Bit: 3 */ +#define LCDDIV4 (0x8000u) /* LCD_C LCD frequency divider Bit: 4 */ + +// LCDCCTL0 +#define LCDON_L (0x0001u) /* LCD_C LCD On */ +#define LCDLP_L (0x0002u) /* LCD_C Low Power Waveform */ +#define LCDSON_L (0x0004u) /* LCD_C LCD Segments On */ +#define LCDMX0_L (0x0008u) /* LCD_C Mux Rate Bit: 0 */ +#define LCDMX1_L (0x0010u) /* LCD_C Mux Rate Bit: 1 */ +#define LCDMX2_L (0x0020u) /* LCD_C Mux Rate Bit: 2 */ +//#define RESERVED (0x0040u) /* LCD_C RESERVED */ +#define LCDSSEL_L (0x0080u) /* LCD_C Clock Select */ + +// LCDCCTL0 +//#define RESERVED (0x0040u) /* LCD_C RESERVED */ +#define LCDPRE0_H (0x0001u) /* LCD_C LCD frequency pre-scaler Bit: 0 */ +#define LCDPRE1_H (0x0002u) /* LCD_C LCD frequency pre-scaler Bit: 1 */ +#define LCDPRE2_H (0x0004u) /* LCD_C LCD frequency pre-scaler Bit: 2 */ +#define LCDDIV0_H (0x0008u) /* LCD_C LCD frequency divider Bit: 0 */ +#define LCDDIV1_H (0x0010u) /* LCD_C LCD frequency divider Bit: 1 */ +#define LCDDIV2_H (0x0020u) /* LCD_C LCD frequency divider Bit: 2 */ +#define LCDDIV3_H (0x0040u) /* LCD_C LCD frequency divider Bit: 3 */ +#define LCDDIV4_H (0x0080u) /* LCD_C LCD frequency divider Bit: 4 */ + +#define LCDPRE_0 (0x0000u) /* LCD_C LCD frequency pre-scaler: /1 */ +#define LCDPRE_1 (0x0100u) /* LCD_C LCD frequency pre-scaler: /2 */ +#define LCDPRE_2 (0x0200u) /* LCD_C LCD frequency pre-scaler: /4 */ +#define LCDPRE_3 (0x0300u) /* LCD_C LCD frequency pre-scaler: /8 */ +#define LCDPRE_4 (0x0400u) /* LCD_C LCD frequency pre-scaler: /16 */ +#define LCDPRE_5 (0x0500u) /* LCD_C LCD frequency pre-scaler: /32 */ +#define LCDPRE__1 (0x0000u) /* LCD_C LCD frequency pre-scaler: /1 */ +#define LCDPRE__2 (0x0100u) /* LCD_C LCD frequency pre-scaler: /2 */ +#define LCDPRE__4 (0x0200u) /* LCD_C LCD frequency pre-scaler: /4 */ +#define LCDPRE__8 (0x0300u) /* LCD_C LCD frequency pre-scaler: /8 */ +#define LCDPRE__16 (0x0400u) /* LCD_C LCD frequency pre-scaler: /16 */ +#define LCDPRE__32 (0x0500u) /* LCD_C LCD frequency pre-scaler: /32 */ + +#define LCDDIV_0 (0x0000u) /* LCD_C LCD frequency divider: /1 */ +#define LCDDIV_1 (0x0800u) /* LCD_C LCD frequency divider: /2 */ +#define LCDDIV_2 (0x1000u) /* LCD_C LCD frequency divider: /3 */ +#define LCDDIV_3 (0x1800u) /* LCD_C LCD frequency divider: /4 */ +#define LCDDIV_4 (0x2000u) /* LCD_C LCD frequency divider: /5 */ +#define LCDDIV_5 (0x2800u) /* LCD_C LCD frequency divider: /6 */ +#define LCDDIV_6 (0x3000u) /* LCD_C LCD frequency divider: /7 */ +#define LCDDIV_7 (0x3800u) /* LCD_C LCD frequency divider: /8 */ +#define LCDDIV_8 (0x4000u) /* LCD_C LCD frequency divider: /9 */ +#define LCDDIV_9 (0x4800u) /* LCD_C LCD frequency divider: /10 */ +#define LCDDIV_10 (0x5000u) /* LCD_C LCD frequency divider: /11 */ +#define LCDDIV_11 (0x5800u) /* LCD_C LCD frequency divider: /12 */ +#define LCDDIV_12 (0x6000u) /* LCD_C LCD frequency divider: /13 */ +#define LCDDIV_13 (0x6800u) /* LCD_C LCD frequency divider: /14 */ +#define LCDDIV_14 (0x7000u) /* LCD_C LCD frequency divider: /15 */ +#define LCDDIV_15 (0x7800u) /* LCD_C LCD frequency divider: /16 */ +#define LCDDIV_16 (0x8000u) /* LCD_C LCD frequency divider: /17 */ +#define LCDDIV_17 (0x8800u) /* LCD_C LCD frequency divider: /18 */ +#define LCDDIV_18 (0x9000u) /* LCD_C LCD frequency divider: /19 */ +#define LCDDIV_19 (0x9800u) /* LCD_C LCD frequency divider: /20 */ +#define LCDDIV_20 (0xA000u) /* LCD_C LCD frequency divider: /21 */ +#define LCDDIV_21 (0xA800u) /* LCD_C LCD frequency divider: /22 */ +#define LCDDIV_22 (0xB000u) /* LCD_C LCD frequency divider: /23 */ +#define LCDDIV_23 (0xB800u) /* LCD_C LCD frequency divider: /24 */ +#define LCDDIV_24 (0xC000u) /* LCD_C LCD frequency divider: /25 */ +#define LCDDIV_25 (0xC800u) /* LCD_C LCD frequency divider: /26 */ +#define LCDDIV_26 (0xD000u) /* LCD_C LCD frequency divider: /27 */ +#define LCDDIV_27 (0xD800u) /* LCD_C LCD frequency divider: /28 */ +#define LCDDIV_28 (0xE000u) /* LCD_C LCD frequency divider: /29 */ +#define LCDDIV_29 (0xE800u) /* LCD_C LCD frequency divider: /30 */ +#define LCDDIV_30 (0xF000u) /* LCD_C LCD frequency divider: /31 */ +#define LCDDIV_31 (0xF800u) /* LCD_C LCD frequency divider: /32 */ +#define LCDDIV__1 (0x0000u) /* LCD_C LCD frequency divider: /1 */ +#define LCDDIV__2 (0x0800u) /* LCD_C LCD frequency divider: /2 */ +#define LCDDIV__3 (0x1000u) /* LCD_C LCD frequency divider: /3 */ +#define LCDDIV__4 (0x1800u) /* LCD_C LCD frequency divider: /4 */ +#define LCDDIV__5 (0x2000u) /* LCD_C LCD frequency divider: /5 */ +#define LCDDIV__6 (0x2800u) /* LCD_C LCD frequency divider: /6 */ +#define LCDDIV__7 (0x3000u) /* LCD_C LCD frequency divider: /7 */ +#define LCDDIV__8 (0x3800u) /* LCD_C LCD frequency divider: /8 */ +#define LCDDIV__9 (0x4000u) /* LCD_C LCD frequency divider: /9 */ +#define LCDDIV__10 (0x4800u) /* LCD_C LCD frequency divider: /10 */ +#define LCDDIV__11 (0x5000u) /* LCD_C LCD frequency divider: /11 */ +#define LCDDIV__12 (0x5800u) /* LCD_C LCD frequency divider: /12 */ +#define LCDDIV__13 (0x6000u) /* LCD_C LCD frequency divider: /13 */ +#define LCDDIV__14 (0x6800u) /* LCD_C LCD frequency divider: /14 */ +#define LCDDIV__15 (0x7000u) /* LCD_C LCD frequency divider: /15 */ +#define LCDDIV__16 (0x7800u) /* LCD_C LCD frequency divider: /16 */ +#define LCDDIV__17 (0x8000u) /* LCD_C LCD frequency divider: /17 */ +#define LCDDIV__18 (0x8800u) /* LCD_C LCD frequency divider: /18 */ +#define LCDDIV__19 (0x9000u) /* LCD_C LCD frequency divider: /19 */ +#define LCDDIV__20 (0x9800u) /* LCD_C LCD frequency divider: /20 */ +#define LCDDIV__21 (0xA000u) /* LCD_C LCD frequency divider: /21 */ +#define LCDDIV__22 (0xA800u) /* LCD_C LCD frequency divider: /22 */ +#define LCDDIV__23 (0xB000u) /* LCD_C LCD frequency divider: /23 */ +#define LCDDIV__24 (0xB800u) /* LCD_C LCD frequency divider: /24 */ +#define LCDDIV__25 (0xC000u) /* LCD_C LCD frequency divider: /25 */ +#define LCDDIV__26 (0xC800u) /* LCD_C LCD frequency divider: /26 */ +#define LCDDIV__27 (0xD000u) /* LCD_C LCD frequency divider: /27 */ +#define LCDDIV__28 (0xD800u) /* LCD_C LCD frequency divider: /28 */ +#define LCDDIV__29 (0xE000u) /* LCD_C LCD frequency divider: /29 */ +#define LCDDIV__30 (0xE800u) /* LCD_C LCD frequency divider: /30 */ +#define LCDDIV__31 (0xF000u) /* LCD_C LCD frequency divider: /31 */ +#define LCDDIV__32 (0xF800u) /* LCD_C LCD frequency divider: /32 */ + +/* Display modes coded with Bits 2-4 */ +#define LCDSTATIC (LCDSON) +#define LCD2MUX (LCDMX0+LCDSON) +#define LCD3MUX (LCDMX1+LCDSON) +#define LCD4MUX (LCDMX1+LCDMX0+LCDSON) +#define LCD5MUX (LCDMX2+LCDSON) +#define LCD6MUX (LCDMX2+LCDMX0+LCDSON) +#define LCD7MUX (LCDMX2+LCDMX1+LCDSON) +#define LCD8MUX (LCDMX2+LCDMX1+LCDMX0+LCDSON) + +// LCDCCTL1 +#define LCDFRMIFG (0x0001u) /* LCD_C LCD frame interrupt flag */ +#define LCDBLKOFFIFG (0x0002u) /* LCD_C LCD blinking off interrupt flag, */ +#define LCDBLKONIFG (0x0004u) /* LCD_C LCD blinking on interrupt flag, */ +#define LCDNOCAPIFG (0x0008u) /* LCD_C No cpacitance connected interrupt flag */ +#define LCDFRMIE (0x0100u) /* LCD_C LCD frame interrupt enable */ +#define LCDBLKOFFIE (0x0200u) /* LCD_C LCD blinking off interrupt flag, */ +#define LCDBLKONIE (0x0400u) /* LCD_C LCD blinking on interrupt flag, */ +#define LCDNOCAPIE (0x0800u) /* LCD_C No cpacitance connected interrupt enable */ + +// LCDCCTL1 +#define LCDFRMIFG_L (0x0001u) /* LCD_C LCD frame interrupt flag */ +#define LCDBLKOFFIFG_L (0x0002u) /* LCD_C LCD blinking off interrupt flag, */ +#define LCDBLKONIFG_L (0x0004u) /* LCD_C LCD blinking on interrupt flag, */ +#define LCDNOCAPIFG_L (0x0008u) /* LCD_C No cpacitance connected interrupt flag */ + +// LCDCCTL1 +#define LCDFRMIE_H (0x0001u) /* LCD_C LCD frame interrupt enable */ +#define LCDBLKOFFIE_H (0x0002u) /* LCD_C LCD blinking off interrupt flag, */ +#define LCDBLKONIE_H (0x0004u) /* LCD_C LCD blinking on interrupt flag, */ +#define LCDNOCAPIE_H (0x0008u) /* LCD_C No cpacitance connected interrupt enable */ + +// LCDCBLKCTL +#define LCDBLKMOD0 (0x0001u) /* LCD_C Blinking mode Bit: 0 */ +#define LCDBLKMOD1 (0x0002u) /* LCD_C Blinking mode Bit: 1 */ +#define LCDBLKPRE0 (0x0004u) /* LCD_C Clock pre-scaler for blinking frequency Bit: 0 */ +#define LCDBLKPRE1 (0x0008u) /* LCD_C Clock pre-scaler for blinking frequency Bit: 1 */ +#define LCDBLKPRE2 (0x0010u) /* LCD_C Clock pre-scaler for blinking frequency Bit: 2 */ +#define LCDBLKDIV0 (0x0020u) /* LCD_C Clock divider for blinking frequency Bit: 0 */ +#define LCDBLKDIV1 (0x0040u) /* LCD_C Clock divider for blinking frequency Bit: 1 */ +#define LCDBLKDIV2 (0x0080u) /* LCD_C Clock divider for blinking frequency Bit: 2 */ + +// LCDCBLKCTL +#define LCDBLKMOD0_L (0x0001u) /* LCD_C Blinking mode Bit: 0 */ +#define LCDBLKMOD1_L (0x0002u) /* LCD_C Blinking mode Bit: 1 */ +#define LCDBLKPRE0_L (0x0004u) /* LCD_C Clock pre-scaler for blinking frequency Bit: 0 */ +#define LCDBLKPRE1_L (0x0008u) /* LCD_C Clock pre-scaler for blinking frequency Bit: 1 */ +#define LCDBLKPRE2_L (0x0010u) /* LCD_C Clock pre-scaler for blinking frequency Bit: 2 */ +#define LCDBLKDIV0_L (0x0020u) /* LCD_C Clock divider for blinking frequency Bit: 0 */ +#define LCDBLKDIV1_L (0x0040u) /* LCD_C Clock divider for blinking frequency Bit: 1 */ +#define LCDBLKDIV2_L (0x0080u) /* LCD_C Clock divider for blinking frequency Bit: 2 */ + +#define LCDBLKMOD_0 (0x0000u) /* LCD_C Blinking mode: Off */ +#define LCDBLKMOD_1 (0x0001u) /* LCD_C Blinking mode: Individual */ +#define LCDBLKMOD_2 (0x0002u) /* LCD_C Blinking mode: All */ +#define LCDBLKMOD_3 (0x0003u) /* LCD_C Blinking mode: Switching */ + +// LCDCMEMCTL +#define LCDDISP (0x0001u) /* LCD_C LCD memory registers for display */ +#define LCDCLRM (0x0002u) /* LCD_C Clear LCD memory */ +#define LCDCLRBM (0x0004u) /* LCD_C Clear LCD blinking memory */ + +// LCDCMEMCTL +#define LCDDISP_L (0x0001u) /* LCD_C LCD memory registers for display */ +#define LCDCLRM_L (0x0002u) /* LCD_C Clear LCD memory */ +#define LCDCLRBM_L (0x0004u) /* LCD_C Clear LCD blinking memory */ + +// LCDCVCTL +#define LCD2B (0x0001u) /* Selects 1/2 bias. */ +#define VLCDREF0 (0x0002u) /* Selects reference voltage for regulated charge pump: 0 */ +#define VLCDREF1 (0x0004u) /* Selects reference voltage for regulated charge pump: 1 */ +#define LCDCPEN (0x0008u) /* LCD Voltage Charge Pump Enable. */ +#define VLCDEXT (0x0010u) /* Select external source for VLCD. */ +#define LCDEXTBIAS (0x0020u) /* V2 - V4 voltage select. */ +#define R03EXT (0x0040u) /* Selects external connections for LCD mid voltages. */ +#define LCDREXT (0x0080u) /* Selects external connection for lowest LCD voltage. */ +#define VLCD0 (0x0200u) /* VLCD select: 0 */ +#define VLCD1 (0x0400u) /* VLCD select: 1 */ +#define VLCD2 (0x0800u) /* VLCD select: 2 */ +#define VLCD3 (0x1000u) /* VLCD select: 3 */ +#define VLCD4 (0x2000u) /* VLCD select: 4 */ +#define VLCD5 (0x4000u) /* VLCD select: 5 */ + +// LCDCVCTL +#define LCD2B_L (0x0001u) /* Selects 1/2 bias. */ +#define VLCDREF0_L (0x0002u) /* Selects reference voltage for regulated charge pump: 0 */ +#define VLCDREF1_L (0x0004u) /* Selects reference voltage for regulated charge pump: 1 */ +#define LCDCPEN_L (0x0008u) /* LCD Voltage Charge Pump Enable. */ +#define VLCDEXT_L (0x0010u) /* Select external source for VLCD. */ +#define LCDEXTBIAS_L (0x0020u) /* V2 - V4 voltage select. */ +#define R03EXT_L (0x0040u) /* Selects external connections for LCD mid voltages. */ +#define LCDREXT_L (0x0080u) /* Selects external connection for lowest LCD voltage. */ + +// LCDCVCTL +#define VLCD0_H (0x0002u) /* VLCD select: 0 */ +#define VLCD1_H (0x0004u) /* VLCD select: 1 */ +#define VLCD2_H (0x0008u) /* VLCD select: 2 */ +#define VLCD3_H (0x0010u) /* VLCD select: 3 */ +#define VLCD4_H (0x0020u) /* VLCD select: 4 */ +#define VLCD5_H (0x0040u) /* VLCD select: 5 */ + +/* Reference voltage source select for the regulated charge pump */ +#define VLCDREF_0 (0x0000u) /* Internal */ +#define VLCDREF_1 (0x0002u) /* External */ +#define VLCDREF_2 (0x0004u) /* Reserved */ +#define VLCDREF_3 (0x0006u) /* Reserved */ + +/* Charge pump voltage selections */ +#define VLCD_0 (0x0000u) /* Charge pump disabled */ +#define VLCD_1 (0x0200u) /* VLCD = 2.60V */ +#define VLCD_2 (0x0400u) /* VLCD = 2.66V */ +#define VLCD_3 (0x0600u) /* VLCD = 2.72V */ +#define VLCD_4 (0x0800u) /* VLCD = 2.78V */ +#define VLCD_5 (0x0A00u) /* VLCD = 2.84V */ +#define VLCD_6 (0x0C00u) /* VLCD = 2.90V */ +#define VLCD_7 (0x0E00u) /* VLCD = 2.96V */ +#define VLCD_8 (0x1000u) /* VLCD = 3.02V */ +#define VLCD_9 (0x1200u) /* VLCD = 3.08V */ +#define VLCD_10 (0x1400u) /* VLCD = 3.14V */ +#define VLCD_11 (0x1600u) /* VLCD = 3.20V */ +#define VLCD_12 (0x1800u) /* VLCD = 3.26V */ +#define VLCD_13 (0x1A00u) /* VLCD = 3.32V */ +#define VLCD_14 (0x1C00u) /* VLCD = 3.38V */ +#define VLCD_15 (0x1E00u) /* VLCD = 3.44V */ + +#define VLCD_DISABLED (0x0000u) /* Charge pump disabled */ +#define VLCD_2_60 (0x0200u) /* VLCD = 2.60V */ +#define VLCD_2_66 (0x0400u) /* VLCD = 2.66V */ +#define VLCD_2_72 (0x0600u) /* VLCD = 2.72V */ +#define VLCD_2_78 (0x0800u) /* VLCD = 2.78V */ +#define VLCD_2_84 (0x0A00u) /* VLCD = 2.84V */ +#define VLCD_2_90 (0x0C00u) /* VLCD = 2.90V */ +#define VLCD_2_96 (0x0E00u) /* VLCD = 2.96V */ +#define VLCD_3_02 (0x1000u) /* VLCD = 3.02V */ +#define VLCD_3_08 (0x1200u) /* VLCD = 3.08V */ +#define VLCD_3_14 (0x1400u) /* VLCD = 3.14V */ +#define VLCD_3_20 (0x1600u) /* VLCD = 3.20V */ +#define VLCD_3_26 (0x1800u) /* VLCD = 3.26V */ +#define VLCD_3_32 (0x1A00u) /* VLCD = 3.32V */ +#define VLCD_3_38 (0x1C00u) /* VLCD = 3.38V */ +#define VLCD_3_44 (0x1E00u) /* VLCD = 3.44V */ + +// LCDCPCTL0 +#define LCDS0 (0x0001u) /* LCD Segment 0 enable. */ +#define LCDS1 (0x0002u) /* LCD Segment 1 enable. */ +#define LCDS2 (0x0004u) /* LCD Segment 2 enable. */ +#define LCDS3 (0x0008u) /* LCD Segment 3 enable. */ +#define LCDS4 (0x0010u) /* LCD Segment 4 enable. */ +#define LCDS5 (0x0020u) /* LCD Segment 5 enable. */ +#define LCDS6 (0x0040u) /* LCD Segment 6 enable. */ +#define LCDS7 (0x0080u) /* LCD Segment 7 enable. */ +#define LCDS8 (0x0100u) /* LCD Segment 8 enable. */ +#define LCDS9 (0x0200u) /* LCD Segment 9 enable. */ +#define LCDS10 (0x0400u) /* LCD Segment 10 enable. */ +#define LCDS11 (0x0800u) /* LCD Segment 11 enable. */ +#define LCDS12 (0x1000u) /* LCD Segment 12 enable. */ +#define LCDS13 (0x2000u) /* LCD Segment 13 enable. */ +#define LCDS14 (0x4000u) /* LCD Segment 14 enable. */ +#define LCDS15 (0x8000u) /* LCD Segment 15 enable. */ + +// LCDCPCTL0 +#define LCDS0_L (0x0001u) /* LCD Segment 0 enable. */ +#define LCDS1_L (0x0002u) /* LCD Segment 1 enable. */ +#define LCDS2_L (0x0004u) /* LCD Segment 2 enable. */ +#define LCDS3_L (0x0008u) /* LCD Segment 3 enable. */ +#define LCDS4_L (0x0010u) /* LCD Segment 4 enable. */ +#define LCDS5_L (0x0020u) /* LCD Segment 5 enable. */ +#define LCDS6_L (0x0040u) /* LCD Segment 6 enable. */ +#define LCDS7_L (0x0080u) /* LCD Segment 7 enable. */ + +// LCDCPCTL0 +#define LCDS8_H (0x0001u) /* LCD Segment 8 enable. */ +#define LCDS9_H (0x0002u) /* LCD Segment 9 enable. */ +#define LCDS10_H (0x0004u) /* LCD Segment 10 enable. */ +#define LCDS11_H (0x0008u) /* LCD Segment 11 enable. */ +#define LCDS12_H (0x0010u) /* LCD Segment 12 enable. */ +#define LCDS13_H (0x0020u) /* LCD Segment 13 enable. */ +#define LCDS14_H (0x0040u) /* LCD Segment 14 enable. */ +#define LCDS15_H (0x0080u) /* LCD Segment 15 enable. */ + +// LCDCPCTL1 +#define LCDS16 (0x0001u) /* LCD Segment 16 enable. */ +#define LCDS17 (0x0002u) /* LCD Segment 17 enable. */ +#define LCDS18 (0x0004u) /* LCD Segment 18 enable. */ +#define LCDS19 (0x0008u) /* LCD Segment 19 enable. */ +#define LCDS20 (0x0010u) /* LCD Segment 20 enable. */ +#define LCDS21 (0x0020u) /* LCD Segment 21 enable. */ +#define LCDS22 (0x0040u) /* LCD Segment 22 enable. */ +#define LCDS23 (0x0080u) /* LCD Segment 23 enable. */ +#define LCDS24 (0x0100u) /* LCD Segment 24 enable. */ +#define LCDS25 (0x0200u) /* LCD Segment 25 enable. */ +#define LCDS26 (0x0400u) /* LCD Segment 26 enable. */ +#define LCDS27 (0x0800u) /* LCD Segment 27 enable. */ +#define LCDS28 (0x1000u) /* LCD Segment 28 enable. */ +#define LCDS29 (0x2000u) /* LCD Segment 29 enable. */ +#define LCDS30 (0x4000u) /* LCD Segment 30 enable. */ +#define LCDS31 (0x8000u) /* LCD Segment 31 enable. */ + +// LCDCPCTL1 +#define LCDS16_L (0x0001u) /* LCD Segment 16 enable. */ +#define LCDS17_L (0x0002u) /* LCD Segment 17 enable. */ +#define LCDS18_L (0x0004u) /* LCD Segment 18 enable. */ +#define LCDS19_L (0x0008u) /* LCD Segment 19 enable. */ +#define LCDS20_L (0x0010u) /* LCD Segment 20 enable. */ +#define LCDS21_L (0x0020u) /* LCD Segment 21 enable. */ +#define LCDS22_L (0x0040u) /* LCD Segment 22 enable. */ +#define LCDS23_L (0x0080u) /* LCD Segment 23 enable. */ + +// LCDCPCTL1 +#define LCDS24_H (0x0001u) /* LCD Segment 24 enable. */ +#define LCDS25_H (0x0002u) /* LCD Segment 25 enable. */ +#define LCDS26_H (0x0004u) /* LCD Segment 26 enable. */ +#define LCDS27_H (0x0008u) /* LCD Segment 27 enable. */ +#define LCDS28_H (0x0010u) /* LCD Segment 28 enable. */ +#define LCDS29_H (0x0020u) /* LCD Segment 29 enable. */ +#define LCDS30_H (0x0040u) /* LCD Segment 30 enable. */ +#define LCDS31_H (0x0080u) /* LCD Segment 31 enable. */ + +// LCDCPCTL2 +#define LCDS32 (0x0001u) /* LCD Segment 32 enable. */ +#define LCDS33 (0x0002u) /* LCD Segment 33 enable. */ +#define LCDS34 (0x0004u) /* LCD Segment 34 enable. */ +#define LCDS35 (0x0008u) /* LCD Segment 35 enable. */ +#define LCDS36 (0x0010u) /* LCD Segment 36 enable. */ +#define LCDS37 (0x0020u) /* LCD Segment 37 enable. */ +#define LCDS38 (0x0040u) /* LCD Segment 38 enable. */ +#define LCDS39 (0x0080u) /* LCD Segment 39 enable. */ +#define LCDS40 (0x0100u) /* LCD Segment 40 enable. */ +#define LCDS41 (0x0200u) /* LCD Segment 41 enable. */ +#define LCDS42 (0x0400u) /* LCD Segment 42 enable. */ +#define LCDS43 (0x0800u) /* LCD Segment 43 enable. */ +#define LCDS44 (0x1000u) /* LCD Segment 44 enable. */ +#define LCDS45 (0x2000u) /* LCD Segment 45 enable. */ +#define LCDS46 (0x4000u) /* LCD Segment 46 enable. */ +#define LCDS47 (0x8000u) /* LCD Segment 47 enable. */ + +// LCDCPCTL2 +#define LCDS32_L (0x0001u) /* LCD Segment 32 enable. */ +#define LCDS33_L (0x0002u) /* LCD Segment 33 enable. */ +#define LCDS34_L (0x0004u) /* LCD Segment 34 enable. */ +#define LCDS35_L (0x0008u) /* LCD Segment 35 enable. */ +#define LCDS36_L (0x0010u) /* LCD Segment 36 enable. */ +#define LCDS37_L (0x0020u) /* LCD Segment 37 enable. */ +#define LCDS38_L (0x0040u) /* LCD Segment 38 enable. */ +#define LCDS39_L (0x0080u) /* LCD Segment 39 enable. */ + +// LCDCPCTL2 +#define LCDS40_H (0x0001u) /* LCD Segment 40 enable. */ +#define LCDS41_H (0x0002u) /* LCD Segment 41 enable. */ +#define LCDS42_H (0x0004u) /* LCD Segment 42 enable. */ +#define LCDS43_H (0x0008u) /* LCD Segment 43 enable. */ +#define LCDS44_H (0x0010u) /* LCD Segment 44 enable. */ +#define LCDS45_H (0x0020u) /* LCD Segment 45 enable. */ +#define LCDS46_H (0x0040u) /* LCD Segment 46 enable. */ +#define LCDS47_H (0x0080u) /* LCD Segment 47 enable. */ + +// LCDCCPCTL +#define LCDCPDIS0 (0x0001u) /* LCD charge pump disable */ +#define LCDCPDIS1 (0x0002u) /* LCD charge pump disable */ +#define LCDCPDIS2 (0x0004u) /* LCD charge pump disable */ +#define LCDCPDIS3 (0x0008u) /* LCD charge pump disable */ +#define LCDCPDIS4 (0x0010u) /* LCD charge pump disable */ +#define LCDCPDIS5 (0x0020u) /* LCD charge pump disable */ +#define LCDCPDIS6 (0x0040u) /* LCD charge pump disable */ +#define LCDCPDIS7 (0x0080u) /* LCD charge pump disable */ +#define LCDCPCLKSYNC (0x8000u) /* LCD charge pump clock synchronization */ + +// LCDCCPCTL +#define LCDCPDIS0_L (0x0001u) /* LCD charge pump disable */ +#define LCDCPDIS1_L (0x0002u) /* LCD charge pump disable */ +#define LCDCPDIS2_L (0x0004u) /* LCD charge pump disable */ +#define LCDCPDIS3_L (0x0008u) /* LCD charge pump disable */ +#define LCDCPDIS4_L (0x0010u) /* LCD charge pump disable */ +#define LCDCPDIS5_L (0x0020u) /* LCD charge pump disable */ +#define LCDCPDIS6_L (0x0040u) /* LCD charge pump disable */ +#define LCDCPDIS7_L (0x0080u) /* LCD charge pump disable */ + +// LCDCCPCTL +#define LCDCPCLKSYNC_H (0x0080u) /* LCD charge pump clock synchronization */ + +#define OFS_LCDM1 (0x0020u) /* LCD Memory 1 */ +#define LCDMEM_ LCDM1 /* LCD Memory */ +#ifndef __IAR_SYSTEMS_ICC__ +#define LCDMEM LCDM1 /* LCD Memory (for assembler) */ +#else +#define LCDMEM ((char*) &LCDM1) /* LCD Memory (for C) */ +#endif +#define OFS_LCDM2 (0x0021u) /* LCD Memory 2 */ +#define OFS_LCDM3 (0x0022u) /* LCD Memory 3 */ +#define OFS_LCDM4 (0x0023u) /* LCD Memory 4 */ +#define OFS_LCDM5 (0x0024u) /* LCD Memory 5 */ +#define OFS_LCDM6 (0x0025u) /* LCD Memory 6 */ +#define OFS_LCDM7 (0x0026u) /* LCD Memory 7 */ +#define OFS_LCDM8 (0x0027u) /* LCD Memory 8 */ +#define OFS_LCDM9 (0x0028u) /* LCD Memory 9 */ +#define OFS_LCDM10 (0x0029u) /* LCD Memory 10 */ +#define OFS_LCDM11 (0x002Au) /* LCD Memory 11 */ +#define OFS_LCDM12 (0x002Bu) /* LCD Memory 12 */ +#define OFS_LCDM13 (0x002Cu) /* LCD Memory 13 */ +#define OFS_LCDM14 (0x002Du) /* LCD Memory 14 */ +#define OFS_LCDM15 (0x002Eu) /* LCD Memory 15 */ +#define OFS_LCDM16 (0x002Fu) /* LCD Memory 16 */ +#define OFS_LCDM17 (0x0030u) /* LCD Memory 17 */ +#define OFS_LCDM18 (0x0031u) /* LCD Memory 18 */ +#define OFS_LCDM19 (0x0032u) /* LCD Memory 19 */ +#define OFS_LCDM20 (0x0033u) /* LCD Memory 20 */ +#define OFS_LCDM21 (0x0034u) /* LCD Memory 21 */ +#define OFS_LCDM22 (0x0035u) /* LCD Memory 22 */ +#define OFS_LCDM23 (0x0036u) /* LCD Memory 23 */ +#define OFS_LCDM24 (0x0037u) /* LCD Memory 24 */ +#define OFS_LCDM25 (0x0038u) /* LCD Memory 25 */ +#define OFS_LCDM26 (0x0039u) /* LCD Memory 26 */ +#define OFS_LCDM27 (0x003Au) /* LCD Memory 27 */ +#define OFS_LCDM28 (0x003Bu) /* LCD Memory 28 */ +#define OFS_LCDM29 (0x003Cu) /* LCD Memory 29 */ +#define OFS_LCDM30 (0x003Du) /* LCD Memory 30 */ +#define OFS_LCDM31 (0x003Eu) /* LCD Memory 31 */ +#define OFS_LCDM32 (0x003Fu) /* LCD Memory 32 */ +#define OFS_LCDM33 (0x0040u) /* LCD Memory 33 */ +#define OFS_LCDM34 (0x0041u) /* LCD Memory 34 */ +#define OFS_LCDM35 (0x0042u) /* LCD Memory 35 */ +#define OFS_LCDM36 (0x0043u) /* LCD Memory 36 */ +#define OFS_LCDM37 (0x0044u) /* LCD Memory 37 */ +#define OFS_LCDM38 (0x0045u) /* LCD Memory 38 */ +#define OFS_LCDM39 (0x0046u) /* LCD Memory 39 */ +#define OFS_LCDM40 (0x0047u) /* LCD Memory 40 */ + +#define OFS_LCDBM1 (0x0040u) /* LCD Blinking Memory 1 */ +#define LCDBMEM_ LCDBM1 /* LCD Blinking Memory */ +#ifndef __IAR_SYSTEMS_ICC__ +#define LCDBMEM (LCDBM1) /* LCD Blinking Memory (for assembler) */ +#else +#define LCDBMEM ((char*) &LCDBM1) /* LCD Blinking Memory (for C) */ +#endif +#define OFS_LCDBM2 (0x0041u) /* LCD Blinking Memory 2 */ +#define OFS_LCDBM3 (0x0042u) /* LCD Blinking Memory 3 */ +#define OFS_LCDBM4 (0x0043u) /* LCD Blinking Memory 4 */ +#define OFS_LCDBM5 (0x0044u) /* LCD Blinking Memory 5 */ +#define OFS_LCDBM6 (0x0045u) /* LCD Blinking Memory 6 */ +#define OFS_LCDBM7 (0x0046u) /* LCD Blinking Memory 7 */ +#define OFS_LCDBM8 (0x0047u) /* LCD Blinking Memory 8 */ +#define OFS_LCDBM9 (0x0048u) /* LCD Blinking Memory 9 */ +#define OFS_LCDBM10 (0x0049u) /* LCD Blinking Memory 10 */ +#define OFS_LCDBM11 (0x004Au) /* LCD Blinking Memory 11 */ +#define OFS_LCDBM12 (0x004Bu) /* LCD Blinking Memory 12 */ +#define OFS_LCDBM13 (0x004Cu) /* LCD Blinking Memory 13 */ +#define OFS_LCDBM14 (0x004Du) /* LCD Blinking Memory 14 */ +#define OFS_LCDBM15 (0x004Eu) /* LCD Blinking Memory 15 */ +#define OFS_LCDBM16 (0x004Fu) /* LCD Blinking Memory 16 */ +#define OFS_LCDBM17 (0x0050u) /* LCD Blinking Memory 17 */ +#define OFS_LCDBM18 (0x0051u) /* LCD Blinking Memory 18 */ +#define OFS_LCDBM19 (0x0052u) /* LCD Blinking Memory 19 */ +#define OFS_LCDBM20 (0x0053u) /* LCD Blinking Memory 20 */ + +/* LCDCIV Definitions */ +#define LCDCIV_NONE (0x0000u) /* No Interrupt pending */ +#define LCDCIV_LCDNOCAPIFG (0x0002u) /* No capacitor connected */ +#define LCDCIV_LCDCLKOFFIFG (0x0004u) /* Blink, segments off */ +#define LCDCIV_LCDCLKONIFG (0x0006u) /* Blink, segments on */ +#define LCDCIV_LCDFRMIFG (0x0008u) /* Frame interrupt */ + +#endif +/************************************************************ +* HARDWARE MULTIPLIER 32Bit +************************************************************/ +#ifdef __MSP430_HAS_MPY32__ /* Definition to show that Module is available */ + +#define OFS_MPY (0x0000u) /* Multiply Unsigned/Operand 1 */ +#define OFS_MPY_L OFS_MPY +#define OFS_MPY_H OFS_MPY+1 +#define OFS_MPYS (0x0002u) /* Multiply Signed/Operand 1 */ +#define OFS_MPYS_L OFS_MPYS +#define OFS_MPYS_H OFS_MPYS+1 +#define OFS_MAC (0x0004u) /* Multiply Unsigned and Accumulate/Operand 1 */ +#define OFS_MAC_L OFS_MAC +#define OFS_MAC_H OFS_MAC+1 +#define OFS_MACS (0x0006u) /* Multiply Signed and Accumulate/Operand 1 */ +#define OFS_MACS_L OFS_MACS +#define OFS_MACS_H OFS_MACS+1 +#define OFS_OP2 (0x0008u) /* Operand 2 */ +#define OFS_OP2_L OFS_OP2 +#define OFS_OP2_H OFS_OP2+1 +#define OFS_RESLO (0x000Au) /* Result Low Word */ +#define OFS_RESLO_L OFS_RESLO +#define OFS_RESLO_H OFS_RESLO+1 +#define OFS_RESHI (0x000Cu) /* Result High Word */ +#define OFS_RESHI_L OFS_RESHI +#define OFS_RESHI_H OFS_RESHI+1 +#define OFS_SUMEXT (0x000Eu) /* Sum Extend */ +#define OFS_SUMEXT_L OFS_SUMEXT +#define OFS_SUMEXT_H OFS_SUMEXT+1 +#define OFS_MPY32CTL0 (0x002Cu) +#define OFS_MPY32CTL0_L OFS_MPY32CTL0 +#define OFS_MPY32CTL0_H OFS_MPY32CTL0+1 + +#define OFS_MPY32L (0x0010u) /* 32-bit operand 1 - multiply - low word */ +#define OFS_MPY32L_L OFS_MPY32L +#define OFS_MPY32L_H OFS_MPY32L+1 +#define OFS_MPY32H (0x0012u) /* 32-bit operand 1 - multiply - high word */ +#define OFS_MPY32H_L OFS_MPY32H +#define OFS_MPY32H_H OFS_MPY32H+1 +#define OFS_MPYS32L (0x0014u) /* 32-bit operand 1 - signed multiply - low word */ +#define OFS_MPYS32L_L OFS_MPYS32L +#define OFS_MPYS32L_H OFS_MPYS32L+1 +#define OFS_MPYS32H (0x0016u) /* 32-bit operand 1 - signed multiply - high word */ +#define OFS_MPYS32H_L OFS_MPYS32H +#define OFS_MPYS32H_H OFS_MPYS32H+1 +#define OFS_MAC32L (0x0018u) /* 32-bit operand 1 - multiply accumulate - low word */ +#define OFS_MAC32L_L OFS_MAC32L +#define OFS_MAC32L_H OFS_MAC32L+1 +#define OFS_MAC32H (0x001Au) /* 32-bit operand 1 - multiply accumulate - high word */ +#define OFS_MAC32H_L OFS_MAC32H +#define OFS_MAC32H_H OFS_MAC32H+1 +#define OFS_MACS32L (0x001Cu) /* 32-bit operand 1 - signed multiply accumulate - low word */ +#define OFS_MACS32L_L OFS_MACS32L +#define OFS_MACS32L_H OFS_MACS32L+1 +#define OFS_MACS32H (0x001Eu) /* 32-bit operand 1 - signed multiply accumulate - high word */ +#define OFS_MACS32H_L OFS_MACS32H +#define OFS_MACS32H_H OFS_MACS32H+1 +#define OFS_OP2L (0x0020u) /* 32-bit operand 2 - low word */ +#define OFS_OP2L_L OFS_OP2L +#define OFS_OP2L_H OFS_OP2L+1 +#define OFS_OP2H (0x0022u) /* 32-bit operand 2 - high word */ +#define OFS_OP2H_L OFS_OP2H +#define OFS_OP2H_H OFS_OP2H+1 +#define OFS_RES0 (0x0024u) /* 32x32-bit result 0 - least significant word */ +#define OFS_RES0_L OFS_RES0 +#define OFS_RES0_H OFS_RES0+1 +#define OFS_RES1 (0x0026u) /* 32x32-bit result 1 */ +#define OFS_RES1_L OFS_RES1 +#define OFS_RES1_H OFS_RES1+1 +#define OFS_RES2 (0x0028u) /* 32x32-bit result 2 */ +#define OFS_RES2_L OFS_RES2 +#define OFS_RES2_H OFS_RES2+1 +#define OFS_RES3 (0x002Au) /* 32x32-bit result 3 - most significant word */ +#define OFS_RES3_L OFS_RES3 +#define OFS_RES3_H OFS_RES3+1 +#define OFS_SUMEXT (0x000Eu) +#define OFS_SUMEXT_L OFS_SUMEXT +#define OFS_SUMEXT_H OFS_SUMEXT+1 +#define OFS_MPY32CTL0 (0x002Cu) /* MPY32 Control Register 0 */ +#define OFS_MPY32CTL0_L OFS_MPY32CTL0 +#define OFS_MPY32CTL0_H OFS_MPY32CTL0+1 + +#define MPY_B MPY_L /* Multiply Unsigned/Operand 1 (Byte Access) */ +#define MPYS_B MPYS_L /* Multiply Signed/Operand 1 (Byte Access) */ +#define MAC_B MAC_L /* Multiply Unsigned and Accumulate/Operand 1 (Byte Access) */ +#define MACS_B MACS_L /* Multiply Signed and Accumulate/Operand 1 (Byte Access) */ +#define OP2_B OP2_L /* Operand 2 (Byte Access) */ +#define MPY32L_B MPY32L_L /* 32-bit operand 1 - multiply - low word (Byte Access) */ +#define MPY32H_B MPY32H_L /* 32-bit operand 1 - multiply - high word (Byte Access) */ +#define MPYS32L_B MPYS32L_L /* 32-bit operand 1 - signed multiply - low word (Byte Access) */ +#define MPYS32H_B MPYS32H_L /* 32-bit operand 1 - signed multiply - high word (Byte Access) */ +#define MAC32L_B MAC32L_L /* 32-bit operand 1 - multiply accumulate - low word (Byte Access) */ +#define MAC32H_B MAC32H_L /* 32-bit operand 1 - multiply accumulate - high word (Byte Access) */ +#define MACS32L_B MACS32L_L /* 32-bit operand 1 - signed multiply accumulate - low word (Byte Access) */ +#define MACS32H_B MACS32H_L /* 32-bit operand 1 - signed multiply accumulate - high word (Byte Access) */ +#define OP2L_B OP2L_L /* 32-bit operand 2 - low word (Byte Access) */ +#define OP2H_B OP2H_L /* 32-bit operand 2 - high word (Byte Access) */ + +/* MPY32CTL0 Control Bits */ +#define MPYC (0x0001u) /* Carry of the multiplier */ +//#define RESERVED (0x0002u) /* Reserved */ +#define MPYFRAC (0x0004u) /* Fractional mode */ +#define MPYSAT (0x0008u) /* Saturation mode */ +#define MPYM0 (0x0010u) /* Multiplier mode Bit:0 */ +#define MPYM1 (0x0020u) /* Multiplier mode Bit:1 */ +#define OP1_32 (0x0040u) /* Bit-width of operand 1 0:16Bit / 1:32Bit */ +#define OP2_32 (0x0080u) /* Bit-width of operand 2 0:16Bit / 1:32Bit */ +#define MPYDLYWRTEN (0x0100u) /* Delayed write enable */ +#define MPYDLY32 (0x0200u) /* Delayed write mode */ + +/* MPY32CTL0 Control Bits */ +#define MPYC_L (0x0001u) /* Carry of the multiplier */ +//#define RESERVED (0x0002u) /* Reserved */ +#define MPYFRAC_L (0x0004u) /* Fractional mode */ +#define MPYSAT_L (0x0008u) /* Saturation mode */ +#define MPYM0_L (0x0010u) /* Multiplier mode Bit:0 */ +#define MPYM1_L (0x0020u) /* Multiplier mode Bit:1 */ +#define OP1_32_L (0x0040u) /* Bit-width of operand 1 0:16Bit / 1:32Bit */ +#define OP2_32_L (0x0080u) /* Bit-width of operand 2 0:16Bit / 1:32Bit */ + +/* MPY32CTL0 Control Bits */ +//#define RESERVED (0x0002u) /* Reserved */ +#define MPYDLYWRTEN_H (0x0001u) /* Delayed write enable */ +#define MPYDLY32_H (0x0002u) /* Delayed write mode */ + +#define MPYM_0 (0x0000u) /* Multiplier mode: MPY */ +#define MPYM_1 (0x0010u) /* Multiplier mode: MPYS */ +#define MPYM_2 (0x0020u) /* Multiplier mode: MAC */ +#define MPYM_3 (0x0030u) /* Multiplier mode: MACS */ +#define MPYM__MPY (0x0000u) /* Multiplier mode: MPY */ +#define MPYM__MPYS (0x0010u) /* Multiplier mode: MPYS */ +#define MPYM__MAC (0x0020u) /* Multiplier mode: MAC */ +#define MPYM__MACS (0x0030u) /* Multiplier mode: MACS */ + +#endif +/************************************************************ +* DIGITAL I/O Port1/2 Pull up / Pull down Resistors +************************************************************/ +#ifdef __MSP430_HAS_PORT1_R__ /* Definition to show that Module is available */ +#ifdef __MSP430_HAS_PORT2_R__ /* Definition to show that Module is available */ +#ifdef __MSP430_HAS_PORTA_R__ /* Definition to show that Module is available */ + +#define OFS_PAIN (0x0000u) /* Port A Input */ +#define OFS_PAIN_L OFS_PAIN +#define OFS_PAIN_H OFS_PAIN+1 +#define OFS_PAOUT (0x0002u) /* Port A Output */ +#define OFS_PAOUT_L OFS_PAOUT +#define OFS_PAOUT_H OFS_PAOUT+1 +#define OFS_PADIR (0x0004u) /* Port A Direction */ +#define OFS_PADIR_L OFS_PADIR +#define OFS_PADIR_H OFS_PADIR+1 +#define OFS_PAREN (0x0006u) /* Port A Resistor Enable */ +#define OFS_PAREN_L OFS_PAREN +#define OFS_PAREN_H OFS_PAREN+1 +#define OFS_PADS (0x0008u) /* Port A Drive Strenght */ +#define OFS_PADS_L OFS_PADS +#define OFS_PADS_H OFS_PADS+1 +#define OFS_PASEL (0x000Au) /* Port A Selection */ +#define OFS_PASEL_L OFS_PASEL +#define OFS_PASEL_H OFS_PASEL+1 +#define OFS_PAIES (0x0018u) /* Port A Interrupt Edge Select */ +#define OFS_PAIES_L OFS_PAIES +#define OFS_PAIES_H OFS_PAIES+1 +#define OFS_PAIE (0x001Au) /* Port A Interrupt Enable */ +#define OFS_PAIE_L OFS_PAIE +#define OFS_PAIE_H OFS_PAIE+1 +#define OFS_PAIFG (0x001Cu) /* Port A Interrupt Flag */ +#define OFS_PAIFG_L OFS_PAIFG +#define OFS_PAIFG_H OFS_PAIFG+1 + + +#define OFS_P1IN (0x0000u) +#define OFS_P1OUT (0x0002u) +#define OFS_P1DIR (0x0004u) +#define OFS_P1REN (0x0006u) +#define OFS_P1DS (0x0008u) +#define OFS_P1SEL (0x000Au) +#define OFS_P1IV (0x000Eu) /* Port 1 Interrupt Vector Word */ +#define OFS_P1IES (0x0018u) +#define OFS_P1IE (0x001Au) +#define OFS_P1IFG (0x001Cu) +#define OFS_P2IN (0x0001u) +#define OFS_P2OUT (0x0003u) +#define OFS_P2DIR (0x0005u) +#define OFS_P2REN (0x0007u) +#define OFS_P2DS (0x0009u) +#define OFS_P2SEL (0x000Bu) +#define OFS_P2IV (0x001Eu) /* Port 2 Interrupt Vector Word */ +#define OFS_P2IES (0x0019u) +#define OFS_P2IE (0x001Bu) +#define OFS_P2IFG (0x001du) +#define P1IN (PAIN_L) /* Port 1 Input */ +#define P1OUT (PAOUT_L) /* Port 1 Output */ +#define P1DIR (PADIR_L) /* Port 1 Direction */ +#define P1REN (PAREN_L) /* Port 1 Resistor Enable */ +#define P1DS (PADS_L) /* Port 1 Drive Strenght */ +#define P1SEL (PASEL_L) /* Port 1 Selection */ +#define P1IES (PAIES_L) /* Port 1 Interrupt Edge Select */ +#define P1IE (PAIE_L) /* Port 1 Interrupt Enable */ +#define P1IFG (PAIFG_L) /* Port 1 Interrupt Flag */ + +//Definitions for P1IV +#define P1IV_NONE (0x0000u) /* No Interrupt pending */ +#define P1IV_P1IFG0 (0x0002u) /* P1IV P1IFG.0 */ +#define P1IV_P1IFG1 (0x0004u) /* P1IV P1IFG.1 */ +#define P1IV_P1IFG2 (0x0006u) /* P1IV P1IFG.2 */ +#define P1IV_P1IFG3 (0x0008u) /* P1IV P1IFG.3 */ +#define P1IV_P1IFG4 (0x000Au) /* P1IV P1IFG.4 */ +#define P1IV_P1IFG5 (0x000Cu) /* P1IV P1IFG.5 */ +#define P1IV_P1IFG6 (0x000Eu) /* P1IV P1IFG.6 */ +#define P1IV_P1IFG7 (0x0010u) /* P1IV P1IFG.7 */ + +#define P2IN (PAIN_H) /* Port 2 Input */ +#define P2OUT (PAOUT_H) /* Port 2 Output */ +#define P2DIR (PADIR_H) /* Port 2 Direction */ +#define P2REN (PAREN_H) /* Port 2 Resistor Enable */ +#define P2DS (PADS_H) /* Port 2 Drive Strenght */ +#define P2SEL (PASEL_H) /* Port 2 Selection */ +#define P2IES (PAIES_H) /* Port 2 Interrupt Edge Select */ +#define P2IE (PAIE_H) /* Port 2 Interrupt Enable */ +#define P2IFG (PAIFG_H) /* Port 2 Interrupt Flag */ + +//Definitions for P2IV +#define P2IV_NONE (0x0000u) /* No Interrupt pending */ +#define P2IV_P2IFG0 (0x0002u) /* P2IV P2IFG.0 */ +#define P2IV_P2IFG1 (0x0004u) /* P2IV P2IFG.1 */ +#define P2IV_P2IFG2 (0x0006u) /* P2IV P2IFG.2 */ +#define P2IV_P2IFG3 (0x0008u) /* P2IV P2IFG.3 */ +#define P2IV_P2IFG4 (0x000Au) /* P2IV P2IFG.4 */ +#define P2IV_P2IFG5 (0x000Cu) /* P2IV P2IFG.5 */ +#define P2IV_P2IFG6 (0x000Eu) /* P2IV P2IFG.6 */ +#define P2IV_P2IFG7 (0x0010u) /* P2IV P2IFG.7 */ + + +#endif +#endif +#endif +/************************************************************ +* DIGITAL I/O Port3/4 Pull up / Pull down Resistors +************************************************************/ +#ifdef __MSP430_HAS_PORT3_R__ /* Definition to show that Module is available */ +#ifdef __MSP430_HAS_PORT4_R__ /* Definition to show that Module is available */ +#ifdef __MSP430_HAS_PORTB_R__ /* Definition to show that Module is available */ + +#define OFS_PBIN (0x0000u) /* Port B Input */ +#define OFS_PBIN_L OFS_PBIN +#define OFS_PBIN_H OFS_PBIN+1 +#define OFS_PBOUT (0x0002u) /* Port B Output */ +#define OFS_PBOUT_L OFS_PBOUT +#define OFS_PBOUT_H OFS_PBOUT+1 +#define OFS_PBDIR (0x0004u) /* Port B Direction */ +#define OFS_PBDIR_L OFS_PBDIR +#define OFS_PBDIR_H OFS_PBDIR+1 +#define OFS_PBREN (0x0006u) /* Port B Resistor Enable */ +#define OFS_PBREN_L OFS_PBREN +#define OFS_PBREN_H OFS_PBREN+1 +#define OFS_PBDS (0x0008u) /* Port B Drive Strenght */ +#define OFS_PBDS_L OFS_PBDS +#define OFS_PBDS_H OFS_PBDS+1 +#define OFS_PBSEL (0x000Au) /* Port B Selection */ +#define OFS_PBSEL_L OFS_PBSEL +#define OFS_PBSEL_H OFS_PBSEL+1 +#define OFS_PBIES (0x0018u) /* Port B Interrupt Edge Select */ +#define OFS_PBIES_L OFS_PBIES +#define OFS_PBIES_H OFS_PBIES+1 +#define OFS_PBIE (0x001Au) /* Port B Interrupt Enable */ +#define OFS_PBIE_L OFS_PBIE +#define OFS_PBIE_H OFS_PBIE+1 +#define OFS_PBIFG (0x001Cu) /* Port B Interrupt Flag */ +#define OFS_PBIFG_L OFS_PBIFG +#define OFS_PBIFG_H OFS_PBIFG+1 + + +#define OFS_P3IN (0x0000u) +#define OFS_P3OUT (0x0002u) +#define OFS_P3DIR (0x0004u) +#define OFS_P3REN (0x0006u) +#define OFS_P3DS (0x0008u) +#define OFS_P3SEL (0x000Au) +#define OFS_P3IV (0x000Eu) /* Port 3 Interrupt Vector Word */ +#define OFS_P3IES (0x0018u) +#define OFS_P3IE (0x001Au) +#define OFS_P3IFG (0x001Cu) +#define OFS_P4IN (0x0001u) +#define OFS_P4OUT (0x0003u) +#define OFS_P4DIR (0x0005u) +#define OFS_P4REN (0x0007u) +#define OFS_P4DS (0x0009u) +#define OFS_P4SEL (0x000Bu) +#define OFS_P4IV (0x001Eu) /* Port 4 Interrupt Vector Word */ +#define OFS_P4IES (0x0019u) +#define OFS_P4IE (0x001Bu) +#define OFS_P4IFG (0x001du) +#define P3IN (PBIN_L) /* Port 3 Input */ +#define P3OUT (PBOUT_L) /* Port 3 Output */ +#define P3DIR (PBDIR_L) /* Port 3 Direction */ +#define P3REN (PBREN_L) /* Port 3 Resistor Enable */ +#define P3DS (PBDS_L) /* Port 3 Drive Strenght */ +#define P3SEL (PBSEL_L) /* Port 3 Selection */ +#define P3IES (PBIES_L) /* Port 3 Interrupt Edge Select */ +#define P3IE (PBIE_L) /* Port 3 Interrupt Enable */ +#define P3IFG (PBIFG_L) /* Port 3 Interrupt Flag */ + +//Definitions for P3IV +#define P3IV_NONE (0x0000u) /* No Interrupt pending */ +#define P3IV_P3IFG0 (0x0002u) /* P3IV P3IFG.0 */ +#define P3IV_P3IFG1 (0x0004u) /* P3IV P3IFG.1 */ +#define P3IV_P3IFG2 (0x0006u) /* P3IV P3IFG.2 */ +#define P3IV_P3IFG3 (0x0008u) /* P3IV P3IFG.3 */ +#define P3IV_P3IFG4 (0x000Au) /* P3IV P3IFG.4 */ +#define P3IV_P3IFG5 (0x000Cu) /* P3IV P3IFG.5 */ +#define P3IV_P3IFG6 (0x000Eu) /* P3IV P3IFG.6 */ +#define P3IV_P3IFG7 (0x0010u) /* P3IV P3IFG.7 */ + +#define P4IN (PBIN_H) /* Port 4 Input */ +#define P4OUT (PBOUT_H) /* Port 4 Output */ +#define P4DIR (PBDIR_H) /* Port 4 Direction */ +#define P4REN (PBREN_H) /* Port 4 Resistor Enable */ +#define P4DS (PBDS_H) /* Port 4 Drive Strenght */ +#define P4SEL (PBSEL_H) /* Port 4 Selection */ +#define P4IES (PBIES_H) /* Port 4 Interrupt Edge Select */ +#define P4IE (PBIE_H) /* Port 4 Interrupt Enable */ +#define P4IFG (PBIFG_H) /* Port 4 Interrupt Flag */ + +//Definitions for P4IV +#define P4IV_NONE (0x0000u) /* No Interrupt pending */ +#define P4IV_P4IFG0 (0x0002u) /* P4IV P4IFG.0 */ +#define P4IV_P4IFG1 (0x0004u) /* P4IV P4IFG.1 */ +#define P4IV_P4IFG2 (0x0006u) /* P4IV P4IFG.2 */ +#define P4IV_P4IFG3 (0x0008u) /* P4IV P4IFG.3 */ +#define P4IV_P4IFG4 (0x000Au) /* P4IV P4IFG.4 */ +#define P4IV_P4IFG5 (0x000Cu) /* P4IV P4IFG.5 */ +#define P4IV_P4IFG6 (0x000Eu) /* P4IV P4IFG.6 */ +#define P4IV_P4IFG7 (0x0010u) /* P4IV P4IFG.7 */ + + +#endif +#endif +#endif +/************************************************************ +* DIGITAL I/O Port5/6 Pull up / Pull down Resistors +************************************************************/ +#ifdef __MSP430_HAS_PORT5_R__ /* Definition to show that Module is available */ +#ifdef __MSP430_HAS_PORT6_R__ /* Definition to show that Module is available */ +#ifdef __MSP430_HAS_PORTC_R__ /* Definition to show that Module is available */ + +#define OFS_PCIN (0x0000u) /* Port C Input */ +#define OFS_PCIN_L OFS_PCIN +#define OFS_PCIN_H OFS_PCIN+1 +#define OFS_PCOUT (0x0002u) /* Port C Output */ +#define OFS_PCOUT_L OFS_PCOUT +#define OFS_PCOUT_H OFS_PCOUT+1 +#define OFS_PCDIR (0x0004u) /* Port C Direction */ +#define OFS_PCDIR_L OFS_PCDIR +#define OFS_PCDIR_H OFS_PCDIR+1 +#define OFS_PCREN (0x0006u) /* Port C Resistor Enable */ +#define OFS_PCREN_L OFS_PCREN +#define OFS_PCREN_H OFS_PCREN+1 +#define OFS_PCDS (0x0008u) /* Port C Drive Strenght */ +#define OFS_PCDS_L OFS_PCDS +#define OFS_PCDS_H OFS_PCDS+1 +#define OFS_PCSEL (0x000Au) /* Port C Selection */ +#define OFS_PCSEL_L OFS_PCSEL +#define OFS_PCSEL_H OFS_PCSEL+1 +#define OFS_PCIES (0x0018u) /* Port C Interrupt Edge Select */ +#define OFS_PCIES_L OFS_PCIES +#define OFS_PCIES_H OFS_PCIES+1 +#define OFS_PCIE (0x001Au) /* Port C Interrupt Enable */ +#define OFS_PCIE_L OFS_PCIE +#define OFS_PCIE_H OFS_PCIE+1 +#define OFS_PCIFG (0x001Cu) /* Port C Interrupt Flag */ +#define OFS_PCIFG_L OFS_PCIFG +#define OFS_PCIFG_H OFS_PCIFG+1 + + +#define OFS_P5IN (0x0000u) +#define OFS_P5OUT (0x0002u) +#define OFS_P5DIR (0x0004u) +#define OFS_P5REN (0x0006u) +#define OFS_P5DS (0x0008u) +#define OFS_P5SEL (0x000Au) +#define OFS_P5IV (0x000Eu) /* Port 5 Interrupt Vector Word */ +#define OFS_P5IES (0x0018u) +#define OFS_P5IE (0x001Au) +#define OFS_P5IFG (0x001Cu) +#define OFS_P6IN (0x0001u) +#define OFS_P6OUT (0x0003u) +#define OFS_P6DIR (0x0005u) +#define OFS_P6REN (0x0007u) +#define OFS_P6DS (0x0009u) +#define OFS_P6SEL (0x000Bu) +#define OFS_P6IV (0x001Eu) /* Port 6 Interrupt Vector Word */ +#define OFS_P6IES (0x0019u) +#define OFS_P6IE (0x001Bu) +#define OFS_P6IFG (0x001du) +#define P5IN (PCIN_L) /* Port 5 Input */ +#define P5OUT (PCOUT_L) /* Port 5 Output */ +#define P5DIR (PCDIR_L) /* Port 5 Direction */ +#define P5REN (PCREN_L) /* Port 5 Resistor Enable */ +#define P5DS (PCDS_L) /* Port 5 Drive Strenght */ +#define P5SEL (PCSEL_L) /* Port 5 Selection */ +#define P5IES (PCIES_L) /* Port 5 Interrupt Edge Select */ +#define P5IE (PCIE_L) /* Port 5 Interrupt Enable */ +#define P5IFG (PCIFG_L) /* Port 5 Interrupt Flag */ + +//Definitions for P5IV +#define P5IV_NONE (0x0000u) /* No Interrupt pending */ +#define P5IV_P5IFG0 (0x0002u) /* P5IV P5IFG.0 */ +#define P5IV_P5IFG1 (0x0004u) /* P5IV P5IFG.1 */ +#define P5IV_P5IFG2 (0x0006u) /* P5IV P5IFG.2 */ +#define P5IV_P5IFG3 (0x0008u) /* P5IV P5IFG.3 */ +#define P5IV_P5IFG4 (0x000Au) /* P5IV P5IFG.4 */ +#define P5IV_P5IFG5 (0x000Cu) /* P5IV P5IFG.5 */ +#define P5IV_P5IFG6 (0x000Eu) /* P5IV P5IFG.6 */ +#define P5IV_P5IFG7 (0x0010u) /* P5IV P5IFG.7 */ + +#define P6IN (PCIN_H) /* Port 6 Input */ +#define P6OUT (PCOUT_H) /* Port 6 Output */ +#define P6DIR (PCDIR_H) /* Port 6 Direction */ +#define P6REN (PCREN_H) /* Port 6 Resistor Enable */ +#define P6DS (PCDS_H) /* Port 6 Drive Strenght */ +#define P6SEL (PCSEL_H) /* Port 6 Selection */ +#define P6IES (PCIES_H) /* Port 6 Interrupt Edge Select */ +#define P6IE (PCIE_H) /* Port 6 Interrupt Enable */ +#define P6IFG (PCIFG_H) /* Port 6 Interrupt Flag */ + +//Definitions for P6IV +#define P6IV_NONE (0x0000u) /* No Interrupt pending */ +#define P6IV_P6IFG0 (0x0002u) /* P6IV P6IFG.0 */ +#define P6IV_P6IFG1 (0x0004u) /* P6IV P6IFG.1 */ +#define P6IV_P6IFG2 (0x0006u) /* P6IV P6IFG.2 */ +#define P6IV_P6IFG3 (0x0008u) /* P6IV P6IFG.3 */ +#define P6IV_P6IFG4 (0x000Au) /* P6IV P6IFG.4 */ +#define P6IV_P6IFG5 (0x000Cu) /* P6IV P6IFG.5 */ +#define P6IV_P6IFG6 (0x000Eu) /* P6IV P6IFG.6 */ +#define P6IV_P6IFG7 (0x0010u) /* P6IV P6IFG.7 */ + + +#endif +#endif +#endif +/************************************************************ +* DIGITAL I/O Port7/8 Pull up / Pull down Resistors +************************************************************/ +#ifdef __MSP430_HAS_PORT7_R__ /* Definition to show that Module is available */ +#ifdef __MSP430_HAS_PORT8_R__ /* Definition to show that Module is available */ +#ifdef __MSP430_HAS_PORTD_R__ /* Definition to show that Module is available */ + +#define OFS_PDIN (0x0000u) /* Port D Input */ +#define OFS_PDIN_L OFS_PDIN +#define OFS_PDIN_H OFS_PDIN+1 +#define OFS_PDOUT (0x0002u) /* Port D Output */ +#define OFS_PDOUT_L OFS_PDOUT +#define OFS_PDOUT_H OFS_PDOUT+1 +#define OFS_PDDIR (0x0004u) /* Port D Direction */ +#define OFS_PDDIR_L OFS_PDDIR +#define OFS_PDDIR_H OFS_PDDIR+1 +#define OFS_PDREN (0x0006u) /* Port D Resistor Enable */ +#define OFS_PDREN_L OFS_PDREN +#define OFS_PDREN_H OFS_PDREN+1 +#define OFS_PDDS (0x0008u) /* Port D Drive Strenght */ +#define OFS_PDDS_L OFS_PDDS +#define OFS_PDDS_H OFS_PDDS+1 +#define OFS_PDSEL (0x000Au) /* Port D Selection */ +#define OFS_PDSEL_L OFS_PDSEL +#define OFS_PDSEL_H OFS_PDSEL+1 +#define OFS_PDIES (0x0018u) /* Port D Interrupt Edge Select */ +#define OFS_PDIES_L OFS_PDIES +#define OFS_PDIES_H OFS_PDIES+1 +#define OFS_PDIE (0x001Au) /* Port D Interrupt Enable */ +#define OFS_PDIE_L OFS_PDIE +#define OFS_PDIE_H OFS_PDIE+1 +#define OFS_PDIFG (0x001Cu) /* Port D Interrupt Flag */ +#define OFS_PDIFG_L OFS_PDIFG +#define OFS_PDIFG_H OFS_PDIFG+1 + + +#define OFS_P7IN (0x0000u) +#define OFS_P7OUT (0x0002u) +#define OFS_P7DIR (0x0004u) +#define OFS_P7REN (0x0006u) +#define OFS_P7DS (0x0008u) +#define OFS_P7SEL (0x000Au) +#define OFS_P7IV (0x000Eu) /* Port 7 Interrupt Vector Word */ +#define OFS_P7IES (0x0018u) +#define OFS_P7IE (0x001Au) +#define OFS_P7IFG (0x001Cu) +#define OFS_P8IN (0x0001u) +#define OFS_P8OUT (0x0003u) +#define OFS_P8DIR (0x0005u) +#define OFS_P8REN (0x0007u) +#define OFS_P8DS (0x0009u) +#define OFS_P8SEL (0x000Bu) +#define OFS_P8IV (0x001Eu) /* Port 8 Interrupt Vector Word */ +#define OFS_P8IES (0x0019u) +#define OFS_P8IE (0x001Bu) +#define OFS_P8IFG (0x001du) +#define P7IN (PDIN_L) /* Port 7 Input */ +#define P7OUT (PDOUT_L) /* Port 7 Output */ +#define P7DIR (PDDIR_L) /* Port 7 Direction */ +#define P7REN (PDREN_L) /* Port 7 Resistor Enable */ +#define P7DS (PDDS_L) /* Port 7 Drive Strenght */ +#define P7SEL (PDSEL_L) /* Port 7 Selection */ +#define P7IES (PDIES_L) /* Port 7 Interrupt Edge Select */ +#define P7IE (PDIE_L) /* Port 7 Interrupt Enable */ +#define P7IFG (PDIFG_L) /* Port 7 Interrupt Flag */ + +//Definitions for P7IV +#define P7IV_NONE (0x0000u) /* No Interrupt pending */ +#define P7IV_P7IFG0 (0x0002u) /* P7IV P7IFG.0 */ +#define P7IV_P7IFG1 (0x0004u) /* P7IV P7IFG.1 */ +#define P7IV_P7IFG2 (0x0006u) /* P7IV P7IFG.2 */ +#define P7IV_P7IFG3 (0x0008u) /* P7IV P7IFG.3 */ +#define P7IV_P7IFG4 (0x000Au) /* P7IV P7IFG.4 */ +#define P7IV_P7IFG5 (0x000Cu) /* P7IV P7IFG.5 */ +#define P7IV_P7IFG6 (0x000Eu) /* P7IV P7IFG.6 */ +#define P7IV_P7IFG7 (0x0010u) /* P7IV P7IFG.7 */ + +#define P8IN (PDIN_H) /* Port 8 Input */ +#define P8OUT (PDOUT_H) /* Port 8 Output */ +#define P8DIR (PDDIR_H) /* Port 8 Direction */ +#define P8REN (PDREN_H) /* Port 8 Resistor Enable */ +#define P8DS (PDDS_H) /* Port 8 Drive Strenght */ +#define P8SEL (PDSEL_H) /* Port 8 Selection */ +#define P8IES (PDIES_H) /* Port 8 Interrupt Edge Select */ +#define P8IE (PDIE_H) /* Port 8 Interrupt Enable */ +#define P8IFG (PDIFG_H) /* Port 8 Interrupt Flag */ + +//Definitions for P8IV +#define P8IV_NONE (0x0000u) /* No Interrupt pending */ +#define P8IV_P8IFG0 (0x0002u) /* P8IV P8IFG.0 */ +#define P8IV_P8IFG1 (0x0004u) /* P8IV P8IFG.1 */ +#define P8IV_P8IFG2 (0x0006u) /* P8IV P8IFG.2 */ +#define P8IV_P8IFG3 (0x0008u) /* P8IV P8IFG.3 */ +#define P8IV_P8IFG4 (0x000Au) /* P8IV P8IFG.4 */ +#define P8IV_P8IFG5 (0x000Cu) /* P8IV P8IFG.5 */ +#define P8IV_P8IFG6 (0x000Eu) /* P8IV P8IFG.6 */ +#define P8IV_P8IFG7 (0x0010u) /* P8IV P8IFG.7 */ + + +#endif +#endif +#endif +/************************************************************ +* DIGITAL I/O Port9/10 Pull up / Pull down Resistors +************************************************************/ +#ifdef __MSP430_HAS_PORT9_R__ /* Definition to show that Module is available */ +#ifdef __MSP430_HAS_PORT10_R__ /* Definition to show that Module is available */ +#ifdef __MSP430_HAS_PORTE_R__ /* Definition to show that Module is available */ + +#define OFS_PEIN (0x0000u) /* Port E Input */ +#define OFS_PEIN_L OFS_PEIN +#define OFS_PEIN_H OFS_PEIN+1 +#define OFS_PEOUT (0x0002u) /* Port E Output */ +#define OFS_PEOUT_L OFS_PEOUT +#define OFS_PEOUT_H OFS_PEOUT+1 +#define OFS_PEDIR (0x0004u) /* Port E Direction */ +#define OFS_PEDIR_L OFS_PEDIR +#define OFS_PEDIR_H OFS_PEDIR+1 +#define OFS_PEREN (0x0006u) /* Port E Resistor Enable */ +#define OFS_PEREN_L OFS_PEREN +#define OFS_PEREN_H OFS_PEREN+1 +#define OFS_PEDS (0x0008u) /* Port E Drive Strenght */ +#define OFS_PEDS_L OFS_PEDS +#define OFS_PEDS_H OFS_PEDS+1 +#define OFS_PESEL (0x000Au) /* Port E Selection */ +#define OFS_PESEL_L OFS_PESEL +#define OFS_PESEL_H OFS_PESEL+1 +#define OFS_PEIES (0x0018u) /* Port E Interrupt Edge Select */ +#define OFS_PEIES_L OFS_PEIES +#define OFS_PEIES_H OFS_PEIES+1 +#define OFS_PEIE (0x001Au) /* Port E Interrupt Enable */ +#define OFS_PEIE_L OFS_PEIE +#define OFS_PEIE_H OFS_PEIE+1 +#define OFS_PEIFG (0x001Cu) /* Port E Interrupt Flag */ +#define OFS_PEIFG_L OFS_PEIFG +#define OFS_PEIFG_H OFS_PEIFG+1 + + +#define OFS_P9IN (0x0000u) +#define OFS_P9OUT (0x0002u) +#define OFS_P9DIR (0x0004u) +#define OFS_P9REN (0x0006u) +#define OFS_P9DS (0x0008u) +#define OFS_P9SEL (0x000Au) +#define OFS_P9IV (0x000Eu) /* Port 9 Interrupt Vector Word */ +#define OFS_P9IES (0x0018u) +#define OFS_P9IE (0x001Au) +#define OFS_P9IFG (0x001Cu) +#define OFS_P10IN (0x0001u) +#define OFS_P10OUT (0x0003u) +#define OFS_P10DIR (0x0005u) +#define OFS_P10REN (0x0007u) +#define OFS_P10DS (0x0009u) +#define OFS_P10SEL (0x000Bu) +#define OFS_P10IV (0x001Eu) /* Port 10 Interrupt Vector Word */ +#define OFS_P10IES (0x0019u) +#define OFS_P10IE (0x001Bu) +#define OFS_P10IFG (0x001du) +#define P9IN (PEIN_L) /* Port 9 Input */ +#define P9OUT (PEOUT_L) /* Port 9 Output */ +#define P9DIR (PEDIR_L) /* Port 9 Direction */ +#define P9REN (PEREN_L) /* Port 9 Resistor Enable */ +#define P9DS (PEDS_L) /* Port 9 Drive Strenght */ +#define P9SEL (PESEL_L) /* Port 9 Selection */ +#define P9IES (PEIES_L) /* Port 9 Interrupt Edge Select */ +#define P9IE (PEIE_L) /* Port 9 Interrupt Enable */ +#define P9IFG (PEIFG_L) /* Port 9 Interrupt Flag */ + +//Definitions for P9IV +#define P9IV_NONE (0x0000u) /* No Interrupt pending */ +#define P9IV_P9IFG0 (0x0002u) /* P9IV P9IFG.0 */ +#define P9IV_P9IFG1 (0x0004u) /* P9IV P9IFG.1 */ +#define P9IV_P9IFG2 (0x0006u) /* P9IV P9IFG.2 */ +#define P9IV_P9IFG3 (0x0008u) /* P9IV P9IFG.3 */ +#define P9IV_P9IFG4 (0x000Au) /* P9IV P9IFG.4 */ +#define P9IV_P9IFG5 (0x000Cu) /* P9IV P9IFG.5 */ +#define P9IV_P9IFG6 (0x000Eu) /* P9IV P9IFG.6 */ +#define P9IV_P9IFG7 (0x0010u) /* P9IV P9IFG.7 */ + +#define P10IN (PEIN_H) /* Port 10 Input */ +#define P10OUT (PEOUT_H) /* Port 10 Output */ +#define P10DIR (PEDIR_H) /* Port 10 Direction */ +#define P10REN (PEREN_H) /* Port 10 Resistor Enable */ +#define P10DS (PEDS_H) /* Port 10 Drive Strenght */ +#define P10SEL (PESEL_H) /* Port 10 Selection */ +#define P10IES (PEIES_H) /* Port 10 Interrupt Edge Select */ +#define P10IE (PEIE_H) /* Port 10 Interrupt Enable */ +#define P10IFG (PEIFG_H) /* Port 10 Interrupt Flag */ + +//Definitions for P10IV +#define P10IV_NONE (0x0000u) /* No Interrupt pending */ +#define P10IV_P10IFG0 (0x0002u) /* P10IV P10IFG.0 */ +#define P10IV_P10IFG1 (0x0004u) /* P10IV P10IFG.1 */ +#define P10IV_P10IFG2 (0x0006u) /* P10IV P10IFG.2 */ +#define P10IV_P10IFG3 (0x0008u) /* P10IV P10IFG.3 */ +#define P10IV_P10IFG4 (0x000Au) /* P10IV P10IFG.4 */ +#define P10IV_P10IFG5 (0x000Cu) /* P10IV P10IFG.5 */ +#define P10IV_P10IFG6 (0x000Eu) /* P10IV P10IFG.6 */ +#define P10IV_P10IFG7 (0x0010u) /* P10IV P10IFG.7 */ + + +#endif +#endif +#endif +/************************************************************ +* DIGITAL I/O Port11 Pull up / Pull down Resistors +************************************************************/ +#ifdef __MSP430_HAS_PORT11_R__ /* Definition to show that Module is available */ +#ifdef __MSP430_HAS_PORTF_R__ /* Definition to show that Module is available */ + +#define OFS_PFIN (0x0000u) /* Port F Input */ +#define OFS_PFIN_L OFS_PFIN +#define OFS_PFIN_H OFS_PFIN+1 +#define OFS_PFOUT (0x0002u) /* Port F Output */ +#define OFS_PFOUT_L OFS_PFOUT +#define OFS_PFOUT_H OFS_PFOUT+1 +#define OFS_PFDIR (0x0004u) /* Port F Direction */ +#define OFS_PFDIR_L OFS_PFDIR +#define OFS_PFDIR_H OFS_PFDIR+1 +#define OFS_PFREN (0x0006u) /* Port F Resistor Enable */ +#define OFS_PFREN_L OFS_PFREN +#define OFS_PFREN_H OFS_PFREN+1 +#define OFS_PFDS (0x0008u) /* Port F Drive Strenght */ +#define OFS_PFDS_L OFS_PFDS +#define OFS_PFDS_H OFS_PFDS+1 +#define OFS_PFSEL (0x000Au) /* Port F Selection */ +#define OFS_PFSEL_L OFS_PFSEL +#define OFS_PFSEL_H OFS_PFSEL+1 +#define OFS_PFIES (0x0018u) /* Port F Interrupt Edge Select */ +#define OFS_PFIES_L OFS_PFIES +#define OFS_PFIES_H OFS_PFIES+1 +#define OFS_PFIE (0x001Au) /* Port F Interrupt Enable */ +#define OFS_PFIE_L OFS_PFIE +#define OFS_PFIE_H OFS_PFIE+1 +#define OFS_PFIFG (0x001Cu) /* Port F Interrupt Flag */ +#define OFS_PFIFG_L OFS_PFIFG +#define OFS_PFIFG_H OFS_PFIFG+1 + + +#define OFS_P11IN (0x0000u) +#define OFS_P11OUT (0x0002u) +#define OFS_P11DIR (0x0004u) +#define OFS_P11REN (0x0006u) +#define OFS_P11DS (0x0008u) +#define OFS_P11SEL (0x000Au) +#define OFS_P11IV (0x000Eu) /* Port 11 Interrupt Vector Word */ +#define OFS_P11IES (0x0018u) +#define OFS_P11IE (0x001Au) +#define OFS_P11IFG (0x001Cu) +#define P11IN (PFIN_L) /* Port 11 Input */ +#define P11OUT (PFOUT_L) /* Port 11 Output */ +#define P11DIR (PFDIR_L) /* Port 11 Direction */ +#define P11REN (PFREN_L) /* Port 11 Resistor Enable */ +#define P11DS (PFDS_L) /* Port 11 Drive Strenght */ +#define P11SEL (PFSEL_L) /* Port 11 Selection */ + +#define P11IES (PFIES_L) /* Port 11 Interrupt Edge Select */ +#define P11IE (PFIE_L) /* Port 11 Interrupt Enable */ +#define P11IFG (PFIFG_L) /* Port 11 Interrupt Flag */ + +//Definitions for P11IV +#define P11IV_NONE (0x0000u) /* No Interrupt pending */ +#define P11IV_P11IFG0 (0x0002u) /* P11IV P11IFG.0 */ +#define P11IV_P11IFG1 (0x0004u) /* P11IV P11IFG.1 */ +#define P11IV_P11IFG2 (0x0006u) /* P11IV P11IFG.2 */ +#define P11IV_P11IFG3 (0x0008u) /* P11IV P11IFG.3 */ +#define P11IV_P11IFG4 (0x000Au) /* P11IV P11IFG.4 */ +#define P11IV_P11IFG5 (0x000Cu) /* P11IV P11IFG.5 */ +#define P11IV_P11IFG6 (0x000Eu) /* P11IV P11IFG.6 */ +#define P11IV_P11IFG7 (0x0010u) /* P11IV P11IFG.7 */ + + +#endif +#endif +/************************************************************ +* DIGITAL I/O PortJ Pull up / Pull down Resistors +************************************************************/ +#ifdef __MSP430_HAS_PORTJ_R__ /* Definition to show that Module is available */ + +#define OFS_PJIN (0x0000u) /* Port J Input */ +#define OFS_PJIN_L OFS_PJIN +#define OFS_PJIN_H OFS_PJIN+1 +#define OFS_PJOUT (0x0002u) /* Port J Output */ +#define OFS_PJOUT_L OFS_PJOUT +#define OFS_PJOUT_H OFS_PJOUT+1 +#define OFS_PJDIR (0x0004u) /* Port J Direction */ +#define OFS_PJDIR_L OFS_PJDIR +#define OFS_PJDIR_H OFS_PJDIR+1 +#define OFS_PJREN (0x0006u) /* Port J Resistor Enable */ +#define OFS_PJREN_L OFS_PJREN +#define OFS_PJREN_H OFS_PJREN+1 +#define OFS_PJDS (0x0008u) /* Port J Drive Strenght */ +#define OFS_PJDS_L OFS_PJDS +#define OFS_PJDS_H OFS_PJDS+1 +#define OFS_PJSEL (0x000Au) /* Port J Selection */ +#define OFS_PJSEL_L OFS_PJSEL +#define OFS_PJSEL_H OFS_PJSEL+1 + +#endif +/************************************************************ +* PORT MAPPING CONTROLLER +************************************************************/ +#ifdef __MSP430_HAS_PORT_MAPPING__ /* Definition to show that Module is available */ + +#define OFS_PMAPKEYID (0x0000u) /* Port Mapping Key register */ +#define OFS_PMAPKEYID_L OFS_PMAPKEYID +#define OFS_PMAPKEYID_H OFS_PMAPKEYID+1 +#define OFS_PMAPCTL (0x0002u) /* Port Mapping control register */ +#define OFS_PMAPCTL_L OFS_PMAPCTL +#define OFS_PMAPCTL_H OFS_PMAPCTL+1 + +#define PMAPKEY (0x2D52u) /* Port Mapping Key */ +#define PMAPPWD PMAPKEYID /* Legacy Definition: Mapping Key register */ +#define PMAPPW (0x2D52u) /* Legacy Definition: Port Mapping Password */ + +/* PMAPCTL Control Bits */ +#define PMAPLOCKED (0x0001u) /* Port Mapping Lock bit. Read only */ +#define PMAPRECFG (0x0002u) /* Port Mapping re-configuration control bit */ + +/* PMAPCTL Control Bits */ +#define PMAPLOCKED_L (0x0001u) /* Port Mapping Lock bit. Read only */ +#define PMAPRECFG_L (0x0002u) /* Port Mapping re-configuration control bit */ + +#endif +/************************************************************ +* PORT 2 MAPPING CONTROLLER +************************************************************/ +#ifdef __MSP430_HAS_PORT2_MAPPING__ /* Definition to show that Module is available */ + +#define OFS_P2MAP01 (0x0000u) /* Port P2.0/1 mapping register */ +#define OFS_P2MAP01_L OFS_P2MAP01 +#define OFS_P2MAP01_H OFS_P2MAP01+1 +#define OFS_P2MAP23 (0x0002u) /* Port P2.2/3 mapping register */ +#define OFS_P2MAP23_L OFS_P2MAP23 +#define OFS_P2MAP23_H OFS_P2MAP23+1 +#define OFS_P2MAP45 (0x0004u) /* Port P2.4/5 mapping register */ +#define OFS_P2MAP45_L OFS_P2MAP45 +#define OFS_P2MAP45_H OFS_P2MAP45+1 +#define OFS_P2MAP67 (0x0006u) /* Port P2.6/7 mapping register */ +#define OFS_P2MAP67_L OFS_P2MAP67 +#define OFS_P2MAP67_H OFS_P2MAP67+1 +#define OFS_P2MAP0 (0x0000u) +#define OFS_P2MAP1 (0x0001u) +#define OFS_P2MAP2 (0x0002u) +#define OFS_P2MAP3 (0x0003u) +#define OFS_P2MAP4 (0x0004u) +#define OFS_P2MAP5 (0x0005u) +#define OFS_P2MAP6 (0x0006u) +#define OFS_P2MAP7 (0x0007u) + +#define P2MAP0 P2MAP01_L /* Port P2.0 mapping register */ +#define P2MAP1 P2MAP01_H /* Port P2.1 mapping register */ +#define P2MAP2 P2MAP23_L /* Port P2.2 mapping register */ +#define P2MAP3 P2MAP23_H /* Port P2.3 mapping register */ +#define P2MAP4 P2MAP45_L /* Port P2.4 mapping register */ +#define P2MAP5 P2MAP45_H /* Port P2.5 mapping register */ +#define P2MAP6 P2MAP67_L /* Port P2.6 mapping register */ +#define P2MAP7 P2MAP67_H /* Port P2.7 mapping register */ + +#endif +/************************************************************ +* PMM - Power Management System +************************************************************/ +#ifdef __MSP430_HAS_PMM__ /* Definition to show that Module is available */ + +#define OFS_PMMCTL0 (0x0000u) /* PMM Control 0 */ +#define OFS_PMMCTL0_L OFS_PMMCTL0 +#define OFS_PMMCTL0_H OFS_PMMCTL0+1 +#define OFS_PMMCTL1 (0x0002u) /* PMM Control 1 */ +#define OFS_PMMCTL1_L OFS_PMMCTL1 +#define OFS_PMMCTL1_H OFS_PMMCTL1+1 +#define OFS_SVSMHCTL (0x0004u) /* SVS and SVM high side control register */ +#define OFS_SVSMHCTL_L OFS_SVSMHCTL +#define OFS_SVSMHCTL_H OFS_SVSMHCTL+1 +#define OFS_SVSMLCTL (0x0006u) /* SVS and SVM low side control register */ +#define OFS_SVSMLCTL_L OFS_SVSMLCTL +#define OFS_SVSMLCTL_H OFS_SVSMLCTL+1 +#define OFS_SVSMIO (0x0008u) /* SVSIN and SVSOUT control register */ +#define OFS_SVSMIO_L OFS_SVSMIO +#define OFS_SVSMIO_H OFS_SVSMIO+1 +#define OFS_PMMIFG (0x000Cu) /* PMM Interrupt Flag */ +#define OFS_PMMIFG_L OFS_PMMIFG +#define OFS_PMMIFG_H OFS_PMMIFG+1 +#define OFS_PMMRIE (0x000Eu) /* PMM and RESET Interrupt Enable */ +#define OFS_PMMRIE_L OFS_PMMRIE +#define OFS_PMMRIE_H OFS_PMMRIE+1 + +#define PMMPW (0xA500u) /* PMM Register Write Password */ +#define PMMPW_H (0xA5) /* PMM Register Write Password for high word access */ + +/* PMMCTL0 Control Bits */ +#define PMMCOREV0 (0x0001u) /* PMM Core Voltage Bit: 0 */ +#define PMMCOREV1 (0x0002u) /* PMM Core Voltage Bit: 1 */ +#define PMMSWBOR (0x0004u) /* PMM Software BOR */ +#define PMMSWPOR (0x0008u) /* PMM Software POR */ +#define PMMREGOFF (0x0010u) /* PMM Turn Regulator off */ +#define PMMHPMRE (0x0080u) /* PMM Global High Power Module Request Enable */ + +/* PMMCTL0 Control Bits */ +#define PMMCOREV0_L (0x0001u) /* PMM Core Voltage Bit: 0 */ +#define PMMCOREV1_L (0x0002u) /* PMM Core Voltage Bit: 1 */ +#define PMMSWBOR_L (0x0004u) /* PMM Software BOR */ +#define PMMSWPOR_L (0x0008u) /* PMM Software POR */ +#define PMMREGOFF_L (0x0010u) /* PMM Turn Regulator off */ +#define PMMHPMRE_L (0x0080u) /* PMM Global High Power Module Request Enable */ + +#define PMMCOREV_0 (0x0000u) /* PMM Core Voltage 0 (1.35V) */ +#define PMMCOREV_1 (0x0001u) /* PMM Core Voltage 1 (1.55V) */ +#define PMMCOREV_2 (0x0002u) /* PMM Core Voltage 2 (1.75V) */ +#define PMMCOREV_3 (0x0003u) /* PMM Core Voltage 3 (1.85V) */ + +/* PMMCTL1 Control Bits */ +#define PMMREFMD (0x0001u) /* PMM Reference Mode */ +#define PMMCMD0 (0x0010u) /* PMM Voltage Regulator Current Mode Bit: 0 */ +#define PMMCMD1 (0x0020u) /* PMM Voltage Regulator Current Mode Bit: 1 */ + +/* PMMCTL1 Control Bits */ +#define PMMREFMD_L (0x0001u) /* PMM Reference Mode */ +#define PMMCMD0_L (0x0010u) /* PMM Voltage Regulator Current Mode Bit: 0 */ +#define PMMCMD1_L (0x0020u) /* PMM Voltage Regulator Current Mode Bit: 1 */ + +/* SVSMHCTL Control Bits */ +#define SVSMHRRL0 (0x0001u) /* SVS and SVM high side Reset Release Voltage Level Bit: 0 */ +#define SVSMHRRL1 (0x0002u) /* SVS and SVM high side Reset Release Voltage Level Bit: 1 */ +#define SVSMHRRL2 (0x0004u) /* SVS and SVM high side Reset Release Voltage Level Bit: 2 */ +#define SVSMHDLYST (0x0008u) /* SVS and SVM high side delay status */ +#define SVSHMD (0x0010u) /* SVS high side mode */ +#define SVSMHEVM (0x0040u) /* SVS and SVM high side event mask */ +#define SVSMHACE (0x0080u) /* SVS and SVM high side auto control enable */ +#define SVSHRVL0 (0x0100u) /* SVS high side reset voltage level Bit: 0 */ +#define SVSHRVL1 (0x0200u) /* SVS high side reset voltage level Bit: 1 */ +#define SVSHE (0x0400u) /* SVS high side enable */ +#define SVSHFP (0x0800u) /* SVS high side full performace mode */ +#define SVMHOVPE (0x1000u) /* SVM high side over-voltage enable */ +#define SVMHE (0x4000u) /* SVM high side enable */ +#define SVMHFP (0x8000u) /* SVM high side full performace mode */ + +/* SVSMHCTL Control Bits */ +#define SVSMHRRL0_L (0x0001u) /* SVS and SVM high side Reset Release Voltage Level Bit: 0 */ +#define SVSMHRRL1_L (0x0002u) /* SVS and SVM high side Reset Release Voltage Level Bit: 1 */ +#define SVSMHRRL2_L (0x0004u) /* SVS and SVM high side Reset Release Voltage Level Bit: 2 */ +#define SVSMHDLYST_L (0x0008u) /* SVS and SVM high side delay status */ +#define SVSHMD_L (0x0010u) /* SVS high side mode */ +#define SVSMHEVM_L (0x0040u) /* SVS and SVM high side event mask */ +#define SVSMHACE_L (0x0080u) /* SVS and SVM high side auto control enable */ + +/* SVSMHCTL Control Bits */ +#define SVSHRVL0_H (0x0001u) /* SVS high side reset voltage level Bit: 0 */ +#define SVSHRVL1_H (0x0002u) /* SVS high side reset voltage level Bit: 1 */ +#define SVSHE_H (0x0004u) /* SVS high side enable */ +#define SVSHFP_H (0x0008u) /* SVS high side full performace mode */ +#define SVMHOVPE_H (0x0010u) /* SVM high side over-voltage enable */ +#define SVMHE_H (0x0040u) /* SVM high side enable */ +#define SVMHFP_H (0x0080u) /* SVM high side full performace mode */ + +#define SVSMHRRL_0 (0x0000u) /* SVS and SVM high side Reset Release Voltage Level 0 */ +#define SVSMHRRL_1 (0x0001u) /* SVS and SVM high side Reset Release Voltage Level 1 */ +#define SVSMHRRL_2 (0x0002u) /* SVS and SVM high side Reset Release Voltage Level 2 */ +#define SVSMHRRL_3 (0x0003u) /* SVS and SVM high side Reset Release Voltage Level 3 */ +#define SVSMHRRL_4 (0x0004u) /* SVS and SVM high side Reset Release Voltage Level 4 */ +#define SVSMHRRL_5 (0x0005u) /* SVS and SVM high side Reset Release Voltage Level 5 */ +#define SVSMHRRL_6 (0x0006u) /* SVS and SVM high side Reset Release Voltage Level 6 */ +#define SVSMHRRL_7 (0x0007u) /* SVS and SVM high side Reset Release Voltage Level 7 */ + +#define SVSHRVL_0 (0x0000u) /* SVS high side Reset Release Voltage Level 0 */ +#define SVSHRVL_1 (0x0100u) /* SVS high side Reset Release Voltage Level 1 */ +#define SVSHRVL_2 (0x0200u) /* SVS high side Reset Release Voltage Level 2 */ +#define SVSHRVL_3 (0x0300u) /* SVS high side Reset Release Voltage Level 3 */ + +/* SVSMLCTL Control Bits */ +#define SVSMLRRL0 (0x0001u) /* SVS and SVM low side Reset Release Voltage Level Bit: 0 */ +#define SVSMLRRL1 (0x0002u) /* SVS and SVM low side Reset Release Voltage Level Bit: 1 */ +#define SVSMLRRL2 (0x0004u) /* SVS and SVM low side Reset Release Voltage Level Bit: 2 */ +#define SVSMLDLYST (0x0008u) /* SVS and SVM low side delay status */ +#define SVSLMD (0x0010u) /* SVS low side mode */ +#define SVSMLEVM (0x0040u) /* SVS and SVM low side event mask */ +#define SVSMLACE (0x0080u) /* SVS and SVM low side auto control enable */ +#define SVSLRVL0 (0x0100u) /* SVS low side reset voltage level Bit: 0 */ +#define SVSLRVL1 (0x0200u) /* SVS low side reset voltage level Bit: 1 */ +#define SVSLE (0x0400u) /* SVS low side enable */ +#define SVSLFP (0x0800u) /* SVS low side full performace mode */ +#define SVMLOVPE (0x1000u) /* SVM low side over-voltage enable */ +#define SVMLE (0x4000u) /* SVM low side enable */ +#define SVMLFP (0x8000u) /* SVM low side full performace mode */ + +/* SVSMLCTL Control Bits */ +#define SVSMLRRL0_L (0x0001u) /* SVS and SVM low side Reset Release Voltage Level Bit: 0 */ +#define SVSMLRRL1_L (0x0002u) /* SVS and SVM low side Reset Release Voltage Level Bit: 1 */ +#define SVSMLRRL2_L (0x0004u) /* SVS and SVM low side Reset Release Voltage Level Bit: 2 */ +#define SVSMLDLYST_L (0x0008u) /* SVS and SVM low side delay status */ +#define SVSLMD_L (0x0010u) /* SVS low side mode */ +#define SVSMLEVM_L (0x0040u) /* SVS and SVM low side event mask */ +#define SVSMLACE_L (0x0080u) /* SVS and SVM low side auto control enable */ + +/* SVSMLCTL Control Bits */ +#define SVSLRVL0_H (0x0001u) /* SVS low side reset voltage level Bit: 0 */ +#define SVSLRVL1_H (0x0002u) /* SVS low side reset voltage level Bit: 1 */ +#define SVSLE_H (0x0004u) /* SVS low side enable */ +#define SVSLFP_H (0x0008u) /* SVS low side full performace mode */ +#define SVMLOVPE_H (0x0010u) /* SVM low side over-voltage enable */ +#define SVMLE_H (0x0040u) /* SVM low side enable */ +#define SVMLFP_H (0x0080u) /* SVM low side full performace mode */ + +#define SVSMLRRL_0 (0x0000u) /* SVS and SVM low side Reset Release Voltage Level 0 */ +#define SVSMLRRL_1 (0x0001u) /* SVS and SVM low side Reset Release Voltage Level 1 */ +#define SVSMLRRL_2 (0x0002u) /* SVS and SVM low side Reset Release Voltage Level 2 */ +#define SVSMLRRL_3 (0x0003u) /* SVS and SVM low side Reset Release Voltage Level 3 */ +#define SVSMLRRL_4 (0x0004u) /* SVS and SVM low side Reset Release Voltage Level 4 */ +#define SVSMLRRL_5 (0x0005u) /* SVS and SVM low side Reset Release Voltage Level 5 */ +#define SVSMLRRL_6 (0x0006u) /* SVS and SVM low side Reset Release Voltage Level 6 */ +#define SVSMLRRL_7 (0x0007u) /* SVS and SVM low side Reset Release Voltage Level 7 */ + +#define SVSLRVL_0 (0x0000u) /* SVS low side Reset Release Voltage Level 0 */ +#define SVSLRVL_1 (0x0100u) /* SVS low side Reset Release Voltage Level 1 */ +#define SVSLRVL_2 (0x0200u) /* SVS low side Reset Release Voltage Level 2 */ +#define SVSLRVL_3 (0x0300u) /* SVS low side Reset Release Voltage Level 3 */ + +/* SVSMIO Control Bits */ +#define SVMLOE (0x0008u) /* SVM low side output enable */ +#define SVMLVLROE (0x0010u) /* SVM low side voltage level reached output enable */ +#define SVMOUTPOL (0x0020u) /* SVMOUT pin polarity */ +#define SVMHOE (0x0800u) /* SVM high side output enable */ +#define SVMHVLROE (0x1000u) /* SVM high side voltage level reached output enable */ + +/* SVSMIO Control Bits */ +#define SVMLOE_L (0x0008u) /* SVM low side output enable */ +#define SVMLVLROE_L (0x0010u) /* SVM low side voltage level reached output enable */ +#define SVMOUTPOL_L (0x0020u) /* SVMOUT pin polarity */ + +/* SVSMIO Control Bits */ +#define SVMHOE_H (0x0008u) /* SVM high side output enable */ +#define SVMHVLROE_H (0x0010u) /* SVM high side voltage level reached output enable */ + +/* PMMIFG Control Bits */ +#define SVSMLDLYIFG (0x0001u) /* SVS and SVM low side Delay expired interrupt flag */ +#define SVMLIFG (0x0002u) /* SVM low side interrupt flag */ +#define SVMLVLRIFG (0x0004u) /* SVM low side Voltage Level Reached interrupt flag */ +#define SVSMHDLYIFG (0x0010u) /* SVS and SVM high side Delay expired interrupt flag */ +#define SVMHIFG (0x0020u) /* SVM high side interrupt flag */ +#define SVMHVLRIFG (0x0040u) /* SVM high side Voltage Level Reached interrupt flag */ +#define PMMBORIFG (0x0100u) /* PMM Software BOR interrupt flag */ +#define PMMRSTIFG (0x0200u) /* PMM RESET pin interrupt flag */ +#define PMMPORIFG (0x0400u) /* PMM Software POR interrupt flag */ +#define SVSHIFG (0x1000u) /* SVS low side interrupt flag */ +#define SVSLIFG (0x2000u) /* SVS high side interrupt flag */ +#define PMMLPM5IFG (0x8000u) /* LPM5 indication Flag */ + +/* PMMIFG Control Bits */ +#define SVSMLDLYIFG_L (0x0001u) /* SVS and SVM low side Delay expired interrupt flag */ +#define SVMLIFG_L (0x0002u) /* SVM low side interrupt flag */ +#define SVMLVLRIFG_L (0x0004u) /* SVM low side Voltage Level Reached interrupt flag */ +#define SVSMHDLYIFG_L (0x0010u) /* SVS and SVM high side Delay expired interrupt flag */ +#define SVMHIFG_L (0x0020u) /* SVM high side interrupt flag */ +#define SVMHVLRIFG_L (0x0040u) /* SVM high side Voltage Level Reached interrupt flag */ + +/* PMMIFG Control Bits */ +#define PMMBORIFG_H (0x0001u) /* PMM Software BOR interrupt flag */ +#define PMMRSTIFG_H (0x0002u) /* PMM RESET pin interrupt flag */ +#define PMMPORIFG_H (0x0004u) /* PMM Software POR interrupt flag */ +#define SVSHIFG_H (0x0010u) /* SVS low side interrupt flag */ +#define SVSLIFG_H (0x0020u) /* SVS high side interrupt flag */ +#define PMMLPM5IFG_H (0x0080u) /* LPM5 indication Flag */ + +#define PMMRSTLPM5IFG PMMLPM5IFG /* LPM5 indication Flag */ + +/* PMMIE and RESET Control Bits */ +#define SVSMLDLYIE (0x0001u) /* SVS and SVM low side Delay expired interrupt enable */ +#define SVMLIE (0x0002u) /* SVM low side interrupt enable */ +#define SVMLVLRIE (0x0004u) /* SVM low side Voltage Level Reached interrupt enable */ +#define SVSMHDLYIE (0x0010u) /* SVS and SVM high side Delay expired interrupt enable */ +#define SVMHIE (0x0020u) /* SVM high side interrupt enable */ +#define SVMHVLRIE (0x0040u) /* SVM high side Voltage Level Reached interrupt enable */ +#define SVSLPE (0x0100u) /* SVS low side POR enable */ +#define SVMLVLRPE (0x0200u) /* SVM low side Voltage Level reached POR enable */ +#define SVSHPE (0x1000u) /* SVS high side POR enable */ +#define SVMHVLRPE (0x2000u) /* SVM high side Voltage Level reached POR enable */ + +/* PMMIE and RESET Control Bits */ +#define SVSMLDLYIE_L (0x0001u) /* SVS and SVM low side Delay expired interrupt enable */ +#define SVMLIE_L (0x0002u) /* SVM low side interrupt enable */ +#define SVMLVLRIE_L (0x0004u) /* SVM low side Voltage Level Reached interrupt enable */ +#define SVSMHDLYIE_L (0x0010u) /* SVS and SVM high side Delay expired interrupt enable */ +#define SVMHIE_L (0x0020u) /* SVM high side interrupt enable */ +#define SVMHVLRIE_L (0x0040u) /* SVM high side Voltage Level Reached interrupt enable */ + +/* PMMIE and RESET Control Bits */ +#define SVSLPE_H (0x0001u) /* SVS low side POR enable */ +#define SVMLVLRPE_H (0x0002u) /* SVM low side Voltage Level reached POR enable */ +#define SVSHPE_H (0x0010u) /* SVS high side POR enable */ +#define SVMHVLRPE_H (0x0020u) /* SVM high side Voltage Level reached POR enable */ + +#endif +/************************************************************ +* Port U +************************************************************/ +#ifdef __MSP430_HAS_PU__ /* Definition to show that Module is available */ + +/* ========================================================================= */ +/* Port U and LDO Control Registers */ +/* ========================================================================= */ +#define OFS_LDOKEYPID (0x0000u) /* LDO Controller peripheral ID and key register */ +#define OFS_LDOKEYPID_L OFS_LDOKEYPID +#define OFS_LDOKEYPID_H OFS_LDOKEYPID+1 +#define OFS_PUCTL (0x0004u) /* PU Control register */ +#define OFS_PUCTL_L OFS_PUCTL +#define OFS_PUCTL_H OFS_PUCTL+1 +#define OFS_LDOPWRCTL (0x0008u) /* LDO Power control register */ +#define OFS_LDOPWRCTL_L OFS_LDOPWRCTL +#define OFS_LDOPWRCTL_H OFS_LDOPWRCTL+1 + +#define LDOKEY (0x9628u) /* LDO Control Register key */ +#define LDOKEYID LDOKEYPID /* Legacy Definiton */ + +/* PUCTL Control Bits */ +#define PUOUT0 (0x0001u) /* PU - PU Output Signal Bit 0 */ +#define PUOUT1 (0x0002u) /* PU - PU Output Signal Bit 1 */ +#define PUIN0 (0x0004u) /* PU - PU0/DP Input Data */ +#define PUIN1 (0x0008u) /* PU - PU1/DM Input Data */ +#define PUOPE (0x0020u) /* PU - Port Output Enable */ +#define PUIPE (0x0100u) /* PU - PHY Single Ended Input enable */ + +/* PUCTL Control Bits */ +#define PUOUT0_L (0x0001u) /* PU - PU Output Signal Bit 0 */ +#define PUOUT1_L (0x0002u) /* PU - PU Output Signal Bit 1 */ +#define PUIN0_L (0x0004u) /* PU - PU0/DP Input Data */ +#define PUIN1_L (0x0008u) /* PU - PU1/DM Input Data */ +#define PUOPE_L (0x0020u) /* PU - Port Output Enable */ + +/* PUCTL Control Bits */ +#define PUIPE_H (0x0001u) /* PU - PHY Single Ended Input enable */ + +#define PUDIR (0x0020u) /* Legacy Definiton */ +#define PSEIEN (0x0100u) /* Legacy Definiton */ + +/* LDOPWRCTL Control Bits */ +#define LDOOVLIFG (0x0001u) /* PU - LDOO Overload Interrupt Flag */ +#define LDOONIFG (0x0002u) /* PU - LDOI "Coming ON" Interrupt Flag */ +#define LDOOFFIFG (0x0004u) /* PU - LDOI "Going OFF" Interrupt Flag */ +#define LDOBGVBV (0x0008u) /* PU - LDO Bandgap and LDOI valid */ +#define OVLAOFF (0x0020u) /* PU - LDO overload auto off enable */ +#define LDOOVLIE (0x0100u) /* PU - Overload indication Interrupt Enable */ +#define LDOONIE (0x0200u) /* PU - LDOI "Coming ON" Interrupt Enable */ +#define LDOOFFIE (0x0400u) /* PU - LDOI "Going OFF" Interrupt Enable */ +#define LDOEN (0x0800u) /* PU - LDO Enable (3.3V) */ + +/* LDOPWRCTL Control Bits */ +#define LDOOVLIFG_L (0x0001u) /* PU - LDOO Overload Interrupt Flag */ +#define LDOONIFG_L (0x0002u) /* PU - LDOI "Coming ON" Interrupt Flag */ +#define LDOOFFIFG_L (0x0004u) /* PU - LDOI "Going OFF" Interrupt Flag */ +#define LDOBGVBV_L (0x0008u) /* PU - LDO Bandgap and LDOI valid */ +#define OVLAOFF_L (0x0020u) /* PU - LDO overload auto off enable */ + +/* LDOPWRCTL Control Bits */ +#define LDOOVLIE_H (0x0001u) /* PU - Overload indication Interrupt Enable */ +#define LDOONIE_H (0x0002u) /* PU - LDOI "Coming ON" Interrupt Enable */ +#define LDOOFFIE_H (0x0004u) /* PU - LDOI "Going OFF" Interrupt Enable */ +#define LDOEN_H (0x0008u) /* PU - LDO Enable (3.3V) */ +#define LDOOEN LDOEN /* Deprecated support for LDO Enable (3.3V) */ +#define LDOOEN_H LDOEN_H /* Deprecated support for LDO Enable (3.3V) */ + +#define VUOVLIFG (0x0001u) /* PU - Legacy Definiton: LDOO Overload Interrupt Flag */ +#define VBONIFG (0x0002u) /* PU - Legacy Definiton: LDOI "Coming ON" Interrupt Flag */ +#define VBOFFIFG (0x0004u) /* PU - Legacy Definiton: LDOI "Going OFF" Interrupt Flag */ +#define VUOVLIE (0x0100u) /* PU - Legacy Definiton: Overload indication Interrupt Enable */ +#define VBONIE (0x0200u) /* PU - Legacy Definiton: LDOI "Coming ON" Interrupt Enable */ +#define VBOFFIE (0x0400u) /* PU - Legacy Definiton: LDOI "Going OFF" Interrupt Enable */ + + +#endif +/************************************************************* +* RAM Control Module +*************************************************************/ +#ifdef __MSP430_HAS_RC__ /* Definition to show that Module is available */ + +#define OFS_RCCTL0 (0x0000u) /* Ram Controller Control Register */ +#define OFS_RCCTL0_L OFS_RCCTL0 +#define OFS_RCCTL0_H OFS_RCCTL0+1 + +/* RCCTL0 Control Bits */ +#define RCRS0OFF (0x0001u) /* RAM Controller RAM Sector 0 Off */ +#define RCRS1OFF (0x0002u) /* RAM Controller RAM Sector 1 Off */ +#define RCRS2OFF (0x0004u) /* RAM Controller RAM Sector 2 Off */ +#define RCRS3OFF (0x0008u) /* RAM Controller RAM Sector 3 Off */ +#define RCRS4OFF (0x0010u) /* RAM Controller RAM Sector 4 Off */ +#define RCRS5OFF (0x0020u) /* RAM Controller RAM Sector 5 Off */ +#define RCRS6OFF (0x0040u) /* RAM Controller RAM Sector 6 Off */ +#define RCRS7OFF (0x0080u) /* RAM Controller RAM Sector 7 (USB) Off */ + +/* RCCTL0 Control Bits */ +#define RCRS0OFF_L (0x0001u) /* RAM Controller RAM Sector 0 Off */ +#define RCRS1OFF_L (0x0002u) /* RAM Controller RAM Sector 1 Off */ +#define RCRS2OFF_L (0x0004u) /* RAM Controller RAM Sector 2 Off */ +#define RCRS3OFF_L (0x0008u) /* RAM Controller RAM Sector 3 Off */ +#define RCRS4OFF_L (0x0010u) /* RAM Controller RAM Sector 4 Off */ +#define RCRS5OFF_L (0x0020u) /* RAM Controller RAM Sector 5 Off */ +#define RCRS6OFF_L (0x0040u) /* RAM Controller RAM Sector 6 Off */ +#define RCRS7OFF_L (0x0080u) /* RAM Controller RAM Sector 7 (USB) Off */ + +#define RCKEY (0x5A00u) + +#endif +/************************************************************ +* Shared Reference +************************************************************/ +#ifdef __MSP430_HAS_REF__ /* Definition to show that Module is available */ + +#define OFS_REFCTL0 (0x0000u) /* REF Shared Reference control register 0 */ +#define OFS_REFCTL0_L OFS_REFCTL0 +#define OFS_REFCTL0_H OFS_REFCTL0+1 + +/* REFCTL0 Control Bits */ +#define REFON (0x0001u) /* REF Reference On */ +#define REFOUT (0x0002u) /* REF Reference output Buffer On */ +//#define RESERVED (0x0004u) /* Reserved */ +#define REFTCOFF (0x0008u) /* REF Temp.Sensor off */ +#define REFVSEL0 (0x0010u) /* REF Reference Voltage Level Select Bit:0 */ +#define REFVSEL1 (0x0020u) /* REF Reference Voltage Level Select Bit:1 */ +//#define RESERVED (0x0040u) /* Reserved */ +#define REFMSTR (0x0080u) /* REF Master Control */ +#define REFGENACT (0x0100u) /* REF Reference generator active */ +#define REFBGACT (0x0200u) /* REF Reference bandgap active */ +#define REFGENBUSY (0x0400u) /* REF Reference generator busy */ +#define BGMODE (0x0800u) /* REF Bandgap mode */ +//#define RESERVED (0x1000u) /* Reserved */ +//#define RESERVED (0x2000u) /* Reserved */ +//#define RESERVED (0x4000u) /* Reserved */ +//#define RESERVED (0x8000u) /* Reserved */ + +/* REFCTL0 Control Bits */ +#define REFON_L (0x0001u) /* REF Reference On */ +#define REFOUT_L (0x0002u) /* REF Reference output Buffer On */ +//#define RESERVED (0x0004u) /* Reserved */ +#define REFTCOFF_L (0x0008u) /* REF Temp.Sensor off */ +#define REFVSEL0_L (0x0010u) /* REF Reference Voltage Level Select Bit:0 */ +#define REFVSEL1_L (0x0020u) /* REF Reference Voltage Level Select Bit:1 */ +//#define RESERVED (0x0040u) /* Reserved */ +#define REFMSTR_L (0x0080u) /* REF Master Control */ +//#define RESERVED (0x1000u) /* Reserved */ +//#define RESERVED (0x2000u) /* Reserved */ +//#define RESERVED (0x4000u) /* Reserved */ +//#define RESERVED (0x8000u) /* Reserved */ + +/* REFCTL0 Control Bits */ +//#define RESERVED (0x0004u) /* Reserved */ +//#define RESERVED (0x0040u) /* Reserved */ +#define REFGENACT_H (0x0001u) /* REF Reference generator active */ +#define REFBGACT_H (0x0002u) /* REF Reference bandgap active */ +#define REFGENBUSY_H (0x0004u) /* REF Reference generator busy */ +#define BGMODE_H (0x0008u) /* REF Bandgap mode */ +//#define RESERVED (0x1000u) /* Reserved */ +//#define RESERVED (0x2000u) /* Reserved */ +//#define RESERVED (0x4000u) /* Reserved */ +//#define RESERVED (0x8000u) /* Reserved */ + +#define REFVSEL_0 (0x0000u) /* REF Reference Voltage Level Select 1.5V */ +#define REFVSEL_1 (0x0010u) /* REF Reference Voltage Level Select 2.0V */ +#define REFVSEL_2 (0x0020u) /* REF Reference Voltage Level Select 2.5V */ +#define REFVSEL_3 (0x0030u) /* REF Reference Voltage Level Select 2.5V */ + +#endif +/************************************************************ +* Shared Reference +************************************************************/ +#ifdef __MSP430_HAS_REF__ /* Definition to show that Module is available */ + +#define OFS_REFCTL0 (0x0000u) /* REF Shared Reference control register 0 */ +#define OFS_REFCTL0_L OFS_REFCTL0 +#define OFS_REFCTL0_H OFS_REFCTL0+1 + +/* REFCTL0 Control Bits */ +#define REFON (0x0001u) /* REF Reference On */ +//#define RESERVED (0x0002u) /* Reserved */ +//#define RESERVED (0x0004u) /* Reserved */ +#define REFTCOFF (0x0008u) /* REF Temp.Sensor off */ +#define REFVSEL0 (0x0010u) /* REF Reference Voltage Level Select Bit:0 */ +#define REFVSEL1 (0x0020u) /* REF Reference Voltage Level Select Bit:1 */ +//#define RESERVED (0x0040u) /* Reserved */ +//#define RESERVED (0x0080u) /* Reserved */ +#define REFGENACT (0x0100u) /* REF Reference generator active */ +#define REFBGACT (0x0200u) /* REF Reference bandgap active */ +#define REFGENBUSY (0x0400u) /* REF Reference generator busy */ +#define BGMODE (0x0800u) /* REF Bandgap mode */ +//#define RESERVED (0x1000u) /* Reserved */ +//#define RESERVED (0x2000u) /* Reserved */ +//#define RESERVED (0x4000u) /* Reserved */ +//#define RESERVED (0x8000u) /* Reserved */ + +/* REFCTL0 Control Bits */ +#define REFON_L (0x0001u) /* REF Reference On */ +//#define RESERVED (0x0002u) /* Reserved */ +//#define RESERVED (0x0004u) /* Reserved */ +#define REFTCOFF_L (0x0008u) /* REF Temp.Sensor off */ +#define REFVSEL0_L (0x0010u) /* REF Reference Voltage Level Select Bit:0 */ +#define REFVSEL1_L (0x0020u) /* REF Reference Voltage Level Select Bit:1 */ +//#define RESERVED (0x0040u) /* Reserved */ +//#define RESERVED (0x0080u) /* Reserved */ +//#define RESERVED (0x1000u) /* Reserved */ +//#define RESERVED (0x2000u) /* Reserved */ +//#define RESERVED (0x4000u) /* Reserved */ +//#define RESERVED (0x8000u) /* Reserved */ + +/* REFCTL0 Control Bits */ +//#define RESERVED (0x0002u) /* Reserved */ +//#define RESERVED (0x0004u) /* Reserved */ +//#define RESERVED (0x0040u) /* Reserved */ +//#define RESERVED (0x0080u) /* Reserved */ +#define REFGENACT_H (0x0001u) /* REF Reference generator active */ +#define REFBGACT_H (0x0002u) /* REF Reference bandgap active */ +#define REFGENBUSY_H (0x0004u) /* REF Reference generator busy */ +#define BGMODE_H (0x0008u) /* REF Bandgap mode */ +//#define RESERVED (0x1000u) /* Reserved */ +//#define RESERVED (0x2000u) /* Reserved */ +//#define RESERVED (0x4000u) /* Reserved */ +//#define RESERVED (0x8000u) /* Reserved */ + +#define REFVSEL_0 (0x0000u) /* REF Reference Voltage Level Select 1.5V */ +#define REFVSEL_1 (0x0010u) /* REF Reference Voltage Level Select 2.0V */ +#define REFVSEL_2 (0x0020u) /* REF Reference Voltage Level Select 2.5V */ +#define REFVSEL_3 (0x0030u) /* REF Reference Voltage Level Select 2.5V */ + +#endif +/************************************************************ +* Real Time Clock +************************************************************/ +#ifdef __MSP430_HAS_RTC__ /* Definition to show that Module is available */ + +#define OFS_RTCCTL01 (0x0000u) /* Real Timer Control 0/1 */ +#define OFS_RTCCTL01_L OFS_RTCCTL01 +#define OFS_RTCCTL01_H OFS_RTCCTL01+1 +#define OFS_RTCCTL23 (0x0002u) /* Real Timer Control 2/3 */ +#define OFS_RTCCTL23_L OFS_RTCCTL23 +#define OFS_RTCCTL23_H OFS_RTCCTL23+1 +#define OFS_RTCPS0CTL (0x0008u) /* Real Timer Prescale Timer 0 Control */ +#define OFS_RTCPS0CTL_L OFS_RTCPS0CTL +#define OFS_RTCPS0CTL_H OFS_RTCPS0CTL+1 +#define OFS_RTCPS1CTL (0x000Au) /* Real Timer Prescale Timer 1 Control */ +#define OFS_RTCPS1CTL_L OFS_RTCPS1CTL +#define OFS_RTCPS1CTL_H OFS_RTCPS1CTL+1 +#define OFS_RTCPS (0x000Cu) /* Real Timer Prescale Timer Control */ +#define OFS_RTCPS_L OFS_RTCPS +#define OFS_RTCPS_H OFS_RTCPS+1 +#define OFS_RTCIV (0x000Eu) /* Real Time Clock Interrupt Vector */ +#define OFS_RTCTIM0 (0x0010u) /* Real Time Clock Time 0 */ +#define OFS_RTCTIM0_L OFS_RTCTIM0 +#define OFS_RTCTIM0_H OFS_RTCTIM0+1 +#define OFS_RTCTIM1 (0x0012u) /* Real Time Clock Time 1 */ +#define OFS_RTCTIM1_L OFS_RTCTIM1 +#define OFS_RTCTIM1_H OFS_RTCTIM1+1 +#define OFS_RTCDATE (0x0014u) /* Real Time Clock Date */ +#define OFS_RTCDATE_L OFS_RTCDATE +#define OFS_RTCDATE_H OFS_RTCDATE+1 +#define OFS_RTCYEAR (0x0016u) /* Real Time Clock Year */ +#define OFS_RTCYEAR_L OFS_RTCYEAR +#define OFS_RTCYEAR_H OFS_RTCYEAR+1 +#define OFS_RTCAMINHR (0x0018u) /* Real Time Clock Alarm Min/Hour */ +#define OFS_RTCAMINHR_L OFS_RTCAMINHR +#define OFS_RTCAMINHR_H OFS_RTCAMINHR+1 +#define OFS_RTCADOWDAY (0x001Au) /* Real Time Clock Alarm day of week/day */ +#define OFS_RTCADOWDAY_L OFS_RTCADOWDAY +#define OFS_RTCADOWDAY_H OFS_RTCADOWDAY+1 +#define OFS_RTCSEC (0x0010u) +#define OFS_RTCMIN (0x0011u) +#define OFS_RTCHOUR (0x0012u) +#define OFS_RTCDOW (0x0013u) +#define OFS_RTCDAY (0x0014u) +#define OFS_RTCMON (0x0015u) +#define OFS_RTCAMIN (0x0018u) +#define OFS_RTCAHOUR (0x0019u) +#define OFS_RTCADOW (0x001Au) +#define OFS_RTCADAY (0x001Bu) + +#define RTCCTL0 RTCCTL01_L /* Real Time Clock Control 0 */ +#define RTCCTL1 RTCCTL01_H /* Real Time Clock Control 1 */ +#define RTCCTL2 RTCCTL23_L /* Real Time Clock Control 2 */ +#define RTCCTL3 RTCCTL23_H /* Real Time Clock Control 3 */ +#define RTCNT12 RTCTIM0 +#define RTCNT34 RTCTIM1 +#define RTCNT1 RTCTIM0_L +#define RTCNT2 RTCTIM0_H +#define RTCNT3 RTCTIM1_L +#define RTCNT4 RTCTIM1_H +#define RTCSEC RTCTIM0_L +#define RTCMIN RTCTIM0_H +#define RTCHOUR RTCTIM1_L +#define RTCDOW RTCTIM1_H +#define RTCDAY RTCDATE_L +#define RTCMON RTCDATE_H +#define RTCYEARL RTCYEAR_L +#define RTCYEARH RTCYEAR_H +#define RT0PS RTCPS_L +#define RT1PS RTCPS_H +#define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */ +#define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */ +#define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */ +#define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */ + +/* RTCCTL01 Control Bits */ +#define RTCBCD (0x8000u) /* RTC BCD 0:Binary / 1:BCD */ +#define RTCHOLD (0x4000u) /* RTC Hold */ +#define RTCMODE (0x2000u) /* RTC Mode 0:Counter / 1: Calendar */ +#define RTCRDY (0x1000u) /* RTC Ready */ +#define RTCSSEL1 (0x0800u) /* RTC Source Select 1 */ +#define RTCSSEL0 (0x0400u) /* RTC Source Select 0 */ +#define RTCTEV1 (0x0200u) /* RTC Time Event 1 */ +#define RTCTEV0 (0x0100u) /* RTC Time Event 0 */ +//#define Reserved (0x0080u) +#define RTCTEVIE (0x0040u) /* RTC Time Event Interrupt Enable Flag */ +#define RTCAIE (0x0020u) /* RTC Alarm Interrupt Enable Flag */ +#define RTCRDYIE (0x0010u) /* RTC Ready Interrupt Enable Flag */ +//#define Reserved (0x0008u) +#define RTCTEVIFG (0x0004u) /* RTC Time Event Interrupt Flag */ +#define RTCAIFG (0x0002u) /* RTC Alarm Interrupt Flag */ +#define RTCRDYIFG (0x0001u) /* RTC Ready Interrupt Flag */ + +/* RTCCTL01 Control Bits */ +//#define Reserved (0x0080u) +#define RTCTEVIE_L (0x0040u) /* RTC Time Event Interrupt Enable Flag */ +#define RTCAIE_L (0x0020u) /* RTC Alarm Interrupt Enable Flag */ +#define RTCRDYIE_L (0x0010u) /* RTC Ready Interrupt Enable Flag */ +//#define Reserved (0x0008u) +#define RTCTEVIFG_L (0x0004u) /* RTC Time Event Interrupt Flag */ +#define RTCAIFG_L (0x0002u) /* RTC Alarm Interrupt Flag */ +#define RTCRDYIFG_L (0x0001u) /* RTC Ready Interrupt Flag */ + +/* RTCCTL01 Control Bits */ +#define RTCBCD_H (0x0080u) /* RTC BCD 0:Binary / 1:BCD */ +#define RTCHOLD_H (0x0040u) /* RTC Hold */ +#define RTCMODE_H (0x0020u) /* RTC Mode 0:Counter / 1: Calendar */ +#define RTCRDY_H (0x0010u) /* RTC Ready */ +#define RTCSSEL1_H (0x0008u) /* RTC Source Select 1 */ +#define RTCSSEL0_H (0x0004u) /* RTC Source Select 0 */ +#define RTCTEV1_H (0x0002u) /* RTC Time Event 1 */ +#define RTCTEV0_H (0x0001u) /* RTC Time Event 0 */ +//#define Reserved (0x0080u) +//#define Reserved (0x0008u) + +#define RTCSSEL_0 (0x0000u) /* RTC Source Select ACLK */ +#define RTCSSEL_1 (0x0400u) /* RTC Source Select SMCLK */ +#define RTCSSEL_2 (0x0800u) /* RTC Source Select RT1PS */ +#define RTCSSEL_3 (0x0C00u) /* RTC Source Select RT1PS */ +#define RTCSSEL__ACLK (0x0000u) /* RTC Source Select ACLK */ +#define RTCSSEL__SMCLK (0x0400u) /* RTC Source Select SMCLK */ +#define RTCSSEL__RT1PS (0x0800u) /* RTC Source Select RT1PS */ +#define RTCTEV_0 (0x0000u) /* RTC Time Event: 0 (Min. changed) */ +#define RTCTEV_1 (0x0100u) /* RTC Time Event: 1 (Hour changed) */ +#define RTCTEV_2 (0x0200u) /* RTC Time Event: 2 (12:00 changed) */ +#define RTCTEV_3 (0x0300u) /* RTC Time Event: 3 (00:00 changed) */ +#define RTCTEV__MIN (0x0000u) /* RTC Time Event: 0 (Min. changed) */ +#define RTCTEV__HOUR (0x0100u) /* RTC Time Event: 1 (Hour changed) */ +#define RTCTEV__0000 (0x0200u) /* RTC Time Event: 2 (00:00 changed) */ +#define RTCTEV__1200 (0x0300u) /* RTC Time Event: 3 (12:00 changed) */ + +/* RTCCTL23 Control Bits */ +#define RTCCALF1 (0x0200u) /* RTC Calibration Frequency Bit 1 */ +#define RTCCALF0 (0x0100u) /* RTC Calibration Frequency Bit 0 */ +#define RTCCALS (0x0080u) /* RTC Calibration Sign */ +//#define Reserved (0x0040u) +#define RTCCAL5 (0x0020u) /* RTC Calibration Bit 5 */ +#define RTCCAL4 (0x0010u) /* RTC Calibration Bit 4 */ +#define RTCCAL3 (0x0008u) /* RTC Calibration Bit 3 */ +#define RTCCAL2 (0x0004u) /* RTC Calibration Bit 2 */ +#define RTCCAL1 (0x0002u) /* RTC Calibration Bit 1 */ +#define RTCCAL0 (0x0001u) /* RTC Calibration Bit 0 */ + +/* RTCCTL23 Control Bits */ +#define RTCCALS_L (0x0080u) /* RTC Calibration Sign */ +//#define Reserved (0x0040u) +#define RTCCAL5_L (0x0020u) /* RTC Calibration Bit 5 */ +#define RTCCAL4_L (0x0010u) /* RTC Calibration Bit 4 */ +#define RTCCAL3_L (0x0008u) /* RTC Calibration Bit 3 */ +#define RTCCAL2_L (0x0004u) /* RTC Calibration Bit 2 */ +#define RTCCAL1_L (0x0002u) /* RTC Calibration Bit 1 */ +#define RTCCAL0_L (0x0001u) /* RTC Calibration Bit 0 */ + +/* RTCCTL23 Control Bits */ +#define RTCCALF1_H (0x0002u) /* RTC Calibration Frequency Bit 1 */ +#define RTCCALF0_H (0x0001u) /* RTC Calibration Frequency Bit 0 */ +//#define Reserved (0x0040u) + +#define RTCCALF_0 (0x0000u) /* RTC Calibration Frequency: No Output */ +#define RTCCALF_1 (0x0100u) /* RTC Calibration Frequency: 512 Hz */ +#define RTCCALF_2 (0x0200u) /* RTC Calibration Frequency: 256 Hz */ +#define RTCCALF_3 (0x0300u) /* RTC Calibration Frequency: 1 Hz */ + +#define RTCAE (0x80) /* Real Time Clock Alarm enable */ + +/* RTCPS0CTL Control Bits */ +//#define Reserved (0x8000u) +#define RT0SSEL (0x4000u) /* RTC Prescale Timer 0 Source Select 0:ACLK / 1:SMCLK */ +#define RT0PSDIV2 (0x2000u) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */ +#define RT0PSDIV1 (0x1000u) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */ +#define RT0PSDIV0 (0x0800u) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */ +//#define Reserved (0x0400u) +//#define Reserved (0x0200u) +#define RT0PSHOLD (0x0100u) /* RTC Prescale Timer 0 Hold */ +//#define Reserved (0x0080u) +//#define Reserved (0x0040u) +//#define Reserved (0x0020u) +#define RT0IP2 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */ +#define RT0IP1 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */ +#define RT0IP0 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */ +#define RT0PSIE (0x0002u) /* RTC Prescale Timer 0 Interrupt Enable Flag */ +#define RT0PSIFG (0x0001u) /* RTC Prescale Timer 0 Interrupt Flag */ + +/* RTCPS0CTL Control Bits */ +//#define Reserved (0x8000u) +//#define Reserved (0x0400u) +//#define Reserved (0x0200u) +//#define Reserved (0x0080u) +//#define Reserved (0x0040u) +//#define Reserved (0x0020u) +#define RT0IP2_L (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */ +#define RT0IP1_L (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */ +#define RT0IP0_L (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */ +#define RT0PSIE_L (0x0002u) /* RTC Prescale Timer 0 Interrupt Enable Flag */ +#define RT0PSIFG_L (0x0001u) /* RTC Prescale Timer 0 Interrupt Flag */ + +/* RTCPS0CTL Control Bits */ +//#define Reserved (0x8000u) +#define RT0SSEL_H (0x0040u) /* RTC Prescale Timer 0 Source Select 0:ACLK / 1:SMCLK */ +#define RT0PSDIV2_H (0x0020u) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */ +#define RT0PSDIV1_H (0x0010u) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */ +#define RT0PSDIV0_H (0x0008u) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */ +//#define Reserved (0x0400u) +//#define Reserved (0x0200u) +#define RT0PSHOLD_H (0x0001u) /* RTC Prescale Timer 0 Hold */ +//#define Reserved (0x0080u) +//#define Reserved (0x0040u) +//#define Reserved (0x0020u) + +#define RT0IP_0 (0x0000u) /* RTC Prescale Timer 0 Interrupt Interval /2 */ +#define RT0IP_1 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval /4 */ +#define RT0IP_2 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval /8 */ +#define RT0IP_3 (0x000Cu) /* RTC Prescale Timer 0 Interrupt Interval /16 */ +#define RT0IP_4 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval /32 */ +#define RT0IP_5 (0x0014u) /* RTC Prescale Timer 0 Interrupt Interval /64 */ +#define RT0IP_6 (0x0018u) /* RTC Prescale Timer 0 Interrupt Interval /128 */ +#define RT0IP_7 (0x001Cu) /* RTC Prescale Timer 0 Interrupt Interval /256 */ + +#define RT0PSDIV_0 (0x0000u) /* RTC Prescale Timer 0 Clock Divide /2 */ +#define RT0PSDIV_1 (0x0800u) /* RTC Prescale Timer 0 Clock Divide /4 */ +#define RT0PSDIV_2 (0x1000u) /* RTC Prescale Timer 0 Clock Divide /8 */ +#define RT0PSDIV_3 (0x1800u) /* RTC Prescale Timer 0 Clock Divide /16 */ +#define RT0PSDIV_4 (0x2000u) /* RTC Prescale Timer 0 Clock Divide /32 */ +#define RT0PSDIV_5 (0x2800u) /* RTC Prescale Timer 0 Clock Divide /64 */ +#define RT0PSDIV_6 (0x3000u) /* RTC Prescale Timer 0 Clock Divide /128 */ +#define RT0PSDIV_7 (0x3800u) /* RTC Prescale Timer 0 Clock Divide /256 */ + +/* RTCPS1CTL Control Bits */ +#define RT1SSEL1 (0x8000u) /* RTC Prescale Timer 1 Source Select Bit 1 */ +#define RT1SSEL0 (0x4000u) /* RTC Prescale Timer 1 Source Select Bit 0 */ +#define RT1PSDIV2 (0x2000u) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */ +#define RT1PSDIV1 (0x1000u) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */ +#define RT1PSDIV0 (0x0800u) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */ +//#define Reserved (0x0400u) +//#define Reserved (0x0200u) +#define RT1PSHOLD (0x0100u) /* RTC Prescale Timer 1 Hold */ +//#define Reserved (0x0080u) +//#define Reserved (0x0040u) +//#define Reserved (0x0020u) +#define RT1IP2 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */ +#define RT1IP1 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */ +#define RT1IP0 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */ +#define RT1PSIE (0x0002u) /* RTC Prescale Timer 1 Interrupt Enable Flag */ +#define RT1PSIFG (0x0001u) /* RTC Prescale Timer 1 Interrupt Flag */ + +/* RTCPS1CTL Control Bits */ +//#define Reserved (0x0400u) +//#define Reserved (0x0200u) +//#define Reserved (0x0080u) +//#define Reserved (0x0040u) +//#define Reserved (0x0020u) +#define RT1IP2_L (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */ +#define RT1IP1_L (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */ +#define RT1IP0_L (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */ +#define RT1PSIE_L (0x0002u) /* RTC Prescale Timer 1 Interrupt Enable Flag */ +#define RT1PSIFG_L (0x0001u) /* RTC Prescale Timer 1 Interrupt Flag */ + +/* RTCPS1CTL Control Bits */ +#define RT1SSEL1_H (0x0080u) /* RTC Prescale Timer 1 Source Select Bit 1 */ +#define RT1SSEL0_H (0x0040u) /* RTC Prescale Timer 1 Source Select Bit 0 */ +#define RT1PSDIV2_H (0x0020u) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */ +#define RT1PSDIV1_H (0x0010u) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */ +#define RT1PSDIV0_H (0x0008u) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */ +//#define Reserved (0x0400u) +//#define Reserved (0x0200u) +#define RT1PSHOLD_H (0x0001u) /* RTC Prescale Timer 1 Hold */ +//#define Reserved (0x0080u) +//#define Reserved (0x0040u) +//#define Reserved (0x0020u) + +#define RT1IP_0 (0x0000u) /* RTC Prescale Timer 1 Interrupt Interval /2 */ +#define RT1IP_1 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval /4 */ +#define RT1IP_2 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval /8 */ +#define RT1IP_3 (0x000Cu) /* RTC Prescale Timer 1 Interrupt Interval /16 */ +#define RT1IP_4 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval /32 */ +#define RT1IP_5 (0x0014u) /* RTC Prescale Timer 1 Interrupt Interval /64 */ +#define RT1IP_6 (0x0018u) /* RTC Prescale Timer 1 Interrupt Interval /128 */ +#define RT1IP_7 (0x001Cu) /* RTC Prescale Timer 1 Interrupt Interval /256 */ + +#define RT1PSDIV_0 (0x0000u) /* RTC Prescale Timer 1 Clock Divide /2 */ +#define RT1PSDIV_1 (0x0800u) /* RTC Prescale Timer 1 Clock Divide /4 */ +#define RT1PSDIV_2 (0x1000u) /* RTC Prescale Timer 1 Clock Divide /8 */ +#define RT1PSDIV_3 (0x1800u) /* RTC Prescale Timer 1 Clock Divide /16 */ +#define RT1PSDIV_4 (0x2000u) /* RTC Prescale Timer 1 Clock Divide /32 */ +#define RT1PSDIV_5 (0x2800u) /* RTC Prescale Timer 1 Clock Divide /64 */ +#define RT1PSDIV_6 (0x3000u) /* RTC Prescale Timer 1 Clock Divide /128 */ +#define RT1PSDIV_7 (0x3800u) /* RTC Prescale Timer 1 Clock Divide /256 */ + +#define RT1SSEL_0 (0x0000u) /* RTC Prescale Timer Source Select ACLK */ +#define RT1SSEL_1 (0x4000u) /* RTC Prescale Timer Source Select SMCLK */ +#define RT1SSEL_2 (0x8000u) /* RTC Prescale Timer Source Select RT0PS */ +#define RT1SSEL_3 (0xC000u) /* RTC Prescale Timer Source Select RT0PS */ + +/* RTC Definitions */ +#define RTCIV_NONE (0x0000u) /* No Interrupt pending */ +#define RTCIV_RTCRDYIFG (0x0002u) /* RTC ready: RTCRDYIFG */ +#define RTCIV_RTCTEVIFG (0x0004u) /* RTC interval timer: RTCTEVIFG */ +#define RTCIV_RTCAIFG (0x0006u) /* RTC user alarm: RTCAIFG */ +#define RTCIV_RT0PSIFG (0x0008u) /* RTC prescaler 0: RT0PSIFG */ +#define RTCIV_RT1PSIFG (0x000Au) /* RTC prescaler 1: RT1PSIFG */ + +/* Legacy Definitions */ +#define RTC_NONE (0x0000u) /* No Interrupt pending */ +#define RTC_RTCRDYIFG (0x0002u) /* RTC ready: RTCRDYIFG */ +#define RTC_RTCTEVIFG (0x0004u) /* RTC interval timer: RTCTEVIFG */ +#define RTC_RTCAIFG (0x0006u) /* RTC user alarm: RTCAIFG */ +#define RTC_RT0PSIFG (0x0008u) /* RTC prescaler 0: RT0PSIFG */ +#define RTC_RT1PSIFG (0x000Au) /* RTC prescaler 1: RT1PSIFG */ + +#endif +/************************************************************ +* Real Time Clock +************************************************************/ +#ifdef __MSP430_HAS_RTC_B__ /* Definition to show that Module is available */ + +#define OFS_RTCCTL01 (0x0000u) /* Real Timer Control 0/1 */ +#define OFS_RTCCTL01_L OFS_RTCCTL01 +#define OFS_RTCCTL01_H OFS_RTCCTL01+1 +#define OFS_RTCCTL23 (0x0002u) /* Real Timer Control 2/3 */ +#define OFS_RTCCTL23_L OFS_RTCCTL23 +#define OFS_RTCCTL23_H OFS_RTCCTL23+1 +#define OFS_RTCPS0CTL (0x0008u) /* Real Timer Prescale Timer 0 Control */ +#define OFS_RTCPS0CTL_L OFS_RTCPS0CTL +#define OFS_RTCPS0CTL_H OFS_RTCPS0CTL+1 +#define OFS_RTCPS1CTL (0x000Au) /* Real Timer Prescale Timer 1 Control */ +#define OFS_RTCPS1CTL_L OFS_RTCPS1CTL +#define OFS_RTCPS1CTL_H OFS_RTCPS1CTL+1 +#define OFS_RTCPS (0x000Cu) /* Real Timer Prescale Timer Control */ +#define OFS_RTCPS_L OFS_RTCPS +#define OFS_RTCPS_H OFS_RTCPS+1 +#define OFS_RTCIV (0x000Eu) /* Real Time Clock Interrupt Vector */ +#define OFS_RTCTIM0 (0x0010u) /* Real Time Clock Time 0 */ +#define OFS_RTCTIM0_L OFS_RTCTIM0 +#define OFS_RTCTIM0_H OFS_RTCTIM0+1 +#define OFS_RTCTIM1 (0x0012u) /* Real Time Clock Time 1 */ +#define OFS_RTCTIM1_L OFS_RTCTIM1 +#define OFS_RTCTIM1_H OFS_RTCTIM1+1 +#define OFS_RTCDATE (0x0014u) /* Real Time Clock Date */ +#define OFS_RTCDATE_L OFS_RTCDATE +#define OFS_RTCDATE_H OFS_RTCDATE+1 +#define OFS_RTCYEAR (0x0016u) /* Real Time Clock Year */ +#define OFS_RTCYEAR_L OFS_RTCYEAR +#define OFS_RTCYEAR_H OFS_RTCYEAR+1 +#define OFS_RTCAMINHR (0x0018u) /* Real Time Clock Alarm Min/Hour */ +#define OFS_RTCAMINHR_L OFS_RTCAMINHR +#define OFS_RTCAMINHR_H OFS_RTCAMINHR+1 +#define OFS_RTCADOWDAY (0x001Au) /* Real Time Clock Alarm day of week/day */ +#define OFS_RTCADOWDAY_L OFS_RTCADOWDAY +#define OFS_RTCADOWDAY_H OFS_RTCADOWDAY+1 +#define OFS_BIN2BCD (0x001Cu) /* Real Time Binary-to-BCD conversion register */ +#define OFS_BCD2BIN (0x001Eu) /* Real Time BCD-to-binary conversion register */ +#define OFS_RTCSEC (0x0010u) +#define OFS_RTCMIN (0x0011u) +#define OFS_RTCHOUR (0x0012u) +#define OFS_RTCDOW (0x0013u) +#define OFS_RTCDAY (0x0014u) +#define OFS_RTCMON (0x0015u) +#define OFS_RTCAMIN (0x0018u) +#define OFS_RTCAHOUR (0x0019u) +#define OFS_RTCADOW (0x001Au) +#define OFS_RTCADAY (0x001Bu) + +#define RTCCTL0 RTCCTL01_L /* Real Time Clock Control 0 */ +#define RTCCTL1 RTCCTL01_H /* Real Time Clock Control 1 */ +#define RTCCTL2 RTCCTL23_L /* Real Time Clock Control 2 */ +#define RTCCTL3 RTCCTL23_H /* Real Time Clock Control 3 */ +#define RTCNT12 RTCTIM0 +#define RTCNT34 RTCTIM1 +#define RTCNT1 RTCTIM0_L +#define RTCNT2 RTCTIM0_H +#define RTCNT3 RTCTIM1_L +#define RTCNT4 RTCTIM1_H +#define RTCSEC RTCTIM0_L +#define RTCMIN RTCTIM0_H +#define RTCHOUR RTCTIM1_L +#define RTCDOW RTCTIM1_H +#define RTCDAY RTCDATE_L +#define RTCMON RTCDATE_H +#define RTCYEARL RTCYEAR_L +#define RTCYEARH RTCYEAR_H +#define RT0PS RTCPS_L +#define RT1PS RTCPS_H +#define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */ +#define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */ +#define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */ +#define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */ + +/* RTCCTL01 Control Bits */ +#define RTCBCD (0x8000u) /* RTC BCD 0:Binary / 1:BCD */ +#define RTCHOLD (0x4000u) /* RTC Hold */ +//#define RESERVED (0x2000u) /* RESERVED */ +#define RTCRDY (0x1000u) /* RTC Ready */ +//#define RESERVED (0x0800u) /* RESERVED */ +//#define RESERVED (0x0400u) /* RESERVED */ +#define RTCTEV1 (0x0200u) /* RTC Time Event 1 */ +#define RTCTEV0 (0x0100u) /* RTC Time Event 0 */ +#define RTCOFIE (0x0080u) /* RTC 32kHz cyrstal oscillator fault interrupt enable */ +#define RTCTEVIE (0x0040u) /* RTC Time Event Interrupt Enable Flag */ +#define RTCAIE (0x0020u) /* RTC Alarm Interrupt Enable Flag */ +#define RTCRDYIE (0x0010u) /* RTC Ready Interrupt Enable Flag */ +#define RTCOFIFG (0x0008u) /* RTC 32kHz cyrstal oscillator fault interrupt flag */ +#define RTCTEVIFG (0x0004u) /* RTC Time Event Interrupt Flag */ +#define RTCAIFG (0x0002u) /* RTC Alarm Interrupt Flag */ +#define RTCRDYIFG (0x0001u) /* RTC Ready Interrupt Flag */ + +/* RTCCTL01 Control Bits */ +//#define RESERVED (0x2000u) /* RESERVED */ +//#define RESERVED (0x0800u) /* RESERVED */ +//#define RESERVED (0x0400u) /* RESERVED */ +#define RTCOFIE_L (0x0080u) /* RTC 32kHz cyrstal oscillator fault interrupt enable */ +#define RTCTEVIE_L (0x0040u) /* RTC Time Event Interrupt Enable Flag */ +#define RTCAIE_L (0x0020u) /* RTC Alarm Interrupt Enable Flag */ +#define RTCRDYIE_L (0x0010u) /* RTC Ready Interrupt Enable Flag */ +#define RTCOFIFG_L (0x0008u) /* RTC 32kHz cyrstal oscillator fault interrupt flag */ +#define RTCTEVIFG_L (0x0004u) /* RTC Time Event Interrupt Flag */ +#define RTCAIFG_L (0x0002u) /* RTC Alarm Interrupt Flag */ +#define RTCRDYIFG_L (0x0001u) /* RTC Ready Interrupt Flag */ + +/* RTCCTL01 Control Bits */ +#define RTCBCD_H (0x0080u) /* RTC BCD 0:Binary / 1:BCD */ +#define RTCHOLD_H (0x0040u) /* RTC Hold */ +//#define RESERVED (0x2000u) /* RESERVED */ +#define RTCRDY_H (0x0010u) /* RTC Ready */ +//#define RESERVED (0x0800u) /* RESERVED */ +//#define RESERVED (0x0400u) /* RESERVED */ +#define RTCTEV1_H (0x0002u) /* RTC Time Event 1 */ +#define RTCTEV0_H (0x0001u) /* RTC Time Event 0 */ + +#define RTCTEV_0 (0x0000u) /* RTC Time Event: 0 (Min. changed) */ +#define RTCTEV_1 (0x0100u) /* RTC Time Event: 1 (Hour changed) */ +#define RTCTEV_2 (0x0200u) /* RTC Time Event: 2 (12:00 changed) */ +#define RTCTEV_3 (0x0300u) /* RTC Time Event: 3 (00:00 changed) */ +#define RTCTEV__MIN (0x0000u) /* RTC Time Event: 0 (Min. changed) */ +#define RTCTEV__HOUR (0x0100u) /* RTC Time Event: 1 (Hour changed) */ +#define RTCTEV__0000 (0x0200u) /* RTC Time Event: 2 (00:00 changed) */ +#define RTCTEV__1200 (0x0300u) /* RTC Time Event: 3 (12:00 changed) */ + +/* RTCCTL23 Control Bits */ +#define RTCCALF1 (0x0200u) /* RTC Calibration Frequency Bit 1 */ +#define RTCCALF0 (0x0100u) /* RTC Calibration Frequency Bit 0 */ +#define RTCCALS (0x0080u) /* RTC Calibration Sign */ +//#define Reserved (0x0040u) +#define RTCCAL5 (0x0020u) /* RTC Calibration Bit 5 */ +#define RTCCAL4 (0x0010u) /* RTC Calibration Bit 4 */ +#define RTCCAL3 (0x0008u) /* RTC Calibration Bit 3 */ +#define RTCCAL2 (0x0004u) /* RTC Calibration Bit 2 */ +#define RTCCAL1 (0x0002u) /* RTC Calibration Bit 1 */ +#define RTCCAL0 (0x0001u) /* RTC Calibration Bit 0 */ + +/* RTCCTL23 Control Bits */ +#define RTCCALS_L (0x0080u) /* RTC Calibration Sign */ +//#define Reserved (0x0040u) +#define RTCCAL5_L (0x0020u) /* RTC Calibration Bit 5 */ +#define RTCCAL4_L (0x0010u) /* RTC Calibration Bit 4 */ +#define RTCCAL3_L (0x0008u) /* RTC Calibration Bit 3 */ +#define RTCCAL2_L (0x0004u) /* RTC Calibration Bit 2 */ +#define RTCCAL1_L (0x0002u) /* RTC Calibration Bit 1 */ +#define RTCCAL0_L (0x0001u) /* RTC Calibration Bit 0 */ + +/* RTCCTL23 Control Bits */ +#define RTCCALF1_H (0x0002u) /* RTC Calibration Frequency Bit 1 */ +#define RTCCALF0_H (0x0001u) /* RTC Calibration Frequency Bit 0 */ +//#define Reserved (0x0040u) + +#define RTCCALF_0 (0x0000u) /* RTC Calibration Frequency: No Output */ +#define RTCCALF_1 (0x0100u) /* RTC Calibration Frequency: 512 Hz */ +#define RTCCALF_2 (0x0200u) /* RTC Calibration Frequency: 256 Hz */ +#define RTCCALF_3 (0x0300u) /* RTC Calibration Frequency: 1 Hz */ + +#define RTCAE (0x80) /* Real Time Clock Alarm enable */ + +/* RTCPS0CTL Control Bits */ +//#define Reserved (0x0080u) +//#define Reserved (0x0040u) +//#define Reserved (0x0020u) +#define RT0IP2 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */ +#define RT0IP1 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */ +#define RT0IP0 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */ +#define RT0PSIE (0x0002u) /* RTC Prescale Timer 0 Interrupt Enable Flag */ +#define RT0PSIFG (0x0001u) /* RTC Prescale Timer 0 Interrupt Flag */ + +/* RTCPS0CTL Control Bits */ +//#define Reserved (0x0080u) +//#define Reserved (0x0040u) +//#define Reserved (0x0020u) +#define RT0IP2_L (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */ +#define RT0IP1_L (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */ +#define RT0IP0_L (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */ +#define RT0PSIE_L (0x0002u) /* RTC Prescale Timer 0 Interrupt Enable Flag */ +#define RT0PSIFG_L (0x0001u) /* RTC Prescale Timer 0 Interrupt Flag */ + +#define RT0IP_0 (0x0000u) /* RTC Prescale Timer 0 Interrupt Interval /2 */ +#define RT0IP_1 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval /4 */ +#define RT0IP_2 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval /8 */ +#define RT0IP_3 (0x000Cu) /* RTC Prescale Timer 0 Interrupt Interval /16 */ +#define RT0IP_4 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval /32 */ +#define RT0IP_5 (0x0014u) /* RTC Prescale Timer 0 Interrupt Interval /64 */ +#define RT0IP_6 (0x0018u) /* RTC Prescale Timer 0 Interrupt Interval /128 */ +#define RT0IP_7 (0x001Cu) /* RTC Prescale Timer 0 Interrupt Interval /256 */ + +#define RT0IP__2 (0x0000u) /* RTC Prescale Timer 0 Interrupt Interval /2 */ +#define RT0IP__4 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval /4 */ +#define RT0IP__8 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval /8 */ +#define RT0IP__16 (0x000Cu) /* RTC Prescale Timer 0 Interrupt Interval /16 */ +#define RT0IP__32 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval /32 */ +#define RT0IP__64 (0x0014u) /* RTC Prescale Timer 0 Interrupt Interval /64 */ +#define RT0IP__128 (0x0018u) /* RTC Prescale Timer 0 Interrupt Interval /128 */ +#define RT0IP__256 (0x001Cu) /* RTC Prescale Timer 0 Interrupt Interval /256 */ + +/* RTCPS1CTL Control Bits */ +//#define Reserved (0x0080u) +//#define Reserved (0x0040u) +//#define Reserved (0x0020u) +#define RT1IP2 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */ +#define RT1IP1 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */ +#define RT1IP0 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */ +#define RT1PSIE (0x0002u) /* RTC Prescale Timer 1 Interrupt Enable Flag */ +#define RT1PSIFG (0x0001u) /* RTC Prescale Timer 1 Interrupt Flag */ + +/* RTCPS1CTL Control Bits */ +//#define Reserved (0x0080u) +//#define Reserved (0x0040u) +//#define Reserved (0x0020u) +#define RT1IP2_L (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */ +#define RT1IP1_L (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */ +#define RT1IP0_L (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */ +#define RT1PSIE_L (0x0002u) /* RTC Prescale Timer 1 Interrupt Enable Flag */ +#define RT1PSIFG_L (0x0001u) /* RTC Prescale Timer 1 Interrupt Flag */ + +#define RT1IP_0 (0x0000u) /* RTC Prescale Timer 1 Interrupt Interval /2 */ +#define RT1IP_1 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval /4 */ +#define RT1IP_2 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval /8 */ +#define RT1IP_3 (0x000Cu) /* RTC Prescale Timer 1 Interrupt Interval /16 */ +#define RT1IP_4 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval /32 */ +#define RT1IP_5 (0x0014u) /* RTC Prescale Timer 1 Interrupt Interval /64 */ +#define RT1IP_6 (0x0018u) /* RTC Prescale Timer 1 Interrupt Interval /128 */ +#define RT1IP_7 (0x001Cu) /* RTC Prescale Timer 1 Interrupt Interval /256 */ + +#define RT1IP__2 (0x0000u) /* RTC Prescale Timer 1 Interrupt Interval /2 */ +#define RT1IP__4 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval /4 */ +#define RT1IP__8 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval /8 */ +#define RT1IP__16 (0x000Cu) /* RTC Prescale Timer 1 Interrupt Interval /16 */ +#define RT1IP__32 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval /32 */ +#define RT1IP__64 (0x0014u) /* RTC Prescale Timer 1 Interrupt Interval /64 */ +#define RT1IP__128 (0x0018u) /* RTC Prescale Timer 1 Interrupt Interval /128 */ +#define RT1IP__256 (0x001Cu) /* RTC Prescale Timer 1 Interrupt Interval /256 */ + +/* RTC Definitions */ +#define RTCIV_NONE (0x0000u) /* No Interrupt pending */ +#define RTCIV_RTCRDYIFG (0x0002u) /* RTC ready: RTCRDYIFG */ +#define RTCIV_RTCTEVIFG (0x0004u) /* RTC interval timer: RTCTEVIFG */ +#define RTCIV_RTCAIFG (0x0006u) /* RTC user alarm: RTCAIFG */ +#define RTCIV_RT0PSIFG (0x0008u) /* RTC prescaler 0: RT0PSIFG */ +#define RTCIV_RT1PSIFG (0x000Au) /* RTC prescaler 1: RT1PSIFG */ +#define RTCIV_RTCOFIFG (0x000Cu) /* RTC Oscillator fault */ + +/* Legacy Definitions */ +#define RTC_NONE (0x0000u) /* No Interrupt pending */ +#define RTC_RTCRDYIFG (0x0002u) /* RTC ready: RTCRDYIFG */ +#define RTC_RTCTEVIFG (0x0004u) /* RTC interval timer: RTCTEVIFG */ +#define RTC_RTCAIFG (0x0006u) /* RTC user alarm: RTCAIFG */ +#define RTC_RT0PSIFG (0x0008u) /* RTC prescaler 0: RT0PSIFG */ +#define RTC_RT1PSIFG (0x000Au) /* RTC prescaler 1: RT1PSIFG */ +#define RTC_RTCOFIFG (0x000Cu) /* RTC Oscillator fault */ + +#endif +/************************************************************ +* Real Time Clock +************************************************************/ +#ifdef __MSP430_HAS_RTC_C__ /* Definition to show that Module is available */ + +#define OFS_RTCCTL0 (0x0000u) /* Real Timer Clock Control 0/Key */ +#define OFS_RTCCTL0_L OFS_RTCCTL0 +#define OFS_RTCCTL0_H OFS_RTCCTL0+1 +#define OFS_RTCCTL13 (0x0002u) /* Real Timer Clock Control 1/3 */ +#define OFS_RTCCTL13_L OFS_RTCCTL13 +#define OFS_RTCCTL13_H OFS_RTCCTL13+1 +#define RTCCTL1 RTCCTL13_L +#define RTCCTL3 RTCCTL13_H +#define OFS_RTCOCAL (0x0004u) /* Real Timer Clock Offset Calibartion */ +#define OFS_RTCOCAL_L OFS_RTCOCAL +#define OFS_RTCOCAL_H OFS_RTCOCAL+1 +#define OFS_RTCTCMP (0x0006u) /* Real Timer Temperature Compensation */ +#define OFS_RTCTCMP_L OFS_RTCTCMP +#define OFS_RTCTCMP_H OFS_RTCTCMP+1 +#define OFS_RTCPS0CTL (0x0008u) /* Real Timer Prescale Timer 0 Control */ +#define OFS_RTCPS0CTL_L OFS_RTCPS0CTL +#define OFS_RTCPS0CTL_H OFS_RTCPS0CTL+1 +#define OFS_RTCPS1CTL (0x000Au) /* Real Timer Prescale Timer 1 Control */ +#define OFS_RTCPS1CTL_L OFS_RTCPS1CTL +#define OFS_RTCPS1CTL_H OFS_RTCPS1CTL+1 +#define OFS_RTCPS (0x000Cu) /* Real Timer Prescale Timer Control */ +#define OFS_RTCPS_L OFS_RTCPS +#define OFS_RTCPS_H OFS_RTCPS+1 +#define OFS_RTCIV (0x000Eu) /* Real Time Clock Interrupt Vector */ +#define OFS_RTCTIM0 (0x0010u) /* Real Time Clock Time 0 */ +#define OFS_RTCTIM0_L OFS_RTCTIM0 +#define OFS_RTCTIM0_H OFS_RTCTIM0+1 +#define OFS_RTCTIM1 (0x0012u) /* Real Time Clock Time 1 */ +#define OFS_RTCTIM1_L OFS_RTCTIM1 +#define OFS_RTCTIM1_H OFS_RTCTIM1+1 +#define OFS_RTCDATE (0x0014u) /* Real Time Clock Date */ +#define OFS_RTCDATE_L OFS_RTCDATE +#define OFS_RTCDATE_H OFS_RTCDATE+1 +#define OFS_RTCYEAR (0x0016u) /* Real Time Clock Year */ +#define OFS_RTCYEAR_L OFS_RTCYEAR +#define OFS_RTCYEAR_H OFS_RTCYEAR+1 +#define OFS_RTCAMINHR (0x0018u) /* Real Time Clock Alarm Min/Hour */ +#define OFS_RTCAMINHR_L OFS_RTCAMINHR +#define OFS_RTCAMINHR_H OFS_RTCAMINHR+1 +#define OFS_RTCADOWDAY (0x001Au) /* Real Time Clock Alarm day of week/day */ +#define OFS_RTCADOWDAY_L OFS_RTCADOWDAY +#define OFS_RTCADOWDAY_H OFS_RTCADOWDAY+1 +#define OFS_BIN2BCD (0x001Cu) /* Real Time Binary-to-BCD conversion register */ +#define OFS_BCD2BIN (0x001Eu) /* Real Time BCD-to-binary conversion register */ +#define OFS_RTCSEC (0x0010u) +#define OFS_RTCMIN (0x0011u) +#define OFS_RTCHOUR (0x0012u) +#define OFS_RTCDOW (0x0013u) +#define OFS_RTCDAY (0x0014u) +#define OFS_RTCMON (0x0015u) +#define OFS_RTCAMIN (0x0018u) +#define OFS_RTCAHOUR (0x0019u) +#define OFS_RTCADOW (0x001Au) +#define OFS_RTCADAY (0x001Bu) + +#define RTCSEC RTCTIM0_L +#define RTCMIN RTCTIM0_H +#define RTCHOUR RTCTIM1_L +#define RTCDOW RTCTIM1_H +#define RTCDAY RTCDATE_L +#define RTCMON RTCDATE_H +#define RTCYEARL RTCYEAR_L +#define RT0PS RTCPS_L +#define RT1PS RTCPS_H +#define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */ +#define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */ +#define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */ +#define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */ + +/* RTCCTL0 Control Bits */ +#define RTCOFIE (0x0080u) /* RTC 32kHz cyrstal oscillator fault interrupt enable */ +#define RTCTEVIE (0x0040u) /* RTC Time Event Interrupt Enable Flag */ +#define RTCAIE (0x0020u) /* RTC Alarm Interrupt Enable Flag */ +#define RTCRDYIE (0x0010u) /* RTC Ready Interrupt Enable Flag */ +#define RTCOFIFG (0x0008u) /* RTC 32kHz cyrstal oscillator fault interrupt flag */ +#define RTCTEVIFG (0x0004u) /* RTC Time Event Interrupt Flag */ +#define RTCAIFG (0x0002u) /* RTC Alarm Interrupt Flag */ +#define RTCRDYIFG (0x0001u) /* RTC Ready Interrupt Flag */ + +/* RTCCTL0 Control Bits */ +#define RTCOFIE_L (0x0080u) /* RTC 32kHz cyrstal oscillator fault interrupt enable */ +#define RTCTEVIE_L (0x0040u) /* RTC Time Event Interrupt Enable Flag */ +#define RTCAIE_L (0x0020u) /* RTC Alarm Interrupt Enable Flag */ +#define RTCRDYIE_L (0x0010u) /* RTC Ready Interrupt Enable Flag */ +#define RTCOFIFG_L (0x0008u) /* RTC 32kHz cyrstal oscillator fault interrupt flag */ +#define RTCTEVIFG_L (0x0004u) /* RTC Time Event Interrupt Flag */ +#define RTCAIFG_L (0x0002u) /* RTC Alarm Interrupt Flag */ +#define RTCRDYIFG_L (0x0001u) /* RTC Ready Interrupt Flag */ + +#define RTCKEY (0xA500u) /* RTC Key for RTC write access */ +#define RTCKEY_H (0xA5) /* RTC Key for RTC write access (high word) */ + +/* RTCCTL13 Control Bits */ +#define RTCCALF1 (0x0200u) /* RTC Calibration Frequency Bit 1 */ +#define RTCCALF0 (0x0100u) /* RTC Calibration Frequency Bit 0 */ +#define RTCBCD (0x0080u) /* RTC BCD 0:Binary / 1:BCD */ +#define RTCHOLD (0x0040u) /* RTC Hold */ +#define RTCMODE (0x0020u) /* RTC Mode 0:Counter / 1: Calendar */ +#define RTCRDY (0x0010u) /* RTC Ready */ +#define RTCSSEL1 (0x0008u) /* RTC Source Select 1 */ +#define RTCSSEL0 (0x0004u) /* RTC Source Select 0 */ +#define RTCTEV1 (0x0002u) /* RTC Time Event 1 */ +#define RTCTEV0 (0x0001u) /* RTC Time Event 0 */ + +/* RTCCTL13 Control Bits */ +#define RTCBCD_L (0x0080u) /* RTC BCD 0:Binary / 1:BCD */ +#define RTCHOLD_L (0x0040u) /* RTC Hold */ +#define RTCMODE_L (0x0020u) /* RTC Mode 0:Counter / 1: Calendar */ +#define RTCRDY_L (0x0010u) /* RTC Ready */ +#define RTCSSEL1_L (0x0008u) /* RTC Source Select 1 */ +#define RTCSSEL0_L (0x0004u) /* RTC Source Select 0 */ +#define RTCTEV1_L (0x0002u) /* RTC Time Event 1 */ +#define RTCTEV0_L (0x0001u) /* RTC Time Event 0 */ + +/* RTCCTL13 Control Bits */ +#define RTCCALF1_H (0x0002u) /* RTC Calibration Frequency Bit 1 */ +#define RTCCALF0_H (0x0001u) /* RTC Calibration Frequency Bit 0 */ + +#define RTCSSEL_0 (0x0000u) /* RTC Source Select ACLK */ +#define RTCSSEL_1 (0x0004u) /* RTC Source Select SMCLK */ +#define RTCSSEL_2 (0x0008u) /* RTC Source Select RT1PS */ +#define RTCSSEL_3 (0x000Cu) /* RTC Source Select RT1PS */ +#define RTCSSEL__ACLK (0x0000u) /* RTC Source Select ACLK */ +#define RTCSSEL__SMCLK (0x0004u) /* RTC Source Select SMCLK */ +#define RTCSSEL__RT1PS (0x0008u) /* RTC Source Select RT1PS */ + +#define RTCTEV_0 (0x0000u) /* RTC Time Event: 0 (Min. changed) */ +#define RTCTEV_1 (0x0001u) /* RTC Time Event: 1 (Hour changed) */ +#define RTCTEV_2 (0x0002u) /* RTC Time Event: 2 (12:00 changed) */ +#define RTCTEV_3 (0x0003u) /* RTC Time Event: 3 (00:00 changed) */ +#define RTCTEV__MIN (0x0000u) /* RTC Time Event: 0 (Min. changed) */ +#define RTCTEV__HOUR (0x0001u) /* RTC Time Event: 1 (Hour changed) */ +#define RTCTEV__0000 (0x0002u) /* RTC Time Event: 2 (00:00 changed) */ +#define RTCTEV__1200 (0x0003u) /* RTC Time Event: 3 (12:00 changed) */ + +#define RTCCALF_0 (0x0000u) /* RTC Calibration Frequency: No Output */ +#define RTCCALF_1 (0x0100u) /* RTC Calibration Frequency: 512 Hz */ +#define RTCCALF_2 (0x0200u) /* RTC Calibration Frequency: 256 Hz */ +#define RTCCALF_3 (0x0300u) /* RTC Calibration Frequency: 1 Hz */ + +/* RTCOCAL Control Bits */ +#define RTCOCALS (0x8000u) /* RTC Offset Calibration Sign */ +#define RTCOCAL7 (0x0080u) /* RTC Offset Calibration Bit 7 */ +#define RTCOCAL6 (0x0040u) /* RTC Offset Calibration Bit 6 */ +#define RTCOCAL5 (0x0020u) /* RTC Offset Calibration Bit 5 */ +#define RTCOCAL4 (0x0010u) /* RTC Offset Calibration Bit 4 */ +#define RTCOCAL3 (0x0008u) /* RTC Offset Calibration Bit 3 */ +#define RTCOCAL2 (0x0004u) /* RTC Offset Calibration Bit 2 */ +#define RTCOCAL1 (0x0002u) /* RTC Offset Calibration Bit 1 */ +#define RTCOCAL0 (0x0001u) /* RTC Offset Calibration Bit 0 */ + +/* RTCOCAL Control Bits */ +#define RTCOCAL7_L (0x0080u) /* RTC Offset Calibration Bit 7 */ +#define RTCOCAL6_L (0x0040u) /* RTC Offset Calibration Bit 6 */ +#define RTCOCAL5_L (0x0020u) /* RTC Offset Calibration Bit 5 */ +#define RTCOCAL4_L (0x0010u) /* RTC Offset Calibration Bit 4 */ +#define RTCOCAL3_L (0x0008u) /* RTC Offset Calibration Bit 3 */ +#define RTCOCAL2_L (0x0004u) /* RTC Offset Calibration Bit 2 */ +#define RTCOCAL1_L (0x0002u) /* RTC Offset Calibration Bit 1 */ +#define RTCOCAL0_L (0x0001u) /* RTC Offset Calibration Bit 0 */ + +/* RTCOCAL Control Bits */ +#define RTCOCALS_H (0x0080u) /* RTC Offset Calibration Sign */ + +/* RTCTCMP Control Bits */ +#define RTCTCMPS (0x8000u) /* RTC Temperature Compensation Sign */ +#define RTCTCRDY (0x4000u) /* RTC Temperature compensation ready */ +#define RTCTCOK (0x2000u) /* RTC Temperature compensation write OK */ +#define RTCTCMP7 (0x0080u) /* RTC Temperature Compensation Bit 7 */ +#define RTCTCMP6 (0x0040u) /* RTC Temperature Compensation Bit 6 */ +#define RTCTCMP5 (0x0020u) /* RTC Temperature Compensation Bit 5 */ +#define RTCTCMP4 (0x0010u) /* RTC Temperature Compensation Bit 4 */ +#define RTCTCMP3 (0x0008u) /* RTC Temperature Compensation Bit 3 */ +#define RTCTCMP2 (0x0004u) /* RTC Temperature Compensation Bit 2 */ +#define RTCTCMP1 (0x0002u) /* RTC Temperature Compensation Bit 1 */ +#define RTCTCMP0 (0x0001u) /* RTC Temperature Compensation Bit 0 */ + +/* RTCTCMP Control Bits */ +#define RTCTCMP7_L (0x0080u) /* RTC Temperature Compensation Bit 7 */ +#define RTCTCMP6_L (0x0040u) /* RTC Temperature Compensation Bit 6 */ +#define RTCTCMP5_L (0x0020u) /* RTC Temperature Compensation Bit 5 */ +#define RTCTCMP4_L (0x0010u) /* RTC Temperature Compensation Bit 4 */ +#define RTCTCMP3_L (0x0008u) /* RTC Temperature Compensation Bit 3 */ +#define RTCTCMP2_L (0x0004u) /* RTC Temperature Compensation Bit 2 */ +#define RTCTCMP1_L (0x0002u) /* RTC Temperature Compensation Bit 1 */ +#define RTCTCMP0_L (0x0001u) /* RTC Temperature Compensation Bit 0 */ + +/* RTCTCMP Control Bits */ +#define RTCTCMPS_H (0x0080u) /* RTC Temperature Compensation Sign */ +#define RTCTCRDY_H (0x0040u) /* RTC Temperature compensation ready */ +#define RTCTCOK_H (0x0020u) /* RTC Temperature compensation write OK */ + +#define RTCAE (0x80) /* Real Time Clock Alarm enable */ + +/* RTCPS0CTL Control Bits */ +//#define Reserved (0x8000u) +//#define Reserved (0x4000u) +#define RT0PSDIV2 (0x2000u) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */ +#define RT0PSDIV1 (0x1000u) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */ +#define RT0PSDIV0 (0x0800u) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */ +//#define Reserved (0x0400u) +//#define Reserved (0x0200u) +#define RT0PSHOLD (0x0100u) /* RTC Prescale Timer 0 Hold */ +//#define Reserved (0x0080u) +//#define Reserved (0x0040u) +//#define Reserved (0x0020u) +#define RT0IP2 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */ +#define RT0IP1 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */ +#define RT0IP0 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */ +#define RT0PSIE (0x0002u) /* RTC Prescale Timer 0 Interrupt Enable Flag */ +#define RT0PSIFG (0x0001u) /* RTC Prescale Timer 0 Interrupt Flag */ + +/* RTCPS0CTL Control Bits */ +//#define Reserved (0x8000u) +//#define Reserved (0x4000u) +//#define Reserved (0x0400u) +//#define Reserved (0x0200u) +//#define Reserved (0x0080u) +//#define Reserved (0x0040u) +//#define Reserved (0x0020u) +#define RT0IP2_L (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */ +#define RT0IP1_L (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */ +#define RT0IP0_L (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */ +#define RT0PSIE_L (0x0002u) /* RTC Prescale Timer 0 Interrupt Enable Flag */ +#define RT0PSIFG_L (0x0001u) /* RTC Prescale Timer 0 Interrupt Flag */ + +/* RTCPS0CTL Control Bits */ +//#define Reserved (0x8000u) +//#define Reserved (0x4000u) +#define RT0PSDIV2_H (0x0020u) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */ +#define RT0PSDIV1_H (0x0010u) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */ +#define RT0PSDIV0_H (0x0008u) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */ +//#define Reserved (0x0400u) +//#define Reserved (0x0200u) +#define RT0PSHOLD_H (0x0001u) /* RTC Prescale Timer 0 Hold */ +//#define Reserved (0x0080u) +//#define Reserved (0x0040u) +//#define Reserved (0x0020u) + +#define RT0IP_0 (0x0000u) /* RTC Prescale Timer 0 Interrupt Interval /2 */ +#define RT0IP_1 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval /4 */ +#define RT0IP_2 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval /8 */ +#define RT0IP_3 (0x000Cu) /* RTC Prescale Timer 0 Interrupt Interval /16 */ +#define RT0IP_4 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval /32 */ +#define RT0IP_5 (0x0014u) /* RTC Prescale Timer 0 Interrupt Interval /64 */ +#define RT0IP_6 (0x0018u) /* RTC Prescale Timer 0 Interrupt Interval /128 */ +#define RT0IP_7 (0x001Cu) /* RTC Prescale Timer 0 Interrupt Interval /256 */ + +/* RTCPS1CTL Control Bits */ +#define RT1SSEL1 (0x8000u) /* RTC Prescale Timer 1 Source Select Bit 1 */ +#define RT1SSEL0 (0x4000u) /* RTC Prescale Timer 1 Source Select Bit 0 */ +#define RT1PSDIV2 (0x2000u) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */ +#define RT1PSDIV1 (0x1000u) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */ +#define RT1PSDIV0 (0x0800u) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */ +//#define Reserved (0x0400u) +//#define Reserved (0x0200u) +#define RT1PSHOLD (0x0100u) /* RTC Prescale Timer 1 Hold */ +//#define Reserved (0x0080u) +//#define Reserved (0x0040u) +//#define Reserved (0x0020u) +#define RT1IP2 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */ +#define RT1IP1 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */ +#define RT1IP0 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */ +#define RT1PSIE (0x0002u) /* RTC Prescale Timer 1 Interrupt Enable Flag */ +#define RT1PSIFG (0x0001u) /* RTC Prescale Timer 1 Interrupt Flag */ + +/* RTCPS1CTL Control Bits */ +//#define Reserved (0x0400u) +//#define Reserved (0x0200u) +//#define Reserved (0x0080u) +//#define Reserved (0x0040u) +//#define Reserved (0x0020u) +#define RT1IP2_L (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */ +#define RT1IP1_L (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */ +#define RT1IP0_L (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */ +#define RT1PSIE_L (0x0002u) /* RTC Prescale Timer 1 Interrupt Enable Flag */ +#define RT1PSIFG_L (0x0001u) /* RTC Prescale Timer 1 Interrupt Flag */ + +/* RTCPS1CTL Control Bits */ +#define RT1SSEL1_H (0x0080u) /* RTC Prescale Timer 1 Source Select Bit 1 */ +#define RT1SSEL0_H (0x0040u) /* RTC Prescale Timer 1 Source Select Bit 0 */ +#define RT1PSDIV2_H (0x0020u) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */ +#define RT1PSDIV1_H (0x0010u) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */ +#define RT1PSDIV0_H (0x0008u) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */ +//#define Reserved (0x0400u) +//#define Reserved (0x0200u) +#define RT1PSHOLD_H (0x0001u) /* RTC Prescale Timer 1 Hold */ +//#define Reserved (0x0080u) +//#define Reserved (0x0040u) +//#define Reserved (0x0020u) + +#define RT1IP_0 (0x0000u) /* RTC Prescale Timer 1 Interrupt Interval /2 */ +#define RT1IP_1 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval /4 */ +#define RT1IP_2 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval /8 */ +#define RT1IP_3 (0x000Cu) /* RTC Prescale Timer 1 Interrupt Interval /16 */ +#define RT1IP_4 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval /32 */ +#define RT1IP_5 (0x0014u) /* RTC Prescale Timer 1 Interrupt Interval /64 */ +#define RT1IP_6 (0x0018u) /* RTC Prescale Timer 1 Interrupt Interval /128 */ +#define RT1IP_7 (0x001Cu) /* RTC Prescale Timer 1 Interrupt Interval /256 */ + +/* RTC Definitions */ +#define RTCIV_NONE (0x0000u) /* No Interrupt pending */ +#define RTCIV_RTCOFIFG (0x0002u) /* RTC Osc fault: RTCOFIFG */ +#define RTCIV_RTCRDYIFG (0x0004u) /* RTC ready: RTCRDYIFG */ +#define RTCIV_RTCTEVIFG (0x0006u) /* RTC interval timer: RTCTEVIFG */ +#define RTCIV_RTCAIFG (0x0008u) /* RTC user alarm: RTCAIFG */ +#define RTCIV_RT0PSIFG (0x000Au) /* RTC prescaler 0: RT0PSIFG */ +#define RTCIV_RT1PSIFG (0x000Cu) /* RTC prescaler 1: RT1PSIFG */ + +/* Legacy Definitions */ +#define RTC_NONE (0x0000u) /* No Interrupt pending */ +#define RTC_RTCOFIFG (0x0002u) /* RTC Osc fault: RTCOFIFG */ +#define RTC_RTCRDYIFG (0x0004u) /* RTC ready: RTCRDYIFG */ +#define RTC_RTCTEVIFG (0x0006u) /* RTC interval timer: RTCTEVIFG */ +#define RTC_RTCAIFG (0x0008u) /* RTC user alarm: RTCAIFG */ +#define RTC_RT0PSIFG (0x000Au) /* RTC prescaler 0: RT0PSIFG */ +#define RTC_RT1PSIFG (0x000Cu) /* RTC prescaler 1: RT1PSIFG */ + +#endif +/************************************************************ +* Real Time Clock +************************************************************/ +#ifdef __MSP430_HAS_RTC_CE__ /* Definition to show that Module is available */ + +#define OFS_RTCCTL0 (0x0000u) /* Real Timer Clock Control 0/Key */ +#define OFS_RTCCTL0_L OFS_RTCCTL0 +#define OFS_RTCCTL0_H OFS_RTCCTL0+1 +#define OFS_RTCCTL13 (0x0002u) /* Real Timer Clock Control 1/3 */ +#define OFS_RTCCTL13_L OFS_RTCCTL13 +#define OFS_RTCCTL13_H OFS_RTCCTL13+1 +#define RTCCTL1 RTCCTL13_L +#define RTCCTL3 RTCCTL13_H +#define OFS_RTCOCAL (0x0004u) /* Real Timer Clock Offset Calibartion */ +#define OFS_RTCOCAL_L OFS_RTCOCAL +#define OFS_RTCOCAL_H OFS_RTCOCAL+1 +#define OFS_RTCTCMP (0x0006u) /* Real Timer Temperature Compensation */ +#define OFS_RTCTCMP_L OFS_RTCTCMP +#define OFS_RTCTCMP_H OFS_RTCTCMP+1 +#define OFS_RTCPS0CTL (0x0008u) /* Real Timer Prescale Timer 0 Control */ +#define OFS_RTCPS0CTL_L OFS_RTCPS0CTL +#define OFS_RTCPS0CTL_H OFS_RTCPS0CTL+1 +#define OFS_RTCPS1CTL (0x000Au) /* Real Timer Prescale Timer 1 Control */ +#define OFS_RTCPS1CTL_L OFS_RTCPS1CTL +#define OFS_RTCPS1CTL_H OFS_RTCPS1CTL+1 +#define OFS_RTCPS (0x000Cu) /* Real Timer Prescale Timer Control */ +#define OFS_RTCPS_L OFS_RTCPS +#define OFS_RTCPS_H OFS_RTCPS+1 +#define OFS_RTCIV (0x000Eu) /* Real Time Clock Interrupt Vector */ +#define OFS_RTCTIM0 (0x0010u) /* Real Time Clock Time 0 */ +#define OFS_RTCTIM0_L OFS_RTCTIM0 +#define OFS_RTCTIM0_H OFS_RTCTIM0+1 +#define OFS_RTCTIM1 (0x0012u) /* Real Time Clock Time 1 */ +#define OFS_RTCTIM1_L OFS_RTCTIM1 +#define OFS_RTCTIM1_H OFS_RTCTIM1+1 +#define OFS_RTCDATE (0x0014u) /* Real Time Clock Date */ +#define OFS_RTCDATE_L OFS_RTCDATE +#define OFS_RTCDATE_H OFS_RTCDATE+1 +#define OFS_RTCYEAR (0x0016u) /* Real Time Clock Year */ +#define OFS_RTCYEAR_L OFS_RTCYEAR +#define OFS_RTCYEAR_H OFS_RTCYEAR+1 +#define OFS_RTCAMINHR (0x0018u) /* Real Time Clock Alarm Min/Hour */ +#define OFS_RTCAMINHR_L OFS_RTCAMINHR +#define OFS_RTCAMINHR_H OFS_RTCAMINHR+1 +#define OFS_RTCADOWDAY (0x001Au) /* Real Time Clock Alarm day of week/day */ +#define OFS_RTCADOWDAY_L OFS_RTCADOWDAY +#define OFS_RTCADOWDAY_H OFS_RTCADOWDAY+1 +#define OFS_BIN2BCD (0x001Cu) /* Real Time Binary-to-BCD conversion register */ +#define OFS_BCD2BIN (0x001Eu) /* Real Time BCD-to-binary conversion register */ +#define OFS_RTCSEC (0x0010u) +#define OFS_RTCMIN (0x0011u) +#define OFS_RTCHOUR (0x0012u) +#define OFS_RTCDOW (0x0013u) +#define OFS_RTCDAY (0x0014u) +#define OFS_RTCMON (0x0015u) +#define OFS_RTCAMIN (0x0018u) +#define OFS_RTCAHOUR (0x0019u) +#define OFS_RTCADOW (0x001Au) +#define OFS_RTCADAY (0x001Bu) + +#define OFS_RTCTCCTL0 (0x0020u) /* Real-Time Clock Time Capture Control Register 0 */ +#define OFS_RTCTCCTL1 (0x0021u) /* Real-Time Clock Time Capture Control Register 1 */ +#define OFS_RTCCAP0CTL (0x0022u) /* Tamper Detect Pin 0 Control Register */ +#define OFS_RTCCAP1CTL (0x0023u) /* Tamper Detect Pin 1 Control Register */ +#define OFS_RTCSECBAK0 (0x0030u) /* Real-Time Clock Seconds Backup Register 0 */ +#define OFS_RTCMINBAK0 (0x0031u) /* Real-Time Clock Minutes Backup Register 0 */ +#define OFS_RTCHOURBAK0 (0x0032u) /* Real-Time Clock Hours Backup Register 0 */ +#define OFS_RTCDAYBAK0 (0x0033u) /* Real-Time Clock Days Backup Register 0 */ +#define OFS_RTCMONBAK0 (0x0034u) /* Real-Time Clock Months Backup Register 0 */ +#define OFS_RTCYEARBAK0 (0x0036u) /* Real-Time Clock year Backup Register 0 */ +#define OFS_RTCSECBAK1 (0x0038u) /* Real-Time Clock Seconds Backup Register 1 */ +#define OFS_RTCMINBAK1 (0x0039u) /* Real-Time Clock Minutes Backup Register 1 */ +#define OFS_RTCHOURBAK1 (0x003Au) /* Real-Time Clock Hours Backup Register 1 */ +#define OFS_RTCDAYBAK1 (0x003Bu) /* Real-Time Clock Days Backup Register 1 */ +#define OFS_RTCMONBAK1 (0x003Cu) /* Real-Time Clock Months Backup Register 1 */ +#define OFS_RTCYEARBAK1 (0x003Eu) /* Real-Time Clock Year Backup Register 1 */ + +#define RTCSEC RTCTIM0_L +#define RTCMIN RTCTIM0_H +#define RTCHOUR RTCTIM1_L +#define RTCDOW RTCTIM1_H +#define RTCDAY RTCDATE_L +#define RTCMON RTCDATE_H +#define RTCYEARL RTCYEAR_L +#define RT0PS RTCPS_L +#define RT1PS RTCPS_H +#define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */ +#define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */ +#define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */ +#define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */ + +/* RTCCTL0 Control Bits */ +#define RTCOFIE (0x0080u) /* RTC 32kHz cyrstal oscillator fault interrupt enable */ +#define RTCTEVIE (0x0040u) /* RTC Time Event Interrupt Enable Flag */ +#define RTCAIE (0x0020u) /* RTC Alarm Interrupt Enable Flag */ +#define RTCRDYIE (0x0010u) /* RTC Ready Interrupt Enable Flag */ +#define RTCOFIFG (0x0008u) /* RTC 32kHz cyrstal oscillator fault interrupt flag */ +#define RTCTEVIFG (0x0004u) /* RTC Time Event Interrupt Flag */ +#define RTCAIFG (0x0002u) /* RTC Alarm Interrupt Flag */ +#define RTCRDYIFG (0x0001u) /* RTC Ready Interrupt Flag */ + +/* RTCCTL0 Control Bits */ +#define RTCOFIE_L (0x0080u) /* RTC 32kHz cyrstal oscillator fault interrupt enable */ +#define RTCTEVIE_L (0x0040u) /* RTC Time Event Interrupt Enable Flag */ +#define RTCAIE_L (0x0020u) /* RTC Alarm Interrupt Enable Flag */ +#define RTCRDYIE_L (0x0010u) /* RTC Ready Interrupt Enable Flag */ +#define RTCOFIFG_L (0x0008u) /* RTC 32kHz cyrstal oscillator fault interrupt flag */ +#define RTCTEVIFG_L (0x0004u) /* RTC Time Event Interrupt Flag */ +#define RTCAIFG_L (0x0002u) /* RTC Alarm Interrupt Flag */ +#define RTCRDYIFG_L (0x0001u) /* RTC Ready Interrupt Flag */ + +#define RTCKEY (0xA500u) /* RTC Key for RTC write access */ +#define RTCKEY_H (0xA5) /* RTC Key for RTC write access (high word) */ + +/* RTCCTL13 Control Bits */ +#define RTCCALF1 (0x0200u) /* RTC Calibration Frequency Bit 1 */ +#define RTCCALF0 (0x0100u) /* RTC Calibration Frequency Bit 0 */ +#define RTCBCD (0x0080u) /* RTC BCD 0:Binary / 1:BCD */ +#define RTCHOLD (0x0040u) /* RTC Hold */ +#define RTCMODE (0x0020u) /* RTC Mode 0:Counter / 1: Calendar */ +#define RTCRDY (0x0010u) /* RTC Ready */ +#define RTCSSEL1 (0x0008u) /* RTC Source Select 1 */ +#define RTCSSEL0 (0x0004u) /* RTC Source Select 0 */ +#define RTCTEV1 (0x0002u) /* RTC Time Event 1 */ +#define RTCTEV0 (0x0001u) /* RTC Time Event 0 */ + +/* RTCCTL13 Control Bits */ +#define RTCBCD_L (0x0080u) /* RTC BCD 0:Binary / 1:BCD */ +#define RTCHOLD_L (0x0040u) /* RTC Hold */ +#define RTCMODE_L (0x0020u) /* RTC Mode 0:Counter / 1: Calendar */ +#define RTCRDY_L (0x0010u) /* RTC Ready */ +#define RTCSSEL1_L (0x0008u) /* RTC Source Select 1 */ +#define RTCSSEL0_L (0x0004u) /* RTC Source Select 0 */ +#define RTCTEV1_L (0x0002u) /* RTC Time Event 1 */ +#define RTCTEV0_L (0x0001u) /* RTC Time Event 0 */ + +/* RTCCTL13 Control Bits */ +#define RTCCALF1_H (0x0002u) /* RTC Calibration Frequency Bit 1 */ +#define RTCCALF0_H (0x0001u) /* RTC Calibration Frequency Bit 0 */ + +#define RTCSSEL_0 (0x0000u) /* RTC Source Select ACLK */ +#define RTCSSEL_1 (0x0004u) /* RTC Source Select SMCLK */ +#define RTCSSEL_2 (0x0008u) /* RTC Source Select RT1PS */ +#define RTCSSEL_3 (0x000Cu) /* RTC Source Select RT1PS */ +#define RTCSSEL__ACLK (0x0000u) /* RTC Source Select ACLK */ +#define RTCSSEL__SMCLK (0x0004u) /* RTC Source Select SMCLK */ +#define RTCSSEL__RT1PS (0x0008u) /* RTC Source Select RT1PS */ + +#define RTCTEV_0 (0x0000u) /* RTC Time Event: 0 (Min. changed) */ +#define RTCTEV_1 (0x0001u) /* RTC Time Event: 1 (Hour changed) */ +#define RTCTEV_2 (0x0002u) /* RTC Time Event: 2 (12:00 changed) */ +#define RTCTEV_3 (0x0003u) /* RTC Time Event: 3 (00:00 changed) */ +#define RTCTEV__MIN (0x0000u) /* RTC Time Event: 0 (Min. changed) */ +#define RTCTEV__HOUR (0x0001u) /* RTC Time Event: 1 (Hour changed) */ +#define RTCTEV__0000 (0x0002u) /* RTC Time Event: 2 (00:00 changed) */ +#define RTCTEV__1200 (0x0003u) /* RTC Time Event: 3 (12:00 changed) */ + +#define RTCCALF_0 (0x0000u) /* RTC Calibration Frequency: No Output */ +#define RTCCALF_1 (0x0100u) /* RTC Calibration Frequency: 512 Hz */ +#define RTCCALF_2 (0x0200u) /* RTC Calibration Frequency: 256 Hz */ +#define RTCCALF_3 (0x0300u) /* RTC Calibration Frequency: 1 Hz */ + +/* RTCOCAL Control Bits */ +#define RTCOCALS (0x8000u) /* RTC Offset Calibration Sign */ +#define RTCOCAL7 (0x0080u) /* RTC Offset Calibration Bit 7 */ +#define RTCOCAL6 (0x0040u) /* RTC Offset Calibration Bit 6 */ +#define RTCOCAL5 (0x0020u) /* RTC Offset Calibration Bit 5 */ +#define RTCOCAL4 (0x0010u) /* RTC Offset Calibration Bit 4 */ +#define RTCOCAL3 (0x0008u) /* RTC Offset Calibration Bit 3 */ +#define RTCOCAL2 (0x0004u) /* RTC Offset Calibration Bit 2 */ +#define RTCOCAL1 (0x0002u) /* RTC Offset Calibration Bit 1 */ +#define RTCOCAL0 (0x0001u) /* RTC Offset Calibration Bit 0 */ + +/* RTCOCAL Control Bits */ +#define RTCOCAL7_L (0x0080u) /* RTC Offset Calibration Bit 7 */ +#define RTCOCAL6_L (0x0040u) /* RTC Offset Calibration Bit 6 */ +#define RTCOCAL5_L (0x0020u) /* RTC Offset Calibration Bit 5 */ +#define RTCOCAL4_L (0x0010u) /* RTC Offset Calibration Bit 4 */ +#define RTCOCAL3_L (0x0008u) /* RTC Offset Calibration Bit 3 */ +#define RTCOCAL2_L (0x0004u) /* RTC Offset Calibration Bit 2 */ +#define RTCOCAL1_L (0x0002u) /* RTC Offset Calibration Bit 1 */ +#define RTCOCAL0_L (0x0001u) /* RTC Offset Calibration Bit 0 */ + +/* RTCOCAL Control Bits */ +#define RTCOCALS_H (0x0080u) /* RTC Offset Calibration Sign */ + +/* RTCTCMP Control Bits */ +#define RTCTCMPS (0x8000u) /* RTC Temperature Compensation Sign */ +#define RTCTCRDY (0x4000u) /* RTC Temperature compensation ready */ +#define RTCTCOK (0x2000u) /* RTC Temperature compensation write OK */ +#define RTCTCMP7 (0x0080u) /* RTC Temperature Compensation Bit 7 */ +#define RTCTCMP6 (0x0040u) /* RTC Temperature Compensation Bit 6 */ +#define RTCTCMP5 (0x0020u) /* RTC Temperature Compensation Bit 5 */ +#define RTCTCMP4 (0x0010u) /* RTC Temperature Compensation Bit 4 */ +#define RTCTCMP3 (0x0008u) /* RTC Temperature Compensation Bit 3 */ +#define RTCTCMP2 (0x0004u) /* RTC Temperature Compensation Bit 2 */ +#define RTCTCMP1 (0x0002u) /* RTC Temperature Compensation Bit 1 */ +#define RTCTCMP0 (0x0001u) /* RTC Temperature Compensation Bit 0 */ + +/* RTCTCMP Control Bits */ +#define RTCTCMP7_L (0x0080u) /* RTC Temperature Compensation Bit 7 */ +#define RTCTCMP6_L (0x0040u) /* RTC Temperature Compensation Bit 6 */ +#define RTCTCMP5_L (0x0020u) /* RTC Temperature Compensation Bit 5 */ +#define RTCTCMP4_L (0x0010u) /* RTC Temperature Compensation Bit 4 */ +#define RTCTCMP3_L (0x0008u) /* RTC Temperature Compensation Bit 3 */ +#define RTCTCMP2_L (0x0004u) /* RTC Temperature Compensation Bit 2 */ +#define RTCTCMP1_L (0x0002u) /* RTC Temperature Compensation Bit 1 */ +#define RTCTCMP0_L (0x0001u) /* RTC Temperature Compensation Bit 0 */ + +/* RTCTCMP Control Bits */ +#define RTCTCMPS_H (0x0080u) /* RTC Temperature Compensation Sign */ +#define RTCTCRDY_H (0x0040u) /* RTC Temperature compensation ready */ +#define RTCTCOK_H (0x0020u) /* RTC Temperature compensation write OK */ + +#define RTCAE (0x80) /* Real Time Clock Alarm enable */ + +/* RTCPS0CTL Control Bits */ +//#define Reserved (0x8000u) +//#define Reserved (0x4000u) +#define RT0PSDIV2 (0x2000u) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */ +#define RT0PSDIV1 (0x1000u) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */ +#define RT0PSDIV0 (0x0800u) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */ +//#define Reserved (0x0400u) +//#define Reserved (0x0200u) +#define RT0PSHOLD (0x0100u) /* RTC Prescale Timer 0 Hold */ +//#define Reserved (0x0080u) +//#define Reserved (0x0040u) +//#define Reserved (0x0020u) +#define RT0IP2 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */ +#define RT0IP1 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */ +#define RT0IP0 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */ +#define RT0PSIE (0x0002u) /* RTC Prescale Timer 0 Interrupt Enable Flag */ +#define RT0PSIFG (0x0001u) /* RTC Prescale Timer 0 Interrupt Flag */ + +/* RTCPS0CTL Control Bits */ +//#define Reserved (0x8000u) +//#define Reserved (0x4000u) +//#define Reserved (0x0400u) +//#define Reserved (0x0200u) +//#define Reserved (0x0080u) +//#define Reserved (0x0040u) +//#define Reserved (0x0020u) +#define RT0IP2_L (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */ +#define RT0IP1_L (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */ +#define RT0IP0_L (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */ +#define RT0PSIE_L (0x0002u) /* RTC Prescale Timer 0 Interrupt Enable Flag */ +#define RT0PSIFG_L (0x0001u) /* RTC Prescale Timer 0 Interrupt Flag */ + +/* RTCPS0CTL Control Bits */ +//#define Reserved (0x8000u) +//#define Reserved (0x4000u) +#define RT0PSDIV2_H (0x0020u) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */ +#define RT0PSDIV1_H (0x0010u) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */ +#define RT0PSDIV0_H (0x0008u) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */ +//#define Reserved (0x0400u) +//#define Reserved (0x0200u) +#define RT0PSHOLD_H (0x0001u) /* RTC Prescale Timer 0 Hold */ +//#define Reserved (0x0080u) +//#define Reserved (0x0040u) +//#define Reserved (0x0020u) + +#define RT0IP_0 (0x0000u) /* RTC Prescale Timer 0 Interrupt Interval /2 */ +#define RT0IP_1 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval /4 */ +#define RT0IP_2 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval /8 */ +#define RT0IP_3 (0x000Cu) /* RTC Prescale Timer 0 Interrupt Interval /16 */ +#define RT0IP_4 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval /32 */ +#define RT0IP_5 (0x0014u) /* RTC Prescale Timer 0 Interrupt Interval /64 */ +#define RT0IP_6 (0x0018u) /* RTC Prescale Timer 0 Interrupt Interval /128 */ +#define RT0IP_7 (0x001Cu) /* RTC Prescale Timer 0 Interrupt Interval /256 */ + +/* RTCPS1CTL Control Bits */ +#define RT1SSEL1 (0x8000u) /* RTC Prescale Timer 1 Source Select Bit 1 */ +#define RT1SSEL0 (0x4000u) /* RTC Prescale Timer 1 Source Select Bit 0 */ +#define RT1PSDIV2 (0x2000u) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */ +#define RT1PSDIV1 (0x1000u) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */ +#define RT1PSDIV0 (0x0800u) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */ +//#define Reserved (0x0400u) +//#define Reserved (0x0200u) +#define RT1PSHOLD (0x0100u) /* RTC Prescale Timer 1 Hold */ +//#define Reserved (0x0080u) +//#define Reserved (0x0040u) +//#define Reserved (0x0020u) +#define RT1IP2 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */ +#define RT1IP1 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */ +#define RT1IP0 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */ +#define RT1PSIE (0x0002u) /* RTC Prescale Timer 1 Interrupt Enable Flag */ +#define RT1PSIFG (0x0001u) /* RTC Prescale Timer 1 Interrupt Flag */ + +/* RTCPS1CTL Control Bits */ +//#define Reserved (0x0400u) +//#define Reserved (0x0200u) +//#define Reserved (0x0080u) +//#define Reserved (0x0040u) +//#define Reserved (0x0020u) +#define RT1IP2_L (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */ +#define RT1IP1_L (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */ +#define RT1IP0_L (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */ +#define RT1PSIE_L (0x0002u) /* RTC Prescale Timer 1 Interrupt Enable Flag */ +#define RT1PSIFG_L (0x0001u) /* RTC Prescale Timer 1 Interrupt Flag */ + +/* RTCPS1CTL Control Bits */ +#define RT1SSEL1_H (0x0080u) /* RTC Prescale Timer 1 Source Select Bit 1 */ +#define RT1SSEL0_H (0x0040u) /* RTC Prescale Timer 1 Source Select Bit 0 */ +#define RT1PSDIV2_H (0x0020u) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */ +#define RT1PSDIV1_H (0x0010u) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */ +#define RT1PSDIV0_H (0x0008u) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */ +//#define Reserved (0x0400u) +//#define Reserved (0x0200u) +#define RT1PSHOLD_H (0x0001u) /* RTC Prescale Timer 1 Hold */ +//#define Reserved (0x0080u) +//#define Reserved (0x0040u) +//#define Reserved (0x0020u) + +#define RT1IP_0 (0x0000u) /* RTC Prescale Timer 1 Interrupt Interval /2 */ +#define RT1IP_1 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval /4 */ +#define RT1IP_2 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval /8 */ +#define RT1IP_3 (0x000Cu) /* RTC Prescale Timer 1 Interrupt Interval /16 */ +#define RT1IP_4 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval /32 */ +#define RT1IP_5 (0x0014u) /* RTC Prescale Timer 1 Interrupt Interval /64 */ +#define RT1IP_6 (0x0018u) /* RTC Prescale Timer 1 Interrupt Interval /128 */ +#define RT1IP_7 (0x001Cu) /* RTC Prescale Timer 1 Interrupt Interval /256 */ + +/* RTCTCCTL0 Control Bits */ +#define TCEN (0x0001u) /* RTC Enable for RTC Tamper Detection with Time Stamp */ +#define AUX3RST (0x0002u) /* RTC Indication of power cycle on AUXVCC3 */ + +/* RTCTCCTL1 Control Bits */ +#define RTCCAPIFG (0x0001u) /* RTC Tamper Event Interrupt Flag */ +#define RTCCAPIE (0x0002u) /* RTC Tamper Event Interrupt Enable */ + +/* RTCCAPxCTL Control Bits */ +#define CAPEV (0x0001u) /* RTC Tamper Event Flag */ +#define CAPES (0x0004u) /* RTC Event Edge Select */ +#define RTCREN (0x0008u) /* RTC RTCCAPx pin pullup/pulldown resistor enable */ +#define RTCCAPIN (0x0010u) /* RTC RTCCAPx input */ +#define RTCCAPDIR (0x0020u) /* RTC RTCCAPx Pin direction */ +#define RTCCAPOUT (0x0040u) /* RTC RTCCAPx Output */ + +/* RTCIV Definitions */ +#define RTCIV_NONE (0x0000u) /* No Interrupt pending */ +#define RTCIV_RTCOFIFG (0x0002u) /* RTC Osc fault: RTCOFIFG */ +#define RTCIV_RTCCAPIFG (0x0004u) /* RTC RTC Tamper Event: RTCCAPIFG */ +#define RTCIV_RTCRDYIFG (0x0006u) /* RTC ready: RTCRDYIFG */ +#define RTCIV_RTCTEVIFG (0x0008u) /* RTC interval timer: RTCTEVIFG */ +#define RTCIV_RTCAIFG (0x000Au) /* RTC user alarm: RTCAIFG */ +#define RTCIV_RT0PSIFG (0x000Cu) /* RTC prescaler 0: RT0PSIFG */ +#define RTCIV_RT1PSIFG (0x000Eu) /* RTC prescaler 1: RT1PSIFG */ + +/* Legacy RTCIV Definitions */ +#define RTC_NONE (0x0000u) /* No Interrupt pending */ +#define RTC_RTCOFIFG (0x0002u) /* RTC Osc fault: RTCOFIFG */ +#define RTC_RTCRDYIFG (0x0006u) /* RTC ready: RTCRDYIFG */ +#define RTC_RTCTEVIFG (0x0008u) /* RTC interval timer: RTCTEVIFG */ +#define RTC_RTCAIFG (0x000Au) /* RTC user alarm: RTCAIFG */ +#define RTC_RT0PSIFG (0x000Cu) /* RTC prescaler 0: RT0PSIFG */ +#define RTC_RT1PSIFG (0x000Eu) /* RTC prescaler 1: RT1PSIFG */ + +#endif +/************************************************************ +* SD24_B - Sigma Delta 24 Bit +************************************************************/ +#ifdef __MSP430_HAS_SD24_B__ /* Definition to show that Module is available */ + +#define OFS_SD24BCTL0 (0x0000u) /* SD24B Control Register 0 */ +#define OFS_SD24BCTL0_L OFS_SD24BCTL0 +#define OFS_SD24BCTL0_H OFS_SD24BCTL0+1 +#define OFS_SD24BCTL1 (0x0002u) /* SD24B Control Register 1 */ +#define OFS_SD24BCTL1_L OFS_SD24BCTL1 +#define OFS_SD24BCTL1_H OFS_SD24BCTL1+1 +#define OFS_SD24BTRGCTL (0x0004u) /* SD24B Trigger Control Register */ +#define OFS_SD24BTRGCTL_L OFS_SD24BTRGCTL +#define OFS_SD24BTRGCTL_H OFS_SD24BTRGCTL+1 +#define OFS_SD24BTRGOSR (0x0006u) /* SD24B Trigger OSR Control Register */ +#define OFS_SD24BTRGOSR_L OFS_SD24BTRGOSR +#define OFS_SD24BTRGOSR_H OFS_SD24BTRGOSR+1 +#define OFS_SD24BTRGPRE (0x0008u) /* SD24B Trigger Preload Register */ +#define OFS_SD24BTRGPRE_L OFS_SD24BTRGPRE +#define OFS_SD24BTRGPRE_H OFS_SD24BTRGPRE+1 +#define OFS_SD24BIFG (0x000Au) /* SD24B Interrupt Flag Register */ +#define OFS_SD24BIFG_L OFS_SD24BIFG +#define OFS_SD24BIFG_H OFS_SD24BIFG+1 +#define OFS_SD24BIE (0x000Cu) /* SD24B Interrupt Enable Register */ +#define OFS_SD24BIE_L OFS_SD24BIE +#define OFS_SD24BIE_H OFS_SD24BIE+1 +#define OFS_SD24BIV (0x000Eu) /* SD24B Interrupt Vector Register */ +#define OFS_SD24BIV_L OFS_SD24BIV +#define OFS_SD24BIV_H OFS_SD24BIV+1 + +#define OFS_SD24BCCTL0 (0x0010u) /* SD24B Channel 0 Control Register */ +#define OFS_SD24BCCTL0_L OFS_SD24BCCTL0 +#define OFS_SD24BCCTL0_H OFS_SD24BCCTL0+1 +#define OFS_SD24BINCTL0 (0x0012u) /* SD24B Channel 0 Input Control Register */ +#define OFS_SD24BINCTL0_L OFS_SD24BINCTL0 +#define OFS_SD24BINCTL0_H OFS_SD24BINCTL0+1 +#define OFS_SD24BOSR0 (0x0014u) /* SD24B Channel 0 OSR Control Register */ +#define OFS_SD24BOSR0_L OFS_SD24BOSR0 +#define OFS_SD24BOSR0_H OFS_SD24BOSR0+1 +#define OFS_SD24BPRE0 (0x0016u) /* SD24B Channel 0 Preload Register */ +#define OFS_SD24BPRE0_L OFS_SD24BPRE0 +#define OFS_SD24BPRE0_H OFS_SD24BPRE0+1 + +#define OFS_SD24BMEML0 (0x0050u) /* SD24B Channel 0 Conversion Memory Low word */ +#define OFS_SD24BMEML0_L OFS_SD24BMEML0 +#define OFS_SD24BMEML0_H OFS_SD24BMEML0+1 +#define OFS_SD24BMEMH0 (0x0052u) /* SD24B Channel 0 Conversion Memory High Word */ +#define OFS_SD24BMEMH0_L OFS_SD24BMEMH0 +#define OFS_SD24BMEMH0_H OFS_SD24BMEMH0+1 + +/* SD24BCTL0 */ +#define SD24OV32 (0x0002u) /* SD24B Overflow Control */ +#define SD24REFS (0x0004u) /* SD24B Reference Select */ +#define SD24SSEL0 (0x0010u) /* SD24B Clock Source Select 0 */ +#define SD24SSEL1 (0x0020u) /* SD24B Clock Source Select 1 */ +#define SD24M4 (0x0040u) /* SD24B Modulator clock to Manchester decoder clock ratio */ +#define SD24CLKOS (0x0080u) /* SD24B Clock Output Select */ +#define SD24PDIV0 (0x0100u) /* SD24B Frequency pre-scaler Bit 0 */ +#define SD24PDIV1 (0x0200u) /* SD24B Frequency pre-scaler Bit 1 */ +#define SD24PDIV2 (0x0400u) /* SD24B Frequency pre-scaler Bit 2 */ +#define SD24DIV0 (0x0800u) /* SD24B Frequency Divider Bit 0 */ +#define SD24DIV1 (0x1000u) /* SD24B Frequency Divider Bit 1 */ +#define SD24DIV2 (0x2000u) /* SD24B Frequency Divider Bit 2 */ +#define SD24DIV3 (0x4000u) /* SD24B Frequency Divider Bit 3 */ +#define SD24DIV4 (0x8000u) /* SD24B Frequency Divider Bit 4 */ + +#define SD24OV32_L (0x0002u) /* SD24B Overflow Control */ +#define SD24REFS_L (0x0004u) /* SD24B Reference Select */ +#define SD24SSEL0_L (0x0010u) /* SD24B Clock Source Select 0 */ +#define SD24SSEL1_L (0x0020u) /* SD24B Clock Source Select 1 */ +#define SD24M4_L (0x0040u) /* SD24B Modulator clock to Manchester decoder clock ratio */ +#define SD24CLKOS_L (0x0080u) /* SD24B Clock Output Select */ + +#define SD24PDIV0_H (0x0001u) /* SD24B Frequency pre-scaler Bit 0 */ +#define SD24PDIV1_H (0x0002u) /* SD24B Frequency pre-scaler Bit 1 */ +#define SD24PDIV2_H (0x0004u) /* SD24B Frequency pre-scaler Bit 2 */ +#define SD24DIV0_H (0x0008u) /* SD24B Frequency Divider Bit 0 */ +#define SD24DIV1_H (0x0010u) /* SD24B Frequency Divider Bit 1 */ +#define SD24DIV2_H (0x0020u) /* SD24B Frequency Divider Bit 2 */ +#define SD24DIV3_H (0x0040u) /* SD24B Frequency Divider Bit 3 */ +#define SD24DIV4_H (0x0080u) /* SD24B Frequency Divider Bit 4 */ + +#define SD24SSEL_0 (0x0000u) /* SD24B Clock Source Select MCLK */ +#define SD24SSEL_1 (0x0010u) /* SD24B Clock Source Select SMCLK */ +#define SD24SSEL_2 (0x0020u) /* SD24B Clock Source Select ACLK */ +#define SD24SSEL_3 (0x0030u) /* SD24B Clock Source Select TACLK */ +#define SD24SSEL__MCLK (0x0000u) /* SD24B Clock Source Select MCLK */ +#define SD24SSEL__SMCLK (0x0010u) /* SD24B Clock Source Select SMCLK */ +#define SD24SSEL__ACLK (0x0020u) /* SD24B Clock Source Select ACLK */ +#define SD24SSEL__SD24CLK (0x0030u) /* SD24B Clock Source Select SD24CLK */ + +#define SD24PDIV_0 (0x0000u) /* SD24B Frequency pre-scaler /1 */ +#define SD24PDIV_1 (0x0100u) /* SD24B Frequency pre-scaler /2 */ +#define SD24PDIV_2 (0x0200u) /* SD24B Frequency pre-scaler /4 */ +#define SD24PDIV_3 (0x0300u) /* SD24B Frequency pre-scaler /8 */ +#define SD24PDIV_4 (0x0400u) /* SD24B Frequency pre-scaler /16 */ +#define SD24PDIV_5 (0x0500u) /* SD24B Frequency pre-scaler /32 */ +#define SD24PDIV_6 (0x0600u) /* SD24B Frequency pre-scaler /64 */ +#define SD24PDIV_7 (0x0700u) /* SD24B Frequency pre-scaler /128 */ + +/* SD24BCTL1 */ +#define SD24GRP0SC (0x0001u) /* SD24B Group 0 Start Conversion */ +#define SD24GRP1SC (0x0002u) /* SD24B Group 1 Start Conversion */ +#define SD24GRP2SC (0x0004u) /* SD24B Group 2 Start Conversion */ +#define SD24GRP3SC (0x0008u) /* SD24B Group 3 Start Conversion */ +#define SD24DMA0 (0x0100u) /* SD24B DMA Trigger Select Bit 0 */ +#define SD24DMA1 (0x0200u) /* SD24B DMA Trigger Select Bit 1 */ +#define SD24DMA2 (0x0400u) /* SD24B DMA Trigger Select Bit 2 */ +#define SD24DMA3 (0x0800u) /* SD24B DMA Trigger Select Bit 3 */ + +#define SD24GRP0SC_L (0x0001u) /* SD24B Group 0 Start Conversion */ +#define SD24GRP1SC_L (0x0002u) /* SD24B Group 1 Start Conversion */ +#define SD24GRP2SC_L (0x0004u) /* SD24B Group 2 Start Conversion */ +#define SD24GRP3SC_L (0x0008u) /* SD24B Group 3 Start Conversion */ + +#define SD24DMA0_H (0x0001u) /* SD24B DMA Trigger Select Bit 0 */ +#define SD24DMA1_H (0x0002u) /* SD24B DMA Trigger Select Bit 1 */ +#define SD24DMA2_H (0x0004u) /* SD24B DMA Trigger Select Bit 2 */ +#define SD24DMA3_H (0x0008u) /* SD24B DMA Trigger Select Bit 3 */ + +#define SD24DMA_0 (0x0000u) /* SD24B DMA Trigger: 0 */ +#define SD24DMA_1 (0x0100u) /* SD24B DMA Trigger: 1 */ +#define SD24DMA_2 (0x0200u) /* SD24B DMA Trigger: 2 */ +#define SD24DMA_3 (0x0300u) /* SD24B DMA Trigger: 3 */ +#define SD24DMA_4 (0x0400u) /* SD24B DMA Trigger: 4 */ +#define SD24DMA_5 (0x0500u) /* SD24B DMA Trigger: 5 */ +#define SD24DMA_6 (0x0600u) /* SD24B DMA Trigger: 6 */ +#define SD24DMA_7 (0x0700u) /* SD24B DMA Trigger: 7 */ +#define SD24DMA_8 (0x0800u) /* SD24B DMA Trigger: 8 */ + +/* SD24BTRGCTL */ +#define SD24SC (0x0001u) /* SD24B Start Conversion */ +#define SD24SCS0 (0x0002u) /* SD24B Start Conversion Select Bit 0 */ +#define SD24SCS1 (0x0004u) /* SD24B Start Conversion Select Bit 1 */ +#define SD24SCS2 (0x0008u) /* SD24B Start Conversion Select Bit 2 */ +#define SD24SNGL (0x0100u) /* SD24B Single Trigger Mode */ +#define SD24TRGIFG (0x0400u) /* SD24B Trigger Interrupt Flag */ +#define SD24TRGIE (0x0800u) /* SD24B Trigger Interrupt Enable */ + +#define SD24SC_L (0x0001u) /* SD24B Start Conversion */ +#define SD24SCS0_L (0x0002u) /* SD24B Start Conversion Select Bit 0 */ +#define SD24SCS1_L (0x0004u) /* SD24B Start Conversion Select Bit 1 */ +#define SD24SCS2_L (0x0008u) /* SD24B Start Conversion Select Bit 2 */ + +#define SD24SNGL_H (0x0001u) /* SD24B Single Trigger Mode */ +#define SD24TRGIFG_H (0x0004u) /* SD24B Trigger Interrupt Flag */ +#define SD24TRGIE_H (0x0008u) /* SD24B Trigger Interrupt Enable */ + +#define SD24SCS_0 (0x0000u) /* SD24B Start Conversion Select: 0 */ +#define SD24SCS_1 (0x0002u) /* SD24B Start Conversion Select: 1 */ +#define SD24SCS_2 (0x0004u) /* SD24B Start Conversion Select: 2 */ +#define SD24SCS_3 (0x0006u) /* SD24B Start Conversion Select: 3 */ +#define SD24SCS_4 (0x0008u) /* SD24B Start Conversion Select: 4 */ +#define SD24SCS_5 (0x000Au) /* SD24B Start Conversion Select: 5 */ +#define SD24SCS_6 (0x000Cu) /* SD24B Start Conversion Select: 6 */ +#define SD24SCS_7 (0x000Eu) /* SD24B Start Conversion Select: 7 */ +#define SD24SCS__SD24SC (0x0000u) /* SD24B Start Conversion Select: SD24SC */ +#define SD24SCS__EXT1 (0x0002u) /* SD24B Start Conversion Select: EXT1 */ +#define SD24SCS__EXT2 (0x0004u) /* SD24B Start Conversion Select: EXT2 */ +#define SD24SCS__EXT3 (0x0006u) /* SD24B Start Conversion Select: EXT3 */ +#define SD24SCS__GROUP0 (0x0008u) /* SD24B Start Conversion Select: GROUP0 */ +#define SD24SCS__GROUP1 (0x000Au) /* SD24B Start Conversion Select: GROUP1 */ +#define SD24SCS__GROUP2 (0x000Cu) /* SD24B Start Conversion Select: GROUP2 */ +#define SD24SCS__GROUP3 (0x000Eu) /* SD24B Start Conversion Select: GROUP3 */ + +/* SD24BIFG */ +#define SD24IFG0 (0x0001u) /* SD24B Channel 0 Interrupt Flag */ +#define SD24OVIFG0 (0x0100u) /* SD24B Channel 0 Overflow Interrupt Flag */ + +#define SD24IFG0_L (0x0001u) /* SD24B Channel 0 Interrupt Flag */ + +#define SD24OVIFG0_H (0x0001u) /* SD24B Channel 0 Overflow Interrupt Flag */ + +/* SD24BIE */ +#define SD24IE0 (0x0001u) /* SD24B Channel 0 Interrupt Enable */ +#define SD24OVIE0 (0x0100u) /* SD24B Channel 0 Overflow Interrupt Enable */ + +#define SD24IE0_L (0x0001u) /* SD24B Channel 0 Interrupt Enable */ + +#define SD24OVIE0_H (0x0001u) /* SD24B Channel 0 Overflow Interrupt Enable */ + +/* SD24BIV Definitions */ +#define SD24BIV_NONE (0x0000u) /* No Interrupt pending */ +#define SD24BIV_SD24OVIFG (0x0002u) /* SD24OVIFG */ +#define SD24BIV_SD24TRGIFG (0x0004u) /* SD24TRGIFG */ +#define SD24BIV_SD24IFG0 (0x0006u) /* SD24IFG0 */ + +/* SD24BCCTLx */ +#define SD24DF0 (0x0010u) /* SD24B Data Format Bit: 0 */ +#define SD24DF1 (0x0020u) /* SD24B Data Format Bit: 1 */ +#define SD24ALGN (0x0040u) /* SD24B Data Alignment */ +#define SD24CAL (0x0200u) /* SD24B Calibration */ +#define SD24DFS0 (0x0400u) /* SD24B Digital Filter Bit: 0 */ +#define SD24DFS1 (0x0800u) /* SD24B Digital Filter Bit: 1 */ +#define SD24DI (0x1000u) /* SD24B Digital Bitstream Input */ +#define SD24MC0 (0x2000u) /* SD24B Manchaster Encoding Bit: 0 */ +#define SD24MC1 (0x4000u) /* SD24B Manchaster Encoding Bit: 1 */ + +#define SD24DF0_L (0x0010u) /* SD24B Data Format Bit: 0 */ +#define SD24DF1_L (0x0020u) /* SD24B Data Format Bit: 1 */ +#define SD24ALGN_L (0x0040u) /* SD24B Data Alignment */ + +#define SD24CAL_H (0x0002u) /* SD24B Calibration */ +#define SD24DFS0_H (0x0004u) /* SD24B Digital Filter Bit: 0 */ +#define SD24DFS1_H (0x0008u) /* SD24B Digital Filter Bit: 1 */ +#define SD24DI_H (0x0010u) /* SD24B Digital Bitstream Input */ +#define SD24MC0_H (0x0020u) /* SD24B Manchaster Encoding Bit: 0 */ +#define SD24MC1_H (0x0040u) /* SD24B Manchaster Encoding Bit: 1 */ + +#define SD24DF_0 (0x0000u) /* SD24B Data Format: Offset Binary */ +#define SD24DF_1 (0x0010u) /* SD24B Data Format: 2's complement */ + +#define SD24DFS_0 (0x0000u) /* SD24B Digital Filter 0 */ +#define SD24DFS_1 (0x0400u) /* SD24B Digital Filter 1 */ +#define SD24DFS_2 (0x0800u) /* SD24B Digital Filter 2 */ +#define SD24DFS_3 (0x0C00u) /* SD24B Digital Filter 3 */ + +#define SD24MC_0 (0x0000u) /* SD24B Manchaster Encoding 0 */ +#define SD24MC_1 (0x2000u) /* SD24B Manchaster Encoding 1 */ +#define SD24MC_2 (0x4000u) /* SD24B Manchaster Encoding 2 */ +#define SD24MC_3 (0x6000u) /* SD24B Manchaster Encoding 3 */ + +/* SD24BINCTLx */ +#define SD24GAIN0 (0x0008u) /* SD24B Input Pre-Amplifier Gain Select 0 */ +#define SD24GAIN1 (0x0010u) /* SD24B Input Pre-Amplifier Gain Select 1 */ +#define SD24GAIN2 (0x0020u) /* SD24B Input Pre-Amplifier Gain Select 2 */ +#define SD24INTDLY0 (0x0040u) /* SD24B Interrupt Delay after 1.Conversion 0 */ +#define SD24INTDLY1 (0x0080u) /* SD24B Interrupt Delay after 1.Conversion 1 */ + +#define SD24GAIN0_L (0x0008u) /* SD24B Input Pre-Amplifier Gain Select 0 */ +#define SD24GAIN1_L (0x0010u) /* SD24B Input Pre-Amplifier Gain Select 1 */ +#define SD24GAIN2_L (0x0020u) /* SD24B Input Pre-Amplifier Gain Select 2 */ +#define SD24INTDLY0_L (0x0040u) /* SD24B Interrupt Delay after 1.Conversion 0 */ +#define SD24INTDLY1_L (0x0080u) /* SD24B Interrupt Delay after 1.Conversion 1 */ + +#define SD24GAIN_1 (0x0000u) /* SD24B Input Pre-Amplifier Gain Select *1 */ +#define SD24GAIN_2 (0x0008u) /* SD24B Input Pre-Amplifier Gain Select *2 */ +#define SD24GAIN_4 (0x0010u) /* SD24B Input Pre-Amplifier Gain Select *4 */ +#define SD24GAIN_8 (0x0018u) /* SD24B Input Pre-Amplifier Gain Select *8 */ +#define SD24GAIN_16 (0x0020u) /* SD24B Input Pre-Amplifier Gain Select *16 */ +#define SD24GAIN_32 (0x0028u) /* SD24B Input Pre-Amplifier Gain Select *32 */ +#define SD24GAIN_64 (0x0030u) /* SD24B Input Pre-Amplifier Gain Select *64 */ +#define SD24GAIN_128 (0x0038u) /* SD24B Input Pre-Amplifier Gain Select *128 */ + +#define SD24INTDLY_0 (0x0000u) /* SD24B Interrupt Delay: Int. after 4.Conversion */ +#define SD24INTDLY_1 (0x0040u) /* SD24B Interrupt Delay: Int. after 3.Conversion */ +#define SD24INTDLY_2 (0x0080u) /* SD24B Interrupt Delay: Int. after 2.Conversion */ +#define SD24INTDLY_3 (0x00C0u) /* SD24B Interrupt Delay: Int. after 1.Conversion */ + +/* SD24BOSRx */ +#define OSR0 (0x0001u) /* SD24B Oversampling Rate Bit: 0 */ +#define OSR1 (0x0002u) /* SD24B Oversampling Rate Bit: 1 */ +#define OSR2 (0x0004u) /* SD24B Oversampling Rate Bit: 2 */ +#define OSR3 (0x0008u) /* SD24B Oversampling Rate Bit: 3 */ +#define OSR4 (0x0010u) /* SD24B Oversampling Rate Bit: 4 */ +#define OSR5 (0x0020u) /* SD24B Oversampling Rate Bit: 5 */ +#define OSR6 (0x0040u) /* SD24B Oversampling Rate Bit: 6 */ +#define OSR7 (0x0080u) /* SD24B Oversampling Rate Bit: 7 */ +#define OSR8 (0x0100u) /* SD24B Oversampling Rate Bit: 8 */ +#define OSR9 (0x0200u) /* SD24B Oversampling Rate Bit: 9 */ +#define OSR10 (0x0400u) /* SD24B Oversampling Rate Bit: 10 */ + +#define OSR0_L (0x0001u) /* SD24B Oversampling Rate Bit: 0 */ +#define OSR1_L (0x0002u) /* SD24B Oversampling Rate Bit: 1 */ +#define OSR2_L (0x0004u) /* SD24B Oversampling Rate Bit: 2 */ +#define OSR3_L (0x0008u) /* SD24B Oversampling Rate Bit: 3 */ +#define OSR4_L (0x0010u) /* SD24B Oversampling Rate Bit: 4 */ +#define OSR5_L (0x0020u) /* SD24B Oversampling Rate Bit: 5 */ +#define OSR6_L (0x0040u) /* SD24B Oversampling Rate Bit: 6 */ +#define OSR7_L (0x0080u) /* SD24B Oversampling Rate Bit: 7 */ + +#define OSR8_H (0x0001u) /* SD24B Oversampling Rate Bit: 8 */ +#define OSR9_H (0x0002u) /* SD24B Oversampling Rate Bit: 9 */ +#define OSR10_H (0x0004u) /* SD24B Oversampling Rate Bit: 10 */ + +/* SD24BTRGOSR */ + +#define OSR__32 (32-1) /* SD24B Oversampling Rate: 32 */ +#define OSR__64 (64-1) /* SD24B Oversampling Rate: 64 */ +#define OSR__128 (128-1) /* SD24B Oversampling Rate: 128 */ +#define OSR__256 (256-1) /* SD24B Oversampling Rate: 256 */ +#define OSR__512 (512-1) /* SD24B Oversampling Rate: 512 */ +#define OSR__1024 (1024-1) /* SD24B Oversampling Rate: 1024 */ + + +#endif +/************************************************************ +* SFR - Special Function Register Module +************************************************************/ +#ifdef __MSP430_HAS_SFR__ /* Definition to show that Module is available */ + +#define OFS_SFRIE1 (0x0000u) /* Interrupt Enable 1 */ +#define OFS_SFRIE1_L OFS_SFRIE1 +#define OFS_SFRIE1_H OFS_SFRIE1+1 + +/* SFRIE1 Control Bits */ +#define WDTIE (0x0001u) /* WDT Interrupt Enable */ +#define OFIE (0x0002u) /* Osc Fault Enable */ +//#define Reserved (0x0004u) +#define VMAIE (0x0008u) /* Vacant Memory Interrupt Enable */ +#define NMIIE (0x0010u) /* NMI Interrupt Enable */ +#ifndef ACCVIE +#define ACCVIE (0x0020u) /* Flash Access Violation Interrupt Enable */ +#endif +#define JMBINIE (0x0040u) /* JTAG Mail Box input Interrupt Enable */ +#define JMBOUTIE (0x0080u) /* JTAG Mail Box output Interrupt Enable */ + +#define WDTIE_L (0x0001u) /* WDT Interrupt Enable */ +#define OFIE_L (0x0002u) /* Osc Fault Enable */ +//#define Reserved (0x0004u) +#define VMAIE_L (0x0008u) /* Vacant Memory Interrupt Enable */ +#define NMIIE_L (0x0010u) /* NMI Interrupt Enable */ +#ifndef ACCVIE +#define ACCVIE_L (0x0020u) /* Flash Access Violation Interrupt Enable */ +#endif +#define JMBINIE_L (0x0040u) /* JTAG Mail Box input Interrupt Enable */ +#define JMBOUTIE_L (0x0080u) /* JTAG Mail Box output Interrupt Enable */ + +#define OFS_SFRIFG1 (0x0002u) /* Interrupt Flag 1 */ +#define OFS_SFRIFG1_L OFS_SFRIFG1 +#define OFS_SFRIFG1_H OFS_SFRIFG1+1 +/* SFRIFG1 Control Bits */ +#define WDTIFG (0x0001u) /* WDT Interrupt Flag */ +#define OFIFG (0x0002u) /* Osc Fault Flag */ +//#define Reserved (0x0004u) +#define VMAIFG (0x0008u) /* Vacant Memory Interrupt Flag */ +#define NMIIFG (0x0010u) /* NMI Interrupt Flag */ +//#define Reserved (0x0020u) +#define JMBINIFG (0x0040u) /* JTAG Mail Box input Interrupt Flag */ +#define JMBOUTIFG (0x0080u) /* JTAG Mail Box output Interrupt Flag */ + +#define WDTIFG_L (0x0001u) /* WDT Interrupt Flag */ +#define OFIFG_L (0x0002u) /* Osc Fault Flag */ +//#define Reserved (0x0004u) +#define VMAIFG_L (0x0008u) /* Vacant Memory Interrupt Flag */ +#define NMIIFG_L (0x0010u) /* NMI Interrupt Flag */ +//#define Reserved (0x0020u) +#define JMBINIFG_L (0x0040u) /* JTAG Mail Box input Interrupt Flag */ +#define JMBOUTIFG_L (0x0080u) /* JTAG Mail Box output Interrupt Flag */ + +#define OFS_SFRRPCR (0x0004u) /* RESET Pin Control Register */ +#define OFS_SFRRPCR_L OFS_SFRRPCR +#define OFS_SFRRPCR_H OFS_SFRRPCR+1 +/* SFRRPCR Control Bits */ +#define SYSNMI (0x0001u) /* NMI select */ +#define SYSNMIIES (0x0002u) /* NMI edge select */ +#define SYSRSTUP (0x0004u) /* RESET Pin pull down/up select */ +#define SYSRSTRE (0x0008u) /* RESET Pin Resistor enable */ + +#define SYSNMI_L (0x0001u) /* NMI select */ +#define SYSNMIIES_L (0x0002u) /* NMI edge select */ +#define SYSRSTUP_L (0x0004u) /* RESET Pin pull down/up select */ +#define SYSRSTRE_L (0x0008u) /* RESET Pin Resistor enable */ + +#endif +/************************************************************ +* SYS - System Module +************************************************************/ +#ifdef __MSP430_HAS_SYS__ /* Definition to show that Module is available */ + +#define OFS_SYSCTL (0x0000u) /* System control */ +#define OFS_SYSCTL_L OFS_SYSCTL +#define OFS_SYSCTL_H OFS_SYSCTL+1 +#define OFS_SYSBSLC (0x0002u) /* Boot strap configuration area */ +#define OFS_SYSBSLC_L OFS_SYSBSLC +#define OFS_SYSBSLC_H OFS_SYSBSLC+1 +#define OFS_SYSJMBC (0x0006u) /* JTAG mailbox control */ +#define OFS_SYSJMBC_L OFS_SYSJMBC +#define OFS_SYSJMBC_H OFS_SYSJMBC+1 +#define OFS_SYSJMBI0 (0x0008u) /* JTAG mailbox input 0 */ +#define OFS_SYSJMBI0_L OFS_SYSJMBI0 +#define OFS_SYSJMBI0_H OFS_SYSJMBI0+1 +#define OFS_SYSJMBI1 (0x000Au) /* JTAG mailbox input 1 */ +#define OFS_SYSJMBI1_L OFS_SYSJMBI1 +#define OFS_SYSJMBI1_H OFS_SYSJMBI1+1 +#define OFS_SYSJMBO0 (0x000Cu) /* JTAG mailbox output 0 */ +#define OFS_SYSJMBO0_L OFS_SYSJMBO0 +#define OFS_SYSJMBO0_H OFS_SYSJMBO0+1 +#define OFS_SYSJMBO1 (0x000Eu) /* JTAG mailbox output 1 */ +#define OFS_SYSJMBO1_L OFS_SYSJMBO1 +#define OFS_SYSJMBO1_H OFS_SYSJMBO1+1 + +#define OFS_SYSBERRIV (0x0018u) /* Bus Error vector generator */ +#define OFS_SYSBERRIV_L OFS_SYSBERRIV +#define OFS_SYSBERRIV_H OFS_SYSBERRIV+1 +#define OFS_SYSUNIV (0x001Au) /* User NMI vector generator */ +#define OFS_SYSUNIV_L OFS_SYSUNIV +#define OFS_SYSUNIV_H OFS_SYSUNIV+1 +#define OFS_SYSSNIV (0x001Cu) /* System NMI vector generator */ +#define OFS_SYSSNIV_L OFS_SYSSNIV +#define OFS_SYSSNIV_H OFS_SYSSNIV+1 +#define OFS_SYSRSTIV (0x001Eu) /* Reset vector generator */ +#define OFS_SYSRSTIV_L OFS_SYSRSTIV +#define OFS_SYSRSTIV_H OFS_SYSRSTIV+1 + +/* SYSCTL Control Bits */ +#define SYSRIVECT (0x0001u) /* SYS - RAM based interrupt vectors */ +//#define RESERVED (0x0002u) /* SYS - Reserved */ +#define SYSPMMPE (0x0004u) /* SYS - PMM access protect */ +//#define RESERVED (0x0008u) /* SYS - Reserved */ +#define SYSBSLIND (0x0010u) /* SYS - TCK/RST indication detected */ +#define SYSJTAGPIN (0x0020u) /* SYS - Dedicated JTAG pins enabled */ +//#define RESERVED (0x0040u) /* SYS - Reserved */ +//#define RESERVED (0x0080u) /* SYS - Reserved */ +//#define RESERVED (0x0100u) /* SYS - Reserved */ +//#define RESERVED (0x0200u) /* SYS - Reserved */ +//#define RESERVED (0x0400u) /* SYS - Reserved */ +//#define RESERVED (0x0800u) /* SYS - Reserved */ +//#define RESERVED (0x1000u) /* SYS - Reserved */ +//#define RESERVED (0x2000u) /* SYS - Reserved */ +//#define RESERVED (0x4000u) /* SYS - Reserved */ +//#define RESERVED (0x8000u) /* SYS - Reserved */ + +/* SYSCTL Control Bits */ +#define SYSRIVECT_L (0x0001u) /* SYS - RAM based interrupt vectors */ +//#define RESERVED (0x0002u) /* SYS - Reserved */ +#define SYSPMMPE_L (0x0004u) /* SYS - PMM access protect */ +//#define RESERVED (0x0008u) /* SYS - Reserved */ +#define SYSBSLIND_L (0x0010u) /* SYS - TCK/RST indication detected */ +#define SYSJTAGPIN_L (0x0020u) /* SYS - Dedicated JTAG pins enabled */ +//#define RESERVED (0x0040u) /* SYS - Reserved */ +//#define RESERVED (0x0080u) /* SYS - Reserved */ +//#define RESERVED (0x0100u) /* SYS - Reserved */ +//#define RESERVED (0x0200u) /* SYS - Reserved */ +//#define RESERVED (0x0400u) /* SYS - Reserved */ +//#define RESERVED (0x0800u) /* SYS - Reserved */ +//#define RESERVED (0x1000u) /* SYS - Reserved */ +//#define RESERVED (0x2000u) /* SYS - Reserved */ +//#define RESERVED (0x4000u) /* SYS - Reserved */ +//#define RESERVED (0x8000u) /* SYS - Reserved */ + +/* SYSBSLC Control Bits */ +#define SYSBSLSIZE0 (0x0001u) /* SYS - BSL Protection Size 0 */ +#define SYSBSLSIZE1 (0x0002u) /* SYS - BSL Protection Size 1 */ +#define SYSBSLR (0x0004u) /* SYS - RAM assigned to BSL */ +//#define RESERVED (0x0008u) /* SYS - Reserved */ +//#define RESERVED (0x0010u) /* SYS - Reserved */ +//#define RESERVED (0x0020u) /* SYS - Reserved */ +//#define RESERVED (0x0040u) /* SYS - Reserved */ +//#define RESERVED (0x0080u) /* SYS - Reserved */ +//#define RESERVED (0x0100u) /* SYS - Reserved */ +//#define RESERVED (0x0200u) /* SYS - Reserved */ +//#define RESERVED (0x0400u) /* SYS - Reserved */ +//#define RESERVED (0x0800u) /* SYS - Reserved */ +//#define RESERVED (0x1000u) /* SYS - Reserved */ +//#define RESERVED (0x2000u) /* SYS - Reserved */ +#define SYSBSLOFF (0x4000u) /* SYS - BSL Memory disabled */ +#define SYSBSLPE (0x8000u) /* SYS - BSL Memory protection enabled */ + +/* SYSBSLC Control Bits */ +#define SYSBSLSIZE0_L (0x0001u) /* SYS - BSL Protection Size 0 */ +#define SYSBSLSIZE1_L (0x0002u) /* SYS - BSL Protection Size 1 */ +#define SYSBSLR_L (0x0004u) /* SYS - RAM assigned to BSL */ +//#define RESERVED (0x0008u) /* SYS - Reserved */ +//#define RESERVED (0x0010u) /* SYS - Reserved */ +//#define RESERVED (0x0020u) /* SYS - Reserved */ +//#define RESERVED (0x0040u) /* SYS - Reserved */ +//#define RESERVED (0x0080u) /* SYS - Reserved */ +//#define RESERVED (0x0100u) /* SYS - Reserved */ +//#define RESERVED (0x0200u) /* SYS - Reserved */ +//#define RESERVED (0x0400u) /* SYS - Reserved */ +//#define RESERVED (0x0800u) /* SYS - Reserved */ +//#define RESERVED (0x1000u) /* SYS - Reserved */ +//#define RESERVED (0x2000u) /* SYS - Reserved */ + +/* SYSBSLC Control Bits */ +//#define RESERVED (0x0008u) /* SYS - Reserved */ +//#define RESERVED (0x0010u) /* SYS - Reserved */ +//#define RESERVED (0x0020u) /* SYS - Reserved */ +//#define RESERVED (0x0040u) /* SYS - Reserved */ +//#define RESERVED (0x0080u) /* SYS - Reserved */ +//#define RESERVED (0x0100u) /* SYS - Reserved */ +//#define RESERVED (0x0200u) /* SYS - Reserved */ +//#define RESERVED (0x0400u) /* SYS - Reserved */ +//#define RESERVED (0x0800u) /* SYS - Reserved */ +//#define RESERVED (0x1000u) /* SYS - Reserved */ +//#define RESERVED (0x2000u) /* SYS - Reserved */ +#define SYSBSLOFF_H (0x0040u) /* SYS - BSL Memory disabled */ +#define SYSBSLPE_H (0x0080u) /* SYS - BSL Memory protection enabled */ + +/* SYSJMBC Control Bits */ +#define JMBIN0FG (0x0001u) /* SYS - Incoming JTAG Mailbox 0 Flag */ +#define JMBIN1FG (0x0002u) /* SYS - Incoming JTAG Mailbox 1 Flag */ +#define JMBOUT0FG (0x0004u) /* SYS - Outgoing JTAG Mailbox 0 Flag */ +#define JMBOUT1FG (0x0008u) /* SYS - Outgoing JTAG Mailbox 1 Flag */ +#define JMBMODE (0x0010u) /* SYS - JMB 16/32 Bit Mode */ +//#define RESERVED (0x0020u) /* SYS - Reserved */ +#define JMBCLR0OFF (0x0040u) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */ +#define JMBCLR1OFF (0x0080u) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */ +//#define RESERVED (0x0100u) /* SYS - Reserved */ +//#define RESERVED (0x0200u) /* SYS - Reserved */ +//#define RESERVED (0x0400u) /* SYS - Reserved */ +//#define RESERVED (0x0800u) /* SYS - Reserved */ +//#define RESERVED (0x1000u) /* SYS - Reserved */ +//#define RESERVED (0x2000u) /* SYS - Reserved */ +//#define RESERVED (0x4000u) /* SYS - Reserved */ +//#define RESERVED (0x8000u) /* SYS - Reserved */ + +/* SYSJMBC Control Bits */ +#define JMBIN0FG_L (0x0001u) /* SYS - Incoming JTAG Mailbox 0 Flag */ +#define JMBIN1FG_L (0x0002u) /* SYS - Incoming JTAG Mailbox 1 Flag */ +#define JMBOUT0FG_L (0x0004u) /* SYS - Outgoing JTAG Mailbox 0 Flag */ +#define JMBOUT1FG_L (0x0008u) /* SYS - Outgoing JTAG Mailbox 1 Flag */ +#define JMBMODE_L (0x0010u) /* SYS - JMB 16/32 Bit Mode */ +//#define RESERVED (0x0020u) /* SYS - Reserved */ +#define JMBCLR0OFF_L (0x0040u) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */ +#define JMBCLR1OFF_L (0x0080u) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */ +//#define RESERVED (0x0100u) /* SYS - Reserved */ +//#define RESERVED (0x0200u) /* SYS - Reserved */ +//#define RESERVED (0x0400u) /* SYS - Reserved */ +//#define RESERVED (0x0800u) /* SYS - Reserved */ +//#define RESERVED (0x1000u) /* SYS - Reserved */ +//#define RESERVED (0x2000u) /* SYS - Reserved */ +//#define RESERVED (0x4000u) /* SYS - Reserved */ +//#define RESERVED (0x8000u) /* SYS - Reserved */ + + +#endif +/************************************************************ +* Timerx_A7 +************************************************************/ +#ifdef __MSP430_HAS_TxA7__ /* Definition to show that Module is available */ + +#define OFS_TAxCTL (0x0000u) /* Timerx_A7 Control */ +#define OFS_TAxCCTL0 (0x0002u) /* Timerx_A7 Capture/Compare Control 0 */ +#define OFS_TAxCCTL1 (0x0004u) /* Timerx_A7 Capture/Compare Control 1 */ +#define OFS_TAxCCTL2 (0x0006u) /* Timerx_A7 Capture/Compare Control 2 */ +#define OFS_TAxCCTL3 (0x0008u) /* Timerx_A7 Capture/Compare Control 3 */ +#define OFS_TAxCCTL4 (0x000Au) /* Timerx_A7 Capture/Compare Control 4 */ +#define OFS_TAxCCTL5 (0x000Cu) /* Timerx_A7 Capture/Compare Control 5 */ +#define OFS_TAxCCTL6 (0x000Eu) /* Timerx_A7 Capture/Compare Control 6 */ +#define OFS_TAxR (0x0010u) /* Timerx_A7 */ +#define OFS_TAxCCR0 (0x0012u) /* Timerx_A7 Capture/Compare 0 */ +#define OFS_TAxCCR1 (0x0014u) /* Timerx_A7 Capture/Compare 1 */ +#define OFS_TAxCCR2 (0x0016u) /* Timerx_A7 Capture/Compare 2 */ +#define OFS_TAxCCR3 (0x0018u) /* Timerx_A7 Capture/Compare 3 */ +#define OFS_TAxCCR4 (0x001Au) /* Timerx_A7 Capture/Compare 4 */ +#define OFS_TAxCCR5 (0x001Cu) /* Timerx_A7 Capture/Compare 5 */ +#define OFS_TAxCCR6 (0x001Eu) /* Timerx_A7 Capture/Compare 6 */ +#define OFS_TAxIV (0x002Eu) /* Timerx_A7 Interrupt Vector Word */ +#define OFS_TAxEX0 (0x0020u) /* Timerx_A7 Expansion Register 0 */ + +/* Bits are already defined within the Timer0_Ax */ + +/* TAxIV Definitions */ +#define TAxIV_NONE (0x0000u) /* No Interrupt pending */ +#define TAxIV_TACCR1 (0x0002u) /* TAxCCR1_CCIFG */ +#define TAxIV_TACCR2 (0x0004u) /* TAxCCR2_CCIFG */ +#define TAxIV_TACCR3 (0x0006u) /* TAxCCR3_CCIFG */ +#define TAxIV_TACCR4 (0x0008u) /* TAxCCR4_CCIFG */ +#define TAxIV_TACCR5 (0x000Au) /* TAxCCR5_CCIFG */ +#define TAxIV_TACCR6 (0x000Cu) /* TAxCCR6_CCIFG */ +#define TAxIV_TAIFG (0x000Eu) /* TAxIFG */ + +/* Legacy Defines */ +#define TAxIV_TAxCCR1 (0x0002u) /* TAxCCR1_CCIFG */ +#define TAxIV_TAxCCR2 (0x0004u) /* TAxCCR2_CCIFG */ +#define TAxIV_TAxCCR3 (0x0006u) /* TAxCCR3_CCIFG */ +#define TAxIV_TAxCCR4 (0x0008u) /* TAxCCR4_CCIFG */ +#define TAxIV_TAxCCR5 (0x000Au) /* TAxCCR5_CCIFG */ +#define TAxIV_TAxCCR6 (0x000Cu) /* TAxCCR6_CCIFG */ +#define TAxIV_TAxIFG (0x000Eu) /* TAxIFG */ + +/* TAxCTL Control Bits */ +#define TASSEL1 (0x0200u) /* Timer A clock source select 1 */ +#define TASSEL0 (0x0100u) /* Timer A clock source select 0 */ +#define ID1 (0x0080u) /* Timer A clock input divider 1 */ +#define ID0 (0x0040u) /* Timer A clock input divider 0 */ +#define MC1 (0x0020u) /* Timer A mode control 1 */ +#define MC0 (0x0010u) /* Timer A mode control 0 */ +#define TACLR (0x0004u) /* Timer A counter clear */ +#define TAIE (0x0002u) /* Timer A counter interrupt enable */ +#define TAIFG (0x0001u) /* Timer A counter interrupt flag */ + +#define MC_0 (0*0x10u) /* Timer A mode control: 0 - Stop */ +#define MC_1 (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */ +#define MC_2 (2*0x10u) /* Timer A mode control: 2 - Continuous up */ +#define MC_3 (3*0x10u) /* Timer A mode control: 3 - Up/Down */ +#define ID_0 (0*0x40u) /* Timer A input divider: 0 - /1 */ +#define ID_1 (1*0x40u) /* Timer A input divider: 1 - /2 */ +#define ID_2 (2*0x40u) /* Timer A input divider: 2 - /4 */ +#define ID_3 (3*0x40u) /* Timer A input divider: 3 - /8 */ +#define TASSEL_0 (0*0x100u) /* Timer A clock source select: 0 - TACLK */ +#define TASSEL_1 (1*0x100u) /* Timer A clock source select: 1 - ACLK */ +#define TASSEL_2 (2*0x100u) /* Timer A clock source select: 2 - SMCLK */ +#define TASSEL_3 (3*0x100u) /* Timer A clock source select: 3 - INCLK */ +#define MC__STOP (0*0x10u) /* Timer A mode control: 0 - Stop */ +#define MC__UP (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */ +#define MC__CONTINUOUS (2*0x10u) /* Timer A mode control: 2 - Continuous up */ +#define MC__CONTINOUS (2*0x10u) /* Legacy define */ +#define MC__UPDOWN (3*0x10u) /* Timer A mode control: 3 - Up/Down */ +#define ID__1 (0*0x40u) /* Timer A input divider: 0 - /1 */ +#define ID__2 (1*0x40u) /* Timer A input divider: 1 - /2 */ +#define ID__4 (2*0x40u) /* Timer A input divider: 2 - /4 */ +#define ID__8 (3*0x40u) /* Timer A input divider: 3 - /8 */ +#define TASSEL__TACLK (0*0x100u) /* Timer A clock source select: 0 - TACLK */ +#define TASSEL__ACLK (1*0x100u) /* Timer A clock source select: 1 - ACLK */ +#define TASSEL__SMCLK (2*0x100u) /* Timer A clock source select: 2 - SMCLK */ +#define TASSEL__INCLK (3*0x100u) /* Timer A clock source select: 3 - INCLK */ + +/* TAxCCTLx Control Bits */ +#define CM1 (0x8000u) /* Capture mode 1 */ +#define CM0 (0x4000u) /* Capture mode 0 */ +#define CCIS1 (0x2000u) /* Capture input select 1 */ +#define CCIS0 (0x1000u) /* Capture input select 0 */ +#define SCS (0x0800u) /* Capture sychronize */ +#define SCCI (0x0400u) /* Latched capture signal (read) */ +#define CAP (0x0100u) /* Capture mode: 1 /Compare mode : 0 */ +#define OUTMOD2 (0x0080u) /* Output mode 2 */ +#define OUTMOD1 (0x0040u) /* Output mode 1 */ +#define OUTMOD0 (0x0020u) /* Output mode 0 */ +#define CCIE (0x0010u) /* Capture/compare interrupt enable */ +#define CCI (0x0008u) /* Capture input signal (read) */ +#define OUT (0x0004u) /* PWM Output signal if output mode 0 */ +#define COV (0x0002u) /* Capture/compare overflow flag */ +#define CCIFG (0x0001u) /* Capture/compare interrupt flag */ + +#define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */ +#define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */ +#define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */ +#define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */ +#define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */ +#define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */ +#define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */ +#define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */ +#define CCIS_0 (0*0x1000u) /* Capture input select: 0 - CCIxA */ +#define CCIS_1 (1*0x1000u) /* Capture input select: 1 - CCIxB */ +#define CCIS_2 (2*0x1000u) /* Capture input select: 2 - GND */ +#define CCIS_3 (3*0x1000u) /* Capture input select: 3 - Vcc */ +#define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */ +#define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */ +#define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */ +#define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */ + +/* TAxEX0 Control Bits */ +#define TAIDEX0 (0x0001u) /* Timer A Input divider expansion Bit: 0 */ +#define TAIDEX1 (0x0002u) /* Timer A Input divider expansion Bit: 1 */ +#define TAIDEX2 (0x0004u) /* Timer A Input divider expansion Bit: 2 */ + +#define TAIDEX_0 (0*0x0001u) /* Timer A Input divider expansion : /1 */ +#define TAIDEX_1 (1*0x0001u) /* Timer A Input divider expansion : /2 */ +#define TAIDEX_2 (2*0x0001u) /* Timer A Input divider expansion : /3 */ +#define TAIDEX_3 (3*0x0001u) /* Timer A Input divider expansion : /4 */ +#define TAIDEX_4 (4*0x0001u) /* Timer A Input divider expansion : /5 */ +#define TAIDEX_5 (5*0x0001u) /* Timer A Input divider expansion : /6 */ +#define TAIDEX_6 (6*0x0001u) /* Timer A Input divider expansion : /7 */ +#define TAIDEX_7 (7*0x0001u) /* Timer A Input divider expansion : /8 */ + +#endif +/************************************************************ +* Timerx_B7 +************************************************************/ +#ifdef __MSP430_HAS_TxB7__ /* Definition to show that Module is available */ + +#define OFS_TBxCTL (0x0000u) /* Timerx_B7 Control */ +#define OFS_TBxCCTL0 (0x0002u) /* Timerx_B7 Capture/Compare Control 0 */ +#define OFS_TBxCCTL1 (0x0004u) /* Timerx_B7 Capture/Compare Control 1 */ +#define OFS_TBxCCTL2 (0x0006u) /* Timerx_B7 Capture/Compare Control 2 */ +#define OFS_TBxCCTL3 (0x0008u) /* Timerx_B7 Capture/Compare Control 3 */ +#define OFS_TBxCCTL4 (0x000Au) /* Timerx_B7 Capture/Compare Control 4 */ +#define OFS_TBxCCTL5 (0x000Cu) /* Timerx_B7 Capture/Compare Control 5 */ +#define OFS_TBxCCTL6 (0x000Eu) /* Timerx_B7 Capture/Compare Control 6 */ +#define OFS_TBxR (0x0010u) /* Timerx_B7 */ +#define OFS_TBxCCR0 (0x0012u) /* Timerx_B7 Capture/Compare 0 */ +#define OFS_TBxCCR1 (0x0014u) /* Timerx_B7 Capture/Compare 1 */ +#define OFS_TBxCCR2 (0x0016u) /* Timerx_B7 Capture/Compare 2 */ +#define OFS_TBxCCR3 (0x0018u) /* Timerx_B7 Capture/Compare 3 */ +#define OFS_TBxCCR4 (0x001Au) /* Timerx_B7 Capture/Compare 4 */ +#define OFS_TBxCCR5 (0x001Cu) /* Timerx_B7 Capture/Compare 5 */ +#define OFS_TBxCCR6 (0x001Eu) /* Timerx_B7 Capture/Compare 6 */ +#define OFS_TBxIV (0x002Eu) /* Timerx_B7 Interrupt Vector Word */ +#define OFS_TBxEX0 (0x0020u) /* Timerx_B7 Expansion Register 0 */ + +/* Bits are already defined within the Timer0_Ax */ + +/* TBxIV Definitions */ +#define TBxIV_NONE (0x0000u) /* No Interrupt pending */ +#define TBxIV_TBCCR1 (0x0002u) /* TBxCCR1_CCIFG */ +#define TBxIV_TBCCR2 (0x0004u) /* TBxCCR2_CCIFG */ +#define TBxIV_TBCCR3 (0x0006u) /* TBxCCR3_CCIFG */ +#define TBxIV_TBCCR4 (0x0008u) /* TBxCCR4_CCIFG */ +#define TBxIV_TBCCR5 (0x000Au) /* TBxCCR5_CCIFG */ +#define TBxIV_TBCCR6 (0x000Cu) /* TBxCCR6_CCIFG */ +#define TBxIV_TBIFG (0x000Eu) /* TBxIFG */ + +/* Legacy Defines */ +#define TBxIV_TBxCCR1 (0x0002u) /* TBxCCR1_CCIFG */ +#define TBxIV_TBxCCR2 (0x0004u) /* TBxCCR2_CCIFG */ +#define TBxIV_TBxCCR3 (0x0006u) /* TBxCCR3_CCIFG */ +#define TBxIV_TBxCCR4 (0x0008u) /* TBxCCR4_CCIFG */ +#define TBxIV_TBxCCR5 (0x000Au) /* TBxCCR5_CCIFG */ +#define TBxIV_TBxCCR6 (0x000Cu) /* TBxCCR6_CCIFG */ +#define TBxIV_TBxIFG (0x000Eu) /* TBxIFG */ + +/* TBxCTL Control Bits */ +#define TBCLGRP1 (0x4000u) /* Timer_B7 Compare latch load group 1 */ +#define TBCLGRP0 (0x2000u) /* Timer_B7 Compare latch load group 0 */ +#define CNTL1 (0x1000u) /* Counter lenght 1 */ +#define CNTL0 (0x0800u) /* Counter lenght 0 */ +#define TBSSEL1 (0x0200u) /* Clock source 1 */ +#define TBSSEL0 (0x0100u) /* Clock source 0 */ +#define TBCLR (0x0004u) /* Timer_B7 counter clear */ +#define TBIE (0x0002u) /* Timer_B7 interrupt enable */ +#define TBIFG (0x0001u) /* Timer_B7 interrupt flag */ + +#define SHR1 (0x4000u) /* Timer_B7 Compare latch load group 1 */ +#define SHR0 (0x2000u) /* Timer_B7 Compare latch load group 0 */ + +#define TBSSEL_0 (0*0x0100u) /* Clock Source: TBCLK */ +#define TBSSEL_1 (1*0x0100u) /* Clock Source: ACLK */ +#define TBSSEL_2 (2*0x0100u) /* Clock Source: SMCLK */ +#define TBSSEL_3 (3*0x0100u) /* Clock Source: INCLK */ +#define CNTL_0 (0*0x0800u) /* Counter lenght: 16 bit */ +#define CNTL_1 (1*0x0800u) /* Counter lenght: 12 bit */ +#define CNTL_2 (2*0x0800u) /* Counter lenght: 10 bit */ +#define CNTL_3 (3*0x0800u) /* Counter lenght: 8 bit */ +#define SHR_0 (0*0x2000u) /* Timer_B7 Group: 0 - individually */ +#define SHR_1 (1*0x2000u) /* Timer_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */ +#define SHR_2 (2*0x2000u) /* Timer_B7 Group: 2 - 2 groups (1-3, 4-6)*/ +#define SHR_3 (3*0x2000u) /* Timer_B7 Group: 3 - 1 group (all) */ +#define TBCLGRP_0 (0*0x2000u) /* Timer_B7 Group: 0 - individually */ +#define TBCLGRP_1 (1*0x2000u) /* Timer_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */ +#define TBCLGRP_2 (2*0x2000u) /* Timer_B7 Group: 2 - 2 groups (1-3, 4-6)*/ +#define TBCLGRP_3 (3*0x2000u) /* Timer_B7 Group: 3 - 1 group (all) */ +#define TBSSEL__TBCLK (0*0x100u) /* Timer0_B7 clock source select: 0 - TBCLK */ +#define TBSSEL__TACLK (0*0x100u) /* Timer0_B7 clock source select: 0 - TBCLK (legacy) */ +#define TBSSEL__ACLK (1*0x100u) /* Timer_B7 clock source select: 1 - ACLK */ +#define TBSSEL__SMCLK (2*0x100u) /* Timer_B7 clock source select: 2 - SMCLK */ +#define TBSSEL__INCLK (3*0x100u) /* Timer_B7 clock source select: 3 - INCLK */ +#define CNTL__16 (0*0x0800u) /* Counter lenght: 16 bit */ +#define CNTL__12 (1*0x0800u) /* Counter lenght: 12 bit */ +#define CNTL__10 (2*0x0800u) /* Counter lenght: 10 bit */ +#define CNTL__8 (3*0x0800u) /* Counter lenght: 8 bit */ + +/* Additional Timer B Control Register bits are defined in Timer A */ +/* TBxCCTLx Control Bits */ +#define CLLD1 (0x0400u) /* Compare latch load source 1 */ +#define CLLD0 (0x0200u) /* Compare latch load source 0 */ + +#define SLSHR1 (0x0400u) /* Compare latch load source 1 */ +#define SLSHR0 (0x0200u) /* Compare latch load source 0 */ + +#define SLSHR_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */ +#define SLSHR_1 (1*0x0200u) /* Compare latch load sourec : 1 - TBR counts to 0 */ +#define SLSHR_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */ +#define SLSHR_3 (3*0x0200u) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */ + +#define CLLD_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */ +#define CLLD_1 (1*0x0200u) /* Compare latch load sourec : 1 - TBR counts to 0 */ +#define CLLD_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */ +#define CLLD_3 (3*0x0200u) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */ + +/* TBxEX0 Control Bits */ +#define TBIDEX0 (0x0001u) /* Timer_B7 Input divider expansion Bit: 0 */ +#define TBIDEX1 (0x0002u) /* Timer_B7 Input divider expansion Bit: 1 */ +#define TBIDEX2 (0x0004u) /* Timer_B7 Input divider expansion Bit: 2 */ + +#define TBIDEX_0 (0*0x0001u) /* Timer_B7 Input divider expansion : /1 */ +#define TBIDEX_1 (1*0x0001u) /* Timer_B7 Input divider expansion : /2 */ +#define TBIDEX_2 (2*0x0001u) /* Timer_B7 Input divider expansion : /3 */ +#define TBIDEX_3 (3*0x0001u) /* Timer_B7 Input divider expansion : /4 */ +#define TBIDEX_4 (4*0x0001u) /* Timer_B7 Input divider expansion : /5 */ +#define TBIDEX_5 (5*0x0001u) /* Timer_B7 Input divider expansion : /6 */ +#define TBIDEX_6 (6*0x0001u) /* Timer_B7 Input divider expansion : /7 */ +#define TBIDEX_7 (7*0x0001u) /* Timer_B7 Input divider expansion : /8 */ +#define TBIDEX__1 (0*0x0001u) /* Timer_B7 Input divider expansion : /1 */ +#define TBIDEX__2 (1*0x0001u) /* Timer_B7 Input divider expansion : /2 */ +#define TBIDEX__3 (2*0x0001u) /* Timer_B7 Input divider expansion : /3 */ +#define TBIDEX__4 (3*0x0001u) /* Timer_B7 Input divider expansion : /4 */ +#define TBIDEX__5 (4*0x0001u) /* Timer_B7 Input divider expansion : /5 */ +#define TBIDEX__6 (5*0x0001u) /* Timer_B7 Input divider expansion : /6 */ +#define TBIDEX__7 (6*0x0001u) /* Timer_B7 Input divider expansion : /7 */ +#define TBIDEX__8 (7*0x0001u) /* Timer_B7 Input divider expansion : /8 */ + + +#define ID1 (0x0080u) /* Timer B clock input divider 1 */ +#define ID0 (0x0040u) /* Timer B clock input divider 0 */ +#define MC1 (0x0020u) /* Timer B mode control 1 */ +#define MC0 (0x0010u) /* Timer B mode control 0 */ +#define MC__STOP (0*0x10u) /* Timer B mode control: 0 - Stop */ +#define MC__UP (1*0x10u) /* Timer B mode control: 1 - Up to CCR0 */ +#define MC__CONTINUOUS (2*0x10u) /* Timer B mode control: 2 - Continuous up */ +#define MC__CONTINOUS (2*0x10u) /* Legacy define */ +#define MC__UPDOWN (3*0x10u) /* Timer B mode control: 3 - Up/Down */ +#define CM1 (0x8000u) /* Capture mode 1 */ +#define CM0 (0x4000u) /* Capture mode 0 */ +#define MC_0 (0*0x10u) /* Timer B mode control: 0 - Stop */ +#define MC_1 (1*0x10u) /* Timer B mode control: 1 - Up to CCR0 */ +#define MC_2 (2*0x10u) /* Timer B mode control: 2 - Continuous up */ +#define MC_3 (3*0x10u) /* Timer B mode control: 3 - Up/Down */ +#define CAP (0x0100u) /* Capture mode: 1 /Compare mode : 0 */ +#define CCIE (0x0010u) /* Capture/compare interrupt enable */ +#define CCIFG (0x0001u) /* Capture/compare interrupt flag */ +#define CCIS_0 (0*0x1000u) +#define CCIS_1 (1*0x1000u) +#define CCIS_2 (2*0x1000u) +#define CCIS_3 (3*0x1000u) +#define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */ +#define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */ +#define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */ +#define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */ +#define OUT (0x0004u) /* PWM Output signal if output mode 0 */ +#define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */ +#define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */ +#define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */ +#define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */ +#define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */ +#define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */ +#define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */ +#define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */ +#define SCCI (0x0400u) /* Latched capture signal (read) */ +#define SCS (0x0800u) /* Capture sychronize */ +#define CCI (0x0008u) /* Capture input signal (read) */ +#define ID__1 (0*0x40u) /* Timer B input divider: 0 - /1 */ +#define ID__2 (1*0x40u) /* Timer B input divider: 1 - /2 */ +#define ID__4 (2*0x40u) /* Timer B input divider: 2 - /4 */ +#define ID__8 (3*0x40u) /* Timer B input divider: 3 - /8 */ +#define ID_0 (0*0x40u) /* Timer B input divider: 0 - /1 */ +#define ID_1 (1*0x40u) /* Timer B input divider: 1 - /2 */ +#define ID_2 (2*0x40u) /* Timer B input divider: 2 - /4 */ +#define ID_3 (3*0x40u) /* Timer B input divider: 3 - /8 */ + +#endif +/************************************************************ +* Timerx_D7 +************************************************************/ +#ifdef __MSP430_HAS_TxD7__ /* Definition to show that Module is available */ + +#define OFS_TDxCTL0 (0x0000u) /* Timerx_D7 Control 0 */ +#define OFS_TDxCTL1 (0x0002u) /* Timerx_D7 Control 1 */ +#define OFS_TDxCTL2 (0x0004u) /* Timerx_D7 Control 2 */ +#define OFS_TDxR (0x0006u) /* Timerx_D7 Counter */ +#define OFS_TDxCCTL0 (0x0008u) /* Timerx_D7 Capture/Compare Control 0 */ +#define OFS_TDxCCR0 (0x000Au) /* Timerx_D7 Capture/Compare 0 */ +#define OFS_TDxCL0 (0x000Cu) /* Timerx_D7 Capture/Compare Latch 0 */ +#define OFS_TDxCCTL1 (0x000Eu) /* Timerx_D7 Capture/Compare Control 1 */ +#define OFS_TDxCCR1 (0x0010u) /* Timerx_D7 Capture/Compare 1 */ +#define OFS_TDxCL1 (0x0012u) /* Timerx_D7 Capture/Compare Latch 1 */ +#define OFS_TDxCCTL2 (0x0014u) /* Timerx_D7 Capture/Compare Control 2 */ +#define OFS_TDxCCR2 (0x0016u) /* Timerx_D7 Capture/Compare 2 */ +#define OFS_TDxCL2 (0x0018u) /* Timerx_D7 Capture/Compare Latch 2 */ +#define OFS_TDxCCTL3 (0x001Au) /* Timerx_D7 Capture/Compare Control 3 */ +#define OFS_TDxCCR3 (0x001Cu) /* Timerx_D7 Capture/Compare 3 */ +#define OFS_TDxCL3 (0x001Eu) /* Timerx_D7 Capture/Compare Latch 3 */ +#define OFS_TDxCCTL4 (0x0020u) /* Timerx_D7 Capture/Compare Control 4 */ +#define OFS_TDxCCR4 (0x0022u) /* Timerx_D7 Capture/Compare 4 */ +#define OFS_TDxCL4 (0x0024u) /* Timerx_D7 Capture/Compare Latch 4 */ +#define OFS_TDxCCTL5 (0x0026u) /* Timerx_D7 Capture/Compare Control 5 */ +#define OFS_TDxCCR5 (0x0028u) /* Timerx_D7 Capture/Compare 5 */ +#define OFS_TDxCL5 (0x002Au) /* Timerx_D7 Capture/Compare Latch 5 */ +#define OFS_TDxCCTL6 (0x002Cu) /* Timerx_D7 Capture/Compare Control 6 */ +#define OFS_TDxCCR6 (0x002Eu) /* Timerx_D7 Capture/Compare 6 */ +#define OFS_TDxCL6 (0x0030u) /* Timerx_D7 Capture/Compare Latch 6 */ +#define OFS_TDxHCTL0 (0x0038u) /* Timerx_D7 High-resolution Control Register 0 */ +#define OFS_TDxHCTL1 (0x003Au) /* Timerx_D7 High-resolution Control Register 1 */ +#define OFS_TDxHINT (0x003Cu) /* Timerx_D7 High-resolution Interrupt Register */ +#define OFS_TDxIV (0x003Eu) /* Timerx_D7 Interrupt Vector Word */ + +/* Bits are already defined within the Timer0_Dx */ + +/* TDxIV Definitions */ +#define TDxIV_NONE (0x0000u) /* No Interrupt pending */ +#define TDxIV_TDCCR1 (0x0002u) /* TDxCCR1_CCIFG */ +#define TDxIV_TDCCR2 (0x0004u) /* TDxCCR2_CCIFG */ +#define TDxIV_TDCCR3 (0x0006u) /* TDxCCR3_CCIFG */ +#define TDxIV_TDCCR4 (0x0008u) /* TDxCCR4_CCIFG */ +#define TDxIV_TDCCR5 (0x000Au) /* TDxCCR5_CCIFG */ +#define TDxIV_TDCCR6 (0x000Cu) /* TDxCCR6_CCIFG */ +#define TDxIV_RES_14 (0x000Eu) /* Reserverd */ +#define TDxIV_TDIFG (0x0010u) /* TDxIFG */ +#define TDxIV_TDHFLIFG (0x0012u) /* TDHFLIFG Clock fail low */ +#define TDxIV_TDHFHIFG (0x0014u) /* TDHFLIFG Clock fail high */ +#define TDxIV_TDHLKIFG (0x0016u) /* TDHLKIE Clock lock*/ +#define TDxIV_TDHUNLKIFG (0x0018u) /* TDHUNLKIE Clock unlock */ + +/* Legacy Defines */ +#define TDxIV_TDxCCR1 (0x0002u) /* TDxCCR1_CCIFG */ +#define TDxIV_TDxCCR2 (0x0004u) /* TDxCCR2_CCIFG */ +#define TDxIV_TDxCCR3 (0x0006u) /* TDxCCR3_CCIFG */ +#define TDxIV_TDxCCR4 (0x0008u) /* TDxCCR4_CCIFG */ +#define TDxIV_TDxCCR5 (0x000Au) /* TDxCCR5_CCIFG */ +#define TDxIV_TDxCCR6 (0x000Cu) /* TDxCCR6_CCIFG */ +#define TDxIV_TDxIFG (0x0010u) /* TDxIFG */ + +/* TDxCTL0 Control Bits */ +#define TDCLGRP1 (0x4000u) /* Timer_D7 Compare latch load group 1 */ +#define TDCLGRP0 (0x2000u) /* Timer_D7 Compare latch load group 0 */ +#define CNTL1 (0x1000u) /* Counter lenght 1 */ +#define CNTL0 (0x0800u) /* Counter lenght 0 */ +#define TDSSEL1 (0x0200u) /* Clock source 1 */ +#define TDSSEL0 (0x0100u) /* Clock source 0 */ +#define TDCLR (0x0004u) /* Timer_D7 counter clear */ +#define TDIE (0x0002u) /* Timer_D7 interrupt enable */ +#define TDIFG (0x0001u) /* Timer_D7 interrupt flag */ + +#define SHR1 (0x4000u) /* Timer_D7 Compare latch load group 1 */ +#define SHR0 (0x2000u) /* Timer_D7 Compare latch load group 0 */ + +#define TDSSEL_0 (0*0x0100u) /* Clock Source: TDCLK */ +#define TDSSEL_1 (1*0x0100u) /* Clock Source: ACLK */ +#define TDSSEL_2 (2*0x0100u) /* Clock Source: SMCLK */ +#define TDSSEL_3 (3*0x0100u) /* Clock Source: INCLK */ +#define CNTL_0 (0*0x0800u) /* Counter lenght: 16 bit */ +#define CNTL_1 (1*0x0800u) /* Counter lenght: 12 bit */ +#define CNTL_2 (2*0x0800u) /* Counter lenght: 10 bit */ +#define CNTL_3 (3*0x0800u) /* Counter lenght: 8 bit */ +#define SHR_0 (0*0x2000u) /* Timer_D7 Group: 0 - individually */ +#define SHR_1 (1*0x2000u) /* Timer_D7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */ +#define SHR_2 (2*0x2000u) /* Timer_D7 Group: 2 - 2 groups (1-3, 4-6)*/ +#define SHR_3 (3*0x2000u) /* Timer_D7 Group: 3 - 1 group (all) */ +#define TDCLGRP_0 (0*0x2000u) /* Timer_D7 Group: 0 - individually */ +#define TDCLGRP_1 (1*0x2000u) /* Timer_D7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */ +#define TDCLGRP_2 (2*0x2000u) /* Timer_D7 Group: 2 - 2 groups (1-3, 4-6)*/ +#define TDCLGRP_3 (3*0x2000u) /* Timer_D7 Group: 3 - 1 group (all) */ +#define TDSSEL__TACLK (0*0x0100u) /* Timer_D7 clock source select: 0 - TACLK */ +#define TDSSEL__ACLK (1*0x0100u) /* Timer_D7 clock source select: 1 - ACLK */ +#define TDSSEL__SMCLK (2*0x0100u) /* Timer_D7 clock source select: 2 - SMCLK */ +#define TDSSEL__INCLK (3*0x0100u) /* Timer_D7 clock source select: 3 - INCLK */ +#define CNTL__16 (0*0x0800u) /* Counter lenght: 16 bit */ +#define CNTL__12 (1*0x0800u) /* Counter lenght: 12 bit */ +#define CNTL__10 (2*0x0800u) /* Counter lenght: 10 bit */ +#define CNTL__8 (3*0x0800u) /* Counter lenght: 8 bit */ + +/* Additional Timer B Control Register bits are defined in Timer A */ + +/* TDxCTL1 Control Bits */ +#define TDCLKM0 (0x0001u) /* Timer_D7 Clocking Mode Bit: 0 */ +#define TDCLKM1 (0x0002u) /* Timer_D7 Clocking Mode Bit: 1 */ +#define TD2CMB (0x0010u) /* Timer_D7 TD0CCR Combination in TD2 */ +#define TD4CMB (0x0020u) /* Timer_D7 TD0CCR Combination in TD4 */ +#define TD6CMB (0x0040u) /* Timer_D7 TD0CCR Combination in TD6 */ +#define TDIDEX0 (0x0100u) /* Timer_D7 Input divider expansion Bit: 0 */ +#define TDIDEX1 (0x0200u) /* Timer_D7 Input divider expansion Bit: 1 */ +#define TDIDEX2 (0x0400u) /* Timer_D7 Input divider expansion Bit: 2 */ + +#define TDCLKM_0 (0x0000u) /* Timer_D7 Clocking Mode: External */ +#define TDCLKM_1 (0x0001u) /* Timer_D7 Clocking Mode: High-Res. local clock */ +#define TDCLKM_2 (0x0002u) /* Timer_D7 Clocking Mode: Aux Clock */ +#define TDCLKM__EXT (0x0000u) /* Timer_D7 Clocking Mode: External */ +#define TDCLKM__HIGHRES (0x0001u) /* Timer_D7 Clocking Mode: High-Res. local clock */ +#define TDCLKM__AUX (0x0002u) /* Timer_D7 Clocking Mode: Aux Clock */ + +#define TDIDEX_0 (0*0x0100u) /* Timer0_D3 Input divider expansion : /1 */ +#define TDIDEX_1 (1*0x0100u) /* Timer0_D3 Input divider expansion : /2 */ +#define TDIDEX_2 (2*0x0100u) /* Timer0_D3 Input divider expansion : /3 */ +#define TDIDEX_3 (3*0x0100u) /* Timer0_D3 Input divider expansion : /4 */ +#define TDIDEX_4 (4*0x0100u) /* Timer0_D3 Input divider expansion : /5 */ +#define TDIDEX_5 (5*0x0100u) /* Timer0_D3 Input divider expansion : /6 */ +#define TDIDEX_6 (6*0x0100u) /* Timer0_D3 Input divider expansion : /7 */ +#define TDIDEX_7 (7*0x0100u) /* Timer0_D3 Input divider expansion : /8 */ +#define TDIDEX__1 (0*0x0100u) /* Timer0_D3 Input divider expansion : /1 */ +#define TDIDEX__2 (1*0x0100u) /* Timer0_D3 Input divider expansion : /2 */ +#define TDIDEX__3 (2*0x0100u) /* Timer0_D3 Input divider expansion : /3 */ +#define TDIDEX__4 (3*0x0100u) /* Timer0_D3 Input divider expansion : /4 */ +#define TDIDEX__5 (4*0x0100u) /* Timer0_D3 Input divider expansion : /5 */ +#define TDIDEX__6 (5*0x0100u) /* Timer0_D3 Input divider expansion : /6 */ +#define TDIDEX__7 (6*0x0100u) /* Timer0_D3 Input divider expansion : /7 */ +#define TDIDEX__8 (7*0x0100u) /* Timer0_D3 Input divider expansion : /8 */ + +/* TDxCTL2 Control Bits */ +#define TDCAPM0 (0x0001u) /* Timer_D7 Capture Mode of Channel 0 */ +#define TDCAPM1 (0x0002u) /* Timer_D7 Capture Mode of Channel 1 */ +#define TDCAPM2 (0x0004u) /* Timer_D7 Capture Mode of Channel 2 */ +#define TDCAPM3 (0x0008u) /* Timer_D7 Capture Mode of Channel 3 */ +#define TDCAPM4 (0x0010u) /* Timer_D7 Capture Mode of Channel 4 */ +#define TDCAPM5 (0x0020u) /* Timer_D7 Capture Mode of Channel 5 */ +#define TDCAPM6 (0x0040u) /* Timer_D7 Capture Mode of Channel 6 */ + +/* TDxCCTLx Control Bits */ +#define CLLD1 (0x0400u) /* Compare latch load source 1 */ +#define CLLD0 (0x0200u) /* Compare latch load source 0 */ + +#define SLSHR1 (0x0400u) /* Compare latch load source 1 */ +#define SLSHR0 (0x0200u) /* Compare latch load source 0 */ + +#define SLSHR_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */ +#define SLSHR_1 (1*0x0200u) /* Compare latch load sourec : 1 - TDR counts to 0 */ +#define SLSHR_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */ +#define SLSHR_3 (3*0x0200u) /* Compare latch load sourec : 3 - TDR counts to TDCTL0 */ + +#define CLLD_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */ +#define CLLD_1 (1*0x0200u) /* Compare latch load sourec : 1 - TDR counts to 0 */ +#define CLLD_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */ +#define CLLD_3 (3*0x0200u) /* Compare latch load sourec : 3 - TDR counts to TDCTL0 */ + +/* TDxHCTL0 Control Bits */ +#define TDHEN (0x0001u) /* Timer_D7 High-Resolution Enable */ +#define TDHREGEN (0x0002u) /* Timer_D7 High-Resolution Regulatied Mode */ +#define TDHEAEN (0x0004u) /* Timer_D7 High-Resolution clock error accum. enable */ +#define TDHRON (0x0008u) /* Timer_D7 High-Resolution Generator forced on*/ +#define TDHM0 (0x0010u) /* Timer_D7 High-Resoltuion Clock Mult. Bit: 0 */ +#define TDHM1 (0x0020u) /* Timer_D7 High-Resoltuion Clock Mult. Bit: 1 */ +#define TDHD0 (0x0040u) /* Timer_D7 High-Resolution clock divider Bit: 0 */ +#define TDHD1 (0x0080u) /* Timer_D7 High-Resolution clock divider Bit: 1 */ +#define TDHFW (0x0100u) /* Timer_D7 High-resolution generator fast wakeup enable */ + +#define TDHCALEN TDHREGEN /* Timer_D7 Lagacy Definition */ + +#define TDHM_0 (0x0000u) /* Timer_D7 High-Resoltuion Clock Mult.: 8x TimerD clock */ +#define TDHM_1 (0x0010u) /* Timer_D7 High-Resoltuion Clock Mult.: 16x TimerD clock */ +#define TDHM__8 (0x0000u) /* Timer_D7 High-Resoltuion Clock Mult.: 8x TimerD clock */ +#define TDHM__16 (0x0010u) /* Timer_D7 High-Resoltuion Clock Mult.: 16x TimerD clock */ +#define TDHD_0 (0x0000u) /* Timer_D7 High-Resolution clock divider: /1 */ +#define TDHD_1 (0x0040u) /* Timer_D7 High-Resolution clock divider: /2 */ +#define TDHD_2 (0x0080u) /* Timer_D7 High-Resolution clock divider: /4 */ +#define TDHD_3 (0x00C0u) /* Timer_D7 High-Resolution clock divider: /8 */ +#define TDHD__1 (0x0000u) /* Timer_D7 High-Resolution clock divider: /1 */ +#define TDHD__2 (0x0040u) /* Timer_D7 High-Resolution clock divider: /2 */ +#define TDHD__4 (0x0080u) /* Timer_D7 High-Resolution clock divider: /4 */ +#define TDHD__8 (0x00C0u) /* Timer_D7 High-Resolution clock divider: /8 */ + +/* TDxHCTL1 Control Bits */ +#define TDHCLKTRIM0 (0x0002u) /* Timer_D7 High-Resolution Clock Trim Bit: 0 */ +#define TDHCLKTRIM1 (0x0004u) /* Timer_D7 High-Resolution Clock Trim Bit: 1 */ +#define TDHCLKTRIM2 (0x0008u) /* Timer_D7 High-Resolution Clock Trim Bit: 2 */ +#define TDHCLKTRIM3 (0x0010u) /* Timer_D7 High-Resolution Clock Trim Bit: 3 */ +#define TDHCLKTRIM4 (0x0020u) /* Timer_D7 High-Resolution Clock Trim Bit: 4 */ +#define TDHCLKTRIM5 (0x0040u) /* Timer_D7 High-Resolution Clock Trim Bit: 5 */ +#define TDHCLKTRIM6 (0x0080u) /* Timer_D7 High-Resolution Clock Trim Bit: 6 */ +#define TDHCLKSR0 (0x0100u) /* Timer_D7 High-Resolution Clock Sub-Range Bit: 0 */ +#define TDHCLKSR1 (0x0200u) /* Timer_D7 High-Resolution Clock Sub-Range Bit: 1 */ +#define TDHCLKSR2 (0x0400u) /* Timer_D7 High-Resolution Clock Sub-Range Bit: 2 */ +#define TDHCLKSR3 (0x0800u) /* Timer_D7 High-Resolution Clock Sub-Range Bit: 3 */ +#define TDHCLKSR4 (0x1000u) /* Timer_D7 High-Resolution Clock Sub-Range Bit: 4 */ +#define TDHCLKR0 (0x2000u) /* Timer_D7 High-Resolution Clock Range Bit: 0 */ +#define TDHCLKR1 (0x4000u) /* Timer_D7 High-Resolution Clock Range Bit: 1 */ +#define TDHCLKCR (0x8000u) /* Timer_D7 High-Resolution Coarse Clock Range */ + +/* TDxHINT Control Bits */ +#define TDHFLIFG (0x0001u) /* Timer_D7 High-Res. fail low Interrupt Flag */ +#define TDHFHIFG (0x0002u) /* Timer_D7 High-Res. fail high Interrupt Flag */ +#define TDHLKIFG (0x0004u) /* Timer_D7 High-Res. frequency lock Interrupt Flag */ +#define TDHUNLKIFG (0x0008u) /* Timer_D7 High-Res. frequency unlock Interrupt Flag */ +#define TDHFLIE (0x0100u) /* Timer_D7 High-Res. fail low Interrupt Enable */ +#define TDHFHIE (0x0200u) /* Timer_D7 High-Res. fail high Interrupt Enable */ +#define TDHLKIE (0x0400u) /* Timer_D7 High-Res. frequency lock Interrupt Enable */ +#define TDHUNLKIE (0x0800u) /* Timer_D7 High-Res. frequency unlock Interrupt Enable */ + +#define ID1 (0x0080u) /* Timer D clock input divider 1 */ +#define ID0 (0x0040u) /* Timer D clock input divider 0 */ +#define MC1 (0x0020u) /* Timer D mode control 1 */ +#define MC0 (0x0010u) /* Timer D mode control 0 */ +#define MC__STOP (0*0x10u) /* Timer D mode control: 0 - Stop */ +#define MC__UP (1*0x10u) /* Timer D mode control: 1 - Up to CCR0 */ +#define MC__CONTINUOUS (2*0x10u) /* Timer D mode control: 2 - Continuous up */ +#define MC__CONTINOUS (2*0x10u) /* Legacy define */ +#define MC__UPDOWN (3*0x10u) /* Timer D mode control: 3 - Up/Down */ +#define CM1 (0x8000u) /* Capture mode 1 */ +#define CM0 (0x4000u) /* Capture mode 0 */ +#define MC_0 (0*0x10u) /* Timer D mode control: 0 - Stop */ +#define MC_1 (1*0x10u) /* Timer D mode control: 1 - Up to CCR0 */ +#define MC_2 (2*0x10u) /* Timer D mode control: 2 - Continuous up */ +#define MC_3 (3*0x10u) /* Timer D mode control: 3 - Up/Down */ +#define CAP (0x0100u) /* Capture mode: 1 /Compare mode : 0 */ +#define CCIE (0x0010u) /* Capture/compare interrupt enable */ +#define CCIFG (0x0001u) /* Capture/compare interrupt flag */ +#define CCIS_0 (0*0x1000u) +#define CCIS_1 (1*0x1000u) +#define CCIS_2 (2*0x1000u) +#define CCIS_3 (3*0x1000u) +#define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */ +#define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */ +#define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */ +#define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */ +#define OUT (0x0004u) /* PWM Output signal if output mode 0 */ +#define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */ +#define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */ +#define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */ +#define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */ +#define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */ +#define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */ +#define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */ +#define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */ +#define SCCI (0x0400u) /* Latched capture signal (read) */ +#define SCS (0x0800u) /* Capture sychronize */ +#define CCI (0x0008u) /* Capture input signal (read) */ +#define ID__1 (0*0x40u) /* Timer D input divider: 0 - /1 */ +#define ID__2 (1*0x40u) /* Timer D input divider: 1 - /2 */ +#define ID__4 (2*0x40u) /* Timer D input divider: 2 - /4 */ +#define ID__8 (3*0x40u) /* Timer D input divider: 3 - /8 */ +#define ID_0 (0*0x40u) /* Timer D input divider: 0 - /1 */ +#define ID_1 (1*0x40u) /* Timer D input divider: 1 - /2 */ +#define ID_2 (2*0x40u) /* Timer D input divider: 2 - /4 */ +#define ID_3 (3*0x40u) /* Timer D input divider: 3 - /8 */ + +#endif +/************************************************************ +* Timer Event Control 0 +************************************************************/ +#ifdef __MSP430_HAS_TEV0__ /* Definition to show that Module is available */ + +#define OFS_TEC0XCTL0 (0x0000u) /* Timer Event Control 0 External Control 0 */ +#define OFS_TEC0XCTL0_L OFS_TEC0XCTL0 +#define OFS_TEC0XCTL0_H OFS_TEC0XCTL0+1 +#define OFS_TEC0XCTL1 (0x0002u) /* Timer Event Control 0 External Control 1 */ +#define OFS_TEC0XCTL1_L OFS_TEC0XCTL1 +#define OFS_TEC0XCTL1_H OFS_TEC0XCTL1+1 +#define OFS_TEC0XCTL2 (0x0004u) /* Timer Event Control 0 External Control 2 */ +#define OFS_TEC0XCTL2_L OFS_TEC0XCTL2 +#define OFS_TEC0XCTL2_H OFS_TEC0XCTL2+1 +#define OFS_TEC0STA (0x0006u) /* Timer Event Control 0 Status */ +#define OFS_TEC0STA_L OFS_TEC0STA +#define OFS_TEC0STA_H OFS_TEC0STA+1 +#define OFS_TEC0XINT (0x0008u) /* Timer Event Control 0 External Interrupt */ +#define OFS_TEC0XINT_L OFS_TEC0XINT +#define OFS_TEC0XINT_H OFS_TEC0XINT+1 +#define OFS_TEC0IV (0x000Au) /* Timer Event Control 0 Interrupt Vector */ +#define OFS_TEC0IV_L OFS_TEC0IV +#define OFS_TEC0IV_H OFS_TEC0IV+1 + +/* TECxXCTL0 Control Bits */ +#define TECXFLTHLD0 (0x0001u) /* TEV Ext. fault signal hold for CE0 */ +#define TECXFLTHLD1 (0x0002u) /* TEV Ext. fault signal hold for CE1 */ +#define TECXFLTHLD2 (0x0004u) /* TEV Ext. fault signal hold for CE2 */ +#define TECXFLTHLD3 (0x0008u) /* TEV Ext. fault signal hold for CE3 */ +#define TECXFLTHLD4 (0x0010u) /* TEV Ext. fault signal hold for CE4 */ +#define TECXFLTHLD5 (0x0020u) /* TEV Ext. fault signal hold for CE5 */ +#define TECXFLTHLD6 (0x0040u) /* TEV Ext. fault signal hold for CE6 */ +#define TECXFLTEN0 (0x0100u) /* TEV Ext. fault signal enable for CE0 */ +#define TECXFLTEN1 (0x0200u) /* TEV Ext. fault signal enable for CE1 */ +#define TECXFLTEN2 (0x0400u) /* TEV Ext. fault signal enable for CE2 */ +#define TECXFLTEN3 (0x0800u) /* TEV Ext. fault signal enable for CE3 */ +#define TECXFLTEN4 (0x1000u) /* TEV Ext. fault signal enable for CE4 */ +#define TECXFLTEN5 (0x2000u) /* TEV Ext. fault signal enable for CE5 */ +#define TECXFLTEN6 (0x4000u) /* TEV Ext. fault signal enable for CE6 */ + +/* TECxXCTL0 Control Bits */ +#define TECXFLTHLD0_L (0x0001u) /* TEV Ext. fault signal hold for CE0 */ +#define TECXFLTHLD1_L (0x0002u) /* TEV Ext. fault signal hold for CE1 */ +#define TECXFLTHLD2_L (0x0004u) /* TEV Ext. fault signal hold for CE2 */ +#define TECXFLTHLD3_L (0x0008u) /* TEV Ext. fault signal hold for CE3 */ +#define TECXFLTHLD4_L (0x0010u) /* TEV Ext. fault signal hold for CE4 */ +#define TECXFLTHLD5_L (0x0020u) /* TEV Ext. fault signal hold for CE5 */ +#define TECXFLTHLD6_L (0x0040u) /* TEV Ext. fault signal hold for CE6 */ + +/* TECxXCTL0 Control Bits */ +#define TECXFLTEN0_H (0x0001u) /* TEV Ext. fault signal enable for CE0 */ +#define TECXFLTEN1_H (0x0002u) /* TEV Ext. fault signal enable for CE1 */ +#define TECXFLTEN2_H (0x0004u) /* TEV Ext. fault signal enable for CE2 */ +#define TECXFLTEN3_H (0x0008u) /* TEV Ext. fault signal enable for CE3 */ +#define TECXFLTEN4_H (0x0010u) /* TEV Ext. fault signal enable for CE4 */ +#define TECXFLTEN5_H (0x0020u) /* TEV Ext. fault signal enable for CE5 */ +#define TECXFLTEN6_H (0x0040u) /* TEV Ext. fault signal enable for CE6 */ + +/* TECxXCTL1 Control Bits */ +#define TECXFLTPOL0 (0x0001u) /* TEV Polarity Bit of ext. fault 0 */ +#define TECXFLTPOL1 (0x0002u) /* TEV Polarity Bit of ext. fault 1 */ +#define TECXFLTPOL2 (0x0004u) /* TEV Polarity Bit of ext. fault 2 */ +#define TECXFLTPOL3 (0x0008u) /* TEV Polarity Bit of ext. fault 3 */ +#define TECXFLTPOL4 (0x0010u) /* TEV Polarity Bit of ext. fault 4 */ +#define TECXFLTPOL5 (0x0020u) /* TEV Polarity Bit of ext. fault 5 */ +#define TECXFLTPOL6 (0x0040u) /* TEV Polarity Bit of ext. fault 6 */ +#define TECXFLTLVS0 (0x0100u) /* TEV Signal Type of Ext. fault 0 */ +#define TECXFLTLVS1 (0x0200u) /* TEV Signal Type of Ext. fault 1 */ +#define TECXFLTLVS2 (0x0400u) /* TEV Signal Type of Ext. fault 2 */ +#define TECXFLTLVS3 (0x0800u) /* TEV Signal Type of Ext. fault 3 */ +#define TECXFLTLVS4 (0x1000u) /* TEV Signal Type of Ext. fault 4 */ +#define TECXFLTLVS5 (0x2000u) /* TEV Signal Type of Ext. fault 5 */ +#define TECXFLTLVS6 (0x4000u) /* TEV Signal Type of Ext. fault 6 */ + +/* TECxXCTL1 Control Bits */ +#define TECXFLTPOL0_L (0x0001u) /* TEV Polarity Bit of ext. fault 0 */ +#define TECXFLTPOL1_L (0x0002u) /* TEV Polarity Bit of ext. fault 1 */ +#define TECXFLTPOL2_L (0x0004u) /* TEV Polarity Bit of ext. fault 2 */ +#define TECXFLTPOL3_L (0x0008u) /* TEV Polarity Bit of ext. fault 3 */ +#define TECXFLTPOL4_L (0x0010u) /* TEV Polarity Bit of ext. fault 4 */ +#define TECXFLTPOL5_L (0x0020u) /* TEV Polarity Bit of ext. fault 5 */ +#define TECXFLTPOL6_L (0x0040u) /* TEV Polarity Bit of ext. fault 6 */ + +/* TECxXCTL1 Control Bits */ +#define TECXFLTLVS0_H (0x0001u) /* TEV Signal Type of Ext. fault 0 */ +#define TECXFLTLVS1_H (0x0002u) /* TEV Signal Type of Ext. fault 1 */ +#define TECXFLTLVS2_H (0x0004u) /* TEV Signal Type of Ext. fault 2 */ +#define TECXFLTLVS3_H (0x0008u) /* TEV Signal Type of Ext. fault 3 */ +#define TECXFLTLVS4_H (0x0010u) /* TEV Signal Type of Ext. fault 4 */ +#define TECXFLTLVS5_H (0x0020u) /* TEV Signal Type of Ext. fault 5 */ +#define TECXFLTLVS6_H (0x0040u) /* TEV Signal Type of Ext. fault 6 */ + +/* TECxXCTL2 Control Bits */ +#define TECCLKSEL0 (0x0001u) /* TEV Aux. Clock Select Bit: 0 */ +#define TECCLKSEL1 (0x0002u) /* TEV Aux. Clock Select Bit: 1 */ +#define TECAXCLREN (0x0004u) /* TEV Auxilary clear signal control */ +#define TECEXCLREN (0x0008u) /* TEV Ext. clear signal control */ +#define TECEXCLRHLD (0x0010u) /* TEV External clear signal hold bit */ +#define TECEXCLRPOL (0x0020u) /* TEV Polarity Bit of ext. clear */ +#define TECEXCLRLVS (0x0040u) /* TEV Signal Type of Ext. clear */ + +/* TECxXCTL2 Control Bits */ +#define TECCLKSEL0_L (0x0001u) /* TEV Aux. Clock Select Bit: 0 */ +#define TECCLKSEL1_L (0x0002u) /* TEV Aux. Clock Select Bit: 1 */ +#define TECAXCLREN_L (0x0004u) /* TEV Auxilary clear signal control */ +#define TECEXCLREN_L (0x0008u) /* TEV Ext. clear signal control */ +#define TECEXCLRHLD_L (0x0010u) /* TEV External clear signal hold bit */ +#define TECEXCLRPOL_L (0x0020u) /* TEV Polarity Bit of ext. clear */ +#define TECEXCLRLVS_L (0x0040u) /* TEV Signal Type of Ext. clear */ + +#define TECCLKSEL_0 (0x0000u) /* TEV Aux. Clock Select: CLK0 */ +#define TECCLKSEL_1 (0x0001u) /* TEV Aux. Clock Select: CLK1 */ +#define TECCLKSEL_2 (0x0002u) /* TEV Aux. Clock Select: CLK2 */ +#define TECCLKSEL_3 (0x0003u) /* TEV Aux. Clock Select: CLK3 */ + +/* TECxSTA Control Bits */ +#define TECXFLT0STA (0x0001u) /* TEV External fault status flag for CE0 */ +#define TECXFLT1STA (0x0002u) /* TEV External fault status flag for CE1 */ +#define TECXFLT2STA (0x0004u) /* TEV External fault status flag for CE2 */ +#define TECXFLT3STA (0x0008u) /* TEV External fault status flag for CE3 */ +#define TECXFLT4STA (0x0010u) /* TEV External fault status flag for CE4 */ +#define TECXFLT5STA (0x0020u) /* TEV External fault status flag for CE5 */ +#define TECXFLT6STA (0x0040u) /* TEV External fault status flag for CE6 */ +#define TECXCLRSTA (0x0100u) /* TEC External clear status flag */ + +/* TECxSTA Control Bits */ +#define TECXFLT0STA_L (0x0001u) /* TEV External fault status flag for CE0 */ +#define TECXFLT1STA_L (0x0002u) /* TEV External fault status flag for CE1 */ +#define TECXFLT2STA_L (0x0004u) /* TEV External fault status flag for CE2 */ +#define TECXFLT3STA_L (0x0008u) /* TEV External fault status flag for CE3 */ +#define TECXFLT4STA_L (0x0010u) /* TEV External fault status flag for CE4 */ +#define TECXFLT5STA_L (0x0020u) /* TEV External fault status flag for CE5 */ +#define TECXFLT6STA_L (0x0040u) /* TEV External fault status flag for CE6 */ + +/* TECxSTA Control Bits */ +#define TECXCLRSTA_H (0x0001u) /* TEC External clear status flag */ + +/* TECxXINT Control Bits */ +#define TECAXCLRIFG (0x0001u) /* TEC Aux. Clear Interrupt Flag */ +#define TECEXCLRIFG (0x0002u) /* TEC External Clear Interrupt Flag */ +#define TECXFLTIFG (0x0004u) /* TEC External Fault Interrupt Flag */ +#define TECAXCLRIE (0x0100u) /* TEC Aux. Clear Interrupt Enable */ +#define TECEXCLRIE (0x0200u) /* TEC External Clear Interrupt Enable */ +#define TECXFLTIE (0x0400u) /* TEC External Fault Interrupt Enable */ + +/* TECxXINT Control Bits */ +#define TECAXCLRIFG_L (0x0001u) /* TEC Aux. Clear Interrupt Flag */ +#define TECEXCLRIFG_L (0x0002u) /* TEC External Clear Interrupt Flag */ +#define TECXFLTIFG_L (0x0004u) /* TEC External Fault Interrupt Flag */ + +/* TECxXINT Control Bits */ +#define TECAXCLRIE_H (0x0001u) /* TEC Aux. Clear Interrupt Enable */ +#define TECEXCLRIE_H (0x0002u) /* TEC External Clear Interrupt Enable */ +#define TECXFLTIE_H (0x0004u) /* TEC External Fault Interrupt Enable */ + +/* TEC0IV Definitions */ +#define TEC0IV_NONE (0x0000u) /* No Interrupt pending */ +#define TEC0IV_TECXFLTIFG (0x0002u) /* TEC0XFLTIFG */ +#define TEC0IV_TECEXCLRIFG (0x0004u) /* TEC0EXCLRIFG */ +#define TEC0IV_TECAXCLRIFG (0x0006u) /* TEC0AXCLRIFG */ + +#endif +/************************************************************ +* Timer Event Control x +************************************************************/ +#ifdef __MSP430_HAS_TEVx__ /* Definition to show that Module is available */ + +#define OFS_TECxXCTL0 (0x0000u) /* Timer Event Control x External Control 0 */ +#define OFS_TECxXCTL0_L OFS_TECxXCTL0 +#define OFS_TECxXCTL0_H OFS_TECxXCTL0+1 +#define OFS_TECxXCTL1 (0x0002u) /* Timer Event Control x External Control 1 */ +#define OFS_TECxXCTL1_L OFS_TECxXCTL1 +#define OFS_TECxXCTL1_H OFS_TECxXCTL1+1 +#define OFS_TECxXCTL2 (0x0004u) /* Timer Event Control x External Control 2 */ +#define OFS_TECxXCTL2_L OFS_TECxXCTL2 +#define OFS_TECxXCTL2_H OFS_TECxXCTL2+1 +#define OFS_TECxSTA (0x0006u) /* Timer Event Control x Status */ +#define OFS_TECxSTA_L OFS_TECxSTA +#define OFS_TECxSTA_H OFS_TECxSTA+1 +#define OFS_TECxXINT (0x0008u) /* Timer Event Control x External Interrupt */ +#define OFS_TECxXINT_L OFS_TECxXINT +#define OFS_TECxXINT_H OFS_TECxXINT+1 +#define OFS_TECxIV (0x000Au) /* Timer Event Control x Interrupt Vector */ +#define OFS_TECxIV_L OFS_TECxIV +#define OFS_TECxIV_H OFS_TECxIV+1 + +/* TECIV Definitions */ +#define TECxIV_NONE (0x0000u) /* No Interrupt pending */ +#define TECxIV_TECXFLTIFG (0x0002u) /* TECxXFLTIFG */ +#define TECxIV_TECEXCLRIFG (0x0004u) /* TECxEXCLRIFG */ +#define TECxIV_TECAXCLRIFG (0x0006u) /* TECxAXCLRIFG */ + + +#endif + +/************************************************************ +* UNIFIED CLOCK SYSTEM +************************************************************/ +#ifdef __MSP430_HAS_UCS__ /* Definition to show that Module is available */ + +#define OFS_UCSCTL0 (0x0000u) /* UCS Control Register 0 */ +#define OFS_UCSCTL0_L OFS_UCSCTL0 +#define OFS_UCSCTL0_H OFS_UCSCTL0+1 +#define OFS_UCSCTL1 (0x0002u) /* UCS Control Register 1 */ +#define OFS_UCSCTL1_L OFS_UCSCTL1 +#define OFS_UCSCTL1_H OFS_UCSCTL1+1 +#define OFS_UCSCTL2 (0x0004u) /* UCS Control Register 2 */ +#define OFS_UCSCTL2_L OFS_UCSCTL2 +#define OFS_UCSCTL2_H OFS_UCSCTL2+1 +#define OFS_UCSCTL3 (0x0006u) /* UCS Control Register 3 */ +#define OFS_UCSCTL3_L OFS_UCSCTL3 +#define OFS_UCSCTL3_H OFS_UCSCTL3+1 +#define OFS_UCSCTL4 (0x0008u) /* UCS Control Register 4 */ +#define OFS_UCSCTL4_L OFS_UCSCTL4 +#define OFS_UCSCTL4_H OFS_UCSCTL4+1 +#define OFS_UCSCTL5 (0x000Au) /* UCS Control Register 5 */ +#define OFS_UCSCTL5_L OFS_UCSCTL5 +#define OFS_UCSCTL5_H OFS_UCSCTL5+1 +#define OFS_UCSCTL6 (0x000Cu) /* UCS Control Register 6 */ +#define OFS_UCSCTL6_L OFS_UCSCTL6 +#define OFS_UCSCTL6_H OFS_UCSCTL6+1 +#define OFS_UCSCTL7 (0x000Eu) /* UCS Control Register 7 */ +#define OFS_UCSCTL7_L OFS_UCSCTL7 +#define OFS_UCSCTL7_H OFS_UCSCTL7+1 +#define OFS_UCSCTL8 (0x0010u) /* UCS Control Register 8 */ +#define OFS_UCSCTL8_L OFS_UCSCTL8 +#define OFS_UCSCTL8_H OFS_UCSCTL8+1 + +/* UCSCTL0 Control Bits */ +//#define RESERVED (0x0001u) /* RESERVED */ +//#define RESERVED (0x0002u) /* RESERVED */ +//#define RESERVED (0x0004u) /* RESERVED */ +#define MOD0 (0x0008u) /* Modulation Bit Counter Bit : 0 */ +#define MOD1 (0x0010u) /* Modulation Bit Counter Bit : 1 */ +#define MOD2 (0x0020u) /* Modulation Bit Counter Bit : 2 */ +#define MOD3 (0x0040u) /* Modulation Bit Counter Bit : 3 */ +#define MOD4 (0x0080u) /* Modulation Bit Counter Bit : 4 */ +#define DCO0 (0x0100u) /* DCO TAP Bit : 0 */ +#define DCO1 (0x0200u) /* DCO TAP Bit : 1 */ +#define DCO2 (0x0400u) /* DCO TAP Bit : 2 */ +#define DCO3 (0x0800u) /* DCO TAP Bit : 3 */ +#define DCO4 (0x1000u) /* DCO TAP Bit : 4 */ +//#define RESERVED (0x2000u) /* RESERVED */ +//#define RESERVED (0x4000u) /* RESERVED */ +//#define RESERVED (0x8000u) /* RESERVED */ + +/* UCSCTL0 Control Bits */ +//#define RESERVED (0x0001u) /* RESERVED */ +//#define RESERVED (0x0002u) /* RESERVED */ +//#define RESERVED (0x0004u) /* RESERVED */ +#define MOD0_L (0x0008u) /* Modulation Bit Counter Bit : 0 */ +#define MOD1_L (0x0010u) /* Modulation Bit Counter Bit : 1 */ +#define MOD2_L (0x0020u) /* Modulation Bit Counter Bit : 2 */ +#define MOD3_L (0x0040u) /* Modulation Bit Counter Bit : 3 */ +#define MOD4_L (0x0080u) /* Modulation Bit Counter Bit : 4 */ +//#define RESERVED (0x2000u) /* RESERVED */ +//#define RESERVED (0x4000u) /* RESERVED */ +//#define RESERVED (0x8000u) /* RESERVED */ + +/* UCSCTL0 Control Bits */ +//#define RESERVED (0x0001u) /* RESERVED */ +//#define RESERVED (0x0002u) /* RESERVED */ +//#define RESERVED (0x0004u) /* RESERVED */ +#define DCO0_H (0x0001u) /* DCO TAP Bit : 0 */ +#define DCO1_H (0x0002u) /* DCO TAP Bit : 1 */ +#define DCO2_H (0x0004u) /* DCO TAP Bit : 2 */ +#define DCO3_H (0x0008u) /* DCO TAP Bit : 3 */ +#define DCO4_H (0x0010u) /* DCO TAP Bit : 4 */ +//#define RESERVED (0x2000u) /* RESERVED */ +//#define RESERVED (0x4000u) /* RESERVED */ +//#define RESERVED (0x8000u) /* RESERVED */ + +/* UCSCTL1 Control Bits */ +#define DISMOD (0x0001u) /* Disable Modulation */ +//#define RESERVED (0x0002u) /* RESERVED */ +//#define RESERVED (0x0004u) /* RESERVED */ +//#define RESERVED (0x0008u) /* RESERVED */ +#define DCORSEL0 (0x0010u) /* DCO Freq. Range Select Bit : 0 */ +#define DCORSEL1 (0x0020u) /* DCO Freq. Range Select Bit : 1 */ +#define DCORSEL2 (0x0040u) /* DCO Freq. Range Select Bit : 2 */ +//#define RESERVED (0x0080u) /* RESERVED */ +//#define RESERVED (0x0100u) /* RESERVED */ +//#define RESERVED (0x0200u) /* RESERVED */ +//#define RESERVED (0x0400u) /* RESERVED */ +//#define RESERVED (0x0800u) /* RESERVED */ +//#define RESERVED (0x1000u) /* RESERVED */ +//#define RESERVED (0x2000u) /* RESERVED */ +//#define RESERVED (0x4000u) /* RESERVED */ +//#define RESERVED (0x8000u) /* RESERVED */ + +/* UCSCTL1 Control Bits */ +#define DISMOD_L (0x0001u) /* Disable Modulation */ +//#define RESERVED (0x0002u) /* RESERVED */ +//#define RESERVED (0x0004u) /* RESERVED */ +//#define RESERVED (0x0008u) /* RESERVED */ +#define DCORSEL0_L (0x0010u) /* DCO Freq. Range Select Bit : 0 */ +#define DCORSEL1_L (0x0020u) /* DCO Freq. Range Select Bit : 1 */ +#define DCORSEL2_L (0x0040u) /* DCO Freq. Range Select Bit : 2 */ +//#define RESERVED (0x0080u) /* RESERVED */ +//#define RESERVED (0x0100u) /* RESERVED */ +//#define RESERVED (0x0200u) /* RESERVED */ +//#define RESERVED (0x0400u) /* RESERVED */ +//#define RESERVED (0x0800u) /* RESERVED */ +//#define RESERVED (0x1000u) /* RESERVED */ +//#define RESERVED (0x2000u) /* RESERVED */ +//#define RESERVED (0x4000u) /* RESERVED */ +//#define RESERVED (0x8000u) /* RESERVED */ + +#define DCORSEL_0 (0x0000u) /* DCO RSEL 0 */ +#define DCORSEL_1 (0x0010u) /* DCO RSEL 1 */ +#define DCORSEL_2 (0x0020u) /* DCO RSEL 2 */ +#define DCORSEL_3 (0x0030u) /* DCO RSEL 3 */ +#define DCORSEL_4 (0x0040u) /* DCO RSEL 4 */ +#define DCORSEL_5 (0x0050u) /* DCO RSEL 5 */ +#define DCORSEL_6 (0x0060u) /* DCO RSEL 6 */ +#define DCORSEL_7 (0x0070u) /* DCO RSEL 7 */ + +/* UCSCTL2 Control Bits */ +#define FLLN0 (0x0001u) /* FLL Multipier Bit : 0 */ +#define FLLN1 (0x0002u) /* FLL Multipier Bit : 1 */ +#define FLLN2 (0x0004u) /* FLL Multipier Bit : 2 */ +#define FLLN3 (0x0008u) /* FLL Multipier Bit : 3 */ +#define FLLN4 (0x0010u) /* FLL Multipier Bit : 4 */ +#define FLLN5 (0x0020u) /* FLL Multipier Bit : 5 */ +#define FLLN6 (0x0040u) /* FLL Multipier Bit : 6 */ +#define FLLN7 (0x0080u) /* FLL Multipier Bit : 7 */ +#define FLLN8 (0x0100u) /* FLL Multipier Bit : 8 */ +#define FLLN9 (0x0200u) /* FLL Multipier Bit : 9 */ +//#define RESERVED (0x0400u) /* RESERVED */ +//#define RESERVED (0x0800u) /* RESERVED */ +#define FLLD0 (0x1000u) /* Loop Divider Bit : 0 */ +#define FLLD1 (0x2000u) /* Loop Divider Bit : 1 */ +#define FLLD2 (0x4000u) /* Loop Divider Bit : 1 */ +//#define RESERVED (0x8000u) /* RESERVED */ + +/* UCSCTL2 Control Bits */ +#define FLLN0_L (0x0001u) /* FLL Multipier Bit : 0 */ +#define FLLN1_L (0x0002u) /* FLL Multipier Bit : 1 */ +#define FLLN2_L (0x0004u) /* FLL Multipier Bit : 2 */ +#define FLLN3_L (0x0008u) /* FLL Multipier Bit : 3 */ +#define FLLN4_L (0x0010u) /* FLL Multipier Bit : 4 */ +#define FLLN5_L (0x0020u) /* FLL Multipier Bit : 5 */ +#define FLLN6_L (0x0040u) /* FLL Multipier Bit : 6 */ +#define FLLN7_L (0x0080u) /* FLL Multipier Bit : 7 */ +//#define RESERVED (0x0400u) /* RESERVED */ +//#define RESERVED (0x0800u) /* RESERVED */ +//#define RESERVED (0x8000u) /* RESERVED */ + +/* UCSCTL2 Control Bits */ +#define FLLN8_H (0x0001u) /* FLL Multipier Bit : 8 */ +#define FLLN9_H (0x0002u) /* FLL Multipier Bit : 9 */ +//#define RESERVED (0x0400u) /* RESERVED */ +//#define RESERVED (0x0800u) /* RESERVED */ +#define FLLD0_H (0x0010u) /* Loop Divider Bit : 0 */ +#define FLLD1_H (0x0020u) /* Loop Divider Bit : 1 */ +#define FLLD2_H (0x0040u) /* Loop Divider Bit : 1 */ +//#define RESERVED (0x8000u) /* RESERVED */ + +#define FLLD_0 (0x0000u) /* Multiply Selected Loop Freq. 1 */ +#define FLLD_1 (0x1000u) /* Multiply Selected Loop Freq. 2 */ +#define FLLD_2 (0x2000u) /* Multiply Selected Loop Freq. 4 */ +#define FLLD_3 (0x3000u) /* Multiply Selected Loop Freq. 8 */ +#define FLLD_4 (0x4000u) /* Multiply Selected Loop Freq. 16 */ +#define FLLD_5 (0x5000u) /* Multiply Selected Loop Freq. 32 */ +#define FLLD_6 (0x6000u) /* Multiply Selected Loop Freq. 32 */ +#define FLLD_7 (0x7000u) /* Multiply Selected Loop Freq. 32 */ +#define FLLD__1 (0x0000u) /* Multiply Selected Loop Freq. By 1 */ +#define FLLD__2 (0x1000u) /* Multiply Selected Loop Freq. By 2 */ +#define FLLD__4 (0x2000u) /* Multiply Selected Loop Freq. By 4 */ +#define FLLD__8 (0x3000u) /* Multiply Selected Loop Freq. By 8 */ +#define FLLD__16 (0x4000u) /* Multiply Selected Loop Freq. By 16 */ +#define FLLD__32 (0x5000u) /* Multiply Selected Loop Freq. By 32 */ + +/* UCSCTL3 Control Bits */ +#define FLLREFDIV0 (0x0001u) /* Reference Divider Bit : 0 */ +#define FLLREFDIV1 (0x0002u) /* Reference Divider Bit : 1 */ +#define FLLREFDIV2 (0x0004u) /* Reference Divider Bit : 2 */ +//#define RESERVED (0x0008u) /* RESERVED */ +#define SELREF0 (0x0010u) /* FLL Reference Clock Select Bit : 0 */ +#define SELREF1 (0x0020u) /* FLL Reference Clock Select Bit : 1 */ +#define SELREF2 (0x0040u) /* FLL Reference Clock Select Bit : 2 */ +//#define RESERVED (0x0080u) /* RESERVED */ +//#define RESERVED (0x0100u) /* RESERVED */ +//#define RESERVED (0x0200u) /* RESERVED */ +//#define RESERVED (0x0400u) /* RESERVED */ +//#define RESERVED (0x0800u) /* RESERVED */ +//#define RESERVED (0x1000u) /* RESERVED */ +//#define RESERVED (0x2000u) /* RESERVED */ +//#define RESERVED (0x4000u) /* RESERVED */ +//#define RESERVED (0x8000u) /* RESERVED */ + +/* UCSCTL3 Control Bits */ +#define FLLREFDIV0_L (0x0001u) /* Reference Divider Bit : 0 */ +#define FLLREFDIV1_L (0x0002u) /* Reference Divider Bit : 1 */ +#define FLLREFDIV2_L (0x0004u) /* Reference Divider Bit : 2 */ +//#define RESERVED (0x0008u) /* RESERVED */ +#define SELREF0_L (0x0010u) /* FLL Reference Clock Select Bit : 0 */ +#define SELREF1_L (0x0020u) /* FLL Reference Clock Select Bit : 1 */ +#define SELREF2_L (0x0040u) /* FLL Reference Clock Select Bit : 2 */ +//#define RESERVED (0x0080u) /* RESERVED */ +//#define RESERVED (0x0100u) /* RESERVED */ +//#define RESERVED (0x0200u) /* RESERVED */ +//#define RESERVED (0x0400u) /* RESERVED */ +//#define RESERVED (0x0800u) /* RESERVED */ +//#define RESERVED (0x1000u) /* RESERVED */ +//#define RESERVED (0x2000u) /* RESERVED */ +//#define RESERVED (0x4000u) /* RESERVED */ +//#define RESERVED (0x8000u) /* RESERVED */ + +#define FLLREFDIV_0 (0x0000u) /* Reference Divider: f(LFCLK)/1 */ +#define FLLREFDIV_1 (0x0001u) /* Reference Divider: f(LFCLK)/2 */ +#define FLLREFDIV_2 (0x0002u) /* Reference Divider: f(LFCLK)/4 */ +#define FLLREFDIV_3 (0x0003u) /* Reference Divider: f(LFCLK)/8 */ +#define FLLREFDIV_4 (0x0004u) /* Reference Divider: f(LFCLK)/12 */ +#define FLLREFDIV_5 (0x0005u) /* Reference Divider: f(LFCLK)/16 */ +#define FLLREFDIV_6 (0x0006u) /* Reference Divider: f(LFCLK)/16 */ +#define FLLREFDIV_7 (0x0007u) /* Reference Divider: f(LFCLK)/16 */ +#define FLLREFDIV__1 (0x0000u) /* Reference Divider: f(LFCLK)/1 */ +#define FLLREFDIV__2 (0x0001u) /* Reference Divider: f(LFCLK)/2 */ +#define FLLREFDIV__4 (0x0002u) /* Reference Divider: f(LFCLK)/4 */ +#define FLLREFDIV__8 (0x0003u) /* Reference Divider: f(LFCLK)/8 */ +#define FLLREFDIV__12 (0x0004u) /* Reference Divider: f(LFCLK)/12 */ +#define FLLREFDIV__16 (0x0005u) /* Reference Divider: f(LFCLK)/16 */ +#define SELREF_0 (0x0000u) /* FLL Reference Clock Select 0 */ +#define SELREF_1 (0x0010u) /* FLL Reference Clock Select 1 */ +#define SELREF_2 (0x0020u) /* FLL Reference Clock Select 2 */ +#define SELREF_3 (0x0030u) /* FLL Reference Clock Select 3 */ +#define SELREF_4 (0x0040u) /* FLL Reference Clock Select 4 */ +#define SELREF_5 (0x0050u) /* FLL Reference Clock Select 5 */ +#define SELREF_6 (0x0060u) /* FLL Reference Clock Select 6 */ +#define SELREF_7 (0x0070u) /* FLL Reference Clock Select 7 */ +#define SELREF__XT1CLK (0x0000u) /* Multiply Selected Loop Freq. By XT1CLK */ +#define SELREF__REFOCLK (0x0020u) /* Multiply Selected Loop Freq. By REFOCLK */ +#define SELREF__XT2CLK (0x0050u) /* Multiply Selected Loop Freq. By XT2CLK */ + +/* UCSCTL4 Control Bits */ +#define SELM0 (0x0001u) /* MCLK Source Select Bit: 0 */ +#define SELM1 (0x0002u) /* MCLK Source Select Bit: 1 */ +#define SELM2 (0x0004u) /* MCLK Source Select Bit: 2 */ +//#define RESERVED (0x0008u) /* RESERVED */ +#define SELS0 (0x0010u) /* SMCLK Source Select Bit: 0 */ +#define SELS1 (0x0020u) /* SMCLK Source Select Bit: 1 */ +#define SELS2 (0x0040u) /* SMCLK Source Select Bit: 2 */ +//#define RESERVED (0x0080u) /* RESERVED */ +#define SELA0 (0x0100u) /* ACLK Source Select Bit: 0 */ +#define SELA1 (0x0200u) /* ACLK Source Select Bit: 1 */ +#define SELA2 (0x0400u) /* ACLK Source Select Bit: 2 */ +//#define RESERVED (0x0800u) /* RESERVED */ +//#define RESERVED (0x1000u) /* RESERVED */ +//#define RESERVED (0x2000u) /* RESERVED */ +//#define RESERVED (0x4000u) /* RESERVED */ +//#define RESERVED (0x8000u) /* RESERVED */ + +/* UCSCTL4 Control Bits */ +#define SELM0_L (0x0001u) /* MCLK Source Select Bit: 0 */ +#define SELM1_L (0x0002u) /* MCLK Source Select Bit: 1 */ +#define SELM2_L (0x0004u) /* MCLK Source Select Bit: 2 */ +//#define RESERVED (0x0008u) /* RESERVED */ +#define SELS0_L (0x0010u) /* SMCLK Source Select Bit: 0 */ +#define SELS1_L (0x0020u) /* SMCLK Source Select Bit: 1 */ +#define SELS2_L (0x0040u) /* SMCLK Source Select Bit: 2 */ +//#define RESERVED (0x0080u) /* RESERVED */ +//#define RESERVED (0x0800u) /* RESERVED */ +//#define RESERVED (0x1000u) /* RESERVED */ +//#define RESERVED (0x2000u) /* RESERVED */ +//#define RESERVED (0x4000u) /* RESERVED */ +//#define RESERVED (0x8000u) /* RESERVED */ + +/* UCSCTL4 Control Bits */ +//#define RESERVED (0x0008u) /* RESERVED */ +//#define RESERVED (0x0080u) /* RESERVED */ +#define SELA0_H (0x0001u) /* ACLK Source Select Bit: 0 */ +#define SELA1_H (0x0002u) /* ACLK Source Select Bit: 1 */ +#define SELA2_H (0x0004u) /* ACLK Source Select Bit: 2 */ +//#define RESERVED (0x0800u) /* RESERVED */ +//#define RESERVED (0x1000u) /* RESERVED */ +//#define RESERVED (0x2000u) /* RESERVED */ +//#define RESERVED (0x4000u) /* RESERVED */ +//#define RESERVED (0x8000u) /* RESERVED */ + +#define SELM_0 (0x0000u) /* MCLK Source Select 0 */ +#define SELM_1 (0x0001u) /* MCLK Source Select 1 */ +#define SELM_2 (0x0002u) /* MCLK Source Select 2 */ +#define SELM_3 (0x0003u) /* MCLK Source Select 3 */ +#define SELM_4 (0x0004u) /* MCLK Source Select 4 */ +#define SELM_5 (0x0005u) /* MCLK Source Select 5 */ +#define SELM_6 (0x0006u) /* MCLK Source Select 6 */ +#define SELM_7 (0x0007u) /* MCLK Source Select 7 */ +#define SELM__XT1CLK (0x0000u) /* MCLK Source Select XT1CLK */ +#define SELM__VLOCLK (0x0001u) /* MCLK Source Select VLOCLK */ +#define SELM__REFOCLK (0x0002u) /* MCLK Source Select REFOCLK */ +#define SELM__DCOCLK (0x0003u) /* MCLK Source Select DCOCLK */ +#define SELM__DCOCLKDIV (0x0004u) /* MCLK Source Select DCOCLKDIV */ +#define SELM__XT2CLK (0x0005u) /* MCLK Source Select XT2CLK */ + +#define SELS_0 (0x0000u) /* SMCLK Source Select 0 */ +#define SELS_1 (0x0010u) /* SMCLK Source Select 1 */ +#define SELS_2 (0x0020u) /* SMCLK Source Select 2 */ +#define SELS_3 (0x0030u) /* SMCLK Source Select 3 */ +#define SELS_4 (0x0040u) /* SMCLK Source Select 4 */ +#define SELS_5 (0x0050u) /* SMCLK Source Select 5 */ +#define SELS_6 (0x0060u) /* SMCLK Source Select 6 */ +#define SELS_7 (0x0070u) /* SMCLK Source Select 7 */ +#define SELS__XT1CLK (0x0000u) /* SMCLK Source Select XT1CLK */ +#define SELS__VLOCLK (0x0010u) /* SMCLK Source Select VLOCLK */ +#define SELS__REFOCLK (0x0020u) /* SMCLK Source Select REFOCLK */ +#define SELS__DCOCLK (0x0030u) /* SMCLK Source Select DCOCLK */ +#define SELS__DCOCLKDIV (0x0040u) /* SMCLK Source Select DCOCLKDIV */ +#define SELS__XT2CLK (0x0050u) /* SMCLK Source Select XT2CLK */ + +#define SELA_0 (0x0000u) /* ACLK Source Select 0 */ +#define SELA_1 (0x0100u) /* ACLK Source Select 1 */ +#define SELA_2 (0x0200u) /* ACLK Source Select 2 */ +#define SELA_3 (0x0300u) /* ACLK Source Select 3 */ +#define SELA_4 (0x0400u) /* ACLK Source Select 4 */ +#define SELA_5 (0x0500u) /* ACLK Source Select 5 */ +#define SELA_6 (0x0600u) /* ACLK Source Select 6 */ +#define SELA_7 (0x0700u) /* ACLK Source Select 7 */ +#define SELA__XT1CLK (0x0000u) /* ACLK Source Select XT1CLK */ +#define SELA__VLOCLK (0x0100u) /* ACLK Source Select VLOCLK */ +#define SELA__REFOCLK (0x0200u) /* ACLK Source Select REFOCLK */ +#define SELA__DCOCLK (0x0300u) /* ACLK Source Select DCOCLK */ +#define SELA__DCOCLKDIV (0x0400u) /* ACLK Source Select DCOCLKDIV */ +#define SELA__XT2CLK (0x0500u) /* ACLK Source Select XT2CLK */ + +/* UCSCTL5 Control Bits */ +#define DIVM0 (0x0001u) /* MCLK Divider Bit: 0 */ +#define DIVM1 (0x0002u) /* MCLK Divider Bit: 1 */ +#define DIVM2 (0x0004u) /* MCLK Divider Bit: 2 */ +//#define RESERVED (0x0008u) /* RESERVED */ +#define DIVS0 (0x0010u) /* SMCLK Divider Bit: 0 */ +#define DIVS1 (0x0020u) /* SMCLK Divider Bit: 1 */ +#define DIVS2 (0x0040u) /* SMCLK Divider Bit: 2 */ +//#define RESERVED (0x0080u) /* RESERVED */ +#define DIVA0 (0x0100u) /* ACLK Divider Bit: 0 */ +#define DIVA1 (0x0200u) /* ACLK Divider Bit: 1 */ +#define DIVA2 (0x0400u) /* ACLK Divider Bit: 2 */ +//#define RESERVED (0x0800u) /* RESERVED */ +#define DIVPA0 (0x1000u) /* ACLK from Pin Divider Bit: 0 */ +#define DIVPA1 (0x2000u) /* ACLK from Pin Divider Bit: 1 */ +#define DIVPA2 (0x4000u) /* ACLK from Pin Divider Bit: 2 */ +//#define RESERVED (0x8000u) /* RESERVED */ + +/* UCSCTL5 Control Bits */ +#define DIVM0_L (0x0001u) /* MCLK Divider Bit: 0 */ +#define DIVM1_L (0x0002u) /* MCLK Divider Bit: 1 */ +#define DIVM2_L (0x0004u) /* MCLK Divider Bit: 2 */ +//#define RESERVED (0x0008u) /* RESERVED */ +#define DIVS0_L (0x0010u) /* SMCLK Divider Bit: 0 */ +#define DIVS1_L (0x0020u) /* SMCLK Divider Bit: 1 */ +#define DIVS2_L (0x0040u) /* SMCLK Divider Bit: 2 */ +//#define RESERVED (0x0080u) /* RESERVED */ +//#define RESERVED (0x0800u) /* RESERVED */ +//#define RESERVED (0x8000u) /* RESERVED */ + +/* UCSCTL5 Control Bits */ +//#define RESERVED (0x0008u) /* RESERVED */ +//#define RESERVED (0x0080u) /* RESERVED */ +#define DIVA0_H (0x0001u) /* ACLK Divider Bit: 0 */ +#define DIVA1_H (0x0002u) /* ACLK Divider Bit: 1 */ +#define DIVA2_H (0x0004u) /* ACLK Divider Bit: 2 */ +//#define RESERVED (0x0800u) /* RESERVED */ +#define DIVPA0_H (0x0010u) /* ACLK from Pin Divider Bit: 0 */ +#define DIVPA1_H (0x0020u) /* ACLK from Pin Divider Bit: 1 */ +#define DIVPA2_H (0x0040u) /* ACLK from Pin Divider Bit: 2 */ +//#define RESERVED (0x8000u) /* RESERVED */ + +#define DIVM_0 (0x0000u) /* MCLK Source Divider 0 */ +#define DIVM_1 (0x0001u) /* MCLK Source Divider 1 */ +#define DIVM_2 (0x0002u) /* MCLK Source Divider 2 */ +#define DIVM_3 (0x0003u) /* MCLK Source Divider 3 */ +#define DIVM_4 (0x0004u) /* MCLK Source Divider 4 */ +#define DIVM_5 (0x0005u) /* MCLK Source Divider 5 */ +#define DIVM_6 (0x0006u) /* MCLK Source Divider 6 */ +#define DIVM_7 (0x0007u) /* MCLK Source Divider 7 */ +#define DIVM__1 (0x0000u) /* MCLK Source Divider f(MCLK)/1 */ +#define DIVM__2 (0x0001u) /* MCLK Source Divider f(MCLK)/2 */ +#define DIVM__4 (0x0002u) /* MCLK Source Divider f(MCLK)/4 */ +#define DIVM__8 (0x0003u) /* MCLK Source Divider f(MCLK)/8 */ +#define DIVM__16 (0x0004u) /* MCLK Source Divider f(MCLK)/16 */ +#define DIVM__32 (0x0005u) /* MCLK Source Divider f(MCLK)/32 */ + +#define DIVS_0 (0x0000u) /* SMCLK Source Divider 0 */ +#define DIVS_1 (0x0010u) /* SMCLK Source Divider 1 */ +#define DIVS_2 (0x0020u) /* SMCLK Source Divider 2 */ +#define DIVS_3 (0x0030u) /* SMCLK Source Divider 3 */ +#define DIVS_4 (0x0040u) /* SMCLK Source Divider 4 */ +#define DIVS_5 (0x0050u) /* SMCLK Source Divider 5 */ +#define DIVS_6 (0x0060u) /* SMCLK Source Divider 6 */ +#define DIVS_7 (0x0070u) /* SMCLK Source Divider 7 */ +#define DIVS__1 (0x0000u) /* SMCLK Source Divider f(SMCLK)/1 */ +#define DIVS__2 (0x0010u) /* SMCLK Source Divider f(SMCLK)/2 */ +#define DIVS__4 (0x0020u) /* SMCLK Source Divider f(SMCLK)/4 */ +#define DIVS__8 (0x0030u) /* SMCLK Source Divider f(SMCLK)/8 */ +#define DIVS__16 (0x0040u) /* SMCLK Source Divider f(SMCLK)/16 */ +#define DIVS__32 (0x0050u) /* SMCLK Source Divider f(SMCLK)/32 */ + +#define DIVA_0 (0x0000u) /* ACLK Source Divider 0 */ +#define DIVA_1 (0x0100u) /* ACLK Source Divider 1 */ +#define DIVA_2 (0x0200u) /* ACLK Source Divider 2 */ +#define DIVA_3 (0x0300u) /* ACLK Source Divider 3 */ +#define DIVA_4 (0x0400u) /* ACLK Source Divider 4 */ +#define DIVA_5 (0x0500u) /* ACLK Source Divider 5 */ +#define DIVA_6 (0x0600u) /* ACLK Source Divider 6 */ +#define DIVA_7 (0x0700u) /* ACLK Source Divider 7 */ +#define DIVA__1 (0x0000u) /* ACLK Source Divider f(ACLK)/1 */ +#define DIVA__2 (0x0100u) /* ACLK Source Divider f(ACLK)/2 */ +#define DIVA__4 (0x0200u) /* ACLK Source Divider f(ACLK)/4 */ +#define DIVA__8 (0x0300u) /* ACLK Source Divider f(ACLK)/8 */ +#define DIVA__16 (0x0400u) /* ACLK Source Divider f(ACLK)/16 */ +#define DIVA__32 (0x0500u) /* ACLK Source Divider f(ACLK)/32 */ + +#define DIVPA_0 (0x0000u) /* ACLK from Pin Source Divider 0 */ +#define DIVPA_1 (0x1000u) /* ACLK from Pin Source Divider 1 */ +#define DIVPA_2 (0x2000u) /* ACLK from Pin Source Divider 2 */ +#define DIVPA_3 (0x3000u) /* ACLK from Pin Source Divider 3 */ +#define DIVPA_4 (0x4000u) /* ACLK from Pin Source Divider 4 */ +#define DIVPA_5 (0x5000u) /* ACLK from Pin Source Divider 5 */ +#define DIVPA_6 (0x6000u) /* ACLK from Pin Source Divider 6 */ +#define DIVPA_7 (0x7000u) /* ACLK from Pin Source Divider 7 */ +#define DIVPA__1 (0x0000u) /* ACLK from Pin Source Divider f(ACLK)/1 */ +#define DIVPA__2 (0x1000u) /* ACLK from Pin Source Divider f(ACLK)/2 */ +#define DIVPA__4 (0x2000u) /* ACLK from Pin Source Divider f(ACLK)/4 */ +#define DIVPA__8 (0x3000u) /* ACLK from Pin Source Divider f(ACLK)/8 */ +#define DIVPA__16 (0x4000u) /* ACLK from Pin Source Divider f(ACLK)/16 */ +#define DIVPA__32 (0x5000u) /* ACLK from Pin Source Divider f(ACLK)/32 */ + +/* UCSCTL6 Control Bits */ +#define XT1OFF (0x0001u) /* High Frequency Oscillator 1 (XT1) disable */ +#define SMCLKOFF (0x0002u) /* SMCLK Off */ +#define XCAP0 (0x0004u) /* XIN/XOUT Cap Bit: 0 */ +#define XCAP1 (0x0008u) /* XIN/XOUT Cap Bit: 1 */ +#define XT1BYPASS (0x0010u) /* XT1 bypass mode : 0: internal 1:sourced from external pin */ +#define XTS (0x0020u) /* 1: Selects high-freq. oscillator */ +#define XT1DRIVE0 (0x0040u) /* XT1 Drive Level mode Bit 0 */ +#define XT1DRIVE1 (0x0080u) /* XT1 Drive Level mode Bit 1 */ +#define XT2OFF (0x0100u) /* High Frequency Oscillator 2 (XT2) disable */ +//#define RESERVED (0x0200u) /* RESERVED */ +//#define RESERVED (0x0400u) /* RESERVED */ +//#define RESERVED (0x0800u) /* RESERVED */ +#define XT2BYPASS (0x1000u) /* XT2 bypass mode : 0: internal 1:sourced from external pin */ +//#define RESERVED (0x2000u) /* RESERVED */ +#define XT2DRIVE0 (0x4000u) /* XT2 Drive Level mode Bit 0 */ +#define XT2DRIVE1 (0x8000u) /* XT2 Drive Level mode Bit 1 */ + +/* UCSCTL6 Control Bits */ +#define XT1OFF_L (0x0001u) /* High Frequency Oscillator 1 (XT1) disable */ +#define SMCLKOFF_L (0x0002u) /* SMCLK Off */ +#define XCAP0_L (0x0004u) /* XIN/XOUT Cap Bit: 0 */ +#define XCAP1_L (0x0008u) /* XIN/XOUT Cap Bit: 1 */ +#define XT1BYPASS_L (0x0010u) /* XT1 bypass mode : 0: internal 1:sourced from external pin */ +#define XTS_L (0x0020u) /* 1: Selects high-freq. oscillator */ +#define XT1DRIVE0_L (0x0040u) /* XT1 Drive Level mode Bit 0 */ +#define XT1DRIVE1_L (0x0080u) /* XT1 Drive Level mode Bit 1 */ +//#define RESERVED (0x0200u) /* RESERVED */ +//#define RESERVED (0x0400u) /* RESERVED */ +//#define RESERVED (0x0800u) /* RESERVED */ +//#define RESERVED (0x2000u) /* RESERVED */ + +/* UCSCTL6 Control Bits */ +#define XT2OFF_H (0x0001u) /* High Frequency Oscillator 2 (XT2) disable */ +//#define RESERVED (0x0200u) /* RESERVED */ +//#define RESERVED (0x0400u) /* RESERVED */ +//#define RESERVED (0x0800u) /* RESERVED */ +#define XT2BYPASS_H (0x0010u) /* XT2 bypass mode : 0: internal 1:sourced from external pin */ +//#define RESERVED (0x2000u) /* RESERVED */ +#define XT2DRIVE0_H (0x0040u) /* XT2 Drive Level mode Bit 0 */ +#define XT2DRIVE1_H (0x0080u) /* XT2 Drive Level mode Bit 1 */ + +#define XCAP_0 (0x0000u) /* XIN/XOUT Cap 0 */ +#define XCAP_1 (0x0004u) /* XIN/XOUT Cap 1 */ +#define XCAP_2 (0x0008u) /* XIN/XOUT Cap 2 */ +#define XCAP_3 (0x000Cu) /* XIN/XOUT Cap 3 */ +#define XT1DRIVE_0 (0x0000u) /* XT1 Drive Level mode: 0 */ +#define XT1DRIVE_1 (0x0040u) /* XT1 Drive Level mode: 1 */ +#define XT1DRIVE_2 (0x0080u) /* XT1 Drive Level mode: 2 */ +#define XT1DRIVE_3 (0x00C0u) /* XT1 Drive Level mode: 3 */ +#define XT2DRIVE_0 (0x0000u) /* XT2 Drive Level mode: 0 */ +#define XT2DRIVE_1 (0x4000u) /* XT2 Drive Level mode: 1 */ +#define XT2DRIVE_2 (0x8000u) /* XT2 Drive Level mode: 2 */ +#define XT2DRIVE_3 (0xC000u) /* XT2 Drive Level mode: 3 */ + +/* UCSCTL7 Control Bits */ +#define DCOFFG (0x0001u) /* DCO Fault Flag */ +#define XT1LFOFFG (0x0002u) /* XT1 Low Frequency Oscillator Fault Flag */ +#define XT1HFOFFG (0x0004u) /* XT1 High Frequency Oscillator 1 Fault Flag */ +#define XT2OFFG (0x0008u) /* High Frequency Oscillator 2 Fault Flag */ +//#define RESERVED (0x0010u) /* RESERVED */ +//#define RESERVED (0x0020u) /* RESERVED */ +//#define RESERVED (0x0040u) /* RESERVED */ +//#define RESERVED (0x0080u) /* RESERVED */ +//#define RESERVED (0x0100u) /* RESERVED */ +//#define RESERVED (0x0200u) /* RESERVED */ +//#define RESERVED (0x0400u) /* RESERVED */ +//#define RESERVED (0x0800u) /* RESERVED */ +//#define RESERVED (0x1000u) /* RESERVED */ +//#define RESERVED (0x2000u) /* RESERVED */ +//#define RESERVED (0x4000u) /* RESERVED */ +//#define RESERVED (0x8000u) /* RESERVED */ + +/* UCSCTL7 Control Bits */ +#define DCOFFG_L (0x0001u) /* DCO Fault Flag */ +#define XT1LFOFFG_L (0x0002u) /* XT1 Low Frequency Oscillator Fault Flag */ +#define XT1HFOFFG_L (0x0004u) /* XT1 High Frequency Oscillator 1 Fault Flag */ +#define XT2OFFG_L (0x0008u) /* High Frequency Oscillator 2 Fault Flag */ +//#define RESERVED (0x0010u) /* RESERVED */ +//#define RESERVED (0x0020u) /* RESERVED */ +//#define RESERVED (0x0040u) /* RESERVED */ +//#define RESERVED (0x0080u) /* RESERVED */ +//#define RESERVED (0x0100u) /* RESERVED */ +//#define RESERVED (0x0200u) /* RESERVED */ +//#define RESERVED (0x0400u) /* RESERVED */ +//#define RESERVED (0x0800u) /* RESERVED */ +//#define RESERVED (0x1000u) /* RESERVED */ +//#define RESERVED (0x2000u) /* RESERVED */ +//#define RESERVED (0x4000u) /* RESERVED */ +//#define RESERVED (0x8000u) /* RESERVED */ + +/* UCSCTL8 Control Bits */ +#define ACLKREQEN (0x0001u) /* ACLK Clock Request Enable */ +#define MCLKREQEN (0x0002u) /* MCLK Clock Request Enable */ +#define SMCLKREQEN (0x0004u) /* SMCLK Clock Request Enable */ +#define MODOSCREQEN (0x0008u) /* MODOSC Clock Request Enable */ +//#define RESERVED (0x0010u) /* RESERVED */ +//#define RESERVED (0x0020u) /* RESERVED */ +//#define RESERVED (0x0040u) /* RESERVED */ +//#define RESERVED (0x0080u) /* RESERVED */ +//#define RESERVED (0x0100u) /* RESERVED */ +//#define RESERVED (0x0200u) /* RESERVED */ +//#define RESERVED (0x0400u) /* RESERVED */ +//#define RESERVED (0x0800u) /* RESERVED */ +//#define RESERVED (0x1000u) /* RESERVED */ +//#define RESERVED (0x2000u) /* RESERVED */ +//#define RESERVED (0x4000u) /* RESERVED */ +//#define RESERVED (0x8000u) /* RESERVED */ + +/* UCSCTL8 Control Bits */ +#define ACLKREQEN_L (0x0001u) /* ACLK Clock Request Enable */ +#define MCLKREQEN_L (0x0002u) /* MCLK Clock Request Enable */ +#define SMCLKREQEN_L (0x0004u) /* SMCLK Clock Request Enable */ +#define MODOSCREQEN_L (0x0008u) /* MODOSC Clock Request Enable */ +//#define RESERVED (0x0010u) /* RESERVED */ +//#define RESERVED (0x0020u) /* RESERVED */ +//#define RESERVED (0x0040u) /* RESERVED */ +//#define RESERVED (0x0080u) /* RESERVED */ +//#define RESERVED (0x0100u) /* RESERVED */ +//#define RESERVED (0x0200u) /* RESERVED */ +//#define RESERVED (0x0400u) /* RESERVED */ +//#define RESERVED (0x0800u) /* RESERVED */ +//#define RESERVED (0x1000u) /* RESERVED */ +//#define RESERVED (0x2000u) /* RESERVED */ +//#define RESERVED (0x4000u) /* RESERVED */ +//#define RESERVED (0x8000u) /* RESERVED */ + +#endif +/************************************************************ +* UNIFIED CLOCK SYSTEM FOR Radio Devices +************************************************************/ +#ifdef __MSP430_HAS_UCS_RF__ /* Definition to show that Module is available */ + +#define OFS_UCSCTL0 (0x0000u) /* UCS Control Register 0 */ +#define OFS_UCSCTL0_L OFS_UCSCTL0 +#define OFS_UCSCTL0_H OFS_UCSCTL0+1 +#define OFS_UCSCTL1 (0x0002u) /* UCS Control Register 1 */ +#define OFS_UCSCTL1_L OFS_UCSCTL1 +#define OFS_UCSCTL1_H OFS_UCSCTL1+1 +#define OFS_UCSCTL2 (0x0004u) /* UCS Control Register 2 */ +#define OFS_UCSCTL2_L OFS_UCSCTL2 +#define OFS_UCSCTL2_H OFS_UCSCTL2+1 +#define OFS_UCSCTL3 (0x0006u) /* UCS Control Register 3 */ +#define OFS_UCSCTL3_L OFS_UCSCTL3 +#define OFS_UCSCTL3_H OFS_UCSCTL3+1 +#define OFS_UCSCTL4 (0x0008u) /* UCS Control Register 4 */ +#define OFS_UCSCTL4_L OFS_UCSCTL4 +#define OFS_UCSCTL4_H OFS_UCSCTL4+1 +#define OFS_UCSCTL5 (0x000Au) /* UCS Control Register 5 */ +#define OFS_UCSCTL5_L OFS_UCSCTL5 +#define OFS_UCSCTL5_H OFS_UCSCTL5+1 +#define OFS_UCSCTL6 (0x000Cu) /* UCS Control Register 6 */ +#define OFS_UCSCTL6_L OFS_UCSCTL6 +#define OFS_UCSCTL6_H OFS_UCSCTL6+1 +#define OFS_UCSCTL7 (0x000Eu) /* UCS Control Register 7 */ +#define OFS_UCSCTL7_L OFS_UCSCTL7 +#define OFS_UCSCTL7_H OFS_UCSCTL7+1 +#define OFS_UCSCTL8 (0x0010u) /* UCS Control Register 8 */ +#define OFS_UCSCTL8_L OFS_UCSCTL8 +#define OFS_UCSCTL8_H OFS_UCSCTL8+1 + +/* UCSCTL0 Control Bits */ +//#define RESERVED (0x0001u) /* RESERVED */ +//#define RESERVED (0x0002u) /* RESERVED */ +//#define RESERVED (0x0004u) /* RESERVED */ +#define MOD0 (0x0008u) /* Modulation Bit Counter Bit : 0 */ +#define MOD1 (0x0010u) /* Modulation Bit Counter Bit : 1 */ +#define MOD2 (0x0020u) /* Modulation Bit Counter Bit : 2 */ +#define MOD3 (0x0040u) /* Modulation Bit Counter Bit : 3 */ +#define MOD4 (0x0080u) /* Modulation Bit Counter Bit : 4 */ +#define DCO0 (0x0100u) /* DCO TAP Bit : 0 */ +#define DCO1 (0x0200u) /* DCO TAP Bit : 1 */ +#define DCO2 (0x0400u) /* DCO TAP Bit : 2 */ +#define DCO3 (0x0800u) /* DCO TAP Bit : 3 */ +#define DCO4 (0x1000u) /* DCO TAP Bit : 4 */ +//#define RESERVED (0x2000u) /* RESERVED */ +//#define RESERVED (0x4000u) /* RESERVED */ +//#define RESERVED (0x8000u) /* RESERVED */ + +/* UCSCTL0 Control Bits */ +//#define RESERVED (0x0001u) /* RESERVED */ +//#define RESERVED (0x0002u) /* RESERVED */ +//#define RESERVED (0x0004u) /* RESERVED */ +#define MOD0_L (0x0008u) /* Modulation Bit Counter Bit : 0 */ +#define MOD1_L (0x0010u) /* Modulation Bit Counter Bit : 1 */ +#define MOD2_L (0x0020u) /* Modulation Bit Counter Bit : 2 */ +#define MOD3_L (0x0040u) /* Modulation Bit Counter Bit : 3 */ +#define MOD4_L (0x0080u) /* Modulation Bit Counter Bit : 4 */ +//#define RESERVED (0x2000u) /* RESERVED */ +//#define RESERVED (0x4000u) /* RESERVED */ +//#define RESERVED (0x8000u) /* RESERVED */ + +/* UCSCTL0 Control Bits */ +//#define RESERVED (0x0001u) /* RESERVED */ +//#define RESERVED (0x0002u) /* RESERVED */ +//#define RESERVED (0x0004u) /* RESERVED */ +#define DCO0_H (0x0001u) /* DCO TAP Bit : 0 */ +#define DCO1_H (0x0002u) /* DCO TAP Bit : 1 */ +#define DCO2_H (0x0004u) /* DCO TAP Bit : 2 */ +#define DCO3_H (0x0008u) /* DCO TAP Bit : 3 */ +#define DCO4_H (0x0010u) /* DCO TAP Bit : 4 */ +//#define RESERVED (0x2000u) /* RESERVED */ +//#define RESERVED (0x4000u) /* RESERVED */ +//#define RESERVED (0x8000u) /* RESERVED */ + +/* UCSCTL1 Control Bits */ +#define DISMOD (0x0001u) /* Disable Modulation */ +//#define RESERVED (0x0002u) /* RESERVED */ +//#define RESERVED (0x0004u) /* RESERVED */ +//#define RESERVED (0x0008u) /* RESERVED */ +#define DCORSEL0 (0x0010u) /* DCO Freq. Range Select Bit : 0 */ +#define DCORSEL1 (0x0020u) /* DCO Freq. Range Select Bit : 1 */ +#define DCORSEL2 (0x0040u) /* DCO Freq. Range Select Bit : 2 */ +//#define RESERVED (0x0080u) /* RESERVED */ +//#define RESERVED (0x0100u) /* RESERVED */ +//#define RESERVED (0x0200u) /* RESERVED */ +//#define RESERVED (0x0400u) /* RESERVED */ +//#define RESERVED (0x0800u) /* RESERVED */ +//#define RESERVED (0x1000u) /* RESERVED */ +//#define RESERVED (0x2000u) /* RESERVED */ +//#define RESERVED (0x4000u) /* RESERVED */ +//#define RESERVED (0x8000u) /* RESERVED */ + +/* UCSCTL1 Control Bits */ +#define DISMOD_L (0x0001u) /* Disable Modulation */ +//#define RESERVED (0x0002u) /* RESERVED */ +//#define RESERVED (0x0004u) /* RESERVED */ +//#define RESERVED (0x0008u) /* RESERVED */ +#define DCORSEL0_L (0x0010u) /* DCO Freq. Range Select Bit : 0 */ +#define DCORSEL1_L (0x0020u) /* DCO Freq. Range Select Bit : 1 */ +#define DCORSEL2_L (0x0040u) /* DCO Freq. Range Select Bit : 2 */ +//#define RESERVED (0x0080u) /* RESERVED */ +//#define RESERVED (0x0100u) /* RESERVED */ +//#define RESERVED (0x0200u) /* RESERVED */ +//#define RESERVED (0x0400u) /* RESERVED */ +//#define RESERVED (0x0800u) /* RESERVED */ +//#define RESERVED (0x1000u) /* RESERVED */ +//#define RESERVED (0x2000u) /* RESERVED */ +//#define RESERVED (0x4000u) /* RESERVED */ +//#define RESERVED (0x8000u) /* RESERVED */ + +#define DCORSEL_0 (0x0000u) /* DCO RSEL 0 */ +#define DCORSEL_1 (0x0010u) /* DCO RSEL 1 */ +#define DCORSEL_2 (0x0020u) /* DCO RSEL 2 */ +#define DCORSEL_3 (0x0030u) /* DCO RSEL 3 */ +#define DCORSEL_4 (0x0040u) /* DCO RSEL 4 */ +#define DCORSEL_5 (0x0050u) /* DCO RSEL 5 */ +#define DCORSEL_6 (0x0060u) /* DCO RSEL 6 */ +#define DCORSEL_7 (0x0070u) /* DCO RSEL 7 */ + +/* UCSCTL2 Control Bits */ +#define FLLN0 (0x0001u) /* FLL Multipier Bit : 0 */ +#define FLLN1 (0x0002u) /* FLL Multipier Bit : 1 */ +#define FLLN2 (0x0004u) /* FLL Multipier Bit : 2 */ +#define FLLN3 (0x0008u) /* FLL Multipier Bit : 3 */ +#define FLLN4 (0x0010u) /* FLL Multipier Bit : 4 */ +#define FLLN5 (0x0020u) /* FLL Multipier Bit : 5 */ +#define FLLN6 (0x0040u) /* FLL Multipier Bit : 6 */ +#define FLLN7 (0x0080u) /* FLL Multipier Bit : 7 */ +#define FLLN8 (0x0100u) /* FLL Multipier Bit : 8 */ +#define FLLN9 (0x0200u) /* FLL Multipier Bit : 9 */ +//#define RESERVED (0x0400u) /* RESERVED */ +//#define RESERVED (0x0800u) /* RESERVED */ +#define FLLD0 (0x1000u) /* Loop Divider Bit : 0 */ +#define FLLD1 (0x2000u) /* Loop Divider Bit : 1 */ +#define FLLD2 (0x4000u) /* Loop Divider Bit : 1 */ +//#define RESERVED (0x8000u) /* RESERVED */ + +/* UCSCTL2 Control Bits */ +#define FLLN0_L (0x0001u) /* FLL Multipier Bit : 0 */ +#define FLLN1_L (0x0002u) /* FLL Multipier Bit : 1 */ +#define FLLN2_L (0x0004u) /* FLL Multipier Bit : 2 */ +#define FLLN3_L (0x0008u) /* FLL Multipier Bit : 3 */ +#define FLLN4_L (0x0010u) /* FLL Multipier Bit : 4 */ +#define FLLN5_L (0x0020u) /* FLL Multipier Bit : 5 */ +#define FLLN6_L (0x0040u) /* FLL Multipier Bit : 6 */ +#define FLLN7_L (0x0080u) /* FLL Multipier Bit : 7 */ +//#define RESERVED (0x0400u) /* RESERVED */ +//#define RESERVED (0x0800u) /* RESERVED */ +//#define RESERVED (0x8000u) /* RESERVED */ + +/* UCSCTL2 Control Bits */ +#define FLLN8_H (0x0001u) /* FLL Multipier Bit : 8 */ +#define FLLN9_H (0x0002u) /* FLL Multipier Bit : 9 */ +//#define RESERVED (0x0400u) /* RESERVED */ +//#define RESERVED (0x0800u) /* RESERVED */ +#define FLLD0_H (0x0010u) /* Loop Divider Bit : 0 */ +#define FLLD1_H (0x0020u) /* Loop Divider Bit : 1 */ +#define FLLD2_H (0x0040u) /* Loop Divider Bit : 1 */ +//#define RESERVED (0x8000u) /* RESERVED */ + +#define FLLD_0 (0x0000u) /* Multiply Selected Loop Freq. 1 */ +#define FLLD_1 (0x1000u) /* Multiply Selected Loop Freq. 2 */ +#define FLLD_2 (0x2000u) /* Multiply Selected Loop Freq. 4 */ +#define FLLD_3 (0x3000u) /* Multiply Selected Loop Freq. 8 */ +#define FLLD_4 (0x4000u) /* Multiply Selected Loop Freq. 16 */ +#define FLLD_5 (0x5000u) /* Multiply Selected Loop Freq. 32 */ +#define FLLD_6 (0x6000u) /* Multiply Selected Loop Freq. 32 */ +#define FLLD_7 (0x7000u) /* Multiply Selected Loop Freq. 32 */ +#define FLLD__1 (0x0000u) /* Multiply Selected Loop Freq. By 1 */ +#define FLLD__2 (0x1000u) /* Multiply Selected Loop Freq. By 2 */ +#define FLLD__4 (0x2000u) /* Multiply Selected Loop Freq. By 4 */ +#define FLLD__8 (0x3000u) /* Multiply Selected Loop Freq. By 8 */ +#define FLLD__16 (0x4000u) /* Multiply Selected Loop Freq. By 16 */ +#define FLLD__32 (0x5000u) /* Multiply Selected Loop Freq. By 32 */ + +/* UCSCTL3 Control Bits */ +#define FLLREFDIV0 (0x0001u) /* Reference Divider Bit : 0 */ +#define FLLREFDIV1 (0x0002u) /* Reference Divider Bit : 1 */ +#define FLLREFDIV2 (0x0004u) /* Reference Divider Bit : 2 */ +//#define RESERVED (0x0008u) /* RESERVED */ +#define SELREF0 (0x0010u) /* FLL Reference Clock Select Bit : 0 */ +#define SELREF1 (0x0020u) /* FLL Reference Clock Select Bit : 1 */ +#define SELREF2 (0x0040u) /* FLL Reference Clock Select Bit : 2 */ +//#define RESERVED (0x0080u) /* RESERVED */ +//#define RESERVED (0x0100u) /* RESERVED */ +//#define RESERVED (0x0200u) /* RESERVED */ +//#define RESERVED (0x0400u) /* RESERVED */ +//#define RESERVED (0x0800u) /* RESERVED */ +//#define RESERVED (0x1000u) /* RESERVED */ +//#define RESERVED (0x2000u) /* RESERVED */ +//#define RESERVED (0x4000u) /* RESERVED */ +//#define RESERVED (0x8000u) /* RESERVED */ + +/* UCSCTL3 Control Bits */ +#define FLLREFDIV0_L (0x0001u) /* Reference Divider Bit : 0 */ +#define FLLREFDIV1_L (0x0002u) /* Reference Divider Bit : 1 */ +#define FLLREFDIV2_L (0x0004u) /* Reference Divider Bit : 2 */ +//#define RESERVED (0x0008u) /* RESERVED */ +#define SELREF0_L (0x0010u) /* FLL Reference Clock Select Bit : 0 */ +#define SELREF1_L (0x0020u) /* FLL Reference Clock Select Bit : 1 */ +#define SELREF2_L (0x0040u) /* FLL Reference Clock Select Bit : 2 */ +//#define RESERVED (0x0080u) /* RESERVED */ +//#define RESERVED (0x0100u) /* RESERVED */ +//#define RESERVED (0x0200u) /* RESERVED */ +//#define RESERVED (0x0400u) /* RESERVED */ +//#define RESERVED (0x0800u) /* RESERVED */ +//#define RESERVED (0x1000u) /* RESERVED */ +//#define RESERVED (0x2000u) /* RESERVED */ +//#define RESERVED (0x4000u) /* RESERVED */ +//#define RESERVED (0x8000u) /* RESERVED */ + +#define FLLREFDIV_0 (0x0000u) /* Reference Divider: f(LFCLK)/1 */ +#define FLLREFDIV_1 (0x0001u) /* Reference Divider: f(LFCLK)/2 */ +#define FLLREFDIV_2 (0x0002u) /* Reference Divider: f(LFCLK)/4 */ +#define FLLREFDIV_3 (0x0003u) /* Reference Divider: f(LFCLK)/8 */ +#define FLLREFDIV_4 (0x0004u) /* Reference Divider: f(LFCLK)/12 */ +#define FLLREFDIV_5 (0x0005u) /* Reference Divider: f(LFCLK)/16 */ +#define FLLREFDIV_6 (0x0006u) /* Reference Divider: f(LFCLK)/16 */ +#define FLLREFDIV_7 (0x0007u) /* Reference Divider: f(LFCLK)/16 */ +#define FLLREFDIV__1 (0x0000u) /* Reference Divider: f(LFCLK)/1 */ +#define FLLREFDIV__2 (0x0001u) /* Reference Divider: f(LFCLK)/2 */ +#define FLLREFDIV__4 (0x0002u) /* Reference Divider: f(LFCLK)/4 */ +#define FLLREFDIV__8 (0x0003u) /* Reference Divider: f(LFCLK)/8 */ +#define FLLREFDIV__12 (0x0004u) /* Reference Divider: f(LFCLK)/12 */ +#define FLLREFDIV__16 (0x0005u) /* Reference Divider: f(LFCLK)/16 */ +#define SELREF_0 (0x0000u) /* FLL Reference Clock Select 0 */ +#define SELREF_1 (0x0010u) /* FLL Reference Clock Select 1 */ +#define SELREF_2 (0x0020u) /* FLL Reference Clock Select 2 */ +#define SELREF_3 (0x0030u) /* FLL Reference Clock Select 3 */ +#define SELREF_4 (0x0040u) /* FLL Reference Clock Select 4 */ +#define SELREF_5 (0x0050u) /* FLL Reference Clock Select 5 */ +#define SELREF_6 (0x0060u) /* FLL Reference Clock Select 6 */ +#define SELREF_7 (0x0070u) /* FLL Reference Clock Select 7 */ +#define SELREF__XT1CLK (0x0000u) /* Multiply Selected Loop Freq. By XT1CLK */ +#define SELREF__REFOCLK (0x0020u) /* Multiply Selected Loop Freq. By REFOCLK */ +#define SELREF__XT2CLK (0x0050u) /* Multiply Selected Loop Freq. By XT2CLK */ + +/* UCSCTL4 Control Bits */ +#define SELM0 (0x0001u) /* MCLK Source Select Bit: 0 */ +#define SELM1 (0x0002u) /* MCLK Source Select Bit: 1 */ +#define SELM2 (0x0004u) /* MCLK Source Select Bit: 2 */ +//#define RESERVED (0x0008u) /* RESERVED */ +#define SELS0 (0x0010u) /* SMCLK Source Select Bit: 0 */ +#define SELS1 (0x0020u) /* SMCLK Source Select Bit: 1 */ +#define SELS2 (0x0040u) /* SMCLK Source Select Bit: 2 */ +//#define RESERVED (0x0080u) /* RESERVED */ +#define SELA0 (0x0100u) /* ACLK Source Select Bit: 0 */ +#define SELA1 (0x0200u) /* ACLK Source Select Bit: 1 */ +#define SELA2 (0x0400u) /* ACLK Source Select Bit: 2 */ +//#define RESERVED (0x0800u) /* RESERVED */ +//#define RESERVED (0x1000u) /* RESERVED */ +//#define RESERVED (0x2000u) /* RESERVED */ +//#define RESERVED (0x4000u) /* RESERVED */ +//#define RESERVED (0x8000u) /* RESERVED */ + +/* UCSCTL4 Control Bits */ +#define SELM0_L (0x0001u) /* MCLK Source Select Bit: 0 */ +#define SELM1_L (0x0002u) /* MCLK Source Select Bit: 1 */ +#define SELM2_L (0x0004u) /* MCLK Source Select Bit: 2 */ +//#define RESERVED (0x0008u) /* RESERVED */ +#define SELS0_L (0x0010u) /* SMCLK Source Select Bit: 0 */ +#define SELS1_L (0x0020u) /* SMCLK Source Select Bit: 1 */ +#define SELS2_L (0x0040u) /* SMCLK Source Select Bit: 2 */ +//#define RESERVED (0x0080u) /* RESERVED */ +//#define RESERVED (0x0800u) /* RESERVED */ +//#define RESERVED (0x1000u) /* RESERVED */ +//#define RESERVED (0x2000u) /* RESERVED */ +//#define RESERVED (0x4000u) /* RESERVED */ +//#define RESERVED (0x8000u) /* RESERVED */ + +/* UCSCTL4 Control Bits */ +//#define RESERVED (0x0008u) /* RESERVED */ +//#define RESERVED (0x0080u) /* RESERVED */ +#define SELA0_H (0x0001u) /* ACLK Source Select Bit: 0 */ +#define SELA1_H (0x0002u) /* ACLK Source Select Bit: 1 */ +#define SELA2_H (0x0004u) /* ACLK Source Select Bit: 2 */ +//#define RESERVED (0x0800u) /* RESERVED */ +//#define RESERVED (0x1000u) /* RESERVED */ +//#define RESERVED (0x2000u) /* RESERVED */ +//#define RESERVED (0x4000u) /* RESERVED */ +//#define RESERVED (0x8000u) /* RESERVED */ + +#define SELM_0 (0x0000u) /* MCLK Source Select 0 */ +#define SELM_1 (0x0001u) /* MCLK Source Select 1 */ +#define SELM_2 (0x0002u) /* MCLK Source Select 2 */ +#define SELM_3 (0x0003u) /* MCLK Source Select 3 */ +#define SELM_4 (0x0004u) /* MCLK Source Select 4 */ +#define SELM_5 (0x0005u) /* MCLK Source Select 5 */ +#define SELM_6 (0x0006u) /* MCLK Source Select 6 */ +#define SELM_7 (0x0007u) /* MCLK Source Select 7 */ +#define SELM__XT1CLK (0x0000u) /* MCLK Source Select XT1CLK */ +#define SELM__VLOCLK (0x0001u) /* MCLK Source Select VLOCLK */ +#define SELM__REFOCLK (0x0002u) /* MCLK Source Select REFOCLK */ +#define SELM__DCOCLK (0x0003u) /* MCLK Source Select DCOCLK */ +#define SELM__DCOCLKDIV (0x0004u) /* MCLK Source Select DCOCLKDIV */ +#define SELM__XT2CLK (0x0005u) /* MCLK Source Select XT2CLK */ + +#define SELS_0 (0x0000u) /* SMCLK Source Select 0 */ +#define SELS_1 (0x0010u) /* SMCLK Source Select 1 */ +#define SELS_2 (0x0020u) /* SMCLK Source Select 2 */ +#define SELS_3 (0x0030u) /* SMCLK Source Select 3 */ +#define SELS_4 (0x0040u) /* SMCLK Source Select 4 */ +#define SELS_5 (0x0050u) /* SMCLK Source Select 5 */ +#define SELS_6 (0x0060u) /* SMCLK Source Select 6 */ +#define SELS_7 (0x0070u) /* SMCLK Source Select 7 */ +#define SELS__XT1CLK (0x0000u) /* SMCLK Source Select XT1CLK */ +#define SELS__VLOCLK (0x0010u) /* SMCLK Source Select VLOCLK */ +#define SELS__REFOCLK (0x0020u) /* SMCLK Source Select REFOCLK */ +#define SELS__DCOCLK (0x0030u) /* SMCLK Source Select DCOCLK */ +#define SELS__DCOCLKDIV (0x0040u) /* SMCLK Source Select DCOCLKDIV */ +#define SELS__XT2CLK (0x0050u) /* SMCLK Source Select XT2CLK */ + +#define SELA_0 (0x0000u) /* ACLK Source Select 0 */ +#define SELA_1 (0x0100u) /* ACLK Source Select 1 */ +#define SELA_2 (0x0200u) /* ACLK Source Select 2 */ +#define SELA_3 (0x0300u) /* ACLK Source Select 3 */ +#define SELA_4 (0x0400u) /* ACLK Source Select 4 */ +#define SELA_5 (0x0500u) /* ACLK Source Select 5 */ +#define SELA_6 (0x0600u) /* ACLK Source Select 6 */ +#define SELA_7 (0x0700u) /* ACLK Source Select 7 */ +#define SELA__XT1CLK (0x0000u) /* ACLK Source Select XT1CLK */ +#define SELA__VLOCLK (0x0100u) /* ACLK Source Select VLOCLK */ +#define SELA__REFOCLK (0x0200u) /* ACLK Source Select REFOCLK */ +#define SELA__DCOCLK (0x0300u) /* ACLK Source Select DCOCLK */ +#define SELA__DCOCLKDIV (0x0400u) /* ACLK Source Select DCOCLKDIV */ +#define SELA__XT2CLK (0x0500u) /* ACLK Source Select XT2CLK */ + +/* UCSCTL5 Control Bits */ +#define DIVM0 (0x0001u) /* MCLK Divider Bit: 0 */ +#define DIVM1 (0x0002u) /* MCLK Divider Bit: 1 */ +#define DIVM2 (0x0004u) /* MCLK Divider Bit: 2 */ +//#define RESERVED (0x0008u) /* RESERVED */ +#define DIVS0 (0x0010u) /* SMCLK Divider Bit: 0 */ +#define DIVS1 (0x0020u) /* SMCLK Divider Bit: 1 */ +#define DIVS2 (0x0040u) /* SMCLK Divider Bit: 2 */ +//#define RESERVED (0x0080u) /* RESERVED */ +#define DIVA0 (0x0100u) /* ACLK Divider Bit: 0 */ +#define DIVA1 (0x0200u) /* ACLK Divider Bit: 1 */ +#define DIVA2 (0x0400u) /* ACLK Divider Bit: 2 */ +//#define RESERVED (0x0800u) /* RESERVED */ +#define DIVPA0 (0x1000u) /* ACLK from Pin Divider Bit: 0 */ +#define DIVPA1 (0x2000u) /* ACLK from Pin Divider Bit: 1 */ +#define DIVPA2 (0x4000u) /* ACLK from Pin Divider Bit: 2 */ +//#define RESERVED (0x8000u) /* RESERVED */ + +/* UCSCTL5 Control Bits */ +#define DIVM0_L (0x0001u) /* MCLK Divider Bit: 0 */ +#define DIVM1_L (0x0002u) /* MCLK Divider Bit: 1 */ +#define DIVM2_L (0x0004u) /* MCLK Divider Bit: 2 */ +//#define RESERVED (0x0008u) /* RESERVED */ +#define DIVS0_L (0x0010u) /* SMCLK Divider Bit: 0 */ +#define DIVS1_L (0x0020u) /* SMCLK Divider Bit: 1 */ +#define DIVS2_L (0x0040u) /* SMCLK Divider Bit: 2 */ +//#define RESERVED (0x0080u) /* RESERVED */ +//#define RESERVED (0x0800u) /* RESERVED */ +//#define RESERVED (0x8000u) /* RESERVED */ + +/* UCSCTL5 Control Bits */ +//#define RESERVED (0x0008u) /* RESERVED */ +//#define RESERVED (0x0080u) /* RESERVED */ +#define DIVA0_H (0x0001u) /* ACLK Divider Bit: 0 */ +#define DIVA1_H (0x0002u) /* ACLK Divider Bit: 1 */ +#define DIVA2_H (0x0004u) /* ACLK Divider Bit: 2 */ +//#define RESERVED (0x0800u) /* RESERVED */ +#define DIVPA0_H (0x0010u) /* ACLK from Pin Divider Bit: 0 */ +#define DIVPA1_H (0x0020u) /* ACLK from Pin Divider Bit: 1 */ +#define DIVPA2_H (0x0040u) /* ACLK from Pin Divider Bit: 2 */ +//#define RESERVED (0x8000u) /* RESERVED */ + +#define DIVM_0 (0x0000u) /* MCLK Source Divider 0 */ +#define DIVM_1 (0x0001u) /* MCLK Source Divider 1 */ +#define DIVM_2 (0x0002u) /* MCLK Source Divider 2 */ +#define DIVM_3 (0x0003u) /* MCLK Source Divider 3 */ +#define DIVM_4 (0x0004u) /* MCLK Source Divider 4 */ +#define DIVM_5 (0x0005u) /* MCLK Source Divider 5 */ +#define DIVM_6 (0x0006u) /* MCLK Source Divider 6 */ +#define DIVM_7 (0x0007u) /* MCLK Source Divider 7 */ +#define DIVM__1 (0x0000u) /* MCLK Source Divider f(MCLK)/1 */ +#define DIVM__2 (0x0001u) /* MCLK Source Divider f(MCLK)/2 */ +#define DIVM__4 (0x0002u) /* MCLK Source Divider f(MCLK)/4 */ +#define DIVM__8 (0x0003u) /* MCLK Source Divider f(MCLK)/8 */ +#define DIVM__16 (0x0004u) /* MCLK Source Divider f(MCLK)/16 */ +#define DIVM__32 (0x0005u) /* MCLK Source Divider f(MCLK)/32 */ + +#define DIVS_0 (0x0000u) /* SMCLK Source Divider 0 */ +#define DIVS_1 (0x0010u) /* SMCLK Source Divider 1 */ +#define DIVS_2 (0x0020u) /* SMCLK Source Divider 2 */ +#define DIVS_3 (0x0030u) /* SMCLK Source Divider 3 */ +#define DIVS_4 (0x0040u) /* SMCLK Source Divider 4 */ +#define DIVS_5 (0x0050u) /* SMCLK Source Divider 5 */ +#define DIVS_6 (0x0060u) /* SMCLK Source Divider 6 */ +#define DIVS_7 (0x0070u) /* SMCLK Source Divider 7 */ +#define DIVS__1 (0x0000u) /* SMCLK Source Divider f(SMCLK)/1 */ +#define DIVS__2 (0x0010u) /* SMCLK Source Divider f(SMCLK)/2 */ +#define DIVS__4 (0x0020u) /* SMCLK Source Divider f(SMCLK)/4 */ +#define DIVS__8 (0x0030u) /* SMCLK Source Divider f(SMCLK)/8 */ +#define DIVS__16 (0x0040u) /* SMCLK Source Divider f(SMCLK)/16 */ +#define DIVS__32 (0x0050u) /* SMCLK Source Divider f(SMCLK)/32 */ + +#define DIVA_0 (0x0000u) /* ACLK Source Divider 0 */ +#define DIVA_1 (0x0100u) /* ACLK Source Divider 1 */ +#define DIVA_2 (0x0200u) /* ACLK Source Divider 2 */ +#define DIVA_3 (0x0300u) /* ACLK Source Divider 3 */ +#define DIVA_4 (0x0400u) /* ACLK Source Divider 4 */ +#define DIVA_5 (0x0500u) /* ACLK Source Divider 5 */ +#define DIVA_6 (0x0600u) /* ACLK Source Divider 6 */ +#define DIVA_7 (0x0700u) /* ACLK Source Divider 7 */ +#define DIVA__1 (0x0000u) /* ACLK Source Divider f(ACLK)/1 */ +#define DIVA__2 (0x0100u) /* ACLK Source Divider f(ACLK)/2 */ +#define DIVA__4 (0x0200u) /* ACLK Source Divider f(ACLK)/4 */ +#define DIVA__8 (0x0300u) /* ACLK Source Divider f(ACLK)/8 */ +#define DIVA__16 (0x0400u) /* ACLK Source Divider f(ACLK)/16 */ +#define DIVA__32 (0x0500u) /* ACLK Source Divider f(ACLK)/32 */ + +#define DIVPA_0 (0x0000u) /* ACLK from Pin Source Divider 0 */ +#define DIVPA_1 (0x1000u) /* ACLK from Pin Source Divider 1 */ +#define DIVPA_2 (0x2000u) /* ACLK from Pin Source Divider 2 */ +#define DIVPA_3 (0x3000u) /* ACLK from Pin Source Divider 3 */ +#define DIVPA_4 (0x4000u) /* ACLK from Pin Source Divider 4 */ +#define DIVPA_5 (0x5000u) /* ACLK from Pin Source Divider 5 */ +#define DIVPA_6 (0x6000u) /* ACLK from Pin Source Divider 6 */ +#define DIVPA_7 (0x7000u) /* ACLK from Pin Source Divider 7 */ +#define DIVPA__1 (0x0000u) /* ACLK from Pin Source Divider f(ACLK)/1 */ +#define DIVPA__2 (0x1000u) /* ACLK from Pin Source Divider f(ACLK)/2 */ +#define DIVPA__4 (0x2000u) /* ACLK from Pin Source Divider f(ACLK)/4 */ +#define DIVPA__8 (0x3000u) /* ACLK from Pin Source Divider f(ACLK)/8 */ +#define DIVPA__16 (0x4000u) /* ACLK from Pin Source Divider f(ACLK)/16 */ +#define DIVPA__32 (0x5000u) /* ACLK from Pin Source Divider f(ACLK)/32 */ + +/* UCSCTL6 Control Bits */ +#define XT1OFF (0x0001u) /* High Frequency Oscillator 1 (XT1) disable */ +#define SMCLKOFF (0x0002u) /* SMCLK Off */ +#define XCAP0 (0x0004u) /* XIN/XOUT Cap Bit: 0 */ +#define XCAP1 (0x0008u) /* XIN/XOUT Cap Bit: 1 */ +#define XT1BYPASS (0x0010u) /* XT1 bypass mode : 0: internal 1:sourced from external pin */ +#define XTS (0x0020u) /* 1: Selects high-freq. oscillator */ +#define XT1DRIVE0 (0x0040u) /* XT1 Drive Level mode Bit 0 */ +#define XT1DRIVE1 (0x0080u) /* XT1 Drive Level mode Bit 1 */ +#define XT2OFF (0x0100u) /* High Frequency Oscillator 2 (XT2) disable */ +//#define RESERVED (0x0200u) /* RESERVED */ +//#define RESERVED (0x0400u) /* RESERVED */ +//#define RESERVED (0x0800u) /* RESERVED */ +//#define RESERVED (0x1000u) /* RESERVED */ +//#define RESERVED (0x2000u) /* RESERVED */ +//#define RESERVED (0x4000u) /* RESERVED */ +//#define RESERVED (0x8000u) /* RESERVED */ + +/* UCSCTL6 Control Bits */ +#define XT1OFF_L (0x0001u) /* High Frequency Oscillator 1 (XT1) disable */ +#define SMCLKOFF_L (0x0002u) /* SMCLK Off */ +#define XCAP0_L (0x0004u) /* XIN/XOUT Cap Bit: 0 */ +#define XCAP1_L (0x0008u) /* XIN/XOUT Cap Bit: 1 */ +#define XT1BYPASS_L (0x0010u) /* XT1 bypass mode : 0: internal 1:sourced from external pin */ +#define XTS_L (0x0020u) /* 1: Selects high-freq. oscillator */ +#define XT1DRIVE0_L (0x0040u) /* XT1 Drive Level mode Bit 0 */ +#define XT1DRIVE1_L (0x0080u) /* XT1 Drive Level mode Bit 1 */ +//#define RESERVED (0x0200u) /* RESERVED */ +//#define RESERVED (0x0400u) /* RESERVED */ +//#define RESERVED (0x0800u) /* RESERVED */ +//#define RESERVED (0x1000u) /* RESERVED */ +//#define RESERVED (0x2000u) /* RESERVED */ +//#define RESERVED (0x4000u) /* RESERVED */ +//#define RESERVED (0x8000u) /* RESERVED */ + +/* UCSCTL6 Control Bits */ +#define XT2OFF_H (0x0001u) /* High Frequency Oscillator 2 (XT2) disable */ +//#define RESERVED (0x0200u) /* RESERVED */ +//#define RESERVED (0x0400u) /* RESERVED */ +//#define RESERVED (0x0800u) /* RESERVED */ +//#define RESERVED (0x1000u) /* RESERVED */ +//#define RESERVED (0x2000u) /* RESERVED */ +//#define RESERVED (0x4000u) /* RESERVED */ +//#define RESERVED (0x8000u) /* RESERVED */ + +#define XCAP_0 (0x0000u) /* XIN/XOUT Cap 0 */ +#define XCAP_1 (0x0004u) /* XIN/XOUT Cap 1 */ +#define XCAP_2 (0x0008u) /* XIN/XOUT Cap 2 */ +#define XCAP_3 (0x000Cu) /* XIN/XOUT Cap 3 */ +#define XT1DRIVE_0 (0x0000u) /* XT1 Drive Level mode: 0 */ +#define XT1DRIVE_1 (0x0040u) /* XT1 Drive Level mode: 1 */ +#define XT1DRIVE_2 (0x0080u) /* XT1 Drive Level mode: 2 */ +#define XT1DRIVE_3 (0x00C0u) /* XT1 Drive Level mode: 3 */ + +/* UCSCTL7 Control Bits */ +#define DCOFFG (0x0001u) /* DCO Fault Flag */ +#define XT1LFOFFG (0x0002u) /* XT1 Low Frequency Oscillator Fault Flag */ +#define XT1HFOFFG (0x0004u) /* XT1 High Frequency Oscillator 1 Fault Flag */ +#define XT2OFFG (0x0008u) /* High Frequency Oscillator 2 Fault Flag */ +//#define RESERVED (0x0010u) /* RESERVED */ +//#define RESERVED (0x0020u) /* RESERVED */ +//#define RESERVED (0x0040u) /* RESERVED */ +//#define RESERVED (0x0080u) /* RESERVED */ +//#define RESERVED (0x0100u) /* RESERVED */ +//#define RESERVED (0x0200u) /* RESERVED */ +//#define RESERVED (0x0400u) /* RESERVED */ +//#define RESERVED (0x0800u) /* RESERVED */ +//#define RESERVED (0x1000u) /* RESERVED */ +//#define RESERVED (0x2000u) /* RESERVED */ +//#define RESERVED (0x4000u) /* RESERVED */ +//#define RESERVED (0x8000u) /* RESERVED */ + +/* UCSCTL7 Control Bits */ +#define DCOFFG_L (0x0001u) /* DCO Fault Flag */ +#define XT1LFOFFG_L (0x0002u) /* XT1 Low Frequency Oscillator Fault Flag */ +#define XT1HFOFFG_L (0x0004u) /* XT1 High Frequency Oscillator 1 Fault Flag */ +#define XT2OFFG_L (0x0008u) /* High Frequency Oscillator 2 Fault Flag */ +//#define RESERVED (0x0010u) /* RESERVED */ +//#define RESERVED (0x0020u) /* RESERVED */ +//#define RESERVED (0x0040u) /* RESERVED */ +//#define RESERVED (0x0080u) /* RESERVED */ +//#define RESERVED (0x0100u) /* RESERVED */ +//#define RESERVED (0x0200u) /* RESERVED */ +//#define RESERVED (0x0400u) /* RESERVED */ +//#define RESERVED (0x0800u) /* RESERVED */ +//#define RESERVED (0x1000u) /* RESERVED */ +//#define RESERVED (0x2000u) /* RESERVED */ +//#define RESERVED (0x4000u) /* RESERVED */ +//#define RESERVED (0x8000u) /* RESERVED */ + +/* UCSCTL8 Control Bits */ +#define ACLKREQEN (0x0001u) /* ACLK Clock Request Enable */ +#define MCLKREQEN (0x0002u) /* MCLK Clock Request Enable */ +#define SMCLKREQEN (0x0004u) /* SMCLK Clock Request Enable */ +#define MODOSCREQEN (0x0008u) /* MODOSC Clock Request Enable */ +//#define RESERVED (0x0010u) /* RESERVED */ +//#define RESERVED (0x0020u) /* RESERVED */ +//#define RESERVED (0x0040u) /* RESERVED */ +//#define RESERVED (0x0080u) /* RESERVED */ +//#define RESERVED (0x0100u) /* RESERVED */ +//#define RESERVED (0x0200u) /* RESERVED */ +//#define RESERVED (0x0400u) /* RESERVED */ +//#define RESERVED (0x0800u) /* RESERVED */ +//#define RESERVED (0x1000u) /* RESERVED */ +//#define RESERVED (0x2000u) /* RESERVED */ +//#define RESERVED (0x4000u) /* RESERVED */ +//#define RESERVED (0x8000u) /* RESERVED */ + +/* UCSCTL8 Control Bits */ +#define ACLKREQEN_L (0x0001u) /* ACLK Clock Request Enable */ +#define MCLKREQEN_L (0x0002u) /* MCLK Clock Request Enable */ +#define SMCLKREQEN_L (0x0004u) /* SMCLK Clock Request Enable */ +#define MODOSCREQEN_L (0x0008u) /* MODOSC Clock Request Enable */ +//#define RESERVED (0x0010u) /* RESERVED */ +//#define RESERVED (0x0020u) /* RESERVED */ +//#define RESERVED (0x0040u) /* RESERVED */ +//#define RESERVED (0x0080u) /* RESERVED */ +//#define RESERVED (0x0100u) /* RESERVED */ +//#define RESERVED (0x0200u) /* RESERVED */ +//#define RESERVED (0x0400u) /* RESERVED */ +//#define RESERVED (0x0800u) /* RESERVED */ +//#define RESERVED (0x1000u) /* RESERVED */ +//#define RESERVED (0x2000u) /* RESERVED */ +//#define RESERVED (0x4000u) /* RESERVED */ +//#define RESERVED (0x8000u) /* RESERVED */ + +#endif +/************************************************************ +* USB +************************************************************/ +#ifdef __MSP430_HAS_USB__ /* Definition to show that Module is available */ + +/* ========================================================================= */ +/* USB Configuration Registers */ +/* ========================================================================= */ +#define OFS_USBKEYID (0x0000u) /* USB Controller key register */ +#define OFS_USBKEYID_L OFS_USBKEYID +#define OFS_USBKEYID_H OFS_USBKEYID+1 +#define OFS_USBCNF (0x0002u) /* USB Module configuration register */ +#define OFS_USBCNF_L OFS_USBCNF +#define OFS_USBCNF_H OFS_USBCNF+1 +#define OFS_USBPHYCTL (0x0004u) /* USB PHY control register */ +#define OFS_USBPHYCTL_L OFS_USBPHYCTL +#define OFS_USBPHYCTL_H OFS_USBPHYCTL+1 +#define OFS_USBPWRCTL (0x0008u) /* USB Power control register */ +#define OFS_USBPWRCTL_L OFS_USBPWRCTL +#define OFS_USBPWRCTL_H OFS_USBPWRCTL+1 +#define OFS_USBPLLCTL (0x0010u) /* USB PLL control register */ +#define OFS_USBPLLCTL_L OFS_USBPLLCTL +#define OFS_USBPLLCTL_H OFS_USBPLLCTL+1 +#define OFS_USBPLLDIVB (0x0012u) /* USB PLL Clock Divider Buffer control register */ +#define OFS_USBPLLDIVB_L OFS_USBPLLDIVB +#define OFS_USBPLLDIVB_H OFS_USBPLLDIVB+1 +#define OFS_USBPLLIR (0x0014u) /* USB PLL Interrupt control register */ +#define OFS_USBPLLIR_L OFS_USBPLLIR +#define OFS_USBPLLIR_H OFS_USBPLLIR+1 + +#define USBKEYPID USBKEYID /* Legacy Definition: USB Controller key register */ +#define USBKEY (0x9628u) /* USB Control Register key */ + +/* USBCNF Control Bits */ +#define USB_EN (0x0001u) /* USB - Module enable */ +#define PUR_EN (0x0002u) /* USB - PUR pin enable */ +#define PUR_IN (0x0004u) /* USB - PUR pin input value */ +#define BLKRDY (0x0008u) /* USB - Block ready signal for DMA */ +#define FNTEN (0x0010u) /* USB - Frame Number receive Trigger enable for DMA */ +//#define RESERVED (0x0020u) /* USB - */ +//#define RESERVED (0x0040u) /* USB - */ +//#define RESERVED (0x0080u) /* USB - */ +//#define RESERVED (0x0100u) /* USB - */ +//#define RESERVED (0x0200u) /* USB - */ +//#define RESERVED (0x0400u) /* USB - */ +//#define RESERVED (0x0800u) /* USB - */ +//#define RESERVED (0x1000u) /* USB - */ +//#define RESERVED (0x2000u) /* USB - */ +//#define RESERVED (0x4000u) /* USB - */ +//#define RESERVED (0x8000u) /* USB - */ + +/* USBCNF Control Bits */ +#define USB_EN_L (0x0001u) /* USB - Module enable */ +#define PUR_EN_L (0x0002u) /* USB - PUR pin enable */ +#define PUR_IN_L (0x0004u) /* USB - PUR pin input value */ +#define BLKRDY_L (0x0008u) /* USB - Block ready signal for DMA */ +#define FNTEN_L (0x0010u) /* USB - Frame Number receive Trigger enable for DMA */ +//#define RESERVED (0x0020u) /* USB - */ +//#define RESERVED (0x0040u) /* USB - */ +//#define RESERVED (0x0080u) /* USB - */ +//#define RESERVED (0x0100u) /* USB - */ +//#define RESERVED (0x0200u) /* USB - */ +//#define RESERVED (0x0400u) /* USB - */ +//#define RESERVED (0x0800u) /* USB - */ +//#define RESERVED (0x1000u) /* USB - */ +//#define RESERVED (0x2000u) /* USB - */ +//#define RESERVED (0x4000u) /* USB - */ +//#define RESERVED (0x8000u) /* USB - */ + +/* USBPHYCTL Control Bits */ +#define PUOUT0 (0x0001u) /* USB - USB Port Output Signal Bit 0 */ +#define PUOUT1 (0x0002u) /* USB - USB Port Output Signal Bit 1 */ +#define PUIN0 (0x0004u) /* USB - PU0/DP Input Data */ +#define PUIN1 (0x0008u) /* USB - PU1/DM Input Data */ +//#define RESERVED (0x0010u) /* USB - */ +#define PUOPE (0x0020u) /* USB - USB Port Output Enable */ +//#define RESERVED (0x0040u) /* USB - */ +#define PUSEL (0x0080u) /* USB - USB Port Function Select */ +#define PUIPE (0x0100u) /* USB - PHY Single Ended Input enable */ +//#define RESERVED (0x0200u) /* USB - */ +//#define RESERVED (0x0100u) /* USB - */ +//#define RESERVED (0x0200u) /* USB - */ +//#define RESERVED (0x0400u) /* USB - */ +//#define RESERVED (0x0800u) /* USB - */ +//#define RESERVED (0x1000u) /* USB - */ +//#define RESERVED (0x2000u) /* USB - */ +//#define RESERVED (0x4000u) /* USB - */ +//#define RESERVED (0x8000u) /* USB - */ + +/* USBPHYCTL Control Bits */ +#define PUOUT0_L (0x0001u) /* USB - USB Port Output Signal Bit 0 */ +#define PUOUT1_L (0x0002u) /* USB - USB Port Output Signal Bit 1 */ +#define PUIN0_L (0x0004u) /* USB - PU0/DP Input Data */ +#define PUIN1_L (0x0008u) /* USB - PU1/DM Input Data */ +//#define RESERVED (0x0010u) /* USB - */ +#define PUOPE_L (0x0020u) /* USB - USB Port Output Enable */ +//#define RESERVED (0x0040u) /* USB - */ +#define PUSEL_L (0x0080u) /* USB - USB Port Function Select */ +//#define RESERVED (0x0200u) /* USB - */ +//#define RESERVED (0x0100u) /* USB - */ +//#define RESERVED (0x0200u) /* USB - */ +//#define RESERVED (0x0400u) /* USB - */ +//#define RESERVED (0x0800u) /* USB - */ +//#define RESERVED (0x1000u) /* USB - */ +//#define RESERVED (0x2000u) /* USB - */ +//#define RESERVED (0x4000u) /* USB - */ +//#define RESERVED (0x8000u) /* USB - */ + +/* USBPHYCTL Control Bits */ +//#define RESERVED (0x0010u) /* USB - */ +//#define RESERVED (0x0040u) /* USB - */ +#define PUIPE_H (0x0001u) /* USB - PHY Single Ended Input enable */ +//#define RESERVED (0x0200u) /* USB - */ +//#define RESERVED (0x0100u) /* USB - */ +//#define RESERVED (0x0200u) /* USB - */ +//#define RESERVED (0x0400u) /* USB - */ +//#define RESERVED (0x0800u) /* USB - */ +//#define RESERVED (0x1000u) /* USB - */ +//#define RESERVED (0x2000u) /* USB - */ +//#define RESERVED (0x4000u) /* USB - */ +//#define RESERVED (0x8000u) /* USB - */ + +#define PUDIR (0x0020u) /* USB - Legacy Definition: USB Port Output Enable */ +#define PSEIEN (0x0100u) /* USB - Legacy Definition: PHY Single Ended Input enable */ + +/* USBPWRCTL Control Bits */ +#define VUOVLIFG (0x0001u) /* USB - VUSB Overload Interrupt Flag */ +#define VBONIFG (0x0002u) /* USB - VBUS "Coming ON" Interrupt Flag */ +#define VBOFFIFG (0x0004u) /* USB - VBUS "Going OFF" Interrupt Flag */ +#define USBBGVBV (0x0008u) /* USB - USB Bandgap and VBUS valid */ +#define USBDETEN (0x0010u) /* USB - VBUS on/off events enable */ +#define OVLAOFF (0x0020u) /* USB - LDO overload auto off enable */ +#define SLDOAON (0x0040u) /* USB - Secondary LDO auto on enable */ +//#define RESERVED (0x0080u) /* USB - */ +#define VUOVLIE (0x0100u) /* USB - Overload indication Interrupt Enable */ +#define VBONIE (0x0200u) /* USB - VBUS "Coming ON" Interrupt Enable */ +#define VBOFFIE (0x0400u) /* USB - VBUS "Going OFF" Interrupt Enable */ +#define VUSBEN (0x0800u) /* USB - LDO Enable (3.3V) */ +#define SLDOEN (0x1000u) /* USB - Secondary LDO Enable (1.8V) */ +//#define RESERVED (0x2000u) /* USB - */ +//#define RESERVED (0x4000u) /* USB - */ +//#define RESERVED (0x8000u) /* USB - */ + +/* USBPWRCTL Control Bits */ +#define VUOVLIFG_L (0x0001u) /* USB - VUSB Overload Interrupt Flag */ +#define VBONIFG_L (0x0002u) /* USB - VBUS "Coming ON" Interrupt Flag */ +#define VBOFFIFG_L (0x0004u) /* USB - VBUS "Going OFF" Interrupt Flag */ +#define USBBGVBV_L (0x0008u) /* USB - USB Bandgap and VBUS valid */ +#define USBDETEN_L (0x0010u) /* USB - VBUS on/off events enable */ +#define OVLAOFF_L (0x0020u) /* USB - LDO overload auto off enable */ +#define SLDOAON_L (0x0040u) /* USB - Secondary LDO auto on enable */ +//#define RESERVED (0x0080u) /* USB - */ +//#define RESERVED (0x2000u) /* USB - */ +//#define RESERVED (0x4000u) /* USB - */ +//#define RESERVED (0x8000u) /* USB - */ + +/* USBPWRCTL Control Bits */ +//#define RESERVED (0x0080u) /* USB - */ +#define VUOVLIE_H (0x0001u) /* USB - Overload indication Interrupt Enable */ +#define VBONIE_H (0x0002u) /* USB - VBUS "Coming ON" Interrupt Enable */ +#define VBOFFIE_H (0x0004u) /* USB - VBUS "Going OFF" Interrupt Enable */ +#define VUSBEN_H (0x0008u) /* USB - LDO Enable (3.3V) */ +#define SLDOEN_H (0x0010u) /* USB - Secondary LDO Enable (1.8V) */ +//#define RESERVED (0x2000u) /* USB - */ +//#define RESERVED (0x4000u) /* USB - */ +//#define RESERVED (0x8000u) /* USB - */ + +/* USBPLLCTL Control Bits */ +//#define RESERVED (0x0001u) /* USB - */ +//#define RESERVED (0x0002u) /* USB - */ +//#define RESERVED (0x0004u) /* USB - */ +//#define RESERVED (0x0008u) /* USB - */ +//#define RESERVED (0x0010u) /* USB - */ +//#define RESERVED (0x0020u) /* USB - */ +#define UCLKSEL0 (0x0040u) /* USB - Module Clock Select Bit 0 */ +#define UCLKSEL1 (0x0080u) /* USB - Module Clock Select Bit 1 */ +#define UPLLEN (0x0100u) /* USB - PLL enable */ +#define UPFDEN (0x0200u) /* USB - Phase Freq. Discriminator enable */ +//#define RESERVED (0x0400u) /* USB - */ +//#define RESERVED (0x0800u) /* USB - */ +//#define RESERVED (0x1000u) /* USB - */ +//#define RESERVED (0x2000u) /* USB - */ +//#define RESERVED (0x4000u) /* USB - */ +//#define RESERVED (0x8000u) /* USB - */ + +/* USBPLLCTL Control Bits */ +//#define RESERVED (0x0001u) /* USB - */ +//#define RESERVED (0x0002u) /* USB - */ +//#define RESERVED (0x0004u) /* USB - */ +//#define RESERVED (0x0008u) /* USB - */ +//#define RESERVED (0x0010u) /* USB - */ +//#define RESERVED (0x0020u) /* USB - */ +#define UCLKSEL0_L (0x0040u) /* USB - Module Clock Select Bit 0 */ +#define UCLKSEL1_L (0x0080u) /* USB - Module Clock Select Bit 1 */ +//#define RESERVED (0x0400u) /* USB - */ +//#define RESERVED (0x0800u) /* USB - */ +//#define RESERVED (0x1000u) /* USB - */ +//#define RESERVED (0x2000u) /* USB - */ +//#define RESERVED (0x4000u) /* USB - */ +//#define RESERVED (0x8000u) /* USB - */ + +/* USBPLLCTL Control Bits */ +//#define RESERVED (0x0001u) /* USB - */ +//#define RESERVED (0x0002u) /* USB - */ +//#define RESERVED (0x0004u) /* USB - */ +//#define RESERVED (0x0008u) /* USB - */ +//#define RESERVED (0x0010u) /* USB - */ +//#define RESERVED (0x0020u) /* USB - */ +#define UPLLEN_H (0x0001u) /* USB - PLL enable */ +#define UPFDEN_H (0x0002u) /* USB - Phase Freq. Discriminator enable */ +//#define RESERVED (0x0400u) /* USB - */ +//#define RESERVED (0x0800u) /* USB - */ +//#define RESERVED (0x1000u) /* USB - */ +//#define RESERVED (0x2000u) /* USB - */ +//#define RESERVED (0x4000u) /* USB - */ +//#define RESERVED (0x8000u) /* USB - */ + +#define UCLKSEL_0 (0x0000u) /* USB - Module Clock Select: 0 */ +#define UCLKSEL_1 (0x0040u) /* USB - Module Clock Select: 1 */ +#define UCLKSEL_2 (0x0080u) /* USB - Module Clock Select: 2 */ +#define UCLKSEL_3 (0x00C0u) /* USB - Module Clock Select: 3 (Reserved) */ + +#define UCLKSEL__PLLCLK (0x0000u) /* USB - Module Clock Select: PLLCLK */ +#define UCLKSEL__XT1CLK (0x0040u) /* USB - Module Clock Select: XT1CLK */ +#define UCLKSEL__XT2CLK (0x0080u) /* USB - Module Clock Select: XT2CLK */ + +/* USBPLLDIVB Control Bits */ +#define UPMB0 (0x0001u) /* USB - PLL feedback divider buffer Bit 0 */ +#define UPMB1 (0x0002u) /* USB - PLL feedback divider buffer Bit 1 */ +#define UPMB2 (0x0004u) /* USB - PLL feedback divider buffer Bit 2 */ +#define UPMB3 (0x0008u) /* USB - PLL feedback divider buffer Bit 3 */ +#define UPMB4 (0x0010u) /* USB - PLL feedback divider buffer Bit 4 */ +#define UPMB5 (0x0020u) /* USB - PLL feedback divider buffer Bit 5 */ +//#define RESERVED (0x0040u) /* USB - */ +//#define RESERVED (0x0080u) /* USB - */ +#define UPQB0 (0x0100u) /* USB - PLL prescale divider buffer Bit 0 */ +#define UPQB1 (0x0200u) /* USB - PLL prescale divider buffer Bit 1 */ +#define UPQB2 (0x0400u) /* USB - PLL prescale divider buffer Bit 2 */ +//#define RESERVED (0x0800u) /* USB - */ +//#define RESERVED (0x1000u) /* USB - */ +//#define RESERVED (0x2000u) /* USB - */ +//#define RESERVED (0x4000u) /* USB - */ +//#define RESERVED (0x8000u) /* USB - */ + +/* USBPLLDIVB Control Bits */ +#define UPMB0_L (0x0001u) /* USB - PLL feedback divider buffer Bit 0 */ +#define UPMB1_L (0x0002u) /* USB - PLL feedback divider buffer Bit 1 */ +#define UPMB2_L (0x0004u) /* USB - PLL feedback divider buffer Bit 2 */ +#define UPMB3_L (0x0008u) /* USB - PLL feedback divider buffer Bit 3 */ +#define UPMB4_L (0x0010u) /* USB - PLL feedback divider buffer Bit 4 */ +#define UPMB5_L (0x0020u) /* USB - PLL feedback divider buffer Bit 5 */ +//#define RESERVED (0x0040u) /* USB - */ +//#define RESERVED (0x0080u) /* USB - */ +//#define RESERVED (0x0800u) /* USB - */ +//#define RESERVED (0x1000u) /* USB - */ +//#define RESERVED (0x2000u) /* USB - */ +//#define RESERVED (0x4000u) /* USB - */ +//#define RESERVED (0x8000u) /* USB - */ + +/* USBPLLDIVB Control Bits */ +//#define RESERVED (0x0040u) /* USB - */ +//#define RESERVED (0x0080u) /* USB - */ +#define UPQB0_H (0x0001u) /* USB - PLL prescale divider buffer Bit 0 */ +#define UPQB1_H (0x0002u) /* USB - PLL prescale divider buffer Bit 1 */ +#define UPQB2_H (0x0004u) /* USB - PLL prescale divider buffer Bit 2 */ +//#define RESERVED (0x0800u) /* USB - */ +//#define RESERVED (0x1000u) /* USB - */ +//#define RESERVED (0x2000u) /* USB - */ +//#define RESERVED (0x4000u) /* USB - */ +//#define RESERVED (0x8000u) /* USB - */ + +#define USBPLL_SETCLK_1_5 (UPMB0*31 | UPQB0*0) /* USB - PLL Set for 1.5 MHz input clock */ +#define USBPLL_SETCLK_1_6 (UPMB0*29 | UPQB0*0) /* USB - PLL Set for 1.6 MHz input clock */ +#define USBPLL_SETCLK_1_7778 (UPMB0*26 | UPQB0*0) /* USB - PLL Set for 1.7778 MHz input clock */ +#define USBPLL_SETCLK_1_8432 (UPMB0*25 | UPQB0*0) /* USB - PLL Set for 1.8432 MHz input clock */ +#define USBPLL_SETCLK_1_8461 (UPMB0*25 | UPQB0*0) /* USB - PLL Set for 1.8461 MHz input clock */ +#define USBPLL_SETCLK_1_92 (UPMB0*24 | UPQB0*0) /* USB - PLL Set for 1.92 MHz input clock */ +#define USBPLL_SETCLK_2_0 (UPMB0*23 | UPQB0*0) /* USB - PLL Set for 2.0 MHz input clock */ +#define USBPLL_SETCLK_2_4 (UPMB0*19 | UPQB0*0) /* USB - PLL Set for 2.4 MHz input clock */ +#define USBPLL_SETCLK_2_6667 (UPMB0*17 | UPQB0*0) /* USB - PLL Set for 2.6667 MHz input clock */ +#define USBPLL_SETCLK_3_0 (UPMB0*15 | UPQB0*0) /* USB - PLL Set for 3.0 MHz input clock */ +#define USBPLL_SETCLK_3_2 (UPMB0*29 | UPQB0*1) /* USB - PLL Set for 3.2 MHz input clock */ +#define USBPLL_SETCLK_3_5556 (UPMB0*26 | UPQB0*1) /* USB - PLL Set for 3.5556 MHz input clock */ +#define USBPLL_SETCLK_3_579545 (UPMB0*26 | UPQB0*1) /* USB - PLL Set for 3.579546 MHz input clock */ +#define USBPLL_SETCLK_3_84 (UPMB0*24 | UPQB0*1) /* USB - PLL Set for 3.84 MHz input clock */ +#define USBPLL_SETCLK_4_0 (UPMB0*23 | UPQB0*1) /* USB - PLL Set for 4.0 MHz input clock */ +#define USBPLL_SETCLK_4_1739 (UPMB0*22 | UPQB0*1) /* USB - PLL Set for 4.1739 MHz input clock */ +#define USBPLL_SETCLK_4_1943 (UPMB0*22 | UPQB0*1) /* USB - PLL Set for 4.1943 MHz input clock */ +#define USBPLL_SETCLK_4_332 (UPMB0*21 | UPQB0*1) /* USB - PLL Set for 4.332 MHz input clock */ +#define USBPLL_SETCLK_4_3636 (UPMB0*21 | UPQB0*1) /* USB - PLL Set for 4.3636 MHz input clock */ +#define USBPLL_SETCLK_4_5 (UPMB0*31 | UPQB0*2) /* USB - PLL Set for 4.5 MHz input clock */ +#define USBPLL_SETCLK_4_8 (UPMB0*19 | UPQB0*1) /* USB - PLL Set for 4.8 MHz input clock */ +#define USBPLL_SETCLK_5_33 (UPMB0*17 | UPQB0*1) /* USB - PLL Set for 5.33 MHz input clock */ +#define USBPLL_SETCLK_5_76 (UPMB0*24 | UPQB0*2) /* USB - PLL Set for 5.76 MHz input clock */ +#define USBPLL_SETCLK_6_0 (UPMB0*23 | UPQB0*2) /* USB - PLL Set for 6.0 MHz input clock */ +#define USBPLL_SETCLK_6_4 (UPMB0*29 | UPQB0*3) /* USB - PLL Set for 6.4 MHz input clock */ +#define USBPLL_SETCLK_7_2 (UPMB0*19 | UPQB0*2) /* USB - PLL Set for 7.2 MHz input clock */ +#define USBPLL_SETCLK_7_68 (UPMB0*24 | UPQB0*3) /* USB - PLL Set for 7.68 MHz input clock */ +#define USBPLL_SETCLK_8_0 (UPMB0*17 | UPQB0*2) /* USB - PLL Set for 8.0 MHz input clock */ +#define USBPLL_SETCLK_9_0 (UPMB0*15 | UPQB0*2) /* USB - PLL Set for 9.0 MHz input clock */ +#define USBPLL_SETCLK_9_6 (UPMB0*19 | UPQB0*3) /* USB - PLL Set for 9.6 MHz input clock */ +#define USBPLL_SETCLK_10_66 (UPMB0*17 | UPQB0*3) /* USB - PLL Set for 10.66 MHz input clock */ +#define USBPLL_SETCLK_12_0 (UPMB0*15 | UPQB0*3) /* USB - PLL Set for 12.0 MHz input clock */ +#define USBPLL_SETCLK_12_8 (UPMB0*29 | UPQB0*5) /* USB - PLL Set for 12.8 MHz input clock */ +#define USBPLL_SETCLK_14_4 (UPMB0*19 | UPQB0*4) /* USB - PLL Set for 14.4 MHz input clock */ +#define USBPLL_SETCLK_16_0 (UPMB0*17 | UPQB0*4) /* USB - PLL Set for 16.0 MHz input clock */ +#define USBPLL_SETCLK_16_9344 (UPMB0*16 | UPQB0*4) /* USB - PLL Set for 16.9344 MHz input clock */ +#define USBPLL_SETCLK_16_94118 (UPMB0*16 | UPQB0*4) /* USB - PLL Set for 16.94118 MHz input clock */ +#define USBPLL_SETCLK_18_0 (UPMB0*15 | UPQB0*4) /* USB - PLL Set for 18.0 MHz input clock */ +#define USBPLL_SETCLK_19_2 (UPMB0*19 | UPQB0*5) /* USB - PLL Set for 19.2 MHz input clock */ +#define USBPLL_SETCLK_24_0 (UPMB0*15 | UPQB0*5) /* USB - PLL Set for 24.0 MHz input clock */ +#define USBPLL_SETCLK_25_6 (UPMB0*29 | UPQB0*7) /* USB - PLL Set for 25.6 MHz input clock */ +#define USBPLL_SETCLK_26_0 (UPMB0*23 | UPQB0*6) /* USB - PLL Set for 26.0 MHz input clock */ +#define USBPLL_SETCLK_32_0 (UPMB0*23 | UPQB0*7) /* USB - PLL Set for 32.0 MHz input clock */ + +/* USBPLLIR Control Bits */ +#define USBOOLIFG (0x0001u) /* USB - PLL out of lock Interrupt Flag */ +#define USBLOSIFG (0x0002u) /* USB - PLL loss of signal Interrupt Flag */ +#define USBOORIFG (0x0004u) /* USB - PLL out of range Interrupt Flag */ +//#define RESERVED (0x0008u) /* USB - */ +//#define RESERVED (0x0010u) /* USB - */ +//#define RESERVED (0x0020u) /* USB - */ +//#define RESERVED (0x0040u) /* USB - */ +//#define RESERVED (0x0080u) /* USB - */ +#define USBOOLIE (0x0100u) /* USB - PLL out of lock Interrupt enable */ +#define USBLOSIE (0x0200u) /* USB - PLL loss of signal Interrupt enable */ +#define USBOORIE (0x0400u) /* USB - PLL out of range Interrupt enable */ +//#define RESERVED (0x0800u) /* USB - */ +//#define RESERVED (0x1000u) /* USB - */ +//#define RESERVED (0x2000u) /* USB - */ +//#define RESERVED (0x4000u) /* USB - */ +//#define RESERVED (0x8000u) /* USB - */ + +/* USBPLLIR Control Bits */ +#define USBOOLIFG_L (0x0001u) /* USB - PLL out of lock Interrupt Flag */ +#define USBLOSIFG_L (0x0002u) /* USB - PLL loss of signal Interrupt Flag */ +#define USBOORIFG_L (0x0004u) /* USB - PLL out of range Interrupt Flag */ +//#define RESERVED (0x0008u) /* USB - */ +//#define RESERVED (0x0010u) /* USB - */ +//#define RESERVED (0x0020u) /* USB - */ +//#define RESERVED (0x0040u) /* USB - */ +//#define RESERVED (0x0080u) /* USB - */ +//#define RESERVED (0x0800u) /* USB - */ +//#define RESERVED (0x1000u) /* USB - */ +//#define RESERVED (0x2000u) /* USB - */ +//#define RESERVED (0x4000u) /* USB - */ +//#define RESERVED (0x8000u) /* USB - */ + +/* USBPLLIR Control Bits */ +//#define RESERVED (0x0008u) /* USB - */ +//#define RESERVED (0x0010u) /* USB - */ +//#define RESERVED (0x0020u) /* USB - */ +//#define RESERVED (0x0040u) /* USB - */ +//#define RESERVED (0x0080u) /* USB - */ +#define USBOOLIE_H (0x0001u) /* USB - PLL out of lock Interrupt enable */ +#define USBLOSIE_H (0x0002u) /* USB - PLL loss of signal Interrupt enable */ +#define USBOORIE_H (0x0004u) /* USB - PLL out of range Interrupt enable */ +//#define RESERVED (0x0800u) /* USB - */ +//#define RESERVED (0x1000u) /* USB - */ +//#define RESERVED (0x2000u) /* USB - */ +//#define RESERVED (0x4000u) /* USB - */ +//#define RESERVED (0x8000u) /* USB - */ + +/* ========================================================================= */ +/* USB Control Registers */ +/* ========================================================================= */ +#define OFS_USBIEPCNF_0 (0x0020u) /* USB Input endpoint_0: Configuration */ +#define OFS_USBIEPCNT_0 (0x0021u) /* USB Input endpoint_0: Byte Count */ +#define OFS_USBOEPCNF_0 (0x0022u) /* USB Output endpoint_0: Configuration */ +#define OFS_USBOEPCNT_0 (0x0023u) /* USB Output endpoint_0: byte count */ +#define OFS_USBIEPIE (0x002Eu) /* USB Input endpoint interrupt enable flags */ +#define OFS_USBOEPIE (0x002Fu) /* USB Output endpoint interrupt enable flags */ +#define OFS_USBIEPIFG (0x0030u) /* USB Input endpoint interrupt flags */ +#define OFS_USBOEPIFG (0x0031u) /* USB Output endpoint interrupt flags */ +#define OFS_USBVECINT (0x0032u) /* USB Vector interrupt register */ +#define OFS_USBVECINT_L OFS_USBVECINT +#define OFS_USBVECINT_H OFS_USBVECINT+1 +#define OFS_USBMAINT (0x0036u) /* USB maintenance register */ +#define OFS_USBMAINT_L OFS_USBMAINT +#define OFS_USBMAINT_H OFS_USBMAINT+1 +#define OFS_USBTSREG (0x0038u) /* USB Time Stamp register */ +#define OFS_USBTSREG_L OFS_USBTSREG +#define OFS_USBTSREG_H OFS_USBTSREG+1 +#define OFS_USBFN (0x003Au) /* USB Frame number */ +#define OFS_USBFN_L OFS_USBFN +#define OFS_USBFN_H OFS_USBFN+1 +#define OFS_USBCTL (0x003Cu) /* USB control register */ +#define OFS_USBIE (0x003Du) /* USB interrupt enable register */ +#define OFS_USBIFG (0x003Eu) /* USB interrupt flag register */ +#define OFS_USBFUNADR (0x003Fu) /* USB Function address register */ + +#define USBIV USBVECINT /* USB Vector interrupt register (alternate define) */ + +/* USBIEPCNF_0 Control Bits */ +/* USBOEPCNF_0 Control Bits */ +//#define RESERVED (0x0001u) /* USB - */ +//#define RESERVED (0x0001u) /* USB - */ +#define USBIIE (0x0004u) /* USB - Transaction Interrupt indication enable */ +#define STALL (0x0008u) /* USB - Stall Condition */ +//#define RESERVED (0x0010u) /* USB - */ +#define TOGGLE (0x0020u) /* USB - Toggle Bit */ +//#define RESERVED (0x0040u) /* USB - */ +#define UBME (0x0080u) /* USB - UBM In-Endpoint Enable */ + +/* USBIEPBCNT_0 Control Bits */ +/* USBOEPBCNT_0 Control Bits */ +#define CNT0 (0x0001u) /* USB - Byte Count Bit 0 */ +#define CNT1 (0x0001u) /* USB - Byte Count Bit 1 */ +#define CNT2 (0x0004u) /* USB - Byte Count Bit 2 */ +#define CNT3 (0x0008u) /* USB - Byte Count Bit 3 */ +//#define RESERVED (0x0010u) /* USB - */ +//#define RESERVED (0x0020u) /* USB - */ +//#define RESERVED (0x0040u) /* USB - */ +#define NAK (0x0080u) /* USB - No Acknowledge Status Bit */ + +/* USBMAINT Control Bits */ +#define UTIFG (0x0001u) /* USB - Timer Interrupt Flag */ +#define UTIE (0x0002u) /* USB - Timer Interrupt Enable */ +//#define RESERVED (0x0004u) /* USB - */ +//#define RESERVED (0x0008u) /* USB - */ +//#define RESERVED (0x0010u) /* USB - */ +//#define RESERVED (0x0020u) /* USB - */ +//#define RESERVED (0x0040u) /* USB - */ +//#define RESERVED (0x0080u) /* USB - */ +#define TSGEN (0x0100u) /* USB - Time Stamp Generator Enable */ +#define TSESEL0 (0x0200u) /* USB - Time Stamp Event Select Bit 0 */ +#define TSESEL1 (0x0400u) /* USB - Time Stamp Event Select Bit 1 */ +#define TSE3 (0x0800u) /* USB - Time Stamp Event #3 Bit */ +//#define RESERVED (0x1000u) /* USB - */ +#define UTSEL0 (0x2000u) /* USB - Timer Select Bit 0 */ +#define UTSEL1 (0x4000u) /* USB - Timer Select Bit 1 */ +#define UTSEL2 (0x8000u) /* USB - Timer Select Bit 2 */ + +/* USBMAINT Control Bits */ +#define UTIFG_L (0x0001u) /* USB - Timer Interrupt Flag */ +#define UTIE_L (0x0002u) /* USB - Timer Interrupt Enable */ +//#define RESERVED (0x0004u) /* USB - */ +//#define RESERVED (0x0008u) /* USB - */ +//#define RESERVED (0x0010u) /* USB - */ +//#define RESERVED (0x0020u) /* USB - */ +//#define RESERVED (0x0040u) /* USB - */ +//#define RESERVED (0x0080u) /* USB - */ +//#define RESERVED (0x1000u) /* USB - */ + +/* USBMAINT Control Bits */ +//#define RESERVED (0x0004u) /* USB - */ +//#define RESERVED (0x0008u) /* USB - */ +//#define RESERVED (0x0010u) /* USB - */ +//#define RESERVED (0x0020u) /* USB - */ +//#define RESERVED (0x0040u) /* USB - */ +//#define RESERVED (0x0080u) /* USB - */ +#define TSGEN_H (0x0001u) /* USB - Time Stamp Generator Enable */ +#define TSESEL0_H (0x0002u) /* USB - Time Stamp Event Select Bit 0 */ +#define TSESEL1_H (0x0004u) /* USB - Time Stamp Event Select Bit 1 */ +#define TSE3_H (0x0008u) /* USB - Time Stamp Event #3 Bit */ +//#define RESERVED (0x1000u) /* USB - */ +#define UTSEL0_H (0x0020u) /* USB - Timer Select Bit 0 */ +#define UTSEL1_H (0x0040u) /* USB - Timer Select Bit 1 */ +#define UTSEL2_H (0x0080u) /* USB - Timer Select Bit 2 */ + +#define TSESEL_0 (0x0000u) /* USB - Time Stamp Event Select: 0 */ +#define TSESEL_1 (0x0200u) /* USB - Time Stamp Event Select: 1 */ +#define TSESEL_2 (0x0400u) /* USB - Time Stamp Event Select: 2 */ +#define TSESEL_3 (0x0600u) /* USB - Time Stamp Event Select: 3 */ + +#define UTSEL_0 (0x0000u) /* USB - Timer Select: 0 */ +#define UTSEL_1 (0x2000u) /* USB - Timer Select: 1 */ +#define UTSEL_2 (0x4000u) /* USB - Timer Select: 2 */ +#define UTSEL_3 (0x6000u) /* USB - Timer Select: 3 */ +#define UTSEL_4 (0x8000u) /* USB - Timer Select: 4 */ +#define UTSEL_5 (0xA000u) /* USB - Timer Select: 5 */ +#define UTSEL_6 (0xC000u) /* USB - Timer Select: 6 */ +#define UTSEL_7 (0xE000u) /* USB - Timer Select: 7 */ + +/* USBCTL Control Bits */ +#define DIR (0x0001u) /* USB - Data Response Bit */ +//#define RESERVED (0x0002u) /* USB - */ +//#define RESERVED (0x0004u) /* USB - */ +//#define RESERVED (0x0008u) /* USB - */ +#define FRSTE (0x0010u) /* USB - Function Reset Connection Enable */ +#define RWUP (0x0020u) /* USB - Device Remote Wakeup Request */ +#define FEN (0x0040u) /* USB - Function Enable Bit */ +//#define RESERVED (0x0080u) /* USB - */ + +/* USBIE Control Bits */ +#define STPOWIE (0x0001u) /* USB - Setup Overwrite Interrupt Enable */ +//#define RESERVED (0x0002u) /* USB - */ +#define SETUPIE (0x0004u) /* USB - Setup Interrupt Enable */ +//#define RESERVED (0x0008u) /* USB - */ +//#define RESERVED (0x0010u) /* USB - */ +#define RESRIE (0x0020u) /* USB - Function Resume Request Interrupt Enable */ +#define SUSRIE (0x0040u) /* USB - Function Suspend Request Interrupt Enable */ +#define RSTRIE (0x0080u) /* USB - Function Reset Request Interrupt Enable */ + +/* USBIFG Control Bits */ +#define STPOWIFG (0x0001u) /* USB - Setup Overwrite Interrupt Flag */ +//#define RESERVED (0x0002u) /* USB - */ +#define SETUPIFG (0x0004u) /* USB - Setup Interrupt Flag */ +//#define RESERVED (0x0008u) /* USB - */ +//#define RESERVED (0x0010u) /* USB - */ +#define RESRIFG (0x0020u) /* USB - Function Resume Request Interrupt Flag */ +#define SUSRIFG (0x0040u) /* USB - Function Suspend Request Interrupt Flag */ +#define RSTRIFG (0x0080u) /* USB - Function Reset Request Interrupt Flag */ + +//values of USBVECINT when USB-interrupt occured +#define USBVECINT_NONE 0x00 +#define USBVECINT_PWR_DROP 0x02 +#define USBVECINT_PLL_LOCK 0x04 +#define USBVECINT_PLL_SIGNAL 0x06 +#define USBVECINT_PLL_RANGE 0x08 +#define USBVECINT_PWR_VBUSOn 0x0A +#define USBVECINT_PWR_VBUSOff 0x0C +#define USBVECINT_USB_TIMESTAMP 0x10 +#define USBVECINT_INPUT_ENDPOINT0 0x12 +#define USBVECINT_OUTPUT_ENDPOINT0 0x14 +#define USBVECINT_RSTR 0x16 +#define USBVECINT_SUSR 0x18 +#define USBVECINT_RESR 0x1A +#define USBVECINT_SETUP_PACKET_RECEIVED 0x20 +#define USBVECINT_STPOW_PACKET_RECEIVED 0x22 +#define USBVECINT_INPUT_ENDPOINT1 0x24 +#define USBVECINT_INPUT_ENDPOINT2 0x26 +#define USBVECINT_INPUT_ENDPOINT3 0x28 +#define USBVECINT_INPUT_ENDPOINT4 0x2A +#define USBVECINT_INPUT_ENDPOINT5 0x2C +#define USBVECINT_INPUT_ENDPOINT6 0x2E +#define USBVECINT_INPUT_ENDPOINT7 0x30 +#define USBVECINT_OUTPUT_ENDPOINT1 0x32 +#define USBVECINT_OUTPUT_ENDPOINT2 0x34 +#define USBVECINT_OUTPUT_ENDPOINT3 0x36 +#define USBVECINT_OUTPUT_ENDPOINT4 0x38 +#define USBVECINT_OUTPUT_ENDPOINT5 0x3A +#define USBVECINT_OUTPUT_ENDPOINT6 0x3C +#define USBVECINT_OUTPUT_ENDPOINT7 0x3E + + +/* ========================================================================= */ +/* USB Operation Registers */ +/* ========================================================================= */ + +#define OFS_USBIEPSIZXY_7 (0x23FFu) /* Input Endpoint_7: X/Y-buffer size */ +#define OFS_USBIEPBCTY_7 (0x23FEu) /* Input Endpoint_7: Y-byte count */ +#define OFS_USBIEPBBAY_7 (0x23FDu) /* Input Endpoint_7: Y-buffer base addr. */ +//#define Spare_O (0x23FCu) /* Not used */ +//#define Spare_O (0x23FBu) /* Not used */ +#define OFS_USBIEPBCTX_7 (0x23FAu) /* Input Endpoint_7: X-byte count */ +#define OFS_USBIEPBBAX_7 (0x23F9u) /* Input Endpoint_7: X-buffer base addr. */ +#define OFS_USBIEPCNF_7 (0x23F8u) /* Input Endpoint_7: Configuration */ +#define OFS_USBIEPSIZXY_6 (0x23F7u) /* Input Endpoint_6: X/Y-buffer size */ +#define OFS_USBIEPBCTY_6 (0x23F6u) /* Input Endpoint_6: Y-byte count */ +#define OFS_USBIEPBBAY_6 (0x23F5u) /* Input Endpoint_6: Y-buffer base addr. */ +//#define Spare_O (0x23F4u) /* Not used */ +//#define Spare_O (0x23F3u) /* Not used */ +#define OFS_USBIEPBCTX_6 (0x23F2u) /* Input Endpoint_6: X-byte count */ +#define OFS_USBIEPBBAX_6 (0x23F1u) /* Input Endpoint_6: X-buffer base addr. */ +#define OFS_USBIEPCNF_6 (0x23F0u) /* Input Endpoint_6: Configuration */ +#define OFS_USBIEPSIZXY_5 (0x23EFu) /* Input Endpoint_5: X/Y-buffer size */ +#define OFS_USBIEPBCTY_5 (0x23EEu) /* Input Endpoint_5: Y-byte count */ +#define OFS_USBIEPBBAY_5 (0x23EDu) /* Input Endpoint_5: Y-buffer base addr. */ +//#define Spare_O (0x23ECu) /* Not used */ +//#define Spare_O (0x23EBu) /* Not used */ +#define OFS_USBIEPBCTX_5 (0x23EAu) /* Input Endpoint_5: X-byte count */ +#define OFS_USBIEPBBAX_5 (0x23E9u) /* Input Endpoint_5: X-buffer base addr. */ +#define OFS_USBIEPCNF_5 (0x23E8u) /* Input Endpoint_5: Configuration */ +#define OFS_USBIEPSIZXY_4 (0x23E7u) /* Input Endpoint_4: X/Y-buffer size */ +#define OFS_USBIEPBCTY_4 (0x23E6u) /* Input Endpoint_4: Y-byte count */ +#define OFS_USBIEPBBAY_4 (0x23E5u) /* Input Endpoint_4: Y-buffer base addr. */ +//#define Spare_O (0x23E4u) /* Not used */ +//#define Spare_O (0x23E3u) /* Not used */ +#define OFS_USBIEPBCTX_4 (0x23E2u) /* Input Endpoint_4: X-byte count */ +#define OFS_USBIEPBBAX_4 (0x23E1u) /* Input Endpoint_4: X-buffer base addr. */ +#define OFS_USBIEPCNF_4 (0x23E0u) /* Input Endpoint_4: Configuration */ +#define OFS_USBIEPSIZXY_3 (0x23DFu) /* Input Endpoint_3: X/Y-buffer size */ +#define OFS_USBIEPBCTY_3 (0x23DEu) /* Input Endpoint_3: Y-byte count */ +#define OFS_USBIEPBBAY_3 (0x23DDu) /* Input Endpoint_3: Y-buffer base addr. */ +//#define Spare_O (0x23DCu) /* Not used */ +//#define Spare_O (0x23DBu) /* Not used */ +#define OFS_USBIEPBCTX_3 (0x23DAu) /* Input Endpoint_3: X-byte count */ +#define OFS_USBIEPBBAX_3 (0x23D9u) /* Input Endpoint_3: X-buffer base addr. */ +#define OFS_USBIEPCNF_3 (0x23D8u) /* Input Endpoint_3: Configuration */ +#define OFS_USBIEPSIZXY_2 (0x23D7u) /* Input Endpoint_2: X/Y-buffer size */ +#define OFS_USBIEPBCTY_2 (0x23D6u) /* Input Endpoint_2: Y-byte count */ +#define OFS_USBIEPBBAY_2 (0x23D5u) /* Input Endpoint_2: Y-buffer base addr. */ +//#define Spare_O (0x23D4u) /* Not used */ +//#define Spare_O (0x23D3u) /* Not used */ +#define OFS_USBIEPBCTX_2 (0x23D2u) /* Input Endpoint_2: X-byte count */ +#define OFS_USBIEPBBAX_2 (0x23D1u) /* Input Endpoint_2: X-buffer base addr. */ +#define OFS_USBIEPCNF_2 (0x23D0u) /* Input Endpoint_2: Configuration */ +#define OFS_USBIEPSIZXY_1 (0x23CFu) /* Input Endpoint_1: X/Y-buffer size */ +#define OFS_USBIEPBCTY_1 (0x23CEu) /* Input Endpoint_1: Y-byte count */ +#define OFS_USBIEPBBAY_1 (0x23CDu) /* Input Endpoint_1: Y-buffer base addr. */ +//#define Spare_O (0x23CCu) /* Not used */ +//#define Spare_O (0x23CBu) /* Not used */ +#define OFS_USBIEPBCTX_1 (0x23CAu) /* Input Endpoint_1: X-byte count */ +#define OFS_USBIEPBBAX_1 (0x23C9u) /* Input Endpoint_1: X-buffer base addr. */ +#define OFS_USBIEPCNF_1 (0x23C8u) /* Input Endpoint_1: Configuration */ +//#define (0x23C7)_O /* */ +//#define RESERVED_O (0x1C00u) /* */ +//#define (0x23C0)_O /* */ +#define OFS_USBOEPSIZXY_7 (0x23BFu) /* Output Endpoint_7: X/Y-buffer size */ +#define OFS_USBOEPBCTY_7 (0x23BEu) /* Output Endpoint_7: Y-byte count */ +#define OFS_USBOEPBBAY_7 (0x23BDu) /* Output Endpoint_7: Y-buffer base addr. */ +//#define Spare_O (0x23BCu) /* Not used */ +//#define Spare_O (0x23BBu) /* Not used */ +#define OFS_USBOEPBCTX_7 (0x23BAu) /* Output Endpoint_7: X-byte count */ +#define OFS_USBOEPBBAX_7 (0x23B9u) /* Output Endpoint_7: X-buffer base addr. */ +#define OFS_USBOEPCNF_7 (0x23B8u) /* Output Endpoint_7: Configuration */ +#define OFS_USBOEPSIZXY_6 (0x23B7u) /* Output Endpoint_6: X/Y-buffer size */ +#define OFS_USBOEPBCTY_6 (0x23B6u) /* Output Endpoint_6: Y-byte count */ +#define OFS_USBOEPBBAY_6 (0x23B5u) /* Output Endpoint_6: Y-buffer base addr. */ +//#define Spare_O (0x23B4u) /* Not used */ +//#define Spare_O (0x23B3u) /* Not used */ +#define OFS_USBOEPBCTX_6 (0x23B2u) /* Output Endpoint_6: X-byte count */ +#define OFS_USBOEPBBAX_6 (0x23B1u) /* Output Endpoint_6: X-buffer base addr. */ +#define OFS_USBOEPCNF_6 (0x23B0u) /* Output Endpoint_6: Configuration */ +#define OFS_USBOEPSIZXY_5 (0x23AFu) /* Output Endpoint_5: X/Y-buffer size */ +#define OFS_USBOEPBCTY_5 (0x23AEu) /* Output Endpoint_5: Y-byte count */ +#define OFS_USBOEPBBAY_5 (0x23ADu) /* Output Endpoint_5: Y-buffer base addr. */ +//#define Spare_O (0x23ACu) /* Not used */ +//#define Spare_O (0x23ABu) /* Not used */ +#define OFS_USBOEPBCTX_5 (0x23AAu) /* Output Endpoint_5: X-byte count */ +#define OFS_USBOEPBBAX_5 (0x23A9u) /* Output Endpoint_5: X-buffer base addr. */ +#define OFS_USBOEPCNF_5 (0x23A8u) /* Output Endpoint_5: Configuration */ +#define OFS_USBOEPSIZXY_4 (0x23A7u) /* Output Endpoint_4: X/Y-buffer size */ +#define OFS_USBOEPBCTY_4 (0x23A6u) /* Output Endpoint_4: Y-byte count */ +#define OFS_USBOEPBBAY_4 (0x23A5u) /* Output Endpoint_4: Y-buffer base addr. */ +//#define Spare_O (0x23A4u) /* Not used */ +//#define Spare_O (0x23A3u) /* Not used */ +#define OFS_USBOEPBCTX_4 (0x23A2u) /* Output Endpoint_4: X-byte count */ +#define OFS_USBOEPBBAX_4 (0x23A1u) /* Output Endpoint_4: X-buffer base addr. */ +#define OFS_USBOEPCNF_4 (0x23A0u) /* Output Endpoint_4: Configuration */ +#define OFS_USBOEPSIZXY_3 (0x239Fu) /* Output Endpoint_3: X/Y-buffer size */ +#define OFS_USBOEPBCTY_3 (0x239Eu) /* Output Endpoint_3: Y-byte count */ +#define OFS_USBOEPBBAY_3 (0x239Du) /* Output Endpoint_3: Y-buffer base addr. */ +//#define Spare_O (0x239Cu) /* Not used */ +//#define Spare_O (0x239Bu) /* Not used */ +#define OFS_USBOEPBCTX_3 (0x239Au) /* Output Endpoint_3: X-byte count */ +#define OFS_USBOEPBBAX_3 (0x2399u) /* Output Endpoint_3: X-buffer base addr. */ +#define OFS_USBOEPCNF_3 (0x2398u) /* Output Endpoint_3: Configuration */ +#define OFS_USBOEPSIZXY_2 (0x2397u) /* Output Endpoint_2: X/Y-buffer size */ +#define OFS_USBOEPBCTY_2 (0x2396u) /* Output Endpoint_2: Y-byte count */ +#define OFS_USBOEPBBAY_2 (0x2395u) /* Output Endpoint_2: Y-buffer base addr. */ +//#define Spare_O (0x2394u) /* Not used */ +//#define Spare_O (0x2393u) /* Not used */ +#define OFS_USBOEPBCTX_2 (0x2392u) /* Output Endpoint_2: X-byte count */ +#define OFS_USBOEPBBAX_2 (0x2391u) /* Output Endpoint_2: X-buffer base addr. */ +#define OFS_USBOEPCNF_2 (0x2390u) /* Output Endpoint_2: Configuration */ +#define OFS_USBOEPSIZXY_1 (0x238Fu) /* Output Endpoint_1: X/Y-buffer size */ +#define OFS_USBOEPBCTY_1 (0x238Eu) /* Output Endpoint_1: Y-byte count */ +#define OFS_USBOEPBBAY_1 (0x238Du) /* Output Endpoint_1: Y-buffer base addr. */ +//#define Spare_O (0x238Cu) /* Not used */ +//#define Spare_O (0x238Bu) /* Not used */ +#define OFS_USBOEPBCTX_1 (0x238Au) /* Output Endpoint_1: X-byte count */ +#define OFS_USBOEPBBAX_1 (0x2389u) /* Output Endpoint_1: X-buffer base addr. */ +#define OFS_USBOEPCNF_1 (0x2388u) /* Output Endpoint_1: Configuration */ +#define OFS_USBSUBLK (0x2380u) /* Setup Packet Block */ +#define OFS_USBIEP0BUF (0x2378u) /* Input endpoint_0 buffer */ +#define OFS_USBOEP0BUF (0x2370u) /* Output endpoint_0 buffer */ +#define OFS_USBTOPBUFF (0x236Fu) /* Top of buffer space */ +// (1904 Bytes) /* Buffer space */ +#define OFS_USBSTABUFF (0x1C00u) /* Start of buffer space */ + +/* USBIEPCNF_n Control Bits */ +/* USBOEPCNF_n Control Bits */ +//#define RESERVED (0x0001u) /* USB - */ +//#define RESERVED (0x0001u) /* USB - */ +#define DBUF (0x0010u) /* USB - Double Buffer Enable */ +//#define RESERVED (0x0040u) /* USB - */ + +/* USBIEPBCNT_n Control Bits */ +/* USBOEPBCNT_n Control Bits */ +#define CNT4 (0x0010u) /* USB - Byte Count Bit 3 */ +#define CNT5 (0x0020u) /* USB - Byte Count Bit 3 */ +#define CNT6 (0x0040u) /* USB - Byte Count Bit 3 */ +#endif +/************************************************************ +* USCI Ax +************************************************************/ +#ifdef __MSP430_HAS_USCI_Ax__ /* Definition to show that Module is available */ + +#define OFS_UCAxCTLW0 (0x0000u) /* USCI Ax Control Word Register 0 */ +#define OFS_UCAxCTLW0_L OFS_UCAxCTLW0 +#define OFS_UCAxCTLW0_H OFS_UCAxCTLW0+1 +#define OFS_UCAxCTL0 (0x0001u) +#define OFS_UCAxCTL1 (0x0000u) +#define UCAxCTL1 UCAxCTLW0_L /* USCI Ax Control Register 1 */ +#define UCAxCTL0 UCAxCTLW0_H /* USCI Ax Control Register 0 */ +#define OFS_UCAxBRW (0x0006u) /* USCI Ax Baud Word Rate 0 */ +#define OFS_UCAxBRW_L OFS_UCAxBRW +#define OFS_UCAxBRW_H OFS_UCAxBRW+1 +#define OFS_UCAxBR0 (0x0006u) +#define OFS_UCAxBR1 (0x0007u) +#define UCAxBR0 UCAxBRW_L /* USCI Ax Baud Rate 0 */ +#define UCAxBR1 UCAxBRW_H /* USCI Ax Baud Rate 1 */ +#define OFS_UCAxMCTL (0x0008u) /* USCI Ax Modulation Control */ +#define OFS_UCAxSTAT (0x000Au) /* USCI Ax Status Register */ +#define OFS_UCAxRXBUF (0x000Cu) /* USCI Ax Receive Buffer */ +#define OFS_UCAxTXBUF (0x000Eu) /* USCI Ax Transmit Buffer */ +#define OFS_UCAxABCTL (0x0010u) /* USCI Ax LIN Control */ +#define OFS_UCAxIRCTL (0x0012u) /* USCI Ax IrDA Transmit Control */ +#define OFS_UCAxIRCTL_L OFS_UCAxIRCTL +#define OFS_UCAxIRCTL_H OFS_UCAxIRCTL+1 +#define OFS_UCAxIRTCTL (0x0012u) +#define OFS_UCAxIRRCTL (0x0013u) +#define UCAxIRTCTL UCAxIRCTL_L /* USCI Ax IrDA Transmit Control */ +#define UCAxIRRCTL UCAxIRCTL_H /* USCI Ax IrDA Receive Control */ +#define OFS_UCAxICTL (0x001Cu) /* USCI Ax Interrupt Enable Register */ +#define OFS_UCAxICTL_L OFS_UCAxICTL +#define OFS_UCAxICTL_H OFS_UCAxICTL+1 +#define OFS_UCAxIE (0x001Cu) +#define OFS_UCAxIFG (0x001Du) +#define UCAxIE UCAxICTL_L /* USCI Ax Interrupt Enable Register */ +#define UCAxIFG UCAxICTL_H /* USCI Ax Interrupt Flags Register */ +#define OFS_UCAxIV (0x001Eu) /* USCI Ax Interrupt Vector Register */ + +#define OFS_UCAxCTLW0__SPI (0x0000u) +#define OFS_UCAxCTLW0__SPI_L OFS_UCAxCTLW0__SPI +#define OFS_UCAxCTLW0__SPI_H OFS_UCAxCTLW0__SPI+1 +#define OFS_UCAxCTL0__SPI (0x0001u) +#define OFS_UCAxCTL1__SPI (0x0000u) +#define OFS_UCAxBRW__SPI (0x0006u) +#define OFS_UCAxBRW__SPI_L OFS_UCAxBRW__SPI +#define OFS_UCAxBRW__SPI_H OFS_UCAxBRW__SPI+1 +#define OFS_UCAxBR0__SPI (0x0006u) +#define OFS_UCAxBR1__SPI (0x0007u) +#define OFS_UCAxMCTL__SPI (0x0008u) +#define OFS_UCAxSTAT__SPI (0x000Au) +#define OFS_UCAxRXBUF__SPI (0x000Cu) +#define OFS_UCAxTXBUF__SPI (0x000Eu) +#define OFS_UCAxICTL__SPI (0x001Cu) +#define OFS_UCAxICTL__SPI_L OFS_UCAxICTL__SPI +#define OFS_UCAxICTL__SPI_H OFS_UCAxICTL__SPI+1 +#define OFS_UCAxIE__SPI (0x001Cu) +#define OFS_UCAxIFG__SPI (0x001Du) +#define OFS_UCAxIV__SPI (0x001Eu) + +#endif +/************************************************************ +* USCI Bx +************************************************************/ +#ifdef __MSP430_HAS_USCI_Bx__ /* Definition to show that Module is available */ + +#define OFS_UCBxCTLW0__SPI (0x0000u) +#define OFS_UCBxCTLW0__SPI_L OFS_UCBxCTLW0__SPI +#define OFS_UCBxCTLW0__SPI_H OFS_UCBxCTLW0__SPI+1 +#define OFS_UCBxCTL0__SPI (0x0001u) +#define OFS_UCBxCTL1__SPI (0x0000u) +#define OFS_UCBxBRW__SPI (0x0006u) +#define OFS_UCBxBRW__SPI_L OFS_UCBxBRW__SPI +#define OFS_UCBxBRW__SPI_H OFS_UCBxBRW__SPI+1 +#define OFS_UCBxBR0__SPI (0x0006u) +#define OFS_UCBxBR1__SPI (0x0007u) +#define OFS_UCBxSTAT__SPI (0x000Au) +#define OFS_UCBxRXBUF__SPI (0x000Cu) +#define OFS_UCBxTXBUF__SPI (0x000Eu) +#define OFS_UCBxICTL__SPI (0x001Cu) +#define OFS_UCBxICTL__SPI_L OFS_UCBxICTL__SPI +#define OFS_UCBxICTL__SPI_H OFS_UCBxICTL__SPI+1 +#define OFS_UCBxIE__SPI (0x001Cu) +#define OFS_UCBxIFG__SPI (0x001Du) +#define OFS_UCBxIV__SPI (0x001Eu) + +#define OFS_UCBxCTLW0 (0x0000u) /* USCI Bx Control Word Register 0 */ +#define OFS_UCBxCTLW0_L OFS_UCBxCTLW0 +#define OFS_UCBxCTLW0_H OFS_UCBxCTLW0+1 +#define OFS_UCBxCTL0 (0x0001u) +#define OFS_UCBxCTL1 (0x0000u) +#define UCBxCTL1 UCBxCTLW0_L /* USCI Bx Control Register 1 */ +#define UCBxCTL0 UCBxCTLW0_H /* USCI Bx Control Register 0 */ +#define OFS_UCBxBRW (0x0006u) /* USCI Bx Baud Word Rate 0 */ +#define OFS_UCBxBRW_L OFS_UCBxBRW +#define OFS_UCBxBRW_H OFS_UCBxBRW+1 +#define OFS_UCBxBR0 (0x0006u) +#define OFS_UCBxBR1 (0x0007u) +#define UCBxBR0 UCBxBRW_L /* USCI Bx Baud Rate 0 */ +#define UCBxBR1 UCBxBRW_H /* USCI Bx Baud Rate 1 */ +#define OFS_UCBxSTAT (0x000Au) /* USCI Bx Status Register */ +#define OFS_UCBxRXBUF (0x000Cu) /* USCI Bx Receive Buffer */ +#define OFS_UCBxTXBUF (0x000Eu) /* USCI Bx Transmit Buffer */ +#define OFS_UCBxI2COA (0x0010u) /* USCI Bx I2C Own Address */ +#define OFS_UCBxI2COA_L OFS_UCBxI2COA +#define OFS_UCBxI2COA_H OFS_UCBxI2COA+1 +#define OFS_UCBxI2CSA (0x0012u) /* USCI Bx I2C Slave Address */ +#define OFS_UCBxI2CSA_L OFS_UCBxI2CSA +#define OFS_UCBxI2CSA_H OFS_UCBxI2CSA+1 +#define OFS_UCBxICTL (0x001Cu) /* USCI Bx Interrupt Enable Register */ +#define OFS_UCBxICTL_L OFS_UCBxICTL +#define OFS_UCBxICTL_H OFS_UCBxICTL+1 +#define OFS_UCBxIE (0x001Cu) +#define OFS_UCBxIFG (0x001Du) +#define UCBxIE UCBxICTL_L /* USCI Bx Interrupt Enable Register */ +#define UCBxIFG UCBxICTL_H /* USCI Bx Interrupt Flags Register */ +#define OFS_UCBxIV (0x001Eu) /* USCI Bx Interrupt Vector Register */ + +#endif +#if (defined(__MSP430_HAS_USCI_Ax__) || defined(__MSP430_HAS_USCI_Bx__)) + +// UCAxCTL0 UART-Mode Control Bits +#define UCPEN (0x80) /* Async. Mode: Parity enable */ +#define UCPAR (0x40) /* Async. Mode: Parity 0:odd / 1:even */ +#define UCMSB (0x20) /* Async. Mode: MSB first 0:LSB / 1:MSB */ +#define UC7BIT (0x10) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */ +#define UCSPB (0x08) /* Async. Mode: Stop Bits 0:one / 1: two */ +#define UCMODE1 (0x04) /* Async. Mode: USCI Mode 1 */ +#define UCMODE0 (0x02) /* Async. Mode: USCI Mode 0 */ +#define UCSYNC (0x01) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */ + +// UCxxCTL0 SPI-Mode Control Bits +#define UCCKPH (0x80) /* Sync. Mode: Clock Phase */ +#define UCCKPL (0x40) /* Sync. Mode: Clock Polarity */ +#define UCMST (0x08) /* Sync. Mode: Master Select */ + +// UCBxCTL0 I2C-Mode Control Bits +#define UCA10 (0x80) /* 10-bit Address Mode */ +#define UCSLA10 (0x40) /* 10-bit Slave Address Mode */ +#define UCMM (0x20) /* Multi-Master Environment */ +//#define res (0x10) /* reserved */ +#define UCMODE_0 (0x00) /* Sync. Mode: USCI Mode: 0 */ +#define UCMODE_1 (0x02) /* Sync. Mode: USCI Mode: 1 */ +#define UCMODE_2 (0x04) /* Sync. Mode: USCI Mode: 2 */ +#define UCMODE_3 (0x06) /* Sync. Mode: USCI Mode: 3 */ + +// UCAxCTL1 UART-Mode Control Bits +#define UCSSEL1 (0x80) /* USCI 0 Clock Source Select 1 */ +#define UCSSEL0 (0x40) /* USCI 0 Clock Source Select 0 */ +#define UCRXEIE (0x20) /* RX Error interrupt enable */ +#define UCBRKIE (0x10) /* Break interrupt enable */ +#define UCDORM (0x08) /* Dormant (Sleep) Mode */ +#define UCTXADDR (0x04) /* Send next Data as Address */ +#define UCTXBRK (0x02) /* Send next Data as Break */ +#define UCSWRST (0x01) /* USCI Software Reset */ + +// UCxxCTL1 SPI-Mode Control Bits +//#define res (0x20) /* reserved */ +//#define res (0x10) /* reserved */ +//#define res (0x08) /* reserved */ +//#define res (0x04) /* reserved */ +//#define res (0x02) /* reserved */ + +// UCBxCTL1 I2C-Mode Control Bits +//#define res (0x20) /* reserved */ +#define UCTR (0x10) /* Transmit/Receive Select/Flag */ +#define UCTXNACK (0x08) /* Transmit NACK */ +#define UCTXSTP (0x04) /* Transmit STOP */ +#define UCTXSTT (0x02) /* Transmit START */ +#define UCSSEL_0 (0x00) /* USCI 0 Clock Source: 0 */ +#define UCSSEL_1 (0x40) /* USCI 0 Clock Source: 1 */ +#define UCSSEL_2 (0x80) /* USCI 0 Clock Source: 2 */ +#define UCSSEL_3 (0xC0) /* USCI 0 Clock Source: 3 */ +#define UCSSEL__UCLK (0x00) /* USCI 0 Clock Source: UCLK */ +#define UCSSEL__ACLK (0x40) /* USCI 0 Clock Source: ACLK */ +#define UCSSEL__SMCLK (0x80) /* USCI 0 Clock Source: SMCLK */ + +/* UCAxMCTL Control Bits */ +#define UCBRF3 (0x80) /* USCI First Stage Modulation Select 3 */ +#define UCBRF2 (0x40) /* USCI First Stage Modulation Select 2 */ +#define UCBRF1 (0x20) /* USCI First Stage Modulation Select 1 */ +#define UCBRF0 (0x10) /* USCI First Stage Modulation Select 0 */ +#define UCBRS2 (0x08) /* USCI Second Stage Modulation Select 2 */ +#define UCBRS1 (0x04) /* USCI Second Stage Modulation Select 1 */ +#define UCBRS0 (0x02) /* USCI Second Stage Modulation Select 0 */ +#define UCOS16 (0x01) /* USCI 16-times Oversampling enable */ + +#define UCBRF_0 (0x00) /* USCI First Stage Modulation: 0 */ +#define UCBRF_1 (0x10) /* USCI First Stage Modulation: 1 */ +#define UCBRF_2 (0x20) /* USCI First Stage Modulation: 2 */ +#define UCBRF_3 (0x30) /* USCI First Stage Modulation: 3 */ +#define UCBRF_4 (0x40) /* USCI First Stage Modulation: 4 */ +#define UCBRF_5 (0x50) /* USCI First Stage Modulation: 5 */ +#define UCBRF_6 (0x60) /* USCI First Stage Modulation: 6 */ +#define UCBRF_7 (0x70) /* USCI First Stage Modulation: 7 */ +#define UCBRF_8 (0x80) /* USCI First Stage Modulation: 8 */ +#define UCBRF_9 (0x90) /* USCI First Stage Modulation: 9 */ +#define UCBRF_10 (0xA0) /* USCI First Stage Modulation: A */ +#define UCBRF_11 (0xB0) /* USCI First Stage Modulation: B */ +#define UCBRF_12 (0xC0) /* USCI First Stage Modulation: C */ +#define UCBRF_13 (0xD0) /* USCI First Stage Modulation: D */ +#define UCBRF_14 (0xE0) /* USCI First Stage Modulation: E */ +#define UCBRF_15 (0xF0) /* USCI First Stage Modulation: F */ + +#define UCBRS_0 (0x00) /* USCI Second Stage Modulation: 0 */ +#define UCBRS_1 (0x02) /* USCI Second Stage Modulation: 1 */ +#define UCBRS_2 (0x04) /* USCI Second Stage Modulation: 2 */ +#define UCBRS_3 (0x06) /* USCI Second Stage Modulation: 3 */ +#define UCBRS_4 (0x08) /* USCI Second Stage Modulation: 4 */ +#define UCBRS_5 (0x0A) /* USCI Second Stage Modulation: 5 */ +#define UCBRS_6 (0x0C) /* USCI Second Stage Modulation: 6 */ +#define UCBRS_7 (0x0E) /* USCI Second Stage Modulation: 7 */ + +/* UCAxSTAT Control Bits */ +#define UCLISTEN (0x80) /* USCI Listen mode */ +#define UCFE (0x40) /* USCI Frame Error Flag */ +#define UCOE (0x20) /* USCI Overrun Error Flag */ +#define UCPE (0x10) /* USCI Parity Error Flag */ +#define UCBRK (0x08) /* USCI Break received */ +#define UCRXERR (0x04) /* USCI RX Error Flag */ +#define UCADDR (0x02) /* USCI Address received Flag */ +#define UCBUSY (0x01) /* USCI Busy Flag */ +#define UCIDLE (0x02) /* USCI Idle line detected Flag */ + +/* UCBxSTAT Control Bits */ +#define UCSCLLOW (0x40) /* SCL low */ +#define UCGC (0x20) /* General Call address received Flag */ +#define UCBBUSY (0x10) /* Bus Busy Flag */ + +/* UCAxIRTCTL Control Bits */ +#define UCIRTXPL5 (0x80) /* IRDA Transmit Pulse Length 5 */ +#define UCIRTXPL4 (0x40) /* IRDA Transmit Pulse Length 4 */ +#define UCIRTXPL3 (0x20) /* IRDA Transmit Pulse Length 3 */ +#define UCIRTXPL2 (0x10) /* IRDA Transmit Pulse Length 2 */ +#define UCIRTXPL1 (0x08) /* IRDA Transmit Pulse Length 1 */ +#define UCIRTXPL0 (0x04) /* IRDA Transmit Pulse Length 0 */ +#define UCIRTXCLK (0x02) /* IRDA Transmit Pulse Clock Select */ +#define UCIREN (0x01) /* IRDA Encoder/Decoder enable */ + +/* UCAxIRRCTL Control Bits */ +#define UCIRRXFL5 (0x80) /* IRDA Receive Filter Length 5 */ +#define UCIRRXFL4 (0x40) /* IRDA Receive Filter Length 4 */ +#define UCIRRXFL3 (0x20) /* IRDA Receive Filter Length 3 */ +#define UCIRRXFL2 (0x10) /* IRDA Receive Filter Length 2 */ +#define UCIRRXFL1 (0x08) /* IRDA Receive Filter Length 1 */ +#define UCIRRXFL0 (0x04) /* IRDA Receive Filter Length 0 */ +#define UCIRRXPL (0x02) /* IRDA Receive Input Polarity */ +#define UCIRRXFE (0x01) /* IRDA Receive Filter enable */ + +/* UCAxABCTL Control Bits */ +//#define res (0x80) /* reserved */ +//#define res (0x40) /* reserved */ +#define UCDELIM1 (0x20) /* Break Sync Delimiter 1 */ +#define UCDELIM0 (0x10) /* Break Sync Delimiter 0 */ +#define UCSTOE (0x08) /* Sync-Field Timeout error */ +#define UCBTOE (0x04) /* Break Timeout error */ +//#define res (0x02) /* reserved */ +#define UCABDEN (0x01) /* Auto Baud Rate detect enable */ + +/* UCBxI2COA Control Bits */ +#define UCGCEN (0x8000u) /* I2C General Call enable */ +#define UCOA9 (0x0200u) /* I2C Own Address 9 */ +#define UCOA8 (0x0100u) /* I2C Own Address 8 */ +#define UCOA7 (0x0080u) /* I2C Own Address 7 */ +#define UCOA6 (0x0040u) /* I2C Own Address 6 */ +#define UCOA5 (0x0020u) /* I2C Own Address 5 */ +#define UCOA4 (0x0010u) /* I2C Own Address 4 */ +#define UCOA3 (0x0008u) /* I2C Own Address 3 */ +#define UCOA2 (0x0004u) /* I2C Own Address 2 */ +#define UCOA1 (0x0002u) /* I2C Own Address 1 */ +#define UCOA0 (0x0001u) /* I2C Own Address 0 */ + +/* UCBxI2COA Control Bits */ +#define UCOA7_L (0x0080u) /* I2C Own Address 7 */ +#define UCOA6_L (0x0040u) /* I2C Own Address 6 */ +#define UCOA5_L (0x0020u) /* I2C Own Address 5 */ +#define UCOA4_L (0x0010u) /* I2C Own Address 4 */ +#define UCOA3_L (0x0008u) /* I2C Own Address 3 */ +#define UCOA2_L (0x0004u) /* I2C Own Address 2 */ +#define UCOA1_L (0x0002u) /* I2C Own Address 1 */ +#define UCOA0_L (0x0001u) /* I2C Own Address 0 */ + +/* UCBxI2COA Control Bits */ +#define UCGCEN_H (0x0080u) /* I2C General Call enable */ +#define UCOA9_H (0x0002u) /* I2C Own Address 9 */ +#define UCOA8_H (0x0001u) /* I2C Own Address 8 */ + +/* UCBxI2CSA Control Bits */ +#define UCSA9 (0x0200u) /* I2C Slave Address 9 */ +#define UCSA8 (0x0100u) /* I2C Slave Address 8 */ +#define UCSA7 (0x0080u) /* I2C Slave Address 7 */ +#define UCSA6 (0x0040u) /* I2C Slave Address 6 */ +#define UCSA5 (0x0020u) /* I2C Slave Address 5 */ +#define UCSA4 (0x0010u) /* I2C Slave Address 4 */ +#define UCSA3 (0x0008u) /* I2C Slave Address 3 */ +#define UCSA2 (0x0004u) /* I2C Slave Address 2 */ +#define UCSA1 (0x0002u) /* I2C Slave Address 1 */ +#define UCSA0 (0x0001u) /* I2C Slave Address 0 */ + +/* UCBxI2CSA Control Bits */ +#define UCSA7_L (0x0080u) /* I2C Slave Address 7 */ +#define UCSA6_L (0x0040u) /* I2C Slave Address 6 */ +#define UCSA5_L (0x0020u) /* I2C Slave Address 5 */ +#define UCSA4_L (0x0010u) /* I2C Slave Address 4 */ +#define UCSA3_L (0x0008u) /* I2C Slave Address 3 */ +#define UCSA2_L (0x0004u) /* I2C Slave Address 2 */ +#define UCSA1_L (0x0002u) /* I2C Slave Address 1 */ +#define UCSA0_L (0x0001u) /* I2C Slave Address 0 */ + +/* UCBxI2CSA Control Bits */ +#define UCSA9_H (0x0002u) /* I2C Slave Address 9 */ +#define UCSA8_H (0x0001u) /* I2C Slave Address 8 */ + +/* UCAxIE Control Bits */ +#define UCTXIE (0x0002u) /* USCI Transmit Interrupt Enable */ +#define UCRXIE (0x0001u) /* USCI Receive Interrupt Enable */ + +/* UCAxIE Control Bits */ +#define UCTXIE_L (0x0002u) /* USCI Transmit Interrupt Enable */ +#define UCRXIE_L (0x0001u) /* USCI Receive Interrupt Enable */ + +/* UCBxIE Control Bits */ +#define UCNACKIE (0x0020u) /* NACK Condition interrupt enable */ +#define UCALIE (0x0010u) /* Arbitration Lost interrupt enable */ +#define UCSTPIE (0x0008u) /* STOP Condition interrupt enable */ +#define UCSTTIE (0x0004u) /* START Condition interrupt enable */ +#define UCTXIE (0x0002u) /* USCI Transmit Interrupt Enable */ +#define UCRXIE (0x0001u) /* USCI Receive Interrupt Enable */ + +/* UCBxIE Control Bits */ +#define UCNACKIE_L (0x0020u) /* NACK Condition interrupt enable */ +#define UCALIE_L (0x0010u) /* Arbitration Lost interrupt enable */ +#define UCSTPIE_L (0x0008u) /* STOP Condition interrupt enable */ +#define UCSTTIE_L (0x0004u) /* START Condition interrupt enable */ +#define UCTXIE_L (0x0002u) /* USCI Transmit Interrupt Enable */ +#define UCRXIE_L (0x0001u) /* USCI Receive Interrupt Enable */ + +/* UCAxIFG Control Bits */ +#define UCTXIFG (0x0002u) /* USCI Transmit Interrupt Flag */ +#define UCRXIFG (0x0001u) /* USCI Receive Interrupt Flag */ + +/* UCAxIFG Control Bits */ +#define UCTXIFG_L (0x0002u) /* USCI Transmit Interrupt Flag */ +#define UCRXIFG_L (0x0001u) /* USCI Receive Interrupt Flag */ + +/* UCBxIFG Control Bits */ +#define UCNACKIFG (0x0020u) /* NAK Condition interrupt Flag */ +#define UCALIFG (0x0010u) /* Arbitration Lost interrupt Flag */ +#define UCSTPIFG (0x0008u) /* STOP Condition interrupt Flag */ +#define UCSTTIFG (0x0004u) /* START Condition interrupt Flag */ +#define UCTXIFG (0x0002u) /* USCI Transmit Interrupt Flag */ +#define UCRXIFG (0x0001u) /* USCI Receive Interrupt Flag */ + +/* UCBxIFG Control Bits */ +#define UCNACKIFG_L (0x0020u) /* NAK Condition interrupt Flag */ +#define UCALIFG_L (0x0010u) /* Arbitration Lost interrupt Flag */ +#define UCSTPIFG_L (0x0008u) /* STOP Condition interrupt Flag */ +#define UCSTTIFG_L (0x0004u) /* START Condition interrupt Flag */ +#define UCTXIFG_L (0x0002u) /* USCI Transmit Interrupt Flag */ +#define UCRXIFG_L (0x0001u) /* USCI Receive Interrupt Flag */ + +/* USCI Definitions */ +#define USCI_NONE (0x0000u) /* No Interrupt pending */ +#define USCI_UCRXIFG (0x0002u) /* USCI UCRXIFG */ +#define USCI_UCTXIFG (0x0004u) /* USCI UCTXIFG */ +#define USCI_I2C_UCALIFG (0x0002u) /* USCI I2C Mode: UCALIFG */ +#define USCI_I2C_UCNACKIFG (0x0004u) /* USCI I2C Mode: UCNACKIFG */ +#define USCI_I2C_UCSTTIFG (0x0006u) /* USCI I2C Mode: UCSTTIFG*/ +#define USCI_I2C_UCSTPIFG (0x0008u) /* USCI I2C Mode: UCSTPIFG*/ +#define USCI_I2C_UCRXIFG (0x000Au) /* USCI I2C Mode: UCRXIFG */ +#define USCI_I2C_UCTXIFG (0x000Cu) /* USCI I2C Mode: UCTXIFG */ + +#endif +/************************************************************ +* USCI Ax +************************************************************/ +#ifdef __MSP430_HAS_EUSCI_Ax__ /* Definition to show that Module is available */ + +#define OFS_UCAxCTLW0 (0x0000u) /* USCI Ax Control Word Register 0 */ +#define OFS_UCAxCTLW0_L OFS_UCAxCTLW0 +#define OFS_UCAxCTLW0_H OFS_UCAxCTLW0+1 +#define OFS_UCAxCTL0 (0x0001u) +#define OFS_UCAxCTL1 (0x0000u) +#define UCAxCTL1 UCAxCTLW0_L /* USCI Ax Control Register 1 */ +#define UCAxCTL0 UCAxCTLW0_H /* USCI Ax Control Register 0 */ +#define OFS_UCAxCTLW1 (0x0002u) /* USCI Ax Control Word Register 1 */ +#define OFS_UCAxCTLW1_L OFS_UCAxCTLW1 +#define OFS_UCAxCTLW1_H OFS_UCAxCTLW1+1 +#define OFS_UCAxBRW (0x0006u) /* USCI Ax Baud Word Rate 0 */ +#define OFS_UCAxBRW_L OFS_UCAxBRW +#define OFS_UCAxBRW_H OFS_UCAxBRW+1 +#define OFS_UCAxBR0 (0x0006u) +#define OFS_UCAxBR1 (0x0007u) +#define UCAxBR0 UCAxBRW_L /* USCI Ax Baud Rate 0 */ +#define UCAxBR1 UCAxBRW_H /* USCI Ax Baud Rate 1 */ +#define OFS_UCAxMCTLW (0x0008u) /* USCI Ax Modulation Control */ +#define OFS_UCAxMCTLW_L OFS_UCAxMCTLW +#define OFS_UCAxMCTLW_H OFS_UCAxMCTLW+1 +#define OFS_UCAxSTATW (0x000Au) /* USCI Ax Status Register */ +#define OFS_UCAxRXBUF (0x000Cu) /* USCI Ax Receive Buffer */ +#define OFS_UCAxRXBUF_L OFS_UCAxRXBUF +#define OFS_UCAxRXBUF_H OFS_UCAxRXBUF+1 +#define OFS_UCAxTXBUF (0x000Eu) /* USCI Ax Transmit Buffer */ +#define OFS_UCAxTXBUF_L OFS_UCAxTXBUF +#define OFS_UCAxTXBUF_H OFS_UCAxTXBUF+1 +#define OFS_UCAxABCTL (0x0010u) /* USCI Ax LIN Control */ +#define OFS_UCAxIRCTL (0x0012u) /* USCI Ax IrDA Transmit Control */ +#define OFS_UCAxIRCTL_L OFS_UCAxIRCTL +#define OFS_UCAxIRCTL_H OFS_UCAxIRCTL+1 +#define OFS_UCAxIRTCTL (0x0012u) +#define OFS_UCAxIRRCTL (0x0013u) +#define UCAxIRTCTL UCAxIRCTL_L /* USCI Ax IrDA Transmit Control */ +#define UCAxIRRCTL UCAxIRCTL_H /* USCI Ax IrDA Receive Control */ +#define OFS_UCAxIE (0x001Au) /* USCI Ax Interrupt Enable Register */ +#define OFS_UCAxIE_L OFS_UCAxIE +#define OFS_UCAxIE_H OFS_UCAxIE+1 +#define OFS_UCAxIFG (0x001Cu) /* USCI Ax Interrupt Flags Register */ +#define OFS_UCAxIFG_L OFS_UCAxIFG +#define OFS_UCAxIFG_H OFS_UCAxIFG+1 +#define OFS_UCAxIE__UART (0x001Au) +#define OFS_UCAxIE__UART_L OFS_UCAxIE__UART +#define OFS_UCAxIE__UART_H OFS_UCAxIE__UART+1 +#define OFS_UCAxIFG__UART (0x001Cu) +#define OFS_UCAxIFG__UART_L OFS_UCAxIFG__UART +#define OFS_UCAxIFG__UART_H OFS_UCAxIFG__UART+1 +#define OFS_UCAxIV (0x001Eu) /* USCI Ax Interrupt Vector Register */ + +#define OFS_UCAxCTLW0__SPI (0x0000u) +#define OFS_UCAxCTLW0__SPI_L OFS_UCAxCTLW0__SPI +#define OFS_UCAxCTLW0__SPI_H OFS_UCAxCTLW0__SPI+1 +#define OFS_UCAxCTL0__SPI (0x0001u) +#define OFS_UCAxCTL1__SPI (0x0000u) +#define OFS_UCAxBRW__SPI (0x0006u) +#define OFS_UCAxBRW__SPI_L OFS_UCAxBRW__SPI +#define OFS_UCAxBRW__SPI_H OFS_UCAxBRW__SPI+1 +#define OFS_UCAxBR0__SPI (0x0006u) +#define OFS_UCAxBR1__SPI (0x0007u) +#define OFS_UCAxSTATW__SPI (0x000Au) +#define OFS_UCAxRXBUF__SPI (0x000Cu) +#define OFS_UCAxRXBUF__SPI_L OFS_UCAxRXBUF__SPI +#define OFS_UCAxRXBUF__SPI_H OFS_UCAxRXBUF__SPI+1 +#define OFS_UCAxTXBUF__SPI (0x000Eu) +#define OFS_UCAxTXBUF__SPI_L OFS_UCAxTXBUF__SPI +#define OFS_UCAxTXBUF__SPI_H OFS_UCAxTXBUF__SPI+1 +#define OFS_UCAxIE__SPI (0x001Au) +#define OFS_UCAxIFG__SPI (0x001Cu) +#define OFS_UCAxIV__SPI (0x001Eu) + +#endif +/************************************************************ +* USCI Bx +************************************************************/ +#ifdef __MSP430_HAS_EUSCI_Bx__ /* Definition to show that Module is available */ + +#define OFS_UCBxCTLW0__SPI (0x0000u) +#define OFS_UCBxCTLW0__SPI_L OFS_UCBxCTLW0__SPI +#define OFS_UCBxCTLW0__SPI_H OFS_UCBxCTLW0__SPI+1 +#define OFS_UCBxCTL0__SPI (0x0001u) +#define OFS_UCBxCTL1__SPI (0x0000u) +#define OFS_UCBxBRW__SPI (0x0006u) +#define OFS_UCBxBRW__SPI_L OFS_UCBxBRW__SPI +#define OFS_UCBxBRW__SPI_H OFS_UCBxBRW__SPI+1 +#define OFS_UCBxBR0__SPI (0x0006u) +#define OFS_UCBxBR1__SPI (0x0007u) +#define OFS_UCBxSTATW__SPI (0x0008u) +#define OFS_UCBxSTATW__SPI_L OFS_UCBxSTATW__SPI +#define OFS_UCBxSTATW__SPI_H OFS_UCBxSTATW__SPI+1 +#define OFS_UCBxRXBUF__SPI (0x000Cu) +#define OFS_UCBxRXBUF__SPI_L OFS_UCBxRXBUF__SPI +#define OFS_UCBxRXBUF__SPI_H OFS_UCBxRXBUF__SPI+1 +#define OFS_UCBxTXBUF__SPI (0x000Eu) +#define OFS_UCBxTXBUF__SPI_L OFS_UCBxTXBUF__SPI +#define OFS_UCBxTXBUF__SPI_H OFS_UCBxTXBUF__SPI+1 +#define OFS_UCBxIE__SPI (0x002Au) +#define OFS_UCBxIE__SPI_L OFS_UCBxIE__SPI +#define OFS_UCBxIE__SPI_H OFS_UCBxIE__SPI+1 +#define OFS_UCBxIFG__SPI (0x002Cu) +#define OFS_UCBxIFG__SPI_L OFS_UCBxIFG__SPI +#define OFS_UCBxIFG__SPI_H OFS_UCBxIFG__SPI+1 +#define OFS_UCBxIV__SPI (0x002Eu) + +#define OFS_UCBxCTLW0 (0x0000u) /* USCI Bx Control Word Register 0 */ +#define OFS_UCBxCTLW0_L OFS_UCBxCTLW0 +#define OFS_UCBxCTLW0_H OFS_UCBxCTLW0+1 +#define OFS_UCBxCTL0 (0x0001u) +#define OFS_UCBxCTL1 (0x0000u) +#define UCBxCTL1 UCBxCTLW0_L /* USCI Bx Control Register 1 */ +#define UCBxCTL0 UCBxCTLW0_H /* USCI Bx Control Register 0 */ +#define OFS_UCBxCTLW1 (0x0002u) /* USCI Bx Control Word Register 1 */ +#define OFS_UCBxCTLW1_L OFS_UCBxCTLW1 +#define OFS_UCBxCTLW1_H OFS_UCBxCTLW1+1 +#define OFS_UCBxBRW (0x0006u) /* USCI Bx Baud Word Rate 0 */ +#define OFS_UCBxBRW_L OFS_UCBxBRW +#define OFS_UCBxBRW_H OFS_UCBxBRW+1 +#define OFS_UCBxBR0 (0x0006u) +#define OFS_UCBxBR1 (0x0007u) +#define UCBxBR0 UCBxBRW_L /* USCI Bx Baud Rate 0 */ +#define UCBxBR1 UCBxBRW_H /* USCI Bx Baud Rate 1 */ +#define OFS_UCBxSTATW (0x0008u) /* USCI Bx Status Word Register */ +#define OFS_UCBxSTATW_L OFS_UCBxSTATW +#define OFS_UCBxSTATW_H OFS_UCBxSTATW+1 +#define OFS_UCBxSTATW__I2C (0x0008u) +#define OFS_UCBxSTAT__I2C (0x0008u) +#define OFS_UCBxBCNT__I2C (0x0009u) +#define UCBxSTAT UCBxSTATW_L /* USCI Bx Status Register */ +#define UCBxBCNT UCBxSTATW_H /* USCI Bx Byte Counter Register */ +#define OFS_UCBxTBCNT (0x000Au) /* USCI Bx Byte Counter Threshold Register */ +#define OFS_UCBxTBCNT_L OFS_UCBxTBCNT +#define OFS_UCBxTBCNT_H OFS_UCBxTBCNT+1 +#define OFS_UCBxRXBUF (0x000Cu) /* USCI Bx Receive Buffer */ +#define OFS_UCBxRXBUF_L OFS_UCBxRXBUF +#define OFS_UCBxRXBUF_H OFS_UCBxRXBUF+1 +#define OFS_UCBxTXBUF (0x000Eu) /* USCI Bx Transmit Buffer */ +#define OFS_UCBxTXBUF_L OFS_UCBxTXBUF +#define OFS_UCBxTXBUF_H OFS_UCBxTXBUF+1 +#define OFS_UCBxI2COA0 (0x0014u) /* USCI Bx I2C Own Address 0 */ +#define OFS_UCBxI2COA0_L OFS_UCBxI2COA0 +#define OFS_UCBxI2COA0_H OFS_UCBxI2COA0+1 +#define OFS_UCBxI2COA1 (0x0016u) /* USCI Bx I2C Own Address 1 */ +#define OFS_UCBxI2COA1_L OFS_UCBxI2COA1 +#define OFS_UCBxI2COA1_H OFS_UCBxI2COA1+1 +#define OFS_UCBxI2COA2 (0x0018u) /* USCI Bx I2C Own Address 2 */ +#define OFS_UCBxI2COA2_L OFS_UCBxI2COA2 +#define OFS_UCBxI2COA2_H OFS_UCBxI2COA2+1 +#define OFS_UCBxI2COA3 (0x001Au) /* USCI Bx I2C Own Address 3 */ +#define OFS_UCBxI2COA3_L OFS_UCBxI2COA3 +#define OFS_UCBxI2COA3_H OFS_UCBxI2COA3+1 +#define OFS_UCBxADDRX (0x001Cu) /* USCI Bx Received Address Register */ +#define OFS_UCBxADDRX_L OFS_UCBxADDRX +#define OFS_UCBxADDRX_H OFS_UCBxADDRX+1 +#define OFS_UCBxADDMASK (0x001Eu) /* USCI Bx Address Mask Register */ +#define OFS_UCBxADDMASK_L OFS_UCBxADDMASK +#define OFS_UCBxADDMASK_H OFS_UCBxADDMASK+1 +#define OFS_UCBxI2CSA (0x0020u) /* USCI Bx I2C Slave Address */ +#define OFS_UCBxI2CSA_L OFS_UCBxI2CSA +#define OFS_UCBxI2CSA_H OFS_UCBxI2CSA+1 +#define OFS_UCBxIE (0x002Au) /* USCI Bx Interrupt Enable Register */ +#define OFS_UCBxIE_L OFS_UCBxIE +#define OFS_UCBxIE_H OFS_UCBxIE+1 +#define OFS_UCBxIFG (0x002Cu) /* USCI Bx Interrupt Flags Register */ +#define OFS_UCBxIFG_L OFS_UCBxIFG +#define OFS_UCBxIFG_H OFS_UCBxIFG+1 +#define OFS_UCBxIE__I2C (0x002Au) +#define OFS_UCBxIE__I2C_L OFS_UCBxIE__I2C +#define OFS_UCBxIE__I2C_H OFS_UCBxIE__I2C+1 +#define OFS_UCBxIFG__I2C (0x002Cu) +#define OFS_UCBxIFG__I2C_L OFS_UCBxIFG__I2C +#define OFS_UCBxIFG__I2C_H OFS_UCBxIFG__I2C+1 +#define OFS_UCBxIV (0x002Eu) /* USCI Bx Interrupt Vector Register */ + +#endif +#if (defined(__MSP430_HAS_EUSCI_Ax__) || defined(__MSP430_HAS_EUSCI_Bx__)) + +// UCAxCTLW0 UART-Mode Control Bits +#define UCPEN (0x8000u) /* Async. Mode: Parity enable */ +#define UCPAR (0x4000u) /* Async. Mode: Parity 0:odd / 1:even */ +#define UCMSB (0x2000u) /* Async. Mode: MSB first 0:LSB / 1:MSB */ +#define UC7BIT (0x1000u) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */ +#define UCSPB (0x0800u) /* Async. Mode: Stop Bits 0:one / 1: two */ +#define UCMODE1 (0x0400u) /* Async. Mode: USCI Mode 1 */ +#define UCMODE0 (0x0200u) /* Async. Mode: USCI Mode 0 */ +#define UCSYNC (0x0100u) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */ +#define UCSSEL1 (0x0080u) /* USCI 0 Clock Source Select 1 */ +#define UCSSEL0 (0x0040u) /* USCI 0 Clock Source Select 0 */ +#define UCRXEIE (0x0020u) /* RX Error interrupt enable */ +#define UCBRKIE (0x0010u) /* Break interrupt enable */ +#define UCDORM (0x0008u) /* Dormant (Sleep) Mode */ +#define UCTXADDR (0x0004u) /* Send next Data as Address */ +#define UCTXBRK (0x0002u) /* Send next Data as Break */ +#define UCSWRST (0x0001u) /* USCI Software Reset */ + +// UCAxCTLW0 UART-Mode Control Bits +#define UCSSEL1_L (0x0080u) /* USCI 0 Clock Source Select 1 */ +#define UCSSEL0_L (0x0040u) /* USCI 0 Clock Source Select 0 */ +#define UCRXEIE_L (0x0020u) /* RX Error interrupt enable */ +#define UCBRKIE_L (0x0010u) /* Break interrupt enable */ +#define UCDORM_L (0x0008u) /* Dormant (Sleep) Mode */ +#define UCTXADDR_L (0x0004u) /* Send next Data as Address */ +#define UCTXBRK_L (0x0002u) /* Send next Data as Break */ +#define UCSWRST_L (0x0001u) /* USCI Software Reset */ + +// UCAxCTLW0 UART-Mode Control Bits +#define UCPEN_H (0x0080u) /* Async. Mode: Parity enable */ +#define UCPAR_H (0x0040u) /* Async. Mode: Parity 0:odd / 1:even */ +#define UCMSB_H (0x0020u) /* Async. Mode: MSB first 0:LSB / 1:MSB */ +#define UC7BIT_H (0x0010u) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */ +#define UCSPB_H (0x0008u) /* Async. Mode: Stop Bits 0:one / 1: two */ +#define UCMODE1_H (0x0004u) /* Async. Mode: USCI Mode 1 */ +#define UCMODE0_H (0x0002u) /* Async. Mode: USCI Mode 0 */ +#define UCSYNC_H (0x0001u) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */ + +// UCxxCTLW0 SPI-Mode Control Bits +#define UCCKPH (0x8000u) /* Sync. Mode: Clock Phase */ +#define UCCKPL (0x4000u) /* Sync. Mode: Clock Polarity */ +#define UCMST (0x0800u) /* Sync. Mode: Master Select */ +//#define res (0x0020u) /* reserved */ +//#define res (0x0010u) /* reserved */ +//#define res (0x0008u) /* reserved */ +//#define res (0x0004u) /* reserved */ +#define UCSTEM (0x0002u) /* USCI STE Mode */ + +// UCBxCTLW0 I2C-Mode Control Bits +#define UCA10 (0x8000u) /* 10-bit Address Mode */ +#define UCSLA10 (0x4000u) /* 10-bit Slave Address Mode */ +#define UCMM (0x2000u) /* Multi-Master Environment */ +//#define res (0x1000u) /* reserved */ +//#define res (0x0100u) /* reserved */ +#define UCTXACK (0x0020u) /* Transmit ACK */ +#define UCTR (0x0010u) /* Transmit/Receive Select/Flag */ +#define UCTXNACK (0x0008u) /* Transmit NACK */ +#define UCTXSTP (0x0004u) /* Transmit STOP */ +#define UCTXSTT (0x0002u) /* Transmit START */ + +// UCBxCTLW0 I2C-Mode Control Bits +//#define res (0x1000u) /* reserved */ +//#define res (0x0100u) /* reserved */ +#define UCTXACK_L (0x0020u) /* Transmit ACK */ +#define UCTR_L (0x0010u) /* Transmit/Receive Select/Flag */ +#define UCTXNACK_L (0x0008u) /* Transmit NACK */ +#define UCTXSTP_L (0x0004u) /* Transmit STOP */ +#define UCTXSTT_L (0x0002u) /* Transmit START */ + +// UCBxCTLW0 I2C-Mode Control Bits +#define UCA10_H (0x0080u) /* 10-bit Address Mode */ +#define UCSLA10_H (0x0040u) /* 10-bit Slave Address Mode */ +#define UCMM_H (0x0020u) /* Multi-Master Environment */ +//#define res (0x1000u) /* reserved */ +//#define res (0x0100u) /* reserved */ + +#define UCMODE_0 (0x0000u) /* Sync. Mode: USCI Mode: 0 */ +#define UCMODE_1 (0x0200u) /* Sync. Mode: USCI Mode: 1 */ +#define UCMODE_2 (0x0400u) /* Sync. Mode: USCI Mode: 2 */ +#define UCMODE_3 (0x0600u) /* Sync. Mode: USCI Mode: 3 */ + +#define UCSSEL_0 (0x0000u) /* USCI 0 Clock Source: 0 */ +#define UCSSEL_1 (0x0040u) /* USCI 0 Clock Source: 1 */ +#define UCSSEL_2 (0x0080u) /* USCI 0 Clock Source: 2 */ +#define UCSSEL_3 (0x00C0u) /* USCI 0 Clock Source: 3 */ +#define UCSSEL__UCLK (0x0000u) /* USCI 0 Clock Source: UCLK */ +#define UCSSEL__ACLK (0x0040u) /* USCI 0 Clock Source: ACLK */ +#define UCSSEL__SMCLK (0x0080u) /* USCI 0 Clock Source: SMCLK */ + +// UCAxCTLW1 UART-Mode Control Bits +#define UCGLIT1 (0x0002u) /* USCI Deglitch Time Bit 1 */ +#define UCGLIT0 (0x0001u) /* USCI Deglitch Time Bit 0 */ + +// UCAxCTLW1 UART-Mode Control Bits +#define UCGLIT1_L (0x0002u) /* USCI Deglitch Time Bit 1 */ +#define UCGLIT0_L (0x0001u) /* USCI Deglitch Time Bit 0 */ + +// UCBxCTLW1 I2C-Mode Control Bits +#define UCETXINT (0x0100u) /* USCI Early UCTXIFG0 */ +#define UCCLTO1 (0x0080u) /* USCI Clock low timeout Bit: 1 */ +#define UCCLTO0 (0x0040u) /* USCI Clock low timeout Bit: 0 */ +#define UCSTPNACK (0x0020u) /* USCI Acknowledge Stop last byte */ +#define UCSWACK (0x0010u) /* USCI Software controlled ACK */ +#define UCASTP1 (0x0008u) /* USCI Automatic Stop condition generation Bit: 1 */ +#define UCASTP0 (0x0004u) /* USCI Automatic Stop condition generation Bit: 0 */ +#define UCGLIT1 (0x0002u) /* USCI Deglitch time Bit: 1 */ +#define UCGLIT0 (0x0001u) /* USCI Deglitch time Bit: 0 */ + +// UCBxCTLW1 I2C-Mode Control Bits +#define UCCLTO1_L (0x0080u) /* USCI Clock low timeout Bit: 1 */ +#define UCCLTO0_L (0x0040u) /* USCI Clock low timeout Bit: 0 */ +#define UCSTPNACK_L (0x0020u) /* USCI Acknowledge Stop last byte */ +#define UCSWACK_L (0x0010u) /* USCI Software controlled ACK */ +#define UCASTP1_L (0x0008u) /* USCI Automatic Stop condition generation Bit: 1 */ +#define UCASTP0_L (0x0004u) /* USCI Automatic Stop condition generation Bit: 0 */ +#define UCGLIT1_L (0x0002u) /* USCI Deglitch time Bit: 1 */ +#define UCGLIT0_L (0x0001u) /* USCI Deglitch time Bit: 0 */ + +// UCBxCTLW1 I2C-Mode Control Bits +#define UCETXINT_H (0x0001u) /* USCI Early UCTXIFG0 */ + +#define UCGLIT_0 (0x0000u) /* USCI Deglitch time: 0 */ +#define UCGLIT_1 (0x0001u) /* USCI Deglitch time: 1 */ +#define UCGLIT_2 (0x0002u) /* USCI Deglitch time: 2 */ +#define UCGLIT_3 (0x0003u) /* USCI Deglitch time: 3 */ + +#define UCASTP_0 (0x0000u) /* USCI Automatic Stop condition generation: 0 */ +#define UCASTP_1 (0x0004u) /* USCI Automatic Stop condition generation: 1 */ +#define UCASTP_2 (0x0008u) /* USCI Automatic Stop condition generation: 2 */ +#define UCASTP_3 (0x000Cu) /* USCI Automatic Stop condition generation: 3 */ + +#define UCCLTO_0 (0x0000u) /* USCI Clock low timeout: 0 */ +#define UCCLTO_1 (0x0040u) /* USCI Clock low timeout: 1 */ +#define UCCLTO_2 (0x0080u) /* USCI Clock low timeout: 2 */ +#define UCCLTO_3 (0x00C0u) /* USCI Clock low timeout: 3 */ + +/* UCAxMCTLW Control Bits */ +#define UCBRS7 (0x8000u) /* USCI Second Stage Modulation Select 7 */ +#define UCBRS6 (0x4000u) /* USCI Second Stage Modulation Select 6 */ +#define UCBRS5 (0x2000u) /* USCI Second Stage Modulation Select 5 */ +#define UCBRS4 (0x1000u) /* USCI Second Stage Modulation Select 4 */ +#define UCBRS3 (0x0800u) /* USCI Second Stage Modulation Select 3 */ +#define UCBRS2 (0x0400u) /* USCI Second Stage Modulation Select 2 */ +#define UCBRS1 (0x0200u) /* USCI Second Stage Modulation Select 1 */ +#define UCBRS0 (0x0100u) /* USCI Second Stage Modulation Select 0 */ +#define UCBRF3 (0x0080u) /* USCI First Stage Modulation Select 3 */ +#define UCBRF2 (0x0040u) /* USCI First Stage Modulation Select 2 */ +#define UCBRF1 (0x0020u) /* USCI First Stage Modulation Select 1 */ +#define UCBRF0 (0x0010u) /* USCI First Stage Modulation Select 0 */ +#define UCOS16 (0x0001u) /* USCI 16-times Oversampling enable */ + +/* UCAxMCTLW Control Bits */ +#define UCBRF3_L (0x0080u) /* USCI First Stage Modulation Select 3 */ +#define UCBRF2_L (0x0040u) /* USCI First Stage Modulation Select 2 */ +#define UCBRF1_L (0x0020u) /* USCI First Stage Modulation Select 1 */ +#define UCBRF0_L (0x0010u) /* USCI First Stage Modulation Select 0 */ +#define UCOS16_L (0x0001u) /* USCI 16-times Oversampling enable */ + +/* UCAxMCTLW Control Bits */ +#define UCBRS7_H (0x0080u) /* USCI Second Stage Modulation Select 7 */ +#define UCBRS6_H (0x0040u) /* USCI Second Stage Modulation Select 6 */ +#define UCBRS5_H (0x0020u) /* USCI Second Stage Modulation Select 5 */ +#define UCBRS4_H (0x0010u) /* USCI Second Stage Modulation Select 4 */ +#define UCBRS3_H (0x0008u) /* USCI Second Stage Modulation Select 3 */ +#define UCBRS2_H (0x0004u) /* USCI Second Stage Modulation Select 2 */ +#define UCBRS1_H (0x0002u) /* USCI Second Stage Modulation Select 1 */ +#define UCBRS0_H (0x0001u) /* USCI Second Stage Modulation Select 0 */ + +#define UCBRF_0 (0x00) /* USCI First Stage Modulation: 0 */ +#define UCBRF_1 (0x10) /* USCI First Stage Modulation: 1 */ +#define UCBRF_2 (0x20) /* USCI First Stage Modulation: 2 */ +#define UCBRF_3 (0x30) /* USCI First Stage Modulation: 3 */ +#define UCBRF_4 (0x40) /* USCI First Stage Modulation: 4 */ +#define UCBRF_5 (0x50) /* USCI First Stage Modulation: 5 */ +#define UCBRF_6 (0x60) /* USCI First Stage Modulation: 6 */ +#define UCBRF_7 (0x70) /* USCI First Stage Modulation: 7 */ +#define UCBRF_8 (0x80) /* USCI First Stage Modulation: 8 */ +#define UCBRF_9 (0x90) /* USCI First Stage Modulation: 9 */ +#define UCBRF_10 (0xA0) /* USCI First Stage Modulation: A */ +#define UCBRF_11 (0xB0) /* USCI First Stage Modulation: B */ +#define UCBRF_12 (0xC0) /* USCI First Stage Modulation: C */ +#define UCBRF_13 (0xD0) /* USCI First Stage Modulation: D */ +#define UCBRF_14 (0xE0) /* USCI First Stage Modulation: E */ +#define UCBRF_15 (0xF0) /* USCI First Stage Modulation: F */ + +/* UCAxSTATW Control Bits */ +#define UCLISTEN (0x0080u) /* USCI Listen mode */ +#define UCFE (0x0040u) /* USCI Frame Error Flag */ +#define UCOE (0x0020u) /* USCI Overrun Error Flag */ +#define UCPE (0x0010u) /* USCI Parity Error Flag */ +#define UCBRK (0x0008u) /* USCI Break received */ +#define UCRXERR (0x0004u) /* USCI RX Error Flag */ +#define UCADDR (0x0002u) /* USCI Address received Flag */ +#define UCBUSY (0x0001u) /* USCI Busy Flag */ +#define UCIDLE (0x0002u) /* USCI Idle line detected Flag */ + +/* UCBxSTATW I2C Control Bits */ +#define UCBCNT7 (0x8000u) /* USCI Byte Counter Bit 7 */ +#define UCBCNT6 (0x4000u) /* USCI Byte Counter Bit 6 */ +#define UCBCNT5 (0x2000u) /* USCI Byte Counter Bit 5 */ +#define UCBCNT4 (0x1000u) /* USCI Byte Counter Bit 4 */ +#define UCBCNT3 (0x0800u) /* USCI Byte Counter Bit 3 */ +#define UCBCNT2 (0x0400u) /* USCI Byte Counter Bit 2 */ +#define UCBCNT1 (0x0200u) /* USCI Byte Counter Bit 1 */ +#define UCBCNT0 (0x0100u) /* USCI Byte Counter Bit 0 */ +#define UCSCLLOW (0x0040u) /* SCL low */ +#define UCGC (0x0020u) /* General Call address received Flag */ +#define UCBBUSY (0x0010u) /* Bus Busy Flag */ + +/* UCBxTBCNT I2C Control Bits */ +#define UCTBCNT7 (0x0080u) /* USCI Byte Counter Bit 7 */ +#define UCTBCNT6 (0x0040u) /* USCI Byte Counter Bit 6 */ +#define UCTBCNT5 (0x0020u) /* USCI Byte Counter Bit 5 */ +#define UCTBCNT4 (0x0010u) /* USCI Byte Counter Bit 4 */ +#define UCTBCNT3 (0x0008u) /* USCI Byte Counter Bit 3 */ +#define UCTBCNT2 (0x0004u) /* USCI Byte Counter Bit 2 */ +#define UCTBCNT1 (0x0002u) /* USCI Byte Counter Bit 1 */ +#define UCTBCNT0 (0x0001u) /* USCI Byte Counter Bit 0 */ + +/* UCAxIRCTL Control Bits */ +#define UCIRRXFL5 (0x8000u) /* IRDA Receive Filter Length 5 */ +#define UCIRRXFL4 (0x4000u) /* IRDA Receive Filter Length 4 */ +#define UCIRRXFL3 (0x2000u) /* IRDA Receive Filter Length 3 */ +#define UCIRRXFL2 (0x1000u) /* IRDA Receive Filter Length 2 */ +#define UCIRRXFL1 (0x0800u) /* IRDA Receive Filter Length 1 */ +#define UCIRRXFL0 (0x0400u) /* IRDA Receive Filter Length 0 */ +#define UCIRRXPL (0x0200u) /* IRDA Receive Input Polarity */ +#define UCIRRXFE (0x0100u) /* IRDA Receive Filter enable */ +#define UCIRTXPL5 (0x0080u) /* IRDA Transmit Pulse Length 5 */ +#define UCIRTXPL4 (0x0040u) /* IRDA Transmit Pulse Length 4 */ +#define UCIRTXPL3 (0x0020u) /* IRDA Transmit Pulse Length 3 */ +#define UCIRTXPL2 (0x0010u) /* IRDA Transmit Pulse Length 2 */ +#define UCIRTXPL1 (0x0008u) /* IRDA Transmit Pulse Length 1 */ +#define UCIRTXPL0 (0x0004u) /* IRDA Transmit Pulse Length 0 */ +#define UCIRTXCLK (0x0002u) /* IRDA Transmit Pulse Clock Select */ +#define UCIREN (0x0001u) /* IRDA Encoder/Decoder enable */ + +/* UCAxIRCTL Control Bits */ +#define UCIRTXPL5_L (0x0080u) /* IRDA Transmit Pulse Length 5 */ +#define UCIRTXPL4_L (0x0040u) /* IRDA Transmit Pulse Length 4 */ +#define UCIRTXPL3_L (0x0020u) /* IRDA Transmit Pulse Length 3 */ +#define UCIRTXPL2_L (0x0010u) /* IRDA Transmit Pulse Length 2 */ +#define UCIRTXPL1_L (0x0008u) /* IRDA Transmit Pulse Length 1 */ +#define UCIRTXPL0_L (0x0004u) /* IRDA Transmit Pulse Length 0 */ +#define UCIRTXCLK_L (0x0002u) /* IRDA Transmit Pulse Clock Select */ +#define UCIREN_L (0x0001u) /* IRDA Encoder/Decoder enable */ + +/* UCAxIRCTL Control Bits */ +#define UCIRRXFL5_H (0x0080u) /* IRDA Receive Filter Length 5 */ +#define UCIRRXFL4_H (0x0040u) /* IRDA Receive Filter Length 4 */ +#define UCIRRXFL3_H (0x0020u) /* IRDA Receive Filter Length 3 */ +#define UCIRRXFL2_H (0x0010u) /* IRDA Receive Filter Length 2 */ +#define UCIRRXFL1_H (0x0008u) /* IRDA Receive Filter Length 1 */ +#define UCIRRXFL0_H (0x0004u) /* IRDA Receive Filter Length 0 */ +#define UCIRRXPL_H (0x0002u) /* IRDA Receive Input Polarity */ +#define UCIRRXFE_H (0x0001u) /* IRDA Receive Filter enable */ + +/* UCAxABCTL Control Bits */ +//#define res (0x80) /* reserved */ +//#define res (0x40) /* reserved */ +#define UCDELIM1 (0x20) /* Break Sync Delimiter 1 */ +#define UCDELIM0 (0x10) /* Break Sync Delimiter 0 */ +#define UCSTOE (0x08) /* Sync-Field Timeout error */ +#define UCBTOE (0x04) /* Break Timeout error */ +//#define res (0x02) /* reserved */ +#define UCABDEN (0x01) /* Auto Baud Rate detect enable */ + +/* UCBxI2COA0 Control Bits */ +#define UCGCEN (0x8000u) /* I2C General Call enable */ +#define UCOAEN (0x0400u) /* I2C Own Address enable */ +#define UCOA9 (0x0200u) /* I2C Own Address Bit 9 */ +#define UCOA8 (0x0100u) /* I2C Own Address Bit 8 */ +#define UCOA7 (0x0080u) /* I2C Own Address Bit 7 */ +#define UCOA6 (0x0040u) /* I2C Own Address Bit 6 */ +#define UCOA5 (0x0020u) /* I2C Own Address Bit 5 */ +#define UCOA4 (0x0010u) /* I2C Own Address Bit 4 */ +#define UCOA3 (0x0008u) /* I2C Own Address Bit 3 */ +#define UCOA2 (0x0004u) /* I2C Own Address Bit 2 */ +#define UCOA1 (0x0002u) /* I2C Own Address Bit 1 */ +#define UCOA0 (0x0001u) /* I2C Own Address Bit 0 */ + +/* UCBxI2COA0 Control Bits */ +#define UCOA7_L (0x0080u) /* I2C Own Address Bit 7 */ +#define UCOA6_L (0x0040u) /* I2C Own Address Bit 6 */ +#define UCOA5_L (0x0020u) /* I2C Own Address Bit 5 */ +#define UCOA4_L (0x0010u) /* I2C Own Address Bit 4 */ +#define UCOA3_L (0x0008u) /* I2C Own Address Bit 3 */ +#define UCOA2_L (0x0004u) /* I2C Own Address Bit 2 */ +#define UCOA1_L (0x0002u) /* I2C Own Address Bit 1 */ +#define UCOA0_L (0x0001u) /* I2C Own Address Bit 0 */ + +/* UCBxI2COA0 Control Bits */ +#define UCGCEN_H (0x0080u) /* I2C General Call enable */ +#define UCOAEN_H (0x0004u) /* I2C Own Address enable */ +#define UCOA9_H (0x0002u) /* I2C Own Address Bit 9 */ +#define UCOA8_H (0x0001u) /* I2C Own Address Bit 8 */ + +/* UCBxI2COAx Control Bits */ +#define UCOAEN (0x0400u) /* I2C Own Address enable */ +#define UCOA9 (0x0200u) /* I2C Own Address Bit 9 */ +#define UCOA8 (0x0100u) /* I2C Own Address Bit 8 */ +#define UCOA7 (0x0080u) /* I2C Own Address Bit 7 */ +#define UCOA6 (0x0040u) /* I2C Own Address Bit 6 */ +#define UCOA5 (0x0020u) /* I2C Own Address Bit 5 */ +#define UCOA4 (0x0010u) /* I2C Own Address Bit 4 */ +#define UCOA3 (0x0008u) /* I2C Own Address Bit 3 */ +#define UCOA2 (0x0004u) /* I2C Own Address Bit 2 */ +#define UCOA1 (0x0002u) /* I2C Own Address Bit 1 */ +#define UCOA0 (0x0001u) /* I2C Own Address Bit 0 */ + +/* UCBxI2COAx Control Bits */ +#define UCOA7_L (0x0080u) /* I2C Own Address Bit 7 */ +#define UCOA6_L (0x0040u) /* I2C Own Address Bit 6 */ +#define UCOA5_L (0x0020u) /* I2C Own Address Bit 5 */ +#define UCOA4_L (0x0010u) /* I2C Own Address Bit 4 */ +#define UCOA3_L (0x0008u) /* I2C Own Address Bit 3 */ +#define UCOA2_L (0x0004u) /* I2C Own Address Bit 2 */ +#define UCOA1_L (0x0002u) /* I2C Own Address Bit 1 */ +#define UCOA0_L (0x0001u) /* I2C Own Address Bit 0 */ + +/* UCBxI2COAx Control Bits */ +#define UCOAEN_H (0x0004u) /* I2C Own Address enable */ +#define UCOA9_H (0x0002u) /* I2C Own Address Bit 9 */ +#define UCOA8_H (0x0001u) /* I2C Own Address Bit 8 */ + +/* UCBxADDRX Control Bits */ +#define UCADDRX9 (0x0200u) /* I2C Receive Address Bit 9 */ +#define UCADDRX8 (0x0100u) /* I2C Receive Address Bit 8 */ +#define UCADDRX7 (0x0080u) /* I2C Receive Address Bit 7 */ +#define UCADDRX6 (0x0040u) /* I2C Receive Address Bit 6 */ +#define UCADDRX5 (0x0020u) /* I2C Receive Address Bit 5 */ +#define UCADDRX4 (0x0010u) /* I2C Receive Address Bit 4 */ +#define UCADDRX3 (0x0008u) /* I2C Receive Address Bit 3 */ +#define UCADDRX2 (0x0004u) /* I2C Receive Address Bit 2 */ +#define UCADDRX1 (0x0002u) /* I2C Receive Address Bit 1 */ +#define UCADDRX0 (0x0001u) /* I2C Receive Address Bit 0 */ + +/* UCBxADDRX Control Bits */ +#define UCADDRX7_L (0x0080u) /* I2C Receive Address Bit 7 */ +#define UCADDRX6_L (0x0040u) /* I2C Receive Address Bit 6 */ +#define UCADDRX5_L (0x0020u) /* I2C Receive Address Bit 5 */ +#define UCADDRX4_L (0x0010u) /* I2C Receive Address Bit 4 */ +#define UCADDRX3_L (0x0008u) /* I2C Receive Address Bit 3 */ +#define UCADDRX2_L (0x0004u) /* I2C Receive Address Bit 2 */ +#define UCADDRX1_L (0x0002u) /* I2C Receive Address Bit 1 */ +#define UCADDRX0_L (0x0001u) /* I2C Receive Address Bit 0 */ + +/* UCBxADDRX Control Bits */ +#define UCADDRX9_H (0x0002u) /* I2C Receive Address Bit 9 */ +#define UCADDRX8_H (0x0001u) /* I2C Receive Address Bit 8 */ + +/* UCBxADDMASK Control Bits */ +#define UCADDMASK9 (0x0200u) /* I2C Address Mask Bit 9 */ +#define UCADDMASK8 (0x0100u) /* I2C Address Mask Bit 8 */ +#define UCADDMASK7 (0x0080u) /* I2C Address Mask Bit 7 */ +#define UCADDMASK6 (0x0040u) /* I2C Address Mask Bit 6 */ +#define UCADDMASK5 (0x0020u) /* I2C Address Mask Bit 5 */ +#define UCADDMASK4 (0x0010u) /* I2C Address Mask Bit 4 */ +#define UCADDMASK3 (0x0008u) /* I2C Address Mask Bit 3 */ +#define UCADDMASK2 (0x0004u) /* I2C Address Mask Bit 2 */ +#define UCADDMASK1 (0x0002u) /* I2C Address Mask Bit 1 */ +#define UCADDMASK0 (0x0001u) /* I2C Address Mask Bit 0 */ + +/* UCBxADDMASK Control Bits */ +#define UCADDMASK7_L (0x0080u) /* I2C Address Mask Bit 7 */ +#define UCADDMASK6_L (0x0040u) /* I2C Address Mask Bit 6 */ +#define UCADDMASK5_L (0x0020u) /* I2C Address Mask Bit 5 */ +#define UCADDMASK4_L (0x0010u) /* I2C Address Mask Bit 4 */ +#define UCADDMASK3_L (0x0008u) /* I2C Address Mask Bit 3 */ +#define UCADDMASK2_L (0x0004u) /* I2C Address Mask Bit 2 */ +#define UCADDMASK1_L (0x0002u) /* I2C Address Mask Bit 1 */ +#define UCADDMASK0_L (0x0001u) /* I2C Address Mask Bit 0 */ + +/* UCBxADDMASK Control Bits */ +#define UCADDMASK9_H (0x0002u) /* I2C Address Mask Bit 9 */ +#define UCADDMASK8_H (0x0001u) /* I2C Address Mask Bit 8 */ + +/* UCBxI2CSA Control Bits */ +#define UCSA9 (0x0200u) /* I2C Slave Address Bit 9 */ +#define UCSA8 (0x0100u) /* I2C Slave Address Bit 8 */ +#define UCSA7 (0x0080u) /* I2C Slave Address Bit 7 */ +#define UCSA6 (0x0040u) /* I2C Slave Address Bit 6 */ +#define UCSA5 (0x0020u) /* I2C Slave Address Bit 5 */ +#define UCSA4 (0x0010u) /* I2C Slave Address Bit 4 */ +#define UCSA3 (0x0008u) /* I2C Slave Address Bit 3 */ +#define UCSA2 (0x0004u) /* I2C Slave Address Bit 2 */ +#define UCSA1 (0x0002u) /* I2C Slave Address Bit 1 */ +#define UCSA0 (0x0001u) /* I2C Slave Address Bit 0 */ + +/* UCBxI2CSA Control Bits */ +#define UCSA7_L (0x0080u) /* I2C Slave Address Bit 7 */ +#define UCSA6_L (0x0040u) /* I2C Slave Address Bit 6 */ +#define UCSA5_L (0x0020u) /* I2C Slave Address Bit 5 */ +#define UCSA4_L (0x0010u) /* I2C Slave Address Bit 4 */ +#define UCSA3_L (0x0008u) /* I2C Slave Address Bit 3 */ +#define UCSA2_L (0x0004u) /* I2C Slave Address Bit 2 */ +#define UCSA1_L (0x0002u) /* I2C Slave Address Bit 1 */ +#define UCSA0_L (0x0001u) /* I2C Slave Address Bit 0 */ + +/* UCBxI2CSA Control Bits */ +#define UCSA9_H (0x0002u) /* I2C Slave Address Bit 9 */ +#define UCSA8_H (0x0001u) /* I2C Slave Address Bit 8 */ + +/* UCAxIE UART Control Bits */ +#define UCTXCPTIE (0x0008u) /* UART Transmit Complete Interrupt Enable */ +#define UCSTTIE (0x0004u) /* UART Start Bit Interrupt Enalble */ +#define UCTXIE (0x0002u) /* UART Transmit Interrupt Enable */ +#define UCRXIE (0x0001u) /* UART Receive Interrupt Enable */ + +/* UCAxIE/UCBxIE SPI Control Bits */ + +/* UCBxIE I2C Control Bits */ +#define UCBIT9IE (0x4000u) /* I2C Bit 9 Position Interrupt Enable 3 */ +#define UCTXIE3 (0x2000u) /* I2C Transmit Interrupt Enable 3 */ +#define UCRXIE3 (0x1000u) /* I2C Receive Interrupt Enable 3 */ +#define UCTXIE2 (0x0800u) /* I2C Transmit Interrupt Enable 2 */ +#define UCRXIE2 (0x0400u) /* I2C Receive Interrupt Enable 2 */ +#define UCTXIE1 (0x0200u) /* I2C Transmit Interrupt Enable 1 */ +#define UCRXIE1 (0x0100u) /* I2C Receive Interrupt Enable 1 */ +#define UCCLTOIE (0x0080u) /* I2C Clock Low Timeout interrupt enable */ +#define UCBCNTIE (0x0040u) /* I2C Automatic stop assertion interrupt enable */ +#define UCNACKIE (0x0020u) /* I2C NACK Condition interrupt enable */ +#define UCALIE (0x0010u) /* I2C Arbitration Lost interrupt enable */ +#define UCSTPIE (0x0008u) /* I2C STOP Condition interrupt enable */ +#define UCSTTIE (0x0004u) /* I2C START Condition interrupt enable */ +#define UCTXIE0 (0x0002u) /* I2C Transmit Interrupt Enable 0 */ +#define UCRXIE0 (0x0001u) /* I2C Receive Interrupt Enable 0 */ + +/* UCAxIFG UART Control Bits */ +#define UCTXCPTIFG (0x0008u) /* UART Transmit Complete Interrupt Flag */ +#define UCSTTIFG (0x0004u) /* UART Start Bit Interrupt Flag */ +#define UCTXIFG (0x0002u) /* UART Transmit Interrupt Flag */ +#define UCRXIFG (0x0001u) /* UART Receive Interrupt Flag */ + +/* UCAxIFG/UCBxIFG SPI Control Bits */ +#define UCTXIFG (0x0002u) /* SPI Transmit Interrupt Flag */ +#define UCRXIFG (0x0001u) /* SPI Receive Interrupt Flag */ + +/* UCBxIFG Control Bits */ +#define UCBIT9IFG (0x4000u) /* I2C Bit 9 Possition Interrupt Flag 3 */ +#define UCTXIFG3 (0x2000u) /* I2C Transmit Interrupt Flag 3 */ +#define UCRXIFG3 (0x1000u) /* I2C Receive Interrupt Flag 3 */ +#define UCTXIFG2 (0x0800u) /* I2C Transmit Interrupt Flag 2 */ +#define UCRXIFG2 (0x0400u) /* I2C Receive Interrupt Flag 2 */ +#define UCTXIFG1 (0x0200u) /* I2C Transmit Interrupt Flag 1 */ +#define UCRXIFG1 (0x0100u) /* I2C Receive Interrupt Flag 1 */ +#define UCCLTOIFG (0x0080u) /* I2C Clock low Timeout interrupt Flag */ +#define UCBCNTIFG (0x0040u) /* I2C Byte counter interrupt flag */ +#define UCNACKIFG (0x0020u) /* I2C NACK Condition interrupt Flag */ +#define UCALIFG (0x0010u) /* I2C Arbitration Lost interrupt Flag */ +#define UCSTPIFG (0x0008u) /* I2C STOP Condition interrupt Flag */ +#define UCSTTIFG (0x0004u) /* I2C START Condition interrupt Flag */ +#define UCTXIFG0 (0x0002u) /* I2C Transmit Interrupt Flag 0 */ +#define UCRXIFG0 (0x0001u) /* I2C Receive Interrupt Flag 0 */ + +/* USCI UART Definitions */ +#define USCI_NONE (0x0000u) /* No Interrupt pending */ +#define USCI_UART_UCRXIFG (0x0002u) /* USCI UCRXIFG */ +#define USCI_UART_UCTXIFG (0x0004u) /* USCI UCTXIFG */ +#define USCI_UART_UCSTTIFG (0x0006u) /* USCI UCSTTIFG */ +#define USCI_UART_UCTXCPTIFG (0x0008u) /* USCI UCTXCPTIFG */ + +/* USCI SPI Definitions */ +#define USCI_SPI_UCRXIFG (0x0002u) /* USCI UCRXIFG */ +#define USCI_SPI_UCTXIFG (0x0004u) /* USCI UCTXIFG */ + +/* USCI I2C Definitions */ +#define USCI_I2C_UCALIFG (0x0002u) /* USCI I2C Mode: UCALIFG */ +#define USCI_I2C_UCNACKIFG (0x0004u) /* USCI I2C Mode: UCNACKIFG */ +#define USCI_I2C_UCSTTIFG (0x0006u) /* USCI I2C Mode: UCSTTIFG*/ +#define USCI_I2C_UCSTPIFG (0x0008u) /* USCI I2C Mode: UCSTPIFG*/ +#define USCI_I2C_UCRXIFG3 (0x000Au) /* USCI I2C Mode: UCRXIFG3 */ +#define USCI_I2C_UCTXIFG3 (0x000Cu) /* USCI I2C Mode: UCTXIFG3 */ +#define USCI_I2C_UCRXIFG2 (0x000Eu) /* USCI I2C Mode: UCRXIFG2 */ +#define USCI_I2C_UCTXIFG2 (0x0010u) /* USCI I2C Mode: UCTXIFG2 */ +#define USCI_I2C_UCRXIFG1 (0x0012u) /* USCI I2C Mode: UCRXIFG1 */ +#define USCI_I2C_UCTXIFG1 (0x0014u) /* USCI I2C Mode: UCTXIFG1 */ +#define USCI_I2C_UCRXIFG0 (0x0016u) /* USCI I2C Mode: UCRXIFG0 */ +#define USCI_I2C_UCTXIFG0 (0x0018u) /* USCI I2C Mode: UCTXIFG0 */ +#define USCI_I2C_UCBCNTIFG (0x001Au) /* USCI I2C Mode: UCBCNTIFG */ +#define USCI_I2C_UCCLTOIFG (0x001Cu) /* USCI I2C Mode: UCCLTOIFG */ +#define USCI_I2C_UCBIT9IFG (0x001Eu) /* USCI I2C Mode: UCBIT9IFG */ + +#endif +/************************************************************ +* WATCHDOG TIMER A +************************************************************/ +#ifdef __MSP430_HAS_WDT_A__ /* Definition to show that Module is available */ + +#define OFS_WDTCTL (0x000Cu) /* Watchdog Timer Control */ +#define OFS_WDTCTL_L OFS_WDTCTL +#define OFS_WDTCTL_H OFS_WDTCTL+1 +/* The bit names have been prefixed with "WDT" */ +/* WDTCTL Control Bits */ +#define WDTIS0 (0x0001u) /* WDT - Timer Interval Select 0 */ +#define WDTIS1 (0x0002u) /* WDT - Timer Interval Select 1 */ +#define WDTIS2 (0x0004u) /* WDT - Timer Interval Select 2 */ +#define WDTCNTCL (0x0008u) /* WDT - Timer Clear */ +#define WDTTMSEL (0x0010u) /* WDT - Timer Mode Select */ +#define WDTSSEL0 (0x0020u) /* WDT - Timer Clock Source Select 0 */ +#define WDTSSEL1 (0x0040u) /* WDT - Timer Clock Source Select 1 */ +#define WDTHOLD (0x0080u) /* WDT - Timer hold */ + +/* WDTCTL Control Bits */ +#define WDTIS0_L (0x0001u) /* WDT - Timer Interval Select 0 */ +#define WDTIS1_L (0x0002u) /* WDT - Timer Interval Select 1 */ +#define WDTIS2_L (0x0004u) /* WDT - Timer Interval Select 2 */ +#define WDTCNTCL_L (0x0008u) /* WDT - Timer Clear */ +#define WDTTMSEL_L (0x0010u) /* WDT - Timer Mode Select */ +#define WDTSSEL0_L (0x0020u) /* WDT - Timer Clock Source Select 0 */ +#define WDTSSEL1_L (0x0040u) /* WDT - Timer Clock Source Select 1 */ +#define WDTHOLD_L (0x0080u) /* WDT - Timer hold */ + +#define WDTPW (0x5A00u) + +#define WDTIS_0 (0*0x0001u) /* WDT - Timer Interval Select: /2G */ +#define WDTIS_1 (1*0x0001u) /* WDT - Timer Interval Select: /128M */ +#define WDTIS_2 (2*0x0001u) /* WDT - Timer Interval Select: /8192k */ +#define WDTIS_3 (3*0x0001u) /* WDT - Timer Interval Select: /512k */ +#define WDTIS_4 (4*0x0001u) /* WDT - Timer Interval Select: /32k */ +#define WDTIS_5 (5*0x0001u) /* WDT - Timer Interval Select: /8192 */ +#define WDTIS_6 (6*0x0001u) /* WDT - Timer Interval Select: /512 */ +#define WDTIS_7 (7*0x0001u) /* WDT - Timer Interval Select: /64 */ +#define WDTIS__2G (0*0x0001u) /* WDT - Timer Interval Select: /2G */ +#define WDTIS__128M (1*0x0001u) /* WDT - Timer Interval Select: /128M */ +#define WDTIS__8192K (2*0x0001u) /* WDT - Timer Interval Select: /8192k */ +#define WDTIS__512K (3*0x0001u) /* WDT - Timer Interval Select: /512k */ +#define WDTIS__32K (4*0x0001u) /* WDT - Timer Interval Select: /32k */ +#define WDTIS__8192 (5*0x0001u) /* WDT - Timer Interval Select: /8192 */ +#define WDTIS__512 (6*0x0001u) /* WDT - Timer Interval Select: /512 */ +#define WDTIS__64 (7*0x0001u) /* WDT - Timer Interval Select: /64 */ + +#define WDTSSEL_0 (0*0x0020u) /* WDT - Timer Clock Source Select: SMCLK */ +#define WDTSSEL_1 (1*0x0020u) /* WDT - Timer Clock Source Select: ACLK */ +#define WDTSSEL_2 (2*0x0020u) /* WDT - Timer Clock Source Select: VLO_CLK */ +#define WDTSSEL_3 (3*0x0020u) /* WDT - Timer Clock Source Select: reserved */ +#define WDTSSEL__SMCLK (0*0x0020u) /* WDT - Timer Clock Source Select: SMCLK */ +#define WDTSSEL__ACLK (1*0x0020u) /* WDT - Timer Clock Source Select: ACLK */ +#define WDTSSEL__VLO (2*0x0020u) /* WDT - Timer Clock Source Select: VLO_CLK */ + +/* WDT-interval times [1ms] coded with Bits 0-2 */ +/* WDT is clocked by fSMCLK (assumed 1MHz) */ +#define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2) /* 32ms interval (default) */ +#define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */ +#define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */ +#define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */ +/* WDT is clocked by fACLK (assumed 32KHz) */ +#define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0) /* 1000ms " */ +#define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS0) /* 250ms " */ +#define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1) /* 16ms " */ +#define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1+WDTIS0) /* 1.9ms " */ +/* Watchdog mode -> reset after expired time */ +/* WDT is clocked by fSMCLK (assumed 1MHz) */ +#define WDT_MRST_32 (WDTPW+WDTCNTCL+WDTIS2) /* 32ms interval (default) */ +#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */ +#define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */ +#define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */ +/* WDT is clocked by fACLK (assumed 32KHz) */ +#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2) /* 1000ms " */ +#define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS0) /* 250ms " */ +#define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1) /* 16ms " */ +#define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1+WDTIS0) /* 1.9ms " */ + +#endif + +/************************************************************ +* TLV Descriptors +************************************************************/ +#define __MSP430_HAS_TLV__ /* Definition to show that Module is available */ +#define TLV_BASE __MSP430_BASEADDRESS_TLV__ + +#define TLV_START (0x1A08u) /* Start Address of the TLV structure */ +#define TLV_END (0x1AFFu) /* End Address of the TLV structure */ + +#define TLV_LDTAG (0x01) /* Legacy descriptor (1xx, 2xx, 4xx families) */ +#define TLV_PDTAG (0x02) /* Peripheral discovery descriptor */ +#define TLV_Reserved3 (0x03) /* Future usage */ +#define TLV_Reserved4 (0x04) /* Future usage */ +#define TLV_BLANK (0x05) /* Blank descriptor */ +#define TLV_Reserved6 (0x06) /* Future usage */ +#define TLV_Reserved7 (0x07) /* Serial Number */ +#define TLV_DIERECORD (0x08) /* Die Record */ +#define TLV_ADCCAL (0x11) /* ADC12 calibration */ +#define TLV_ADC12CAL (0x11) /* ADC12 calibration */ +#define TLV_REFCAL (0x12) /* REF calibration */ +#define TLV_ADC10CAL (0x13) /* ADC10 calibration */ +#define TLV_TIMERDCAL (0x15) /* TIMER_D calibration */ +#define TLV_TAGEXT (0xFE) /* Tag extender */ +#define TLV_TAGEND (0xFF) /* Tag End of Table */ + +/************************************************************ +* Interrupt Vectors (offset from 0xFF80) +************************************************************/ + + +/************************************************************ +* End of Modules +************************************************************/ +#pragma language=default + +#endif /* #ifndef __msp430F5XX_F6XXGENERIC */ + diff --git a/source/driverlib/MSP430F5xx_6xx/deprecated/dma.c b/source/driverlib/MSP430F5xx_6xx/deprecated/dma.c new file mode 100644 index 0000000..f9da677 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/deprecated/dma.c @@ -0,0 +1,769 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// dma.c - Driver for the dma Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup dma_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef DRIVERLIB_LEGACY_MODE + +#if defined(__MSP430_HAS_DMAX_3__) || defined(__MSP430_HAS_DMAX_6__) +#include "dma.h" + +#include + +//***************************************************************************** +// +//! \brief DEPRECATED - Initializes the specified DMA channel. +//! +//! This function initializes the specified DMA channel. Upon successful +//! completion of initialization of the selected channel the control registers +//! will be cleared and the given variables will be set. Please note, if +//! transfers have been enabled with the enableTransfers() function, then a +//! call to disableTransfers() is necessary before re-initialization. Also +//! note, that the trigger sources are device dependent and can be found in the +//! device family data sheet. The amount of DMA channels available are also +//! device specific. +//! +//! \param baseAddress is the base address of the DMA module. +//! \param channelSelect is the specified channel to initialize. +//! Valid values are: +//! - \b DMA_CHANNEL_0 +//! - \b DMA_CHANNEL_1 +//! - \b DMA_CHANNEL_2 +//! - \b DMA_CHANNEL_3 +//! - \b DMA_CHANNEL_4 +//! - \b DMA_CHANNEL_5 +//! - \b DMA_CHANNEL_6 +//! - \b DMA_CHANNEL_7 +//! \param transferModeSelect is the transfer mode of the selected channel. +//! Valid values are: +//! - \b DMA_TRANSFER_SINGLE [Default] - Single transfer, transfers +//! disabled after transferAmount of transfers. +//! - \b DMA_TRANSFER_BLOCK - Multiple transfers of transferAmount, +//! transfers disabled once finished. +//! - \b DMA_TRANSFER_BURSTBLOCK - Multiple transfers of transferAmount +//! interleaved with CPU activity, transfers disabled once finished. +//! - \b DMA_TRANSFER_REPEATED_SINGLE - Repeated single transfer by +//! trigger. +//! - \b DMA_TRANSFER_REPEATED_BLOCK - Multiple transfers of +//! transferAmount by trigger. +//! - \b DMA_TRANSFER_REPEATED_BURSTBLOCK - Multiple transfers of +//! transferAmount by trigger interleaved with CPU activity. +//! \n Modified bits are \b DMADT of \b DMAxCTL register. +//! \param transferSize is the amount of transfers to complete in a block +//! transfer mode, as well as how many transfers to complete before the +//! interrupt flag is set. Valid value is between 1-65535, if 0, no +//! transfers will occur. +//! \n Modified bits are \b DMAxSZ of \b DMAxSZ register. +//! \param triggerSourceSelect is the source that will trigger the start of +//! each transfer, note that the sources are device specific. +//! Valid values are: +//! - \b DMA_TRIGGERSOURCE_0 [Default] +//! - \b DMA_TRIGGERSOURCE_1 +//! - \b DMA_TRIGGERSOURCE_2 +//! - \b DMA_TRIGGERSOURCE_3 +//! - \b DMA_TRIGGERSOURCE_4 +//! - \b DMA_TRIGGERSOURCE_5 +//! - \b DMA_TRIGGERSOURCE_6 +//! - \b DMA_TRIGGERSOURCE_7 +//! - \b DMA_TRIGGERSOURCE_8 +//! - \b DMA_TRIGGERSOURCE_9 +//! - \b DMA_TRIGGERSOURCE_10 +//! - \b DMA_TRIGGERSOURCE_11 +//! - \b DMA_TRIGGERSOURCE_12 +//! - \b DMA_TRIGGERSOURCE_13 +//! - \b DMA_TRIGGERSOURCE_14 +//! - \b DMA_TRIGGERSOURCE_15 +//! - \b DMA_TRIGGERSOURCE_16 +//! - \b DMA_TRIGGERSOURCE_17 +//! - \b DMA_TRIGGERSOURCE_18 +//! - \b DMA_TRIGGERSOURCE_19 +//! - \b DMA_TRIGGERSOURCE_20 +//! - \b DMA_TRIGGERSOURCE_21 +//! - \b DMA_TRIGGERSOURCE_22 +//! - \b DMA_TRIGGERSOURCE_23 +//! - \b DMA_TRIGGERSOURCE_24 +//! - \b DMA_TRIGGERSOURCE_25 +//! - \b DMA_TRIGGERSOURCE_26 +//! - \b DMA_TRIGGERSOURCE_27 +//! - \b DMA_TRIGGERSOURCE_28 +//! - \b DMA_TRIGGERSOURCE_29 +//! - \b DMA_TRIGGERSOURCE_30 +//! - \b DMA_TRIGGERSOURCE_31 +//! \n Modified bits are \b DMAxTSEL of \b DMACTLx register. +//! \param transferUnitSelect is the specified size of transfers. +//! Valid values are: +//! - \b DMA_SIZE_SRCWORD_DSTWORD [Default] +//! - \b DMA_SIZE_SRCBYTE_DSTWORD +//! - \b DMA_SIZE_SRCWORD_DSTBYTE +//! - \b DMA_SIZE_SRCBYTE_DSTBYTE +//! \n Modified bits are \b DMASRCBYTE and \b DMADSTBYTE of \b DMAxCTL +//! register. +//! \param triggerTypeSelect is the type of trigger that the trigger signal +//! needs to be to start a transfer. +//! Valid values are: +//! - \b DMA_TRIGGER_RISINGEDGE [Default] +//! - \b DMA_TRIGGER_HIGH - A trigger would be a high signal from the +//! trigger source, to be held high through the length of the +//! transfer(s). +//! \n Modified bits are \b DMALEVEL of \b DMAxCTL register. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the initialization process. +// +//***************************************************************************** +bool DMA_init (uint16_t baseAddress, + uint8_t channelSelect, + uint16_t transferModeSelect, + uint16_t transferSize, + uint8_t triggerSourceSelect, + uint8_t transferUnitSelect, + uint8_t triggerTypeSelect) +{ + DMA_initializeParam param = {0}; + param.channelSelect = channelSelect; + param.transferModeSelect = transferModeSelect; + param.transferSize = transferSize; + param.triggerSourceSelect = triggerSourceSelect; + param.transferUnitSelect = transferUnitSelect; + param.triggerTypeSelect = triggerTypeSelect; + + return DMA_initialize(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Initializes the specified DMA channel. +//! +//! This function initializes the specified DMA channel. Upon successful +//! completion of initialization of the selected channel the control registers +//! will be cleared and the given variables will be set. Please note, if +//! transfers have been enabled with the enableTransfers() function, then a +//! call to disableTransfers() is necessary before re-initialization. Also +//! note, that the trigger sources are device dependent and can be found in the +//! device family data sheet. The amount of DMA channels available are also +//! device specific. +//! +//! \param baseAddress is the base address of the DMA module. +//! \param param is the pointer to struct for initialization. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the initialization process. +// +//***************************************************************************** +bool DMA_initialize(uint16_t baseAddress, DMA_initializeParam *param) +{ + assert(param != 0); + assert(param->channelSelect <= DMA_CHANNEL_7); + assert(param->transferModeSelect <= DMA_TRANSFER_REPEATED_BURSTBLOCK); + assert(param->triggerSourceSelect <= DMA_TRIGGERSOURCE_31); + assert(param->transferUnitSelect <= DMA_SIZE_SRCBYTE_DSTBYTE); + assert(param->triggerTypeSelect <= DMA_TRIGGER_HIGH); + + bool retVal = STATUS_SUCCESS; + uint8_t triggerOffset = (param->channelSelect >> 4); + + //Reset and Set DMA Control 0 Register + HWREG16(baseAddress + param->channelSelect + OFS_DMA0CTL) = + param->transferModeSelect //Set Transfer Mode + + param->transferUnitSelect //Set Transfer Unit Size + + param->triggerTypeSelect; //Set Trigger Type + + //Set Transfer Size Amount + HWREG16(baseAddress + param->channelSelect + OFS_DMA0SZ) = param->transferSize; + + if (triggerOffset & 0x01){ //Odd Channel + HWREG16(baseAddress + (triggerOffset & 0x0E)) &= 0x00FF; //Reset Trigger Select + HWREG16(baseAddress + + (triggerOffset & 0x0E)) |= (param->triggerSourceSelect << 8); + } else { //Even Channel + HWREG16(baseAddress + (triggerOffset & 0x0E)) &= 0xFF00; //Reset Trigger Select + HWREG16(baseAddress + (triggerOffset & 0x0E)) |= param->triggerSourceSelect; + } + + return (retVal) ; +} +//***************************************************************************** +// +//! \brief Sets the specified amount of transfers for the selected DMA channel. +//! +//! This function sets the specified amount of transfers for the selected DMA +//! channel without having to reinitialize the DMA channel. +//! +//! \param baseAddress is the base address of the DMA module. +//! \param channelSelect is the specified channel to set source address +//! direction for. +//! Valid values are: +//! - \b DMA_CHANNEL_0 +//! - \b DMA_CHANNEL_1 +//! - \b DMA_CHANNEL_2 +//! - \b DMA_CHANNEL_3 +//! - \b DMA_CHANNEL_4 +//! - \b DMA_CHANNEL_5 +//! - \b DMA_CHANNEL_6 +//! - \b DMA_CHANNEL_7 +//! \param transferSize is the amount of transfers to complete in a block +//! transfer mode, as well as how many transfers to complete before the +//! interrupt flag is set. Valid value is between 1-65535, if 0, no +//! transfers will occur. +//! \n Modified bits are \b DMAxSZ of \b DMAxSZ register. +//! +//! \return None +// +//***************************************************************************** +void DMA_setTransferSize (uint16_t baseAddress, + uint8_t channelSelect, + uint16_t transferSize) +{ + //Set Transfer Size Amount + HWREG16(baseAddress + channelSelect + OFS_DMA0SZ) = transferSize; +} + +//***************************************************************************** +// +//! \brief Sets source address and the direction that the source address will +//! move after a transfer. +//! +//! This function sets the source address and the direction that the source +//! address will move after a transfer is complete. It may be incremented, +//! decremented or unchanged. +//! +//! \param baseAddress is the base address of the DMA module. +//! \param channelSelect is the specified channel to set source address +//! direction for. +//! Valid values are: +//! - \b DMA_CHANNEL_0 +//! - \b DMA_CHANNEL_1 +//! - \b DMA_CHANNEL_2 +//! - \b DMA_CHANNEL_3 +//! - \b DMA_CHANNEL_4 +//! - \b DMA_CHANNEL_5 +//! - \b DMA_CHANNEL_6 +//! - \b DMA_CHANNEL_7 +//! \param srcAddress is the address of where the data will be transferred +//! from. +//! \n Modified bits are \b DMAxSA of \b DMAxSA register. +//! \param directionSelect is the specified direction of the source address +//! after a transfer. +//! Valid values are: +//! - \b DMA_DIRECTION_UNCHANGED +//! - \b DMA_DIRECTION_DECREMENT +//! - \b DMA_DIRECTION_INCREMENT +//! \n Modified bits are \b DMASRCINCR of \b DMAxCTL register. +//! +//! \return None +// +//***************************************************************************** +void DMA_setSrcAddress (uint16_t baseAddress, + uint8_t channelSelect, + uint32_t srcAddress, + uint16_t directionSelect) +{ + assert(channelSelect <= DMA_CHANNEL_7); + assert(directionSelect <= DMA_DIRECTION_INCREMENT); + + //Set the Source Address + __data16_write_addr((unsigned short)(baseAddress + channelSelect + OFS_DMA0SA), + srcAddress); + + //Reset bits before setting them + HWREG16(baseAddress + channelSelect + OFS_DMA0CTL) &= ~(DMASRCINCR_3); + HWREG16(baseAddress + channelSelect + OFS_DMA0CTL) |= directionSelect; +} + +//***************************************************************************** +// +//! \brief Sets the destination address and the direction that the destination +//! address will move after a transfer. +//! +//! This function sets the destination address and the direction that the +//! destination address will move after a transfer is complete. It may be +//! incremented, decremented, or unchanged. +//! +//! \param baseAddress is the base address of the DMA module. +//! \param channelSelect is the specified channel to set the destination +//! address direction for. +//! Valid values are: +//! - \b DMA_CHANNEL_0 +//! - \b DMA_CHANNEL_1 +//! - \b DMA_CHANNEL_2 +//! - \b DMA_CHANNEL_3 +//! - \b DMA_CHANNEL_4 +//! - \b DMA_CHANNEL_5 +//! - \b DMA_CHANNEL_6 +//! - \b DMA_CHANNEL_7 +//! \param dstAddress is the address of where the data will be transferred to. +//! \n Modified bits are \b DMAxDA of \b DMAxDA register. +//! \param directionSelect is the specified direction of the destination +//! address after a transfer. +//! Valid values are: +//! - \b DMA_DIRECTION_UNCHANGED +//! - \b DMA_DIRECTION_DECREMENT +//! - \b DMA_DIRECTION_INCREMENT +//! \n Modified bits are \b DMADSTINCR of \b DMAxCTL register. +//! +//! \return None +// +//***************************************************************************** +void DMA_setDstAddress (uint16_t baseAddress, + uint8_t channelSelect, + uint32_t dstAddress, + uint16_t directionSelect) +{ + assert(channelSelect <= DMA_CHANNEL_7); + assert(directionSelect <= DMA_DIRECTION_INCREMENT); + + //Set the Destination Address + __data16_write_addr((unsigned short)(baseAddress + channelSelect + OFS_DMA0DA), + dstAddress); + + //Reset bits before setting them + HWREG16(baseAddress + channelSelect + OFS_DMA0CTL) &= ~(DMADSTINCR_3); + HWREG16(baseAddress + channelSelect + OFS_DMA0CTL) |= (directionSelect << 2); +} + +//***************************************************************************** +// +//! \brief Enables transfers to be triggered. +//! +//! This function enables transfers upon appropriate trigger of the selected +//! trigger source for the selected channel. +//! +//! \param baseAddress is the base address of the DMA module. +//! \param channelSelect is the specified channel to enable transfer for. +//! Valid values are: +//! - \b DMA_CHANNEL_0 +//! - \b DMA_CHANNEL_1 +//! - \b DMA_CHANNEL_2 +//! - \b DMA_CHANNEL_3 +//! - \b DMA_CHANNEL_4 +//! - \b DMA_CHANNEL_5 +//! - \b DMA_CHANNEL_6 +//! - \b DMA_CHANNEL_7 +//! +//! \return None +// +//***************************************************************************** +void DMA_enableTransfers (uint16_t baseAddress, + uint8_t channelSelect) +{ + assert(channelSelect <= DMA_CHANNEL_7); + + HWREG16(baseAddress + channelSelect + OFS_DMA0CTL) |= DMAEN; +} + +//***************************************************************************** +// +//! \brief Disables transfers from being triggered. +//! +//! This function disables transfer from being triggered for the selected +//! channel. This function should be called before any re-initialization of the +//! selected DMA channel. +//! +//! \param baseAddress is the base address of the DMA module. +//! \param channelSelect is the specified channel to disable transfers for. +//! Valid values are: +//! - \b DMA_CHANNEL_0 +//! - \b DMA_CHANNEL_1 +//! - \b DMA_CHANNEL_2 +//! - \b DMA_CHANNEL_3 +//! - \b DMA_CHANNEL_4 +//! - \b DMA_CHANNEL_5 +//! - \b DMA_CHANNEL_6 +//! - \b DMA_CHANNEL_7 +//! +//! \return None +// +//***************************************************************************** +void DMA_disableTransfers (uint16_t baseAddress, + uint8_t channelSelect) +{ + assert(channelSelect <= DMA_CHANNEL_7); + + HWREG16(baseAddress + channelSelect + OFS_DMA0CTL) &= ~(DMAEN); +} + +//***************************************************************************** +// +//! \brief Starts a transfer if using the default trigger source selected in +//! initialization. +//! +//! This functions triggers a transfer of data from source to destination if +//! the trigger source chosen from initialization is the DMA_TRIGGERSOURCE_0. +//! Please note, this function needs to be called for each (repeated-)single +//! transfer, and when transferAmount of transfers have been complete in +//! (repeated-)block transfers. +//! +//! \param baseAddress is the base address of the DMA module. +//! \param channelSelect is the specified channel to start transfers for. +//! Valid values are: +//! - \b DMA_CHANNEL_0 +//! - \b DMA_CHANNEL_1 +//! - \b DMA_CHANNEL_2 +//! - \b DMA_CHANNEL_3 +//! - \b DMA_CHANNEL_4 +//! - \b DMA_CHANNEL_5 +//! - \b DMA_CHANNEL_6 +//! - \b DMA_CHANNEL_7 +//! +//! \return None +// +//***************************************************************************** +void DMA_startTransfer (uint16_t baseAddress, + uint8_t channelSelect) +{ + assert(channelSelect <= DMA_CHANNEL_7); + + HWREG16(baseAddress + channelSelect + OFS_DMA0CTL) |= DMAREQ; +} + +//***************************************************************************** +// +//! \brief Enables the DMA interrupt for the selected channel. +//! +//! Enables the DMA interrupt source. Only the sources that are enabled can be +//! reflected to the processor interrupt; disabled sources have no effect on +//! the processor. Does not clear interrupt flags. +//! +//! \param baseAddress is the base address of the DMA module. +//! \param channelSelect is the specified channel to enable the interrupt for. +//! Valid values are: +//! - \b DMA_CHANNEL_0 +//! - \b DMA_CHANNEL_1 +//! - \b DMA_CHANNEL_2 +//! - \b DMA_CHANNEL_3 +//! - \b DMA_CHANNEL_4 +//! - \b DMA_CHANNEL_5 +//! - \b DMA_CHANNEL_6 +//! - \b DMA_CHANNEL_7 +//! +//! \return None +// +//***************************************************************************** +void DMA_enableInterrupt (uint16_t baseAddress, + uint8_t channelSelect) +{ + assert(channelSelect <= DMA_CHANNEL_7); + + HWREG16(baseAddress + channelSelect + OFS_DMA0CTL) |= DMAIE; +} + +//***************************************************************************** +// +//! \brief Disables the DMA interrupt for the selected channel. +//! +//! Disables the DMA interrupt source. Only the sources that are enabled can be +//! reflected to the processor interrupt; disabled sources have no effect on +//! the processor. +//! +//! \param baseAddress is the base address of the DMA module. +//! \param channelSelect is the specified channel to disable the interrupt for. +//! Valid values are: +//! - \b DMA_CHANNEL_0 +//! - \b DMA_CHANNEL_1 +//! - \b DMA_CHANNEL_2 +//! - \b DMA_CHANNEL_3 +//! - \b DMA_CHANNEL_4 +//! - \b DMA_CHANNEL_5 +//! - \b DMA_CHANNEL_6 +//! - \b DMA_CHANNEL_7 +//! +//! \return None +// +//***************************************************************************** +void DMA_disableInterrupt (uint16_t baseAddress, + uint8_t channelSelect) +{ + assert(channelSelect <= DMA_CHANNEL_7); + + HWREG16(baseAddress + channelSelect + OFS_DMA0CTL) &= ~(DMAIE); +} + +//***************************************************************************** +// +//! \brief Returns the status of the interrupt flag for the selected channel. +//! +//! Returns the status of the interrupt flag for the selected channel. +//! +//! \param baseAddress is the base address of the DMA module. +//! \param channelSelect is the specified channel to return the interrupt flag +//! status from. +//! Valid values are: +//! - \b DMA_CHANNEL_0 +//! - \b DMA_CHANNEL_1 +//! - \b DMA_CHANNEL_2 +//! - \b DMA_CHANNEL_3 +//! - \b DMA_CHANNEL_4 +//! - \b DMA_CHANNEL_5 +//! - \b DMA_CHANNEL_6 +//! - \b DMA_CHANNEL_7 +//! +//! \return One of the following: +//! - \b DMA_INT_INACTIVE +//! - \b DMA_INT_ACTIVE +//! \n indicating the status of the current interrupt flag +// +//***************************************************************************** +uint16_t DMA_getInterruptStatus (uint16_t baseAddress, + uint8_t channelSelect) +{ + assert(channelSelect <= DMA_CHANNEL_7); + + return (HWREG16(baseAddress + channelSelect + OFS_DMA0CTL) & DMAIFG); +} + +//***************************************************************************** +// +//! \brief Clears the interrupt flag for the selected channel. +//! +//! This function clears the DMA interrupt flag is cleared, so that it no +//! longer asserts. +//! +//! \param baseAddress is the base address of the DMA module. +//! \param channelSelect is the specified channel to clear the interrupt flag +//! for. +//! Valid values are: +//! - \b DMA_CHANNEL_0 +//! - \b DMA_CHANNEL_1 +//! - \b DMA_CHANNEL_2 +//! - \b DMA_CHANNEL_3 +//! - \b DMA_CHANNEL_4 +//! - \b DMA_CHANNEL_5 +//! - \b DMA_CHANNEL_6 +//! - \b DMA_CHANNEL_7 +//! +//! \return None +// +//***************************************************************************** +void DMA_clearInterrupt (uint16_t baseAddress, + uint8_t channelSelect) +{ + assert(channelSelect <= DMA_CHANNEL_7); + + HWREG16(baseAddress + channelSelect + OFS_DMA0CTL) &= ~(DMAIFG); +} + +//***************************************************************************** +// +//! \brief Returns the status of the NMIAbort for the selected channel. +//! +//! This function returns the status of the NMI Abort flag for the selected +//! channel. If this flag has been set, it is because a transfer on this +//! channel was aborted due to a interrupt from an NMI. +//! +//! \param baseAddress is the base address of the DMA module. +//! \param channelSelect is the specified channel to return the status of the +//! NMI Abort flag for. +//! Valid values are: +//! - \b DMA_CHANNEL_0 +//! - \b DMA_CHANNEL_1 +//! - \b DMA_CHANNEL_2 +//! - \b DMA_CHANNEL_3 +//! - \b DMA_CHANNEL_4 +//! - \b DMA_CHANNEL_5 +//! - \b DMA_CHANNEL_6 +//! - \b DMA_CHANNEL_7 +//! +//! \return One of the following: +//! - \b DMA_NOTABORTED +//! - \b DMA_ABORTED +//! \n indicating the status of the NMIAbort for the selected channel +// +//***************************************************************************** +uint16_t DMA_NMIAbortStatus (uint16_t baseAddress, + uint8_t channelSelect) +{ + assert(channelSelect <= DMA_CHANNEL_7); + + return (HWREG16(baseAddress + channelSelect + OFS_DMA0CTL) & DMAABORT); +} + +//***************************************************************************** +// +//! \brief Clears the status of the NMIAbort to proceed with transfers for the +//! selected channel. +//! +//! This function clears the status of the NMI Abort flag for the selected +//! channel to allow for transfers on the channel to continue. +//! +//! \param baseAddress is the base address of the DMA module. +//! \param channelSelect is the specified channel to clear the NMI Abort flag +//! for. +//! Valid values are: +//! - \b DMA_CHANNEL_0 +//! - \b DMA_CHANNEL_1 +//! - \b DMA_CHANNEL_2 +//! - \b DMA_CHANNEL_3 +//! - \b DMA_CHANNEL_4 +//! - \b DMA_CHANNEL_5 +//! - \b DMA_CHANNEL_6 +//! - \b DMA_CHANNEL_7 +//! +//! \return None +// +//***************************************************************************** +void DMA_clearNMIAbort (uint16_t baseAddress, + uint8_t channelSelect) +{ + assert(channelSelect <= DMA_CHANNEL_7); + + HWREG16(baseAddress + channelSelect + OFS_DMA0CTL) &= ~(DMAABORT); +} + +//***************************************************************************** +// +//! \brief Disables the DMA from stopping the CPU during a Read-Modify-Write +//! Operation to start a transfer. +//! +//! This function allows the CPU to finish any read-modify-write operations it +//! may be in the middle of before transfers of and DMA channel stop the CPU. +//! +//! \param baseAddress is the base address of the DMA module. +//! +//! \return None +// +//***************************************************************************** +void DMA_disableTransferDuringReadModifyWrite (uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_DMACTL4) |= DMARMWDIS; +} + +//***************************************************************************** +// +//! \brief Enables the DMA to stop the CPU during a Read-Modify-Write Operation +//! to start a transfer. +//! +//! This function allows the DMA to stop the CPU in the middle of a read- +//! modify-write operation to transfer data. +//! +//! \param baseAddress is the base address of the DMA module. +//! +//! \return None +// +//***************************************************************************** +void DMA_enableTransferDuringReadModifyWrite (uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_DMACTL4) &= ~(DMARMWDIS); +} + +//***************************************************************************** +// +//! \brief Enables Round Robin prioritization. +//! +//! This function enables Round Robin Prioritization of DMA channels. In the +//! case of Round Robin Prioritization, the last DMA channel to have +//! transferred data then has the last priority, which comes into play when +//! multiple DMA channels are ready to transfer at the same time. +//! +//! \param baseAddress is the base address of the DMA module. +//! +//! \return None +// +//***************************************************************************** +void DMA_enableRoundRobinPriority (uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_DMACTL4) |= ROUNDROBIN; +} + +//***************************************************************************** +// +//! \brief Disables Round Robin prioritization. +//! +//! This function disables Round Robin Prioritization, enabling static +//! prioritization of the DMA channels. In static prioritization, the DMA +//! channels are prioritized with the lowest DMA channel index having the +//! highest priority (i.e. DMA Channel 0 has the highest priority). +//! +//! \param baseAddress is the base address of the DMA module. +//! +//! \return None +// +//***************************************************************************** +void DMA_disableRoundRobinPriority (uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_DMACTL4) &= ~(ROUNDROBIN); +} + +//***************************************************************************** +// +//! \brief Enables a NMI to interrupt a DMA transfer. +//! +//! This function allow NMI's to interrupting any DMA transfer currently in +//! progress and stops any future transfers to begin before the NMI is done +//! processing. +//! +//! \param baseAddress is the base address of the DMA module. +//! +//! \return None +// +//***************************************************************************** +void DMA_enableNMIAbort (uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_DMACTL4) |= ENNMI; +} + +//***************************************************************************** +// +//! \brief Disables any NMI from interrupting a DMA transfer. +//! +//! This function disables NMI's from interrupting any DMA transfer currently +//! in progress. +//! +//! \param baseAddress is the base address of the DMA module. +//! +//! \return None +// +//***************************************************************************** +void DMA_disableNMIAbort (uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_DMACTL4) &= ~(ENNMI); +} + + +#endif +#endif +//***************************************************************************** +// +//! Close the doxygen group for dma_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/deprecated/dma.h b/source/driverlib/MSP430F5xx_6xx/deprecated/dma.h new file mode 100644 index 0000000..4997a1a --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/deprecated/dma.h @@ -0,0 +1,274 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// dma.h - Driver for the DMA Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_DMA_H__ +#define __MSP430WARE_DMA_H__ + +#include "inc/hw_memmap.h" + +#if defined(__MSP430_HAS_DMAX_3__) || defined(__MSP430_HAS_DMAX_6__) + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//****************************************************************************** +// +// The following is a struct that is passed to DMA_initialize() +// +//****************************************************************************** +typedef struct DMA_initializeParam { + uint8_t channelSelect; + uint16_t transferModeSelect; + uint16_t transferSize; + uint8_t triggerSourceSelect; + uint8_t transferUnitSelect; + uint8_t triggerTypeSelect; +} DMA_initializeParam; + + +//***************************************************************************** +// +// The following are values that can be passed to the triggerSourceSelect +// parameter for functions: DMA_init(). +// +//***************************************************************************** +#define DMA_TRIGGERSOURCE_0 (0x00) +#define DMA_TRIGGERSOURCE_1 (0x01) +#define DMA_TRIGGERSOURCE_2 (0x02) +#define DMA_TRIGGERSOURCE_3 (0x03) +#define DMA_TRIGGERSOURCE_4 (0x04) +#define DMA_TRIGGERSOURCE_5 (0x05) +#define DMA_TRIGGERSOURCE_6 (0x06) +#define DMA_TRIGGERSOURCE_7 (0x07) +#define DMA_TRIGGERSOURCE_8 (0x08) +#define DMA_TRIGGERSOURCE_9 (0x09) +#define DMA_TRIGGERSOURCE_10 (0x0A) +#define DMA_TRIGGERSOURCE_11 (0x0B) +#define DMA_TRIGGERSOURCE_12 (0x0C) +#define DMA_TRIGGERSOURCE_13 (0x0D) +#define DMA_TRIGGERSOURCE_14 (0x0E) +#define DMA_TRIGGERSOURCE_15 (0x0F) +#define DMA_TRIGGERSOURCE_16 (0x10) +#define DMA_TRIGGERSOURCE_17 (0x11) +#define DMA_TRIGGERSOURCE_18 (0x12) +#define DMA_TRIGGERSOURCE_19 (0x13) +#define DMA_TRIGGERSOURCE_20 (0x14) +#define DMA_TRIGGERSOURCE_21 (0x15) +#define DMA_TRIGGERSOURCE_22 (0x16) +#define DMA_TRIGGERSOURCE_23 (0x17) +#define DMA_TRIGGERSOURCE_24 (0x18) +#define DMA_TRIGGERSOURCE_25 (0x19) +#define DMA_TRIGGERSOURCE_26 (0x1A) +#define DMA_TRIGGERSOURCE_27 (0x1B) +#define DMA_TRIGGERSOURCE_28 (0x1C) +#define DMA_TRIGGERSOURCE_29 (0x1D) +#define DMA_TRIGGERSOURCE_30 (0x1E) +#define DMA_TRIGGERSOURCE_31 (0x1F) + +//***************************************************************************** +// +// The following are values that can be passed to the transferModeSelect +// parameter for functions: DMA_init(). +// +//***************************************************************************** +#define DMA_TRANSFER_SINGLE (DMADT_0) +#define DMA_TRANSFER_BLOCK (DMADT_1) +#define DMA_TRANSFER_BURSTBLOCK (DMADT_2) +#define DMA_TRANSFER_REPEATED_SINGLE (DMADT_4) +#define DMA_TRANSFER_REPEATED_BLOCK (DMADT_5) +#define DMA_TRANSFER_REPEATED_BURSTBLOCK (DMADT_6) + +//***************************************************************************** +// +// The following are values that can be passed to the channelSelect parameter +// for functions: DMA_init(), DMA_setTransferSize(), DMA_setSrcAddress(), +// DMA_setDstAddress(), DMA_enableTransfers(), DMA_disableTransfers(), +// DMA_startTransfer(), DMA_enableInterrupt(), DMA_disableInterrupt(), +// DMA_getInterruptStatus(), DMA_clearInterrupt(), DMA_NMIAbortStatus(), and +// DMA_clearNMIAbort(). +// +//***************************************************************************** +#define DMA_CHANNEL_0 (0x00) +#define DMA_CHANNEL_1 (0x10) +#define DMA_CHANNEL_2 (0x20) +#define DMA_CHANNEL_3 (0x30) +#define DMA_CHANNEL_4 (0x40) +#define DMA_CHANNEL_5 (0x50) +#define DMA_CHANNEL_6 (0x60) +#define DMA_CHANNEL_7 (0x70) + +//***************************************************************************** +// +// The following are values that can be passed to the triggerTypeSelect +// parameter for functions: DMA_init(). +// +//***************************************************************************** +#define DMA_TRIGGER_RISINGEDGE (!(DMALEVEL)) +#define DMA_TRIGGER_HIGH (DMALEVEL) + +//***************************************************************************** +// +// The following are values that can be passed to the transferUnitSelect +// parameter for functions: DMA_init(). +// +//***************************************************************************** +#define DMA_SIZE_SRCWORD_DSTWORD (!(DMASRCBYTE + DMADSTBYTE)) +#define DMA_SIZE_SRCBYTE_DSTWORD (DMASRCBYTE) +#define DMA_SIZE_SRCWORD_DSTBYTE (DMADSTBYTE) +#define DMA_SIZE_SRCBYTE_DSTBYTE (DMASRCBYTE + DMADSTBYTE) + +//***************************************************************************** +// +// The following are values that can be passed to the directionSelect parameter +// for functions: DMA_setSrcAddress(), and DMA_setDstAddress(). +// +//***************************************************************************** +#define DMA_DIRECTION_UNCHANGED (DMASRCINCR_0) +#define DMA_DIRECTION_DECREMENT (DMASRCINCR_2) +#define DMA_DIRECTION_INCREMENT (DMASRCINCR_3) + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the DMA_getInterruptStatus() function. +// +//***************************************************************************** +#define DMA_INT_INACTIVE (0x0) +#define DMA_INT_ACTIVE (DMAIFG) + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the DMA_NMIAbortStatus() function. +// +//***************************************************************************** +#define DMA_NOTABORTED (0x0) +#define DMA_ABORTED (DMAABORT) + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern bool DMA_initialize(uint16_t baseAddress, + DMA_initializeParam *param); + +extern void DMA_setTransferSize(uint16_t baseAddress, + uint8_t channelSelect, + uint16_t transferSize); + +extern void DMA_setSrcAddress(uint16_t baseAddress, + uint8_t channelSelect, + uint32_t srcAddress, + uint16_t directionSelect); + +extern void DMA_setDstAddress(uint16_t baseAddress, + uint8_t channelSelect, + uint32_t dstAddress, + uint16_t directionSelect); + +extern void DMA_enableTransfers(uint16_t baseAddress, + uint8_t channelSelect); + +extern void DMA_disableTransfers(uint16_t baseAddress, + uint8_t channelSelect); + +extern void DMA_startTransfer(uint16_t baseAddress, + uint8_t channelSelect); + +extern void DMA_enableInterrupt(uint16_t baseAddress, + uint8_t channelSelect); + +extern void DMA_disableInterrupt(uint16_t baseAddress, + uint8_t channelSelect); + +extern uint16_t DMA_getInterruptStatus(uint16_t baseAddress, + uint8_t channelSelect); + +extern void DMA_clearInterrupt(uint16_t baseAddress, + uint8_t channelSelect); + +extern uint16_t DMA_NMIAbortStatus(uint16_t baseAddress, + uint8_t channelSelect); + +extern void DMA_clearNMIAbort(uint16_t baseAddress, + uint8_t channelSelect); + +extern void DMA_disableTransferDuringReadModifyWrite(uint16_t baseAddress); + +extern void DMA_enableTransferDuringReadModifyWrite(uint16_t baseAddress); + +extern void DMA_enableRoundRobinPriority(uint16_t baseAddress); + +extern void DMA_disableRoundRobinPriority(uint16_t baseAddress); + +extern void DMA_enableNMIAbort(uint16_t baseAddress); + +extern void DMA_disableNMIAbort(uint16_t baseAddress); + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +extern bool DMA_init(uint16_t baseAddress, + uint8_t channelSelect, + uint16_t transferModeSelect, + uint16_t transferSize, + uint8_t triggerSourceSelect, + uint8_t transferUnitSelect, + uint8_t triggerTypeSelect); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_DMA_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/deprecated/flash.c b/source/driverlib/MSP430F5xx_6xx/deprecated/flash.c new file mode 100644 index 0000000..b4b9fe5 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/deprecated/flash.c @@ -0,0 +1,481 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// flash.c - Driver for the flash Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup flash_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef DRIVERLIB_LEGACY_MODE + +#ifdef __MSP430_HAS_FLASH__ +#include "flash.h" + +#include + +//***************************************************************************** +// +//! \brief Erase a single segment of the flash memory. +//! +//! For devices like MSP430i204x, if the specified segment is the information +//! flash segment, the FLASH_unlockInfo API must be called prior to calling +//! this API. +//! +//! \param baseAddress is the base address of the FLASH module. +//! \param flash_ptr is the pointer into the flash segment to be erased +//! +//! \return None +// +//***************************************************************************** +void FLASH_segmentErase (uint16_t baseAddress, uint8_t *flash_ptr) +{ + //Clear Lock bit + HWREG16(baseAddress + OFS_FCTL3) = FWKEY; + + //Set Erase bit + HWREG16(baseAddress + OFS_FCTL1) = FWKEY + ERASE; + + //Dummy write to erase Flash seg + *flash_ptr = 0; + + //test busy + while (HWREG8(baseAddress + OFS_FCTL3) & BUSY) ; + + //Clear ERASE bit + HWREG16(baseAddress + OFS_FCTL1) = FWKEY; + + //Set LOCK bit + HWREG16(baseAddress + OFS_FCTL3) = FWKEY + LOCK; +} + +//***************************************************************************** +// +//! \brief Erase a single bank of the flash memory. +//! +//! This function erases a single bank of the flash memory. This API will +//! erase the entire flash if device contains only one flash bank. +//! +//! \param baseAddress is the base address of the FLASH module. +//! \param flash_ptr is a pointer into the bank to be erased +//! +//! \return None +// +//***************************************************************************** +void FLASH_bankErase (uint16_t baseAddress, uint8_t *flash_ptr) +{ + //Clear Lock bit + HWREG16(baseAddress + OFS_FCTL3) = FWKEY; + + while (HWREG8(baseAddress + OFS_FCTL3) & BUSY) ; + + //Set MERAS bit + HWREG16(baseAddress + OFS_FCTL1) = FWKEY + MERAS; + + //Dummy write to erase Flash seg + *flash_ptr = 0; + + //test busy + while (HWREG8(baseAddress + OFS_FCTL3) & BUSY) ; + + //Clear MERAS bit + HWREG16(baseAddress + OFS_FCTL1) = FWKEY; + + //Set LOCK bit + HWREG16(baseAddress + OFS_FCTL3) = FWKEY + LOCK; +} + +//***************************************************************************** +// +//! \brief Erase all flash memory. +//! +//! This function erases all the flash memory banks. For devices like +//! MSP430i204x, this API erases main memory and information flash memory if +//! the FLASH_unlockInfo API was previously executed (otherwise the information +//! flash is not erased). Also note that erasing information flash memory in +//! the MSP430i204x impacts the TLV calibration constants located at the +//! information memory. +//! +//! \param baseAddress is the base address of the FLASH module. +//! \param flash_ptr is a pointer into the bank to be erased +//! +//! \return None +// +//***************************************************************************** +void FLASH_massErase (uint16_t baseAddress, uint8_t *flash_ptr) +{ + //Clear Lock bit + HWREG16(baseAddress + OFS_FCTL3) = FWKEY; + + while (HWREG8(baseAddress + OFS_FCTL3) & BUSY) ; + + //Set MERAS bit + HWREG16(baseAddress + OFS_FCTL1) = FWKEY + MERAS + ERASE; + + //Dummy write to erase Flash seg + *flash_ptr = 0; + + //test busy + while (HWREG8(baseAddress + OFS_FCTL3) & BUSY) ; + + //Clear MERAS bit + HWREG16(baseAddress + OFS_FCTL1) = FWKEY; + + //Set LOCK bit + HWREG16(baseAddress + OFS_FCTL3) = FWKEY + LOCK; +} + +//***************************************************************************** +// +//! \brief Erase check of the flash memory +//! +//! This function checks bytes in flash memory to make sure that they are in an +//! erased state (are set to 0xFF). +//! +//! \param baseAddress is the base address of the FLASH module. +//! \param flash_ptr is the pointer to the starting location of the erase check +//! \param numberOfBytes is the number of bytes to be checked +//! +//! \return STATUS_SUCCESS or STATUS_FAIL +// +//***************************************************************************** +bool FLASH_eraseCheck (uint16_t baseAddress, + uint8_t *flash_ptr, + uint16_t numberOfBytes + ) +{ + uint16_t i; + + for (i = 0; i < numberOfBytes; i++) + { + //was erasing successfull? + if ((*(flash_ptr + i)) != 0xFF){ + return ( STATUS_FAIL) ; + } + } + return ( STATUS_SUCCESS) ; +} + +//***************************************************************************** +// +//! \brief Write data into the flash memory in byte format, pass by reference +//! +//! This function writes a byte array of size count into flash memory. Assumes +//! the flash memory is already erased and unlocked. FLASH_segmentErase can be +//! used to erase a segment. +//! +//! \param baseAddress is the base address of the FLASH module. +//! \param data_ptr is the pointer to the data to be written +//! \param flash_ptr is the pointer into which to write the data +//! \param count number of times to write the value +//! +//! \return None +// +//***************************************************************************** +void FLASH_write8 (uint16_t baseAddress, + uint8_t *data_ptr, + uint8_t *flash_ptr, + uint16_t count + ) +{ + //Clear Lock bit + HWREG16(baseAddress + OFS_FCTL3) = FWKEY; + + //Enable byte/word write mode + HWREG16(baseAddress + OFS_FCTL1) = FWKEY + WRT; + + while (count > 0) + { + //test busy + while (HWREG8(baseAddress + OFS_FCTL3) & BUSY) ; + + //Write to Flash + *flash_ptr++ = *data_ptr++; + count--; + } + + //Clear WRT bit + HWREG16(baseAddress + OFS_FCTL1) = FWKEY; + + //Set LOCK bit + HWREG16(baseAddress + OFS_FCTL3) = FWKEY + LOCK; +} + +//***************************************************************************** +// +//! \brief Write data into the flash memory in 16-bit word format, pass by +//! reference +//! +//! This function writes a 16-bit word array of size count into flash memory. +//! Assumes the flash memory is already erased and unlocked. FLASH_segmentErase +//! can be used to erase a segment. +//! +//! \param baseAddress is the base address of the FLASH module. +//! \param data_ptr is the pointer to the data to be written +//! \param flash_ptr is the pointer into which to write the data +//! \param count number of times to write the value +//! +//! \return None +// +//***************************************************************************** +void FLASH_write16 (uint16_t baseAddress, + uint16_t *data_ptr, + uint16_t *flash_ptr, + uint16_t count + ) +{ + //Clear Lock bit + HWREG16(baseAddress + OFS_FCTL3) = FWKEY; + + //Enable byte/word write mode + HWREG16(baseAddress + OFS_FCTL1) = FWKEY + WRT; + + while (count > 0) + { + //test busy + while (HWREG8(baseAddress + OFS_FCTL3) & BUSY) ; + + //Write to Flash + *flash_ptr++ = *data_ptr++; + count--; + } + + //Clear WRT bit + HWREG16(baseAddress + OFS_FCTL1) = FWKEY; + + //Set LOCK bit + HWREG16(baseAddress + OFS_FCTL3) = FWKEY + LOCK; +} + +//***************************************************************************** +// +//! \brief Write data into the flash memory in 32-bit word format, pass by +//! reference +//! +//! This function writes a 32-bit array of size count into flash memory. +//! Assumes the flash memory is already erased and unlocked. FLASH_segmentErase +//! can be used to erase a segment. +//! +//! \param baseAddress is the base address of the FLASH module. +//! \param data_ptr is the pointer to the data to be written +//! \param flash_ptr is the pointer into which to write the data +//! \param count number of times to write the value +//! +//! \return None +// +//***************************************************************************** +void FLASH_write32 (uint16_t baseAddress, + uint32_t *data_ptr, + uint32_t *flash_ptr, + uint16_t count + ) +{ + //Clear Lock bit + HWREG16(baseAddress + OFS_FCTL3) = FWKEY; + + //Enable long-word write + HWREG16(baseAddress + OFS_FCTL1) = FWKEY + BLKWRT; + + while (count > 0) + { + //test busy + while (HWREG8(baseAddress + OFS_FCTL3) & BUSY) ; + + //Write to Flash + *flash_ptr++ = *data_ptr++; + + count--; + } + + //Clear BLKWRT bit + HWREG16(baseAddress + OFS_FCTL1) = FWKEY; + + //Set LOCK bit + HWREG16(baseAddress + OFS_FCTL3) = FWKEY + LOCK; +} + +//***************************************************************************** +// +//! \brief Write data into the flash memory in 32-bit word format, pass by +//! value +//! +//! This function writes a 32-bit data value into flash memory, count times. +//! Assumes the flash memory is already erased and unlocked. FLASH_segmentErase +//! can be used to erase a segment. +//! +//! \param baseAddress is the base address of the FLASH module. +//! \param value value to fill memory with +//! \param flash_ptr is the pointer into which to write the data +//! \param count number of times to write the value +//! +//! \return None +// +//***************************************************************************** +void FLASH_memoryFill32 (uint16_t baseAddress, + uint32_t value, + uint32_t *flash_ptr, + uint16_t count + ) +{ + //Clear Lock bit + HWREG16(baseAddress + OFS_FCTL3) = FWKEY; + + //Enable long-word write + HWREG16(baseAddress + OFS_FCTL1) = FWKEY + BLKWRT; + + //test busy + while (count > 0) + { + while ((HWREG8(baseAddress + OFS_FCTL3)) & BUSY) ; + + //Write to Flash + *flash_ptr++ = value; + + count--; + } + + //Clear BLKWRT bit + HWREG16(baseAddress + OFS_FCTL1) = FWKEY; + + //Set LOCK bit + HWREG16(baseAddress + OFS_FCTL3) = FWKEY + LOCK; +} + +//***************************************************************************** +// +//! \brief Check FLASH status to see if it is currently busy erasing or +//! programming +//! +//! This function checks the status register to determine if the flash memory +//! is ready for writing. +//! +//! \param baseAddress is the base address of the FLASH module. +//! \param mask FLASH status to read +//! Mask value is the logical OR of any of the following: +//! - \b FLASH_READY_FOR_NEXT_WRITE +//! - \b FLASH_ACCESS_VIOLATION_INTERRUPT_FLAG +//! - \b FLASH_PASSWORD_WRITTEN_INCORRECTLY +//! - \b FLASH_BUSY +//! +//! \return Logical OR of any of the following: +//! - \b FLASH_READY_FOR_NEXT_WRITE +//! - \b FLASH_ACCESS_VIOLATION_INTERRUPT_FLAG +//! - \b FLASH_PASSWORD_WRITTEN_INCORRECTLY +//! - \b FLASH_BUSY +//! \n indicating the status of the FLASH +// +//***************************************************************************** +uint8_t FLASH_status (uint16_t baseAddress, + uint8_t mask + ) +{ + return ((HWREG8(baseAddress + OFS_FCTL3) & mask )); +} + +//***************************************************************************** +// +//! \brief Locks the information flash memory segment A +//! +//! This function is typically called after an erase or write operation on the +//! information flash segment is performed by any of the other API functions in +//! order to re-lock the information flash segment. +//! +//! \param baseAddress is the base address of the FLASH module. +//! +//! \return None +// +//***************************************************************************** +void FLASH_lockInfoA (uint16_t baseAddress) +{ + //Disable global interrupts while doing RMW operation on LOCKA bit + uint16_t gieStatus; + gieStatus = __get_SR_register() & GIE; //Store current SR register + __disable_interrupt(); //Disable global interrupt + + //Set the LOCKA bit in FCTL3. + //Since LOCKA toggles when you write a 1 (and writing 0 has no effect), + //read the register, XOR with LOCKA mask, mask the lower byte + //and write it back. + HWREG16(baseAddress + OFS_FCTL3) = FWKEY + + ((HWREG16(baseAddress + OFS_FCTL3) ^ LOCKA) & 0xFF); + + //Reinstate SR register to restore global interrupt enable status + __bis_SR_register(gieStatus); +} + +//***************************************************************************** +// +//! \brief Unlocks the information flash memory segment A +//! +//! This function must be called before an erase or write operation on the +//! information flash segment is performed by any of the other API functions. +//! +//! \param baseAddress is the base address of the FLASH module. +//! +//! \return None +// +//***************************************************************************** +void FLASH_unlockInfoA (uint16_t baseAddress) +{ + //Disable global interrupts while doing RMW operation on LOCKA bit + uint16_t gieStatus; + gieStatus = __get_SR_register() & GIE; //Store current SR register + __disable_interrupt(); //Disable global interrupt + + //Clear the LOCKA bit in FCTL3. + //Since LOCKA toggles when you write a 1 (and writing 0 has no effect), + //read the register, mask the lower byte, and write it back. + HWREG16(baseAddress + OFS_FCTL3) = FWKEY + + (HWREG16(baseAddress + OFS_FCTL3) & 0xFF); + + //Reinstate SR register to restore global interrupt enable status + __bis_SR_register(gieStatus); +} + + +#endif +#endif +//***************************************************************************** +// +//! Close the doxygen group for flash_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/deprecated/flash.h b/source/driverlib/MSP430F5xx_6xx/deprecated/flash.h new file mode 100644 index 0000000..49766c0 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/deprecated/flash.h @@ -0,0 +1,123 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// flash.h - Driver for the FLASH Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_FLASH_H__ +#define __MSP430WARE_FLASH_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_FLASH__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the mask parameter for +// functions: FLASH_status() as well as returned by the FLASH_status() +// function. +// +//***************************************************************************** +#define FLASH_READY_FOR_NEXT_WRITE WAIT +#define FLASH_ACCESS_VIOLATION_INTERRUPT_FLAG ACCVIFG +#define FLASH_PASSWORD_WRITTEN_INCORRECTLY KEYV +#define FLASH_BUSY BUSY + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void FLASH_segmentErase(uint16_t baseAddress, + uint8_t *flash_ptr); + +extern void FLASH_bankErase(uint16_t baseAddress, + uint8_t *flash_ptr); + +extern void FLASH_massErase(uint16_t baseAddress, + uint8_t *flash_ptr); + +extern bool FLASH_eraseCheck(uint16_t baseAddress, + uint8_t *flash_ptr, + uint16_t numberOfBytes); + +extern void FLASH_write8(uint16_t baseAddress, + uint8_t *data_ptr, + uint8_t *flash_ptr, + uint16_t count); + +extern void FLASH_write16(uint16_t baseAddress, + uint16_t *data_ptr, + uint16_t *flash_ptr, + uint16_t count); + +extern void FLASH_write32(uint16_t baseAddress, + uint32_t *data_ptr, + uint32_t *flash_ptr, + uint16_t count); + +extern void FLASH_memoryFill32(uint16_t baseAddress, + uint32_t value, + uint32_t *flash_ptr, + uint16_t count); + +extern uint8_t FLASH_status(uint16_t baseAddress, + uint8_t mask); + +extern void FLASH_lockInfoA(uint16_t baseAddress); + +extern void FLASH_unlockInfoA(uint16_t baseAddress); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_FLASH_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/deprecated/mpy32.c b/source/driverlib/MSP430F5xx_6xx/deprecated/mpy32.c new file mode 100644 index 0000000..5149f40 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/deprecated/mpy32.c @@ -0,0 +1,598 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// mpy32.c - Driver for the mpy32 Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup mpy32_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef DRIVERLIB_LEGACY_MODE + +#ifdef __MSP430_HAS_MPY32__ +#include "mpy32.h" + +#include + +//***************************************************************************** +// +//! \brief Sets the write delay setting for the MPY32 module. +//! +//! This function sets up a write delay to the MPY module's registers, which +//! holds any writes to the registers until all calculations are complete. +//! There are two different settings, one which waits for 32-bit results to be +//! ready, and one which waits for 64-bit results to be ready. This prevents +//! unpredicatble results if registers are changed before the results are +//! ready. +//! +//! \param baseAddress is the Base Address of the MPY32 Module. +//! \param writeDelaySelect delays the write to any MPY32 register until the +//! selected bit size of result has been written. +//! Valid values are: +//! - \b MPY32_WRITEDELAY_OFF [Default] - writes are not delayed +//! - \b MPY32_WRITEDELAY_32BIT - writes are delayed until a 32-bit +//! result is available in the result registers +//! - \b MPY32_WRITEDELAY_64BIT - writes are delayed until a 64-bit +//! result is available in the result registers +//! \n Modified bits are \b MPYDLY32 and \b MPYDLYWRTEN of \b MPY32CTL0 +//! register. +//! +//! \return None +// +//***************************************************************************** +void MPY32_setWriteDelay (uint16_t baseAddress, + uint16_t writeDelaySelect) +{ + HWREG16(baseAddress + OFS_MPY32CTL0) &= ~(MPYDLY32 + MPYDLYWRTEN); + HWREG16(baseAddress + OFS_MPY32CTL0) |= writeDelaySelect; +} + +//***************************************************************************** +// +//! \brief Enables Saturation Mode. +//! +//! This function enables saturation mode. When this is enabled, the result +//! read out from the MPY result registers is converted to the most-positive +//! number in the case of an overflow, or the most-negative number in the case +//! of an underflow. Please note, that the raw value in the registers does not +//! reflect the result returned, and if the saturation mode is disabled, then +//! the raw value of the registers will be returned instead. +//! +//! \param baseAddress is the Base Address of the MPY32 Module. +//! +//! \return None +// +//***************************************************************************** +void MPY32_enableSaturationMode (uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_MPY32CTL0_L) |= MPYSAT; +} + +//***************************************************************************** +// +//! \brief Disables Saturation Mode. +//! +//! This function disables saturation mode, which allows the raw result of the +//! MPY result registers to be returned. +//! +//! \param baseAddress is the Base Address of the MPY32 Module. +//! +//! \return None +// +//***************************************************************************** +void MPY32_disableSaturationMode (uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_MPY32CTL0_L) &= ~(MPYSAT); +} + +//***************************************************************************** +// +//! \brief Gets the Saturation Mode. +//! +//! This function gets the current saturation mode. +//! +//! +//! \return Gets the Saturation Mode +//! Return one of the following: +//! - \b MPY32_SATURATION_MODE_DISABLED +//! - \b MPY32_SATURATION_MODE_ENABLED +//! \n Gets the Saturation Mode +// +//***************************************************************************** +uint8_t MPY32_getSaturationMode (uint16_t baseAddress) +{ + return (HWREG8(baseAddress + OFS_MPY32CTL0_L) &(MPYSAT)); +} + +//***************************************************************************** +// +//! \brief Enables Fraction Mode. +//! +//! This function enables fraction mode. +//! +//! \param baseAddress is the Base Address of the MPY32 Module. +//! +//! \return None +// +//***************************************************************************** +void MPY32_enableFractionalMode (uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_MPY32CTL0_L) |= MPYFRAC; +} + +//***************************************************************************** +// +//! \brief Disables Fraction Mode. +//! +//! This function disables fraction mode. +//! +//! \param baseAddress is the Base Address of the MPY32 Module. +//! +//! \return None +// +//***************************************************************************** +void MPY32_disableFractionalMode (uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_MPY32CTL0_L) &= ~(MPYFRAC); +} + +//***************************************************************************** +// +//! \brief Gets the Fractional Mode. +//! +//! This function gets the current fractional mode. +//! +//! +//! \return Gets the fractional mode +//! Return one of the following: +//! - \b MPY32_FRACTIONAL_MODE_DISABLED +//! - \b MPY32_FRACTIONAL_MODE_ENABLED +//! \n Gets the Fractional Mode +// +//***************************************************************************** +uint8_t MPY32_getFractionalMode (uint16_t baseAddress) +{ + return (HWREG8(baseAddress + OFS_MPY32CTL0_L) &(MPYFRAC)); +} + +//***************************************************************************** +// +//! \brief Sets an 8-bit value into operand 1. +//! +//! This function sets the first operand for multiplication and determines what +//! type of operation should be performed. Once the second operand is set, then +//! the operation will begin. +//! +//! \param baseAddress is the Base Address of the MPY32 Module. +//! \param multiplicationType is the type of multiplication to perform once the +//! second operand is set. +//! Valid values are: +//! - \b MPY32_MULTIPLY_UNSIGNED +//! - \b MPY32_MULTIPLY_SIGNED +//! - \b MPY32_MULTIPLYACCUMULATE_UNSIGNED +//! - \b MPY32_MULTIPLYACCUMULATE_SIGNED +//! \param operand is the 8-bit value to load into the 1st operand. +//! +//! \return None +// +//***************************************************************************** +void MPY32_setOperandOne8Bit (uint16_t baseAddress, + uint8_t multiplicationType, + uint8_t operand) +{ + HWREG8(baseAddress + OFS_MPY + multiplicationType) = operand; +} + +//***************************************************************************** +// +//! \brief Sets an 16-bit value into operand 1. +//! +//! This function sets the first operand for multiplication and determines what +//! type of operation should be performed. Once the second operand is set, then +//! the operation will begin. +//! +//! \param baseAddress is the Base Address of the MPY32 Module. +//! \param multiplicationType is the type of multiplication to perform once the +//! second operand is set. +//! Valid values are: +//! - \b MPY32_MULTIPLY_UNSIGNED +//! - \b MPY32_MULTIPLY_SIGNED +//! - \b MPY32_MULTIPLYACCUMULATE_UNSIGNED +//! - \b MPY32_MULTIPLYACCUMULATE_SIGNED +//! \param operand is the 16-bit value to load into the 1st operand. +//! +//! \return None +// +//***************************************************************************** +void MPY32_setOperandOne16Bit (uint16_t baseAddress, + uint8_t multiplicationType, + uint16_t operand) +{ + HWREG16(baseAddress + OFS_MPY + multiplicationType) = operand; +} + +//***************************************************************************** +// +//! \brief Sets an 24-bit value into operand 1. +//! +//! This function sets the first operand for multiplication and determines what +//! type of operation should be performed. Once the second operand is set, then +//! the operation will begin. +//! +//! \param baseAddress is the Base Address of the MPY32 Module. +//! \param multiplicationType is the type of multiplication to perform once the +//! second operand is set. +//! Valid values are: +//! - \b MPY32_MULTIPLY_UNSIGNED +//! - \b MPY32_MULTIPLY_SIGNED +//! - \b MPY32_MULTIPLYACCUMULATE_UNSIGNED +//! - \b MPY32_MULTIPLYACCUMULATE_SIGNED +//! \param operand is the 24-bit value to load into the 1st operand. +//! +//! \return None +// +//***************************************************************************** +void MPY32_setOperandOne24Bit (uint16_t baseAddress, + uint8_t multiplicationType, + uint32_t operand) +{ + multiplicationType <<= 1; + HWREG16(baseAddress + OFS_MPY32L + multiplicationType) = operand; + HWREG8(baseAddress + OFS_MPY32H + multiplicationType) = (operand >> 16); +} + +//***************************************************************************** +// +//! \brief Sets an 32-bit value into operand 1. +//! +//! This function sets the first operand for multiplication and determines what +//! type of operation should be performed. Once the second operand is set, then +//! the operation will begin. +//! +//! \param baseAddress is the Base Address of the MPY32 Module. +//! \param multiplicationType is the type of multiplication to perform once the +//! second operand is set. +//! Valid values are: +//! - \b MPY32_MULTIPLY_UNSIGNED +//! - \b MPY32_MULTIPLY_SIGNED +//! - \b MPY32_MULTIPLYACCUMULATE_UNSIGNED +//! - \b MPY32_MULTIPLYACCUMULATE_SIGNED +//! \param operand is the 32-bit value to load into the 1st operand. +//! +//! \return None +// +//***************************************************************************** +void MPY32_setOperandOne32Bit (uint16_t baseAddress, + uint8_t multiplicationType, + uint32_t operand) +{ + multiplicationType <<= 1; + HWREG16(baseAddress + OFS_MPY32L + multiplicationType) = operand; + HWREG16(baseAddress + OFS_MPY32H + multiplicationType) = (operand >> 16); +} + +//***************************************************************************** +// +//! \brief Sets an 8-bit value into operand 2, which starts the multiplication. +//! +//! This function sets the second operand of the multiplication operation and +//! starts the operation. +//! +//! \param baseAddress is the Base Address of the MPY32 Module. +//! \param operand is the 8-bit value to load into the 2nd operand. +//! +//! \return None +// +//***************************************************************************** +void MPY32_setOperandTwo8Bit (uint16_t baseAddress, + uint8_t operand) +{ + HWREG8(baseAddress + OFS_OP2) = operand; +} + +//***************************************************************************** +// +//! \brief Sets an 16-bit value into operand 2, which starts the +//! multiplication. +//! +//! This function sets the second operand of the multiplication operation and +//! starts the operation. +//! +//! \param baseAddress is the Base Address of the MPY32 Module. +//! \param operand is the 16-bit value to load into the 2nd operand. +//! +//! \return None +// +//***************************************************************************** +void MPY32_setOperandTwo16Bit (uint16_t baseAddress, + uint16_t operand) +{ + HWREG16(baseAddress + OFS_OP2) = operand; +} + +//***************************************************************************** +// +//! \brief Sets an 24-bit value into operand 2, which starts the +//! multiplication. +//! +//! This function sets the second operand of the multiplication operation and +//! starts the operation. +//! +//! \param baseAddress is the Base Address of the MPY32 Module. +//! \param operand is the 24-bit value to load into the 2nd operand. +//! +//! \return None +// +//***************************************************************************** +void MPY32_setOperandTwo24Bit (uint16_t baseAddress, + uint32_t operand) +{ + HWREG16(baseAddress + OFS_OP2L) = operand; + HWREG8(baseAddress + OFS_OP2H) = (operand >> 16); +} + +//***************************************************************************** +// +//! \brief Sets an 32-bit value into operand 2, which starts the +//! multiplication. +//! +//! This function sets the second operand of the multiplication operation and +//! starts the operation. +//! +//! \param baseAddress is the Base Address of the MPY32 Module. +//! \param operand is the 32-bit value to load into the 2nd operand. +//! +//! \return None +// +//***************************************************************************** +void MPY32_setOperandTwo32Bit (uint16_t baseAddress, + uint32_t operand) +{ + HWREG16(baseAddress + OFS_OP2L) = operand; + HWREG16(baseAddress + OFS_OP2H) = (operand >> 16); +} + +//***************************************************************************** +// +//! \brief Deprecated - Returns an 8-bit result of the last multiplication +//! operation. +//! +//! This function returns the 8 least significant bits of the result registers. +//! This can improve efficiency if the operation has no more than an 8-bit +//! result. +//! +//! \param baseAddress is the Base Address of the MPY32 Module. +//! +//! \return The 8-bit result of the last multiplication operation. +// +//***************************************************************************** +uint8_t MPY32_getResult8Bit (uint16_t baseAddress) +{ + return ( HWREG8(baseAddress + OFS_RES0_L) ); +} + +//***************************************************************************** +// +//! \brief Deprecated - Returns an 16-bit result of the last multiplication +//! operation. +//! +//! This function returns the 16 least significant bits of the result +//! registers. This can improve efficiency if the operation has no more than a +//! 16-bit result. +//! +//! \param baseAddress is the Base Address of the MPY32 Module. +//! +//! \return The 16-bit result of the last multiplication operation. +// +//***************************************************************************** +uint16_t MPY32_getResult16Bit (uint16_t baseAddress) +{ + return ( HWREG16(baseAddress + OFS_RES0) ); +} + +//***************************************************************************** +// +//! \brief Deprecated - Returns an 24-bit result of the last multiplication +//! operation. +//! +//! This function returns the 24 least significant bits of the result +//! registers. This can improve efficiency if the operation has no more than an +//! 24-bit result. +//! +//! \param baseAddress is the Base Address of the MPY32 Module. +//! +//! \return The 24-bit result of the last multiplication operation. +// +//***************************************************************************** +uint32_t MPY32_getResult24Bit (uint16_t baseAddress) +{ + uint32_t result = HWREG16(baseAddress + OFS_RES1); + + result = (result << 16) + HWREG16(baseAddress + OFS_RES0); + return ( result ); +} + +//***************************************************************************** +// +//! \brief Deprecated - Returns an 32-bit result of the last multiplication +//! operation. +//! +//! This function returns a 32-bit result of the last multiplication operation, +//! which is the maximum amount of bits of a 16 x 16 operation. +//! +//! \param baseAddress is the Base Address of the MPY32 Module. +//! +//! \return The 32-bit result of the last multiplication operation. +// +//***************************************************************************** +uint32_t MPY32_getResult32Bit (uint16_t baseAddress) +{ + uint32_t result = HWREG16(baseAddress + OFS_RES1); + + result = (result << 16) + HWREG16(baseAddress + OFS_RES0); + return ( result ); +} + +//***************************************************************************** +// +//! \brief Deprecated - Returns an 64-bit result of the last multiplication +//! operation. +//! +//! This function returns all 64 bits of the result registers. The way this is +//! passed is with 4 integers contained within a uint16 struct. +//! +//! \param baseAddress is the Base Address of the MPY32 Module. +//! +//! \return The 64-bit result separated into 4 uint16_ts in a uint16 struct +// +//***************************************************************************** +uint64 MPY32_getResult64Bit (uint16_t baseAddress) +{ + uint64 result; + + result.RES0 = HWREG16(baseAddress + OFS_RES0); + result.RES1 = HWREG16(baseAddress + OFS_RES1); + result.RES2 = HWREG16(baseAddress + OFS_RES2); + result.RES3 = HWREG16(baseAddress + OFS_RES3); + return ( result ); +} + +//***************************************************************************** +// +//! \brief Returns an 64-bit result of the last multiplication operation. +//! +//! This function returns all 64 bits of the result registers +//! +//! \param baseAddress is the Base Address of the MPY32 Module. +//! +//! \return The 64-bit result is returned as a uint64_t type +// +//***************************************************************************** +uint64_t MPY32_getResult (uint16_t baseAddress) +{ + uint64_t result; + + result = HWREG16(baseAddress + OFS_RES0); + result += ((uint64_t)HWREG16(baseAddress + OFS_RES1) << 16); + result += ((uint64_t)HWREG16(baseAddress + OFS_RES2) << 32); + result += ((uint64_t)HWREG16(baseAddress + OFS_RES3) << 48); + return ( result ); +} + +//***************************************************************************** +// +//! \brief Returns the Sum Extension of the last multiplication operation. +//! +//! This function returns the Sum Extension of the MPY module, which either +//! gives the sign after a signed operation or shows a carry after a multiply- +//! and-accumulate operation. The Sum Extension acts as a check for overflows +//! or underflows. +//! +//! \param baseAddress is the Base Address of the MPY32 Module. +//! +//! \return The value of the MPY32 module Sum Extension. +// +//***************************************************************************** +uint16_t MPY32_getSumExtension (uint16_t baseAddress) +{ + return ( HWREG16(baseAddress + OFS_SUMEXT) ); +} + +//***************************************************************************** +// +//! \brief Returns the Carry Bit of the last multiplication operation. +//! +//! This function returns the Carry Bit of the MPY module, which either gives +//! the sign after a signed operation or shows a carry after a multiply- and- +//! accumulate operation. +//! +//! \param baseAddress is the Base Address of the MPY32 Module. +//! +//! \return The value of the MPY32 module Carry Bit 0x0 or 0x1. +// +//***************************************************************************** +uint16_t MPY32_getCarryBitValue (uint16_t baseAddress) +{ + return ( HWREG16(baseAddress + OFS_MPY32CTL0) | MPYC); +} +//***************************************************************************** +// +//! \brief Clears the Carry Bit of the last multiplication operation. +//! +//! This function clears the Carry Bit of the MPY module +//! +//! \param baseAddress is the Base Address of the MPY32 Module. +//! +//! \return The value of the MPY32 module Carry Bit 0x0 or 0x1. +// +//***************************************************************************** +void MPY32_clearCarryBitValue (uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_MPY32CTL0) &= ~MPYC; +} +//***************************************************************************** +// +//! \brief Preloads the result register +//! +//! This function Preloads the result register +//! +//! \param baseAddress is the Base Address of the MPY32 Module. +//! +//! \return None +// +//***************************************************************************** +void MPY32_preloadResult (uint16_t baseAddress, + uint64_t result) +{ + HWREG16(baseAddress + OFS_RES0) = (result & 0xFFFF); + HWREG16(baseAddress + OFS_RES1) = ((result >> 16) & 0xFFFF); + HWREG16(baseAddress + OFS_RES2) = ((result >> 32) & 0xFFFF); + HWREG16(baseAddress + OFS_RES3) = ((result >> 48) & 0xFFFF); +} + +#endif +#endif +//***************************************************************************** +// +//! Close the doxygen group for mpy32_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/deprecated/mpy32.h b/source/driverlib/MSP430F5xx_6xx/deprecated/mpy32.h new file mode 100644 index 0000000..cab9b8e --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/deprecated/mpy32.h @@ -0,0 +1,216 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// mpy32.h - Driver for the MPY32 Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_MPY32_H__ +#define __MSP430WARE_MPY32_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_MPY32__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//****************************************************************************** +// +// The following is a struct that can be returned by MPY32_getResult64Bit() +// +//****************************************************************************** +typedef struct { + uint16_t RES0; + uint16_t RES1; + uint16_t RES2; + uint16_t RES3; +} uint64; + +//***************************************************************************** +// +// The following are values that can be passed to the writeDelaySelect +// parameter for functions: MPY32_setWriteDelay(). +// +//***************************************************************************** +#define MPY32_WRITEDELAY_OFF (!(MPYDLY32 + MPYDLYWRTEN)) +#define MPY32_WRITEDELAY_32BIT (MPYDLYWRTEN) +#define MPY32_WRITEDELAY_64BIT (MPYDLY32 + MPYDLYWRTEN) + +//***************************************************************************** +// +// The following are values that can be passed to the multiplicationType +// parameter for functions: MPY32_setOperandOne8Bit(), +// MPY32_setOperandOne16Bit(), MPY32_setOperandOne24Bit(), and +// MPY32_setOperandOne32Bit(). +// +//***************************************************************************** +#define MPY32_MULTIPLY_UNSIGNED (0x00) +#define MPY32_MULTIPLY_SIGNED (0x02) +#define MPY32_MULTIPLYACCUMULATE_UNSIGNED (0x04) +#define MPY32_MULTIPLYACCUMULATE_SIGNED (0x06) + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the MPY32_getSaturationMode() function. +// +//***************************************************************************** +#define MPY32_SATURATION_MODE_DISABLED 0x00 +#define MPY32_SATURATION_MODE_ENABLED MPYSAT + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the MPY32_getFractionalMode() function. +// +//***************************************************************************** +#define MPY32_FRACTIONAL_MODE_DISABLED 0x00 +#define MPY32_FRACTIONAL_MODE_ENABLED MPYFRAC + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void MPY32_setWriteDelay(uint16_t baseAddress, + uint16_t writeDelaySelect); + +extern void MPY32_enableSaturationMode(uint16_t baseAddress); + +extern void MPY32_disableSaturationMode(uint16_t baseAddress); + +extern uint8_t MPY32_getSaturationMode(uint16_t baseAddress); + +extern void MPY32_enableFractionalMode(uint16_t baseAddress); + +extern void MPY32_disableFractionalMode(uint16_t baseAddress); + +extern uint8_t MPY32_getFractionalMode(uint16_t baseAddress); + +extern void MPY32_setOperandOne8Bit(uint16_t baseAddress, + uint8_t multiplicationType, + uint8_t operand); + +extern void MPY32_setOperandOne16Bit(uint16_t baseAddress, + uint8_t multiplicationType, + uint16_t operand); + +extern void MPY32_setOperandOne24Bit(uint16_t baseAddress, + uint8_t multiplicationType, + uint32_t operand); + +extern void MPY32_setOperandOne32Bit(uint16_t baseAddress, + uint8_t multiplicationType, + uint32_t operand); + +extern void MPY32_setOperandTwo8Bit(uint16_t baseAddress, + uint8_t operand); + +extern void MPY32_setOperandTwo16Bit(uint16_t baseAddress, + uint16_t operand); + +extern void MPY32_setOperandTwo24Bit(uint16_t baseAddress, + uint32_t operand); + +extern void MPY32_setOperandTwo32Bit(uint16_t baseAddress, + uint32_t operand); + +extern uint8_t MPY32_getResult8Bit(uint16_t baseAddress); + +extern uint16_t MPY32_getResult16Bit(uint16_t baseAddress); + +extern uint32_t MPY32_getResult24Bit(uint16_t baseAddress); + +extern uint32_t MPY32_getResult32Bit(uint16_t baseAddress); + +extern uint64 MPY32_getResult64Bit(uint16_t baseAddress); + +extern uint64_t MPY32_getResult(uint16_t baseAddress); + +extern uint16_t MPY32_getSumExtension(uint16_t baseAddress); + +extern uint16_t MPY32_getCarryBitValue(uint16_t baseAddress); + +extern void MPY32_clearCarryBitValue(uint16_t baseAddress); + +extern void MPY32_preloadResult(uint16_t baseAddress, + uint64_t result); + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +#define MPY32_setFractionMode MPY32_enableFractionalMode + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +#define MPY32_resetFractionMode MPY32_disableFractionalMode + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +#define MPY32_setSaturationMode MPY32_enableSaturationMode + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +#define MPY32_resetSaturationMode MPY32_disableSaturationMode + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_MPY32_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/deprecated/pmm.c b/source/driverlib/MSP430F5xx_6xx/deprecated/pmm.c new file mode 100644 index 0000000..017c2ca --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/deprecated/pmm.c @@ -0,0 +1,988 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// pmm.c - Driver for the pmm Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup pmm_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef DRIVERLIB_LEGACY_MODE + +#ifdef __MSP430_HAS_PMM__ +#include "pmm.h" + +#include + +//***************************************************************************** +// +//! \brief Enables the low-side SVS circuitry +//! +//! \param baseAddress is the base address of the PMM module. +//! +//! Modified bits of \b PMMCTL0 register and bits of \b SVSMLCTL register. +//! +//! \return None +// +//***************************************************************************** +void PMM_enableSvsL (uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0xA5; + HWREG16(baseAddress + OFS_SVSMLCTL) |= SVSLE; + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Disables the low-side SVS circuitry +//! +//! \param baseAddress is the base address of the PMM module. +//! +//! Modified bits of \b PMMCTL0 register and bits of \b SVSMLCTL register. +//! +//! \return None +// +//***************************************************************************** +void PMM_disableSvsL (uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0xA5; + HWREG16(baseAddress + OFS_SVSMLCTL) &= ~SVSLE; + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Enables the low-side SVM circuitry +//! +//! \param baseAddress is the base address of the PMM module. +//! +//! Modified bits of \b PMMCTL0 register and bits of \b SVSMLCTL register. +//! +//! \return None +// +//***************************************************************************** +void PMM_enableSvmL (uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0xA5; + HWREG16(baseAddress + OFS_SVSMLCTL) |= SVMLE; + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Disables the low-side SVM circuitry +//! +//! \param baseAddress is the base address of the PMM module. +//! +//! Modified bits of \b PMMCTL0 register and bits of \b SVSMLCTL register. +//! +//! \return None +// +//***************************************************************************** +void PMM_disableSvmL (uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0xA5; + HWREG16(baseAddress + OFS_SVSMLCTL) &= ~SVMLE; + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Enables the high-side SVS circuitry +//! +//! \param baseAddress is the base address of the PMM module. +//! +//! Modified bits of \b PMMCTL0 register and bits of \b SVSMHCTL register. +//! +//! \return None +// +//***************************************************************************** +void PMM_enableSvsH (uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0xA5; + HWREG16(baseAddress + OFS_SVSMHCTL) |= SVSHE; + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Disables the high-side SVS circuitry +//! +//! \param baseAddress is the base address of the PMM module. +//! +//! Modified bits of \b PMMCTL0 register and bits of \b SVSMHCTL register. +//! +//! \return None +// +//***************************************************************************** +void PMM_disableSvsH (uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0xA5; + HWREG16(baseAddress + OFS_SVSMHCTL) &= ~SVSHE; + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Enables the high-side SVM circuitry +//! +//! \param baseAddress is the base address of the PMM module. +//! +//! Modified bits of \b PMMCTL0 register and bits of \b SVSMHCTL register. +//! +//! \return None +// +//***************************************************************************** +void PMM_enableSvmH (uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0xA5; + HWREG16(baseAddress + OFS_SVSMHCTL) |= SVMHE; + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Disables the high-side SVM circuitry +//! +//! \param baseAddress is the base address of the PMM module. +//! +//! Modified bits of \b PMMCTL0 register and bits of \b SVSMHCTL register. +//! +//! \return None +// +//***************************************************************************** +void PMM_disableSvmH (uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0xA5; + HWREG16(baseAddress + OFS_SVSMHCTL) &= ~SVMHE; + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Enables the low-side SVS and SVM circuitry +//! +//! \param baseAddress is the base address of the PMM module. +//! +//! Modified bits of \b PMMCTL0 register and bits of \b SVSMLCTL register. +//! +//! \return None +// +//***************************************************************************** +void PMM_enableSvsLSvmL (uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0xA5; + HWREG16(baseAddress + OFS_SVSMLCTL) |= (SVSLE + SVMLE); + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Disables the low-side SVS and SVM circuitry +//! +//! \param baseAddress is the base address of the PMM module. +//! +//! Modified bits of \b PMMCTL0 register and bits of \b SVSMLCTL register. +//! +//! \return None +// +//***************************************************************************** +void PMM_disableSvsLSvmL (uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0xA5; + HWREG16(baseAddress + OFS_SVSMLCTL) &= ~(SVSLE + SVMLE); + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Enables the high-side SVS and SVM circuitry +//! +//! \param baseAddress is the base address of the PMM module. +//! +//! Modified bits of \b PMMCTL0 register and bits of \b SVSMHCTL register. +//! +//! \return None +// +//***************************************************************************** +void PMM_enableSvsHSvmH (uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0xA5; + HWREG16(baseAddress + OFS_SVSMHCTL) |= (SVSHE + SVMHE); + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Disables the high-side SVS and SVM circuitry +//! +//! \param baseAddress is the base address of the PMM module. +//! +//! Modified bits of \b PMMCTL0 register and bits of \b SVSMHCTL register. +//! +//! \return None +// +//***************************************************************************** +void PMM_disableSvsHSvmH (uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0xA5; + HWREG16(baseAddress + OFS_SVSMHCTL) &= ~(SVSHE + SVMHE); + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Enables the POR signal generation when a low-voltage event is +//! registered by the low-side SVS +//! +//! \param baseAddress is the base address of the PMM module. +//! +//! Modified bits of \b PMMCTL0 register and bits of \b PMMIE register. +//! +//! \return None +// +//***************************************************************************** +void PMM_enableSvsLReset (uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0xA5; + HWREG16(baseAddress + OFS_PMMRIE) |= SVSLPE; + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Disables the POR signal generation when a low-voltage event is +//! registered by the low-side SVS +//! +//! \param baseAddress is the base address of the PMM module. +//! +//! Modified bits of \b PMMCTL0 register and bits of \b PMMIE register. +//! +//! \return None +// +//***************************************************************************** +void PMM_disableSvsLReset (uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0xA5; + HWREG16(baseAddress + OFS_PMMRIE) &= ~SVSLPE; + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Enables the interrupt generation when a low-voltage event is +//! registered by the low-side SVM +//! +//! \param baseAddress is the base address of the PMM module. +//! +//! Modified bits of \b PMMCTL0 register and bits of \b PMMIE register. +//! +//! \return None +// +//***************************************************************************** +void PMM_enableSvmLInterrupt (uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0xA5; + HWREG16(baseAddress + OFS_PMMRIE) |= SVMLIE; + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Disables the interrupt generation when a low-voltage event is +//! registered by the low-side SVM +//! +//! \param baseAddress is the base address of the PMM module. +//! +//! Modified bits of \b PMMCTL0 register and bits of \b PMMIE register. +//! +//! \return None +// +//***************************************************************************** +void PMM_disableSvmLInterrupt (uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0xA5; + HWREG16(baseAddress + OFS_PMMRIE) &= ~SVMLIE; + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Enables the POR signal generation when a low-voltage event is +//! registered by the high-side SVS +//! +//! \param baseAddress is the base address of the PMM module. +//! +//! Modified bits of \b PMMCTL0 register and bits of \b PMMIE register. +//! +//! \return None +// +//***************************************************************************** +void PMM_enableSvsHReset (uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0xA5; + HWREG16(baseAddress + OFS_PMMRIE) |= SVSHPE; + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Disables the POR signal generation when a low-voltage event is +//! registered by the high-side SVS +//! +//! \param baseAddress is the base address of the PMM module. +//! +//! Modified bits of \b PMMCTL0 register and bits of \b PMMIE register. +//! +//! \return None +// +//***************************************************************************** +void PMM_disableSvsHReset (uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0xA5; + HWREG16(baseAddress + OFS_PMMRIE) &= ~SVSHPE; + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Enables the interrupt generation when a low-voltage event is +//! registered by the high-side SVM +//! +//! \param baseAddress is the base address of the PMM module. +//! +//! Modified bits of \b PMMCTL0 register and bits of \b PMMIE register. +//! +//! \return None +// +//***************************************************************************** +void PMM_enableSvmHInterrupt (uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0xA5; + HWREG16(baseAddress + OFS_PMMRIE) |= SVMHIE; + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Disables the interrupt generation when a low-voltage event is +//! registered by the high-side SVM +//! +//! \param baseAddress is the base address of the PMM module. +//! +//! Modified bits of \b PMMCTL0 register and bits of \b PMMIE register. +//! +//! \return None +// +//***************************************************************************** +void PMM_disableSvmHInterrupt (uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0xA5; + HWREG16(baseAddress + OFS_PMMRIE) &= ~SVMHIE; + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Clear all interrupt flags for the PMM +//! +//! \param baseAddress is the base address of the PMM module. +//! +//! Modified bits of \b PMMCTL0 register and bits of \b PMMIFG register. +//! +//! \return None +// +//***************************************************************************** +void PMM_clearPMMIFGS (uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0xA5; + HWREG16(baseAddress + OFS_PMMIFG) = 0; + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Enables supervisor low side in LPM with twake-up-fast from LPM2, +//! LPM3, and LPM4 +//! +//! \param baseAddress is the base address of the PMM module. +//! +//! Modified bits of \b PMMCTL0 register and bits of \b SVSMLCTL register. +//! +//! \return None +// +//***************************************************************************** +void PMM_SvsLEnabledInLPMFastWake (uint16_t baseAddress) +{ + //These settings use SVSH/LACE = 0 + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0xA5; + HWREG16(baseAddress + OFS_SVSMLCTL) |= (SVSLFP + SVSLMD); + HWREG16(baseAddress + OFS_SVSMLCTL) &= ~SVSMLACE; + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Enables supervisor low side in LPM with twake-up-slow from LPM2, +//! LPM3, and LPM4 +//! +//! \param baseAddress is the base address of the PMM module. +//! +//! Modified bits of \b PMMCTL0 register and bits of \b SVSMLCTL register. +//! +//! \return None +// +//***************************************************************************** +void PMM_SvsLEnabledInLPMSlowWake (uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0xA5; + HWREG16(baseAddress + OFS_SVSMLCTL) |= SVSLMD; + HWREG16(baseAddress + OFS_SVSMLCTL) &= ~(SVSLFP + SVSMLACE); + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Disables supervisor low side in LPM with twake-up-fast from LPM2, +//! LPM3, and LPM4 +//! +//! \param baseAddress is the base address of the PMM module. +//! +//! Modified bits of \b PMMCTL0 register and bits of \b SVSMLCTL register. +//! +//! \return None +// +//***************************************************************************** +void PMM_SvsLDisabledInLPMFastWake (uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0xA5; + HWREG16(baseAddress + OFS_SVSMLCTL) |= SVSLFP; + HWREG16(baseAddress + OFS_SVSMLCTL) &= ~(SVSLMD + SVSMLACE); + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Disables supervisor low side in LPM with twake-up-slow from LPM2, +//! LPM3, and LPM4 +//! +//! \param baseAddress is the base address of the PMM module. +//! +//! Modified bits of \b PMMCTL0 register and bits of \b SVSMLCTL register. +//! +//! \return None +// +//***************************************************************************** +void PMM_SvsLDisabledInLPMSlowWake (uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0xA5; + HWREG16(baseAddress + OFS_SVSMLCTL) &= ~(SVSLFP + SVSMLACE + SVSLMD); + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Enables supervisor high side in LPM with tpd = 20 ?s(1) +//! +//! \param baseAddress is the base address of the PMM module. +//! +//! Modified bits of \b PMMCTL0 register and bits of \b SVSMHCTL register. +//! +//! \return None +// +//***************************************************************************** +void PMM_SvsHEnabledInLPMNormPerf (uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0xA5; + HWREG16(baseAddress + OFS_SVSMHCTL) |= SVSHMD; + HWREG16(baseAddress + OFS_SVSMHCTL) &= ~(SVSMHACE + SVSHFP); + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Enables supervisor high side in LPM with tpd = 2.5 ?s(1) +//! +//! \param baseAddress is the base address of the PMM module. +//! +//! Modified bits of \b PMMCTL0 register and bits of \b SVSMHCTL register. +//! +//! \return None +// +//***************************************************************************** +void PMM_SvsHEnabledInLPMFullPerf (uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0xA5; + HWREG16(baseAddress + OFS_SVSMHCTL) |= (SVSHMD + SVSHFP); + HWREG16(baseAddress + OFS_SVSMHCTL) &= ~SVSMHACE; + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Disables supervisor high side in LPM with tpd = 20 ?s(1) +//! +//! \param baseAddress is the base address of the PMM module. +//! +//! Modified bits of \b PMMCTL0 register and bits of \b SVSMHCTL register. +//! +//! \return None +// +//***************************************************************************** +void PMM_SvsHDisabledInLPMNormPerf (uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0xA5; + HWREG16(baseAddress + OFS_SVSMHCTL) &= ~(SVSMHACE + SVSHFP + SVSHMD); + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Disables supervisor high side in LPM with tpd = 2.5 ?s(1) +//! +//! \param baseAddress is the base address of the PMM module. +//! +//! Modified bits of \b PMMCTL0 register and bits of \b SVSMHCTL register. +//! +//! \return None +// +//***************************************************************************** +void PMM_SvsHDisabledInLPMFullPerf (uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0xA5; + HWREG16(baseAddress + OFS_SVSMHCTL) |= SVSHFP; + HWREG16(baseAddress + OFS_SVSMHCTL) &= ~(SVSMHACE + SVSHMD); + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Optimized to provide twake-up-fast from LPM2, LPM3, and LPM4 with +//! least power +//! +//! \param baseAddress is the base address of the PMM module. +//! +//! Modified bits of \b PMMCTL0 register and bits of \b SVSMLCTL register. +//! +//! \return None +// +//***************************************************************************** +void PMM_SvsLOptimizedInLPMFastWake (uint16_t baseAddress) +{ + //These setting use SVSH/LACE = 1 + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0xA5; + HWREG16(baseAddress + OFS_SVSMLCTL) |= (SVSLFP + SVSLMD + SVSMLACE); + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Optimized to provide tpd = 2.5 ?s(1) in LPM with least power +//! +//! \param baseAddress is the base address of the PMM module. +//! +//! Modified bits of \b PMMCTL0 register and bits of \b SVSMLCTL register. +//! +//! \return None +// +//***************************************************************************** +void PMM_SvsHOptimizedInLPMFullPerf (uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0xA5; + HWREG16(baseAddress + OFS_SVSMHCTL) |= (SVSHMD + SVSHFP + SVSMHACE); + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Increase Vcore by one level +//! +//! \param baseAddress is the base address of the PMM module. +//! \param level level to which Vcore needs to be increased +//! Valid values are: +//! - \b PMM_CORE_LEVEL_0 [Default] +//! - \b PMM_CORE_LEVEL_1 +//! - \b PMM_CORE_LEVEL_2 +//! - \b PMM_CORE_LEVEL_3 +//! +//! Modified bits of \b PMMCTL0 register, bits of \b PMMIFG register, bits of +//! \b PMMRIE register, bits of \b SVSMHCTL register and bits of \b SVSMLCTL +//! register. +//! +//! \return STATUS_SUCCESS or STATUS_FAIL +// +//***************************************************************************** +uint16_t PMM_setVCoreUp (uint16_t baseAddress, uint8_t level) +{ + uint32_t PMMRIE_backup, SVSMHCTL_backup, SVSMLCTL_backup; + + //The code flow for increasing the Vcore has been altered to work around + //the erratum FLASH37. + //Please refer to the Errata sheet to know if a specific device is affected + //DO NOT ALTER THIS FUNCTION + + //Open PMM registers for write access + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0xA5; + + //Disable dedicated Interrupts + //Backup all registers + PMMRIE_backup = HWREG16(baseAddress + OFS_PMMRIE); + HWREG16(baseAddress + OFS_PMMRIE) &= ~(SVMHVLRPE | SVSHPE | SVMLVLRPE | + SVSLPE | SVMHVLRIE | SVMHIE | + SVSMHDLYIE | SVMLVLRIE | SVMLIE | + SVSMLDLYIE + ); + SVSMHCTL_backup = HWREG16(baseAddress + OFS_SVSMHCTL); + SVSMLCTL_backup = HWREG16(baseAddress + OFS_SVSMLCTL); + + //Clear flags + HWREG16(baseAddress + OFS_PMMIFG) = 0; + + //Set SVM highside to new level and check if a VCore increase is possible + HWREG16(baseAddress + OFS_SVSMHCTL) = SVMHE | SVSHE | (SVSMHRRL0 * level); + + //Wait until SVM highside is settled + while ((HWREG16(baseAddress + OFS_PMMIFG) & SVSMHDLYIFG) == 0) ; + + //Clear flag + HWREG16(baseAddress + OFS_PMMIFG) &= ~SVSMHDLYIFG; + + //Check if a VCore increase is possible + if ((HWREG16(baseAddress + OFS_PMMIFG) & SVMHIFG) == SVMHIFG){ + //-> Vcc is too low for a Vcore increase + //recover the previous settings + HWREG16(baseAddress + OFS_PMMIFG) &= ~SVSMHDLYIFG; + HWREG16(baseAddress + OFS_SVSMHCTL) = SVSMHCTL_backup; + + //Wait until SVM highside is settled + while ((HWREG16(baseAddress + OFS_PMMIFG) & SVSMHDLYIFG) == 0) ; + + //Clear all Flags + HWREG16(baseAddress + + OFS_PMMIFG) &= ~(SVMHVLRIFG | SVMHIFG | SVSMHDLYIFG | + SVMLVLRIFG | SVMLIFG | + SVSMLDLYIFG + ); + + //Restore PMM interrupt enable register + HWREG16(baseAddress + OFS_PMMRIE) = PMMRIE_backup; + //Lock PMM registers for write access + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; + //return: voltage not set + return ( STATUS_FAIL) ; + } + + //Set also SVS highside to new level + //Vcc is high enough for a Vcore increase + HWREG16(baseAddress + OFS_SVSMHCTL) |= (SVSHRVL0 * level); + + //Wait until SVM highside is settled + while ((HWREG16(baseAddress + OFS_PMMIFG) & SVSMHDLYIFG) == 0) ; + + //Clear flag + HWREG16(baseAddress + OFS_PMMIFG) &= ~SVSMHDLYIFG; + + //Set VCore to new level + HWREG8(baseAddress + OFS_PMMCTL0_L) = PMMCOREV0 * level; + + //Set SVM, SVS low side to new level + HWREG16(baseAddress + OFS_SVSMLCTL) = SVMLE | (SVSMLRRL0 * level) | + SVSLE | (SVSLRVL0 * level); + + //Wait until SVM, SVS low side is settled + while ((HWREG16(baseAddress + OFS_PMMIFG) & SVSMLDLYIFG) == 0) ; + + //Clear flag + HWREG16(baseAddress + OFS_PMMIFG) &= ~SVSMLDLYIFG; + //SVS, SVM core and high side are now set to protect for the new core level + + //Restore Low side settings + //Clear all other bits _except_ level settings + HWREG16(baseAddress + OFS_SVSMLCTL) &= (SVSLRVL0 + SVSLRVL1 + SVSMLRRL0 + + SVSMLRRL1 + SVSMLRRL2 + ); + + //Clear level settings in the backup register,keep all other bits + SVSMLCTL_backup &= + ~(SVSLRVL0 + SVSLRVL1 + SVSMLRRL0 + SVSMLRRL1 + SVSMLRRL2); + + //Restore low-side SVS monitor settings + HWREG16(baseAddress + OFS_SVSMLCTL) |= SVSMLCTL_backup; + + //Restore High side settings + //Clear all other bits except level settings + HWREG16(baseAddress + OFS_SVSMHCTL) &= (SVSHRVL0 + SVSHRVL1 + + SVSMHRRL0 + SVSMHRRL1 + + SVSMHRRL2 + ); + + //Clear level settings in the backup register,keep all other bits + SVSMHCTL_backup &= + ~(SVSHRVL0 + SVSHRVL1 + SVSMHRRL0 + SVSMHRRL1 + SVSMHRRL2); + + //Restore backup + HWREG16(baseAddress + OFS_SVSMHCTL) |= SVSMHCTL_backup; + + //Wait until high side, low side settled + while (((HWREG16(baseAddress + OFS_PMMIFG) & SVSMLDLYIFG) == 0) || + ((HWREG16(baseAddress + OFS_PMMIFG) & SVSMHDLYIFG) == 0)) ; + + //Clear all Flags + HWREG16(baseAddress + OFS_PMMIFG) &= ~(SVMHVLRIFG | SVMHIFG | SVSMHDLYIFG | + SVMLVLRIFG | SVMLIFG | SVSMLDLYIFG + ); + + //Restore PMM interrupt enable register + HWREG16(baseAddress + OFS_PMMRIE) = PMMRIE_backup; + + //Lock PMM registers for write access + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; + + return ( STATUS_SUCCESS) ; +} + +//***************************************************************************** +// +//! \brief Decrease Vcore by one level +//! +//! \param baseAddress is the base address of the PMM module. +//! \param level level to which Vcore needs to be decreased +//! Valid values are: +//! - \b PMM_CORE_LEVEL_0 [Default] +//! - \b PMM_CORE_LEVEL_1 +//! - \b PMM_CORE_LEVEL_2 +//! - \b PMM_CORE_LEVEL_3 +//! +//! Modified bits of \b PMMCTL0 register, bits of \b PMMIFG register, bits of +//! \b PMMRIE register, bits of \b SVSMHCTL register and bits of \b SVSMLCTL +//! register. +//! +//! \return STATUS_SUCCESS +// +//***************************************************************************** +uint16_t PMM_setVCoreDown (uint16_t baseAddress, uint8_t level) +{ + uint32_t PMMRIE_backup, SVSMHCTL_backup, SVSMLCTL_backup; + + //The code flow for decreasing the Vcore has been altered to work around + //the erratum FLASH37. + //Please refer to the Errata sheet to know if a specific device is affected + //DO NOT ALTER THIS FUNCTION + + //Open PMM registers for write access + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0xA5; + + //Disable dedicated Interrupts + //Backup all registers + PMMRIE_backup = HWREG16(baseAddress + OFS_PMMRIE); + HWREG16(baseAddress + OFS_PMMRIE) &= ~(SVMHVLRPE | SVSHPE | SVMLVLRPE | + SVSLPE | SVMHVLRIE | SVMHIE | + SVSMHDLYIE | SVMLVLRIE | SVMLIE | + SVSMLDLYIE + ); + SVSMHCTL_backup = HWREG16(baseAddress + OFS_SVSMHCTL); + SVSMLCTL_backup = HWREG16(baseAddress + OFS_SVSMLCTL); + + //Clear flags + HWREG16(baseAddress + OFS_PMMIFG) &= ~(SVMHIFG | SVSMHDLYIFG | + SVMLIFG | SVSMLDLYIFG + ); + + //Set SVM, SVS high & low side to new settings in normal mode + HWREG16(baseAddress + OFS_SVSMHCTL) = SVMHE | (SVSMHRRL0 * level) | + SVSHE | (SVSHRVL0 * level); + HWREG16(baseAddress + OFS_SVSMLCTL) = SVMLE | (SVSMLRRL0 * level) | + SVSLE | (SVSLRVL0 * level); + + //Wait until SVM high side and SVM low side is settled + while ((HWREG16(baseAddress + OFS_PMMIFG) & SVSMHDLYIFG) == 0 || + (HWREG16(baseAddress + OFS_PMMIFG) & SVSMLDLYIFG) == 0) ; + + //Clear flags + HWREG16(baseAddress + OFS_PMMIFG) &= ~(SVSMHDLYIFG + SVSMLDLYIFG); + //SVS, SVM core and high side are now set to protect for the new core level + + //Set VCore to new level + HWREG8(baseAddress + OFS_PMMCTL0_L) = PMMCOREV0 * level; + + //Restore Low side settings + //Clear all other bits _except_ level settings + HWREG16(baseAddress + OFS_SVSMLCTL) &= (SVSLRVL0 + SVSLRVL1 + SVSMLRRL0 + + SVSMLRRL1 + SVSMLRRL2 + ); + + //Clear level settings in the backup register,keep all other bits + SVSMLCTL_backup &= + ~(SVSLRVL0 + SVSLRVL1 + SVSMLRRL0 + SVSMLRRL1 + SVSMLRRL2); + + //Restore low-side SVS monitor settings + HWREG16(baseAddress + OFS_SVSMLCTL) |= SVSMLCTL_backup; + + //Restore High side settings + //Clear all other bits except level settings + HWREG16(baseAddress + OFS_SVSMHCTL) &= (SVSHRVL0 + SVSHRVL1 + SVSMHRRL0 + + SVSMHRRL1 + SVSMHRRL2 + ); + + //Clear level settings in the backup register, keep all other bits + SVSMHCTL_backup &= + ~(SVSHRVL0 + SVSHRVL1 + SVSMHRRL0 + SVSMHRRL1 + SVSMHRRL2); + + //Restore backup + HWREG16(baseAddress + OFS_SVSMHCTL) |= SVSMHCTL_backup; + + //Wait until high side, low side settled + while (((HWREG16(baseAddress + OFS_PMMIFG) & SVSMLDLYIFG) == 0) || + ((HWREG16(baseAddress + OFS_PMMIFG) & SVSMHDLYIFG) == 0)) ; + + //Clear all Flags + HWREG16(baseAddress + OFS_PMMIFG) &= ~(SVMHVLRIFG | SVMHIFG | SVSMHDLYIFG | + SVMLVLRIFG | SVMLIFG | SVSMLDLYIFG + ); + + //Restore PMM interrupt enable register + HWREG16(baseAddress + OFS_PMMRIE) = PMMRIE_backup; + //Lock PMM registers for write access + HWREG8(baseAddress + OFS_PMMCTL0_H) = 0x00; + //Return: OK + return ( STATUS_SUCCESS) ; +} + +//***************************************************************************** +// +//! \brief Set Vcore to expected level +//! +//! \param baseAddress is the base address of the PMM module. +//! \param level level to which Vcore needs to be decreased/increased +//! Valid values are: +//! - \b PMM_CORE_LEVEL_0 [Default] +//! - \b PMM_CORE_LEVEL_1 +//! - \b PMM_CORE_LEVEL_2 +//! - \b PMM_CORE_LEVEL_3 +//! +//! Modified bits of \b PMMCTL0 register, bits of \b PMMIFG register, bits of +//! \b PMMRIE register, bits of \b SVSMHCTL register and bits of \b SVSMLCTL +//! register. +//! +//! \return STATUS_SUCCESS or STATUS_FAIL +// +//***************************************************************************** +bool PMM_setVCore (uint16_t baseAddress, uint8_t level) +{ + assert( + (PMM_CORE_LEVEL_0 == level) || + (PMM_CORE_LEVEL_1 == level) || + (PMM_CORE_LEVEL_2 == level) || + (PMM_CORE_LEVEL_3 == level) + ); + + uint8_t actlevel; + bool status = STATUS_SUCCESS; + + //Set Mask for Max. level + level &= PMMCOREV_3; + + //Get actual VCore + actlevel = (HWREG16(baseAddress + OFS_PMMCTL0) & PMMCOREV_3); + + //step by step increase or decrease + while ((level != actlevel) && (status == STATUS_SUCCESS)) + { + if (level > actlevel){ + status = PMM_setVCoreUp(baseAddress, ++actlevel); + } else { + status = PMM_setVCoreDown(baseAddress, --actlevel); + } + } + + return ( status) ; +} + +//***************************************************************************** +// +//! \brief Returns interrupt status +//! +//! \param baseAddress is the base address of the PMM module. +//! \param mask is the mask for specifying the required flag +//! Mask value is the logical OR of any of the following: +//! - \b PMM_SVSMLDLYIFG +//! - \b PMM_SVMLIFG +//! - \b PMM_SVMLVLRIFG +//! - \b PMM_SVSMHDLYIFG +//! - \b PMM_SVMHIFG +//! - \b PMM_SVMHVLRIFG +//! - \b PMM_PMMBORIFG +//! - \b PMM_PMMRSTIFG +//! - \b PMM_PMMPORIFG +//! - \b PMM_SVSHIFG +//! - \b PMM_SVSLIFG +//! - \b PMM_PMMLPM5IFG +//! +//! \return Logical OR of any of the following: +//! - \b PMM_SVSMLDLYIFG +//! - \b PMM_SVMLIFG +//! - \b PMM_SVMLVLRIFG +//! - \b PMM_SVSMHDLYIFG +//! - \b PMM_SVMHIFG +//! - \b PMM_SVMHVLRIFG +//! - \b PMM_PMMBORIFG +//! - \b PMM_PMMRSTIFG +//! - \b PMM_PMMPORIFG +//! - \b PMM_SVSHIFG +//! - \b PMM_SVSLIFG +//! - \b PMM_PMMLPM5IFG +//! \n indicating the status of the masked interrupts +// +//***************************************************************************** +uint16_t PMM_getInterruptStatus (uint16_t baseAddress, + uint16_t mask) +{ + return ( (HWREG16(baseAddress + OFS_PMMIFG)) & mask ); +} + +#endif +#endif +//***************************************************************************** +// +//! Close the doxygen group for pmm_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/deprecated/pmm.h b/source/driverlib/MSP430F5xx_6xx/deprecated/pmm.h new file mode 100644 index 0000000..d6bf410 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/deprecated/pmm.h @@ -0,0 +1,176 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// pmm.h - Driver for the PMM Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_PMM_H__ +#define __MSP430WARE_PMM_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_PMM__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the level parameter for +// functions: PMM_setVCoreUp(), PMM_setVCoreDown(), and PMM_setVCore(). +// +//***************************************************************************** +#define PMM_CORE_LEVEL_0 PMMCOREV_0 +#define PMM_CORE_LEVEL_1 PMMCOREV_1 +#define PMM_CORE_LEVEL_2 PMMCOREV_2 +#define PMM_CORE_LEVEL_3 PMMCOREV_3 + +//***************************************************************************** +// +// The following are values that can be passed to the mask parameter for +// functions: PMM_getInterruptStatus() as well as returned by the +// PMM_getInterruptStatus() function. +// +//***************************************************************************** +#define PMM_SVSMLDLYIFG SVSMLDLYIFG +#define PMM_SVMLIFG SVMLIFG +#define PMM_SVMLVLRIFG SVMLVLRIFG +#define PMM_SVSMHDLYIFG SVSMHDLYIFG +#define PMM_SVMHIFG SVMHIFG +#define PMM_SVMHVLRIFG SVMHVLRIFG +#define PMM_PMMBORIFG PMMBORIFG +#define PMM_PMMRSTIFG PMMRSTIFG +#define PMM_PMMPORIFG PMMPORIFG +#define PMM_SVSHIFG SVSHIFG +#define PMM_SVSLIFG SVSLIFG +#define PMM_PMMLPM5IFG PMMLPM5IFG + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void PMM_enableSvsL(uint16_t baseAddress); + +extern void PMM_disableSvsL(uint16_t baseAddress); + +extern void PMM_enableSvmL(uint16_t baseAddress); + +extern void PMM_disableSvmL(uint16_t baseAddress); + +extern void PMM_enableSvsH(uint16_t baseAddress); + +extern void PMM_disableSvsH(uint16_t baseAddress); + +extern void PMM_enableSvmH(uint16_t baseAddress); + +extern void PMM_disableSvmH(uint16_t baseAddress); + +extern void PMM_enableSvsLSvmL(uint16_t baseAddress); + +extern void PMM_disableSvsLSvmL(uint16_t baseAddress); + +extern void PMM_enableSvsHSvmH(uint16_t baseAddress); + +extern void PMM_disableSvsHSvmH(uint16_t baseAddress); + +extern void PMM_enableSvsLReset(uint16_t baseAddress); + +extern void PMM_disableSvsLReset(uint16_t baseAddress); + +extern void PMM_enableSvmLInterrupt(uint16_t baseAddress); + +extern void PMM_disableSvmLInterrupt(uint16_t baseAddress); + +extern void PMM_enableSvsHReset(uint16_t baseAddress); + +extern void PMM_disableSvsHReset(uint16_t baseAddress); + +extern void PMM_enableSvmHInterrupt(uint16_t baseAddress); + +extern void PMM_disableSvmHInterrupt(uint16_t baseAddress); + +extern void PMM_clearPMMIFGS(uint16_t baseAddress); + +extern void PMM_SvsLEnabledInLPMFastWake(uint16_t baseAddress); + +extern void PMM_SvsLEnabledInLPMSlowWake(uint16_t baseAddress); + +extern void PMM_SvsLDisabledInLPMFastWake(uint16_t baseAddress); + +extern void PMM_SvsLDisabledInLPMSlowWake(uint16_t baseAddress); + +extern void PMM_SvsHEnabledInLPMNormPerf(uint16_t baseAddress); + +extern void PMM_SvsHEnabledInLPMFullPerf(uint16_t baseAddress); + +extern void PMM_SvsHDisabledInLPMNormPerf(uint16_t baseAddress); + +extern void PMM_SvsHDisabledInLPMFullPerf(uint16_t baseAddress); + +extern void PMM_SvsLOptimizedInLPMFastWake(uint16_t baseAddress); + +extern void PMM_SvsHOptimizedInLPMFullPerf(uint16_t baseAddress); + +extern uint16_t PMM_setVCoreUp(uint16_t baseAddress, + uint8_t level); + +extern uint16_t PMM_setVCoreDown(uint16_t baseAddress, + uint8_t level); + +extern bool PMM_setVCore(uint16_t baseAddress, + uint8_t level); + +extern uint16_t PMM_getInterruptStatus(uint16_t baseAddress, + uint16_t mask); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_PMM_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/deprecated/ram.c b/source/driverlib/MSP430F5xx_6xx/deprecated/ram.c new file mode 100644 index 0000000..5daeede --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/deprecated/ram.c @@ -0,0 +1,144 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// ram.c - Driver for the ram Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup ram_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef DRIVERLIB_LEGACY_MODE + +#ifdef __MSP430_HAS_RC__ +#include "ram.h" + +#include + +//***************************************************************************** +// +//! \brief Set specified RAM sector off +//! +//! \param baseAddress is the base address of the RAM module. +//! \param sector is specified sector to be set off. +//! Mask value is the logical OR of any of the following: +//! - \b RAM_SECTOR0 +//! - \b RAM_SECTOR1 +//! - \b RAM_SECTOR2 +//! - \b RAM_SECTOR3 +//! - \b RAM_SECTOR4 +//! - \b RAM_SECTOR5 +//! - \b RAM_SECTOR6 +//! - \b RAM_SECTOR7 +//! +//! Modified bits of \b RCCTL0 register. +//! +//! \return None +// +//***************************************************************************** +void RAM_setSectorOff (uint16_t baseAddress, + uint8_t sector + ) +{ + assert(0x00 == sector & (~(RAM_SECTOR0 + + RAM_SECTOR1 + + RAM_SECTOR2 + + RAM_SECTOR3 + ) + ) + + ); + //Write key to start write to RCCTL0 and sector + HWREG16(baseAddress + OFS_RCCTL0) = (RCKEY + sector); +} + +//***************************************************************************** +// +//! \brief Get RAM sector ON/OFF status +//! +//! \param baseAddress is the base address of the RAM module. +//! \param sector is specified sector +//! Mask value is the logical OR of any of the following: +//! - \b RAM_SECTOR0 +//! - \b RAM_SECTOR1 +//! - \b RAM_SECTOR2 +//! - \b RAM_SECTOR3 +//! - \b RAM_SECTOR4 +//! - \b RAM_SECTOR5 +//! - \b RAM_SECTOR6 +//! - \b RAM_SECTOR7 +//! +//! Modified bits of \b RCCTL0 register. +//! +//! \return Logical OR of any of the following: +//! - \b RAM_SECTOR0 +//! - \b RAM_SECTOR1 +//! - \b RAM_SECTOR2 +//! - \b RAM_SECTOR3 +//! - \b RAM_SECTOR4 +//! - \b RAM_SECTOR5 +//! - \b RAM_SECTOR6 +//! - \b RAM_SECTOR7 +//! \n indicating the status of the masked sectors +// +//***************************************************************************** +uint8_t RAM_getSectorState (uint16_t baseAddress, + uint8_t sector + ) +{ + assert(0x00 == sector & (~(RAM_SECTOR0 + + RAM_SECTOR1 + + RAM_SECTOR2 + + RAM_SECTOR3 + ) + ) + + ); + return (HWREG8(baseAddress + OFS_RCCTL0_L) & sector); +} + +#endif +#endif +//***************************************************************************** +// +//! Close the doxygen group for ram_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/deprecated/ram.h b/source/driverlib/MSP430F5xx_6xx/deprecated/ram.h new file mode 100644 index 0000000..62af8bf --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/deprecated/ram.h @@ -0,0 +1,93 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// ram.h - Driver for the RAM Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_RAM_H__ +#define __MSP430WARE_RAM_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_RC__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the sector parameter for +// functions: RAM_setSectorOff(), and RAM_getSectorState() as well as returned +// by the RAM_getSectorState() function. +// +//***************************************************************************** +#define RAM_SECTOR0 RCRS0OFF +#define RAM_SECTOR1 RCRS1OFF +#define RAM_SECTOR2 RCRS2OFF +#define RAM_SECTOR3 RCRS3OFF +#define RAM_SECTOR4 RCRS4OFF +#define RAM_SECTOR5 RCRS5OFF +#define RAM_SECTOR6 RCRS6OFF +#define RAM_SECTOR7 RCRS7OFF + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void RAM_setSectorOff(uint16_t baseAddress, + uint8_t sector); + +extern uint8_t RAM_getSectorState(uint16_t baseAddress, + uint8_t sector); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_RAM_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/deprecated/sfr.c b/source/driverlib/MSP430F5xx_6xx/deprecated/sfr.c new file mode 100644 index 0000000..163628c --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/deprecated/sfr.c @@ -0,0 +1,287 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// sfr.c - Driver for the sfr Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup sfr_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef DRIVERLIB_LEGACY_MODE + +#ifdef __MSP430_HAS_SFR__ +#include "sfr.h" + +#include + +//***************************************************************************** +// +//! \brief Enables selected SFR interrupt sources. +//! +//! This function enables the selected SFR interrupt sources. Only the sources +//! that are enabled can be reflected to the processor interrupt; disabled +//! sources have no effect on the processor. +//! +//! \param baseAddress is the Base Address of the SFR Module. +//! \param interruptMask is the bit mask of interrupts that will be enabled. +//! Mask value is the logical OR of any of the following: +//! - \b SFR_JTAG_OUTBOX_INTERRUPT - JTAG outbox interrupt enable +//! - \b SFR_JTAG_INBOX_INTERRUPT - JTAG inbox interrupt enable +//! - \b SFR_NMI_PIN_INTERRUPT - NMI pin interrupt enable, if NMI +//! function is chosen +//! - \b SFR_VACANT_MEMORY_ACCESS_INTERRUPT - Vacant memory access +//! interrupt enable +//! - \b SFR_OSCILLATOR_FAULT_INTERRUPT - Oscillator fault interrupt +//! enable +//! - \b SFR_WATCHDOG_INTERVAL_TIMER_INTERRUPT - Watchdog interval timer +//! interrupt enable +//! - \b SFR_FLASH_CONTROLLER_ACCESS_VIOLATION_INTERRUPT - Flash +//! controller access violation interrupt enable +//! +//! \return None +// +//***************************************************************************** +void SFR_enableInterrupt (uint16_t baseAddress, + uint8_t interruptMask) +{ + HWREG8(baseAddress + OFS_SFRIE1_L) |= interruptMask; +} + +//***************************************************************************** +// +//! \brief Disables selected SFR interrupt sources. +//! +//! This function disables the selected SFR interrupt sources. Only the sources +//! that are enabled can be reflected to the processor interrupt; disabled +//! sources have no effect on the processor. +//! +//! \param baseAddress is the Base Address of the SFR Module. +//! \param interruptMask is the bit mask of interrupts that will be disabled. +//! Mask value is the logical OR of any of the following: +//! - \b SFR_JTAG_OUTBOX_INTERRUPT - JTAG outbox interrupt enable +//! - \b SFR_JTAG_INBOX_INTERRUPT - JTAG inbox interrupt enable +//! - \b SFR_NMI_PIN_INTERRUPT - NMI pin interrupt enable, if NMI +//! function is chosen +//! - \b SFR_VACANT_MEMORY_ACCESS_INTERRUPT - Vacant memory access +//! interrupt enable +//! - \b SFR_OSCILLATOR_FAULT_INTERRUPT - Oscillator fault interrupt +//! enable +//! - \b SFR_WATCHDOG_INTERVAL_TIMER_INTERRUPT - Watchdog interval timer +//! interrupt enable +//! - \b SFR_FLASH_CONTROLLER_ACCESS_VIOLATION_INTERRUPT - Flash +//! controller access violation interrupt enable +//! +//! \return None +// +//***************************************************************************** +void SFR_disableInterrupt (uint16_t baseAddress, + uint8_t interruptMask) +{ + HWREG8(baseAddress + OFS_SFRIE1_L) &= ~(interruptMask); +} + +//***************************************************************************** +// +//! \brief Returns the status of the selected SFR interrupt flags. +//! +//! This function returns the status of the selected SFR interrupt flags in a +//! bit mask format matching that passed into the interruptFlagMask parameter. +//! +//! \param baseAddress is the Base Address of the SFR Module. +//! \param interruptFlagMask is the bit mask of interrupt flags that the status +//! of should be returned. +//! Mask value is the logical OR of any of the following: +//! - \b SFR_JTAG_OUTBOX_INTERRUPT - JTAG outbox interrupt enable +//! - \b SFR_JTAG_INBOX_INTERRUPT - JTAG inbox interrupt enable +//! - \b SFR_NMI_PIN_INTERRUPT - NMI pin interrupt enable, if NMI +//! function is chosen +//! - \b SFR_VACANT_MEMORY_ACCESS_INTERRUPT - Vacant memory access +//! interrupt enable +//! - \b SFR_OSCILLATOR_FAULT_INTERRUPT - Oscillator fault interrupt +//! enable +//! - \b SFR_WATCHDOG_INTERVAL_TIMER_INTERRUPT - Watchdog interval timer +//! interrupt enable +//! - \b SFR_FLASH_CONTROLLER_ACCESS_VIOLATION_INTERRUPT - Flash +//! controller access violation interrupt enable +//! +//! \return Logical OR of any of the following: +//! - \b SFR_JTAG_OUTBOX_INTERRUPT JTAG outbox interrupt enable +//! - \b SFR_JTAG_INBOX_INTERRUPT JTAG inbox interrupt enable +//! - \b SFR_NMI_PIN_INTERRUPT NMI pin interrupt enable, if NMI +//! function is chosen +//! - \b SFR_VACANT_MEMORY_ACCESS_INTERRUPT Vacant memory access +//! interrupt enable +//! - \b SFR_OSCILLATOR_FAULT_INTERRUPT Oscillator fault interrupt +//! enable +//! - \b SFR_WATCHDOG_INTERVAL_TIMER_INTERRUPT Watchdog interval timer +//! interrupt enable +//! - \b SFR_FLASH_CONTROLLER_ACCESS_VIOLATION_INTERRUPT Flash +//! controller access violation interrupt enable +//! \n indicating the status of the masked interrupts +// +//***************************************************************************** +uint8_t SFR_getInterruptStatus (uint16_t baseAddress, + uint8_t interruptFlagMask) +{ + return ( HWREG8(baseAddress + OFS_SFRIFG1_L) & interruptFlagMask ); +} + +//***************************************************************************** +// +//! \brief Clears the selected SFR interrupt flags. +//! +//! This function clears the status of the selected SFR interrupt flags. +//! +//! \param baseAddress is the Base Address of the SFR Module. +//! \param interruptFlagMask is the bit mask of interrupt flags that should be +//! cleared +//! Mask value is the logical OR of any of the following: +//! - \b SFR_JTAG_OUTBOX_INTERRUPT - JTAG outbox interrupt enable +//! - \b SFR_JTAG_INBOX_INTERRUPT - JTAG inbox interrupt enable +//! - \b SFR_NMI_PIN_INTERRUPT - NMI pin interrupt enable, if NMI +//! function is chosen +//! - \b SFR_VACANT_MEMORY_ACCESS_INTERRUPT - Vacant memory access +//! interrupt enable +//! - \b SFR_OSCILLATOR_FAULT_INTERRUPT - Oscillator fault interrupt +//! enable +//! - \b SFR_WATCHDOG_INTERVAL_TIMER_INTERRUPT - Watchdog interval timer +//! interrupt enable +//! - \b SFR_FLASH_CONTROLLER_ACCESS_VIOLATION_INTERRUPT - Flash +//! controller access violation interrupt enable +//! +//! \return None +// +//***************************************************************************** +void SFR_clearInterrupt (uint16_t baseAddress, + uint8_t interruptFlagMask) +{ + HWREG8(baseAddress + OFS_SFRIFG1_L) &= ~(interruptFlagMask); +} + +//***************************************************************************** +// +//! \brief Sets the pull-up/down resistor on the ~RST/NMI pin. +//! +//! This function sets the pull-up/down resistors on the ~RST/NMI pin to the +//! settings from the pullResistorSetup parameter. +//! +//! \param baseAddress is the Base Address of the SFR Module. +//! \param pullResistorSetup is the selection of how the pull-up/down resistor +//! on the ~RST/NMI pin should be setup or disabled. +//! Valid values are: +//! - \b SFR_RESISTORDISABLE +//! - \b SFR_RESISTORENABLE_PULLUP [Default] +//! - \b SFR_RESISTORENABLE_PULLDOWN +//! \n Modified bits are \b SYSRSTUP of \b SFRRPCR register. +//! +//! \return None +// +//***************************************************************************** +void SFR_setResetPinPullResistor (uint16_t baseAddress, + uint16_t pullResistorSetup) +{ + HWREG8(baseAddress + OFS_SFRRPCR_L) &= ~(SYSRSTRE + SYSRSTUP); + HWREG8(baseAddress + OFS_SFRRPCR_L) |= pullResistorSetup; +} + +//***************************************************************************** +// +//! \brief Sets the edge direction that will assert an NMI from a signal on the +//! ~RST/NMI pin if NMI function is active. +//! +//! This function sets the edge direction that will assert an NMI from a signal +//! on the ~RST/NMI pin if the NMI function is active. To activate the NMI +//! function of the ~RST/NMI use the SFR_setResetNMIPinFunction() passing +//! SFR_RESETPINFUNC_NMI into the resetPinFunction parameter. +//! +//! \param baseAddress is the Base Address of the SFR Module. +//! \param edgeDirection is the direction that the signal on the ~RST/NMI pin +//! should go to signal an interrupt, if enabled. +//! Valid values are: +//! - \b SFR_NMI_RISINGEDGE [Default] +//! - \b SFR_NMI_FALLINGEDGE +//! \n Modified bits are \b SYSNMIIES of \b SFRRPCR register. +//! +//! \return None +// +//***************************************************************************** +void SFR_setNMIEdge (uint16_t baseAddress, + uint16_t edgeDirection) +{ + HWREG8(baseAddress + OFS_SFRRPCR_L) &= ~(SYSNMIIES); + HWREG8(baseAddress + OFS_SFRRPCR_L) |= edgeDirection; +} + +//***************************************************************************** +// +//! \brief Sets the function of the ~RST/NMI pin. +//! +//! This function sets the functionality of the ~RST/NMI pin, whether in reset +//! mode which will assert a reset if a low signal is observed on that pin, or +//! an NMI which will assert an interrupt from an edge of the signal dependent +//! on the setting of the edgeDirection parameter in SFR_setNMIEdge(). +//! +//! \param baseAddress is the Base Address of the SFR Module. +//! \param resetPinFunction is the function that the ~RST/NMI pin should take +//! on. +//! Valid values are: +//! - \b SFR_RESETPINFUNC_RESET [Default] +//! - \b SFR_RESETPINFUNC_NMI +//! \n Modified bits are \b SYSNMI of \b SFRRPCR register. +//! +//! \return None +// +//***************************************************************************** +void SFR_setResetNMIPinFunction (uint16_t baseAddress, + uint8_t resetPinFunction) +{ + HWREG8(baseAddress + OFS_SFRRPCR_L) &= ~(SYSNMI); + HWREG8(baseAddress + OFS_SFRRPCR_L) |= resetPinFunction; +} + +#endif +#endif +//***************************************************************************** +// +//! Close the doxygen group for sfr_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/deprecated/sfr.h b/source/driverlib/MSP430F5xx_6xx/deprecated/sfr.h new file mode 100644 index 0000000..e088f52 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/deprecated/sfr.h @@ -0,0 +1,137 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// sfr.h - Driver for the SFR Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_SFR_H__ +#define __MSP430WARE_SFR_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_SFR__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the interruptMask parameter +// for functions: SFR_enableInterrupt(), and SFR_disableInterrupt(); the +// interruptFlagMask parameter for functions: SFR_getInterruptStatus(), and +// SFR_clearInterrupt() as well as returned by the SFR_getInterruptStatus() +// function. +// +//***************************************************************************** +#define SFR_JTAG_OUTBOX_INTERRUPT JMBOUTIE +#define SFR_JTAG_INBOX_INTERRUPT JMBINIE +#define SFR_NMI_PIN_INTERRUPT NMIIE +#define SFR_VACANT_MEMORY_ACCESS_INTERRUPT VMAIE +#define SFR_OSCILLATOR_FAULT_INTERRUPT OFIE +#define SFR_WATCHDOG_INTERVAL_TIMER_INTERRUPT WDTIE +#define SFR_FLASH_CONTROLLER_ACCESS_VIOLATION_INTERRUPT ACCVIE + +//***************************************************************************** +// +// The following are values that can be passed to the pullResistorSetup +// parameter for functions: SFR_setResetPinPullResistor(). +// +//***************************************************************************** +#define SFR_RESISTORDISABLE (!(SYSRSTRE + SYSRSTUP)) +#define SFR_RESISTORENABLE_PULLUP (SYSRSTRE + SYSRSTUP) +#define SFR_RESISTORENABLE_PULLDOWN (SYSRSTRE) + +//***************************************************************************** +// +// The following are values that can be passed to the edgeDirection parameter +// for functions: SFR_setNMIEdge(). +// +//***************************************************************************** +#define SFR_NMI_RISINGEDGE (!(SYSNMIIES)) +#define SFR_NMI_FALLINGEDGE (SYSNMIIES) + +//***************************************************************************** +// +// The following are values that can be passed to the resetPinFunction +// parameter for functions: SFR_setResetNMIPinFunction(). +// +//***************************************************************************** +#define SFR_RESETPINFUNC_RESET (!(SYSNMI)) +#define SFR_RESETPINFUNC_NMI (SYSNMI) + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SFR_enableInterrupt(uint16_t baseAddress, + uint8_t interruptMask); + +extern void SFR_disableInterrupt(uint16_t baseAddress, + uint8_t interruptMask); + +extern uint8_t SFR_getInterruptStatus(uint16_t baseAddress, + uint8_t interruptFlagMask); + +extern void SFR_clearInterrupt(uint16_t baseAddress, + uint8_t interruptFlagMask); + +extern void SFR_setResetPinPullResistor(uint16_t baseAddress, + uint16_t pullResistorSetup); + +extern void SFR_setNMIEdge(uint16_t baseAddress, + uint16_t edgeDirection); + +extern void SFR_setResetNMIPinFunction(uint16_t baseAddress, + uint8_t resetPinFunction); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_SFR_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/deprecated/sys.c b/source/driverlib/MSP430F5xx_6xx/deprecated/sys.c new file mode 100644 index 0000000..c9986be --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/deprecated/sys.c @@ -0,0 +1,468 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// sys.c - Driver for the sys Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup sys_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef DRIVERLIB_LEGACY_MODE + +#ifdef __MSP430_HAS_SYS__ +#include "sys.h" + +#include + +//***************************************************************************** +// +//! \brief Sets the JTAG pins to be exclusively for JTAG until a BOR occurs. +//! +//! This function sets the JTAG pins to be exclusively used for the JTAG, and +//! not to be shared with the GPIO pins. This setting can only be cleared when +//! a BOR occurs. +//! +//! \param baseAddress is the Base Address of the SYS Module. +//! +//! \return None +// +//***************************************************************************** +void SYS_enableDedicatedJTAGPins (uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_SYSCTL_L) |= SYSJTAGPIN; +} + +//***************************************************************************** +// +//! \brief Returns the indication of a BSL entry sequence from the Spy-Bi-Wire. +//! +//! This function returns the indication of a BSL entry sequence from the Spy- +//! Bi-Wire. +//! +//! \param baseAddress is the Base Address of the SYS Module. +//! +//! \return One of the following: +//! - \b SYS_BSLENTRY_INDICATED +//! - \b SYS_BSLENTRY_NOTINDICATED +//! \n indicating if a BSL entry sequence was detected +// +//***************************************************************************** +uint8_t SYS_getBSLEntryIndication (uint16_t baseAddress) +{ + if ( HWREG8(baseAddress + OFS_SYSCTL_L) & SYSBSLIND){ + return (SYS_BSLENTRY_INDICATED) ; + } else { + return (SYS_BSLENTRY_NOTINDICATED) ; + } +} + +//***************************************************************************** +// +//! \brief Enables PMM Access Protection. +//! +//! This function enables the PMM Access Protection, which will lock any +//! changes on the PMM control registers until a BOR occurs. +//! +//! \param baseAddress is the Base Address of the SYS Module. +//! +//! \return None +// +//***************************************************************************** +void SYS_enablePMMAccessProtect (uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_SYSCTL_L) |= SYSPMMPE; +} + +//***************************************************************************** +// +//! \brief Enables RAM-based Interrupt Vectors. +//! +//! This function enables RAM-base Interrupt Vectors, which means that +//! interrupt vectors are generated with the end address at the top of RAM, +//! instead of the top of the lower 64kB of flash. +//! +//! \param baseAddress is the Base Address of the SYS Module. +//! +//! \return None +// +//***************************************************************************** +void SYS_enableRAMBasedInterruptVectors (uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_SYSCTL_L) |= SYSRIVECT; +} + +//***************************************************************************** +// +//! \brief Disables RAM-based Interrupt Vectors. +//! +//! This function disables the interrupt vectors from being generated at the +//! top of the RAM. +//! +//! \param baseAddress is the Base Address of the SYS Module. +//! +//! \return None +// +//***************************************************************************** +void SYS_disableRAMBasedInterruptVectors (uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_SYSCTL_L) &= ~(SYSRIVECT); +} + +//***************************************************************************** +// +//! \brief Enables BSL memory protection. +//! +//! This function enables protection on the BSL memory, which prevents any +//! reading, programming, or erasing of the BSL memory. +//! +//! \param baseAddress is the Base Address of the SYS Module. +//! +//! \return None +// +//***************************************************************************** +void SYS_enableBSLProtect (uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_SYSBSLC) |= SYSBSLPE; +} + +//***************************************************************************** +// +//! \brief Disables BSL memory protection. +//! +//! This function disables protection on the BSL memory. +//! +//! \param baseAddress is the Base Address of the SYS Module. +//! +//! \return None +// +//***************************************************************************** +void SYS_disableBSLProtect (uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_SYSBSLC) &= ~(SYSBSLPE); +} + +//***************************************************************************** +// +//! \brief Enables BSL memory. +//! +//! This function enables BSL memory, which allows BSL memory to be addressed +//! +//! \param baseAddress is the Base Address of the SYS Module. +//! +//! \return None +// +//***************************************************************************** +void SYS_enableBSLMemory (uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_SYSBSLC) &= ~(SYSBSLOFF); +} + +//***************************************************************************** +// +//! \brief Disables BSL memory. +//! +//! This function disables BSL memory, which makes BSL memory act like vacant +//! memory. +//! +//! \param baseAddress is the Base Address of the SYS Module. +//! +//! \return None +// +//***************************************************************************** +void SYS_disableBSLMemory (uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_SYSBSLC) |= SYSBSLOFF; +} + +//***************************************************************************** +// +//! \brief Sets RAM assignment to BSL area. +//! +//! This function allows RAM to be assigned to BSL, based on the selection of +//! the BSLRAMAssignment parameter. +//! +//! \param baseAddress is the Base Address of the SYS Module. +//! \param BSLRAMAssignment is the selection of if the BSL should be placed in +//! RAM or not. +//! Valid values are: +//! - \b SYS_BSLRAMASSIGN_NORAM [Default] +//! - \b SYS_BSLRAMASSIGN_LOWEST16BYTES +//! \n Modified bits are \b SYSBSLR of \b SYSBSLC register. +//! +//! \return None +// +//***************************************************************************** +void SYS_setRAMAssignedToBSL (uint16_t baseAddress, + uint8_t BSLRAMAssignment) +{ + HWREG8(baseAddress + OFS_SYSBSLC_L) &= ~(SYSBSLR); + HWREG8(baseAddress + OFS_SYSBSLC_L) |= BSLRAMAssignment; +} + +//***************************************************************************** +// +//! \brief Sets the size of the BSL in Flash. +//! +//! This function sets the size of the BSL in Flash memory. +//! +//! \param baseAddress is the Base Address of the SYS Module. +//! \param BSLSizeSelect is the amount of segments the BSL should take. +//! Valid values are: +//! - \b SYS_BSLSIZE_SEG3 +//! - \b SYS_BSLSIZE_SEGS23 +//! - \b SYS_BSLSIZE_SEGS123 +//! - \b SYS_BSLSIZE_SEGS1234 [Default] +//! \n Modified bits are \b SYSBSLSIZE of \b SYSBSLC register. +//! +//! \return None +// +//***************************************************************************** +void SYS_setBSLSize (uint16_t baseAddress, + uint8_t BSLSizeSelect) +{ + HWREG8(baseAddress + OFS_SYSBSLC_L) &= ~(SYSBSLSIZE0 + SYSBSLSIZE1); + HWREG8(baseAddress + OFS_SYSBSLC_L) |= BSLSizeSelect; +} + +//***************************************************************************** +// +//! \brief Initializes JTAG Mailbox with selected properties. +//! +//! This function sets the specified settings for the JTAG Mailbox system. The +//! settings that can be set are the size of the JTAG messages, and the auto- +//! clearing of the inbox flags. If the inbox flags are set to auto-clear, then +//! the inbox flags will be cleared upon reading of the inbox message buffer, +//! otherwise they will have to be reset by software using the +//! SYS_clearJTAGMailboxFlagStatus() function. +//! +//! \param baseAddress is the Base Address of the SYS Module. +//! \param mailboxSizeSelect is the size of the JTAG Mailboxes, whether 16- or +//! 32-bits. +//! Valid values are: +//! - \b SYS_JTAGMBSIZE_16BIT [Default] - the JTAG messages will take up +//! only one JTAG mailbox (i. e. an outgoing message will take up +//! only 1 outbox of the JTAG mailboxes) +//! - \b SYS_JTAGMBSIZE_32BIT - the JTAG messages will be contained +//! within both JTAG mailboxes (i. e. an outgoing message will take +//! up both Outboxes of the JTAG mailboxes) +//! \n Modified bits are \b JMBMODE of \b SYSJMBC register. +//! \param autoClearInboxFlagSelect decides how the JTAG inbox flags should be +//! cleared, whether automatically after the corresponding outbox has +//! been written to, or manually by software. +//! Valid values are: +//! - \b SYS_JTAGINBOX0AUTO_JTAGINBOX1AUTO [Default] - both JTAG inbox +//! flags will be reset automatically when the corresponding inbox is +//! read from. +//! - \b SYS_JTAGINBOX0AUTO_JTAGINBOX1SW - only JTAG inbox 0 flag is +//! reset automatically, while JTAG inbox 1 is reset with the +//! - \b SYS_JTAGINBOX0SW_JTAGINBOX1AUTO - only JTAG inbox 1 flag is +//! reset automatically, while JTAG inbox 0 is reset with the +//! - \b SYS_JTAGINBOX0SW_JTAGINBOX1SW - both JTAG inbox flags will need +//! to be reset manually by the +//! \n Modified bits are \b JMBCLR0OFF and \b JMBCLR1OFF of \b SYSJMBC +//! register. +//! +//! \return None +// +//***************************************************************************** +void SYS_JTAGMailboxInit (uint16_t baseAddress, + uint8_t mailboxSizeSelect, + uint8_t autoClearInboxFlagSelect) +{ + HWREG8(baseAddress + OFS_SYSJMBC_L) &= ~(JMBCLR1OFF + JMBCLR0OFF + JMBMODE); + HWREG8(baseAddress + OFS_SYSJMBC_L) |= + mailboxSizeSelect + autoClearInboxFlagSelect; +} + +//***************************************************************************** +// +//! \brief Returns the status of the selected JTAG Mailbox flags. +//! +//! This function will return the status of the selected JTAG Mailbox flags in +//! bit mask format matching that passed into the mailboxFlagMask parameter. +//! +//! \param baseAddress is the Base Address of the SYS Module. +//! \param mailboxFlagMask is the bit mask of JTAG mailbox flags that the +//! status of should be returned. +//! Mask value is the logical OR of any of the following: +//! - \b SYS_JTAGOUTBOX_FLAG0 - flag for JTAG outbox 0 +//! - \b SYS_JTAGOUTBOX_FLAG1 - flag for JTAG outbox 1 +//! - \b SYS_JTAGINBOX_FLAG0 - flag for JTAG inbox 0 +//! - \b SYS_JTAGINBOX_FLAG1 - flag for JTAG inbox 1 +//! +//! \return A bit mask of the status of the selected mailbox flags. +// +//***************************************************************************** +uint8_t SYS_getJTAGMailboxFlagStatus (uint16_t baseAddress, + uint8_t mailboxFlagMask) +{ + return ( HWREG8(baseAddress + OFS_SYSJMBC_L) & mailboxFlagMask); +} + +//***************************************************************************** +// +//! \brief Clears the status of the selected JTAG Mailbox flags. +//! +//! This function clears the selected JTAG Mailbox flags. +//! +//! \param baseAddress is the Base Address of the SYS Module. +//! \param mailboxFlagMask is the bit mask of JTAG mailbox flags that the +//! status of should be cleared. +//! Mask value is the logical OR of any of the following: +//! - \b SYS_JTAGOUTBOX_FLAG0 - flag for JTAG outbox 0 +//! - \b SYS_JTAGOUTBOX_FLAG1 - flag for JTAG outbox 1 +//! - \b SYS_JTAGINBOX_FLAG0 - flag for JTAG inbox 0 +//! - \b SYS_JTAGINBOX_FLAG1 - flag for JTAG inbox 1 +//! +//! \return None +// +//***************************************************************************** +void SYS_clearJTAGMailboxFlagStatus (uint16_t baseAddress, + uint8_t mailboxFlagMask) +{ + HWREG8(baseAddress + OFS_SYSJMBC_L) &= ~(mailboxFlagMask); +} + +//***************************************************************************** +// +//! \brief Returns the contents of the selected JTAG Inbox in a 16 bit format. +//! +//! This function returns the message contents of the selected JTAG inbox. If +//! the auto clear settings for the Inbox flags were set, then using this +//! function will automatically clear the corresponding JTAG inbox flag. +//! +//! \param baseAddress is the Base Address of the SYS Module. +//! \param inboxSelect is the chosen JTAG inbox that the contents of should be +//! returned +//! Valid values are: +//! - \b SYS_JTAGINBOX_0 - return contents of JTAG inbox 0 +//! - \b SYS_JTAGINBOX_1 - return contents of JTAG inbox 1 +//! +//! \return The contents of the selected JTAG inbox in a 16 bit format. +// +//***************************************************************************** +uint16_t SYS_getJTAGInboxMessage16Bit (uint16_t baseAddress, + uint8_t inboxSelect) +{ + return ( HWREG16(baseAddress + OFS_SYSJMBI0 + inboxSelect) ); +} + +//***************************************************************************** +// +//! \brief Returns the contents of JTAG Inboxes in a 32 bit format. +//! +//! This function returns the message contents of both JTAG inboxes in a 32 bit +//! format. This function should be used if 32-bit messaging has been set in +//! the SYS_JTAGMailboxInit() function. If the auto clear settings for the +//! Inbox flags were set, then using this function will automatically clear +//! both JTAG inbox flags. +//! +//! \param baseAddress is the Base Address of the SYS Module. +//! +//! \return The contents of both JTAG messages in a 32 bit format. +// +//***************************************************************************** +uint32_t SYS_getJTAGInboxMessage32Bit (uint16_t baseAddress) +{ + uint32_t JTAGInboxMessageLow = HWREG16(baseAddress + OFS_SYSJMBI0); + uint32_t JTAGInboxMessageHigh = HWREG16(baseAddress + OFS_SYSJMBI1); + + return ( (JTAGInboxMessageHigh << 16) + JTAGInboxMessageLow ); +} + +//***************************************************************************** +// +//! \brief Sets a 16 bit outgoing message in to the selected JTAG Outbox. +//! +//! This function sets the outgoing message in the selected JTAG outbox. The +//! corresponding JTAG outbox flag is cleared after this function, and set +//! after the JTAG has read the message. +//! +//! \param baseAddress is the Base Address of the SYS Module. +//! \param outboxSelect is the chosen JTAG outbox that the message should be +//! set it. +//! Valid values are: +//! - \b SYS_JTAGOUTBOX_0 - set the contents of JTAG outbox 0 +//! - \b SYS_JTAGOUTBOX_1 - set the contents of JTAG outbox 1 +//! \param outgoingMessage is the message to send to the JTAG. +//! \n Modified bits are \b MSGHI and \b MSGLO of \b SYSJMBOx register. +//! +//! \return None +// +//***************************************************************************** +void SYS_setJTAGOutgoingMessage16Bit (uint16_t baseAddress, + uint8_t outboxSelect, + uint16_t outgoingMessage) +{ + HWREG16(baseAddress + OFS_SYSJMBO0 + outboxSelect) = outgoingMessage; +} + +//***************************************************************************** +// +//! \brief Sets a 32 bit message in to both JTAG Outboxes. +//! +//! This function sets the 32-bit outgoing message in both JTAG outboxes. The +//! JTAG outbox flags are cleared after this function, and set after the JTAG +//! has read the message. +//! +//! \param baseAddress is the Base Address of the SYS Module. +//! \param outgoingMessage is the message to send to the JTAG. +//! \n Modified bits are \b MSGHI and \b MSGLO of \b SYSJMBOx register. +//! +//! \return None +// +//***************************************************************************** +void SYS_setJTAGOutgoingMessage32Bit (uint16_t baseAddress, + uint32_t outgoingMessage) +{ + HWREG16(baseAddress + OFS_SYSJMBO0) = (outgoingMessage); + HWREG16(baseAddress + OFS_SYSJMBO1) = (outgoingMessage >> 16); +} + + +#endif +#endif +//***************************************************************************** +// +//! Close the doxygen group for sys_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/deprecated/sys.h b/source/driverlib/MSP430F5xx_6xx/deprecated/sys.h new file mode 100644 index 0000000..79dbd39 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/deprecated/sys.h @@ -0,0 +1,196 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// sys.h - Driver for the SYS Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_SYS_H__ +#define __MSP430WARE_SYS_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_SYS__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the BSLRAMAssignment +// parameter for functions: SYS_setRAMAssignedToBSL(). +// +//***************************************************************************** +#define SYS_BSLRAMASSIGN_NORAM (!(SYSBSLR)) +#define SYS_BSLRAMASSIGN_LOWEST16BYTES (SYSBSLR) + +//***************************************************************************** +// +// The following are values that can be passed to the BSLSizeSelect parameter +// for functions: SYS_setBSLSize(). +// +//***************************************************************************** +#define SYS_BSLSIZE_SEG3 (~(SYSBSLSIZE0 + SYSBSLSIZE1)) +#define SYS_BSLSIZE_SEGS23 (SYSBSLSIZE0) +#define SYS_BSLSIZE_SEGS123 (SYSBSLSIZE1) +#define SYS_BSLSIZE_SEGS1234 (SYSBSLSIZE0 + SYSBSLSIZE1) + +//***************************************************************************** +// +// The following are values that can be passed to the mailboxSizeSelect +// parameter for functions: SYS_JTAGMailboxInit(). +// +//***************************************************************************** +#define SYS_JTAGMBSIZE_16BIT (!(JMBMODE)) +#define SYS_JTAGMBSIZE_32BIT (JMBMODE) + +//***************************************************************************** +// +// The following are values that can be passed to the autoClearInboxFlagSelect +// parameter for functions: SYS_JTAGMailboxInit(). +// +//***************************************************************************** +#define SYS_JTAGINBOX0AUTO_JTAGINBOX1AUTO (!(JMBCLR0OFF + JMBCLR1OFF)) +#define SYS_JTAGINBOX0AUTO_JTAGINBOX1SW (JMBCLR1OFF) +#define SYS_JTAGINBOX0SW_JTAGINBOX1AUTO (JMBCLR0OFF) +#define SYS_JTAGINBOX0SW_JTAGINBOX1SW (JMBCLR0OFF + JMBCLR1OFF) + +//***************************************************************************** +// +// The following are values that can be passed to the mailboxFlagMask parameter +// for functions: SYS_getJTAGMailboxFlagStatus(), and +// SYS_clearJTAGMailboxFlagStatus(). +// +//***************************************************************************** +#define SYS_JTAGOUTBOX_FLAG0 (JMBOUT0FG) +#define SYS_JTAGOUTBOX_FLAG1 (JMBOUT1FG) +#define SYS_JTAGINBOX_FLAG0 (JMBIN0FG) +#define SYS_JTAGINBOX_FLAG1 (JMBIN1FG) + +//***************************************************************************** +// +// The following are values that can be passed to the inboxSelect parameter for +// functions: SYS_getJTAGInboxMessage16Bit(). +// +//***************************************************************************** +#define SYS_JTAGINBOX_0 (0x0) +#define SYS_JTAGINBOX_1 (0x2) + +//***************************************************************************** +// +// The following are values that can be passed to the outboxSelect parameter +// for functions: SYS_setJTAGOutgoingMessage16Bit(). +// +//***************************************************************************** +#define SYS_JTAGOUTBOX_0 (0x0) +#define SYS_JTAGOUTBOX_1 (0x2) + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the SYS_getBSLEntryIndication() function. +// +//***************************************************************************** +#define SYS_BSLENTRY_INDICATED (0x1) +#define SYS_BSLENTRY_NOTINDICATED (0x0) + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SYS_enableDedicatedJTAGPins(uint16_t baseAddress); + +extern uint8_t SYS_getBSLEntryIndication(uint16_t baseAddress); + +extern void SYS_enablePMMAccessProtect(uint16_t baseAddress); + +extern void SYS_enableRAMBasedInterruptVectors(uint16_t baseAddress); + +extern void SYS_disableRAMBasedInterruptVectors(uint16_t baseAddress); + +extern void SYS_enableBSLProtect(uint16_t baseAddress); + +extern void SYS_disableBSLProtect(uint16_t baseAddress); + +extern void SYS_enableBSLMemory(uint16_t baseAddress); + +extern void SYS_disableBSLMemory(uint16_t baseAddress); + +extern void SYS_setRAMAssignedToBSL(uint16_t baseAddress, + uint8_t BSLRAMAssignment); + +extern void SYS_setBSLSize(uint16_t baseAddress, + uint8_t BSLSizeSelect); + +extern void SYS_JTAGMailboxInit(uint16_t baseAddress, + uint8_t mailboxSizeSelect, + uint8_t autoClearInboxFlagSelect); + +extern uint8_t SYS_getJTAGMailboxFlagStatus(uint16_t baseAddress, + uint8_t mailboxFlagMask); + +extern void SYS_clearJTAGMailboxFlagStatus(uint16_t baseAddress, + uint8_t mailboxFlagMask); + +extern uint16_t SYS_getJTAGInboxMessage16Bit(uint16_t baseAddress, + uint8_t inboxSelect); + +extern uint32_t SYS_getJTAGInboxMessage32Bit(uint16_t baseAddress); + +extern void SYS_setJTAGOutgoingMessage16Bit(uint16_t baseAddress, + uint8_t outboxSelect, + uint16_t outgoingMessage); + +extern void SYS_setJTAGOutgoingMessage32Bit(uint16_t baseAddress, + uint32_t outgoingMessage); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_SYS_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/deprecated/ucs.c b/source/driverlib/MSP430F5xx_6xx/deprecated/ucs.c new file mode 100644 index 0000000..fa4ff92 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/deprecated/ucs.c @@ -0,0 +1,1552 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// ucs.c - Driver for the ucs Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup ucs_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef DRIVERLIB_LEGACY_MODE + +#ifdef __MSP430_HAS_UCS__ +#include "ucs.h" + +#include + +#ifdef __GNUC__ +#define __delay_cycles(x) \ +({ \ + volatile unsigned int j; \ + for (j=0;j> 12; + + for (i = 0; i < tempDivider; i++){ + D_value = D_value * 2; + } + + CLKFrequency *= D_value; + } + return ( CLKFrequency) ; +} + +//***************************************************************************** +// +//! \brief Compute the clock frequency given the clock source and divider +//! +//! \param baseAddress is the base address of the UCS module. +//! \param CLKSource is the clock source +//! \param CLKSourceDivider is the clock source divider +//! +//! \return Calculated clock frequency in Hz +// +//***************************************************************************** +static uint32_t privateUCSComputeCLKFrequency ( uint16_t baseAddress, + uint16_t CLKSource, + uint16_t CLKSourceDivider + ) +{ + uint32_t CLKFrequency; + uint8_t CLKSourceFrequencyDivider = 1; + uint8_t i = 0; + + for ( i = 0; i < CLKSourceDivider; i++){ + CLKSourceFrequencyDivider *= 2; + } + + switch (CLKSource){ + case SELM__XT1CLK: + CLKFrequency = (UCS_XT1ClockFrequency / + CLKSourceFrequencyDivider); + + if(XTS != (HWREG16(baseAddress + OFS_UCSCTL6) & XTS)) { + if (HWREG8(baseAddress + OFS_UCSCTL7) & XT1LFOFFG){ + HWREG8(baseAddress + OFS_UCSCTL7) &= ~(XT1LFOFFG); + //Clear OFIFG fault flag + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + + if (HWREG8(baseAddress + OFS_UCSCTL7) & XT1LFOFFG){ + CLKFrequency = UCS_REFOCLK_FREQUENCY; + } + } + } + else { + if (HWREG8(baseAddress + OFS_UCSCTL7) & XT1HFOFFG){ + HWREG8(baseAddress + OFS_UCSCTL7) &= ~(XT1HFOFFG); + //Clear OFIFG fault flag + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + + if (HWREG8(baseAddress + OFS_UCSCTL7) & XT1HFOFFG){ + CLKFrequency = UCS_REFOCLK_FREQUENCY; + } + } + } + break; + + case SELM__VLOCLK: + CLKFrequency = + (UCS_VLOCLK_FREQUENCY / CLKSourceFrequencyDivider); + break; + case SELM__REFOCLK: + CLKFrequency = + (UCS_REFOCLK_FREQUENCY / CLKSourceFrequencyDivider); + break; + case SELM__XT2CLK: + CLKFrequency = + (UCS_XT2ClockFrequency / CLKSourceFrequencyDivider); + + if (HWREG8(baseAddress + OFS_UCSCTL7) & XT2OFFG){ + + HWREG8(baseAddress + OFS_UCSCTL7) &= ~XT2OFFG; + //Clear OFIFG fault flag + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + } + + if (HWREG8(baseAddress + OFS_UCSCTL7) & XT2OFFG){ + CLKFrequency = + privateUCSSourceClockFromDCO(baseAddress, SELM__DCOCLKDIV); + } + break; + case SELM__DCOCLK: + case SELM__DCOCLKDIV: + CLKFrequency = privateUCSSourceClockFromDCO(baseAddress, + CLKSource) / CLKSourceFrequencyDivider; + break; + } + + return ( CLKFrequency) ; +} + +//***************************************************************************** +// +//! \brief Sets the external clock source +//! +//! This function sets the external clock sources XT1 and XT2 crystal +//! oscillator frequency values. This function must be called if an external +//! crystal XT1 or XT2 is used and the user intends to call UCS_getMCLK, +//! UCS_getSMCLK or UCS_getACLK APIs. If not, it is not necessary to invoke +//! this API. +//! +//! \param baseAddress is the base address of the UCS module. +//! \param XT1CLK_frequency is the XT1 crystal frequencies in Hz +//! \param XT2CLK_frequency is the XT2 crystal frequencies in Hz +//! +//! \return None +// +//***************************************************************************** +void UCS_setExternalClockSource (uint16_t baseAddress, + uint32_t XT1CLK_frequency, + uint32_t XT2CLK_frequency + ) +{ + UCS_XT1ClockFrequency = XT1CLK_frequency; + UCS_XT2ClockFrequency = XT2CLK_frequency; +} + +//***************************************************************************** +// +//! \brief Initializes a clock signal +//! +//! This function initializes each of the clock signals. The user must ensure +//! that this function is called for each clock signal. If not, the default +//! state is assumed for the particular clock signal. Refer MSP430Ware +//! documentation for UCS module or Device Family User's Guide for details of +//! default clock signal states. +//! +//! \param baseAddress is the base address of the UCS module. +//! \param selectedClockSignal selected clock signal +//! Valid values are: +//! - \b UCS_ACLK +//! - \b UCS_MCLK +//! - \b UCS_SMCLK +//! - \b UCS_FLLREF +//! \param clockSource is clock source for the selectedClockSignal +//! Valid values are: +//! - \b UCS_XT1CLK_SELECT +//! - \b UCS_VLOCLK_SELECT +//! - \b UCS_REFOCLK_SELECT +//! - \b UCS_DCOCLK_SELECT +//! - \b UCS_DCOCLKDIV_SELECT +//! - \b UCS_XT2CLK_SELECT +//! \param clockSourceDivider selected the clock divider to calculate +//! clocksignal from clock source. +//! Valid values are: +//! - \b UCS_CLOCK_DIVIDER_1 [Default] +//! - \b UCS_CLOCK_DIVIDER_2 +//! - \b UCS_CLOCK_DIVIDER_4 +//! - \b UCS_CLOCK_DIVIDER_8 +//! - \b UCS_CLOCK_DIVIDER_12 - [Valid only for UCS_FLLREF] +//! - \b UCS_CLOCK_DIVIDER_16 +//! - \b UCS_CLOCK_DIVIDER_32 - [Not valid for UCS_FLLREF] +//! +//! Modified bits of \b UCSCTL5 register, bits of \b UCSCTL4 register and bits +//! of \b UCSCTL3 register. +//! +//! \return None +// +//***************************************************************************** +void UCS_clockSignalInit ( uint16_t baseAddress, + uint8_t selectedClockSignal, + uint16_t clockSource, + uint16_t clockSourceDivider + ) +{ + assert( + (UCS_XT1CLK_SELECT == clockSource) || + (UCS_VLOCLK_SELECT == clockSource) || + (UCS_REFOCLK_SELECT == clockSource) || + (UCS_DCOCLK_SELECT == clockSource) || + (UCS_DCOCLKDIV_SELECT == clockSource) || + (UCS_XT2CLK_SELECT == clockSource) + ); + + assert( + (UCS_CLOCK_DIVIDER_1 == clockSourceDivider) || + (UCS_CLOCK_DIVIDER_2 == clockSourceDivider) || + (UCS_CLOCK_DIVIDER_4 == clockSourceDivider) || + (UCS_CLOCK_DIVIDER_8 == clockSourceDivider) || + (UCS_CLOCK_DIVIDER_16 == clockSourceDivider) || + (UCS_CLOCK_DIVIDER_32 == clockSourceDivider) + ); + + switch (selectedClockSignal){ + case UCS_ACLK: + HWREG16(baseAddress + OFS_UCSCTL4) &= ~(SELA_7); + clockSource = clockSource << 8; + HWREG16(baseAddress + OFS_UCSCTL4) |= (clockSource); + + HWREG16(baseAddress + OFS_UCSCTL5) &= ~(DIVA_7); + clockSourceDivider = clockSourceDivider << 8; + HWREG16(baseAddress + OFS_UCSCTL5) |= clockSourceDivider; + break; + case UCS_SMCLK: + HWREG16(baseAddress + OFS_UCSCTL4) &= ~(SELS_7); + clockSource = clockSource << 4; + HWREG16(baseAddress + OFS_UCSCTL4) |= (clockSource); + + HWREG16(baseAddress + OFS_UCSCTL5) &= ~(DIVS_7); + clockSourceDivider = clockSourceDivider << 4; + HWREG16(baseAddress + OFS_UCSCTL5) |= clockSourceDivider; + break; + case UCS_MCLK: + HWREG16(baseAddress + OFS_UCSCTL4) &= ~(SELM_7); + HWREG16(baseAddress + OFS_UCSCTL4) |= (clockSource); + + HWREG16(baseAddress + OFS_UCSCTL5) &= ~(DIVM_7); + HWREG16(baseAddress + OFS_UCSCTL5) |= clockSourceDivider; + break; + case UCS_FLLREF: + assert(clockSource <= SELA_5); + HWREG8(baseAddress + OFS_UCSCTL3) &= ~(SELREF_7); + + clockSource = clockSource << 4; + HWREG8(baseAddress + OFS_UCSCTL3) |= (clockSource); + + HWREG8(baseAddress + OFS_UCSCTL3) &= ~(FLLREFDIV_7); + //Note that dividers for FLLREF are slightly different + //Hence handled differently from other CLK signals + switch(clockSourceDivider) + { + case UCS_CLOCK_DIVIDER_12: + HWREG8(baseAddress + OFS_UCSCTL3) |= FLLREFDIV__12; + break; + case UCS_CLOCK_DIVIDER_16: + HWREG8(baseAddress + OFS_UCSCTL3) |= FLLREFDIV__16; + break; + default: + HWREG8(baseAddress + OFS_UCSCTL3) |= clockSourceDivider; + break; + } + + break; + } +} + +//***************************************************************************** +// +//! \brief Initializes the XT1 crystal oscillator in low frequency mode +//! +//! Initializes the XT1 crystal oscillator in low frequency mode. Loops until +//! all oscillator fault flags are cleared, with no timeout. See the device- +//! specific data sheet for appropriate drive settings. +//! +//! \param baseAddress is the base address of the UCS module. +//! \param xt1drive is the target drive strength for the XT1 crystal +//! oscillator. +//! Valid values are: +//! - \b UCS_XT1_DRIVE0 +//! - \b UCS_XT1_DRIVE1 +//! - \b UCS_XT1_DRIVE2 +//! - \b UCS_XT1_DRIVE3 [Default] +//! \n Modified bits are \b XT1DRIVE of \b UCSCTL6 register. +//! \param xcap is the selected capacitor value. This parameter selects the +//! capacitors applied to the LF crystal (XT1) or resonator in the LF +//! mode. The effective capacitance (seen by the crystal) is Ceff. (CXIN +//! + 2 pF)/2. It is assumed that CXIN = CXOUT and that a parasitic +//! capacitance of 2 pF is added by the package and the printed circuit +//! board. For details about the typical internal and the effective +//! capacitors, refer to the device-specific data sheet. +//! Valid values are: +//! - \b UCS_XCAP_0 +//! - \b UCS_XCAP_1 +//! - \b UCS_XCAP_2 +//! - \b UCS_XCAP_3 [Default] +//! +//! Modified bits are \b XCAP of \b UCSCTL6 register. +//! +//! \return None +// +//***************************************************************************** +void UCS_LFXT1Start (uint16_t baseAddress, + uint16_t xt1drive, + uint8_t xcap + ) +{ + assert((xcap == UCS_XCAP_0) || + (xcap == UCS_XCAP_1) || + (xcap == UCS_XCAP_2) || + (xcap == UCS_XCAP_3) ); + + assert((xt1drive == UCS_XT1_DRIVE0 ) || + (xt1drive == UCS_XT1_DRIVE1 ) || + (xt1drive == UCS_XT1_DRIVE2 ) || + (xt1drive == UCS_XT1_DRIVE3 )); + + //If the drive setting is not already set to maximum + //Set it to max for LFXT startup + if ((HWREG16(baseAddress + OFS_UCSCTL6) & XT1DRIVE_3) != XT1DRIVE_3){ + //Highest drive setting for XT1startup + HWREG16(baseAddress + OFS_UCSCTL6_L) |= XT1DRIVE1_L + XT1DRIVE0_L; + } + + //Enable LF mode and clear xcap and bypass + HWREG16(baseAddress + OFS_UCSCTL6) &= ~(XTS + XCAP_3 + XT1BYPASS); + HWREG16(baseAddress + OFS_UCSCTL6) |= xcap; + + while (HWREG8(baseAddress + OFS_UCSCTL7) & XT1LFOFFG) + { + //Clear OSC flaut Flags fault flags + HWREG8(baseAddress + OFS_UCSCTL7) &= ~(XT1LFOFFG); + + //Clear OFIFG fault flag + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + } + + //set requested Drive mode + HWREG16(baseAddress + OFS_UCSCTL6) = ( HWREG16(baseAddress + OFS_UCSCTL6) & + ~(XT1DRIVE_3) + ) | + (xt1drive); + + //Switch ON XT1 oscillator + HWREG16(baseAddress + OFS_UCSCTL6) &= ~XT1OFF; +} + +//***************************************************************************** +// +//! \brief Initializes the XT1 crystal oscillator in low frequency mode +//! +//! Initializes the XT1 crystal oscillator in high frequency mode. Loops until +//! all oscillator fault flags are cleared, with no timeout. See the device- +//! specific data sheet for appropriate drive settings. +//! +//! \param baseAddress is the base address of the UCS module. +//! \param xt1drive is the target drive strength for the XT1 crystal +//! oscillator. +//! Valid values are: +//! - \b UCS_XT1_DRIVE0 +//! - \b UCS_XT1_DRIVE1 +//! - \b UCS_XT1_DRIVE2 +//! - \b UCS_XT1_DRIVE3 [Default] +//! +//! Modified bits of \b UCSCTL7 register, bits of \b UCSCTL6 register and bits +//! of \b SFRIFG register. +//! +//! \return None +// +//***************************************************************************** +void UCS_HFXT1Start(uint16_t baseAddress, + uint16_t xt1drive + ) +{ + //Check if drive value is the expected one + if ((HWREG16(baseAddress + OFS_UCSCTL6) & XT1DRIVE_3) != xt1drive){ + //Clear XT1drive field + HWREG16(baseAddress + OFS_UCSCTL6) &= ~XT1DRIVE_3; + + //Set requested value + HWREG16(baseAddress + OFS_UCSCTL6) |= xt1drive; + } + + //Enable HF mode + HWREG16(baseAddress + OFS_UCSCTL6) |= XTS; + + HWREG16(baseAddress + OFS_UCSCTL6) &= ~XT1BYPASS; + + // Check XT1 fault flags + while((HWREG8(baseAddress + OFS_UCSCTL7) & (XT1HFOFFG))){ + //Clear OSC flaut Flags fault flags + HWREG8(baseAddress + OFS_UCSCTL7) &= ~(XT1HFOFFG); + + //Clear OFIFG fault flag + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + } + + //Switch ON XT1 oscillator + HWREG16(baseAddress + OFS_UCSCTL6) &= ~XT1OFF; +} + +//***************************************************************************** +// +//! \brief Bypass the XT1 crystal oscillator +//! +//! Bypasses the XT1 crystal oscillator. Loops until all oscillator fault flags +//! are cleared, with no timeout. +//! +//! \param baseAddress is the base address of the UCS module. +//! \param highOrLowFrequency selects high frequency or low frequency mode for +//! XT1. +//! Valid values are: +//! - \b UCS_XT1_HIGH_FREQUENCY +//! - \b UCS_XT1_LOW_FREQUENCY [Default] +//! +//! Modified bits of \b UCSCTL7 register, bits of \b UCSCTL6 register and bits +//! of \b SFRIFG register. +//! +//! \return None +// +//***************************************************************************** +void UCS_bypassXT1 ( uint16_t baseAddress, + uint8_t highOrLowFrequency + ) +{ + assert((UCS_XT1_LOW_FREQUENCY == highOrLowFrequency) || + (UCS_XT1_HIGH_FREQUENCY == highOrLowFrequency ) + ); + + //Enable HF/LF mode + HWREG16(baseAddress + OFS_UCSCTL6) &= ~XTS; + HWREG16(baseAddress + OFS_UCSCTL6) |= highOrLowFrequency; + + //Switch OFF XT1 oscillator and enable BYPASS mode + HWREG16(baseAddress + OFS_UCSCTL6) |= (XT1BYPASS + XT1OFF); + + if (UCS_XT1_LOW_FREQUENCY == highOrLowFrequency){ + while (HWREG8(baseAddress + OFS_UCSCTL7) & (XT1LFOFFG)) { + //Clear OSC flaut Flags fault flags + HWREG8(baseAddress + OFS_UCSCTL7) &= ~(XT1LFOFFG); + + // Clear the global fault flag. In case the XT1 caused the global fault + // flag to get set this will clear the global error condition. If any + // error condition persists, global flag will get again. + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + } + } else { + while (HWREG8(baseAddress + OFS_UCSCTL7) & (XT1HFOFFG)) { + //Clear OSC flaut Flags fault flags + HWREG8(baseAddress + OFS_UCSCTL7) &= ~(XT1HFOFFG); + + //Clear the global fault flag. In case the XT1 caused the global fault + //flag to get set this will clear the global error condition. If any + //error condition persists, global flag will get again. + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + } + } + +} + +//***************************************************************************** +// +//! \brief Initializes the XT1 crystal oscillator in low frequency mode with +//! timeout +//! +//! Initializes the XT1 crystal oscillator in low frequency mode with timeout. +//! Loops until all oscillator fault flags are cleared or until a timeout +//! counter is decremented and equals to zero. See the device-specific +//! datasheet for appropriate drive settings. +//! +//! \param baseAddress is the base address of the UCS module. +//! \param xt1drive is the target drive strength for the XT1 crystal +//! oscillator. +//! Valid values are: +//! - \b UCS_XT1_DRIVE0 +//! - \b UCS_XT1_DRIVE1 +//! - \b UCS_XT1_DRIVE2 +//! - \b UCS_XT1_DRIVE3 [Default] +//! \param xcap is the selected capacitor value. This parameter selects the +//! capacitors applied to the LF crystal (XT1) or resonator in the LF +//! mode. The effective capacitance (seen by the crystal) is Ceff. (CXIN +//! + 2 pF)/2. It is assumed that CXIN = CXOUT and that a parasitic +//! capacitance of 2 pF is added by the package and the printed circuit +//! board. For details about the typical internal and the effective +//! capacitors, refer to the device-specific data sheet. +//! Valid values are: +//! - \b UCS_XCAP_0 +//! - \b UCS_XCAP_1 +//! - \b UCS_XCAP_2 +//! - \b UCS_XCAP_3 [Default] +//! \param timeout is the count value that gets decremented every time the loop +//! that clears oscillator fault flags gets executed. +//! +//! Modified bits of \b UCSCTL7 register, bits of \b UCSCTL6 register and bits +//! of \b SFRIFG register. +//! +//! \return STATUS_SUCCESS or STATUS_FAIL +// +//***************************************************************************** +bool UCS_LFXT1StartWithTimeout(uint16_t baseAddress, + uint16_t xt1drive, + uint8_t xcap, + uint16_t timeout + ) +{ + assert((xcap == UCS_XCAP_0) || + (xcap == UCS_XCAP_1) || + (xcap == UCS_XCAP_2) || + (xcap == UCS_XCAP_3) ); + + assert((xt1drive == UCS_XT1_DRIVE0 ) || + (xt1drive == UCS_XT1_DRIVE1 ) || + (xt1drive == UCS_XT1_DRIVE2 ) || + (xt1drive == UCS_XT1_DRIVE3 )); + + assert(timeout > 0); + + //If the drive setting is not already set to maximum + //Set it to max for LFXT startup + if ((HWREG16(baseAddress + OFS_UCSCTL6) & XT1DRIVE_3) != XT1DRIVE_3){ + //Highest drive setting for XT1startup + HWREG16(baseAddress + OFS_UCSCTL6_L) |= XT1DRIVE1_L + XT1DRIVE0_L; + } + + //Enable LF mode and clear xcap and bypass + HWREG16(baseAddress + OFS_UCSCTL6) &= ~(XTS + XCAP_3 + XT1BYPASS); + HWREG16(baseAddress + OFS_UCSCTL6) |= xcap; + + do + { + HWREG8(baseAddress + OFS_UCSCTL7) &= ~(XT1LFOFFG); + + //Clear OFIFG fault flag + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + }while ((HWREG8(baseAddress + OFS_UCSCTL7) & XT1LFOFFG) && --timeout); + + if (timeout){ + //set requested Drive mode + HWREG16(baseAddress + OFS_UCSCTL6) = ( HWREG16(baseAddress + OFS_UCSCTL6) & + ~(XT1DRIVE_3) + ) | + (xt1drive); + //Switch ON XT1 oscillator + HWREG16(baseAddress + OFS_UCSCTL6) &= ~XT1OFF; + + return (STATUS_SUCCESS); + } else { + return (STATUS_FAIL); + } +} + +//***************************************************************************** +// +//! \brief Initializes the XT1 crystal oscillator in high frequency mode with +//! timeout +//! +//! Initializes the XT1 crystal oscillator in high frequency mode with timeout. +//! Loops until all oscillator fault flags are cleared or until a timeout +//! counter is decremented and equals to zero. See the device-specific data +//! sheet for appropriate drive settings. +//! +//! \param baseAddress is the base address of the UCS module. +//! \param xt1drive is the target drive strength for the XT1 crystal +//! oscillator. +//! Valid values are: +//! - \b UCS_XT1_DRIVE0 +//! - \b UCS_XT1_DRIVE1 +//! - \b UCS_XT1_DRIVE2 +//! - \b UCS_XT1_DRIVE3 [Default] +//! \param timeout is the count value that gets decremented every time the loop +//! that clears oscillator fault flags gets executed. +//! +//! Modified bits of \b UCSCTL7 register, bits of \b UCSCTL6 register and bits +//! of \b SFRIFG register. +//! +//! \return STATUS_SUCCESS or STATUS_FAIL +// +//***************************************************************************** +bool UCS_HFXT1StartWithTimeout ( uint16_t baseAddress, + uint16_t xt1drive, + uint16_t timeout + ) +{ + assert((xt1drive == UCS_XT1_DRIVE0 ) || + (xt1drive == UCS_XT1_DRIVE1 ) || + (xt1drive == UCS_XT1_DRIVE2 ) || + (xt1drive == UCS_XT1_DRIVE3 )); + + assert(timeout > 0); + + //Check if drive value is the expected one + if ((HWREG16(baseAddress + OFS_UCSCTL6) & XT1DRIVE_3) != xt1drive){ + //Clear XT1drive field + HWREG16(baseAddress + OFS_UCSCTL6) &= ~XT1DRIVE_3; + + //Set requested value + HWREG16(baseAddress + OFS_UCSCTL6) |= xt1drive; + } + + //Enable HF mode + HWREG16(baseAddress + OFS_UCSCTL6) |= XTS; + + HWREG16(baseAddress + OFS_UCSCTL6) &= ~XT1BYPASS; + + // Check XT1 fault flags + do + { + HWREG8(baseAddress + OFS_UCSCTL7) &= ~(XT1HFOFFG); + + //Clear OFIFG fault flag + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + }while ((HWREG8(baseAddress + OFS_UCSCTL7) & ( XT1HFOFFG)) + && --timeout); + + if (timeout){ + //Switch ON XT1 oscillator + HWREG16(baseAddress + OFS_UCSCTL6) &= ~XT1OFF; + + return (STATUS_SUCCESS); + } else { + return (STATUS_FAIL); + } +} + +//***************************************************************************** +// +//! \brief Bypasses the XT1 crystal oscillator with time out +//! +//! Bypasses the XT1 crystal oscillator with time out. Loops until all +//! oscillator fault flags are cleared or until a timeout counter is +//! decremented and equals to zero. +//! +//! \param baseAddress is the base address of the UCS module. +//! \param highOrLowFrequency selects high frequency or low frequency mode for +//! XT1. +//! Valid values are: +//! - \b UCS_XT1_HIGH_FREQUENCY +//! - \b UCS_XT1_LOW_FREQUENCY [Default] +//! \param timeout is the count value that gets decremented every time the loop +//! that clears oscillator fault flags gets executed. +//! +//! Modified bits of \b UCSCTL7 register, bits of \b UCSCTL6 register and bits +//! of \b SFRIFG register. +//! +//! \return STATUS_SUCCESS or STATUS_FAIL +// +//***************************************************************************** +bool UCS_bypassXT1WithTimeout (uint16_t baseAddress, + uint8_t highOrLowFrequency, + uint16_t timeout + ) +{ + assert((UCS_XT1_LOW_FREQUENCY == highOrLowFrequency) || + (UCS_XT1_HIGH_FREQUENCY == highOrLowFrequency ) + ); + + assert(timeout > 0); + + //Enable HF/LF mode + HWREG16(baseAddress + OFS_UCSCTL6) &= ~XTS; + HWREG16(baseAddress + OFS_UCSCTL6) |= highOrLowFrequency; + + //Switch OFF XT1 oscillator and enable bypass + HWREG16(baseAddress + OFS_UCSCTL6) |= (XT1BYPASS + XT1OFF); + + if (UCS_XT1_LOW_FREQUENCY == highOrLowFrequency){ + do { + //Clear OSC flaut Flags fault flags + HWREG8(baseAddress + OFS_UCSCTL7) &= ~(XT1LFOFFG); + + // Clear the global fault flag. In case the XT1 caused the global fault + // flag to get set this will clear the global error condition. If any + // error condition persists, global flag will get again. + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + }while ((HWREG8(baseAddress + OFS_UCSCTL7) & (XT1LFOFFG)) && --timeout); + + } else { + do { + //Clear OSC flaut Flags fault flags + HWREG8(baseAddress + OFS_UCSCTL7) &= ~(XT1HFOFFG); + + //Clear the global fault flag. In case the XT1 caused the global fault + //flag to get set this will clear the global error condition. If any + //error condition persists, global flag will get again. + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + }while ((HWREG8(baseAddress + OFS_UCSCTL7) & (XT1HFOFFG))&& --timeout); + } + + if (timeout){ + return (STATUS_SUCCESS); + } else { + return (STATUS_FAIL); + } +} + +//***************************************************************************** +// +//! \brief Stops the XT1 oscillator using the XT1OFF bit. +//! +//! \param baseAddress is the base address of the UCS module. +//! +//! \return None +// +//***************************************************************************** +void UCS_XT1Off (uint16_t baseAddress) +{ + //Switch off XT1 oscillator + HWREG16(baseAddress + OFS_UCSCTL6) |= XT1OFF; +} + +//***************************************************************************** +// +//! \brief Initializes the XT2 crystal oscillator +//! +//! Initializes the XT2 crystal oscillator, which supports crystal frequencies +//! between 4 MHz and 32 MHz, depending on the selected drive strength. Loops +//! until all oscillator fault flags are cleared, with no timeout. See the +//! device-specific data sheet for appropriate drive settings. +//! +//! \param baseAddress is the base address of the UCS module. +//! \param xt2drive is the target drive strength for the XT2 crystal +//! oscillator. +//! Valid values are: +//! - \b UCS_XT2DRIVE_4MHZ_8MHZ +//! - \b UCS_XT2DRIVE_8MHZ_16MHZ +//! - \b UCS_XT2DRIVE_16MHZ_24MHZ +//! - \b UCS_XT2DRIVE_24MHZ_32MHZ [Default] +//! +//! Modified bits of \b UCSCTL7 register, bits of \b UCSCTL6 register and bits +//! of \b SFRIFG register. +//! +//! \return None +// +//***************************************************************************** +void UCS_XT2Start ( uint16_t baseAddress, + uint16_t xt2drive + ) +{ +#if !defined (__CC430F5133__) || (__CC430F5135__) || (__CC430F5137__) || \ + (__CC430F6125__) || (__CC430F6126__) || (__CC430F6127__) || \ + (__CC430F6135__) || (__CC430F6137__) || (__CC430F5123__) || \ + (__CC430F5125__) || (__CC430F5143__) || (__CC430F5145__) || \ + (__CC430F5147__) || (__CC430F6143__) || (__CC430F6145__) || \ + (__CC430F6147__) + + //Check if drive value is the expected one + if ((HWREG16(baseAddress + OFS_UCSCTL6) & XT2DRIVE_3) != xt2drive){ + //Clear XT2drive field + HWREG16(baseAddress + OFS_UCSCTL6) &= ~XT2DRIVE_3; + + //Set requested value + HWREG16(baseAddress + OFS_UCSCTL6) |= xt2drive; + } +#endif + + //Enable XT2 and Switch on XT2 oscillator + HWREG16(baseAddress + OFS_UCSCTL6) &= ~XT2BYPASS; + HWREG16(baseAddress + OFS_UCSCTL6) &= ~XT2OFF; + + while (HWREG8(baseAddress + OFS_UCSCTL7) & XT2OFFG){ + //Clear OSC flaut Flags + HWREG8(baseAddress + OFS_UCSCTL7) &= ~(XT2OFFG); + +#if defined (__CC430F5133__) || (__CC430F5135__) || (__CC430F5137__) || \ + (__CC430F6125__) || (__CC430F6126__) || (__CC430F6127__) || \ + (__CC430F6135__) || (__CC430F6137__) || (__CC430F5123__) || \ + (__CC430F5125__) || (__CC430F5143__) || (__CC430F5145__) || \ + (__CC430F5147__) || (__CC430F6143__) || (__CC430F6145__) || \ + (__CC430F6147__) + // CC430 uses a different fault mechanism. It requires 3 VLO clock + // cycles delay.If 20MHz CPU, 5000 clock cycles are required in worst + // case. + __delay_cycles(5000); +#endif + + //Clear OFIFG fault flag + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + } +} + +//***************************************************************************** +// +//! \brief Bypasses the XT2 crystal oscillator +//! +//! Bypasses the XT2 crystal oscillator, which supports crystal frequencies +//! between 4 MHz and 32 MHz. Loops until all oscillator fault flags are +//! cleared, with no timeout. +//! +//! \param baseAddress is the base address of the UCS module. +//! +//! Modified bits of \b UCSCTL7 register, bits of \b UCSCTL6 register and bits +//! of \b SFRIFG register. +//! +//! \return None +// +//***************************************************************************** +void UCS_bypassXT2 ( uint16_t baseAddress ) +{ + //Switch on XT2 oscillator + HWREG16(baseAddress + OFS_UCSCTL6) |= ( XT2BYPASS + XT2OFF ); + + while (HWREG8(baseAddress + OFS_UCSCTL7) & XT2OFFG){ + //Clear OSC flaut Flags + HWREG8(baseAddress + OFS_UCSCTL7) &= ~(XT2OFFG); + +#if defined (__CC430F5133__) || (__CC430F5135__) || (__CC430F5137__) || \ + (__CC430F6125__) || (__CC430F6126__) || (__CC430F6127__) || \ + (__CC430F6135__) || (__CC430F6137__) || (__CC430F5123__) || \ + (__CC430F5125__) || (__CC430F5143__) || (__CC430F5145__) || \ + (__CC430F5147__) || (__CC430F6143__) || (__CC430F6145__) || \ + (__CC430F6147__) + // CC430 uses a different fault mechanism. It requires 3 VLO clock + // cycles delay.If 20MHz CPU, 5000 clock cycles are required in worst + // case. + __delay_cycles(5000); +#endif + + //Clear OFIFG fault flag + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + } +} + +//***************************************************************************** +// +//! \brief Initializes the XT2 crystal oscillator with timeout +//! +//! Initializes the XT2 crystal oscillator, which supports crystal frequencies +//! between 4 MHz and 32 MHz, depending on the selected drive strength. Loops +//! until all oscillator fault flags are cleared or until a timeout counter is +//! decremented and equals to zero. See the device-specific data sheet for +//! appropriate drive settings. +//! +//! \param baseAddress is the base address of the UCS module. +//! \param xt2drive is the target drive strength for the XT2 crystal +//! oscillator. +//! Valid values are: +//! - \b UCS_XT2DRIVE_4MHZ_8MHZ +//! - \b UCS_XT2DRIVE_8MHZ_16MHZ +//! - \b UCS_XT2DRIVE_16MHZ_24MHZ +//! - \b UCS_XT2DRIVE_24MHZ_32MHZ [Default] +//! \param timeout is the count value that gets decremented every time the loop +//! that clears oscillator fault flags gets executed. +//! +//! Modified bits of \b UCSCTL7 register, bits of \b UCSCTL6 register and bits +//! of \b SFRIFG register. +//! +//! \return STATUS_SUCCESS or STATUS_FAIL +// +//***************************************************************************** +bool UCS_XT2StartWithTimeout ( uint16_t baseAddress, + uint16_t xt2drive, + uint16_t timeout + ) +{ + assert(timeout > 0); + +#if !defined (__CC430F5133__) || (__CC430F5135__) || (__CC430F5137__) || \ + (__CC430F6125__) || (__CC430F6126__) || (__CC430F6127__) || \ + (__CC430F6135__) || (__CC430F6137__) || (__CC430F5123__) || \ + (__CC430F5125__) || (__CC430F5143__) || (__CC430F5145__) || \ + (__CC430F5147__) || (__CC430F6143__) || (__CC430F6145__) || \ + (__CC430F6147__) + //Check if drive value is the expected one + if ((HWREG16(baseAddress + OFS_UCSCTL6) & XT2DRIVE_3) != xt2drive){ + //Clear XT2drive field + HWREG16(baseAddress + OFS_UCSCTL6) &= ~XT2DRIVE_3; + + //Set requested value + HWREG16(baseAddress + OFS_UCSCTL6) |= xt2drive; + } + +#endif + + HWREG16(baseAddress + OFS_UCSCTL6) &= ~XT2BYPASS; + + //Switch on XT2 oscillator + HWREG16(baseAddress + OFS_UCSCTL6) &= ~XT2OFF; + + do{ + //Clear OSC flaut Flags + HWREG8(baseAddress + OFS_UCSCTL7) &= ~(XT2OFFG); + +#if defined (__CC430F5133__) || (__CC430F5135__) || (__CC430F5137__) || \ + (__CC430F6125__) || (__CC430F6126__) || (__CC430F6127__) || \ + (__CC430F6135__) || (__CC430F6137__) || (__CC430F5123__) || \ + (__CC430F5125__) || (__CC430F5143__) || (__CC430F5145__) || \ + (__CC430F5147__) || (__CC430F6143__) || (__CC430F6145__) || \ + (__CC430F6147__) + // CC430 uses a different fault mechanism. It requires 3 VLO clock + // cycles delay.If 20MHz CPU, 5000 clock cycles are required in worst + // case. + __delay_cycles(5000); +#endif + + //Clear OFIFG fault flag + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + }while ((HWREG8(baseAddress + OFS_UCSCTL7) & XT2OFFG) && --timeout); + + if (timeout){ + return (STATUS_SUCCESS); + } else { + return (STATUS_FAIL); + } +} + +//***************************************************************************** +// +//! \brief Bypasses the XT2 crystal oscillator with timeout +//! +//! Bypasses the XT2 crystal oscillator, which supports crystal frequencies +//! between 4 MHz and 32 MHz. Loops until all oscillator fault flags are +//! cleared or until a timeout counter is decremented and equals to zero. +//! +//! \param baseAddress is the base address of the UCS module. +//! \param timeout is the count value that gets decremented every time the loop +//! that clears oscillator fault flags gets executed. +//! +//! Modified bits of \b UCSCTL7 register, bits of \b UCSCTL6 register and bits +//! of \b SFRIFG register. +//! +//! \return STATUS_SUCCESS or STATUS_FAIL +// +//***************************************************************************** +bool UCS_bypassXT2WithTimeout ( uint16_t baseAddress, + uint16_t timeout + ) +{ + assert(timeout > 0); + + //Switch off XT2 oscillator and enable BYPASS mode + HWREG16(baseAddress + OFS_UCSCTL6) |= (XT2BYPASS + XT2OFF ); + + do{ + //Clear OSC flaut Flags + HWREG8(baseAddress + OFS_UCSCTL7) &= ~(XT2OFFG); + +#if defined (__CC430F5133__) || (__CC430F5135__) || (__CC430F5137__) || \ + (__CC430F6125__) || (__CC430F6126__) || (__CC430F6127__) || \ + (__CC430F6135__) || (__CC430F6137__) || (__CC430F5123__) || \ + (__CC430F5125__) || (__CC430F5143__) || (__CC430F5145__) || \ + (__CC430F5147__) || (__CC430F6143__) || (__CC430F6145__) || \ + (__CC430F6147__) + // CC430 uses a different fault mechanism. It requires 3 VLO clock + // cycles delay.If 20MHz CPU, 5000 clock cycles are required in worst + // case. + __delay_cycles(5000); +#endif + + //Clear OFIFG fault flag + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + }while ((HWREG8(baseAddress + OFS_UCSCTL7) & XT2OFFG) && --timeout); + + if (timeout){ + return (STATUS_SUCCESS); + } else { + return (STATUS_FAIL); + } +} + +//***************************************************************************** +// +//! \brief Stops the XT2 oscillator using the XT2OFF bit. +//! +//! \param baseAddress is the base address of the UCS module. +//! +//! Modified bits of \b UCSCTL6 register. +//! +//! \return None +// +//***************************************************************************** +void UCS_XT2Off (uint16_t baseAddress) +{ + //Switch off XT2 oscillator + HWREG16(baseAddress + OFS_UCSCTL6) |= XT2OFF; +} + +//***************************************************************************** +// +//! \brief Initializes the DCO to operate a frequency that is a multiple of the +//! reference frequency into the FLL +//! +//! Initializes the DCO to operate a frequency that is a multiple of the +//! reference frequency into the FLL. Loops until all oscillator fault flags +//! are cleared, with a timeout. If the frequency is greater than 16 MHz, the +//! function sets the MCLK and SMCLK source to the undivided DCO frequency. +//! Otherwise, the function sets the MCLK and SMCLK source to the DCOCLKDIV +//! frequency. This function executes a software delay that is proportional in +//! length to the ratio of the target FLL frequency and the FLL reference. +//! +//! \param baseAddress is the base address of the UCS module. +//! \param fsystem is the target frequency for MCLK in kHz +//! \param ratio is the ratio x/y, where x = fsystem and y = FLL reference +//! frequency. +//! +//! Modified bits of \b UCSCTL0 register, bits of \b UCSCTL4 register, bits of +//! \b UCSCTL7 register, bits of \b UCSCTL1 register, bits of \b SFRIFG1 +//! register and bits of \b UCSCTL2 register. +//! +//! \return None +// +//***************************************************************************** +void UCS_initFLLSettle ( uint16_t baseAddress, + uint16_t fsystem, + uint16_t ratio + ) +{ + volatile uint16_t x = ratio * 32; + + UCS_initFLL(baseAddress, fsystem, ratio); + + while (x--) + { + __delay_cycles(30); + } +} + +//***************************************************************************** +// +//! \brief Initializes the DCO to operate a frequency that is a multiple of the +//! reference frequency into the FLL +//! +//! Initializes the DCO to operate a frequency that is a multiple of the +//! reference frequency into the FLL. Loops until all oscillator fault flags +//! are cleared, with no timeout. If the frequency is greater than 16 MHz, the +//! function sets the MCLK and SMCLK source to the undivided DCO frequency. +//! Otherwise, the function sets the MCLK and SMCLK source to the DCOCLKDIV +//! frequency. +//! +//! \param baseAddress is the base address of the UCS module. +//! \param fsystem is the target frequency for MCLK in kHz +//! \param ratio is the ratio x/y, where x = fsystem and y = FLL reference +//! frequency. +//! +//! Modified bits of \b UCSCTL0 register, bits of \b UCSCTL4 register, bits of +//! \b UCSCTL7 register, bits of \b UCSCTL1 register, bits of \b SFRIFG1 +//! register and bits of \b UCSCTL2 register. +//! +//! \return None +// +//***************************************************************************** +void UCS_initFLL ( uint16_t baseAddress, + uint16_t fsystem, + uint16_t ratio + ) +{ + uint16_t d, dco_div_bits; + uint16_t mode = 0; + + //Save actual state of FLL loop control, then disable it. This is needed to + //prevent the FLL from acting as we are making fundamental modifications to + //the clock setup. + uint16_t srRegisterState = __get_SR_register() & SCG0; + + d = ratio; + //Have at least a divider of 2 + dco_div_bits = FLLD__2; + + if (fsystem > 16000){ + d >>= 1 ; + mode = 1; + } else { + //fsystem = fsystem * 2 + fsystem <<= 1; + } + + while (d > 512) + { + //Set next higher div level + dco_div_bits = dco_div_bits + FLLD0; + d >>= 1; + } + + // Disable FLL + __bis_SR_register(SCG0); + + //Set DCO to lowest Tap + HWREG8(baseAddress + OFS_UCSCTL0_H) = 0x0000; + + //Reset FN bits + HWREG16(baseAddress + OFS_UCSCTL2) &= ~(0x03FF); + HWREG16(baseAddress + OFS_UCSCTL2) = dco_div_bits | (d - 1); + + if (fsystem <= 630){ //fsystem < 0.63MHz + HWREG8(baseAddress + OFS_UCSCTL1) = DCORSEL_0; + } else if (fsystem < 1250){ //0.63MHz < fsystem < 1.25MHz + HWREG8(baseAddress + OFS_UCSCTL1) = DCORSEL_1; + } else if (fsystem < 2500){ //1.25MHz < fsystem < 2.5MHz + HWREG8(baseAddress + OFS_UCSCTL1) = DCORSEL_2; + } else if (fsystem < 5000){ //2.5MHz < fsystem < 5MHz + HWREG8(baseAddress + OFS_UCSCTL1) = DCORSEL_3; + } else if (fsystem < 10000){ //5MHz < fsystem < 10MHz + HWREG8(baseAddress + OFS_UCSCTL1) = DCORSEL_4; + } else if (fsystem < 20000){ //10MHz < fsystem < 20MHz + HWREG8(baseAddress + OFS_UCSCTL1) = DCORSEL_5; + } else if (fsystem < 40000){ //20MHz < fsystem < 40MHz + HWREG8(baseAddress + OFS_UCSCTL1) = DCORSEL_6; + } else { + HWREG8(baseAddress + OFS_UCSCTL1) = DCORSEL_7; + } + + // Re-enable FLL + __bic_SR_register(SCG0); + + while (HWREG8(baseAddress + OFS_UCSCTL7_L) & DCOFFG) + { + //Clear OSC flaut Flags + HWREG8(baseAddress + OFS_UCSCTL7_L) &= ~(DCOFFG); + + //Clear OFIFG fault flag + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + } + + // Restore previous SCG0 + __bis_SR_register(srRegisterState); + + if (mode == 1){ + //fsystem > 16000 + //Select DCOCLK + HWREG16(baseAddress + OFS_UCSCTL4) &= ~(SELM_7 + SELS_7); + HWREG16(baseAddress + OFS_UCSCTL4) |= SELM__DCOCLK + SELS__DCOCLK; + } else { + //Select DCODIVCLK + HWREG16(baseAddress + OFS_UCSCTL4) &= ~(SELM_7 + SELS_7); + HWREG16(baseAddress + OFS_UCSCTL4) |= SELM__DCOCLKDIV + SELS__DCOCLKDIV; + } + +} + +//***************************************************************************** +// +//! \brief Enables conditional module requests +//! +//! \param baseAddress is the base address of the UCS module. +//! \param selectClock selects specific request enables +//! Valid values are: +//! - \b UCS_ACLK +//! - \b UCS_SMCLK +//! - \b UCS_MCLK +//! - \b UCS_MODOSC +//! +//! Modified bits of \b UCSCTL8 register. +//! +//! \return None +// +//***************************************************************************** +void UCS_enableClockRequest (uint16_t baseAddress, + uint8_t selectClock + ) +{ + HWREG8(baseAddress + OFS_UCSCTL8) |= selectClock; +} + +//***************************************************************************** +// +//! \brief Disables conditional module requests +//! +//! \param baseAddress is the base address of the UCS module. +//! \param selectClock selects specific request disable +//! Valid values are: +//! - \b UCS_ACLK +//! - \b UCS_SMCLK +//! - \b UCS_MCLK +//! - \b UCS_MODOSC +//! +//! Modified bits of \b UCSCTL8 register. +//! +//! \return None +// +//***************************************************************************** +void UCS_disableClockRequest (uint16_t baseAddress, + uint8_t selectClock + ) +{ + HWREG8(baseAddress + OFS_UCSCTL8) &= ~selectClock; +} + +//***************************************************************************** +// +//! \brief Gets the current UCS fault flag status. +//! +//! \param baseAddress is the base address of the UCS module. +//! \param mask is the masked interrupt flag status to be returned. Mask +//! parameter can be either any of the following selection. +//! Valid values are: +//! - \b UCS_XT2OFFG - XT2 oscillator fault flag +//! - \b UCS_XT1HFOFFG - XT1 oscillator fault flag (HF mode) +//! - \b UCS_XT1LFOFFG - XT1 oscillator fault flag (LF mode) +//! - \b UCS_DCOFFG - DCO fault flag +//! +// +//***************************************************************************** +uint8_t UCS_faultFlagStatus (uint16_t baseAddress, + uint8_t mask + ) +{ + assert(mask <= UCS_XT2OFFG ); + return (HWREG8(baseAddress + OFS_UCSCTL7) & mask); +} + +//***************************************************************************** +// +//! \brief Clears the current UCS fault flag status for the masked bit. +//! +//! \param baseAddress is the base address of the UCS module. +//! \param mask is the masked interrupt flag status to be returned. mask +//! parameter can be any one of the following +//! Valid values are: +//! - \b UCS_XT2OFFG - XT2 oscillator fault flag +//! - \b UCS_XT1HFOFFG - XT1 oscillator fault flag (HF mode) +//! - \b UCS_XT1LFOFFG - XT1 oscillator fault flag (LF mode) +//! - \b UCS_DCOFFG - DCO fault flag +//! +//! Modified bits of \b UCSCTL7 register. +//! +//! \return None +// +//***************************************************************************** +void UCS_clearFaultFlag (uint16_t baseAddress, + uint8_t mask + ) +{ + assert(mask <= UCS_XT2OFFG ); + HWREG8(baseAddress + OFS_UCSCTL7) &= ~mask; +} + +//***************************************************************************** +// +//! \brief Turns off SMCLK using the SMCLKOFF bit +//! +//! \param baseAddress is the base address of the UCS module. +//! +//! Modified bits of \b UCSCTL6 register. +//! +//! \return None +// +//***************************************************************************** +void UCS_SMCLKOff (uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_UCSCTL6) |= SMCLKOFF; +} + +//***************************************************************************** +// +//! \brief Turns ON SMCLK using the SMCLKOFF bit +//! +//! \param baseAddress is the base address of the UCS module. +//! +//! Modified bits of \b UCSCTL6 register. +//! +//! \return None +// +//***************************************************************************** +void UCS_SMCLKOn (uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_UCSCTL6) &= ~SMCLKOFF; +} + +//***************************************************************************** +// +//! \brief Get the current ACLK frequency +//! +//! Get the current ACLK frequency. The user of this API must ensure that +//! UCS_setExternalClockSource API was invoked before in case XT1 or XT2 is +//! being used. +//! +//! \param baseAddress is the base address of the UCS module. +//! +//! \return Current ACLK frequency in Hz +// +//***************************************************************************** +uint32_t UCS_getACLK (uint16_t baseAddress) +{ + //Find ACLK source + uint16_t ACLKSource = (HWREG16(baseAddress + OFS_UCSCTL4) & SELA_7); + + ACLKSource = ACLKSource >> 8; + + uint16_t ACLKSourceDivider = HWREG16(baseAddress + OFS_UCSCTL5) & DIVA_7; + ACLKSourceDivider = ACLKSourceDivider >> 8; + + return (privateUCSComputeCLKFrequency(baseAddress, + ACLKSource, + ACLKSourceDivider + )); +} + +//***************************************************************************** +// +//! \brief Get the current SMCLK frequency +//! +//! Get the current SMCLK frequency. The user of this API must ensure that +//! UCS_setExternalClockSource API was invoked before in case XT1 or XT2 is +//! being used. +//! +//! \param baseAddress is the base address of the UCS module. +//! +//! \return Current SMCLK frequency in Hz +// +//***************************************************************************** +uint32_t UCS_getSMCLK (uint16_t baseAddress) +{ + uint16_t SMCLKSource = HWREG8(baseAddress + OFS_UCSCTL4_L) & SELS_7; + + SMCLKSource = SMCLKSource >> 4; + + uint16_t SMCLKSourceDivider = + HWREG16(baseAddress + OFS_UCSCTL5) & DIVS_7; + SMCLKSourceDivider = SMCLKSourceDivider >> 4; + + return (privateUCSComputeCLKFrequency(baseAddress, + SMCLKSource, + SMCLKSourceDivider ) + ); +} + +//***************************************************************************** +// +//! \brief Get the current MCLK frequency +//! +//! Get the current MCLK frequency. The user of this API must ensure that +//! UCS_setExternalClockSource API was invoked before in case XT1 or XT2 is +//! being used. +//! +//! \param baseAddress is the base address of the UCS module. +//! +//! \return Current MCLK frequency in Hz +// +//***************************************************************************** +uint32_t UCS_getMCLK (uint16_t baseAddress) +{ + //Find AMCLK source + uint16_t MCLKSource = (HWREG16(baseAddress + OFS_UCSCTL4) & SELM_7); + + uint16_t MCLKSourceDivider = HWREG16(baseAddress + OFS_UCSCTL5) & DIVM_7; + + return (privateUCSComputeCLKFrequency(baseAddress, + MCLKSource, + MCLKSourceDivider ) + ); +} + +//***************************************************************************** +// +//! \brief Clears all the Oscillator Flags +//! +//! \param baseAddress is the base address of the UCS module. +//! \param timeout is the count value that gets decremented every time the loop +//! that clears oscillator fault flags gets executed. +//! +//! \return Logical OR of any of the following: +//! - \b UCS_XT2OFFG XT2 oscillator fault flag +//! - \b UCS_XT1HFOFFG XT1 oscillator fault flag (HF mode) +//! - \b UCS_XT1LFOFFG XT1 oscillator fault flag (LF mode) +//! - \b UCS_DCOFFG DCO fault flag +//! \n indicating the status of the oscillator fault flags +// +//***************************************************************************** +uint16_t UCS_clearAllOscFlagsWithTimeout(uint16_t baseAddress, + uint16_t timeout + ) +{ + assert(timeout > 0); + + do { + // Clear all osc fault flags + HWREG8(baseAddress + OFS_UCSCTL7) &= ~(DCOFFG + + XT1LFOFFG + + XT1HFOFFG + + XT2OFFG + ); + +#if defined (__CC430F5133__) || (__CC430F5135__) || (__CC430F5137__) || \ + (__CC430F6125__) || (__CC430F6126__) || (__CC430F6127__) || \ + (__CC430F6135__) || (__CC430F6137__) || (__CC430F5123__) || \ + (__CC430F5125__) || (__CC430F5143__) || (__CC430F5145__) || \ + (__CC430F5147__) || (__CC430F6143__) || (__CC430F6145__) || \ + (__CC430F6147__) + // CC430 uses a different fault mechanism. It requires 3 VLO clock + // cycles delay.If 20MHz CPU, 5000 clock cycles are required in worst + // case. + __delay_cycles(5000); +#endif + + // Clear the global osc fault flag. + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + + // Check XT1 fault flags + } while ((HWREG8(SFR_BASE + OFS_SFRIFG1) & OFIFG) && --timeout); + + return (HWREG8(baseAddress + OFS_UCSCTL7) & (DCOFFG + + XT1LFOFFG + + XT1HFOFFG + + XT2OFFG) + ); +} + +#endif +#endif +//***************************************************************************** +// +//! Close the doxygen group for ucs_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/deprecated/ucs.h b/source/driverlib/MSP430F5xx_6xx/deprecated/ucs.h new file mode 100644 index 0000000..0a6af05 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/deprecated/ucs.h @@ -0,0 +1,271 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// ucs.h - Driver for the UCS Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_UCS_H__ +#define __MSP430WARE_UCS_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_UCS__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Internal very low power VLOCLK, low frequency oscillator with 10 kHz typical +// frequency +// +//***************************************************************************** +#define UCS_VLOCLK_FREQUENCY 10000 + +//***************************************************************************** +// +// Internal, trimmed, low-frequency oscillator with 32768 Hz typical frequency +// +//***************************************************************************** +#define UCS_REFOCLK_FREQUENCY 32768 + +//***************************************************************************** +// +// The following are values that can be passed to the clockSourceDivider +// parameter for functions: UCS_clockSignalInit(). +// +//***************************************************************************** +#define UCS_CLOCK_DIVIDER_1 DIVM__1 +#define UCS_CLOCK_DIVIDER_2 DIVM__2 +#define UCS_CLOCK_DIVIDER_4 DIVM__4 +#define UCS_CLOCK_DIVIDER_8 DIVM__8 +#define UCS_CLOCK_DIVIDER_12 DIVM__32 +#define UCS_CLOCK_DIVIDER_16 DIVM__16 +#define UCS_CLOCK_DIVIDER_32 DIVM__32 + +//***************************************************************************** +// +// The following are values that can be passed to the selectedClockSignal +// parameter for functions: UCS_clockSignalInit(). +// +//***************************************************************************** +#define UCS_ACLK 0x01 +#define UCS_MCLK 0x02 +#define UCS_SMCLK 0x04 +#define UCS_FLLREF 0x08 + +//***************************************************************************** +// +// The following are values that can be passed to the clockSource parameter for +// functions: UCS_clockSignalInit(). +// +//***************************************************************************** +#define UCS_XT1CLK_SELECT SELM__XT1CLK +#define UCS_VLOCLK_SELECT SELM__VLOCLK +#define UCS_REFOCLK_SELECT SELM__REFOCLK +#define UCS_DCOCLK_SELECT SELM__DCOCLK +#define UCS_DCOCLKDIV_SELECT SELM__DCOCLKDIV +#define UCS_XT2CLK_SELECT SELM__XT2CLK + +//***************************************************************************** +// +// The following are values that can be passed to the xcap parameter for +// functions: UCS_LFXT1Start(), and UCS_LFXT1StartWithTimeout(). +// +//***************************************************************************** +#define UCS_XCAP_0 XCAP_0 +#define UCS_XCAP_1 XCAP_1 +#define UCS_XCAP_2 XCAP_2 +#define UCS_XCAP_3 XCAP_3 + +//***************************************************************************** +// +// The following are values that can be passed to the xt1drive parameter for +// functions: UCS_LFXT1Start(), UCS_HFXT1Start(), UCS_LFXT1StartWithTimeout(), +// and UCS_HFXT1StartWithTimeout(). +// +//***************************************************************************** +#define UCS_XT1_DRIVE0 XT1DRIVE_0 +#define UCS_XT1_DRIVE1 XT1DRIVE_1 +#define UCS_XT1_DRIVE2 XT1DRIVE_2 +#define UCS_XT1_DRIVE3 XT1DRIVE_3 + +//***************************************************************************** +// +// The following are values that can be passed to the highOrLowFrequency +// parameter for functions: UCS_bypassXT1(), and UCS_bypassXT1WithTimeout(). +// +//***************************************************************************** +#define UCS_XT1_HIGH_FREQUENCY XTS +#define UCS_XT1_LOW_FREQUENCY 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the xt2drive parameter for +// functions: UCS_XT2Start(), and UCS_XT2StartWithTimeout(). +// +//***************************************************************************** +#define UCS_XT2DRIVE_4MHZ_8MHZ XT2DRIVE_0 +#define UCS_XT2DRIVE_8MHZ_16MHZ XT2DRIVE_1 +#define UCS_XT2DRIVE_16MHZ_24MHZ XT2DRIVE_2 +#define UCS_XT2DRIVE_24MHZ_32MHZ XT2DRIVE_3 + +//***************************************************************************** +// +// The following are values that can be passed to the selectClock parameter for +// functions: UCS_enableClockRequest(), and UCS_disableClockRequest(). +// +//***************************************************************************** +#define UCS_ACLK 0x01 +#define UCS_SMCLK 0x04 +#define UCS_MCLK 0x02 +#define UCS_MODOSC MODOSCREQEN + +//***************************************************************************** +// +// The following are values that can be passed to the mask parameter for +// functions: UCS_faultFlagStatus(), and UCS_clearFaultFlag() as well as +// returned by the UCS_clearAllOscFlagsWithTimeout() function. +// +//***************************************************************************** +#define UCS_XT2OFFG XT2OFFG +#define UCS_XT1HFOFFG XT1HFOFFG +#define UCS_XT1LFOFFG XT1LFOFFG +#define UCS_DCOFFG DCOFFG + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void UCS_setExternalClockSource(uint16_t baseAddress, + uint32_t XT1CLK_frequency, + uint32_t XT2CLK_frequency); + +extern void UCS_clockSignalInit(uint16_t baseAddress, + uint8_t selectedClockSignal, + uint16_t clockSource, + uint16_t clockSourceDivider); + +extern void UCS_LFXT1Start(uint16_t baseAddress, + uint16_t xt1drive, + uint8_t xcap); + +extern void UCS_HFXT1Start(uint16_t baseAddress, + uint16_t xt1drive); + +extern void UCS_bypassXT1(uint16_t baseAddress, + uint8_t highOrLowFrequency); + +extern bool UCS_LFXT1StartWithTimeout(uint16_t baseAddress, + uint16_t xt1drive, + uint8_t xcap, + uint16_t timeout); + +extern bool UCS_HFXT1StartWithTimeout(uint16_t baseAddress, + uint16_t xt1drive, + uint16_t timeout); + +extern bool UCS_bypassXT1WithTimeout(uint16_t baseAddress, + uint8_t highOrLowFrequency, + uint16_t timeout); + +extern void UCS_XT1Off(uint16_t baseAddress); + +extern void UCS_XT2Start(uint16_t baseAddress, + uint16_t xt2drive); + +extern void UCS_bypassXT2(uint16_t baseAddress); + +extern bool UCS_XT2StartWithTimeout(uint16_t baseAddress, + uint16_t xt2drive, + uint16_t timeout); + +extern bool UCS_bypassXT2WithTimeout(uint16_t baseAddress, + uint16_t timeout); + +extern void UCS_XT2Off(uint16_t baseAddress); + +extern void UCS_initFLLSettle(uint16_t baseAddress, + uint16_t fsystem, + uint16_t ratio); + +extern void UCS_initFLL(uint16_t baseAddress, + uint16_t fsystem, + uint16_t ratio); + +extern void UCS_enableClockRequest(uint16_t baseAddress, + uint8_t selectClock); + +extern void UCS_disableClockRequest(uint16_t baseAddress, + uint8_t selectClock); + +extern uint8_t UCS_faultFlagStatus(uint16_t baseAddress, + uint8_t mask); + +extern void UCS_clearFaultFlag(uint16_t baseAddress, + uint8_t mask); + +extern void UCS_SMCLKOff(uint16_t baseAddress); + +extern void UCS_SMCLKOn(uint16_t baseAddress); + +extern uint32_t UCS_getACLK(uint16_t baseAddress); + +extern uint32_t UCS_getSMCLK(uint16_t baseAddress); + +extern uint32_t UCS_getMCLK(uint16_t baseAddress); + +extern uint16_t UCS_clearAllOscFlagsWithTimeout(uint16_t baseAddress, + uint16_t timeout); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_UCS_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/dma.c b/source/driverlib/MSP430F5xx_6xx/dma.c new file mode 100644 index 0000000..fa3ca10 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/dma.c @@ -0,0 +1,737 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// dma.c - Driver for the dma Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup dma_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifndef DRIVERLIB_LEGACY_MODE + +#if defined(__MSP430_HAS_DMAX_3__) || defined(__MSP430_HAS_DMAX_6__) +#include "dma.h" + +#include + +//***************************************************************************** +// +//! \brief DEPRECATED - Initializes the specified DMA channel. +//! +//! This function initializes the specified DMA channel. Upon successful +//! completion of initialization of the selected channel the control registers +//! will be cleared and the given variables will be set. Please note, if +//! transfers have been enabled with the enableTransfers() function, then a +//! call to disableTransfers() is necessary before re-initialization. Also +//! note, that the trigger sources are device dependent and can be found in the +//! device family data sheet. The amount of DMA channels available are also +//! device specific. +//! +//! \param channelSelect is the specified channel to initialize. +//! Valid values are: +//! - \b DMA_CHANNEL_0 +//! - \b DMA_CHANNEL_1 +//! - \b DMA_CHANNEL_2 +//! - \b DMA_CHANNEL_3 +//! - \b DMA_CHANNEL_4 +//! - \b DMA_CHANNEL_5 +//! - \b DMA_CHANNEL_6 +//! - \b DMA_CHANNEL_7 +//! \param transferModeSelect is the transfer mode of the selected channel. +//! Valid values are: +//! - \b DMA_TRANSFER_SINGLE [Default] - Single transfer, transfers +//! disabled after transferAmount of transfers. +//! - \b DMA_TRANSFER_BLOCK - Multiple transfers of transferAmount, +//! transfers disabled once finished. +//! - \b DMA_TRANSFER_BURSTBLOCK - Multiple transfers of transferAmount +//! interleaved with CPU activity, transfers disabled once finished. +//! - \b DMA_TRANSFER_REPEATED_SINGLE - Repeated single transfer by +//! trigger. +//! - \b DMA_TRANSFER_REPEATED_BLOCK - Multiple transfers of +//! transferAmount by trigger. +//! - \b DMA_TRANSFER_REPEATED_BURSTBLOCK - Multiple transfers of +//! transferAmount by trigger interleaved with CPU activity. +//! \n Modified bits are \b DMADT of \b DMAxCTL register. +//! \param transferSize is the amount of transfers to complete in a block +//! transfer mode, as well as how many transfers to complete before the +//! interrupt flag is set. Valid value is between 1-65535, if 0, no +//! transfers will occur. +//! \n Modified bits are \b DMAxSZ of \b DMAxSZ register. +//! \param triggerSourceSelect is the source that will trigger the start of +//! each transfer, note that the sources are device specific. +//! Valid values are: +//! - \b DMA_TRIGGERSOURCE_0 [Default] +//! - \b DMA_TRIGGERSOURCE_1 +//! - \b DMA_TRIGGERSOURCE_2 +//! - \b DMA_TRIGGERSOURCE_3 +//! - \b DMA_TRIGGERSOURCE_4 +//! - \b DMA_TRIGGERSOURCE_5 +//! - \b DMA_TRIGGERSOURCE_6 +//! - \b DMA_TRIGGERSOURCE_7 +//! - \b DMA_TRIGGERSOURCE_8 +//! - \b DMA_TRIGGERSOURCE_9 +//! - \b DMA_TRIGGERSOURCE_10 +//! - \b DMA_TRIGGERSOURCE_11 +//! - \b DMA_TRIGGERSOURCE_12 +//! - \b DMA_TRIGGERSOURCE_13 +//! - \b DMA_TRIGGERSOURCE_14 +//! - \b DMA_TRIGGERSOURCE_15 +//! - \b DMA_TRIGGERSOURCE_16 +//! - \b DMA_TRIGGERSOURCE_17 +//! - \b DMA_TRIGGERSOURCE_18 +//! - \b DMA_TRIGGERSOURCE_19 +//! - \b DMA_TRIGGERSOURCE_20 +//! - \b DMA_TRIGGERSOURCE_21 +//! - \b DMA_TRIGGERSOURCE_22 +//! - \b DMA_TRIGGERSOURCE_23 +//! - \b DMA_TRIGGERSOURCE_24 +//! - \b DMA_TRIGGERSOURCE_25 +//! - \b DMA_TRIGGERSOURCE_26 +//! - \b DMA_TRIGGERSOURCE_27 +//! - \b DMA_TRIGGERSOURCE_28 +//! - \b DMA_TRIGGERSOURCE_29 +//! - \b DMA_TRIGGERSOURCE_30 +//! - \b DMA_TRIGGERSOURCE_31 +//! \n Modified bits are \b DMAxTSEL of \b DMACTLx register. +//! \param transferUnitSelect is the specified size of transfers. +//! Valid values are: +//! - \b DMA_SIZE_SRCWORD_DSTWORD [Default] +//! - \b DMA_SIZE_SRCBYTE_DSTWORD +//! - \b DMA_SIZE_SRCWORD_DSTBYTE +//! - \b DMA_SIZE_SRCBYTE_DSTBYTE +//! \n Modified bits are \b DMASRCBYTE and \b DMADSTBYTE of \b DMAxCTL +//! register. +//! \param triggerTypeSelect is the type of trigger that the trigger signal +//! needs to be to start a transfer. +//! Valid values are: +//! - \b DMA_TRIGGER_RISINGEDGE [Default] +//! - \b DMA_TRIGGER_HIGH - A trigger would be a high signal from the +//! trigger source, to be held high through the length of the +//! transfer(s). +//! \n Modified bits are \b DMALEVEL of \b DMAxCTL register. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the initialization process. +// +//***************************************************************************** +bool DMA_init(uint8_t channelSelect, + uint16_t transferModeSelect, + uint16_t transferSize, + uint8_t triggerSourceSelect, + uint8_t transferUnitSelect, + uint8_t triggerTypeSelect) +{ + DMA_initializeParam param = { 0 }; + + param.channelSelect = channelSelect; + param.transferModeSelect = transferModeSelect; + param.transferSize = transferSize; + param.triggerSourceSelect = triggerSourceSelect; + param.transferUnitSelect = transferUnitSelect; + param.triggerTypeSelect = triggerTypeSelect; + + return DMA_initialize(¶m); +} + +//***************************************************************************** +// +//! \brief Initializes the specified DMA channel. +//! +//! This function initializes the specified DMA channel. Upon successful +//! completion of initialization of the selected channel the control registers +//! will be cleared and the given variables will be set. Please note, if +//! transfers have been enabled with the enableTransfers() function, then a +//! call to disableTransfers() is necessary before re-initialization. Also +//! note, that the trigger sources are device dependent and can be found in the +//! device family data sheet. The amount of DMA channels available are also +//! device specific. +//! +//! \param param is the pointer to struct for initialization. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the initialization process. +// +//***************************************************************************** +bool DMA_initialize( DMA_initializeParam *param) +{ + assert(param != 0); + assert(param->channelSelect <= DMA_CHANNEL_7); + assert(param->transferModeSelect <= DMA_TRANSFER_REPEATED_BURSTBLOCK); + assert(param->triggerSourceSelect <= DMA_TRIGGERSOURCE_31); + assert(param->transferUnitSelect <= DMA_SIZE_SRCBYTE_DSTBYTE); + assert(param->triggerTypeSelect <= DMA_TRIGGER_HIGH); + + bool retVal = STATUS_SUCCESS; + uint8_t triggerOffset = (param->channelSelect >> 4); + + //Reset and Set DMA Control 0 Register + HWREG16(DMA_BASE + param->channelSelect + OFS_DMA0CTL) = + param->transferModeSelect //Set Transfer Mode + + param->transferUnitSelect //Set Transfer Unit Size + + param->triggerTypeSelect; //Set Trigger Type + + //Set Transfer Size Amount + HWREG16(DMA_BASE + param->channelSelect + OFS_DMA0SZ) = param->transferSize; + + if (triggerOffset & 0x01) { //Odd Channel + HWREG16(DMA_BASE + (triggerOffset & 0x0E)) &= 0x00FF; //Reset Trigger Select + HWREG16(DMA_BASE + + (triggerOffset & 0x0E)) |= (param->triggerSourceSelect << 8); + } else { //Even Channel + HWREG16(DMA_BASE + (triggerOffset & 0x0E)) &= 0xFF00; //Reset Trigger Select + HWREG16(DMA_BASE + (triggerOffset & 0x0E)) |= param->triggerSourceSelect; + } + + return retVal; +} +//***************************************************************************** +// +//! \brief Sets the specified amount of transfers for the selected DMA channel. +//! +//! This function sets the specified amount of transfers for the selected DMA +//! channel without having to reinitialize the DMA channel. +//! +//! \param channelSelect is the specified channel to set source address +//! direction for. +//! Valid values are: +//! - \b DMA_CHANNEL_0 +//! - \b DMA_CHANNEL_1 +//! - \b DMA_CHANNEL_2 +//! - \b DMA_CHANNEL_3 +//! - \b DMA_CHANNEL_4 +//! - \b DMA_CHANNEL_5 +//! - \b DMA_CHANNEL_6 +//! - \b DMA_CHANNEL_7 +//! \param transferSize is the amount of transfers to complete in a block +//! transfer mode, as well as how many transfers to complete before the +//! interrupt flag is set. Valid value is between 1-65535, if 0, no +//! transfers will occur. +//! \n Modified bits are \b DMAxSZ of \b DMAxSZ register. +//! +//! \return None +// +//***************************************************************************** +void DMA_setTransferSize(uint8_t channelSelect, + uint16_t transferSize) +{ + //Set Transfer Size Amount + HWREG16(DMA_BASE + channelSelect + OFS_DMA0SZ) = transferSize; +} + +//***************************************************************************** +// +//! \brief Sets source address and the direction that the source address will +//! move after a transfer. +//! +//! This function sets the source address and the direction that the source +//! address will move after a transfer is complete. It may be incremented, +//! decremented or unchanged. +//! +//! \param channelSelect is the specified channel to set source address +//! direction for. +//! Valid values are: +//! - \b DMA_CHANNEL_0 +//! - \b DMA_CHANNEL_1 +//! - \b DMA_CHANNEL_2 +//! - \b DMA_CHANNEL_3 +//! - \b DMA_CHANNEL_4 +//! - \b DMA_CHANNEL_5 +//! - \b DMA_CHANNEL_6 +//! - \b DMA_CHANNEL_7 +//! \param srcAddress is the address of where the data will be transferred +//! from. +//! \n Modified bits are \b DMAxSA of \b DMAxSA register. +//! \param directionSelect is the specified direction of the source address +//! after a transfer. +//! Valid values are: +//! - \b DMA_DIRECTION_UNCHANGED +//! - \b DMA_DIRECTION_DECREMENT +//! - \b DMA_DIRECTION_INCREMENT +//! \n Modified bits are \b DMASRCINCR of \b DMAxCTL register. +//! +//! \return None +// +//***************************************************************************** +void DMA_setSrcAddress(uint8_t channelSelect, + uint32_t srcAddress, + uint16_t directionSelect) +{ + assert(channelSelect <= DMA_CHANNEL_7); + assert(directionSelect <= DMA_DIRECTION_INCREMENT); + + //Set the Source Address + __data16_write_addr((unsigned short)(DMA_BASE + channelSelect + OFS_DMA0SA), + srcAddress); + + //Reset bits before setting them + HWREG16(DMA_BASE + channelSelect + OFS_DMA0CTL) &= ~(DMASRCINCR_3); + HWREG16(DMA_BASE + channelSelect + OFS_DMA0CTL) |= directionSelect; +} + +//***************************************************************************** +// +//! \brief Sets the destination address and the direction that the destination +//! address will move after a transfer. +//! +//! This function sets the destination address and the direction that the +//! destination address will move after a transfer is complete. It may be +//! incremented, decremented, or unchanged. +//! +//! \param channelSelect is the specified channel to set the destination +//! address direction for. +//! Valid values are: +//! - \b DMA_CHANNEL_0 +//! - \b DMA_CHANNEL_1 +//! - \b DMA_CHANNEL_2 +//! - \b DMA_CHANNEL_3 +//! - \b DMA_CHANNEL_4 +//! - \b DMA_CHANNEL_5 +//! - \b DMA_CHANNEL_6 +//! - \b DMA_CHANNEL_7 +//! \param dstAddress is the address of where the data will be transferred to. +//! \n Modified bits are \b DMAxDA of \b DMAxDA register. +//! \param directionSelect is the specified direction of the destination +//! address after a transfer. +//! Valid values are: +//! - \b DMA_DIRECTION_UNCHANGED +//! - \b DMA_DIRECTION_DECREMENT +//! - \b DMA_DIRECTION_INCREMENT +//! \n Modified bits are \b DMADSTINCR of \b DMAxCTL register. +//! +//! \return None +// +//***************************************************************************** +void DMA_setDstAddress(uint8_t channelSelect, + uint32_t dstAddress, + uint16_t directionSelect) +{ + assert(channelSelect <= DMA_CHANNEL_7); + assert(directionSelect <= DMA_DIRECTION_INCREMENT); + + //Set the Destination Address + __data16_write_addr((unsigned short)(DMA_BASE + channelSelect + OFS_DMA0DA), + dstAddress); + + //Reset bits before setting them + HWREG16(DMA_BASE + channelSelect + OFS_DMA0CTL) &= ~(DMADSTINCR_3); + HWREG16(DMA_BASE + channelSelect + OFS_DMA0CTL) |= (directionSelect << 2); +} + +//***************************************************************************** +// +//! \brief Enables transfers to be triggered. +//! +//! This function enables transfers upon appropriate trigger of the selected +//! trigger source for the selected channel. +//! +//! \param channelSelect is the specified channel to enable transfer for. +//! Valid values are: +//! - \b DMA_CHANNEL_0 +//! - \b DMA_CHANNEL_1 +//! - \b DMA_CHANNEL_2 +//! - \b DMA_CHANNEL_3 +//! - \b DMA_CHANNEL_4 +//! - \b DMA_CHANNEL_5 +//! - \b DMA_CHANNEL_6 +//! - \b DMA_CHANNEL_7 +//! +//! \return None +// +//***************************************************************************** +void DMA_enableTransfers(uint8_t channelSelect) +{ + assert(channelSelect <= DMA_CHANNEL_7); + + HWREG16(DMA_BASE + channelSelect + OFS_DMA0CTL) |= DMAEN; +} + +//***************************************************************************** +// +//! \brief Disables transfers from being triggered. +//! +//! This function disables transfer from being triggered for the selected +//! channel. This function should be called before any re-initialization of the +//! selected DMA channel. +//! +//! \param channelSelect is the specified channel to disable transfers for. +//! Valid values are: +//! - \b DMA_CHANNEL_0 +//! - \b DMA_CHANNEL_1 +//! - \b DMA_CHANNEL_2 +//! - \b DMA_CHANNEL_3 +//! - \b DMA_CHANNEL_4 +//! - \b DMA_CHANNEL_5 +//! - \b DMA_CHANNEL_6 +//! - \b DMA_CHANNEL_7 +//! +//! \return None +// +//***************************************************************************** +void DMA_disableTransfers(uint8_t channelSelect) +{ + assert(channelSelect <= DMA_CHANNEL_7); + + HWREG16(DMA_BASE + channelSelect + OFS_DMA0CTL) &= ~(DMAEN); +} + +//***************************************************************************** +// +//! \brief Starts a transfer if using the default trigger source selected in +//! initialization. +//! +//! This functions triggers a transfer of data from source to destination if +//! the trigger source chosen from initialization is the DMA_TRIGGERSOURCE_0. +//! Please note, this function needs to be called for each (repeated-)single +//! transfer, and when transferAmount of transfers have been complete in +//! (repeated-)block transfers. +//! +//! \param channelSelect is the specified channel to start transfers for. +//! Valid values are: +//! - \b DMA_CHANNEL_0 +//! - \b DMA_CHANNEL_1 +//! - \b DMA_CHANNEL_2 +//! - \b DMA_CHANNEL_3 +//! - \b DMA_CHANNEL_4 +//! - \b DMA_CHANNEL_5 +//! - \b DMA_CHANNEL_6 +//! - \b DMA_CHANNEL_7 +//! +//! \return None +// +//***************************************************************************** +void DMA_startTransfer(uint8_t channelSelect) +{ + assert(channelSelect <= DMA_CHANNEL_7); + + HWREG16(DMA_BASE + channelSelect + OFS_DMA0CTL) |= DMAREQ; +} + +//***************************************************************************** +// +//! \brief Enables the DMA interrupt for the selected channel. +//! +//! Enables the DMA interrupt source. Only the sources that are enabled can be +//! reflected to the processor interrupt; disabled sources have no effect on +//! the processor. Does not clear interrupt flags. +//! +//! \param channelSelect is the specified channel to enable the interrupt for. +//! Valid values are: +//! - \b DMA_CHANNEL_0 +//! - \b DMA_CHANNEL_1 +//! - \b DMA_CHANNEL_2 +//! - \b DMA_CHANNEL_3 +//! - \b DMA_CHANNEL_4 +//! - \b DMA_CHANNEL_5 +//! - \b DMA_CHANNEL_6 +//! - \b DMA_CHANNEL_7 +//! +//! \return None +// +//***************************************************************************** +void DMA_enableInterrupt(uint8_t channelSelect) +{ + assert(channelSelect <= DMA_CHANNEL_7); + + HWREG16(DMA_BASE + channelSelect + OFS_DMA0CTL) |= DMAIE; +} + +//***************************************************************************** +// +//! \brief Disables the DMA interrupt for the selected channel. +//! +//! Disables the DMA interrupt source. Only the sources that are enabled can be +//! reflected to the processor interrupt; disabled sources have no effect on +//! the processor. +//! +//! \param channelSelect is the specified channel to disable the interrupt for. +//! Valid values are: +//! - \b DMA_CHANNEL_0 +//! - \b DMA_CHANNEL_1 +//! - \b DMA_CHANNEL_2 +//! - \b DMA_CHANNEL_3 +//! - \b DMA_CHANNEL_4 +//! - \b DMA_CHANNEL_5 +//! - \b DMA_CHANNEL_6 +//! - \b DMA_CHANNEL_7 +//! +//! \return None +// +//***************************************************************************** +void DMA_disableInterrupt(uint8_t channelSelect) +{ + assert(channelSelect <= DMA_CHANNEL_7); + + HWREG16(DMA_BASE + channelSelect + OFS_DMA0CTL) &= ~(DMAIE); +} + +//***************************************************************************** +// +//! \brief Returns the status of the interrupt flag for the selected channel. +//! +//! Returns the status of the interrupt flag for the selected channel. +//! +//! \param channelSelect is the specified channel to return the interrupt flag +//! status from. +//! Valid values are: +//! - \b DMA_CHANNEL_0 +//! - \b DMA_CHANNEL_1 +//! - \b DMA_CHANNEL_2 +//! - \b DMA_CHANNEL_3 +//! - \b DMA_CHANNEL_4 +//! - \b DMA_CHANNEL_5 +//! - \b DMA_CHANNEL_6 +//! - \b DMA_CHANNEL_7 +//! +//! \return One of the following: +//! - \b DMA_INT_INACTIVE +//! - \b DMA_INT_ACTIVE +//! \n indicating the status of the current interrupt flag +// +//***************************************************************************** +uint16_t DMA_getInterruptStatus(uint8_t channelSelect) +{ + assert(channelSelect <= DMA_CHANNEL_7); + + return HWREG16(DMA_BASE + channelSelect + OFS_DMA0CTL) & DMAIFG; +} + +//***************************************************************************** +// +//! \brief Clears the interrupt flag for the selected channel. +//! +//! This function clears the DMA interrupt flag is cleared, so that it no +//! longer asserts. +//! +//! \param channelSelect is the specified channel to clear the interrupt flag +//! for. +//! Valid values are: +//! - \b DMA_CHANNEL_0 +//! - \b DMA_CHANNEL_1 +//! - \b DMA_CHANNEL_2 +//! - \b DMA_CHANNEL_3 +//! - \b DMA_CHANNEL_4 +//! - \b DMA_CHANNEL_5 +//! - \b DMA_CHANNEL_6 +//! - \b DMA_CHANNEL_7 +//! +//! \return None +// +//***************************************************************************** +void DMA_clearInterrupt(uint8_t channelSelect) +{ + assert(channelSelect <= DMA_CHANNEL_7); + + HWREG16(DMA_BASE + channelSelect + OFS_DMA0CTL) &= ~(DMAIFG); +} + +//***************************************************************************** +// +//! \brief Returns the status of the NMIAbort for the selected channel. +//! +//! This function returns the status of the NMI Abort flag for the selected +//! channel. If this flag has been set, it is because a transfer on this +//! channel was aborted due to a interrupt from an NMI. +//! +//! \param channelSelect is the specified channel to return the status of the +//! NMI Abort flag for. +//! Valid values are: +//! - \b DMA_CHANNEL_0 +//! - \b DMA_CHANNEL_1 +//! - \b DMA_CHANNEL_2 +//! - \b DMA_CHANNEL_3 +//! - \b DMA_CHANNEL_4 +//! - \b DMA_CHANNEL_5 +//! - \b DMA_CHANNEL_6 +//! - \b DMA_CHANNEL_7 +//! +//! \return One of the following: +//! - \b DMA_NOTABORTED +//! - \b DMA_ABORTED +//! \n indicating the status of the NMIAbort for the selected channel +// +//***************************************************************************** +uint16_t DMA_NMIAbortStatus(uint8_t channelSelect) +{ + assert(channelSelect <= DMA_CHANNEL_7); + + return HWREG16(DMA_BASE + channelSelect + OFS_DMA0CTL) & DMAABORT; +} + +//***************************************************************************** +// +//! \brief Clears the status of the NMIAbort to proceed with transfers for the +//! selected channel. +//! +//! This function clears the status of the NMI Abort flag for the selected +//! channel to allow for transfers on the channel to continue. +//! +//! \param channelSelect is the specified channel to clear the NMI Abort flag +//! for. +//! Valid values are: +//! - \b DMA_CHANNEL_0 +//! - \b DMA_CHANNEL_1 +//! - \b DMA_CHANNEL_2 +//! - \b DMA_CHANNEL_3 +//! - \b DMA_CHANNEL_4 +//! - \b DMA_CHANNEL_5 +//! - \b DMA_CHANNEL_6 +//! - \b DMA_CHANNEL_7 +//! +//! \return None +// +//***************************************************************************** +void DMA_clearNMIAbort(uint8_t channelSelect) +{ + assert(channelSelect <= DMA_CHANNEL_7); + + HWREG16(DMA_BASE + channelSelect + OFS_DMA0CTL) &= ~(DMAABORT); +} + +//***************************************************************************** +// +//! \brief Disables the DMA from stopping the CPU during a Read-Modify-Write +//! Operation to start a transfer. +//! +//! This function allows the CPU to finish any read-modify-write operations it +//! may be in the middle of before transfers of and DMA channel stop the CPU. +//! +//! +//! \return None +// +//***************************************************************************** +void DMA_disableTransferDuringReadModifyWrite(void) +{ + HWREG16(DMA_BASE + OFS_DMACTL4) |= DMARMWDIS; +} + +//***************************************************************************** +// +//! \brief Enables the DMA to stop the CPU during a Read-Modify-Write Operation +//! to start a transfer. +//! +//! This function allows the DMA to stop the CPU in the middle of a read- +//! modify-write operation to transfer data. +//! +//! +//! \return None +// +//***************************************************************************** +void DMA_enableTransferDuringReadModifyWrite(void) +{ + HWREG16(DMA_BASE + OFS_DMACTL4) &= ~(DMARMWDIS); +} + +//***************************************************************************** +// +//! \brief Enables Round Robin prioritization. +//! +//! This function enables Round Robin Prioritization of DMA channels. In the +//! case of Round Robin Prioritization, the last DMA channel to have +//! transferred data then has the last priority, which comes into play when +//! multiple DMA channels are ready to transfer at the same time. +//! +//! +//! \return None +// +//***************************************************************************** +void DMA_enableRoundRobinPriority(void) +{ + HWREG16(DMA_BASE + OFS_DMACTL4) |= ROUNDROBIN; +} + +//***************************************************************************** +// +//! \brief Disables Round Robin prioritization. +//! +//! This function disables Round Robin Prioritization, enabling static +//! prioritization of the DMA channels. In static prioritization, the DMA +//! channels are prioritized with the lowest DMA channel index having the +//! highest priority (i.e. DMA Channel 0 has the highest priority). +//! +//! +//! \return None +// +//***************************************************************************** +void DMA_disableRoundRobinPriority(void) +{ + HWREG16(DMA_BASE + OFS_DMACTL4) &= ~(ROUNDROBIN); +} + +//***************************************************************************** +// +//! \brief Enables a NMI to interrupt a DMA transfer. +//! +//! This function allow NMI's to interrupting any DMA transfer currently in +//! progress and stops any future transfers to begin before the NMI is done +//! processing. +//! +//! +//! \return None +// +//***************************************************************************** +void DMA_enableNMIAbort(void) +{ + HWREG16(DMA_BASE + OFS_DMACTL4) |= ENNMI; +} + +//***************************************************************************** +// +//! \brief Disables any NMI from interrupting a DMA transfer. +//! +//! This function disables NMI's from interrupting any DMA transfer currently +//! in progress. +//! +//! +//! \return None +// +//***************************************************************************** +void DMA_disableNMIAbort(void) +{ + HWREG16(DMA_BASE + OFS_DMACTL4) &= ~(ENNMI); +} + + +#endif +#endif +//***************************************************************************** +// +//! Close the doxygen group for dma_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/dma.h b/source/driverlib/MSP430F5xx_6xx/dma.h new file mode 100644 index 0000000..4fc098d --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/dma.h @@ -0,0 +1,260 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// dma.h - Driver for the DMA Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_DMA_H__ +#define __MSP430WARE_DMA_H__ + +#include "inc/hw_memmap.h" + +#if defined(__MSP430_HAS_DMAX_3__) || defined(__MSP430_HAS_DMAX_6__) + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//****************************************************************************** +// +// The following is a struct that is passed to DMA_initialize() +// +//****************************************************************************** +typedef struct DMA_initializeParam { + uint8_t channelSelect; + uint16_t transferModeSelect; + uint16_t transferSize; + uint8_t triggerSourceSelect; + uint8_t transferUnitSelect; + uint8_t triggerTypeSelect; +} DMA_initializeParam; + + +//***************************************************************************** +// +// The following are values that can be passed to the triggerSourceSelect +// parameter for functions: DMA_init(). +// +//***************************************************************************** +#define DMA_TRIGGERSOURCE_0 (0x00) +#define DMA_TRIGGERSOURCE_1 (0x01) +#define DMA_TRIGGERSOURCE_2 (0x02) +#define DMA_TRIGGERSOURCE_3 (0x03) +#define DMA_TRIGGERSOURCE_4 (0x04) +#define DMA_TRIGGERSOURCE_5 (0x05) +#define DMA_TRIGGERSOURCE_6 (0x06) +#define DMA_TRIGGERSOURCE_7 (0x07) +#define DMA_TRIGGERSOURCE_8 (0x08) +#define DMA_TRIGGERSOURCE_9 (0x09) +#define DMA_TRIGGERSOURCE_10 (0x0A) +#define DMA_TRIGGERSOURCE_11 (0x0B) +#define DMA_TRIGGERSOURCE_12 (0x0C) +#define DMA_TRIGGERSOURCE_13 (0x0D) +#define DMA_TRIGGERSOURCE_14 (0x0E) +#define DMA_TRIGGERSOURCE_15 (0x0F) +#define DMA_TRIGGERSOURCE_16 (0x10) +#define DMA_TRIGGERSOURCE_17 (0x11) +#define DMA_TRIGGERSOURCE_18 (0x12) +#define DMA_TRIGGERSOURCE_19 (0x13) +#define DMA_TRIGGERSOURCE_20 (0x14) +#define DMA_TRIGGERSOURCE_21 (0x15) +#define DMA_TRIGGERSOURCE_22 (0x16) +#define DMA_TRIGGERSOURCE_23 (0x17) +#define DMA_TRIGGERSOURCE_24 (0x18) +#define DMA_TRIGGERSOURCE_25 (0x19) +#define DMA_TRIGGERSOURCE_26 (0x1A) +#define DMA_TRIGGERSOURCE_27 (0x1B) +#define DMA_TRIGGERSOURCE_28 (0x1C) +#define DMA_TRIGGERSOURCE_29 (0x1D) +#define DMA_TRIGGERSOURCE_30 (0x1E) +#define DMA_TRIGGERSOURCE_31 (0x1F) + +//***************************************************************************** +// +// The following are values that can be passed to the transferModeSelect +// parameter for functions: DMA_init(). +// +//***************************************************************************** +#define DMA_TRANSFER_SINGLE (DMADT_0) +#define DMA_TRANSFER_BLOCK (DMADT_1) +#define DMA_TRANSFER_BURSTBLOCK (DMADT_2) +#define DMA_TRANSFER_REPEATED_SINGLE (DMADT_4) +#define DMA_TRANSFER_REPEATED_BLOCK (DMADT_5) +#define DMA_TRANSFER_REPEATED_BURSTBLOCK (DMADT_6) + +//***************************************************************************** +// +// The following are values that can be passed to the channelSelect parameter +// for functions: DMA_init(), DMA_setTransferSize(), DMA_setSrcAddress(), +// DMA_setDstAddress(), DMA_enableTransfers(), DMA_disableTransfers(), +// DMA_startTransfer(), DMA_enableInterrupt(), DMA_disableInterrupt(), +// DMA_getInterruptStatus(), DMA_clearInterrupt(), DMA_NMIAbortStatus(), and +// DMA_clearNMIAbort(). +// +//***************************************************************************** +#define DMA_CHANNEL_0 (0x00) +#define DMA_CHANNEL_1 (0x10) +#define DMA_CHANNEL_2 (0x20) +#define DMA_CHANNEL_3 (0x30) +#define DMA_CHANNEL_4 (0x40) +#define DMA_CHANNEL_5 (0x50) +#define DMA_CHANNEL_6 (0x60) +#define DMA_CHANNEL_7 (0x70) + +//***************************************************************************** +// +// The following are values that can be passed to the triggerTypeSelect +// parameter for functions: DMA_init(). +// +//***************************************************************************** +#define DMA_TRIGGER_RISINGEDGE (!(DMALEVEL)) +#define DMA_TRIGGER_HIGH (DMALEVEL) + +//***************************************************************************** +// +// The following are values that can be passed to the transferUnitSelect +// parameter for functions: DMA_init(). +// +//***************************************************************************** +#define DMA_SIZE_SRCWORD_DSTWORD (!(DMASRCBYTE + DMADSTBYTE)) +#define DMA_SIZE_SRCBYTE_DSTWORD (DMASRCBYTE) +#define DMA_SIZE_SRCWORD_DSTBYTE (DMADSTBYTE) +#define DMA_SIZE_SRCBYTE_DSTBYTE (DMASRCBYTE + DMADSTBYTE) + +//***************************************************************************** +// +// The following are values that can be passed to the directionSelect parameter +// for functions: DMA_setSrcAddress(), and DMA_setDstAddress(). +// +//***************************************************************************** +#define DMA_DIRECTION_UNCHANGED (DMASRCINCR_0) +#define DMA_DIRECTION_DECREMENT (DMASRCINCR_2) +#define DMA_DIRECTION_INCREMENT (DMASRCINCR_3) + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the DMA_getInterruptStatus() function. +// +//***************************************************************************** +#define DMA_INT_INACTIVE (0x0) +#define DMA_INT_ACTIVE (DMAIFG) + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the DMA_NMIAbortStatus() function. +// +//***************************************************************************** +#define DMA_NOTABORTED (0x0) +#define DMA_ABORTED (DMAABORT) + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern bool DMA_initialize(DMA_initializeParam *param); + +extern void DMA_setTransferSize(uint8_t channelSelect, + uint16_t transferSize); + +extern void DMA_setSrcAddress(uint8_t channelSelect, + uint32_t srcAddress, + uint16_t directionSelect); + +extern void DMA_setDstAddress(uint8_t channelSelect, + uint32_t dstAddress, + uint16_t directionSelect); + +extern void DMA_enableTransfers(uint8_t channelSelect); + +extern void DMA_disableTransfers(uint8_t channelSelect); + +extern void DMA_startTransfer(uint8_t channelSelect); + +extern void DMA_enableInterrupt(uint8_t channelSelect); + +extern void DMA_disableInterrupt(uint8_t channelSelect); + +extern uint16_t DMA_getInterruptStatus(uint8_t channelSelect); + +extern void DMA_clearInterrupt(uint8_t channelSelect); + +extern uint16_t DMA_NMIAbortStatus(uint8_t channelSelect); + +extern void DMA_clearNMIAbort(uint8_t channelSelect); + +extern void DMA_disableTransferDuringReadModifyWrite(void); + +extern void DMA_enableTransferDuringReadModifyWrite(void); + +extern void DMA_enableRoundRobinPriority(void); + +extern void DMA_disableRoundRobinPriority(void); + +extern void DMA_enableNMIAbort(void); + +extern void DMA_disableNMIAbort(void); + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +extern bool DMA_init(uint8_t channelSelect, + uint16_t transferModeSelect, + uint16_t transferSize, + uint8_t triggerSourceSelect, + uint8_t transferUnitSelect, + uint8_t triggerTypeSelect); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_DMA_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/driverlib.h b/source/driverlib/MSP430F5xx_6xx/driverlib.h new file mode 100644 index 0000000..0ce9c94 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/driverlib.h @@ -0,0 +1,108 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +#include "inc/hw_memmap.h" + +#include "adc10_a.h" +#include "adc12_a.h" +#include "aes.h" +#include "bak_batt.h" +#include "comp_b.h" +#include "crc.h" +#include "dac12_a.h" +#ifdef DRIVERLIB_LEGACY_MODE + #include "deprecated/dma.h" +#else + #include "dma.h" +#endif +#include "eusci_a_spi.h" +#include "eusci_a_uart.h" +#include "eusci_b_i2c.h" +#include "eusci_b_spi.h" +#include "eusci_i2c.h" +#include "eusci_spi.h" +#include "eusci_uart.h" +#ifdef DRIVERLIB_LEGACY_MODE + #include "deprecated/flash.h" +#else + #include "flash.h" +#endif +#include "gpio.h" +#include "ldopwr.h" +#ifdef DRIVERLIB_LEGACY_MODE + #include "deprecated/mpy32.h" +#else + #include "mpy32.h" +#endif +#include "pmap.h" +#ifdef DRIVERLIB_LEGACY_MODE + #include "deprecated/pmm.h" +#else + #include "pmm.h" +#endif +#ifdef DRIVERLIB_LEGACY_MODE + #include "deprecated/ram.h" +#else + #include "ram.h" +#endif +#include "ref.h" +#include "rtc_a.h" +#include "rtc_b.h" +#include "rtc_c.h" +#include "sd24_b.h" +#ifdef DRIVERLIB_LEGACY_MODE + #include "deprecated/sfr.h" +#else + #include "sfr.h" +#endif +#ifdef DRIVERLIB_LEGACY_MODE + #include "deprecated/sys.h" +#else + #include "sys.h" +#endif +#include "tec.h" +#include "timer_a.h" +#include "timer_b.h" +#include "timer_d.h" +#include "tlv.h" +#ifdef DRIVERLIB_LEGACY_MODE + #include "deprecated/ucs.h" +#else + #include "ucs.h" +#endif +#include "usci_a_spi.h" +#include "usci_a_uart.h" +#include "usci_b_i2c.h" +#include "usci_b_spi.h" +#include "usci_i2c.h" +#include "usci_spi.h" +#include "usci_uart.h" +#include "wdt_a.h" diff --git a/source/driverlib/MSP430F5xx_6xx/eusci_a_spi.c b/source/driverlib/MSP430F5xx_6xx/eusci_a_spi.c new file mode 100644 index 0000000..fff3740 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/eusci_a_spi.c @@ -0,0 +1,694 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// eusci_a_spi.c - Driver for the eusci_a_spi Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup eusci_a_spi_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_EUSCI_Ax__ +#include "eusci_a_spi.h" + +#include + +//***************************************************************************** +// +//! \brief DEPRECATED - Initializes the SPI Master block. +//! +//! Upon successful initialization of the SPI master block, this function will +//! have set the bus speed for the master, but the SPI Master block still +//! remains disabled and must be enabled with EUSCI_A_SPI_enable() +//! +//! \param baseAddress is the base address of the EUSCI_A_SPI Master module. +//! \param selectClockSource selects Clock source. +//! Valid values are: +//! - \b EUSCI_A_SPI_CLOCKSOURCE_ACLK +//! - \b EUSCI_A_SPI_CLOCKSOURCE_SMCLK +//! \param clockSourceFrequency is the frequency of the selected clock source +//! \param desiredSpiClock is the desired clock rate for SPI communication +//! \param msbFirst controls the direction of the receive and transmit shift +//! register. +//! Valid values are: +//! - \b EUSCI_A_SPI_MSB_FIRST +//! - \b EUSCI_A_SPI_LSB_FIRST [Default] +//! \param clockPhase is clock phase select. +//! Valid values are: +//! - \b EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT +//! [Default] +//! - \b EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT +//! \param clockPolarity is clock polarity select +//! Valid values are: +//! - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH +//! - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default] +//! \param spiMode is SPI mode select +//! Valid values are: +//! - \b EUSCI_A_SPI_3PIN +//! - \b EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH +//! - \b EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW +//! +//! Modified bits are \b UCCKPH, \b UCCKPL, \b UC7BIT, \b UCMSB, \b UCSSELx and +//! \b UCSWRST of \b UCAxCTLW0 register. +//! +//! \return STATUS_SUCCESS +// +//***************************************************************************** +void EUSCI_A_SPI_masterInit(uint16_t baseAddress, + uint8_t selectClockSource, + uint32_t clockSourceFrequency, + uint32_t desiredSpiClock, + uint16_t msbFirst, + uint16_t clockPhase, + uint16_t clockPolarity, + uint16_t spiMode + ) +{ + EUSCI_A_SPI_initMasterParam param = { 0 }; + + param.selectClockSource = selectClockSource; + param.clockSourceFrequency = clockSourceFrequency; + param.desiredSpiClock = desiredSpiClock; + param.msbFirst = msbFirst; + param.clockPhase = clockPhase; + param.clockPolarity = clockPolarity; + param.spiMode = spiMode; + + EUSCI_A_SPI_initMaster(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Initializes the SPI Master block. +//! +//! Upon successful initialization of the SPI master block, this function will +//! have set the bus speed for the master, but the SPI Master block still +//! remains disabled and must be enabled with EUSCI_A_SPI_enable() +//! +//! \param baseAddress is the base address of the EUSCI_A_SPI Master module. +//! \param param is the pointer to struct for master initialization. +//! +//! Modified bits are \b UCCKPH, \b UCCKPL, \b UC7BIT, \b UCMSB, \b UCSSELx and +//! \b UCSWRST of \b UCAxCTLW0 register. +//! +//! \return STATUS_SUCCESS +// +//***************************************************************************** +void EUSCI_A_SPI_initMaster(uint16_t baseAddress, + EUSCI_A_SPI_initMasterParam *param) +{ + assert(param != 0); + + assert( + (EUSCI_A_SPI_CLOCKSOURCE_ACLK == param->selectClockSource) || + (EUSCI_A_SPI_CLOCKSOURCE_SMCLK == param->selectClockSource) + ); + + assert((EUSCI_A_SPI_MSB_FIRST == param->msbFirst) || + (EUSCI_A_SPI_LSB_FIRST == param->msbFirst) + ); + + assert((EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT == param->clockPhase) || + (EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT == param->clockPhase) + ); + + assert((EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == param->clockPolarity) || + (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW == param->clockPolarity) + ); + + assert( + (EUSCI_A_SPI_3PIN == param->spiMode) || + (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH == param->spiMode) || + (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW == param->spiMode) + ); + + //Disable the USCI Module + HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCSWRST; + + //Reset OFS_UCAxCTLW0 values + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCCKPH + UCCKPL + UC7BIT + UCMSB + + UCMST + UCMODE_3 + UCSYNC); + + //Reset OFS_UCAxCTLW0 values + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCSSEL_3); + + //Select Clock + HWREG16(baseAddress + OFS_UCAxCTLW0) |= param->selectClockSource; + + HWREG16(baseAddress + OFS_UCAxBRW) = + (uint16_t)(param->clockSourceFrequency / param->desiredSpiClock); + + /* + * Configure as SPI master mode. + * Clock phase select, polarity, msb + * UCMST = Master mode + * UCSYNC = Synchronous mode + * UCMODE_0 = 3-pin SPI + */ + HWREG16(baseAddress + OFS_UCAxCTLW0) |= ( + param->msbFirst + + param->clockPhase + + param->clockPolarity + + UCMST + + UCSYNC + + param->spiMode + ); + //No modulation + HWREG16(baseAddress + OFS_UCAxMCTLW) = 0; +} + +//***************************************************************************** +// +//! \brief Selects 4Pin Functionality +//! +//! This function should be invoked only in 4-wire mode. Invoking this function +//! has no effect in 3-wire mode. +//! +//! \param baseAddress is the base address of the EUSCI_A_SPI module. +//! \param select4PinFunctionality selects 4 pin functionality +//! Valid values are: +//! - \b EUSCI_A_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS +//! - \b EUSCI_A_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE +//! +//! Modified bits are \b UCSTEM of \b UCAxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_A_SPI_select4PinFunctionality(uint16_t baseAddress, + uint8_t select4PinFunctionality + ) +{ + assert( (EUSCI_A_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS == select4PinFunctionality) || + (EUSCI_A_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE == select4PinFunctionality) + ); + + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCSTEM; + HWREG16(baseAddress + OFS_UCAxCTLW0) |= select4PinFunctionality; +} + +//***************************************************************************** +// +//! \brief DEPRECATED - Initializes the SPI Master clock. At the end of this +//! function call, SPI module is left enabled. +//! +//! \param baseAddress is the base address of the EUSCI_A_SPI module. +//! \param clockSourceFrequency is the frequency of the selected clock source +//! \param desiredSpiClock is the desired clock rate for SPI communication +//! +//! Modified bits are \b UCSWRST of \b UCAxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_A_SPI_masterChangeClock(uint16_t baseAddress, + uint32_t clockSourceFrequency, + uint32_t desiredSpiClock + ) +{ + EUSCI_A_SPI_changeMasterClockParam param = { 0 }; + + param.clockSourceFrequency = clockSourceFrequency; + param.desiredSpiClock = desiredSpiClock; + EUSCI_A_SPI_changeMasterClock(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Initializes the SPI Master clock. At the end of this function call, +//! SPI module is left enabled. +//! +//! \param baseAddress is the base address of the EUSCI_A_SPI module. +//! \param param is the pointer to struct for master clock setting. +//! +//! Modified bits are \b UCSWRST of \b UCAxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_A_SPI_changeMasterClock(uint16_t baseAddress, + EUSCI_A_SPI_changeMasterClockParam *param) +{ + assert(param != 0); + + //Disable the USCI Module + HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCSWRST; + + HWREG16(baseAddress + OFS_UCAxBRW) = + (uint16_t)(param->clockSourceFrequency / param->desiredSpiClock); + + //Reset the UCSWRST bit to enable the USCI Module + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCSWRST); +} +//***************************************************************************** +// +//! \brief DEPRECATED - Initializes the SPI Slave block. +//! +//! Upon successful initialization of the SPI slave block, this function will +//! have initialized the slave block, but the SPI Slave block still remains +//! disabled and must be enabled with EUSCI_A_SPI_enable() +//! +//! \param baseAddress is the base address of the EUSCI_A_SPI Slave module. +//! \param msbFirst controls the direction of the receive and transmit shift +//! register. +//! Valid values are: +//! - \b EUSCI_A_SPI_MSB_FIRST +//! - \b EUSCI_A_SPI_LSB_FIRST [Default] +//! \param clockPhase is clock phase select. +//! Valid values are: +//! - \b EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT +//! [Default] +//! - \b EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT +//! \param clockPolarity is clock polarity select +//! Valid values are: +//! - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH +//! - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default] +//! \param spiMode is SPI mode select +//! Valid values are: +//! - \b EUSCI_A_SPI_3PIN +//! - \b EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH +//! - \b EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW +//! +//! Modified bits are \b UCMSB, \b UCMST, \b UC7BIT, \b UCCKPL, \b UCCKPH, \b +//! UCMODE and \b UCSWRST of \b UCAxCTLW0 register. +//! +//! \return STATUS_SUCCESS +// +//***************************************************************************** +void EUSCI_A_SPI_slaveInit(uint16_t baseAddress, + uint16_t msbFirst, + uint16_t clockPhase, + uint16_t clockPolarity, + uint16_t spiMode + ) +{ + EUSCI_A_SPI_initSlaveParam param = { 0 }; + + param.msbFirst = msbFirst; + param.clockPhase = clockPhase; + param.clockPolarity = clockPolarity; + param.spiMode = spiMode; + + EUSCI_A_SPI_initSlave(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Initializes the SPI Slave block. +//! +//! Upon successful initialization of the SPI slave block, this function will +//! have initialized the slave block, but the SPI Slave block still remains +//! disabled and must be enabled with EUSCI_A_SPI_enable() +//! +//! \param baseAddress is the base address of the EUSCI_A_SPI Slave module. +//! \param param is the pointer to struct for slave initialization. +//! +//! Modified bits are \b UCMSB, \b UCMST, \b UC7BIT, \b UCCKPL, \b UCCKPH, \b +//! UCMODE and \b UCSWRST of \b UCAxCTLW0 register. +//! +//! \return STATUS_SUCCESS +// +//***************************************************************************** +void EUSCI_A_SPI_initSlave(uint16_t baseAddress, EUSCI_A_SPI_initSlaveParam *param) +{ + assert(param != 0); + + assert( + (EUSCI_A_SPI_MSB_FIRST == param->msbFirst) || + (EUSCI_A_SPI_LSB_FIRST == param->msbFirst) + ); + + assert( + (EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT == param->clockPhase) || + (EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT == param->clockPhase) + ); + + assert( + (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == param->clockPolarity) || + (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW == param->clockPolarity) + ); + + assert( + (EUSCI_A_SPI_3PIN == param->spiMode) || + (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH == param->spiMode) || + (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW == param->spiMode) + ); + + //Disable USCI Module + HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCSWRST; + + //Reset OFS_UCAxCTLW0 register + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCMSB + + UC7BIT + + UCMST + + UCCKPL + + UCCKPH + + UCMODE_3 + ); + + //Clock polarity, phase select, msbFirst, SYNC, Mode0 + HWREG16(baseAddress + OFS_UCAxCTLW0) |= (param->clockPhase + + param->clockPolarity + + param->msbFirst + + UCSYNC + + param->spiMode + ); +} + +//***************************************************************************** +// +//! \brief Changes the SPI clock phase and polarity. At the end of this +//! function call, SPI module is left enabled. +//! +//! \param baseAddress is the base address of the EUSCI_A_SPI module. +//! \param clockPhase is clock phase select. +//! Valid values are: +//! - \b EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT +//! [Default] +//! - \b EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT +//! \param clockPolarity is clock polarity select +//! Valid values are: +//! - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH +//! - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default] +//! +//! Modified bits are \b UCCKPL, \b UCCKPH and \b UCSWRST of \b UCAxCTLW0 +//! register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_A_SPI_changeClockPhasePolarity(uint16_t baseAddress, + uint16_t clockPhase, + uint16_t clockPolarity + ) +{ + + assert( (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == clockPolarity) || + (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW == clockPolarity) + ); + + assert( (EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT == clockPhase) || + (EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT == clockPhase) + ); + + //Disable the USCI Module + HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCSWRST; + + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCCKPH + UCCKPL); + + HWREG16(baseAddress + OFS_UCAxCTLW0) |= ( + clockPhase + + clockPolarity + ); + + //Reset the UCSWRST bit to enable the USCI Module + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCSWRST); +} + +//***************************************************************************** +// +//! \brief Transmits a byte from the SPI Module. +//! +//! This function will place the supplied data into SPI transmit data register +//! to start transmission. +//! +//! \param baseAddress is the base address of the EUSCI_A_SPI module. +//! \param transmitData data to be transmitted from the SPI module +//! +//! \return None +// +//***************************************************************************** +void EUSCI_A_SPI_transmitData( uint16_t baseAddress, + uint8_t transmitData + ) +{ + HWREG16(baseAddress + OFS_UCAxTXBUF) = transmitData; +} + +//***************************************************************************** +// +//! \brief Receives a byte that has been sent to the SPI Module. +//! +//! This function reads a byte of data from the SPI receive data Register. +//! +//! \param baseAddress is the base address of the EUSCI_A_SPI module. +//! +//! \return Returns the byte received from by the SPI module, cast as an +//! uint8_t. +// +//***************************************************************************** +uint8_t EUSCI_A_SPI_receiveData(uint16_t baseAddress) +{ + return HWREG16(baseAddress + OFS_UCAxRXBUF); +} + +//***************************************************************************** +// +//! \brief Enables individual SPI interrupt sources. +//! +//! Enables the indicated SPI interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. Does not clear interrupt flags. +//! +//! \param baseAddress is the base address of the EUSCI_A_SPI module. +//! \param mask is the bit mask of the interrupt sources to be enabled. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT +//! - \b EUSCI_A_SPI_RECEIVE_INTERRUPT +//! +//! Modified bits of \b UCAxIFG register and bits of \b UCAxIE register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_A_SPI_enableInterrupt(uint16_t baseAddress, + uint8_t mask + ) +{ + assert(!(mask & ~(EUSCI_A_SPI_RECEIVE_INTERRUPT + | EUSCI_A_SPI_TRANSMIT_INTERRUPT))); + + HWREG16(baseAddress + OFS_UCAxIE) |= mask; +} + +//***************************************************************************** +// +//! \brief Disables individual SPI interrupt sources. +//! +//! Disables the indicated SPI interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! \param baseAddress is the base address of the EUSCI_A_SPI module. +//! \param mask is the bit mask of the interrupt sources to be disabled. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT +//! - \b EUSCI_A_SPI_RECEIVE_INTERRUPT +//! +//! Modified bits of \b UCAxIE register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_A_SPI_disableInterrupt(uint16_t baseAddress, + uint8_t mask + ) +{ + assert(!(mask & ~(EUSCI_A_SPI_RECEIVE_INTERRUPT + | EUSCI_A_SPI_TRANSMIT_INTERRUPT))); + + HWREG16(baseAddress + OFS_UCAxIE) &= ~mask; +} + +//***************************************************************************** +// +//! \brief Gets the current SPI interrupt status. +//! +//! This returns the interrupt status for the SPI module based on which flag is +//! passed. +//! +//! \param baseAddress is the base address of the EUSCI_A_SPI module. +//! \param mask is the masked interrupt flag status to be returned. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT +//! - \b EUSCI_A_SPI_RECEIVE_INTERRUPT +//! +//! \return Logical OR of any of the following: +//! - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT +//! - \b EUSCI_A_SPI_RECEIVE_INTERRUPT +//! \n indicating the status of the masked interrupts +// +//***************************************************************************** +uint8_t EUSCI_A_SPI_getInterruptStatus(uint16_t baseAddress, + uint8_t mask + ) +{ + assert(!(mask & ~(EUSCI_A_SPI_RECEIVE_INTERRUPT + | EUSCI_A_SPI_TRANSMIT_INTERRUPT))); + + return HWREG16(baseAddress + OFS_UCAxIFG) & mask; +} + +//***************************************************************************** +// +//! \brief Clears the selected SPI interrupt status flag. +//! +//! \param baseAddress is the base address of the EUSCI_A_SPI module. +//! \param mask is the masked interrupt flag to be cleared. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT +//! - \b EUSCI_A_SPI_RECEIVE_INTERRUPT +//! +//! Modified bits of \b UCAxIFG register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_A_SPI_clearInterruptFlag(uint16_t baseAddress, + uint8_t mask + ) +{ + assert(!(mask & ~(EUSCI_A_SPI_RECEIVE_INTERRUPT + | EUSCI_A_SPI_TRANSMIT_INTERRUPT))); + + HWREG16(baseAddress + OFS_UCAxIFG) &= ~mask; +} + +//***************************************************************************** +// +//! \brief Enables the SPI block. +//! +//! This will enable operation of the SPI block. +//! +//! \param baseAddress is the base address of the EUSCI_A_SPI module. +//! +//! Modified bits are \b UCSWRST of \b UCAxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_A_SPI_enable(uint16_t baseAddress) +{ + //Reset the UCSWRST bit to enable the USCI Module + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCSWRST); +} + +//***************************************************************************** +// +//! \brief Disables the SPI block. +//! +//! This will disable operation of the SPI block. +//! +//! \param baseAddress is the base address of the EUSCI_A_SPI module. +//! +//! Modified bits are \b UCSWRST of \b UCAxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_A_SPI_disable(uint16_t baseAddress) +{ + //Set the UCSWRST bit to disable the USCI Module + HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCSWRST; +} + +//***************************************************************************** +// +//! \brief Returns the address of the RX Buffer of the SPI for the DMA module. +//! +//! Returns the address of the SPI RX Buffer. This can be used in conjunction +//! with the DMA to store the received data directly to memory. +//! +//! \param baseAddress is the base address of the EUSCI_A_SPI module. +//! +//! \return the address of the RX Buffer +// +//***************************************************************************** +uint32_t EUSCI_A_SPI_getReceiveBufferAddress(uint16_t baseAddress) +{ + return baseAddress + OFS_UCAxRXBUF; +} + +//***************************************************************************** +// +//! \brief Returns the address of the TX Buffer of the SPI for the DMA module. +//! +//! Returns the address of the SPI TX Buffer. This can be used in conjunction +//! with the DMA to obtain transmitted data directly from memory. +//! +//! \param baseAddress is the base address of the EUSCI_A_SPI module. +//! +//! \return the address of the TX Buffer +// +//***************************************************************************** +uint32_t EUSCI_A_SPI_getTransmitBufferAddress(uint16_t baseAddress) +{ + return baseAddress + OFS_UCAxTXBUF; +} + +//***************************************************************************** +// +//! \brief Indicates whether or not the SPI bus is busy. +//! +//! This function returns an indication of whether or not the SPI bus is +//! busy.This function checks the status of the bus via UCBBUSY bit +//! +//! \param baseAddress is the base address of the EUSCI_A_SPI module. +//! +//! \return One of the following: +//! - \b EUSCI_A_SPI_BUSY +//! - \b EUSCI_A_SPI_NOT_BUSY +//! \n indicating if the EUSCI_A_SPI is busy +// +//***************************************************************************** +uint16_t EUSCI_A_SPI_isBusy(uint16_t baseAddress) +{ + //Return the bus busy status. + return HWREG16(baseAddress + OFS_UCAxSTATW) & UCBUSY; +} + + +#endif +//***************************************************************************** +// +//! Close the doxygen group for eusci_a_spi_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/eusci_a_spi.h b/source/driverlib/MSP430F5xx_6xx/eusci_a_spi.h new file mode 100644 index 0000000..af13bbf --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/eusci_a_spi.h @@ -0,0 +1,268 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// eusci_a_spi.h - Driver for the EUSCI_A_SPI Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_EUSCI_A_SPI_H__ +#define __MSP430WARE_EUSCI_A_SPI_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_EUSCI_Ax__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//****************************************************************************** +// +// The following is a struct that is passed to EUSCI_A_SPI_initMaster() +// +//****************************************************************************** +typedef struct EUSCI_A_SPI_initMasterParam { + uint8_t selectClockSource; + uint32_t clockSourceFrequency; + uint32_t desiredSpiClock; + uint16_t msbFirst; + uint16_t clockPhase; + uint16_t clockPolarity; + uint16_t spiMode; +} EUSCI_A_SPI_initMasterParam; + +//****************************************************************************** +// +// The following is a struct that is passed to EUSCI_A_SPI_initSlave() +// +//****************************************************************************** +typedef struct EUSCI_A_SPI_initSlaveParam { + uint16_t msbFirst; + uint16_t clockPhase; + uint16_t clockPolarity; + uint16_t spiMode; +} EUSCI_A_SPI_initSlaveParam; + +//****************************************************************************** +// +// The following is a struct that is passed to EUSCI_A_SPI_changeMasterParam() +// +//****************************************************************************** +typedef struct EUSCI_A_SPI_changeMasterClockParam { + uint32_t clockSourceFrequency; + uint32_t desiredSpiClock; +} EUSCI_A_SPI_changeMasterClockParam; + +//***************************************************************************** +// +// The following are values that can be passed to the clockPhase parameter for +// functions: EUSCI_A_SPI_masterInit(), EUSCI_A_SPI_slaveInit(), and +// EUSCI_A_SPI_changeClockPhasePolarity(). +// +//***************************************************************************** +#define EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT 0x00 +#define EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT UCCKPH + +//***************************************************************************** +// +// The following are values that can be passed to the msbFirst parameter for +// functions: EUSCI_A_SPI_masterInit(), and EUSCI_A_SPI_slaveInit(). +// +//***************************************************************************** +#define EUSCI_A_SPI_MSB_FIRST UCMSB +#define EUSCI_A_SPI_LSB_FIRST 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the clockPolarity parameter +// for functions: EUSCI_A_SPI_masterInit(), EUSCI_A_SPI_slaveInit(), and +// EUSCI_A_SPI_changeClockPhasePolarity(). +// +//***************************************************************************** +#define EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH UCCKPL +#define EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the selectClockSource +// parameter for functions: EUSCI_A_SPI_masterInit(). +// +//***************************************************************************** +#define EUSCI_A_SPI_CLOCKSOURCE_ACLK UCSSEL__ACLK +#define EUSCI_A_SPI_CLOCKSOURCE_SMCLK UCSSEL__SMCLK + +//***************************************************************************** +// +// The following are values that can be passed to the spiMode parameter for +// functions: EUSCI_A_SPI_masterInit(), and EUSCI_A_SPI_slaveInit(). +// +//***************************************************************************** +#define EUSCI_A_SPI_3PIN UCMODE_0 +#define EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH UCMODE_1 +#define EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW UCMODE_2 + +//***************************************************************************** +// +// The following are values that can be passed to the select4PinFunctionality +// parameter for functions: EUSCI_A_SPI_select4PinFunctionality(). +// +//***************************************************************************** +#define EUSCI_A_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS 0x00 +#define EUSCI_A_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE UCSTEM + +//***************************************************************************** +// +// The following are values that can be passed to the mask parameter for +// functions: EUSCI_A_SPI_enableInterrupt(), EUSCI_A_SPI_disableInterrupt(), +// EUSCI_A_SPI_getInterruptStatus(), and EUSCI_A_SPI_clearInterruptFlag() as +// well as returned by the EUSCI_A_SPI_getInterruptStatus() function. +// +//***************************************************************************** +#define EUSCI_A_SPI_TRANSMIT_INTERRUPT UCTXIE +#define EUSCI_A_SPI_RECEIVE_INTERRUPT UCRXIE + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the EUSCI_A_SPI_isBusy() function. +// +//***************************************************************************** +#define EUSCI_A_SPI_BUSY UCBUSY +#define EUSCI_A_SPI_NOT_BUSY 0x00 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void EUSCI_A_SPI_initMaster(uint16_t baseAddress, + EUSCI_A_SPI_initMasterParam *param); + +extern void EUSCI_A_SPI_select4PinFunctionality(uint16_t baseAddress, + uint8_t select4PinFunctionality); + +extern void EUSCI_A_SPI_changeMasterClock(uint16_t baseAddress, + EUSCI_A_SPI_changeMasterClockParam *param); + +extern void EUSCI_A_SPI_initSlave(uint16_t baseAddress, + EUSCI_A_SPI_initSlaveParam *param); + +extern void EUSCI_A_SPI_changeClockPhasePolarity(uint16_t baseAddress, + uint16_t clockPhase, + uint16_t clockPolarity); + +extern void EUSCI_A_SPI_transmitData(uint16_t baseAddress, + uint8_t transmitData); + +extern uint8_t EUSCI_A_SPI_receiveData(uint16_t baseAddress); + +extern void EUSCI_A_SPI_enableInterrupt(uint16_t baseAddress, + uint8_t mask); + +extern void EUSCI_A_SPI_disableInterrupt(uint16_t baseAddress, + uint8_t mask); + +extern uint8_t EUSCI_A_SPI_getInterruptStatus(uint16_t baseAddress, + uint8_t mask); + +extern void EUSCI_A_SPI_clearInterruptFlag(uint16_t baseAddress, + uint8_t mask); + +extern void EUSCI_A_SPI_enable(uint16_t baseAddress); + +extern void EUSCI_A_SPI_disable(uint16_t baseAddress); + +extern uint32_t EUSCI_A_SPI_getReceiveBufferAddress(uint16_t baseAddress); + +extern uint32_t EUSCI_A_SPI_getTransmitBufferAddress(uint16_t baseAddress); + +extern uint16_t EUSCI_A_SPI_isBusy(uint16_t baseAddress); + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +#define EUSCI_A_SPI_getTransmitBufferAddressForDMA \ + EUSCI_A_SPI_getTransmitBufferAddress + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +#define EUSCI_A_SPI_getReceiveBufferAddressForDMA \ + EUSCI_A_SPI_getReceiveBufferAddress + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +extern void EUSCI_A_SPI_masterInit(uint16_t baseAddress, + uint8_t selectClockSource, + uint32_t clockSourceFrequency, + uint32_t desiredSpiClock, + uint16_t msbFirst, + uint16_t clockPhase, + uint16_t clockPolarity, + uint16_t spiMode); + +extern void EUSCI_A_SPI_masterChangeClock(uint16_t baseAddress, + uint32_t clockSourceFrequency, + uint32_t desiredSpiClock); + +extern void EUSCI_A_SPI_slaveInit(uint16_t baseAddress, + uint16_t msbFirst, + uint16_t clockPhase, + uint16_t clockPolarity, + uint16_t spiMode); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_EUSCI_A_SPI_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/eusci_a_uart.c b/source/driverlib/MSP430F5xx_6xx/eusci_a_uart.c new file mode 100644 index 0000000..891adf0 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/eusci_a_uart.c @@ -0,0 +1,736 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// eusci_a_uart.c - Driver for the eusci_a_uart Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup eusci_a_uart_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_EUSCI_Ax__ +#include "eusci_a_uart.h" + +#include + +//***************************************************************************** +// +//! \brief DEPRECATED - Advanced initialization routine for the UART block. The +//! values to be written into the clockPrescalar, firstModReg, secondModReg and +//! overSampling parameters should be pre-computed and passed into the +//! initialization function. +//! +//! Upon successful initialization of the UART block, this function will have +//! initialized the module, but the UART block still remains disabled and must +//! be enabled with EUSCI_A_UART_enable(). To calculate values for +//! clockPrescalar, firstModReg, secondModReg and overSampling please use the +//! link below. +//! +//! http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSP430BaudRateConverter/index.html +//! +//! \param baseAddress is the base address of the EUSCI_A_UART module. +//! \param selectClockSource selects Clock source. +//! Valid values are: +//! - \b EUSCI_A_UART_CLOCKSOURCE_SMCLK +//! - \b EUSCI_A_UART_CLOCKSOURCE_ACLK +//! \param clockPrescalar is the value to be written into UCBRx bits +//! \param firstModReg is First modulation stage register setting. This value +//! is a pre-calculated value which can be obtained from the Device +//! Users Guide. This value is written into UCBRFx bits of UCAxMCTLW. +//! \param secondModReg is Second modulation stage register setting. This value +//! is a pre-calculated value which can be obtained from the Device +//! Users Guide. This value is written into UCBRSx bits of UCAxMCTLW. +//! \param parity is the desired parity. +//! Valid values are: +//! - \b EUSCI_A_UART_NO_PARITY [Default] +//! - \b EUSCI_A_UART_ODD_PARITY +//! - \b EUSCI_A_UART_EVEN_PARITY +//! \param msborLsbFirst controls direction of receive and transmit shift +//! register. +//! Valid values are: +//! - \b EUSCI_A_UART_MSB_FIRST +//! - \b EUSCI_A_UART_LSB_FIRST [Default] +//! \param numberofStopBits indicates one/two STOP bits +//! Valid values are: +//! - \b EUSCI_A_UART_ONE_STOP_BIT [Default] +//! - \b EUSCI_A_UART_TWO_STOP_BITS +//! \param uartMode selects the mode of operation +//! Valid values are: +//! - \b EUSCI_A_UART_MODE [Default] +//! - \b EUSCI_A_UART_IDLE_LINE_MULTI_PROCESSOR_MODE +//! - \b EUSCI_A_UART_ADDRESS_BIT_MULTI_PROCESSOR_MODE +//! - \b EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE +//! \param overSampling indicates low frequency or oversampling baud generation +//! Valid values are: +//! - \b EUSCI_A_UART_OVERSAMPLING_BAUDRATE_GENERATION +//! - \b EUSCI_A_UART_LOW_FREQUENCY_BAUDRATE_GENERATION +//! +//! Modified bits are \b UCPEN, \b UCPAR, \b UCMSB, \b UC7BIT, \b UCSPB, \b +//! UCMODEx and \b UCSYNC of \b UCAxCTL0 register; bits \b UCSSELx and \b +//! UCSWRST of \b UCAxCTL1 register. +//! +//! \return STATUS_SUCCESS or STATUS_FAIL of the initialization process +// +//***************************************************************************** +bool EUSCI_A_UART_initAdvance( uint16_t baseAddress, + uint8_t selectClockSource, + uint16_t clockPrescalar, + uint8_t firstModReg, + uint8_t secondModReg, + uint8_t parity, + uint16_t msborLsbFirst, + uint16_t numberofStopBits, + uint16_t uartMode, + uint8_t overSampling + ) +{ + EUSCI_A_UART_initParam param = { 0 }; + + param.selectClockSource = selectClockSource; + param.clockPrescalar = clockPrescalar; + param.firstModReg = firstModReg; + param.secondModReg = secondModReg; + param.parity = parity; + param.msborLsbFirst = msborLsbFirst; + param.numberofStopBits = numberofStopBits; + param.uartMode = uartMode; + param.overSampling = overSampling; + + return EUSCI_A_UART_init(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Advanced initialization routine for the UART block. The values to be +//! written into the clockPrescalar, firstModReg, secondModReg and overSampling +//! parameters should be pre-computed and passed into the initialization +//! function. +//! +//! Upon successful initialization of the UART block, this function will have +//! initialized the module, but the UART block still remains disabled and must +//! be enabled with EUSCI_A_UART_enable(). To calculate values for +//! clockPrescalar, firstModReg, secondModReg and overSampling please use the +//! link below. +//! +//! http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSP430BaudRateConverter/index.html +//! +//! \param baseAddress is the base address of the EUSCI_A_UART module. +//! \param param is the pointer to struct for initialization. +//! +//! Modified bits are \b UCPEN, \b UCPAR, \b UCMSB, \b UC7BIT, \b UCSPB, \b +//! UCMODEx and \b UCSYNC of \b UCAxCTL0 register; bits \b UCSSELx and \b +//! UCSWRST of \b UCAxCTL1 register. +//! +//! \return STATUS_SUCCESS or STATUS_FAIL of the initialization process +// +//***************************************************************************** +bool EUSCI_A_UART_init(uint16_t baseAddress, EUSCI_A_UART_initParam *param) +{ + assert(param != 0); + + assert( + (EUSCI_A_UART_MODE == param->uartMode) || + (EUSCI_A_UART_IDLE_LINE_MULTI_PROCESSOR_MODE == param->uartMode) || + (EUSCI_A_UART_ADDRESS_BIT_MULTI_PROCESSOR_MODE == param->uartMode) || + (EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE == param->uartMode) + ); + + assert( + (EUSCI_A_UART_CLOCKSOURCE_ACLK == param->selectClockSource) || + (EUSCI_A_UART_CLOCKSOURCE_SMCLK == param->selectClockSource) + ); + + assert( + (EUSCI_A_UART_MSB_FIRST == param->msborLsbFirst) || + (EUSCI_A_UART_LSB_FIRST == param->msborLsbFirst) + ); + + assert( + (EUSCI_A_UART_ONE_STOP_BIT == param->numberofStopBits) || + (EUSCI_A_UART_TWO_STOP_BITS == param->numberofStopBits) + ); + + assert( + (EUSCI_A_UART_NO_PARITY == param->parity) || + (EUSCI_A_UART_ODD_PARITY == param->parity) || + (EUSCI_A_UART_EVEN_PARITY == param->parity) + ); + + bool retVal = STATUS_SUCCESS; + + //Disable the USCI Module + HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCSWRST; + + //Clock source select + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCSSEL_3; + HWREG16(baseAddress + OFS_UCAxCTLW0) |= param->selectClockSource; + + //MSB, LSB select + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCMSB; + HWREG16(baseAddress + OFS_UCAxCTLW0) |= param->msborLsbFirst; + + //UCSPB = 0(1 stop bit) OR 1(2 stop bits) + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCSPB; + HWREG16(baseAddress + OFS_UCAxCTLW0) |= param->numberofStopBits; + + //Parity + switch (param->parity) { + case EUSCI_A_UART_NO_PARITY: + //No Parity + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCPEN; + break; + case EUSCI_A_UART_ODD_PARITY: + //Odd Parity + HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCPEN; + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCPAR; + break; + case EUSCI_A_UART_EVEN_PARITY: + //Even Parity + HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCPEN; + HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCPAR; + break; + } + + //BaudRate Control Register + HWREG16(baseAddress + OFS_UCAxBRW ) = param->clockPrescalar; + //Modulation Control Register + HWREG16(baseAddress + OFS_UCAxMCTLW) = ((param->secondModReg << 8) + + (param->firstModReg << 4) + param->overSampling ); + + //Asynchronous mode & 8 bit character select & clear mode + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCSYNC + + UC7BIT + + UCMODE_3 + ); + + //Configure UART mode. + HWREG16(baseAddress + OFS_UCAxCTLW0) |= param->uartMode; + + //Reset UCRXIE, UCBRKIE, UCDORM, UCTXADDR, UCTXBRK + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCRXEIE + UCBRKIE + UCDORM + + UCTXADDR + UCTXBRK + ); + + return retVal; +} +//***************************************************************************** +// +//! \brief Transmits a byte from the UART Module. +//! +//! This function will place the supplied data into UART transmit data register +//! to start transmission +//! +//! \param baseAddress is the base address of the EUSCI_A_UART module. +//! \param transmitData data to be transmitted from the UART module +//! +//! Modified bits of \b UCAxTXBUF register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_A_UART_transmitData( uint16_t baseAddress, + uint8_t transmitData + ) +{ + //If interrupts are not used, poll for flags + if (!(HWREG16(baseAddress + OFS_UCAxIE) & UCTXIE)) + //Poll for transmit interrupt flag + while (!(HWREG16(baseAddress + OFS_UCAxIFG) & UCTXIFG)) ; + + HWREG16(baseAddress + OFS_UCAxTXBUF) = transmitData; +} + +//***************************************************************************** +// +//! \brief Receives a byte that has been sent to the UART Module. +//! +//! This function reads a byte of data from the UART receive data Register. +//! +//! \param baseAddress is the base address of the EUSCI_A_UART module. +//! +//! Modified bits of \b UCAxRXBUF register. +//! +//! \return Returns the byte received from by the UART module, cast as an +//! uint8_t. +// +//***************************************************************************** +uint8_t EUSCI_A_UART_receiveData(uint16_t baseAddress) +{ + //If interrupts are not used, poll for flags + if (!(HWREG16(baseAddress + OFS_UCAxIE) & UCRXIE)) + //Poll for receive interrupt flag + while (!(HWREG16(baseAddress + OFS_UCAxIFG) & UCRXIFG)) ; + + return HWREG16(baseAddress + OFS_UCAxRXBUF); +} + +//***************************************************************************** +// +//! \brief Enables individual UART interrupt sources. +//! +//! Enables the indicated UART interrupt sources. The interrupt flag is first +//! and then the corresponding interrupt is enabled. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. Does not clear interrupt flags. +//! +//! \param baseAddress is the base address of the EUSCI_A_UART module. +//! \param mask is the bit mask of the interrupt sources to be enabled. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_A_UART_RECEIVE_INTERRUPT - Receive interrupt +//! - \b EUSCI_A_UART_TRANSMIT_INTERRUPT - Transmit interrupt +//! - \b EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT - Receive +//! erroneous-character interrupt enable +//! - \b EUSCI_A_UART_BREAKCHAR_INTERRUPT - Receive break character +//! interrupt enable +//! - \b EUSCI_A_UART_STARTBIT_INTERRUPT - Start bit received interrupt +//! enable +//! - \b EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT - Transmit complete +//! interrupt enable +//! +//! Modified bits of \b UCAxCTL1 register and bits of \b UCAxIE register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_A_UART_enableInterrupt(uint16_t baseAddress, + uint8_t mask + ) +{ + assert(!(mask & ~(EUSCI_A_UART_RECEIVE_INTERRUPT + | EUSCI_A_UART_TRANSMIT_INTERRUPT + | EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT + | EUSCI_A_UART_BREAKCHAR_INTERRUPT + | EUSCI_A_UART_STARTBIT_INTERRUPT + | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT))); + + uint8_t locMask; + + locMask = (mask & (EUSCI_A_UART_RECEIVE_INTERRUPT + | EUSCI_A_UART_TRANSMIT_INTERRUPT + | EUSCI_A_UART_STARTBIT_INTERRUPT + | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT)); + + HWREG16(baseAddress + OFS_UCAxIE) |= locMask; + + locMask = (mask & (EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT + | EUSCI_A_UART_BREAKCHAR_INTERRUPT)); + HWREG16(baseAddress + OFS_UCAxCTLW0) |= locMask; + +} + +//***************************************************************************** +// +//! \brief Disables individual UART interrupt sources. +//! +//! Disables the indicated UART interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! \param baseAddress is the base address of the EUSCI_A_UART module. +//! \param mask is the bit mask of the interrupt sources to be disabled. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_A_UART_RECEIVE_INTERRUPT - Receive interrupt +//! - \b EUSCI_A_UART_TRANSMIT_INTERRUPT - Transmit interrupt +//! - \b EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT - Receive +//! erroneous-character interrupt enable +//! - \b EUSCI_A_UART_BREAKCHAR_INTERRUPT - Receive break character +//! interrupt enable +//! - \b EUSCI_A_UART_STARTBIT_INTERRUPT - Start bit received interrupt +//! enable +//! - \b EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT - Transmit complete +//! interrupt enable +//! +//! Modified bits of \b UCAxCTL1 register and bits of \b UCAxIE register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_A_UART_disableInterrupt(uint16_t baseAddress, + uint8_t mask + ) +{ + assert(!(mask & ~(EUSCI_A_UART_RECEIVE_INTERRUPT + | EUSCI_A_UART_TRANSMIT_INTERRUPT + | EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT + | EUSCI_A_UART_BREAKCHAR_INTERRUPT + | EUSCI_A_UART_STARTBIT_INTERRUPT + | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT))); + + uint8_t locMask; + + locMask = (mask & (EUSCI_A_UART_RECEIVE_INTERRUPT + | EUSCI_A_UART_TRANSMIT_INTERRUPT + | EUSCI_A_UART_STARTBIT_INTERRUPT + | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT)); + HWREG16(baseAddress + OFS_UCAxIE) &= ~locMask; + + + locMask = (mask & (EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT + | EUSCI_A_UART_BREAKCHAR_INTERRUPT)); + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~locMask; +} + +//***************************************************************************** +// +//! \brief Gets the current UART interrupt status. +//! +//! This returns the interrupt status for the UART module based on which flag +//! is passed. +//! +//! \param baseAddress is the base address of the EUSCI_A_UART module. +//! \param mask is the masked interrupt flag status to be returned. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG +//! - \b EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG +//! - \b EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG +//! - \b EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG +//! +//! Modified bits of \b UCAxIFG register. +//! +//! \return Logical OR of any of the following: +//! - \b EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG +//! - \b EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG +//! - \b EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG +//! - \b EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG +//! \n indicating the status of the masked flags +// +//***************************************************************************** +uint8_t EUSCI_A_UART_getInterruptStatus(uint16_t baseAddress, + uint8_t mask) +{ + assert(!(mask & ~(EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG + | EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG + | EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG + | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG))); + + return HWREG16(baseAddress + OFS_UCAxIFG) & mask; +} + +//***************************************************************************** +// +//! \brief Clears UART interrupt sources. +//! +//! The UART interrupt source is cleared, so that it no longer asserts. The +//! highest interrupt flag is automatically cleared when an interrupt vector +//! generator is used. +//! +//! \param baseAddress is the base address of the EUSCI_A_UART module. +//! \param mask is a bit mask of the interrupt sources to be cleared. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG +//! - \b EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG +//! - \b EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG +//! - \b EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG +//! +//! Modified bits of \b UCAxIFG register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_A_UART_clearInterruptFlag(uint16_t baseAddress, uint8_t mask) +{ + assert(!(mask & ~(EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG + | EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG + | EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG + | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG))); + + //Clear the UART interrupt source. + HWREG16(baseAddress + OFS_UCAxIFG) &= ~(mask); +} + +//***************************************************************************** +// +//! \brief Enables the UART block. +//! +//! This will enable operation of the UART block. +//! +//! \param baseAddress is the base address of the EUSCI_A_UART module. +//! +//! Modified bits are \b UCSWRST of \b UCAxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_A_UART_enable(uint16_t baseAddress) +{ + //Reset the UCSWRST bit to enable the USCI Module + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCSWRST); +} + +//***************************************************************************** +// +//! \brief Disables the UART block. +//! +//! This will disable operation of the UART block. +//! +//! \param baseAddress is the base address of the EUSCI_A_UART module. +//! +//! Modified bits are \b UCSWRST of \b UCAxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_A_UART_disable(uint16_t baseAddress) +{ + //Set the UCSWRST bit to disable the USCI Module + HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCSWRST; +} + +//***************************************************************************** +// +//! \brief Gets the current UART status flags. +//! +//! This returns the status for the UART module based on which flag is passed. +//! +//! \param baseAddress is the base address of the EUSCI_A_UART module. +//! \param mask is the masked interrupt flag status to be returned. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_A_UART_LISTEN_ENABLE +//! - \b EUSCI_A_UART_FRAMING_ERROR +//! - \b EUSCI_A_UART_OVERRUN_ERROR +//! - \b EUSCI_A_UART_PARITY_ERROR +//! - \b EUSCI_A_UART_BREAK_DETECT +//! - \b EUSCI_A_UART_RECEIVE_ERROR +//! - \b EUSCI_A_UART_ADDRESS_RECEIVED +//! - \b EUSCI_A_UART_IDLELINE +//! - \b EUSCI_A_UART_BUSY +//! +//! Modified bits of \b UCAxSTAT register. +//! +//! \return Logical OR of any of the following: +//! - \b EUSCI_A_UART_LISTEN_ENABLE +//! - \b EUSCI_A_UART_FRAMING_ERROR +//! - \b EUSCI_A_UART_OVERRUN_ERROR +//! - \b EUSCI_A_UART_PARITY_ERROR +//! - \b EUSCI_A_UART_BREAK_DETECT +//! - \b EUSCI_A_UART_RECEIVE_ERROR +//! - \b EUSCI_A_UART_ADDRESS_RECEIVED +//! - \b EUSCI_A_UART_IDLELINE +//! - \b EUSCI_A_UART_BUSY +//! \n indicating the status of the masked interrupt flags +// +//***************************************************************************** +uint8_t EUSCI_A_UART_queryStatusFlags(uint16_t baseAddress, + uint8_t mask) +{ + assert( 0x00 != mask && (EUSCI_A_UART_LISTEN_ENABLE + + EUSCI_A_UART_FRAMING_ERROR + + EUSCI_A_UART_OVERRUN_ERROR + + EUSCI_A_UART_PARITY_ERROR + + EUSCI_A_UART_BREAK_DETECT + + EUSCI_A_UART_RECEIVE_ERROR + + EUSCI_A_UART_ADDRESS_RECEIVED + + EUSCI_A_UART_IDLELINE + + EUSCI_A_UART_BUSY + )); + + return HWREG16(baseAddress + OFS_UCAxSTATW) & mask; +} + +//***************************************************************************** +// +//! \brief Sets the UART module in dormant mode +//! +//! Puts USCI in sleep mode Only characters that are preceded by an idle-line +//! or with address bit set UCRXIFG. In UART mode with automatic baud-rate +//! detection, only the combination of a break and sync field sets UCRXIFG. +//! +//! \param baseAddress is the base address of the EUSCI_A_UART module. +//! +//! Modified bits of \b UCAxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_A_UART_setDormant(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCDORM; +} + +//***************************************************************************** +// +//! \brief Re-enables UART module from dormant mode +//! +//! Not dormant. All received characters set UCRXIFG. +//! +//! \param baseAddress is the base address of the EUSCI_A_UART module. +//! +//! Modified bits are \b UCDORM of \b UCAxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_A_UART_resetDormant(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCDORM; +} + +//***************************************************************************** +// +//! \brief Transmits the next byte to be transmitted marked as address +//! depending on selected multiprocessor mode +//! +//! \param baseAddress is the base address of the EUSCI_A_UART module. +//! \param transmitAddress is the next byte to be transmitted +//! +//! Modified bits of \b UCAxTXBUF register and bits of \b UCAxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_A_UART_transmitAddress(uint16_t baseAddress, + uint8_t transmitAddress) +{ + //Set UCTXADDR bit + HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCTXADDR; + + //Place next byte to be sent into the transmit buffer + HWREG16(baseAddress + OFS_UCAxTXBUF) = transmitAddress; +} + +//***************************************************************************** +// +//! \brief Transmit break. +//! +//! Transmits a break with the next write to the transmit buffer. In UART mode +//! with automatic baud-rate detection, +//! EUSCI_A_UART_AUTOMATICBAUDRATE_SYNC(0x55) must be written into UCAxTXBUF to +//! generate the required break/sync fields. Otherwise, DEFAULT_SYNC(0x00) must +//! be written into the transmit buffer. Also ensures module is ready for +//! transmitting the next data. +//! +//! \param baseAddress is the base address of the EUSCI_A_UART module. +//! +//! Modified bits of \b UCAxTXBUF register and bits of \b UCAxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_A_UART_transmitBreak(uint16_t baseAddress) +{ + //Set UCTXADDR bit + HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCTXBRK; + + //If current mode is automatic baud-rate detection + if (EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE == + (HWREG16(baseAddress + OFS_UCAxCTLW0) & + EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE)) + HWREG16(baseAddress + OFS_UCAxTXBUF) = EUSCI_A_UART_AUTOMATICBAUDRATE_SYNC; + else + HWREG16(baseAddress + OFS_UCAxTXBUF) = DEFAULT_SYNC; + + //If interrupts are not used, poll for flags + if (!(HWREG16(baseAddress + OFS_UCAxIE) & UCTXIE)) + //Poll for transmit interrupt flag + while (!(HWREG16(baseAddress + OFS_UCAxIFG) & UCTXIFG)) ; +} + +//***************************************************************************** +// +//! \brief Returns the address of the RX Buffer of the UART for the DMA module. +//! +//! Returns the address of the UART RX Buffer. This can be used in conjunction +//! with the DMA to store the received data directly to memory. +//! +//! \param baseAddress is the base address of the EUSCI_A_UART module. +//! +//! \return Address of RX Buffer +// +//***************************************************************************** +uint32_t EUSCI_A_UART_getReceiveBufferAddress(uint16_t baseAddress) +{ + return baseAddress + OFS_UCAxRXBUF; +} + +//***************************************************************************** +// +//! \brief Returns the address of the TX Buffer of the UART for the DMA module. +//! +//! Returns the address of the UART TX Buffer. This can be used in conjunction +//! with the DMA to obtain transmitted data directly from memory. +//! +//! \param baseAddress is the base address of the EUSCI_A_UART module. +//! +//! \return Address of TX Buffer +// +//***************************************************************************** +uint32_t EUSCI_A_UART_getTransmitBufferAddress(uint16_t baseAddress) +{ + return baseAddress + OFS_UCAxTXBUF; +} + +//***************************************************************************** +// +//! \brief Sets the deglitch time +//! +//! \param baseAddress is the base address of the EUSCI_A_UART module. +//! \param deglitchTime is the selected deglitch time +//! Valid values are: +//! - \b EUSCI_A_UART_DEGLITCH_TIME_2ns +//! - \b EUSCI_A_UART_DEGLITCH_TIME_50ns +//! - \b EUSCI_A_UART_DEGLITCH_TIME_100ns +//! - \b EUSCI_A_UART_DEGLITCH_TIME_200ns +//! +//! \return None +// +//***************************************************************************** +void EUSCI_A_UART_selectDeglitchTime(uint16_t baseAddress, + uint16_t deglitchTime + ) +{ + assert((EUSCI_A_UART_DEGLITCH_TIME_2ns == deglitchTime) || + (EUSCI_A_UART_DEGLITCH_TIME_50ns == deglitchTime) || + (EUSCI_A_UART_DEGLITCH_TIME_100ns == deglitchTime) || + (EUSCI_A_UART_DEGLITCH_TIME_200ns == deglitchTime) + ); + + HWREG16(baseAddress + OFS_UCAxCTLW1) &= ~(UCGLIT1 + UCGLIT0); + + HWREG16(baseAddress + OFS_UCAxCTLW1) |= deglitchTime; +} + + +#endif +//***************************************************************************** +// +//! Close the doxygen group for eusci_a_uart_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/eusci_a_uart.h b/source/driverlib/MSP430F5xx_6xx/eusci_a_uart.h new file mode 100644 index 0000000..51bba61 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/eusci_a_uart.h @@ -0,0 +1,283 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// eusci_a_uart.h - Driver for the EUSCI_A_UART Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_EUSCI_A_UART_H__ +#define __MSP430WARE_EUSCI_A_UART_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_EUSCI_Ax__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//****************************************************************************** +// +// The following is a struct that is passed to EUSCI_A_UART_init() +// +//****************************************************************************** +typedef struct EUSCI_A_UART_initParam { + uint8_t selectClockSource; + uint16_t clockPrescalar; + uint8_t firstModReg; + uint8_t secondModReg; + uint8_t parity; + uint16_t msborLsbFirst; + uint16_t numberofStopBits; + uint16_t uartMode; + uint8_t overSampling; +} EUSCI_A_UART_initParam; + +//***************************************************************************** +// +// The following values are the sync characters possible. +// +//***************************************************************************** +#define DEFAULT_SYNC 0x00 +#define EUSCI_A_UART_AUTOMATICBAUDRATE_SYNC 0x55 + +//***************************************************************************** +// +// The following are values that can be passed to the parity parameter for +// functions: EUSCI_A_UART_initAdvance(). +// +//***************************************************************************** +#define EUSCI_A_UART_NO_PARITY 0x00 +#define EUSCI_A_UART_ODD_PARITY 0x01 +#define EUSCI_A_UART_EVEN_PARITY 0x02 + +//***************************************************************************** +// +// The following are values that can be passed to the msborLsbFirst parameter +// for functions: EUSCI_A_UART_initAdvance(). +// +//***************************************************************************** +#define EUSCI_A_UART_MSB_FIRST UCMSB +#define EUSCI_A_UART_LSB_FIRST 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the uartMode parameter for +// functions: EUSCI_A_UART_initAdvance(). +// +//***************************************************************************** +#define EUSCI_A_UART_MODE UCMODE_0 +#define EUSCI_A_UART_IDLE_LINE_MULTI_PROCESSOR_MODE UCMODE_1 +#define EUSCI_A_UART_ADDRESS_BIT_MULTI_PROCESSOR_MODE UCMODE_2 +#define EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE UCMODE_3 + +//***************************************************************************** +// +// The following are values that can be passed to the selectClockSource +// parameter for functions: EUSCI_A_UART_initAdvance(). +// +//***************************************************************************** +#define EUSCI_A_UART_CLOCKSOURCE_SMCLK UCSSEL__SMCLK +#define EUSCI_A_UART_CLOCKSOURCE_ACLK UCSSEL__ACLK + +//***************************************************************************** +// +// The following are values that can be passed to the numberofStopBits +// parameter for functions: EUSCI_A_UART_initAdvance(). +// +//***************************************************************************** +#define EUSCI_A_UART_ONE_STOP_BIT 0x00 +#define EUSCI_A_UART_TWO_STOP_BITS UCSPB + +//***************************************************************************** +// +// The following are values that can be passed to the overSampling parameter +// for functions: EUSCI_A_UART_initAdvance(). +// +//***************************************************************************** +#define EUSCI_A_UART_OVERSAMPLING_BAUDRATE_GENERATION 0x01 +#define EUSCI_A_UART_LOW_FREQUENCY_BAUDRATE_GENERATION 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the mask parameter for +// functions: EUSCI_A_UART_enableInterrupt(), and +// EUSCI_A_UART_disableInterrupt(). +// +//***************************************************************************** +#define EUSCI_A_UART_RECEIVE_INTERRUPT UCRXIE +#define EUSCI_A_UART_TRANSMIT_INTERRUPT UCTXIE +#define EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT UCRXEIE +#define EUSCI_A_UART_BREAKCHAR_INTERRUPT UCBRKIE +#define EUSCI_A_UART_STARTBIT_INTERRUPT UCSTTIE +#define EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT UCTXCPTIE + +//***************************************************************************** +// +// The following are values that can be passed to the mask parameter for +// functions: EUSCI_A_UART_getInterruptStatus(), and +// EUSCI_A_UART_clearInterruptFlag() as well as returned by the +// EUSCI_A_UART_getInterruptStatus() function. +// +//***************************************************************************** +#define EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG UCRXIFG +#define EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG UCTXIFG +#define EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG UCSTTIFG +#define EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG UCTXCPTIFG + +//***************************************************************************** +// +// The following are values that can be passed to the mask parameter for +// functions: EUSCI_A_UART_queryStatusFlags() as well as returned by the +// EUSCI_A_UART_queryStatusFlags() function. +// +//***************************************************************************** +#define EUSCI_A_UART_LISTEN_ENABLE UCLISTEN +#define EUSCI_A_UART_FRAMING_ERROR UCFE +#define EUSCI_A_UART_OVERRUN_ERROR UCOE +#define EUSCI_A_UART_PARITY_ERROR UCPE +#define EUSCI_A_UART_BREAK_DETECT UCBRK +#define EUSCI_A_UART_RECEIVE_ERROR UCRXERR +#define EUSCI_A_UART_ADDRESS_RECEIVED UCADDR +#define EUSCI_A_UART_IDLELINE UCIDLE +#define EUSCI_A_UART_BUSY UCBUSY + +//***************************************************************************** +// +// The following are values that can be passed to the deglitchTime parameter +// for functions: EUSCI_A_UART_selectDeglitchTime(). +// +//***************************************************************************** +#define EUSCI_A_UART_DEGLITCH_TIME_2ns 0x00 +#define EUSCI_A_UART_DEGLITCH_TIME_50ns UCGLIT0 +#define EUSCI_A_UART_DEGLITCH_TIME_100ns UCGLIT1 +#define EUSCI_A_UART_DEGLITCH_TIME_200ns (UCGLIT0 + UCGLIT1) + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern bool EUSCI_A_UART_init(uint16_t baseAddress, + EUSCI_A_UART_initParam *param); + +extern void EUSCI_A_UART_transmitData(uint16_t baseAddress, + uint8_t transmitData); + +extern uint8_t EUSCI_A_UART_receiveData(uint16_t baseAddress); + +extern void EUSCI_A_UART_enableInterrupt(uint16_t baseAddress, + uint8_t mask); + +extern void EUSCI_A_UART_disableInterrupt(uint16_t baseAddress, + uint8_t mask); + +extern uint8_t EUSCI_A_UART_getInterruptStatus(uint16_t baseAddress, + uint8_t mask); + +extern void EUSCI_A_UART_clearInterruptFlag(uint16_t baseAddress, + uint8_t mask); + +extern void EUSCI_A_UART_enable(uint16_t baseAddress); + +extern void EUSCI_A_UART_disable(uint16_t baseAddress); + +extern uint8_t EUSCI_A_UART_queryStatusFlags(uint16_t baseAddress, + uint8_t mask); + +extern void EUSCI_A_UART_setDormant(uint16_t baseAddress); + +extern void EUSCI_A_UART_resetDormant(uint16_t baseAddress); + +extern void EUSCI_A_UART_transmitAddress(uint16_t baseAddress, + uint8_t transmitAddress); + +extern void EUSCI_A_UART_transmitBreak(uint16_t baseAddress); + +extern uint32_t EUSCI_A_UART_getReceiveBufferAddress(uint16_t baseAddress); + +extern uint32_t EUSCI_A_UART_getTransmitBufferAddress(uint16_t baseAddress); + +extern void EUSCI_A_UART_selectDeglitchTime(uint16_t baseAddress, + uint16_t deglitchTime); + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +#define EUSCI_A_UART_getTransmitBufferAddressForDMA \ + EUSCI_A_UART_getTransmitBufferAddress + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +#define EUSCI_A_UART_getReceiveBufferAddressForDMA \ + EUSCI_A_UART_getReceiveBufferAddress + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +extern bool EUSCI_A_UART_initAdvance(uint16_t baseAddress, + uint8_t selectClockSource, + uint16_t clockPrescalar, + uint8_t firstModReg, + uint8_t secondModReg, + uint8_t parity, + uint16_t msborLsbFirst, + uint16_t numberofStopBits, + uint16_t uartMode, + uint8_t overSampling); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_EUSCI_A_UART_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/eusci_b_i2c.c b/source/driverlib/MSP430F5xx_6xx/eusci_b_i2c.c new file mode 100644 index 0000000..fc4faa2 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/eusci_b_i2c.c @@ -0,0 +1,1445 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// eusci_b_i2c.c - Driver for the eusci_b_i2c Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup eusci_b_i2c_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_EUSCI_Bx__ +#include "eusci_b_i2c.h" + +#include + +//***************************************************************************** +// +//! \brief DEPRECATED - Initializes the I2C Master block. +//! +//! This function initializes operation of the I2C Master block. Upon +//! successful initialization of the I2C block, this function will have set the +//! bus speed for the master; however I2C module is still disabled till +//! EUSCI_B_I2C_enable is invoked. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param selectClockSource is the clocksource. +//! Valid values are: +//! - \b EUSCI_B_I2C_CLOCKSOURCE_ACLK +//! - \b EUSCI_B_I2C_CLOCKSOURCE_SMCLK +//! \param i2cClk is the rate of the clock supplied to the I2C module (the +//! frequency in Hz of the clock source specified in selectClockSource). +//! \param dataRate setup for selecting data transfer rate. +//! Valid values are: +//! - \b EUSCI_B_I2C_SET_DATA_RATE_400KBPS +//! - \b EUSCI_B_I2C_SET_DATA_RATE_100KBPS +//! \param byteCounterThreshold sets threshold for automatic STOP or UCSTPIFG +//! \param autoSTOPGeneration sets up the STOP condition generation. +//! Valid values are: +//! - \b EUSCI_B_I2C_NO_AUTO_STOP +//! - \b EUSCI_B_I2C_SET_BYTECOUNT_THRESHOLD_FLAG +//! - \b EUSCI_B_I2C_SEND_STOP_AUTOMATICALLY_ON_BYTECOUNT_THRESHOLD +//! +//! \return None +// +//***************************************************************************** +void EUSCI_B_I2C_masterInit(uint16_t baseAddress, + uint8_t selectClockSource, + uint32_t i2cClk, + uint32_t dataRate, + uint8_t byteCounterThreshold, + uint8_t autoSTOPGeneration + ) +{ + EUSCI_B_I2C_initMasterParam param = { 0 }; + + param.selectClockSource = selectClockSource; + param.i2cClk = i2cClk; + param.dataRate = dataRate; + param.byteCounterThreshold = byteCounterThreshold; + param.autoSTOPGeneration = autoSTOPGeneration; + + EUSCI_B_I2C_initMaster(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Initializes the I2C Master block. +//! +//! This function initializes operation of the I2C Master block. Upon +//! successful initialization of the I2C block, this function will have set the +//! bus speed for the master; however I2C module is still disabled till +//! EUSCI_B_I2C_enable is invoked. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param param is the pointer to the struct for master initialization. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_B_I2C_initMaster(uint16_t baseAddress, + EUSCI_B_I2C_initMasterParam *param + ) +{ + uint16_t preScalarValue; + + assert(param != 0); + + assert((EUSCI_B_I2C_CLOCKSOURCE_ACLK == param->selectClockSource) || + (EUSCI_B_I2C_CLOCKSOURCE_SMCLK == param->selectClockSource) + ); + + assert((EUSCI_B_I2C_SET_DATA_RATE_400KBPS == param->dataRate) || + (EUSCI_B_I2C_SET_DATA_RATE_100KBPS == param->dataRate) + ); + + assert((EUSCI_B_I2C_NO_AUTO_STOP == param->autoSTOPGeneration) || + (EUSCI_B_I2C_SET_BYTECOUNT_THRESHOLD_FLAG == param->autoSTOPGeneration) || + (EUSCI_B_I2C_SEND_STOP_AUTOMATICALLY_ON_BYTECOUNT_THRESHOLD == param->autoSTOPGeneration) + ); + + //Disable the USCI module and clears the other bits of control register + HWREG16(baseAddress + OFS_UCBxCTLW0) = UCSWRST; + + //Configure Automatic STOP condition generation + HWREG16(baseAddress + OFS_UCBxCTLW1) &= ~UCASTP_3; + HWREG16(baseAddress + OFS_UCBxCTLW1) |= param->autoSTOPGeneration; + + //Byte Count Threshold + HWREG16(baseAddress + OFS_UCBxTBCNT) = param->byteCounterThreshold; + /* + * Configure as I2C master mode. + * UCMST = Master mode + * UCMODE_3 = I2C mode + * UCSYNC = Synchronous mode + */ + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCMST + UCMODE_3 + UCSYNC; + + //Configure I2C clock source + HWREG16(baseAddress + OFS_UCBxCTLW0) |= (param->selectClockSource + UCSWRST); + + /* + * Compute the clock divider that achieves the fastest speed less than or + * equal to the desired speed. The numerator is biased to favor a larger + * clock divider so that the resulting clock is always less than or equal + * to the desired clock, never greater. + */ + preScalarValue = (uint16_t)(param->i2cClk / param->dataRate); + HWREG16(baseAddress + OFS_UCBxBRW) = preScalarValue; +} + +//***************************************************************************** +// +//! \brief DEPRECATED - Initializes the I2C Slave block. +//! +//! This function initializes operation of the I2C as a Slave mode. Upon +//! successful initialization of the I2C blocks, this function will have set +//! the slave address but the I2C module is still disabled till +//! EUSCI_B_I2C_enable is invoked. +//! +//! \param baseAddress is the base address of the I2C Slave module. +//! \param slaveAddress 7-bit slave address +//! \param slaveAddressOffset Own address Offset referred to- 'x' value of +//! UCBxI2COAx. +//! Valid values are: +//! - \b EUSCI_B_I2C_OWN_ADDRESS_OFFSET0 +//! - \b EUSCI_B_I2C_OWN_ADDRESS_OFFSET1 +//! - \b EUSCI_B_I2C_OWN_ADDRESS_OFFSET2 +//! - \b EUSCI_B_I2C_OWN_ADDRESS_OFFSET3 +//! \param slaveOwnAddressEnable selects if the specified address is enabled or +//! disabled. +//! Valid values are: +//! - \b EUSCI_B_I2C_OWN_ADDRESS_DISABLE +//! - \b EUSCI_B_I2C_OWN_ADDRESS_ENABLE +//! +//! \return None +// +//***************************************************************************** +void EUSCI_B_I2C_slaveInit(uint16_t baseAddress, + uint8_t slaveAddress, + uint8_t slaveAddressOffset, + uint32_t slaveOwnAddressEnable + ) +{ + EUSCI_B_I2C_initSlaveParam param = { 0 }; + + param.slaveAddress = slaveAddress; + param.slaveAddressOffset = slaveAddressOffset; + param.slaveOwnAddressEnable = slaveOwnAddressEnable; + + EUSCI_B_I2C_initSlave(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Initializes the I2C Slave block. +//! +//! This function initializes operation of the I2C as a Slave mode. Upon +//! successful initialization of the I2C blocks, this function will have set +//! the slave address but the I2C module is still disabled till +//! EUSCI_B_I2C_enable is invoked. +//! +//! \param baseAddress is the base address of the I2C Slave module. +//! \param param is the pointer to the struct for slave initialization. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_B_I2C_initSlave(uint16_t baseAddress, + EUSCI_B_I2C_initSlaveParam *param + ) +{ + assert(param != 0); + + assert((EUSCI_B_I2C_OWN_ADDRESS_OFFSET0 == param->slaveAddressOffset) || + (EUSCI_B_I2C_OWN_ADDRESS_OFFSET1 == param->slaveAddressOffset) || + (EUSCI_B_I2C_OWN_ADDRESS_OFFSET2 == param->slaveAddressOffset) || + (EUSCI_B_I2C_OWN_ADDRESS_OFFSET3 == param->slaveAddressOffset) + ); + + //Disable the USCI module + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCSWRST; + + //Clear USCI master mode + HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~UCMST; + + //Configure I2C as Slave and Synchronous mode + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCMODE_3 + UCSYNC; + + //Set up the slave address. + HWREG16(baseAddress + OFS_UCBxI2COA0 + param->slaveAddressOffset) + = param->slaveAddress + param->slaveOwnAddressEnable; +} +//***************************************************************************** +// +//! \brief Enables the I2C block. +//! +//! This will enable operation of the I2C block. +//! +//! \param baseAddress is the base address of the USCI I2C module. +//! +//! Modified bits are \b UCSWRST of \b UCBxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_B_I2C_enable(uint16_t baseAddress) +{ + //Reset the UCSWRST bit to enable the USCI Module + HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~(UCSWRST); +} + +//***************************************************************************** +// +//! \brief Disables the I2C block. +//! +//! This will disable operation of the I2C block. +//! +//! \param baseAddress is the base address of the USCI I2C module. +//! +//! Modified bits are \b UCSWRST of \b UCBxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_B_I2C_disable(uint16_t baseAddress) +{ + //Set the UCSWRST bit to disable the USCI Module + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCSWRST; +} + +//***************************************************************************** +// +//! \brief Sets the address that the I2C Master will place on the bus. +//! +//! This function will set the address that the I2C Master will place on the +//! bus when initiating a transaction. +//! +//! \param baseAddress is the base address of the USCI I2C module. +//! \param slaveAddress 7-bit slave address +//! +//! Modified bits of \b UCBxI2CSA register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_B_I2C_setSlaveAddress(uint16_t baseAddress, + uint8_t slaveAddress + ) +{ + //Set the address of the slave with which the master will communicate. + HWREG16(baseAddress + OFS_UCBxI2CSA) = (slaveAddress); +} + +//***************************************************************************** +// +//! \brief Sets the mode of the I2C device +//! +//! When the receive parameter is set to EUSCI_B_I2C_TRANSMIT_MODE, the address +//! will indicate that the I2C module is in receive mode; otherwise, the I2C +//! module is in send mode. +//! +//! \param baseAddress is the base address of the USCI I2C module. +//! \param mode Mode for the EUSCI_B_I2C module +//! Valid values are: +//! - \b EUSCI_B_I2C_TRANSMIT_MODE [Default] +//! - \b EUSCI_B_I2C_RECEIVE_MODE +//! +//! Modified bits are \b UCTR of \b UCBxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_B_I2C_setMode(uint16_t baseAddress, + uint8_t mode + ) +{ + assert((EUSCI_B_I2C_TRANSMIT_MODE == mode) || + (EUSCI_B_I2C_RECEIVE_MODE == mode) + ); + + HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~EUSCI_B_I2C_TRANSMIT_MODE; + HWREG16(baseAddress + OFS_UCBxCTLW0) |= mode; +} + +//***************************************************************************** +// +//! \brief Gets the mode of the I2C device +//! +//! Current I2C transmit/receive mode. +//! +//! \param baseAddress is the base address of the I2C module. +//! +//! Modified bits are \b UCTR of \b UCBxCTLW0 register. +//! +//! \return None +//! Return one of the following: +//! - \b EUSCI_B_I2C_TRANSMIT_MODE +//! - \b EUSCI_B_I2C_RECEIVE_MODE +//! \n indicating the current mode +// +//***************************************************************************** +uint8_t EUSCI_B_I2C_getMode(uint16_t baseAddress) +{ + //Read the I2C mode. + return (HWREG16(baseAddress + OFS_UCBxCTLW0) & UCTR); + +} + +//***************************************************************************** +// +//! \brief Transmits a byte from the I2C Module. +//! +//! This function will place the supplied data into I2C transmit data register +//! to start transmission. +//! +//! \param baseAddress is the base address of the I2C Slave module. +//! \param transmitData data to be transmitted from the I2C module +//! +//! Modified bits of \b UCBxTXBUF register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_B_I2C_slaveDataPut(uint16_t baseAddress, + uint8_t transmitData + ) +{ + //Send single byte data. + HWREG16(baseAddress + OFS_UCBxTXBUF) = transmitData; +} + +//***************************************************************************** +// +//! \brief Receives a byte that has been sent to the I2C Module. +//! +//! This function reads a byte of data from the I2C receive data Register. +//! +//! \param baseAddress is the base address of the I2C Slave module. +//! +//! \return Returns the byte received from by the I2C module, cast as an +//! uint8_t. +// +//***************************************************************************** +uint8_t EUSCI_B_I2C_slaveDataGet(uint16_t baseAddress) +{ + //Read a byte. + return HWREG16(baseAddress + OFS_UCBxRXBUF); +} + +//***************************************************************************** +// +//! \brief Indicates whether or not the I2C bus is busy. +//! +//! This function returns an indication of whether or not the I2C bus is busy. +//! This function checks the status of the bus via UCBBUSY bit in UCBxSTAT +//! register. +//! +//! \param baseAddress is the base address of the I2C module. +//! +//! \return One of the following: +//! - \b EUSCI_B_I2C_BUS_BUSY +//! - \b EUSCI_B_I2C_BUS_NOT_BUSY +//! \n indicating whether the bus is busy +// +//***************************************************************************** +uint16_t EUSCI_B_I2C_isBusBusy(uint16_t baseAddress) +{ + //Return the bus busy status. + return HWREG16(baseAddress + OFS_UCBxSTATW) & UCBBUSY; +} + +//***************************************************************************** +// +//! \brief Indicates whether STOP got sent. +//! +//! This function returns an indication of whether or not STOP got sent This +//! function checks the status of the bus via UCTXSTP bit in UCBxCTL1 register. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! +//! \return One of the following: +//! - \b EUSCI_B_I2C_STOP_SEND_COMPLETE +//! - \b EUSCI_B_I2C_SENDING_STOP +//! \n indicating whether the stop was sent +// +//***************************************************************************** +uint16_t EUSCI_B_I2C_masterIsStopSent(uint16_t baseAddress) +{ + return HWREG16(baseAddress + OFS_UCBxCTLW0) & UCTXSTP; +} + +//***************************************************************************** +// +//! \brief Indicates whether Start got sent. +//! +//! This function returns an indication of whether or not Start got sent This +//! function checks the status of the bus via UCTXSTT bit in UCBxCTL1 register. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! +//! \return One of the following: +//! - \b EUSCI_B_I2C_START_SEND_COMPLETE +//! - \b EUSCI_B_I2C_SENDING_START +//! \n indicating whether the start was sent +// +//***************************************************************************** +uint16_t EUSCI_B_I2C_masterIsStartSent(uint16_t baseAddress) +{ + return HWREG16(baseAddress + OFS_UCBxCTLW0) & UCTXSTT; +} + +//***************************************************************************** +// +//! \brief Enables individual I2C interrupt sources. +//! +//! Enables the indicated I2C interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! \param baseAddress is the base address of the I2C module. +//! \param mask is the bit mask of the interrupt sources to be enabled. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_B_I2C_NAK_INTERRUPT - Not-acknowledge interrupt +//! - \b EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT - Arbitration lost +//! interrupt +//! - \b EUSCI_B_I2C_STOP_INTERRUPT - STOP condition interrupt +//! - \b EUSCI_B_I2C_START_INTERRUPT - START condition interrupt +//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT0 - Transmit interrupt0 +//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT1 - Transmit interrupt1 +//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT2 - Transmit interrupt2 +//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT3 - Transmit interrupt3 +//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT0 - Receive interrupt0 +//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT1 - Receive interrupt1 +//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT2 - Receive interrupt2 +//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT3 - Receive interrupt3 +//! - \b EUSCI_B_I2C_BIT9_POSITION_INTERRUPT - Bit position 9 interrupt +//! - \b EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT - Clock low timeout +//! interrupt enable +//! - \b EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT - Byte counter interrupt +//! enable +//! +//! Modified bits of \b UCBxIE register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_B_I2C_enableInterrupt(uint16_t baseAddress, + uint16_t mask + ) +{ + assert( 0x00 == ( mask & ~(EUSCI_B_I2C_STOP_INTERRUPT + + EUSCI_B_I2C_START_INTERRUPT + + EUSCI_B_I2C_NAK_INTERRUPT + + EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT + + EUSCI_B_I2C_BIT9_POSITION_INTERRUPT + + EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT + + EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT + + EUSCI_B_I2C_TRANSMIT_INTERRUPT0 + + EUSCI_B_I2C_TRANSMIT_INTERRUPT1 + + EUSCI_B_I2C_TRANSMIT_INTERRUPT2 + + EUSCI_B_I2C_TRANSMIT_INTERRUPT3 + + EUSCI_B_I2C_RECEIVE_INTERRUPT0 + + EUSCI_B_I2C_RECEIVE_INTERRUPT1 + + EUSCI_B_I2C_RECEIVE_INTERRUPT2 + + EUSCI_B_I2C_RECEIVE_INTERRUPT3 + )) + ); + + //Enable the interrupt masked bit + HWREG16(baseAddress + OFS_UCBxIE) |= mask; +} + +//***************************************************************************** +// +//! \brief Disables individual I2C interrupt sources. +//! +//! Disables the indicated I2C interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! \param baseAddress is the base address of the I2C module. +//! \param mask is the bit mask of the interrupt sources to be disabled. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_B_I2C_NAK_INTERRUPT - Not-acknowledge interrupt +//! - \b EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT - Arbitration lost +//! interrupt +//! - \b EUSCI_B_I2C_STOP_INTERRUPT - STOP condition interrupt +//! - \b EUSCI_B_I2C_START_INTERRUPT - START condition interrupt +//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT0 - Transmit interrupt0 +//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT1 - Transmit interrupt1 +//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT2 - Transmit interrupt2 +//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT3 - Transmit interrupt3 +//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT0 - Receive interrupt0 +//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT1 - Receive interrupt1 +//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT2 - Receive interrupt2 +//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT3 - Receive interrupt3 +//! - \b EUSCI_B_I2C_BIT9_POSITION_INTERRUPT - Bit position 9 interrupt +//! - \b EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT - Clock low timeout +//! interrupt enable +//! - \b EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT - Byte counter interrupt +//! enable +//! +//! Modified bits of \b UCBxIE register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_B_I2C_disableInterrupt(uint16_t baseAddress, + uint16_t mask + ) +{ + assert( 0x00 == ( mask & ~(EUSCI_B_I2C_STOP_INTERRUPT + + EUSCI_B_I2C_START_INTERRUPT + + EUSCI_B_I2C_NAK_INTERRUPT + + EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT + + EUSCI_B_I2C_BIT9_POSITION_INTERRUPT + + EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT + + EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT + + EUSCI_B_I2C_TRANSMIT_INTERRUPT0 + + EUSCI_B_I2C_TRANSMIT_INTERRUPT1 + + EUSCI_B_I2C_TRANSMIT_INTERRUPT2 + + EUSCI_B_I2C_TRANSMIT_INTERRUPT3 + + EUSCI_B_I2C_RECEIVE_INTERRUPT0 + + EUSCI_B_I2C_RECEIVE_INTERRUPT1 + + EUSCI_B_I2C_RECEIVE_INTERRUPT2 + + EUSCI_B_I2C_RECEIVE_INTERRUPT3 + )) + ); + + //Disable the interrupt masked bit + HWREG16(baseAddress + OFS_UCBxIE) &= ~(mask); +} + +//***************************************************************************** +// +//! \brief Clears I2C interrupt sources. +//! +//! The I2C interrupt source is cleared, so that it no longer asserts. The +//! highest interrupt flag is automatically cleared when an interrupt vector +//! generator is used. +//! +//! \param baseAddress is the base address of the I2C module. +//! \param mask is a bit mask of the interrupt sources to be cleared. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_B_I2C_NAK_INTERRUPT - Not-acknowledge interrupt +//! - \b EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT - Arbitration lost +//! interrupt +//! - \b EUSCI_B_I2C_STOP_INTERRUPT - STOP condition interrupt +//! - \b EUSCI_B_I2C_START_INTERRUPT - START condition interrupt +//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT0 - Transmit interrupt0 +//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT1 - Transmit interrupt1 +//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT2 - Transmit interrupt2 +//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT3 - Transmit interrupt3 +//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT0 - Receive interrupt0 +//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT1 - Receive interrupt1 +//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT2 - Receive interrupt2 +//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT3 - Receive interrupt3 +//! - \b EUSCI_B_I2C_BIT9_POSITION_INTERRUPT - Bit position 9 interrupt +//! - \b EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT - Clock low timeout +//! interrupt enable +//! - \b EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT - Byte counter interrupt +//! enable +//! +//! Modified bits of \b UCBxIFG register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_B_I2C_clearInterruptFlag(uint16_t baseAddress, + uint16_t mask + ) +{ + assert( 0x00 == ( mask & ~(EUSCI_B_I2C_STOP_INTERRUPT + + EUSCI_B_I2C_START_INTERRUPT + + EUSCI_B_I2C_NAK_INTERRUPT + + EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT + + EUSCI_B_I2C_BIT9_POSITION_INTERRUPT + + EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT + + EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT + + EUSCI_B_I2C_TRANSMIT_INTERRUPT0 + + EUSCI_B_I2C_TRANSMIT_INTERRUPT1 + + EUSCI_B_I2C_TRANSMIT_INTERRUPT2 + + EUSCI_B_I2C_TRANSMIT_INTERRUPT3 + + EUSCI_B_I2C_RECEIVE_INTERRUPT0 + + EUSCI_B_I2C_RECEIVE_INTERRUPT1 + + EUSCI_B_I2C_RECEIVE_INTERRUPT2 + + EUSCI_B_I2C_RECEIVE_INTERRUPT3 + )) + ); + //Clear the I2C interrupt source. + HWREG16(baseAddress + OFS_UCBxIFG) &= ~(mask); +} + +//***************************************************************************** +// +//! \brief Gets the current I2C interrupt status. +//! +//! This returns the interrupt status for the I2C module based on which flag is +//! passed. +//! +//! \param baseAddress is the base address of the I2C module. +//! \param mask is the masked interrupt flag status to be returned. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_B_I2C_NAK_INTERRUPT - Not-acknowledge interrupt +//! - \b EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT - Arbitration lost +//! interrupt +//! - \b EUSCI_B_I2C_STOP_INTERRUPT - STOP condition interrupt +//! - \b EUSCI_B_I2C_START_INTERRUPT - START condition interrupt +//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT0 - Transmit interrupt0 +//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT1 - Transmit interrupt1 +//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT2 - Transmit interrupt2 +//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT3 - Transmit interrupt3 +//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT0 - Receive interrupt0 +//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT1 - Receive interrupt1 +//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT2 - Receive interrupt2 +//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT3 - Receive interrupt3 +//! - \b EUSCI_B_I2C_BIT9_POSITION_INTERRUPT - Bit position 9 interrupt +//! - \b EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT - Clock low timeout +//! interrupt enable +//! - \b EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT - Byte counter interrupt +//! enable +//! +//! \return Logical OR of any of the following: +//! - \b EUSCI_B_I2C_NAK_INTERRUPT Not-acknowledge interrupt +//! - \b EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT Arbitration lost +//! interrupt +//! - \b EUSCI_B_I2C_STOP_INTERRUPT STOP condition interrupt +//! - \b EUSCI_B_I2C_START_INTERRUPT START condition interrupt +//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT0 Transmit interrupt0 +//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT1 Transmit interrupt1 +//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT2 Transmit interrupt2 +//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT3 Transmit interrupt3 +//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT0 Receive interrupt0 +//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT1 Receive interrupt1 +//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT2 Receive interrupt2 +//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT3 Receive interrupt3 +//! - \b EUSCI_B_I2C_BIT9_POSITION_INTERRUPT Bit position 9 interrupt +//! - \b EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT Clock low timeout +//! interrupt enable +//! - \b EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT Byte counter interrupt +//! enable +//! \n indicating the status of the masked interrupts +// +//***************************************************************************** +uint16_t EUSCI_B_I2C_getInterruptStatus(uint16_t baseAddress, + uint16_t mask + ) +{ + assert( 0x00 == ( mask & ~(EUSCI_B_I2C_STOP_INTERRUPT + + EUSCI_B_I2C_START_INTERRUPT + + EUSCI_B_I2C_NAK_INTERRUPT + + EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT + + EUSCI_B_I2C_BIT9_POSITION_INTERRUPT + + EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT + + EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT + + EUSCI_B_I2C_TRANSMIT_INTERRUPT0 + + EUSCI_B_I2C_TRANSMIT_INTERRUPT1 + + EUSCI_B_I2C_TRANSMIT_INTERRUPT2 + + EUSCI_B_I2C_TRANSMIT_INTERRUPT3 + + EUSCI_B_I2C_RECEIVE_INTERRUPT0 + + EUSCI_B_I2C_RECEIVE_INTERRUPT1 + + EUSCI_B_I2C_RECEIVE_INTERRUPT2 + + EUSCI_B_I2C_RECEIVE_INTERRUPT3 + )) + ); + //Return the interrupt status of the request masked bit. + return HWREG16(baseAddress + OFS_UCBxIFG) & mask; +} + +//***************************************************************************** +// +//! \brief Does single byte transmission from Master to Slave +//! +//! This function is used by the Master module to send a single byte. This +//! function sends a start, then transmits the byte to the slave and then sends +//! a stop. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param txData is the data byte to be transmitted +//! +//! Modified bits of \b UCBxTXBUF register, bits of \b UCBxCTLW0 register, bits +//! of \b UCBxIE register and bits of \b UCBxIFG register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_B_I2C_masterSendSingleByte(uint16_t baseAddress, + uint8_t txData + ) +{ + //Store current TXIE status + uint16_t txieStatus = HWREG16(baseAddress + OFS_UCBxIE) & UCTXIE; + + //Disable transmit interrupt enable + HWREG16(baseAddress + OFS_UCBxIE) &= ~(UCTXIE); + + //Send start condition. + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTR + UCTXSTT; + + //Poll for transmit interrupt flag. + while (!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) ; + + //Send single byte data. + HWREG16(baseAddress + OFS_UCBxTXBUF) = txData; + + //Poll for transmit interrupt flag. + while (!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) ; + + //Send stop condition. + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTXSTP; + + //Clear transmit interrupt flag before enabling interrupt again + HWREG16(baseAddress + OFS_UCBxIFG) &= ~(UCTXIFG); + + //Reinstate transmit interrupt enable + HWREG16(baseAddress + OFS_UCBxIE) |= txieStatus; +} + +//***************************************************************************** +// +//! \brief Does single byte reception from Slave +//! +//! This function is used by the Master module to receive a single byte. This +//! function sends start and stop, waits for data reception and then receives +//! the data from the slave +//! +//! \param baseAddress is the base address of the I2C Master module. +//! +//! Modified bits of \b UCBxTXBUF register, bits of \b UCBxCTLW0 register, bits +//! of \b UCBxIE register and bits of \b UCBxIFG register. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the transmission process. +// +//***************************************************************************** +uint8_t EUSCI_B_I2C_masterReceiveSingleByte(uint16_t baseAddress) +{ + //Set USCI in Receive mode + HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~UCTR; + //Send start + HWREG16(baseAddress + OFS_UCBxCTLW0) |= (UCTXSTT + UCTXSTP); + + //Poll for receive interrupt flag. + while (!(HWREG16(baseAddress + OFS_UCBxIFG) & UCRXIFG)) ; + + //Send single byte data. + return HWREG16(baseAddress + OFS_UCBxRXBUF); +} + +//***************************************************************************** +// +//! \brief Does single byte transmission from Master to Slave with timeout +//! +//! This function is used by the Master module to send a single byte. This +//! function sends a start, then transmits the byte to the slave and then sends +//! a stop. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param txData is the data byte to be transmitted +//! \param timeout is the amount of time to wait until giving up +//! +//! Modified bits of \b UCBxTXBUF register, bits of \b UCBxCTLW0 register, bits +//! of \b UCBxIE register and bits of \b UCBxIFG register. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the transmission process. +// +//***************************************************************************** +bool EUSCI_B_I2C_masterSendSingleByteWithTimeout(uint16_t baseAddress, + uint8_t txData, + uint32_t timeout + ) +{ + assert(timeout > 0); + + // Creating variable for second timeout scenario + uint32_t timeout2 = timeout; + + //Store current TXIE status + uint16_t txieStatus = HWREG16(baseAddress + OFS_UCBxIE) & UCTXIE; + + //Disable transmit interrupt enable + HWREG16(baseAddress + OFS_UCBxIE) &= ~(UCTXIE); + + //Send start condition. + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTR + UCTXSTT; + + //Poll for transmit interrupt flag. + while ((!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) && --timeout) ; + + //Check if transfer timed out + if (timeout == 0) + return STATUS_FAIL; + + //Send single byte data. + HWREG16(baseAddress + OFS_UCBxTXBUF) = txData; + + //Poll for transmit interrupt flag. + while ((!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) && --timeout2) ; + + //Check if transfer timed out + if (timeout2 == 0) + return STATUS_FAIL; + + //Send stop condition. + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTXSTP; + + //Clear transmit interrupt flag before enabling interrupt again + HWREG16(baseAddress + OFS_UCBxIFG) &= ~(UCTXIFG); + + //Reinstate transmit interrupt enable + HWREG16(baseAddress + OFS_UCBxIE) |= txieStatus; + + return STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! \brief Starts multi-byte transmission from Master to Slave +//! +//! This function is used by the master module to start a multi byte +//! transaction. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param txData is the first data byte to be transmitted +//! +//! Modified bits of \b UCBxTXBUF register, bits of \b UCBxCTLW0 register, bits +//! of \b UCBxIE register and bits of \b UCBxIFG register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_B_I2C_masterMultiByteSendStart(uint16_t baseAddress, + uint8_t txData + ) +{ + //Store current transmit interrupt enable + uint16_t txieStatus = HWREG16(baseAddress + OFS_UCBxIE) & UCTXIE; + + //Disable transmit interrupt enable + HWREG16(baseAddress + OFS_UCBxIE) &= ~(UCTXIE); + + //Send start condition. + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTR + UCTXSTT; + + //Poll for transmit interrupt flag. + while (!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) ; + + //Send single byte data. + HWREG16(baseAddress + OFS_UCBxTXBUF) = txData; + + //Reinstate transmit interrupt enable + HWREG16(baseAddress + OFS_UCBxIE) |= txieStatus; +} + +//***************************************************************************** +// +//! \brief Starts multi-byte transmission from Master to Slave with timeout +//! +//! This function is used by the master module to start a multi byte +//! transaction. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param txData is the first data byte to be transmitted +//! \param timeout is the amount of time to wait until giving up +//! +//! Modified bits of \b UCBxTXBUF register, bits of \b UCBxCTLW0 register, bits +//! of \b UCBxIE register and bits of \b UCBxIFG register. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the transmission process. +// +//***************************************************************************** +bool EUSCI_B_I2C_masterMultiByteSendStartWithTimeout(uint16_t baseAddress, + uint8_t txData, + uint32_t timeout + ) +{ + assert(timeout > 0); + + //Store current transmit interrupt enable + uint16_t txieStatus = HWREG16(baseAddress + OFS_UCBxIE) & UCTXIE; + + //Disable transmit interrupt enable + HWREG16(baseAddress + OFS_UCBxIE) &= ~(UCTXIE); + + //Send start condition. + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTR + UCTXSTT; + + //Poll for transmit interrupt flag. + while ((!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) && --timeout) ; + + //Check if transfer timed out + if (timeout == 0) + return STATUS_FAIL; + + //Send single byte data. + HWREG16(baseAddress + OFS_UCBxTXBUF) = txData; + + //Reinstate transmit interrupt enable + HWREG16(baseAddress + OFS_UCBxIE) |= txieStatus; + + return STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! \brief Continues multi-byte transmission from Master to Slave +//! +//! This function is used by the Master module continue each byte of a multi- +//! byte transmission. This function transmits each data byte of a multi-byte +//! transmission to the slave. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param txData is the next data byte to be transmitted +//! +//! Modified bits of \b UCBxTXBUF register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_B_I2C_masterMultiByteSendNext(uint16_t baseAddress, + uint8_t txData + ) +{ + //If interrupts are not used, poll for flags + if (!(HWREG16(baseAddress + OFS_UCBxIE) & UCTXIE)) + //Poll for transmit interrupt flag. + while (!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) ; + + //Send single byte data. + HWREG16(baseAddress + OFS_UCBxTXBUF) = txData; +} + +//***************************************************************************** +// +//! \brief Continues multi-byte transmission from Master to Slave with timeout +//! +//! This function is used by the Master module continue each byte of a multi- +//! byte transmission. This function transmits each data byte of a multi-byte +//! transmission to the slave. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param txData is the next data byte to be transmitted +//! \param timeout is the amount of time to wait until giving up +//! +//! Modified bits of \b UCBxTXBUF register. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the transmission process. +// +//***************************************************************************** +bool EUSCI_B_I2C_masterMultiByteSendNextWithTimeout(uint16_t baseAddress, + uint8_t txData, + uint32_t timeout + ) +{ + assert(timeout > 0); + + //If interrupts are not used, poll for flags + if (!(HWREG16(baseAddress + OFS_UCBxIE) & UCTXIE)) { + //Poll for transmit interrupt flag. + while ((!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) && --timeout) ; + + //Check if transfer timed out + if (timeout == 0) + return STATUS_FAIL; + } + + //Send single byte data. + HWREG16(baseAddress + OFS_UCBxTXBUF) = txData; + + return STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! \brief Finishes multi-byte transmission from Master to Slave +//! +//! This function is used by the Master module to send the last byte and STOP. +//! This function transmits the last data byte of a multi-byte transmission to +//! the slave and then sends a stop. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param txData is the last data byte to be transmitted in a multi-byte +//! transmission +//! +//! Modified bits of \b UCBxTXBUF register and bits of \b UCBxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_B_I2C_masterMultiByteSendFinish(uint16_t baseAddress, + uint8_t txData + ) +{ + //If interrupts are not used, poll for flags + if (!(HWREG16(baseAddress + OFS_UCBxIE) & UCTXIE)) + //Poll for transmit interrupt flag. + while (!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) ; + + //Send single byte data. + HWREG16(baseAddress + OFS_UCBxTXBUF) = txData; + + //Poll for transmit interrupt flag. + while (!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) ; + + //Send stop condition. + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTXSTP; +} + +//***************************************************************************** +// +//! \brief Finishes multi-byte transmission from Master to Slave with timeout +//! +//! This function is used by the Master module to send the last byte and STOP. +//! This function transmits the last data byte of a multi-byte transmission to +//! the slave and then sends a stop. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param txData is the last data byte to be transmitted in a multi-byte +//! transmission +//! \param timeout is the amount of time to wait until giving up +//! +//! Modified bits of \b UCBxTXBUF register and bits of \b UCBxCTLW0 register. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the transmission process. +// +//***************************************************************************** +bool EUSCI_B_I2C_masterMultiByteSendFinishWithTimeout(uint16_t baseAddress, + uint8_t txData, + uint32_t timeout + ) +{ + uint32_t timeout2 = timeout; + + assert(timeout > 0); + + //If interrupts are not used, poll for flags + if (!(HWREG16(baseAddress + OFS_UCBxIE) & UCTXIE)) { + //Poll for transmit interrupt flag. + while ((!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) && --timeout) ; + + //Check if transfer timed out + if (timeout == 0) + return STATUS_FAIL; + } + + //Send single byte data. + HWREG16(baseAddress + OFS_UCBxTXBUF) = txData; + + //Poll for transmit interrupt flag. + while ((!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) && --timeout2) ; + + //Check if transfer timed out + if (timeout2 == 0) + return STATUS_FAIL; + + //Send stop condition. + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTXSTP; + + return STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! \brief This function is used by the Master module to initiate START +//! +//! This function is used by the Master module to initiate START +//! +//! \param baseAddress is the base address of the I2C Master module. +//! +//! Modified bits are \b UCTXSTT of \b UCBxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_B_I2C_masterSendStart(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTXSTT; +} + +//***************************************************************************** +// +//! \brief Send STOP byte at the end of a multi-byte transmission from Master +//! to Slave +//! +//! This function is used by the Master module send STOP at the end of a multi- +//! byte transmission. This function sends a stop after current transmission is +//! complete. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! +//! Modified bits are \b UCTXSTP of \b UCBxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_B_I2C_masterMultiByteSendStop(uint16_t baseAddress) +{ + //If interrupts are not used, poll for flags + if (!(HWREG16(baseAddress + OFS_UCBxIE) & UCTXIE)) + //Poll for transmit interrupt flag. + while (!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) ; + + //Send stop condition. + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTXSTP; +} + +//***************************************************************************** +// +//! \brief Send STOP byte at the end of a multi-byte transmission from Master +//! to Slave with timeout +//! +//! This function is used by the Master module send STOP at the end of a multi- +//! byte transmission. This function sends a stop after current transmission is +//! complete. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param timeout is the amount of time to wait until giving up +//! +//! Modified bits are \b UCTXSTP of \b UCBxCTLW0 register. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the transmission process. +// +//***************************************************************************** +bool EUSCI_B_I2C_masterMultiByteSendStopWithTimeout(uint16_t baseAddress, + uint32_t timeout) +{ + assert(timeout > 0); + + //If interrupts are not used, poll for flags + if (!(HWREG16(baseAddress + OFS_UCBxIE) & UCTXIE)) { + //Poll for transmit interrupt flag. + while ((!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) && --timeout) ; + + //Check if transfer timed out + if (timeout == 0) + return STATUS_FAIL; + } + + //Send stop condition. + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTXSTP; + + return STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! \brief Starts reception at the Master end +//! +//! This function is used by the Master module initiate reception of a single +//! byte. This function sends a start. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! +//! Modified bits are \b UCTXSTT of \b UCBxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_B_I2C_masterReceiveStart(uint16_t baseAddress) +{ + //Set USCI in Receive mode + HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~UCTR; + //Send start + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTXSTT; +} + +//***************************************************************************** +// +//! \brief Starts multi-byte reception at the Master end one byte at a time +//! +//! This function is used by the Master module to receive each byte of a multi- +//! byte reception. This function reads currently received byte. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! +//! \return Received byte at Master end. +// +//***************************************************************************** +uint8_t EUSCI_B_I2C_masterMultiByteReceiveNext(uint16_t baseAddress) +{ + return HWREG16(baseAddress + OFS_UCBxRXBUF); +} + +//***************************************************************************** +// +//! \brief Finishes multi-byte reception at the Master end +//! +//! This function is used by the Master module to initiate completion of a +//! multi-byte reception. This function receives the current byte and initiates +//! the STOP from master to slave. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! +//! Modified bits are \b UCTXSTP of \b UCBxCTLW0 register. +//! +//! \return Received byte at Master end. +// +//***************************************************************************** +uint8_t EUSCI_B_I2C_masterMultiByteReceiveFinish(uint16_t baseAddress) +{ + //Send stop condition. + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTXSTP; + + //Wait for Stop to finish + while (HWREG16(baseAddress + OFS_UCBxCTLW0) & UCTXSTP) + + // Wait for RX buffer + while (!(HWREG16(baseAddress + OFS_UCBxIFG) & UCRXIFG)) ; + + //Capture data from receive buffer after setting stop bit due to + //MSP430 I2C critical timing. + return HWREG16(baseAddress + OFS_UCBxRXBUF); +} + +//***************************************************************************** +// +//! \brief Finishes multi-byte reception at the Master end with timeout +//! +//! This function is used by the Master module to initiate completion of a +//! multi-byte reception. This function receives the current byte and initiates +//! the STOP from master to slave. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param txData is a pointer to the location to store the received byte at +//! master end +//! \param timeout is the amount of time to wait until giving up +//! +//! Modified bits are \b UCTXSTP of \b UCBxCTLW0 register. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the reception process +// +//***************************************************************************** +bool EUSCI_B_I2C_masterMultiByteReceiveFinishWithTimeout(uint16_t baseAddress, + uint8_t *txData, + uint32_t timeout + ) +{ + assert(timeout > 0); + + uint32_t timeout2 = timeout; + + //Send stop condition. + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTXSTP; + + //Wait for Stop to finish + while ((HWREG16(baseAddress + OFS_UCBxCTLW0) & UCTXSTP) && --timeout) ; + + //Check if transfer timed out + if (timeout == 0) + return STATUS_FAIL; + + // Wait for RX buffer + while ((!(HWREG16(baseAddress + OFS_UCBxIFG) & UCRXIFG)) && --timeout2) ; + + //Check if transfer timed out + if (timeout2 == 0) + return STATUS_FAIL; + + //Capture data from receive buffer after setting stop bit due to + //MSP430 I2C critical timing. + *txData = (HWREG8(baseAddress + OFS_UCBxRXBUF)); + + return STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! \brief Sends the STOP at the end of a multi-byte reception at the Master +//! end +//! +//! This function is used by the Master module to initiate STOP +//! +//! \param baseAddress is the base address of the I2C Master module. +//! +//! Modified bits are \b UCTXSTP of \b UCBxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_B_I2C_masterMultiByteReceiveStop(uint16_t baseAddress) +{ + //Send stop condition. + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTXSTP; +} + +//***************************************************************************** +// +//! \brief Enables Multi Master Mode +//! +//! At the end of this function, the I2C module is still disabled till +//! EUSCI_B_I2C_enable is invoked +//! +//! \param baseAddress is the base address of the I2C module. +//! +//! Modified bits are \b UCSWRST and \b UCMM of \b UCBxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_B_I2C_enableMultiMasterMode(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCSWRST; + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCMM; +} + +//***************************************************************************** +// +//! \brief Disables Multi Master Mode +//! +//! At the end of this function, the I2C module is still disabled till +//! EUSCI_B_I2C_enable is invoked +//! +//! \param baseAddress is the base address of the I2C module. +//! +//! Modified bits are \b UCSWRST and \b UCMM of \b UCBxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_B_I2C_disableMultiMasterMode(uint16_t baseAddress) +{ + + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCSWRST; + HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~UCMM; +} + +//***************************************************************************** +// +//! \brief receives a byte that has been sent to the I2C Master Module. +//! +//! This function reads a byte of data from the I2C receive data Register. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! +//! \return Returns the byte received from by the I2C module, cast as an +//! uint8_t. +// +//***************************************************************************** +uint8_t EUSCI_B_I2C_masterSingleReceive(uint16_t baseAddress) +{ + //Polling RXIFG0 if RXIE is not enabled + if (!(HWREG16(baseAddress + OFS_UCBxIE) & UCRXIE0)) + while (!(HWREG16(baseAddress + OFS_UCBxIFG) & UCRXIFG0)) ; + + //Read a byte. + return HWREG16(baseAddress + OFS_UCBxRXBUF); +} + +//***************************************************************************** +// +//! \brief Returns the address of the RX Buffer of the I2C for the DMA module. +//! +//! Returns the address of the I2C RX Buffer. This can be used in conjunction +//! with the DMA to store the received data directly to memory. +//! +//! \param baseAddress is the base address of the I2C module. +//! +//! \return The address of the I2C RX Buffer +// +//***************************************************************************** +uint32_t EUSCI_B_I2C_getReceiveBufferAddress(uint16_t baseAddress) +{ + return baseAddress + OFS_UCBxRXBUF; +} + +//***************************************************************************** +// +//! \brief Returns the address of the TX Buffer of the I2C for the DMA module. +//! +//! Returns the address of the I2C TX Buffer. This can be used in conjunction +//! with the DMA to obtain transmitted data directly from memory. +//! +//! \param baseAddress is the base address of the I2C module. +//! +//! \return The address of the I2C TX Buffer +// +//***************************************************************************** +uint32_t EUSCI_B_I2C_getTransmitBufferAddress(uint16_t baseAddress) +{ + return baseAddress + OFS_UCBxTXBUF; +} + +#endif +//***************************************************************************** +// +//! Close the doxygen group for eusci_b_i2c_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/eusci_b_i2c.h b/source/driverlib/MSP430F5xx_6xx/eusci_b_i2c.h new file mode 100644 index 0000000..fcb1127 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/eusci_b_i2c.h @@ -0,0 +1,344 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// eusci_b_i2c.h - Driver for the EUSCI_B_I2C Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_EUSCI_B_I2C_H__ +#define __MSP430WARE_EUSCI_B_I2C_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_EUSCI_Bx__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//****************************************************************************** +// +// The following is a struct that is passed to EUSCI_B_I2C_initMaster() +// +//****************************************************************************** +typedef struct EUSCI_B_I2C_initMasterParam { + uint8_t selectClockSource; + uint32_t i2cClk; + uint32_t dataRate; + uint8_t byteCounterThreshold; + uint8_t autoSTOPGeneration; +} EUSCI_B_I2C_initMasterParam; + +//****************************************************************************** +// +// The following is a struct that is passed to EUSCI_B_I2C_initSlave() +// +//****************************************************************************** +typedef struct EUSCI_B_I2C_initSlaveParam { + uint8_t slaveAddress; + uint8_t slaveAddressOffset; + uint32_t slaveOwnAddressEnable; +} EUSCI_B_I2C_initSlaveParam; + +//***************************************************************************** +// +// The following are values that can be passed to the autoSTOPGeneration +// parameter for functions: EUSCI_B_I2C_masterInit(). +// +//***************************************************************************** +#define EUSCI_B_I2C_NO_AUTO_STOP UCASTP_0 +#define EUSCI_B_I2C_SET_BYTECOUNT_THRESHOLD_FLAG UCASTP_1 +#define EUSCI_B_I2C_SEND_STOP_AUTOMATICALLY_ON_BYTECOUNT_THRESHOLD UCASTP_2 + +//***************************************************************************** +// +// The following are values that can be passed to the dataRate parameter for +// functions: EUSCI_B_I2C_masterInit(). +// +//***************************************************************************** +#define EUSCI_B_I2C_SET_DATA_RATE_400KBPS 400000 +#define EUSCI_B_I2C_SET_DATA_RATE_100KBPS 100000 + +//***************************************************************************** +// +// The following are values that can be passed to the selectClockSource +// parameter for functions: EUSCI_B_I2C_masterInit(). +// +//***************************************************************************** +#define EUSCI_B_I2C_CLOCKSOURCE_ACLK UCSSEL__ACLK +#define EUSCI_B_I2C_CLOCKSOURCE_SMCLK UCSSEL__SMCLK + +//***************************************************************************** +// +// The following are values that can be passed to the slaveAddressOffset +// parameter for functions: EUSCI_B_I2C_slaveInit(). +// +//***************************************************************************** +#define EUSCI_B_I2C_OWN_ADDRESS_OFFSET0 0x00 +#define EUSCI_B_I2C_OWN_ADDRESS_OFFSET1 0x02 +#define EUSCI_B_I2C_OWN_ADDRESS_OFFSET2 0x04 +#define EUSCI_B_I2C_OWN_ADDRESS_OFFSET3 0x06 + +//***************************************************************************** +// +// The following are values that can be passed to the slaveOwnAddressEnable +// parameter for functions: EUSCI_B_I2C_slaveInit(). +// +//***************************************************************************** +#define EUSCI_B_I2C_OWN_ADDRESS_DISABLE 0x00 +#define EUSCI_B_I2C_OWN_ADDRESS_ENABLE UCOAEN + +//***************************************************************************** +// +// The following are values that can be passed to the mode parameter for +// functions: EUSCI_B_I2C_setMode() as well as returned by the +// EUSCI_B_I2C_getMode() function. +// +//***************************************************************************** +#define EUSCI_B_I2C_TRANSMIT_MODE UCTR +#define EUSCI_B_I2C_RECEIVE_MODE 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the mask parameter for +// functions: EUSCI_B_I2C_enableInterrupt(), EUSCI_B_I2C_disableInterrupt(), +// EUSCI_B_I2C_clearInterruptFlag(), and EUSCI_B_I2C_getInterruptStatus() as +// well as returned by the EUSCI_B_I2C_getInterruptStatus() function. +// +//***************************************************************************** +#define EUSCI_B_I2C_NAK_INTERRUPT UCNACKIE +#define EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT UCALIE +#define EUSCI_B_I2C_STOP_INTERRUPT UCSTPIE +#define EUSCI_B_I2C_START_INTERRUPT UCSTTIE +#define EUSCI_B_I2C_TRANSMIT_INTERRUPT0 UCTXIE0 +#define EUSCI_B_I2C_TRANSMIT_INTERRUPT1 UCTXIE1 +#define EUSCI_B_I2C_TRANSMIT_INTERRUPT2 UCTXIE2 +#define EUSCI_B_I2C_TRANSMIT_INTERRUPT3 UCTXIE3 +#define EUSCI_B_I2C_RECEIVE_INTERRUPT0 UCRXIE0 +#define EUSCI_B_I2C_RECEIVE_INTERRUPT1 UCRXIE1 +#define EUSCI_B_I2C_RECEIVE_INTERRUPT2 UCRXIE2 +#define EUSCI_B_I2C_RECEIVE_INTERRUPT3 UCRXIE3 +#define EUSCI_B_I2C_BIT9_POSITION_INTERRUPT UCBIT9IE +#define EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT UCCLTOIE +#define EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT UCBCNTIE + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the EUSCI_B_I2C_isBusBusy() function. +// +//***************************************************************************** +#define EUSCI_B_I2C_BUS_BUSY UCBBUSY +#define EUSCI_B_I2C_BUS_NOT_BUSY 0x00 + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the EUSCI_B_I2C_masterIsStopSent() function. +// +//***************************************************************************** +#define EUSCI_B_I2C_STOP_SEND_COMPLETE 0x00 +#define EUSCI_B_I2C_SENDING_STOP UCTXSTP + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the EUSCI_B_I2C_masterIsStartSent() function. +// +//***************************************************************************** +#define EUSCI_B_I2C_START_SEND_COMPLETE 0x00 +#define EUSCI_B_I2C_SENDING_START UCTXSTT + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void EUSCI_B_I2C_initMaster(uint16_t baseAddress, + EUSCI_B_I2C_initMasterParam *param); + +extern void EUSCI_B_I2C_initSlave(uint16_t baseAddress, + EUSCI_B_I2C_initSlaveParam *param); + +extern void EUSCI_B_I2C_enable(uint16_t baseAddress); + +extern void EUSCI_B_I2C_disable(uint16_t baseAddress); + +extern void EUSCI_B_I2C_setSlaveAddress(uint16_t baseAddress, + uint8_t slaveAddress); + +extern void EUSCI_B_I2C_setMode(uint16_t baseAddress, + uint8_t mode); + +extern uint8_t EUSCI_B_I2C_getMode(uint16_t baseAddress); + +extern void EUSCI_B_I2C_slaveDataPut(uint16_t baseAddress, + uint8_t transmitData); + +extern uint8_t EUSCI_B_I2C_slaveDataGet(uint16_t baseAddress); + +extern uint16_t EUSCI_B_I2C_isBusBusy(uint16_t baseAddress); + +extern uint16_t EUSCI_B_I2C_masterIsStopSent(uint16_t baseAddress); + +extern uint16_t EUSCI_B_I2C_masterIsStartSent(uint16_t baseAddress); + +extern void EUSCI_B_I2C_enableInterrupt(uint16_t baseAddress, + uint16_t mask); + +extern void EUSCI_B_I2C_disableInterrupt(uint16_t baseAddress, + uint16_t mask); + +extern void EUSCI_B_I2C_clearInterruptFlag(uint16_t baseAddress, + uint16_t mask); + +extern uint16_t EUSCI_B_I2C_getInterruptStatus(uint16_t baseAddress, + uint16_t mask); + +extern void EUSCI_B_I2C_masterSendSingleByte(uint16_t baseAddress, + uint8_t txData); + +extern uint8_t EUSCI_B_I2C_masterReceiveSingleByte(uint16_t baseAddress); + +extern bool EUSCI_B_I2C_masterSendSingleByteWithTimeout(uint16_t baseAddress, + uint8_t txData, + uint32_t timeout); + +extern void EUSCI_B_I2C_masterMultiByteSendStart(uint16_t baseAddress, + uint8_t txData); + +extern bool EUSCI_B_I2C_masterMultiByteSendStartWithTimeout(uint16_t baseAddress, + uint8_t txData, + uint32_t timeout); + +extern void EUSCI_B_I2C_masterMultiByteSendNext(uint16_t baseAddress, + uint8_t txData); + +extern bool EUSCI_B_I2C_masterMultiByteSendNextWithTimeout(uint16_t baseAddress, + uint8_t txData, + uint32_t timeout); + +extern void EUSCI_B_I2C_masterMultiByteSendFinish(uint16_t baseAddress, + uint8_t txData); + +extern bool EUSCI_B_I2C_masterMultiByteSendFinishWithTimeout(uint16_t baseAddress, + uint8_t txData, + uint32_t timeout); + +extern void EUSCI_B_I2C_masterSendStart(uint16_t baseAddress); + +extern void EUSCI_B_I2C_masterMultiByteSendStop(uint16_t baseAddress); + +extern bool EUSCI_B_I2C_masterMultiByteSendStopWithTimeout(uint16_t baseAddress, + uint32_t timeout); + +extern void EUSCI_B_I2C_masterReceiveStart(uint16_t baseAddress); + +extern uint8_t EUSCI_B_I2C_masterMultiByteReceiveNext(uint16_t baseAddress); + +extern uint8_t EUSCI_B_I2C_masterMultiByteReceiveFinish(uint16_t baseAddress); + +extern bool EUSCI_B_I2C_masterMultiByteReceiveFinishWithTimeout(uint16_t baseAddress, + uint8_t *txData, + uint32_t timeout); + +extern void EUSCI_B_I2C_masterMultiByteReceiveStop(uint16_t baseAddress); + +extern void EUSCI_B_I2C_enableMultiMasterMode(uint16_t baseAddress); + +extern void EUSCI_B_I2C_disableMultiMasterMode(uint16_t baseAddress); + +extern uint8_t EUSCI_B_I2C_masterSingleReceive(uint16_t baseAddress); + +extern uint32_t EUSCI_B_I2C_getReceiveBufferAddress(uint16_t baseAddress); + +extern uint32_t EUSCI_B_I2C_getTransmitBufferAddress(uint16_t baseAddress); + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +#define EUSCI_B_I2C_getTransmitBufferAddressForDMA \ + EUSCI_B_I2C_getTransmitBufferAddress + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +#define EUSCI_B_I2C_getReceiveBufferAddressForDMA \ + EUSCI_B_I2C_getReceiveBufferAddress + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +#define EUSCI_B_I2C_masterIsSTOPSent EUSCI_B_I2C_masterIsStopSent + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +extern void EUSCI_B_I2C_masterInit(uint16_t baseAddress, + uint8_t selectClockSource, + uint32_t i2cClk, + uint32_t dataRate, + uint8_t byteCounterThreshold, + uint8_t autoSTOPGeneration); + +extern void EUSCI_B_I2C_slaveInit(uint16_t baseAddress, + uint8_t slaveAddress, + uint8_t slaveAddressOffset, + uint32_t slaveOwnAddressEnable); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_EUSCI_B_I2C_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/eusci_b_spi.c b/source/driverlib/MSP430F5xx_6xx/eusci_b_spi.c new file mode 100644 index 0000000..23684cb --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/eusci_b_spi.c @@ -0,0 +1,694 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// eusci_b_spi.c - Driver for the eusci_b_spi Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup eusci_b_spi_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_EUSCI_Bx__ +#include "eusci_b_spi.h" + +#include + +//***************************************************************************** +// +//! \brief DEPRECATED - Initializes the SPI Master block. +//! +//! Upon successful initialization of the SPI master block, this function will +//! have set the bus speed for the master, but the SPI Master block still +//! remains disabled and must be enabled with EUSCI_B_SPI_enable() +//! +//! \param baseAddress is the base address of the EUSCI_B_SPI Master module. +//! \param selectClockSource selects Clock source. +//! Valid values are: +//! - \b EUSCI_B_SPI_CLOCKSOURCE_ACLK +//! - \b EUSCI_B_SPI_CLOCKSOURCE_SMCLK +//! \param clockSourceFrequency is the frequency of the selected clock source +//! \param desiredSpiClock is the desired clock rate for SPI communication +//! \param msbFirst controls the direction of the receive and transmit shift +//! register. +//! Valid values are: +//! - \b EUSCI_B_SPI_MSB_FIRST +//! - \b EUSCI_B_SPI_LSB_FIRST [Default] +//! \param clockPhase is clock phase select. +//! Valid values are: +//! - \b EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT +//! [Default] +//! - \b EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT +//! \param clockPolarity is clock polarity select +//! Valid values are: +//! - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH +//! - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default] +//! \param spiMode is SPI mode select +//! Valid values are: +//! - \b EUSCI_B_SPI_3PIN +//! - \b EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH +//! - \b EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW +//! +//! Modified bits are \b UCCKPH, \b UCCKPL, \b UC7BIT, \b UCMSB, \b UCSSELx and +//! \b UCSWRST of \b UCAxCTLW0 register. +//! +//! \return STATUS_SUCCESS +// +//***************************************************************************** +void EUSCI_B_SPI_masterInit(uint16_t baseAddress, + uint8_t selectClockSource, + uint32_t clockSourceFrequency, + uint32_t desiredSpiClock, + uint16_t msbFirst, + uint16_t clockPhase, + uint16_t clockPolarity, + uint16_t spiMode + ) +{ + EUSCI_B_SPI_initMasterParam param = { 0 }; + + param.selectClockSource = selectClockSource; + param.clockSourceFrequency = clockSourceFrequency; + param.desiredSpiClock = desiredSpiClock; + param.msbFirst = msbFirst; + param.clockPhase = clockPhase; + param.clockPolarity = clockPolarity; + param.spiMode = spiMode; + + EUSCI_B_SPI_initMaster(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Initializes the SPI Master block. +//! +//! Upon successful initialization of the SPI master block, this function will +//! have set the bus speed for the master, but the SPI Master block still +//! remains disabled and must be enabled with EUSCI_B_SPI_enable() +//! +//! \param baseAddress is the base address of the EUSCI_B_SPI Master module. +//! \param param is the pointer to struct for master initialization. +//! +//! Modified bits are \b UCCKPH, \b UCCKPL, \b UC7BIT, \b UCMSB, \b UCSSELx and +//! \b UCSWRST of \b UCAxCTLW0 register. +//! +//! \return STATUS_SUCCESS +// +//***************************************************************************** +void EUSCI_B_SPI_initMaster(uint16_t baseAddress, + EUSCI_B_SPI_initMasterParam *param) +{ + assert(param != 0); + + assert( + (EUSCI_B_SPI_CLOCKSOURCE_ACLK == param->selectClockSource) || + (EUSCI_B_SPI_CLOCKSOURCE_SMCLK == param->selectClockSource) + ); + + assert((EUSCI_B_SPI_MSB_FIRST == param->msbFirst) || + (EUSCI_B_SPI_LSB_FIRST == param->msbFirst) + ); + + assert((EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT == param->clockPhase) || + (EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT == param->clockPhase) + ); + + assert((EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == param->clockPolarity) || + (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW == param->clockPolarity) + ); + + assert( + (EUSCI_B_SPI_3PIN == param->spiMode) || + (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH == param->spiMode) || + (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW == param->spiMode) + ); + + //Disable the USCI Module + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCSWRST; + + //Reset OFS_UCBxCTLW0 values + HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~(UCCKPH + UCCKPL + UC7BIT + UCMSB + + UCMST + UCMODE_3 + UCSYNC); + + //Reset OFS_UCBxCTLW0 values + HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~(UCSSEL_3); + + //Select Clock + HWREG16(baseAddress + OFS_UCBxCTLW0) |= param->selectClockSource; + + HWREG16(baseAddress + OFS_UCBxBRW) = + (uint16_t)(param->clockSourceFrequency / param->desiredSpiClock); + + /* + * Configure as SPI master mode. + * Clock phase select, polarity, msb + * UCMST = Master mode + * UCSYNC = Synchronous mode + * UCMODE_0 = 3-pin SPI + */ + HWREG16(baseAddress + OFS_UCBxCTLW0) |= ( + param->msbFirst + + param->clockPhase + + param->clockPolarity + + UCMST + + UCSYNC + + param->spiMode + ); +} + +//***************************************************************************** +// +//! \brief Selects 4Pin Functionality +//! +//! This function should be invoked only in 4-wire mode. Invoking this function +//! has no effect in 3-wire mode. +//! +//! \param baseAddress is the base address of the EUSCI_B_SPI module. +//! \param select4PinFunctionality selects 4 pin functionality +//! Valid values are: +//! - \b EUSCI_B_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS +//! - \b EUSCI_B_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE +//! +//! Modified bits are \b UCSTEM of \b UCAxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_B_SPI_select4PinFunctionality(uint16_t baseAddress, + uint8_t select4PinFunctionality + ) +{ + assert( (EUSCI_B_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS == select4PinFunctionality) || + (EUSCI_B_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE == select4PinFunctionality) + ); + + HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~UCSTEM; + HWREG16(baseAddress + OFS_UCBxCTLW0) |= select4PinFunctionality; +} + +//***************************************************************************** +// +//! \brief DEPRECATED - Initializes the SPI Master clock. At the end of this +//! function call, SPI module is left enabled. +//! +//! \param baseAddress is the base address of the EUSCI_B_SPI module. +//! \param clockSourceFrequency is the frequency of the selected clock source +//! \param desiredSpiClock is the desired clock rate for SPI communication +//! +//! Modified bits are \b UCSWRST of \b UCAxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_B_SPI_masterChangeClock(uint16_t baseAddress, + uint32_t clockSourceFrequency, + uint32_t desiredSpiClock + ) +{ + EUSCI_B_SPI_changeMasterClockParam param = { 0 }; + + param.clockSourceFrequency = clockSourceFrequency; + param.desiredSpiClock = desiredSpiClock; + + EUSCI_B_SPI_changeMasterClock(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Initializes the SPI Master clock. At the end of this function call, +//! SPI module is left enabled. +//! +//! \param baseAddress is the base address of the EUSCI_B_SPI module. +//! \param param is the pointer to struct for master clock setting. +//! +//! Modified bits are \b UCSWRST of \b UCAxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_B_SPI_changeMasterClock(uint16_t baseAddress, + EUSCI_B_SPI_changeMasterClockParam *param) +{ + assert(param != 0); + + //Disable the USCI Module + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCSWRST; + + HWREG16(baseAddress + OFS_UCBxBRW) = + (uint16_t)(param->clockSourceFrequency / param->desiredSpiClock); + + //Reset the UCSWRST bit to enable the USCI Module + HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~(UCSWRST); +} +//***************************************************************************** +// +//! \brief DEPRECATED - Initializes the SPI Slave block. +//! +//! Upon successful initialization of the SPI slave block, this function will +//! have initialized the slave block, but the SPI Slave block still remains +//! disabled and must be enabled with EUSCI_B_SPI_enable() +//! +//! \param baseAddress is the base address of the EUSCI_B_SPI Slave module. +//! \param msbFirst controls the direction of the receive and transmit shift +//! register. +//! Valid values are: +//! - \b EUSCI_B_SPI_MSB_FIRST +//! - \b EUSCI_B_SPI_LSB_FIRST [Default] +//! \param clockPhase is clock phase select. +//! Valid values are: +//! - \b EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT +//! [Default] +//! - \b EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT +//! \param clockPolarity is clock polarity select +//! Valid values are: +//! - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH +//! - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default] +//! \param spiMode is SPI mode select +//! Valid values are: +//! - \b EUSCI_B_SPI_3PIN +//! - \b EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH +//! - \b EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW +//! +//! Modified bits are \b UCMSB, \b UCMST, \b UC7BIT, \b UCCKPL, \b UCCKPH, \b +//! UCMODE and \b UCSWRST of \b UCAxCTLW0 register. +//! +//! \return STATUS_SUCCESS +// +//***************************************************************************** +void EUSCI_B_SPI_slaveInit(uint16_t baseAddress, + uint16_t msbFirst, + uint16_t clockPhase, + uint16_t clockPolarity, + uint16_t spiMode + ) +{ + EUSCI_B_SPI_initSlaveParam param = { 0 }; + + param.msbFirst = msbFirst; + param.clockPhase = clockPhase; + param.clockPolarity = clockPolarity; + param.spiMode = spiMode; + + EUSCI_B_SPI_initSlave(baseAddress, ¶m); + +} + +//***************************************************************************** +// +//! \brief Initializes the SPI Slave block. +//! +//! Upon successful initialization of the SPI slave block, this function will +//! have initialized the slave block, but the SPI Slave block still remains +//! disabled and must be enabled with EUSCI_B_SPI_enable() +//! +//! \param baseAddress is the base address of the EUSCI_B_SPI Slave module. +//! \param param is the pointer to struct for slave initialization. +//! +//! Modified bits are \b UCMSB, \b UCMST, \b UC7BIT, \b UCCKPL, \b UCCKPH, \b +//! UCMODE and \b UCSWRST of \b UCAxCTLW0 register. +//! +//! \return STATUS_SUCCESS +// +//***************************************************************************** +void EUSCI_B_SPI_initSlave(uint16_t baseAddress, EUSCI_B_SPI_initSlaveParam *param) +{ + assert(param != 0); + + assert( + (EUSCI_B_SPI_MSB_FIRST == param->msbFirst) || + (EUSCI_B_SPI_LSB_FIRST == param->msbFirst) + ); + + assert( + (EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT == param->clockPhase) || + (EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT == param->clockPhase) + ); + + assert( + (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == param->clockPolarity) || + (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW == param->clockPolarity) + ); + + assert( + (EUSCI_B_SPI_3PIN == param->spiMode) || + (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH == param->spiMode) || + (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW == param->spiMode) + ); + + //Disable USCI Module + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCSWRST; + + //Reset OFS_UCBxCTLW0 register + HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~(UCMSB + + UC7BIT + + UCMST + + UCCKPL + + UCCKPH + + UCMODE_3 + ); + + //Clock polarity, phase select, msbFirst, SYNC, Mode0 + HWREG16(baseAddress + OFS_UCBxCTLW0) |= (param->clockPhase + + param->clockPolarity + + param->msbFirst + + UCSYNC + + param->spiMode + ); +} + +//***************************************************************************** +// +//! \brief Changes the SPI clock phase and polarity. At the end of this +//! function call, SPI module is left enabled. +//! +//! \param baseAddress is the base address of the EUSCI_B_SPI module. +//! \param clockPhase is clock phase select. +//! Valid values are: +//! - \b EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT +//! [Default] +//! - \b EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT +//! \param clockPolarity is clock polarity select +//! Valid values are: +//! - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH +//! - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default] +//! +//! Modified bits are \b UCCKPL, \b UCCKPH and \b UCSWRST of \b UCAxCTLW0 +//! register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_B_SPI_changeClockPhasePolarity(uint16_t baseAddress, + uint16_t clockPhase, + uint16_t clockPolarity + ) +{ + + assert( (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == clockPolarity) || + (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW == clockPolarity) + ); + + assert( (EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT == clockPhase) || + (EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT == clockPhase) + ); + + //Disable the USCI Module + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCSWRST; + + HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~(UCCKPH + UCCKPL); + + HWREG16(baseAddress + OFS_UCBxCTLW0) |= ( + clockPhase + + clockPolarity + ); + + //Reset the UCSWRST bit to enable the USCI Module + HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~(UCSWRST); +} + +//***************************************************************************** +// +//! \brief Transmits a byte from the SPI Module. +//! +//! This function will place the supplied data into SPI transmit data register +//! to start transmission. +//! +//! \param baseAddress is the base address of the EUSCI_B_SPI module. +//! \param transmitData data to be transmitted from the SPI module +//! +//! \return None +// +//***************************************************************************** +void EUSCI_B_SPI_transmitData( uint16_t baseAddress, + uint8_t transmitData + ) +{ + HWREG16(baseAddress + OFS_UCBxTXBUF) = transmitData; +} + +//***************************************************************************** +// +//! \brief Receives a byte that has been sent to the SPI Module. +//! +//! This function reads a byte of data from the SPI receive data Register. +//! +//! \param baseAddress is the base address of the EUSCI_B_SPI module. +//! +//! \return Returns the byte received from by the SPI module, cast as an +//! uint8_t. +// +//***************************************************************************** +uint8_t EUSCI_B_SPI_receiveData(uint16_t baseAddress) +{ + return HWREG16(baseAddress + OFS_UCBxRXBUF); +} + +//***************************************************************************** +// +//! \brief Enables individual SPI interrupt sources. +//! +//! Enables the indicated SPI interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. Does not clear interrupt flags. +//! +//! \param baseAddress is the base address of the EUSCI_B_SPI module. +//! \param mask is the bit mask of the interrupt sources to be enabled. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT +//! - \b EUSCI_B_SPI_RECEIVE_INTERRUPT +//! +//! Modified bits of \b UCAxIFG register and bits of \b UCAxIE register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_B_SPI_enableInterrupt(uint16_t baseAddress, + uint8_t mask + ) +{ + assert(!(mask & ~(EUSCI_B_SPI_RECEIVE_INTERRUPT + | EUSCI_B_SPI_TRANSMIT_INTERRUPT))); + + HWREG16(baseAddress + OFS_UCBxIE) |= mask; +} + +//***************************************************************************** +// +//! \brief Disables individual SPI interrupt sources. +//! +//! Disables the indicated SPI interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! \param baseAddress is the base address of the EUSCI_B_SPI module. +//! \param mask is the bit mask of the interrupt sources to be disabled. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT +//! - \b EUSCI_B_SPI_RECEIVE_INTERRUPT +//! +//! Modified bits of \b UCAxIE register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_B_SPI_disableInterrupt(uint16_t baseAddress, + uint8_t mask + ) +{ + assert(!(mask & ~(EUSCI_B_SPI_RECEIVE_INTERRUPT + | EUSCI_B_SPI_TRANSMIT_INTERRUPT))); + + HWREG16(baseAddress + OFS_UCBxIE) &= ~mask; +} + +//***************************************************************************** +// +//! \brief Gets the current SPI interrupt status. +//! +//! This returns the interrupt status for the SPI module based on which flag is +//! passed. +//! +//! \param baseAddress is the base address of the EUSCI_B_SPI module. +//! \param mask is the masked interrupt flag status to be returned. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT +//! - \b EUSCI_B_SPI_RECEIVE_INTERRUPT +//! +//! \return Logical OR of any of the following: +//! - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT +//! - \b EUSCI_B_SPI_RECEIVE_INTERRUPT +//! \n indicating the status of the masked interrupts +// +//***************************************************************************** +uint8_t EUSCI_B_SPI_getInterruptStatus(uint16_t baseAddress, + uint8_t mask + ) +{ + assert(!(mask & ~(EUSCI_B_SPI_RECEIVE_INTERRUPT + | EUSCI_B_SPI_TRANSMIT_INTERRUPT))); + + return HWREG16(baseAddress + OFS_UCBxIFG) & mask; +} + +//***************************************************************************** +// +//! \brief Clears the selected SPI interrupt status flag. +//! +//! \param baseAddress is the base address of the EUSCI_B_SPI module. +//! \param mask is the masked interrupt flag to be cleared. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT +//! - \b EUSCI_B_SPI_RECEIVE_INTERRUPT +//! +//! Modified bits of \b UCAxIFG register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_B_SPI_clearInterruptFlag(uint16_t baseAddress, + uint8_t mask + ) +{ + assert(!(mask & ~(EUSCI_B_SPI_RECEIVE_INTERRUPT + | EUSCI_B_SPI_TRANSMIT_INTERRUPT))); + + HWREG16(baseAddress + OFS_UCBxIFG) &= ~mask; +} + +//***************************************************************************** +// +//! \brief Enables the SPI block. +//! +//! This will enable operation of the SPI block. +//! +//! \param baseAddress is the base address of the EUSCI_B_SPI module. +//! +//! Modified bits are \b UCSWRST of \b UCAxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_B_SPI_enable(uint16_t baseAddress) +{ + //Reset the UCSWRST bit to enable the USCI Module + HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~(UCSWRST); +} + +//***************************************************************************** +// +//! \brief Disables the SPI block. +//! +//! This will disable operation of the SPI block. +//! +//! \param baseAddress is the base address of the EUSCI_B_SPI module. +//! +//! Modified bits are \b UCSWRST of \b UCAxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_B_SPI_disable(uint16_t baseAddress) +{ + //Set the UCSWRST bit to disable the USCI Module + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCSWRST; +} + +//***************************************************************************** +// +//! \brief Returns the address of the RX Buffer of the SPI for the DMA module. +//! +//! Returns the address of the SPI RX Buffer. This can be used in conjunction +//! with the DMA to store the received data directly to memory. +//! +//! \param baseAddress is the base address of the EUSCI_B_SPI module. +//! +//! \return the address of the RX Buffer +// +//***************************************************************************** +uint32_t EUSCI_B_SPI_getReceiveBufferAddress(uint16_t baseAddress) +{ + return baseAddress + OFS_UCBxRXBUF; +} + +//***************************************************************************** +// +//! \brief Returns the address of the TX Buffer of the SPI for the DMA module. +//! +//! Returns the address of the SPI TX Buffer. This can be used in conjunction +//! with the DMA to obtain transmitted data directly from memory. +//! +//! \param baseAddress is the base address of the EUSCI_B_SPI module. +//! +//! \return the address of the TX Buffer +// +//***************************************************************************** +uint32_t EUSCI_B_SPI_getTransmitBufferAddress(uint16_t baseAddress) +{ + return baseAddress + OFS_UCBxTXBUF; +} + +//***************************************************************************** +// +//! \brief Indicates whether or not the SPI bus is busy. +//! +//! This function returns an indication of whether or not the SPI bus is +//! busy.This function checks the status of the bus via UCBBUSY bit +//! +//! \param baseAddress is the base address of the EUSCI_B_SPI module. +//! +//! \return One of the following: +//! - \b EUSCI_B_SPI_BUSY +//! - \b EUSCI_B_SPI_NOT_BUSY +//! \n indicating if the EUSCI_B_SPI is busy +// +//***************************************************************************** +uint16_t EUSCI_B_SPI_isBusy(uint16_t baseAddress) +{ + //Return the bus busy status. + return HWREG16(baseAddress + OFS_UCBxSTATW) & UCBUSY; +} + + +#endif +//***************************************************************************** +// +//! Close the doxygen group for eusci_b_spi_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/eusci_b_spi.h b/source/driverlib/MSP430F5xx_6xx/eusci_b_spi.h new file mode 100644 index 0000000..3fd4741 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/eusci_b_spi.h @@ -0,0 +1,268 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// eusci_b_spi.h - Driver for the EUSCI_B_SPI Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_EUSCI_B_SPI_H__ +#define __MSP430WARE_EUSCI_B_SPI_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_EUSCI_Bx__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//****************************************************************************** +// +// The following is a struct that is passed to EUSCI_B_SPI_initMaster() +// +//****************************************************************************** +typedef struct EUSCI_B_SPI_initMasterParam { + uint8_t selectClockSource; + uint32_t clockSourceFrequency; + uint32_t desiredSpiClock; + uint16_t msbFirst; + uint16_t clockPhase; + uint16_t clockPolarity; + uint16_t spiMode; +} EUSCI_B_SPI_initMasterParam; + +//****************************************************************************** +// +// The following is a struct that is passed to EUSCI_B_SPI_initSlave() +// +//****************************************************************************** +typedef struct EUSCI_B_SPI_initSlaveParam { + uint16_t msbFirst; + uint16_t clockPhase; + uint16_t clockPolarity; + uint16_t spiMode; +} EUSCI_B_SPI_initSlaveParam; + +//****************************************************************************** +// +// The following is a struct that is passed to EUSCI_B_SPI_changeMasterClock() +// +//****************************************************************************** +typedef struct EUSCI_B_SPI_changeMasterClockParam { + uint32_t clockSourceFrequency; + uint32_t desiredSpiClock; +} EUSCI_B_SPI_changeMasterClockParam; + +//***************************************************************************** +// +// The following are values that can be passed to the clockPhase parameter for +// functions: EUSCI_B_SPI_masterInit(), EUSCI_B_SPI_slaveInit(), and +// EUSCI_B_SPI_changeClockPhasePolarity(). +// +//***************************************************************************** +#define EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT 0x00 +#define EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT UCCKPH + +//***************************************************************************** +// +// The following are values that can be passed to the msbFirst parameter for +// functions: EUSCI_B_SPI_masterInit(), and EUSCI_B_SPI_slaveInit(). +// +//***************************************************************************** +#define EUSCI_B_SPI_MSB_FIRST UCMSB +#define EUSCI_B_SPI_LSB_FIRST 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the clockPolarity parameter +// for functions: EUSCI_B_SPI_masterInit(), EUSCI_B_SPI_slaveInit(), and +// EUSCI_B_SPI_changeClockPhasePolarity(). +// +//***************************************************************************** +#define EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH UCCKPL +#define EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the selectClockSource +// parameter for functions: EUSCI_B_SPI_masterInit(). +// +//***************************************************************************** +#define EUSCI_B_SPI_CLOCKSOURCE_ACLK UCSSEL__ACLK +#define EUSCI_B_SPI_CLOCKSOURCE_SMCLK UCSSEL__SMCLK + +//***************************************************************************** +// +// The following are values that can be passed to the spiMode parameter for +// functions: EUSCI_B_SPI_masterInit(), and EUSCI_B_SPI_slaveInit(). +// +//***************************************************************************** +#define EUSCI_B_SPI_3PIN UCMODE_0 +#define EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH UCMODE_1 +#define EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW UCMODE_2 + +//***************************************************************************** +// +// The following are values that can be passed to the select4PinFunctionality +// parameter for functions: EUSCI_B_SPI_select4PinFunctionality(). +// +//***************************************************************************** +#define EUSCI_B_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS 0x00 +#define EUSCI_B_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE UCSTEM + +//***************************************************************************** +// +// The following are values that can be passed to the mask parameter for +// functions: EUSCI_B_SPI_enableInterrupt(), EUSCI_B_SPI_disableInterrupt(), +// EUSCI_B_SPI_getInterruptStatus(), and EUSCI_B_SPI_clearInterruptFlag() as +// well as returned by the EUSCI_B_SPI_getInterruptStatus() function. +// +//***************************************************************************** +#define EUSCI_B_SPI_TRANSMIT_INTERRUPT UCTXIE +#define EUSCI_B_SPI_RECEIVE_INTERRUPT UCRXIE + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the EUSCI_B_SPI_isBusy() function. +// +//***************************************************************************** +#define EUSCI_B_SPI_BUSY UCBUSY +#define EUSCI_B_SPI_NOT_BUSY 0x00 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void EUSCI_B_SPI_initMaster(uint16_t baseAddress, + EUSCI_B_SPI_initMasterParam *param); + +extern void EUSCI_B_SPI_select4PinFunctionality(uint16_t baseAddress, + uint8_t select4PinFunctionality); + +extern void EUSCI_B_SPI_changeMasterClock(uint16_t baseAddress, + EUSCI_B_SPI_changeMasterClockParam *param); + +extern void EUSCI_B_SPI_initSlave(uint16_t baseAddress, + EUSCI_B_SPI_initSlaveParam *param); + +extern void EUSCI_B_SPI_changeClockPhasePolarity(uint16_t baseAddress, + uint16_t clockPhase, + uint16_t clockPolarity); + +extern void EUSCI_B_SPI_transmitData(uint16_t baseAddress, + uint8_t transmitData); + +extern uint8_t EUSCI_B_SPI_receiveData(uint16_t baseAddress); + +extern void EUSCI_B_SPI_enableInterrupt(uint16_t baseAddress, + uint8_t mask); + +extern void EUSCI_B_SPI_disableInterrupt(uint16_t baseAddress, + uint8_t mask); + +extern uint8_t EUSCI_B_SPI_getInterruptStatus(uint16_t baseAddress, + uint8_t mask); + +extern void EUSCI_B_SPI_clearInterruptFlag(uint16_t baseAddress, + uint8_t mask); + +extern void EUSCI_B_SPI_enable(uint16_t baseAddress); + +extern void EUSCI_B_SPI_disable(uint16_t baseAddress); + +extern uint32_t EUSCI_B_SPI_getReceiveBufferAddress(uint16_t baseAddress); + +extern uint32_t EUSCI_B_SPI_getTransmitBufferAddress(uint16_t baseAddress); + +extern uint16_t EUSCI_B_SPI_isBusy(uint16_t baseAddress); + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +#define EUSCI_B_SPI_getTransmitBufferAddressForDMA \ + EUSCI_B_SPI_getTransmitBufferAddress + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +#define EUSCI_B_SPI_getReceiveBufferAddressForDMA \ + EUSCI_B_SPI_getReceiveBufferAddress + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +extern void EUSCI_B_SPI_masterInit(uint16_t baseAddress, + uint8_t selectClockSource, + uint32_t clockSourceFrequency, + uint32_t desiredSpiClock, + uint16_t msbFirst, + uint16_t clockPhase, + uint16_t clockPolarity, + uint16_t spiMode); + +extern void EUSCI_B_SPI_masterChangeClock(uint16_t baseAddress, + uint32_t clockSourceFrequency, + uint32_t desiredSpiClock); + +extern void EUSCI_B_SPI_slaveInit(uint16_t baseAddress, + uint16_t msbFirst, + uint16_t clockPhase, + uint16_t clockPolarity, + uint16_t spiMode); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_EUSCI_B_SPI_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/eusci_i2c.c b/source/driverlib/MSP430F5xx_6xx/eusci_i2c.c new file mode 100644 index 0000000..80f311e --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/eusci_i2c.c @@ -0,0 +1,1443 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// eusci_i2c.c - Driver for the eusci_i2c Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup eusci_i2c_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_EUSCI_Bx__ +#include "eusci_i2c.h" + +#include + +//***************************************************************************** +// +//! \brief DEPRECATED - Initializes the I2C Master block. +//! +//! This function initializes operation of the I2C Master block. Upon +//! successful initialization of the I2C block, this function will have set the +//! bus speed for the master; however I2C module is still disabled till +//! EUSCI_I2C_enable is invoked. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param selectClockSource is the clocksource. +//! Valid values are: +//! - \b EUSCI_I2C_CLOCKSOURCE_ACLK +//! - \b EUSCI_I2C_CLOCKSOURCE_SMCLK +//! \param i2cClk is the rate of the clock supplied to the I2C module (the +//! frequency in Hz of the clock source specified in selectClockSource). +//! \param dataRate setup for selecting data transfer rate. +//! Valid values are: +//! - \b EUSCI_I2C_SET_DATA_RATE_400KBPS +//! - \b EUSCI_I2C_SET_DATA_RATE_100KBPS +//! \param byteCounterThreshold sets threshold for automatic STOP or UCSTPIFG +//! \param autoSTOPGeneration sets up the STOP condition generation. +//! Valid values are: +//! - \b EUSCI_I2C_NO_AUTO_STOP +//! - \b EUSCI_I2C_SET_BYTECOUNT_THRESHOLD_FLAG +//! - \b EUSCI_I2C_SEND_STOP_AUTOMATICALLY_ON_BYTECOUNT_THRESHOLD +//! +//! \return None +// +//***************************************************************************** +void EUSCI_I2C_masterInit(uint16_t baseAddress, + uint8_t selectClockSource, + uint32_t i2cClk, + uint32_t dataRate, + uint8_t byteCounterThreshold, + uint8_t autoSTOPGeneration + ) +{ + EUSCI_I2C_initMasterParam param = { 0 }; + + param.selectClockSource = selectClockSource; + param.i2cClk = i2cClk; + param.dataRate = dataRate; + param.byteCounterThreshold = byteCounterThreshold; + param.autoSTOPGeneration = autoSTOPGeneration; + + EUSCI_I2C_initMaster(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Initializes the I2C Master block. +//! +//! This function initializes operation of the I2C Master block. Upon +//! successful initialization of the I2C block, this function will have set the +//! bus speed for the master; however I2C module is still disabled till +//! EUSCI_I2C_enable is invoked. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param param is the pointer to the struct for master initialization. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_I2C_initMaster(uint16_t baseAddress, + EUSCI_I2C_initMasterParam *param + ) +{ + uint16_t preScalarValue; + + assert(param != 0); + + assert((EUSCI_I2C_CLOCKSOURCE_ACLK == param->selectClockSource) || + (EUSCI_I2C_CLOCKSOURCE_SMCLK == param->selectClockSource) + ); + + assert((EUSCI_I2C_SET_DATA_RATE_400KBPS == param->dataRate) || + (EUSCI_I2C_SET_DATA_RATE_100KBPS == param->dataRate) + ); + + assert((EUSCI_I2C_NO_AUTO_STOP == param->autoSTOPGeneration) || + (EUSCI_I2C_SET_BYTECOUNT_THRESHOLD_FLAG == param->autoSTOPGeneration) || + (EUSCI_I2C_SEND_STOP_AUTOMATICALLY_ON_BYTECOUNT_THRESHOLD == param->autoSTOPGeneration) + ); + + //Disable the USCI module and clears the other bits of control register + HWREG16(baseAddress + OFS_UCBxCTLW0) = UCSWRST; + + //Configure Automatic STOP condition generation + HWREG16(baseAddress + OFS_UCBxCTLW1) &= ~UCASTP_3; + HWREG16(baseAddress + OFS_UCBxCTLW1) |= param->autoSTOPGeneration; + + //Byte Count Threshold + HWREG16(baseAddress + OFS_UCBxTBCNT) = param->byteCounterThreshold; + /* + * Configure as I2C master mode. + * UCMST = Master mode + * UCMODE_3 = I2C mode + * UCSYNC = Synchronous mode + */ + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCMST + UCMODE_3 + UCSYNC; + + //Configure I2C clock source + HWREG16(baseAddress + OFS_UCBxCTLW0) |= (param->selectClockSource + UCSWRST); + + /* + * Compute the clock divider that achieves the fastest speed less than or + * equal to the desired speed. The numerator is biased to favor a larger + * clock divider so that the resulting clock is always less than or equal + * to the desired clock, never greater. + */ + preScalarValue = (uint16_t)(param->i2cClk / param->dataRate); + HWREG16(baseAddress + OFS_UCBxBRW) = preScalarValue; +} + +//***************************************************************************** +// +//! \brief DEPRECATED - Initializes the I2C Slave block. +//! +//! This function initializes operation of the I2C as a Slave mode. Upon +//! successful initialization of the I2C blocks, this function will have set +//! the slave address but the I2C module is still disabled till +//! EUSCI_I2C_enable is invoked. +//! +//! \param baseAddress is the base address of the I2C Slave module. +//! \param slaveAddress 7-bit slave address +//! \param slaveAddressOffset Own address Offset referred to- 'x' value of +//! UCBxI2COAx. +//! Valid values are: +//! - \b EUSCI_I2C_OWN_ADDRESS_OFFSET0 +//! - \b EUSCI_I2C_OWN_ADDRESS_OFFSET1 +//! - \b EUSCI_I2C_OWN_ADDRESS_OFFSET2 +//! - \b EUSCI_I2C_OWN_ADDRESS_OFFSET3 +//! \param slaveOwnAddressEnable selects if the specified address is enabled or +//! disabled. +//! Valid values are: +//! - \b EUSCI_I2C_OWN_ADDRESS_DISABLE +//! - \b EUSCI_I2C_OWN_ADDRESS_ENABLE +//! +//! \return None +// +//***************************************************************************** +void EUSCI_I2C_slaveInit(uint16_t baseAddress, + uint8_t slaveAddress, + uint8_t slaveAddressOffset, + uint32_t slaveOwnAddressEnable + ) +{ + EUSCI_I2C_initSlaveParam param = { 0 }; + + param.slaveAddress = slaveAddress; + param.slaveAddressOffset = slaveAddressOffset; + param.slaveOwnAddressEnable = slaveOwnAddressEnable; + + EUSCI_I2C_initSlave(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Initializes the I2C Slave block. +//! +//! This function initializes operation of the I2C as a Slave mode. Upon +//! successful initialization of the I2C blocks, this function will have set +//! the slave address but the I2C module is still disabled till +//! EUSCI_I2C_enable is invoked. +//! +//! \param baseAddress is the base address of the I2C Slave module. +//! \param param is the pointer to the struct for slave initialization. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_I2C_initSlave(uint16_t baseAddress, + EUSCI_I2C_initSlaveParam *param + ) +{ + assert(param != 0); + + assert((EUSCI_I2C_OWN_ADDRESS_OFFSET0 == param->slaveAddressOffset) || + (EUSCI_I2C_OWN_ADDRESS_OFFSET1 == param->slaveAddressOffset) || + (EUSCI_I2C_OWN_ADDRESS_OFFSET2 == param->slaveAddressOffset) || + (EUSCI_I2C_OWN_ADDRESS_OFFSET3 == param->slaveAddressOffset) + ); + + //Disable the USCI module + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCSWRST; + + //Clear USCI master mode + HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~UCMST; + + //Configure I2C as Slave and Synchronous mode + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCMODE_3 + UCSYNC; + + //Set up the slave address. + HWREG16(baseAddress + OFS_UCBxI2COA0 + param->slaveAddressOffset) + = param->slaveAddress + param->slaveOwnAddressEnable; +} +//***************************************************************************** +// +//! \brief Enables the I2C block. +//! +//! This will enable operation of the I2C block. +//! +//! \param baseAddress is the base address of the USCI I2C module. +//! +//! Modified bits are \b UCSWRST of \b UCBxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_I2C_enable(uint16_t baseAddress) +{ + //Reset the UCSWRST bit to enable the USCI Module + HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~(UCSWRST); +} + +//***************************************************************************** +// +//! \brief Disables the I2C block. +//! +//! This will disable operation of the I2C block. +//! +//! \param baseAddress is the base address of the USCI I2C module. +//! +//! Modified bits are \b UCSWRST of \b UCBxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_I2C_disable(uint16_t baseAddress) +{ + //Set the UCSWRST bit to disable the USCI Module + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCSWRST; +} + +//***************************************************************************** +// +//! \brief Sets the address that the I2C Master will place on the bus. +//! +//! This function will set the address that the I2C Master will place on the +//! bus when initiating a transaction. +//! +//! \param baseAddress is the base address of the USCI I2C module. +//! \param slaveAddress 7-bit slave address +//! +//! Modified bits of \b UCBxI2CSA register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_I2C_setSlaveAddress(uint16_t baseAddress, + uint8_t slaveAddress + ) +{ + //Set the address of the slave with which the master will communicate. + HWREG16(baseAddress + OFS_UCBxI2CSA) = (slaveAddress); +} + +//***************************************************************************** +// +//! \brief Sets the mode of the I2C device +//! +//! When the receive parameter is set to EUSCI_I2C_TRANSMIT_MODE, the address +//! will indicate that the I2C module is in receive mode; otherwise, the I2C +//! module is in send mode. +//! +//! \param baseAddress is the base address of the USCI I2C module. +//! \param mode Mode for the EUSCI_I2C module +//! Valid values are: +//! - \b EUSCI_I2C_TRANSMIT_MODE [Default] +//! - \b EUSCI_I2C_RECEIVE_MODE +//! +//! Modified bits are \b UCTR of \b UCBxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_I2C_setMode(uint16_t baseAddress, + uint8_t mode + ) +{ + assert((EUSCI_I2C_TRANSMIT_MODE == mode) || + (EUSCI_I2C_RECEIVE_MODE == mode) + ); + + HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~EUSCI_I2C_TRANSMIT_MODE; + HWREG16(baseAddress + OFS_UCBxCTLW0) |= mode; +} + +//***************************************************************************** +// +//! \brief Gets the mode of the I2C device +//! +//! Current I2C transmit/receive mode. +//! +//! \param baseAddress is the base address of the I2C module. +//! +//! Modified bits are \b UCTR of \b UCBxCTLW0 register. +//! +//! \return None +//! Return one of the following: +//! - \b EUSCI_I2C_TRANSMIT_MODE +//! - \b EUSCI_I2C_RECEIVE_MODE +//! \n indicating the current mode +// +//***************************************************************************** +uint8_t EUSCI_I2C_getMode(uint16_t baseAddress) +{ + //Read the I2C mode. + return (HWREG16(baseAddress + OFS_UCBxCTLW0) & UCTR); + +} + +//***************************************************************************** +// +//! \brief Transmits a byte from the I2C Module. +//! +//! This function will place the supplied data into I2C transmit data register +//! to start transmission. +//! +//! \param baseAddress is the base address of the I2C Slave module. +//! \param transmitData data to be transmitted from the I2C module +//! +//! Modified bits of \b UCBxTXBUF register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_I2C_slaveDataPut(uint16_t baseAddress, + uint8_t transmitData + ) +{ + //Send single byte data. + HWREG16(baseAddress + OFS_UCBxTXBUF) = transmitData; +} + +//***************************************************************************** +// +//! \brief Receives a byte that has been sent to the I2C Module. +//! +//! This function reads a byte of data from the I2C receive data Register. +//! +//! \param baseAddress is the base address of the I2C Slave module. +//! +//! \return Returns the byte received from by the I2C module, cast as an +//! uint8_t. +// +//***************************************************************************** +uint8_t EUSCI_I2C_slaveDataGet(uint16_t baseAddress) +{ + //Read a byte. + return HWREG16(baseAddress + OFS_UCBxRXBUF); +} + +//***************************************************************************** +// +//! \brief Indicates whether or not the I2C bus is busy. +//! +//! This function returns an indication of whether or not the I2C bus is busy. +//! This function checks the status of the bus via UCBBUSY bit in UCBxSTAT +//! register. +//! +//! \param baseAddress is the base address of the I2C module. +//! +//! \return One of the following: +//! - \b EUSCI_I2C_BUS_BUSY +//! - \b EUSCI_I2C_BUS_NOT_BUSY +//! \n indicating whether the bus is busy +// +//***************************************************************************** +uint16_t EUSCI_I2C_isBusBusy(uint16_t baseAddress) +{ + //Return the bus busy status. + return HWREG16(baseAddress + OFS_UCBxSTATW) & UCBBUSY; +} + +//***************************************************************************** +// +//! \brief Indicates whether STOP got sent. +//! +//! This function returns an indication of whether or not STOP got sent This +//! function checks the status of the bus via UCTXSTP bit in UCBxCTL1 register. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! +//! \return One of the following: +//! - \b EUSCI_I2C_STOP_SEND_COMPLETE +//! - \b EUSCI_I2C_SENDING_STOP +//! \n indicating whether the stop was sent +// +//***************************************************************************** +uint16_t EUSCI_I2C_masterIsStopSent(uint16_t baseAddress) +{ + return HWREG16(baseAddress + OFS_UCBxCTLW0) & UCTXSTP; +} + +//***************************************************************************** +// +//! \brief Indicates whether Start got sent. +//! +//! This function returns an indication of whether or not Start got sent This +//! function checks the status of the bus via UCTXSTT bit in UCBxCTL1 register. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! +//! \return One of the following: +//! - \b EUSCI_I2C_START_SEND_COMPLETE +//! - \b EUSCI_I2C_SENDING_START +//! \n indicating whether the start was sent +// +//***************************************************************************** +uint16_t EUSCI_I2C_masterIsStartSent(uint16_t baseAddress) +{ + return HWREG16(baseAddress + OFS_UCBxCTLW0) & UCTXSTT; +} + +//***************************************************************************** +// +//! \brief Enables individual I2C interrupt sources. +//! +//! Enables the indicated I2C interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! \param baseAddress is the base address of the I2C module. +//! \param mask is the bit mask of the interrupt sources to be enabled. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_I2C_NAK_INTERRUPT - Not-acknowledge interrupt +//! - \b EUSCI_I2C_ARBITRATIONLOST_INTERRUPT - Arbitration lost +//! interrupt +//! - \b EUSCI_I2C_STOP_INTERRUPT - STOP condition interrupt +//! - \b EUSCI_I2C_START_INTERRUPT - START condition interrupt +//! - \b EUSCI_I2C_TRANSMIT_INTERRUPT0 - Transmit interrupt0 +//! - \b EUSCI_I2C_TRANSMIT_INTERRUPT1 - Transmit interrupt1 +//! - \b EUSCI_I2C_TRANSMIT_INTERRUPT2 - Transmit interrupt2 +//! - \b EUSCI_I2C_TRANSMIT_INTERRUPT3 - Transmit interrupt3 +//! - \b EUSCI_I2C_RECEIVE_INTERRUPT0 - Receive interrupt0 +//! - \b EUSCI_I2C_RECEIVE_INTERRUPT1 - Receive interrupt1 +//! - \b EUSCI_I2C_RECEIVE_INTERRUPT2 - Receive interrupt2 +//! - \b EUSCI_I2C_RECEIVE_INTERRUPT3 - Receive interrupt3 +//! - \b EUSCI_I2C_BIT9_POSITION_INTERRUPT - Bit position 9 interrupt +//! - \b EUSCI_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT - Clock low timeout +//! interrupt enable +//! - \b EUSCI_I2C_BYTE_COUNTER_INTERRUPT - Byte counter interrupt +//! enable +//! +//! Modified bits of \b UCBxIE register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_I2C_enableInterrupt(uint16_t baseAddress, + uint16_t mask + ) +{ + assert( 0x00 == ( mask & ~(EUSCI_I2C_STOP_INTERRUPT + + EUSCI_I2C_START_INTERRUPT + + EUSCI_I2C_NAK_INTERRUPT + + EUSCI_I2C_ARBITRATIONLOST_INTERRUPT + + EUSCI_I2C_BIT9_POSITION_INTERRUPT + + EUSCI_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT + + EUSCI_I2C_BYTE_COUNTER_INTERRUPT + + EUSCI_I2C_TRANSMIT_INTERRUPT0 + + EUSCI_I2C_TRANSMIT_INTERRUPT1 + + EUSCI_I2C_TRANSMIT_INTERRUPT2 + + EUSCI_I2C_TRANSMIT_INTERRUPT3 + + EUSCI_I2C_RECEIVE_INTERRUPT0 + + EUSCI_I2C_RECEIVE_INTERRUPT1 + + EUSCI_I2C_RECEIVE_INTERRUPT2 + + EUSCI_I2C_RECEIVE_INTERRUPT3 + )) + ); + + //Enable the interrupt masked bit + HWREG16(baseAddress + OFS_UCBxIE) |= mask; +} + +//***************************************************************************** +// +//! \brief Disables individual I2C interrupt sources. +//! +//! Disables the indicated I2C interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! \param baseAddress is the base address of the I2C module. +//! \param mask is the bit mask of the interrupt sources to be disabled. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_I2C_NAK_INTERRUPT - Not-acknowledge interrupt +//! - \b EUSCI_I2C_ARBITRATIONLOST_INTERRUPT - Arbitration lost +//! interrupt +//! - \b EUSCI_I2C_STOP_INTERRUPT - STOP condition interrupt +//! - \b EUSCI_I2C_START_INTERRUPT - START condition interrupt +//! - \b EUSCI_I2C_TRANSMIT_INTERRUPT0 - Transmit interrupt0 +//! - \b EUSCI_I2C_TRANSMIT_INTERRUPT1 - Transmit interrupt1 +//! - \b EUSCI_I2C_TRANSMIT_INTERRUPT2 - Transmit interrupt2 +//! - \b EUSCI_I2C_TRANSMIT_INTERRUPT3 - Transmit interrupt3 +//! - \b EUSCI_I2C_RECEIVE_INTERRUPT0 - Receive interrupt0 +//! - \b EUSCI_I2C_RECEIVE_INTERRUPT1 - Receive interrupt1 +//! - \b EUSCI_I2C_RECEIVE_INTERRUPT2 - Receive interrupt2 +//! - \b EUSCI_I2C_RECEIVE_INTERRUPT3 - Receive interrupt3 +//! - \b EUSCI_I2C_BIT9_POSITION_INTERRUPT - Bit position 9 interrupt +//! - \b EUSCI_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT - Clock low timeout +//! interrupt enable +//! - \b EUSCI_I2C_BYTE_COUNTER_INTERRUPT - Byte counter interrupt +//! enable +//! +//! Modified bits of \b UCBxIE register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_I2C_disableInterrupt(uint16_t baseAddress, + uint16_t mask + ) +{ + assert( 0x00 == ( mask & ~(EUSCI_I2C_STOP_INTERRUPT + + EUSCI_I2C_START_INTERRUPT + + EUSCI_I2C_NAK_INTERRUPT + + EUSCI_I2C_ARBITRATIONLOST_INTERRUPT + + EUSCI_I2C_BIT9_POSITION_INTERRUPT + + EUSCI_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT + + EUSCI_I2C_BYTE_COUNTER_INTERRUPT + + EUSCI_I2C_TRANSMIT_INTERRUPT0 + + EUSCI_I2C_TRANSMIT_INTERRUPT1 + + EUSCI_I2C_TRANSMIT_INTERRUPT2 + + EUSCI_I2C_TRANSMIT_INTERRUPT3 + + EUSCI_I2C_RECEIVE_INTERRUPT0 + + EUSCI_I2C_RECEIVE_INTERRUPT1 + + EUSCI_I2C_RECEIVE_INTERRUPT2 + + EUSCI_I2C_RECEIVE_INTERRUPT3 + )) + ); + + //Disable the interrupt masked bit + HWREG16(baseAddress + OFS_UCBxIE) &= ~(mask); +} + +//***************************************************************************** +// +//! \brief Clears I2C interrupt sources. +//! +//! The I2C interrupt source is cleared, so that it no longer asserts. The +//! highest interrupt flag is automatically cleared when an interrupt vector +//! generator is used. +//! +//! \param baseAddress is the base address of the I2C module. +//! \param mask is a bit mask of the interrupt sources to be cleared. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_I2C_NAK_INTERRUPT - Not-acknowledge interrupt +//! - \b EUSCI_I2C_ARBITRATIONLOST_INTERRUPT - Arbitration lost +//! interrupt +//! - \b EUSCI_I2C_STOP_INTERRUPT - STOP condition interrupt +//! - \b EUSCI_I2C_START_INTERRUPT - START condition interrupt +//! - \b EUSCI_I2C_TRANSMIT_INTERRUPT0 - Transmit interrupt0 +//! - \b EUSCI_I2C_TRANSMIT_INTERRUPT1 - Transmit interrupt1 +//! - \b EUSCI_I2C_TRANSMIT_INTERRUPT2 - Transmit interrupt2 +//! - \b EUSCI_I2C_TRANSMIT_INTERRUPT3 - Transmit interrupt3 +//! - \b EUSCI_I2C_RECEIVE_INTERRUPT0 - Receive interrupt0 +//! - \b EUSCI_I2C_RECEIVE_INTERRUPT1 - Receive interrupt1 +//! - \b EUSCI_I2C_RECEIVE_INTERRUPT2 - Receive interrupt2 +//! - \b EUSCI_I2C_RECEIVE_INTERRUPT3 - Receive interrupt3 +//! - \b EUSCI_I2C_BIT9_POSITION_INTERRUPT - Bit position 9 interrupt +//! - \b EUSCI_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT - Clock low timeout +//! interrupt enable +//! - \b EUSCI_I2C_BYTE_COUNTER_INTERRUPT - Byte counter interrupt +//! enable +//! +//! Modified bits of \b UCBxIFG register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_I2C_clearInterruptFlag(uint16_t baseAddress, + uint16_t mask + ) +{ + assert( 0x00 == ( mask & ~(EUSCI_I2C_STOP_INTERRUPT + + EUSCI_I2C_START_INTERRUPT + + EUSCI_I2C_NAK_INTERRUPT + + EUSCI_I2C_ARBITRATIONLOST_INTERRUPT + + EUSCI_I2C_BIT9_POSITION_INTERRUPT + + EUSCI_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT + + EUSCI_I2C_BYTE_COUNTER_INTERRUPT + + EUSCI_I2C_TRANSMIT_INTERRUPT0 + + EUSCI_I2C_TRANSMIT_INTERRUPT1 + + EUSCI_I2C_TRANSMIT_INTERRUPT2 + + EUSCI_I2C_TRANSMIT_INTERRUPT3 + + EUSCI_I2C_RECEIVE_INTERRUPT0 + + EUSCI_I2C_RECEIVE_INTERRUPT1 + + EUSCI_I2C_RECEIVE_INTERRUPT2 + + EUSCI_I2C_RECEIVE_INTERRUPT3 + )) + ); + //Clear the I2C interrupt source. + HWREG16(baseAddress + OFS_UCBxIFG) &= ~(mask); +} + +//***************************************************************************** +// +//! \brief Gets the current I2C interrupt status. +//! +//! This returns the interrupt status for the I2C module based on which flag is +//! passed. +//! +//! \param baseAddress is the base address of the I2C module. +//! \param mask is the masked interrupt flag status to be returned. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_I2C_NAK_INTERRUPT - Not-acknowledge interrupt +//! - \b EUSCI_I2C_ARBITRATIONLOST_INTERRUPT - Arbitration lost +//! interrupt +//! - \b EUSCI_I2C_STOP_INTERRUPT - STOP condition interrupt +//! - \b EUSCI_I2C_START_INTERRUPT - START condition interrupt +//! - \b EUSCI_I2C_TRANSMIT_INTERRUPT0 - Transmit interrupt0 +//! - \b EUSCI_I2C_TRANSMIT_INTERRUPT1 - Transmit interrupt1 +//! - \b EUSCI_I2C_TRANSMIT_INTERRUPT2 - Transmit interrupt2 +//! - \b EUSCI_I2C_TRANSMIT_INTERRUPT3 - Transmit interrupt3 +//! - \b EUSCI_I2C_RECEIVE_INTERRUPT0 - Receive interrupt0 +//! - \b EUSCI_I2C_RECEIVE_INTERRUPT1 - Receive interrupt1 +//! - \b EUSCI_I2C_RECEIVE_INTERRUPT2 - Receive interrupt2 +//! - \b EUSCI_I2C_RECEIVE_INTERRUPT3 - Receive interrupt3 +//! - \b EUSCI_I2C_BIT9_POSITION_INTERRUPT - Bit position 9 interrupt +//! - \b EUSCI_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT - Clock low timeout +//! interrupt enable +//! - \b EUSCI_I2C_BYTE_COUNTER_INTERRUPT - Byte counter interrupt +//! enable +//! +//! \return Logical OR of any of the following: +//! - \b EUSCI_I2C_NAK_INTERRUPT Not-acknowledge interrupt +//! - \b EUSCI_I2C_ARBITRATIONLOST_INTERRUPT Arbitration lost interrupt +//! - \b EUSCI_I2C_STOP_INTERRUPT STOP condition interrupt +//! - \b EUSCI_I2C_START_INTERRUPT START condition interrupt +//! - \b EUSCI_I2C_TRANSMIT_INTERRUPT0 Transmit interrupt0 +//! - \b EUSCI_I2C_TRANSMIT_INTERRUPT1 Transmit interrupt1 +//! - \b EUSCI_I2C_TRANSMIT_INTERRUPT2 Transmit interrupt2 +//! - \b EUSCI_I2C_TRANSMIT_INTERRUPT3 Transmit interrupt3 +//! - \b EUSCI_I2C_RECEIVE_INTERRUPT0 Receive interrupt0 +//! - \b EUSCI_I2C_RECEIVE_INTERRUPT1 Receive interrupt1 +//! - \b EUSCI_I2C_RECEIVE_INTERRUPT2 Receive interrupt2 +//! - \b EUSCI_I2C_RECEIVE_INTERRUPT3 Receive interrupt3 +//! - \b EUSCI_I2C_BIT9_POSITION_INTERRUPT Bit position 9 interrupt +//! - \b EUSCI_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT Clock low timeout +//! interrupt enable +//! - \b EUSCI_I2C_BYTE_COUNTER_INTERRUPT Byte counter interrupt enable +//! \n indicating the status of the masked interrupts +// +//***************************************************************************** +uint16_t EUSCI_I2C_getInterruptStatus(uint16_t baseAddress, + uint16_t mask + ) +{ + assert( 0x00 == ( mask & ~(EUSCI_I2C_STOP_INTERRUPT + + EUSCI_I2C_START_INTERRUPT + + EUSCI_I2C_NAK_INTERRUPT + + EUSCI_I2C_ARBITRATIONLOST_INTERRUPT + + EUSCI_I2C_BIT9_POSITION_INTERRUPT + + EUSCI_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT + + EUSCI_I2C_BYTE_COUNTER_INTERRUPT + + EUSCI_I2C_TRANSMIT_INTERRUPT0 + + EUSCI_I2C_TRANSMIT_INTERRUPT1 + + EUSCI_I2C_TRANSMIT_INTERRUPT2 + + EUSCI_I2C_TRANSMIT_INTERRUPT3 + + EUSCI_I2C_RECEIVE_INTERRUPT0 + + EUSCI_I2C_RECEIVE_INTERRUPT1 + + EUSCI_I2C_RECEIVE_INTERRUPT2 + + EUSCI_I2C_RECEIVE_INTERRUPT3 + )) + ); + //Return the interrupt status of the request masked bit. + return HWREG16(baseAddress + OFS_UCBxIFG) & mask; +} + +//***************************************************************************** +// +//! \brief Does single byte transmission from Master to Slave +//! +//! This function is used by the Master module to send a single byte. This +//! function sends a start, then transmits the byte to the slave and then sends +//! a stop. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param txData is the data byte to be transmitted +//! +//! Modified bits of \b UCBxTXBUF register, bits of \b UCBxCTLW0 register, bits +//! of \b UCBxIE register and bits of \b UCBxIFG register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_I2C_masterSendSingleByte(uint16_t baseAddress, + uint8_t txData + ) +{ + //Store current TXIE status + uint16_t txieStatus = HWREG16(baseAddress + OFS_UCBxIE) & UCTXIE; + + //Disable transmit interrupt enable + HWREG16(baseAddress + OFS_UCBxIE) &= ~(UCTXIE); + + //Send start condition. + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTR + UCTXSTT; + + //Poll for transmit interrupt flag. + while (!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) ; + + //Send single byte data. + HWREG16(baseAddress + OFS_UCBxTXBUF) = txData; + + //Poll for transmit interrupt flag. + while (!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) ; + + //Send stop condition. + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTXSTP; + + //Clear transmit interrupt flag before enabling interrupt again + HWREG16(baseAddress + OFS_UCBxIFG) &= ~(UCTXIFG); + + //Reinstate transmit interrupt enable + HWREG16(baseAddress + OFS_UCBxIE) |= txieStatus; +} + +//***************************************************************************** +// +//! \brief Does single byte reception from Slave +//! +//! This function is used by the Master module to receive a single byte. This +//! function sends start and stop, waits for data reception and then receives +//! the data from the slave +//! +//! \param baseAddress is the base address of the I2C Master module. +//! +//! Modified bits of \b UCBxTXBUF register, bits of \b UCBxCTLW0 register, bits +//! of \b UCBxIE register and bits of \b UCBxIFG register. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the transmission process. +// +//***************************************************************************** +uint8_t EUSCI_I2C_masterReceiveSingleByte(uint16_t baseAddress) +{ + //Set USCI in Receive mode + HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~UCTR; + //Send start + HWREG16(baseAddress + OFS_UCBxCTLW0) |= (UCTXSTT + UCTXSTP); + + //Poll for receive interrupt flag. + while (!(HWREG16(baseAddress + OFS_UCBxIFG) & UCRXIFG)) ; + + //Send single byte data. + return HWREG16(baseAddress + OFS_UCBxRXBUF); +} + +//***************************************************************************** +// +//! \brief Does single byte transmission from Master to Slave with timeout +//! +//! This function is used by the Master module to send a single byte. This +//! function sends a start, then transmits the byte to the slave and then sends +//! a stop. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param txData is the data byte to be transmitted +//! \param timeout is the amount of time to wait until giving up +//! +//! Modified bits of \b UCBxTXBUF register, bits of \b UCBxCTLW0 register, bits +//! of \b UCBxIE register and bits of \b UCBxIFG register. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the transmission process. +// +//***************************************************************************** +bool EUSCI_I2C_masterSendSingleByteWithTimeout(uint16_t baseAddress, + uint8_t txData, + uint32_t timeout + ) +{ + assert(timeout > 0); + + // Creating variable for second timeout scenario + uint32_t timeout2 = timeout; + + //Store current TXIE status + uint16_t txieStatus = HWREG16(baseAddress + OFS_UCBxIE) & UCTXIE; + + //Disable transmit interrupt enable + HWREG16(baseAddress + OFS_UCBxIE) &= ~(UCTXIE); + + //Send start condition. + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTR + UCTXSTT; + + //Poll for transmit interrupt flag. + while ((!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) && --timeout) ; + + //Check if transfer timed out + if (timeout == 0) + return STATUS_FAIL; + + //Send single byte data. + HWREG16(baseAddress + OFS_UCBxTXBUF) = txData; + + //Poll for transmit interrupt flag. + while ((!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) && --timeout2) ; + + //Check if transfer timed out + if (timeout2 == 0) + return STATUS_FAIL; + + //Send stop condition. + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTXSTP; + + //Clear transmit interrupt flag before enabling interrupt again + HWREG16(baseAddress + OFS_UCBxIFG) &= ~(UCTXIFG); + + //Reinstate transmit interrupt enable + HWREG16(baseAddress + OFS_UCBxIE) |= txieStatus; + + return STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! \brief Starts multi-byte transmission from Master to Slave +//! +//! This function is used by the master module to start a multi byte +//! transaction. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param txData is the first data byte to be transmitted +//! +//! Modified bits of \b UCBxTXBUF register, bits of \b UCBxCTLW0 register, bits +//! of \b UCBxIE register and bits of \b UCBxIFG register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_I2C_masterMultiByteSendStart(uint16_t baseAddress, + uint8_t txData + ) +{ + //Store current transmit interrupt enable + uint16_t txieStatus = HWREG16(baseAddress + OFS_UCBxIE) & UCTXIE; + + //Disable transmit interrupt enable + HWREG16(baseAddress + OFS_UCBxIE) &= ~(UCTXIE); + + //Send start condition. + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTR + UCTXSTT; + + //Poll for transmit interrupt flag. + while (!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) ; + + //Send single byte data. + HWREG16(baseAddress + OFS_UCBxTXBUF) = txData; + + //Reinstate transmit interrupt enable + HWREG16(baseAddress + OFS_UCBxIE) |= txieStatus; +} + +//***************************************************************************** +// +//! \brief Starts multi-byte transmission from Master to Slave with timeout +//! +//! This function is used by the master module to start a multi byte +//! transaction. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param txData is the first data byte to be transmitted +//! \param timeout is the amount of time to wait until giving up +//! +//! Modified bits of \b UCBxTXBUF register, bits of \b UCBxCTLW0 register, bits +//! of \b UCBxIE register and bits of \b UCBxIFG register. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the transmission process. +// +//***************************************************************************** +bool EUSCI_I2C_masterMultiByteSendStartWithTimeout(uint16_t baseAddress, + uint8_t txData, + uint32_t timeout + ) +{ + assert(timeout > 0); + + //Store current transmit interrupt enable + uint16_t txieStatus = HWREG16(baseAddress + OFS_UCBxIE) & UCTXIE; + + //Disable transmit interrupt enable + HWREG16(baseAddress + OFS_UCBxIE) &= ~(UCTXIE); + + //Send start condition. + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTR + UCTXSTT; + + //Poll for transmit interrupt flag. + while ((!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) && --timeout) ; + + //Check if transfer timed out + if (timeout == 0) + return STATUS_FAIL; + + //Send single byte data. + HWREG16(baseAddress + OFS_UCBxTXBUF) = txData; + + //Reinstate transmit interrupt enable + HWREG16(baseAddress + OFS_UCBxIE) |= txieStatus; + + return STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! \brief Continues multi-byte transmission from Master to Slave +//! +//! This function is used by the Master module continue each byte of a multi- +//! byte transmission. This function transmits each data byte of a multi-byte +//! transmission to the slave. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param txData is the next data byte to be transmitted +//! +//! Modified bits of \b UCBxTXBUF register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_I2C_masterMultiByteSendNext(uint16_t baseAddress, + uint8_t txData + ) +{ + //If interrupts are not used, poll for flags + if (!(HWREG16(baseAddress + OFS_UCBxIE) & UCTXIE)) + //Poll for transmit interrupt flag. + while (!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) ; + + //Send single byte data. + HWREG16(baseAddress + OFS_UCBxTXBUF) = txData; +} + +//***************************************************************************** +// +//! \brief Continues multi-byte transmission from Master to Slave with timeout +//! +//! This function is used by the Master module continue each byte of a multi- +//! byte transmission. This function transmits each data byte of a multi-byte +//! transmission to the slave. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param txData is the next data byte to be transmitted +//! \param timeout is the amount of time to wait until giving up +//! +//! Modified bits of \b UCBxTXBUF register. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the transmission process. +// +//***************************************************************************** +bool EUSCI_I2C_masterMultiByteSendNextWithTimeout(uint16_t baseAddress, + uint8_t txData, + uint32_t timeout + ) +{ + assert(timeout > 0); + + //If interrupts are not used, poll for flags + if (!(HWREG16(baseAddress + OFS_UCBxIE) & UCTXIE)) { + //Poll for transmit interrupt flag. + while ((!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) && --timeout) ; + + //Check if transfer timed out + if (timeout == 0) + return STATUS_FAIL; + } + + //Send single byte data. + HWREG16(baseAddress + OFS_UCBxTXBUF) = txData; + + return STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! \brief Finishes multi-byte transmission from Master to Slave +//! +//! This function is used by the Master module to send the last byte and STOP. +//! This function transmits the last data byte of a multi-byte transmission to +//! the slave and then sends a stop. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param txData is the last data byte to be transmitted in a multi-byte +//! transmission +//! +//! Modified bits of \b UCBxTXBUF register and bits of \b UCBxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_I2C_masterMultiByteSendFinish(uint16_t baseAddress, + uint8_t txData + ) +{ + //If interrupts are not used, poll for flags + if (!(HWREG16(baseAddress + OFS_UCBxIE) & UCTXIE)) + //Poll for transmit interrupt flag. + while (!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) ; + + //Send single byte data. + HWREG16(baseAddress + OFS_UCBxTXBUF) = txData; + + //Poll for transmit interrupt flag. + while (!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) ; + + //Send stop condition. + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTXSTP; +} + +//***************************************************************************** +// +//! \brief Finishes multi-byte transmission from Master to Slave with timeout +//! +//! This function is used by the Master module to send the last byte and STOP. +//! This function transmits the last data byte of a multi-byte transmission to +//! the slave and then sends a stop. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param txData is the last data byte to be transmitted in a multi-byte +//! transmission +//! \param timeout is the amount of time to wait until giving up +//! +//! Modified bits of \b UCBxTXBUF register and bits of \b UCBxCTLW0 register. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the transmission process. +// +//***************************************************************************** +bool EUSCI_I2C_masterMultiByteSendFinishWithTimeout(uint16_t baseAddress, + uint8_t txData, + uint32_t timeout + ) +{ + uint32_t timeout2 = timeout; + + assert(timeout > 0); + + //If interrupts are not used, poll for flags + if (!(HWREG16(baseAddress + OFS_UCBxIE) & UCTXIE)) { + //Poll for transmit interrupt flag. + while ((!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) && --timeout) ; + + //Check if transfer timed out + if (timeout == 0) + return STATUS_FAIL; + } + + //Send single byte data. + HWREG16(baseAddress + OFS_UCBxTXBUF) = txData; + + //Poll for transmit interrupt flag. + while ((!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) && --timeout2) ; + + //Check if transfer timed out + if (timeout2 == 0) + return STATUS_FAIL; + + //Send stop condition. + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTXSTP; + + return STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! \brief This function is used by the Master module to initiate START +//! +//! This function is used by the Master module to initiate START +//! +//! \param baseAddress is the base address of the I2C Master module. +//! +//! Modified bits are \b UCTXSTT of \b UCBxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_I2C_masterSendStart(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTXSTT; +} + +//***************************************************************************** +// +//! \brief Send STOP byte at the end of a multi-byte transmission from Master +//! to Slave +//! +//! This function is used by the Master module send STOP at the end of a multi- +//! byte transmission. This function sends a stop after current transmission is +//! complete. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! +//! Modified bits are \b UCTXSTP of \b UCBxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_I2C_masterMultiByteSendStop(uint16_t baseAddress) +{ + //If interrupts are not used, poll for flags + if (!(HWREG16(baseAddress + OFS_UCBxIE) & UCTXIE)) + //Poll for transmit interrupt flag. + while (!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) ; + + //Send stop condition. + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTXSTP; +} + +//***************************************************************************** +// +//! \brief Send STOP byte at the end of a multi-byte transmission from Master +//! to Slave with timeout +//! +//! This function is used by the Master module send STOP at the end of a multi- +//! byte transmission. This function sends a stop after current transmission is +//! complete. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param timeout is the amount of time to wait until giving up +//! +//! Modified bits are \b UCTXSTP of \b UCBxCTLW0 register. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the transmission process. +// +//***************************************************************************** +bool EUSCI_I2C_masterMultiByteSendStopWithTimeout(uint16_t baseAddress, + uint32_t timeout) +{ + assert(timeout > 0); + + //If interrupts are not used, poll for flags + if (!(HWREG16(baseAddress + OFS_UCBxIE) & UCTXIE)) { + //Poll for transmit interrupt flag. + while ((!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) && --timeout) ; + + //Check if transfer timed out + if (timeout == 0) + return STATUS_FAIL; + } + + //Send stop condition. + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTXSTP; + + return STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! \brief Starts reception at the Master end +//! +//! This function is used by the Master module initiate reception of a single +//! byte. This function sends a start. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! +//! Modified bits are \b UCTXSTT of \b UCBxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_I2C_masterReceiveStart(uint16_t baseAddress) +{ + //Set USCI in Receive mode + HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~UCTR; + //Send start + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTXSTT; +} + +//***************************************************************************** +// +//! \brief Starts multi-byte reception at the Master end one byte at a time +//! +//! This function is used by the Master module to receive each byte of a multi- +//! byte reception. This function reads currently received byte. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! +//! \return Received byte at Master end. +// +//***************************************************************************** +uint8_t EUSCI_I2C_masterMultiByteReceiveNext(uint16_t baseAddress) +{ + return HWREG16(baseAddress + OFS_UCBxRXBUF); +} + +//***************************************************************************** +// +//! \brief Finishes multi-byte reception at the Master end +//! +//! This function is used by the Master module to initiate completion of a +//! multi-byte reception. This function receives the current byte and initiates +//! the STOP from master to slave. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! +//! Modified bits are \b UCTXSTP of \b UCBxCTLW0 register. +//! +//! \return Received byte at Master end. +// +//***************************************************************************** +uint8_t EUSCI_I2C_masterMultiByteReceiveFinish(uint16_t baseAddress) +{ + //Send stop condition. + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTXSTP; + + //Wait for Stop to finish + while (HWREG16(baseAddress + OFS_UCBxCTLW0) & UCTXSTP) + + // Wait for RX buffer + while (!(HWREG16(baseAddress + OFS_UCBxIFG) & UCRXIFG)) ; + + //Capture data from receive buffer after setting stop bit due to + //MSP430 I2C critical timing. + return HWREG16(baseAddress + OFS_UCBxRXBUF); +} + +//***************************************************************************** +// +//! \brief Finishes multi-byte reception at the Master end with timeout +//! +//! This function is used by the Master module to initiate completion of a +//! multi-byte reception. This function receives the current byte and initiates +//! the STOP from master to slave. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param txData is a pointer to the location to store the received byte at +//! master end +//! \param timeout is the amount of time to wait until giving up +//! +//! Modified bits are \b UCTXSTP of \b UCBxCTLW0 register. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the reception process +// +//***************************************************************************** +bool EUSCI_I2C_masterMultiByteReceiveFinishWithTimeout(uint16_t baseAddress, + uint8_t *txData, + uint32_t timeout + ) +{ + assert(timeout > 0); + + uint32_t timeout2 = timeout; + + //Send stop condition. + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTXSTP; + + //Wait for Stop to finish + while ((HWREG16(baseAddress + OFS_UCBxCTLW0) & UCTXSTP) && --timeout) ; + + //Check if transfer timed out + if (timeout == 0) + return STATUS_FAIL; + + // Wait for RX buffer + while ((!(HWREG16(baseAddress + OFS_UCBxIFG) & UCRXIFG)) && --timeout2) ; + + //Check if transfer timed out + if (timeout2 == 0) + return STATUS_FAIL; + + //Capture data from receive buffer after setting stop bit due to + //MSP430 I2C critical timing. + *txData = (HWREG8(baseAddress + OFS_UCBxRXBUF)); + + return STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! \brief Sends the STOP at the end of a multi-byte reception at the Master +//! end +//! +//! This function is used by the Master module to initiate STOP +//! +//! \param baseAddress is the base address of the I2C Master module. +//! +//! Modified bits are \b UCTXSTP of \b UCBxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_I2C_masterMultiByteReceiveStop(uint16_t baseAddress) +{ + //Send stop condition. + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTXSTP; +} + +//***************************************************************************** +// +//! \brief Enables Multi Master Mode +//! +//! At the end of this function, the I2C module is still disabled till +//! EUSCI_I2C_enable is invoked +//! +//! \param baseAddress is the base address of the I2C module. +//! +//! Modified bits are \b UCSWRST and \b UCMM of \b UCBxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_I2C_enableMultiMasterMode(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCSWRST; + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCMM; +} + +//***************************************************************************** +// +//! \brief Disables Multi Master Mode +//! +//! At the end of this function, the I2C module is still disabled till +//! EUSCI_I2C_enable is invoked +//! +//! \param baseAddress is the base address of the I2C module. +//! +//! Modified bits are \b UCSWRST and \b UCMM of \b UCBxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_I2C_disableMultiMasterMode(uint16_t baseAddress) +{ + + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCSWRST; + HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~UCMM; +} + +//***************************************************************************** +// +//! \brief receives a byte that has been sent to the I2C Master Module. +//! +//! This function reads a byte of data from the I2C receive data Register. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! +//! \return Returns the byte received from by the I2C module, cast as an +//! uint8_t. +// +//***************************************************************************** +uint8_t EUSCI_I2C_masterSingleReceive(uint16_t baseAddress) +{ + //Polling RXIFG0 if RXIE is not enabled + if (!(HWREG16(baseAddress + OFS_UCBxIE) & UCRXIE0)) + while (!(HWREG16(baseAddress + OFS_UCBxIFG) & UCRXIFG0)) ; + + //Read a byte. + return HWREG16(baseAddress + OFS_UCBxRXBUF); +} + +//***************************************************************************** +// +//! \brief Returns the address of the RX Buffer of the I2C for the DMA module. +//! +//! Returns the address of the I2C RX Buffer. This can be used in conjunction +//! with the DMA to store the received data directly to memory. +//! +//! \param baseAddress is the base address of the I2C module. +//! +//! \return The address of the I2C RX Buffer +// +//***************************************************************************** +uint32_t EUSCI_I2C_getReceiveBufferAddress(uint16_t baseAddress) +{ + return baseAddress + OFS_UCBxRXBUF; +} + +//***************************************************************************** +// +//! \brief Returns the address of the TX Buffer of the I2C for the DMA module. +//! +//! Returns the address of the I2C TX Buffer. This can be used in conjunction +//! with the DMA to obtain transmitted data directly from memory. +//! +//! \param baseAddress is the base address of the I2C module. +//! +//! \return The address of the I2C TX Buffer +// +//***************************************************************************** +uint32_t EUSCI_I2C_getTransmitBufferAddress(uint16_t baseAddress) +{ + return baseAddress + OFS_UCBxTXBUF; +} + +#endif +//***************************************************************************** +// +//! Close the doxygen group for eusci_i2c_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/eusci_i2c.h b/source/driverlib/MSP430F5xx_6xx/eusci_i2c.h new file mode 100644 index 0000000..f629378 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/eusci_i2c.h @@ -0,0 +1,344 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// eusci_i2c.h - Driver for the EUSCI_I2C Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_EUSCI_I2C_H__ +#define __MSP430WARE_EUSCI_I2C_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_EUSCI_Bx__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//****************************************************************************** +// +// The following is a struct that is passed to EUSCI_I2C_initMaster() +// +//****************************************************************************** +typedef struct EUSCI_I2C_initMasterParam { + uint8_t selectClockSource; + uint32_t i2cClk; + uint32_t dataRate; + uint8_t byteCounterThreshold; + uint8_t autoSTOPGeneration; +} EUSCI_I2C_initMasterParam; + +//****************************************************************************** +// +// The following is a struct that is passed to EUSCI_I2C_initSlave() +// +//****************************************************************************** +typedef struct EUSCI_I2C_initSlaveParam { + uint8_t slaveAddress; + uint8_t slaveAddressOffset; + uint32_t slaveOwnAddressEnable; +} EUSCI_I2C_initSlaveParam; + +//***************************************************************************** +// +// The following are values that can be passed to the autoSTOPGeneration +// parameter for functions: EUSCI_I2C_masterInit(). +// +//***************************************************************************** +#define EUSCI_I2C_NO_AUTO_STOP UCASTP_0 +#define EUSCI_I2C_SET_BYTECOUNT_THRESHOLD_FLAG UCASTP_1 +#define EUSCI_I2C_SEND_STOP_AUTOMATICALLY_ON_BYTECOUNT_THRESHOLD UCASTP_2 + +//***************************************************************************** +// +// The following are values that can be passed to the dataRate parameter for +// functions: EUSCI_I2C_masterInit(). +// +//***************************************************************************** +#define EUSCI_I2C_SET_DATA_RATE_400KBPS 400000 +#define EUSCI_I2C_SET_DATA_RATE_100KBPS 100000 + +//***************************************************************************** +// +// The following are values that can be passed to the selectClockSource +// parameter for functions: EUSCI_I2C_masterInit(). +// +//***************************************************************************** +#define EUSCI_I2C_CLOCKSOURCE_ACLK UCSSEL__ACLK +#define EUSCI_I2C_CLOCKSOURCE_SMCLK UCSSEL__SMCLK + +//***************************************************************************** +// +// The following are values that can be passed to the slaveAddressOffset +// parameter for functions: EUSCI_I2C_slaveInit(). +// +//***************************************************************************** +#define EUSCI_I2C_OWN_ADDRESS_OFFSET0 0x00 +#define EUSCI_I2C_OWN_ADDRESS_OFFSET1 0x02 +#define EUSCI_I2C_OWN_ADDRESS_OFFSET2 0x04 +#define EUSCI_I2C_OWN_ADDRESS_OFFSET3 0x06 + +//***************************************************************************** +// +// The following are values that can be passed to the slaveOwnAddressEnable +// parameter for functions: EUSCI_I2C_slaveInit(). +// +//***************************************************************************** +#define EUSCI_I2C_OWN_ADDRESS_DISABLE 0x00 +#define EUSCI_I2C_OWN_ADDRESS_ENABLE UCOAEN + +//***************************************************************************** +// +// The following are values that can be passed to the mode parameter for +// functions: EUSCI_I2C_setMode() as well as returned by the +// EUSCI_I2C_getMode() function. +// +//***************************************************************************** +#define EUSCI_I2C_TRANSMIT_MODE UCTR +#define EUSCI_I2C_RECEIVE_MODE 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the mask parameter for +// functions: EUSCI_I2C_enableInterrupt(), EUSCI_I2C_disableInterrupt(), +// EUSCI_I2C_clearInterruptFlag(), and EUSCI_I2C_getInterruptStatus() as well +// as returned by the EUSCI_I2C_getInterruptStatus() function. +// +//***************************************************************************** +#define EUSCI_I2C_NAK_INTERRUPT UCNACKIE +#define EUSCI_I2C_ARBITRATIONLOST_INTERRUPT UCALIE +#define EUSCI_I2C_STOP_INTERRUPT UCSTPIE +#define EUSCI_I2C_START_INTERRUPT UCSTTIE +#define EUSCI_I2C_TRANSMIT_INTERRUPT0 UCTXIE0 +#define EUSCI_I2C_TRANSMIT_INTERRUPT1 UCTXIE1 +#define EUSCI_I2C_TRANSMIT_INTERRUPT2 UCTXIE2 +#define EUSCI_I2C_TRANSMIT_INTERRUPT3 UCTXIE3 +#define EUSCI_I2C_RECEIVE_INTERRUPT0 UCRXIE0 +#define EUSCI_I2C_RECEIVE_INTERRUPT1 UCRXIE1 +#define EUSCI_I2C_RECEIVE_INTERRUPT2 UCRXIE2 +#define EUSCI_I2C_RECEIVE_INTERRUPT3 UCRXIE3 +#define EUSCI_I2C_BIT9_POSITION_INTERRUPT UCBIT9IE +#define EUSCI_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT UCCLTOIE +#define EUSCI_I2C_BYTE_COUNTER_INTERRUPT UCBCNTIE + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the EUSCI_I2C_isBusBusy() function. +// +//***************************************************************************** +#define EUSCI_I2C_BUS_BUSY UCBBUSY +#define EUSCI_I2C_BUS_NOT_BUSY 0x00 + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the EUSCI_I2C_masterIsStopSent() function. +// +//***************************************************************************** +#define EUSCI_I2C_STOP_SEND_COMPLETE 0x00 +#define EUSCI_I2C_SENDING_STOP UCTXSTP + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the EUSCI_I2C_masterIsStartSent() function. +// +//***************************************************************************** +#define EUSCI_I2C_START_SEND_COMPLETE 0x00 +#define EUSCI_I2C_SENDING_START UCTXSTT + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void EUSCI_I2C_initMaster(uint16_t baseAddress, + EUSCI_I2C_initMasterParam *param); + +extern void EUSCI_I2C_initSlave(uint16_t baseAddress, + EUSCI_I2C_initSlaveParam *param); + +extern void EUSCI_I2C_enable(uint16_t baseAddress); + +extern void EUSCI_I2C_disable(uint16_t baseAddress); + +extern void EUSCI_I2C_setSlaveAddress(uint16_t baseAddress, + uint8_t slaveAddress); + +extern void EUSCI_I2C_setMode(uint16_t baseAddress, + uint8_t mode); + +extern uint8_t EUSCI_I2C_getMode(uint16_t baseAddress); + +extern void EUSCI_I2C_slaveDataPut(uint16_t baseAddress, + uint8_t transmitData); + +extern uint8_t EUSCI_I2C_slaveDataGet(uint16_t baseAddress); + +extern uint16_t EUSCI_I2C_isBusBusy(uint16_t baseAddress); + +extern uint16_t EUSCI_I2C_masterIsStopSent(uint16_t baseAddress); + +extern uint16_t EUSCI_I2C_masterIsStartSent(uint16_t baseAddress); + +extern void EUSCI_I2C_enableInterrupt(uint16_t baseAddress, + uint16_t mask); + +extern void EUSCI_I2C_disableInterrupt(uint16_t baseAddress, + uint16_t mask); + +extern void EUSCI_I2C_clearInterruptFlag(uint16_t baseAddress, + uint16_t mask); + +extern uint16_t EUSCI_I2C_getInterruptStatus(uint16_t baseAddress, + uint16_t mask); + +extern void EUSCI_I2C_masterSendSingleByte(uint16_t baseAddress, + uint8_t txData); + +extern uint8_t EUSCI_I2C_masterReceiveSingleByte(uint16_t baseAddress); + +extern bool EUSCI_I2C_masterSendSingleByteWithTimeout(uint16_t baseAddress, + uint8_t txData, + uint32_t timeout); + +extern void EUSCI_I2C_masterMultiByteSendStart(uint16_t baseAddress, + uint8_t txData); + +extern bool EUSCI_I2C_masterMultiByteSendStartWithTimeout(uint16_t baseAddress, + uint8_t txData, + uint32_t timeout); + +extern void EUSCI_I2C_masterMultiByteSendNext(uint16_t baseAddress, + uint8_t txData); + +extern bool EUSCI_I2C_masterMultiByteSendNextWithTimeout(uint16_t baseAddress, + uint8_t txData, + uint32_t timeout); + +extern void EUSCI_I2C_masterMultiByteSendFinish(uint16_t baseAddress, + uint8_t txData); + +extern bool EUSCI_I2C_masterMultiByteSendFinishWithTimeout(uint16_t baseAddress, + uint8_t txData, + uint32_t timeout); + +extern void EUSCI_I2C_masterSendStart(uint16_t baseAddress); + +extern void EUSCI_I2C_masterMultiByteSendStop(uint16_t baseAddress); + +extern bool EUSCI_I2C_masterMultiByteSendStopWithTimeout(uint16_t baseAddress, + uint32_t timeout); + +extern void EUSCI_I2C_masterReceiveStart(uint16_t baseAddress); + +extern uint8_t EUSCI_I2C_masterMultiByteReceiveNext(uint16_t baseAddress); + +extern uint8_t EUSCI_I2C_masterMultiByteReceiveFinish(uint16_t baseAddress); + +extern bool EUSCI_I2C_masterMultiByteReceiveFinishWithTimeout(uint16_t baseAddress, + uint8_t *txData, + uint32_t timeout); + +extern void EUSCI_I2C_masterMultiByteReceiveStop(uint16_t baseAddress); + +extern void EUSCI_I2C_enableMultiMasterMode(uint16_t baseAddress); + +extern void EUSCI_I2C_disableMultiMasterMode(uint16_t baseAddress); + +extern uint8_t EUSCI_I2C_masterSingleReceive(uint16_t baseAddress); + +extern uint32_t EUSCI_I2C_getReceiveBufferAddress(uint16_t baseAddress); + +extern uint32_t EUSCI_I2C_getTransmitBufferAddress(uint16_t baseAddress); + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +#define EUSCI_I2C_getTransmitBufferAddressForDMA \ + EUSCI_I2C_getTransmitBufferAddress + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +#define EUSCI_I2C_getReceiveBufferAddressForDMA \ + EUSCI_I2C_getReceiveBufferAddress + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +#define EUSCI_I2C_masterIsSTOPSent EUSCI_I2C_masterIsStopSent + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +extern void EUSCI_I2C_masterInit(uint16_t baseAddress, + uint8_t selectClockSource, + uint32_t i2cClk, + uint32_t dataRate, + uint8_t byteCounterThreshold, + uint8_t autoSTOPGeneration); + +extern void EUSCI_I2C_slaveInit(uint16_t baseAddress, + uint8_t slaveAddress, + uint8_t slaveAddressOffset, + uint32_t slaveOwnAddressEnable); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_EUSCI_I2C_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/eusci_spi.c b/source/driverlib/MSP430F5xx_6xx/eusci_spi.c new file mode 100644 index 0000000..e9fbab8 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/eusci_spi.c @@ -0,0 +1,691 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// eusci_spi.c - Driver for the eusci_spi Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup eusci_spi_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_EUSCI_Ax__ +#include "eusci_spi.h" + +#include + +//***************************************************************************** +// +//! \brief DEPRECATED - Initializes the SPI Master block. +//! +//! Upon successful initialization of the SPI master block, this function will +//! have set the bus speed for the master, but the SPI Master block still +//! remains disabled and must be enabled with EUSCI_SPI_enable() +//! +//! \param baseAddress is the base address of the EUSCI_SPI Master module. +//! \param selectClockSource selects Clock source. +//! Valid values are: +//! - \b EUSCI_SPI_CLOCKSOURCE_ACLK +//! - \b EUSCI_SPI_CLOCKSOURCE_SMCLK +//! \param clockSourceFrequency is the frequency of the selected clock source +//! \param desiredSpiClock is the desired clock rate for SPI communication +//! \param msbFirst controls the direction of the receive and transmit shift +//! register. +//! Valid values are: +//! - \b EUSCI_SPI_MSB_FIRST +//! - \b EUSCI_SPI_LSB_FIRST [Default] +//! \param clockPhase is clock phase select. +//! Valid values are: +//! - \b EUSCI_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT [Default] +//! - \b EUSCI_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT +//! \param clockPolarity is clock polarity select +//! Valid values are: +//! - \b EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_HIGH +//! - \b EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default] +//! \param spiMode is SPI mode select +//! Valid values are: +//! - \b EUSCI_SPI_3PIN +//! - \b EUSCI_SPI_4PIN_UCxSTE_ACTIVE_HIGH +//! - \b EUSCI_SPI_4PIN_UCxSTE_ACTIVE_LOW +//! +//! Modified bits are \b UCCKPH, \b UCCKPL, \b UC7BIT, \b UCMSB, \b UCSSELx and +//! \b UCSWRST of \b UCAxCTLW0 register. +//! +//! \return STATUS_SUCCESS +// +//***************************************************************************** +void EUSCI_SPI_masterInit(uint16_t baseAddress, + uint8_t selectClockSource, + uint32_t clockSourceFrequency, + uint32_t desiredSpiClock, + uint16_t msbFirst, + uint16_t clockPhase, + uint16_t clockPolarity, + uint16_t spiMode + ) +{ + EUSCI_SPI_initMasterParam param = { 0 }; + + param.selectClockSource = selectClockSource; + param.clockSourceFrequency = clockSourceFrequency; + param.desiredSpiClock = desiredSpiClock; + param.msbFirst = msbFirst; + param.clockPhase = clockPhase; + param.clockPolarity = clockPolarity; + param.spiMode = spiMode; + + EUSCI_SPI_initMaster(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Initializes the SPI Master block. +//! +//! Upon successful initialization of the SPI master block, this function will +//! have set the bus speed for the master, but the SPI Master block still +//! remains disabled and must be enabled with EUSCI_SPI_enable() +//! +//! \param baseAddress is the base address of the EUSCI_SPI Master module. +//! \param param is the pointer to struct for master initialization. +//! +//! Modified bits are \b UCCKPH, \b UCCKPL, \b UC7BIT, \b UCMSB, \b UCSSELx and +//! \b UCSWRST of \b UCAxCTLW0 register. +//! +//! \return STATUS_SUCCESS +// +//***************************************************************************** +void EUSCI_SPI_initMaster(uint16_t baseAddress, + EUSCI_SPI_initMasterParam *param) +{ + assert(param != 0); + + assert( + (EUSCI_SPI_CLOCKSOURCE_ACLK == param->selectClockSource) || + (EUSCI_SPI_CLOCKSOURCE_SMCLK == param->selectClockSource) + ); + + assert((EUSCI_SPI_MSB_FIRST == param->msbFirst) || + (EUSCI_SPI_LSB_FIRST == param->msbFirst) + ); + + assert((EUSCI_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT == param->clockPhase) || + (EUSCI_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT == param->clockPhase) + ); + + assert((EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == param->clockPolarity) || + (EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_LOW == param->clockPolarity) + ); + + assert( + (EUSCI_SPI_3PIN == param->spiMode) || + (EUSCI_SPI_4PIN_UCxSTE_ACTIVE_HIGH == param->spiMode) || + (EUSCI_SPI_4PIN_UCxSTE_ACTIVE_LOW == param->spiMode) + ); + + //Disable the USCI Module + HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCSWRST; + + //Reset OFS_UCAxCTLW0 values + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCCKPH + UCCKPL + UC7BIT + UCMSB + + UCMST + UCMODE_3 + UCSYNC); + + //Reset OFS_UCAxCTLW0 values + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCSSEL_3); + + //Select Clock + HWREG16(baseAddress + OFS_UCAxCTLW0) |= param->selectClockSource; + + HWREG16(baseAddress + OFS_UCAxBRW) = + (uint16_t)(param->clockSourceFrequency / param->desiredSpiClock); + + /* + * Configure as SPI master mode. + * Clock phase select, polarity, msb + * UCMST = Master mode + * UCSYNC = Synchronous mode + * UCMODE_0 = 3-pin SPI + */ + HWREG16(baseAddress + OFS_UCAxCTLW0) |= ( + param->msbFirst + + param->clockPhase + + param->clockPolarity + + UCMST + + UCSYNC + + param->spiMode + ); + //No modulation + HWREG16(baseAddress + OFS_UCAxMCTLW) = 0; +} + +//***************************************************************************** +// +//! \brief Selects 4Pin Functionality +//! +//! This function should be invoked only in 4-wire mode. Invoking this function +//! has no effect in 3-wire mode. +//! +//! \param baseAddress is the base address of the EUSCI_SPI module. +//! \param select4PinFunctionality selects 4 pin functionality +//! Valid values are: +//! - \b EUSCI_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS +//! - \b EUSCI_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE +//! +//! Modified bits are \b UCSTEM of \b UCAxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_SPI_select4PinFunctionality(uint16_t baseAddress, + uint8_t select4PinFunctionality + ) +{ + assert( (EUSCI_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS == select4PinFunctionality) || + (EUSCI_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE == select4PinFunctionality) + ); + + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCSTEM; + HWREG16(baseAddress + OFS_UCAxCTLW0) |= select4PinFunctionality; +} + +//***************************************************************************** +// +//! \brief DEPRECATED - Initializes the SPI Master clock. At the end of this +//! function call, SPI module is left enabled. +//! +//! \param baseAddress is the base address of the EUSCI_SPI module. +//! \param clockSourceFrequency is the frequency of the selected clock source +//! \param desiredSpiClock is the desired clock rate for SPI communication +//! +//! Modified bits are \b UCSWRST of \b UCAxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_SPI_masterChangeClock(uint16_t baseAddress, + uint32_t clockSourceFrequency, + uint32_t desiredSpiClock + ) +{ + EUSCI_SPI_changeMasterClockParam param = { 0 }; + + param.clockSourceFrequency = clockSourceFrequency; + param.desiredSpiClock = desiredSpiClock; + EUSCI_SPI_changeMasterClock(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Initializes the SPI Master clock. At the end of this function call, +//! SPI module is left enabled. +//! +//! \param baseAddress is the base address of the EUSCI_SPI module. +//! \param param is the pointer to struct for master clock setting. +//! +//! Modified bits are \b UCSWRST of \b UCAxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_SPI_changeMasterClock(uint16_t baseAddress, + EUSCI_SPI_changeMasterClockParam *param) +{ + assert(param != 0); + + //Disable the USCI Module + HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCSWRST; + + HWREG16(baseAddress + OFS_UCAxBRW) = + (uint16_t)(param->clockSourceFrequency / param->desiredSpiClock); + + //Reset the UCSWRST bit to enable the USCI Module + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCSWRST); +} +//***************************************************************************** +// +//! \brief DEPRECATED - Initializes the SPI Slave block. +//! +//! Upon successful initialization of the SPI slave block, this function will +//! have initialized the slave block, but the SPI Slave block still remains +//! disabled and must be enabled with EUSCI_SPI_enable() +//! +//! \param baseAddress is the base address of the EUSCI_SPI Slave module. +//! \param msbFirst controls the direction of the receive and transmit shift +//! register. +//! Valid values are: +//! - \b EUSCI_SPI_MSB_FIRST +//! - \b EUSCI_SPI_LSB_FIRST [Default] +//! \param clockPhase is clock phase select. +//! Valid values are: +//! - \b EUSCI_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT [Default] +//! - \b EUSCI_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT +//! \param clockPolarity is clock polarity select +//! Valid values are: +//! - \b EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_HIGH +//! - \b EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default] +//! \param spiMode is SPI mode select +//! Valid values are: +//! - \b EUSCI_SPI_3PIN +//! - \b EUSCI_SPI_4PIN_UCxSTE_ACTIVE_HIGH +//! - \b EUSCI_SPI_4PIN_UCxSTE_ACTIVE_LOW +//! +//! Modified bits are \b UCMSB, \b UCMST, \b UC7BIT, \b UCCKPL, \b UCCKPH, \b +//! UCMODE and \b UCSWRST of \b UCAxCTLW0 register. +//! +//! \return STATUS_SUCCESS +// +//***************************************************************************** +void EUSCI_SPI_slaveInit(uint16_t baseAddress, + uint16_t msbFirst, + uint16_t clockPhase, + uint16_t clockPolarity, + uint16_t spiMode + ) +{ + EUSCI_SPI_initSlaveParam param = { 0 }; + + param.msbFirst = msbFirst; + param.clockPhase = clockPhase; + param.clockPolarity = clockPolarity; + param.spiMode = spiMode; + + EUSCI_SPI_initSlave(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Initializes the SPI Slave block. +//! +//! Upon successful initialization of the SPI slave block, this function will +//! have initialized the slave block, but the SPI Slave block still remains +//! disabled and must be enabled with EUSCI_SPI_enable() +//! +//! \param baseAddress is the base address of the EUSCI_SPI Slave module. +//! \param param is the pointer to struct for slave initialization. +//! +//! Modified bits are \b UCMSB, \b UCMST, \b UC7BIT, \b UCCKPL, \b UCCKPH, \b +//! UCMODE and \b UCSWRST of \b UCAxCTLW0 register. +//! +//! \return STATUS_SUCCESS +// +//***************************************************************************** +void EUSCI_SPI_initSlave(uint16_t baseAddress, EUSCI_SPI_initSlaveParam *param) +{ + assert(param != 0); + + assert( + (EUSCI_SPI_MSB_FIRST == param->msbFirst) || + (EUSCI_SPI_LSB_FIRST == param->msbFirst) + ); + + assert( + (EUSCI_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT == param->clockPhase) || + (EUSCI_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT == param->clockPhase) + ); + + assert( + (EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == param->clockPolarity) || + (EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_LOW == param->clockPolarity) + ); + + assert( + (EUSCI_SPI_3PIN == param->spiMode) || + (EUSCI_SPI_4PIN_UCxSTE_ACTIVE_HIGH == param->spiMode) || + (EUSCI_SPI_4PIN_UCxSTE_ACTIVE_LOW == param->spiMode) + ); + + //Disable USCI Module + HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCSWRST; + + //Reset OFS_UCAxCTLW0 register + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCMSB + + UC7BIT + + UCMST + + UCCKPL + + UCCKPH + + UCMODE_3 + ); + + //Clock polarity, phase select, msbFirst, SYNC, Mode0 + HWREG16(baseAddress + OFS_UCAxCTLW0) |= (param->clockPhase + + param->clockPolarity + + param->msbFirst + + UCSYNC + + param->spiMode + ); +} + +//***************************************************************************** +// +//! \brief Changes the SPI clock phase and polarity. At the end of this +//! function call, SPI module is left enabled. +//! +//! \param baseAddress is the base address of the EUSCI_SPI module. +//! \param clockPhase is clock phase select. +//! Valid values are: +//! - \b EUSCI_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT [Default] +//! - \b EUSCI_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT +//! \param clockPolarity is clock polarity select +//! Valid values are: +//! - \b EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_HIGH +//! - \b EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default] +//! +//! Modified bits are \b UCCKPL, \b UCCKPH and \b UCSWRST of \b UCAxCTLW0 +//! register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_SPI_changeClockPhasePolarity(uint16_t baseAddress, + uint16_t clockPhase, + uint16_t clockPolarity + ) +{ + + assert( (EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == clockPolarity) || + (EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_LOW == clockPolarity) + ); + + assert( (EUSCI_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT == clockPhase) || + (EUSCI_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT == clockPhase) + ); + + //Disable the USCI Module + HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCSWRST; + + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCCKPH + UCCKPL); + + HWREG16(baseAddress + OFS_UCAxCTLW0) |= ( + clockPhase + + clockPolarity + ); + + //Reset the UCSWRST bit to enable the USCI Module + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCSWRST); +} + +//***************************************************************************** +// +//! \brief Transmits a byte from the SPI Module. +//! +//! This function will place the supplied data into SPI transmit data register +//! to start transmission. +//! +//! \param baseAddress is the base address of the EUSCI_SPI module. +//! \param transmitData data to be transmitted from the SPI module +//! +//! \return None +// +//***************************************************************************** +void EUSCI_SPI_transmitData( uint16_t baseAddress, + uint8_t transmitData + ) +{ + HWREG16(baseAddress + OFS_UCAxTXBUF) = transmitData; +} + +//***************************************************************************** +// +//! \brief Receives a byte that has been sent to the SPI Module. +//! +//! This function reads a byte of data from the SPI receive data Register. +//! +//! \param baseAddress is the base address of the EUSCI_SPI module. +//! +//! \return Returns the byte received from by the SPI module, cast as an +//! uint8_t. +// +//***************************************************************************** +uint8_t EUSCI_SPI_receiveData(uint16_t baseAddress) +{ + return HWREG16(baseAddress + OFS_UCAxRXBUF); +} + +//***************************************************************************** +// +//! \brief Enables individual SPI interrupt sources. +//! +//! Enables the indicated SPI interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. Does not clear interrupt flags. +//! +//! \param baseAddress is the base address of the EUSCI_SPI module. +//! \param mask is the bit mask of the interrupt sources to be enabled. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_SPI_TRANSMIT_INTERRUPT +//! - \b EUSCI_SPI_RECEIVE_INTERRUPT +//! +//! Modified bits of \b UCAxIFG register and bits of \b UCAxIE register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_SPI_enableInterrupt(uint16_t baseAddress, + uint8_t mask + ) +{ + assert(!(mask & ~(EUSCI_SPI_RECEIVE_INTERRUPT + | EUSCI_SPI_TRANSMIT_INTERRUPT))); + + HWREG16(baseAddress + OFS_UCAxIE) |= mask; +} + +//***************************************************************************** +// +//! \brief Disables individual SPI interrupt sources. +//! +//! Disables the indicated SPI interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! \param baseAddress is the base address of the EUSCI_SPI module. +//! \param mask is the bit mask of the interrupt sources to be disabled. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_SPI_TRANSMIT_INTERRUPT +//! - \b EUSCI_SPI_RECEIVE_INTERRUPT +//! +//! Modified bits of \b UCAxIE register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_SPI_disableInterrupt(uint16_t baseAddress, + uint8_t mask + ) +{ + assert(!(mask & ~(EUSCI_SPI_RECEIVE_INTERRUPT + | EUSCI_SPI_TRANSMIT_INTERRUPT))); + + HWREG16(baseAddress + OFS_UCAxIE) &= ~mask; +} + +//***************************************************************************** +// +//! \brief Gets the current SPI interrupt status. +//! +//! This returns the interrupt status for the SPI module based on which flag is +//! passed. +//! +//! \param baseAddress is the base address of the EUSCI_SPI module. +//! \param mask is the masked interrupt flag status to be returned. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_SPI_TRANSMIT_INTERRUPT +//! - \b EUSCI_SPI_RECEIVE_INTERRUPT +//! +//! \return Logical OR of any of the following: +//! - \b EUSCI_SPI_TRANSMIT_INTERRUPT +//! - \b EUSCI_SPI_RECEIVE_INTERRUPT +//! \n indicating the status of the masked interrupts +// +//***************************************************************************** +uint8_t EUSCI_SPI_getInterruptStatus(uint16_t baseAddress, + uint8_t mask + ) +{ + assert(!(mask & ~(EUSCI_SPI_RECEIVE_INTERRUPT + | EUSCI_SPI_TRANSMIT_INTERRUPT))); + + return HWREG16(baseAddress + OFS_UCAxIFG) & mask; +} + +//***************************************************************************** +// +//! \brief Clears the selected SPI interrupt status flag. +//! +//! \param baseAddress is the base address of the EUSCI_SPI module. +//! \param mask is the masked interrupt flag to be cleared. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_SPI_TRANSMIT_INTERRUPT +//! - \b EUSCI_SPI_RECEIVE_INTERRUPT +//! +//! Modified bits of \b UCAxIFG register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_SPI_clearInterruptFlag(uint16_t baseAddress, + uint8_t mask + ) +{ + assert(!(mask & ~(EUSCI_SPI_RECEIVE_INTERRUPT + | EUSCI_SPI_TRANSMIT_INTERRUPT))); + + HWREG16(baseAddress + OFS_UCAxIFG) &= ~mask; +} + +//***************************************************************************** +// +//! \brief Enables the SPI block. +//! +//! This will enable operation of the SPI block. +//! +//! \param baseAddress is the base address of the EUSCI_SPI module. +//! +//! Modified bits are \b UCSWRST of \b UCAxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_SPI_enable(uint16_t baseAddress) +{ + //Reset the UCSWRST bit to enable the USCI Module + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCSWRST); +} + +//***************************************************************************** +// +//! \brief Disables the SPI block. +//! +//! This will disable operation of the SPI block. +//! +//! \param baseAddress is the base address of the EUSCI_SPI module. +//! +//! Modified bits are \b UCSWRST of \b UCAxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_SPI_disable(uint16_t baseAddress) +{ + //Set the UCSWRST bit to disable the USCI Module + HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCSWRST; +} + +//***************************************************************************** +// +//! \brief Returns the address of the RX Buffer of the SPI for the DMA module. +//! +//! Returns the address of the SPI RX Buffer. This can be used in conjunction +//! with the DMA to store the received data directly to memory. +//! +//! \param baseAddress is the base address of the EUSCI_SPI module. +//! +//! \return the address of the RX Buffer +// +//***************************************************************************** +uint32_t EUSCI_SPI_getReceiveBufferAddress(uint16_t baseAddress) +{ + return baseAddress + OFS_UCAxRXBUF; +} + +//***************************************************************************** +// +//! \brief Returns the address of the TX Buffer of the SPI for the DMA module. +//! +//! Returns the address of the SPI TX Buffer. This can be used in conjunction +//! with the DMA to obtain transmitted data directly from memory. +//! +//! \param baseAddress is the base address of the EUSCI_SPI module. +//! +//! \return the address of the TX Buffer +// +//***************************************************************************** +uint32_t EUSCI_SPI_getTransmitBufferAddress(uint16_t baseAddress) +{ + return baseAddress + OFS_UCAxTXBUF; +} + +//***************************************************************************** +// +//! \brief Indicates whether or not the SPI bus is busy. +//! +//! This function returns an indication of whether or not the SPI bus is +//! busy.This function checks the status of the bus via UCBBUSY bit +//! +//! \param baseAddress is the base address of the EUSCI_SPI module. +//! +//! \return One of the following: +//! - \b EUSCI_SPI_BUSY +//! - \b EUSCI_SPI_NOT_BUSY +//! \n indicating if the EUSCI_SPI is busy +// +//***************************************************************************** +uint16_t EUSCI_SPI_isBusy(uint16_t baseAddress) +{ + //Return the bus busy status. + return HWREG16(baseAddress + OFS_UCAxSTATW) & UCBUSY; +} + + +#endif +//***************************************************************************** +// +//! Close the doxygen group for eusci_spi_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/eusci_spi.h b/source/driverlib/MSP430F5xx_6xx/eusci_spi.h new file mode 100644 index 0000000..bf648f1 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/eusci_spi.h @@ -0,0 +1,268 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// eusci_spi.h - Driver for the EUSCI_SPI Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_EUSCI_SPI_H__ +#define __MSP430WARE_EUSCI_SPI_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_EUSCI_Ax__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//****************************************************************************** +// +// The following is a struct that is passed to EUSCI_SPI_initMaster() +// +//****************************************************************************** +typedef struct EUSCI_SPI_initMasterParam { + uint8_t selectClockSource; + uint32_t clockSourceFrequency; + uint32_t desiredSpiClock; + uint16_t msbFirst; + uint16_t clockPhase; + uint16_t clockPolarity; + uint16_t spiMode; +} EUSCI_SPI_initMasterParam; + +//****************************************************************************** +// +// The following is a struct that is passed to EUSCI_SPI_initSlave() +// +//****************************************************************************** +typedef struct EUSCI_SPI_initSlaveParam { + uint16_t msbFirst; + uint16_t clockPhase; + uint16_t clockPolarity; + uint16_t spiMode; +} EUSCI_SPI_initSlaveParam; + +//****************************************************************************** +// +// The following is a struct that is passed to EUSCI_SPI_changeMasterParam() +// +//****************************************************************************** +typedef struct EUSCI_SPI_changeMasterClockParam { + uint32_t clockSourceFrequency; + uint32_t desiredSpiClock; +} EUSCI_SPI_changeMasterClockParam; + +//***************************************************************************** +// +// The following are values that can be passed to the clockPhase parameter for +// functions: EUSCI_SPI_masterInit(), EUSCI_SPI_slaveInit(), and +// EUSCI_SPI_changeClockPhasePolarity(). +// +//***************************************************************************** +#define EUSCI_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT 0x00 +#define EUSCI_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT UCCKPH + +//***************************************************************************** +// +// The following are values that can be passed to the msbFirst parameter for +// functions: EUSCI_SPI_masterInit(), and EUSCI_SPI_slaveInit(). +// +//***************************************************************************** +#define EUSCI_SPI_MSB_FIRST UCMSB +#define EUSCI_SPI_LSB_FIRST 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the clockPolarity parameter +// for functions: EUSCI_SPI_masterInit(), EUSCI_SPI_slaveInit(), and +// EUSCI_SPI_changeClockPhasePolarity(). +// +//***************************************************************************** +#define EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_HIGH UCCKPL +#define EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_LOW 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the selectClockSource +// parameter for functions: EUSCI_SPI_masterInit(). +// +//***************************************************************************** +#define EUSCI_SPI_CLOCKSOURCE_ACLK UCSSEL__ACLK +#define EUSCI_SPI_CLOCKSOURCE_SMCLK UCSSEL__SMCLK + +//***************************************************************************** +// +// The following are values that can be passed to the spiMode parameter for +// functions: EUSCI_SPI_masterInit(), and EUSCI_SPI_slaveInit(). +// +//***************************************************************************** +#define EUSCI_SPI_3PIN UCMODE_0 +#define EUSCI_SPI_4PIN_UCxSTE_ACTIVE_HIGH UCMODE_1 +#define EUSCI_SPI_4PIN_UCxSTE_ACTIVE_LOW UCMODE_2 + +//***************************************************************************** +// +// The following are values that can be passed to the select4PinFunctionality +// parameter for functions: EUSCI_SPI_select4PinFunctionality(). +// +//***************************************************************************** +#define EUSCI_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS 0x00 +#define EUSCI_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE UCSTEM + +//***************************************************************************** +// +// The following are values that can be passed to the mask parameter for +// functions: EUSCI_SPI_enableInterrupt(), EUSCI_SPI_disableInterrupt(), +// EUSCI_SPI_getInterruptStatus(), and EUSCI_SPI_clearInterruptFlag() as well +// as returned by the EUSCI_SPI_getInterruptStatus() function. +// +//***************************************************************************** +#define EUSCI_SPI_TRANSMIT_INTERRUPT UCTXIE +#define EUSCI_SPI_RECEIVE_INTERRUPT UCRXIE + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the EUSCI_SPI_isBusy() function. +// +//***************************************************************************** +#define EUSCI_SPI_BUSY UCBUSY +#define EUSCI_SPI_NOT_BUSY 0x00 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void EUSCI_SPI_initMaster(uint16_t baseAddress, + EUSCI_SPI_initMasterParam *param); + +extern void EUSCI_SPI_select4PinFunctionality(uint16_t baseAddress, + uint8_t select4PinFunctionality); + +extern void EUSCI_SPI_changeMasterClock(uint16_t baseAddress, + EUSCI_SPI_changeMasterClockParam *param); + +extern void EUSCI_SPI_initSlave(uint16_t baseAddress, + EUSCI_SPI_initSlaveParam *param); + +extern void EUSCI_SPI_changeClockPhasePolarity(uint16_t baseAddress, + uint16_t clockPhase, + uint16_t clockPolarity); + +extern void EUSCI_SPI_transmitData(uint16_t baseAddress, + uint8_t transmitData); + +extern uint8_t EUSCI_SPI_receiveData(uint16_t baseAddress); + +extern void EUSCI_SPI_enableInterrupt(uint16_t baseAddress, + uint8_t mask); + +extern void EUSCI_SPI_disableInterrupt(uint16_t baseAddress, + uint8_t mask); + +extern uint8_t EUSCI_SPI_getInterruptStatus(uint16_t baseAddress, + uint8_t mask); + +extern void EUSCI_SPI_clearInterruptFlag(uint16_t baseAddress, + uint8_t mask); + +extern void EUSCI_SPI_enable(uint16_t baseAddress); + +extern void EUSCI_SPI_disable(uint16_t baseAddress); + +extern uint32_t EUSCI_SPI_getReceiveBufferAddress(uint16_t baseAddress); + +extern uint32_t EUSCI_SPI_getTransmitBufferAddress(uint16_t baseAddress); + +extern uint16_t EUSCI_SPI_isBusy(uint16_t baseAddress); + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +#define EUSCI_SPI_getTransmitBufferAddressForDMA \ + EUSCI_SPI_getTransmitBufferAddress + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +#define EUSCI_SPI_getReceiveBufferAddressForDMA \ + EUSCI_SPI_getReceiveBufferAddress + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +extern void EUSCI_SPI_masterInit(uint16_t baseAddress, + uint8_t selectClockSource, + uint32_t clockSourceFrequency, + uint32_t desiredSpiClock, + uint16_t msbFirst, + uint16_t clockPhase, + uint16_t clockPolarity, + uint16_t spiMode); + +extern void EUSCI_SPI_masterChangeClock(uint16_t baseAddress, + uint32_t clockSourceFrequency, + uint32_t desiredSpiClock); + +extern void EUSCI_SPI_slaveInit(uint16_t baseAddress, + uint16_t msbFirst, + uint16_t clockPhase, + uint16_t clockPolarity, + uint16_t spiMode); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_EUSCI_SPI_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/eusci_uart.c b/source/driverlib/MSP430F5xx_6xx/eusci_uart.c new file mode 100644 index 0000000..97ca8a4 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/eusci_uart.c @@ -0,0 +1,735 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// eusci_uart.c - Driver for the eusci_uart Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup eusci_uart_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_EUSCI_Ax__ +#include "eusci_uart.h" + +#include + +//***************************************************************************** +// +//! \brief DEPRECATED - Advanced initialization routine for the UART block. The +//! values to be written into the clockPrescalar, firstModReg, secondModReg and +//! overSampling parameters should be pre-computed and passed into the +//! initialization function. +//! +//! Upon successful initialization of the UART block, this function will have +//! initialized the module, but the UART block still remains disabled and must +//! be enabled with EUSCI_UART_enable(). To calculate values for +//! clockPrescalar, firstModReg, secondModReg and overSampling please use the +//! link below. +//! +//! http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSP430BaudRateConverter/index.html +//! +//! \param baseAddress is the base address of the EUSCI_UART module. +//! \param selectClockSource selects Clock source. +//! Valid values are: +//! - \b EUSCI_UART_CLOCKSOURCE_SMCLK +//! - \b EUSCI_UART_CLOCKSOURCE_ACLK +//! \param clockPrescalar is the value to be written into UCBRx bits +//! \param firstModReg is First modulation stage register setting. This value +//! is a pre-calculated value which can be obtained from the Device +//! Users Guide. This value is written into UCBRFx bits of UCAxMCTLW. +//! \param secondModReg is Second modulation stage register setting. This value +//! is a pre-calculated value which can be obtained from the Device +//! Users Guide. This value is written into UCBRSx bits of UCAxMCTLW. +//! \param parity is the desired parity. +//! Valid values are: +//! - \b EUSCI_UART_NO_PARITY [Default] +//! - \b EUSCI_UART_ODD_PARITY +//! - \b EUSCI_UART_EVEN_PARITY +//! \param msborLsbFirst controls direction of receive and transmit shift +//! register. +//! Valid values are: +//! - \b EUSCI_UART_MSB_FIRST +//! - \b EUSCI_UART_LSB_FIRST [Default] +//! \param numberofStopBits indicates one/two STOP bits +//! Valid values are: +//! - \b EUSCI_UART_ONE_STOP_BIT [Default] +//! - \b EUSCI_UART_TWO_STOP_BITS +//! \param uartMode selects the mode of operation +//! Valid values are: +//! - \b EUSCI_UART_MODE [Default] +//! - \b EUSCI_UART_IDLE_LINE_MULTI_PROCESSOR_MODE +//! - \b EUSCI_UART_ADDRESS_BIT_MULTI_PROCESSOR_MODE +//! - \b EUSCI_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE +//! \param overSampling indicates low frequency or oversampling baud generation +//! Valid values are: +//! - \b EUSCI_UART_OVERSAMPLING_BAUDRATE_GENERATION +//! - \b EUSCI_UART_LOW_FREQUENCY_BAUDRATE_GENERATION +//! +//! Modified bits are \b UCPEN, \b UCPAR, \b UCMSB, \b UC7BIT, \b UCSPB, \b +//! UCMODEx and \b UCSYNC of \b UCAxCTL0 register; bits \b UCSSELx and \b +//! UCSWRST of \b UCAxCTL1 register. +//! +//! \return STATUS_SUCCESS or STATUS_FAIL of the initialization process +// +//***************************************************************************** +bool EUSCI_UART_initAdvance( uint16_t baseAddress, + uint8_t selectClockSource, + uint16_t clockPrescalar, + uint8_t firstModReg, + uint8_t secondModReg, + uint8_t parity, + uint16_t msborLsbFirst, + uint16_t numberofStopBits, + uint16_t uartMode, + uint8_t overSampling + ) +{ + EUSCI_UART_initParam param = { 0 }; + + param.selectClockSource = selectClockSource; + param.clockPrescalar = clockPrescalar; + param.firstModReg = firstModReg; + param.secondModReg = secondModReg; + param.parity = parity; + param.msborLsbFirst = msborLsbFirst; + param.numberofStopBits = numberofStopBits; + param.uartMode = uartMode; + param.overSampling = overSampling; + + return EUSCI_UART_init(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Advanced initialization routine for the UART block. The values to be +//! written into the clockPrescalar, firstModReg, secondModReg and overSampling +//! parameters should be pre-computed and passed into the initialization +//! function. +//! +//! Upon successful initialization of the UART block, this function will have +//! initialized the module, but the UART block still remains disabled and must +//! be enabled with EUSCI_UART_enable(). To calculate values for +//! clockPrescalar, firstModReg, secondModReg and overSampling please use the +//! link below. +//! +//! http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSP430BaudRateConverter/index.html +//! +//! \param baseAddress is the base address of the EUSCI_UART module. +//! \param param is the pointer to struct for initialization. +//! +//! Modified bits are \b UCPEN, \b UCPAR, \b UCMSB, \b UC7BIT, \b UCSPB, \b +//! UCMODEx and \b UCSYNC of \b UCAxCTL0 register; bits \b UCSSELx and \b +//! UCSWRST of \b UCAxCTL1 register. +//! +//! \return STATUS_SUCCESS or STATUS_FAIL of the initialization process +// +//***************************************************************************** +bool EUSCI_UART_init(uint16_t baseAddress, EUSCI_UART_initParam *param) +{ + assert(param != 0); + + assert( + (EUSCI_UART_MODE == param->uartMode) || + (EUSCI_UART_IDLE_LINE_MULTI_PROCESSOR_MODE == param->uartMode) || + (EUSCI_UART_ADDRESS_BIT_MULTI_PROCESSOR_MODE == param->uartMode) || + (EUSCI_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE == param->uartMode) + ); + + assert( + (EUSCI_UART_CLOCKSOURCE_ACLK == param->selectClockSource) || + (EUSCI_UART_CLOCKSOURCE_SMCLK == param->selectClockSource) + ); + + assert( + (EUSCI_UART_MSB_FIRST == param->msborLsbFirst) || + (EUSCI_UART_LSB_FIRST == param->msborLsbFirst) + ); + + assert( + (EUSCI_UART_ONE_STOP_BIT == param->numberofStopBits) || + (EUSCI_UART_TWO_STOP_BITS == param->numberofStopBits) + ); + + assert( + (EUSCI_UART_NO_PARITY == param->parity) || + (EUSCI_UART_ODD_PARITY == param->parity) || + (EUSCI_UART_EVEN_PARITY == param->parity) + ); + + bool retVal = STATUS_SUCCESS; + + //Disable the USCI Module + HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCSWRST; + + //Clock source select + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCSSEL_3; + HWREG16(baseAddress + OFS_UCAxCTLW0) |= param->selectClockSource; + + //MSB, LSB select + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCMSB; + HWREG16(baseAddress + OFS_UCAxCTLW0) |= param->msborLsbFirst; + + //UCSPB = 0(1 stop bit) OR 1(2 stop bits) + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCSPB; + HWREG16(baseAddress + OFS_UCAxCTLW0) |= param->numberofStopBits; + + //Parity + switch (param->parity) { + case EUSCI_UART_NO_PARITY: + //No Parity + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCPEN; + break; + case EUSCI_UART_ODD_PARITY: + //Odd Parity + HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCPEN; + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCPAR; + break; + case EUSCI_UART_EVEN_PARITY: + //Even Parity + HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCPEN; + HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCPAR; + break; + } + + //BaudRate Control Register + HWREG16(baseAddress + OFS_UCAxBRW ) = param->clockPrescalar; + //Modulation Control Register + HWREG16(baseAddress + OFS_UCAxMCTLW) = ((param->secondModReg << 8) + + (param->firstModReg << 4) + param->overSampling ); + + //Asynchronous mode & 8 bit character select & clear mode + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCSYNC + + UC7BIT + + UCMODE_3 + ); + + //Configure UART mode. + HWREG16(baseAddress + OFS_UCAxCTLW0) |= param->uartMode; + + //Reset UCRXIE, UCBRKIE, UCDORM, UCTXADDR, UCTXBRK + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCRXEIE + UCBRKIE + UCDORM + + UCTXADDR + UCTXBRK + ); + + return retVal; +} +//***************************************************************************** +// +//! \brief Transmits a byte from the UART Module. +//! +//! This function will place the supplied data into UART transmit data register +//! to start transmission +//! +//! \param baseAddress is the base address of the EUSCI_UART module. +//! \param transmitData data to be transmitted from the UART module +//! +//! Modified bits of \b UCAxTXBUF register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_UART_transmitData( uint16_t baseAddress, + uint8_t transmitData + ) +{ + //If interrupts are not used, poll for flags + if (!(HWREG16(baseAddress + OFS_UCAxIE) & UCTXIE)) + //Poll for transmit interrupt flag + while (!(HWREG16(baseAddress + OFS_UCAxIFG) & UCTXIFG)) ; + + HWREG16(baseAddress + OFS_UCAxTXBUF) = transmitData; +} + +//***************************************************************************** +// +//! \brief Receives a byte that has been sent to the UART Module. +//! +//! This function reads a byte of data from the UART receive data Register. +//! +//! \param baseAddress is the base address of the EUSCI_UART module. +//! +//! Modified bits of \b UCAxRXBUF register. +//! +//! \return Returns the byte received from by the UART module, cast as an +//! uint8_t. +// +//***************************************************************************** +uint8_t EUSCI_UART_receiveData(uint16_t baseAddress) +{ + //If interrupts are not used, poll for flags + if (!(HWREG16(baseAddress + OFS_UCAxIE) & UCRXIE)) + //Poll for receive interrupt flag + while (!(HWREG16(baseAddress + OFS_UCAxIFG) & UCRXIFG)) ; + + return HWREG16(baseAddress + OFS_UCAxRXBUF); +} + +//***************************************************************************** +// +//! \brief Enables individual UART interrupt sources. +//! +//! Enables the indicated UART interrupt sources. The interrupt flag is first +//! and then the corresponding interrupt is enabled. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. Does not clear interrupt flags. +//! +//! \param baseAddress is the base address of the EUSCI_UART module. +//! \param mask is the bit mask of the interrupt sources to be enabled. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_UART_RECEIVE_INTERRUPT - Receive interrupt +//! - \b EUSCI_UART_TRANSMIT_INTERRUPT - Transmit interrupt +//! - \b EUSCI_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT - Receive erroneous- +//! character interrupt enable +//! - \b EUSCI_UART_BREAKCHAR_INTERRUPT - Receive break character +//! interrupt enable +//! - \b EUSCI_UART_STARTBIT_INTERRUPT - Start bit received interrupt +//! enable +//! - \b EUSCI_UART_TRANSMIT_COMPLETE_INTERRUPT - Transmit complete +//! interrupt enable +//! +//! Modified bits of \b UCAxCTL1 register and bits of \b UCAxIE register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_UART_enableInterrupt(uint16_t baseAddress, + uint8_t mask + ) +{ + assert(!(mask & ~(EUSCI_UART_RECEIVE_INTERRUPT + | EUSCI_UART_TRANSMIT_INTERRUPT + | EUSCI_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT + | EUSCI_UART_BREAKCHAR_INTERRUPT + | EUSCI_UART_STARTBIT_INTERRUPT + | EUSCI_UART_TRANSMIT_COMPLETE_INTERRUPT))); + + uint8_t locMask; + + locMask = (mask & (EUSCI_UART_RECEIVE_INTERRUPT + | EUSCI_UART_TRANSMIT_INTERRUPT + | EUSCI_UART_STARTBIT_INTERRUPT + | EUSCI_UART_TRANSMIT_COMPLETE_INTERRUPT)); + + HWREG16(baseAddress + OFS_UCAxIE) |= locMask; + + locMask = (mask & (EUSCI_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT + | EUSCI_UART_BREAKCHAR_INTERRUPT)); + HWREG16(baseAddress + OFS_UCAxCTLW0) |= locMask; + +} + +//***************************************************************************** +// +//! \brief Disables individual UART interrupt sources. +//! +//! Disables the indicated UART interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! \param baseAddress is the base address of the EUSCI_UART module. +//! \param mask is the bit mask of the interrupt sources to be disabled. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_UART_RECEIVE_INTERRUPT - Receive interrupt +//! - \b EUSCI_UART_TRANSMIT_INTERRUPT - Transmit interrupt +//! - \b EUSCI_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT - Receive erroneous- +//! character interrupt enable +//! - \b EUSCI_UART_BREAKCHAR_INTERRUPT - Receive break character +//! interrupt enable +//! - \b EUSCI_UART_STARTBIT_INTERRUPT - Start bit received interrupt +//! enable +//! - \b EUSCI_UART_TRANSMIT_COMPLETE_INTERRUPT - Transmit complete +//! interrupt enable +//! +//! Modified bits of \b UCAxCTL1 register and bits of \b UCAxIE register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_UART_disableInterrupt(uint16_t baseAddress, + uint8_t mask + ) +{ + assert(!(mask & ~(EUSCI_UART_RECEIVE_INTERRUPT + | EUSCI_UART_TRANSMIT_INTERRUPT + | EUSCI_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT + | EUSCI_UART_BREAKCHAR_INTERRUPT + | EUSCI_UART_STARTBIT_INTERRUPT + | EUSCI_UART_TRANSMIT_COMPLETE_INTERRUPT))); + + uint8_t locMask; + + locMask = (mask & (EUSCI_UART_RECEIVE_INTERRUPT + | EUSCI_UART_TRANSMIT_INTERRUPT + | EUSCI_UART_STARTBIT_INTERRUPT + | EUSCI_UART_TRANSMIT_COMPLETE_INTERRUPT)); + HWREG16(baseAddress + OFS_UCAxIE) &= ~locMask; + + + locMask = (mask & (EUSCI_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT + | EUSCI_UART_BREAKCHAR_INTERRUPT)); + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~locMask; +} + +//***************************************************************************** +// +//! \brief Gets the current UART interrupt status. +//! +//! This returns the interrupt status for the UART module based on which flag +//! is passed. +//! +//! \param baseAddress is the base address of the EUSCI_UART module. +//! \param mask is the masked interrupt flag status to be returned. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_UART_RECEIVE_INTERRUPT_FLAG +//! - \b EUSCI_UART_TRANSMIT_INTERRUPT_FLAG +//! - \b EUSCI_UART_STARTBIT_INTERRUPT_FLAG +//! - \b EUSCI_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG +//! +//! Modified bits of \b UCAxIFG register. +//! +//! \return Logical OR of any of the following: +//! - \b EUSCI_UART_RECEIVE_INTERRUPT_FLAG +//! - \b EUSCI_UART_TRANSMIT_INTERRUPT_FLAG +//! - \b EUSCI_UART_STARTBIT_INTERRUPT_FLAG +//! - \b EUSCI_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG +//! \n indicating the status of the masked flags +// +//***************************************************************************** +uint8_t EUSCI_UART_getInterruptStatus(uint16_t baseAddress, + uint8_t mask) +{ + assert(!(mask & ~(EUSCI_UART_RECEIVE_INTERRUPT_FLAG + | EUSCI_UART_TRANSMIT_INTERRUPT_FLAG + | EUSCI_UART_STARTBIT_INTERRUPT_FLAG + | EUSCI_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG))); + + return HWREG16(baseAddress + OFS_UCAxIFG) & mask; +} + +//***************************************************************************** +// +//! \brief Clears UART interrupt sources. +//! +//! The UART interrupt source is cleared, so that it no longer asserts. The +//! highest interrupt flag is automatically cleared when an interrupt vector +//! generator is used. +//! +//! \param baseAddress is the base address of the EUSCI_UART module. +//! \param mask is a bit mask of the interrupt sources to be cleared. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_UART_RECEIVE_INTERRUPT_FLAG +//! - \b EUSCI_UART_TRANSMIT_INTERRUPT_FLAG +//! - \b EUSCI_UART_STARTBIT_INTERRUPT_FLAG +//! - \b EUSCI_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG +//! +//! Modified bits of \b UCAxIFG register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_UART_clearInterruptFlag(uint16_t baseAddress, uint8_t mask) +{ + assert(!(mask & ~(EUSCI_UART_RECEIVE_INTERRUPT_FLAG + | EUSCI_UART_TRANSMIT_INTERRUPT_FLAG + | EUSCI_UART_STARTBIT_INTERRUPT_FLAG + | EUSCI_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG))); + + //Clear the UART interrupt source. + HWREG16(baseAddress + OFS_UCAxIFG) &= ~(mask); +} + +//***************************************************************************** +// +//! \brief Enables the UART block. +//! +//! This will enable operation of the UART block. +//! +//! \param baseAddress is the base address of the EUSCI_UART module. +//! +//! Modified bits are \b UCSWRST of \b UCAxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_UART_enable(uint16_t baseAddress) +{ + //Reset the UCSWRST bit to enable the USCI Module + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCSWRST); +} + +//***************************************************************************** +// +//! \brief Disables the UART block. +//! +//! This will disable operation of the UART block. +//! +//! \param baseAddress is the base address of the EUSCI_UART module. +//! +//! Modified bits are \b UCSWRST of \b UCAxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_UART_disable(uint16_t baseAddress) +{ + //Set the UCSWRST bit to disable the USCI Module + HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCSWRST; +} + +//***************************************************************************** +// +//! \brief Gets the current UART status flags. +//! +//! This returns the status for the UART module based on which flag is passed. +//! +//! \param baseAddress is the base address of the EUSCI_UART module. +//! \param mask is the masked interrupt flag status to be returned. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_UART_LISTEN_ENABLE +//! - \b EUSCI_UART_FRAMING_ERROR +//! - \b EUSCI_UART_OVERRUN_ERROR +//! - \b EUSCI_UART_PARITY_ERROR +//! - \b EUSCI_UART_BREAK_DETECT +//! - \b EUSCI_UART_RECEIVE_ERROR +//! - \b EUSCI_UART_ADDRESS_RECEIVED +//! - \b EUSCI_UART_IDLELINE +//! - \b EUSCI_UART_BUSY +//! +//! Modified bits of \b UCAxSTAT register. +//! +//! \return Logical OR of any of the following: +//! - \b EUSCI_UART_LISTEN_ENABLE +//! - \b EUSCI_UART_FRAMING_ERROR +//! - \b EUSCI_UART_OVERRUN_ERROR +//! - \b EUSCI_UART_PARITY_ERROR +//! - \b EUSCI_UART_BREAK_DETECT +//! - \b EUSCI_UART_RECEIVE_ERROR +//! - \b EUSCI_UART_ADDRESS_RECEIVED +//! - \b EUSCI_UART_IDLELINE +//! - \b EUSCI_UART_BUSY +//! \n indicating the status of the masked interrupt flags +// +//***************************************************************************** +uint8_t EUSCI_UART_queryStatusFlags(uint16_t baseAddress, + uint8_t mask) +{ + assert( 0x00 != mask && (EUSCI_UART_LISTEN_ENABLE + + EUSCI_UART_FRAMING_ERROR + + EUSCI_UART_OVERRUN_ERROR + + EUSCI_UART_PARITY_ERROR + + EUSCI_UART_BREAK_DETECT + + EUSCI_UART_RECEIVE_ERROR + + EUSCI_UART_ADDRESS_RECEIVED + + EUSCI_UART_IDLELINE + + EUSCI_UART_BUSY + )); + + return HWREG16(baseAddress + OFS_UCAxSTATW) & mask; +} + +//***************************************************************************** +// +//! \brief Sets the UART module in dormant mode +//! +//! Puts USCI in sleep mode Only characters that are preceded by an idle-line +//! or with address bit set UCRXIFG. In UART mode with automatic baud-rate +//! detection, only the combination of a break and sync field sets UCRXIFG. +//! +//! \param baseAddress is the base address of the EUSCI_UART module. +//! +//! Modified bits of \b UCAxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_UART_setDormant(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCDORM; +} + +//***************************************************************************** +// +//! \brief Re-enables UART module from dormant mode +//! +//! Not dormant. All received characters set UCRXIFG. +//! +//! \param baseAddress is the base address of the EUSCI_UART module. +//! +//! Modified bits are \b UCDORM of \b UCAxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_UART_resetDormant(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCDORM; +} + +//***************************************************************************** +// +//! \brief Transmits the next byte to be transmitted marked as address +//! depending on selected multiprocessor mode +//! +//! \param baseAddress is the base address of the EUSCI_UART module. +//! \param transmitAddress is the next byte to be transmitted +//! +//! Modified bits of \b UCAxTXBUF register and bits of \b UCAxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_UART_transmitAddress(uint16_t baseAddress, + uint8_t transmitAddress) +{ + //Set UCTXADDR bit + HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCTXADDR; + + //Place next byte to be sent into the transmit buffer + HWREG16(baseAddress + OFS_UCAxTXBUF) = transmitAddress; +} + +//***************************************************************************** +// +//! \brief Transmit break. +//! +//! Transmits a break with the next write to the transmit buffer. In UART mode +//! with automatic baud-rate detection, EUSCI_UART_AUTOMATICBAUDRATE_SYNC(0x55) +//! must be written into UCAxTXBUF to generate the required break/sync fields. +//! Otherwise, DEFAULT_SYNC(0x00) must be written into the transmit buffer. +//! Also ensures module is ready for transmitting the next data. +//! +//! \param baseAddress is the base address of the EUSCI_UART module. +//! +//! Modified bits of \b UCAxTXBUF register and bits of \b UCAxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void EUSCI_UART_transmitBreak(uint16_t baseAddress) +{ + //Set UCTXADDR bit + HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCTXBRK; + + //If current mode is automatic baud-rate detection + if (EUSCI_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE == + (HWREG16(baseAddress + OFS_UCAxCTLW0) & + EUSCI_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE)) + HWREG16(baseAddress + OFS_UCAxTXBUF) = EUSCI_UART_AUTOMATICBAUDRATE_SYNC; + else + HWREG16(baseAddress + OFS_UCAxTXBUF) = DEFAULT_SYNC; + + //If interrupts are not used, poll for flags + if (!(HWREG16(baseAddress + OFS_UCAxIE) & UCTXIE)) + //Poll for transmit interrupt flag + while (!(HWREG16(baseAddress + OFS_UCAxIFG) & UCTXIFG)) ; +} + +//***************************************************************************** +// +//! \brief Returns the address of the RX Buffer of the UART for the DMA module. +//! +//! Returns the address of the UART RX Buffer. This can be used in conjunction +//! with the DMA to store the received data directly to memory. +//! +//! \param baseAddress is the base address of the EUSCI_UART module. +//! +//! \return Address of RX Buffer +// +//***************************************************************************** +uint32_t EUSCI_UART_getReceiveBufferAddress(uint16_t baseAddress) +{ + return baseAddress + OFS_UCAxRXBUF; +} + +//***************************************************************************** +// +//! \brief Returns the address of the TX Buffer of the UART for the DMA module. +//! +//! Returns the address of the UART TX Buffer. This can be used in conjunction +//! with the DMA to obtain transmitted data directly from memory. +//! +//! \param baseAddress is the base address of the EUSCI_UART module. +//! +//! \return Address of TX Buffer +// +//***************************************************************************** +uint32_t EUSCI_UART_getTransmitBufferAddress(uint16_t baseAddress) +{ + return baseAddress + OFS_UCAxTXBUF; +} + +//***************************************************************************** +// +//! \brief Sets the deglitch time +//! +//! \param baseAddress is the base address of the EUSCI_UART module. +//! \param deglitchTime is the selected deglitch time +//! Valid values are: +//! - \b EUSCI_UART_DEGLITCH_TIME_2ns +//! - \b EUSCI_UART_DEGLITCH_TIME_50ns +//! - \b EUSCI_UART_DEGLITCH_TIME_100ns +//! - \b EUSCI_UART_DEGLITCH_TIME_200ns +//! +//! \return None +// +//***************************************************************************** +void EUSCI_UART_selectDeglitchTime(uint16_t baseAddress, + uint16_t deglitchTime + ) +{ + assert((EUSCI_UART_DEGLITCH_TIME_2ns == deglitchTime) || + (EUSCI_UART_DEGLITCH_TIME_50ns == deglitchTime) || + (EUSCI_UART_DEGLITCH_TIME_100ns == deglitchTime) || + (EUSCI_UART_DEGLITCH_TIME_200ns == deglitchTime) + ); + + HWREG16(baseAddress + OFS_UCAxCTLW1) &= ~(UCGLIT1 + UCGLIT0); + + HWREG16(baseAddress + OFS_UCAxCTLW1) |= deglitchTime; +} + + +#endif +//***************************************************************************** +// +//! Close the doxygen group for eusci_uart_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/eusci_uart.h b/source/driverlib/MSP430F5xx_6xx/eusci_uart.h new file mode 100644 index 0000000..0e1e021 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/eusci_uart.h @@ -0,0 +1,282 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// eusci_uart.h - Driver for the EUSCI_UART Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_EUSCI_UART_H__ +#define __MSP430WARE_EUSCI_UART_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_EUSCI_Ax__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//****************************************************************************** +// +// The following is a struct that is passed to EUSCI_UART_init() +// +//****************************************************************************** +typedef struct EUSCI_UART_initParam { + uint8_t selectClockSource; + uint16_t clockPrescalar; + uint8_t firstModReg; + uint8_t secondModReg; + uint8_t parity; + uint16_t msborLsbFirst; + uint16_t numberofStopBits; + uint16_t uartMode; + uint8_t overSampling; +} EUSCI_UART_initParam; + +//***************************************************************************** +// +// The following values are the sync characters possible. +// +//***************************************************************************** +#define DEFAULT_SYNC 0x00 +#define EUSCI_UART_AUTOMATICBAUDRATE_SYNC 0x55 + +//***************************************************************************** +// +// The following are values that can be passed to the parity parameter for +// functions: EUSCI_UART_initAdvance(). +// +//***************************************************************************** +#define EUSCI_UART_NO_PARITY 0x00 +#define EUSCI_UART_ODD_PARITY 0x01 +#define EUSCI_UART_EVEN_PARITY 0x02 + +//***************************************************************************** +// +// The following are values that can be passed to the msborLsbFirst parameter +// for functions: EUSCI_UART_initAdvance(). +// +//***************************************************************************** +#define EUSCI_UART_MSB_FIRST UCMSB +#define EUSCI_UART_LSB_FIRST 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the uartMode parameter for +// functions: EUSCI_UART_initAdvance(). +// +//***************************************************************************** +#define EUSCI_UART_MODE UCMODE_0 +#define EUSCI_UART_IDLE_LINE_MULTI_PROCESSOR_MODE UCMODE_1 +#define EUSCI_UART_ADDRESS_BIT_MULTI_PROCESSOR_MODE UCMODE_2 +#define EUSCI_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE UCMODE_3 + +//***************************************************************************** +// +// The following are values that can be passed to the selectClockSource +// parameter for functions: EUSCI_UART_initAdvance(). +// +//***************************************************************************** +#define EUSCI_UART_CLOCKSOURCE_SMCLK UCSSEL__SMCLK +#define EUSCI_UART_CLOCKSOURCE_ACLK UCSSEL__ACLK + +//***************************************************************************** +// +// The following are values that can be passed to the numberofStopBits +// parameter for functions: EUSCI_UART_initAdvance(). +// +//***************************************************************************** +#define EUSCI_UART_ONE_STOP_BIT 0x00 +#define EUSCI_UART_TWO_STOP_BITS UCSPB + +//***************************************************************************** +// +// The following are values that can be passed to the overSampling parameter +// for functions: EUSCI_UART_initAdvance(). +// +//***************************************************************************** +#define EUSCI_UART_OVERSAMPLING_BAUDRATE_GENERATION 0x01 +#define EUSCI_UART_LOW_FREQUENCY_BAUDRATE_GENERATION 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the mask parameter for +// functions: EUSCI_UART_enableInterrupt(), and EUSCI_UART_disableInterrupt(). +// +//***************************************************************************** +#define EUSCI_UART_RECEIVE_INTERRUPT UCRXIE +#define EUSCI_UART_TRANSMIT_INTERRUPT UCTXIE +#define EUSCI_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT UCRXEIE +#define EUSCI_UART_BREAKCHAR_INTERRUPT UCBRKIE +#define EUSCI_UART_STARTBIT_INTERRUPT UCSTTIE +#define EUSCI_UART_TRANSMIT_COMPLETE_INTERRUPT UCTXCPTIE + +//***************************************************************************** +// +// The following are values that can be passed to the mask parameter for +// functions: EUSCI_UART_getInterruptStatus(), and +// EUSCI_UART_clearInterruptFlag() as well as returned by the +// EUSCI_UART_getInterruptStatus() function. +// +//***************************************************************************** +#define EUSCI_UART_RECEIVE_INTERRUPT_FLAG UCRXIFG +#define EUSCI_UART_TRANSMIT_INTERRUPT_FLAG UCTXIFG +#define EUSCI_UART_STARTBIT_INTERRUPT_FLAG UCSTTIFG +#define EUSCI_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG UCTXCPTIFG + +//***************************************************************************** +// +// The following are values that can be passed to the mask parameter for +// functions: EUSCI_UART_queryStatusFlags() as well as returned by the +// EUSCI_UART_queryStatusFlags() function. +// +//***************************************************************************** +#define EUSCI_UART_LISTEN_ENABLE UCLISTEN +#define EUSCI_UART_FRAMING_ERROR UCFE +#define EUSCI_UART_OVERRUN_ERROR UCOE +#define EUSCI_UART_PARITY_ERROR UCPE +#define EUSCI_UART_BREAK_DETECT UCBRK +#define EUSCI_UART_RECEIVE_ERROR UCRXERR +#define EUSCI_UART_ADDRESS_RECEIVED UCADDR +#define EUSCI_UART_IDLELINE UCIDLE +#define EUSCI_UART_BUSY UCBUSY + +//***************************************************************************** +// +// The following are values that can be passed to the deglitchTime parameter +// for functions: EUSCI_UART_selectDeglitchTime(). +// +//***************************************************************************** +#define EUSCI_UART_DEGLITCH_TIME_2ns 0x00 +#define EUSCI_UART_DEGLITCH_TIME_50ns UCGLIT0 +#define EUSCI_UART_DEGLITCH_TIME_100ns UCGLIT1 +#define EUSCI_UART_DEGLITCH_TIME_200ns (UCGLIT0 + UCGLIT1) + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern bool EUSCI_UART_init(uint16_t baseAddress, + EUSCI_UART_initParam *param); + +extern void EUSCI_UART_transmitData(uint16_t baseAddress, + uint8_t transmitData); + +extern uint8_t EUSCI_UART_receiveData(uint16_t baseAddress); + +extern void EUSCI_UART_enableInterrupt(uint16_t baseAddress, + uint8_t mask); + +extern void EUSCI_UART_disableInterrupt(uint16_t baseAddress, + uint8_t mask); + +extern uint8_t EUSCI_UART_getInterruptStatus(uint16_t baseAddress, + uint8_t mask); + +extern void EUSCI_UART_clearInterruptFlag(uint16_t baseAddress, + uint8_t mask); + +extern void EUSCI_UART_enable(uint16_t baseAddress); + +extern void EUSCI_UART_disable(uint16_t baseAddress); + +extern uint8_t EUSCI_UART_queryStatusFlags(uint16_t baseAddress, + uint8_t mask); + +extern void EUSCI_UART_setDormant(uint16_t baseAddress); + +extern void EUSCI_UART_resetDormant(uint16_t baseAddress); + +extern void EUSCI_UART_transmitAddress(uint16_t baseAddress, + uint8_t transmitAddress); + +extern void EUSCI_UART_transmitBreak(uint16_t baseAddress); + +extern uint32_t EUSCI_UART_getReceiveBufferAddress(uint16_t baseAddress); + +extern uint32_t EUSCI_UART_getTransmitBufferAddress(uint16_t baseAddress); + +extern void EUSCI_UART_selectDeglitchTime(uint16_t baseAddress, + uint16_t deglitchTime); + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +#define EUSCI_UART_getTransmitBufferAddressForDMA \ + EUSCI_UART_getTransmitBufferAddress + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +#define EUSCI_UART_getReceiveBufferAddressForDMA \ + EUSCI_UART_getReceiveBufferAddress + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +extern bool EUSCI_UART_initAdvance(uint16_t baseAddress, + uint8_t selectClockSource, + uint16_t clockPrescalar, + uint8_t firstModReg, + uint8_t secondModReg, + uint8_t parity, + uint16_t msborLsbFirst, + uint16_t numberofStopBits, + uint16_t uartMode, + uint8_t overSampling); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_EUSCI_UART_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/flash.c b/source/driverlib/MSP430F5xx_6xx/flash.c new file mode 100644 index 0000000..0a96c34 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/flash.c @@ -0,0 +1,460 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// flash.c - Driver for the flash Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup flash_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifndef DRIVERLIB_LEGACY_MODE + +#ifdef __MSP430_HAS_FLASH__ +#include "flash.h" + +#include + +//***************************************************************************** +// +//! \brief Erase a single segment of the flash memory. +//! +//! For devices like MSP430i204x, if the specified segment is the information +//! flash segment, the FLASH_unlockInfo API must be called prior to calling +//! this API. +//! +//! \param flash_ptr is the pointer into the flash segment to be erased +//! +//! \return None +// +//***************************************************************************** +void FLASH_segmentErase( uint8_t *flash_ptr) +{ + //Clear Lock bit + HWREG16(FLASH_BASE + OFS_FCTL3) = FWKEY; + + //Set Erase bit + HWREG16(FLASH_BASE + OFS_FCTL1) = FWKEY + ERASE; + + //Dummy write to erase Flash seg + *flash_ptr = 0; + + //test busy + while (HWREG8(FLASH_BASE + OFS_FCTL3) & BUSY) ; + + //Clear ERASE bit + HWREG16(FLASH_BASE + OFS_FCTL1) = FWKEY; + + //Set LOCK bit + HWREG16(FLASH_BASE + OFS_FCTL3) = FWKEY + LOCK; +} + +//***************************************************************************** +// +//! \brief Erase a single bank of the flash memory. +//! +//! This function erases a single bank of the flash memory. This API will +//! erase the entire flash if device contains only one flash bank. +//! +//! \param flash_ptr is a pointer into the bank to be erased +//! +//! \return None +// +//***************************************************************************** +void FLASH_bankErase( uint8_t *flash_ptr) +{ + //Clear Lock bit + HWREG16(FLASH_BASE + OFS_FCTL3) = FWKEY; + + while (HWREG8(FLASH_BASE + OFS_FCTL3) & BUSY) ; + + //Set MERAS bit + HWREG16(FLASH_BASE + OFS_FCTL1) = FWKEY + MERAS; + + //Dummy write to erase Flash seg + *flash_ptr = 0; + + //test busy + while (HWREG8(FLASH_BASE + OFS_FCTL3) & BUSY) ; + + //Clear MERAS bit + HWREG16(FLASH_BASE + OFS_FCTL1) = FWKEY; + + //Set LOCK bit + HWREG16(FLASH_BASE + OFS_FCTL3) = FWKEY + LOCK; +} + +//***************************************************************************** +// +//! \brief Erase all flash memory. +//! +//! This function erases all the flash memory banks. For devices like +//! MSP430i204x, this API erases main memory and information flash memory if +//! the FLASH_unlockInfo API was previously executed (otherwise the information +//! flash is not erased). Also note that erasing information flash memory in +//! the MSP430i204x impacts the TLV calibration constants located at the +//! information memory. +//! +//! \param flash_ptr is a pointer into the bank to be erased +//! +//! \return None +// +//***************************************************************************** +void FLASH_massErase( uint8_t *flash_ptr) +{ + //Clear Lock bit + HWREG16(FLASH_BASE + OFS_FCTL3) = FWKEY; + + while (HWREG8(FLASH_BASE + OFS_FCTL3) & BUSY) ; + + //Set MERAS bit + HWREG16(FLASH_BASE + OFS_FCTL1) = FWKEY + MERAS + ERASE; + + //Dummy write to erase Flash seg + *flash_ptr = 0; + + //test busy + while (HWREG8(FLASH_BASE + OFS_FCTL3) & BUSY) ; + + //Clear MERAS bit + HWREG16(FLASH_BASE + OFS_FCTL1) = FWKEY; + + //Set LOCK bit + HWREG16(FLASH_BASE + OFS_FCTL3) = FWKEY + LOCK; +} + +//***************************************************************************** +// +//! \brief Erase check of the flash memory +//! +//! This function checks bytes in flash memory to make sure that they are in an +//! erased state (are set to 0xFF). +//! +//! \param flash_ptr is the pointer to the starting location of the erase check +//! \param numberOfBytes is the number of bytes to be checked +//! +//! \return STATUS_SUCCESS or STATUS_FAIL +// +//***************************************************************************** +bool FLASH_eraseCheck(uint8_t *flash_ptr, + uint16_t numberOfBytes + ) +{ + uint16_t i; + + for (i = 0; i < numberOfBytes; i++) { + //was erasing successfull? + if ((*(flash_ptr + i)) != 0xFF) + return STATUS_FAIL; + } + return STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! \brief Write data into the flash memory in byte format, pass by reference +//! +//! This function writes a byte array of size count into flash memory. Assumes +//! the flash memory is already erased and unlocked. FLASH_segmentErase can be +//! used to erase a segment. +//! +//! \param data_ptr is the pointer to the data to be written +//! \param flash_ptr is the pointer into which to write the data +//! \param count number of times to write the value +//! +//! \return None +// +//***************************************************************************** +void FLASH_write8(uint8_t *data_ptr, + uint8_t *flash_ptr, + uint16_t count + ) +{ + //Clear Lock bit + HWREG16(FLASH_BASE + OFS_FCTL3) = FWKEY; + + //Enable byte/word write mode + HWREG16(FLASH_BASE + OFS_FCTL1) = FWKEY + WRT; + + while (count > 0) { + //test busy + while (HWREG8(FLASH_BASE + OFS_FCTL3) & BUSY) ; + + //Write to Flash + *flash_ptr++ = *data_ptr++; + count--; + } + + //Clear WRT bit + HWREG16(FLASH_BASE + OFS_FCTL1) = FWKEY; + + //Set LOCK bit + HWREG16(FLASH_BASE + OFS_FCTL3) = FWKEY + LOCK; +} + +//***************************************************************************** +// +//! \brief Write data into the flash memory in 16-bit word format, pass by +//! reference +//! +//! This function writes a 16-bit word array of size count into flash memory. +//! Assumes the flash memory is already erased and unlocked. FLASH_segmentErase +//! can be used to erase a segment. +//! +//! \param data_ptr is the pointer to the data to be written +//! \param flash_ptr is the pointer into which to write the data +//! \param count number of times to write the value +//! +//! \return None +// +//***************************************************************************** +void FLASH_write16(uint16_t *data_ptr, + uint16_t *flash_ptr, + uint16_t count + ) +{ + //Clear Lock bit + HWREG16(FLASH_BASE + OFS_FCTL3) = FWKEY; + + //Enable byte/word write mode + HWREG16(FLASH_BASE + OFS_FCTL1) = FWKEY + WRT; + + while (count > 0) { + //test busy + while (HWREG8(FLASH_BASE + OFS_FCTL3) & BUSY) ; + + //Write to Flash + *flash_ptr++ = *data_ptr++; + count--; + } + + //Clear WRT bit + HWREG16(FLASH_BASE + OFS_FCTL1) = FWKEY; + + //Set LOCK bit + HWREG16(FLASH_BASE + OFS_FCTL3) = FWKEY + LOCK; +} + +//***************************************************************************** +// +//! \brief Write data into the flash memory in 32-bit word format, pass by +//! reference +//! +//! This function writes a 32-bit array of size count into flash memory. +//! Assumes the flash memory is already erased and unlocked. FLASH_segmentErase +//! can be used to erase a segment. +//! +//! \param data_ptr is the pointer to the data to be written +//! \param flash_ptr is the pointer into which to write the data +//! \param count number of times to write the value +//! +//! \return None +// +//***************************************************************************** +void FLASH_write32(uint32_t *data_ptr, + uint32_t *flash_ptr, + uint16_t count + ) +{ + //Clear Lock bit + HWREG16(FLASH_BASE + OFS_FCTL3) = FWKEY; + + //Enable long-word write + HWREG16(FLASH_BASE + OFS_FCTL1) = FWKEY + BLKWRT; + + while (count > 0) { + //test busy + while (HWREG8(FLASH_BASE + OFS_FCTL3) & BUSY) ; + + //Write to Flash + *flash_ptr++ = *data_ptr++; + + count--; + } + + //Clear BLKWRT bit + HWREG16(FLASH_BASE + OFS_FCTL1) = FWKEY; + + //Set LOCK bit + HWREG16(FLASH_BASE + OFS_FCTL3) = FWKEY + LOCK; +} + +//***************************************************************************** +// +//! \brief Write data into the flash memory in 32-bit word format, pass by +//! value +//! +//! This function writes a 32-bit data value into flash memory, count times. +//! Assumes the flash memory is already erased and unlocked. FLASH_segmentErase +//! can be used to erase a segment. +//! +//! \param value value to fill memory with +//! \param flash_ptr is the pointer into which to write the data +//! \param count number of times to write the value +//! +//! \return None +// +//***************************************************************************** +void FLASH_memoryFill32(uint32_t value, + uint32_t *flash_ptr, + uint16_t count + ) +{ + //Clear Lock bit + HWREG16(FLASH_BASE + OFS_FCTL3) = FWKEY; + + //Enable long-word write + HWREG16(FLASH_BASE + OFS_FCTL1) = FWKEY + BLKWRT; + + //test busy + while (count > 0) { + while ((HWREG8(FLASH_BASE + OFS_FCTL3)) & BUSY) ; + + //Write to Flash + *flash_ptr++ = value; + + count--; + } + + //Clear BLKWRT bit + HWREG16(FLASH_BASE + OFS_FCTL1) = FWKEY; + + //Set LOCK bit + HWREG16(FLASH_BASE + OFS_FCTL3) = FWKEY + LOCK; +} + +//***************************************************************************** +// +//! \brief Check FLASH status to see if it is currently busy erasing or +//! programming +//! +//! This function checks the status register to determine if the flash memory +//! is ready for writing. +//! +//! \param mask FLASH status to read +//! Mask value is the logical OR of any of the following: +//! - \b FLASH_READY_FOR_NEXT_WRITE +//! - \b FLASH_ACCESS_VIOLATION_INTERRUPT_FLAG +//! - \b FLASH_PASSWORD_WRITTEN_INCORRECTLY +//! - \b FLASH_BUSY +//! +//! \return Logical OR of any of the following: +//! - \b FLASH_READY_FOR_NEXT_WRITE +//! - \b FLASH_ACCESS_VIOLATION_INTERRUPT_FLAG +//! - \b FLASH_PASSWORD_WRITTEN_INCORRECTLY +//! - \b FLASH_BUSY +//! \n indicating the status of the FLASH +// +//***************************************************************************** +uint8_t FLASH_status(uint8_t mask + ) +{ + return (HWREG8(FLASH_BASE + OFS_FCTL3) & mask ); +} + +//***************************************************************************** +// +//! \brief Locks the information flash memory segment A +//! +//! This function is typically called after an erase or write operation on the +//! information flash segment is performed by any of the other API functions in +//! order to re-lock the information flash segment. +//! +//! +//! \return None +// +//***************************************************************************** +void FLASH_lockInfoA(void) +{ + //Disable global interrupts while doing RMW operation on LOCKA bit + uint16_t gieStatus; + + gieStatus = __get_SR_register() & GIE; //Store current SR register + __disable_interrupt(); //Disable global interrupt + + //Set the LOCKA bit in FCTL3. + //Since LOCKA toggles when you write a 1 (and writing 0 has no effect), + //read the register, XOR with LOCKA mask, mask the lower byte + //and write it back. + HWREG16(FLASH_BASE + OFS_FCTL3) = FWKEY + + ((HWREG16(FLASH_BASE + OFS_FCTL3) ^ LOCKA) & 0xFF); + + //Reinstate SR register to restore global interrupt enable status + __bis_SR_register(gieStatus); +} + +//***************************************************************************** +// +//! \brief Unlocks the information flash memory segment A +//! +//! This function must be called before an erase or write operation on the +//! information flash segment is performed by any of the other API functions. +//! +//! +//! \return None +// +//***************************************************************************** +void FLASH_unlockInfoA(void) +{ + //Disable global interrupts while doing RMW operation on LOCKA bit + uint16_t gieStatus; + + gieStatus = __get_SR_register() & GIE; //Store current SR register + __disable_interrupt(); //Disable global interrupt + + //Clear the LOCKA bit in FCTL3. + //Since LOCKA toggles when you write a 1 (and writing 0 has no effect), + //read the register, mask the lower byte, and write it back. + HWREG16(FLASH_BASE + OFS_FCTL3) = FWKEY + + (HWREG16(FLASH_BASE + OFS_FCTL3) & 0xFF); + + //Reinstate SR register to restore global interrupt enable status + __bis_SR_register(gieStatus); +} + + +#endif +#endif +//***************************************************************************** +// +//! Close the doxygen group for flash_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/flash.h b/source/driverlib/MSP430F5xx_6xx/flash.h new file mode 100644 index 0000000..d0174f7 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/flash.h @@ -0,0 +1,114 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// flash.h - Driver for the FLASH Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_FLASH_H__ +#define __MSP430WARE_FLASH_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_FLASH__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the mask parameter for +// functions: FLASH_status() as well as returned by the FLASH_status() +// function. +// +//***************************************************************************** +#define FLASH_READY_FOR_NEXT_WRITE WAIT +#define FLASH_ACCESS_VIOLATION_INTERRUPT_FLAG ACCVIFG +#define FLASH_PASSWORD_WRITTEN_INCORRECTLY KEYV +#define FLASH_BUSY BUSY + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void FLASH_segmentErase(uint8_t *flash_ptr); + +extern void FLASH_bankErase(uint8_t *flash_ptr); + +extern void FLASH_massErase(uint8_t *flash_ptr); + +extern bool FLASH_eraseCheck(uint8_t *flash_ptr, + uint16_t numberOfBytes); + +extern void FLASH_write8(uint8_t *data_ptr, + uint8_t *flash_ptr, + uint16_t count); + +extern void FLASH_write16(uint16_t *data_ptr, + uint16_t *flash_ptr, + uint16_t count); + +extern void FLASH_write32(uint32_t *data_ptr, + uint32_t *flash_ptr, + uint16_t count); + +extern void FLASH_memoryFill32(uint32_t value, + uint32_t *flash_ptr, + uint16_t count); + +extern uint8_t FLASH_status(uint8_t mask); + +extern void FLASH_lockInfoA(void); + +extern void FLASH_unlockInfoA(void); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_FLASH_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/gpio.c b/source/driverlib/MSP430F5xx_6xx/gpio.c new file mode 100644 index 0000000..606d8a3 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/gpio.c @@ -0,0 +1,1260 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// gpio.c - Driver for the gpio Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup gpio_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_PORT1_R__ +#include "gpio.h" + +#include + +static const uint16_t GPIO_PORT_TO_BASE[] = { + 0x00, +#if defined(__MSP430_HAS_PORT1_R__) + __MSP430_BASEADDRESS_PORT1_R__, +#elif defined(__MSP430_HAS_PORT1__) + __MSP430_BASEADDRESS_PORT1__, +#else + 0xFFFF, +#endif +#if defined(__MSP430_HAS_PORT2_R__) + __MSP430_BASEADDRESS_PORT2_R__, +#elif defined(__MSP430_HAS_PORT2__) + __MSP430_BASEADDRESS_PORT2__, +#else + 0xFFFF, +#endif +#if defined(__MSP430_HAS_PORT3_R__) + __MSP430_BASEADDRESS_PORT3_R__, +#elif defined(__MSP430_HAS_PORT3__) + __MSP430_BASEADDRESS_PORT3__, +#else + 0xFFFF, +#endif +#if defined(__MSP430_HAS_PORT4_R__) + __MSP430_BASEADDRESS_PORT4_R__, +#elif defined(__MSP430_HAS_PORT4__) + __MSP430_BASEADDRESS_PORT4__, +#else + 0xFFFF, +#endif +#if defined(__MSP430_HAS_PORT5_R__) + __MSP430_BASEADDRESS_PORT5_R__, +#elif defined(__MSP430_HAS_PORT5__) + __MSP430_BASEADDRESS_PORT5__, +#else + 0xFFFF, +#endif +#if defined(__MSP430_HAS_PORT6_R__) + __MSP430_BASEADDRESS_PORT6_R__, +#elif defined(__MSP430_HAS_PORT6__) + __MSP430_BASEADDRESS_PORT6__, +#else + 0xFFFF, +#endif +#if defined(__MSP430_HAS_PORT7_R__) + __MSP430_BASEADDRESS_PORT7_R__, +#elif defined(__MSP430_HAS_PORT7__) + __MSP430_BASEADDRESS_PORT7__, +#else + 0xFFFF, +#endif +#if defined(__MSP430_HAS_PORT8_R__) + __MSP430_BASEADDRESS_PORT8_R__, +#elif defined(__MSP430_HAS_PORT8__) + __MSP430_BASEADDRESS_PORT8__, +#else + 0xFFFF, +#endif +#if defined(__MSP430_HAS_PORT9_R__) + __MSP430_BASEADDRESS_PORT9_R__, +#elif defined(__MSP430_HAS_PORT9__) + __MSP430_BASEADDRESS_PORT9__, +#else + 0xFFFF, +#endif +#if defined(__MSP430_HAS_PORT10_R__) + __MSP430_BASEADDRESS_PORT10_R__, +#elif defined(__MSP430_HAS_PORT10__) + __MSP430_BASEADDRESS_PORT10__, +#else + 0xFFFF, +#endif +#if defined(__MSP430_HAS_PORT11_R__) + __MSP430_BASEADDRESS_PORT11_R__, +#elif defined(__MSP430_HAS_PORT11__) + __MSP430_BASEADDRESS_PORT11__, +#else + 0xFFFF, +#endif + 0xFFFF, +#if defined(__MSP430_HAS_PORTJ_R__) + __MSP430_BASEADDRESS_PORTJ_R__ +#elif defined(__MSP430_HAS_PORTJ__) + __MSP430_BASEADDRESS_PORTJ__ +#else + 0xFFFF +#endif +}; + +//***************************************************************************** +// +//! \brief This function configures the selected Pin as output pin +//! +//! This function selected pins on a selected port as output pins. +//! +//! \param selectedPort is the selected port. +//! Valid values are: +//! - \b GPIO_PORT_P1 +//! - \b GPIO_PORT_P2 +//! - \b GPIO_PORT_P3 +//! - \b GPIO_PORT_P4 +//! - \b GPIO_PORT_P5 +//! - \b GPIO_PORT_P6 +//! - \b GPIO_PORT_P7 +//! - \b GPIO_PORT_P8 +//! - \b GPIO_PORT_P9 +//! - \b GPIO_PORT_P10 +//! - \b GPIO_PORT_P11 +//! - \b GPIO_PORT_PA +//! - \b GPIO_PORT_PB +//! - \b GPIO_PORT_PC +//! - \b GPIO_PORT_PD +//! - \b GPIO_PORT_PE +//! - \b GPIO_PORT_PF +//! - \b GPIO_PORT_PJ +//! \param selectedPins is the specified pin in the selected port. +//! Mask value is the logical OR of any of the following: +//! - \b GPIO_PIN0 +//! - \b GPIO_PIN1 +//! - \b GPIO_PIN2 +//! - \b GPIO_PIN3 +//! - \b GPIO_PIN4 +//! - \b GPIO_PIN5 +//! - \b GPIO_PIN6 +//! - \b GPIO_PIN7 +//! - \b GPIO_PIN8 +//! - \b GPIO_PIN9 +//! - \b GPIO_PIN10 +//! - \b GPIO_PIN11 +//! - \b GPIO_PIN12 +//! - \b GPIO_PIN13 +//! - \b GPIO_PIN14 +//! - \b GPIO_PIN15 +//! +//! Modified bits of \b PxDIR register and bits of \b PxSEL register. +//! +//! \return None +// +//***************************************************************************** +void GPIO_setAsOutputPin(uint8_t selectedPort, uint16_t selectedPins) +{ + + uint16_t baseAddress = GPIO_PORT_TO_BASE[selectedPort]; + + #ifndef NDEBUG + if (baseAddress == 0xFFFF) + return; + + #endif + + // Shift by 8 if port is even (upper 8-bits) + if ((selectedPort & 1) ^ 1) + selectedPins <<= 8; + + HWREG16(baseAddress + OFS_PASEL) &= ~selectedPins; + HWREG16(baseAddress + OFS_PADIR) |= selectedPins; + + return; +} + +//***************************************************************************** +// +//! \brief This function configures the selected Pin as input pin +//! +//! This function selected pins on a selected port as input pins. +//! +//! \param selectedPort is the selected port. +//! Valid values are: +//! - \b GPIO_PORT_P1 +//! - \b GPIO_PORT_P2 +//! - \b GPIO_PORT_P3 +//! - \b GPIO_PORT_P4 +//! - \b GPIO_PORT_P5 +//! - \b GPIO_PORT_P6 +//! - \b GPIO_PORT_P7 +//! - \b GPIO_PORT_P8 +//! - \b GPIO_PORT_P9 +//! - \b GPIO_PORT_P10 +//! - \b GPIO_PORT_P11 +//! - \b GPIO_PORT_PA +//! - \b GPIO_PORT_PB +//! - \b GPIO_PORT_PC +//! - \b GPIO_PORT_PD +//! - \b GPIO_PORT_PE +//! - \b GPIO_PORT_PF +//! - \b GPIO_PORT_PJ +//! \param selectedPins is the specified pin in the selected port. +//! Mask value is the logical OR of any of the following: +//! - \b GPIO_PIN0 +//! - \b GPIO_PIN1 +//! - \b GPIO_PIN2 +//! - \b GPIO_PIN3 +//! - \b GPIO_PIN4 +//! - \b GPIO_PIN5 +//! - \b GPIO_PIN6 +//! - \b GPIO_PIN7 +//! - \b GPIO_PIN8 +//! - \b GPIO_PIN9 +//! - \b GPIO_PIN10 +//! - \b GPIO_PIN11 +//! - \b GPIO_PIN12 +//! - \b GPIO_PIN13 +//! - \b GPIO_PIN14 +//! - \b GPIO_PIN15 +//! +//! Modified bits of \b PxDIR register, bits of \b PxREN register and bits of +//! \b PxSEL register. +//! +//! \return None +// +//***************************************************************************** +void GPIO_setAsInputPin(uint8_t selectedPort, uint16_t selectedPins) +{ + + uint16_t baseAddress = GPIO_PORT_TO_BASE[selectedPort]; + + #ifndef NDEBUG + if (baseAddress == 0xFFFF) + return; + + #endif + + // Shift by 8 if port is even (upper 8-bits) + if ((selectedPort & 1) ^ 1) + selectedPins <<= 8; + + HWREG16(baseAddress + OFS_PASEL) &= ~selectedPins; + HWREG16(baseAddress + OFS_PADIR) &= ~selectedPins; + HWREG16(baseAddress + OFS_PAREN) &= ~selectedPins; +} + +//***************************************************************************** +// +//! \brief This function configures the peripheral module function in the +//! output direction for the selected pin for either primary, secondary or +//! ternary module function modes +//! +//! This function configures the peripheral module function in the output +//! direction for the selected pin for either primary, secondary or ternary +//! module function modes. Accepted values for mode are +//! GPIO_PRIMARY_MODULE_FUNCTION, GPIO_SECONDARY_MODULE_FUNCTION, and +//! GPIO_TERNARY_MODULE_FUNCTION +//! +//! \param selectedPort is the selected port. +//! Valid values are: +//! - \b GPIO_PORT_P1 +//! - \b GPIO_PORT_P2 +//! - \b GPIO_PORT_P3 +//! - \b GPIO_PORT_P4 +//! - \b GPIO_PORT_P5 +//! - \b GPIO_PORT_P6 +//! - \b GPIO_PORT_P7 +//! - \b GPIO_PORT_P8 +//! - \b GPIO_PORT_P9 +//! - \b GPIO_PORT_P10 +//! - \b GPIO_PORT_P11 +//! - \b GPIO_PORT_PA +//! - \b GPIO_PORT_PB +//! - \b GPIO_PORT_PC +//! - \b GPIO_PORT_PD +//! - \b GPIO_PORT_PE +//! - \b GPIO_PORT_PF +//! - \b GPIO_PORT_PJ +//! \param selectedPins is the specified pin in the selected port. +//! Mask value is the logical OR of any of the following: +//! - \b GPIO_PIN0 +//! - \b GPIO_PIN1 +//! - \b GPIO_PIN2 +//! - \b GPIO_PIN3 +//! - \b GPIO_PIN4 +//! - \b GPIO_PIN5 +//! - \b GPIO_PIN6 +//! - \b GPIO_PIN7 +//! - \b GPIO_PIN8 +//! - \b GPIO_PIN9 +//! - \b GPIO_PIN10 +//! - \b GPIO_PIN11 +//! - \b GPIO_PIN12 +//! - \b GPIO_PIN13 +//! - \b GPIO_PIN14 +//! - \b GPIO_PIN15 +//! +//! Modified bits of \b PxDIR register and bits of \b PxSEL register. +//! +//! \return None +// +//***************************************************************************** +void GPIO_setAsPeripheralModuleFunctionOutputPin(uint8_t selectedPort, + uint16_t selectedPins + ) +{ + + uint16_t baseAddress = GPIO_PORT_TO_BASE[selectedPort]; + + #ifndef NDEBUG + if (baseAddress == 0xFFFF) + return; + + #endif + + // Shift by 8 if port is even (upper 8-bits) + if ((selectedPort & 1) ^ 1) + selectedPins <<= 8; + + HWREG16(baseAddress + OFS_PADIR) |= selectedPins; + HWREG16(baseAddress + OFS_PASEL) |= selectedPins; +} + +//***************************************************************************** +// +//! \brief This function configures the peripheral module function in the input +//! direction for the selected pin for either primary, secondary or ternary +//! module function modes. +//! +//! This function configures the peripheral module function in the input +//! direction for the selected pin for either primary, secondary or ternary +//! module function modes. Accepted values for mode are +//! GPIO_PRIMARY_MODULE_FUNCTION, GPIO_SECONDARY_MODULE_FUNCTION, and +//! GPIO_TERNARY_MODULE_FUNCTION +//! +//! \param selectedPort is the selected port. +//! Valid values are: +//! - \b GPIO_PORT_P1 +//! - \b GPIO_PORT_P2 +//! - \b GPIO_PORT_P3 +//! - \b GPIO_PORT_P4 +//! - \b GPIO_PORT_P5 +//! - \b GPIO_PORT_P6 +//! - \b GPIO_PORT_P7 +//! - \b GPIO_PORT_P8 +//! - \b GPIO_PORT_P9 +//! - \b GPIO_PORT_P10 +//! - \b GPIO_PORT_P11 +//! - \b GPIO_PORT_PA +//! - \b GPIO_PORT_PB +//! - \b GPIO_PORT_PC +//! - \b GPIO_PORT_PD +//! - \b GPIO_PORT_PE +//! - \b GPIO_PORT_PF +//! - \b GPIO_PORT_PJ +//! \param selectedPins is the specified pin in the selected port. +//! Mask value is the logical OR of any of the following: +//! - \b GPIO_PIN0 +//! - \b GPIO_PIN1 +//! - \b GPIO_PIN2 +//! - \b GPIO_PIN3 +//! - \b GPIO_PIN4 +//! - \b GPIO_PIN5 +//! - \b GPIO_PIN6 +//! - \b GPIO_PIN7 +//! - \b GPIO_PIN8 +//! - \b GPIO_PIN9 +//! - \b GPIO_PIN10 +//! - \b GPIO_PIN11 +//! - \b GPIO_PIN12 +//! - \b GPIO_PIN13 +//! - \b GPIO_PIN14 +//! - \b GPIO_PIN15 +//! +//! Modified bits of \b PxDIR register and bits of \b PxSEL register. +//! +//! \return None +// +//***************************************************************************** +void GPIO_setAsPeripheralModuleFunctionInputPin(uint8_t selectedPort, + uint16_t selectedPins + ) +{ + uint16_t baseAddress = GPIO_PORT_TO_BASE[selectedPort]; + + #ifndef NDEBUG + if (baseAddress == 0xFFFF) + return; + + #endif + + // Shift by 8 if port is even (upper 8-bits) + if ((selectedPort & 1) ^ 1) + selectedPins <<= 8; + + HWREG16(baseAddress + OFS_PADIR) &= ~selectedPins; + HWREG16(baseAddress + OFS_PASEL) |= selectedPins; +} + +//***************************************************************************** +// +//! \brief This function sets output HIGH on the selected Pin +//! +//! This function sets output HIGH on the selected port's pin. +//! +//! \param selectedPort is the selected port. +//! Valid values are: +//! - \b GPIO_PORT_P1 +//! - \b GPIO_PORT_P2 +//! - \b GPIO_PORT_P3 +//! - \b GPIO_PORT_P4 +//! - \b GPIO_PORT_P5 +//! - \b GPIO_PORT_P6 +//! - \b GPIO_PORT_P7 +//! - \b GPIO_PORT_P8 +//! - \b GPIO_PORT_P9 +//! - \b GPIO_PORT_P10 +//! - \b GPIO_PORT_P11 +//! - \b GPIO_PORT_PA +//! - \b GPIO_PORT_PB +//! - \b GPIO_PORT_PC +//! - \b GPIO_PORT_PD +//! - \b GPIO_PORT_PE +//! - \b GPIO_PORT_PF +//! - \b GPIO_PORT_PJ +//! \param selectedPins is the specified pin in the selected port. +//! Mask value is the logical OR of any of the following: +//! - \b GPIO_PIN0 +//! - \b GPIO_PIN1 +//! - \b GPIO_PIN2 +//! - \b GPIO_PIN3 +//! - \b GPIO_PIN4 +//! - \b GPIO_PIN5 +//! - \b GPIO_PIN6 +//! - \b GPIO_PIN7 +//! - \b GPIO_PIN8 +//! - \b GPIO_PIN9 +//! - \b GPIO_PIN10 +//! - \b GPIO_PIN11 +//! - \b GPIO_PIN12 +//! - \b GPIO_PIN13 +//! - \b GPIO_PIN14 +//! - \b GPIO_PIN15 +//! +//! Modified bits of \b PxOUT register. +//! +//! \return None +// +//***************************************************************************** +void GPIO_setOutputHighOnPin(uint8_t selectedPort, + uint16_t selectedPins) +{ + + uint16_t baseAddress = GPIO_PORT_TO_BASE[selectedPort]; + + #ifndef NDEBUG + if (baseAddress == 0xFFFF) + return; + + #endif + + // Shift by 8 if port is even (upper 8-bits) + if ((selectedPort & 1) ^ 1) + selectedPins <<= 8; + + HWREG16(baseAddress + OFS_PAOUT) |= selectedPins; +} + +//***************************************************************************** +// +//! \brief This function sets output LOW on the selected Pin +//! +//! This function sets output LOW on the selected port's pin. +//! +//! \param selectedPort is the selected port. +//! Valid values are: +//! - \b GPIO_PORT_P1 +//! - \b GPIO_PORT_P2 +//! - \b GPIO_PORT_P3 +//! - \b GPIO_PORT_P4 +//! - \b GPIO_PORT_P5 +//! - \b GPIO_PORT_P6 +//! - \b GPIO_PORT_P7 +//! - \b GPIO_PORT_P8 +//! - \b GPIO_PORT_P9 +//! - \b GPIO_PORT_P10 +//! - \b GPIO_PORT_P11 +//! - \b GPIO_PORT_PA +//! - \b GPIO_PORT_PB +//! - \b GPIO_PORT_PC +//! - \b GPIO_PORT_PD +//! - \b GPIO_PORT_PE +//! - \b GPIO_PORT_PF +//! - \b GPIO_PORT_PJ +//! \param selectedPins is the specified pin in the selected port. +//! Mask value is the logical OR of any of the following: +//! - \b GPIO_PIN0 +//! - \b GPIO_PIN1 +//! - \b GPIO_PIN2 +//! - \b GPIO_PIN3 +//! - \b GPIO_PIN4 +//! - \b GPIO_PIN5 +//! - \b GPIO_PIN6 +//! - \b GPIO_PIN7 +//! - \b GPIO_PIN8 +//! - \b GPIO_PIN9 +//! - \b GPIO_PIN10 +//! - \b GPIO_PIN11 +//! - \b GPIO_PIN12 +//! - \b GPIO_PIN13 +//! - \b GPIO_PIN14 +//! - \b GPIO_PIN15 +//! +//! Modified bits of \b PxOUT register. +//! +//! \return None +// +//***************************************************************************** +void GPIO_setOutputLowOnPin(uint8_t selectedPort, uint16_t selectedPins) +{ + + uint16_t baseAddress = GPIO_PORT_TO_BASE[selectedPort]; + + #ifndef NDEBUG + if (baseAddress == 0xFFFF) + return; + + #endif + + // Shift by 8 if port is even (upper 8-bits) + if ((selectedPort & 1) ^ 1) + selectedPins <<= 8; + + HWREG16(baseAddress + OFS_PAOUT) &= ~selectedPins; +} + +//***************************************************************************** +// +//! \brief This function toggles the output on the selected Pin +//! +//! This function toggles the output on the selected port's pin. +//! +//! \param selectedPort is the selected port. +//! Valid values are: +//! - \b GPIO_PORT_P1 +//! - \b GPIO_PORT_P2 +//! - \b GPIO_PORT_P3 +//! - \b GPIO_PORT_P4 +//! - \b GPIO_PORT_P5 +//! - \b GPIO_PORT_P6 +//! - \b GPIO_PORT_P7 +//! - \b GPIO_PORT_P8 +//! - \b GPIO_PORT_P9 +//! - \b GPIO_PORT_P10 +//! - \b GPIO_PORT_P11 +//! - \b GPIO_PORT_PA +//! - \b GPIO_PORT_PB +//! - \b GPIO_PORT_PC +//! - \b GPIO_PORT_PD +//! - \b GPIO_PORT_PE +//! - \b GPIO_PORT_PF +//! - \b GPIO_PORT_PJ +//! \param selectedPins is the specified pin in the selected port. +//! Mask value is the logical OR of any of the following: +//! - \b GPIO_PIN0 +//! - \b GPIO_PIN1 +//! - \b GPIO_PIN2 +//! - \b GPIO_PIN3 +//! - \b GPIO_PIN4 +//! - \b GPIO_PIN5 +//! - \b GPIO_PIN6 +//! - \b GPIO_PIN7 +//! - \b GPIO_PIN8 +//! - \b GPIO_PIN9 +//! - \b GPIO_PIN10 +//! - \b GPIO_PIN11 +//! - \b GPIO_PIN12 +//! - \b GPIO_PIN13 +//! - \b GPIO_PIN14 +//! - \b GPIO_PIN15 +//! +//! Modified bits of \b PxOUT register. +//! +//! \return None +// +//***************************************************************************** +void GPIO_toggleOutputOnPin(uint8_t selectedPort, uint16_t selectedPins) +{ + + uint16_t baseAddress = GPIO_PORT_TO_BASE[selectedPort]; + + #ifndef NDEBUG + if (baseAddress == 0xFFFF) + return; + + #endif + + // Shift by 8 if port is even (upper 8-bits) + if ((selectedPort & 1) ^ 1) + selectedPins <<= 8; + + HWREG16(baseAddress + OFS_PAOUT) ^= selectedPins; +} + +//***************************************************************************** +// +//! \brief This function sets the selected Pin in input Mode with Pull Down +//! resistor +//! +//! This function sets the selected Pin in input Mode with Pull Down resistor. +//! +//! \param selectedPort is the selected port. +//! Valid values are: +//! - \b GPIO_PORT_P1 +//! - \b GPIO_PORT_P2 +//! - \b GPIO_PORT_P3 +//! - \b GPIO_PORT_P4 +//! - \b GPIO_PORT_P5 +//! - \b GPIO_PORT_P6 +//! - \b GPIO_PORT_P7 +//! - \b GPIO_PORT_P8 +//! - \b GPIO_PORT_P9 +//! - \b GPIO_PORT_P10 +//! - \b GPIO_PORT_P11 +//! - \b GPIO_PORT_PA +//! - \b GPIO_PORT_PB +//! - \b GPIO_PORT_PC +//! - \b GPIO_PORT_PD +//! - \b GPIO_PORT_PE +//! - \b GPIO_PORT_PF +//! - \b GPIO_PORT_PJ +//! \param selectedPins is the specified pin in the selected port. +//! Mask value is the logical OR of any of the following: +//! - \b GPIO_PIN0 +//! - \b GPIO_PIN1 +//! - \b GPIO_PIN2 +//! - \b GPIO_PIN3 +//! - \b GPIO_PIN4 +//! - \b GPIO_PIN5 +//! - \b GPIO_PIN6 +//! - \b GPIO_PIN7 +//! - \b GPIO_PIN8 +//! - \b GPIO_PIN9 +//! - \b GPIO_PIN10 +//! - \b GPIO_PIN11 +//! - \b GPIO_PIN12 +//! - \b GPIO_PIN13 +//! - \b GPIO_PIN14 +//! - \b GPIO_PIN15 +//! +//! Modified bits of \b PxDIR register, bits of \b PxOUT register and bits of +//! \b PxREN register. +//! +//! \return None +// +//***************************************************************************** +void GPIO_setAsInputPinWithPullDownResistor(uint8_t selectedPort, + uint16_t selectedPins) +{ + + uint16_t baseAddress = GPIO_PORT_TO_BASE[selectedPort]; + + #ifndef NDEBUG + if (baseAddress == 0xFFFF) + return; + + #endif + + // Shift by 8 if port is even (upper 8-bits) + if ((selectedPort & 1) ^ 1) + selectedPins <<= 8; + + HWREG16(baseAddress + OFS_PASEL) &= ~selectedPins; + + HWREG16(baseAddress + OFS_PADIR) &= ~selectedPins; + HWREG16(baseAddress + OFS_PAREN) |= selectedPins; + HWREG16(baseAddress + OFS_PAOUT) &= ~selectedPins; +} + +//***************************************************************************** +// +//! \brief This function sets the selected Pin in input Mode with Pull Up +//! resistor +//! +//! This function sets the selected Pin in input Mode with Pull Up resistor. +//! +//! \param selectedPort is the selected port. +//! Valid values are: +//! - \b GPIO_PORT_P1 +//! - \b GPIO_PORT_P2 +//! - \b GPIO_PORT_P3 +//! - \b GPIO_PORT_P4 +//! - \b GPIO_PORT_P5 +//! - \b GPIO_PORT_P6 +//! - \b GPIO_PORT_P7 +//! - \b GPIO_PORT_P8 +//! - \b GPIO_PORT_P9 +//! - \b GPIO_PORT_P10 +//! - \b GPIO_PORT_P11 +//! - \b GPIO_PORT_PA +//! - \b GPIO_PORT_PB +//! - \b GPIO_PORT_PC +//! - \b GPIO_PORT_PD +//! - \b GPIO_PORT_PE +//! - \b GPIO_PORT_PF +//! - \b GPIO_PORT_PJ +//! \param selectedPins is the specified pin in the selected port. +//! Mask value is the logical OR of any of the following: +//! - \b GPIO_PIN0 +//! - \b GPIO_PIN1 +//! - \b GPIO_PIN2 +//! - \b GPIO_PIN3 +//! - \b GPIO_PIN4 +//! - \b GPIO_PIN5 +//! - \b GPIO_PIN6 +//! - \b GPIO_PIN7 +//! - \b GPIO_PIN8 +//! - \b GPIO_PIN9 +//! - \b GPIO_PIN10 +//! - \b GPIO_PIN11 +//! - \b GPIO_PIN12 +//! - \b GPIO_PIN13 +//! - \b GPIO_PIN14 +//! - \b GPIO_PIN15 +//! +//! Modified bits of \b PxDIR register, bits of \b PxOUT register and bits of +//! \b PxREN register. +//! +//! \return None +// +//***************************************************************************** +void GPIO_setAsInputPinWithPullUpResistor(uint8_t selectedPort, + uint16_t selectedPins) +{ + + uint16_t baseAddress = GPIO_PORT_TO_BASE[selectedPort]; + + #ifndef NDEBUG + if (baseAddress == 0xFFFF) + return; + + #endif + + // Shift by 8 if port is even (upper 8-bits) + if ((selectedPort & 1) ^ 1) + selectedPins <<= 8; + + HWREG16(baseAddress + OFS_PASEL) &= ~selectedPins; + HWREG16(baseAddress + OFS_PADIR) &= ~selectedPins; + HWREG16(baseAddress + OFS_PAREN) |= selectedPins; + HWREG16(baseAddress + OFS_PAOUT) |= selectedPins; +} + +//***************************************************************************** +// +//! \brief This function gets the input value on the selected pin +//! +//! This function gets the input value on the selected pin. +//! +//! \param selectedPort is the selected port. +//! Valid values are: +//! - \b GPIO_PORT_P1 +//! - \b GPIO_PORT_P2 +//! - \b GPIO_PORT_P3 +//! - \b GPIO_PORT_P4 +//! - \b GPIO_PORT_P5 +//! - \b GPIO_PORT_P6 +//! - \b GPIO_PORT_P7 +//! - \b GPIO_PORT_P8 +//! - \b GPIO_PORT_P9 +//! - \b GPIO_PORT_P10 +//! - \b GPIO_PORT_P11 +//! - \b GPIO_PORT_PA +//! - \b GPIO_PORT_PB +//! - \b GPIO_PORT_PC +//! - \b GPIO_PORT_PD +//! - \b GPIO_PORT_PE +//! - \b GPIO_PORT_PF +//! - \b GPIO_PORT_PJ +//! \param selectedPins is the specified pin in the selected port. +//! Valid values are: +//! - \b GPIO_PIN0 +//! - \b GPIO_PIN1 +//! - \b GPIO_PIN2 +//! - \b GPIO_PIN3 +//! - \b GPIO_PIN4 +//! - \b GPIO_PIN5 +//! - \b GPIO_PIN6 +//! - \b GPIO_PIN7 +//! - \b GPIO_PIN8 +//! - \b GPIO_PIN9 +//! - \b GPIO_PIN10 +//! - \b GPIO_PIN11 +//! - \b GPIO_PIN12 +//! - \b GPIO_PIN13 +//! - \b GPIO_PIN14 +//! - \b GPIO_PIN15 +//! +//! \return One of the following: +//! - \b GPIO_INPUT_PIN_HIGH +//! - \b GPIO_INPUT_PIN_LOW +//! \n indicating the status of the pin +// +//***************************************************************************** +uint8_t GPIO_getInputPinValue(uint8_t selectedPort, + uint16_t selectedPins) +{ + + uint16_t baseAddress = GPIO_PORT_TO_BASE[selectedPort]; + + #ifndef NDEBUG + if (baseAddress == 0xFFFF) + return; + + #endif + + // Shift by 8 if port is even (upper 8-bits) + if ((selectedPort & 1) ^ 1) + selectedPins <<= 8; + + uint16_t inputPinValue = HWREG16(baseAddress + OFS_PAIN) & (selectedPins); + + if (inputPinValue > 0) + return GPIO_INPUT_PIN_HIGH; + return GPIO_INPUT_PIN_LOW; +} + +//***************************************************************************** +// +//! \brief This function enables the port interrupt on the selected pin +//! +//! This function enables the port interrupt on the selected pin. Note that +//! only Port 1,2, A have this capability. +//! +//! \param selectedPort is the selected port. +//! Valid values are: +//! - \b GPIO_PORT_P1 +//! - \b GPIO_PORT_P2 +//! - \b GPIO_PORT_PA +//! \param selectedPins is the specified pin in the selected port. +//! Mask value is the logical OR of any of the following: +//! - \b GPIO_PIN0 +//! - \b GPIO_PIN1 +//! - \b GPIO_PIN2 +//! - \b GPIO_PIN3 +//! - \b GPIO_PIN4 +//! - \b GPIO_PIN5 +//! - \b GPIO_PIN6 +//! - \b GPIO_PIN7 +//! - \b GPIO_PIN8 +//! - \b GPIO_PIN9 +//! - \b GPIO_PIN10 +//! - \b GPIO_PIN11 +//! - \b GPIO_PIN12 +//! - \b GPIO_PIN13 +//! - \b GPIO_PIN14 +//! - \b GPIO_PIN15 +//! +//! Modified bits of \b PxIE register. +//! +//! \return None +// +//***************************************************************************** +void GPIO_enableInterrupt(uint8_t selectedPort, uint16_t selectedPins) +{ + + uint16_t baseAddress = GPIO_PORT_TO_BASE[selectedPort]; + + #ifndef NDEBUG + if (baseAddress == 0xFFFF) + return; + + #endif + + // Shift by 8 if port is even (upper 8-bits) + if ((selectedPort & 1) ^ 1) + selectedPins <<= 8; + + HWREG16(baseAddress + OFS_PAIE) |= selectedPins; +} + +//***************************************************************************** +// +//! \brief This function disables the port interrupt on the selected pin +//! +//! This function disables the port interrupt on the selected pin. Note that +//! only Port 1,2, A have this capability. +//! +//! \param selectedPort is the selected port. +//! Valid values are: +//! - \b GPIO_PORT_P1 +//! - \b GPIO_PORT_P2 +//! - \b GPIO_PORT_PA +//! \param selectedPins is the specified pin in the selected port. +//! Mask value is the logical OR of any of the following: +//! - \b GPIO_PIN0 +//! - \b GPIO_PIN1 +//! - \b GPIO_PIN2 +//! - \b GPIO_PIN3 +//! - \b GPIO_PIN4 +//! - \b GPIO_PIN5 +//! - \b GPIO_PIN6 +//! - \b GPIO_PIN7 +//! - \b GPIO_PIN8 +//! - \b GPIO_PIN9 +//! - \b GPIO_PIN10 +//! - \b GPIO_PIN11 +//! - \b GPIO_PIN12 +//! - \b GPIO_PIN13 +//! - \b GPIO_PIN14 +//! - \b GPIO_PIN15 +//! +//! Modified bits of \b PxIE register. +//! +//! \return None +// +//***************************************************************************** +void GPIO_disableInterrupt(uint8_t selectedPort, uint16_t selectedPins) +{ + + uint16_t baseAddress = GPIO_PORT_TO_BASE[selectedPort]; + + #ifndef NDEBUG + if (baseAddress == 0xFFFF) + return; + + #endif + + // Shift by 8 if port is even (upper 8-bits) + if ((selectedPort & 1) ^ 1) + selectedPins <<= 8; + + HWREG16(baseAddress + OFS_PAIE) &= ~selectedPins; +} + +//***************************************************************************** +// +//! \brief This function gets the interrupt status of the selected pin +//! +//! This function gets the interrupt status of the selected pin. Note that only +//! Port 1,2, A have this capability. +//! +//! \param selectedPort is the selected port. +//! Valid values are: +//! - \b GPIO_PORT_P1 +//! - \b GPIO_PORT_P2 +//! - \b GPIO_PORT_PA +//! \param selectedPins is the specified pin in the selected port. +//! Mask value is the logical OR of any of the following: +//! - \b GPIO_PIN0 +//! - \b GPIO_PIN1 +//! - \b GPIO_PIN2 +//! - \b GPIO_PIN3 +//! - \b GPIO_PIN4 +//! - \b GPIO_PIN5 +//! - \b GPIO_PIN6 +//! - \b GPIO_PIN7 +//! - \b GPIO_PIN8 +//! - \b GPIO_PIN9 +//! - \b GPIO_PIN10 +//! - \b GPIO_PIN11 +//! - \b GPIO_PIN12 +//! - \b GPIO_PIN13 +//! - \b GPIO_PIN14 +//! - \b GPIO_PIN15 +//! +//! \return Logical OR of any of the following: +//! - \b GPIO_PIN0 +//! - \b GPIO_PIN1 +//! - \b GPIO_PIN2 +//! - \b GPIO_PIN3 +//! - \b GPIO_PIN4 +//! - \b GPIO_PIN5 +//! - \b GPIO_PIN6 +//! - \b GPIO_PIN7 +//! - \b GPIO_PIN8 +//! - \b GPIO_PIN9 +//! - \b GPIO_PIN10 +//! - \b GPIO_PIN11 +//! - \b GPIO_PIN12 +//! - \b GPIO_PIN13 +//! - \b GPIO_PIN14 +//! - \b GPIO_PIN15 +//! \n indicating the interrupt status of the selected pins [Default: +//! 0] +// +//***************************************************************************** +uint16_t GPIO_getInterruptStatus(uint8_t selectedPort, uint16_t selectedPins) +{ + + uint16_t baseAddress = GPIO_PORT_TO_BASE[selectedPort]; + + #ifndef NDEBUG + if (baseAddress == 0xFFFF) + return; + + #endif + + // Shift by 8 if port is even (upper 8-bits) + if ((selectedPort & 1) ^ 1) + selectedPins <<= 8; + + return HWREG16(baseAddress + OFS_PAIFG) & selectedPins; +} + +//***************************************************************************** +// +//! \brief This function clears the interrupt flag on the selected pin +//! +//! This function clears the interrupt flag on the selected pin. Note that only +//! Port 1,2,A have this capability. +//! +//! \param selectedPort is the selected port. +//! Valid values are: +//! - \b GPIO_PORT_P1 +//! - \b GPIO_PORT_P2 +//! - \b GPIO_PORT_PA +//! \param selectedPins is the specified pin in the selected port. +//! Mask value is the logical OR of any of the following: +//! - \b GPIO_PIN0 +//! - \b GPIO_PIN1 +//! - \b GPIO_PIN2 +//! - \b GPIO_PIN3 +//! - \b GPIO_PIN4 +//! - \b GPIO_PIN5 +//! - \b GPIO_PIN6 +//! - \b GPIO_PIN7 +//! - \b GPIO_PIN8 +//! - \b GPIO_PIN9 +//! - \b GPIO_PIN10 +//! - \b GPIO_PIN11 +//! - \b GPIO_PIN12 +//! - \b GPIO_PIN13 +//! - \b GPIO_PIN14 +//! - \b GPIO_PIN15 +//! +//! Modified bits of \b PxIFG register. +//! +//! \return None +// +//***************************************************************************** +void GPIO_clearInterruptFlag(uint8_t selectedPort, uint16_t selectedPins) +{ + + uint16_t baseAddress = GPIO_PORT_TO_BASE[selectedPort]; + + #ifndef NDEBUG + if (baseAddress == 0xFFFF) + return; + + #endif + + // Shift by 8 if port is even (upper 8-bits) + if ((selectedPort & 1) ^ 1) + selectedPins <<= 8; + + HWREG16(baseAddress + OFS_PAIFG) &= ~selectedPins; +} + +//***************************************************************************** +// +//! \brief This function selects on what edge the port interrupt flag should be +//! set for a transition +//! +//! This function selects on what edge the port interrupt flag should be set +//! for a transition. Values for edgeSelect should be +//! GPIO_LOW_TO_HIGH_TRANSITION or GPIO_HIGH_TO_LOW_TRANSITION. +//! +//! \param selectedPort is the selected port. +//! Valid values are: +//! - \b GPIO_PORT_P1 +//! - \b GPIO_PORT_P2 +//! - \b GPIO_PORT_P3 +//! - \b GPIO_PORT_P4 +//! - \b GPIO_PORT_P5 +//! - \b GPIO_PORT_P6 +//! - \b GPIO_PORT_P7 +//! - \b GPIO_PORT_P8 +//! - \b GPIO_PORT_P9 +//! - \b GPIO_PORT_P10 +//! - \b GPIO_PORT_P11 +//! - \b GPIO_PORT_PA +//! - \b GPIO_PORT_PB +//! - \b GPIO_PORT_PC +//! - \b GPIO_PORT_PD +//! - \b GPIO_PORT_PE +//! - \b GPIO_PORT_PF +//! - \b GPIO_PORT_PJ +//! \param selectedPins is the specified pin in the selected port. +//! Mask value is the logical OR of any of the following: +//! - \b GPIO_PIN0 +//! - \b GPIO_PIN1 +//! - \b GPIO_PIN2 +//! - \b GPIO_PIN3 +//! - \b GPIO_PIN4 +//! - \b GPIO_PIN5 +//! - \b GPIO_PIN6 +//! - \b GPIO_PIN7 +//! - \b GPIO_PIN8 +//! - \b GPIO_PIN9 +//! - \b GPIO_PIN10 +//! - \b GPIO_PIN11 +//! - \b GPIO_PIN12 +//! - \b GPIO_PIN13 +//! - \b GPIO_PIN14 +//! - \b GPIO_PIN15 +//! \param edgeSelect specifies what transition sets the interrupt flag +//! Valid values are: +//! - \b GPIO_HIGH_TO_LOW_TRANSITION +//! - \b GPIO_LOW_TO_HIGH_TRANSITION +//! +//! Modified bits of \b PxIES register. +//! +//! \return None +// +//***************************************************************************** +void GPIO_interruptEdgeSelect(uint8_t selectedPort, uint16_t selectedPins, + uint8_t edgeSelect) +{ + + uint16_t baseAddress = GPIO_PORT_TO_BASE[selectedPort]; + + #ifndef NDEBUG + if (baseAddress == 0xFFFF) + return; + + #endif + + // Shift by 8 if port is even (upper 8-bits) + if ((selectedPort & 1) ^ 1) + selectedPins <<= 8; + + if (GPIO_LOW_TO_HIGH_TRANSITION == edgeSelect) + HWREG16(baseAddress + OFS_PAIES) &= ~selectedPins; + else + HWREG16(baseAddress + OFS_PAIES) |= selectedPins; +} + +//***************************************************************************** +// +//! \brief This function sets the drive strength for the selected port pin. +//! +//! his function sets the drive strength for the selected port pin. Acceptable +//! values for driveStrength are GPIO_REDUCED_OUTPUT_DRIVE_STRENGTH and +//! GPIO_FULL_OUTPUT_DRIVE_STRENGTH. +//! +//! \param selectedPort is the selected port. +//! Valid values are: +//! - \b GPIO_PORT_P1 +//! - \b GPIO_PORT_P2 +//! - \b GPIO_PORT_P3 +//! - \b GPIO_PORT_P4 +//! - \b GPIO_PORT_P5 +//! - \b GPIO_PORT_P6 +//! - \b GPIO_PORT_P7 +//! - \b GPIO_PORT_P8 +//! - \b GPIO_PORT_P9 +//! - \b GPIO_PORT_P10 +//! - \b GPIO_PORT_P11 +//! - \b GPIO_PORT_PA +//! - \b GPIO_PORT_PB +//! - \b GPIO_PORT_PC +//! - \b GPIO_PORT_PD +//! - \b GPIO_PORT_PE +//! - \b GPIO_PORT_PF +//! - \b GPIO_PORT_PJ +//! \param selectedPins is the specified pin in the selected port. +//! Mask value is the logical OR of any of the following: +//! - \b GPIO_PIN0 +//! - \b GPIO_PIN1 +//! - \b GPIO_PIN2 +//! - \b GPIO_PIN3 +//! - \b GPIO_PIN4 +//! - \b GPIO_PIN5 +//! - \b GPIO_PIN6 +//! - \b GPIO_PIN7 +//! - \b GPIO_PIN8 +//! - \b GPIO_PIN9 +//! - \b GPIO_PIN10 +//! - \b GPIO_PIN11 +//! - \b GPIO_PIN12 +//! - \b GPIO_PIN13 +//! - \b GPIO_PIN14 +//! - \b GPIO_PIN15 +//! \param driveStrength specifies the drive strength of the pin +//! Valid values are: +//! - \b GPIO_REDUCED_OUTPUT_DRIVE_STRENGTH +//! - \b GPIO_FULL_OUTPUT_DRIVE_STRENGTH +//! +//! Modified bits of \b PxDS register. +//! +//! \return None +// +//***************************************************************************** +void GPIO_setDriveStrength(uint8_t selectedPort, uint16_t selectedPins, + uint8_t driveStrength) +{ + + uint16_t baseAddress = GPIO_PORT_TO_BASE[selectedPort]; + + #ifndef NDEBUG + if (baseAddress == 0xFFFF) + return; + + #endif + + // Shift by 8 if port is even (upper 8-bits) + if ((selectedPort & 1) ^ 1) + selectedPins <<= 8; + + if (GPIO_REDUCED_OUTPUT_DRIVE_STRENGTH == driveStrength) + HWREG16(baseAddress + OFS_PADS) &= ~selectedPins; + else + HWREG16(baseAddress + OFS_PADS) |= selectedPins; +} + +#endif +//***************************************************************************** +// +//! Close the doxygen group for gpio_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/gpio.h b/source/driverlib/MSP430F5xx_6xx/gpio.h new file mode 100644 index 0000000..e120e7f --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/gpio.h @@ -0,0 +1,232 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// gpio.h - Driver for the GPIO Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_GPIO_H__ +#define __MSP430WARE_GPIO_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_PORT1_R__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the selectedPort parameter +// for functions: GPIO_setAsOutputPin(), GPIO_setAsInputPin(), +// GPIO_setAsPeripheralModuleFunctionOutputPin(), +// GPIO_setAsPeripheralModuleFunctionInputPin(), GPIO_setOutputHighOnPin(), +// GPIO_setOutputLowOnPin(), GPIO_toggleOutputOnPin(), +// GPIO_setAsInputPinWithPullDownResistor(), +// GPIO_setAsInputPinWithPullUpResistor(), GPIO_getInputPinValue(), +// GPIO_interruptEdgeSelect(), and GPIO_setDriveStrength(). +// +//***************************************************************************** +#define GPIO_PORT_P1 1 +#define GPIO_PORT_P2 2 +#define GPIO_PORT_P3 3 +#define GPIO_PORT_P4 4 +#define GPIO_PORT_P5 5 +#define GPIO_PORT_P6 6 +#define GPIO_PORT_P7 7 +#define GPIO_PORT_P8 8 +#define GPIO_PORT_P9 9 +#define GPIO_PORT_P10 10 +#define GPIO_PORT_P11 11 +#define GPIO_PORT_PA 1 +#define GPIO_PORT_PB 3 +#define GPIO_PORT_PC 5 +#define GPIO_PORT_PD 7 +#define GPIO_PORT_PE 9 +#define GPIO_PORT_PF 11 +#define GPIO_PORT_PJ 13 + +//***************************************************************************** +// +// The following are values that can be passed to the selectedPort parameter +// for functions: GPIO_enableInterrupt(), GPIO_disableInterrupt(), +// GPIO_getInterruptStatus(), and GPIO_clearInterruptFlag(). +// +//***************************************************************************** +#define GPIO_PORT_P1 1 +#define GPIO_PORT_P2 2 +#define GPIO_PORT_PA 1 + +//***************************************************************************** +// +// The following are values that can be passed to the selectedPins parameter +// for functions: GPIO_setAsOutputPin(), GPIO_setAsInputPin(), +// GPIO_setAsPeripheralModuleFunctionOutputPin(), +// GPIO_setAsPeripheralModuleFunctionInputPin(), GPIO_setOutputHighOnPin(), +// GPIO_setOutputLowOnPin(), GPIO_toggleOutputOnPin(), +// GPIO_setAsInputPinWithPullDownResistor(), +// GPIO_setAsInputPinWithPullUpResistor(), GPIO_getInputPinValue(), +// GPIO_enableInterrupt(), GPIO_disableInterrupt(), GPIO_getInterruptStatus(), +// GPIO_clearInterruptFlag(), GPIO_interruptEdgeSelect(), and +// GPIO_setDriveStrength() as well as returned by the GPIO_getInterruptStatus() +// function. +// +//***************************************************************************** +#define GPIO_PIN0 (0x0001) +#define GPIO_PIN1 (0x0002) +#define GPIO_PIN2 (0x0004) +#define GPIO_PIN3 (0x0008) +#define GPIO_PIN4 (0x0010) +#define GPIO_PIN5 (0x0020) +#define GPIO_PIN6 (0x0040) +#define GPIO_PIN7 (0x0080) +#define GPIO_PIN8 (0x0100) +#define GPIO_PIN9 (0x0200) +#define GPIO_PIN10 (0x0400) +#define GPIO_PIN11 (0x0800) +#define GPIO_PIN12 (0x1000) +#define GPIO_PIN13 (0x2000) +#define GPIO_PIN14 (0x4000) +#define GPIO_PIN15 (0x8000) + +//***************************************************************************** +// +// The following are values that can be passed to the edgeSelect parameter for +// functions: GPIO_interruptEdgeSelect(). +// +//***************************************************************************** +#define GPIO_HIGH_TO_LOW_TRANSITION (0x01) +#define GPIO_LOW_TO_HIGH_TRANSITION (0x00) + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the GPIO_getInputPinValue() function. +// +//***************************************************************************** +#define GPIO_INPUT_PIN_HIGH (0x01) +#define GPIO_INPUT_PIN_LOW (0x00) + +//***************************************************************************** +// +// The following are values that can be passed to the driveStrength parameter +// for functions: GPIO_setDriveStrength(). +// +//***************************************************************************** +#define GPIO_REDUCED_OUTPUT_DRIVE_STRENGTH 0x00 +#define GPIO_FULL_OUTPUT_DRIVE_STRENGTH 0x01 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void GPIO_setAsOutputPin(uint8_t selectedPort, + uint16_t selectedPins); + +extern void GPIO_setAsInputPin(uint8_t selectedPort, + uint16_t selectedPins); + +extern void GPIO_setAsPeripheralModuleFunctionOutputPin(uint8_t selectedPort, + uint16_t selectedPins); + +extern void GPIO_setAsPeripheralModuleFunctionInputPin(uint8_t selectedPort, + uint16_t selectedPins); + +extern void GPIO_setOutputHighOnPin(uint8_t selectedPort, + uint16_t selectedPins); + +extern void GPIO_setOutputLowOnPin(uint8_t selectedPort, + uint16_t selectedPins); + +extern void GPIO_toggleOutputOnPin(uint8_t selectedPort, + uint16_t selectedPins); + +extern void GPIO_setAsInputPinWithPullDownResistor(uint8_t selectedPort, + uint16_t selectedPins); + +extern void GPIO_setAsInputPinWithPullUpResistor(uint8_t selectedPort, + uint16_t selectedPins); + +extern uint8_t GPIO_getInputPinValue(uint8_t selectedPort, + uint16_t selectedPins); + +extern void GPIO_enableInterrupt(uint8_t selectedPort, + uint16_t selectedPins); + +extern void GPIO_disableInterrupt(uint8_t selectedPort, + uint16_t selectedPins); + +extern uint16_t GPIO_getInterruptStatus(uint8_t selectedPort, + uint16_t selectedPins); + +extern void GPIO_clearInterruptFlag(uint8_t selectedPort, + uint16_t selectedPins); + +extern void GPIO_interruptEdgeSelect(uint8_t selectedPort, + uint16_t selectedPins, + uint8_t edgeSelect); + +extern void GPIO_setDriveStrength(uint8_t selectedPort, + uint16_t selectedPins, + uint8_t driveStrength); + +//***************************************************************************** +// +// The following APIs are deprecated. +// +//***************************************************************************** +#define GPIO_setAsInputPinWithPullUpresistor \ + GPIO_setAsInputPinWithPullUpResistor +#define GPIO_setAsInputPinWithPullDownresistor \ + GPIO_setAsInputPinWithPullDownResistor + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_GPIO_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/inc/hw_memmap.h b/source/driverlib/MSP430F5xx_6xx/inc/hw_memmap.h new file mode 100644 index 0000000..97568b7 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/inc/hw_memmap.h @@ -0,0 +1,361 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +#ifndef __HW_MEMMAP__ +#define __HW_MEMMAP__ + +#define __DRIVERLIB_MSP430F5XX_6XX_FAMILY__ +//***************************************************************************** +// +// Include device specific header file +// +//***************************************************************************** +#include + +#if defined(__IAR_SYSTEMS_ICC__) +#include "../deprecated/IAR/msp430f5xx_6xxgeneric.h" +#elif defined(__TI_COMPILER_VERSION__) +#include "../deprecated/CCS/msp430f5xx_6xxgeneric.h" +#elif defined(__GNUC__) +#include "msp430f5xx_6xxgeneric.h" +#else +#include "msp430f5xx_6xxgeneric.h" +#endif + +#include "stdint.h" +#include "stdbool.h" + +//***************************************************************************** +// +// SUCCESS and FAILURE for API return value +// +//***************************************************************************** +#define STATUS_SUCCESS 0x01 +#define STATUS_FAIL 0x00 + +//***************************************************************************** +// +// The following are defines for the base address of the peripherals. +// +//***************************************************************************** +#ifdef __MSP430_HAS_ADC10_A__ + #define ADC10_A_BASE __MSP430_BASEADDRESS_ADC10_A__ +#endif +#ifdef __MSP430_HAS_ADC10_B__ + #define ADC10_B_BASE __MSP430_BASEADDRESS_ADC10_B__ +#endif +#ifdef __MSP430_HAS_ADC12_B__ + #define ADC12_B_BASE __MSP430_BASEADDRESS_ADC12_B__ +#endif +#ifdef __MSP430_HAS_ADC12_PLUS__ + #define ADC12_A_BASE __MSP430_BASEADDRESS_ADC12_PLUS__ +#endif +#ifdef __MSP430_HAS_AES256__ + #define AES256_BASE __MSP430_BASEADDRESS_AES256__ +#endif +#ifdef __MSP430_HAS_AES__ + #define AES_BASE __MSP430_BASEADDRESS_AES__ +#endif +#ifdef __MSP430_HAS_AUX_SUPPLY__ + #define AUX_SUPPLY_BASE __MSP430_BASEADDRESS_AUX_SUPPLY__ +#endif +#ifdef __MSP430_HAS_BACKUP_RAM__ + #define BAK_RAM_BASE __MSP430_BASEADDRESS_BACKUP_RAM__ +#endif +#ifdef __MSP430_HAS_BATTERY_CHARGER__ + #define BAK_BATT_BASE __MSP430_BASEADDRESS_BATTERY_CHARGER__ +#endif +#ifdef __MSP430_HAS_CAP_SENSE_IO_0__ + #define CAP_TOUCH_0_BASE __MSP430_BASEADDRESS_CAP_SENSE_IO_0__ +#endif +#ifdef __MSP430_HAS_CAP_SENSE_IO_1__ + #define CAP_TOUCH_1_BASE __MSP430_BASEADDRESS_CAP_SENSE_IO_1__ +#endif +#ifdef __MSP430_HAS_COMPB__ + #define COMP_B_BASE __MSP430_BASEADDRESS_COMPB__ +#endif +#ifdef __MSP430_HAS_COMPD__ + #define COMP_D_BASE __MSP430_BASEADDRESS_COMPD__ +#endif +#ifdef __MSP430_HAS_COMP_E__ + #define COMP_E_BASE __MSP430_BASEADDRESS_COMP_E__ +#endif +#ifdef __MSP430_HAS_COMP_E__ + #define __MSP430_BASEADDRESS_COMPE__ __MSP430_BASEADDRESS_COMP_E__ +#endif +#ifdef __MSP430_HAS_CRC__ + #define CRC_BASE __MSP430_BASEADDRESS_CRC__ +#endif +#ifdef __MSP430_HAS_CS__ + #define CS_BASE __MSP430_BASEADDRESS_CS__ +#endif +#ifdef __MSP430_HAS_DAC12_2__ + #define DAC12_A_BASE __MSP430_BASEADDRESS_DAC12_2__ +#endif +#ifdef __MSP430_HAS_DMAX_3__ + #define DMA_BASE __MSP430_BASEADDRESS_DMAX_3__ +#endif +#ifdef __MSP430_HAS_DMAX_6__ + #define DMA_BASE __MSP430_BASEADDRESS_DMAX_6__ +#endif +#ifdef __MSP430_HAS_EUSCI_A0__ + #define EUSCI_A0_BASE __MSP430_BASEADDRESS_EUSCI_A0__ +#endif +#ifdef __MSP430_HAS_EUSCI_A1__ + #define EUSCI_A1_BASE __MSP430_BASEADDRESS_EUSCI_A1__ +#endif +#ifdef __MSP430_HAS_EUSCI_A2__ + #define EUSCI_A2_BASE __MSP430_BASEADDRESS_EUSCI_A2__ +#endif +#ifdef __MSP430_HAS_EUSCI_A3__ + #define EUSCI_A3_BASE __MSP430_BASEADDRESS_EUSCI_A3__ +#endif +#ifdef __MSP430_HAS_EUSCI_B0__ + #define EUSCI_B0_BASE __MSP430_BASEADDRESS_EUSCI_B0__ +#endif +#ifdef __MSP430_HAS_EUSCI_B1__ + #define EUSCI_B1_BASE __MSP430_BASEADDRESS_EUSCI_B1__ +#endif +#ifdef __MSP430_HAS_FLASH__ + #define FLASH_BASE __MSP430_BASEADDRESS_FLASH__ +#endif +#ifdef __MSP430_HAS_FRAM_FR5XX__ + #define FRAM_BASE __MSP430_BASEADDRESS_FRAM_FR5XX__ +#endif +#ifdef __MSP430_HAS_FRAM__ + #define FRAM_BASE __MSP430_BASEADDRESS_FRAM__ +#endif +#ifdef __MSP430_HAS_LCD_B__ + #define LCD_B_BASE __MSP430_BASEADDRESS_LCD_B__ +#endif +#ifdef __MSP430_HAS_LCD_C__ + #define LCD_C_BASE __MSP430_BASEADDRESS_LCD_C__ +#endif +#ifdef __MSP430_HAS_MPU_A__ + #define MPU_BASE __MSP430_BASEADDRESS_MPU_A__ +#endif +#ifdef __MSP430_HAS_MPU__ + #define MPU_BASE __MSP430_BASEADDRESS_MPU__ +#endif +#ifdef __MSP430_HAS_MPY32__ + #define MPY32_BASE __MSP430_BASEADDRESS_MPY32__ +#endif +#ifdef __MSP430_HAS_PMM_FR5xx__ + #define PMM_BASE __MSP430_BASEADDRESS_PMM_FR5xx__ +#endif +#ifdef __MSP430_HAS_PMM_FRAM__ + #define PMM_BASE __MSP430_BASEADDRESS_PMM_FRAM__ +#endif +#ifdef __MSP430_HAS_PMM__ + #define PMM_BASE __MSP430_BASEADDRESS_PMM__ +#endif +#ifdef __MSP430_HAS_PORT10_R__ + #define P10_BASE __MSP430_BASEADDRESS_PORT10_R__ +#endif +#ifdef __MSP430_HAS_PORT11_R__ + #define P11_BASE __MSP430_BASEADDRESS_PORT11_R__ +#endif +#ifdef __MSP430_HAS_PORT1_MAPPING__ + #define P1MAP_BASE __MSP430_BASEADDRESS_PORT1_MAPPING__ +#endif +#ifdef __MSP430_HAS_PORT1_R__ + #define P1_BASE __MSP430_BASEADDRESS_PORT1_R__ +#endif +#ifdef __MSP430_HAS_PORT2_MAPPING__ + #define P2MAP_BASE __MSP430_BASEADDRESS_PORT2_MAPPING__ +#endif +#ifdef __MSP430_HAS_PORT2_R__ + #define P2_BASE __MSP430_BASEADDRESS_PORT2_R__ +#endif +#ifdef __MSP430_HAS_PORT3_MAPPING__ + #define P3MAP_BASE __MSP430_BASEADDRESS_PORT3_MAPPING__ +#endif +#ifdef __MSP430_HAS_PORT3_R__ + #define P3_BASE __MSP430_BASEADDRESS_PORT3_R__ +#endif +#ifdef __MSP430_HAS_PORT4_MAPPING__ + #define P4MAP_BASE __MSP430_BASEADDRESS_PORT4_MAPPING__ +#endif +#ifdef __MSP430_HAS_PORT4_R__ + #define P4_BASE __MSP430_BASEADDRESS_PORT4_R__ +#endif +#ifdef __MSP430_HAS_PORT5_R__ + #define P5_BASE __MSP430_BASEADDRESS_PORT5_R__ +#endif +#ifdef __MSP430_HAS_PORT6_R__ + #define P6_BASE __MSP430_BASEADDRESS_PORT6_R__ +#endif +#ifdef __MSP430_HAS_PORT7_R__ + #define P7_BASE __MSP430_BASEADDRESS_PORT7_R__ +#endif +#ifdef __MSP430_HAS_PORT8_R__ + #define P8_BASE __MSP430_BASEADDRESS_PORT8_R__ +#endif +#ifdef __MSP430_HAS_PORT9_R__ + #define P9_BASE __MSP430_BASEADDRESS_PORT9_R__ +#endif +#ifdef __MSP430_HAS_PORTA_R__ + #define PA_BASE __MSP430_BASEADDRESS_PORTA_R__ +#endif +#ifdef __MSP430_HAS_PORTB_R__ + #define PB_BASE __MSP430_BASEADDRESS_PORTB_R__ +#endif +#ifdef __MSP430_HAS_PORTC_R__ + #define PC_BASE __MSP430_BASEADDRESS_PORTC_R__ +#endif +#ifdef __MSP430_HAS_PORTD_R__ + #define PD_BASE __MSP430_BASEADDRESS_PORTD_R__ +#endif +#ifdef __MSP430_HAS_PORTE_R__ + #define PE_BASE __MSP430_BASEADDRESS_PORTE_R__ +#endif +#ifdef __MSP430_HAS_PORTF_R__ + #define PF_BASE __MSP430_BASEADDRESS_PORTF_R__ +#endif +#ifdef __MSP430_HAS_PORTJ_R__ + #define PJ_BASE __MSP430_BASEADDRESS_PORTJ_R__ +#endif +#ifdef __MSP430_HAS_PORT_MAPPING__ + #define PMAP_CTRL_BASE __MSP430_BASEADDRESS_PORT_MAPPING__ +#endif +#ifdef __MSP430_HAS_PU__ + #define LDOPWR_BASE __MSP430_BASEADDRESS_PU__ +#endif +#ifdef __MSP430_HAS_RC__ + #define RAM_BASE __MSP430_BASEADDRESS_RC__ +#endif +#ifdef __MSP430_HAS_REF_A__ + #define REF_A_BASE __MSP430_BASEADDRESS_REF_A__ +#endif +#ifdef __MSP430_HAS_REF__ + #define REF_BASE __MSP430_BASEADDRESS_REF__ +#endif +#ifdef __MSP430_HAS_RTC_B__ + #define RTC_B_BASE __MSP430_BASEADDRESS_RTC_B__ +#endif +#ifdef __MSP430_HAS_RTC_C__ + #define RTC_C_BASE __MSP430_BASEADDRESS_RTC_C__ +#endif +#ifdef __MSP430_HAS_RTC_D__ + #define RTC_D_BASE __MSP430_BASEADDRESS_RTC_D__ +#endif +#ifdef __MSP430_HAS_RTC__ + #define RTC_A_BASE __MSP430_BASEADDRESS_RTC__ +#endif +#ifdef __MSP430_HAS_SD24_B__ + #define SD24_BASE __MSP430_BASEADDRESS_SD24_B__ +#endif +#ifdef __MSP430_HAS_SFR__ + #define SFR_BASE __MSP430_BASEADDRESS_SFR__ +#endif +#ifdef __MSP430_HAS_SYS__ + #define SYS_BASE __MSP430_BASEADDRESS_SYS__ +#endif +#ifdef __MSP430_HAS_T0A3__ + #define TIMER_A0_BASE __MSP430_BASEADDRESS_T0A3__ +#endif +#ifdef __MSP430_HAS_T0A5__ + #define TIMER_A0_BASE __MSP430_BASEADDRESS_T0A5__ +#endif +#ifdef __MSP430_HAS_T0B3__ + #define TIMER_B0_BASE __MSP430_BASEADDRESS_T0B3__ +#endif +#ifdef __MSP430_HAS_T0B7__ + #define TIMER_B0_BASE __MSP430_BASEADDRESS_T0B7__ +#endif +#ifdef __MSP430_HAS_T0D3__ + #define TIMER_D0_BASE __MSP430_BASEADDRESS_T0D3__ +#endif +#ifdef __MSP430_HAS_T1A2__ + #define TIMER_A1_BASE __MSP430_BASEADDRESS_T1A2__ +#endif +#ifdef __MSP430_HAS_T1A3__ + #define TIMER_A1_BASE __MSP430_BASEADDRESS_T1A3__ +#endif +#ifdef __MSP430_HAS_T1B3__ + #define TIMER_B1_BASE __MSP430_BASEADDRESS_T1B3__ +#endif +#ifdef __MSP430_HAS_T1D3__ + #define TIMER_D1_BASE __MSP430_BASEADDRESS_T1D3__ +#endif +#ifdef __MSP430_HAS_T2A2__ + #define TIMER_A2_BASE __MSP430_BASEADDRESS_T2A2__ +#endif +#ifdef __MSP430_HAS_T2A3__ + #define TIMER_A2_BASE __MSP430_BASEADDRESS_T2A3__ +#endif +#ifdef __MSP430_HAS_T2B3__ + #define TIMER_B2_BASE __MSP430_BASEADDRESS_T2B3__ +#endif +#ifdef __MSP430_HAS_T3A2__ + #define TIMER_A3_BASE __MSP430_BASEADDRESS_T3A2__ +#endif +#ifdef __MSP430_HAS_TEV0__ + #define TEC0_BASE __MSP430_BASEADDRESS_TEV0__ +#endif +#ifdef __MSP430_HAS_TEV1__ + #define TEC1_BASE __MSP430_BASEADDRESS_TEV1__ +#endif +#ifdef __MSP430_HAS_UCS__ + #define UCS_BASE __MSP430_BASEADDRESS_UCS__ +#endif +#ifdef __MSP430_HAS_USB__ + #define USB_BASE __MSP430_BASEADDRESS_USB__ +#endif +#ifdef __MSP430_HAS_USCI_A0__ + #define USCI_A0_BASE __MSP430_BASEADDRESS_USCI_A0__ +#endif +#ifdef __MSP430_HAS_USCI_A1__ + #define USCI_A1_BASE __MSP430_BASEADDRESS_USCI_A1__ +#endif +#ifdef __MSP430_HAS_USCI_A2__ + #define USCI_A2_BASE __MSP430_BASEADDRESS_USCI_A2__ +#endif +#ifdef __MSP430_HAS_USCI_A3__ + #define USCI_A3_BASE __MSP430_BASEADDRESS_USCI_A3__ +#endif +#ifdef __MSP430_HAS_USCI_B0__ + #define USCI_B0_BASE __MSP430_BASEADDRESS_USCI_B0__ +#endif +#ifdef __MSP430_HAS_USCI_B1__ + #define USCI_B1_BASE __MSP430_BASEADDRESS_USCI_B1__ +#endif +#ifdef __MSP430_HAS_USCI_B2__ + #define USCI_B2_BASE __MSP430_BASEADDRESS_USCI_B2__ +#endif +#ifdef __MSP430_HAS_USCI_B3__ + #define USCI_B3_BASE __MSP430_BASEADDRESS_USCI_B3__ +#endif +#ifdef __MSP430_HAS_WDT_A__ + #define WDT_A_BASE __MSP430_BASEADDRESS_WDT_A__ +#endif + +#endif // #ifndef __HW_MEMMAP__ diff --git a/source/driverlib/MSP430F5xx_6xx/inc/hw_regaccess.h b/source/driverlib/MSP430F5xx_6xx/inc/hw_regaccess.h new file mode 100644 index 0000000..4e67298 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/inc/hw_regaccess.h @@ -0,0 +1,64 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +#ifndef __HW_REGACCESS__ +#define __HW_REGACCESS__ + +#include "stdint.h" +#include "stdbool.h" + +//***************************************************************************** +// +// Macro for enabling assert statements for debugging +// +//***************************************************************************** +#define NDEBUG +//***************************************************************************** +// +// Macros for hardware access +// +//***************************************************************************** +#define HWREG32(x) \ + (*((volatile uint32_t*)((uint16_t)x))) +#define HWREG16(x) \ + (*((volatile uint16_t*)((uint16_t)x))) +#define HWREG8(x) \ + (*((volatile uint8_t*)((uint16_t)x))) + +//***************************************************************************** +// +// SUCCESS and FAILURE for API return value +// +//***************************************************************************** +#define STATUS_SUCCESS 0x01 +#define STATUS_FAIL 0x00 + +#endif // #ifndef __HW_REGACCESS__ diff --git a/source/driverlib/MSP430F5xx_6xx/inc/hw_types.h b/source/driverlib/MSP430F5xx_6xx/inc/hw_types.h new file mode 100644 index 0000000..7734c76 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/inc/hw_types.h @@ -0,0 +1,61 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +#ifndef __HW_TYPES__ +#define __HW_TYPES__ + +//***************************************************************************** +// +// Macro for enabling assert statements for debugging +// +//***************************************************************************** +#define NDEBUG + +//***************************************************************************** +// +// Macros for hardware access +// +//***************************************************************************** +#define HWREG(x) \ + (*((volatile unsigned int*)(x))) +#define HWREGB(x) \ + (*((volatile unsigned char*)(x))) + + +//***************************************************************************** +// +// SUCCESS and FAILURE for API return value +// +//***************************************************************************** +#define STATUS_SUCCESS 0x01 +#define STATUS_FAIL 0x00 + +#endif // #ifndef __HW_TYPES__ diff --git a/source/driverlib/MSP430F5xx_6xx/inc/version.h b/source/driverlib/MSP430F5xx_6xx/inc/version.h new file mode 100644 index 0000000..f863ca3 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/inc/version.h @@ -0,0 +1,42 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +#ifndef __DRIVERLIB_VERSION__ + #define DRIVERLIB_VER_MAJOR 1 + #define DRIVERLIB_VER_MINOR 90 + #define DRIVERLIB_VER_PATCH 00 + #define DRIVERLIB_VER_BUILD 65 +#endif + +#define getVersion() ((uint32_t)DRIVERLIB_VER_MAJOR << 24 | \ + (uint32_t)DRIVERLIB_VER_MINOR << 16 | \ + (uint32_t)DRIVERLIB_VER_PATCH << 8 | \ + (uint32_t)DRIVERLIB_VER_BUILD) diff --git a/source/driverlib/MSP430F5xx_6xx/ldopwr.c b/source/driverlib/MSP430F5xx_6xx/ldopwr.c new file mode 100644 index 0000000..92bdef0 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/ldopwr.c @@ -0,0 +1,517 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// ldopwr.c - Driver for the ldopwr Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup ldopwr_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_PU__ +#include "ldopwr.h" + +#include + +//***************************************************************************** +// +//! \brief Unlocks the configuration registers and enables write access +//! +//! \param baseAddress is the base address of the LDOPWR module. +//! +//! Modified bits of \b LDOKEYPID register. +//! +//! \return None +// +//***************************************************************************** +void LDOPWR_unLockConfiguration( uint16_t baseAddress ) +{ + HWREG16(baseAddress + OFS_LDOKEYPID) = 0x9628; +} + +//***************************************************************************** +// +//! \brief Locks the configuration registers and disables write access +//! +//! \param baseAddress is the base address of the LDOPWR module. +//! +//! Modified bits of \b LDOKEYPID register. +//! +//! \return None +// +//***************************************************************************** +void LDOPWR_lockConfiguration( uint16_t baseAddress ) +{ + HWREG16(baseAddress + OFS_LDOKEYPID) = 0x0000; +} + +//***************************************************************************** +// +//! \brief Enables Port U inputs +//! +//! \param baseAddress is the base address of the LDOPWR module. +//! +//! Modified bits of \b PUCTL register. +//! +//! \return None +// +//***************************************************************************** +void LDOPWR_enablePort_U_inputs(uint16_t baseAddress ) +{ + HWREG8(baseAddress + OFS_PUCTL_H) |= PUIPE_H; +} + +//***************************************************************************** +// +//! \brief Disables Port U inputs +//! +//! \param baseAddress is the base address of the LDOPWR module. +//! +//! Modified bits of \b PUCTL register. +//! +//! \return None +// +//***************************************************************************** +void LDOPWR_disablePort_U_inputs(uint16_t baseAddress ) +{ + HWREG8(baseAddress + OFS_PUCTL_H) &= ~PUIPE_H; +} + +//***************************************************************************** +// +//! \brief Enables Port U outputs +//! +//! \param baseAddress is the base address of the LDOPWR module. +//! +//! Modified bits of \b PUCTL register. +//! +//! \return None +// +//***************************************************************************** +void LDOPWR_enablePort_U_outputs(uint16_t baseAddress ) +{ + HWREG8(baseAddress + OFS_PUCTL_L) |= PUOPE; +} + +//***************************************************************************** +// +//! \brief Disables Port U inputs +//! +//! \param baseAddress is the base address of the LDOPWR module. +//! +//! Modified bits of \b PUCTL register. +//! +//! \return None +// +//***************************************************************************** +void LDOPWR_disablePort_U_outputs(uint16_t baseAddress ) +{ + HWREG8(baseAddress + OFS_PUCTL_L) &= ~PUOPE; +} + +//***************************************************************************** +// +//! \brief Returns PU.1 input data +//! +//! \param baseAddress is the base address of the LDOPWR module. +//! +//! \return One of the following: +//! - \b LDOPWR_PORTU_PIN_HIGH +//! - \b LDOPWR_PORTU_PIN_LOW +// +//***************************************************************************** +uint8_t LDOPWR_getPort_U1_inputData(uint16_t baseAddress ) +{ + return (HWREG8(baseAddress + OFS_PUCTL_L) & PUIN1) >> 3; +} + +//***************************************************************************** +// +//! \brief Returns PU.0 input data +//! +//! \param baseAddress is the base address of the LDOPWR module. +//! +//! \return One of the following: +//! - \b LDOPWR_PORTU_PIN_HIGH +//! - \b LDOPWR_PORTU_PIN_LOW +// +//***************************************************************************** +uint8_t LDOPWR_getPort_U0_inputData(uint16_t baseAddress ) +{ + return (HWREG8(baseAddress + OFS_PUCTL_L) & PUIN0) >> 2; +} + +//***************************************************************************** +// +//! \brief Returns PU.1 output data +//! +//! \param baseAddress is the base address of the LDOPWR module. +//! +//! \return One of the following: +//! - \b LDOPWR_PORTU_PIN_HIGH +//! - \b LDOPWR_PORTU_PIN_LOW +// +//***************************************************************************** +uint8_t LDOPWR_getPort_U1_outputData(uint16_t baseAddress ) +{ + return (HWREG8(baseAddress + OFS_PUCTL_L) & PUOUT1) >> 1; +} + +//***************************************************************************** +// +//! \brief Returns PU.0 output data +//! +//! \param baseAddress is the base address of the LDOPWR module. +//! +//! \return One of the following: +//! - \b LDOPWR_PORTU_PIN_HIGH +//! - \b LDOPWR_PORTU_PIN_LOW +// +//***************************************************************************** +uint8_t LDOPWR_getPort_U0_outputData(uint16_t baseAddress ) +{ + return HWREG8(baseAddress + OFS_PUCTL_L) & PUOUT0; +} + +//***************************************************************************** +// +//! \brief Sets PU.1 output data +//! +//! \param baseAddress is the base address of the LDOPWR module. +//! \param value +//! Valid values are: +//! - \b LDOPWR_PORTU_PIN_HIGH +//! - \b LDOPWR_PORTU_PIN_LOW +//! +//! Modified bits of \b PUCTL register. +//! +//! \return None +// +//***************************************************************************** +void LDOPWR_setPort_U1_outputData(uint16_t baseAddress, + uint8_t value + ) +{ + if (LDOPWR_PORTU_PIN_HIGH == value) + HWREG8(baseAddress + OFS_PUCTL_L) |= PUOUT1; + else + HWREG8(baseAddress + OFS_PUCTL_L) &= ~PUOUT1; +} + +//***************************************************************************** +// +//! \brief Sets PU.0 output data +//! +//! \param baseAddress is the base address of the LDOPWR module. +//! \param value +//! Valid values are: +//! - \b LDOPWR_PORTU_PIN_HIGH +//! - \b LDOPWR_PORTU_PIN_LOW +//! +//! Modified bits of \b PUCTL register. +//! +//! \return None +// +//***************************************************************************** +void LDOPWR_setPort_U0_outputData(uint16_t baseAddress, + uint8_t value + ) +{ + if (LDOPWR_PORTU_PIN_HIGH == value) + HWREG8(baseAddress + OFS_PUCTL_L) |= PUOUT0; + else + HWREG8(baseAddress + OFS_PUCTL_L) &= ~PUOUT0; +} + +//***************************************************************************** +// +//! \brief Toggles PU.1 output data +//! +//! \param baseAddress is the base address of the LDOPWR module. +//! +//! Modified bits of \b PUCTL register. +//! +//! \return None +// +//***************************************************************************** +void LDOPWR_togglePort_U1_outputData(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_PUCTL_L) ^= PUOUT1; +} + +//***************************************************************************** +// +//! \brief Toggles PU.0 output data +//! +//! \param baseAddress is the base address of the LDOPWR module. +//! +//! Modified bits of \b PUCTL register. +//! +//! \return None +// +//***************************************************************************** +void LDOPWR_togglePort_U0_outputData(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_PUCTL_L) ^= PUOUT0; +} + +//***************************************************************************** +// +//! \brief Enables LDO-PWR module interrupts +//! +//! Does not clear interrupt flags. +//! +//! \param baseAddress is the base address of the LDOPWR module. +//! \param mask mask of interrupts to enable +//! Mask value is the logical OR of any of the following: +//! - \b LDOPWR_LDOI_VOLTAGE_GOING_OFF_INTERRUPT +//! - \b LDOPWR_LDOI_VOLTAGE_COMING_ON_INTERRUPT +//! - \b LDOPWR_LDO_OVERLOAD_INDICATION_INTERRUPT +//! +//! Modified bits of \b LDOPWRCTL register. +//! +//! \return None +// +//***************************************************************************** +void LDOPWR_enableInterrupt(uint16_t baseAddress, + uint16_t mask + ) +{ + assert(0x00 == (mask & ~(LDOPWR_LDOI_VOLTAGE_GOING_OFF_INTERRUPT + + LDOPWR_LDOI_VOLTAGE_COMING_ON_INTERRUPT + + LDOPWR_LDO_OVERLOAD_INDICATION_INTERRUPT + ) + ) + ); + HWREG8(baseAddress + OFS_LDOPWRCTL_H) |= mask; +} + +//***************************************************************************** +// +//! \brief Disables LDO-PWR module interrupts +//! +//! \param baseAddress is the base address of the LDOPWR module. +//! \param mask mask of interrupts to disable +//! Mask value is the logical OR of any of the following: +//! - \b LDOPWR_LDOI_VOLTAGE_GOING_OFF_INTERRUPT +//! - \b LDOPWR_LDOI_VOLTAGE_COMING_ON_INTERRUPT +//! - \b LDOPWR_LDO_OVERLOAD_INDICATION_INTERRUPT +//! +//! Modified bits of \b LDOPWRCTL register. +//! +//! \return None +// +//***************************************************************************** +void LDOPWR_disableInterrupt(uint16_t baseAddress, + uint16_t mask + ) +{ + assert(0x00 == (mask & ~(LDOPWR_LDOI_VOLTAGE_GOING_OFF_INTERRUPT + + LDOPWR_LDOI_VOLTAGE_COMING_ON_INTERRUPT + + LDOPWR_LDO_OVERLOAD_INDICATION_INTERRUPT + ) + ) + ); + HWREG8(baseAddress + OFS_LDOPWRCTL_H) &= ~mask; +} + +//***************************************************************************** +// +//! \brief Enables LDO-PWR module +//! +//! \param baseAddress is the base address of the LDOPWR module. +//! +//! Modified bits of \b LDOPWRCTL register. +//! +//! \return None +// +//***************************************************************************** +void LDOPWR_enable(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_LDOPWRCTL_H) |= LDOOEN_H; +} + +//***************************************************************************** +// +//! \brief Disables LDO-PWR module +//! +//! \param baseAddress is the base address of the LDOPWR module. +//! +//! Modified bits of \b LDOPWRCTL register. +//! +//! \return None +// +//***************************************************************************** +void LDOPWR_disable(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_LDOPWRCTL_H) &= ~LDOOEN_H; +} + +//***************************************************************************** +// +//! \brief Returns the interrupt status of LDO-PWR module interrupts +//! +//! \param baseAddress is the base address of the LDOPWR module. +//! \param mask mask of interrupts to get the status of +//! Mask value is the logical OR of any of the following: +//! - \b LDOPWR_LDOI_VOLTAGE_GOING_OFF_INTERRUPT +//! - \b LDOPWR_LDOI_VOLTAGE_COMING_ON_INTERRUPT +//! - \b LDOPWR_LDO_OVERLOAD_INDICATION_INTERRUPT +//! +//! \return Logical OR of any of the following: +//! - \b LDOPWR_LDOI_VOLTAGE_GOING_OFF_INTERRUPT +//! - \b LDOPWR_LDOI_VOLTAGE_COMING_ON_INTERRUPT +//! - \b LDOPWR_LDO_OVERLOAD_INDICATION_INTERRUPT +//! \n indicating the status of the masked interrupts +// +//***************************************************************************** +uint8_t LDOPWR_getInterruptStatus(uint16_t baseAddress, + uint16_t mask + ) +{ + assert(0x00 == (mask & ~(LDOPWR_LDOI_VOLTAGE_GOING_OFF_INTERRUPT + + LDOPWR_LDOI_VOLTAGE_COMING_ON_INTERRUPT + + LDOPWR_LDO_OVERLOAD_INDICATION_INTERRUPT + ) + ) + ); + return HWREG8(baseAddress + OFS_LDOPWRCTL_L) & mask; +} + +//***************************************************************************** +// +//! \brief Clears the interrupt status of LDO-PWR module interrupts +//! +//! \param baseAddress is the base address of the LDOPWR module. +//! \param mask mask of interrupts to clear the status of +//! Mask value is the logical OR of any of the following: +//! - \b LDOPWR_LDOI_VOLTAGE_GOING_OFF_INTERRUPT +//! - \b LDOPWR_LDOI_VOLTAGE_COMING_ON_INTERRUPT +//! - \b LDOPWR_LDO_OVERLOAD_INDICATION_INTERRUPT +//! +//! Modified bits of \b LDOPWRCTL register. +//! +//! \return None +// +//***************************************************************************** +void LDOPWR_clearInterruptStatus(uint16_t baseAddress, + uint16_t mask + ) +{ + assert(0x00 == (mask & ~(LDOPWR_LDOI_VOLTAGE_GOING_OFF_INTERRUPT + + LDOPWR_LDOI_VOLTAGE_COMING_ON_INTERRUPT + + LDOPWR_LDO_OVERLOAD_INDICATION_INTERRUPT + ) + ) + ); + HWREG8(baseAddress + OFS_LDOPWRCTL_L) &= ~mask; +} + +//***************************************************************************** +// +//! \brief Returns if the the LDOI is valid and within bounds +//! +//! \param baseAddress is the base address of the LDOPWR module. +//! +//! \return One of the following: +//! - \b LDOPWR_LDO_INPUT_VALID +//! - \b LDOPWR_LDO_INPUT_INVALID +// +//***************************************************************************** +uint8_t LDOPWR_isLDOInputValid(uint16_t baseAddress) +{ + return HWREG8(baseAddress + OFS_LDOPWRCTL_L) & LDOBGVBV; +} + +//***************************************************************************** +// +//! \brief Enables the LDO overload auto-off +//! +//! \param baseAddress is the base address of the LDOPWR module. +//! +//! Modified bits of \b LDOPWRCTL register. +//! +//! \return None +// +//***************************************************************************** +void LDOPWR_enableOverloadAutoOff(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_LDOPWRCTL_L) |= OVLAOFF_L; +} + +//***************************************************************************** +// +//! \brief Disables the LDO overload auto-off +//! +//! \param baseAddress is the base address of the LDOPWR module. +//! +//! Modified bits of \b LDOPWRCTL register. +//! +//! \return None +// +//***************************************************************************** +void LDOPWR_disableOverloadAutoOff(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_LDOPWRCTL_L) &= ~OVLAOFF_L; +} + +//***************************************************************************** +// +//! \brief Returns if the LDOI overload auto-off is enabled or disabled +//! +//! \param baseAddress is the base address of the LDOPWR module. +//! +//! \return One of the following: +//! - \b LDOPWR_AUTOOFF_ENABLED +//! - \b LDOPWR_AUTOOFF_DISABLED +// +//***************************************************************************** +uint8_t LDOPWR_getOverloadAutoOffStatus(uint16_t baseAddress) +{ + return HWREG8(baseAddress + OFS_LDOPWRCTL_L) & OVLAOFF_L; +} + +#endif +//***************************************************************************** +// +//! Close the doxygen group for ldopwr_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/ldopwr.h b/source/driverlib/MSP430F5xx_6xx/ldopwr.h new file mode 100644 index 0000000..ad1e886 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/ldopwr.h @@ -0,0 +1,168 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// ldopwr.h - Driver for the LDOPWR Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_LDOPWR_H__ +#define __MSP430WARE_LDOPWR_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_PU__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the value parameter for +// functions: LDOPWR_setPort_U1_outputData(), and +// LDOPWR_setPort_U0_outputData() as well as returned by the +// LDOPWR_getPort_U1_inputData() function, the LDOPWR_getPort_U0_inputData() +// function, the LDOPWR_getPort_U1_outputData() function and the +// LDOPWR_getPort_U0_outputData() function. +// +//***************************************************************************** +#define LDOPWR_PORTU_PIN_HIGH PUOUT0 +#define LDOPWR_PORTU_PIN_LOW 0x00 + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the LDOPWR_isLDOInputValid() function. +// +//***************************************************************************** +#define LDOPWR_LDO_INPUT_VALID LDOBGVBV +#define LDOPWR_LDO_INPUT_INVALID 0x00 + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the LDOPWR_getOverloadAutoOffStatus() function. +// +//***************************************************************************** +#define LDOPWR_AUTOOFF_ENABLED OVLAOFF_H +#define LDOPWR_AUTOOFF_DISABLED 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the mask parameter for +// functions: LDOPWR_enableInterrupt(), LDOPWR_disableInterrupt(), +// LDOPWR_getInterruptStatus(), and LDOPWR_clearInterruptStatus() as well as +// returned by the LDOPWR_getInterruptStatus() function. +// +//***************************************************************************** +#define LDOPWR_LDOI_VOLTAGE_GOING_OFF_INTERRUPT LDOOFFIE_H +#define LDOPWR_LDOI_VOLTAGE_COMING_ON_INTERRUPT LDOONIE_H +#define LDOPWR_LDO_OVERLOAD_INDICATION_INTERRUPT LDOOVLIE_H + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void LDOPWR_unLockConfiguration(uint16_t baseAddress); + +extern void LDOPWR_lockConfiguration(uint16_t baseAddress); + +extern void LDOPWR_enablePort_U_inputs(uint16_t baseAddress); + +extern void LDOPWR_disablePort_U_inputs(uint16_t baseAddress); + +extern void LDOPWR_enablePort_U_outputs(uint16_t baseAddress); + +extern void LDOPWR_disablePort_U_outputs(uint16_t baseAddress); + +extern uint8_t LDOPWR_getPort_U1_inputData(uint16_t baseAddress); + +extern uint8_t LDOPWR_getPort_U0_inputData(uint16_t baseAddress); + +extern uint8_t LDOPWR_getPort_U1_outputData(uint16_t baseAddress); + +extern uint8_t LDOPWR_getPort_U0_outputData(uint16_t baseAddress); + +extern void LDOPWR_setPort_U1_outputData(uint16_t baseAddress, + uint8_t value); + +extern void LDOPWR_setPort_U0_outputData(uint16_t baseAddress, + uint8_t value); + +extern void LDOPWR_togglePort_U1_outputData(uint16_t baseAddress); + +extern void LDOPWR_togglePort_U0_outputData(uint16_t baseAddress); + +extern void LDOPWR_enableInterrupt(uint16_t baseAddress, + uint16_t mask); + +extern void LDOPWR_disableInterrupt(uint16_t baseAddress, + uint16_t mask); + +extern void LDOPWR_enable(uint16_t baseAddress); + +extern void LDOPWR_disable(uint16_t baseAddress); + +extern uint8_t LDOPWR_getInterruptStatus(uint16_t baseAddress, + uint16_t mask); + +extern void LDOPWR_clearInterruptStatus(uint16_t baseAddress, + uint16_t mask); + +extern uint8_t LDOPWR_isLDOInputValid(uint16_t baseAddress); + +extern void LDOPWR_enableOverloadAutoOff(uint16_t baseAddress); + +extern void LDOPWR_disableOverloadAutoOff(uint16_t baseAddress); + +extern uint8_t LDOPWR_getOverloadAutoOffStatus(uint16_t baseAddress); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_LDOPWR_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/mpy32.c b/source/driverlib/MSP430F5xx_6xx/mpy32.c new file mode 100644 index 0000000..aed810f --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/mpy32.c @@ -0,0 +1,565 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// mpy32.c - Driver for the mpy32 Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup mpy32_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifndef DRIVERLIB_LEGACY_MODE + +#ifdef __MSP430_HAS_MPY32__ +#include "mpy32.h" + +#include + +//***************************************************************************** +// +//! \brief Sets the write delay setting for the MPY32 module. +//! +//! This function sets up a write delay to the MPY module's registers, which +//! holds any writes to the registers until all calculations are complete. +//! There are two different settings, one which waits for 32-bit results to be +//! ready, and one which waits for 64-bit results to be ready. This prevents +//! unpredicatble results if registers are changed before the results are +//! ready. +//! +//! \param writeDelaySelect delays the write to any MPY32 register until the +//! selected bit size of result has been written. +//! Valid values are: +//! - \b MPY32_WRITEDELAY_OFF [Default] - writes are not delayed +//! - \b MPY32_WRITEDELAY_32BIT - writes are delayed until a 32-bit +//! result is available in the result registers +//! - \b MPY32_WRITEDELAY_64BIT - writes are delayed until a 64-bit +//! result is available in the result registers +//! \n Modified bits are \b MPYDLY32 and \b MPYDLYWRTEN of \b MPY32CTL0 +//! register. +//! +//! \return None +// +//***************************************************************************** +void MPY32_setWriteDelay(uint16_t writeDelaySelect) +{ + HWREG16(MPY32_BASE + OFS_MPY32CTL0) &= ~(MPYDLY32 + MPYDLYWRTEN); + HWREG16(MPY32_BASE + OFS_MPY32CTL0) |= writeDelaySelect; +} + +//***************************************************************************** +// +//! \brief Enables Saturation Mode. +//! +//! This function enables saturation mode. When this is enabled, the result +//! read out from the MPY result registers is converted to the most-positive +//! number in the case of an overflow, or the most-negative number in the case +//! of an underflow. Please note, that the raw value in the registers does not +//! reflect the result returned, and if the saturation mode is disabled, then +//! the raw value of the registers will be returned instead. +//! +//! +//! \return None +// +//***************************************************************************** +void MPY32_enableSaturationMode(void) +{ + HWREG8(MPY32_BASE + OFS_MPY32CTL0_L) |= MPYSAT; +} + +//***************************************************************************** +// +//! \brief Disables Saturation Mode. +//! +//! This function disables saturation mode, which allows the raw result of the +//! MPY result registers to be returned. +//! +//! +//! \return None +// +//***************************************************************************** +void MPY32_disableSaturationMode(void) +{ + HWREG8(MPY32_BASE + OFS_MPY32CTL0_L) &= ~(MPYSAT); +} + +//***************************************************************************** +// +//! \brief Gets the Saturation Mode. +//! +//! This function gets the current saturation mode. +//! +//! +//! \return Gets the Saturation Mode +//! Return one of the following: +//! - \b MPY32_SATURATION_MODE_DISABLED +//! - \b MPY32_SATURATION_MODE_ENABLED +//! \n Gets the Saturation Mode +// +//***************************************************************************** +uint8_t MPY32_getSaturationMode(void) +{ + return HWREG8(MPY32_BASE + OFS_MPY32CTL0_L) & (MPYSAT); +} + +//***************************************************************************** +// +//! \brief Enables Fraction Mode. +//! +//! This function enables fraction mode. +//! +//! +//! \return None +// +//***************************************************************************** +void MPY32_enableFractionalMode(void) +{ + HWREG8(MPY32_BASE + OFS_MPY32CTL0_L) |= MPYFRAC; +} + +//***************************************************************************** +// +//! \brief Disables Fraction Mode. +//! +//! This function disables fraction mode. +//! +//! +//! \return None +// +//***************************************************************************** +void MPY32_disableFractionalMode(void) +{ + HWREG8(MPY32_BASE + OFS_MPY32CTL0_L) &= ~(MPYFRAC); +} + +//***************************************************************************** +// +//! \brief Gets the Fractional Mode. +//! +//! This function gets the current fractional mode. +//! +//! +//! \return Gets the fractional mode +//! Return one of the following: +//! - \b MPY32_FRACTIONAL_MODE_DISABLED +//! - \b MPY32_FRACTIONAL_MODE_ENABLED +//! \n Gets the Fractional Mode +// +//***************************************************************************** +uint8_t MPY32_getFractionalMode(void) +{ + return HWREG8(MPY32_BASE + OFS_MPY32CTL0_L) & (MPYFRAC); +} + +//***************************************************************************** +// +//! \brief Sets an 8-bit value into operand 1. +//! +//! This function sets the first operand for multiplication and determines what +//! type of operation should be performed. Once the second operand is set, then +//! the operation will begin. +//! +//! \param multiplicationType is the type of multiplication to perform once the +//! second operand is set. +//! Valid values are: +//! - \b MPY32_MULTIPLY_UNSIGNED +//! - \b MPY32_MULTIPLY_SIGNED +//! - \b MPY32_MULTIPLYACCUMULATE_UNSIGNED +//! - \b MPY32_MULTIPLYACCUMULATE_SIGNED +//! \param operand is the 8-bit value to load into the 1st operand. +//! +//! \return None +// +//***************************************************************************** +void MPY32_setOperandOne8Bit(uint8_t multiplicationType, + uint8_t operand) +{ + HWREG8(MPY32_BASE + OFS_MPY + multiplicationType) = operand; +} + +//***************************************************************************** +// +//! \brief Sets an 16-bit value into operand 1. +//! +//! This function sets the first operand for multiplication and determines what +//! type of operation should be performed. Once the second operand is set, then +//! the operation will begin. +//! +//! \param multiplicationType is the type of multiplication to perform once the +//! second operand is set. +//! Valid values are: +//! - \b MPY32_MULTIPLY_UNSIGNED +//! - \b MPY32_MULTIPLY_SIGNED +//! - \b MPY32_MULTIPLYACCUMULATE_UNSIGNED +//! - \b MPY32_MULTIPLYACCUMULATE_SIGNED +//! \param operand is the 16-bit value to load into the 1st operand. +//! +//! \return None +// +//***************************************************************************** +void MPY32_setOperandOne16Bit(uint8_t multiplicationType, + uint16_t operand) +{ + HWREG16(MPY32_BASE + OFS_MPY + multiplicationType) = operand; +} + +//***************************************************************************** +// +//! \brief Sets an 24-bit value into operand 1. +//! +//! This function sets the first operand for multiplication and determines what +//! type of operation should be performed. Once the second operand is set, then +//! the operation will begin. +//! +//! \param multiplicationType is the type of multiplication to perform once the +//! second operand is set. +//! Valid values are: +//! - \b MPY32_MULTIPLY_UNSIGNED +//! - \b MPY32_MULTIPLY_SIGNED +//! - \b MPY32_MULTIPLYACCUMULATE_UNSIGNED +//! - \b MPY32_MULTIPLYACCUMULATE_SIGNED +//! \param operand is the 24-bit value to load into the 1st operand. +//! +//! \return None +// +//***************************************************************************** +void MPY32_setOperandOne24Bit(uint8_t multiplicationType, + uint32_t operand) +{ + multiplicationType <<= 1; + HWREG16(MPY32_BASE + OFS_MPY32L + multiplicationType) = operand; + HWREG8(MPY32_BASE + OFS_MPY32H + multiplicationType) = (operand >> 16); +} + +//***************************************************************************** +// +//! \brief Sets an 32-bit value into operand 1. +//! +//! This function sets the first operand for multiplication and determines what +//! type of operation should be performed. Once the second operand is set, then +//! the operation will begin. +//! +//! \param multiplicationType is the type of multiplication to perform once the +//! second operand is set. +//! Valid values are: +//! - \b MPY32_MULTIPLY_UNSIGNED +//! - \b MPY32_MULTIPLY_SIGNED +//! - \b MPY32_MULTIPLYACCUMULATE_UNSIGNED +//! - \b MPY32_MULTIPLYACCUMULATE_SIGNED +//! \param operand is the 32-bit value to load into the 1st operand. +//! +//! \return None +// +//***************************************************************************** +void MPY32_setOperandOne32Bit(uint8_t multiplicationType, + uint32_t operand) +{ + multiplicationType <<= 1; + HWREG16(MPY32_BASE + OFS_MPY32L + multiplicationType) = operand; + HWREG16(MPY32_BASE + OFS_MPY32H + multiplicationType) = (operand >> 16); +} + +//***************************************************************************** +// +//! \brief Sets an 8-bit value into operand 2, which starts the multiplication. +//! +//! This function sets the second operand of the multiplication operation and +//! starts the operation. +//! +//! \param operand is the 8-bit value to load into the 2nd operand. +//! +//! \return None +// +//***************************************************************************** +void MPY32_setOperandTwo8Bit(uint8_t operand) +{ + HWREG8(MPY32_BASE + OFS_OP2) = operand; +} + +//***************************************************************************** +// +//! \brief Sets an 16-bit value into operand 2, which starts the +//! multiplication. +//! +//! This function sets the second operand of the multiplication operation and +//! starts the operation. +//! +//! \param operand is the 16-bit value to load into the 2nd operand. +//! +//! \return None +// +//***************************************************************************** +void MPY32_setOperandTwo16Bit(uint16_t operand) +{ + HWREG16(MPY32_BASE + OFS_OP2) = operand; +} + +//***************************************************************************** +// +//! \brief Sets an 24-bit value into operand 2, which starts the +//! multiplication. +//! +//! This function sets the second operand of the multiplication operation and +//! starts the operation. +//! +//! \param operand is the 24-bit value to load into the 2nd operand. +//! +//! \return None +// +//***************************************************************************** +void MPY32_setOperandTwo24Bit(uint32_t operand) +{ + HWREG16(MPY32_BASE + OFS_OP2L) = operand; + HWREG8(MPY32_BASE + OFS_OP2H) = (operand >> 16); +} + +//***************************************************************************** +// +//! \brief Sets an 32-bit value into operand 2, which starts the +//! multiplication. +//! +//! This function sets the second operand of the multiplication operation and +//! starts the operation. +//! +//! \param operand is the 32-bit value to load into the 2nd operand. +//! +//! \return None +// +//***************************************************************************** +void MPY32_setOperandTwo32Bit(uint32_t operand) +{ + HWREG16(MPY32_BASE + OFS_OP2L) = operand; + HWREG16(MPY32_BASE + OFS_OP2H) = (operand >> 16); +} + +//***************************************************************************** +// +//! \brief Deprecated - Returns an 8-bit result of the last multiplication +//! operation. +//! +//! This function returns the 8 least significant bits of the result registers. +//! This can improve efficiency if the operation has no more than an 8-bit +//! result. +//! +//! +//! \return The 8-bit result of the last multiplication operation. +// +//***************************************************************************** +uint8_t MPY32_getResult8Bit(void) +{ + return HWREG8(MPY32_BASE + OFS_RES0_L); +} + +//***************************************************************************** +// +//! \brief Deprecated - Returns an 16-bit result of the last multiplication +//! operation. +//! +//! This function returns the 16 least significant bits of the result +//! registers. This can improve efficiency if the operation has no more than a +//! 16-bit result. +//! +//! +//! \return The 16-bit result of the last multiplication operation. +// +//***************************************************************************** +uint16_t MPY32_getResult16Bit(void) +{ + return HWREG16(MPY32_BASE + OFS_RES0); +} + +//***************************************************************************** +// +//! \brief Deprecated - Returns an 24-bit result of the last multiplication +//! operation. +//! +//! This function returns the 24 least significant bits of the result +//! registers. This can improve efficiency if the operation has no more than an +//! 24-bit result. +//! +//! +//! \return The 24-bit result of the last multiplication operation. +// +//***************************************************************************** +uint32_t MPY32_getResult24Bit(void) +{ + uint32_t result = HWREG16(MPY32_BASE + OFS_RES1); + + result = (result << 16) + HWREG16(MPY32_BASE + OFS_RES0); + return result; +} + +//***************************************************************************** +// +//! \brief Deprecated - Returns an 32-bit result of the last multiplication +//! operation. +//! +//! This function returns a 32-bit result of the last multiplication operation, +//! which is the maximum amount of bits of a 16 x 16 operation. +//! +//! +//! \return The 32-bit result of the last multiplication operation. +// +//***************************************************************************** +uint32_t MPY32_getResult32Bit(void) +{ + uint32_t result = HWREG16(MPY32_BASE + OFS_RES1); + + result = (result << 16) + HWREG16(MPY32_BASE + OFS_RES0); + return result; +} + +//***************************************************************************** +// +//! \brief Deprecated - Returns an 64-bit result of the last multiplication +//! operation. +//! +//! This function returns all 64 bits of the result registers. The way this is +//! passed is with 4 integers contained within a uint16 struct. +//! +//! +//! \return The 64-bit result separated into 4 uint16_ts in a uint16 struct +// +//***************************************************************************** +uint64 MPY32_getResult64Bit(void) +{ + uint64 result; + + result.RES0 = HWREG16(MPY32_BASE + OFS_RES0); + result.RES1 = HWREG16(MPY32_BASE + OFS_RES1); + result.RES2 = HWREG16(MPY32_BASE + OFS_RES2); + result.RES3 = HWREG16(MPY32_BASE + OFS_RES3); + return result; +} + +//***************************************************************************** +// +//! \brief Returns an 64-bit result of the last multiplication operation. +//! +//! This function returns all 64 bits of the result registers +//! +//! +//! \return The 64-bit result is returned as a uint64_t type +// +//***************************************************************************** +uint64_t MPY32_getResult(void) +{ + uint64_t result; + + result = HWREG16(MPY32_BASE + OFS_RES0); + result += ((uint64_t)HWREG16(MPY32_BASE + OFS_RES1) << 16); + result += ((uint64_t)HWREG16(MPY32_BASE + OFS_RES2) << 32); + result += ((uint64_t)HWREG16(MPY32_BASE + OFS_RES3) << 48); + return result; +} + +//***************************************************************************** +// +//! \brief Returns the Sum Extension of the last multiplication operation. +//! +//! This function returns the Sum Extension of the MPY module, which either +//! gives the sign after a signed operation or shows a carry after a multiply- +//! and-accumulate operation. The Sum Extension acts as a check for overflows +//! or underflows. +//! +//! +//! \return The value of the MPY32 module Sum Extension. +// +//***************************************************************************** +uint16_t MPY32_getSumExtension(void) +{ + return HWREG16(MPY32_BASE + OFS_SUMEXT); +} + +//***************************************************************************** +// +//! \brief Returns the Carry Bit of the last multiplication operation. +//! +//! This function returns the Carry Bit of the MPY module, which either gives +//! the sign after a signed operation or shows a carry after a multiply- and- +//! accumulate operation. +//! +//! +//! \return The value of the MPY32 module Carry Bit 0x0 or 0x1. +// +//***************************************************************************** +uint16_t MPY32_getCarryBitValue(void) +{ + return HWREG16(MPY32_BASE + OFS_MPY32CTL0) | MPYC; +} +//***************************************************************************** +// +//! \brief Clears the Carry Bit of the last multiplication operation. +//! +//! This function clears the Carry Bit of the MPY module +//! +//! +//! \return The value of the MPY32 module Carry Bit 0x0 or 0x1. +// +//***************************************************************************** +void MPY32_clearCarryBitValue(void) +{ + HWREG16(MPY32_BASE + OFS_MPY32CTL0) &= ~MPYC; +} +//***************************************************************************** +// +//! \brief Preloads the result register +//! +//! This function Preloads the result register +//! +//! +//! \return None +// +//***************************************************************************** +void MPY32_preloadResult(uint64_t result) +{ + HWREG16(MPY32_BASE + OFS_RES0) = (result & 0xFFFF); + HWREG16(MPY32_BASE + OFS_RES1) = ((result >> 16) & 0xFFFF); + HWREG16(MPY32_BASE + OFS_RES2) = ((result >> 32) & 0xFFFF); + HWREG16(MPY32_BASE + OFS_RES3) = ((result >> 48) & 0xFFFF); +} + +#endif +#endif +//***************************************************************************** +// +//! Close the doxygen group for mpy32_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/mpy32.h b/source/driverlib/MSP430F5xx_6xx/mpy32.h new file mode 100644 index 0000000..faaf204 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/mpy32.h @@ -0,0 +1,206 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// mpy32.h - Driver for the MPY32 Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_MPY32_H__ +#define __MSP430WARE_MPY32_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_MPY32__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//****************************************************************************** +// +// The following is a struct that can be returned by MPY32_getResult64Bit() +// +//****************************************************************************** +typedef struct { + uint16_t RES0; + uint16_t RES1; + uint16_t RES2; + uint16_t RES3; +} uint64; + +//***************************************************************************** +// +// The following are values that can be passed to the writeDelaySelect +// parameter for functions: MPY32_setWriteDelay(). +// +//***************************************************************************** +#define MPY32_WRITEDELAY_OFF (!(MPYDLY32 + MPYDLYWRTEN)) +#define MPY32_WRITEDELAY_32BIT (MPYDLYWRTEN) +#define MPY32_WRITEDELAY_64BIT (MPYDLY32 + MPYDLYWRTEN) + +//***************************************************************************** +// +// The following are values that can be passed to the multiplicationType +// parameter for functions: MPY32_setOperandOne8Bit(), +// MPY32_setOperandOne16Bit(), MPY32_setOperandOne24Bit(), and +// MPY32_setOperandOne32Bit(). +// +//***************************************************************************** +#define MPY32_MULTIPLY_UNSIGNED (0x00) +#define MPY32_MULTIPLY_SIGNED (0x02) +#define MPY32_MULTIPLYACCUMULATE_UNSIGNED (0x04) +#define MPY32_MULTIPLYACCUMULATE_SIGNED (0x06) + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the MPY32_getSaturationMode() function. +// +//***************************************************************************** +#define MPY32_SATURATION_MODE_DISABLED 0x00 +#define MPY32_SATURATION_MODE_ENABLED MPYSAT + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the MPY32_getFractionalMode() function. +// +//***************************************************************************** +#define MPY32_FRACTIONAL_MODE_DISABLED 0x00 +#define MPY32_FRACTIONAL_MODE_ENABLED MPYFRAC + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void MPY32_setWriteDelay(uint16_t writeDelaySelect); + +extern void MPY32_enableSaturationMode(void); + +extern void MPY32_disableSaturationMode(void); + +extern uint8_t MPY32_getSaturationMode(void); + +extern void MPY32_enableFractionalMode(void); + +extern void MPY32_disableFractionalMode(void); + +extern uint8_t MPY32_getFractionalMode(void); + +extern void MPY32_setOperandOne8Bit(uint8_t multiplicationType, + uint8_t operand); + +extern void MPY32_setOperandOne16Bit(uint8_t multiplicationType, + uint16_t operand); + +extern void MPY32_setOperandOne24Bit(uint8_t multiplicationType, + uint32_t operand); + +extern void MPY32_setOperandOne32Bit(uint8_t multiplicationType, + uint32_t operand); + +extern void MPY32_setOperandTwo8Bit(uint8_t operand); + +extern void MPY32_setOperandTwo16Bit(uint16_t operand); + +extern void MPY32_setOperandTwo24Bit(uint32_t operand); + +extern void MPY32_setOperandTwo32Bit(uint32_t operand); + +extern uint8_t MPY32_getResult8Bit(void); + +extern uint16_t MPY32_getResult16Bit(void); + +extern uint32_t MPY32_getResult24Bit(void); + +extern uint32_t MPY32_getResult32Bit(void); + +extern uint64 MPY32_getResult64Bit(void); + +extern uint64_t MPY32_getResult(void); + +extern uint16_t MPY32_getSumExtension(void); + +extern uint16_t MPY32_getCarryBitValue(void); + +extern void MPY32_clearCarryBitValue(void); + +extern void MPY32_preloadResult(uint64_t result); + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +#define MPY32_setFractionMode MPY32_enableFractionalMode + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +#define MPY32_resetFractionMode MPY32_disableFractionalMode + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +#define MPY32_setSaturationMode MPY32_enableSaturationMode + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +#define MPY32_resetSaturationMode MPY32_disableSaturationMode + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_MPY32_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/pmap.c b/source/driverlib/MSP430F5xx_6xx/pmap.c new file mode 100644 index 0000000..801c494 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/pmap.c @@ -0,0 +1,140 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// pmap.c - Driver for the pmap Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup pmap_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_PORT_MAPPING__ +#include "pmap.h" + +#include + +//***************************************************************************** +// +//! \brief DEPRECATED - This function configures the MSP430 Port Mapper +//! +//! This function port maps a set of pins to a new set. +//! +//! \param baseAddress is the base address of the PMAP control module. +//! \param portMapping is the pointer to init Data +//! \param PxMAPy is the pointer start of first PMAP to initialize +//! \param numberOfPorts is the number of Ports to initialize +//! \param portMapReconfigure is used to enable/disable reconfiguration +//! Valid values are: +//! - \b PMAP_ENABLE_RECONFIGURATION +//! - \b PMAP_DISABLE_RECONFIGURATION [Default] +//! +//! Modified bits of \b PMAPKETID register and bits of \b PMAPCTL register. +//! +//! \return None +// +//***************************************************************************** +void PMAP_configurePorts( uint16_t baseAddress, + const uint8_t *portMapping, + uint8_t *PxMAPy, + uint8_t numberOfPorts, + uint8_t portMapReconfigure + ) +{ + PMAP_initPortsParam param = { 0 }; + + param.portMapping = portMapping; + param.PxMAPy = PxMAPy; + param.numberOfPorts = numberOfPorts; + param.portMapReconfigure = portMapReconfigure; + + PMAP_initPorts(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief This function configures the MSP430 Port Mapper +//! +//! This function port maps a set of pins to a new set. +//! +//! +//! Modified bits of \b PMAPKETID register and bits of \b PMAPCTL register. +//! +//! \return None +// +//***************************************************************************** +void PMAP_initPorts( uint16_t baseAddress, + PMAP_initPortsParam *param) +{ + assert(param != 0); + + assert((param->portMapReconfigure == PMAP_ENABLE_RECONFIGURATION) || + (param->portMapReconfigure == PMAP_DISABLE_RECONFIGURATION) + ); + + //Store current interrupt state, then disable all interrupts + uint16_t globalInterruptState = __get_SR_register() & GIE; + __disable_interrupt(); + + //Get write-access to port mapping registers: + HWREG16(baseAddress + OFS_PMAPKEYID) = PMAPPW; + + //Enable/Disable reconfiguration during runtime + HWREG8(baseAddress + OFS_PMAPCTL) &= ~PMAPRECFG; + HWREG8(baseAddress + OFS_PMAPCTL) |= param->portMapReconfigure; + + //Configure Port Mapping: + uint16_t i; + for (i = 0; i < param->numberOfPorts * 8; i++) + param->PxMAPy[i] = param->portMapping[i]; + + //Disable write-access to port mapping registers: + HWREG8(baseAddress + OFS_PMAPKEYID) = 0; + + //Restore previous interrupt state + __bis_SR_register(globalInterruptState); +} + +#endif +//***************************************************************************** +// +//! Close the doxygen group for pmap_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/pmap.h b/source/driverlib/MSP430F5xx_6xx/pmap.h new file mode 100644 index 0000000..69c0c52 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/pmap.h @@ -0,0 +1,106 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// pmap.h - Driver for the PMAP Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_PMAP_H__ +#define __MSP430WARE_PMAP_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_PORT_MAPPING__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//****************************************************************************** +// +// The following is a struct that is passed to PMAP_initPorts() +// +//****************************************************************************** +typedef struct PMAP_initPortsParam { + const uint8_t *portMapping; + uint8_t *PxMAPy; + uint8_t numberOfPorts; + uint8_t portMapReconfigure; +} PMAP_initPortsParam; + +//***************************************************************************** +// +// The following are values that can be passed to the portMapReconfigure +// parameter for functions: PMAP_configurePorts(). +// +//***************************************************************************** +#define PMAP_ENABLE_RECONFIGURATION PMAPRECFG +#define PMAP_DISABLE_RECONFIGURATION 0x00 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void PMAP_initPorts(uint16_t baseAddress, + PMAP_initPortsParam *param); + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +extern void PMAP_configurePorts(uint16_t baseAddress, + const uint8_t *portMapping, + uint8_t *PxMAPy, + uint8_t numberOfPorts, + uint8_t portMapReconfigure); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_PMAP_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/pmm.c b/source/driverlib/MSP430F5xx_6xx/pmm.c new file mode 100644 index 0000000..e22badf --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/pmm.c @@ -0,0 +1,950 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// pmm.c - Driver for the pmm Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup pmm_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifndef DRIVERLIB_LEGACY_MODE + +#ifdef __MSP430_HAS_PMM__ +#include "pmm.h" + +#include + +//***************************************************************************** +// +//! \brief Enables the low-side SVS circuitry +//! +//! +//! Modified bits of \b PMMCTL0 register and bits of \b SVSMLCTL register. +//! +//! \return None +// +//***************************************************************************** +void PMM_enableSvsL(void) +{ + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5; + HWREG16(PMM_BASE + OFS_SVSMLCTL) |= SVSLE; + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Disables the low-side SVS circuitry +//! +//! +//! Modified bits of \b PMMCTL0 register and bits of \b SVSMLCTL register. +//! +//! \return None +// +//***************************************************************************** +void PMM_disableSvsL(void) +{ + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5; + HWREG16(PMM_BASE + OFS_SVSMLCTL) &= ~SVSLE; + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Enables the low-side SVM circuitry +//! +//! +//! Modified bits of \b PMMCTL0 register and bits of \b SVSMLCTL register. +//! +//! \return None +// +//***************************************************************************** +void PMM_enableSvmL(void) +{ + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5; + HWREG16(PMM_BASE + OFS_SVSMLCTL) |= SVMLE; + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Disables the low-side SVM circuitry +//! +//! +//! Modified bits of \b PMMCTL0 register and bits of \b SVSMLCTL register. +//! +//! \return None +// +//***************************************************************************** +void PMM_disableSvmL(void) +{ + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5; + HWREG16(PMM_BASE + OFS_SVSMLCTL) &= ~SVMLE; + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Enables the high-side SVS circuitry +//! +//! +//! Modified bits of \b PMMCTL0 register and bits of \b SVSMHCTL register. +//! +//! \return None +// +//***************************************************************************** +void PMM_enableSvsH(void) +{ + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5; + HWREG16(PMM_BASE + OFS_SVSMHCTL) |= SVSHE; + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Disables the high-side SVS circuitry +//! +//! +//! Modified bits of \b PMMCTL0 register and bits of \b SVSMHCTL register. +//! +//! \return None +// +//***************************************************************************** +void PMM_disableSvsH(void) +{ + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5; + HWREG16(PMM_BASE + OFS_SVSMHCTL) &= ~SVSHE; + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Enables the high-side SVM circuitry +//! +//! +//! Modified bits of \b PMMCTL0 register and bits of \b SVSMHCTL register. +//! +//! \return None +// +//***************************************************************************** +void PMM_enableSvmH(void) +{ + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5; + HWREG16(PMM_BASE + OFS_SVSMHCTL) |= SVMHE; + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Disables the high-side SVM circuitry +//! +//! +//! Modified bits of \b PMMCTL0 register and bits of \b SVSMHCTL register. +//! +//! \return None +// +//***************************************************************************** +void PMM_disableSvmH(void) +{ + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5; + HWREG16(PMM_BASE + OFS_SVSMHCTL) &= ~SVMHE; + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Enables the low-side SVS and SVM circuitry +//! +//! +//! Modified bits of \b PMMCTL0 register and bits of \b SVSMLCTL register. +//! +//! \return None +// +//***************************************************************************** +void PMM_enableSvsLSvmL(void) +{ + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5; + HWREG16(PMM_BASE + OFS_SVSMLCTL) |= (SVSLE + SVMLE); + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Disables the low-side SVS and SVM circuitry +//! +//! +//! Modified bits of \b PMMCTL0 register and bits of \b SVSMLCTL register. +//! +//! \return None +// +//***************************************************************************** +void PMM_disableSvsLSvmL(void) +{ + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5; + HWREG16(PMM_BASE + OFS_SVSMLCTL) &= ~(SVSLE + SVMLE); + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Enables the high-side SVS and SVM circuitry +//! +//! +//! Modified bits of \b PMMCTL0 register and bits of \b SVSMHCTL register. +//! +//! \return None +// +//***************************************************************************** +void PMM_enableSvsHSvmH(void) +{ + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5; + HWREG16(PMM_BASE + OFS_SVSMHCTL) |= (SVSHE + SVMHE); + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Disables the high-side SVS and SVM circuitry +//! +//! +//! Modified bits of \b PMMCTL0 register and bits of \b SVSMHCTL register. +//! +//! \return None +// +//***************************************************************************** +void PMM_disableSvsHSvmH(void) +{ + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5; + HWREG16(PMM_BASE + OFS_SVSMHCTL) &= ~(SVSHE + SVMHE); + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Enables the POR signal generation when a low-voltage event is +//! registered by the low-side SVS +//! +//! +//! Modified bits of \b PMMCTL0 register and bits of \b PMMIE register. +//! +//! \return None +// +//***************************************************************************** +void PMM_enableSvsLReset(void) +{ + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5; + HWREG16(PMM_BASE + OFS_PMMRIE) |= SVSLPE; + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Disables the POR signal generation when a low-voltage event is +//! registered by the low-side SVS +//! +//! +//! Modified bits of \b PMMCTL0 register and bits of \b PMMIE register. +//! +//! \return None +// +//***************************************************************************** +void PMM_disableSvsLReset(void) +{ + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5; + HWREG16(PMM_BASE + OFS_PMMRIE) &= ~SVSLPE; + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Enables the interrupt generation when a low-voltage event is +//! registered by the low-side SVM +//! +//! +//! Modified bits of \b PMMCTL0 register and bits of \b PMMIE register. +//! +//! \return None +// +//***************************************************************************** +void PMM_enableSvmLInterrupt(void) +{ + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5; + HWREG16(PMM_BASE + OFS_PMMRIE) |= SVMLIE; + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Disables the interrupt generation when a low-voltage event is +//! registered by the low-side SVM +//! +//! +//! Modified bits of \b PMMCTL0 register and bits of \b PMMIE register. +//! +//! \return None +// +//***************************************************************************** +void PMM_disableSvmLInterrupt(void) +{ + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5; + HWREG16(PMM_BASE + OFS_PMMRIE) &= ~SVMLIE; + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Enables the POR signal generation when a low-voltage event is +//! registered by the high-side SVS +//! +//! +//! Modified bits of \b PMMCTL0 register and bits of \b PMMIE register. +//! +//! \return None +// +//***************************************************************************** +void PMM_enableSvsHReset(void) +{ + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5; + HWREG16(PMM_BASE + OFS_PMMRIE) |= SVSHPE; + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Disables the POR signal generation when a low-voltage event is +//! registered by the high-side SVS +//! +//! +//! Modified bits of \b PMMCTL0 register and bits of \b PMMIE register. +//! +//! \return None +// +//***************************************************************************** +void PMM_disableSvsHReset(void) +{ + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5; + HWREG16(PMM_BASE + OFS_PMMRIE) &= ~SVSHPE; + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Enables the interrupt generation when a low-voltage event is +//! registered by the high-side SVM +//! +//! +//! Modified bits of \b PMMCTL0 register and bits of \b PMMIE register. +//! +//! \return None +// +//***************************************************************************** +void PMM_enableSvmHInterrupt(void) +{ + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5; + HWREG16(PMM_BASE + OFS_PMMRIE) |= SVMHIE; + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Disables the interrupt generation when a low-voltage event is +//! registered by the high-side SVM +//! +//! +//! Modified bits of \b PMMCTL0 register and bits of \b PMMIE register. +//! +//! \return None +// +//***************************************************************************** +void PMM_disableSvmHInterrupt(void) +{ + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5; + HWREG16(PMM_BASE + OFS_PMMRIE) &= ~SVMHIE; + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Clear all interrupt flags for the PMM +//! +//! +//! Modified bits of \b PMMCTL0 register and bits of \b PMMIFG register. +//! +//! \return None +// +//***************************************************************************** +void PMM_clearPMMIFGS(void) +{ + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5; + HWREG16(PMM_BASE + OFS_PMMIFG) = 0; + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Enables supervisor low side in LPM with twake-up-fast from LPM2, +//! LPM3, and LPM4 +//! +//! +//! Modified bits of \b PMMCTL0 register and bits of \b SVSMLCTL register. +//! +//! \return None +// +//***************************************************************************** +void PMM_SvsLEnabledInLPMFastWake(void) +{ + //These settings use SVSH/LACE = 0 + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5; + HWREG16(PMM_BASE + OFS_SVSMLCTL) |= (SVSLFP + SVSLMD); + HWREG16(PMM_BASE + OFS_SVSMLCTL) &= ~SVSMLACE; + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Enables supervisor low side in LPM with twake-up-slow from LPM2, +//! LPM3, and LPM4 +//! +//! +//! Modified bits of \b PMMCTL0 register and bits of \b SVSMLCTL register. +//! +//! \return None +// +//***************************************************************************** +void PMM_SvsLEnabledInLPMSlowWake(void) +{ + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5; + HWREG16(PMM_BASE + OFS_SVSMLCTL) |= SVSLMD; + HWREG16(PMM_BASE + OFS_SVSMLCTL) &= ~(SVSLFP + SVSMLACE); + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Disables supervisor low side in LPM with twake-up-fast from LPM2, +//! LPM3, and LPM4 +//! +//! +//! Modified bits of \b PMMCTL0 register and bits of \b SVSMLCTL register. +//! +//! \return None +// +//***************************************************************************** +void PMM_SvsLDisabledInLPMFastWake(void) +{ + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5; + HWREG16(PMM_BASE + OFS_SVSMLCTL) |= SVSLFP; + HWREG16(PMM_BASE + OFS_SVSMLCTL) &= ~(SVSLMD + SVSMLACE); + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Disables supervisor low side in LPM with twake-up-slow from LPM2, +//! LPM3, and LPM4 +//! +//! +//! Modified bits of \b PMMCTL0 register and bits of \b SVSMLCTL register. +//! +//! \return None +// +//***************************************************************************** +void PMM_SvsLDisabledInLPMSlowWake(void) +{ + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5; + HWREG16(PMM_BASE + OFS_SVSMLCTL) &= ~(SVSLFP + SVSMLACE + SVSLMD); + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Enables supervisor high side in LPM with tpd = 20 ?s(1) +//! +//! +//! Modified bits of \b PMMCTL0 register and bits of \b SVSMHCTL register. +//! +//! \return None +// +//***************************************************************************** +void PMM_SvsHEnabledInLPMNormPerf(void) +{ + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5; + HWREG16(PMM_BASE + OFS_SVSMHCTL) |= SVSHMD; + HWREG16(PMM_BASE + OFS_SVSMHCTL) &= ~(SVSMHACE + SVSHFP); + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Enables supervisor high side in LPM with tpd = 2.5 ?s(1) +//! +//! +//! Modified bits of \b PMMCTL0 register and bits of \b SVSMHCTL register. +//! +//! \return None +// +//***************************************************************************** +void PMM_SvsHEnabledInLPMFullPerf(void) +{ + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5; + HWREG16(PMM_BASE + OFS_SVSMHCTL) |= (SVSHMD + SVSHFP); + HWREG16(PMM_BASE + OFS_SVSMHCTL) &= ~SVSMHACE; + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Disables supervisor high side in LPM with tpd = 20 ?s(1) +//! +//! +//! Modified bits of \b PMMCTL0 register and bits of \b SVSMHCTL register. +//! +//! \return None +// +//***************************************************************************** +void PMM_SvsHDisabledInLPMNormPerf(void) +{ + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5; + HWREG16(PMM_BASE + OFS_SVSMHCTL) &= ~(SVSMHACE + SVSHFP + SVSHMD); + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Disables supervisor high side in LPM with tpd = 2.5 ?s(1) +//! +//! +//! Modified bits of \b PMMCTL0 register and bits of \b SVSMHCTL register. +//! +//! \return None +// +//***************************************************************************** +void PMM_SvsHDisabledInLPMFullPerf(void) +{ + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5; + HWREG16(PMM_BASE + OFS_SVSMHCTL) |= SVSHFP; + HWREG16(PMM_BASE + OFS_SVSMHCTL) &= ~(SVSMHACE + SVSHMD); + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Optimized to provide twake-up-fast from LPM2, LPM3, and LPM4 with +//! least power +//! +//! +//! Modified bits of \b PMMCTL0 register and bits of \b SVSMLCTL register. +//! +//! \return None +// +//***************************************************************************** +void PMM_SvsLOptimizedInLPMFastWake(void) +{ + //These setting use SVSH/LACE = 1 + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5; + HWREG16(PMM_BASE + OFS_SVSMLCTL) |= (SVSLFP + SVSLMD + SVSMLACE); + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Optimized to provide tpd = 2.5 ?s(1) in LPM with least power +//! +//! +//! Modified bits of \b PMMCTL0 register and bits of \b SVSMLCTL register. +//! +//! \return None +// +//***************************************************************************** +void PMM_SvsHOptimizedInLPMFullPerf(void) +{ + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5; + HWREG16(PMM_BASE + OFS_SVSMHCTL) |= (SVSHMD + SVSHFP + SVSMHACE); + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Increase Vcore by one level +//! +//! \param level level to which Vcore needs to be increased +//! Valid values are: +//! - \b PMM_CORE_LEVEL_0 [Default] +//! - \b PMM_CORE_LEVEL_1 +//! - \b PMM_CORE_LEVEL_2 +//! - \b PMM_CORE_LEVEL_3 +//! +//! Modified bits of \b PMMCTL0 register, bits of \b PMMIFG register, bits of +//! \b PMMRIE register, bits of \b SVSMHCTL register and bits of \b SVSMLCTL +//! register. +//! +//! \return STATUS_SUCCESS or STATUS_FAIL +// +//***************************************************************************** +uint16_t PMM_setVCoreUp( uint8_t level) +{ + uint32_t PMMRIE_backup, SVSMHCTL_backup, SVSMLCTL_backup; + + //The code flow for increasing the Vcore has been altered to work around + //the erratum FLASH37. + //Please refer to the Errata sheet to know if a specific device is affected + //DO NOT ALTER THIS FUNCTION + + //Open PMM registers for write access + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5; + + //Disable dedicated Interrupts + //Backup all registers + PMMRIE_backup = HWREG16(PMM_BASE + OFS_PMMRIE); + HWREG16(PMM_BASE + OFS_PMMRIE) &= ~(SVMHVLRPE | SVSHPE | SVMLVLRPE | + SVSLPE | SVMHVLRIE | SVMHIE | + SVSMHDLYIE | SVMLVLRIE | SVMLIE | + SVSMLDLYIE + ); + SVSMHCTL_backup = HWREG16(PMM_BASE + OFS_SVSMHCTL); + SVSMLCTL_backup = HWREG16(PMM_BASE + OFS_SVSMLCTL); + + //Clear flags + HWREG16(PMM_BASE + OFS_PMMIFG) = 0; + + //Set SVM highside to new level and check if a VCore increase is possible + HWREG16(PMM_BASE + OFS_SVSMHCTL) = SVMHE | SVSHE | (SVSMHRRL0 * level); + + //Wait until SVM highside is settled + while ((HWREG16(PMM_BASE + OFS_PMMIFG) & SVSMHDLYIFG) == 0) ; + + //Clear flag + HWREG16(PMM_BASE + OFS_PMMIFG) &= ~SVSMHDLYIFG; + + //Check if a VCore increase is possible + if ((HWREG16(PMM_BASE + OFS_PMMIFG) & SVMHIFG) == SVMHIFG) { + //-> Vcc is too low for a Vcore increase + //recover the previous settings + HWREG16(PMM_BASE + OFS_PMMIFG) &= ~SVSMHDLYIFG; + HWREG16(PMM_BASE + OFS_SVSMHCTL) = SVSMHCTL_backup; + + //Wait until SVM highside is settled + while ((HWREG16(PMM_BASE + OFS_PMMIFG) & SVSMHDLYIFG) == 0) ; + + //Clear all Flags + HWREG16(PMM_BASE + + OFS_PMMIFG) &= ~(SVMHVLRIFG | SVMHIFG | SVSMHDLYIFG | + SVMLVLRIFG | SVMLIFG | + SVSMLDLYIFG + ); + + //Restore PMM interrupt enable register + HWREG16(PMM_BASE + OFS_PMMRIE) = PMMRIE_backup; + //Lock PMM registers for write access + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00; + //return: voltage not set + return STATUS_FAIL; + } + + //Set also SVS highside to new level + //Vcc is high enough for a Vcore increase + HWREG16(PMM_BASE + OFS_SVSMHCTL) |= (SVSHRVL0 * level); + + //Wait until SVM highside is settled + while ((HWREG16(PMM_BASE + OFS_PMMIFG) & SVSMHDLYIFG) == 0) ; + + //Clear flag + HWREG16(PMM_BASE + OFS_PMMIFG) &= ~SVSMHDLYIFG; + + //Set VCore to new level + HWREG8(PMM_BASE + OFS_PMMCTL0_L) = PMMCOREV0 * level; + + //Set SVM, SVS low side to new level + HWREG16(PMM_BASE + OFS_SVSMLCTL) = SVMLE | (SVSMLRRL0 * level) | + SVSLE | (SVSLRVL0 * level); + + //Wait until SVM, SVS low side is settled + while ((HWREG16(PMM_BASE + OFS_PMMIFG) & SVSMLDLYIFG) == 0) ; + + //Clear flag + HWREG16(PMM_BASE + OFS_PMMIFG) &= ~SVSMLDLYIFG; + //SVS, SVM core and high side are now set to protect for the new core level + + //Restore Low side settings + //Clear all other bits _except_ level settings + HWREG16(PMM_BASE + OFS_SVSMLCTL) &= (SVSLRVL0 + SVSLRVL1 + SVSMLRRL0 + + SVSMLRRL1 + SVSMLRRL2 + ); + + //Clear level settings in the backup register,keep all other bits + SVSMLCTL_backup &= + ~(SVSLRVL0 + SVSLRVL1 + SVSMLRRL0 + SVSMLRRL1 + SVSMLRRL2); + + //Restore low-side SVS monitor settings + HWREG16(PMM_BASE + OFS_SVSMLCTL) |= SVSMLCTL_backup; + + //Restore High side settings + //Clear all other bits except level settings + HWREG16(PMM_BASE + OFS_SVSMHCTL) &= (SVSHRVL0 + SVSHRVL1 + + SVSMHRRL0 + SVSMHRRL1 + + SVSMHRRL2 + ); + + //Clear level settings in the backup register,keep all other bits + SVSMHCTL_backup &= + ~(SVSHRVL0 + SVSHRVL1 + SVSMHRRL0 + SVSMHRRL1 + SVSMHRRL2); + + //Restore backup + HWREG16(PMM_BASE + OFS_SVSMHCTL) |= SVSMHCTL_backup; + + //Wait until high side, low side settled + while (((HWREG16(PMM_BASE + OFS_PMMIFG) & SVSMLDLYIFG) == 0) || + ((HWREG16(PMM_BASE + OFS_PMMIFG) & SVSMHDLYIFG) == 0)) ; + + //Clear all Flags + HWREG16(PMM_BASE + OFS_PMMIFG) &= ~(SVMHVLRIFG | SVMHIFG | SVSMHDLYIFG | + SVMLVLRIFG | SVMLIFG | SVSMLDLYIFG + ); + + //Restore PMM interrupt enable register + HWREG16(PMM_BASE + OFS_PMMRIE) = PMMRIE_backup; + + //Lock PMM registers for write access + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00; + + return STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! \brief Decrease Vcore by one level +//! +//! \param level level to which Vcore needs to be decreased +//! Valid values are: +//! - \b PMM_CORE_LEVEL_0 [Default] +//! - \b PMM_CORE_LEVEL_1 +//! - \b PMM_CORE_LEVEL_2 +//! - \b PMM_CORE_LEVEL_3 +//! +//! Modified bits of \b PMMCTL0 register, bits of \b PMMIFG register, bits of +//! \b PMMRIE register, bits of \b SVSMHCTL register and bits of \b SVSMLCTL +//! register. +//! +//! \return STATUS_SUCCESS +// +//***************************************************************************** +uint16_t PMM_setVCoreDown( uint8_t level) +{ + uint32_t PMMRIE_backup, SVSMHCTL_backup, SVSMLCTL_backup; + + //The code flow for decreasing the Vcore has been altered to work around + //the erratum FLASH37. + //Please refer to the Errata sheet to know if a specific device is affected + //DO NOT ALTER THIS FUNCTION + + //Open PMM registers for write access + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5; + + //Disable dedicated Interrupts + //Backup all registers + PMMRIE_backup = HWREG16(PMM_BASE + OFS_PMMRIE); + HWREG16(PMM_BASE + OFS_PMMRIE) &= ~(SVMHVLRPE | SVSHPE | SVMLVLRPE | + SVSLPE | SVMHVLRIE | SVMHIE | + SVSMHDLYIE | SVMLVLRIE | SVMLIE | + SVSMLDLYIE + ); + SVSMHCTL_backup = HWREG16(PMM_BASE + OFS_SVSMHCTL); + SVSMLCTL_backup = HWREG16(PMM_BASE + OFS_SVSMLCTL); + + //Clear flags + HWREG16(PMM_BASE + OFS_PMMIFG) &= ~(SVMHIFG | SVSMHDLYIFG | + SVMLIFG | SVSMLDLYIFG + ); + + //Set SVM, SVS high & low side to new settings in normal mode + HWREG16(PMM_BASE + OFS_SVSMHCTL) = SVMHE | (SVSMHRRL0 * level) | + SVSHE | (SVSHRVL0 * level); + HWREG16(PMM_BASE + OFS_SVSMLCTL) = SVMLE | (SVSMLRRL0 * level) | + SVSLE | (SVSLRVL0 * level); + + //Wait until SVM high side and SVM low side is settled + while ((HWREG16(PMM_BASE + OFS_PMMIFG) & SVSMHDLYIFG) == 0 || + (HWREG16(PMM_BASE + OFS_PMMIFG) & SVSMLDLYIFG) == 0) ; + + //Clear flags + HWREG16(PMM_BASE + OFS_PMMIFG) &= ~(SVSMHDLYIFG + SVSMLDLYIFG); + //SVS, SVM core and high side are now set to protect for the new core level + + //Set VCore to new level + HWREG8(PMM_BASE + OFS_PMMCTL0_L) = PMMCOREV0 * level; + + //Restore Low side settings + //Clear all other bits _except_ level settings + HWREG16(PMM_BASE + OFS_SVSMLCTL) &= (SVSLRVL0 + SVSLRVL1 + SVSMLRRL0 + + SVSMLRRL1 + SVSMLRRL2 + ); + + //Clear level settings in the backup register,keep all other bits + SVSMLCTL_backup &= + ~(SVSLRVL0 + SVSLRVL1 + SVSMLRRL0 + SVSMLRRL1 + SVSMLRRL2); + + //Restore low-side SVS monitor settings + HWREG16(PMM_BASE + OFS_SVSMLCTL) |= SVSMLCTL_backup; + + //Restore High side settings + //Clear all other bits except level settings + HWREG16(PMM_BASE + OFS_SVSMHCTL) &= (SVSHRVL0 + SVSHRVL1 + SVSMHRRL0 + + SVSMHRRL1 + SVSMHRRL2 + ); + + //Clear level settings in the backup register, keep all other bits + SVSMHCTL_backup &= + ~(SVSHRVL0 + SVSHRVL1 + SVSMHRRL0 + SVSMHRRL1 + SVSMHRRL2); + + //Restore backup + HWREG16(PMM_BASE + OFS_SVSMHCTL) |= SVSMHCTL_backup; + + //Wait until high side, low side settled + while (((HWREG16(PMM_BASE + OFS_PMMIFG) & SVSMLDLYIFG) == 0) || + ((HWREG16(PMM_BASE + OFS_PMMIFG) & SVSMHDLYIFG) == 0)) ; + + //Clear all Flags + HWREG16(PMM_BASE + OFS_PMMIFG) &= ~(SVMHVLRIFG | SVMHIFG | SVSMHDLYIFG | + SVMLVLRIFG | SVMLIFG | SVSMLDLYIFG + ); + + //Restore PMM interrupt enable register + HWREG16(PMM_BASE + OFS_PMMRIE) = PMMRIE_backup; + //Lock PMM registers for write access + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00; + //Return: OK + return STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! \brief Set Vcore to expected level +//! +//! \param level level to which Vcore needs to be decreased/increased +//! Valid values are: +//! - \b PMM_CORE_LEVEL_0 [Default] +//! - \b PMM_CORE_LEVEL_1 +//! - \b PMM_CORE_LEVEL_2 +//! - \b PMM_CORE_LEVEL_3 +//! +//! Modified bits of \b PMMCTL0 register, bits of \b PMMIFG register, bits of +//! \b PMMRIE register, bits of \b SVSMHCTL register and bits of \b SVSMLCTL +//! register. +//! +//! \return STATUS_SUCCESS or STATUS_FAIL +// +//***************************************************************************** +bool PMM_setVCore( uint8_t level) +{ + assert( + (PMM_CORE_LEVEL_0 == level) || + (PMM_CORE_LEVEL_1 == level) || + (PMM_CORE_LEVEL_2 == level) || + (PMM_CORE_LEVEL_3 == level) + ); + + uint8_t actlevel; + bool status = STATUS_SUCCESS; + + //Set Mask for Max. level + level &= PMMCOREV_3; + + //Get actual VCore + actlevel = (HWREG16(PMM_BASE + OFS_PMMCTL0) & PMMCOREV_3); + + //step by step increase or decrease + while ((level != actlevel) && (status == STATUS_SUCCESS)) { + if (level > actlevel) + status = PMM_setVCoreUp(++actlevel); + else + status = PMM_setVCoreDown(--actlevel); + } + + return status; +} + +//***************************************************************************** +// +//! \brief Returns interrupt status +//! +//! \param mask is the mask for specifying the required flag +//! Mask value is the logical OR of any of the following: +//! - \b PMM_SVSMLDLYIFG +//! - \b PMM_SVMLIFG +//! - \b PMM_SVMLVLRIFG +//! - \b PMM_SVSMHDLYIFG +//! - \b PMM_SVMHIFG +//! - \b PMM_SVMHVLRIFG +//! - \b PMM_PMMBORIFG +//! - \b PMM_PMMRSTIFG +//! - \b PMM_PMMPORIFG +//! - \b PMM_SVSHIFG +//! - \b PMM_SVSLIFG +//! - \b PMM_PMMLPM5IFG +//! +//! \return Logical OR of any of the following: +//! - \b PMM_SVSMLDLYIFG +//! - \b PMM_SVMLIFG +//! - \b PMM_SVMLVLRIFG +//! - \b PMM_SVSMHDLYIFG +//! - \b PMM_SVMHIFG +//! - \b PMM_SVMHVLRIFG +//! - \b PMM_PMMBORIFG +//! - \b PMM_PMMRSTIFG +//! - \b PMM_PMMPORIFG +//! - \b PMM_SVSHIFG +//! - \b PMM_SVSLIFG +//! - \b PMM_PMMLPM5IFG +//! \n indicating the status of the masked interrupts +// +//***************************************************************************** +uint16_t PMM_getInterruptStatus(uint16_t mask) +{ + return (HWREG16(PMM_BASE + OFS_PMMIFG)) & mask; +} + +#endif +#endif +//***************************************************************************** +// +//! Close the doxygen group for pmm_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/pmm.h b/source/driverlib/MSP430F5xx_6xx/pmm.h new file mode 100644 index 0000000..ccc5497 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/pmm.h @@ -0,0 +1,172 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// pmm.h - Driver for the PMM Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_PMM_H__ +#define __MSP430WARE_PMM_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_PMM__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the level parameter for +// functions: PMM_setVCoreUp(), PMM_setVCoreDown(), and PMM_setVCore(). +// +//***************************************************************************** +#define PMM_CORE_LEVEL_0 PMMCOREV_0 +#define PMM_CORE_LEVEL_1 PMMCOREV_1 +#define PMM_CORE_LEVEL_2 PMMCOREV_2 +#define PMM_CORE_LEVEL_3 PMMCOREV_3 + +//***************************************************************************** +// +// The following are values that can be passed to the mask parameter for +// functions: PMM_getInterruptStatus() as well as returned by the +// PMM_getInterruptStatus() function. +// +//***************************************************************************** +#define PMM_SVSMLDLYIFG SVSMLDLYIFG +#define PMM_SVMLIFG SVMLIFG +#define PMM_SVMLVLRIFG SVMLVLRIFG +#define PMM_SVSMHDLYIFG SVSMHDLYIFG +#define PMM_SVMHIFG SVMHIFG +#define PMM_SVMHVLRIFG SVMHVLRIFG +#define PMM_PMMBORIFG PMMBORIFG +#define PMM_PMMRSTIFG PMMRSTIFG +#define PMM_PMMPORIFG PMMPORIFG +#define PMM_SVSHIFG SVSHIFG +#define PMM_SVSLIFG SVSLIFG +#define PMM_PMMLPM5IFG PMMLPM5IFG + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void PMM_enableSvsL(void); + +extern void PMM_disableSvsL(void); + +extern void PMM_enableSvmL(void); + +extern void PMM_disableSvmL(void); + +extern void PMM_enableSvsH(void); + +extern void PMM_disableSvsH(void); + +extern void PMM_enableSvmH(void); + +extern void PMM_disableSvmH(void); + +extern void PMM_enableSvsLSvmL(void); + +extern void PMM_disableSvsLSvmL(void); + +extern void PMM_enableSvsHSvmH(void); + +extern void PMM_disableSvsHSvmH(void); + +extern void PMM_enableSvsLReset(void); + +extern void PMM_disableSvsLReset(void); + +extern void PMM_enableSvmLInterrupt(void); + +extern void PMM_disableSvmLInterrupt(void); + +extern void PMM_enableSvsHReset(void); + +extern void PMM_disableSvsHReset(void); + +extern void PMM_enableSvmHInterrupt(void); + +extern void PMM_disableSvmHInterrupt(void); + +extern void PMM_clearPMMIFGS(void); + +extern void PMM_SvsLEnabledInLPMFastWake(void); + +extern void PMM_SvsLEnabledInLPMSlowWake(void); + +extern void PMM_SvsLDisabledInLPMFastWake(void); + +extern void PMM_SvsLDisabledInLPMSlowWake(void); + +extern void PMM_SvsHEnabledInLPMNormPerf(void); + +extern void PMM_SvsHEnabledInLPMFullPerf(void); + +extern void PMM_SvsHDisabledInLPMNormPerf(void); + +extern void PMM_SvsHDisabledInLPMFullPerf(void); + +extern void PMM_SvsLOptimizedInLPMFastWake(void); + +extern void PMM_SvsHOptimizedInLPMFullPerf(void); + +extern uint16_t PMM_setVCoreUp(uint8_t level); + +extern uint16_t PMM_setVCoreDown(uint8_t level); + +extern bool PMM_setVCore(uint8_t level); + +extern uint16_t PMM_getInterruptStatus(uint16_t mask); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_PMM_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/ram.c b/source/driverlib/MSP430F5xx_6xx/ram.c new file mode 100644 index 0000000..fced772 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/ram.c @@ -0,0 +1,140 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// ram.c - Driver for the ram Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup ram_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifndef DRIVERLIB_LEGACY_MODE + +#ifdef __MSP430_HAS_RC__ +#include "ram.h" + +#include + +//***************************************************************************** +// +//! \brief Set specified RAM sector off +//! +//! \param sector is specified sector to be set off. +//! Mask value is the logical OR of any of the following: +//! - \b RAM_SECTOR0 +//! - \b RAM_SECTOR1 +//! - \b RAM_SECTOR2 +//! - \b RAM_SECTOR3 +//! - \b RAM_SECTOR4 +//! - \b RAM_SECTOR5 +//! - \b RAM_SECTOR6 +//! - \b RAM_SECTOR7 +//! +//! Modified bits of \b RCCTL0 register. +//! +//! \return None +// +//***************************************************************************** +void RAM_setSectorOff(uint8_t sector + ) +{ + assert(0x00 == sector & (~(RAM_SECTOR0 + + RAM_SECTOR1 + + RAM_SECTOR2 + + RAM_SECTOR3 + ) + ) + + ); + //Write key to start write to RCCTL0 and sector + HWREG16(RAM_BASE + OFS_RCCTL0) = (RCKEY + sector); +} + +//***************************************************************************** +// +//! \brief Get RAM sector ON/OFF status +//! +//! \param sector is specified sector +//! Mask value is the logical OR of any of the following: +//! - \b RAM_SECTOR0 +//! - \b RAM_SECTOR1 +//! - \b RAM_SECTOR2 +//! - \b RAM_SECTOR3 +//! - \b RAM_SECTOR4 +//! - \b RAM_SECTOR5 +//! - \b RAM_SECTOR6 +//! - \b RAM_SECTOR7 +//! +//! Modified bits of \b RCCTL0 register. +//! +//! \return Logical OR of any of the following: +//! - \b RAM_SECTOR0 +//! - \b RAM_SECTOR1 +//! - \b RAM_SECTOR2 +//! - \b RAM_SECTOR3 +//! - \b RAM_SECTOR4 +//! - \b RAM_SECTOR5 +//! - \b RAM_SECTOR6 +//! - \b RAM_SECTOR7 +//! \n indicating the status of the masked sectors +// +//***************************************************************************** +uint8_t RAM_getSectorState(uint8_t sector + ) +{ + assert(0x00 == sector & (~(RAM_SECTOR0 + + RAM_SECTOR1 + + RAM_SECTOR2 + + RAM_SECTOR3 + ) + ) + + ); + return HWREG8(RAM_BASE + OFS_RCCTL0_L) & sector; +} + +#endif +#endif +//***************************************************************************** +// +//! Close the doxygen group for ram_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/ram.h b/source/driverlib/MSP430F5xx_6xx/ram.h new file mode 100644 index 0000000..a28ebaf --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/ram.h @@ -0,0 +1,91 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// ram.h - Driver for the RAM Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_RAM_H__ +#define __MSP430WARE_RAM_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_RC__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the sector parameter for +// functions: RAM_setSectorOff(), and RAM_getSectorState() as well as returned +// by the RAM_getSectorState() function. +// +//***************************************************************************** +#define RAM_SECTOR0 RCRS0OFF +#define RAM_SECTOR1 RCRS1OFF +#define RAM_SECTOR2 RCRS2OFF +#define RAM_SECTOR3 RCRS3OFF +#define RAM_SECTOR4 RCRS4OFF +#define RAM_SECTOR5 RCRS5OFF +#define RAM_SECTOR6 RCRS6OFF +#define RAM_SECTOR7 RCRS7OFF + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void RAM_setSectorOff(uint8_t sector); + +extern uint8_t RAM_getSectorState(uint8_t sector); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_RAM_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/ref.c b/source/driverlib/MSP430F5xx_6xx/ref.c new file mode 100644 index 0000000..0f1168c --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/ref.c @@ -0,0 +1,313 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// ref.c - Driver for the ref Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup ref_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_REF__ +#include "ref.h" + +#include + +//***************************************************************************** +// +//! \brief Sets the reference voltage for the voltage generator. +//! +//! This function sets the reference voltage generated by the voltage generator +//! to be used by other peripherals. This reference voltage will only be valid +//! while the REF module is in control. Please note, if the REF_isRefGenBusy() +//! returns REF_BUSY, this function will have no effect. +//! +//! \param baseAddress is the base address of the REF module. +//! \param referenceVoltageSelect is the desired voltage to generate for a +//! reference voltage. +//! Valid values are: +//! - \b REF_VREF1_5V [Default] +//! - \b REF_VREF2_0V +//! - \b REF_VREF2_5V +//! \n Modified bits are \b REFVSEL of \b REFCTL0 register. +//! +//! \return None +// +//***************************************************************************** +void REF_setReferenceVoltage(uint16_t baseAddress, + uint8_t referenceVoltageSelect) +{ + assert(referenceVoltageSelect <= REF_VREF2_5V); + + HWREG8(baseAddress + OFS_REFCTL0_L) &= ~(REFVSEL_3); + HWREG8(baseAddress + OFS_REFCTL0_L) |= referenceVoltageSelect; +} + +//***************************************************************************** +// +//! \brief Disables the internal temperature sensor to save power consumption. +//! +//! This function is used to turn off the internal temperature sensor to save +//! on power consumption. The temperature sensor is enabled by default. Please +//! note, that giving ADC12 module control over the REF module, the state of +//! the temperature sensor is dependent on the controls of the ADC12 module. +//! Please note, if the REF_isRefGenBusy() returns REF_BUSY, this function will +//! have no effect. +//! +//! \param baseAddress is the base address of the REF module. +//! +//! Modified bits are \b RFETCOFF of \b REFCTL0 register. +//! +//! \return None +// +//***************************************************************************** +void REF_disableTempSensor(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_REFCTL0_L) |= REFTCOFF; +} + +//***************************************************************************** +// +//! \brief Enables the internal temperature sensor. +//! +//! This function is used to turn on the internal temperature sensor to use by +//! other peripherals. The temperature sensor is enabled by default. Please +//! note, if the REF_isRefGenBusy() returns REF_BUSY, this function will have +//! no effect. +//! +//! \param baseAddress is the base address of the REF module. +//! +//! Modified bits are \b REFTCOFF of \b REFCTL0 register. +//! +//! \return None +// +//***************************************************************************** +void REF_enableTempSensor(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_REFCTL0_L) &= ~(REFTCOFF); +} + +//***************************************************************************** +// +//! \brief Outputs the reference voltage to an output pin. +//! +//! This function is used to output the reference voltage being generated to an +//! output pin. Please note, the output pin is device specific. Please note, +//! that giving ADC12 module control over the REF module, the state of the +//! reference voltage as an output to a pin is dependent on the controls of the +//! ADC12 module. Please note, if the REF_isRefGenBusy() returns REF_BUSY, this +//! function will have no effect. +//! +//! \param baseAddress is the base address of the REF module. +//! +//! Modified bits are \b REFOUT of \b REFCTL0 register. +//! +//! \return None +// +//***************************************************************************** +void REF_enableReferenceVoltageOutput(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_REFCTL0_L) |= REFOUT; +} + +//***************************************************************************** +// +//! \brief Disables the reference voltage as an output to a pin. +//! +//! This function is used to disables the reference voltage being generated to +//! be given to an output pin. Please note, if the REF_isRefGenBusy() returns +//! REF_BUSY, this function will have no effect. +//! +//! \param baseAddress is the base address of the REF module. +//! +//! \return None +// +//***************************************************************************** +void REF_disableReferenceVoltageOutput(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_REFCTL0_L) &= ~(REFOUT); +} + +//***************************************************************************** +// +//! \brief Enables the reference voltage to be used by peripherals. +//! +//! This function is used to enable the generated reference voltage to be used +//! other peripherals or by an output pin, if enabled. Please note, that giving +//! ADC12 module control over the REF module, the state of the reference +//! voltage is dependent on the controls of the ADC12 module. Please note, if +//! the REF_isRefGenBusy() returns REF_BUSY, this function will have no effect. +//! +//! \param baseAddress is the base address of the REF module. +//! +//! Modified bits are \b REFON of \b REFCTL0 register. +//! +//! \return None +// +//***************************************************************************** +void REF_enableReferenceVoltage(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_REFCTL0_L) |= REFON; +} + +//***************************************************************************** +// +//! \brief Disables the reference voltage. +//! +//! This function is used to disable the generated reference voltage. Please +//! note, if the REF_isRefGenBusy() returns REF_BUSY, this function will have +//! no effect. +//! +//! \param baseAddress is the base address of the REF module. +//! +//! Modified bits are \b REFON of \b REFCTL0 register. +//! +//! \return None +// +//***************************************************************************** +void REF_disableReferenceVoltage(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_REFCTL0_L) &= ~(REFON); +} + +//***************************************************************************** +// +//! \brief Returns the bandgap mode of the REF module. +//! +//! This function is used to return the bandgap mode of the REF module, +//! requested by the peripherals using the bandgap. If a peripheral requests +//! static mode, then the bandgap mode will be static for all modules, whereas +//! if all of the peripherals using the bandgap request sample mode, then that +//! will be the mode returned. Sample mode allows the bandgap to be active only +//! when necessary to save on power consumption, static mode requires the +//! bandgap to be active until no peripherals are using it anymore. +//! +//! \param baseAddress is the base address of the REF module. +//! +//! \return One of the following: +//! - \b REF_STATICMODE if the bandgap is operating in static mode +//! - \b REF_SAMPLEMODE if the bandgap is operating in sample mode +//! \n indicating the REF bandgap mode +// +//***************************************************************************** +uint16_t REF_getBandgapMode(uint16_t baseAddress) +{ + return HWREG16((baseAddress) + OFS_REFCTL0) & BGMODE; +} + +//***************************************************************************** +// +//! \brief Returns the active status of the bandgap in the REF module. +//! +//! This function is used to return the active status of the bandgap in the REF +//! module. If the bandgap is in use by a peripheral, then the status will be +//! seen as active. +//! +//! \param baseAddress is the base address of the REF module. +//! +//! \return One of the following: +//! - \b REF_INACTIVE +//! - \b REF_ACTIVE +//! \n indicating the bandgap active status of the REF module +// +//***************************************************************************** +bool REF_isBandgapActive(uint16_t baseAddress) +{ + if (HWREG16((baseAddress) + OFS_REFCTL0) & REFBGACT) + return REF_ACTIVE; + else + return REF_INACTIVE; +} + +//***************************************************************************** +// +//! \brief Returns the busy status of the reference generator in the REF +//! module. +//! +//! This function is used to return the busy status of the reference generator +//! in the REF module. If the ref. generator is in use by a peripheral, then +//! the status will be seen as busy. +//! +//! \param baseAddress is the base address of the REF module. +//! +//! \return One of the following: +//! - \b REF_NOTBUSY if the reference generator is not being used +//! - \b REF_BUSY if the reference generator is being used, disallowing +//! any changes to be made to the REF module controls +//! \n indicating the REF generator busy status +// +//***************************************************************************** +uint16_t REF_isRefGenBusy(uint16_t baseAddress) +{ + return HWREG16((baseAddress) + OFS_REFCTL0) & REFGENBUSY; +} + +//***************************************************************************** +// +//! \brief Returns the active status of the reference generator in the REF +//! module. +//! +//! This function is used to return the active status of the reference +//! generator in the REF module. If the ref. generator is on and ready to use, +//! then the status will be seen as active. +//! +//! \param baseAddress is the base address of the REF module. +//! +//! \return One of the following: +//! - \b REF_INACTIVE +//! - \b REF_ACTIVE +//! \n indicating the REF generator status +// +//***************************************************************************** +bool REF_isRefGenActive(uint16_t baseAddress) +{ + if (HWREG16((baseAddress) + OFS_REFCTL0) & REFGENACT) + return REF_ACTIVE; + else + return REF_INACTIVE; +} + +#endif +//***************************************************************************** +// +//! Close the doxygen group for ref_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/ref.h b/source/driverlib/MSP430F5xx_6xx/ref.h new file mode 100644 index 0000000..39fbeb4 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/ref.h @@ -0,0 +1,132 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// ref.h - Driver for the REF Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_REF_H__ +#define __MSP430WARE_REF_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_REF__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the referenceVoltageSelect +// parameter for functions: REF_setReferenceVoltage(). +// +//***************************************************************************** +#define REF_VREF1_5V (REFVSEL_0) +#define REF_VREF2_0V (REFVSEL_1) +#define REF_VREF2_5V (REFVSEL_2) + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the REF_isBandgapActive() function and the +// REF_isRefGenActive() function. +// +//***************************************************************************** +#define REF_INACTIVE false +#define REF_ACTIVE true + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the REF_isRefGenBusy() function. +// +//***************************************************************************** +#define REF_NOTBUSY 0x00 +#define REF_BUSY REFGENBUSY + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the REF_getBandgapMode() function. +// +//***************************************************************************** +#define REF_STATICMODE (0x0) +#define REF_SAMPLEMODE (BGMODE) + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void REF_setReferenceVoltage(uint16_t baseAddress, + uint8_t referenceVoltageSelect); + +extern void REF_disableTempSensor(uint16_t baseAddress); + +extern void REF_enableTempSensor(uint16_t baseAddress); + +extern void REF_enableReferenceVoltageOutput(uint16_t baseAddress); + +extern void REF_disableReferenceVoltageOutput(uint16_t baseAddress); + +extern void REF_enableReferenceVoltage(uint16_t baseAddress); + +extern void REF_disableReferenceVoltage(uint16_t baseAddress); + +extern uint16_t REF_getBandgapMode(uint16_t baseAddress); + +extern bool REF_isBandgapActive(uint16_t baseAddress); + +extern uint16_t REF_isRefGenBusy(uint16_t baseAddress); + +extern bool REF_isRefGenActive(uint16_t baseAddress); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_REF_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/rtc_a.c b/source/driverlib/MSP430F5xx_6xx/rtc_a.c new file mode 100644 index 0000000..6af945f --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/rtc_a.c @@ -0,0 +1,835 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// rtc_a.c - Driver for the rtc_a Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup rtc_a_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_RTC__ +#include "rtc_a.h" + +#include + +//***************************************************************************** +// +//! \brief Starts the RTC. +//! +//! This function clears the RTC main hold bit to allow the RTC to function. +//! +//! \param baseAddress is the base address of the RTC_A module. +//! +//! \return None +// +//***************************************************************************** +void RTC_A_startClock(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_RTCCTL01_H) &= ~(RTCHOLD_H); +} + +//***************************************************************************** +// +//! \brief Holds the RTC. +//! +//! This function sets the RTC main hold bit to disable RTC functionality. +//! +//! \param baseAddress is the base address of the RTC_A module. +//! +//! \return None +// +//***************************************************************************** +void RTC_A_holdClock(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_RTCCTL01_H) |= RTCHOLD_H; +} + +//***************************************************************************** +// +//! \brief Allows and Sets the frequency output to RTCCLK pin for calibration +//! measurement. +//! +//! This function sets a frequency to measure at the RTCCLK output pin. After +//! testing the set frequency, the calibration could be set accordingly. +//! +//! \param baseAddress is the base address of the RTC_A module. +//! \param frequencySelect is the frequency output to RTCCLK. +//! Valid values are: +//! - \b RTC_A_CALIBRATIONFREQ_OFF [Default] - turn off calibration +//! output +//! - \b RTC_A_CALIBRATIONFREQ_512HZ - output signal at 512Hz for +//! calibration +//! - \b RTC_A_CALIBRATIONFREQ_256HZ - output signal at 256Hz for +//! calibration +//! - \b RTC_A_CALIBRATIONFREQ_1HZ - output signal at 1Hz for +//! calibration +//! \n Modified bits are \b RTCCALF of \b RTCCTL3 register. +//! +//! \return None +// +//***************************************************************************** +void RTC_A_setCalibrationFrequency(uint16_t baseAddress, + uint16_t frequencySelect) +{ + HWREG16(baseAddress + OFS_RTCCTL23) &= ~(RTCCALF_3); + HWREG16(baseAddress + OFS_RTCCTL23) |= frequencySelect; +} + +//***************************************************************************** +// +//! \brief Sets the specified calibration for the RTC. +//! +//! This function sets the calibration offset to make the RTC as accurate as +//! possible. The offsetDirection can be either +4-ppm or -2-ppm, and the +//! offsetValue should be from 1-63 and is multiplied by the direction setting +//! (i.e. +4-ppm * 8 (offsetValue) = +32-ppm). Please note, when measuring the +//! frequency after setting the calibration, you will only see a change on the +//! 1Hz frequency. +//! +//! \param baseAddress is the base address of the RTC_A module. +//! \param offsetDirection is the direction that the calibration offset will +//! go. +//! Valid values are: +//! - \b RTC_A_CALIBRATION_DOWN2PPM - calibrate at steps of -2 +//! - \b RTC_A_CALIBRATION_UP4PPM - calibrate at steps of +4 +//! \n Modified bits are \b RTCCALS of \b RTCCTL2 register. +//! \param offsetValue is the value that the offset will be a factor of; a +//! valid value is any integer from 1-63. +//! \n Modified bits are \b RTCCAL of \b RTCCTL2 register. +//! +//! \return None +// +//***************************************************************************** +void RTC_A_setCalibrationData(uint16_t baseAddress, + uint8_t offsetDirection, + uint8_t offsetValue) +{ + HWREG8(baseAddress + OFS_RTCCTL23_L) = offsetValue + offsetDirection; +} + +//***************************************************************************** +// +//! \brief Initializes the settings to operate the RTC in Counter mode. +//! +//! This function initializes the Counter mode of the RTC_A. Setting the clock +//! source and counter size will allow an interrupt from the RTCTEVIFG once an +//! overflow to the counter register occurs. +//! +//! \param baseAddress is the base address of the RTC_A module. +//! \param clockSelect is the selected clock for the counter mode to use. +//! Valid values are: +//! - \b RTC_A_CLOCKSELECT_ACLK [Default] +//! - \b RTC_A_CLOCKSELECT_SMCLK +//! - \b RTC_A_CLOCKSELECT_RT1PS - use Prescaler 1 as source to RTC +//! \n Modified bits are \b RTCSSEL of \b RTCCTL1 register. +//! \param counterSizeSelect is the size of the counter. +//! Valid values are: +//! - \b RTC_A_COUNTERSIZE_8BIT [Default] +//! - \b RTC_A_COUNTERSIZE_16BIT +//! - \b RTC_A_COUNTERSIZE_24BIT +//! - \b RTC_A_COUNTERSIZE_32BIT +//! \n Modified bits are \b RTCTEV of \b RTCCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void RTC_A_initCounter(uint16_t baseAddress, + uint16_t clockSelect, + uint16_t counterSizeSelect) +{ + HWREG8(baseAddress + OFS_RTCCTL01_H) |= RTCHOLD_H; + HWREG8(baseAddress + OFS_RTCCTL01_H) &= ~(RTCMODE_H); + + HWREG16(baseAddress + OFS_RTCCTL01) &= 0xF0FF; //~(RTCSSEL_3 + RTCTEV_3); + HWREG16(baseAddress + OFS_RTCCTL01) |= clockSelect + counterSizeSelect; +} + +//***************************************************************************** +// +//! \brief Initializes the settings to operate the RTC in calendar mode +//! +//! This function initializes the Calendar mode of the RTC module. +//! +//! \param baseAddress is the base address of the RTC_A module. +//! \param CalendarTime is the pointer to the structure containing the values +//! for the Calendar to be initialized to. Valid values should be of +//! type pointer to Calendar and should contain the following members +//! and corresponding values: \b Seconds between 0-59 \b Minutes between +//! 0-59 \b Hours between 0-24 \b DayOfWeek between 0-6 \b DayOfMonth +//! between 0-31 \b Year between 0-4095 NOTE: Values beyond the ones +//! specified may result in erratic behavior. +//! \param formatSelect is the format for the Calendar registers to use. +//! Valid values are: +//! - \b RTC_A_FORMAT_BINARY [Default] +//! - \b RTC_A_FORMAT_BCD +//! \n Modified bits are \b RTCBCD of \b RTCCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void RTC_A_initCalendar(uint16_t baseAddress, + Calendar *CalendarTime, + uint16_t formatSelect) +{ + HWREG8(baseAddress + OFS_RTCCTL01_H) |= RTCMODE_H + RTCHOLD_H; + + HWREG16(baseAddress + OFS_RTCCTL01) &= ~(RTCBCD); + HWREG16(baseAddress + OFS_RTCCTL01) |= formatSelect; + + HWREG8(baseAddress + OFS_RTCTIM0_L) = CalendarTime->Seconds; + HWREG8(baseAddress + OFS_RTCTIM0_H) = CalendarTime->Minutes; + HWREG8(baseAddress + OFS_RTCTIM1_L) = CalendarTime->Hours; + HWREG8(baseAddress + OFS_RTCTIM1_H) = CalendarTime->DayOfWeek; + HWREG8(baseAddress + OFS_RTCDATE_L) = CalendarTime->DayOfMonth; + HWREG8(baseAddress + OFS_RTCDATE_H) = CalendarTime->Month; + HWREG16(baseAddress + OFS_RTCYEAR) = CalendarTime->Year; +} + +//***************************************************************************** +// +//! \brief Deprecated - Initializes the settings to operate the RTC in calendar +//! mode +//! +//! This function initializes the Calendar mode of the RTC module. +//! +//! \param baseAddress is the base address of the RTC_A module. +//! \param CalendarTime is the structure containing the values for the Calendar +//! to be initialized to. Valid values should be of type Calendar and +//! should contain the following members and corresponding values: \b +//! Seconds between 0-59 \b Minutes between 0-59 \b Hours between 0-24 +//! \b DayOfWeek between 0-6 \b DayOfMonth between 0-31 \b Year between +//! 0-4095 NOTE: Values beyond the ones specified may result in erratic +//! behavior. +//! \param formatSelect is the format for the Calendar registers to use. +//! Valid values are: +//! - \b RTC_A_FORMAT_BINARY [Default] +//! - \b RTC_A_FORMAT_BCD +//! \n Modified bits are \b RTCBCD of \b RTCCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void RTC_A_calendarInit(uint16_t baseAddress, + Calendar CalendarTime, + uint16_t formatSelect) +{ + HWREG8(baseAddress + OFS_RTCCTL01_H) |= RTCMODE_H + RTCHOLD_H; + + HWREG16(baseAddress + OFS_RTCCTL01) &= ~(RTCBCD); + HWREG16(baseAddress + OFS_RTCCTL01) |= formatSelect; + + HWREG8(baseAddress + OFS_RTCTIM0_L) = CalendarTime.Seconds; + HWREG8(baseAddress + OFS_RTCTIM0_H) = CalendarTime.Minutes; + HWREG8(baseAddress + OFS_RTCTIM1_L) = CalendarTime.Hours; + HWREG8(baseAddress + OFS_RTCTIM1_H) = CalendarTime.DayOfWeek; + HWREG8(baseAddress + OFS_RTCDATE_L) = CalendarTime.DayOfMonth; + HWREG8(baseAddress + OFS_RTCDATE_H) = CalendarTime.Month; + HWREG16(baseAddress + OFS_RTCYEAR) = CalendarTime.Year; +} + +//***************************************************************************** +// +//! \brief Returns the Calendar Time stored in the Calendar registers of the +//! RTC. +//! +//! This function returns the current Calendar time in the form of a Calendar +//! structure. The RTCRDY polling is used in this function to prevent reading +//! invalid time. +//! +//! \param baseAddress is the base address of the RTC_A module. +//! +//! \return A Calendar structure containing the current time. +// +//***************************************************************************** +Calendar RTC_A_getCalendarTime(uint16_t baseAddress) +{ + Calendar tempCal; + + while ( !(HWREG16(baseAddress + OFS_RTCCTL01) & RTCRDY) ) ; + + tempCal.Seconds = HWREG8(baseAddress + OFS_RTCTIM0_L); + tempCal.Minutes = HWREG8(baseAddress + OFS_RTCTIM0_H); + tempCal.Hours = HWREG8(baseAddress + OFS_RTCTIM1_L); + tempCal.DayOfWeek = HWREG8(baseAddress + OFS_RTCTIM1_H); + tempCal.DayOfMonth = HWREG8(baseAddress + OFS_RTCDATE_L); + tempCal.Month = HWREG8(baseAddress + OFS_RTCDATE_H); + tempCal.Year = HWREG16(baseAddress + OFS_RTCYEAR); + + return tempCal; +} + +//***************************************************************************** +// +//! \brief DEPRECATED - Sets and Enables the desired Calendar Alarm settings. +//! +//! This function sets a Calendar interrupt condition to assert the RTCAIFG +//! interrupt flag. The condition is a logical and of all of the parameters. +//! For example if the minutes and hours alarm is set, then the interrupt will +//! only assert when the minutes AND the hours change to the specified setting. +//! Use the RTC_A_ALARM_OFF for any alarm settings that should not be apart of +//! the alarm condition. +//! +//! \param baseAddress is the base address of the RTC_A module. +//! \param minutesAlarm is the alarm condition for the minutes. +//! Valid values are: +//! - \b RTC_A_ALARMCONDITION_OFF [Default] +//! - \b An integer between 0-59 +//! \param hoursAlarm is the alarm condition for the hours. +//! Valid values are: +//! - \b RTC_A_ALARMCONDITION_OFF [Default] +//! - \b An integer between 0-24 +//! \param dayOfWeekAlarm is the alarm condition for the day of week. +//! Valid values are: +//! - \b RTC_A_ALARMCONDITION_OFF [Default] +//! - \b An integer between 0-6 +//! \param dayOfMonthAlarm is the alarm condition for the day of the month. +//! Valid values are: +//! - \b RTC_A_ALARMCONDITION_OFF [Default] +//! - \b An integer between 0-31 +//! +//! \return None +// +//***************************************************************************** +void RTC_A_setCalendarAlarm(uint16_t baseAddress, + uint8_t minutesAlarm, + uint8_t hoursAlarm, + uint8_t dayOfWeekAlarm, + uint8_t dayOfMonthAlarm) +{ + RTC_A_configureCalendarAlarmParam param = { 0 }; + + param.minutesAlarm = minutesAlarm; + param.hoursAlarm = hoursAlarm; + param.dayOfWeekAlarm = dayOfWeekAlarm; + param.dayOfMonthAlarm = dayOfMonthAlarm; + + RTC_A_configureCalendarAlarm(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Sets and Enables the desired Calendar Alarm settings. +//! +//! This function sets a Calendar interrupt condition to assert the RTCAIFG +//! interrupt flag. The condition is a logical and of all of the parameters. +//! For example if the minutes and hours alarm is set, then the interrupt will +//! only assert when the minutes AND the hours change to the specified setting. +//! Use the RTC_A_ALARM_OFF for any alarm settings that should not be apart of +//! the alarm condition. +//! +//! \param baseAddress is the base address of the RTC_A module. +//! \param param is the pointer to struct for calendar alarm configuration. +//! +//! \return None +// +//***************************************************************************** +void RTC_A_configureCalendarAlarm(uint16_t baseAddress, + RTC_A_configureCalendarAlarmParam *param) +{ + assert(param != 0); + + //Each of these is XORed with 0x80 to turn on if an integer is passed, + //or turn OFF if RTC_A_ALARM_OFF (0x80) is passed. + HWREG8(baseAddress + OFS_RTCAMINHR_L) = (param->minutesAlarm ^ 0x80); + HWREG8(baseAddress + OFS_RTCAMINHR_H) = (param->hoursAlarm ^ 0x80); + HWREG8(baseAddress + OFS_RTCADOWDAY_L) = (param->dayOfWeekAlarm ^ 0x80); + HWREG8(baseAddress + OFS_RTCADOWDAY_H) = (param->dayOfMonthAlarm ^ 0x80); +} //***************************************************************************** +// +//! \brief Sets a single specified Calendar interrupt condition +//! +//! This function sets a specified event to assert the RTCTEVIFG interrupt. +//! This interrupt is independent from the Calendar alarm interrupt. +//! +//! \param baseAddress is the base address of the RTC_A module. +//! \param eventSelect is the condition selected. +//! Valid values are: +//! - \b RTC_A_CALENDAREVENT_MINUTECHANGE - assert interrupt on every +//! minute +//! - \b RTC_A_CALENDAREVENT_HOURCHANGE - assert interrupt on every hour +//! - \b RTC_A_CALENDAREVENT_NOON - assert interrupt when hour is 12 +//! - \b RTC_A_CALENDAREVENT_MIDNIGHT - assert interrupt when hour is 0 +//! \n Modified bits are \b RTCTEV of \b RTCCTL register. +//! +//! \return None +// +//***************************************************************************** +void RTC_A_setCalendarEvent(uint16_t baseAddress, + uint16_t eventSelect) +{ + HWREG16(baseAddress + OFS_RTCCTL01) &= ~(RTCTEV_3); //Reset bits + HWREG16(baseAddress + OFS_RTCCTL01) |= eventSelect; +} + +//***************************************************************************** +// +//! \brief Returns the value of the Counter register. +//! +//! This function returns the value of the counter register for the RTC_A +//! module. It will return the 32-bit value no matter the size set during +//! initialization. The RTC should be held before trying to use this function. +//! +//! \param baseAddress is the base address of the RTC_A module. +//! +//! \return The raw value of the full 32-bit Counter Register. +// +//***************************************************************************** +uint32_t RTC_A_getCounterValue(uint16_t baseAddress) +{ + if ( (HWREG8(baseAddress + OFS_RTCCTL01_H) & RTCHOLD_H) + || (HWREG8(baseAddress + OFS_RTCPS1CTL) & RT1PSHOLD) ) + return 0; + + uint32_t counterValue_L = HWREG16(baseAddress + OFS_RTCTIM0); + uint32_t counterValue_H = HWREG16(baseAddress + OFS_RTCTIM1); + return (counterValue_H << 16) + counterValue_L; +} + +//***************************************************************************** +// +//! \brief Sets the value of the Counter register +//! +//! This function sets the counter register of the RTC_A module. +//! +//! \param baseAddress is the base address of the RTC_A module. +//! \param counterValue is the value to set the Counter register to; a valid +//! value may be any 32-bit integer. +//! +//! \return None +// +//***************************************************************************** +void RTC_A_setCounterValue(uint16_t baseAddress, + uint32_t counterValue) +{ + HWREG16(baseAddress + OFS_RTCTIM0) = counterValue; + HWREG16(baseAddress + OFS_RTCTIM1) = ( counterValue >> 16 ); +} + +//***************************************************************************** +// +//! \brief Initializes the Prescaler for Counter mode. +//! +//! This function initializes the selected prescaler for the counter mode in +//! the RTC_A module. If the RTC is initialized in Calendar mode, then these +//! are automatically initialized. The Prescalers can be used to divide a clock +//! source additionally before it gets to the main RTC clock. +//! +//! \param baseAddress is the base address of the RTC_A module. +//! \param prescaleSelect is the prescaler to initialize. +//! Valid values are: +//! - \b RTC_A_PRESCALE_0 +//! - \b RTC_A_PRESCALE_1 +//! \param prescaleClockSelect is the clock to drive the selected prescaler. +//! Valid values are: +//! - \b RTC_A_PSCLOCKSELECT_ACLK +//! - \b RTC_A_PSCLOCKSELECT_SMCLK +//! - \b RTC_A_PSCLOCKSELECT_RT0PS - use Prescaler 0 as source to +//! Prescaler 1 (May only be used if prescaleSelect is +//! RTC_A_PRESCALE_1) +//! \n Modified bits are \b RTxSSEL of \b RTCPSxCTL register. +//! \param prescaleDivider is the divider for the selected clock source. +//! Valid values are: +//! - \b RTC_A_PSDIVIDER_2 [Default] +//! - \b RTC_A_PSDIVIDER_4 +//! - \b RTC_A_PSDIVIDER_8 +//! - \b RTC_A_PSDIVIDER_16 +//! - \b RTC_A_PSDIVIDER_32 +//! - \b RTC_A_PSDIVIDER_64 +//! - \b RTC_A_PSDIVIDER_128 +//! - \b RTC_A_PSDIVIDER_256 +//! \n Modified bits are \b RTxPSDIV of \b RTCPSxCTL register. +//! +//! \return None +// +//***************************************************************************** +void RTC_A_initCounterPrescale(uint16_t baseAddress, + uint8_t prescaleSelect, + uint16_t prescaleClockSelect, + uint16_t prescaleDivider) +{ + //Reset bits and set clock select + HWREG16(baseAddress + OFS_RTCPS0CTL + prescaleSelect) = + prescaleClockSelect + prescaleDivider; +} + +//***************************************************************************** +// +//! \brief Holds the selected Prescaler. +//! +//! This function holds the prescale counter from continuing. This will only +//! work in counter mode, in Calendar mode, the RTC_A_holdClock() must be used. +//! In counter mode, if using both prescalers in conjunction with the main RTC +//! counter, then stopping RT0PS will stop RT1PS, but stopping RT1PS will not +//! stop RT0PS. +//! +//! \param baseAddress is the base address of the RTC_A module. +//! \param prescaleSelect is the prescaler to hold. +//! Valid values are: +//! - \b RTC_A_PRESCALE_0 +//! - \b RTC_A_PRESCALE_1 +//! +//! \return None +// +//***************************************************************************** +void RTC_A_holdCounterPrescale(uint16_t baseAddress, + uint8_t prescaleSelect) +{ + HWREG8(baseAddress + OFS_RTCPS0CTL_H + prescaleSelect) |= RT0PSHOLD_H; +} + +//***************************************************************************** +// +//! \brief Starts the selected Prescaler. +//! +//! This function starts the selected prescale counter. This function will only +//! work if the RTC is in counter mode. +//! +//! \param baseAddress is the base address of the RTC_A module. +//! \param prescaleSelect is the prescaler to start. +//! Valid values are: +//! - \b RTC_A_PRESCALE_0 +//! - \b RTC_A_PRESCALE_1 +//! +//! \return None +// +//***************************************************************************** +void RTC_A_startCounterPrescale(uint16_t baseAddress, + uint8_t prescaleSelect) +{ + HWREG8(baseAddress + OFS_RTCPS0CTL_H + prescaleSelect) &= ~(RT0PSHOLD_H); +} + +//***************************************************************************** +// +//! \brief Sets up an interrupt condition for the selected Prescaler. +//! +//! This function sets the condition for an interrupt to assert based on the +//! individual prescalers. +//! +//! \param baseAddress is the base address of the RTC_A module. +//! \param prescaleSelect is the prescaler to define an interrupt for. +//! Valid values are: +//! - \b RTC_A_PRESCALE_0 +//! - \b RTC_A_PRESCALE_1 +//! \param prescaleEventDivider is a divider to specify when an interrupt can +//! occur based on the clock source of the selected prescaler. (Does not +//! affect timer of the selected prescaler). +//! Valid values are: +//! - \b RTC_A_PSEVENTDIVIDER_2 [Default] +//! - \b RTC_A_PSEVENTDIVIDER_4 +//! - \b RTC_A_PSEVENTDIVIDER_8 +//! - \b RTC_A_PSEVENTDIVIDER_16 +//! - \b RTC_A_PSEVENTDIVIDER_32 +//! - \b RTC_A_PSEVENTDIVIDER_64 +//! - \b RTC_A_PSEVENTDIVIDER_128 +//! - \b RTC_A_PSEVENTDIVIDER_256 +//! \n Modified bits are \b RTxIP of \b RTCPSxCTL register. +//! +//! \return None +// +//***************************************************************************** +void RTC_A_definePrescaleEvent(uint16_t baseAddress, + uint8_t prescaleSelect, + uint8_t prescaleEventDivider) +{ + HWREG8(baseAddress + OFS_RTCPS0CTL_L + prescaleSelect) &= ~(RT0IP_7); + HWREG8(baseAddress + OFS_RTCPS0CTL_L + + prescaleSelect) |= prescaleEventDivider; +} + +//***************************************************************************** +// +//! \brief Returns the selected prescaler value. +//! +//! This function returns the value of the selected prescale counter register. +//! Note that the counter value should be held by calling RTC_A_holdClock() +//! before calling this API. +//! +//! \param baseAddress is the base address of the RTC_A module. +//! \param prescaleSelect is the prescaler to obtain the value of. +//! Valid values are: +//! - \b RTC_A_PRESCALE_0 +//! - \b RTC_A_PRESCALE_1 +//! +//! \return The value of the specified prescaler count register +// +//***************************************************************************** +uint8_t RTC_A_getPrescaleValue(uint16_t baseAddress, + uint8_t prescaleSelect) +{ + if (HWREG8(baseAddress + OFS_RTCPS0CTL_H + prescaleSelect) & RT0PSHOLD_H) + return 0; + + if (RTC_A_PRESCALE_0 == prescaleSelect) + return HWREG8(baseAddress + OFS_RTCPS_L); + else if (RTC_A_PRESCALE_1 == prescaleSelect) + return HWREG8(baseAddress + OFS_RTCPS_H); + else + return 0; +} + +//***************************************************************************** +// +//! \brief Sets the selected prescaler value. +//! +//! This function sets the prescale counter value. Before setting the prescale +//! counter, it should be held by calling RTC_A_holdClock(). +//! +//! \param baseAddress is the base address of the RTC_A module. +//! \param prescaleSelect is the prescaler to set the value for. +//! Valid values are: +//! - \b RTC_A_PRESCALE_0 +//! - \b RTC_A_PRESCALE_1 +//! \param prescaleCounterValue is the specified value to set the prescaler to. +//! Valid values are any integer between 0-255 +//! \n Modified bits are \b RTxPS of \b RTxPS register. +//! +//! \return None +// +//***************************************************************************** +void RTC_A_setPrescaleValue(uint16_t baseAddress, + uint8_t prescaleSelect, + uint8_t prescaleCounterValue) +{ + if (RTC_A_PRESCALE_0 == prescaleSelect) + HWREG8(baseAddress + OFS_RTCPS_L) = prescaleCounterValue; + else if (RTC_A_PRESCALE_1 == prescaleSelect) + HWREG8(baseAddress + OFS_RTCPS_H) = prescaleCounterValue; +} + +//***************************************************************************** +// +//! \brief Enables selected RTC interrupt sources. +//! +//! This function enables the selected RTC interrupt source. Only the sources +//! that are enabled can be reflected to the processor interrupt; disabled +//! sources have no effect on the processor. Does not clear interrupt flags. +//! +//! \param baseAddress is the base address of the RTC_A module. +//! \param interruptMask is a bit mask of the interrupts to enable. +//! Mask value is the logical OR of any of the following: +//! - \b RTC_A_TIME_EVENT_INTERRUPT - asserts when counter overflows in +//! counter mode or when Calendar event condition defined by +//! defineCalendarEvent() is met. +//! - \b RTC_A_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in +//! Calendar mode is met. +//! - \b RTC_A_CLOCK_READ_READY_INTERRUPT - asserts when Calendar +//! registers are settled. +//! - \b RTC_A_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0 +//! event condition is met. +//! - \b RTC_A_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1 +//! event condition is met. +//! +//! \return None +// +//***************************************************************************** +void RTC_A_enableInterrupt(uint16_t baseAddress, + uint8_t interruptMask) +{ + if ( interruptMask & (RTCTEVIE + RTCAIE + RTCRDYIE) ) + HWREG8(baseAddress + OFS_RTCCTL01_L) |= + (interruptMask & (RTCTEVIE + RTCAIE + RTCRDYIE)); + + if (interruptMask & RTC_A_PRESCALE_TIMER0_INTERRUPT) + HWREG8(baseAddress + OFS_RTCPS0CTL) |= RT0PSIE; + + if (interruptMask & RTC_A_PRESCALE_TIMER1_INTERRUPT) + HWREG8(baseAddress + OFS_RTCPS1CTL) |= RT1PSIE; +} + +//***************************************************************************** +// +//! \brief Disables selected RTC interrupt sources. +//! +//! This function disables the selected RTC interrupt source. Only the sources +//! that are enabled can be reflected to the processor interrupt; disabled +//! sources have no effect on the processor. +//! +//! \param baseAddress is the base address of the RTC_A module. +//! \param interruptMask is a bit mask of the interrupts to disable. +//! Mask value is the logical OR of any of the following: +//! - \b RTC_A_TIME_EVENT_INTERRUPT - asserts when counter overflows in +//! counter mode or when Calendar event condition defined by +//! defineCalendarEvent() is met. +//! - \b RTC_A_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in +//! Calendar mode is met. +//! - \b RTC_A_CLOCK_READ_READY_INTERRUPT - asserts when Calendar +//! registers are settled. +//! - \b RTC_A_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0 +//! event condition is met. +//! - \b RTC_A_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1 +//! event condition is met. +//! +//! \return None +// +//***************************************************************************** +void RTC_A_disableInterrupt(uint16_t baseAddress, + uint8_t interruptMask) +{ + if ( interruptMask & ( RTCTEVIE + RTCAIE + RTCRDYIE) ) + HWREG8(baseAddress + OFS_RTCCTL01_L) &= + ~(interruptMask & (RTCTEVIE + RTCAIE + RTCRDYIE)); + + if (interruptMask & RTC_A_PRESCALE_TIMER0_INTERRUPT) + HWREG8(baseAddress + OFS_RTCPS0CTL) &= ~(RT0PSIE); + + if (interruptMask & RTC_A_PRESCALE_TIMER1_INTERRUPT) + HWREG8(baseAddress + OFS_RTCPS1CTL) &= ~(RT1PSIE); +} + +//***************************************************************************** +// +//! \brief Returns the status of the selected interrupts flags. +//! +//! This function returns the status of the interrupt flag for the selected +//! channel. +//! +//! \param baseAddress is the base address of the RTC_A module. +//! \param interruptFlagMask is a bit mask of the interrupt flags to return the +//! status of. +//! Mask value is the logical OR of any of the following: +//! - \b RTC_A_TIME_EVENT_INTERRUPT - asserts when counter overflows in +//! counter mode or when Calendar event condition defined by +//! defineCalendarEvent() is met. +//! - \b RTC_A_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in +//! Calendar mode is met. +//! - \b RTC_A_CLOCK_READ_READY_INTERRUPT - asserts when Calendar +//! registers are settled. +//! - \b RTC_A_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0 +//! event condition is met. +//! - \b RTC_A_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1 +//! event condition is met. +//! +//! \return Logical OR of any of the following: +//! - \b RTC_A_TIME_EVENT_INTERRUPT asserts when counter overflows in +//! counter mode or when Calendar event condition defined by +//! defineCalendarEvent() is met. +//! - \b RTC_A_CLOCK_ALARM_INTERRUPT asserts when alarm condition in +//! Calendar mode is met. +//! - \b RTC_A_CLOCK_READ_READY_INTERRUPT asserts when Calendar +//! registers are settled. +//! - \b RTC_A_PRESCALE_TIMER0_INTERRUPT asserts when Prescaler 0 event +//! condition is met. +//! - \b RTC_A_PRESCALE_TIMER1_INTERRUPT asserts when Prescaler 1 event +//! condition is met. +//! \n indicating the status of the masked interrupts +// +//***************************************************************************** +uint8_t RTC_A_getInterruptStatus(uint16_t baseAddress, + uint8_t interruptFlagMask) +{ + uint8_t tempInterruptFlagMask = 0x0000; + + tempInterruptFlagMask |= (HWREG8(baseAddress + OFS_RTCCTL01_L) + & ((interruptFlagMask >> 4) + & ( + RTCTEVIFG + + RTCAIFG + + RTCRDYIFG))); + + tempInterruptFlagMask = tempInterruptFlagMask << 4; + + if (interruptFlagMask & RTC_A_PRESCALE_TIMER0_INTERRUPT) + if ( HWREG8(baseAddress + OFS_RTCPS0CTL) & RT0PSIFG) + tempInterruptFlagMask |= RTC_A_PRESCALE_TIMER0_INTERRUPT; + + if (interruptFlagMask & RTC_A_PRESCALE_TIMER1_INTERRUPT) + if ( HWREG8(baseAddress + OFS_RTCPS1CTL) & RT1PSIFG) + tempInterruptFlagMask |= RTC_A_PRESCALE_TIMER1_INTERRUPT; + + return tempInterruptFlagMask; +} + +//***************************************************************************** +// +//! \brief Clears selected RTC interrupt flags. +//! +//! This function clears the RTC interrupt flag is cleared, so that it no +//! longer asserts. +//! +//! \param baseAddress is the base address of the RTC_A module. +//! \param interruptFlagMask is a bit mask of the interrupt flags to be +//! cleared. +//! Mask value is the logical OR of any of the following: +//! - \b RTC_A_TIME_EVENT_INTERRUPT - asserts when counter overflows in +//! counter mode or when Calendar event condition defined by +//! defineCalendarEvent() is met. +//! - \b RTC_A_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in +//! Calendar mode is met. +//! - \b RTC_A_CLOCK_READ_READY_INTERRUPT - asserts when Calendar +//! registers are settled. +//! - \b RTC_A_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0 +//! event condition is met. +//! - \b RTC_A_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1 +//! event condition is met. +//! +//! \return None +// +//***************************************************************************** +void RTC_A_clearInterrupt(uint16_t baseAddress, + uint8_t interruptFlagMask) +{ + if ( interruptFlagMask & (RTC_A_TIME_EVENT_INTERRUPT + + RTC_A_CLOCK_ALARM_INTERRUPT + + RTC_A_CLOCK_READ_READY_INTERRUPT + ) ) { + + HWREG8(baseAddress + OFS_RTCCTL01_L) &= + ~((interruptFlagMask >> 4) & (RTCTEVIFG + + RTCAIFG + + RTCRDYIFG)); + } + + if (interruptFlagMask & RTC_A_PRESCALE_TIMER0_INTERRUPT) + HWREG8(baseAddress + OFS_RTCPS0CTL) &= ~(RT0PSIFG); + + if (interruptFlagMask & RTC_A_PRESCALE_TIMER1_INTERRUPT) + HWREG8(baseAddress + OFS_RTCPS1CTL) &= ~(RT1PSIFG); +} + + +#endif +//***************************************************************************** +// +//! Close the doxygen group for rtc_a_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/rtc_a.h b/source/driverlib/MSP430F5xx_6xx/rtc_a.h new file mode 100644 index 0000000..cb6d48b --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/rtc_a.h @@ -0,0 +1,353 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// rtc_a.h - Driver for the RTC_A Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_RTC_A_H__ +#define __MSP430WARE_RTC_A_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_RTC__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following is a struct that can be passed to RTC_A_CalendarInit() in the +// CalendarTime parameter, as well as returned by RTC_A_getCalendarTime() +// +//***************************************************************************** +typedef struct { + uint8_t Seconds; + uint8_t Minutes; + uint8_t Hours; + uint8_t DayOfWeek; + uint8_t DayOfMonth; + uint8_t Month; + uint16_t Year; +} Calendar; + +//****************************************************************************** +// +// The following is a struct that is passed to RTC_A_configureCalendarAlarm() +// +//****************************************************************************** +typedef struct RTC_A_configureCalendarAlarmParam { + uint8_t minutesAlarm; + uint8_t hoursAlarm; + uint8_t dayOfWeekAlarm; + uint8_t dayOfMonthAlarm; +} RTC_A_configureCalendarAlarmParam; + +//***************************************************************************** +// +// The following are values that can be passed to the frequencySelect parameter +// for functions: RTC_A_setCalibrationFrequency(). +// +//***************************************************************************** +#define RTC_A_CALIBRATIONFREQ_OFF (RTCCALF_0) +#define RTC_A_CALIBRATIONFREQ_512HZ (RTCCALF_1) +#define RTC_A_CALIBRATIONFREQ_256HZ (RTCCALF_2) +#define RTC_A_CALIBRATIONFREQ_1HZ (RTCCALF_3) + +//***************************************************************************** +// +// The following are values that can be passed to the offsetDirection parameter +// for functions: RTC_A_setCalibrationData(). +// +//***************************************************************************** +#define RTC_A_CALIBRATION_DOWN2PPM (!(RTCCALS)) +#define RTC_A_CALIBRATION_UP4PPM (RTCCALS) + +//***************************************************************************** +// +// The following are values that can be passed to the formatSelect parameter +// for functions: RTC_A_initCalendar(), and RTC_A_calendarInit(). +// +//***************************************************************************** +#define RTC_A_FORMAT_BINARY (!(RTCBCD)) +#define RTC_A_FORMAT_BCD (RTCBCD) + +//***************************************************************************** +// +// The following are values that can be passed to the minutesAlarm parameter +// for functions: RTC_A_setCalendarAlarm(); the dayOfMonthAlarm parameter for +// functions: RTC_A_setCalendarAlarm(); the hoursAlarm parameter for functions: +// RTC_A_setCalendarAlarm(); the dayOfWeekAlarm parameter for functions: +// RTC_A_setCalendarAlarm(). +// +//***************************************************************************** +#define RTC_A_ALARMCONDITION_OFF (0x80) + +//***************************************************************************** +// +// The following are values that can be passed to the eventSelect parameter for +// functions: RTC_A_setCalendarEvent(). +// +//***************************************************************************** +#define RTC_A_CALENDAREVENT_MINUTECHANGE (RTCTEV_0) +#define RTC_A_CALENDAREVENT_HOURCHANGE (RTCTEV_1) +#define RTC_A_CALENDAREVENT_NOON (RTCTEV_2) +#define RTC_A_CALENDAREVENT_MIDNIGHT (RTCTEV_3) + +//***************************************************************************** +// +// The following are values that can be passed to the prescaleSelect parameter +// for functions: RTC_A_initCounterPrescale(), RTC_A_holdCounterPrescale(), +// RTC_A_startCounterPrescale(), RTC_A_definePrescaleEvent(), +// RTC_A_getPrescaleValue(), and RTC_A_setPrescaleValue(). +// +//***************************************************************************** +#define RTC_A_PRESCALE_0 (0x0) +#define RTC_A_PRESCALE_1 (0x2) + +//***************************************************************************** +// +// The following are values that can be passed to the clockSelect parameter for +// functions: RTC_A_initCounter(). +// +//***************************************************************************** +#define RTC_A_CLOCKSELECT_ACLK (RTCSSEL_0) +#define RTC_A_CLOCKSELECT_SMCLK (RTCSSEL_1) +#define RTC_A_CLOCKSELECT_RT1PS (RTCSSEL_2) + +//***************************************************************************** +// +// The following are values that can be passed to the prescaleClockSelect +// parameter for functions: RTC_A_initCounterPrescale(). +// +//***************************************************************************** +#define RTC_A_PSCLOCKSELECT_ACLK (RT1SSEL_0) +#define RTC_A_PSCLOCKSELECT_SMCLK (RT1SSEL_1) +#define RTC_A_PSCLOCKSELECT_RT0PS (RT1SSEL_2) + +//***************************************************************************** +// +// The following are values that can be passed to the counterSizeSelect +// parameter for functions: RTC_A_initCounter(). +// +//***************************************************************************** +#define RTC_A_COUNTERSIZE_8BIT (RTCTEV_0) +#define RTC_A_COUNTERSIZE_16BIT (RTCTEV_1) +#define RTC_A_COUNTERSIZE_24BIT (RTCTEV_2) +#define RTC_A_COUNTERSIZE_32BIT (RTCTEV_3) + +//***************************************************************************** +// +// The following are values that can be passed to the prescaleDivider parameter +// for functions: RTC_A_initCounterPrescale(). +// +//***************************************************************************** +#define RTC_A_PSDIVIDER_2 (RT0PSDIV_0) +#define RTC_A_PSDIVIDER_4 (RT0PSDIV_1) +#define RTC_A_PSDIVIDER_8 (RT0PSDIV_2) +#define RTC_A_PSDIVIDER_16 (RT0PSDIV_3) +#define RTC_A_PSDIVIDER_32 (RT0PSDIV_4) +#define RTC_A_PSDIVIDER_64 (RT0PSDIV_5) +#define RTC_A_PSDIVIDER_128 (RT0PSDIV_6) +#define RTC_A_PSDIVIDER_256 (RT0PSDIV_7) + +//***************************************************************************** +// +// The following are values that can be passed to the prescaleEventDivider +// parameter for functions: RTC_A_definePrescaleEvent(). +// +//***************************************************************************** +#define RTC_A_PSEVENTDIVIDER_2 (RT0IP_0) +#define RTC_A_PSEVENTDIVIDER_4 (RT0IP_1) +#define RTC_A_PSEVENTDIVIDER_8 (RT0IP_2) +#define RTC_A_PSEVENTDIVIDER_16 (RT0IP_3) +#define RTC_A_PSEVENTDIVIDER_32 (RT0IP_4) +#define RTC_A_PSEVENTDIVIDER_64 (RT0IP_5) +#define RTC_A_PSEVENTDIVIDER_128 (RT0IP_6) +#define RTC_A_PSEVENTDIVIDER_256 (RT0IP_7) + +//***************************************************************************** +// +// The following are values that can be passed to the interruptMask parameter +// for functions: RTC_A_enableInterrupt(), and RTC_A_disableInterrupt(); the +// interruptFlagMask parameter for functions: RTC_A_getInterruptStatus(), and +// RTC_A_clearInterrupt() as well as returned by the RTC_A_getInterruptStatus() +// function. +// +//***************************************************************************** +#define RTC_A_TIME_EVENT_INTERRUPT RTCTEVIE +#define RTC_A_CLOCK_ALARM_INTERRUPT RTCAIE +#define RTC_A_CLOCK_READ_READY_INTERRUPT RTCRDYIE +#define RTC_A_PRESCALE_TIMER0_INTERRUPT 0x02 +#define RTC_A_PRESCALE_TIMER1_INTERRUPT 0x01 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void RTC_A_startClock(uint16_t baseAddress); + +extern void RTC_A_holdClock(uint16_t baseAddress); + +extern void RTC_A_setCalibrationFrequency(uint16_t baseAddress, + uint16_t frequencySelect); + +extern void RTC_A_setCalibrationData(uint16_t baseAddress, + uint8_t offsetDirection, + uint8_t offsetValue); + +extern void RTC_A_initCounter(uint16_t baseAddress, + uint16_t clockSelect, + uint16_t counterSizeSelect); + +extern void RTC_A_initCalendar(uint16_t baseAddress, + Calendar *CalendarTime, + uint16_t formatSelect); + +extern Calendar RTC_A_getCalendarTime(uint16_t baseAddress); + +extern void RTC_A_configureCalendarAlarm(uint16_t baseAddress, + RTC_A_configureCalendarAlarmParam *param); + +extern void RTC_A_setCalendarEvent(uint16_t baseAddress, + uint16_t eventSelect); + +extern uint32_t RTC_A_getCounterValue(uint16_t baseAddress); + +extern void RTC_A_setCounterValue(uint16_t baseAddress, + uint32_t counterValue); + +extern void RTC_A_initCounterPrescale(uint16_t baseAddress, + uint8_t prescaleSelect, + uint16_t prescaleClockSelect, + uint16_t prescaleDivider); + +extern void RTC_A_holdCounterPrescale(uint16_t baseAddress, + uint8_t prescaleSelect); + +extern void RTC_A_startCounterPrescale(uint16_t baseAddress, + uint8_t prescaleSelect); + +extern void RTC_A_definePrescaleEvent(uint16_t baseAddress, + uint8_t prescaleSelect, + uint8_t prescaleEventDivider); + +extern uint8_t RTC_A_getPrescaleValue(uint16_t baseAddress, + uint8_t prescaleSelect); + +extern void RTC_A_setPrescaleValue(uint16_t baseAddress, + uint8_t prescaleSelect, + uint8_t prescaleCounterValue); + +extern void RTC_A_enableInterrupt(uint16_t baseAddress, + uint8_t interruptMask); + +extern void RTC_A_disableInterrupt(uint16_t baseAddress, + uint8_t interruptMask); + +extern uint8_t RTC_A_getInterruptStatus(uint16_t baseAddress, + uint8_t interruptFlagMask); + +extern void RTC_A_clearInterrupt(uint16_t baseAddress, + uint8_t interruptFlagMask); + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +#define RTC_A_CounterInit RTC_A_initCounter + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +#define RTC_A_setPrescaleCounterValue RTC_A_setPrescaleValue + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +#define RTC_A_counterPrescaleInit RTC_A_initCounterPrescale + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +#define RTC_A_counterPrescaleStart RTC_A_startCounterPrescale + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +#define RTC_A_counterPrescaleHold RTC_A_holdCounterPrescale + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +extern void RTC_A_calendarInit(uint16_t baseAddress, + Calendar CalendarTime, + uint16_t formatSelect); + +extern void RTC_A_setCalendarAlarm(uint16_t baseAddress, + uint8_t minutesAlarm, + uint8_t hoursAlarm, + uint8_t dayOfWeekAlarm, + uint8_t dayOfMonthAlarm); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_RTC_A_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/rtc_b.c b/source/driverlib/MSP430F5xx_6xx/rtc_b.c new file mode 100644 index 0000000..80b15a0 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/rtc_b.c @@ -0,0 +1,708 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// rtc_b.c - Driver for the rtc_b Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup rtc_b_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_RTC_B__ +#include "rtc_b.h" + +#include + +//***************************************************************************** +// +//! \brief Starts the RTC. +//! +//! This function clears the RTC main hold bit to allow the RTC to function. +//! +//! \param baseAddress is the base address of the RTC_B module. +//! +//! \return None +// +//***************************************************************************** +void RTC_B_startClock(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_RTCCTL01_H) &= ~(RTCHOLD_H); +} + +//***************************************************************************** +// +//! \brief Holds the RTC. +//! +//! This function sets the RTC main hold bit to disable RTC functionality. +//! +//! \param baseAddress is the base address of the RTC_B module. +//! +//! \return None +// +//***************************************************************************** +void RTC_B_holdClock(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_RTCCTL01_H) |= RTCHOLD_H; +} + +//***************************************************************************** +// +//! \brief Allows and Sets the frequency output to RTCCLK pin for calibration +//! measurement. +//! +//! This function sets a frequency to measure at the RTCCLK output pin. After +//! testing the set frequency, the calibration could be set accordingly. +//! +//! \param baseAddress is the base address of the RTC_B module. +//! \param frequencySelect is the frequency output to RTCCLK. +//! Valid values are: +//! - \b RTC_B_CALIBRATIONFREQ_OFF [Default] - turn off calibration +//! output +//! - \b RTC_B_CALIBRATIONFREQ_512HZ - output signal at 512Hz for +//! calibration +//! - \b RTC_B_CALIBRATIONFREQ_256HZ - output signal at 256Hz for +//! calibration +//! - \b RTC_B_CALIBRATIONFREQ_1HZ - output signal at 1Hz for +//! calibration +//! \n Modified bits are \b RTCCALF of \b RTCCTL3 register. +//! +//! \return None +// +//***************************************************************************** +void RTC_B_setCalibrationFrequency(uint16_t baseAddress, + uint16_t frequencySelect) +{ + HWREG16(baseAddress + OFS_RTCCTL23) &= ~(RTCCALF_3); + HWREG16(baseAddress + OFS_RTCCTL23) |= frequencySelect; +} + +//***************************************************************************** +// +//! \brief Sets the specified calibration for the RTC. +//! +//! This function sets the calibration offset to make the RTC as accurate as +//! possible. The offsetDirection can be either +4-ppm or -2-ppm, and the +//! offsetValue should be from 1-63 and is multiplied by the direction setting +//! (i.e. +4-ppm * 8 (offsetValue) = +32-ppm). Please note, when measuring the +//! frequency after setting the calibration, you will only see a change on the +//! 1Hz frequency. +//! +//! \param baseAddress is the base address of the RTC_B module. +//! \param offsetDirection is the direction that the calibration offset will +//! go. +//! Valid values are: +//! - \b RTC_B_CALIBRATION_DOWN2PPM - calibrate at steps of -2 +//! - \b RTC_B_CALIBRATION_UP4PPM - calibrate at steps of +4 +//! \n Modified bits are \b RTCCALS of \b RTCCTL2 register. +//! \param offsetValue is the value that the offset will be a factor of; a +//! valid value is any integer from 1-63. +//! \n Modified bits are \b RTCCAL of \b RTCCTL2 register. +//! +//! \return None +// +//***************************************************************************** +void RTC_B_setCalibrationData(uint16_t baseAddress, + uint8_t offsetDirection, + uint8_t offsetValue) +{ + HWREG8(baseAddress + OFS_RTCCTL23_L) = offsetValue + offsetDirection; +} + +//***************************************************************************** +// +//! \brief Initializes the settings to operate the RTC in calendar mode +//! +//! This function initializes the Calendar mode of the RTC module. +//! +//! \param baseAddress is the base address of the RTC_B module. +//! \param CalendarTime is the pointer to the structure containing the values +//! for the Calendar to be initialized to. Valid values should be of +//! type pointer to Calendar and should contain the following members +//! and corresponding values: \b Seconds between 0-59 \b Minutes between +//! 0-59 \b Hours between 0-24 \b DayOfWeek between 0-6 \b DayOfMonth +//! between 0-31 \b Year between 0-4095 NOTE: Values beyond the ones +//! specified may result in erratic behavior. +//! \param formatSelect is the format for the Calendar registers to use. +//! Valid values are: +//! - \b RTC_B_FORMAT_BINARY [Default] +//! - \b RTC_B_FORMAT_BCD +//! \n Modified bits are \b RTCBCD of \b RTCCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void RTC_B_initCalendar(uint16_t baseAddress, + Calendar *CalendarTime, + uint16_t formatSelect) +{ + HWREG8(baseAddress + OFS_RTCCTL01_H) |= RTCHOLD_H; + + HWREG16(baseAddress + OFS_RTCCTL01) &= ~(RTCBCD); + HWREG16(baseAddress + OFS_RTCCTL01) |= formatSelect; + + HWREG8(baseAddress + OFS_RTCTIM0_L) = CalendarTime->Seconds; + HWREG8(baseAddress + OFS_RTCTIM0_H) = CalendarTime->Minutes; + HWREG8(baseAddress + OFS_RTCTIM1_L) = CalendarTime->Hours; + HWREG8(baseAddress + OFS_RTCTIM1_H) = CalendarTime->DayOfWeek; + HWREG8(baseAddress + OFS_RTCDATE_L) = CalendarTime->DayOfMonth; + HWREG8(baseAddress + OFS_RTCDATE_H) = CalendarTime->Month; + HWREG16(baseAddress + OFS_RTCYEAR) = CalendarTime->Year; +} + +//***************************************************************************** +// +//! \brief Deprecated - Initializes the settings to operate the RTC in calendar +//! mode. +//! +//! This function initializes the Calendar mode of the RTC module. +//! +//! \param baseAddress is the base address of the RTC_B module. +//! \param CalendarTime is the structure containing the values for the Calendar +//! to be initialized to. Valid values should be of type Calendar and +//! should contain the following members and corresponding values: \b +//! Seconds between 0-59 \b Minutes between 0-59 \b Hours between 0-24 +//! \b DayOfWeek between 0-6 \b DayOfMonth between 0-31 \b Year between +//! 0-4095 NOTE: Values beyond the ones specified may result in erratic +//! behavior. +//! \param formatSelect is the format for the Calendar registers to use. +//! Valid values are: +//! - \b RTC_B_FORMAT_BINARY [Default] +//! - \b RTC_B_FORMAT_BCD +//! \n Modified bits are \b RTCBCD of \b RTCCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void RTC_B_calendarInit(uint16_t baseAddress, + Calendar CalendarTime, + uint16_t formatSelect) +{ + HWREG8(baseAddress + OFS_RTCCTL01_H) |= RTCHOLD_H; + + HWREG16(baseAddress + OFS_RTCCTL01) &= ~(RTCBCD); + HWREG16(baseAddress + OFS_RTCCTL01) |= formatSelect; + + HWREG8(baseAddress + OFS_RTCTIM0_L) = CalendarTime.Seconds; + HWREG8(baseAddress + OFS_RTCTIM0_H) = CalendarTime.Minutes; + HWREG8(baseAddress + OFS_RTCTIM1_L) = CalendarTime.Hours; + HWREG8(baseAddress + OFS_RTCTIM1_H) = CalendarTime.DayOfWeek; + HWREG8(baseAddress + OFS_RTCDATE_L) = CalendarTime.DayOfMonth; + HWREG8(baseAddress + OFS_RTCDATE_H) = CalendarTime.Month; + HWREG16(baseAddress + OFS_RTCYEAR) = CalendarTime.Year; +} + +//***************************************************************************** +// +//! \brief Returns the Calendar Time stored in the Calendar registers of the +//! RTC. +//! +//! This function returns the current Calendar time in the form of a Calendar +//! structure. The RTCRDY polling is used in this function to prevent reading +//! invalid time. +//! +//! \param baseAddress is the base address of the RTC_B module. +//! +//! \return A Calendar structure containing the current time. +// +//***************************************************************************** +Calendar RTC_B_getCalendarTime(uint16_t baseAddress) +{ + Calendar tempCal; + + while ( !(HWREG16(baseAddress + OFS_RTCCTL01) & RTCRDY) ) ; + + tempCal.Seconds = HWREG8(baseAddress + OFS_RTCTIM0_L); + tempCal.Minutes = HWREG8(baseAddress + OFS_RTCTIM0_H); + tempCal.Hours = HWREG8(baseAddress + OFS_RTCTIM1_L); + tempCal.DayOfWeek = HWREG8(baseAddress + OFS_RTCTIM1_H); + tempCal.DayOfMonth = HWREG8(baseAddress + OFS_RTCDATE_L); + tempCal.Month = HWREG8(baseAddress + OFS_RTCDATE_H); + tempCal.Year = HWREG16(baseAddress + OFS_RTCYEAR); + + return tempCal; +} + +//***************************************************************************** +// +//! \brief DEPRECATED - Sets and Enables the desired Calendar Alarm settings. +//! +//! This function sets a Calendar interrupt condition to assert the RTCAIFG +//! interrupt flag. The condition is a logical and of all of the parameters. +//! For example if the minutes and hours alarm is set, then the interrupt will +//! only assert when the minutes AND the hours change to the specified setting. +//! Use the RTC_B_ALARM_OFF for any alarm settings that should not be apart of +//! the alarm condition. +//! +//! \param baseAddress is the base address of the RTC_B module. +//! \param minutesAlarm is the alarm condition for the minutes. +//! Valid values are: +//! - \b RTC_B_ALARMCONDITION_OFF [Default] +//! - \b An integer between 0-59 +//! \param hoursAlarm is the alarm condition for the hours. +//! Valid values are: +//! - \b RTC_B_ALARMCONDITION_OFF [Default] +//! - \b An integer between 0-24 +//! \param dayOfWeekAlarm is the alarm condition for the day of week. +//! Valid values are: +//! - \b RTC_B_ALARMCONDITION_OFF [Default] +//! - \b An integer between 0-6 +//! \param dayOfMonthAlarm is the alarm condition for the day of the month. +//! Valid values are: +//! - \b RTC_B_ALARMCONDITION_OFF [Default] +//! - \b An integer between 0-31 +//! +//! \return None +// +//***************************************************************************** +void RTC_B_setCalendarAlarm(uint16_t baseAddress, + uint8_t minutesAlarm, + uint8_t hoursAlarm, + uint8_t dayOfWeekAlarm, + uint8_t dayOfMonthAlarm) +{ + RTC_B_configureCalendarAlarmParam param = { 0 }; + + param.minutesAlarm = minutesAlarm; + param.hoursAlarm = hoursAlarm; + param.dayOfWeekAlarm = dayOfWeekAlarm; + param.dayOfMonthAlarm = dayOfMonthAlarm; + RTC_B_configureCalendarAlarm(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Sets and Enables the desired Calendar Alarm settings. +//! +//! This function sets a Calendar interrupt condition to assert the RTCAIFG +//! interrupt flag. The condition is a logical and of all of the parameters. +//! For example if the minutes and hours alarm is set, then the interrupt will +//! only assert when the minutes AND the hours change to the specified setting. +//! Use the RTC_B_ALARM_OFF for any alarm settings that should not be apart of +//! the alarm condition. +//! +//! \param baseAddress is the base address of the RTC_B module. +//! \param param is the pointer to struct for calendar alarm configuration. +//! +//! \return None +// +//***************************************************************************** +void RTC_B_configureCalendarAlarm(uint16_t baseAddress, + RTC_B_configureCalendarAlarmParam *param) +{ + //Each of these is XORed with 0x80 to turn on if an integer is passed, + //or turn OFF if RTC_B_ALARM_OFF (0x80) is passed. + HWREG8(baseAddress + OFS_RTCAMINHR_L) = (param->minutesAlarm ^ 0x80); + HWREG8(baseAddress + OFS_RTCAMINHR_H) = (param->hoursAlarm ^ 0x80); + HWREG8(baseAddress + OFS_RTCADOWDAY_L) = (param->dayOfWeekAlarm ^ 0x80); + HWREG8(baseAddress + OFS_RTCADOWDAY_H) = (param->dayOfMonthAlarm ^ 0x80); +} +//***************************************************************************** +// +//! \brief Sets a single specified Calendar interrupt condition +//! +//! This function sets a specified event to assert the RTCTEVIFG interrupt. +//! This interrupt is independent from the Calendar alarm interrupt. +//! +//! \param baseAddress is the base address of the RTC_B module. +//! \param eventSelect is the condition selected. +//! Valid values are: +//! - \b RTC_B_CALENDAREVENT_MINUTECHANGE - assert interrupt on every +//! minute +//! - \b RTC_B_CALENDAREVENT_HOURCHANGE - assert interrupt on every hour +//! - \b RTC_B_CALENDAREVENT_NOON - assert interrupt when hour is 12 +//! - \b RTC_B_CALENDAREVENT_MIDNIGHT - assert interrupt when hour is 0 +//! \n Modified bits are \b RTCTEV of \b RTCCTL register. +//! +//! \return None +// +//***************************************************************************** +void RTC_B_setCalendarEvent(uint16_t baseAddress, + uint16_t eventSelect) +{ + HWREG16(baseAddress + OFS_RTCCTL01) &= ~(RTCTEV_3); //Reset bits + HWREG16(baseAddress + OFS_RTCCTL01) |= eventSelect; +} + +//***************************************************************************** +// +//! \brief Sets up an interrupt condition for the selected Prescaler. +//! +//! This function sets the condition for an interrupt to assert based on the +//! individual prescalers. +//! +//! \param baseAddress is the base address of the RTC_B module. +//! \param prescaleSelect is the prescaler to define an interrupt for. +//! Valid values are: +//! - \b RTC_B_PRESCALE_0 +//! - \b RTC_B_PRESCALE_1 +//! \param prescaleEventDivider is a divider to specify when an interrupt can +//! occur based on the clock source of the selected prescaler. (Does not +//! affect timer of the selected prescaler). +//! Valid values are: +//! - \b RTC_B_PSEVENTDIVIDER_2 [Default] +//! - \b RTC_B_PSEVENTDIVIDER_4 +//! - \b RTC_B_PSEVENTDIVIDER_8 +//! - \b RTC_B_PSEVENTDIVIDER_16 +//! - \b RTC_B_PSEVENTDIVIDER_32 +//! - \b RTC_B_PSEVENTDIVIDER_64 +//! - \b RTC_B_PSEVENTDIVIDER_128 +//! - \b RTC_B_PSEVENTDIVIDER_256 +//! \n Modified bits are \b RTxIP of \b RTCPSxCTL register. +//! +//! \return None +// +//***************************************************************************** +void RTC_B_definePrescaleEvent(uint16_t baseAddress, + uint8_t prescaleSelect, + uint8_t prescaleEventDivider) +{ + HWREG8(baseAddress + OFS_RTCPS0CTL_L + prescaleSelect) &= ~(RT0IP_7); + HWREG8(baseAddress + OFS_RTCPS0CTL_L + + prescaleSelect) |= prescaleEventDivider; +} + +//***************************************************************************** +// +//! \brief Returns the selected prescaler value. +//! +//! This function returns the value of the selected prescale counter register. +//! Note that the counter value should be held by calling RTC_B_holdClock() +//! before calling this API. +//! +//! \param baseAddress is the base address of the RTC_B module. +//! \param prescaleSelect is the prescaler to obtain the value of. +//! Valid values are: +//! - \b RTC_B_PRESCALE_0 +//! - \b RTC_B_PRESCALE_1 +//! +//! \return The value of the specified prescaler count register +// +//***************************************************************************** +uint8_t RTC_B_getPrescaleValue(uint16_t baseAddress, + uint8_t prescaleSelect) +{ + if (RTC_B_PRESCALE_0 == prescaleSelect) + return HWREG8(baseAddress + OFS_RTCPS_L); + else if (RTC_B_PRESCALE_1 == prescaleSelect) + return HWREG8(baseAddress + OFS_RTCPS_H); + else + return 0; +} + +//***************************************************************************** +// +//! \brief Sets the selected prescaler value. +//! +//! This function sets the prescale counter value. Before setting the prescale +//! counter, it should be held by calling RTC_B_holdClock(). +//! +//! \param baseAddress is the base address of the RTC_B module. +//! \param prescaleSelect is the prescaler to set the value for. +//! Valid values are: +//! - \b RTC_B_PRESCALE_0 +//! - \b RTC_B_PRESCALE_1 +//! \param prescaleCounterValue is the specified value to set the prescaler to. +//! Valid values are any integer between 0-255 +//! \n Modified bits are \b RTxPS of \b RTxPS register. +//! +//! \return None +// +//***************************************************************************** +void RTC_B_setPrescaleValue(uint16_t baseAddress, + uint8_t prescaleSelect, + uint8_t prescaleCounterValue) +{ + if (RTC_B_PRESCALE_0 == prescaleSelect) + HWREG8(baseAddress + OFS_RTCPS_L) = prescaleCounterValue; + else if (RTC_B_PRESCALE_1 == prescaleSelect) + HWREG8(baseAddress + OFS_RTCPS_H) = prescaleCounterValue; +} + +//***************************************************************************** +// +//! \brief Enables selected RTC interrupt sources. +//! +//! This function enables the selected RTC interrupt source. Only the sources +//! that are enabled can be reflected to the processor interrupt; disabled +//! sources have no effect on the processor. Does not clear interrupt flags. +//! +//! \param baseAddress is the base address of the RTC_B module. +//! \param interruptMask is a bit mask of the interrupts to enable. +//! Mask value is the logical OR of any of the following: +//! - \b RTC_B_TIME_EVENT_INTERRUPT - asserts when counter overflows in +//! counter mode or when Calendar event condition defined by +//! defineCalendarEvent() is met. +//! - \b RTC_B_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in +//! Calendar mode is met. +//! - \b RTC_B_CLOCK_READ_READY_INTERRUPT - asserts when Calendar +//! registers are settled. +//! - \b RTC_B_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0 +//! event condition is met. +//! - \b RTC_B_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1 +//! event condition is met. +//! - \b RTC_B_OSCILLATOR_FAULT_INTERRUPT - asserts if there is a +//! problem with the 32kHz oscillator, while the RTC is running. +//! +//! \return None +// +//***************************************************************************** +void RTC_B_enableInterrupt(uint16_t baseAddress, + uint8_t interruptMask) +{ + if ( interruptMask & (RTCOFIE + RTCTEVIE + RTCAIE + RTCRDYIE) ) + HWREG8(baseAddress + OFS_RTCCTL01_L) |= + (interruptMask & (RTCOFIE + RTCTEVIE + RTCAIE + RTCRDYIE)); + + if (interruptMask & RTC_B_PRESCALE_TIMER0_INTERRUPT) + HWREG8(baseAddress + OFS_RTCPS0CTL) |= RT0PSIE; + + if (interruptMask & RTC_B_PRESCALE_TIMER1_INTERRUPT) + HWREG8(baseAddress + OFS_RTCPS1CTL) |= RT1PSIE; +} + +//***************************************************************************** +// +//! \brief Disables selected RTC interrupt sources. +//! +//! This function disables the selected RTC interrupt source. Only the sources +//! that are enabled can be reflected to the processor interrupt; disabled +//! sources have no effect on the processor. +//! +//! \param baseAddress is the base address of the RTC_B module. +//! \param interruptMask is a bit mask of the interrupts to disable. +//! Mask value is the logical OR of any of the following: +//! - \b RTC_B_TIME_EVENT_INTERRUPT - asserts when counter overflows in +//! counter mode or when Calendar event condition defined by +//! defineCalendarEvent() is met. +//! - \b RTC_B_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in +//! Calendar mode is met. +//! - \b RTC_B_CLOCK_READ_READY_INTERRUPT - asserts when Calendar +//! registers are settled. +//! - \b RTC_B_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0 +//! event condition is met. +//! - \b RTC_B_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1 +//! event condition is met. +//! - \b RTC_B_OSCILLATOR_FAULT_INTERRUPT - asserts if there is a +//! problem with the 32kHz oscillator, while the RTC is running. +//! +//! \return None +// +//***************************************************************************** +void RTC_B_disableInterrupt(uint16_t baseAddress, + uint8_t interruptMask) +{ + if ( interruptMask & (RTCOFIE + RTCTEVIE + RTCAIE + RTCRDYIE) ) + HWREG8(baseAddress + OFS_RTCCTL01_L) &= + ~(interruptMask & (RTCOFIE + RTCTEVIE + RTCAIE + RTCRDYIE)); + + if (interruptMask & RTC_B_PRESCALE_TIMER0_INTERRUPT) + HWREG8(baseAddress + OFS_RTCPS0CTL) &= ~(RT0PSIE); + + if (interruptMask & RTC_B_PRESCALE_TIMER1_INTERRUPT) + HWREG8(baseAddress + OFS_RTCPS1CTL) &= ~(RT1PSIE); +} + +//***************************************************************************** +// +//! \brief Returns the status of the selected interrupts flags. +//! +//! This function returns the status of the interrupt flag for the selected +//! channel. +//! +//! \param baseAddress is the base address of the RTC_B module. +//! \param interruptFlagMask is a bit mask of the interrupt flags to return the +//! status of. +//! Mask value is the logical OR of any of the following: +//! - \b RTC_B_TIME_EVENT_INTERRUPT - asserts when counter overflows in +//! counter mode or when Calendar event condition defined by +//! defineCalendarEvent() is met. +//! - \b RTC_B_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in +//! Calendar mode is met. +//! - \b RTC_B_CLOCK_READ_READY_INTERRUPT - asserts when Calendar +//! registers are settled. +//! - \b RTC_B_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0 +//! event condition is met. +//! - \b RTC_B_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1 +//! event condition is met. +//! - \b RTC_B_OSCILLATOR_FAULT_INTERRUPT - asserts if there is a +//! problem with the 32kHz oscillator, while the RTC is running. +//! +//! \return Logical OR of any of the following: +//! - \b RTC_B_TIME_EVENT_INTERRUPT asserts when counter overflows in +//! counter mode or when Calendar event condition defined by +//! defineCalendarEvent() is met. +//! - \b RTC_B_CLOCK_ALARM_INTERRUPT asserts when alarm condition in +//! Calendar mode is met. +//! - \b RTC_B_CLOCK_READ_READY_INTERRUPT asserts when Calendar +//! registers are settled. +//! - \b RTC_B_PRESCALE_TIMER0_INTERRUPT asserts when Prescaler 0 event +//! condition is met. +//! - \b RTC_B_PRESCALE_TIMER1_INTERRUPT asserts when Prescaler 1 event +//! condition is met. +//! - \b RTC_B_OSCILLATOR_FAULT_INTERRUPT asserts if there is a problem +//! with the 32kHz oscillator, while the RTC is running. +//! \n indicating the status of the masked interrupts +// +//***************************************************************************** +uint8_t RTC_B_getInterruptStatus(uint16_t baseAddress, + uint8_t interruptFlagMask) +{ + uint8_t tempInterruptFlagMask = 0x0000; + + tempInterruptFlagMask |= (HWREG8(baseAddress + OFS_RTCCTL01_L) + & ((interruptFlagMask >> 4) + & (RTCOFIFG + + RTCTEVIFG + + RTCAIFG + + RTCRDYIFG))); + + tempInterruptFlagMask = tempInterruptFlagMask << 4; + + if (interruptFlagMask & RTC_B_PRESCALE_TIMER0_INTERRUPT) + if ( HWREG8(baseAddress + OFS_RTCPS0CTL) & RT0PSIFG) + tempInterruptFlagMask |= RTC_B_PRESCALE_TIMER0_INTERRUPT; + + if (interruptFlagMask & RTC_B_PRESCALE_TIMER1_INTERRUPT) + if ( HWREG8(baseAddress + OFS_RTCPS1CTL) & RT1PSIFG) + tempInterruptFlagMask |= RTC_B_PRESCALE_TIMER1_INTERRUPT; + + return tempInterruptFlagMask; +} + +//***************************************************************************** +// +//! \brief Clears selected RTC interrupt flags. +//! +//! This function clears the RTC interrupt flag is cleared, so that it no +//! longer asserts. +//! +//! \param baseAddress is the base address of the RTC_B module. +//! \param interruptFlagMask is a bit mask of the interrupt flags to be +//! cleared. +//! Mask value is the logical OR of any of the following: +//! - \b RTC_B_TIME_EVENT_INTERRUPT - asserts when counter overflows in +//! counter mode or when Calendar event condition defined by +//! defineCalendarEvent() is met. +//! - \b RTC_B_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in +//! Calendar mode is met. +//! - \b RTC_B_CLOCK_READ_READY_INTERRUPT - asserts when Calendar +//! registers are settled. +//! - \b RTC_B_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0 +//! event condition is met. +//! - \b RTC_B_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1 +//! event condition is met. +//! - \b RTC_B_OSCILLATOR_FAULT_INTERRUPT - asserts if there is a +//! problem with the 32kHz oscillator, while the RTC is running. +//! +//! \return None +// +//***************************************************************************** +void RTC_B_clearInterrupt(uint16_t baseAddress, + uint8_t interruptFlagMask) +{ + if ( interruptFlagMask & (RTC_B_TIME_EVENT_INTERRUPT + + RTC_B_CLOCK_ALARM_INTERRUPT + + RTC_B_CLOCK_READ_READY_INTERRUPT + + RTC_B_OSCILLATOR_FAULT_INTERRUPT) ) { + + HWREG8(baseAddress + OFS_RTCCTL01_L) &= + ~((interruptFlagMask >> 4) & (RTCOFIFG + + RTCTEVIFG + + RTCAIFG + + RTCRDYIFG)); + } + + if (interruptFlagMask & RTC_B_PRESCALE_TIMER0_INTERRUPT) + HWREG8(baseAddress + OFS_RTCPS0CTL) &= ~(RT0PSIFG); + + if (interruptFlagMask & RTC_B_PRESCALE_TIMER1_INTERRUPT) + HWREG8(baseAddress + OFS_RTCPS1CTL) &= ~(RT1PSIFG); +} + +//***************************************************************************** +// +//! \brief Convert the given BCD value to binary format +//! +//! This function converts BCD values to binary format. This API uses the +//! hardware registers to perform the conversion rather than a software method. +//! +//! \param baseAddress is the base address of the RTC_B module. +//! \param valueToConvert is the raw value in BCD format to convert to Binary. +//! \n Modified bits are \b BCD2BIN of \b BCD2BIN register. +//! +//! \return The binary version of the input parameter +// +//***************************************************************************** +uint16_t RTC_B_convertBCDToBinary(uint16_t baseAddress, + uint16_t valueToConvert) +{ + HWREG16(baseAddress + OFS_BCD2BIN) = valueToConvert; + return HWREG16(baseAddress + OFS_BCD2BIN); +} + +//***************************************************************************** +// +//! \brief Convert the given binary value to BCD format +//! +//! This function converts binary values to BCD format. This API uses the +//! hardware registers to perform the conversion rather than a software method. +//! +//! \param baseAddress is the base address of the RTC_B module. +//! \param valueToConvert is the raw value in Binary format to convert to BCD. +//! \n Modified bits are \b BIN2BCD of \b BIN2BCD register. +//! +//! \return The BCD version of the valueToConvert parameter +// +//***************************************************************************** +uint16_t RTC_B_convertBinaryToBCD(uint16_t baseAddress, + uint16_t valueToConvert) +{ + HWREG16(baseAddress + OFS_BIN2BCD) = valueToConvert; + return HWREG16(baseAddress + OFS_BIN2BCD); +} + + +#endif +//***************************************************************************** +// +//! Close the doxygen group for rtc_b_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/rtc_b.h b/source/driverlib/MSP430F5xx_6xx/rtc_b.h new file mode 100644 index 0000000..7279384 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/rtc_b.h @@ -0,0 +1,265 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// rtc_b.h - Driver for the RTC_B Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_RTC_B_H__ +#define __MSP430WARE_RTC_B_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_RTC_B__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following is a struct that can be passed to RTC_B_CalendarInit() in the +// CalendarTime parameter, as well as returned by RTC_B_getCalendarTime() +// +//***************************************************************************** +typedef struct { + uint8_t Seconds; + uint8_t Minutes; + uint8_t Hours; + uint8_t DayOfWeek; + uint8_t DayOfMonth; + uint8_t Month; + uint16_t Year; +} Calendar; + +//****************************************************************************** +// +// The following is a struct that is passed to RTC_B_configureCalendarAlarm() +// +//****************************************************************************** +typedef struct RTC_B_configureCalendarAlarmParam { + uint8_t minutesAlarm; + uint8_t hoursAlarm; + uint8_t dayOfWeekAlarm; + uint8_t dayOfMonthAlarm; +} RTC_B_configureCalendarAlarmParam; + +//***************************************************************************** +// +// The following are values that can be passed to the frequencySelect parameter +// for functions: RTC_B_setCalibrationFrequency(). +// +//***************************************************************************** +#define RTC_B_CALIBRATIONFREQ_OFF (RTCCALF_0) +#define RTC_B_CALIBRATIONFREQ_512HZ (RTCCALF_1) +#define RTC_B_CALIBRATIONFREQ_256HZ (RTCCALF_2) +#define RTC_B_CALIBRATIONFREQ_1HZ (RTCCALF_3) + +//***************************************************************************** +// +// The following are values that can be passed to the offsetDirection parameter +// for functions: RTC_B_setCalibrationData(). +// +//***************************************************************************** +#define RTC_B_CALIBRATION_DOWN2PPM (!(RTCCALS)) +#define RTC_B_CALIBRATION_UP4PPM (RTCCALS) + +//***************************************************************************** +// +// The following are values that can be passed to the formatSelect parameter +// for functions: RTC_B_initCalendar(), and RTC_B_calendarInit(). +// +//***************************************************************************** +#define RTC_B_FORMAT_BINARY (!(RTCBCD)) +#define RTC_B_FORMAT_BCD (RTCBCD) + +//***************************************************************************** +// +// The following are values that can be passed to the minutesAlarm parameter +// for functions: RTC_B_setCalendarAlarm(); the dayOfMonthAlarm parameter for +// functions: RTC_B_setCalendarAlarm(); the hoursAlarm parameter for functions: +// RTC_B_setCalendarAlarm(); the dayOfWeekAlarm parameter for functions: +// RTC_B_setCalendarAlarm(). +// +//***************************************************************************** +#define RTC_B_ALARMCONDITION_OFF (0x80) + +//***************************************************************************** +// +// The following are values that can be passed to the eventSelect parameter for +// functions: RTC_B_setCalendarEvent(). +// +//***************************************************************************** +#define RTC_B_CALENDAREVENT_MINUTECHANGE (RTCTEV_0) +#define RTC_B_CALENDAREVENT_HOURCHANGE (RTCTEV_1) +#define RTC_B_CALENDAREVENT_NOON (RTCTEV_2) +#define RTC_B_CALENDAREVENT_MIDNIGHT (RTCTEV_3) + +//***************************************************************************** +// +// The following are values that can be passed to the prescaleEventDivider +// parameter for functions: RTC_B_definePrescaleEvent(). +// +//***************************************************************************** +#define RTC_B_PSEVENTDIVIDER_2 (RT0IP_0) +#define RTC_B_PSEVENTDIVIDER_4 (RT0IP_1) +#define RTC_B_PSEVENTDIVIDER_8 (RT0IP_2) +#define RTC_B_PSEVENTDIVIDER_16 (RT0IP_3) +#define RTC_B_PSEVENTDIVIDER_32 (RT0IP_4) +#define RTC_B_PSEVENTDIVIDER_64 (RT0IP_5) +#define RTC_B_PSEVENTDIVIDER_128 (RT0IP_6) +#define RTC_B_PSEVENTDIVIDER_256 (RT0IP_7) + +//***************************************************************************** +// +// The following are values that can be passed to the prescaleSelect parameter +// for functions: RTC_B_definePrescaleEvent(), RTC_B_getPrescaleValue(), and +// RTC_B_setPrescaleValue(). +// +//***************************************************************************** +#define RTC_B_PRESCALE_0 (0x0) +#define RTC_B_PRESCALE_1 (0x2) + +//***************************************************************************** +// +// The following are values that can be passed to the interruptMask parameter +// for functions: RTC_B_enableInterrupt(), and RTC_B_disableInterrupt(); the +// interruptFlagMask parameter for functions: RTC_B_getInterruptStatus(), and +// RTC_B_clearInterrupt() as well as returned by the RTC_B_getInterruptStatus() +// function. +// +//***************************************************************************** +#define RTC_B_TIME_EVENT_INTERRUPT RTCTEVIE +#define RTC_B_CLOCK_ALARM_INTERRUPT RTCAIE +#define RTC_B_CLOCK_READ_READY_INTERRUPT RTCRDYIE +#define RTC_B_PRESCALE_TIMER0_INTERRUPT 0x02 +#define RTC_B_PRESCALE_TIMER1_INTERRUPT 0x01 +#define RTC_B_OSCILLATOR_FAULT_INTERRUPT RTCOFIE + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void RTC_B_startClock(uint16_t baseAddress); + +extern void RTC_B_holdClock(uint16_t baseAddress); + +extern void RTC_B_setCalibrationFrequency(uint16_t baseAddress, + uint16_t frequencySelect); + +extern void RTC_B_setCalibrationData(uint16_t baseAddress, + uint8_t offsetDirection, + uint8_t offsetValue); + +extern void RTC_B_initCalendar(uint16_t baseAddress, + Calendar *CalendarTime, + uint16_t formatSelect); + +extern Calendar RTC_B_getCalendarTime(uint16_t baseAddress); + +extern void RTC_B_configureCalendarAlarm(uint16_t baseAddress, + RTC_B_configureCalendarAlarmParam *param); + +extern void RTC_B_setCalendarEvent(uint16_t baseAddress, + uint16_t eventSelect); + +extern void RTC_B_definePrescaleEvent(uint16_t baseAddress, + uint8_t prescaleSelect, + uint8_t prescaleEventDivider); + +extern uint8_t RTC_B_getPrescaleValue(uint16_t baseAddress, + uint8_t prescaleSelect); + +extern void RTC_B_setPrescaleValue(uint16_t baseAddress, + uint8_t prescaleSelect, + uint8_t prescaleCounterValue); + +extern void RTC_B_enableInterrupt(uint16_t baseAddress, + uint8_t interruptMask); + +extern void RTC_B_disableInterrupt(uint16_t baseAddress, + uint8_t interruptMask); + +extern uint8_t RTC_B_getInterruptStatus(uint16_t baseAddress, + uint8_t interruptFlagMask); + +extern void RTC_B_clearInterrupt(uint16_t baseAddress, + uint8_t interruptFlagMask); + +extern uint16_t RTC_B_convertBCDToBinary(uint16_t baseAddress, + uint16_t valueToConvert); + +extern uint16_t RTC_B_convertBinaryToBCD(uint16_t baseAddress, + uint16_t valueToConvert); + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +#define RTC_B_setPrescaleCounterValue RTC_B_setPrescaleValue + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +extern void RTC_B_calendarInit(uint16_t baseAddress, + Calendar CalendarTime, + uint16_t formatSelect); + +extern void RTC_B_setCalendarAlarm(uint16_t baseAddress, + uint8_t minutesAlarm, + uint8_t hoursAlarm, + uint8_t dayOfWeekAlarm, + uint8_t dayOfMonthAlarm); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_RTC_B_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/rtc_c.c b/source/driverlib/MSP430F5xx_6xx/rtc_c.c new file mode 100644 index 0000000..251ad17 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/rtc_c.c @@ -0,0 +1,957 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// rtc_c.c - Driver for the rtc_c Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup rtc_c_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#if defined(__MSP430_HAS_RTC_C__) || defined(__MSP430_HAS_RTC_CE__) +#include "rtc_c.h" + +#include + +//***************************************************************************** +// +//! \brief Starts the RTC. +//! +//! This function clears the RTC main hold bit to allow the RTC to function. +//! +//! \param baseAddress is the base address of the RTC_C module. +//! +//! \return None +// +//***************************************************************************** +void RTC_C_startClock(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_RTCCTL0_H) = RTCKEY_H; + HWREG8(baseAddress + OFS_RTCCTL13_L) &= ~(RTCHOLD); + HWREG8(baseAddress + OFS_RTCCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Holds the RTC. +//! +//! This function sets the RTC main hold bit to disable RTC functionality. +//! +//! \param baseAddress is the base address of the RTC_C module. +//! +//! \return None +// +//***************************************************************************** +void RTC_C_holdClock(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_RTCCTL0_H) = RTCKEY_H; + HWREG8(baseAddress + OFS_RTCCTL13_L) |= RTCHOLD; + HWREG8(baseAddress + OFS_RTCCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Allows and Sets the frequency output to RTCCLK pin for calibration +//! measurement. +//! +//! This function sets a frequency to measure at the RTCCLK output pin. After +//! testing the set frequency, the calibration could be set accordingly. +//! +//! \param baseAddress is the base address of the RTC_C module. +//! \param frequencySelect is the frequency output to RTCCLK. +//! Valid values are: +//! - \b RTC_C_CALIBRATIONFREQ_OFF [Default] - turn off calibration +//! output +//! - \b RTC_C_CALIBRATIONFREQ_512HZ - output signal at 512Hz for +//! calibration +//! - \b RTC_C_CALIBRATIONFREQ_256HZ - output signal at 256Hz for +//! calibration +//! - \b RTC_C_CALIBRATIONFREQ_1HZ - output signal at 1Hz for +//! calibration +//! \n Modified bits are \b RTCCALF of \b RTCCTL3 register. +//! +//! \return None +// +//***************************************************************************** +void RTC_C_setCalibrationFrequency(uint16_t baseAddress, + uint16_t frequencySelect) +{ + HWREG8(baseAddress + OFS_RTCCTL0_H) = RTCKEY_H; + HWREG16(baseAddress + OFS_RTCCTL13) &= ~(RTCCALF_3); + HWREG16(baseAddress + OFS_RTCCTL13) |= frequencySelect; + HWREG8(baseAddress + OFS_RTCCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Sets the specified calibration for the RTC. +//! +//! This function sets the calibration offset to make the RTC as accurate as +//! possible. The offsetDirection can be either +4-ppm or -2-ppm, and the +//! offsetValue should be from 1-63 and is multiplied by the direction setting +//! (i.e. +4-ppm * 8 (offsetValue) = +32-ppm). +//! +//! \param baseAddress is the base address of the RTC_C module. +//! \param offsetDirection is the direction that the calibration offset will +//! go. +//! Valid values are: +//! - \b RTC_C_CALIBRATION_DOWN1PPM - calibrate at steps of -1 +//! - \b RTC_C_CALIBRATION_UP1PPM - calibrate at steps of +1 +//! \n Modified bits are \b RTC0CALS of \b RTC0CAL register. +//! \param offsetValue is the value that the offset will be a factor of; a +//! valid value is any integer from 1-240. +//! \n Modified bits are \b RTC0CALx of \b RTC0CAL register. +//! +//! \return None +// +//***************************************************************************** +void RTC_C_setCalibrationData(uint16_t baseAddress, + uint8_t offsetDirection, + uint8_t offsetValue) +{ + HWREG8(baseAddress + OFS_RTCCTL0_H) = RTCKEY_H; + HWREG16(baseAddress + OFS_RTCOCAL) = offsetValue + offsetDirection; + HWREG8(baseAddress + OFS_RTCCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Initializes the settings to operate the RTC in Counter mode. +//! +//! This function initializes the Counter mode of the RTC_C. Setting the clock +//! source and counter size will allow an interrupt from the RTCTEVIFG once an +//! overflow to the counter register occurs. +//! +//! \param baseAddress is the base address of the RTC_C module. +//! \param clockSelect is the selected clock for the counter mode to use. +//! Valid values are: +//! - \b RTC_C_CLOCKSELECT_32KHZ_OSC +//! - \b RTC_C_CLOCKSELECT_RT1PS +//! \n Modified bits are \b RTCSSEL of \b RTCCTL1 register. +//! \param counterSizeSelect is the size of the counter. +//! Valid values are: +//! - \b RTC_C_COUNTERSIZE_8BIT [Default] +//! - \b RTC_C_COUNTERSIZE_16BIT +//! - \b RTC_C_COUNTERSIZE_24BIT +//! - \b RTC_C_COUNTERSIZE_32BIT +//! \n Modified bits are \b RTCTEV of \b RTCCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void RTC_C_initCounter(uint16_t baseAddress, + uint16_t clockSelect, + uint16_t counterSizeSelect) +{ + HWREG8(baseAddress + OFS_RTCCTL13) |= RTCHOLD; + HWREG8(baseAddress + OFS_RTCCTL13) &= ~(RTCMODE); + + HWREG16(baseAddress + OFS_RTCCTL13) &= ~(RTCSSEL_3 | RTCTEV_3 ); + HWREG16(baseAddress + OFS_RTCCTL13) |= clockSelect + counterSizeSelect; +} + +//***************************************************************************** +// +//! \brief Sets the specified temperature compensation for the RTC. +//! +//! This function sets the calibration offset to make the RTC as accurate as +//! possible. The offsetDirection can be either +1-ppm or -1-ppm, and the +//! offsetValue should be from 1-240 and is multiplied by the direction setting +//! (i.e. +1-ppm * 8 (offsetValue) = +8-ppm). +//! +//! \param baseAddress is the base address of the RTC_C module. +//! \param offsetDirection is the direction that the calibration offset wil go +//! Valid values are: +//! - \b RTC_C_COMPENSATION_DOWN1PPM +//! - \b RTC_C_COMPENSATION_UP1PPM +//! \n Modified bits are \b RTCTCMPS of \b RTCTCMP register. +//! \param offsetValue is the value that the offset will be a factor of; a +//! valid value is any integer from 1-240. +//! \n Modified bits are \b RTCTCMPx of \b RTCTCMP register. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of setting the temperature +//! compensation +// +//***************************************************************************** +bool RTC_C_setTemperatureCompensation(uint16_t baseAddress, + uint16_t offsetDirection, + uint8_t offsetValue) +{ + + while (!(HWREG8(baseAddress + OFS_RTCTCMP_H) & RTCTCRDY_H)) ; + + HWREG16(baseAddress + OFS_RTCTCMP) = offsetValue + offsetDirection; + + if (HWREG8(baseAddress + OFS_RTCTCMP_H) & RTCTCOK_H) + return STATUS_SUCCESS; + else + return STATUS_FAIL; +} + +//***************************************************************************** +// +//! \brief Deprecated - Initializes the settings to operate the RTC in calendar +//! mode +//! +//! This function initializes the Calendar mode of the RTC module. +//! +//! \param baseAddress is the base address of the RTC_C module. +//! \param CalendarTime is the structure containing the values for the Calendar +//! to be initialized to. Valid values should be of type Calendar and +//! should contain the following members and corresponding values: \b +//! Seconds between 0-59 \b Minutes between 0-59 \b Hours between 0-24 +//! \b DayOfWeek between 0-6 \b DayOfMonth between 0-31 \b Year between +//! 0-4095 NOTE: Values beyond the ones specified may result in erratic +//! behavior. +//! \param formatSelect is the format for the Calendar registers to use. +//! Valid values are: +//! - \b RTC_C_FORMAT_BINARY [Default] +//! - \b RTC_C_FORMAT_BCD +//! \n Modified bits are \b RTCBCD of \b RTCCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void RTC_C_calendarInit(uint16_t baseAddress, + Calendar CalendarTime, + uint16_t formatSelect) +{ + + HWREG8(baseAddress + OFS_RTCCTL0_H) = RTCKEY_H; + + HWREG8(baseAddress + OFS_RTCCTL13_L) |= RTCHOLD; + + HWREG16(baseAddress + OFS_RTCCTL13_L) &= ~(RTCBCD); + HWREG16(baseAddress + OFS_RTCCTL13_L) |= formatSelect; + + HWREG8(baseAddress + OFS_RTCTIM0_L) = CalendarTime.Seconds; + HWREG8(baseAddress + OFS_RTCTIM0_H) = CalendarTime.Minutes; + HWREG8(baseAddress + OFS_RTCTIM1_L) = CalendarTime.Hours; + HWREG8(baseAddress + OFS_RTCTIM1_H) = CalendarTime.DayOfWeek; + HWREG8(baseAddress + OFS_RTCDATE_L) = CalendarTime.DayOfMonth; + HWREG8(baseAddress + OFS_RTCDATE_H) = CalendarTime.Month; + HWREG16(baseAddress + OFS_RTCYEAR) = CalendarTime.Year; + + HWREG8(baseAddress + OFS_RTCCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Initializes the settings to operate the RTC in calendar mode +//! +//! This function initializes the Calendar mode of the RTC module. +//! +//! \param baseAddress is the base address of the RTC_C module. +//! \param CalendarTime is the pointer to the structure containing the values +//! for the Calendar to be initialized to. Valid values should be of +//! type pointer to Calendar and should contain the following members +//! and corresponding values: \b Seconds between 0-59 \b Minutes between +//! 0-59 \b Hours between 0-24 \b DayOfWeek between 0-6 \b DayOfMonth +//! between 0-31 \b Year between 0-4095 NOTE: Values beyond the ones +//! specified may result in erratic behavior. +//! \param formatSelect is the format for the Calendar registers to use. +//! Valid values are: +//! - \b RTC_C_FORMAT_BINARY [Default] +//! - \b RTC_C_FORMAT_BCD +//! \n Modified bits are \b RTCBCD of \b RTCCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void RTC_C_initCalendar(uint16_t baseAddress, + Calendar *CalendarTime, + uint16_t formatSelect) +{ + + HWREG8(baseAddress + OFS_RTCCTL0_H) = RTCKEY_H; + + HWREG8(baseAddress + OFS_RTCCTL13_L) |= RTCHOLD; + + HWREG16(baseAddress + OFS_RTCCTL13_L) &= ~(RTCBCD); + HWREG16(baseAddress + OFS_RTCCTL13_L) |= formatSelect; + + HWREG8(baseAddress + OFS_RTCTIM0_L) = CalendarTime->Seconds; + HWREG8(baseAddress + OFS_RTCTIM0_H) = CalendarTime->Minutes; + HWREG8(baseAddress + OFS_RTCTIM1_L) = CalendarTime->Hours; + HWREG8(baseAddress + OFS_RTCTIM1_H) = CalendarTime->DayOfWeek; + HWREG8(baseAddress + OFS_RTCDATE_L) = CalendarTime->DayOfMonth; + HWREG8(baseAddress + OFS_RTCDATE_H) = CalendarTime->Month; + HWREG16(baseAddress + OFS_RTCYEAR) = CalendarTime->Year; + + HWREG8(baseAddress + OFS_RTCCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Returns the Calendar Time stored in the Calendar registers of the +//! RTC. +//! +//! This function returns the current Calendar time in the form of a Calendar +//! structure. The RTCRDY polling is used in this function to prevent reading +//! invalid time. +//! +//! \param baseAddress is the base address of the RTC_C module. +//! +//! \return A Calendar structure containing the current time. +// +//***************************************************************************** +Calendar RTC_C_getCalendarTime(uint16_t baseAddress) +{ + Calendar tempCal; + + while ( !(HWREG8(baseAddress + OFS_RTCCTL13_L) & RTCRDY) ) ; + + tempCal.Seconds = HWREG8(baseAddress + OFS_RTCTIM0_L); + tempCal.Minutes = HWREG8(baseAddress + OFS_RTCTIM0_H); + tempCal.Hours = HWREG8(baseAddress + OFS_RTCTIM1_L); + tempCal.DayOfWeek = HWREG8(baseAddress + OFS_RTCTIM1_H); + tempCal.DayOfMonth = HWREG8(baseAddress + OFS_RTCDATE_L); + tempCal.Month = HWREG8(baseAddress + OFS_RTCDATE_H); + tempCal.Year = HWREG16(baseAddress + OFS_RTCYEAR); + + return tempCal; +} + +//***************************************************************************** +// +//! \brief DEPRECATED - Sets and Enables the desired Calendar Alarm settings. +//! +//! This function sets a Calendar interrupt condition to assert the RTCAIFG +//! interrupt flag. The condition is a logical and of all of the parameters. +//! For example if the minutes and hours alarm is set, then the interrupt will +//! only assert when the minutes AND the hours change to the specified setting. +//! Use the RTC_C_ALARM_OFF for any alarm settings that should not be apart of +//! the alarm condition. +//! +//! \param baseAddress is the base address of the RTC_C module. +//! \param minutesAlarm is the alarm condition for the minutes. +//! Valid values are: +//! - \b RTC_C_ALARMCONDITION_OFF [Default] +//! - \b An integer between 0-59 +//! \param hoursAlarm is the alarm condition for the hours. +//! Valid values are: +//! - \b RTC_C_ALARMCONDITION_OFF [Default] +//! - \b An integer between 0-24 +//! \param dayOfWeekAlarm is the alarm condition for the day of week. +//! Valid values are: +//! - \b RTC_C_ALARMCONDITION_OFF [Default] +//! - \b An integer between 0-6 +//! \param dayOfMonthAlarm is the alarm condition for the day of the month. +//! Valid values are: +//! - \b RTC_C_ALARMCONDITION_OFF [Default] +//! - \b An integer between 0-31 +//! +//! \return None +// +//***************************************************************************** +void RTC_C_setCalendarAlarm(uint16_t baseAddress, + uint8_t minutesAlarm, + uint8_t hoursAlarm, + uint8_t dayOfWeekAlarm, + uint8_t dayOfMonthAlarm) +{ + RTC_C_configureCalendarAlarmParam param = { 0 }; + + param.minutesAlarm = minutesAlarm; + param.hoursAlarm = hoursAlarm; + param.dayOfWeekAlarm = dayOfWeekAlarm; + param.dayOfMonthAlarm = dayOfMonthAlarm; + RTC_C_configureCalendarAlarm(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Sets and Enables the desired Calendar Alarm settings. +//! +//! This function sets a Calendar interrupt condition to assert the RTCAIFG +//! interrupt flag. The condition is a logical and of all of the parameters. +//! For example if the minutes and hours alarm is set, then the interrupt will +//! only assert when the minutes AND the hours change to the specified setting. +//! Use the RTC_C_ALARM_OFF for any alarm settings that should not be apart of +//! the alarm condition. +//! +//! \param baseAddress is the base address of the RTC_C module. +//! \param param is the pointer to struct for calendar alarm configuration. +//! +//! \return None +// +//***************************************************************************** +void RTC_C_configureCalendarAlarm(uint16_t baseAddress, + RTC_C_configureCalendarAlarmParam *param) +{ + //Each of these is XORed with 0x80 to turn on if an integer is passed, + //or turn OFF if RTC_C_ALARM_OFF (0x80) is passed. + HWREG8(baseAddress + OFS_RTCAMINHR_L) = (param->minutesAlarm ^ 0x80); + HWREG8(baseAddress + OFS_RTCAMINHR_H) = (param->hoursAlarm ^ 0x80); + HWREG8(baseAddress + OFS_RTCADOWDAY_L) = (param->dayOfWeekAlarm ^ 0x80); + HWREG8(baseAddress + OFS_RTCADOWDAY_H) = (param->dayOfMonthAlarm ^ 0x80); +} +//***************************************************************************** +// +//! \brief Sets a single specified Calendar interrupt condition +//! +//! This function sets a specified event to assert the RTCTEVIFG interrupt. +//! This interrupt is independent from the Calendar alarm interrupt. +//! +//! \param baseAddress is the base address of the RTC_C module. +//! \param eventSelect is the condition selected. +//! Valid values are: +//! - \b RTC_C_CALENDAREVENT_MINUTECHANGE - assert interrupt on every +//! minute +//! - \b RTC_C_CALENDAREVENT_HOURCHANGE - assert interrupt on every hour +//! - \b RTC_C_CALENDAREVENT_NOON - assert interrupt when hour is 12 +//! - \b RTC_C_CALENDAREVENT_MIDNIGHT - assert interrupt when hour is 0 +//! \n Modified bits are \b RTCTEV of \b RTCCTL register. +//! +//! \return None +// +//***************************************************************************** +void RTC_C_setCalendarEvent(uint16_t baseAddress, + uint16_t eventSelect) +{ + HWREG8(baseAddress + OFS_RTCCTL0_H) = RTCKEY_H; + HWREG8(baseAddress + OFS_RTCCTL13_L) &= ~(RTCTEV_3); //Reset bits + HWREG8(baseAddress + OFS_RTCCTL13_L) |= eventSelect; + HWREG8(baseAddress + OFS_RTCCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Returns the value of the Counter register. +//! +//! This function returns the value of the counter register for the RTC_C +//! module. It will return the 32-bit value no matter the size set during +//! initialization. The RTC should be held before trying to use this function. +//! +//! \param baseAddress is the base address of the RTC_C module. +//! +//! \return The raw value of the full 32-bit Counter Register. +// +//***************************************************************************** +uint32_t RTC_C_getCounterValue(uint16_t baseAddress) +{ + if ( (HWREG8(baseAddress + OFS_RTCCTL13) & RTCHOLD) + || (HWREG8(baseAddress + OFS_RTCPS1CTL) & RT1PSHOLD) ) + return 0; + + uint32_t counterValue_L = HWREG16(baseAddress + OFS_RTCTIM0); + uint32_t counterValue_H = HWREG16(baseAddress + OFS_RTCTIM1); + return (counterValue_H << 16) + counterValue_L; +} + +//***************************************************************************** +// +//! \brief Sets the value of the Counter register +//! +//! This function sets the counter register of the RTC_C module. +//! +//! \param baseAddress is the base address of the RTC_C module. +//! \param counterValue is the value to set the Counter register to; a valid +//! value may be any 32-bit integer. +//! +//! \return None +// +//***************************************************************************** +void RTC_C_setCounterValue(uint16_t baseAddress, + uint32_t counterValue) +{ + uint16_t mode = HWREG16(baseAddress + OFS_RTCCTL13) & RTCTEV_3; + + if (mode == RTC_C_COUNTERSIZE_8BIT && counterValue > 0xF) + counterValue = 0xF; + else if (mode == RTC_C_COUNTERSIZE_16BIT && counterValue > 0xFF) + counterValue = 0xFF; + else if (mode == RTC_C_COUNTERSIZE_24BIT && counterValue > 0xFFFFFF) + counterValue = 0xFFFFFF; + + HWREG16(baseAddress + OFS_RTCTIM0) = counterValue; + HWREG16(baseAddress + OFS_RTCTIM1) = ( counterValue >> 16 ); +} + +//***************************************************************************** +// +//! \brief Initializes the Prescaler for Counter mode. +//! +//! This function initializes the selected prescaler for the counter mode in +//! the RTC_C module. If the RTC is initialized in Calendar mode, then these +//! are automatically initialized. The Prescalers can be used to divide a clock +//! source additionally before it gets to the main RTC clock. +//! +//! \param baseAddress is the base address of the RTC_C module. +//! \param prescaleSelect is the prescaler to initialize. +//! Valid values are: +//! - \b RTC_C_PRESCALE_0 +//! - \b RTC_C_PRESCALE_1 +//! \param prescaleClockSelect is the clock to drive the selected prescaler. +//! Valid values are: +//! - \b RTC_C_PSCLOCKSELECT_ACLK +//! - \b RTC_C_PSCLOCKSELECT_SMCLK +//! - \b RTC_C_PSCLOCKSELECT_RT0PS - use Prescaler 0 as source to +//! Prescaler 1 (May only be used if prescaleSelect is +//! RTC_C_PRESCALE_1) +//! \n Modified bits are \b RTxSSEL of \b RTCPSxCTL register. +//! \param prescaleDivider is the divider for the selected clock source. +//! Valid values are: +//! - \b RTC_C_PSDIVIDER_2 [Default] +//! - \b RTC_C_PSDIVIDER_4 +//! - \b RTC_C_PSDIVIDER_8 +//! - \b RTC_C_PSDIVIDER_16 +//! - \b RTC_C_PSDIVIDER_32 +//! - \b RTC_C_PSDIVIDER_64 +//! - \b RTC_C_PSDIVIDER_128 +//! - \b RTC_C_PSDIVIDER_256 +//! \n Modified bits are \b RTxPSDIV of \b RTCPSxCTL register. +//! +//! \return None +// +//***************************************************************************** +void RTC_C_initCounterPrescale(uint16_t baseAddress, + uint8_t prescaleSelect, + uint16_t prescaleClockSelect, + uint16_t prescaleDivider) +{ + //Reset bits and set clock select + HWREG16(baseAddress + OFS_RTCPS0CTL + prescaleSelect) = + prescaleClockSelect + prescaleDivider; +} + +//***************************************************************************** +// +//! \brief Holds the selected Prescaler. +//! +//! This function holds the prescale counter from continuing. This will only +//! work in counter mode, in Calendar mode, the RTC_C_holdClock() must be used. +//! In counter mode, if using both prescalers in conjunction with the main RTC +//! counter, then stopping RT0PS will stop RT1PS, but stopping RT1PS will not +//! stop RT0PS. +//! +//! \param baseAddress is the base address of the RTC_C module. +//! \param prescaleSelect is the prescaler to hold. +//! Valid values are: +//! - \b RTC_C_PRESCALE_0 +//! - \b RTC_C_PRESCALE_1 +//! +//! \return None +// +//***************************************************************************** +void RTC_C_holdCounterPrescale(uint16_t baseAddress, + uint8_t prescaleSelect) +{ + HWREG8(baseAddress + OFS_RTCPS0CTL_H + prescaleSelect) |= RT0PSHOLD_H; +} + +//***************************************************************************** +// +//! \brief Starts the selected Prescaler. +//! +//! This function starts the selected prescale counter. This function will only +//! work if the RTC is in counter mode. +//! +//! \param baseAddress is the base address of the RTC_C module. +//! \param prescaleSelect is the prescaler to start. +//! Valid values are: +//! - \b RTC_C_PRESCALE_0 +//! - \b RTC_C_PRESCALE_1 +//! +//! \return None +// +//***************************************************************************** +void RTC_C_startCounterPrescale(uint16_t baseAddress, + uint8_t prescaleSelect) +{ + HWREG8(baseAddress + OFS_RTCPS0CTL_H + prescaleSelect) &= ~(RT0PSHOLD_H); +} + +//***************************************************************************** +// +//! \brief Sets up an interrupt condition for the selected Prescaler. +//! +//! This function sets the condition for an interrupt to assert based on the +//! individual prescalers. +//! +//! \param baseAddress is the base address of the RTC_C module. +//! \param prescaleSelect is the prescaler to define an interrupt for. +//! Valid values are: +//! - \b RTC_C_PRESCALE_0 +//! - \b RTC_C_PRESCALE_1 +//! \param prescaleEventDivider is a divider to specify when an interrupt can +//! occur based on the clock source of the selected prescaler. (Does not +//! affect timer of the selected prescaler). +//! Valid values are: +//! - \b RTC_C_PSEVENTDIVIDER_2 [Default] +//! - \b RTC_C_PSEVENTDIVIDER_4 +//! - \b RTC_C_PSEVENTDIVIDER_8 +//! - \b RTC_C_PSEVENTDIVIDER_16 +//! - \b RTC_C_PSEVENTDIVIDER_32 +//! - \b RTC_C_PSEVENTDIVIDER_64 +//! - \b RTC_C_PSEVENTDIVIDER_128 +//! - \b RTC_C_PSEVENTDIVIDER_256 +//! \n Modified bits are \b RTxIP of \b RTCPSxCTL register. +//! +//! \return None +// +//***************************************************************************** +void RTC_C_definePrescaleEvent(uint16_t baseAddress, + uint8_t prescaleSelect, + uint8_t prescaleEventDivider) +{ + HWREG8(baseAddress + OFS_RTCPS0CTL_L + prescaleSelect) &= ~(RT0IP_7); + HWREG8(baseAddress + OFS_RTCPS0CTL_L + + prescaleSelect) |= prescaleEventDivider; +} + +//***************************************************************************** +// +//! \brief Returns the selected prescaler value. +//! +//! This function returns the value of the selected prescale counter register. +//! Note that the counter value should be held by calling RTC_C_holdClock() +//! before calling this API. +//! +//! \param baseAddress is the base address of the RTC_C module. +//! \param prescaleSelect is the prescaler to obtain the value of. +//! Valid values are: +//! - \b RTC_C_PRESCALE_0 +//! - \b RTC_C_PRESCALE_1 +//! +//! \return The value of the specified prescaler count register +// +//***************************************************************************** +uint8_t RTC_C_getPrescaleValue(uint16_t baseAddress, + uint8_t prescaleSelect) +{ + if (RTC_C_PRESCALE_0 == prescaleSelect) + return HWREG8(baseAddress + OFS_RTCPS_L); + else if (RTC_C_PRESCALE_1 == prescaleSelect) + return HWREG8(baseAddress + OFS_RTCPS_H); + else + return 0; +} + +//***************************************************************************** +// +//! \brief Sets the selected Prescaler value. +//! +//! This function sets the prescale counter value. Before setting the prescale +//! counter, it should be held by calling RTC_C_holdClock(). +//! +//! \param baseAddress is the base address of the RTC_C module. +//! \param prescaleSelect is the prescaler to set the value for. +//! Valid values are: +//! - \b RTC_C_PRESCALE_0 +//! - \b RTC_C_PRESCALE_1 +//! \param prescaleCounterValue is the specified value to set the prescaler to. +//! Valid values are any integer between 0-255 +//! \n Modified bits are \b RTxPS of \b RTxPS register. +//! +//! \return None +// +//***************************************************************************** +void RTC_C_setPrescaleValue(uint16_t baseAddress, + uint8_t prescaleSelect, + uint8_t prescaleCounterValue) +{ + HWREG8(baseAddress + OFS_RTCCTL0_H) = RTCKEY_H; + if (RTC_C_PRESCALE_0 == prescaleSelect) + HWREG8(baseAddress + OFS_RTCPS_L) = prescaleCounterValue; + else if (RTC_C_PRESCALE_1 == prescaleSelect) + HWREG8(baseAddress + OFS_RTCPS_H) = prescaleCounterValue; + HWREG8(baseAddress + OFS_RTCCTL0_H) = 0x00; +} + +//***************************************************************************** +// +//! \brief Enables selected RTC interrupt sources. +//! +//! This function enables the selected RTC interrupt source. Only the sources +//! that are enabled can be reflected to the processor interrupt; disabled +//! sources have no effect on the processor. Does not clear interrupt flags. +//! +//! \param baseAddress is the base address of the RTC_C module. +//! \param interruptMask is a bit mask of the interrupts to enable. +//! Mask value is the logical OR of any of the following: +//! - \b RTC_C_TIME_EVENT_INTERRUPT - asserts when counter overflows in +//! counter mode or when Calendar event condition defined by +//! defineCalendarEvent() is met. +//! - \b RTC_C_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in +//! Calendar mode is met. +//! - \b RTC_C_CLOCK_READ_READY_INTERRUPT - asserts when Calendar +//! registers are settled. +//! - \b RTC_C_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0 +//! event condition is met. +//! - \b RTC_C_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1 +//! event condition is met. +//! - \b RTC_C_OSCILLATOR_FAULT_INTERRUPT - asserts if there is a +//! problem with the 32kHz oscillator, while the RTC is running. +//! +//! \return None +// +//***************************************************************************** +void RTC_C_enableInterrupt(uint16_t baseAddress, + uint8_t interruptMask) +{ + if ( interruptMask & (RTCOFIE + RTCTEVIE + RTCAIE + RTCRDYIE) ) { + HWREG8(baseAddress + OFS_RTCCTL0_H) = RTCKEY_H; + HWREG8(baseAddress + OFS_RTCCTL0_L) |= + (interruptMask & (RTCOFIE + RTCTEVIE + RTCAIE + RTCRDYIE)); + HWREG8(baseAddress + OFS_RTCCTL0_H) = 0x00; + } + + if (interruptMask & RTC_C_PRESCALE_TIMER0_INTERRUPT) + HWREG8(baseAddress + OFS_RTCPS0CTL_L) |= RT0PSIE; + + if (interruptMask & RTC_C_PRESCALE_TIMER1_INTERRUPT) + HWREG8(baseAddress + OFS_RTCPS1CTL_L) |= RT1PSIE; +} + +//***************************************************************************** +// +//! \brief Disables selected RTC interrupt sources. +//! +//! This function disables the selected RTC interrupt source. Only the sources +//! that are enabled can be reflected to the processor interrupt; disabled +//! sources have no effect on the processor. +//! +//! \param baseAddress is the base address of the RTC_C module. +//! \param interruptMask is a bit mask of the interrupts to disable. +//! Mask value is the logical OR of any of the following: +//! - \b RTC_C_TIME_EVENT_INTERRUPT - asserts when counter overflows in +//! counter mode or when Calendar event condition defined by +//! defineCalendarEvent() is met. +//! - \b RTC_C_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in +//! Calendar mode is met. +//! - \b RTC_C_CLOCK_READ_READY_INTERRUPT - asserts when Calendar +//! registers are settled. +//! - \b RTC_C_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0 +//! event condition is met. +//! - \b RTC_C_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1 +//! event condition is met. +//! - \b RTC_C_OSCILLATOR_FAULT_INTERRUPT - asserts if there is a +//! problem with the 32kHz oscillator, while the RTC is running. +//! +//! \return None +// +//***************************************************************************** +void RTC_C_disableInterrupt(uint16_t baseAddress, + uint8_t interruptMask) +{ + + if ( interruptMask & (RTCOFIE + RTCTEVIE + RTCAIE + RTCRDYIE) ) { + HWREG8(baseAddress + OFS_RTCCTL0_H) = RTCKEY_H; + HWREG8(baseAddress + OFS_RTCCTL0_L) &= + ~(interruptMask & (RTCOFIE + RTCTEVIE + RTCAIE + RTCRDYIE)); + HWREG8(baseAddress + OFS_RTCCTL0_H) = 0x00; + } + + if (interruptMask & RTC_C_PRESCALE_TIMER0_INTERRUPT) + HWREG8(baseAddress + OFS_RTCPS0CTL_L) &= ~(RT0PSIE); + + if (interruptMask & RTC_C_PRESCALE_TIMER1_INTERRUPT) + HWREG8(baseAddress + OFS_RTCPS1CTL_L) &= ~(RT1PSIE); +} + +//***************************************************************************** +// +//! \brief Returns the status of the selected interrupts flags. +//! +//! This function returns the status of the interrupt flag for the selected +//! channel. +//! +//! \param baseAddress is the base address of the RTC_C module. +//! \param interruptFlagMask is a bit mask of the interrupt flags to return the +//! status of. +//! Mask value is the logical OR of any of the following: +//! - \b RTC_C_TIME_EVENT_INTERRUPT - asserts when counter overflows in +//! counter mode or when Calendar event condition defined by +//! defineCalendarEvent() is met. +//! - \b RTC_C_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in +//! Calendar mode is met. +//! - \b RTC_C_CLOCK_READ_READY_INTERRUPT - asserts when Calendar +//! registers are settled. +//! - \b RTC_C_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0 +//! event condition is met. +//! - \b RTC_C_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1 +//! event condition is met. +//! - \b RTC_C_OSCILLATOR_FAULT_INTERRUPT - asserts if there is a +//! problem with the 32kHz oscillator, while the RTC is running. +//! +//! \return Logical OR of any of the following: +//! - \b RTC_C_TIME_EVENT_INTERRUPT asserts when counter overflows in +//! counter mode or when Calendar event condition defined by +//! defineCalendarEvent() is met. +//! - \b RTC_C_CLOCK_ALARM_INTERRUPT asserts when alarm condition in +//! Calendar mode is met. +//! - \b RTC_C_CLOCK_READ_READY_INTERRUPT asserts when Calendar +//! registers are settled. +//! - \b RTC_C_PRESCALE_TIMER0_INTERRUPT asserts when Prescaler 0 event +//! condition is met. +//! - \b RTC_C_PRESCALE_TIMER1_INTERRUPT asserts when Prescaler 1 event +//! condition is met. +//! - \b RTC_C_OSCILLATOR_FAULT_INTERRUPT asserts if there is a problem +//! with the 32kHz oscillator, while the RTC is running. +//! \n indicating the status of the masked interrupts +// +//***************************************************************************** +uint8_t RTC_C_getInterruptStatus(uint16_t baseAddress, + uint8_t interruptFlagMask) +{ + uint8_t tempInterruptFlagMask = 0x0000; + + tempInterruptFlagMask |= (HWREG8(baseAddress + OFS_RTCCTL0_L) + & ((interruptFlagMask >> 4) + & (RTCOFIFG + + RTCTEVIFG + + RTCAIFG + + RTCRDYIFG))); + + tempInterruptFlagMask = tempInterruptFlagMask << 4; + + if (interruptFlagMask & RTC_C_PRESCALE_TIMER0_INTERRUPT) + if ( HWREG8(baseAddress + OFS_RTCPS0CTL_L) & RT0PSIFG) + tempInterruptFlagMask |= RTC_C_PRESCALE_TIMER0_INTERRUPT; + + if (interruptFlagMask & RTC_C_PRESCALE_TIMER1_INTERRUPT) + if ( HWREG8(baseAddress + OFS_RTCPS1CTL_L) & RT1PSIFG) + tempInterruptFlagMask |= RTC_C_PRESCALE_TIMER1_INTERRUPT; + + return tempInterruptFlagMask; +} + +//***************************************************************************** +// +//! \brief Clears selected RTC interrupt flags. +//! +//! This function clears the RTC interrupt flag is cleared, so that it no +//! longer asserts. +//! +//! \param baseAddress is the base address of the RTC_C module. +//! \param interruptFlagMask is a bit mask of the interrupt flags to be +//! cleared. +//! Mask value is the logical OR of any of the following: +//! - \b RTC_C_TIME_EVENT_INTERRUPT - asserts when counter overflows in +//! counter mode or when Calendar event condition defined by +//! defineCalendarEvent() is met. +//! - \b RTC_C_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in +//! Calendar mode is met. +//! - \b RTC_C_CLOCK_READ_READY_INTERRUPT - asserts when Calendar +//! registers are settled. +//! - \b RTC_C_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0 +//! event condition is met. +//! - \b RTC_C_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1 +//! event condition is met. +//! - \b RTC_C_OSCILLATOR_FAULT_INTERRUPT - asserts if there is a +//! problem with the 32kHz oscillator, while the RTC is running. +//! +//! \return None +// +//***************************************************************************** +void RTC_C_clearInterrupt(uint16_t baseAddress, + uint8_t interruptFlagMask) +{ + + if ( interruptFlagMask & (RTC_C_TIME_EVENT_INTERRUPT + + RTC_C_CLOCK_ALARM_INTERRUPT + + RTC_C_CLOCK_READ_READY_INTERRUPT + + RTC_C_OSCILLATOR_FAULT_INTERRUPT) ) { + HWREG8(baseAddress + OFS_RTCCTL0_H) = RTCKEY_H; + HWREG8(baseAddress + OFS_RTCCTL0_L) &= + ~((interruptFlagMask >> 4) & (RTCOFIFG + + RTCTEVIFG + + RTCAIFG + + RTCRDYIFG)); + HWREG8(baseAddress + OFS_RTCCTL0_H) = 0x00; + } + + if (interruptFlagMask & RTC_C_PRESCALE_TIMER0_INTERRUPT) + HWREG8(baseAddress + OFS_RTCPS0CTL_L) &= ~(RT0PSIFG); + + if (interruptFlagMask & RTC_C_PRESCALE_TIMER1_INTERRUPT) + HWREG8(baseAddress + OFS_RTCPS1CTL_L) &= ~(RT1PSIFG); +} + +//***************************************************************************** +// +//! \brief Convert the given BCD value to binary format +//! +//! This function converts BCD values to binary format. This API uses the +//! hardware registers to perform the conversion rather than a software method. +//! +//! \param baseAddress is the base address of the RTC_C module. +//! \param valueToConvert is the raw value in BCD format to convert to Binary. +//! \n Modified bits are \b BCD2BIN of \b BCD2BIN register. +//! +//! \return The binary version of the input parameter +// +//***************************************************************************** +uint16_t RTC_C_convertBCDToBinary(uint16_t baseAddress, + uint16_t valueToConvert) +{ + HWREG16(baseAddress + OFS_BCD2BIN) = valueToConvert; + return HWREG16(baseAddress + OFS_BCD2BIN); +} + +//***************************************************************************** +// +//! \brief Convert the given binary value to BCD format +//! +//! This function converts binary values to BCD format. This API uses the +//! hardware registers to perform the conversion rather than a software method. +//! +//! \param baseAddress is the base address of the RTC_C module. +//! \param valueToConvert is the raw value in Binary format to convert to BCD. +//! \n Modified bits are \b BIN2BCD of \b BIN2BCD register. +//! +//! \return The BCD version of the valueToConvert parameter +// +//***************************************************************************** +uint16_t RTC_C_convertBinaryToBCD(uint16_t baseAddress, + uint16_t valueToConvert) +{ + HWREG16(baseAddress + OFS_BIN2BCD) = valueToConvert; + return HWREG16(baseAddress + OFS_BIN2BCD); +} + +#endif +//***************************************************************************** +// +//! Close the doxygen group for rtc_c_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/rtc_c.h b/source/driverlib/MSP430F5xx_6xx/rtc_c.h new file mode 100644 index 0000000..a69cd03 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/rtc_c.h @@ -0,0 +1,365 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// rtc_c.h - Driver for the RTC_C Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_RTC_C_H__ +#define __MSP430WARE_RTC_C_H__ + +#include "inc/hw_memmap.h" + +#if defined(__MSP430_HAS_RTC_C__) || defined(__MSP430_HAS_RTC_CE__) + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following is a struct that can be passed to RTC_C_CalendarInit() in the +// CalendarTime parameter, as well as returned by RTC_C_getCalendarTime() +// +//***************************************************************************** +typedef struct { + uint8_t Seconds; + uint8_t Minutes; + uint8_t Hours; + uint8_t DayOfWeek; + uint8_t DayOfMonth; + uint8_t Month; + uint16_t Year; +} Calendar; + +//****************************************************************************** +// +// The following is a struct that is passed to RTC_C_configureCalendarAlarm() +// +//****************************************************************************** +typedef struct RTC_C_configureCalendarAlarmParam { + uint8_t minutesAlarm; + uint8_t hoursAlarm; + uint8_t dayOfWeekAlarm; + uint8_t dayOfMonthAlarm; +} RTC_C_configureCalendarAlarmParam; + +//***************************************************************************** +// +// The following are values that can be passed to the frequencySelect parameter +// for functions: RTC_C_setCalibrationFrequency(). +// +//***************************************************************************** +#define RTC_C_CALIBRATIONFREQ_OFF (RTCCALF_0) +#define RTC_C_CALIBRATIONFREQ_512HZ (RTCCALF_1) +#define RTC_C_CALIBRATIONFREQ_256HZ (RTCCALF_2) +#define RTC_C_CALIBRATIONFREQ_1HZ (RTCCALF_3) + +//***************************************************************************** +// +// The following are values that can be passed to the offsetDirection parameter +// for functions: RTC_C_setCalibrationData(). +// +//***************************************************************************** +#define RTC_C_CALIBRATION_DOWN1PPM (!(RTCCALS)) +#define RTC_C_CALIBRATION_UP1PPM (RTCCALS) + +//***************************************************************************** +// +// The following are values that can be passed to the offsetDirection parameter +// for functions: RTC_C_setTemperatureCompensation(). +// +//***************************************************************************** +#define RTC_C_COMPENSATION_DOWN1PPM (!(RTCTCMPS)) +#define RTC_C_COMPENSATION_UP1PPM (RTCTCMPS) + +//***************************************************************************** +// +// The following are values that can be passed to the clockSelect parameter for +// functions: RTC_C_initCounter(). +// +//***************************************************************************** +#define RTC_C_CLOCKSELECT_32KHZ_OSC (RTCSSEL_0) +#define RTC_C_CLOCKSELECT_RT1PS (RTCSSEL_2) + +//***************************************************************************** +// +// The following are values that can be passed to the counterSizeSelect +// parameter for functions: RTC_C_initCounter(). +// +//***************************************************************************** +#define RTC_C_COUNTERSIZE_8BIT (RTCTEV_0) +#define RTC_C_COUNTERSIZE_16BIT (RTCTEV_1) +#define RTC_C_COUNTERSIZE_24BIT (RTCTEV_2) +#define RTC_C_COUNTERSIZE_32BIT (RTCTEV_3) + +//***************************************************************************** +// +// The following are values that can be passed to the formatSelect parameter +// for functions: RTC_C_initCalendar(), and RTC_C_calendarInit(). +// +//***************************************************************************** +#define RTC_C_FORMAT_BINARY (!(RTCBCD)) +#define RTC_C_FORMAT_BCD (RTCBCD) + +//***************************************************************************** +// +// The following are values that can be passed to the minutesAlarm parameter +// for functions: RTC_C_setCalendarAlarm(); the dayOfMonthAlarm parameter for +// functions: RTC_C_setCalendarAlarm(); the hoursAlarm parameter for functions: +// RTC_C_setCalendarAlarm(); the dayOfWeekAlarm parameter for functions: +// RTC_C_setCalendarAlarm(). +// +//***************************************************************************** +#define RTC_C_ALARMCONDITION_OFF (0x80) + +//***************************************************************************** +// +// The following are values that can be passed to the eventSelect parameter for +// functions: RTC_C_setCalendarEvent(). +// +//***************************************************************************** +#define RTC_C_CALENDAREVENT_MINUTECHANGE (RTCTEV_0) +#define RTC_C_CALENDAREVENT_HOURCHANGE (RTCTEV_1) +#define RTC_C_CALENDAREVENT_NOON (RTCTEV_2) +#define RTC_C_CALENDAREVENT_MIDNIGHT (RTCTEV_3) + +//***************************************************************************** +// +// The following are values that can be passed to the prescaleDivider parameter +// for functions: RTC_C_initCounterPrescale(). +// +//***************************************************************************** +#define RTC_C_PSDIVIDER_2 (RT0PSDIV_0) +#define RTC_C_PSDIVIDER_4 (RT0PSDIV_1) +#define RTC_C_PSDIVIDER_8 (RT0PSDIV_2) +#define RTC_C_PSDIVIDER_16 (RT0PSDIV_3) +#define RTC_C_PSDIVIDER_32 (RT0PSDIV_4) +#define RTC_C_PSDIVIDER_64 (RT0PSDIV_5) +#define RTC_C_PSDIVIDER_128 (RT0PSDIV_6) +#define RTC_C_PSDIVIDER_256 (RT0PSDIV_7) + +//***************************************************************************** +// +// The following are values that can be passed to the prescaleClockSelect +// parameter for functions: RTC_C_initCounterPrescale(). +// +//***************************************************************************** +#define RTC_C_PSCLOCKSELECT_ACLK (RT1SSEL_0) +#define RTC_C_PSCLOCKSELECT_SMCLK (RT1SSEL_1) +#define RTC_C_PSCLOCKSELECT_RT0PS (RT1SSEL_2) + +//***************************************************************************** +// +// The following are values that can be passed to the prescaleEventDivider +// parameter for functions: RTC_C_definePrescaleEvent(). +// +//***************************************************************************** +#define RTC_C_PSEVENTDIVIDER_2 (RT0IP_0) +#define RTC_C_PSEVENTDIVIDER_4 (RT0IP_1) +#define RTC_C_PSEVENTDIVIDER_8 (RT0IP_2) +#define RTC_C_PSEVENTDIVIDER_16 (RT0IP_3) +#define RTC_C_PSEVENTDIVIDER_32 (RT0IP_4) +#define RTC_C_PSEVENTDIVIDER_64 (RT0IP_5) +#define RTC_C_PSEVENTDIVIDER_128 (RT0IP_6) +#define RTC_C_PSEVENTDIVIDER_256 (RT0IP_7) + +//***************************************************************************** +// +// The following are values that can be passed to the prescaleSelect parameter +// for functions: RTC_C_initCounterPrescale(), RTC_C_holdCounterPrescale(), +// RTC_C_startCounterPrescale(), RTC_C_definePrescaleEvent(), +// RTC_C_getPrescaleValue(), and RTC_C_setPrescaleValue(). +// +//***************************************************************************** +#define RTC_C_PRESCALE_0 (0x0) +#define RTC_C_PRESCALE_1 (0x2) + +//***************************************************************************** +// +// The following are values that can be passed to the interruptMask parameter +// for functions: RTC_C_enableInterrupt(), and RTC_C_disableInterrupt(); the +// interruptFlagMask parameter for functions: RTC_C_getInterruptStatus(), and +// RTC_C_clearInterrupt() as well as returned by the RTC_C_getInterruptStatus() +// function. +// +//***************************************************************************** +#define RTC_C_TIME_EVENT_INTERRUPT RTCTEVIE +#define RTC_C_CLOCK_ALARM_INTERRUPT RTCAIE +#define RTC_C_CLOCK_READ_READY_INTERRUPT RTCRDYIE +#define RTC_C_PRESCALE_TIMER0_INTERRUPT 0x02 +#define RTC_C_PRESCALE_TIMER1_INTERRUPT 0x01 +#define RTC_C_OSCILLATOR_FAULT_INTERRUPT RTCOFIE + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void RTC_C_startClock(uint16_t baseAddress); + +extern void RTC_C_holdClock(uint16_t baseAddress); + +extern void RTC_C_setCalibrationFrequency(uint16_t baseAddress, + uint16_t frequencySelect); + +extern void RTC_C_setCalibrationData(uint16_t baseAddress, + uint8_t offsetDirection, + uint8_t offsetValue); + +extern void RTC_C_initCounter(uint16_t baseAddress, + uint16_t clockSelect, + uint16_t counterSizeSelect); + +extern bool RTC_C_setTemperatureCompensation(uint16_t baseAddress, + uint16_t offsetDirection, + uint8_t offsetValue); + +extern void RTC_C_initCalendar(uint16_t baseAddress, + Calendar *CalendarTime, + uint16_t formatSelect); + +extern Calendar RTC_C_getCalendarTime(uint16_t baseAddress); + +extern void RTC_C_configureCalendarAlarm(uint16_t baseAddress, + RTC_C_configureCalendarAlarmParam *param); + +extern void RTC_C_setCalendarEvent(uint16_t baseAddress, + uint16_t eventSelect); + +extern uint32_t RTC_C_getCounterValue(uint16_t baseAddress); + +extern void RTC_C_setCounterValue(uint16_t baseAddress, + uint32_t counterValue); + +extern void RTC_C_initCounterPrescale(uint16_t baseAddress, + uint8_t prescaleSelect, + uint16_t prescaleClockSelect, + uint16_t prescaleDivider); + +extern void RTC_C_holdCounterPrescale(uint16_t baseAddress, + uint8_t prescaleSelect); + +extern void RTC_C_startCounterPrescale(uint16_t baseAddress, + uint8_t prescaleSelect); + +extern void RTC_C_definePrescaleEvent(uint16_t baseAddress, + uint8_t prescaleSelect, + uint8_t prescaleEventDivider); + +extern uint8_t RTC_C_getPrescaleValue(uint16_t baseAddress, + uint8_t prescaleSelect); + +extern void RTC_C_setPrescaleValue(uint16_t baseAddress, + uint8_t prescaleSelect, + uint8_t prescaleCounterValue); + +extern void RTC_C_enableInterrupt(uint16_t baseAddress, + uint8_t interruptMask); + +extern void RTC_C_disableInterrupt(uint16_t baseAddress, + uint8_t interruptMask); + +extern uint8_t RTC_C_getInterruptStatus(uint16_t baseAddress, + uint8_t interruptFlagMask); + +extern void RTC_C_clearInterrupt(uint16_t baseAddress, + uint8_t interruptFlagMask); + +extern uint16_t RTC_C_convertBCDToBinary(uint16_t baseAddress, + uint16_t valueToConvert); + +extern uint16_t RTC_C_convertBinaryToBCD(uint16_t baseAddress, + uint16_t valueToConvert); + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +#define RTC_C_counterInit RTC_C_initCounter + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +#define RTC_C_counterPrescaleInit RTC_C_initCounterPrescale + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +#define RTC_C_counterPrescaleStart RTC_C_startCounterPrescale + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +#define RTC_C_counterPrescaleHold RTC_C_holdCounterPrescale + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +extern void RTC_C_calendarInit(uint16_t baseAddress, + Calendar CalendarTime, + uint16_t formatSelect); + +extern void RTC_C_setCalendarAlarm(uint16_t baseAddress, + uint8_t minutesAlarm, + uint8_t hoursAlarm, + uint8_t dayOfWeekAlarm, + uint8_t dayOfMonthAlarm); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_RTC_C_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/sd24_b.c b/source/driverlib/MSP430F5xx_6xx/sd24_b.c new file mode 100644 index 0000000..179f140 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/sd24_b.c @@ -0,0 +1,1154 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// sd24_b.c - Driver for the sd24_b Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup sd24_b_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_SD24_B__ +#include "sd24_b.h" + +#include + +//***************************************************************************** +// +//! \brief DEPRECATED - Initializes the SD24_B Module +//! +//! This function initializes the SD24_B module sigma-delta analog-to-digital +//! conversions. Specifically the function sets up the clock source for the +//! SD24_B core to use for conversions. Upon completion of the initialization +//! the SD24_B interrupt registers will be reset and the given parameters will +//! be set. The converter configuration settings are independent of this +//! function. The values you choose for the clock divider and predivider are +//! used to determine the effective clock frequency. The formula used is: +//! f_sd24 = f_clk /(divider * predivider) +//! +//! \param baseAddress is the base address of the SD24_B module. +//! \param clockSourceSelect selects the clock that will be used as the SD24_B +//! core +//! Valid values are: +//! - \b SD24_B_CLOCKSOURCE_MCLK [Default] +//! - \b SD24_B_CLOCKSOURCE_SMCLK +//! - \b SD24_B_CLOCKSOURCE_ACLK +//! - \b SD24_B_CLOCKSOURCE_SD24CLK +//! \n Modified bits are \b SD24SSEL of \b SD24BCTL0 register. +//! \param clockPreDivider selects the amount that the clock will be predivided +//! Valid values are: +//! - \b SD24_B_PRECLOCKDIVIDER_1 [Default] +//! - \b SD24_B_PRECLOCKDIVIDER_2 +//! - \b SD24_B_PRECLOCKDIVIDER_4 +//! - \b SD24_B_PRECLOCKDIVIDER_8 +//! - \b SD24_B_PRECLOCKDIVIDER_16 +//! - \b SD24_B_PRECLOCKDIVIDER_32 +//! - \b SD24_B_PRECLOCKDIVIDER_64 +//! - \b SD24_B_PRECLOCKDIVIDER_128 +//! \n Modified bits are \b SD24PDIVx of \b SD24BCTL0 register. +//! \param clockDivider selects the amount that the clock will be divided. +//! Valid values are: +//! - \b SD24_B_CLOCKDIVIDER_1 [Default] +//! - \b SD24_B_CLOCKDIVIDER_2 +//! - \b SD24_B_CLOCKDIVIDER_3 +//! - \b SD24_B_CLOCKDIVIDER_4 +//! - \b SD24_B_CLOCKDIVIDER_5 +//! - \b SD24_B_CLOCKDIVIDER_6 +//! - \b SD24_B_CLOCKDIVIDER_7 +//! - \b SD24_B_CLOCKDIVIDER_8 +//! - \b SD24_B_CLOCKDIVIDER_9 +//! - \b SD24_B_CLOCKDIVIDER_10 +//! - \b SD24_B_CLOCKDIVIDER_11 +//! - \b SD24_B_CLOCKDIVIDER_12 +//! - \b SD24_B_CLOCKDIVIDER_13 +//! - \b SD24_B_CLOCKDIVIDER_14 +//! - \b SD24_B_CLOCKDIVIDER_15 +//! - \b SD24_B_CLOCKDIVIDER_16 +//! - \b SD24_B_CLOCKDIVIDER_17 +//! - \b SD24_B_CLOCKDIVIDER_18 +//! - \b SD24_B_CLOCKDIVIDER_19 +//! - \b SD24_B_CLOCKDIVIDER_20 +//! - \b SD24_B_CLOCKDIVIDER_21 +//! - \b SD24_B_CLOCKDIVIDER_22 +//! - \b SD24_B_CLOCKDIVIDER_23 +//! - \b SD24_B_CLOCKDIVIDER_24 +//! - \b SD24_B_CLOCKDIVIDER_25 +//! - \b SD24_B_CLOCKDIVIDER_26 +//! - \b SD24_B_CLOCKDIVIDER_27 +//! - \b SD24_B_CLOCKDIVIDER_28 +//! - \b SD24_B_CLOCKDIVIDER_29 +//! - \b SD24_B_CLOCKDIVIDER_30 +//! - \b SD24_B_CLOCKDIVIDER_31 +//! - \b SD24_B_CLOCKDIVIDER_32 +//! \n Modified bits are \b SD24DIVx of \b SD24BCTL0 register. +//! \param referenceSelect selects the reference source for the SD24_B core +//! Valid values are: +//! - \b SD24_B_REF_EXTERNAL [Default] +//! - \b SD24_B_REF_INTERNAL +//! \n Modified bits are \b SD24REFS of \b SD24BCTL0 register. +//! +//! \return None +// +//***************************************************************************** +void SD24_B_init(uint16_t baseAddress, + uint16_t clockSourceSelect, + uint16_t clockPreDivider, + uint16_t clockDivider, + uint16_t referenceSelect ) +{ + SD24_B_initializeParam param = { 0 }; + + param.clockSourceSelect = clockSourceSelect; + param.clockPreDivider = clockPreDivider; + param.clockDivider = clockDivider; + param.referenceSelect = referenceSelect; + + SD24_B_initialize(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Initializes the SD24_B Module +//! +//! This function initializes the SD24_B module sigma-delta analog-to-digital +//! conversions. Specifically the function sets up the clock source for the +//! SD24_B core to use for conversions. Upon completion of the initialization +//! the SD24_B interrupt registers will be reset and the given parameters will +//! be set. The converter configuration settings are independent of this +//! function. The values you choose for the clock divider and predivider are +//! used to determine the effective clock frequency. The formula used is: +//! f_sd24 = f_clk /(divider * predivider) +//! +//! \param baseAddress is the base address of the SD24_B module. +//! \param param is the pointer to struct for initialization. +//! +//! \return None +// +//***************************************************************************** +void SD24_B_initialize(uint16_t baseAddress, SD24_B_initializeParam *param) +{ + assert(param != 0); + assert( + (SD24_B_CLOCKSOURCE_MCLK == param->clockSourceSelect) || + (SD24_B_CLOCKSOURCE_SMCLK == param->clockSourceSelect) || + (SD24_B_CLOCKSOURCE_ACLK == param->clockSourceSelect) || + (SD24_B_CLOCKSOURCE_SD24CLK == param->clockSourceSelect) + ); + + assert( + (SD24_B_REF_EXTERNAL == param->referenceSelect) || + (SD24_B_REF_INTERNAL == param->referenceSelect) + ); + + // Reset all interrupts and flags + HWREG16(baseAddress + OFS_SD24BIE) &= 0x0000; //Reset ALL interrupt enables + HWREG16(baseAddress + OFS_SD24BIFG) &= 0x0000; //Reset ALL interrupt flags + HWREG16(baseAddress + OFS_SD24BTRGCTL) &= ~(SD24TRGIE | SD24TRGIFG); + + // Turn off all group conversions + HWREG16(baseAddress + OFS_SD24BCTL1) &= ~(SD24GRP0SC | SD24GRP1SC + | SD24GRP2SC | SD24GRP3SC); + + // Configure SD24_B + HWREG16(baseAddress + OFS_SD24BCTL0) &= ~((SD24DIV4 | SD24DIV3 | SD24DIV2 + | SD24DIV1 | SD24DIV0) | SD24PDIV_7 | SD24SSEL_3 | SD24REFS); + HWREG16(baseAddress + OFS_SD24BCTL0) |= (param->clockSourceSelect | + param->clockPreDivider | param->clockDivider | param->referenceSelect); + + return; +} + +//***************************************************************************** +// +//! \brief DEPRECATED - Configure SD24_B converter +//! +//! This function initializes a converter of the SD24_B module. Upon completion +//! the converter will be ready for a conversion and can be started with the +//! SD24_B_startGroupConversion() or SD24_B_startConverterConversion() +//! depending on the startSelect parameter. Additional configuration such as +//! data format can be configured in SD24_B_setConverterDataFormat(). +//! +//! \param baseAddress is the base address of the SD24_B module. +//! \param converter selects the converter that will be configured. Check check +//! datasheet for available converters on device. +//! Valid values are: +//! - \b SD24_B_CONVERTER_0 +//! - \b SD24_B_CONVERTER_1 +//! - \b SD24_B_CONVERTER_2 +//! - \b SD24_B_CONVERTER_3 +//! - \b SD24_B_CONVERTER_4 +//! - \b SD24_B_CONVERTER_5 +//! - \b SD24_B_CONVERTER_6 +//! - \b SD24_B_CONVERTER_7 +//! \param alignment selects how the data will be aligned in result +//! Valid values are: +//! - \b SD24_B_ALIGN_RIGHT [Default] +//! - \b SD24_B_ALIGN_LEFT +//! \n Modified bits are \b SD24ALGN of \b SD24BCCTLx register. +//! \param startSelect selects what will trigger the start of the converter +//! Valid values are: +//! - \b SD24_B_CONVERSION_SELECT_SD24SC [Default] +//! - \b SD24_B_CONVERSION_SELECT_EXT1 +//! - \b SD24_B_CONVERSION_SELECT_EXT2 +//! - \b SD24_B_CONVERSION_SELECT_EXT3 +//! - \b SD24_B_CONVERSION_SELECT_GROUP0 +//! - \b SD24_B_CONVERSION_SELECT_GROUP1 +//! - \b SD24_B_CONVERSION_SELECT_GROUP2 +//! - \b SD24_B_CONVERSION_SELECT_GROUP3 +//! \n Modified bits are \b SD24SCSx of \b SD24BCCTLx register. +//! \param conversionMode determines whether the converter will do continuous +//! samples or a single sample +//! Valid values are: +//! - \b SD24_B_CONTINUOUS_MODE [Default] +//! - \b SD24_B_SINGLE_MODE +//! \n Modified bits are \b SD24SNGL of \b SD24BCCTLx register. +//! +//! \return None +// +//***************************************************************************** +void SD24_B_configureConverter(uint16_t baseAddress, + uint8_t converter, + uint8_t alignment, + uint8_t startSelect, + uint8_t conversionMode ) +{ + SD24_B_initConverterParam param = { 0 }; + + param.converter = converter; + param.alignment = alignment; + param.startSelect = startSelect; + param.conversionMode = conversionMode; + + SD24_B_initConverter(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Configure SD24_B converter +//! +//! This function initializes a converter of the SD24_B module. Upon completion +//! the converter will be ready for a conversion and can be started with the +//! SD24_B_startGroupConversion() or SD24_B_startConverterConversion() +//! depending on the startSelect parameter. Additional configuration such as +//! data format can be configured in SD24_B_setConverterDataFormat(). +//! +//! \param baseAddress is the base address of the SD24_B module. +//! \param param is the pointer to struct for converter configuration. +//! +//! \return None +// +//***************************************************************************** +void SD24_B_initConverter(uint16_t baseAddress, + SD24_B_initConverterParam *param) +{ + assert(param != 0); + assert( + (SD24_B_CONVERTER_0 == param->converter) || + (SD24_B_CONVERTER_1 == param->converter) || + (SD24_B_CONVERTER_2 == param->converter) || + (SD24_B_CONVERTER_3 == param->converter) || + (SD24_B_CONVERTER_4 == param->converter) || + (SD24_B_CONVERTER_5 == param->converter) || + (SD24_B_CONVERTER_6 == param->converter) || + (SD24_B_CONVERTER_7 == param->converter) + ); + + uint16_t address = baseAddress + (OFS_SD24BCCTL0 + (param->converter * 0x08)); + + // Clearing previous settings for configuration + HWREG16(address) &= ~(SD24ALGN | SD24SNGL | SD24SCS__GROUP3); + + HWREG16(address) |= (param->alignment | param->startSelect | + (((uint16_t)param->conversionMode) << 8)); +} + +//***************************************************************************** +// +//! \brief DEPRECATED - Configure SD24_B converter - Advanced Configure +//! +//! This function initializes a converter of the SD24_B module. Upon completion +//! the converter will be ready for a conversion and can be started with the +//! SD24_B_startGroupConversion() or SD24_B_startConverterConversion() +//! depending on the startSelect parameter. +//! +//! \param baseAddress is the base address of the SD24_B module. +//! \param converter selects the converter that will be configured. Check check +//! datasheet for available converters on device. +//! Valid values are: +//! - \b SD24_B_CONVERTER_0 +//! - \b SD24_B_CONVERTER_1 +//! - \b SD24_B_CONVERTER_2 +//! - \b SD24_B_CONVERTER_3 +//! - \b SD24_B_CONVERTER_4 +//! - \b SD24_B_CONVERTER_5 +//! - \b SD24_B_CONVERTER_6 +//! - \b SD24_B_CONVERTER_7 +//! \param alignment selects how the data will be aligned in result +//! Valid values are: +//! - \b SD24_B_ALIGN_RIGHT [Default] +//! - \b SD24_B_ALIGN_LEFT +//! \n Modified bits are \b SD24ALGN of \b SD24BCCTLx register. +//! \param startSelect selects what will trigger the start of the converter +//! Valid values are: +//! - \b SD24_B_CONVERSION_SELECT_SD24SC [Default] +//! - \b SD24_B_CONVERSION_SELECT_EXT1 +//! - \b SD24_B_CONVERSION_SELECT_EXT2 +//! - \b SD24_B_CONVERSION_SELECT_EXT3 +//! - \b SD24_B_CONVERSION_SELECT_GROUP0 +//! - \b SD24_B_CONVERSION_SELECT_GROUP1 +//! - \b SD24_B_CONVERSION_SELECT_GROUP2 +//! - \b SD24_B_CONVERSION_SELECT_GROUP3 +//! \n Modified bits are \b SD24SCSx of \b SD24BCCTLx register. +//! \param conversionMode determines whether the converter will do continuous +//! samples or a single sample +//! Valid values are: +//! - \b SD24_B_CONTINUOUS_MODE [Default] +//! - \b SD24_B_SINGLE_MODE +//! \n Modified bits are \b SD24SNGL of \b SD24BCCTLx register. +//! \param dataFormat selects how the data format of the results +//! Valid values are: +//! - \b SD24_B_DATA_FORMAT_BINARY [Default] +//! - \b SD24_B_DATA_FORMAT_2COMPLEMENT +//! \n Modified bits are \b SD24DFx of \b SD24BCCTLx register. +//! \param sampleDelay selects the delay for the interrupt +//! Valid values are: +//! - \b SD24_B_FOURTH_SAMPLE_INTERRUPT [Default] +//! - \b SD24_B_THIRD_SAMPLE_INTERRUPT +//! - \b SD24_B_SECOND_SAMPLE_INTERRUPT +//! - \b SD24_B_FIRST_SAMPLE_INTERRUPT +//! \n Modified bits are \b SD24INTDLYx of \b SD24INCTLx register. +//! \param oversampleRatio selects oversampling ratio for the converter +//! Valid values are: +//! - \b SD24_B_OVERSAMPLE_32 +//! - \b SD24_B_OVERSAMPLE_64 +//! - \b SD24_B_OVERSAMPLE_128 +//! - \b SD24_B_OVERSAMPLE_256 +//! - \b SD24_B_OVERSAMPLE_512 +//! - \b SD24_B_OVERSAMPLE_1024 +//! \n Modified bits are \b SD24OSRx of \b SD24BOSRx register. +//! \param gain selects the gain for the converter +//! Valid values are: +//! - \b SD24_B_GAIN_1 [Default] +//! - \b SD24_B_GAIN_2 +//! - \b SD24_B_GAIN_4 +//! - \b SD24_B_GAIN_8 +//! - \b SD24_B_GAIN_16 +//! - \b SD24_B_GAIN_32 +//! - \b SD24_B_GAIN_64 +//! - \b SD24_B_GAIN_128 +//! \n Modified bits are \b SD24GAINx of \b SD24BINCTLx register. +//! +//! \return None +// +//***************************************************************************** +void SD24_B_configureConverterAdvanced(uint16_t baseAddress, + uint8_t converter, + uint8_t alignment, + uint8_t startSelect, + uint8_t conversionMode, + uint8_t dataFormat, + uint8_t sampleDelay, + uint16_t oversampleRatio, + uint8_t gain + ) +{ + SD24_B_initConverterAdvancedParam param = { 0 }; + + param.converter = converter; + param.alignment = alignment; + param.startSelect = startSelect; + param.conversionMode = conversionMode; + param.dataFormat = dataFormat; + param.sampleDelay = sampleDelay; + param.oversampleRatio = oversampleRatio; + param.gain = gain; + + SD24_B_initConverterAdvanced(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Configure SD24_B converter - Advanced Configure +//! +//! This function initializes a converter of the SD24_B module. Upon completion +//! the converter will be ready for a conversion and can be started with the +//! SD24_B_startGroupConversion() or SD24_B_startConverterConversion() +//! depending on the startSelect parameter. +//! +//! \param baseAddress is the base address of the SD24_B module. +//! \param param is the pointer to struct for converter advanced configuration. +//! +//! \return None +// +//***************************************************************************** +void SD24_B_initConverterAdvanced(uint16_t baseAddress, + SD24_B_initConverterAdvancedParam *param) +{ + assert(param != 0); + assert( + (SD24_B_CONVERTER_0 == param->converter) || + (SD24_B_CONVERTER_1 == param->converter) || + (SD24_B_CONVERTER_2 == param->converter) || + (SD24_B_CONVERTER_3 == param->converter) || + (SD24_B_CONVERTER_4 == param->converter) || + (SD24_B_CONVERTER_5 == param->converter) || + (SD24_B_CONVERTER_6 == param->converter) || + (SD24_B_CONVERTER_7 == param->converter) + ); + + // Getting correct SD24BCCTLx register + uint16_t address = baseAddress + (OFS_SD24BCCTL0 + (param->converter * 0x08)); + + // Clearing previous settings for configuration + HWREG16(address) &= ~(SD24ALGN | SD24SNGL | SD24DF_1 | SD24DF_0 | SD24SCS__GROUP3 ); + + HWREG16(address) |= (param->alignment | param->startSelect | param->dataFormat | + (((uint16_t)param->conversionMode) << 8)); + + // Getting correct SDBINTCTLx register + address = baseAddress + (OFS_SD24BINCTL0 + (param->converter * 0x08)); + + // Clearing previous settings for configuration + HWREG16(address) &= ~(SD24GAIN_128 | SD24INTDLY_3); + + HWREG16(address) |= (param->gain | param->sampleDelay); + + // Getting correct SDBOSRx register + address = baseAddress + (OFS_SD24BOSR0 + (param->converter * 0x08)); + + // Clearing previous settings for configuration + HWREG16(address) &= ~(OSR10 | OSR9 | OSR8 | OSR7 | OSR6 | OSR5 | OSR4 | + OSR3 | OSR2 | OSR1 | OSR0); + + HWREG16(address) |= param->oversampleRatio; +} +//***************************************************************************** +// +//! \brief Set SD24_B converter data format +//! +//! This function sets the converter format so that the resulting data can be +//! viewed in either binary or 2's complement. +//! +//! \param baseAddress is the base address of the SD24_B module. +//! \param converter selects the converter that will be configured. Check check +//! datasheet for available converters on device. +//! Valid values are: +//! - \b SD24_B_CONVERTER_0 +//! - \b SD24_B_CONVERTER_1 +//! - \b SD24_B_CONVERTER_2 +//! - \b SD24_B_CONVERTER_3 +//! - \b SD24_B_CONVERTER_4 +//! - \b SD24_B_CONVERTER_5 +//! - \b SD24_B_CONVERTER_6 +//! - \b SD24_B_CONVERTER_7 +//! \param dataFormat selects how the data format of the results +//! Valid values are: +//! - \b SD24_B_DATA_FORMAT_BINARY [Default] +//! - \b SD24_B_DATA_FORMAT_2COMPLEMENT +//! \n Modified bits are \b SD24DFx of \b SD24BCCTLx register. +//! +//! \return None +// +//***************************************************************************** +void SD24_B_setConverterDataFormat(uint16_t baseAddress, + uint8_t converter, + uint8_t dataFormat) +{ + + uint16_t address = baseAddress + (OFS_SD24BCCTL0_L + + (converter * 0x08)); + + assert( + (SD24_B_CONVERTER_0 == converter) || + (SD24_B_CONVERTER_1 == converter) || + (SD24_B_CONVERTER_2 == converter) || + (SD24_B_CONVERTER_3 == converter) || + (SD24_B_CONVERTER_4 == converter) || + (SD24_B_CONVERTER_5 == converter) || + (SD24_B_CONVERTER_6 == converter) || + (SD24_B_CONVERTER_7 == converter) + ); + + // Clearing previous settings for configuration + HWREG8(address) &= ~(SD24DF0 | SD24DF1); + + HWREG8(address) |= dataFormat; +} + +//***************************************************************************** +// +//! \brief Start Conversion Group +//! +//! This function starts all the converters that are associated with a group. +//! To set a converter to a group use the SD24_B_configureConverter() function. +//! +//! \param baseAddress is the base address of the SD24_B module. +//! \param group selects the group that will be started +//! Valid values are: +//! - \b SD24_B_GROUP0 +//! - \b SD24_B_GROUP1 +//! - \b SD24_B_GROUP2 +//! - \b SD24_B_GROUP3 +//! \n Modified bits are \b SD24DGRPxSC of \b SD24BCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void SD24_B_startGroupConversion(uint16_t baseAddress, + uint8_t group) +{ + switch (group) { + case SD24_B_GROUP0: + HWREG16(baseAddress + OFS_SD24BCTL1) |= SD24GRP0SC; break; + case SD24_B_GROUP1: + HWREG16(baseAddress + OFS_SD24BCTL1) |= SD24GRP1SC; break; + case SD24_B_GROUP2: + HWREG16(baseAddress + OFS_SD24BCTL1) |= SD24GRP2SC; break; + case SD24_B_GROUP3: + HWREG16(baseAddress + OFS_SD24BCTL1) |= SD24GRP3SC; break; + } +} + +//***************************************************************************** +// +//! \brief Stop Conversion Group +//! +//! This function stops all the converters that are associated with a group. To +//! set a converter to a group use the SD24_B_configureConverter() function. +//! +//! \param baseAddress is the base address of the SD24_B module. +//! \param group selects the group that will be stopped +//! Valid values are: +//! - \b SD24_B_GROUP0 +//! - \b SD24_B_GROUP1 +//! - \b SD24_B_GROUP2 +//! - \b SD24_B_GROUP3 +//! \n Modified bits are \b SD24DGRPxSC of \b SD24BCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void SD24_B_stopGroupConversion(uint16_t baseAddress, + uint8_t group) +{ + switch (group) { + case SD24_B_GROUP0: + HWREG16(baseAddress + OFS_SD24BCTL1) &= ~(SD24GRP0SC); break; + case SD24_B_GROUP1: + HWREG16(baseAddress + OFS_SD24BCTL1) &= ~(SD24GRP1SC); break; + case SD24_B_GROUP2: + HWREG16(baseAddress + OFS_SD24BCTL1) &= ~(SD24GRP2SC); break; + case SD24_B_GROUP3: + HWREG16(baseAddress + OFS_SD24BCTL1) &= ~(SD24GRP3SC); break; + } +} + +//***************************************************************************** +// +//! \brief Start Conversion for Converter +//! +//! This function starts a single converter. +//! +//! \param baseAddress is the base address of the SD24_B module. +//! \param converter selects the converter that will be started +//! Valid values are: +//! - \b SD24_B_CONVERTER_0 +//! - \b SD24_B_CONVERTER_1 +//! - \b SD24_B_CONVERTER_2 +//! - \b SD24_B_CONVERTER_3 +//! - \b SD24_B_CONVERTER_4 +//! - \b SD24_B_CONVERTER_5 +//! - \b SD24_B_CONVERTER_6 +//! - \b SD24_B_CONVERTER_7 +//! \n Modified bits are \b SD24SC of \b SD24BCCTLx register. +//! +//! \return None +// +//***************************************************************************** +void SD24_B_startConverterConversion(uint16_t baseAddress, + uint8_t converter) +{ + uint16_t address = baseAddress + (OFS_SD24BCCTL0 + (converter * 0x08)); + + assert( + (SD24_B_CONVERTER_0 == converter) || + (SD24_B_CONVERTER_1 == converter) || + (SD24_B_CONVERTER_2 == converter) || + (SD24_B_CONVERTER_3 == converter) || + (SD24_B_CONVERTER_4 == converter) || + (SD24_B_CONVERTER_5 == converter) || + (SD24_B_CONVERTER_6 == converter) || + (SD24_B_CONVERTER_7 == converter) + ); + // Clearing trigger generation select + HWREG16(address) &= ~(SD24SCS_7); + + // Setting SD24SC bit to start conversion + HWREG16(address) |= SD24SC; +} + +//***************************************************************************** +// +//! \brief Stop Conversion for Converter +//! +//! This function stops a single converter. +//! +//! \param baseAddress is the base address of the SD24_B module. +//! \param converter selects the converter that will be stopped +//! Valid values are: +//! - \b SD24_B_CONVERTER_0 +//! - \b SD24_B_CONVERTER_1 +//! - \b SD24_B_CONVERTER_2 +//! - \b SD24_B_CONVERTER_3 +//! - \b SD24_B_CONVERTER_4 +//! - \b SD24_B_CONVERTER_5 +//! - \b SD24_B_CONVERTER_6 +//! - \b SD24_B_CONVERTER_7 +//! \n Modified bits are \b SD24SC of \b SD24BCCTLx register. +//! +//! \return None +// +//***************************************************************************** +void SD24_B_stopConverterConversion(uint16_t baseAddress, + uint8_t converter) +{ + assert( + (SD24_B_CONVERTER_0 == converter) || + (SD24_B_CONVERTER_1 == converter) || + (SD24_B_CONVERTER_2 == converter) || + (SD24_B_CONVERTER_3 == converter) || + (SD24_B_CONVERTER_4 == converter) || + (SD24_B_CONVERTER_5 == converter) || + (SD24_B_CONVERTER_6 == converter) || + (SD24_B_CONVERTER_7 == converter) + ); + + uint16_t address = baseAddress + (OFS_SD24BCCTL0 + (converter * 0x08)); + + // Clearing trigger generation select + HWREG16(address) &= ~(SD24SCS_7); + + // Setting SD24SC bit to start conversion + HWREG16(address) &= ~(SD24SC); +} + +//***************************************************************************** +// +//! \brief Configures the converter that triggers a DMA transfer +//! +//! This function chooses which interrupt will trigger a DMA transfer. +//! +//! \param baseAddress is the base address of the SD24_B module. +//! \param interruptFlag selects the converter interrupt that triggers a DMA +//! transfer. +//! Valid values are: +//! - \b SD24_B_DMA_TRIGGER_IFG0 +//! - \b SD24_B_DMA_TRIGGER_IFG1 +//! - \b SD24_B_DMA_TRIGGER_IFG2 +//! - \b SD24_B_DMA_TRIGGER_IFG3 +//! - \b SD24_B_DMA_TRIGGER_IFG4 +//! - \b SD24_B_DMA_TRIGGER_IFG5 +//! - \b SD24_B_DMA_TRIGGER_IFG6 +//! - \b SD24_B_DMA_TRIGGER_IFG7 +//! - \b SD24_B_DMA_TRIGGER_TRGIFG +//! \n Modified bits are \b SD24DMAx of \b SD24BCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void SD24_B_configureDMATrigger(uint16_t baseAddress, + uint16_t interruptFlag) +{ + // Clearing previous settings + HWREG16(baseAddress + OFS_SD24BCTL1) &= ~(SD24DMA_3 | SD24DMA_2 | + SD24DMA_1 | SD24DMA_0); + + HWREG16(baseAddress + OFS_SD24BCTL1) |= interruptFlag; +} + +//***************************************************************************** +// +//! \brief Configures the delay for an interrupt to trigger +//! +//! This function configures the delay for the first interrupt service request +//! for the corresponding converter. This feature delays the interrupt request +//! for a completed conversion by up to four conversion cycles allowing the +//! digital filter to settle prior to generating an interrupt request. +//! +//! \param baseAddress is the base address of the SD24_B module. +//! \param converter selects the converter that will be stopped +//! Valid values are: +//! - \b SD24_B_CONVERTER_0 +//! - \b SD24_B_CONVERTER_1 +//! - \b SD24_B_CONVERTER_2 +//! - \b SD24_B_CONVERTER_3 +//! - \b SD24_B_CONVERTER_4 +//! - \b SD24_B_CONVERTER_5 +//! - \b SD24_B_CONVERTER_6 +//! - \b SD24_B_CONVERTER_7 +//! \param sampleDelay selects the delay for the interrupt +//! Valid values are: +//! - \b SD24_B_FOURTH_SAMPLE_INTERRUPT [Default] +//! - \b SD24_B_THIRD_SAMPLE_INTERRUPT +//! - \b SD24_B_SECOND_SAMPLE_INTERRUPT +//! - \b SD24_B_FIRST_SAMPLE_INTERRUPT +//! \n Modified bits are \b SD24INTDLYx of \b SD24INCTLx register. +//! +//! \return None +// +//***************************************************************************** +void SD24_B_setInterruptDelay(uint16_t baseAddress, + uint8_t converter, + uint8_t sampleDelay) +{ + assert( + (SD24_B_CONVERTER_0 == converter) || + (SD24_B_CONVERTER_1 == converter) || + (SD24_B_CONVERTER_2 == converter) || + (SD24_B_CONVERTER_3 == converter) || + (SD24_B_CONVERTER_4 == converter) || + (SD24_B_CONVERTER_5 == converter) || + (SD24_B_CONVERTER_6 == converter) || + (SD24_B_CONVERTER_7 == converter) + ); + + uint16_t address = baseAddress + (OFS_SD24BINCTL0 + (converter * 0x08)); + + // Clear previous settings + HWREG16(address) &= ~(SD24INTDLY_3); + + HWREG16(address) |= sampleDelay; + +} + +//***************************************************************************** +// +//! \brief Configures the oversampling ratio for a converter +//! +//! This function configures the oversampling ratio for a given converter. +//! +//! \param baseAddress is the base address of the SD24_B module. +//! \param converter selects the converter that will be configured +//! Valid values are: +//! - \b SD24_B_CONVERTER_0 +//! - \b SD24_B_CONVERTER_1 +//! - \b SD24_B_CONVERTER_2 +//! - \b SD24_B_CONVERTER_3 +//! - \b SD24_B_CONVERTER_4 +//! - \b SD24_B_CONVERTER_5 +//! - \b SD24_B_CONVERTER_6 +//! - \b SD24_B_CONVERTER_7 +//! \param oversampleRatio selects oversampling ratio for the converter +//! Valid values are: +//! - \b SD24_B_OVERSAMPLE_32 +//! - \b SD24_B_OVERSAMPLE_64 +//! - \b SD24_B_OVERSAMPLE_128 +//! - \b SD24_B_OVERSAMPLE_256 +//! - \b SD24_B_OVERSAMPLE_512 +//! - \b SD24_B_OVERSAMPLE_1024 +//! \n Modified bits are \b SD24OSRx of \b SD24BOSRx register. +//! +//! \return None +// +//***************************************************************************** +void SD24_B_setOversampling(uint16_t baseAddress, + uint8_t converter, + uint16_t oversampleRatio) +{ + uint16_t address = baseAddress + (OFS_SD24BOSR0 + (converter * 0x08)); + + assert( + (SD24_B_CONVERTER_0 == converter) || + (SD24_B_CONVERTER_1 == converter) || + (SD24_B_CONVERTER_2 == converter) || + (SD24_B_CONVERTER_3 == converter) || + (SD24_B_CONVERTER_4 == converter) || + (SD24_B_CONVERTER_5 == converter) || + (SD24_B_CONVERTER_6 == converter) || + (SD24_B_CONVERTER_7 == converter) + ); + // Clear previous settings + HWREG16(address) &= ~(OSR10 | OSR9 | OSR8 | OSR7 | OSR6 | OSR5 | OSR4 | + OSR3 | OSR2 | OSR1 | OSR0); + + HWREG16(address) |= oversampleRatio; +} + +//***************************************************************************** +// +//! \brief Configures the gain for the converter +//! +//! This function configures the gain for a single converter. +//! +//! \param baseAddress is the base address of the SD24_B module. +//! \param converter selects the converter that will be configured +//! Valid values are: +//! - \b SD24_B_CONVERTER_0 +//! - \b SD24_B_CONVERTER_1 +//! - \b SD24_B_CONVERTER_2 +//! - \b SD24_B_CONVERTER_3 +//! - \b SD24_B_CONVERTER_4 +//! - \b SD24_B_CONVERTER_5 +//! - \b SD24_B_CONVERTER_6 +//! - \b SD24_B_CONVERTER_7 +//! \param gain selects the gain for the converter +//! Valid values are: +//! - \b SD24_B_GAIN_1 [Default] +//! - \b SD24_B_GAIN_2 +//! - \b SD24_B_GAIN_4 +//! - \b SD24_B_GAIN_8 +//! - \b SD24_B_GAIN_16 +//! - \b SD24_B_GAIN_32 +//! - \b SD24_B_GAIN_64 +//! - \b SD24_B_GAIN_128 +//! \n Modified bits are \b SD24GAINx of \b SD24BINCTLx register. +//! +//! \return None +// +//***************************************************************************** +void SD24_B_setGain(uint16_t baseAddress, + uint8_t converter, + uint8_t gain) +{ + uint16_t address = baseAddress + (OFS_SD24BINCTL0 + (converter * 0x08)); + + assert( + (SD24_B_CONVERTER_0 == converter) || + (SD24_B_CONVERTER_1 == converter) || + (SD24_B_CONVERTER_2 == converter) || + (SD24_B_CONVERTER_3 == converter) || + (SD24_B_CONVERTER_4 == converter) || + (SD24_B_CONVERTER_5 == converter) || + (SD24_B_CONVERTER_6 == converter) || + (SD24_B_CONVERTER_7 == converter) + ); + + // Clear previous settings + HWREG16(address) &= ~(SD24GAIN_128); + + HWREG16(address) |= gain; +} + +//***************************************************************************** +// +//! \brief Returns the results for a converter +//! +//! This function gets the results from the SD24BMEMLx and SD24MEMHx registers +//! and concatenates them to form a long. The actual result is a maximum 24 +//! bits. +//! +//! \param baseAddress is the base address of the SD24_B module. +//! \param converter selects the converter who's results will be returned +//! Valid values are: +//! - \b SD24_B_CONVERTER_0 +//! - \b SD24_B_CONVERTER_1 +//! - \b SD24_B_CONVERTER_2 +//! - \b SD24_B_CONVERTER_3 +//! - \b SD24_B_CONVERTER_4 +//! - \b SD24_B_CONVERTER_5 +//! - \b SD24_B_CONVERTER_6 +//! - \b SD24_B_CONVERTER_7 +//! +//! \return Result of conversion +// +//***************************************************************************** +uint32_t SD24_B_getResults(uint16_t baseAddress, + uint8_t converter) +{ + assert( + (SD24_B_CONVERTER_0 == converter) || + (SD24_B_CONVERTER_1 == converter) || + (SD24_B_CONVERTER_2 == converter) || + (SD24_B_CONVERTER_3 == converter) || + (SD24_B_CONVERTER_4 == converter) || + (SD24_B_CONVERTER_5 == converter) || + (SD24_B_CONVERTER_6 == converter) || + (SD24_B_CONVERTER_7 == converter) + ); + + // Calculating address to low word + uint16_t address = baseAddress + (OFS_SD24BMEML0 + (converter * 0x04)); + + // Getting low word result + uint16_t lowResult = HWREG16(address); + + // Getting high word result and concatenate with low word + uint32_t result = (((uint32_t)HWREG16(address + 0x02) ) << 16) + lowResult; + + return result; +} + +//***************************************************************************** +// +//! \brief Returns the high word results for a converter +//! +//! This function gets the results from the SD24MEMHx register and returns it. +//! +//! \param baseAddress is the base address of the SD24_B module. +//! \param converter selects the converter who's results will be returned +//! Valid values are: +//! - \b SD24_B_CONVERTER_0 +//! - \b SD24_B_CONVERTER_1 +//! - \b SD24_B_CONVERTER_2 +//! - \b SD24_B_CONVERTER_3 +//! - \b SD24_B_CONVERTER_4 +//! - \b SD24_B_CONVERTER_5 +//! - \b SD24_B_CONVERTER_6 +//! - \b SD24_B_CONVERTER_7 +//! +//! \return Result of conversion +// +//***************************************************************************** +uint16_t SD24_B_getHighWordResults(uint16_t baseAddress, + uint8_t converter) +{ + assert( + (SD24_B_CONVERTER_0 == converter) || + (SD24_B_CONVERTER_1 == converter) || + (SD24_B_CONVERTER_2 == converter) || + (SD24_B_CONVERTER_3 == converter) || + (SD24_B_CONVERTER_4 == converter) || + (SD24_B_CONVERTER_5 == converter) || + (SD24_B_CONVERTER_6 == converter) || + (SD24_B_CONVERTER_7 == converter) + ); + + // Calculating address + uint16_t address = baseAddress + (OFS_SD24BMEMH0 + (converter * 0x04)); + + // Getting high word result + uint16_t result = HWREG16(address); + + return result; +} + +//***************************************************************************** +// +//! \brief Enables interrupts for the SD24_B Module +//! +//! This function enables interrupts for the SD24_B module. Does not clear +//! interrupt flags. +//! +//! \param baseAddress is the base address of the SD24_B module. +//! \param converter is the selected converter. +//! Valid values are: +//! - \b SD24_B_CONVERTER_0 +//! - \b SD24_B_CONVERTER_1 +//! - \b SD24_B_CONVERTER_2 +//! - \b SD24_B_CONVERTER_3 +//! - \b SD24_B_CONVERTER_4 +//! - \b SD24_B_CONVERTER_5 +//! - \b SD24_B_CONVERTER_6 +//! - \b SD24_B_CONVERTER_7 +//! \param mask is the bit mask of the converter interrupt sources to be +//! enabled. +//! Mask value is the logical OR of any of the following: +//! - \b SD24_B_CONVERTER_INTERRUPT +//! - \b SD24_B_CONVERTER_OVERFLOW_INTERRUPT +//! \n Modified bits are \b SD24OVIEx of \b SD24BIE register. +//! +//! \return None +// +//***************************************************************************** +void SD24_B_enableInterrupt(uint16_t baseAddress, + uint8_t converter, + uint16_t mask) +{ + assert( + (SD24_B_CONVERTER_0 == converter) || + (SD24_B_CONVERTER_1 == converter) || + (SD24_B_CONVERTER_2 == converter) || + (SD24_B_CONVERTER_3 == converter) || + (SD24_B_CONVERTER_4 == converter) || + (SD24_B_CONVERTER_5 == converter) || + (SD24_B_CONVERTER_6 == converter) || + (SD24_B_CONVERTER_7 == converter) + ); + + //Enable Interrupt + HWREG16(baseAddress + OFS_SD24BIE) |= (mask << converter); + +} + +//***************************************************************************** +// +//! \brief Disables interrupts for the SD24_B Module +//! +//! This function disables interrupts for the SD24_B module. +//! +//! \param baseAddress is the base address of the SD24_B module. +//! \param converter is the selected converter. +//! Valid values are: +//! - \b SD24_B_CONVERTER_0 +//! - \b SD24_B_CONVERTER_1 +//! - \b SD24_B_CONVERTER_2 +//! - \b SD24_B_CONVERTER_3 +//! - \b SD24_B_CONVERTER_4 +//! - \b SD24_B_CONVERTER_5 +//! - \b SD24_B_CONVERTER_6 +//! - \b SD24_B_CONVERTER_7 +//! \param mask is the bit mask of the converter interrupt sources to be +//! disabled. +//! Mask value is the logical OR of any of the following: +//! - \b SD24_B_CONVERTER_INTERRUPT +//! - \b SD24_B_CONVERTER_OVERFLOW_INTERRUPT +//! \n Modified bits are \b SD24OVIEx of \b SD24BIE register. +//! +//! Modified bits of \b SD24BIE register. +//! +//! \return None +// +//***************************************************************************** +void SD24_B_disableInterrupt(uint16_t baseAddress, + uint8_t converter, + uint16_t mask) +{ + assert( + (SD24_B_CONVERTER_0 == converter) || + (SD24_B_CONVERTER_1 == converter) || + (SD24_B_CONVERTER_2 == converter) || + (SD24_B_CONVERTER_3 == converter) || + (SD24_B_CONVERTER_4 == converter) || + (SD24_B_CONVERTER_5 == converter) || + (SD24_B_CONVERTER_6 == converter) || + (SD24_B_CONVERTER_7 == converter) + ); + + HWREG16(baseAddress + OFS_SD24BIE) &= ~(mask << converter); + +} + +//***************************************************************************** +// +//! \brief Clears interrupts for the SD24_B Module +//! +//! This function clears interrupt flags for the SD24_B module. +//! +//! \param baseAddress is the base address of the SD24_B module. +//! \param converter is the selected converter. +//! Valid values are: +//! - \b SD24_B_CONVERTER_0 +//! - \b SD24_B_CONVERTER_1 +//! - \b SD24_B_CONVERTER_2 +//! - \b SD24_B_CONVERTER_3 +//! - \b SD24_B_CONVERTER_4 +//! - \b SD24_B_CONVERTER_5 +//! - \b SD24_B_CONVERTER_6 +//! - \b SD24_B_CONVERTER_7 +//! \param mask is the bit mask of the converter interrupt sources to clear. +//! Mask value is the logical OR of any of the following: +//! - \b SD24_B_CONVERTER_INTERRUPT +//! - \b SD24_B_CONVERTER_OVERFLOW_INTERRUPT +//! \n Modified bits are \b SD24OVIFGx of \b SD24BIFG register. +//! +//! \return None +// +//***************************************************************************** +void SD24_B_clearInterrupt(uint16_t baseAddress, + uint8_t converter, + uint16_t mask) +{ + assert( + (SD24_B_CONVERTER_0 == converter) || + (SD24_B_CONVERTER_1 == converter) || + (SD24_B_CONVERTER_2 == converter) || + (SD24_B_CONVERTER_3 == converter) || + (SD24_B_CONVERTER_4 == converter) || + (SD24_B_CONVERTER_5 == converter) || + (SD24_B_CONVERTER_6 == converter) || + (SD24_B_CONVERTER_7 == converter) + ); + HWREG16(baseAddress + OFS_SD24BIFG) &= ~(mask << converter); +} + +//***************************************************************************** +// +//! \brief Returns the interrupt status for the SD24_B Module +//! +//! This function returns interrupt flag statuses for the SD24_B module. +//! +//! \param baseAddress is the base address of the SD24_B module. +//! \param converter is the selected converter. +//! Valid values are: +//! - \b SD24_B_CONVERTER_0 +//! - \b SD24_B_CONVERTER_1 +//! - \b SD24_B_CONVERTER_2 +//! - \b SD24_B_CONVERTER_3 +//! - \b SD24_B_CONVERTER_4 +//! - \b SD24_B_CONVERTER_5 +//! - \b SD24_B_CONVERTER_6 +//! - \b SD24_B_CONVERTER_7 +//! \param mask is the bit mask of the converter interrupt sources to return. +//! Mask value is the logical OR of any of the following: +//! - \b SD24_B_CONVERTER_INTERRUPT +//! - \b SD24_B_CONVERTER_OVERFLOW_INTERRUPT +//! +//! \return Logical OR of any of the following: +//! - \b SD24_B_CONVERTER_INTERRUPT +//! - \b SD24_B_CONVERTER_OVERFLOW_INTERRUPT +//! \n indicating the status of the masked interrupts +// +//***************************************************************************** +uint16_t SD24_B_getInterruptStatus(uint16_t baseAddress, + uint8_t converter, + uint16_t mask) +{ + assert( + (SD24_B_CONVERTER_0 == converter) || + (SD24_B_CONVERTER_1 == converter) || + (SD24_B_CONVERTER_2 == converter) || + (SD24_B_CONVERTER_3 == converter) || + (SD24_B_CONVERTER_4 == converter) || + (SD24_B_CONVERTER_5 == converter) || + (SD24_B_CONVERTER_6 == converter) || + (SD24_B_CONVERTER_7 == converter) + ); + + return HWREG16(baseAddress + OFS_SD24BIFG) & (mask << converter); +} + + +#endif +//***************************************************************************** +// +//! Close the doxygen group for sd24_b_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/sd24_b.h b/source/driverlib/MSP430F5xx_6xx/sd24_b.h new file mode 100644 index 0000000..311c3cc --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/sd24_b.h @@ -0,0 +1,440 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// sd24_b.h - Driver for the SD24_B Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_SD24_B_H__ +#define __MSP430WARE_SD24_B_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_SD24_B__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//****************************************************************************** +// +// The following is a struct that is passed to SD24_B_initializeParam() +// +//****************************************************************************** +typedef struct SD24_B_initializeParam { + uint16_t clockSourceSelect; + uint16_t clockPreDivider; + uint16_t clockDivider; + uint16_t referenceSelect; +} SD24_B_initializeParam; + +//****************************************************************************** +// +// The following is a struct that is passed to SD24_B_initConverterParam() +// +//****************************************************************************** +typedef struct SD24_B_initConverterParam { + uint8_t converter; + uint8_t alignment; + uint8_t startSelect; + uint8_t conversionMode; +} SD24_B_initConverterParam; + +//****************************************************************************** +// +// The following is a struct that is passed to SD24_B_initConverterAdvancedParam() +// +//****************************************************************************** +typedef struct SD24_B_initConverterAdvancedParam { + uint8_t converter; + uint8_t alignment; + uint8_t startSelect; + uint8_t conversionMode; + uint8_t dataFormat; + uint8_t sampleDelay; + uint16_t oversampleRatio; + uint8_t gain; +} SD24_B_initConverterAdvancedParam; +//***************************************************************************** +// +// The following are values that can be passed to the clockSourceSelect +// parameter for functions: SD24_B_init(). +// +//***************************************************************************** +#define SD24_B_CLOCKSOURCE_MCLK (SD24SSEL__MCLK) +#define SD24_B_CLOCKSOURCE_SMCLK (SD24SSEL__SMCLK) +#define SD24_B_CLOCKSOURCE_ACLK (SD24SSEL__ACLK) +#define SD24_B_CLOCKSOURCE_SD24CLK (SD24SSEL__SD24CLK) + +//***************************************************************************** +// +// The following are values that can be passed to the referenceSelect parameter +// for functions: SD24_B_init(). +// +//***************************************************************************** +#define SD24_B_REF_EXTERNAL (0x00) +#define SD24_B_REF_INTERNAL (SD24REFS) + +//***************************************************************************** +// +// The following are values that can be passed to the clockPreDivider parameter +// for functions: SD24_B_init(). +// +//***************************************************************************** +#define SD24_B_PRECLOCKDIVIDER_1 (SD24PDIV_0) +#define SD24_B_PRECLOCKDIVIDER_2 (SD24PDIV_1) +#define SD24_B_PRECLOCKDIVIDER_4 (SD24PDIV_2) +#define SD24_B_PRECLOCKDIVIDER_8 (SD24PDIV_3) +#define SD24_B_PRECLOCKDIVIDER_16 (SD24PDIV_4) +#define SD24_B_PRECLOCKDIVIDER_32 (SD24PDIV_5) +#define SD24_B_PRECLOCKDIVIDER_64 (SD24PDIV_6) +#define SD24_B_PRECLOCKDIVIDER_128 (SD24PDIV_7) + +//***************************************************************************** +// +// The following are values that can be passed to the clockDivider parameter +// for functions: SD24_B_init(). +// +//***************************************************************************** +#define SD24_B_CLOCKDIVIDER_1 (0x00) +#define SD24_B_CLOCKDIVIDER_2 (SD24DIV0) +#define SD24_B_CLOCKDIVIDER_3 (SD24DIV1) +#define SD24_B_CLOCKDIVIDER_4 (SD24DIV1 | SD24DIV0) +#define SD24_B_CLOCKDIVIDER_5 (SD24DIV2) +#define SD24_B_CLOCKDIVIDER_6 (SD24DIV2 | SD24DIV0) +#define SD24_B_CLOCKDIVIDER_7 (SD24DIV2 | SD24DIV1) +#define SD24_B_CLOCKDIVIDER_8 (SD24DIV2 | SD24DIV1 | SD24DIV0) +#define SD24_B_CLOCKDIVIDER_9 (SD24DIV3) +#define SD24_B_CLOCKDIVIDER_10 (SD24DIV3 | SD24DIV0) +#define SD24_B_CLOCKDIVIDER_11 (SD24DIV3 | SD24DIV1) +#define SD24_B_CLOCKDIVIDER_12 (SD24DIV3 | SD24DIV1 | SD24DIV0) +#define SD24_B_CLOCKDIVIDER_13 (SD24DIV3 | SD24DIV2) +#define SD24_B_CLOCKDIVIDER_14 (SD24DIV3 | SD24DIV2 | SD24DIV0) +#define SD24_B_CLOCKDIVIDER_15 (SD24DIV3 | SD24DIV2 | SD24DIV1) +#define SD24_B_CLOCKDIVIDER_16 (SD24DIV3 | SD24DIV2 | SD24DIV1 | SD24DIV0) +#define SD24_B_CLOCKDIVIDER_17 (SD24DIV4) +#define SD24_B_CLOCKDIVIDER_18 (SD24DIV4 | SD24DIV0) +#define SD24_B_CLOCKDIVIDER_19 (SD24DIV4 | SD24DIV1) +#define SD24_B_CLOCKDIVIDER_20 (SD24DIV4 | SD24DIV1 | SD24DIV0) +#define SD24_B_CLOCKDIVIDER_21 (SD24DIV4 | SD24DIV2) +#define SD24_B_CLOCKDIVIDER_22 (SD24DIV4 | SD24DIV2 | SD24DIV0) +#define SD24_B_CLOCKDIVIDER_23 (SD24DIV4 | SD24DIV2 | SD24DIV1) +#define SD24_B_CLOCKDIVIDER_24 (SD24DIV4 | SD24DIV2 | SD24DIV1 | SD24DIV0) +#define SD24_B_CLOCKDIVIDER_25 (SD24DIV4 | SD24DIV3) +#define SD24_B_CLOCKDIVIDER_26 (SD24DIV4 | SD24DIV3 | SD24DIV0) +#define SD24_B_CLOCKDIVIDER_27 (SD24DIV4 | SD24DIV3 | SD24DIV1) +#define SD24_B_CLOCKDIVIDER_28 (SD24DIV4 | SD24DIV3 | SD24DIV1 | SD24DIV0) +#define SD24_B_CLOCKDIVIDER_29 (SD24DIV4 | SD24DIV3 | SD24DIV2) +#define SD24_B_CLOCKDIVIDER_30 (SD24DIV4 | SD24DIV3 | SD24DIV2 | SD24DIV0) +#define SD24_B_CLOCKDIVIDER_31 (SD24DIV4 | SD24DIV3 | SD24DIV2 | SD24DIV1) +#define SD24_B_CLOCKDIVIDER_32 \ + (SD24DIV4 | SD24DIV3 | SD24DIV2 | SD24DIV1 | SD24DIV0) + +//***************************************************************************** +// +// The following are values that can be passed to the conversionMode parameter +// for functions: SD24_B_configureConverter(), and +// SD24_B_configureConverterAdvanced(). +// +//***************************************************************************** +#define SD24_B_CONTINUOUS_MODE (0x00) +#define SD24_B_SINGLE_MODE (SD24SNGL_H) + +//***************************************************************************** +// +// The following are values that can be passed to the converter parameter for +// functions: SD24_B_configureConverter(), SD24_B_configureConverterAdvanced(), +// SD24_B_setConverterDataFormat(), SD24_B_startConverterConversion(), +// SD24_B_stopConverterConversion(), SD24_B_setInterruptDelay(), +// SD24_B_setOversampling(), SD24_B_setGain(), SD24_B_getResults(), +// SD24_B_getHighWordResults(), SD24_B_enableInterrupt(), +// SD24_B_disableInterrupt(), SD24_B_clearInterrupt(), and +// SD24_B_getInterruptStatus(). +// +//***************************************************************************** +#define SD24_B_CONVERTER_0 0 +#define SD24_B_CONVERTER_1 1 +#define SD24_B_CONVERTER_2 2 +#define SD24_B_CONVERTER_3 3 +#define SD24_B_CONVERTER_4 4 +#define SD24_B_CONVERTER_5 5 +#define SD24_B_CONVERTER_6 6 +#define SD24_B_CONVERTER_7 7 + +//***************************************************************************** +// +// The following are values that can be passed to the alignment parameter for +// functions: SD24_B_configureConverter(), and +// SD24_B_configureConverterAdvanced(). +// +//***************************************************************************** +#define SD24_B_ALIGN_RIGHT (0x00) +#define SD24_B_ALIGN_LEFT (SD24ALGN) + +//***************************************************************************** +// +// The following are values that can be passed to the startSelect parameter for +// functions: SD24_B_configureConverter(), and +// SD24_B_configureConverterAdvanced(). +// +//***************************************************************************** +#define SD24_B_CONVERSION_SELECT_SD24SC (SD24SCS__SD24SC) +#define SD24_B_CONVERSION_SELECT_EXT1 (SD24SCS__EXT1) +#define SD24_B_CONVERSION_SELECT_EXT2 (SD24SCS__EXT2) +#define SD24_B_CONVERSION_SELECT_EXT3 (SD24SCS__EXT3) +#define SD24_B_CONVERSION_SELECT_GROUP0 (SD24SCS__GROUP0) +#define SD24_B_CONVERSION_SELECT_GROUP1 (SD24SCS__GROUP1) +#define SD24_B_CONVERSION_SELECT_GROUP2 (SD24SCS__GROUP2) +#define SD24_B_CONVERSION_SELECT_GROUP3 (SD24SCS__GROUP3) + +//***************************************************************************** +// +// The following are values that can be passed to the oversampleRatio parameter +// for functions: SD24_B_configureConverterAdvanced(), and +// SD24_B_setOversampling(). +// +//***************************************************************************** +#define SD24_B_OVERSAMPLE_32 (OSR__32) +#define SD24_B_OVERSAMPLE_64 (OSR__64) +#define SD24_B_OVERSAMPLE_128 (OSR__128) +#define SD24_B_OVERSAMPLE_256 (OSR__256) +#define SD24_B_OVERSAMPLE_512 (OSR__512) +#define SD24_B_OVERSAMPLE_1024 (OSR__1024) + +//***************************************************************************** +// +// The following are values that can be passed to the dataFormat parameter for +// functions: SD24_B_configureConverterAdvanced(), and +// SD24_B_setConverterDataFormat(). +// +//***************************************************************************** +#define SD24_B_DATA_FORMAT_BINARY (SD24DF_0) +#define SD24_B_DATA_FORMAT_2COMPLEMENT (SD24DF_1) + +//***************************************************************************** +// +// The following are values that can be passed to the gain parameter for +// functions: SD24_B_configureConverterAdvanced(), and SD24_B_setGain(). +// +//***************************************************************************** +#define SD24_B_GAIN_1 (SD24GAIN_1) +#define SD24_B_GAIN_2 (SD24GAIN_2) +#define SD24_B_GAIN_4 (SD24GAIN_4) +#define SD24_B_GAIN_8 (SD24GAIN_8) +#define SD24_B_GAIN_16 (SD24GAIN_16) +#define SD24_B_GAIN_32 (SD24GAIN_32) +#define SD24_B_GAIN_64 (SD24GAIN_64) +#define SD24_B_GAIN_128 (SD24GAIN_128) + +//***************************************************************************** +// +// The following are values that can be passed to the sampleDelay parameter for +// functions: SD24_B_configureConverterAdvanced(), and +// SD24_B_setInterruptDelay(). +// +//***************************************************************************** +#define SD24_B_FOURTH_SAMPLE_INTERRUPT (SD24INTDLY_0) +#define SD24_B_THIRD_SAMPLE_INTERRUPT (SD24INTDLY_1) +#define SD24_B_SECOND_SAMPLE_INTERRUPT (SD24INTDLY_2) +#define SD24_B_FIRST_SAMPLE_INTERRUPT (SD24INTDLY_3) + +//***************************************************************************** +// +// The following are values that can be passed to the group parameter for +// functions: SD24_B_startGroupConversion(), and SD24_B_stopGroupConversion(). +// +//***************************************************************************** +#define SD24_B_GROUP0 0 +#define SD24_B_GROUP1 1 +#define SD24_B_GROUP2 2 +#define SD24_B_GROUP3 3 + +//***************************************************************************** +// +// The following are values that can be passed to the interruptFlag parameter +// for functions: SD24_B_configureDMATrigger(). +// +//***************************************************************************** +#define SD24_B_DMA_TRIGGER_IFG0 (SD24DMA_0) +#define SD24_B_DMA_TRIGGER_IFG1 (SD24DMA_1) +#define SD24_B_DMA_TRIGGER_IFG2 (SD24DMA_2) +#define SD24_B_DMA_TRIGGER_IFG3 (SD24DMA_3) +#define SD24_B_DMA_TRIGGER_IFG4 (SD24DMA_4) +#define SD24_B_DMA_TRIGGER_IFG5 (SD24DMA_5) +#define SD24_B_DMA_TRIGGER_IFG6 (SD24DMA_6) +#define SD24_B_DMA_TRIGGER_IFG7 (SD24DMA_7) +#define SD24_B_DMA_TRIGGER_TRGIFG (SD24DMA_8) + +//***************************************************************************** +// +// The following are values that can be passed to the mask parameter for +// functions: SD24_B_enableInterrupt(), SD24_B_disableInterrupt(), +// SD24_B_clearInterrupt(), and SD24_B_getInterruptStatus() as well as returned +// by the SD24_B_getInterruptStatus() function. +// +//***************************************************************************** +#define SD24_B_CONVERTER_INTERRUPT SD24IE0 +#define SD24_B_CONVERTER_OVERFLOW_INTERRUPT SD24OVIE0 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SD24_B_initialize(uint16_t baseAddress, + SD24_B_initializeParam *param); + +extern void SD24_B_initConverter(uint16_t baseAddress, + SD24_B_initConverterParam *param); + +extern void SD24_B_initConverterAdvanced(uint16_t baseAddress, + SD24_B_initConverterAdvancedParam *param); + +extern void SD24_B_setConverterDataFormat(uint16_t baseAddress, + uint8_t converter, + uint8_t dataFormat); + +extern void SD24_B_startGroupConversion(uint16_t baseAddress, + uint8_t group); + +extern void SD24_B_stopGroupConversion(uint16_t baseAddress, + uint8_t group); + +extern void SD24_B_startConverterConversion(uint16_t baseAddress, + uint8_t converter); + +extern void SD24_B_stopConverterConversion(uint16_t baseAddress, + uint8_t converter); + +extern void SD24_B_configureDMATrigger(uint16_t baseAddress, + uint16_t interruptFlag); + +extern void SD24_B_setInterruptDelay(uint16_t baseAddress, + uint8_t converter, + uint8_t sampleDelay); + +extern void SD24_B_setOversampling(uint16_t baseAddress, + uint8_t converter, + uint16_t oversampleRatio); + +extern void SD24_B_setGain(uint16_t baseAddress, + uint8_t converter, + uint8_t gain); + +extern uint32_t SD24_B_getResults(uint16_t baseAddress, + uint8_t converter); + +extern uint16_t SD24_B_getHighWordResults(uint16_t baseAddress, + uint8_t converter); + +extern void SD24_B_enableInterrupt(uint16_t baseAddress, + uint8_t converter, + uint16_t mask); + +extern void SD24_B_disableInterrupt(uint16_t baseAddress, + uint8_t converter, + uint16_t mask); + +extern void SD24_B_clearInterrupt(uint16_t baseAddress, + uint8_t converter, + uint16_t mask); + +extern uint16_t SD24_B_getInterruptStatus(uint16_t baseAddress, + uint8_t converter, + uint16_t mask); + +//***************************************************************************** +// +// The following values are deprecated values. Please refer to the documenation +// for the correct values to use. +// +//***************************************************************************** +#define SD24_CONVERTER_INTERRUPT SD24_B_CONVERTER_INTERRUPT +#define SD24_CONVERTER_OVERFLOW_INTERRUPT SD24_B_CONVERTER_OVERFLOW_INTERRUPT +#define SD24_DATA_FORMAT_BINARY SD24_B_DATA_FORMAT_BINARY +#define SD24_DATA_FORMAT_2COMPLEMENT SD24_B_DATA_FORMAT_2COMPLEMENT +#define SD24_DMA_TRIGGER_IFG0 SD24_B_DMA_TRIGGER_IFG0 +#define SD24_DMA_TRIGGER_IFG1 SD24_B_DMA_TRIGGER_IFG1 +#define SD24_DMA_TRIGGER_IFG2 SD24_B_DMA_TRIGGER_IFG2 +#define SD24_DMA_TRIGGER_IFG3 SD24_B_DMA_TRIGGER_IFG3 +#define SD24_DMA_TRIGGER_IFG4 SD24_B_DMA_TRIGGER_IFG4 +#define SD24_DMA_TRIGGER_IFG5 SD24_B_DMA_TRIGGER_IFG5 +#define SD24_DMA_TRIGGER_IFG6 SD24_B_DMA_TRIGGER_IFG6 +#define SD24_DMA_TRIGGER_IFG7 SD24_B_DMA_TRIGGER_IFG7 +#define SD24_DMA_TRIGGER_TRGIFG SD24_B_DMA_TRIGGER_TRGIFG + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +extern void SD24_B_init(uint16_t baseAddress, + uint16_t clockSourceSelect, + uint16_t clockPreDivider, + uint16_t clockDivider, + uint16_t referenceSelect); + +extern void SD24_B_configureConverter(uint16_t baseAddress, + uint8_t converter, + uint8_t alignment, + uint8_t startSelect, + uint8_t conversionMode); + +extern void SD24_B_configureConverterAdvanced(uint16_t baseAddress, + uint8_t converter, + uint8_t alignment, + uint8_t startSelect, + uint8_t conversionMode, + uint8_t dataFormat, + uint8_t sampleDelay, + uint16_t oversampleRatio, + uint8_t gain); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_SD24_B_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/sfr.c b/source/driverlib/MSP430F5xx_6xx/sfr.c new file mode 100644 index 0000000..b17467f --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/sfr.c @@ -0,0 +1,273 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// sfr.c - Driver for the sfr Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup sfr_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifndef DRIVERLIB_LEGACY_MODE + +#ifdef __MSP430_HAS_SFR__ +#include "sfr.h" + +#include + +//***************************************************************************** +// +//! \brief Enables selected SFR interrupt sources. +//! +//! This function enables the selected SFR interrupt sources. Only the sources +//! that are enabled can be reflected to the processor interrupt; disabled +//! sources have no effect on the processor. +//! +//! \param interruptMask is the bit mask of interrupts that will be enabled. +//! Mask value is the logical OR of any of the following: +//! - \b SFR_JTAG_OUTBOX_INTERRUPT - JTAG outbox interrupt enable +//! - \b SFR_JTAG_INBOX_INTERRUPT - JTAG inbox interrupt enable +//! - \b SFR_NMI_PIN_INTERRUPT - NMI pin interrupt enable, if NMI +//! function is chosen +//! - \b SFR_VACANT_MEMORY_ACCESS_INTERRUPT - Vacant memory access +//! interrupt enable +//! - \b SFR_OSCILLATOR_FAULT_INTERRUPT - Oscillator fault interrupt +//! enable +//! - \b SFR_WATCHDOG_INTERVAL_TIMER_INTERRUPT - Watchdog interval timer +//! interrupt enable +//! - \b SFR_FLASH_CONTROLLER_ACCESS_VIOLATION_INTERRUPT - Flash +//! controller access violation interrupt enable +//! +//! \return None +// +//***************************************************************************** +void SFR_enableInterrupt(uint8_t interruptMask) +{ + HWREG8(SFR_BASE + OFS_SFRIE1_L) |= interruptMask; +} + +//***************************************************************************** +// +//! \brief Disables selected SFR interrupt sources. +//! +//! This function disables the selected SFR interrupt sources. Only the sources +//! that are enabled can be reflected to the processor interrupt; disabled +//! sources have no effect on the processor. +//! +//! \param interruptMask is the bit mask of interrupts that will be disabled. +//! Mask value is the logical OR of any of the following: +//! - \b SFR_JTAG_OUTBOX_INTERRUPT - JTAG outbox interrupt enable +//! - \b SFR_JTAG_INBOX_INTERRUPT - JTAG inbox interrupt enable +//! - \b SFR_NMI_PIN_INTERRUPT - NMI pin interrupt enable, if NMI +//! function is chosen +//! - \b SFR_VACANT_MEMORY_ACCESS_INTERRUPT - Vacant memory access +//! interrupt enable +//! - \b SFR_OSCILLATOR_FAULT_INTERRUPT - Oscillator fault interrupt +//! enable +//! - \b SFR_WATCHDOG_INTERVAL_TIMER_INTERRUPT - Watchdog interval timer +//! interrupt enable +//! - \b SFR_FLASH_CONTROLLER_ACCESS_VIOLATION_INTERRUPT - Flash +//! controller access violation interrupt enable +//! +//! \return None +// +//***************************************************************************** +void SFR_disableInterrupt(uint8_t interruptMask) +{ + HWREG8(SFR_BASE + OFS_SFRIE1_L) &= ~(interruptMask); +} + +//***************************************************************************** +// +//! \brief Returns the status of the selected SFR interrupt flags. +//! +//! This function returns the status of the selected SFR interrupt flags in a +//! bit mask format matching that passed into the interruptFlagMask parameter. +//! +//! \param interruptFlagMask is the bit mask of interrupt flags that the status +//! of should be returned. +//! Mask value is the logical OR of any of the following: +//! - \b SFR_JTAG_OUTBOX_INTERRUPT - JTAG outbox interrupt enable +//! - \b SFR_JTAG_INBOX_INTERRUPT - JTAG inbox interrupt enable +//! - \b SFR_NMI_PIN_INTERRUPT - NMI pin interrupt enable, if NMI +//! function is chosen +//! - \b SFR_VACANT_MEMORY_ACCESS_INTERRUPT - Vacant memory access +//! interrupt enable +//! - \b SFR_OSCILLATOR_FAULT_INTERRUPT - Oscillator fault interrupt +//! enable +//! - \b SFR_WATCHDOG_INTERVAL_TIMER_INTERRUPT - Watchdog interval timer +//! interrupt enable +//! - \b SFR_FLASH_CONTROLLER_ACCESS_VIOLATION_INTERRUPT - Flash +//! controller access violation interrupt enable +//! +//! \return Logical OR of any of the following: +//! - \b SFR_JTAG_OUTBOX_INTERRUPT JTAG outbox interrupt enable +//! - \b SFR_JTAG_INBOX_INTERRUPT JTAG inbox interrupt enable +//! - \b SFR_NMI_PIN_INTERRUPT NMI pin interrupt enable, if NMI +//! function is chosen +//! - \b SFR_VACANT_MEMORY_ACCESS_INTERRUPT Vacant memory access +//! interrupt enable +//! - \b SFR_OSCILLATOR_FAULT_INTERRUPT Oscillator fault interrupt +//! enable +//! - \b SFR_WATCHDOG_INTERVAL_TIMER_INTERRUPT Watchdog interval timer +//! interrupt enable +//! - \b SFR_FLASH_CONTROLLER_ACCESS_VIOLATION_INTERRUPT Flash +//! controller access violation interrupt enable +//! \n indicating the status of the masked interrupts +// +//***************************************************************************** +uint8_t SFR_getInterruptStatus(uint8_t interruptFlagMask) +{ + return HWREG8(SFR_BASE + OFS_SFRIFG1_L) & interruptFlagMask; +} + +//***************************************************************************** +// +//! \brief Clears the selected SFR interrupt flags. +//! +//! This function clears the status of the selected SFR interrupt flags. +//! +//! \param interruptFlagMask is the bit mask of interrupt flags that should be +//! cleared +//! Mask value is the logical OR of any of the following: +//! - \b SFR_JTAG_OUTBOX_INTERRUPT - JTAG outbox interrupt enable +//! - \b SFR_JTAG_INBOX_INTERRUPT - JTAG inbox interrupt enable +//! - \b SFR_NMI_PIN_INTERRUPT - NMI pin interrupt enable, if NMI +//! function is chosen +//! - \b SFR_VACANT_MEMORY_ACCESS_INTERRUPT - Vacant memory access +//! interrupt enable +//! - \b SFR_OSCILLATOR_FAULT_INTERRUPT - Oscillator fault interrupt +//! enable +//! - \b SFR_WATCHDOG_INTERVAL_TIMER_INTERRUPT - Watchdog interval timer +//! interrupt enable +//! - \b SFR_FLASH_CONTROLLER_ACCESS_VIOLATION_INTERRUPT - Flash +//! controller access violation interrupt enable +//! +//! \return None +// +//***************************************************************************** +void SFR_clearInterrupt(uint8_t interruptFlagMask) +{ + HWREG8(SFR_BASE + OFS_SFRIFG1_L) &= ~(interruptFlagMask); +} + +//***************************************************************************** +// +//! \brief Sets the pull-up/down resistor on the ~RST/NMI pin. +//! +//! This function sets the pull-up/down resistors on the ~RST/NMI pin to the +//! settings from the pullResistorSetup parameter. +//! +//! \param pullResistorSetup is the selection of how the pull-up/down resistor +//! on the ~RST/NMI pin should be setup or disabled. +//! Valid values are: +//! - \b SFR_RESISTORDISABLE +//! - \b SFR_RESISTORENABLE_PULLUP [Default] +//! - \b SFR_RESISTORENABLE_PULLDOWN +//! \n Modified bits are \b SYSRSTUP of \b SFRRPCR register. +//! +//! \return None +// +//***************************************************************************** +void SFR_setResetPinPullResistor(uint16_t pullResistorSetup) +{ + HWREG8(SFR_BASE + OFS_SFRRPCR_L) &= ~(SYSRSTRE + SYSRSTUP); + HWREG8(SFR_BASE + OFS_SFRRPCR_L) |= pullResistorSetup; +} + +//***************************************************************************** +// +//! \brief Sets the edge direction that will assert an NMI from a signal on the +//! ~RST/NMI pin if NMI function is active. +//! +//! This function sets the edge direction that will assert an NMI from a signal +//! on the ~RST/NMI pin if the NMI function is active. To activate the NMI +//! function of the ~RST/NMI use the SFR_setResetNMIPinFunction() passing +//! SFR_RESETPINFUNC_NMI into the resetPinFunction parameter. +//! +//! \param edgeDirection is the direction that the signal on the ~RST/NMI pin +//! should go to signal an interrupt, if enabled. +//! Valid values are: +//! - \b SFR_NMI_RISINGEDGE [Default] +//! - \b SFR_NMI_FALLINGEDGE +//! \n Modified bits are \b SYSNMIIES of \b SFRRPCR register. +//! +//! \return None +// +//***************************************************************************** +void SFR_setNMIEdge(uint16_t edgeDirection) +{ + HWREG8(SFR_BASE + OFS_SFRRPCR_L) &= ~(SYSNMIIES); + HWREG8(SFR_BASE + OFS_SFRRPCR_L) |= edgeDirection; +} + +//***************************************************************************** +// +//! \brief Sets the function of the ~RST/NMI pin. +//! +//! This function sets the functionality of the ~RST/NMI pin, whether in reset +//! mode which will assert a reset if a low signal is observed on that pin, or +//! an NMI which will assert an interrupt from an edge of the signal dependent +//! on the setting of the edgeDirection parameter in SFR_setNMIEdge(). +//! +//! \param resetPinFunction is the function that the ~RST/NMI pin should take +//! on. +//! Valid values are: +//! - \b SFR_RESETPINFUNC_RESET [Default] +//! - \b SFR_RESETPINFUNC_NMI +//! \n Modified bits are \b SYSNMI of \b SFRRPCR register. +//! +//! \return None +// +//***************************************************************************** +void SFR_setResetNMIPinFunction(uint8_t resetPinFunction) +{ + HWREG8(SFR_BASE + OFS_SFRRPCR_L) &= ~(SYSNMI); + HWREG8(SFR_BASE + OFS_SFRRPCR_L) |= resetPinFunction; +} + +#endif +#endif +//***************************************************************************** +// +//! Close the doxygen group for sfr_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/sfr.h b/source/driverlib/MSP430F5xx_6xx/sfr.h new file mode 100644 index 0000000..8ef4b94 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/sfr.h @@ -0,0 +1,130 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// sfr.h - Driver for the SFR Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_SFR_H__ +#define __MSP430WARE_SFR_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_SFR__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the interruptMask parameter +// for functions: SFR_enableInterrupt(), and SFR_disableInterrupt(); the +// interruptFlagMask parameter for functions: SFR_getInterruptStatus(), and +// SFR_clearInterrupt() as well as returned by the SFR_getInterruptStatus() +// function. +// +//***************************************************************************** +#define SFR_JTAG_OUTBOX_INTERRUPT JMBOUTIE +#define SFR_JTAG_INBOX_INTERRUPT JMBINIE +#define SFR_NMI_PIN_INTERRUPT NMIIE +#define SFR_VACANT_MEMORY_ACCESS_INTERRUPT VMAIE +#define SFR_OSCILLATOR_FAULT_INTERRUPT OFIE +#define SFR_WATCHDOG_INTERVAL_TIMER_INTERRUPT WDTIE +#define SFR_FLASH_CONTROLLER_ACCESS_VIOLATION_INTERRUPT ACCVIE + +//***************************************************************************** +// +// The following are values that can be passed to the pullResistorSetup +// parameter for functions: SFR_setResetPinPullResistor(). +// +//***************************************************************************** +#define SFR_RESISTORDISABLE (!(SYSRSTRE + SYSRSTUP)) +#define SFR_RESISTORENABLE_PULLUP (SYSRSTRE + SYSRSTUP) +#define SFR_RESISTORENABLE_PULLDOWN (SYSRSTRE) + +//***************************************************************************** +// +// The following are values that can be passed to the edgeDirection parameter +// for functions: SFR_setNMIEdge(). +// +//***************************************************************************** +#define SFR_NMI_RISINGEDGE (!(SYSNMIIES)) +#define SFR_NMI_FALLINGEDGE (SYSNMIIES) + +//***************************************************************************** +// +// The following are values that can be passed to the resetPinFunction +// parameter for functions: SFR_setResetNMIPinFunction(). +// +//***************************************************************************** +#define SFR_RESETPINFUNC_RESET (!(SYSNMI)) +#define SFR_RESETPINFUNC_NMI (SYSNMI) + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SFR_enableInterrupt(uint8_t interruptMask); + +extern void SFR_disableInterrupt(uint8_t interruptMask); + +extern uint8_t SFR_getInterruptStatus(uint8_t interruptFlagMask); + +extern void SFR_clearInterrupt(uint8_t interruptFlagMask); + +extern void SFR_setResetPinPullResistor(uint16_t pullResistorSetup); + +extern void SFR_setNMIEdge(uint16_t edgeDirection); + +extern void SFR_setResetNMIPinFunction(uint8_t resetPinFunction); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_SFR_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/sys.c b/source/driverlib/MSP430F5xx_6xx/sys.c new file mode 100644 index 0000000..34986fd --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/sys.c @@ -0,0 +1,441 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// sys.c - Driver for the sys Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup sys_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifndef DRIVERLIB_LEGACY_MODE + +#ifdef __MSP430_HAS_SYS__ +#include "sys.h" + +#include + +//***************************************************************************** +// +//! \brief Sets the JTAG pins to be exclusively for JTAG until a BOR occurs. +//! +//! This function sets the JTAG pins to be exclusively used for the JTAG, and +//! not to be shared with the GPIO pins. This setting can only be cleared when +//! a BOR occurs. +//! +//! +//! \return None +// +//***************************************************************************** +void SYS_enableDedicatedJTAGPins(void) +{ + HWREG8(SYS_BASE + OFS_SYSCTL_L) |= SYSJTAGPIN; +} + +//***************************************************************************** +// +//! \brief Returns the indication of a BSL entry sequence from the Spy-Bi-Wire. +//! +//! This function returns the indication of a BSL entry sequence from the Spy- +//! Bi-Wire. +//! +//! +//! \return One of the following: +//! - \b SYS_BSLENTRY_INDICATED +//! - \b SYS_BSLENTRY_NOTINDICATED +//! \n indicating if a BSL entry sequence was detected +// +//***************************************************************************** +uint8_t SYS_getBSLEntryIndication(void) +{ + if ( HWREG8(SYS_BASE + OFS_SYSCTL_L) & SYSBSLIND) + return SYS_BSLENTRY_INDICATED; + else + return SYS_BSLENTRY_NOTINDICATED; +} + +//***************************************************************************** +// +//! \brief Enables PMM Access Protection. +//! +//! This function enables the PMM Access Protection, which will lock any +//! changes on the PMM control registers until a BOR occurs. +//! +//! +//! \return None +// +//***************************************************************************** +void SYS_enablePMMAccessProtect(void) +{ + HWREG8(SYS_BASE + OFS_SYSCTL_L) |= SYSPMMPE; +} + +//***************************************************************************** +// +//! \brief Enables RAM-based Interrupt Vectors. +//! +//! This function enables RAM-base Interrupt Vectors, which means that +//! interrupt vectors are generated with the end address at the top of RAM, +//! instead of the top of the lower 64kB of flash. +//! +//! +//! \return None +// +//***************************************************************************** +void SYS_enableRAMBasedInterruptVectors(void) +{ + HWREG8(SYS_BASE + OFS_SYSCTL_L) |= SYSRIVECT; +} + +//***************************************************************************** +// +//! \brief Disables RAM-based Interrupt Vectors. +//! +//! This function disables the interrupt vectors from being generated at the +//! top of the RAM. +//! +//! +//! \return None +// +//***************************************************************************** +void SYS_disableRAMBasedInterruptVectors(void) +{ + HWREG8(SYS_BASE + OFS_SYSCTL_L) &= ~(SYSRIVECT); +} + +//***************************************************************************** +// +//! \brief Enables BSL memory protection. +//! +//! This function enables protection on the BSL memory, which prevents any +//! reading, programming, or erasing of the BSL memory. +//! +//! +//! \return None +// +//***************************************************************************** +void SYS_enableBSLProtect(void) +{ + HWREG16(SYS_BASE + OFS_SYSBSLC) |= SYSBSLPE; +} + +//***************************************************************************** +// +//! \brief Disables BSL memory protection. +//! +//! This function disables protection on the BSL memory. +//! +//! +//! \return None +// +//***************************************************************************** +void SYS_disableBSLProtect(void) +{ + HWREG16(SYS_BASE + OFS_SYSBSLC) &= ~(SYSBSLPE); +} + +//***************************************************************************** +// +//! \brief Enables BSL memory. +//! +//! This function enables BSL memory, which allows BSL memory to be addressed +//! +//! +//! \return None +// +//***************************************************************************** +void SYS_enableBSLMemory(void) +{ + HWREG16(SYS_BASE + OFS_SYSBSLC) &= ~(SYSBSLOFF); +} + +//***************************************************************************** +// +//! \brief Disables BSL memory. +//! +//! This function disables BSL memory, which makes BSL memory act like vacant +//! memory. +//! +//! +//! \return None +// +//***************************************************************************** +void SYS_disableBSLMemory(void) +{ + HWREG16(SYS_BASE + OFS_SYSBSLC) |= SYSBSLOFF; +} + +//***************************************************************************** +// +//! \brief Sets RAM assignment to BSL area. +//! +//! This function allows RAM to be assigned to BSL, based on the selection of +//! the BSLRAMAssignment parameter. +//! +//! \param BSLRAMAssignment is the selection of if the BSL should be placed in +//! RAM or not. +//! Valid values are: +//! - \b SYS_BSLRAMASSIGN_NORAM [Default] +//! - \b SYS_BSLRAMASSIGN_LOWEST16BYTES +//! \n Modified bits are \b SYSBSLR of \b SYSBSLC register. +//! +//! \return None +// +//***************************************************************************** +void SYS_setRAMAssignedToBSL(uint8_t BSLRAMAssignment) +{ + HWREG8(SYS_BASE + OFS_SYSBSLC_L) &= ~(SYSBSLR); + HWREG8(SYS_BASE + OFS_SYSBSLC_L) |= BSLRAMAssignment; +} + +//***************************************************************************** +// +//! \brief Sets the size of the BSL in Flash. +//! +//! This function sets the size of the BSL in Flash memory. +//! +//! \param BSLSizeSelect is the amount of segments the BSL should take. +//! Valid values are: +//! - \b SYS_BSLSIZE_SEG3 +//! - \b SYS_BSLSIZE_SEGS23 +//! - \b SYS_BSLSIZE_SEGS123 +//! - \b SYS_BSLSIZE_SEGS1234 [Default] +//! \n Modified bits are \b SYSBSLSIZE of \b SYSBSLC register. +//! +//! \return None +// +//***************************************************************************** +void SYS_setBSLSize(uint8_t BSLSizeSelect) +{ + HWREG8(SYS_BASE + OFS_SYSBSLC_L) &= ~(SYSBSLSIZE0 + SYSBSLSIZE1); + HWREG8(SYS_BASE + OFS_SYSBSLC_L) |= BSLSizeSelect; +} + +//***************************************************************************** +// +//! \brief Initializes JTAG Mailbox with selected properties. +//! +//! This function sets the specified settings for the JTAG Mailbox system. The +//! settings that can be set are the size of the JTAG messages, and the auto- +//! clearing of the inbox flags. If the inbox flags are set to auto-clear, then +//! the inbox flags will be cleared upon reading of the inbox message buffer, +//! otherwise they will have to be reset by software using the +//! SYS_clearJTAGMailboxFlagStatus() function. +//! +//! \param mailboxSizeSelect is the size of the JTAG Mailboxes, whether 16- or +//! 32-bits. +//! Valid values are: +//! - \b SYS_JTAGMBSIZE_16BIT [Default] - the JTAG messages will take up +//! only one JTAG mailbox (i. e. an outgoing message will take up +//! only 1 outbox of the JTAG mailboxes) +//! - \b SYS_JTAGMBSIZE_32BIT - the JTAG messages will be contained +//! within both JTAG mailboxes (i. e. an outgoing message will take +//! up both Outboxes of the JTAG mailboxes) +//! \n Modified bits are \b JMBMODE of \b SYSJMBC register. +//! \param autoClearInboxFlagSelect decides how the JTAG inbox flags should be +//! cleared, whether automatically after the corresponding outbox has +//! been written to, or manually by software. +//! Valid values are: +//! - \b SYS_JTAGINBOX0AUTO_JTAGINBOX1AUTO [Default] - both JTAG inbox +//! flags will be reset automatically when the corresponding inbox is +//! read from. +//! - \b SYS_JTAGINBOX0AUTO_JTAGINBOX1SW - only JTAG inbox 0 flag is +//! reset automatically, while JTAG inbox 1 is reset with the +//! - \b SYS_JTAGINBOX0SW_JTAGINBOX1AUTO - only JTAG inbox 1 flag is +//! reset automatically, while JTAG inbox 0 is reset with the +//! - \b SYS_JTAGINBOX0SW_JTAGINBOX1SW - both JTAG inbox flags will need +//! to be reset manually by the +//! \n Modified bits are \b JMBCLR0OFF and \b JMBCLR1OFF of \b SYSJMBC +//! register. +//! +//! \return None +// +//***************************************************************************** +void SYS_JTAGMailboxInit(uint8_t mailboxSizeSelect, + uint8_t autoClearInboxFlagSelect) +{ + HWREG8(SYS_BASE + OFS_SYSJMBC_L) &= ~(JMBCLR1OFF + JMBCLR0OFF + JMBMODE); + HWREG8(SYS_BASE + OFS_SYSJMBC_L) |= + mailboxSizeSelect + autoClearInboxFlagSelect; +} + +//***************************************************************************** +// +//! \brief Returns the status of the selected JTAG Mailbox flags. +//! +//! This function will return the status of the selected JTAG Mailbox flags in +//! bit mask format matching that passed into the mailboxFlagMask parameter. +//! +//! \param mailboxFlagMask is the bit mask of JTAG mailbox flags that the +//! status of should be returned. +//! Mask value is the logical OR of any of the following: +//! - \b SYS_JTAGOUTBOX_FLAG0 - flag for JTAG outbox 0 +//! - \b SYS_JTAGOUTBOX_FLAG1 - flag for JTAG outbox 1 +//! - \b SYS_JTAGINBOX_FLAG0 - flag for JTAG inbox 0 +//! - \b SYS_JTAGINBOX_FLAG1 - flag for JTAG inbox 1 +//! +//! \return A bit mask of the status of the selected mailbox flags. +// +//***************************************************************************** +uint8_t SYS_getJTAGMailboxFlagStatus(uint8_t mailboxFlagMask) +{ + return HWREG8(SYS_BASE + OFS_SYSJMBC_L) & mailboxFlagMask; +} + +//***************************************************************************** +// +//! \brief Clears the status of the selected JTAG Mailbox flags. +//! +//! This function clears the selected JTAG Mailbox flags. +//! +//! \param mailboxFlagMask is the bit mask of JTAG mailbox flags that the +//! status of should be cleared. +//! Mask value is the logical OR of any of the following: +//! - \b SYS_JTAGOUTBOX_FLAG0 - flag for JTAG outbox 0 +//! - \b SYS_JTAGOUTBOX_FLAG1 - flag for JTAG outbox 1 +//! - \b SYS_JTAGINBOX_FLAG0 - flag for JTAG inbox 0 +//! - \b SYS_JTAGINBOX_FLAG1 - flag for JTAG inbox 1 +//! +//! \return None +// +//***************************************************************************** +void SYS_clearJTAGMailboxFlagStatus(uint8_t mailboxFlagMask) +{ + HWREG8(SYS_BASE + OFS_SYSJMBC_L) &= ~(mailboxFlagMask); +} + +//***************************************************************************** +// +//! \brief Returns the contents of the selected JTAG Inbox in a 16 bit format. +//! +//! This function returns the message contents of the selected JTAG inbox. If +//! the auto clear settings for the Inbox flags were set, then using this +//! function will automatically clear the corresponding JTAG inbox flag. +//! +//! \param inboxSelect is the chosen JTAG inbox that the contents of should be +//! returned +//! Valid values are: +//! - \b SYS_JTAGINBOX_0 - return contents of JTAG inbox 0 +//! - \b SYS_JTAGINBOX_1 - return contents of JTAG inbox 1 +//! +//! \return The contents of the selected JTAG inbox in a 16 bit format. +// +//***************************************************************************** +uint16_t SYS_getJTAGInboxMessage16Bit(uint8_t inboxSelect) +{ + return HWREG16(SYS_BASE + OFS_SYSJMBI0 + inboxSelect); +} + +//***************************************************************************** +// +//! \brief Returns the contents of JTAG Inboxes in a 32 bit format. +//! +//! This function returns the message contents of both JTAG inboxes in a 32 bit +//! format. This function should be used if 32-bit messaging has been set in +//! the SYS_JTAGMailboxInit() function. If the auto clear settings for the +//! Inbox flags were set, then using this function will automatically clear +//! both JTAG inbox flags. +//! +//! +//! \return The contents of both JTAG messages in a 32 bit format. +// +//***************************************************************************** +uint32_t SYS_getJTAGInboxMessage32Bit(void) +{ + uint32_t JTAGInboxMessageLow = HWREG16(SYS_BASE + OFS_SYSJMBI0); + uint32_t JTAGInboxMessageHigh = HWREG16(SYS_BASE + OFS_SYSJMBI1); + + return (JTAGInboxMessageHigh << 16) + JTAGInboxMessageLow; +} + +//***************************************************************************** +// +//! \brief Sets a 16 bit outgoing message in to the selected JTAG Outbox. +//! +//! This function sets the outgoing message in the selected JTAG outbox. The +//! corresponding JTAG outbox flag is cleared after this function, and set +//! after the JTAG has read the message. +//! +//! \param outboxSelect is the chosen JTAG outbox that the message should be +//! set it. +//! Valid values are: +//! - \b SYS_JTAGOUTBOX_0 - set the contents of JTAG outbox 0 +//! - \b SYS_JTAGOUTBOX_1 - set the contents of JTAG outbox 1 +//! \param outgoingMessage is the message to send to the JTAG. +//! \n Modified bits are \b MSGHI and \b MSGLO of \b SYSJMBOx register. +//! +//! \return None +// +//***************************************************************************** +void SYS_setJTAGOutgoingMessage16Bit(uint8_t outboxSelect, + uint16_t outgoingMessage) +{ + HWREG16(SYS_BASE + OFS_SYSJMBO0 + outboxSelect) = outgoingMessage; +} + +//***************************************************************************** +// +//! \brief Sets a 32 bit message in to both JTAG Outboxes. +//! +//! This function sets the 32-bit outgoing message in both JTAG outboxes. The +//! JTAG outbox flags are cleared after this function, and set after the JTAG +//! has read the message. +//! +//! \param outgoingMessage is the message to send to the JTAG. +//! \n Modified bits are \b MSGHI and \b MSGLO of \b SYSJMBOx register. +//! +//! \return None +// +//***************************************************************************** +void SYS_setJTAGOutgoingMessage32Bit(uint32_t outgoingMessage) +{ + HWREG16(SYS_BASE + OFS_SYSJMBO0) = (outgoingMessage); + HWREG16(SYS_BASE + OFS_SYSJMBO1) = (outgoingMessage >> 16); +} + + +#endif +#endif +//***************************************************************************** +// +//! Close the doxygen group for sys_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/sys.h b/source/driverlib/MSP430F5xx_6xx/sys.h new file mode 100644 index 0000000..eebe2a0 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/sys.h @@ -0,0 +1,188 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// sys.h - Driver for the SYS Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_SYS_H__ +#define __MSP430WARE_SYS_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_SYS__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the BSLRAMAssignment +// parameter for functions: SYS_setRAMAssignedToBSL(). +// +//***************************************************************************** +#define SYS_BSLRAMASSIGN_NORAM (!(SYSBSLR)) +#define SYS_BSLRAMASSIGN_LOWEST16BYTES (SYSBSLR) + +//***************************************************************************** +// +// The following are values that can be passed to the BSLSizeSelect parameter +// for functions: SYS_setBSLSize(). +// +//***************************************************************************** +#define SYS_BSLSIZE_SEG3 (~(SYSBSLSIZE0 + SYSBSLSIZE1)) +#define SYS_BSLSIZE_SEGS23 (SYSBSLSIZE0) +#define SYS_BSLSIZE_SEGS123 (SYSBSLSIZE1) +#define SYS_BSLSIZE_SEGS1234 (SYSBSLSIZE0 + SYSBSLSIZE1) + +//***************************************************************************** +// +// The following are values that can be passed to the mailboxSizeSelect +// parameter for functions: SYS_JTAGMailboxInit(). +// +//***************************************************************************** +#define SYS_JTAGMBSIZE_16BIT (!(JMBMODE)) +#define SYS_JTAGMBSIZE_32BIT (JMBMODE) + +//***************************************************************************** +// +// The following are values that can be passed to the autoClearInboxFlagSelect +// parameter for functions: SYS_JTAGMailboxInit(). +// +//***************************************************************************** +#define SYS_JTAGINBOX0AUTO_JTAGINBOX1AUTO (!(JMBCLR0OFF + JMBCLR1OFF)) +#define SYS_JTAGINBOX0AUTO_JTAGINBOX1SW (JMBCLR1OFF) +#define SYS_JTAGINBOX0SW_JTAGINBOX1AUTO (JMBCLR0OFF) +#define SYS_JTAGINBOX0SW_JTAGINBOX1SW (JMBCLR0OFF + JMBCLR1OFF) + +//***************************************************************************** +// +// The following are values that can be passed to the mailboxFlagMask parameter +// for functions: SYS_getJTAGMailboxFlagStatus(), and +// SYS_clearJTAGMailboxFlagStatus(). +// +//***************************************************************************** +#define SYS_JTAGOUTBOX_FLAG0 (JMBOUT0FG) +#define SYS_JTAGOUTBOX_FLAG1 (JMBOUT1FG) +#define SYS_JTAGINBOX_FLAG0 (JMBIN0FG) +#define SYS_JTAGINBOX_FLAG1 (JMBIN1FG) + +//***************************************************************************** +// +// The following are values that can be passed to the inboxSelect parameter for +// functions: SYS_getJTAGInboxMessage16Bit(). +// +//***************************************************************************** +#define SYS_JTAGINBOX_0 (0x0) +#define SYS_JTAGINBOX_1 (0x2) + +//***************************************************************************** +// +// The following are values that can be passed to the outboxSelect parameter +// for functions: SYS_setJTAGOutgoingMessage16Bit(). +// +//***************************************************************************** +#define SYS_JTAGOUTBOX_0 (0x0) +#define SYS_JTAGOUTBOX_1 (0x2) + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the SYS_getBSLEntryIndication() function. +// +//***************************************************************************** +#define SYS_BSLENTRY_INDICATED (0x1) +#define SYS_BSLENTRY_NOTINDICATED (0x0) + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SYS_enableDedicatedJTAGPins(void); + +extern uint8_t SYS_getBSLEntryIndication(void); + +extern void SYS_enablePMMAccessProtect(void); + +extern void SYS_enableRAMBasedInterruptVectors(void); + +extern void SYS_disableRAMBasedInterruptVectors(void); + +extern void SYS_enableBSLProtect(void); + +extern void SYS_disableBSLProtect(void); + +extern void SYS_enableBSLMemory(void); + +extern void SYS_disableBSLMemory(void); + +extern void SYS_setRAMAssignedToBSL(uint8_t BSLRAMAssignment); + +extern void SYS_setBSLSize(uint8_t BSLSizeSelect); + +extern void SYS_JTAGMailboxInit(uint8_t mailboxSizeSelect, + uint8_t autoClearInboxFlagSelect); + +extern uint8_t SYS_getJTAGMailboxFlagStatus(uint8_t mailboxFlagMask); + +extern void SYS_clearJTAGMailboxFlagStatus(uint8_t mailboxFlagMask); + +extern uint16_t SYS_getJTAGInboxMessage16Bit(uint8_t inboxSelect); + +extern uint32_t SYS_getJTAGInboxMessage32Bit(void); + +extern void SYS_setJTAGOutgoingMessage16Bit(uint8_t outboxSelect, + uint16_t outgoingMessage); + +extern void SYS_setJTAGOutgoingMessage32Bit(uint32_t outgoingMessage); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_SYS_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/tec.c b/source/driverlib/MSP430F5xx_6xx/tec.c new file mode 100644 index 0000000..44bc226 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/tec.c @@ -0,0 +1,596 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// tec.c - Driver for the tec Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup tec_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_TEV0__ +#include "tec.h" + +#include + +//***************************************************************************** +// +//! \brief Configures the Timer Event Control External Clear Input +//! +//! \param baseAddress is the base address of the TEC module. +//! \param signalType is the selected signal type +//! Valid values are: +//! - \b TEC_EXTERNAL_CLEAR_SIGNALTYPE_EDGE_SENSITIVE [Default] +//! - \b TEC_EXTERNAL_CLEAR_SIGNALTYPE_LEVEL_SENSITIVE +//! \param signalHold is the selected signal hold +//! Valid values are: +//! - \b TEC_EXTERNAL_CLEAR_SIGNAL_NOT_HELD [Default] +//! - \b TEC_EXTERNAL_CLEAR_SIGNAL_HELD +//! \param polarityBit is the selected signal type +//! Valid values are: +//! - \b TEC_EXTERNAL_CLEAR_POLARITY_FALLING_EDGE_OR_LOW_LEVEL [Default] +//! - \b TEC_EXTERNAL_CLEAR_POLARITY_RISING_EDGE_OR_HIGH_LEVEL +//! +//! Modified bits of \b TECxCTL2 register. +//! +//! \return None +// +//***************************************************************************** +void TEC_initExternalClearInput(uint16_t baseAddress, + uint8_t signalType, + uint8_t signalHold, + uint8_t polarityBit + ) +{ + assert( signalType == TEC_EXTERNAL_CLEAR_SIGNALTYPE_EDGE_SENSITIVE || + signalType == TEC_EXTERNAL_CLEAR_SIGNALTYPE_LEVEL_SENSITIVE + ); + assert( signalHold == TEC_EXTERNAL_CLEAR_SIGNAL_NOT_HELD || + signalHold == TEC_EXTERNAL_CLEAR_SIGNAL_HELD + ); + assert( polarityBit == TEC_EXTERNAL_CLEAR_POLARITY_FALLING_EDGE_OR_LOW_LEVEL || + polarityBit == TEC_EXTERNAL_CLEAR_POLARITY_RISING_EDGE_OR_HIGH_LEVEL + ); + + HWREG8(baseAddress + OFS_TEC0XCTL2_L) &= ~(TEC_EXTERNAL_CLEAR_SIGNALTYPE_LEVEL_SENSITIVE + + TEC_EXTERNAL_CLEAR_SIGNAL_HELD + + TEC_EXTERNAL_CLEAR_POLARITY_RISING_EDGE_OR_HIGH_LEVEL + ); + + HWREG8(baseAddress + OFS_TEC0XCTL2_L) |= (signalType + + signalHold + + polarityBit + ); +} + +//***************************************************************************** +// +//! \brief DEPRECATED - Configures the Timer Event Control External Fault Input +//! +//! \param baseAddress is the base address of the TEC module. +//! \param selectedExternalFault is the selected external fault +//! Valid values are: +//! - \b TEC_EXTERNAL_FAULT_0 +//! - \b TEC_EXTERNAL_FAULT_1 +//! - \b TEC_EXTERNAL_FAULT_2 +//! - \b TEC_EXTERNAL_FAULT_3 +//! - \b TEC_EXTERNAL_FAULT_4 +//! - \b TEC_EXTERNAL_FAULT_5 +//! - \b TEC_EXTERNAL_FAULT_6 +//! \param signalType is the selected signal type +//! Valid values are: +//! - \b TEC_EXTERNAL_FAULT_SIGNALTYPE_EDGE_SENSITIVE [Default] +//! - \b TEC_EXTERNAL_FAULT_SIGNALTYPE_LEVEL_SENSITIVE +//! \param signalHold is the selected signal hold +//! Valid values are: +//! - \b TEC_EXTERNAL_FAULT_SIGNAL_NOT_HELD [Default] +//! - \b TEC_EXTERNAL_FAULT_SIGNAL_HELD +//! \param polarityBit is the selected signal type +//! Valid values are: +//! - \b TEC_EXTERNAL_FAULT_POLARITY_FALLING_EDGE_OR_LOW_LEVEL [Default] +//! - \b TEC_EXTERNAL_FAULT_POLARITY_RISING_EDGE_OR_HIGH_LEVEL +//! +//! Modified bits of \b TECxCTL2 register. +//! +//! \return None +// +//***************************************************************************** +void TEC_configureExternalFaultInput(uint16_t baseAddress, + uint8_t selectedExternalFault, + uint16_t signalType, + uint8_t signalHold, + uint8_t polarityBit + ) +{ + TEC_initExternalFaultInputParam param = { 0 }; + + param.selectedExternalFault = selectedExternalFault; + param.signalType = signalType; + param.signalHold = signalHold; + param.polarityBit = polarityBit; + + TEC_initExternalFaultInput(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Configures the Timer Event Control External Fault Input +//! +//! \param baseAddress is the base address of the TEC module. +//! \param param is the pointer to struct for external fault input +//! initialization. +//! +//! Modified bits of \b TECxCTL2 register. +//! +//! \return None +// +//***************************************************************************** +void TEC_initExternalFaultInput(uint16_t baseAddress, + TEC_initExternalFaultInputParam *param) +{ + assert(param != 0); + + assert(param->selectedExternalFault == TEC_EXTERNAL_FAULT_0 || + param->selectedExternalFault == TEC_EXTERNAL_FAULT_1 || + param->selectedExternalFault == TEC_EXTERNAL_FAULT_2 || + param->selectedExternalFault == TEC_EXTERNAL_FAULT_3 || + param->selectedExternalFault == TEC_EXTERNAL_FAULT_4 || + param->selectedExternalFault == TEC_EXTERNAL_FAULT_5 || + param->selectedExternalFault == TEC_EXTERNAL_FAULT_6 + ); + + assert(param->signalType == TEC_EXTERNAL_FAULT_SIGNALTYPE_EDGE_SENSITIVE || + param->signalType == TEC_EXTERNAL_FAULT_SIGNALTYPE_LEVEL_SENSITIVE + ); + + assert(param->signalHold == TEC_EXTERNAL_FAULT_SIGNAL_NOT_HELD || + param->signalHold == TEC_EXTERNAL_FAULT_SIGNAL_HELD + ); + + assert(param->polarityBit == TEC_EXTERNAL_FAULT_POLARITY_FALLING_EDGE_OR_LOW_LEVEL || + param->polarityBit == TEC_EXTERNAL_FAULT_POLARITY_RISING_EDGE_OR_HIGH_LEVEL + ); + + HWREG8(baseAddress + OFS_TEC0XCTL2_L) &= ~((TEC_EXTERNAL_FAULT_SIGNALTYPE_LEVEL_SENSITIVE << param->selectedExternalFault) + + (TEC_EXTERNAL_FAULT_POLARITY_RISING_EDGE_OR_HIGH_LEVEL << param->selectedExternalFault) + + (TEC_EXTERNAL_FAULT_SIGNAL_HELD << param->selectedExternalFault ) + ); + + HWREG8(baseAddress + OFS_TEC0XCTL2_L) |= ((param->signalType << param->selectedExternalFault) + + (param->polarityBit << param->selectedExternalFault) + + (param->signalHold << param->selectedExternalFault ) + ); +} +//***************************************************************************** +// +//! \brief Enable the Timer Event Control External fault input +//! +//! \param baseAddress is the base address of the TEC module. +//! \param channelEventBlock selects the channel event block +//! Valid values are: +//! - \b TEC_CE0 +//! - \b TEC_CE1 +//! - \b TEC_CE2 +//! - \b TEC_CE3 - (available on TEC5 TEC7) +//! - \b TEC_CE4 - (available on TEC5 TEC7) +//! - \b TEC_CE5 - (only available on TEC7) +//! - \b TEC_CE6 - (only available on TEC7) +//! +//! Modified bits of \b TECxCTL0 register. +//! +//! \return None +// +//***************************************************************************** +void TEC_enableExternalFaultInput(uint16_t baseAddress, + uint8_t channelEventBlock + ) +{ + + assert( channelEventBlock == TEC_CE0 || + channelEventBlock == TEC_CE1 || + channelEventBlock == TEC_CE2 || + channelEventBlock == TEC_CE3 || + channelEventBlock == TEC_CE4 || + channelEventBlock == TEC_CE5 || + channelEventBlock == TEC_CE6 + ); + + HWREG8(baseAddress + OFS_TEC0XCTL0_H) |= (1 << channelEventBlock ); +} + +//***************************************************************************** +// +//! \brief Disable the Timer Event Control External fault input +//! +//! \param baseAddress is the base address of the TEC module. +//! \param channelEventBlock selects the channel event block +//! Valid values are: +//! - \b TEC_CE0 +//! - \b TEC_CE1 +//! - \b TEC_CE2 +//! - \b TEC_CE3 - (available on TEC5 TEC7) +//! - \b TEC_CE4 - (available on TEC5 TEC7) +//! - \b TEC_CE5 - (only available on TEC7) +//! - \b TEC_CE6 - (only available on TEC7) +//! +//! Modified bits of \b TECxCTL0 register. +//! +//! \return None +// +//***************************************************************************** +void TEC_disableExternalFaultInput(uint16_t baseAddress, + uint8_t channelEventBlock + ) +{ + + assert( channelEventBlock == TEC_CE0 || + channelEventBlock == TEC_CE1 || + channelEventBlock == TEC_CE2 || + channelEventBlock == TEC_CE3 || + channelEventBlock == TEC_CE4 || + channelEventBlock == TEC_CE5 || + channelEventBlock == TEC_CE6 + ); + + HWREG8(baseAddress + OFS_TEC0XCTL0_H) &= ~(1 << channelEventBlock ); +} + +//***************************************************************************** +// +//! \brief Enable the Timer Event Control External Clear Input +//! +//! \param baseAddress is the base address of the TEC module. +//! +//! Modified bits of \b TECxCTL2 register. +//! +//! \return None +// +//***************************************************************************** +void TEC_enableExternalClearInput(uint16_t baseAddress ) +{ + HWREG8(baseAddress + OFS_TEC0XCTL2_L) |= TECEXCLREN; +} + +//***************************************************************************** +// +//! \brief Disable the Timer Event Control External Clear Input +//! +//! \param baseAddress is the base address of the TEC module. +//! +//! Modified bits of \b TECxCTL2 register. +//! +//! \return None +// +//***************************************************************************** +void TEC_disableExternalClearInput(uint16_t baseAddress ) +{ + HWREG8(baseAddress + OFS_TEC0XCTL2_L) &= ~TECEXCLREN; +} + +//***************************************************************************** +// +//! \brief Enable the Timer Event Control Auxiliary Clear Signal +//! +//! \param baseAddress is the base address of the TEC module. +//! +//! Modified bits of \b TECxCTL2 register. +//! +//! \return None +// +//***************************************************************************** +void TEC_enableAuxiliaryClearSignal(uint16_t baseAddress ) +{ + HWREG8(baseAddress + OFS_TEC0XCTL2_L) |= TECAXCLREN; +} + +//***************************************************************************** +// +//! \brief Disable the Timer Event Control Auxiliary Clear Signal +//! +//! \param baseAddress is the base address of the TEC module. +//! +//! Modified bits of \b TECxCTL2 register. +//! +//! \return None +// +//***************************************************************************** +void TEC_disableAuxiliaryClearSignal(uint16_t baseAddress ) +{ + HWREG8(baseAddress + OFS_TEC0XCTL2_L) &= ~TECAXCLREN; +} + +//***************************************************************************** +// +//! \brief Clears the Timer Event Control Interrupt flag +//! +//! \param baseAddress is the base address of the TEC module. +//! \param mask is the masked interrupt flag to be cleared. +//! Mask value is the logical OR of any of the following: +//! - \b TEC_EXTERNAL_FAULT_INTERRUPT - External fault interrupt flag +//! - \b TEC_EXTERNAL_CLEAR_INTERRUPT - External clear interrupt flag +//! - \b TEC_AUXILIARY_CLEAR_INTERRUPT - Auxiliary clear interrupt flag +//! +//! Modified bits of \b TECxINT register. +//! +//! \return None +// +//***************************************************************************** +void TEC_clearInterruptFlag(uint16_t baseAddress, + uint8_t mask + ) +{ + assert( 0x00 == ( mask & ~(TEC_EXTERNAL_FAULT_INTERRUPT + + TEC_EXTERNAL_CLEAR_INTERRUPT + + TEC_AUXILIARY_CLEAR_INTERRUPT + )) + ); + + HWREG8(baseAddress + OFS_TEC0XINT_L) &= ~mask; +} + +//***************************************************************************** +// +//! \brief Gets the current Timer Event Control interrupt status. +//! +//! This returns the interrupt status for the module based on which flag is +//! passed. +//! +//! \param baseAddress is the base address of the TEC module. +//! \param mask is the masked interrupt flag status to be returned. +//! Mask value is the logical OR of any of the following: +//! - \b TEC_EXTERNAL_FAULT_INTERRUPT - External fault interrupt flag +//! - \b TEC_EXTERNAL_CLEAR_INTERRUPT - External clear interrupt flag +//! - \b TEC_AUXILIARY_CLEAR_INTERRUPT - Auxiliary clear interrupt flag +//! +//! \return Logical OR of any of the following: +//! - \b TEC_EXTERNAL_FAULT_INTERRUPT External fault interrupt flag +//! - \b TEC_EXTERNAL_CLEAR_INTERRUPT External clear interrupt flag +//! - \b TEC_AUXILIARY_CLEAR_INTERRUPT Auxiliary clear interrupt flag +//! \n indicating the status of the masked interrupts +// +//***************************************************************************** +uint8_t TEC_getInterruptStatus(uint16_t baseAddress, + uint8_t mask + ) +{ + assert( 0x00 == ( mask & ~(TEC_EXTERNAL_FAULT_INTERRUPT + + TEC_EXTERNAL_CLEAR_INTERRUPT + + TEC_AUXILIARY_CLEAR_INTERRUPT + )) + ); + //Return the interrupt status of the request masked bit. + return HWREG8(baseAddress + OFS_TEC0XINT_L) & mask; +} + +//***************************************************************************** +// +//! \brief Enables individual Timer Event Control interrupt sources. +//! +//! Enables the indicated Timer Event Control interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. Does not clear interrupt +//! flags. +//! +//! \param baseAddress is the base address of the TEC module. +//! \param mask is the bit mask of the interrupt sources to be enabled. +//! Mask value is the logical OR of any of the following: +//! - \b TEC_EXTERNAL_FAULT_INTERRUPT - External fault interrupt flag +//! - \b TEC_EXTERNAL_CLEAR_INTERRUPT - External clear interrupt flag +//! - \b TEC_AUXILIARY_CLEAR_INTERRUPT - Auxiliary clear interrupt flag +//! +//! Modified bits of \b TECxINT register. +//! +//! \return None +// +//***************************************************************************** +void TEC_enableInterrupt(uint16_t baseAddress, + uint8_t mask + ) +{ + assert( 0x00 == ( mask & ~(TEC_EXTERNAL_FAULT_INTERRUPT + + TEC_EXTERNAL_CLEAR_INTERRUPT + + TEC_AUXILIARY_CLEAR_INTERRUPT + )) + ); + + //Enable the interrupt masked bit + HWREG8(baseAddress + OFS_TEC0XINT_H) |= mask; +} + +//***************************************************************************** +// +//! \brief Disables individual Timer Event Control interrupt sources. +//! +//! Disables the indicated Timer Event Control interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt; +//! disabled sources have no effect on the processor. +//! +//! \param baseAddress is the base address of the TEC module. +//! \param mask is the bit mask of the interrupt sources to be disabled. +//! Mask value is the logical OR of any of the following: +//! - \b TEC_EXTERNAL_FAULT_INTERRUPT - External fault interrupt flag +//! - \b TEC_EXTERNAL_CLEAR_INTERRUPT - External clear interrupt flag +//! - \b TEC_AUXILIARY_CLEAR_INTERRUPT - Auxiliary clear interrupt flag +//! +//! Modified bits of \b TECxINT register. +//! +//! \return None +// +//***************************************************************************** +void TEC_disableInterrupt(uint16_t baseAddress, + uint8_t mask + ) +{ + assert( 0x00 == ( mask & ~(TEC_EXTERNAL_FAULT_INTERRUPT + + TEC_EXTERNAL_CLEAR_INTERRUPT + + TEC_AUXILIARY_CLEAR_INTERRUPT + )) + ); + + //Disable the interrupt masked bit + HWREG8(baseAddress + OFS_TEC0XINT_H) &= ~(mask); +} + +//***************************************************************************** +// +//! \brief Gets the current Timer Event Control External Fault Status +//! +//! This returns the Timer Event Control fault status for the module. +//! +//! \param baseAddress is the base address of the TEC module. +//! \param mask is the masked interrupt flag status to be returned. +//! Mask value is the logical OR of any of the following: +//! - \b TEC_CE0 +//! - \b TEC_CE1 +//! - \b TEC_CE2 +//! - \b TEC_CE3 - (available on TEC5 TEC7) +//! - \b TEC_CE4 - (available on TEC5 TEC7) +//! - \b TEC_CE5 - (only available on TEC7) +//! - \b TEC_CE6 - (only available on TEC7) +//! +//! \return Logical OR of any of the following: +//! - \b TEC_CE0 +//! - \b TEC_CE1 +//! - \b TEC_CE2 +//! - \b TEC_CE3 (available on TEC5 TEC7) +//! - \b TEC_CE4 (available on TEC5 TEC7) +//! - \b TEC_CE5 (only available on TEC7) +//! - \b TEC_CE6 (only available on TEC7) +//! \n indicating the external fault status of the masked channel event +//! blocks +// +//***************************************************************************** +uint8_t TEC_getExternalFaultStatus(uint16_t baseAddress, + uint8_t mask + ) +{ + assert( 0x00 == ( mask & ~(TEC_CE0 + + TEC_CE1 + + TEC_CE2 + + TEC_CE3 + + TEC_CE4 + + TEC_CE5 + + TEC_CE6 + )) + ); + //Return the interrupt status of the request masked bit. + return HWREG8(baseAddress + OFS_TEC0STA_L) & mask; +} + +//***************************************************************************** +// +//! \brief Clears the Timer Event Control External Fault Status +//! +//! \param baseAddress is the base address of the TEC module. +//! \param mask is the masked status flag be cleared +//! Mask value is the logical OR of any of the following: +//! - \b TEC_CE0 +//! - \b TEC_CE1 +//! - \b TEC_CE2 +//! - \b TEC_CE3 - (available on TEC5 TEC7) +//! - \b TEC_CE4 - (available on TEC5 TEC7) +//! - \b TEC_CE5 - (only available on TEC7) +//! - \b TEC_CE6 - (only available on TEC7) +//! +//! Modified bits of \b TECxINT register. +//! +//! \return None +// +//***************************************************************************** +void TEC_clearExternalFaultStatus(uint16_t baseAddress, + uint8_t mask + ) +{ + assert( 0x00 == ( mask & ~(TEC_CE0 + + TEC_CE1 + + TEC_CE2 + + TEC_CE3 + + TEC_CE4 + + TEC_CE5 + + TEC_CE6 + )) + ); + + HWREG8(baseAddress + OFS_TEC0STA_L) &= ~mask; +} + +//***************************************************************************** +// +//! \brief Gets the current Timer Event Control External Clear Status +//! +//! \param baseAddress is the base address of the TEC module. +//! +//! \return One of the following: +//! - \b TEC_EXTERNAL_CLEAR_DETECTED +//! - \b TEC_EXTERNAL_CLEAR_NOT_DETECTED +//! \n indicating the status of the external clear +// +//***************************************************************************** +uint8_t TEC_getExternalClearStatus(uint16_t baseAddress) + +{ + //Return the interrupt status of the request masked bit. + return HWREG8(baseAddress + OFS_TEC0STA_L) & TECXCLRSTA; +} + +//***************************************************************************** +// +//! \brief Clears the Timer Event Control External Clear Status +//! +//! \param baseAddress is the base address of the TEC module. +//! +//! Modified bits of \b TECxINT register. +//! +//! \return None +// +//***************************************************************************** +void TEC_clearExternalClearStatus(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_TEC0STA_L) &= ~TECXCLRSTA; +} + + +#endif +//***************************************************************************** +// +//! Close the doxygen group for tec_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/tec.h b/source/driverlib/MSP430F5xx_6xx/tec.h new file mode 100644 index 0000000..cd7ef6f --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/tec.h @@ -0,0 +1,251 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// tec.h - Driver for the TEC Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_TEC_H__ +#define __MSP430WARE_TEC_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_TEV0__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//****************************************************************************** +// +// The following is a struct that is passed to TEC_initExternalFaultInput() +// +//****************************************************************************** +typedef struct TEC_initExternalFaultInputParam { + uint8_t selectedExternalFault; + uint16_t signalType; + uint8_t signalHold; + uint8_t polarityBit; +} TEC_initExternalFaultInputParam; + +//***************************************************************************** +// +// The following are values that can be passed to the signalHold parameter for +// functions: TEC_initExternalClearInput(). +// +//***************************************************************************** +#define TEC_EXTERNAL_CLEAR_SIGNAL_NOT_HELD 0x00 +#define TEC_EXTERNAL_CLEAR_SIGNAL_HELD TECEXCLRHLD + +//***************************************************************************** +// +// The following are values that can be passed to the signalHold parameter for +// functions: TEC_configureExternalFaultInput(). +// +//***************************************************************************** +#define TEC_EXTERNAL_FAULT_SIGNAL_NOT_HELD 0x00 +#define TEC_EXTERNAL_FAULT_SIGNAL_HELD TECXFLTHLD0 + +//***************************************************************************** +// +// The following are values that can be passed to the polarityBit parameter for +// functions: TEC_initExternalClearInput(). +// +//***************************************************************************** +#define TEC_EXTERNAL_CLEAR_POLARITY_FALLING_EDGE_OR_LOW_LEVEL 0x00 +#define TEC_EXTERNAL_CLEAR_POLARITY_RISING_EDGE_OR_HIGH_LEVEL TECEXCLRPOL + +//***************************************************************************** +// +// The following are values that can be passed to the polarityBit parameter for +// functions: TEC_configureExternalFaultInput(). +// +//***************************************************************************** +#define TEC_EXTERNAL_FAULT_POLARITY_FALLING_EDGE_OR_LOW_LEVEL 0x00 +#define TEC_EXTERNAL_FAULT_POLARITY_RISING_EDGE_OR_HIGH_LEVEL TECXFLTPOL0 + +//***************************************************************************** +// +// The following are values that can be passed to the signalType parameter for +// functions: TEC_initExternalClearInput(). +// +//***************************************************************************** +#define TEC_EXTERNAL_CLEAR_SIGNALTYPE_EDGE_SENSITIVE 0x00 +#define TEC_EXTERNAL_CLEAR_SIGNALTYPE_LEVEL_SENSITIVE TECEXCLRLVS + +//***************************************************************************** +// +// The following are values that can be passed to the signalType parameter for +// functions: TEC_configureExternalFaultInput(). +// +//***************************************************************************** +#define TEC_EXTERNAL_FAULT_SIGNALTYPE_EDGE_SENSITIVE 0x00 +#define TEC_EXTERNAL_FAULT_SIGNALTYPE_LEVEL_SENSITIVE TECXFLTLVS0 + +//***************************************************************************** +// +// The following are values that can be passed to the selectedExternalFault +// parameter for functions: TEC_configureExternalFaultInput(). +// +//***************************************************************************** +#define TEC_EXTERNAL_FAULT_0 0 +#define TEC_EXTERNAL_FAULT_1 1 +#define TEC_EXTERNAL_FAULT_2 2 +#define TEC_EXTERNAL_FAULT_3 3 +#define TEC_EXTERNAL_FAULT_4 4 +#define TEC_EXTERNAL_FAULT_5 5 +#define TEC_EXTERNAL_FAULT_6 6 + +//***************************************************************************** +// +// The following are values that can be passed to the channelEventBlock +// parameter for functions: TEC_enableExternalFaultInput(), and +// TEC_disableExternalFaultInput(); the mask parameter for functions: +// TEC_clearExternalFaultStatus(), and TEC_getExternalFaultStatus() as well as +// returned by the TEC_getExternalFaultStatus() function. +// +//***************************************************************************** +#define TEC_CE0 TECXFLT0STA +#define TEC_CE1 TECXFLT1STA +#define TEC_CE2 TECXFLT2STA +#define TEC_CE3 TECXFLT3STA +#define TEC_CE4 TECXFLT4STA +#define TEC_CE5 TECXFLT5STA +#define TEC_CE6 TECXFLT6STA + +//***************************************************************************** +// +// The following are values that can be passed to the mask parameter for +// functions: TEC_clearInterruptFlag(), TEC_getInterruptStatus(), +// TEC_enableInterrupt(), and TEC_disableInterrupt() as well as returned by the +// TEC_getInterruptStatus() function. +// +//***************************************************************************** +#define TEC_EXTERNAL_FAULT_INTERRUPT TECXFLTIFG +#define TEC_EXTERNAL_CLEAR_INTERRUPT TECEXCLRIFG +#define TEC_AUXILIARY_CLEAR_INTERRUPT TECAXCLRIFG + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the TEC_getExternalClearStatus() function. +// +//***************************************************************************** +#define TEC_EXTERNAL_CLEAR_DETECTED TECXCLRSTA +#define TEC_EXTERNAL_CLEAR_NOT_DETECTED 0x00 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void TEC_initExternalClearInput(uint16_t baseAddress, + uint8_t signalType, + uint8_t signalHold, + uint8_t polarityBit); + +extern void TEC_initExternalFaultInput(uint16_t baseAddress, + TEC_initExternalFaultInputParam *param); + +extern void TEC_enableExternalFaultInput(uint16_t baseAddress, + uint8_t channelEventBlock); + +extern void TEC_disableExternalFaultInput(uint16_t baseAddress, + uint8_t channelEventBlock); + +extern void TEC_enableExternalClearInput(uint16_t baseAddress); + +extern void TEC_disableExternalClearInput(uint16_t baseAddress); + +extern void TEC_enableAuxiliaryClearSignal(uint16_t baseAddress); + +extern void TEC_disableAuxiliaryClearSignal(uint16_t baseAddress); + +extern void TEC_clearInterruptFlag(uint16_t baseAddress, + uint8_t mask); + +extern uint8_t TEC_getInterruptStatus(uint16_t baseAddress, + uint8_t mask); + +extern void TEC_enableInterrupt(uint16_t baseAddress, + uint8_t mask); + +extern void TEC_disableInterrupt(uint16_t baseAddress, + uint8_t mask); + +extern uint8_t TEC_getExternalFaultStatus(uint16_t baseAddress, + uint8_t mask); + +extern void TEC_clearExternalFaultStatus(uint16_t baseAddress, + uint8_t mask); + +extern uint8_t TEC_getExternalClearStatus(uint16_t baseAddress); + +extern void TEC_clearExternalClearStatus(uint16_t baseAddress); + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +#define TEC_configureExternalClearInput TEC_initExternalClearInput + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +extern void TEC_configureExternalFaultInput(uint16_t baseAddress, + uint8_t selectedExternalFault, + uint16_t signalType, + uint8_t signalHold, + uint8_t polarityBit); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_TEC_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/timer_a.c b/source/driverlib/MSP430F5xx_6xx/timer_a.c new file mode 100644 index 0000000..7f3f6f8 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/timer_a.c @@ -0,0 +1,1725 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// timer_a.c - Driver for the timer_a Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup timer_a_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_TxA7__ +#include "timer_a.h" + +#include + +//***************************************************************************** +// +//! \brief Starts TIMER_A counter +//! +//! This function assumes that the timer has been previously configured using +//! TIMER_A_configureContinuousMode, TIMER_A_configureUpMode or +//! TIMER_A_configureUpDownMode. +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! \param timerMode mode to put the timer in +//! Valid values are: +//! - \b TIMER_A_STOP_MODE +//! - \b TIMER_A_UP_MODE +//! - \b TIMER_A_CONTINUOUS_MODE [Default] +//! - \b TIMER_A_UPDOWN_MODE +//! +//! Modified bits of \b TAxCTL register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_A_startCounter( uint16_t baseAddress, + uint16_t timerMode + ) +{ + assert( + (TIMER_A_UPDOWN_MODE == timerMode) || + (TIMER_A_CONTINUOUS_MODE == timerMode) || + (TIMER_A_UP_MODE == timerMode) + ); + + HWREG16(baseAddress + OFS_TAxCTL) |= timerMode; +} + +//***************************************************************************** +// +//! \brief Configures TIMER_A in continuous mode. +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! \param param is the pointer to struct for continuous mode initialization. +//! +//! Modified bits of \b TAxCTL register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_A_initContinuousMode(uint16_t baseAddress, + TIMER_A_initContinuousModeParam *param) +{ + assert(param != 0); + + assert( + (TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK == param->clockSource) || + (TIMER_A_CLOCKSOURCE_ACLK == param->clockSource) || + (TIMER_A_CLOCKSOURCE_SMCLK == param->clockSource) || + (TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK == param->clockSource) + ); + + assert( + (TIMER_A_DO_CLEAR == param->timerClear) || + (TIMER_A_SKIP_CLEAR == param->timerClear) + ); + + assert( + (TIMER_A_TAIE_INTERRUPT_ENABLE == param->timerInterruptEnable_TAIE) || + (TIMER_A_TAIE_INTERRUPT_DISABLE == param->timerInterruptEnable_TAIE) + ); + + assert( + (TIMER_A_CLOCKSOURCE_DIVIDER_1 == param->clockSourceDivider) || + (TIMER_A_CLOCKSOURCE_DIVIDER_2 == param->clockSourceDivider) || + (TIMER_A_CLOCKSOURCE_DIVIDER_4 == param->clockSourceDivider) || + (TIMER_A_CLOCKSOURCE_DIVIDER_8 == param->clockSourceDivider) || + (TIMER_A_CLOCKSOURCE_DIVIDER_3 == param->clockSourceDivider) || + (TIMER_A_CLOCKSOURCE_DIVIDER_5 == param->clockSourceDivider) || + (TIMER_A_CLOCKSOURCE_DIVIDER_6 == param->clockSourceDivider) || + (TIMER_A_CLOCKSOURCE_DIVIDER_7 == param->clockSourceDivider) || + (TIMER_A_CLOCKSOURCE_DIVIDER_10 == param->clockSourceDivider) || + (TIMER_A_CLOCKSOURCE_DIVIDER_12 == param->clockSourceDivider) || + (TIMER_A_CLOCKSOURCE_DIVIDER_14 == param->clockSourceDivider) || + (TIMER_A_CLOCKSOURCE_DIVIDER_16 == param->clockSourceDivider) || + (TIMER_A_CLOCKSOURCE_DIVIDER_20 == param->clockSourceDivider) || + (TIMER_A_CLOCKSOURCE_DIVIDER_24 == param->clockSourceDivider) || + (TIMER_A_CLOCKSOURCE_DIVIDER_28 == param->clockSourceDivider) || + (TIMER_A_CLOCKSOURCE_DIVIDER_32 == param->clockSourceDivider) || + (TIMER_A_CLOCKSOURCE_DIVIDER_40 == param->clockSourceDivider) || + (TIMER_A_CLOCKSOURCE_DIVIDER_48 == param->clockSourceDivider) || + (TIMER_A_CLOCKSOURCE_DIVIDER_56 == param->clockSourceDivider) || + (TIMER_A_CLOCKSOURCE_DIVIDER_64 == param->clockSourceDivider) + ); + + HWREG16(baseAddress + + OFS_TAxCTL) &= ~(TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK + + TIMER_A_UPDOWN_MODE + + TIMER_A_DO_CLEAR + + TIMER_A_TAIE_INTERRUPT_ENABLE + + ID__8 + ); + HWREG16(baseAddress + OFS_TAxEX0) &= ~TAIDEX_7; + + HWREG16(baseAddress + OFS_TAxEX0) |= param->clockSourceDivider & 0x7; + HWREG16(baseAddress + OFS_TAxCTL) |= (param->clockSource + + param->timerClear + + param->timerInterruptEnable_TAIE + + ((param->clockSourceDivider >> 3) << 6)); + + if (param->startTimer) + HWREG16(baseAddress + OFS_TAxCTL) |= TIMER_A_CONTINUOUS_MODE; +} + +//***************************************************************************** +// +//! \brief DEPRECATED - Configures TIMER_A in continuous mode. +//! +//! This API does not start the timer. Timer needs to be started when required +//! using the TIMER_A_startCounter API. +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! \param clockSource selects Clock source. +//! Valid values are: +//! - \b TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK [Default] +//! - \b TIMER_A_CLOCKSOURCE_ACLK +//! - \b TIMER_A_CLOCKSOURCE_SMCLK +//! - \b TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK +//! \param clockSourceDivider is the desired divider for the clock source +//! Valid values are: +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_1 [Default] +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_2 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_3 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_4 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_5 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_6 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_7 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_8 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_10 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_12 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_14 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_16 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_20 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_24 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_28 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_32 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_40 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_48 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_56 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_64 +//! \param timerInterruptEnable_TAIE is to enable or disable TIMER_A interrupt +//! Valid values are: +//! - \b TIMER_A_TAIE_INTERRUPT_ENABLE +//! - \b TIMER_A_TAIE_INTERRUPT_DISABLE [Default] +//! \param timerClear decides if TIMER_A clock divider, count direction, count +//! need to be reset. +//! Valid values are: +//! - \b TIMER_A_DO_CLEAR +//! - \b TIMER_A_SKIP_CLEAR [Default] +//! +//! Modified bits of \b TAxCTL register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_A_configureContinuousMode( uint16_t baseAddress, + uint16_t clockSource, + uint16_t clockSourceDivider, + uint16_t timerInterruptEnable_TAIE, + uint16_t timerClear + ) +{ + TIMER_A_initContinuousModeParam param = { 0 }; + + param.clockSource = clockSource; + param.clockSourceDivider = clockSourceDivider; + param.timerInterruptEnable_TAIE = timerInterruptEnable_TAIE; + param.timerClear = timerClear; + param.startTimer = false; + + TIMER_A_initContinuousMode(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Configures TIMER_A in up mode. +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! \param param is the pointer to struct for up mode initialization. +//! +//! Modified bits of \b TAxCTL register, bits of \b TAxCCTL0 register and bits +//! of \b TAxCCR0 register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_A_initUpMode(uint16_t baseAddress, + TIMER_A_initUpModeParam *param) +{ + assert(param != 0); + + assert( + (TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK == param->clockSource) || + (TIMER_A_CLOCKSOURCE_ACLK == param->clockSource) || + (TIMER_A_CLOCKSOURCE_SMCLK == param->clockSource) || + (TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK == param->clockSource) + ); + + assert( + (TIMER_A_DO_CLEAR == param->timerClear) || + (TIMER_A_SKIP_CLEAR == param->timerClear) + ); + + assert( + (TIMER_A_DO_CLEAR == param->timerClear) || + (TIMER_A_SKIP_CLEAR == param->timerClear) + ); + + HWREG16(baseAddress + OFS_TAxCTL) &= + ~(TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK + + TIMER_A_UPDOWN_MODE + + TIMER_A_DO_CLEAR + + TIMER_A_TAIE_INTERRUPT_ENABLE + + ID__8 + ); + HWREG16(baseAddress + OFS_TAxEX0) &= ~TAIDEX_7; + + HWREG16(baseAddress + OFS_TAxEX0) |= param->clockSourceDivider & 0x7; + HWREG16(baseAddress + OFS_TAxCTL) |= (param->clockSource + + param->timerClear + + param->timerInterruptEnable_TAIE + + ((param->clockSourceDivider >> 3) << 6)); + + if (param->startTimer) + HWREG16(baseAddress + OFS_TAxCTL) |= TIMER_A_UP_MODE; + + if (TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE == + param->captureCompareInterruptEnable_CCR0_CCIE) + HWREG16(baseAddress + OFS_TAxCCTL0) |= TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE; + else + HWREG16(baseAddress + OFS_TAxCCTL0) &= ~TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE; + + HWREG16(baseAddress + OFS_TAxCCR0) = param->timerPeriod; +} + +//***************************************************************************** +// +//! \brief DEPRECATED - Configures TIMER_A in up mode. +//! +//! This API does not start the timer. Timer needs to be started when required +//! using the TIMER_A_startCounter API. +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! \param clockSource selects Clock source. +//! Valid values are: +//! - \b TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK [Default] +//! - \b TIMER_A_CLOCKSOURCE_ACLK +//! - \b TIMER_A_CLOCKSOURCE_SMCLK +//! - \b TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK +//! \param clockSourceDivider is the desired divider for the clock source +//! Valid values are: +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_1 [Default] +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_2 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_3 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_4 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_5 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_6 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_7 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_8 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_10 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_12 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_14 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_16 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_20 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_24 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_28 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_32 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_40 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_48 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_56 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_64 +//! \param timerPeriod is the specified TIMER_A period. This is the value that +//! gets written into the CCR0. Limited to 16 bits[uint16_t] +//! \param timerInterruptEnable_TAIE is to enable or disable TIMER_A interrupt +//! Valid values are: +//! - \b TIMER_A_TAIE_INTERRUPT_ENABLE +//! - \b TIMER_A_TAIE_INTERRUPT_DISABLE [Default] +//! \param captureCompareInterruptEnable_CCR0_CCIE is to enable or disable +//! TIMER_A CCR0 captureComapre interrupt. +//! Valid values are: +//! - \b TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE +//! - \b TIMER_A_CCIE_CCR0_INTERRUPT_DISABLE [Default] +//! \param timerClear decides if TIMER_A clock divider, count direction, count +//! need to be reset. +//! Valid values are: +//! - \b TIMER_A_DO_CLEAR +//! - \b TIMER_A_SKIP_CLEAR [Default] +//! +//! Modified bits of \b TAxCTL register, bits of \b TAxCCTL0 register and bits +//! of \b TAxCCR0 register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_A_configureUpMode(uint16_t baseAddress, + uint16_t clockSource, + uint16_t clockSourceDivider, + uint16_t timerPeriod, + uint16_t timerInterruptEnable_TAIE, + uint16_t captureCompareInterruptEnable_CCR0_CCIE, + uint16_t timerClear + ) +{ + TIMER_A_initUpModeParam param = { 0 }; + + param.clockSource = clockSource; + param.clockSourceDivider = clockSourceDivider; + param.timerPeriod = timerPeriod; + param.timerInterruptEnable_TAIE = timerInterruptEnable_TAIE; + param.captureCompareInterruptEnable_CCR0_CCIE = + captureCompareInterruptEnable_CCR0_CCIE; + param.timerClear = timerClear; + param.startTimer = false; + + TIMER_A_initUpMode(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Configures TIMER_A in up down mode. +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! \param param is the pointer to struct for up-down mode initialization. +//! +//! Modified bits of \b TAxCTL register, bits of \b TAxCCTL0 register and bits +//! of \b TAxCCR0 register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_A_initUpDownMode(uint16_t baseAddress, + TIMER_A_initUpDownModeParam *param) +{ + assert(param != 0); + + assert( + (TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK == param->clockSource) || + (TIMER_A_CLOCKSOURCE_ACLK == param->clockSource) || + (TIMER_A_CLOCKSOURCE_SMCLK == param->clockSource) || + (TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK == param->clockSource) + ); + + assert( + (TIMER_A_DO_CLEAR == param->timerClear) || + (TIMER_A_SKIP_CLEAR == param->timerClear) + ); + + HWREG16(baseAddress + OFS_TAxCTL) &= + ~(TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK + + TIMER_A_UPDOWN_MODE + + TIMER_A_DO_CLEAR + + TIMER_A_TAIE_INTERRUPT_ENABLE + + ID__8 + ); + HWREG16(baseAddress + OFS_TAxEX0) &= ~TAIDEX_7; + + HWREG16(baseAddress + OFS_TAxEX0) |= param->clockSourceDivider & 0x7; + HWREG16(baseAddress + OFS_TAxCTL) |= (param->clockSource + + param->timerClear + + param->timerInterruptEnable_TAIE + + ((param->clockSourceDivider >> 3) << 6)); + + if (param->startTimer) + HWREG16(baseAddress + OFS_TAxCTL) |= TIMER_A_UPDOWN_MODE; + + if (TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE == + param->captureCompareInterruptEnable_CCR0_CCIE) + HWREG16(baseAddress + OFS_TAxCCTL0) |= TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE; + else + HWREG16(baseAddress + OFS_TAxCCTL0) &= ~TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE; + + HWREG16(baseAddress + OFS_TAxCCR0) = param->timerPeriod; +} + +//***************************************************************************** +// +//! \brief DEPRECATED - Configures TIMER_A in up down mode. +//! +//! This API does not start the timer. Timer needs to be started when required +//! using the TIMER_A_startCounter API. +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! \param clockSource selects Clock source. +//! Valid values are: +//! - \b TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK [Default] +//! - \b TIMER_A_CLOCKSOURCE_ACLK +//! - \b TIMER_A_CLOCKSOURCE_SMCLK +//! - \b TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK +//! \param clockSourceDivider is the desired divider for the clock source +//! Valid values are: +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_1 [Default] +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_2 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_3 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_4 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_5 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_6 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_7 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_8 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_10 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_12 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_14 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_16 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_20 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_24 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_28 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_32 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_40 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_48 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_56 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_64 +//! \param timerPeriod is the specified TIMER_A period +//! \param timerInterruptEnable_TAIE is to enable or disable TIMER_A interrupt +//! Valid values are: +//! - \b TIMER_A_TAIE_INTERRUPT_ENABLE +//! - \b TIMER_A_TAIE_INTERRUPT_DISABLE [Default] +//! \param captureCompareInterruptEnable_CCR0_CCIE is to enable or disable +//! TIMER_A CCR0 captureComapre interrupt. +//! Valid values are: +//! - \b TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE +//! - \b TIMER_A_CCIE_CCR0_INTERRUPT_DISABLE [Default] +//! \param timerClear decides if TIMER_A clock divider, count direction, count +//! need to be reset. +//! Valid values are: +//! - \b TIMER_A_DO_CLEAR +//! - \b TIMER_A_SKIP_CLEAR [Default] +//! +//! Modified bits of \b TAxCTL register, bits of \b TAxCCTL0 register and bits +//! of \b TAxCCR0 register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_A_configureUpDownMode( + uint16_t baseAddress, + uint16_t clockSource, + uint16_t clockSourceDivider, + uint16_t timerPeriod, + uint16_t timerInterruptEnable_TAIE, + uint16_t captureCompareInterruptEnable_CCR0_CCIE, + uint16_t timerClear + ) +{ + TIMER_A_initUpDownModeParam param = { 0 }; + + param.clockSource = clockSource; + param.clockSourceDivider = clockSourceDivider; + param.timerPeriod = timerPeriod; + param.timerInterruptEnable_TAIE = timerInterruptEnable_TAIE; + param.captureCompareInterruptEnable_CCR0_CCIE = + captureCompareInterruptEnable_CCR0_CCIE; + param.timerClear = timerClear; + param.startTimer = false; + + TIMER_A_initUpDownMode(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief DEPRECATED - Starts timer in continuous mode. +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! \param clockSource selects Clock source. +//! Valid values are: +//! - \b TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK [Default] +//! - \b TIMER_A_CLOCKSOURCE_ACLK +//! - \b TIMER_A_CLOCKSOURCE_SMCLK +//! - \b TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK +//! \param clockSourceDivider is the desired divider for the clock source +//! Valid values are: +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_1 [Default] +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_2 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_3 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_4 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_5 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_6 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_7 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_8 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_10 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_12 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_14 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_16 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_20 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_24 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_28 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_32 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_40 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_48 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_56 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_64 +//! \param timerInterruptEnable_TAIE is to enable or disable timer interrupt +//! Valid values are: +//! - \b TIMER_A_TAIE_INTERRUPT_ENABLE +//! - \b TIMER_A_TAIE_INTERRUPT_DISABLE [Default] +//! \param timerClear decides if timer clock divider, count direction, count +//! need to be reset. +//! Valid values are: +//! - \b TIMER_A_DO_CLEAR +//! - \b TIMER_A_SKIP_CLEAR [Default] +//! +//! Modified bits of \b TAxCTL register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_A_startContinuousMode( uint16_t baseAddress, + uint16_t clockSource, + uint16_t clockSourceDivider, + uint16_t timerInterruptEnable_TAIE, + uint16_t timerClear + ) +{ + TIMER_A_initContinuousModeParam param = { 0 }; + + param.clockSource = clockSource; + param.clockSourceDivider = clockSourceDivider; + param.timerInterruptEnable_TAIE = timerInterruptEnable_TAIE; + param.timerClear = timerClear; + param.startTimer = true; + + TIMER_A_initContinuousMode(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief DEPRECATED - Spelling Error Fixed. Starts timer in continuous mode. +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! \param clockSource selects Clock source. +//! Valid values are: +//! - \b TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK [Default] +//! - \b TIMER_A_CLOCKSOURCE_ACLK +//! - \b TIMER_A_CLOCKSOURCE_SMCLK +//! - \b TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK +//! \param clockSourceDivider is the desired divider for the clock source +//! Valid values are: +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_1 [Default] +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_2 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_3 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_4 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_5 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_6 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_7 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_8 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_10 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_12 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_14 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_16 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_20 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_24 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_28 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_32 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_40 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_48 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_56 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_64 +//! \param timerInterruptEnable_TAIE is to enable or disable timer interrupt +//! Valid values are: +//! - \b TIMER_A_TAIE_INTERRUPT_ENABLE +//! - \b TIMER_A_TAIE_INTERRUPT_DISABLE [Default] +//! \param timerClear decides if timer clock divider, count direction, count +//! need to be reset. +//! Valid values are: +//! - \b TIMER_A_DO_CLEAR +//! - \b TIMER_A_SKIP_CLEAR [Default] +//! +//! Modified bits of \b TAxCTL register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_A_startContinousMode( uint16_t baseAddress, + uint16_t clockSource, + uint16_t clockSourceDivider, + uint16_t timerInterruptEnable_TAIE, + uint16_t timerClear + ) +{ + TIMER_A_startContinuousMode(baseAddress, + clockSource, + clockSourceDivider, + timerInterruptEnable_TAIE, + timerClear + ); +} + +//***************************************************************************** +// +//! \brief DEPRECATED - Replaced by TIMER_A_configureUpMode and +//! TIMER_A_startCounter API. Starts timer in up mode. +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! \param clockSource selects Clock source. +//! Valid values are: +//! - \b TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK [Default] +//! - \b TIMER_A_CLOCKSOURCE_ACLK +//! - \b TIMER_A_CLOCKSOURCE_SMCLK +//! - \b TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK +//! \param clockSourceDivider is the desired divider for the clock source +//! Valid values are: +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_1 [Default] +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_2 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_3 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_4 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_5 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_6 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_7 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_8 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_10 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_12 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_14 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_16 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_20 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_24 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_28 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_32 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_40 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_48 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_56 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_64 +//! \param timerPeriod is the specified timer period. This is the value that +//! gets written into the CCR0. Limited to 16 bits[uint16_t] +//! \param timerInterruptEnable_TAIE is to enable or disable timer interrupt +//! Valid values are: +//! - \b TIMER_A_TAIE_INTERRUPT_ENABLE +//! - \b TIMER_A_TAIE_INTERRUPT_DISABLE [Default] +//! \param captureCompareInterruptEnable_CCR0_CCIE is to enable or disable +//! timer CCR0 captureComapre interrupt. +//! Valid values are: +//! - \b TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE +//! - \b TIMER_A_CCIE_CCR0_INTERRUPT_DISABLE [Default] +//! \param timerClear decides if timer clock divider, count direction, count +//! need to be reset. +//! Valid values are: +//! - \b TIMER_A_DO_CLEAR +//! - \b TIMER_A_SKIP_CLEAR [Default] +//! +//! Modified bits of \b TAxCTL register, bits of \b TAxCCTL0 register and bits +//! of \b TAxCCR0 register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_A_startUpMode( uint16_t baseAddress, + uint16_t clockSource, + uint16_t clockSourceDivider, + uint16_t timerPeriod, + uint16_t timerInterruptEnable_TAIE, + uint16_t captureCompareInterruptEnable_CCR0_CCIE, + uint16_t timerClear + ) +{ + TIMER_A_initUpModeParam param = { 0 }; + + param.clockSource = clockSource; + param.clockSourceDivider = clockSourceDivider; + param.timerPeriod = timerPeriod; + param.timerInterruptEnable_TAIE = timerInterruptEnable_TAIE; + param.captureCompareInterruptEnable_CCR0_CCIE = + captureCompareInterruptEnable_CCR0_CCIE; + param.timerClear = timerClear; + param.startTimer = true; + + TIMER_A_initUpMode(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief DEPRECATED - Replaced by TIMER_A_configureUpMode and +//! TIMER_A_startCounter API. Starts timer in up down mode. +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! \param clockSource selects Clock source. +//! Valid values are: +//! - \b TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK [Default] +//! - \b TIMER_A_CLOCKSOURCE_ACLK +//! - \b TIMER_A_CLOCKSOURCE_SMCLK +//! - \b TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK +//! \param clockSourceDivider is the desired divider for the clock source +//! Valid values are: +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_1 [Default] +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_2 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_3 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_4 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_5 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_6 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_7 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_8 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_10 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_12 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_14 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_16 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_20 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_24 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_28 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_32 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_40 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_48 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_56 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_64 +//! \param timerPeriod is the specified timer period +//! \param timerInterruptEnable_TAIE is to enable or disable timer interrupt +//! Valid values are: +//! - \b TIMER_A_TAIE_INTERRUPT_ENABLE +//! - \b TIMER_A_TAIE_INTERRUPT_DISABLE [Default] +//! \param captureCompareInterruptEnable_CCR0_CCIE is to enable or disable +//! timer CCR0 captureComapre interrupt. +//! Valid values are: +//! - \b TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE +//! - \b TIMER_A_CCIE_CCR0_INTERRUPT_DISABLE [Default] +//! \param timerClear decides if timer clock divider, count direction, count +//! need to be reset. +//! Valid values are: +//! - \b TIMER_A_DO_CLEAR +//! - \b TIMER_A_SKIP_CLEAR [Default] +//! +//! Modified bits of \b TAxCTL register, bits of \b TAxCCTL0 register and bits +//! of \b TAxCCR0 register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_A_startUpDownMode( + uint16_t baseAddress, + uint16_t clockSource, + uint16_t clockSourceDivider, + uint16_t timerPeriod, + uint16_t timerInterruptEnable_TAIE, + uint16_t captureCompareInterruptEnable_CCR0_CCIE, + uint16_t timerClear + ) +{ + TIMER_A_initUpDownModeParam param = { 0 }; + + param.clockSource = clockSource; + param.clockSourceDivider = clockSourceDivider; + param.timerPeriod = timerPeriod; + param.timerInterruptEnable_TAIE = timerInterruptEnable_TAIE; + param.captureCompareInterruptEnable_CCR0_CCIE = + captureCompareInterruptEnable_CCR0_CCIE; + param.timerClear = timerClear; + param.startTimer = true; + + TIMER_A_initUpDownMode(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Initializes Capture Mode +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! \param param is the pointer to struct for capture mode initialization. +//! +//! Modified bits of \b TAxCCTLn register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_A_initCaptureMode(uint16_t baseAddress, + TIMER_A_initCaptureModeParam *param) +{ + assert(param != 0); + + assert((TIMER_A_CAPTURECOMPARE_REGISTER_0 == param->captureRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_1 == param->captureRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_2 == param->captureRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_3 == param->captureRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_4 == param->captureRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_5 == param->captureRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_6 == param->captureRegister) + ); + + assert((TIMER_A_CAPTUREMODE_NO_CAPTURE == param->captureMode) || + (TIMER_A_CAPTUREMODE_RISING_EDGE == param->captureMode) || + (TIMER_A_CAPTUREMODE_FALLING_EDGE == param->captureMode) || + (TIMER_A_CAPTUREMODE_RISING_AND_FALLING_EDGE == param->captureMode) + ); + + assert((TIMER_A_CAPTURE_INPUTSELECT_CCIxA == param->captureInputSelect) || + (TIMER_A_CAPTURE_INPUTSELECT_CCIxB == param->captureInputSelect) || + (TIMER_A_CAPTURE_INPUTSELECT_GND == param->captureInputSelect) || + (TIMER_A_CAPTURE_INPUTSELECT_Vcc == param->captureInputSelect) + ); + + assert((TIMER_A_CAPTURE_ASYNCHRONOUS == param->synchronizeCaptureSource) || + (TIMER_A_CAPTURE_SYNCHRONOUS == param->synchronizeCaptureSource) + ); + + assert( + (TIMER_A_CAPTURECOMPARE_INTERRUPT_DISABLE == param->captureInterruptEnable) || + (TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE == param->captureInterruptEnable) + ); + + assert((TIMER_A_OUTPUTMODE_OUTBITVALUE == param->captureOutputMode) || + (TIMER_A_OUTPUTMODE_SET == param->captureOutputMode) || + (TIMER_A_OUTPUTMODE_TOGGLE_RESET == param->captureOutputMode) || + (TIMER_A_OUTPUTMODE_SET_RESET == param->captureOutputMode) || + (TIMER_A_OUTPUTMODE_TOGGLE == param->captureOutputMode) || + (TIMER_A_OUTPUTMODE_RESET == param->captureOutputMode) || + (TIMER_A_OUTPUTMODE_TOGGLE_SET == param->captureOutputMode) || + (TIMER_A_OUTPUTMODE_RESET_SET == param->captureOutputMode) + ); + + //CaptureCompare register 0 only supports certain modes + assert((TIMER_A_CAPTURECOMPARE_REGISTER_0 == param->captureRegister) && + ((TIMER_A_OUTPUTMODE_OUTBITVALUE == param->captureOutputMode) || + (TIMER_A_OUTPUTMODE_SET == param->captureOutputMode) || + (TIMER_A_OUTPUTMODE_TOGGLE == param->captureOutputMode) || + (TIMER_A_OUTPUTMODE_RESET == param->captureOutputMode))); + + HWREG16(baseAddress + param->captureRegister ) |= CAP; + + HWREG16(baseAddress + param->captureRegister) &= + ~(TIMER_A_CAPTUREMODE_RISING_AND_FALLING_EDGE + + TIMER_A_CAPTURE_INPUTSELECT_Vcc + + TIMER_A_CAPTURE_SYNCHRONOUS + + TIMER_A_DO_CLEAR + + TIMER_A_TAIE_INTERRUPT_ENABLE + + CM_3 + ); + + HWREG16(baseAddress + param->captureRegister) |= (param->captureMode + + param->captureInputSelect + + param->synchronizeCaptureSource + + param->captureInterruptEnable + + param->captureOutputMode + ); +} + +//***************************************************************************** +// +//! \brief DEPRECATED - Initializes Capture Mode +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! \param captureRegister selects the Capture register being used. Refer to +//! datasheet to ensure the device has the capture compare register +//! being used. +//! Valid values are: +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_6 +//! \param captureMode is the capture mode selected. +//! Valid values are: +//! - \b TIMER_A_CAPTUREMODE_NO_CAPTURE [Default] +//! - \b TIMER_A_CAPTUREMODE_RISING_EDGE +//! - \b TIMER_A_CAPTUREMODE_FALLING_EDGE +//! - \b TIMER_A_CAPTUREMODE_RISING_AND_FALLING_EDGE +//! \param captureInputSelect decides the Input Select +//! Valid values are: +//! - \b TIMER_A_CAPTURE_INPUTSELECT_CCIxA +//! - \b TIMER_A_CAPTURE_INPUTSELECT_CCIxB +//! - \b TIMER_A_CAPTURE_INPUTSELECT_GND +//! - \b TIMER_A_CAPTURE_INPUTSELECT_Vcc +//! \param synchronizeCaptureSource decides if capture source should be +//! synchronized with timer clock +//! Valid values are: +//! - \b TIMER_A_CAPTURE_ASYNCHRONOUS [Default] +//! - \b TIMER_A_CAPTURE_SYNCHRONOUS +//! \param captureInterruptEnable is to enable or disable timer captureComapre +//! interrupt. +//! Valid values are: +//! - \b TIMER_A_CAPTURECOMPARE_INTERRUPT_DISABLE [Default] +//! - \b TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE +//! \param captureOutputMode specifies the output mode. +//! Valid values are: +//! - \b TIMER_A_OUTPUTMODE_OUTBITVALUE [Default] +//! - \b TIMER_A_OUTPUTMODE_SET +//! - \b TIMER_A_OUTPUTMODE_TOGGLE_RESET +//! - \b TIMER_A_OUTPUTMODE_SET_RESET +//! - \b TIMER_A_OUTPUTMODE_TOGGLE +//! - \b TIMER_A_OUTPUTMODE_RESET +//! - \b TIMER_A_OUTPUTMODE_TOGGLE_SET +//! - \b TIMER_A_OUTPUTMODE_RESET_SET +//! +//! Modified bits of \b TAxCCTLn register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_A_initCapture(uint16_t baseAddress, + uint16_t captureRegister, + uint16_t captureMode, + uint16_t captureInputSelect, + uint16_t synchronizeCaptureSource, + uint16_t captureInterruptEnable, + uint16_t captureOutputMode + ) +{ + TIMER_A_initCaptureModeParam param = { 0 }; + + param.captureRegister = captureRegister; + param.captureMode = captureMode; + param.captureInputSelect = captureInputSelect; + param.synchronizeCaptureSource = synchronizeCaptureSource; + param.captureInterruptEnable = captureInterruptEnable; + param.captureOutputMode = captureOutputMode; + + TIMER_A_initCaptureMode(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Initializes Compare Mode +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! \param param is the pointer to struct for compare mode initialization. +//! +//! Modified bits of \b TAxCCRn register and bits of \b TAxCCTLn register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_A_initCompareMode(uint16_t baseAddress, + TIMER_A_initCompareModeParam *param) +{ + assert(param != 0); + + assert((TIMER_A_CAPTURECOMPARE_REGISTER_0 == param->compareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_1 == param->compareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_2 == param->compareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_3 == param->compareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_4 == param->compareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_5 == param->compareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_6 == param->compareRegister) + ); + + assert((TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE == param->compareInterruptEnable) || + (TIMER_A_CAPTURECOMPARE_INTERRUPT_DISABLE == param->compareInterruptEnable) + ); + + assert((TIMER_A_OUTPUTMODE_OUTBITVALUE == param->compareOutputMode) || + (TIMER_A_OUTPUTMODE_SET == param->compareOutputMode) || + (TIMER_A_OUTPUTMODE_TOGGLE_RESET == param->compareOutputMode) || + (TIMER_A_OUTPUTMODE_SET_RESET == param->compareOutputMode) || + (TIMER_A_OUTPUTMODE_TOGGLE == param->compareOutputMode) || + (TIMER_A_OUTPUTMODE_RESET == param->compareOutputMode) || + (TIMER_A_OUTPUTMODE_TOGGLE_SET == param->compareOutputMode) || + (TIMER_A_OUTPUTMODE_RESET_SET == param->compareOutputMode) + ); + + //CaptureCompare register 0 only supports certain modes + assert((TIMER_A_CAPTURECOMPARE_REGISTER_0 == param->compareRegister) && + ((TIMER_A_OUTPUTMODE_OUTBITVALUE == param->compareOutputMode) || + (TIMER_A_OUTPUTMODE_SET == param->compareOutputMode) || + (TIMER_A_OUTPUTMODE_TOGGLE == param->compareOutputMode) || + (TIMER_A_OUTPUTMODE_RESET == param->compareOutputMode))); + + HWREG16(baseAddress + param->compareRegister ) &= ~CAP; + + HWREG16(baseAddress + param->compareRegister) &= + ~(TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE + + TIMER_A_OUTPUTMODE_RESET_SET + ); + + HWREG16(baseAddress + param->compareRegister) |= (param->compareInterruptEnable + + param->compareOutputMode + ); + + HWREG16(baseAddress + param->compareRegister + OFS_TAxR) = param->compareValue; +} + +//***************************************************************************** +// +//! \brief DEPRECATED - Initializes Compare Mode +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! \param compareRegister selects the Capture register being used. Refer to +//! datasheet to ensure the device has the capture compare register +//! being used. +//! Valid values are: +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_6 +//! \param compareInterruptEnable is to enable or disable timer captureComapre +//! interrupt. +//! Valid values are: +//! - \b TIMER_A_CAPTURECOMPARE_INTERRUPT_DISABLE [Default] +//! - \b TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE +//! \param compareOutputMode specifies the output mode. +//! Valid values are: +//! - \b TIMER_A_OUTPUTMODE_OUTBITVALUE [Default] +//! - \b TIMER_A_OUTPUTMODE_SET +//! - \b TIMER_A_OUTPUTMODE_TOGGLE_RESET +//! - \b TIMER_A_OUTPUTMODE_SET_RESET +//! - \b TIMER_A_OUTPUTMODE_TOGGLE +//! - \b TIMER_A_OUTPUTMODE_RESET +//! - \b TIMER_A_OUTPUTMODE_TOGGLE_SET +//! - \b TIMER_A_OUTPUTMODE_RESET_SET +//! \param compareValue is the count to be compared with in compare mode +//! +//! Modified bits of \b TAxCCRn register and bits of \b TAxCCTLn register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_A_initCompare( uint16_t baseAddress, + uint16_t compareRegister, + uint16_t compareInterruptEnable, + uint16_t compareOutputMode, + uint16_t compareValue + ) +{ + TIMER_A_initCompareModeParam param = { 0 }; + + param.compareRegister = compareRegister; + param.compareInterruptEnable = compareInterruptEnable; + param.compareOutputMode = compareOutputMode; + param.compareValue = compareValue; + + TIMER_A_initCompareMode(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Enable timer interrupt +//! +//! Does not clear interrupt flags +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! +//! Modified bits of \b TAxCTL register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_A_enableInterrupt(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_TAxCTL) |= TAIE; +} + +//***************************************************************************** +// +//! \brief Disable timer interrupt +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! +//! Modified bits of \b TAxCTL register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_A_disableInterrupt(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_TAxCTL) &= ~TAIE; +} + +//***************************************************************************** +// +//! \brief Get timer interrupt status +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! +//! \return One of the following: +//! - \b TIMER_A_INTERRUPT_NOT_PENDING +//! - \b TIMER_A_INTERRUPT_PENDING +//! \n indicating the TIMER_A interrupt status +// +//***************************************************************************** +uint32_t TIMER_A_getInterruptStatus(uint16_t baseAddress) +{ + return HWREG16(baseAddress + OFS_TAxCTL) & TAIFG; +} + +//***************************************************************************** +// +//! \brief Enable capture compare interrupt +//! +//! Does not clear interrupt flags +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! \param captureCompareRegister is the selected capture compare register +//! Valid values are: +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_6 +//! +//! Modified bits of \b TAxCCTLn register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_A_enableCaptureCompareInterrupt(uint16_t baseAddress, + uint16_t captureCompareRegister + ) +{ + assert((TIMER_A_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_1 == captureCompareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_2 == captureCompareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_3 == captureCompareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_4 == captureCompareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_5 == captureCompareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_6 == captureCompareRegister) + ); + + HWREG16(baseAddress + captureCompareRegister) |= CCIE; +} + +//***************************************************************************** +// +//! \brief Disable capture compare interrupt +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! \param captureCompareRegister is the selected capture compare register +//! Valid values are: +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_6 +//! +//! Modified bits of \b TAxCCTLn register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_A_disableCaptureCompareInterrupt(uint16_t baseAddress, + uint16_t captureCompareRegister + ) +{ + assert((TIMER_A_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_1 == captureCompareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_2 == captureCompareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_3 == captureCompareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_4 == captureCompareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_5 == captureCompareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_6 == captureCompareRegister) + ); + HWREG16(baseAddress + captureCompareRegister) &= ~CCIE; +} + +//***************************************************************************** +// +//! \brief Return capture compare interrupt status +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! \param captureCompareRegister is the selected capture compare register +//! Valid values are: +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_6 +//! \param mask is the mask for the interrupt status +//! Mask value is the logical OR of any of the following: +//! - \b TIMER_A_CAPTURE_OVERFLOW +//! - \b TIMER_A_CAPTURECOMPARE_INTERRUPT_FLAG +//! +//! \return Logical OR of any of the following: +//! - \b TIMER_A_CAPTURE_OVERFLOW +//! - \b TIMER_A_CAPTURECOMPARE_INTERRUPT_FLAG +//! \n indicating the status of the masked interrupts +// +//***************************************************************************** +uint32_t TIMER_A_getCaptureCompareInterruptStatus(uint16_t baseAddress, + uint16_t captureCompareRegister, + uint16_t mask + ) +{ + return HWREG16(baseAddress + captureCompareRegister) & mask; +} + +//***************************************************************************** +// +//! \brief Reset/Clear the timer clock divider, count direction, count +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! +//! Modified bits of \b TAxCTL register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_A_clear(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_TAxCTL) |= TACLR; +} + +//***************************************************************************** +// +//! \brief Get synchronized capturecompare input +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! \param captureCompareRegister +//! Valid values are: +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_6 +//! \param synchronized +//! Valid values are: +//! - \b TIMER_A_READ_SYNCHRONIZED_CAPTURECOMPAREINPUT +//! - \b TIMER_A_READ_CAPTURE_COMPARE_INPUT +//! +//! \return One of the following: +//! - \b TIMER_A_CAPTURECOMPARE_INPUT_HIGH +//! - \b TIMER_A_CAPTURECOMPARE_INPUT_LOW +// +//***************************************************************************** +uint8_t TIMER_A_getSynchronizedCaptureCompareInput + (uint16_t baseAddress, + uint16_t captureCompareRegister, + uint16_t synchronized + ) +{ + assert((TIMER_A_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_1 == captureCompareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_2 == captureCompareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_3 == captureCompareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_4 == captureCompareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_5 == captureCompareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_6 == captureCompareRegister) + ); + + assert((TIMER_A_READ_CAPTURE_COMPARE_INPUT == synchronized) || + (TIMER_A_READ_SYNCHRONIZED_CAPTURECOMPAREINPUT == synchronized) + ); + + if (HWREG16(baseAddress + captureCompareRegister) & synchronized) + return TIMER_A_CAPTURECOMPARE_INPUT_HIGH; + else + return TIMER_A_CAPTURECOMPARE_INPUT_LOW; +} + +//***************************************************************************** +// +//! \brief Get output bit for output mode +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! \param captureCompareRegister +//! Valid values are: +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_6 +//! +//! \return One of the following: +//! - \b TIMER_A_OUTPUTMODE_OUTBITVALUE_HIGH +//! - \b TIMER_A_OUTPUTMODE_OUTBITVALUE_LOW +// +//***************************************************************************** +uint8_t TIMER_A_getOutputForOutputModeOutBitValue + (uint16_t baseAddress, + uint16_t captureCompareRegister + ) +{ + assert((TIMER_A_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_1 == captureCompareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_2 == captureCompareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_3 == captureCompareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_4 == captureCompareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_5 == captureCompareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_6 == captureCompareRegister) + ); + + if (HWREG16(baseAddress + captureCompareRegister) & OUT) + return TIMER_A_OUTPUTMODE_OUTBITVALUE_HIGH; + else + return TIMER_A_OUTPUTMODE_OUTBITVALUE_LOW; +} + +//***************************************************************************** +// +//! \brief Get current capturecompare count +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! \param captureCompareRegister +//! Valid values are: +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_6 +//! +//! \return Current count as an uint16_t +// +//***************************************************************************** +uint16_t TIMER_A_getCaptureCompareCount + (uint16_t baseAddress, + uint16_t captureCompareRegister + ) +{ + assert((TIMER_A_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_1 == captureCompareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_2 == captureCompareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_3 == captureCompareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_4 == captureCompareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_5 == captureCompareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_6 == captureCompareRegister) + ); + + return HWREG16(baseAddress + OFS_TAxR + captureCompareRegister); +} + +//***************************************************************************** +// +//! \brief Set output bit for output mode +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! \param captureCompareRegister +//! Valid values are: +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_6 +//! \param outputModeOutBitValue is the value to be set for out bit +//! Valid values are: +//! - \b TIMER_A_OUTPUTMODE_OUTBITVALUE_HIGH +//! - \b TIMER_A_OUTPUTMODE_OUTBITVALUE_LOW +//! +//! Modified bits of \b TAxCCTLn register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_A_setOutputForOutputModeOutBitValue + (uint16_t baseAddress, + uint16_t captureCompareRegister, + uint8_t outputModeOutBitValue + ) +{ + assert((TIMER_A_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_1 == captureCompareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_2 == captureCompareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_3 == captureCompareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_4 == captureCompareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_5 == captureCompareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_6 == captureCompareRegister) + ); + + assert((TIMER_A_OUTPUTMODE_OUTBITVALUE_HIGH == outputModeOutBitValue) || + (TIMER_A_OUTPUTMODE_OUTBITVALUE_LOW == outputModeOutBitValue) + ); + + HWREG16(baseAddress + captureCompareRegister) &= ~OUT; + HWREG16(baseAddress + captureCompareRegister) |= outputModeOutBitValue; +} + +//***************************************************************************** +// +//! \brief Generate a PWM with timer running in up mode +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! \param param is the pointer to struct for PWM configuration. +//! +//! Modified bits of \b TAxCTL register, bits of \b TAxCCTL0 register, bits of +//! \b TAxCCR0 register and bits of \b TAxCCTLn register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_A_outputPWM(uint16_t baseAddress, TIMER_A_outputPWMParam *param) +{ + assert(param != 0); + + assert( + (TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK == param->clockSource) || + (TIMER_A_CLOCKSOURCE_ACLK == param->clockSource) || + (TIMER_A_CLOCKSOURCE_SMCLK == param->clockSource) || + (TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK == param->clockSource) + ); + + assert((TIMER_A_CAPTURECOMPARE_REGISTER_0 == param->compareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_1 == param->compareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_2 == param->compareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_3 == param->compareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_4 == param->compareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_5 == param->compareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_6 == param->compareRegister) + ); + + assert((TIMER_A_OUTPUTMODE_OUTBITVALUE == param->compareOutputMode) || + (TIMER_A_OUTPUTMODE_SET == param->compareOutputMode) || + (TIMER_A_OUTPUTMODE_TOGGLE_RESET == param->compareOutputMode) || + (TIMER_A_OUTPUTMODE_SET_RESET == param->compareOutputMode) || + (TIMER_A_OUTPUTMODE_TOGGLE == param->compareOutputMode) || + (TIMER_A_OUTPUTMODE_RESET == param->compareOutputMode) || + (TIMER_A_OUTPUTMODE_TOGGLE_SET == param->compareOutputMode) || + (TIMER_A_OUTPUTMODE_RESET_SET == param->compareOutputMode) + ); + + HWREG16(baseAddress + OFS_TAxCTL) &= + ~( TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK + + TIMER_A_UPDOWN_MODE + TIMER_A_DO_CLEAR + + TIMER_A_TAIE_INTERRUPT_ENABLE + + ID__8 + ); + HWREG16(baseAddress + OFS_TAxEX0) &= ~TAIDEX_7; + + HWREG16(baseAddress + OFS_TAxEX0) |= param->clockSourceDivider & 0x7; + HWREG16(baseAddress + OFS_TAxCTL) |= (param->clockSource + + TIMER_A_UP_MODE + + TIMER_A_DO_CLEAR + + ((param->clockSourceDivider >> 3) << 6)); + + HWREG16(baseAddress + OFS_TAxCCR0) = param->timerPeriod; + + HWREG16(baseAddress + OFS_TAxCCTL0) &= + ~(TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE + + TIMER_A_OUTPUTMODE_RESET_SET + ); + HWREG16(baseAddress + param->compareRegister) |= param->compareOutputMode; + + HWREG16(baseAddress + param->compareRegister + OFS_TAxR) = param->dutyCycle; +} //***************************************************************************** +// +//! \brief DEPRECATED - Generate a PWM with timer running in up mode +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! \param clockSource selects Clock source. +//! Valid values are: +//! - \b TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK [Default] +//! - \b TIMER_A_CLOCKSOURCE_ACLK +//! - \b TIMER_A_CLOCKSOURCE_SMCLK +//! - \b TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK +//! \param clockSourceDivider is the desired divider for the clock source +//! Valid values are: +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_1 [Default] +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_2 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_3 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_4 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_5 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_6 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_7 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_8 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_10 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_12 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_14 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_16 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_20 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_24 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_28 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_32 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_40 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_48 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_56 +//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_64 +//! \param timerPeriod selects the desired timer period +//! \param compareRegister selects the compare register being used. Refer to +//! datasheet to ensure the device has the capture compare register +//! being used. +//! Valid values are: +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_6 +//! \param compareOutputMode specifies the output mode. +//! Valid values are: +//! - \b TIMER_A_OUTPUTMODE_OUTBITVALUE [Default] +//! - \b TIMER_A_OUTPUTMODE_SET +//! - \b TIMER_A_OUTPUTMODE_TOGGLE_RESET +//! - \b TIMER_A_OUTPUTMODE_SET_RESET +//! - \b TIMER_A_OUTPUTMODE_TOGGLE +//! - \b TIMER_A_OUTPUTMODE_RESET +//! - \b TIMER_A_OUTPUTMODE_TOGGLE_SET +//! - \b TIMER_A_OUTPUTMODE_RESET_SET +//! \param dutyCycle specifies the dutycycle for the generated waveform +//! +//! Modified bits of \b TAxCTL register, bits of \b TAxCCTL0 register, bits of +//! \b TAxCCR0 register and bits of \b TAxCCTLn register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_A_generatePWM(uint16_t baseAddress, + uint16_t clockSource, + uint16_t clockSourceDivider, + uint16_t timerPeriod, + uint16_t compareRegister, + uint16_t compareOutputMode, + uint16_t dutyCycle + ) +{ + TIMER_A_outputPWMParam param = { 0 }; + + param.clockSource = clockSource; + param.clockSourceDivider = clockSourceDivider; + param.timerPeriod = timerPeriod; + param.compareRegister = compareRegister; + param.compareOutputMode = compareOutputMode; + param.dutyCycle = dutyCycle; + + TIMER_A_outputPWM(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Stops the timer +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! +//! Modified bits of \b TAxCTL register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_A_stop( uint16_t baseAddress ) +{ + HWREG16(baseAddress + OFS_TAxCTL) &= ~MC_3; + HWREG16(baseAddress + OFS_TAxCTL) |= MC_0; +} + +//***************************************************************************** +// +//! \brief Sets the value of the capture-compare register +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! \param compareRegister selects the Capture register being used. Refer to +//! datasheet to ensure the device has the capture compare register +//! being used. +//! Valid values are: +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_6 +//! \param compareValue is the count to be compared with in compare mode +//! +//! Modified bits of \b TAxCCRn register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_A_setCompareValue( uint16_t baseAddress, + uint16_t compareRegister, + uint16_t compareValue + ) +{ + assert((TIMER_A_CAPTURECOMPARE_REGISTER_0 == compareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_1 == compareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_2 == compareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_3 == compareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_4 == compareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_5 == compareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_6 == compareRegister) + ); + + HWREG16(baseAddress + compareRegister + OFS_TAxR) = compareValue; +} + +//***************************************************************************** +// +//! \brief Clears the Timer TAIFG interrupt flag +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! +//! Modified bits are \b TAIFG of \b TAxCTL register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_A_clearTimerInterruptFlag(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_TAxCTL) &= ~TAIFG; +} + +//***************************************************************************** +// +//! \brief Clears the capture-compare interrupt flag +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! \param captureCompareRegister selects the Capture-compare register being +//! used. +//! Valid values are: +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_6 +//! +//! Modified bits are \b CCIFG of \b TAxCCTLn register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_A_clearCaptureCompareInterruptFlag(uint16_t baseAddress, + uint16_t captureCompareRegister + ) +{ + assert((TIMER_A_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_1 == captureCompareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_2 == captureCompareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_3 == captureCompareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_4 == captureCompareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_5 == captureCompareRegister) || + (TIMER_A_CAPTURECOMPARE_REGISTER_6 == captureCompareRegister) + ); + + HWREG16(baseAddress + captureCompareRegister) &= ~CCIFG; +} + +//***************************************************************************** +// +//! \brief Reads the current timer count value +//! +//! Reads the current count value of the timer. There is a majority vote system +//! in place to confirm an accurate value is returned. The TIMER_A_THRESHOLD +//! #define in the corresponding header file can be modified so that the votes +//! must be closer together for a consensus to occur. +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! +//! \return Majority vote of timer count value +// +//***************************************************************************** +uint16_t TIMER_A_getCounterValue(uint16_t baseAddress) +{ + uint16_t voteOne, voteTwo, res; + + voteTwo = HWREG16(baseAddress + OFS_TAxR); + + do { + voteOne = voteTwo; + voteTwo = HWREG16(baseAddress + OFS_TAxR); + + if (voteTwo > voteOne) + res = voteTwo - voteOne; + else if (voteOne > voteTwo) + res = voteOne - voteTwo; + else + res = 0; + + } while ( res > TIMER_A_THRESHOLD); + + return voteTwo; +} + + +#endif +//***************************************************************************** +// +//! Close the doxygen group for timer_a_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/timer_a.h b/source/driverlib/MSP430F5xx_6xx/timer_a.h new file mode 100644 index 0000000..4eff307 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/timer_a.h @@ -0,0 +1,525 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// timer_a.h - Driver for the TIMER_A Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_TIMER_A_H__ +#define __MSP430WARE_TIMER_A_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_TxA7__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//****************************************************************************** +// +// The following is a struct that is passed to TIMER_A_initContinuousMode() +// +//****************************************************************************** +typedef struct TIMER_A_initContinuousModeParam { + uint16_t clockSource; + uint16_t clockSourceDivider; + uint16_t timerInterruptEnable_TAIE; + uint16_t timerClear; + bool startTimer; +} TIMER_A_initContinuousModeParam; + +//****************************************************************************** +// +// The following is a struct that is passed to TIMER_A_initUpMode() +// +//****************************************************************************** +typedef struct TIMER_A_initUpModeParam { + uint16_t clockSource; + uint16_t clockSourceDivider; + uint16_t timerPeriod; + uint16_t timerInterruptEnable_TAIE; + uint16_t captureCompareInterruptEnable_CCR0_CCIE; + uint16_t timerClear; + bool startTimer; +} TIMER_A_initUpModeParam; + +//****************************************************************************** +// +// The following is a struct that is passed to TIMER_A_initUpDownMode() +// +//****************************************************************************** +typedef struct TIMER_A_initUpDownModeParam { + uint16_t clockSource; + uint16_t clockSourceDivider; + uint16_t timerPeriod; + uint16_t timerInterruptEnable_TAIE; + uint16_t captureCompareInterruptEnable_CCR0_CCIE; + uint16_t timerClear; + bool startTimer; +} TIMER_A_initUpDownModeParam; + +//****************************************************************************** +// +// The following is a struct that is passed to TIMER_A_initCaptureMode() +// +//****************************************************************************** +typedef struct TIMER_A_initCaptureModeParam { + uint16_t captureRegister; + uint16_t captureMode; + uint16_t captureInputSelect; + uint16_t synchronizeCaptureSource; + uint16_t captureInterruptEnable; + uint16_t captureOutputMode; +} TIMER_A_initCaptureModeParam; + +//****************************************************************************** +// +// The following is a struct that is passed to TIMER_A_initCompareMode() +// +//****************************************************************************** +typedef struct TIMER_A_initCompareModeParam { + uint16_t compareRegister; + uint16_t compareInterruptEnable; + uint16_t compareOutputMode; + uint16_t compareValue; +} TIMER_A_initCompareModeParam; + +//****************************************************************************** +// +// The following is a struct that is passed to TIMER_A_outputPWM() +// +//****************************************************************************** +typedef struct TIMER_A_outputPWMParam { + uint16_t clockSource; + uint16_t clockSourceDivider; + uint16_t timerPeriod; + uint16_t compareRegister; + uint16_t compareOutputMode; + uint16_t dutyCycle; +} TIMER_A_outputPWMParam; + +//***************************************************************************** +// +// The following is a parameter used for TIMER_A_getCounterValue that +// determines the maximum difference in counts of the TAxR register for a +// majority vote. +// +//***************************************************************************** +#define TIMER_A_THRESHOLD 50 + +//***************************************************************************** +// +// The following are values that can be passed to the clockSourceDivider +// parameter for functions: TIMER_A_configureContinuousMode(), +// TIMER_A_configureUpMode(), TIMER_A_configureUpDownMode(), +// TIMER_A_startContinuousMode(), TIMER_A_startContinousMode(), +// TIMER_A_startUpMode(), TIMER_A_startUpDownMode(), and TIMER_A_generatePWM(). +// +//***************************************************************************** +#define TIMER_A_CLOCKSOURCE_DIVIDER_1 0x00 +#define TIMER_A_CLOCKSOURCE_DIVIDER_2 0x08 +#define TIMER_A_CLOCKSOURCE_DIVIDER_3 0x02 +#define TIMER_A_CLOCKSOURCE_DIVIDER_4 0x10 +#define TIMER_A_CLOCKSOURCE_DIVIDER_5 0x04 +#define TIMER_A_CLOCKSOURCE_DIVIDER_6 0x05 +#define TIMER_A_CLOCKSOURCE_DIVIDER_7 0x06 +#define TIMER_A_CLOCKSOURCE_DIVIDER_8 0x18 +#define TIMER_A_CLOCKSOURCE_DIVIDER_10 0x0C +#define TIMER_A_CLOCKSOURCE_DIVIDER_12 0x0D +#define TIMER_A_CLOCKSOURCE_DIVIDER_14 0x0E +#define TIMER_A_CLOCKSOURCE_DIVIDER_16 0x0F +#define TIMER_A_CLOCKSOURCE_DIVIDER_20 0x14 +#define TIMER_A_CLOCKSOURCE_DIVIDER_24 0x15 +#define TIMER_A_CLOCKSOURCE_DIVIDER_28 0x16 +#define TIMER_A_CLOCKSOURCE_DIVIDER_32 0x17 +#define TIMER_A_CLOCKSOURCE_DIVIDER_40 0x1C +#define TIMER_A_CLOCKSOURCE_DIVIDER_48 0x1D +#define TIMER_A_CLOCKSOURCE_DIVIDER_56 0x1E +#define TIMER_A_CLOCKSOURCE_DIVIDER_64 0x1F + +//***************************************************************************** +// +// The following are values that can be passed to the timerMode parameter for +// functions: TIMER_A_startCounter(). +// +//***************************************************************************** +#define TIMER_A_STOP_MODE MC_0 +#define TIMER_A_UP_MODE MC_1 +#define TIMER_A_CONTINUOUS_MODE MC_2 +#define TIMER_A_UPDOWN_MODE MC_3 + +//***************************************************************************** +// +// The following are values that can be passed to the timerClear parameter for +// functions: TIMER_A_configureContinuousMode(), TIMER_A_configureUpMode(), +// TIMER_A_configureUpDownMode(), TIMER_A_startContinuousMode(), +// TIMER_A_startContinousMode(), TIMER_A_startUpMode(), and +// TIMER_A_startUpDownMode(). +// +//***************************************************************************** +#define TIMER_A_DO_CLEAR TACLR +#define TIMER_A_SKIP_CLEAR 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the clockSource parameter for +// functions: TIMER_A_configureContinuousMode(), TIMER_A_configureUpMode(), +// TIMER_A_configureUpDownMode(), TIMER_A_startContinuousMode(), +// TIMER_A_startContinousMode(), TIMER_A_startUpMode(), +// TIMER_A_startUpDownMode(), and TIMER_A_generatePWM(). +// +//***************************************************************************** +#define TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK TASSEL__TACLK +#define TIMER_A_CLOCKSOURCE_ACLK TASSEL__ACLK +#define TIMER_A_CLOCKSOURCE_SMCLK TASSEL__SMCLK +#define TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK TASSEL__INCLK + +//***************************************************************************** +// +// The following are values that can be passed to the timerInterruptEnable_TAIE +// parameter for functions: TIMER_A_configureContinuousMode(), +// TIMER_A_configureUpMode(), TIMER_A_configureUpDownMode(), +// TIMER_A_startContinuousMode(), TIMER_A_startContinousMode(), +// TIMER_A_startUpMode(), and TIMER_A_startUpDownMode(). +// +//***************************************************************************** +#define TIMER_A_TAIE_INTERRUPT_ENABLE TAIE +#define TIMER_A_TAIE_INTERRUPT_DISABLE 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the +// captureCompareInterruptEnable_CCR0_CCIE parameter for functions: +// TIMER_A_configureUpMode(), TIMER_A_configureUpDownMode(), +// TIMER_A_startUpMode(), and TIMER_A_startUpDownMode(). +// +//***************************************************************************** +#define TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE CCIE +#define TIMER_A_CCIE_CCR0_INTERRUPT_DISABLE 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the captureInterruptEnable +// parameter for functions: TIMER_A_initCapture(); the compareInterruptEnable +// parameter for functions: TIMER_A_initCompare(). +// +//***************************************************************************** +#define TIMER_A_CAPTURECOMPARE_INTERRUPT_DISABLE 0x00 +#define TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE CCIE + +//***************************************************************************** +// +// The following are values that can be passed to the captureInputSelect +// parameter for functions: TIMER_A_initCapture(). +// +//***************************************************************************** +#define TIMER_A_CAPTURE_INPUTSELECT_CCIxA CCIS_0 +#define TIMER_A_CAPTURE_INPUTSELECT_CCIxB CCIS_1 +#define TIMER_A_CAPTURE_INPUTSELECT_GND CCIS_2 +#define TIMER_A_CAPTURE_INPUTSELECT_Vcc CCIS_3 + +//***************************************************************************** +// +// The following are values that can be passed to the compareOutputMode +// parameter for functions: TIMER_A_initCompare(), and TIMER_A_generatePWM(); +// the captureOutputMode parameter for functions: TIMER_A_initCapture(). +// +//***************************************************************************** +#define TIMER_A_OUTPUTMODE_OUTBITVALUE OUTMOD_0 +#define TIMER_A_OUTPUTMODE_SET OUTMOD_1 +#define TIMER_A_OUTPUTMODE_TOGGLE_RESET OUTMOD_2 +#define TIMER_A_OUTPUTMODE_SET_RESET OUTMOD_3 +#define TIMER_A_OUTPUTMODE_TOGGLE OUTMOD_4 +#define TIMER_A_OUTPUTMODE_RESET OUTMOD_5 +#define TIMER_A_OUTPUTMODE_TOGGLE_SET OUTMOD_6 +#define TIMER_A_OUTPUTMODE_RESET_SET OUTMOD_7 + +//***************************************************************************** +// +// The following are values that can be passed to the compareRegister parameter +// for functions: TIMER_A_initCompare(), TIMER_A_generatePWM(), and +// TIMER_A_setCompareValue(); the captureCompareRegister parameter for +// functions: TIMER_A_enableCaptureCompareInterrupt(), +// TIMER_A_disableCaptureCompareInterrupt(), +// TIMER_A_getCaptureCompareInterruptStatus(), +// TIMER_A_getSynchronizedCaptureCompareInput(), +// TIMER_A_getOutputForOutputModeOutBitValue(), +// TIMER_A_getCaptureCompareCount(), +// TIMER_A_setOutputForOutputModeOutBitValue(), and +// TIMER_A_clearCaptureCompareInterruptFlag(); the captureRegister parameter +// for functions: TIMER_A_initCapture(). +// +//***************************************************************************** +#define TIMER_A_CAPTURECOMPARE_REGISTER_0 0x02 +#define TIMER_A_CAPTURECOMPARE_REGISTER_1 0x04 +#define TIMER_A_CAPTURECOMPARE_REGISTER_2 0x06 +#define TIMER_A_CAPTURECOMPARE_REGISTER_3 0x08 +#define TIMER_A_CAPTURECOMPARE_REGISTER_4 0x0A +#define TIMER_A_CAPTURECOMPARE_REGISTER_5 0x0C +#define TIMER_A_CAPTURECOMPARE_REGISTER_6 0x0E + +//***************************************************************************** +// +// The following are values that can be passed to the captureMode parameter for +// functions: TIMER_A_initCapture(). +// +//***************************************************************************** +#define TIMER_A_CAPTUREMODE_NO_CAPTURE CM_0 +#define TIMER_A_CAPTUREMODE_RISING_EDGE CM_1 +#define TIMER_A_CAPTUREMODE_FALLING_EDGE CM_2 +#define TIMER_A_CAPTUREMODE_RISING_AND_FALLING_EDGE CM_3 + +//***************************************************************************** +// +// The following are values that can be passed to the synchronizeCaptureSource +// parameter for functions: TIMER_A_initCapture(). +// +//***************************************************************************** +#define TIMER_A_CAPTURE_ASYNCHRONOUS 0x00 +#define TIMER_A_CAPTURE_SYNCHRONOUS SCS + +//***************************************************************************** +// +// The following are values that can be passed to the mask parameter for +// functions: TIMER_A_getCaptureCompareInterruptStatus() as well as returned by +// the TIMER_A_getCaptureCompareInterruptStatus() function. +// +//***************************************************************************** +#define TIMER_A_CAPTURE_OVERFLOW COV +#define TIMER_A_CAPTURECOMPARE_INTERRUPT_FLAG CCIFG + +//***************************************************************************** +// +// The following are values that can be passed to the synchronized parameter +// for functions: TIMER_A_getSynchronizedCaptureCompareInput(). +// +//***************************************************************************** +#define TIMER_A_READ_SYNCHRONIZED_CAPTURECOMPAREINPUT SCCI +#define TIMER_A_READ_CAPTURE_COMPARE_INPUT CCI + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the TIMER_A_getSynchronizedCaptureCompareInput() +// function. +// +//***************************************************************************** +#define TIMER_A_CAPTURECOMPARE_INPUT_HIGH 0x01 +#define TIMER_A_CAPTURECOMPARE_INPUT_LOW 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the outputModeOutBitValue +// parameter for functions: TIMER_A_setOutputForOutputModeOutBitValue() as well +// as returned by the TIMER_A_getOutputForOutputModeOutBitValue() function. +// +//***************************************************************************** +#define TIMER_A_OUTPUTMODE_OUTBITVALUE_HIGH OUT +#define TIMER_A_OUTPUTMODE_OUTBITVALUE_LOW 0x00 + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the TIMER_A_getInterruptStatus() function. +// +//***************************************************************************** +#define TIMER_A_INTERRUPT_NOT_PENDING 0x00 +#define TIMER_A_INTERRUPT_PENDING 0x01 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void TIMER_A_startCounter(uint16_t baseAddress, + uint16_t timerMode); + +extern void TIMER_A_initContinuousMode(uint16_t baseAddress, + TIMER_A_initContinuousModeParam *param); + +extern void TIMER_A_initUpMode(uint16_t baseAddress, + TIMER_A_initUpModeParam *param); + +extern void TIMER_A_initUpDownMode(uint16_t baseAddress, + TIMER_A_initUpDownModeParam *param); + +extern void TIMER_A_initCaptureMode(uint16_t baseAddress, + TIMER_A_initCaptureModeParam *param); + +extern void TIMER_A_initCompareMode(uint16_t baseAddress, + TIMER_A_initCompareModeParam *param); + +extern void TIMER_A_enableInterrupt(uint16_t baseAddress); + +extern void TIMER_A_disableInterrupt(uint16_t baseAddress); + +extern uint32_t TIMER_A_getInterruptStatus(uint16_t baseAddress); + +extern void TIMER_A_enableCaptureCompareInterrupt(uint16_t baseAddress, + uint16_t captureCompareRegister); + +extern void TIMER_A_disableCaptureCompareInterrupt(uint16_t baseAddress, + uint16_t captureCompareRegister); + +extern uint32_t TIMER_A_getCaptureCompareInterruptStatus(uint16_t baseAddress, + uint16_t captureCompareRegister, + uint16_t mask); + +extern void TIMER_A_clear(uint16_t baseAddress); + +extern uint8_t TIMER_A_getSynchronizedCaptureCompareInput(uint16_t baseAddress, + uint16_t captureCompareRegister, + uint16_t synchronized); + +extern uint8_t TIMER_A_getOutputForOutputModeOutBitValue(uint16_t baseAddress, + uint16_t captureCompareRegister); + +extern uint16_t TIMER_A_getCaptureCompareCount(uint16_t baseAddress, + uint16_t captureCompareRegister); + +extern void TIMER_A_setOutputForOutputModeOutBitValue(uint16_t baseAddress, + uint16_t captureCompareRegister, + uint8_t outputModeOutBitValue); + +extern void TIMER_A_outputPWM(uint16_t baseAddress, + TIMER_A_outputPWMParam *param); + +extern void TIMER_A_stop(uint16_t baseAddress); + +extern void TIMER_A_setCompareValue(uint16_t baseAddress, + uint16_t compareRegister, + uint16_t compareValue); + +extern void TIMER_A_clearTimerInterruptFlag(uint16_t baseAddress); + +extern void TIMER_A_clearCaptureCompareInterruptFlag(uint16_t baseAddress, + uint16_t captureCompareRegister); + +extern uint16_t TIMER_A_getCounterValue(uint16_t baseAddress); + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +extern void TIMER_A_configureContinuousMode(uint16_t baseAddress, + uint16_t clockSource, + uint16_t clockSourceDivider, + uint16_t timerInterruptEnable_TAIE, + uint16_t timerClear); + +extern void TIMER_A_configureUpMode(uint16_t baseAddress, + uint16_t clockSource, + uint16_t clockSourceDivider, + uint16_t timerPeriod, + uint16_t timerInterruptEnable_TAIE, + uint16_t captureCompareInterruptEnable_CCR0_CCIE, + uint16_t timerClear); + +extern void TIMER_A_configureUpDownMode(uint16_t baseAddress, + uint16_t clockSource, + uint16_t clockSourceDivider, + uint16_t timerPeriod, + uint16_t timerInterruptEnable_TAIE, + uint16_t captureCompareInterruptEnable_CCR0_CCIE, + uint16_t timerClear); + +extern void TIMER_A_startContinuousMode(uint16_t baseAddress, + uint16_t clockSource, + uint16_t clockSourceDivider, + uint16_t timerInterruptEnable_TAIE, + uint16_t timerClear); + +extern void TIMER_A_startContinousMode(uint16_t baseAddress, + uint16_t clockSource, + uint16_t clockSourceDivider, + uint16_t timerInterruptEnable_TAIE, + uint16_t timerClear); + +extern void TIMER_A_startUpMode(uint16_t baseAddress, + uint16_t clockSource, + uint16_t clockSourceDivider, + uint16_t timerPeriod, + uint16_t timerInterruptEnable_TAIE, + uint16_t captureCompareInterruptEnable_CCR0_CCIE, + uint16_t timerClear); + +extern void TIMER_A_startUpDownMode(uint16_t baseAddress, + uint16_t clockSource, + uint16_t clockSourceDivider, + uint16_t timerPeriod, + uint16_t timerInterruptEnable_TAIE, + uint16_t captureCompareInterruptEnable_CCR0_CCIE, + uint16_t timerClear); + +extern void TIMER_A_initCapture(uint16_t baseAddress, + uint16_t captureRegister, + uint16_t captureMode, + uint16_t captureInputSelect, + uint16_t synchronizeCaptureSource, + uint16_t captureInterruptEnable, + uint16_t captureOutputMode); + +extern void TIMER_A_initCompare(uint16_t baseAddress, + uint16_t compareRegister, + uint16_t compareInterruptEnable, + uint16_t compareOutputMode, + uint16_t compareValue); + +extern void TIMER_A_generatePWM(uint16_t baseAddress, + uint16_t clockSource, + uint16_t clockSourceDivider, + uint16_t timerPeriod, + uint16_t compareRegister, + uint16_t compareOutputMode, + uint16_t dutyCycle); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_TIMER_A_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/timer_b.c b/source/driverlib/MSP430F5xx_6xx/timer_b.c new file mode 100644 index 0000000..b2d3b07 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/timer_b.c @@ -0,0 +1,1860 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// timer_b.c - Driver for the timer_b Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup timer_b_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_TxB7__ +#include "timer_b.h" + +#include + +//***************************************************************************** +// +//! \brief Starts TIMER_B counter +//! +//! This function assumes that the timer has been previously configured using +//! TIMER_B_configureContinuousMode, TIMER_B_configureUpMode or +//! TIMER_B_configureUpDownMode. +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param timerMode selects the mode of the timer +//! Valid values are: +//! - \b TIMER_B_STOP_MODE +//! - \b TIMER_B_UP_MODE +//! - \b TIMER_B_CONTINUOUS_MODE [Default] +//! - \b TIMER_B_UPDOWN_MODE +//! +//! Modified bits of \b TBxCTL register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_B_startCounter( uint16_t baseAddress, + uint16_t timerMode + ) +{ + assert( + (TIMER_B_UPDOWN_MODE == timerMode) || + (TIMER_B_CONTINUOUS_MODE == timerMode) || + (TIMER_B_UP_MODE == timerMode) + ); + + HWREG16(baseAddress + OFS_TBxCTL) |= timerMode; +} + +//***************************************************************************** +// +//! \brief Configures TIMER_B in continuous mode. +//! +//! This API does not start the timer. Timer needs to be started when required +//! using the TIMER_B_startCounter API. +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param param is the pointer to struct for continuous mode initialization. +//! +//! Modified bits of \b TBxCTL register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_B_initContinuousMode(uint16_t baseAddress, + TIMER_B_initContinuousModeParam *param) +{ + assert(param != 0); + + assert( + (TIMER_B_CLOCKSOURCE_EXTERNAL_TXCLK == param->clockSource) || + (TIMER_B_CLOCKSOURCE_ACLK == param->clockSource) || + (TIMER_B_CLOCKSOURCE_SMCLK == param->clockSource) || + (TIMER_B_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK == param->clockSource) + ); + + assert( + (TIMER_B_DO_CLEAR == param->timerClear) || + (TIMER_B_SKIP_CLEAR == param->timerClear) + ); + + assert( + (TIMER_B_TBIE_INTERRUPT_ENABLE == param->timerInterruptEnable_TBIE) || + (TIMER_B_TBIE_INTERRUPT_DISABLE == param->timerInterruptEnable_TBIE) + ); + + assert( + (TIMER_B_CLOCKSOURCE_DIVIDER_1 == param->clockSourceDivider) || + (TIMER_B_CLOCKSOURCE_DIVIDER_2 == param->clockSourceDivider) || + (TIMER_B_CLOCKSOURCE_DIVIDER_4 == param->clockSourceDivider) || + (TIMER_B_CLOCKSOURCE_DIVIDER_8 == param->clockSourceDivider) || + (TIMER_B_CLOCKSOURCE_DIVIDER_3 == param->clockSourceDivider) || + (TIMER_B_CLOCKSOURCE_DIVIDER_5 == param->clockSourceDivider) || + (TIMER_B_CLOCKSOURCE_DIVIDER_6 == param->clockSourceDivider) || + (TIMER_B_CLOCKSOURCE_DIVIDER_7 == param->clockSourceDivider) || + (TIMER_B_CLOCKSOURCE_DIVIDER_10 == param->clockSourceDivider) || + (TIMER_B_CLOCKSOURCE_DIVIDER_12 == param->clockSourceDivider) || + (TIMER_B_CLOCKSOURCE_DIVIDER_14 == param->clockSourceDivider) || + (TIMER_B_CLOCKSOURCE_DIVIDER_16 == param->clockSourceDivider) || + (TIMER_B_CLOCKSOURCE_DIVIDER_20 == param->clockSourceDivider) || + (TIMER_B_CLOCKSOURCE_DIVIDER_24 == param->clockSourceDivider) || + (TIMER_B_CLOCKSOURCE_DIVIDER_28 == param->clockSourceDivider) || + (TIMER_B_CLOCKSOURCE_DIVIDER_32 == param->clockSourceDivider) || + (TIMER_B_CLOCKSOURCE_DIVIDER_40 == param->clockSourceDivider) || + (TIMER_B_CLOCKSOURCE_DIVIDER_48 == param->clockSourceDivider) || + (TIMER_B_CLOCKSOURCE_DIVIDER_56 == param->clockSourceDivider) || + (TIMER_B_CLOCKSOURCE_DIVIDER_64 == param->clockSourceDivider) + ); + + HWREG16(baseAddress + + OFS_TBxCTL) &= ~(TIMER_B_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK + + TIMER_B_UPDOWN_MODE + + TIMER_B_DO_CLEAR + + TIMER_B_TBIE_INTERRUPT_ENABLE + + CNTL_3 + + ID__8 + ); + HWREG16(baseAddress + OFS_TBxEX0) &= ~TBIDEX_7; + + HWREG16(baseAddress + OFS_TBxEX0) |= param->clockSourceDivider & 0x7; + + HWREG16(baseAddress + OFS_TBxCTL) |= (param->clockSource + + param->timerClear + + param->timerInterruptEnable_TBIE + + ((param->clockSourceDivider >> 3) << 6)); + + if (param->startTimer) + HWREG16(baseAddress + OFS_TBxCTL) |= TIMER_B_CONTINUOUS_MODE; +} + +//***************************************************************************** +// +//! \brief DEPRECATED - Configures TIMER_B in continuous mode. +//! +//! This API does not start the timer. Timer needs to be started when required +//! using the TIMER_B_startCounter API. +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param clockSource selects the clock source +//! Valid values are: +//! - \b TIMER_B_CLOCKSOURCE_EXTERNAL_TXCLK [Default] +//! - \b TIMER_B_CLOCKSOURCE_ACLK +//! - \b TIMER_B_CLOCKSOURCE_SMCLK +//! - \b TIMER_B_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK +//! \param clockSourceDivider is the divider for Clock source. +//! Valid values are: +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_1 [Default] +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_2 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_3 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_4 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_5 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_6 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_7 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_8 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_10 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_12 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_14 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_16 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_20 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_24 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_28 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_32 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_40 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_48 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_56 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_64 +//! \param timerInterruptEnable_TBIE is to enable or disable TIMER_B interrupt +//! Valid values are: +//! - \b TIMER_B_TBIE_INTERRUPT_ENABLE +//! - \b TIMER_B_TBIE_INTERRUPT_DISABLE [Default] +//! \param timerClear decides if TIMER_B clock divider, count direction, count +//! need to be reset. +//! Valid values are: +//! - \b TIMER_B_DO_CLEAR +//! - \b TIMER_B_SKIP_CLEAR [Default] +//! +//! Modified bits of \b TBxCTL register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_B_configureContinuousMode( uint16_t baseAddress, + uint16_t clockSource, + uint16_t clockSourceDivider, + uint16_t timerInterruptEnable_TBIE, + uint16_t timerClear + ) +{ + TIMER_B_initContinuousModeParam param = { 0 }; + + param.clockSource = clockSource; + param.clockSourceDivider = clockSourceDivider; + param.timerInterruptEnable_TBIE = timerInterruptEnable_TBIE; + param.timerClear = timerClear; + param.startTimer = false; + + TIMER_B_initContinuousMode(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Configures TIMER_B in up mode. +//! +//! This API does not start the timer. Timer needs to be started when required +//! using the TIMER_B_startCounter API. +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param param is the pointer to struct for up mode initialization. +//! +//! Modified bits of \b TBxCTL register, bits of \b TBxCCTL0 register and bits +//! of \b TBxCCR0 register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_B_initUpMode(uint16_t baseAddress, + TIMER_B_initUpModeParam *param) +{ + assert(param != 0); + + assert( + (TIMER_B_CLOCKSOURCE_EXTERNAL_TXCLK == param->clockSource) || + (TIMER_B_CLOCKSOURCE_ACLK == param->clockSource) || + (TIMER_B_CLOCKSOURCE_SMCLK == param->clockSource) || + (TIMER_B_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK == param->clockSource) + ); + + assert( + (TIMER_B_DO_CLEAR == param->timerClear) || + (TIMER_B_SKIP_CLEAR == param->timerClear) + ); + + assert( + (TIMER_B_DO_CLEAR == param->timerClear) || + (TIMER_B_SKIP_CLEAR == param->timerClear) + ); + + HWREG16(baseAddress + OFS_TBxCTL) &= + ~(TIMER_B_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK + + TIMER_B_UPDOWN_MODE + + TIMER_B_DO_CLEAR + + TIMER_B_TBIE_INTERRUPT_ENABLE + + CNTL_3 + ); + HWREG16(baseAddress + OFS_TBxEX0) &= ~TBIDEX_7; + + HWREG16(baseAddress + OFS_TBxEX0) |= param->clockSourceDivider & 0x7; + + HWREG16(baseAddress + OFS_TBxCTL) |= (param->clockSource + + param->timerClear + + param->timerInterruptEnable_TBIE + + ((param->clockSourceDivider >> 3) << 6)); + + if (param->startTimer) + HWREG16(baseAddress + OFS_TBxCTL) |= TIMER_B_UP_MODE; + + if (TIMER_B_CCIE_CCR0_INTERRUPT_ENABLE == + param->captureCompareInterruptEnable_CCR0_CCIE) + HWREG16(baseAddress + OFS_TBxCCTL0) |= TIMER_B_CCIE_CCR0_INTERRUPT_ENABLE; + else + HWREG16(baseAddress + OFS_TBxCCTL0) &= ~TIMER_B_CCIE_CCR0_INTERRUPT_ENABLE; + + HWREG16(baseAddress + OFS_TBxCCR0) = param->timerPeriod; +} + +//***************************************************************************** +// +//! \brief DEPRECATED - Configures TIMER_B in up mode. +//! +//! This API does not start the timer. Timer needs to be started when required +//! using the TIMER_B_startCounter API. +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param clockSource selects the clock source +//! Valid values are: +//! - \b TIMER_B_CLOCKSOURCE_EXTERNAL_TXCLK [Default] +//! - \b TIMER_B_CLOCKSOURCE_ACLK +//! - \b TIMER_B_CLOCKSOURCE_SMCLK +//! - \b TIMER_B_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK +//! \param clockSourceDivider is the divider for Clock source. +//! Valid values are: +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_1 [Default] +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_2 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_3 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_4 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_5 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_6 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_7 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_8 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_10 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_12 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_14 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_16 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_20 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_24 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_28 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_32 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_40 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_48 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_56 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_64 +//! \param timerPeriod is the specified TIMER_B period. This is the value that +//! gets written into the CCR0. Limited to 16 bits[uint16_t] +//! \param timerInterruptEnable_TBIE is to enable or disable TIMER_B interrupt +//! Valid values are: +//! - \b TIMER_B_TBIE_INTERRUPT_ENABLE +//! - \b TIMER_B_TBIE_INTERRUPT_DISABLE [Default] +//! \param captureCompareInterruptEnable_CCR0_CCIE is to enable or disable +//! TIMER_B CCR0 capture compare interrupt. +//! Valid values are: +//! - \b TIMER_B_CCIE_CCR0_INTERRUPT_ENABLE +//! - \b TIMER_B_CCIE_CCR0_INTERRUPT_DISABLE [Default] +//! \param timerClear decides if TIMER_B clock divider, count direction, count +//! need to be reset. +//! Valid values are: +//! - \b TIMER_B_DO_CLEAR +//! - \b TIMER_B_SKIP_CLEAR [Default] +//! +//! Modified bits of \b TBxCTL register, bits of \b TBxCCTL0 register and bits +//! of \b TBxCCR0 register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_B_configureUpMode( uint16_t baseAddress, + uint16_t clockSource, + uint16_t clockSourceDivider, + uint16_t timerPeriod, + uint16_t timerInterruptEnable_TBIE, + uint16_t captureCompareInterruptEnable_CCR0_CCIE, + uint16_t timerClear + ) +{ + TIMER_B_initUpModeParam param = { 0 }; + + param.clockSource = clockSource; + param.clockSourceDivider = clockSourceDivider; + param.timerPeriod = timerPeriod; + param.timerInterruptEnable_TBIE = timerInterruptEnable_TBIE; + param.captureCompareInterruptEnable_CCR0_CCIE = + captureCompareInterruptEnable_CCR0_CCIE; + param.timerClear = timerClear; + param.startTimer = false; + + TIMER_B_initUpMode(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Configures TIMER_B in up down mode. +//! +//! This API does not start the timer. Timer needs to be started when required +//! using the TIMER_B_startCounter API. +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param param is the pointer to struct for up-down mode initialization. +//! +//! Modified bits of \b TBxCTL register, bits of \b TBxCCTL0 register and bits +//! of \b TBxCCR0 register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_B_initUpDownMode(uint16_t baseAddress, + TIMER_B_initUpDownModeParam *param) +{ + assert(param != 0); + + assert( + (TIMER_B_CLOCKSOURCE_EXTERNAL_TXCLK == param->clockSource) || + (TIMER_B_CLOCKSOURCE_ACLK == param->clockSource) || + (TIMER_B_CLOCKSOURCE_SMCLK == param->clockSource) || + (TIMER_B_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK == param->clockSource) + ); + + assert( + (TIMER_B_DO_CLEAR == param->timerClear) || + (TIMER_B_SKIP_CLEAR == param->timerClear) + ); + + assert( + (TIMER_B_DO_CLEAR == param->timerClear) || + (TIMER_B_SKIP_CLEAR == param->timerClear) + ); + + HWREG16(baseAddress + OFS_TBxCTL) &= + ~(TIMER_B_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK + + TIMER_B_UPDOWN_MODE + + TIMER_B_DO_CLEAR + + TIMER_B_TBIE_INTERRUPT_ENABLE + + CNTL_3 + ); + HWREG16(baseAddress + OFS_TBxEX0) &= ~TBIDEX_7; + + HWREG16(baseAddress + OFS_TBxEX0) |= param->clockSourceDivider & 0x7; + + HWREG16(baseAddress + OFS_TBxCTL) |= (param->clockSource + + TIMER_B_STOP_MODE + + param->timerClear + + param->timerInterruptEnable_TBIE + + ((param->clockSourceDivider >> 3) << 6)); + + if (param->startTimer) + HWREG16(baseAddress + OFS_TBxCTL) |= TIMER_B_UPDOWN_MODE; + + if (TIMER_B_CCIE_CCR0_INTERRUPT_ENABLE == + param->captureCompareInterruptEnable_CCR0_CCIE) + HWREG16(baseAddress + OFS_TBxCCTL0) |= TIMER_B_CCIE_CCR0_INTERRUPT_ENABLE; + else + HWREG16(baseAddress + OFS_TBxCCTL0) &= ~TIMER_B_CCIE_CCR0_INTERRUPT_ENABLE; + + HWREG16(baseAddress + OFS_TBxCCR0) = param->timerPeriod; +} + +//***************************************************************************** +// +//! \brief DEPRECATED - Configures TIMER_B in up down mode. +//! +//! This API does not start the timer. Timer needs to be started when required +//! using the TIMER_B_startCounter API. +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param clockSource selects the clock source +//! Valid values are: +//! - \b TIMER_B_CLOCKSOURCE_EXTERNAL_TXCLK [Default] +//! - \b TIMER_B_CLOCKSOURCE_ACLK +//! - \b TIMER_B_CLOCKSOURCE_SMCLK +//! - \b TIMER_B_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK +//! \param clockSourceDivider is the divider for Clock source. +//! Valid values are: +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_1 [Default] +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_2 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_3 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_4 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_5 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_6 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_7 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_8 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_10 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_12 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_14 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_16 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_20 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_24 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_28 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_32 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_40 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_48 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_56 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_64 +//! \param timerPeriod is the specified TIMER_B period +//! \param timerInterruptEnable_TBIE is to enable or disable TIMER_B interrupt +//! Valid values are: +//! - \b TIMER_B_TBIE_INTERRUPT_ENABLE +//! - \b TIMER_B_TBIE_INTERRUPT_DISABLE [Default] +//! \param captureCompareInterruptEnable_CCR0_CCIE is to enable or disable +//! TIMER_B CCR0 capture compare interrupt. +//! Valid values are: +//! - \b TIMER_B_CCIE_CCR0_INTERRUPT_ENABLE +//! - \b TIMER_B_CCIE_CCR0_INTERRUPT_DISABLE [Default] +//! \param timerClear decides if TIMER_B clock divider, count direction, count +//! need to be reset. +//! Valid values are: +//! - \b TIMER_B_DO_CLEAR +//! - \b TIMER_B_SKIP_CLEAR [Default] +//! +//! Modified bits of \b TBxCTL register, bits of \b TBxCCTL0 register and bits +//! of \b TBxCCR0 register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_B_configureUpDownMode( + uint16_t baseAddress, + uint16_t clockSource, + uint16_t clockSourceDivider, + uint16_t timerPeriod, + uint16_t timerInterruptEnable_TBIE, + uint16_t captureCompareInterruptEnable_CCR0_CCIE, + uint16_t timerClear + ) +{ + TIMER_B_initUpDownModeParam param = { 0 }; + + param.clockSource = clockSource; + param.clockSourceDivider = clockSourceDivider; + param.timerPeriod = timerPeriod; + param.timerInterruptEnable_TBIE = timerInterruptEnable_TBIE; + param.captureCompareInterruptEnable_CCR0_CCIE = + captureCompareInterruptEnable_CCR0_CCIE; + param.timerClear = timerClear; + param.startTimer = false; + + TIMER_B_initUpDownMode(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief DEPRECATED - Replaced by TIMER_B_configureContinuousMode and +//! TIMER_B_startCounter API. Starts TIMER_B in continuous mode. +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param clockSource selects the clock source +//! Valid values are: +//! - \b TIMER_B_CLOCKSOURCE_EXTERNAL_TXCLK [Default] +//! - \b TIMER_B_CLOCKSOURCE_ACLK +//! - \b TIMER_B_CLOCKSOURCE_SMCLK +//! - \b TIMER_B_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK +//! \param clockSourceDivider is the divider for Clock source. +//! Valid values are: +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_1 [Default] +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_2 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_3 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_4 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_5 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_6 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_7 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_8 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_10 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_12 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_14 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_16 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_20 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_24 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_28 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_32 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_40 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_48 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_56 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_64 +//! \param timerInterruptEnable_TBIE is to enable or disable TIMER_B interrupt +//! Valid values are: +//! - \b TIMER_B_TBIE_INTERRUPT_ENABLE +//! - \b TIMER_B_TBIE_INTERRUPT_DISABLE [Default] +//! \param timerClear decides if TIMER_B clock divider, count direction, count +//! need to be reset. +//! Valid values are: +//! - \b TIMER_B_DO_CLEAR +//! - \b TIMER_B_SKIP_CLEAR [Default] +//! +//! Modified bits of \b TBxCTL register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_B_startContinuousMode( uint16_t baseAddress, + uint16_t clockSource, + uint16_t clockSourceDivider, + uint16_t timerInterruptEnable_TBIE, + uint16_t timerClear + ) +{ + TIMER_B_initContinuousModeParam param = { 0 }; + + param.clockSource = clockSource; + param.clockSourceDivider = clockSourceDivider; + param.timerInterruptEnable_TBIE = timerInterruptEnable_TBIE; + param.timerClear = timerClear; + param.startTimer = true; + + TIMER_B_initContinuousMode(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief DEPRECATED - Spelling Error Fixed. Starts TIMER_B in continuous +//! mode. +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param clockSource selects the clock source +//! Valid values are: +//! - \b TIMER_B_CLOCKSOURCE_EXTERNAL_TXCLK [Default] +//! - \b TIMER_B_CLOCKSOURCE_ACLK +//! - \b TIMER_B_CLOCKSOURCE_SMCLK +//! - \b TIMER_B_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK +//! \param clockSourceDivider is the divider for Clock source. +//! Valid values are: +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_1 [Default] +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_2 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_3 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_4 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_5 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_6 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_7 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_8 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_10 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_12 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_14 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_16 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_20 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_24 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_28 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_32 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_40 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_48 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_56 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_64 +//! \param timerInterruptEnable_TBIE is to enable or disable TIMER_B interrupt +//! Valid values are: +//! - \b TIMER_B_TBIE_INTERRUPT_ENABLE +//! - \b TIMER_B_TBIE_INTERRUPT_DISABLE [Default] +//! \param timerClear decides if TIMER_B clock divider, count direction, count +//! need to be reset. +//! Valid values are: +//! - \b TIMER_B_DO_CLEAR +//! - \b TIMER_B_SKIP_CLEAR [Default] +//! +//! Modified bits of \b TBxCTL register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_B_startContinousMode( uint16_t baseAddress, + uint16_t clockSource, + uint16_t clockSourceDivider, + uint16_t timerInterruptEnable_TBIE, + uint16_t timerClear + ) +{ + TIMER_B_startContinuousMode(baseAddress, + clockSource, + clockSourceDivider, + timerInterruptEnable_TBIE, + timerClear + ); +} + +//***************************************************************************** +// +//! \brief DEPRECATED - Replaced by TIMER_B_configureUpMode and +//! TIMER_B_startCounter API. Starts TIMER_B in up mode. +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param clockSource selects the clock source +//! Valid values are: +//! - \b TIMER_B_CLOCKSOURCE_EXTERNAL_TXCLK [Default] +//! - \b TIMER_B_CLOCKSOURCE_ACLK +//! - \b TIMER_B_CLOCKSOURCE_SMCLK +//! - \b TIMER_B_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK +//! \param clockSourceDivider is the divider for Clock source. +//! Valid values are: +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_1 [Default] +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_2 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_3 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_4 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_5 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_6 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_7 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_8 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_10 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_12 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_14 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_16 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_20 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_24 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_28 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_32 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_40 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_48 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_56 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_64 +//! \param timerPeriod is the specified TIMER_B period. This is the value that +//! gets written into the CCR0. Limited to 16 bits[uint16_t] +//! \param timerInterruptEnable_TBIE is to enable or disable TIMER_B interrupt +//! Valid values are: +//! - \b TIMER_B_TBIE_INTERRUPT_ENABLE +//! - \b TIMER_B_TBIE_INTERRUPT_DISABLE [Default] +//! \param captureCompareInterruptEnable_CCR0_CCIE is to enable or disable +//! TIMER_B CCR0 capture compare interrupt. +//! Valid values are: +//! - \b TIMER_B_CCIE_CCR0_INTERRUPT_ENABLE +//! - \b TIMER_B_CCIE_CCR0_INTERRUPT_DISABLE [Default] +//! \param timerClear decides if TIMER_B clock divider, count direction, count +//! need to be reset. +//! Valid values are: +//! - \b TIMER_B_DO_CLEAR +//! - \b TIMER_B_SKIP_CLEAR [Default] +//! +//! Modified bits of \b TBxCTL register, bits of \b TBxCCTL0 register and bits +//! of \b TBxCCR0 register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_B_startUpMode( uint16_t baseAddress, + uint16_t clockSource, + uint16_t clockSourceDivider, + uint16_t timerPeriod, + uint16_t timerInterruptEnable_TBIE, + uint16_t captureCompareInterruptEnable_CCR0_CCIE, + uint16_t timerClear + ) +{ + TIMER_B_initUpModeParam param = { 0 }; + + param.clockSource = clockSource; + param.clockSourceDivider = clockSourceDivider; + param.timerPeriod = timerPeriod; + param.timerInterruptEnable_TBIE = timerInterruptEnable_TBIE; + param.captureCompareInterruptEnable_CCR0_CCIE = + captureCompareInterruptEnable_CCR0_CCIE; + param.timerClear = timerClear; + param.startTimer = true; + + TIMER_B_initUpMode(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief DEPRECATED - Replaced by TIMER_B_configureUpDownMode and +//! TIMER_B_startCounter API. Starts TIMER_B in up down mode. +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param clockSource selects the clock source +//! Valid values are: +//! - \b TIMER_B_CLOCKSOURCE_EXTERNAL_TXCLK [Default] +//! - \b TIMER_B_CLOCKSOURCE_ACLK +//! - \b TIMER_B_CLOCKSOURCE_SMCLK +//! - \b TIMER_B_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK +//! \param clockSourceDivider is the divider for Clock source. +//! Valid values are: +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_1 [Default] +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_2 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_3 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_4 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_5 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_6 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_7 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_8 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_10 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_12 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_14 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_16 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_20 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_24 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_28 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_32 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_40 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_48 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_56 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_64 +//! \param timerPeriod is the specified TIMER_B period +//! \param timerInterruptEnable_TBIE is to enable or disable TIMER_B interrupt +//! Valid values are: +//! - \b TIMER_B_TBIE_INTERRUPT_ENABLE +//! - \b TIMER_B_TBIE_INTERRUPT_DISABLE [Default] +//! \param captureCompareInterruptEnable_CCR0_CCIE is to enable or disable +//! TIMER_B CCR0 capture compare interrupt. +//! Valid values are: +//! - \b TIMER_B_CCIE_CCR0_INTERRUPT_ENABLE +//! - \b TIMER_B_CCIE_CCR0_INTERRUPT_DISABLE [Default] +//! \param timerClear decides if TIMER_B clock divider, count direction, count +//! need to be reset. +//! Valid values are: +//! - \b TIMER_B_DO_CLEAR +//! - \b TIMER_B_SKIP_CLEAR [Default] +//! +//! Modified bits of \b TBxCTL register, bits of \b TBxCCTL0 register and bits +//! of \b TBxCCR0 register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_B_startUpDownMode( + uint16_t baseAddress, + uint16_t clockSource, + uint16_t clockSourceDivider, + uint16_t timerPeriod, + uint16_t timerInterruptEnable_TBIE, + uint16_t captureCompareInterruptEnable_CCR0_CCIE, + uint16_t timerClear + ) +{ + TIMER_B_initUpDownModeParam param = { 0 }; + + param.clockSource = clockSource; + param.clockSourceDivider = clockSourceDivider; + param.timerPeriod = timerPeriod; + param.timerInterruptEnable_TBIE = timerInterruptEnable_TBIE; + param.captureCompareInterruptEnable_CCR0_CCIE = + captureCompareInterruptEnable_CCR0_CCIE; + param.timerClear = timerClear; + param.startTimer = true; + + TIMER_B_initUpDownMode(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Initializes Capture Mode +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param param is the pointer to struct for capture mode initialization. +//! +//! Modified bits of \b TBxCCTLn register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_B_initCaptureMode(uint16_t baseAddress, + TIMER_B_initCaptureModeParam *param) +{ + assert(param != 0); + + assert((TIMER_B_CAPTURECOMPARE_REGISTER_0 == param->captureRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_1 == param->captureRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_2 == param->captureRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_3 == param->captureRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_4 == param->captureRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_5 == param->captureRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_6 == param->captureRegister) + ); + + assert((TIMER_B_CAPTUREMODE_NO_CAPTURE == param->captureMode) || + (TIMER_B_CAPTUREMODE_RISING_EDGE == param->captureMode) || + (TIMER_B_CAPTUREMODE_FALLING_EDGE == param->captureMode) || + (TIMER_B_CAPTUREMODE_RISING_AND_FALLING_EDGE == param->captureMode) + ); + + assert((TIMER_B_CAPTURE_INPUTSELECT_CCIxA == param->captureInputSelect) || + (TIMER_B_CAPTURE_INPUTSELECT_CCIxB == param->captureInputSelect) || + (TIMER_B_CAPTURE_INPUTSELECT_GND == param->captureInputSelect) || + (TIMER_B_CAPTURE_INPUTSELECT_Vcc == param->captureInputSelect) + ); + + assert((TIMER_B_CAPTURE_ASYNCHRONOUS == param->synchronizeCaptureSource) || + (TIMER_B_CAPTURE_SYNCHRONOUS == param->synchronizeCaptureSource) + ); + + assert( + (TIMER_B_CAPTURECOMPARE_INTERRUPT_DISABLE == param->captureInterruptEnable) || + (TIMER_B_CAPTURECOMPARE_INTERRUPT_ENABLE == param->captureInterruptEnable) + ); + + assert((TIMER_B_OUTPUTMODE_OUTBITVALUE == param->captureOutputMode) || + (TIMER_B_OUTPUTMODE_SET == param->captureOutputMode) || + (TIMER_B_OUTPUTMODE_TOGGLE_RESET == param->captureOutputMode) || + (TIMER_B_OUTPUTMODE_SET_RESET == param->captureOutputMode) || + (TIMER_B_OUTPUTMODE_TOGGLE == param->captureOutputMode) || + (TIMER_B_OUTPUTMODE_RESET == param->captureOutputMode) || + (TIMER_B_OUTPUTMODE_TOGGLE_SET == param->captureOutputMode) || + (TIMER_B_OUTPUTMODE_RESET_SET == param->captureOutputMode) + ); + + //CaptureCompare register 0 only supports certain modes + assert((TIMER_B_CAPTURECOMPARE_REGISTER_0 == param->captureRegister) && + ((TIMER_B_OUTPUTMODE_OUTBITVALUE == param->captureOutputMode) || + (TIMER_B_OUTPUTMODE_SET == param->captureOutputMode) || + (TIMER_B_OUTPUTMODE_TOGGLE == param->captureOutputMode) || + (TIMER_B_OUTPUTMODE_RESET == param->captureOutputMode))); + + HWREG16(baseAddress + param->captureRegister ) |= CAP; + + HWREG16(baseAddress + param->captureRegister) &= + ~(TIMER_B_CAPTUREMODE_RISING_AND_FALLING_EDGE + + TIMER_B_CAPTURE_INPUTSELECT_Vcc + + TIMER_B_CAPTURE_SYNCHRONOUS + + TIMER_B_DO_CLEAR + + TIMER_B_TBIE_INTERRUPT_ENABLE + + CM_3 + ); + + HWREG16(baseAddress + param->captureRegister) |= (param->captureMode + + param->captureInputSelect + + param->synchronizeCaptureSource + + param->captureInterruptEnable + + param->captureOutputMode + ); +} + +//***************************************************************************** +// +//! \brief DEPRECATED - Initializes Capture Mode +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param captureRegister selects the capture register being used. Refer to +//! datasheet to ensure the device has the capture register being used. +//! Valid values are: +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_6 +//! \param captureMode is the capture mode selected. +//! Valid values are: +//! - \b TIMER_B_CAPTUREMODE_NO_CAPTURE [Default] +//! - \b TIMER_B_CAPTUREMODE_RISING_EDGE +//! - \b TIMER_B_CAPTUREMODE_FALLING_EDGE +//! - \b TIMER_B_CAPTUREMODE_RISING_AND_FALLING_EDGE +//! \param captureInputSelect decides the Input Select +//! Valid values are: +//! - \b TIMER_B_CAPTURE_INPUTSELECT_CCIxA [Default] +//! - \b TIMER_B_CAPTURE_INPUTSELECT_CCIxB +//! - \b TIMER_B_CAPTURE_INPUTSELECT_GND +//! - \b TIMER_B_CAPTURE_INPUTSELECT_Vcc +//! \param synchronizeCaptureSource decides if capture source should be +//! synchronized with TIMER_B clock +//! Valid values are: +//! - \b TIMER_B_CAPTURE_ASYNCHRONOUS [Default] +//! - \b TIMER_B_CAPTURE_SYNCHRONOUS +//! \param captureInterruptEnable is to enable or disable TIMER_B capture +//! compare interrupt. +//! Valid values are: +//! - \b TIMER_B_CAPTURECOMPARE_INTERRUPT_DISABLE [Default] +//! - \b TIMER_B_CAPTURECOMPARE_INTERRUPT_ENABLE +//! \param captureOutputMode specifies the output mode. +//! Valid values are: +//! - \b TIMER_B_OUTPUTMODE_OUTBITVALUE [Default] +//! - \b TIMER_B_OUTPUTMODE_SET +//! - \b TIMER_B_OUTPUTMODE_TOGGLE_RESET +//! - \b TIMER_B_OUTPUTMODE_SET_RESET +//! - \b TIMER_B_OUTPUTMODE_TOGGLE +//! - \b TIMER_B_OUTPUTMODE_RESET +//! - \b TIMER_B_OUTPUTMODE_TOGGLE_SET +//! - \b TIMER_B_OUTPUTMODE_RESET_SET +//! +//! Modified bits of \b TBxCCTLn register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_B_initCapture(uint16_t baseAddress, + uint16_t captureRegister, + uint16_t captureMode, + uint16_t captureInputSelect, + uint16_t synchronizeCaptureSource, + uint16_t captureInterruptEnable, + uint16_t captureOutputMode + ) +{ + TIMER_B_initCaptureModeParam param = { 0 }; + + param.captureRegister = captureRegister; + param.captureMode = captureMode; + param.captureInputSelect = captureInputSelect; + param.synchronizeCaptureSource = synchronizeCaptureSource; + param.captureInterruptEnable = captureInterruptEnable; + param.captureOutputMode = captureOutputMode; + + TIMER_B_initCaptureMode(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Initializes Compare Mode +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param param is the pointer to struct for compare mode initialization. +//! +//! Modified bits of \b TBxCCTLn register and bits of \b TBxCCRn register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_B_initCompareMode(uint16_t baseAddress, + TIMER_B_initCompareModeParam *param) +{ + assert(param != 0); + + assert((TIMER_B_CAPTURECOMPARE_REGISTER_0 == param->compareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_1 == param->compareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_2 == param->compareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_3 == param->compareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_4 == param->compareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_5 == param->compareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_6 == param->compareRegister) + ); + + assert((TIMER_B_CAPTURECOMPARE_INTERRUPT_ENABLE == param->compareInterruptEnable) || + (TIMER_B_CAPTURECOMPARE_INTERRUPT_DISABLE == param->compareInterruptEnable) + ); + + assert((TIMER_B_OUTPUTMODE_OUTBITVALUE == param->compareOutputMode) || + (TIMER_B_OUTPUTMODE_SET == param->compareOutputMode) || + (TIMER_B_OUTPUTMODE_TOGGLE_RESET == param->compareOutputMode) || + (TIMER_B_OUTPUTMODE_SET_RESET == param->compareOutputMode) || + (TIMER_B_OUTPUTMODE_TOGGLE == param->compareOutputMode) || + (TIMER_B_OUTPUTMODE_RESET == param->compareOutputMode) || + (TIMER_B_OUTPUTMODE_TOGGLE_SET == param->compareOutputMode) || + (TIMER_B_OUTPUTMODE_RESET_SET == param->compareOutputMode) + ); + + //CaptureCompare register 0 only supports certain modes + assert((TIMER_B_CAPTURECOMPARE_REGISTER_0 == param->compareRegister) && + ((TIMER_B_OUTPUTMODE_OUTBITVALUE == param->compareOutputMode) || + (TIMER_B_OUTPUTMODE_SET == param->compareOutputMode) || + (TIMER_B_OUTPUTMODE_TOGGLE == param->compareOutputMode) || + (TIMER_B_OUTPUTMODE_RESET == param->compareOutputMode))); + + HWREG16(baseAddress + param->compareRegister ) &= ~CAP; + + HWREG16(baseAddress + param->compareRegister) &= + ~(TIMER_B_CAPTURECOMPARE_INTERRUPT_ENABLE + + TIMER_B_OUTPUTMODE_RESET_SET + ); + + HWREG16(baseAddress + param->compareRegister) |= (param->compareInterruptEnable + + param->compareOutputMode + ); + + HWREG16(baseAddress + param->compareRegister + OFS_TBxR) = param->compareValue; +} + +//***************************************************************************** +// +//! \brief DEPRECATED - Initializes Compare Mode +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param compareRegister selects the compare register being used. Refer to +//! datasheet to ensure the device has the compare register being used. +//! Valid values are: +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_6 +//! \param compareInterruptEnable is to enable or disable TIMER_B capture +//! compare interrupt. +//! Valid values are: +//! - \b TIMER_B_CAPTURECOMPARE_INTERRUPT_DISABLE [Default] +//! - \b TIMER_B_CAPTURECOMPARE_INTERRUPT_ENABLE +//! \param compareOutputMode specifies the output mode. +//! Valid values are: +//! - \b TIMER_B_OUTPUTMODE_OUTBITVALUE [Default] +//! - \b TIMER_B_OUTPUTMODE_SET +//! - \b TIMER_B_OUTPUTMODE_TOGGLE_RESET +//! - \b TIMER_B_OUTPUTMODE_SET_RESET +//! - \b TIMER_B_OUTPUTMODE_TOGGLE +//! - \b TIMER_B_OUTPUTMODE_RESET +//! - \b TIMER_B_OUTPUTMODE_TOGGLE_SET +//! - \b TIMER_B_OUTPUTMODE_RESET_SET +//! \param compareValue is the count to be compared with in compare mode +//! +//! Modified bits of \b TBxCCTLn register and bits of \b TBxCCRn register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_B_initCompare( uint16_t baseAddress, + uint16_t compareRegister, + uint16_t compareInterruptEnable, + uint16_t compareOutputMode, + uint16_t compareValue + ) +{ + TIMER_B_initCompareModeParam param = { 0 }; + + param.compareRegister = compareRegister; + param.compareInterruptEnable = compareInterruptEnable; + param.compareOutputMode = compareOutputMode; + param.compareValue = compareValue; + + TIMER_B_initCompareMode(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Enable TIMER_B interrupt +//! +//! Enables TIMER_B interrupt. Does not clear interrupt flags. +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! +//! Modified bits of \b TBxCTL register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_B_enableInterrupt(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_TBxCTL) |= TBIE; +} + +//***************************************************************************** +// +//! \brief Disable TIMER_B interrupt +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! +//! Modified bits of \b TBxCTL register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_B_disableInterrupt(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_TBxCTL) &= ~TBIE; +} + +//***************************************************************************** +// +//! \brief Get TIMER_B interrupt status +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! +//! \return One of the following: +//! - \b TIMER_B_INTERRUPT_NOT_PENDING +//! - \b TIMER_B_INTERRUPT_PENDING +//! \n indicating the status of the TIMER_B interrupt +// +//***************************************************************************** +uint32_t TIMER_B_getInterruptStatus(uint16_t baseAddress) +{ + return HWREG16(baseAddress + OFS_TBxCTL) & TBIFG; +} + +//***************************************************************************** +// +//! \brief Enable capture compare interrupt +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param captureCompareRegister selects the capture compare register being +//! used. Refer to datasheet to ensure the device has the capture +//! compare register being used. +//! Valid values are: +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_6 +//! +//! Modified bits of \b TBxCCTLn register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_B_enableCaptureCompareInterrupt(uint16_t baseAddress, + uint16_t captureCompareRegister + ) +{ + assert((TIMER_B_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_1 == captureCompareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_2 == captureCompareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_3 == captureCompareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_4 == captureCompareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_5 == captureCompareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_6 == captureCompareRegister) + ); + + HWREG16(baseAddress + captureCompareRegister) |= CCIE; +} + +//***************************************************************************** +// +//! \brief Disable capture compare interrupt +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param captureCompareRegister selects the capture compare register being +//! used. Refer to datasheet to ensure the device has the capture +//! compare register being used. +//! Valid values are: +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_6 +//! +//! Modified bits of \b TBxCCTLn register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_B_disableCaptureCompareInterrupt(uint16_t baseAddress, + uint16_t captureCompareRegister + ) +{ + assert((TIMER_B_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_1 == captureCompareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_2 == captureCompareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_3 == captureCompareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_4 == captureCompareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_5 == captureCompareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_6 == captureCompareRegister) + ); + HWREG16(baseAddress + captureCompareRegister) &= ~CCIE; +} + +//***************************************************************************** +// +//! \brief Return capture compare interrupt status +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param captureCompareRegister selects the capture compare register being +//! used. Refer to datasheet to ensure the device has the capture +//! compare register being used. +//! Valid values are: +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_6 +//! \param mask is the mask for the interrupt status +//! Mask value is the logical OR of any of the following: +//! - \b TIMER_B_CAPTURE_OVERFLOW +//! - \b TIMER_B_CAPTURECOMPARE_INTERRUPT_FLAG +//! +//! \return Logical OR of any of the following: +//! - \b TIMER_B_CAPTURE_OVERFLOW +//! - \b TIMER_B_CAPTURECOMPARE_INTERRUPT_FLAG +//! \n indicating the status of the masked interrupts +// +//***************************************************************************** +uint32_t TIMER_B_getCaptureCompareInterruptStatus(uint16_t baseAddress, + uint16_t captureCompareRegister, + uint16_t mask + ) +{ + return HWREG16(baseAddress + captureCompareRegister) & mask; +} + +//***************************************************************************** +// +//! \brief Reset/Clear the TIMER_B clock divider, count direction, count +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! +//! Modified bits of \b TBxCTL register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_B_clear(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_TBxCTL) |= TBCLR; +} + +//***************************************************************************** +// +//! \brief Get synchronized capturecompare input +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param captureCompareRegister selects the capture compare register being +//! used. Refer to datasheet to ensure the device has the capture +//! compare register being used. +//! Valid values are: +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_6 +//! \param synchronized selects the type of capture compare input +//! Valid values are: +//! - \b TIMER_B_READ_SYNCHRONIZED_CAPTURECOMPAREINPUT +//! - \b TIMER_B_READ_CAPTURE_COMPARE_INPUT +//! +//! \return One of the following: +//! - \b TIMER_B_CAPTURECOMPARE_INPUT_HIGH +//! - \b TIMER_B_CAPTURECOMPARE_INPUT_LOW +// +//***************************************************************************** +uint8_t TIMER_B_getSynchronizedCaptureCompareInput + (uint16_t baseAddress, + uint16_t captureCompareRegister, + uint16_t synchronized + ) +{ + assert((TIMER_B_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_1 == captureCompareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_2 == captureCompareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_3 == captureCompareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_4 == captureCompareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_5 == captureCompareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_6 == captureCompareRegister) + ); + + assert((TIMER_B_READ_CAPTURE_COMPARE_INPUT == synchronized) || + (TIMER_B_READ_SYNCHRONIZED_CAPTURECOMPAREINPUT == synchronized) + ); + + if (HWREG16(baseAddress + captureCompareRegister) & synchronized) + return TIMER_B_CAPTURECOMPARE_INPUT_HIGH; + else + return TIMER_B_CAPTURECOMPARE_INPUT_LOW; +} + +//***************************************************************************** +// +//! \brief Get output bit for output mode +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param captureCompareRegister selects the capture compare register being +//! used. Refer to datasheet to ensure the device has the capture +//! compare register being used. +//! Valid values are: +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_6 +//! +//! \return One of the following: +//! - \b TIMER_B_OUTPUTMODE_OUTBITVALUE_HIGH +//! - \b TIMER_B_OUTPUTMODE_OUTBITVALUE_LOW +// +//***************************************************************************** +uint8_t TIMER_B_getOutputForOutputModeOutBitValue + (uint16_t baseAddress, + uint16_t captureCompareRegister + ) +{ + assert((TIMER_B_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_1 == captureCompareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_2 == captureCompareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_3 == captureCompareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_4 == captureCompareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_5 == captureCompareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_6 == captureCompareRegister) + ); + + if (HWREG16(baseAddress + captureCompareRegister) & OUT) + return TIMER_B_OUTPUTMODE_OUTBITVALUE_HIGH; + else + return TIMER_B_OUTPUTMODE_OUTBITVALUE_LOW; +} + +//***************************************************************************** +// +//! \brief Get current capturecompare count +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param captureCompareRegister selects the capture compare register being +//! used. Refer to datasheet to ensure the device has the capture +//! compare register being used. +//! Valid values are: +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_6 +//! +//! \return Current count as uint16_t +// +//***************************************************************************** +uint16_t TIMER_B_getCaptureCompareCount + (uint16_t baseAddress, + uint16_t captureCompareRegister + ) +{ + assert((TIMER_B_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_1 == captureCompareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_2 == captureCompareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_3 == captureCompareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_4 == captureCompareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_5 == captureCompareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_6 == captureCompareRegister) + ); + + return HWREG16(baseAddress + OFS_TBxR + captureCompareRegister); +} + +//***************************************************************************** +// +//! \brief Set output bit for output mode +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param captureCompareRegister selects the capture compare register being +//! used. Refer to datasheet to ensure the device has the capture +//! compare register being used. +//! Valid values are: +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_6 +//! \param outputModeOutBitValue the value to be set for out bit +//! Valid values are: +//! - \b TIMER_B_OUTPUTMODE_OUTBITVALUE_HIGH +//! - \b TIMER_B_OUTPUTMODE_OUTBITVALUE_LOW +//! +//! Modified bits of \b TBxCCTLn register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_B_setOutputForOutputModeOutBitValue + (uint16_t baseAddress, + uint16_t captureCompareRegister, + uint8_t outputModeOutBitValue + ) +{ + assert((TIMER_B_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_1 == captureCompareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_2 == captureCompareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_3 == captureCompareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_4 == captureCompareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_5 == captureCompareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_6 == captureCompareRegister) + ); + + assert((TIMER_B_OUTPUTMODE_OUTBITVALUE_HIGH == outputModeOutBitValue) || + (TIMER_B_OUTPUTMODE_OUTBITVALUE_LOW == outputModeOutBitValue) + ); + + HWREG16(baseAddress + captureCompareRegister) &= ~OUT; + HWREG16(baseAddress + captureCompareRegister) |= outputModeOutBitValue; +} + +//***************************************************************************** +// +//! \brief Generate a PWM with TIMER_B running in up mode +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param param is the pointer to struct for PWM configuration. +//! +//! Modified bits of \b TBxCCTLn register, bits of \b TBxCTL register, bits of +//! \b TBxCCTL0 register and bits of \b TBxCCR0 register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_B_outputPWM(uint16_t baseAddress, TIMER_B_outputPWMParam *param) +{ + assert(param != 0); + + assert( + (TIMER_B_CLOCKSOURCE_EXTERNAL_TXCLK == param->clockSource) || + (TIMER_B_CLOCKSOURCE_ACLK == param->clockSource) || + (TIMER_B_CLOCKSOURCE_SMCLK == param->clockSource) || + (TIMER_B_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK == param->clockSource) + ); + + assert((TIMER_B_CAPTURECOMPARE_REGISTER_0 == param->compareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_1 == param->compareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_2 == param->compareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_3 == param->compareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_4 == param->compareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_5 == param->compareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_6 == param->compareRegister) + ); + + assert((TIMER_B_OUTPUTMODE_OUTBITVALUE == param->compareOutputMode) || + (TIMER_B_OUTPUTMODE_SET == param->compareOutputMode) || + (TIMER_B_OUTPUTMODE_TOGGLE_RESET == param->compareOutputMode) || + (TIMER_B_OUTPUTMODE_SET_RESET == param->compareOutputMode) || + (TIMER_B_OUTPUTMODE_TOGGLE == param->compareOutputMode) || + (TIMER_B_OUTPUTMODE_RESET == param->compareOutputMode) || + (TIMER_B_OUTPUTMODE_TOGGLE_SET == param->compareOutputMode) || + (TIMER_B_OUTPUTMODE_RESET_SET == param->compareOutputMode) + ); + + HWREG16(baseAddress + OFS_TBxCTL) &= + ~( TIMER_B_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK + + TIMER_B_UPDOWN_MODE + TIMER_B_DO_CLEAR + + TIMER_B_TBIE_INTERRUPT_ENABLE + ); + HWREG16(baseAddress + OFS_TBxEX0) &= ~TBIDEX_7; + + HWREG16(baseAddress + OFS_TBxEX0) |= param->clockSourceDivider & 0x7; + + HWREG16(baseAddress + OFS_TBxCTL) |= (param->clockSource + + TIMER_B_UP_MODE + + TIMER_B_DO_CLEAR + + ((param->clockSourceDivider >> 3) << 6)); + + HWREG16(baseAddress + OFS_TBxCCR0) = param->timerPeriod; + + HWREG16(baseAddress + OFS_TBxCCTL0) &= + ~(TIMER_B_CAPTURECOMPARE_INTERRUPT_ENABLE + + TIMER_B_OUTPUTMODE_RESET_SET + ); + + HWREG16(baseAddress + param->compareRegister) |= param->compareOutputMode; + + HWREG16(baseAddress + param->compareRegister + OFS_TBxR) = param->dutyCycle; +} //***************************************************************************** +// +//! \brief DEPRECATED - Generate a PWM with TIMER_B running in up mode +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param clockSource selects the clock source +//! Valid values are: +//! - \b TIMER_B_CLOCKSOURCE_EXTERNAL_TXCLK [Default] +//! - \b TIMER_B_CLOCKSOURCE_ACLK +//! - \b TIMER_B_CLOCKSOURCE_SMCLK +//! - \b TIMER_B_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK +//! \param clockSourceDivider is the divider for Clock source. +//! Valid values are: +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_1 [Default] +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_2 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_3 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_4 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_5 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_6 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_7 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_8 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_10 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_12 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_14 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_16 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_20 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_24 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_28 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_32 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_40 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_48 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_56 +//! - \b TIMER_B_CLOCKSOURCE_DIVIDER_64 +//! \param timerPeriod selects the desired TIMER_B period +//! \param compareRegister selects the compare register being used. Refer to +//! datasheet to ensure the device has the compare register being used. +//! Valid values are: +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_6 +//! \param compareOutputMode specifies the output mode. +//! Valid values are: +//! - \b TIMER_B_OUTPUTMODE_OUTBITVALUE [Default] +//! - \b TIMER_B_OUTPUTMODE_SET +//! - \b TIMER_B_OUTPUTMODE_TOGGLE_RESET +//! - \b TIMER_B_OUTPUTMODE_SET_RESET +//! - \b TIMER_B_OUTPUTMODE_TOGGLE +//! - \b TIMER_B_OUTPUTMODE_RESET +//! - \b TIMER_B_OUTPUTMODE_TOGGLE_SET +//! - \b TIMER_B_OUTPUTMODE_RESET_SET +//! \param dutyCycle specifies the dutycycle for the generated waveform +//! +//! Modified bits of \b TBxCCTLn register, bits of \b TBxCTL register, bits of +//! \b TBxCCTL0 register and bits of \b TBxCCR0 register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_B_generatePWM( uint16_t baseAddress, + uint16_t clockSource, + uint16_t clockSourceDivider, + uint16_t timerPeriod, + uint16_t compareRegister, + uint16_t compareOutputMode, + uint16_t dutyCycle + ) +{ + TIMER_B_outputPWMParam param = { 0 }; + + param.clockSource = clockSource; + param.clockSourceDivider = clockSourceDivider; + param.timerPeriod = timerPeriod; + param.compareRegister = compareRegister; + param.compareOutputMode = compareOutputMode; + param.dutyCycle = dutyCycle; + + TIMER_B_outputPWM(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Stops the TIMER_B +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! +//! Modified bits of \b TBxCTL register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_B_stop( uint16_t baseAddress ) +{ + HWREG16(baseAddress + OFS_TBxCTL) &= ~MC_3; + HWREG16(baseAddress + OFS_TBxCTL) |= MC_0; +} + +//***************************************************************************** +// +//! \brief Sets the value of the capture-compare register +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param compareRegister selects the compare register being used. Refer to +//! datasheet to ensure the device has the compare register being used. +//! Valid values are: +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_6 +//! \param compareValue is the count to be compared with in compare mode +//! +//! Modified bits of \b TBxCCRn register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_B_setCompareValue( uint16_t baseAddress, + uint16_t compareRegister, + uint16_t compareValue + ) +{ + assert((TIMER_B_CAPTURECOMPARE_REGISTER_0 == compareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_1 == compareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_2 == compareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_3 == compareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_4 == compareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_5 == compareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_6 == compareRegister) + ); + + HWREG16(baseAddress + compareRegister + OFS_TBxR) = compareValue; +} + +//***************************************************************************** +// +//! \brief Clears the TIMER_B TBIFG interrupt flag +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! +//! Modified bits are \b TBIFG of \b TBxCTL register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_B_clearTimerInterruptFlag(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_TBxCTL) &= ~TBIFG; +} + +//***************************************************************************** +// +//! \brief Clears the capture-compare interrupt flag +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param captureCompareRegister selects the capture compare register being +//! used. Refer to datasheet to ensure the device has the capture +//! compare register being used. +//! Valid values are: +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_6 +//! +//! Modified bits are \b CCIFG of \b TBxCCTLn register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_B_clearCaptureCompareInterruptFlag(uint16_t baseAddress, + uint16_t captureCompareRegister + ) +{ + assert((TIMER_B_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_1 == captureCompareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_2 == captureCompareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_3 == captureCompareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_4 == captureCompareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_5 == captureCompareRegister) || + (TIMER_B_CAPTURECOMPARE_REGISTER_6 == captureCompareRegister) + ); + + HWREG16(baseAddress + captureCompareRegister) &= ~CCIFG; +} + +//***************************************************************************** +// +//! \brief Selects TIMER_B counter length +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param counterLength selects the value of counter length. +//! Valid values are: +//! - \b TIMER_B_COUNTER_16BIT [Default] +//! - \b TIMER_B_COUNTER_12BIT +//! - \b TIMER_B_COUNTER_10BIT +//! - \b TIMER_B_COUNTER_8BIT +//! +//! Modified bits are \b CNTL of \b TBxCTL register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_B_selectCounterLength(uint16_t baseAddress, + uint16_t counterLength + ) +{ + assert((TIMER_B_COUNTER_8BIT == counterLength) || + (TIMER_B_COUNTER_10BIT == counterLength) || + (TIMER_B_COUNTER_12BIT == counterLength) || + (TIMER_B_COUNTER_16BIT == counterLength) + ); + + HWREG16(baseAddress + OFS_TBxCTL) &= ~CNTL_3; + HWREG16(baseAddress + OFS_TBxCTL) |= counterLength; +} + +//***************************************************************************** +// +//! \brief Selects TIMER_B Latching Group +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param groupLatch selects the latching group. +//! Valid values are: +//! - \b TIMER_B_GROUP_NONE [Default] +//! - \b TIMER_B_GROUP_CL12_CL23_CL56 +//! - \b TIMER_B_GROUP_CL123_CL456 +//! - \b TIMER_B_GROUP_ALL +//! +//! Modified bits are \b TBCLGRP of \b TBxCTL register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_B_selectLatchingGroup(uint16_t baseAddress, + uint16_t groupLatch) +{ + assert((TIMER_B_GROUP_NONE == groupLatch) || + (TIMER_B_GROUP_CL12_CL23_CL56 == groupLatch) || + (TIMER_B_GROUP_CL123_CL456 == groupLatch) || + (TIMER_B_GROUP_ALL == groupLatch) + ); + + HWREG16(baseAddress + OFS_TBxCTL) &= ~TBCLGRP_3; + HWREG16(baseAddress + OFS_TBxCTL) |= groupLatch; +} + +//***************************************************************************** +// +//! \brief Selects Compare Latch Load Event +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param compareRegister selects the compare register being used. Refer to +//! datasheet to ensure the device has the compare register being used. +//! Valid values are: +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_6 +//! \param compareLatchLoadEvent selects the latch load event +//! Valid values are: +//! - \b TIMER_B_LATCH_ON_WRITE_TO_TBxCCRn_COMPARE_REGISTER [Default] +//! - \b TIMER_B_LATCH_WHEN_COUNTER_COUNTS_TO_0_IN_UP_OR_CONT_MODE +//! - \b TIMER_B_LATCH_WHEN_COUNTER_COUNTS_TO_0_IN_UPDOWN_MODE +//! - \b +//! TIMER_B_LATCH_WHEN_COUNTER_COUNTS_TO_CURRENT_COMPARE_LATCH_VALUE +//! +//! Modified bits are \b CLLD of \b TBxCCTLn register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_B_initCompareLatchLoadEvent(uint16_t baseAddress, + uint16_t compareRegister, + uint16_t compareLatchLoadEvent + ) +{ + assert((TIMER_B_LATCH_ON_WRITE_TO_TBxCCRn_COMPARE_REGISTER == compareLatchLoadEvent) || + (TIMER_B_LATCH_WHEN_COUNTER_COUNTS_TO_0_IN_UP_OR_CONT_MODE == compareLatchLoadEvent) || + (TIMER_B_LATCH_WHEN_COUNTER_COUNTS_TO_0_IN_UPDOWN_MODE == compareLatchLoadEvent) || + (TIMER_B_LATCH_WHEN_COUNTER_COUNTS_TO_CURRENT_COMPARE_LATCH_VALUE == compareLatchLoadEvent) + ); + + HWREG16(baseAddress + compareRegister) &= ~CLLD_3; + HWREG16(baseAddress + compareRegister) |= compareLatchLoadEvent; +} + +//***************************************************************************** +// +//! \brief Reads the current timer count value +//! +//! Reads the current count value of the timer. There is a majority vote system +//! in place to confirm an accurate value is returned. The TIMER_B_THRESHOLD +//! #define in the associated header file can be modified so that the votes +//! must be closer together for a consensus to occur. +//! +//! \param baseAddress is the base address of the Timer module. +//! +//! \return Majority vote of timer count value +// +//***************************************************************************** +uint16_t TIMER_B_getCounterValue(uint16_t baseAddress) +{ + uint16_t voteOne, voteTwo, res; + + voteTwo = HWREG16(baseAddress + OFS_TBxR); + + do { + voteOne = voteTwo; + voteTwo = HWREG16(baseAddress + OFS_TBxR); + + if (voteTwo > voteOne) + res = voteTwo - voteOne; + else if (voteOne > voteTwo) + res = voteOne - voteTwo; + else + res = 0; + + } while ( res > TIMER_B_THRESHOLD); + + return voteTwo; +} + + +#endif +//***************************************************************************** +// +//! Close the doxygen group for timer_b_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/timer_b.h b/source/driverlib/MSP430F5xx_6xx/timer_b.h new file mode 100644 index 0000000..0fa488d --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/timer_b.h @@ -0,0 +1,569 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// timer_b.h - Driver for the TIMER_B Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_TIMER_B_H__ +#define __MSP430WARE_TIMER_B_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_TxB7__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//****************************************************************************** +// +// The following is a struct that is passed to TIMER_B_initContinuousMode() +// +//****************************************************************************** +typedef struct TIMER_B_initContinuousModeParam { + uint16_t clockSource; + uint16_t clockSourceDivider; + uint16_t timerInterruptEnable_TBIE; + uint16_t timerClear; + bool startTimer; +} TIMER_B_initContinuousModeParam; + +//****************************************************************************** +// +// The following is a struct that is passed to TIMER_B_initUpMode() +// +//****************************************************************************** +typedef struct TIMER_B_initUpModeParam { + uint16_t clockSource; + uint16_t clockSourceDivider; + uint16_t timerPeriod; + uint16_t timerInterruptEnable_TBIE; + uint16_t captureCompareInterruptEnable_CCR0_CCIE; + uint16_t timerClear; + bool startTimer; +} TIMER_B_initUpModeParam; + +//****************************************************************************** +// +// The following is a struct that is passed to TIMER_B_initUpDownMode() +// +//****************************************************************************** +typedef struct TIMER_B_initUpDownModeParam { + uint16_t clockSource; + uint16_t clockSourceDivider; + uint16_t timerPeriod; + uint16_t timerInterruptEnable_TBIE; + uint16_t captureCompareInterruptEnable_CCR0_CCIE; + uint16_t timerClear; + bool startTimer; +} TIMER_B_initUpDownModeParam; + +//****************************************************************************** +// +// The following is a struct that is passed to TIMER_B_initCaptureMode() +// +//****************************************************************************** +typedef struct TIMER_B_initCaptureModeParam { + uint16_t captureRegister; + uint16_t captureMode; + uint16_t captureInputSelect; + uint16_t synchronizeCaptureSource; + uint16_t captureInterruptEnable; + uint16_t captureOutputMode; +} TIMER_B_initCaptureModeParam; + +//****************************************************************************** +// +// The following is a struct that is passed to TIMER_B_initCompareMode() +// +//****************************************************************************** +typedef struct TIMER_B_initCompareModeParam { + uint16_t compareRegister; + uint16_t compareInterruptEnable; + uint16_t compareOutputMode; + uint16_t compareValue; +} TIMER_B_initCompareModeParam; + +//****************************************************************************** +// +// The following is a struct that is passed to TIMER_B_outputPWM() +// +//****************************************************************************** +typedef struct TIMER_B_outputPWMParam { + uint16_t clockSource; + uint16_t clockSourceDivider; + uint16_t timerPeriod; + uint16_t compareRegister; + uint16_t compareOutputMode; + uint16_t dutyCycle; +} TIMER_B_outputPWMParam; + +//***************************************************************************** +// +// The following is a parameter used for TIMER_B_getCounterValue that +// determines the maximum difference in counts of the TAxR register for a +// majority vote. +// +//***************************************************************************** +#define TIMER_B_THRESHOLD 50 + +//***************************************************************************** +// +// The following are values that can be passed to the clockSourceDivider +// parameter for functions: TIMER_B_configureContinuousMode(), +// TIMER_B_configureUpMode(), TIMER_B_configureUpDownMode(), +// TIMER_B_startContinuousMode(), TIMER_B_startContinousMode(), +// TIMER_B_startUpMode(), TIMER_B_startUpDownMode(), and TIMER_B_generatePWM(). +// +//***************************************************************************** +#define TIMER_B_CLOCKSOURCE_DIVIDER_1 0x00 +#define TIMER_B_CLOCKSOURCE_DIVIDER_2 0x08 +#define TIMER_B_CLOCKSOURCE_DIVIDER_3 0x02 +#define TIMER_B_CLOCKSOURCE_DIVIDER_4 0x10 +#define TIMER_B_CLOCKSOURCE_DIVIDER_5 0x04 +#define TIMER_B_CLOCKSOURCE_DIVIDER_6 0x05 +#define TIMER_B_CLOCKSOURCE_DIVIDER_7 0x06 +#define TIMER_B_CLOCKSOURCE_DIVIDER_8 0x18 +#define TIMER_B_CLOCKSOURCE_DIVIDER_10 0x0C +#define TIMER_B_CLOCKSOURCE_DIVIDER_12 0x0D +#define TIMER_B_CLOCKSOURCE_DIVIDER_14 0x0E +#define TIMER_B_CLOCKSOURCE_DIVIDER_16 0x0F +#define TIMER_B_CLOCKSOURCE_DIVIDER_20 0x14 +#define TIMER_B_CLOCKSOURCE_DIVIDER_24 0x15 +#define TIMER_B_CLOCKSOURCE_DIVIDER_28 0x16 +#define TIMER_B_CLOCKSOURCE_DIVIDER_32 0x17 +#define TIMER_B_CLOCKSOURCE_DIVIDER_40 0x1C +#define TIMER_B_CLOCKSOURCE_DIVIDER_48 0x1D +#define TIMER_B_CLOCKSOURCE_DIVIDER_56 0x1E +#define TIMER_B_CLOCKSOURCE_DIVIDER_64 0x1F + +//***************************************************************************** +// +// The following are values that can be passed to the timerMode parameter for +// functions: TIMER_B_startCounter(). +// +//***************************************************************************** +#define TIMER_B_STOP_MODE MC_0 +#define TIMER_B_UP_MODE MC_1 +#define TIMER_B_CONTINUOUS_MODE MC_2 +#define TIMER_B_UPDOWN_MODE MC_3 + +//***************************************************************************** +// +// The following are values that can be passed to the timerClear parameter for +// functions: TIMER_B_configureContinuousMode(), TIMER_B_configureUpMode(), +// TIMER_B_configureUpDownMode(), TIMER_B_startContinuousMode(), +// TIMER_B_startContinousMode(), TIMER_B_startUpMode(), and +// TIMER_B_startUpDownMode(). +// +//***************************************************************************** +#define TIMER_B_DO_CLEAR TBCLR +#define TIMER_B_SKIP_CLEAR 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the clockSource parameter for +// functions: TIMER_B_configureContinuousMode(), TIMER_B_configureUpMode(), +// TIMER_B_configureUpDownMode(), TIMER_B_startContinuousMode(), +// TIMER_B_startContinousMode(), TIMER_B_startUpMode(), +// TIMER_B_startUpDownMode(), and TIMER_B_generatePWM(). +// +//***************************************************************************** +#define TIMER_B_CLOCKSOURCE_EXTERNAL_TXCLK TBSSEL__TACLK +#define TIMER_B_CLOCKSOURCE_ACLK TBSSEL__ACLK +#define TIMER_B_CLOCKSOURCE_SMCLK TBSSEL__SMCLK +#define TIMER_B_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK TBSSEL__INCLK + +//***************************************************************************** +// +// The following are values that can be passed to the timerInterruptEnable_TBIE +// parameter for functions: TIMER_B_configureContinuousMode(), +// TIMER_B_configureUpMode(), TIMER_B_configureUpDownMode(), +// TIMER_B_startContinuousMode(), TIMER_B_startContinousMode(), +// TIMER_B_startUpMode(), and TIMER_B_startUpDownMode(). +// +//***************************************************************************** +#define TIMER_B_TBIE_INTERRUPT_ENABLE TBIE +#define TIMER_B_TBIE_INTERRUPT_DISABLE 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the +// captureCompareInterruptEnable_CCR0_CCIE parameter for functions: +// TIMER_B_configureUpMode(), TIMER_B_configureUpDownMode(), +// TIMER_B_startUpMode(), and TIMER_B_startUpDownMode(). +// +//***************************************************************************** +#define TIMER_B_CCIE_CCR0_INTERRUPT_ENABLE CCIE +#define TIMER_B_CCIE_CCR0_INTERRUPT_DISABLE 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the captureInterruptEnable +// parameter for functions: TIMER_B_initCapture(); the compareInterruptEnable +// parameter for functions: TIMER_B_initCompare(). +// +//***************************************************************************** +#define TIMER_B_CAPTURECOMPARE_INTERRUPT_DISABLE 0x00 +#define TIMER_B_CAPTURECOMPARE_INTERRUPT_ENABLE CCIE + +//***************************************************************************** +// +// The following are values that can be passed to the captureInputSelect +// parameter for functions: TIMER_B_initCapture(). +// +//***************************************************************************** +#define TIMER_B_CAPTURE_INPUTSELECT_CCIxA CCIS_0 +#define TIMER_B_CAPTURE_INPUTSELECT_CCIxB CCIS_1 +#define TIMER_B_CAPTURE_INPUTSELECT_GND CCIS_2 +#define TIMER_B_CAPTURE_INPUTSELECT_Vcc CCIS_3 + +//***************************************************************************** +// +// The following are values that can be passed to the compareOutputMode +// parameter for functions: TIMER_B_initCompare(), and TIMER_B_generatePWM(); +// the captureOutputMode parameter for functions: TIMER_B_initCapture(). +// +//***************************************************************************** +#define TIMER_B_OUTPUTMODE_OUTBITVALUE OUTMOD_0 +#define TIMER_B_OUTPUTMODE_SET OUTMOD_1 +#define TIMER_B_OUTPUTMODE_TOGGLE_RESET OUTMOD_2 +#define TIMER_B_OUTPUTMODE_SET_RESET OUTMOD_3 +#define TIMER_B_OUTPUTMODE_TOGGLE OUTMOD_4 +#define TIMER_B_OUTPUTMODE_RESET OUTMOD_5 +#define TIMER_B_OUTPUTMODE_TOGGLE_SET OUTMOD_6 +#define TIMER_B_OUTPUTMODE_RESET_SET OUTMOD_7 + +//***************************************************************************** +// +// The following are values that can be passed to the compareRegister parameter +// for functions: TIMER_B_initCompare(), TIMER_B_generatePWM(), +// TIMER_B_setCompareValue(), and TIMER_B_initCompareLatchLoadEvent(); the +// captureCompareRegister parameter for functions: +// TIMER_B_enableCaptureCompareInterrupt(), +// TIMER_B_disableCaptureCompareInterrupt(), +// TIMER_B_getCaptureCompareInterruptStatus(), +// TIMER_B_getSynchronizedCaptureCompareInput(), +// TIMER_B_getOutputForOutputModeOutBitValue(), +// TIMER_B_getCaptureCompareCount(), +// TIMER_B_setOutputForOutputModeOutBitValue(), and +// TIMER_B_clearCaptureCompareInterruptFlag(); the captureRegister parameter +// for functions: TIMER_B_initCapture(). +// +//***************************************************************************** +#define TIMER_B_CAPTURECOMPARE_REGISTER_0 0x02 +#define TIMER_B_CAPTURECOMPARE_REGISTER_1 0x04 +#define TIMER_B_CAPTURECOMPARE_REGISTER_2 0x06 +#define TIMER_B_CAPTURECOMPARE_REGISTER_3 0x08 +#define TIMER_B_CAPTURECOMPARE_REGISTER_4 0x0A +#define TIMER_B_CAPTURECOMPARE_REGISTER_5 0x0C +#define TIMER_B_CAPTURECOMPARE_REGISTER_6 0x0E + +//***************************************************************************** +// +// The following are values that can be passed to the captureMode parameter for +// functions: TIMER_B_initCapture(). +// +//***************************************************************************** +#define TIMER_B_CAPTUREMODE_NO_CAPTURE CM_0 +#define TIMER_B_CAPTUREMODE_RISING_EDGE CM_1 +#define TIMER_B_CAPTUREMODE_FALLING_EDGE CM_2 +#define TIMER_B_CAPTUREMODE_RISING_AND_FALLING_EDGE CM_3 + +//***************************************************************************** +// +// The following are values that can be passed to the synchronizeCaptureSource +// parameter for functions: TIMER_B_initCapture(). +// +//***************************************************************************** +#define TIMER_B_CAPTURE_ASYNCHRONOUS 0x00 +#define TIMER_B_CAPTURE_SYNCHRONOUS SCS + +//***************************************************************************** +// +// The following are values that can be passed to the mask parameter for +// functions: TIMER_B_getCaptureCompareInterruptStatus() as well as returned by +// the TIMER_B_getCaptureCompareInterruptStatus() function. +// +//***************************************************************************** +#define TIMER_B_CAPTURE_OVERFLOW COV +#define TIMER_B_CAPTURECOMPARE_INTERRUPT_FLAG CCIFG + +//***************************************************************************** +// +// The following are values that can be passed to the synchronized parameter +// for functions: TIMER_B_getSynchronizedCaptureCompareInput(). +// +//***************************************************************************** +#define TIMER_B_READ_SYNCHRONIZED_CAPTURECOMPAREINPUT SCCI +#define TIMER_B_READ_CAPTURE_COMPARE_INPUT CCI + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the TIMER_B_getSynchronizedCaptureCompareInput() +// function. +// +//***************************************************************************** +#define TIMER_B_CAPTURECOMPARE_INPUT_HIGH 0x01 +#define TIMER_B_CAPTURECOMPARE_INPUT_LOW 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the outputModeOutBitValue +// parameter for functions: TIMER_B_setOutputForOutputModeOutBitValue() as well +// as returned by the TIMER_B_getOutputForOutputModeOutBitValue() function. +// +//***************************************************************************** +#define TIMER_B_OUTPUTMODE_OUTBITVALUE_HIGH OUT +#define TIMER_B_OUTPUTMODE_OUTBITVALUE_LOW 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the counterLength parameter +// for functions: TIMER_B_selectCounterLength(). +// +//***************************************************************************** +#define TIMER_B_COUNTER_16BIT CNTL_3 +#define TIMER_B_COUNTER_12BIT CNTL_2 +#define TIMER_B_COUNTER_10BIT CNTL_1 +#define TIMER_B_COUNTER_8BIT CNTL_0 + +//***************************************************************************** +// +// The following are values that can be passed to the groupLatch parameter for +// functions: TIMER_B_selectLatchingGroup(). +// +//***************************************************************************** +#define TIMER_B_GROUP_NONE TBCLGRP_0 +#define TIMER_B_GROUP_CL12_CL23_CL56 TBCLGRP_1 +#define TIMER_B_GROUP_CL123_CL456 TBCLGRP_2 +#define TIMER_B_GROUP_ALL TBCLGRP_3 + +//***************************************************************************** +// +// The following are values that can be passed to the compareLatchLoadEvent +// parameter for functions: TIMER_B_initCompareLatchLoadEvent(). +// +//***************************************************************************** +#define TIMER_B_LATCH_ON_WRITE_TO_TBxCCRn_COMPARE_REGISTER CLLD_0 +#define TIMER_B_LATCH_WHEN_COUNTER_COUNTS_TO_0_IN_UP_OR_CONT_MODE CLLD_1 +#define TIMER_B_LATCH_WHEN_COUNTER_COUNTS_TO_0_IN_UPDOWN_MODE CLLD_2 +#define TIMER_B_LATCH_WHEN_COUNTER_COUNTS_TO_CURRENT_COMPARE_LATCH_VALUE CLLD_3 + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the TIMER_B_getInterruptStatus() function. +// +//***************************************************************************** +#define TIMER_B_INTERRUPT_NOT_PENDING 0x00 +#define TIMER_B_INTERRUPT_PENDING 0x01 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void TIMER_B_startCounter(uint16_t baseAddress, + uint16_t timerMode); + +extern void TIMER_B_initContinuousMode(uint16_t baseAddress, + TIMER_B_initContinuousModeParam *param); + +extern void TIMER_B_initUpMode(uint16_t baseAddress, + TIMER_B_initUpModeParam *param); + +extern void TIMER_B_initUpDownMode(uint16_t baseAddress, + TIMER_B_initUpDownModeParam *param); + +extern void TIMER_B_initCaptureMode(uint16_t baseAddress, + TIMER_B_initCaptureModeParam *param); + +extern void TIMER_B_initCompareMode(uint16_t baseAddress, + TIMER_B_initCompareModeParam *param); + +extern void TIMER_B_enableInterrupt(uint16_t baseAddress); + +extern void TIMER_B_disableInterrupt(uint16_t baseAddress); + +extern uint32_t TIMER_B_getInterruptStatus(uint16_t baseAddress); + +extern void TIMER_B_enableCaptureCompareInterrupt(uint16_t baseAddress, + uint16_t captureCompareRegister); + +extern void TIMER_B_disableCaptureCompareInterrupt(uint16_t baseAddress, + uint16_t captureCompareRegister); + +extern uint32_t TIMER_B_getCaptureCompareInterruptStatus(uint16_t baseAddress, + uint16_t captureCompareRegister, + uint16_t mask); + +extern void TIMER_B_clear(uint16_t baseAddress); + +extern uint8_t TIMER_B_getSynchronizedCaptureCompareInput(uint16_t baseAddress, + uint16_t captureCompareRegister, + uint16_t synchronized); + +extern uint8_t TIMER_B_getOutputForOutputModeOutBitValue(uint16_t baseAddress, + uint16_t captureCompareRegister); + +extern uint16_t TIMER_B_getCaptureCompareCount(uint16_t baseAddress, + uint16_t captureCompareRegister); + +extern void TIMER_B_setOutputForOutputModeOutBitValue(uint16_t baseAddress, + uint16_t captureCompareRegister, + uint8_t outputModeOutBitValue); + +extern void TIMER_B_outputPWM(uint16_t baseAddress, + TIMER_B_outputPWMParam *param); + +extern void TIMER_B_stop(uint16_t baseAddress); + +extern void TIMER_B_setCompareValue(uint16_t baseAddress, + uint16_t compareRegister, + uint16_t compareValue); + +extern void TIMER_B_clearTimerInterruptFlag(uint16_t baseAddress); + +extern void TIMER_B_clearCaptureCompareInterruptFlag(uint16_t baseAddress, + uint16_t captureCompareRegister); + +extern void TIMER_B_selectCounterLength(uint16_t baseAddress, + uint16_t counterLength); + +extern void TIMER_B_selectLatchingGroup(uint16_t baseAddress, + uint16_t groupLatch); + +extern void TIMER_B_initCompareLatchLoadEvent(uint16_t baseAddress, + uint16_t compareRegister, + uint16_t compareLatchLoadEvent); + +extern uint16_t TIMER_B_getCounterValue(uint16_t baseAddress); + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +extern void TIMER_B_configureContinuousMode(uint16_t baseAddress, + uint16_t clockSource, + uint16_t clockSourceDivider, + uint16_t timerInterruptEnable_TBIE, + uint16_t timerClear); + +extern void TIMER_B_configureUpMode(uint16_t baseAddress, + uint16_t clockSource, + uint16_t clockSourceDivider, + uint16_t timerPeriod, + uint16_t timerInterruptEnable_TBIE, + uint16_t captureCompareInterruptEnable_CCR0_CCIE, + uint16_t timerClear); + +extern void TIMER_B_configureUpDownMode(uint16_t baseAddress, + uint16_t clockSource, + uint16_t clockSourceDivider, + uint16_t timerPeriod, + uint16_t timerInterruptEnable_TBIE, + uint16_t captureCompareInterruptEnable_CCR0_CCIE, + uint16_t timerClear); + +extern void TIMER_B_startContinuousMode(uint16_t baseAddress, + uint16_t clockSource, + uint16_t clockSourceDivider, + uint16_t timerInterruptEnable_TBIE, + uint16_t timerClear); + +extern void TIMER_B_startContinousMode(uint16_t baseAddress, + uint16_t clockSource, + uint16_t clockSourceDivider, + uint16_t timerInterruptEnable_TBIE, + uint16_t timerClear); + +extern void TIMER_B_startUpMode(uint16_t baseAddress, + uint16_t clockSource, + uint16_t clockSourceDivider, + uint16_t timerPeriod, + uint16_t timerInterruptEnable_TBIE, + uint16_t captureCompareInterruptEnable_CCR0_CCIE, + uint16_t timerClear); + +extern void TIMER_B_startUpDownMode(uint16_t baseAddress, + uint16_t clockSource, + uint16_t clockSourceDivider, + uint16_t timerPeriod, + uint16_t timerInterruptEnable_TBIE, + uint16_t captureCompareInterruptEnable_CCR0_CCIE, + uint16_t timerClear); + +extern void TIMER_B_initCapture(uint16_t baseAddress, + uint16_t captureRegister, + uint16_t captureMode, + uint16_t captureInputSelect, + uint16_t synchronizeCaptureSource, + uint16_t captureInterruptEnable, + uint16_t captureOutputMode); + +extern void TIMER_B_initCompare(uint16_t baseAddress, + uint16_t compareRegister, + uint16_t compareInterruptEnable, + uint16_t compareOutputMode, + uint16_t compareValue); + +extern void TIMER_B_generatePWM(uint16_t baseAddress, + uint16_t clockSource, + uint16_t clockSourceDivider, + uint16_t timerPeriod, + uint16_t compareRegister, + uint16_t compareOutputMode, + uint16_t dutyCycle); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_TIMER_B_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/timer_d.c b/source/driverlib/MSP430F5xx_6xx/timer_d.c new file mode 100644 index 0000000..2234e0d --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/timer_d.c @@ -0,0 +1,2401 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// timer_d.c - Driver for the timer_d Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup timer_d_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_TxD7__ +#include "timer_d.h" + +#include + +//***************************************************************************** +// +//! \brief Starts TIMER_D counter +//! +//! NOTE: This function assumes that the timer has been previously configured +//! using TIMER_D_configureContinuousMode, TIMER_D_configureUpMode or +//! TIMER_D_configureUpDownMode. +//! +//! \param baseAddress is the base address of the TIMER_DA module. +//! \param timerMode selects the mode of the timer +//! Valid values are: +//! - \b TIMER_D_STOP_MODE +//! - \b TIMER_D_UP_MODE +//! - \b TIMER_D_CONTINUOUS_MODE [Default] +//! - \b TIMER_D_UPDOWN_MODE +//! +//! Modified bits of \b TDxCTL0 register. +//! +//! \return None +// +//***************************************************************************** +#include "tlv.h" +void TIMER_D_startCounter( uint16_t baseAddress, + uint16_t timerMode + ) +{ + assert( + (TIMER_D_UPDOWN_MODE == timerMode) || + (TIMER_D_CONTINUOUS_MODE == timerMode) || + (TIMER_D_UP_MODE == timerMode) + ); + + HWREG16(baseAddress + OFS_TDxCTL0) |= timerMode; +} +//***************************************************************************** +// +//! \brief Configures timer in continuous mode. +//! +//! This API does not start the timer. Timer needs to be started when required +//! using the TIMER_D_start API. +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! \param param is the pointer to struct for continuous mode initialization. +//! +//! Modified bits of \b TDxCTL0 register and bits of \b TDxCTL1 register. +//! +//! \return None +// +//***************************************************************************** + +void TIMER_D_initContinuousMode(uint16_t baseAddress, + TIMER_D_initContinuousModeParam *param) +{ + assert(param != 0); + + assert( + (TIMER_D_DO_CLEAR == param->timerClear) || + (TIMER_D_SKIP_CLEAR == param->timerClear) + ); + + assert( + (TIMER_D_TDIE_INTERRUPT_ENABLE == param->timerInterruptEnable_TDIE) || + (TIMER_D_TDIE_INTERRUPT_DISABLE == param->timerInterruptEnable_TDIE) + ); + + assert( + (TIMER_D_CLOCKSOURCE_EXTERNAL_TDCLK == param->clockSource) || + (TIMER_D_CLOCKSOURCE_ACLK == param->clockSource) || + (TIMER_D_CLOCKSOURCE_SMCLK == param->clockSource) || + (TIMER_D_CLOCKSOURCE_INVERTED_EXTERNAL_TDCLK == param->clockSource) + ); + + assert( + (TIMER_D_CLOCKSOURCE_DIVIDER_1 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_2 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_4 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_8 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_3 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_5 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_6 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_7 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_10 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_12 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_14 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_16 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_20 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_24 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_28 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_32 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_40 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_48 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_56 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_64 == param->clockSourceDivider) + ); + + assert( + (TIMER_D_CLOCKINGMODE_EXTERNAL_CLOCK == param->clockingMode) || + (TIMER_D_CLOCKINGMODE_HIRES_LOCAL_CLOCK == param->clockingMode) || + (TIMER_D_CLOCKINGMODE_AUXILIARY_CLK == param->clockingMode) + ); + + HWREG16(baseAddress + + OFS_TDxCTL0) &= ~(TIMER_D_CLOCKSOURCE_INVERTED_EXTERNAL_TDCLK + + TIMER_D_UPDOWN_MODE + + TIMER_D_DO_CLEAR + + TIMER_D_TDIE_INTERRUPT_ENABLE + + ID__8 + ); + HWREG16(baseAddress + OFS_TDxCTL1) &= ~(TDCLKM0 + TDCLKM1 + TDIDEX_7); + + HWREG16(baseAddress + OFS_TDxCTL0) |= param->clockSource; + HWREG16(baseAddress + OFS_TDxCTL1) |= (param->clockingMode + + ((param->clockSourceDivider & 0x7) << 8)); + + HWREG16(baseAddress + OFS_TDxCTL0) |= (param->timerClear + + param->timerInterruptEnable_TDIE + + ((param->clockSourceDivider >> 3) << 6)); +} + +//***************************************************************************** +// +//! \brief DEPRECATED - Configures timer in continuous mode. +//! +//! This API does not start the timer. Timer needs to be started when required +//! using the TIMER_D_start API. +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! \param clockSource selects Clock source. +//! Valid values are: +//! - \b TIMER_D_CLOCKSOURCE_EXTERNAL_TDCLK [Default] +//! - \b TIMER_D_CLOCKSOURCE_ACLK +//! - \b TIMER_D_CLOCKSOURCE_SMCLK +//! - \b TIMER_D_CLOCKSOURCE_INVERTED_EXTERNAL_TDCLK +//! \param clockSourceDivider is the divider for clock source. +//! Valid values are: +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_1 [Default] +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_2 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_3 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_4 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_5 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_6 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_7 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_8 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_10 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_12 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_14 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_16 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_20 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_24 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_28 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_32 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_40 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_48 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_56 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_64 +//! \param clockingMode is the selected clock mode register values. +//! Valid values are: +//! - \b TIMER_D_CLOCKINGMODE_EXTERNAL_CLOCK [Default] +//! - \b TIMER_D_CLOCKINGMODE_HIRES_LOCAL_CLOCK +//! - \b TIMER_D_CLOCKINGMODE_AUXILIARY_CLK +//! \param timerInterruptEnable_TDIE is to enable or disable timer interrupt +//! Valid values are: +//! - \b TIMER_D_TDIE_INTERRUPT_ENABLE +//! - \b TIMER_D_TDIE_INTERRUPT_DISABLE [Default] +//! \param timerClear decides if timer clock divider, count direction, count +//! need to be reset. +//! Valid values are: +//! - \b TIMER_D_DO_CLEAR +//! - \b TIMER_D_SKIP_CLEAR [Default] +//! +//! Modified bits of \b TDxCTL0 register and bits of \b TDxCTL1 register. +//! +//! \return None +// +//***************************************************************************** + +void TIMER_D_configureContinuousMode( uint16_t baseAddress, + uint16_t clockSource, + uint16_t clockSourceDivider, + uint16_t clockingMode, + uint16_t timerInterruptEnable_TDIE, + uint16_t timerClear + ) +{ + TIMER_D_initContinuousModeParam param = { 0 }; + + param.clockSource = clockSource; + param.clockSourceDivider = clockSourceDivider; + param.clockingMode = clockingMode; + param.timerInterruptEnable_TDIE = timerInterruptEnable_TDIE; + param.timerClear = timerClear; + + TIMER_D_initContinuousMode(baseAddress, ¶m); +} +//***************************************************************************** +// +//! \brief Configures timer in up mode. +//! +//! This API does not start the timer. Timer needs to be started when required +//! using the TIMER_D_start API. +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! \param param is the pointer to struct for up mode initialization. +//! +//! Modified bits of \b TDxCCR0 register, bits of \b TDxCCTL0 register, bits of +//! \b TDxCTL0 register and bits of \b TDxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_D_initUpMode(uint16_t baseAddress, TIMER_D_initUpModeParam *param) +{ + assert(param != 0); + + assert( + (TIMER_D_DO_CLEAR == param->timerClear) || + (TIMER_D_SKIP_CLEAR == param->timerClear) + ); + + assert( + (TIMER_D_CLOCKSOURCE_EXTERNAL_TDCLK == param->clockSource) || + (TIMER_D_CLOCKSOURCE_ACLK == param->clockSource) || + (TIMER_D_CLOCKSOURCE_SMCLK == param->clockSource) || + (TIMER_D_CLOCKSOURCE_INVERTED_EXTERNAL_TDCLK == param->clockSource) + ); + + assert( + (TIMER_D_CLOCKSOURCE_DIVIDER_1 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_2 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_4 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_8 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_3 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_5 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_6 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_7 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_10 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_12 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_14 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_16 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_20 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_24 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_28 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_32 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_40 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_48 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_56 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_64 == param->clockSourceDivider) + ); + + assert( + (TIMER_D_CLOCKINGMODE_EXTERNAL_CLOCK == param->clockingMode) || + (TIMER_D_CLOCKINGMODE_HIRES_LOCAL_CLOCK == param->clockingMode) || + (TIMER_D_CLOCKINGMODE_AUXILIARY_CLK == param->clockingMode) + ); + + HWREG16(baseAddress + OFS_TDxCTL0) &= + ~(TIMER_D_CLOCKSOURCE_INVERTED_EXTERNAL_TDCLK + + TIMER_D_UPDOWN_MODE + + TIMER_D_DO_CLEAR + + TIMER_D_TDIE_INTERRUPT_ENABLE + + ID__8 + ); + HWREG16(baseAddress + OFS_TDxCTL1) &= ~(TDCLKM0 + TDCLKM1 + TDIDEX_7); + + HWREG16(baseAddress + OFS_TDxCTL0) |= param->clockSource; + HWREG16(baseAddress + OFS_TDxCTL1) |= (param->clockingMode + + ((param->clockSourceDivider & 0x7) << 8)); + + HWREG16(baseAddress + OFS_TDxCTL0) |= (TIMER_D_STOP_MODE + + param->timerClear + + param->timerInterruptEnable_TDIE + + ((param->clockSourceDivider >> 3) << 6)); + + if (TIMER_D_CCIE_CCR0_INTERRUPT_ENABLE == + param->captureCompareInterruptEnable_CCR0_CCIE) + HWREG16(baseAddress + OFS_TDxCCTL0) |= TIMER_D_CCIE_CCR0_INTERRUPT_ENABLE; + else + HWREG16(baseAddress + OFS_TDxCCTL0) &= ~TIMER_D_CCIE_CCR0_INTERRUPT_ENABLE; + + HWREG16(baseAddress + OFS_TDxCCR0) = param->timerPeriod; +} + +//***************************************************************************** +// +//! \brief DEPRECATED - Configures timer in up mode. +//! +//! This API does not start the timer. Timer needs to be started when required +//! using the TIMER_D_start API. +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! \param clockSource selects Clock source. +//! Valid values are: +//! - \b TIMER_D_CLOCKSOURCE_EXTERNAL_TDCLK [Default] +//! - \b TIMER_D_CLOCKSOURCE_ACLK +//! - \b TIMER_D_CLOCKSOURCE_SMCLK +//! - \b TIMER_D_CLOCKSOURCE_INVERTED_EXTERNAL_TDCLK +//! \param clockSourceDivider is the divider for clock source. +//! Valid values are: +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_1 [Default] +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_2 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_3 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_4 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_5 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_6 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_7 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_8 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_10 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_12 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_14 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_16 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_20 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_24 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_28 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_32 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_40 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_48 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_56 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_64 +//! \param clockingMode is the selected clock mode register values. +//! Valid values are: +//! - \b TIMER_D_CLOCKINGMODE_EXTERNAL_CLOCK [Default] +//! - \b TIMER_D_CLOCKINGMODE_HIRES_LOCAL_CLOCK +//! - \b TIMER_D_CLOCKINGMODE_AUXILIARY_CLK +//! \param timerPeriod is the specified timer period. This is the value that +//! gets written into the CCR0. Limited to 16 bits [uint16_t] +//! \param timerInterruptEnable_TDIE is to enable or disable timer interrupt +//! Valid values are: +//! - \b TIMER_D_TDIE_INTERRUPT_ENABLE +//! - \b TIMER_D_TDIE_INTERRUPT_DISABLE [Default] +//! \param captureCompareInterruptEnable_CCR0_CCIE is to enable or disable +//! timer CCR0 captureComapre interrupt. +//! Valid values are: +//! - \b TIMER_D_CCIE_CCR0_INTERRUPT_ENABLE +//! - \b TIMER_D_CCIE_CCR0_INTERRUPT_DISABLE [Default] +//! \param timerClear decides if timer clock divider, count direction, count +//! need to be reset. +//! Valid values are: +//! - \b TIMER_D_DO_CLEAR +//! - \b TIMER_D_SKIP_CLEAR [Default] +//! +//! Modified bits of \b TDxCCR0 register, bits of \b TDxCCTL0 register, bits of +//! \b TDxCTL0 register and bits of \b TDxCTL1 register. +//! +//! \return None +// +//***************************************************************************** + +void TIMER_D_configureUpMode( uint16_t baseAddress, + uint16_t clockSource, + uint16_t clockSourceDivider, + uint16_t clockingMode, + uint16_t timerPeriod, + uint16_t timerInterruptEnable_TDIE, + uint16_t captureCompareInterruptEnable_CCR0_CCIE, + uint16_t timerClear + ) +{ + TIMER_D_initUpModeParam param = { 0 }; + + param.clockSource = clockSource; + param.clockSourceDivider = clockSourceDivider; + param.clockingMode = clockingMode; + param.timerPeriod = timerPeriod; + param.timerInterruptEnable_TDIE = timerInterruptEnable_TDIE; + param.captureCompareInterruptEnable_CCR0_CCIE = + captureCompareInterruptEnable_CCR0_CCIE; + param.timerClear = timerClear; + + TIMER_D_initUpMode(baseAddress, ¶m); + +} +//***************************************************************************** +// +//! \brief Configures timer in up down mode. +//! +//! This API does not start the timer. Timer needs to be started when required +//! using the TIMER_D_start API. +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! \param param is the pointer to struct for up-down mode initialization. +//! +//! Modified bits of \b TDxCCR0 register, bits of \b TDxCCTL0 register, bits of +//! \b TDxCTL0 register and bits of \b TDxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_D_initUpDownMode(uint16_t baseAddress, + TIMER_D_initUpDownModeParam *param) +{ + assert(param != 0); + + assert( + (TIMER_D_DO_CLEAR == param->timerClear) || + (TIMER_D_SKIP_CLEAR == param->timerClear) + ); + + assert( + (TIMER_D_CLOCKSOURCE_EXTERNAL_TDCLK == param->clockSource) || + (TIMER_D_CLOCKSOURCE_ACLK == param->clockSource) || + (TIMER_D_CLOCKSOURCE_SMCLK == param->clockSource) || + (TIMER_D_CLOCKSOURCE_INVERTED_EXTERNAL_TDCLK == param->clockSource) + ); + + assert( + (TIMER_D_CLOCKSOURCE_DIVIDER_1 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_2 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_4 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_8 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_3 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_5 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_6 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_7 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_10 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_12 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_14 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_16 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_20 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_24 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_28 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_32 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_40 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_48 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_56 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_64 == param->clockSourceDivider) + ); + + assert( + (TIMER_D_CLOCKINGMODE_EXTERNAL_CLOCK == param->clockingMode) || + (TIMER_D_CLOCKINGMODE_HIRES_LOCAL_CLOCK == param->clockingMode) || + (TIMER_D_CLOCKINGMODE_AUXILIARY_CLK == param->clockingMode) + ); + + HWREG16(baseAddress + OFS_TDxCTL0) &= + ~(TIMER_D_CLOCKSOURCE_INVERTED_EXTERNAL_TDCLK + + TIMER_D_UPDOWN_MODE + + TIMER_D_DO_CLEAR + + TIMER_D_TDIE_INTERRUPT_ENABLE + + ID__8 + ); + HWREG16(baseAddress + OFS_TDxCTL1) &= ~(TDCLKM0 + TDCLKM1 + TDIDEX_7); + + HWREG16(baseAddress + OFS_TDxCTL0) |= param->clockSource; + HWREG16(baseAddress + OFS_TDxCTL1) |= (param->clockingMode + + ((param->clockSourceDivider & 0x7) << 8)); + + HWREG16(baseAddress + OFS_TDxCTL0) |= (TIMER_D_STOP_MODE + + param->timerClear + + param->timerInterruptEnable_TDIE + + ((param->clockSourceDivider >> 3) << 6)); + + if (TIMER_D_CCIE_CCR0_INTERRUPT_ENABLE == + param->captureCompareInterruptEnable_CCR0_CCIE) + HWREG16(baseAddress + OFS_TDxCCTL0) |= TIMER_D_CCIE_CCR0_INTERRUPT_ENABLE; + else + HWREG16(baseAddress + OFS_TDxCCTL0) &= ~TIMER_D_CCIE_CCR0_INTERRUPT_ENABLE; + + HWREG16(baseAddress + OFS_TDxCCR0) = param->timerPeriod; +} + +//***************************************************************************** +// +//! \brief DEPRECATED - Configures timer in up down mode. +//! +//! This API does not start the timer. Timer needs to be started when required +//! using the TIMER_D_start API. +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! \param clockSource selects Clock source. +//! Valid values are: +//! - \b TIMER_D_CLOCKSOURCE_EXTERNAL_TDCLK [Default] +//! - \b TIMER_D_CLOCKSOURCE_ACLK +//! - \b TIMER_D_CLOCKSOURCE_SMCLK +//! - \b TIMER_D_CLOCKSOURCE_INVERTED_EXTERNAL_TDCLK +//! \param clockSourceDivider is the divider for clock source. +//! Valid values are: +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_1 [Default] +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_2 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_3 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_4 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_5 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_6 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_7 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_8 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_10 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_12 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_14 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_16 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_20 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_24 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_28 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_32 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_40 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_48 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_56 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_64 +//! \param clockingMode is the selected clock mode register values. +//! Valid values are: +//! - \b TIMER_D_CLOCKINGMODE_EXTERNAL_CLOCK [Default] +//! - \b TIMER_D_CLOCKINGMODE_HIRES_LOCAL_CLOCK +//! - \b TIMER_D_CLOCKINGMODE_AUXILIARY_CLK +//! \param timerPeriod is the specified timer period +//! \param timerInterruptEnable_TDIE is to enable or disable timer interrupt +//! Valid values are: +//! - \b TIMER_D_TDIE_INTERRUPT_ENABLE +//! - \b TIMER_D_TDIE_INTERRUPT_DISABLE [Default] +//! \param captureCompareInterruptEnable_CCR0_CCIE is to enable or disable +//! timer CCR0 captureComapre interrupt. +//! Valid values are: +//! - \b TIMER_D_CCIE_CCR0_INTERRUPT_ENABLE +//! - \b TIMER_D_CCIE_CCR0_INTERRUPT_DISABLE [Default] +//! \param timerClear decides if timer clock divider, count direction, count +//! need to be reset. +//! Valid values are: +//! - \b TIMER_D_DO_CLEAR +//! - \b TIMER_D_SKIP_CLEAR [Default] +//! +//! Modified bits of \b TDxCCR0 register, bits of \b TDxCCTL0 register, bits of +//! \b TDxCTL0 register and bits of \b TDxCTL1 register. +//! +//! \return None +// +//***************************************************************************** + +void TIMER_D_configureUpDownMode( + uint16_t baseAddress, + uint16_t clockSource, + uint16_t clockSourceDivider, + uint16_t clockingMode, + uint16_t timerPeriod, + uint16_t timerInterruptEnable_TDIE, + uint16_t captureCompareInterruptEnable_CCR0_CCIE, + uint16_t timerClear + ) +{ + TIMER_D_initUpDownModeParam param = { 0 }; + + param.clockSource = clockSource; + param.clockSourceDivider = clockSourceDivider; + param.clockingMode = clockingMode; + param.timerPeriod = timerPeriod; + param.timerInterruptEnable_TDIE = timerInterruptEnable_TDIE; + param.captureCompareInterruptEnable_CCR0_CCIE = + captureCompareInterruptEnable_CCR0_CCIE; + param.timerClear = timerClear; + + TIMER_D_initUpDownMode(baseAddress, ¶m); +} +//***************************************************************************** +// +//! \brief Initializes Capture Mode +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! \param param is the pointer to struct for capture mode initialization. +//! +//! Modified bits of \b TDxCCTLn register and bits of \b TDxCTL2 register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_D_initCaptureMode(uint16_t baseAddress, + TIMER_D_initCaptureModeParam *param) +{ + assert(param != 0); + + assert((TIMER_D_CAPTURECOMPARE_REGISTER_0 == param->captureRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_1 == param->captureRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_2 == param->captureRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_3 == param->captureRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_4 == param->captureRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_5 == param->captureRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_6 == param->captureRegister) + ); + + assert((TIMER_D_CAPTUREMODE_NO_CAPTURE == param->captureMode) || + (TIMER_D_CAPTUREMODE_RISING_EDGE == param->captureMode) || + (TIMER_D_CAPTUREMODE_FALLING_EDGE == param->captureMode) || + (TIMER_D_CAPTUREMODE_RISING_AND_FALLING_EDGE == param->captureMode) + ); + + assert((TIMER_D_CAPTURE_INPUTSELECT_CCIxA == param->captureInputSelect) || + (TIMER_D_CAPTURE_INPUTSELECT_CCIxB == param->captureInputSelect) || + (TIMER_D_CAPTURE_INPUTSELECT_GND == param->captureInputSelect) || + (TIMER_D_CAPTURE_INPUTSELECT_Vcc == param->captureInputSelect) + ); + + assert((TIMER_D_CAPTURE_ASYNCHRONOUS == param->synchronizeCaptureSource) || + (TIMER_D_CAPTURE_SYNCHRONOUS == param->synchronizeCaptureSource) + ); + + assert( + (TIMER_D_CAPTURECOMPARE_INTERRUPT_DISABLE == param->captureInterruptEnable) || + (TIMER_D_CAPTURECOMPARE_INTERRUPT_ENABLE == param->captureInterruptEnable) + ); + + assert((TIMER_D_OUTPUTMODE_OUTBITVALUE == param->captureOutputMode) || + (TIMER_D_OUTPUTMODE_SET == param->captureOutputMode) || + (TIMER_D_OUTPUTMODE_TOGGLE_RESET == param->captureOutputMode) || + (TIMER_D_OUTPUTMODE_SET_RESET == param->captureOutputMode) || + (TIMER_D_OUTPUTMODE_TOGGLE == param->captureOutputMode) || + (TIMER_D_OUTPUTMODE_RESET == param->captureOutputMode) || + (TIMER_D_OUTPUTMODE_TOGGLE_SET == param->captureOutputMode) || + (TIMER_D_OUTPUTMODE_RESET_SET == param->captureOutputMode) + ); + + assert((TIMER_D_SINGLE_CAPTURE_MODE == param->channelCaptureMode) || + (TIMER_D_DUAL_CAPTURE_MODE == param->channelCaptureMode) + ); + + //CaptureCompare register 0 only supports certain modes + assert((TIMER_D_CAPTURECOMPARE_REGISTER_0 == param->captureRegister) && + ((TIMER_D_OUTPUTMODE_OUTBITVALUE == param->captureOutputMode) || + (TIMER_D_OUTPUTMODE_SET == param->captureOutputMode) || + (TIMER_D_OUTPUTMODE_TOGGLE == param->captureOutputMode) || + (TIMER_D_OUTPUTMODE_RESET == param->captureOutputMode))); + + HWREG16(baseAddress + param->captureRegister ) |= CAP; + + HWREG8(baseAddress + OFS_TDxCTL2) |= + (param->channelCaptureMode << ((param->captureRegister - TIMER_D_CAPTURECOMPARE_REGISTER_0) / 6)); + + HWREG16(baseAddress + param->captureRegister) &= + ~(TIMER_D_CAPTUREMODE_RISING_AND_FALLING_EDGE + + TIMER_D_CAPTURE_INPUTSELECT_Vcc + + TIMER_D_CAPTURE_SYNCHRONOUS + + TIMER_D_DO_CLEAR + + TIMER_D_TDIE_INTERRUPT_ENABLE + + CM_3 + ); + + HWREG16(baseAddress + param->captureRegister) |= (param->captureMode + + param->captureInputSelect + + param->synchronizeCaptureSource + + param->captureInterruptEnable + + param->captureOutputMode + ); +} + +//***************************************************************************** +// +//! \brief DEPRECATED - Initializes Capture Mode +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! \param captureRegister selects the Capture register being used. Refer to +//! datasheet to ensure the device has the capture compare register +//! being used +//! Valid values are: +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_6 +//! \param captureMode is the capture mode selected. +//! Valid values are: +//! - \b TIMER_D_CAPTUREMODE_NO_CAPTURE [Default] +//! - \b TIMER_D_CAPTUREMODE_RISING_EDGE +//! - \b TIMER_D_CAPTUREMODE_FALLING_EDGE +//! - \b TIMER_D_CAPTUREMODE_RISING_AND_FALLING_EDGE +//! \param captureInputSelect decides the Input Select +//! Valid values are: +//! - \b TIMER_D_CAPTURE_INPUTSELECT_CCIxA [Default] +//! - \b TIMER_D_CAPTURE_INPUTSELECT_CCIxB +//! - \b TIMER_D_CAPTURE_INPUTSELECT_GND +//! - \b TIMER_D_CAPTURE_INPUTSELECT_Vcc +//! \param synchronizeCaptureSource decides if capture source should be +//! synchronized with timer clock +//! Valid values are: +//! - \b TIMER_D_CAPTURE_ASYNCHRONOUS [Default] +//! - \b TIMER_D_CAPTURE_SYNCHRONOUS +//! +//! Modified bits of \b TDxCCTLn register and bits of \b TDxCTL2 register. +//! +//! \return None +// +//***************************************************************************** + +void TIMER_D_initCapture(uint16_t baseAddress, + uint16_t captureRegister, + uint16_t captureMode, + uint16_t captureInputSelect, + uint16_t synchronizeCaptureSource, + uint16_t captureInterruptEnable, + uint16_t captureOutputMode, + uint8_t channelCaptureMode + ) +{ + TIMER_D_initCaptureModeParam param = { 0 }; + + param.captureRegister = captureRegister; + param.captureMode = captureMode; + param.captureInputSelect = captureInputSelect; + param.synchronizeCaptureSource = synchronizeCaptureSource; + param.captureInterruptEnable = captureInterruptEnable; + param.captureOutputMode = captureOutputMode; + param.channelCaptureMode = channelCaptureMode; + + TIMER_D_initCaptureMode(baseAddress, ¶m); +} +//***************************************************************************** +// +//! \brief Initializes Compare Mode +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! \param param is the pointer to struct for compare mode initialization. +//! +//! Modified bits of \b TDxCCTLn register and bits of \b TDxCCRn register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_D_initCompareMode(uint16_t baseAddress, + TIMER_D_initCompareModeParam *param) +{ + assert(param != 0); + + assert((TIMER_D_CAPTURECOMPARE_REGISTER_0 == param->compareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_1 == param->compareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_2 == param->compareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_3 == param->compareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_4 == param->compareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_5 == param->compareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_6 == param->compareRegister) + ); + + assert((TIMER_D_CAPTURECOMPARE_INTERRUPT_ENABLE == param->compareInterruptEnable) || + (TIMER_D_CAPTURECOMPARE_INTERRUPT_DISABLE == param->compareInterruptEnable) + ); + + assert((TIMER_D_OUTPUTMODE_OUTBITVALUE == param->compareOutputMode) || + (TIMER_D_OUTPUTMODE_SET == param->compareOutputMode) || + (TIMER_D_OUTPUTMODE_TOGGLE_RESET == param->compareOutputMode) || + (TIMER_D_OUTPUTMODE_SET_RESET == param->compareOutputMode) || + (TIMER_D_OUTPUTMODE_TOGGLE == param->compareOutputMode) || + (TIMER_D_OUTPUTMODE_RESET == param->compareOutputMode) || + (TIMER_D_OUTPUTMODE_TOGGLE_SET == param->compareOutputMode) || + (TIMER_D_OUTPUTMODE_RESET_SET == param->compareOutputMode) + ); + + //CaptureCompare register 0 only supports certain modes + assert((TIMER_D_CAPTURECOMPARE_REGISTER_0 == param->compareRegister) && + ((TIMER_D_OUTPUTMODE_OUTBITVALUE == param->compareOutputMode) || + (TIMER_D_OUTPUTMODE_SET == param->compareOutputMode) || + (TIMER_D_OUTPUTMODE_TOGGLE == param->compareOutputMode) || + (TIMER_D_OUTPUTMODE_RESET == param->compareOutputMode))); + + HWREG16(baseAddress + param->compareRegister ) &= ~CAP; + + HWREG16(baseAddress + param->compareRegister) &= + ~(TIMER_D_CAPTURECOMPARE_INTERRUPT_ENABLE + + TIMER_D_OUTPUTMODE_RESET_SET + ); + + HWREG16(baseAddress + param->compareRegister) |= (param->compareInterruptEnable + + param->compareOutputMode + ); + + HWREG16(baseAddress + param->compareRegister + 2) = param->compareValue; +} + +//***************************************************************************** +// +//! \brief DEPRECATED - Initializes Compare Mode +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! \param compareRegister selects the Capture register being used. +//! Valid values are: +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_6 +//! \param compareInterruptEnable is to enable or disable timer captureComapre +//! interrupt. +//! Valid values are: +//! - \b TIMER_D_CAPTURECOMPARE_INTERRUPT_ENABLE +//! - \b TIMER_D_CAPTURECOMPARE_INTERRUPT_DISABLE [Default] +//! \param compareOutputMode specifies the output mode. +//! Valid values are: +//! - \b TIMER_D_OUTPUTMODE_OUTBITVALUE [Default] +//! - \b TIMER_D_OUTPUTMODE_SET +//! - \b TIMER_D_OUTPUTMODE_TOGGLE_RESET +//! - \b TIMER_D_OUTPUTMODE_SET_RESET +//! - \b TIMER_D_OUTPUTMODE_TOGGLE +//! - \b TIMER_D_OUTPUTMODE_RESET +//! - \b TIMER_D_OUTPUTMODE_TOGGLE_SET +//! - \b TIMER_D_OUTPUTMODE_RESET_SET +//! \param compareValue is the count to be compared with in compare mode +//! +//! Modified bits of \b TDxCCTLn register and bits of \b TDxCCRn register. +//! +//! \return None +// +//***************************************************************************** + +void TIMER_D_initCompare( uint16_t baseAddress, + uint16_t compareRegister, + uint16_t compareInterruptEnable, + uint16_t compareOutputMode, + uint16_t compareValue + ) +{ + TIMER_D_initCompareModeParam param = { 0 }; + + param.compareRegister = compareRegister; + param.compareInterruptEnable = compareInterruptEnable; + param.compareOutputMode = compareOutputMode; + param.compareValue = compareValue; + + TIMER_D_initCompareMode(baseAddress, ¶m); +} +//***************************************************************************** +// +//! \brief Enable timer interrupt +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! +//! Modified bits of \b TDxCTL0 register. +//! +//! \return None +// +//***************************************************************************** + +void TIMER_D_enableTimerInterrupt(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_TDxCTL0) &= ~TDIFG; + HWREG8(baseAddress + OFS_TDxCTL0) |= TDIE; +} +//***************************************************************************** +// +//! \brief Enable High Resolution interrupt +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! \param mask is the mask of interrupts to enable +//! Mask value is the logical OR of any of the following: +//! - \b TIMER_D_HIGH_RES_FREQUENCY_UNLOCK +//! - \b TIMER_D_HIGH_RES_FREQUENCY_LOCK +//! - \b TIMER_D_HIGH_RES_FAIL_HIGH +//! - \b TIMER_D_HIGH_RES_FAIL_LOW +//! +//! Modified bits of \b TDxHINT register. +//! +//! \return None +// +//***************************************************************************** + +void TIMER_D_enableHighResInterrupt(uint16_t baseAddress, + uint16_t mask) +{ + HWREG16(baseAddress + OFS_TDxHINT) &= ~(mask >> 8); + HWREG16(baseAddress + OFS_TDxHINT) |= mask; +} +//***************************************************************************** +// +//! \brief Disable timer interrupt +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! +//! Modified bits of \b TDxCTL0 register. +//! +//! \return None +// +//***************************************************************************** + +void TIMER_D_disableTimerInterrupt(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_TDxCTL0) &= ~TDIE; +} +//***************************************************************************** +// +//! \brief Disable High Resolution interrupt +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! \param mask is the mask of interrupts to disable +//! Mask value is the logical OR of any of the following: +//! - \b TIMER_D_HIGH_RES_FREQUENCY_UNLOCK +//! - \b TIMER_D_HIGH_RES_FREQUENCY_LOCK +//! - \b TIMER_D_HIGH_RES_FAIL_HIGH +//! - \b TIMER_D_HIGH_RES_FAIL_LOW +//! +//! Modified bits of \b TDxHINT register. +//! +//! \return None +// +//***************************************************************************** + +void TIMER_D_disableHighResInterrupt(uint16_t baseAddress, + uint16_t mask) +{ + HWREG16(baseAddress + OFS_TDxHINT) &= ~mask; +} +//***************************************************************************** +// +//! \brief Get timer interrupt status +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! +//! \return One of the following: +//! - \b TIMER_D_INTERRUPT_NOT_PENDING +//! - \b TIMER_D_INTERRUPT_PENDING +//! \n indicating the timer interrupt status +// +//***************************************************************************** + +uint32_t TIMER_D_getTimerInterruptStatus(uint16_t baseAddress) +{ + return HWREG8(baseAddress + OFS_TDxCTL0) & TDIFG; +} +//***************************************************************************** +// +//! \brief Enable capture compare interrupt +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! \param captureCompareRegister is the selected capture compare register +//! Valid values are: +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_6 +//! +//! Modified bits of \b TDxCCTLn register. +//! +//! \return None +// +//***************************************************************************** + +void TIMER_D_enableCaptureCompareInterrupt(uint16_t baseAddress, + uint16_t captureCompareRegister + ) +{ + assert((TIMER_D_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_1 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_2 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_3 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_4 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_5 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_6 == captureCompareRegister) + ); + + HWREG8(baseAddress + captureCompareRegister) &= ~CCIFG; + HWREG16(baseAddress + captureCompareRegister) |= CCIE; +} +//***************************************************************************** +// +//! \brief Disable capture compare interrupt +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! \param captureCompareRegister is the selected capture compare register +//! Valid values are: +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_6 +//! +//! Modified bits of \b TDxCCTLn register. +//! +//! \return None +// +//***************************************************************************** + +void TIMER_D_disableCaptureCompareInterrupt(uint16_t baseAddress, + uint16_t captureCompareRegister + ) +{ + assert((TIMER_D_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_1 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_2 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_3 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_4 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_5 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_6 == captureCompareRegister) + ); + HWREG16(baseAddress + captureCompareRegister) &= ~CCIE; +} +//***************************************************************************** +// +//! \brief Return capture compare interrupt status +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! \param captureCompareRegister is the selected capture compare register +//! Valid values are: +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_6 +//! \param mask is the mask for the interrupt status +//! Mask value is the logical OR of any of the following: +//! - \b TIMER_D_CAPTURE_OVERFLOW +//! - \b TIMER_D_CAPTURECOMPARE_INTERRUPT_FLAG +//! +//! \return Logical OR of any of the following: +//! - \b TIMER_D_CAPTURE_OVERFLOW +//! - \b TIMER_D_CAPTURECOMPARE_INTERRUPT_FLAG +//! \n indicating the status of the masked flags +// +//***************************************************************************** + +uint32_t TIMER_D_getCaptureCompareInterruptStatus(uint16_t baseAddress, + uint16_t captureCompareRegister, + uint16_t mask + ) +{ + return HWREG16(baseAddress + captureCompareRegister) & mask; +} +//***************************************************************************** +// +//! \brief Returns High Resolution interrupt status +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! \param mask is the mask for the interrupt status +//! Mask value is the logical OR of any of the following: +//! - \b TIMER_D_HIGH_RES_FREQUENCY_UNLOCK +//! - \b TIMER_D_HIGH_RES_FREQUENCY_LOCK +//! - \b TIMER_D_HIGH_RES_FAIL_HIGH +//! - \b TIMER_D_HIGH_RES_FAIL_LOW +//! +//! Modified bits of \b TDxHINT register. +//! +//! \return Logical OR of any of the following: +//! - \b TIMER_D_HIGH_RES_FREQUENCY_UNLOCK +//! - \b TIMER_D_HIGH_RES_FREQUENCY_LOCK +//! - \b TIMER_D_HIGH_RES_FAIL_HIGH +//! - \b TIMER_D_HIGH_RES_FAIL_LOW +//! \n indicating the status of the masked interrupts +// +//***************************************************************************** + +uint16_t TIMER_D_getHighResInterruptStatus(uint16_t baseAddress, + uint16_t mask) +{ + mask = (mask >> 8); + return (HWREG16(baseAddress + OFS_TDxHINT) & mask) << 8; +} +//***************************************************************************** +// +//! \brief Reset/Clear the timer clock divider, count direction, count +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! +//! Modified bits of \b TDxCTL0 register. +//! +//! \return None +// +//***************************************************************************** + +void TIMER_D_clear(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_TDxCTL0) |= TDCLR; +} +//***************************************************************************** +// +//! \brief Clears High Resolution interrupt status +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! \param mask is the mask for the interrupts to clear +//! Mask value is the logical OR of any of the following: +//! - \b TIMER_D_HIGH_RES_FREQUENCY_UNLOCK +//! - \b TIMER_D_HIGH_RES_FREQUENCY_LOCK +//! - \b TIMER_D_HIGH_RES_FAIL_HIGH +//! - \b TIMER_D_HIGH_RES_FAIL_LOW +//! +//! Modified bits of \b TDxHINT register. +//! +//! \return None +// +//***************************************************************************** + +void TIMER_D_clearHighResInterruptStatus(uint16_t baseAddress, + uint16_t mask) +{ + mask = (mask >> 8); + HWREG16(baseAddress + OFS_TDxHINT) &= ~mask; +} +//***************************************************************************** +// +//! \brief Get synchronized capturecompare input +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! \param captureCompareRegister selects the Capture register being used. +//! Valid values are: +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_6 +//! \param synchronized is to select type of capture compare input. +//! Valid values are: +//! - \b TIMER_D_READ_SYNCHRONIZED_CAPTURECOMPAREINPUT +//! - \b TIMER_D_READ_CAPTURE_COMPARE_INPUT +//! +//! \return One of the following: +//! - \b TIMER_D_CAPTURECOMPARE_INPUT_HIGH +//! - \b TIMER_D_CAPTURECOMPARE_INPUT_LOW +// +//***************************************************************************** + +uint8_t TIMER_D_getSynchronizedCaptureCompareInput + (uint16_t baseAddress, + uint16_t captureCompareRegister, + uint16_t synchronized + ) +{ + assert((TIMER_D_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_1 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_2 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_3 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_4 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_5 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_6 == captureCompareRegister) + ); + + assert((TIMER_D_READ_CAPTURE_COMPARE_INPUT == synchronized) || + (TIMER_D_READ_SYNCHRONIZED_CAPTURECOMPAREINPUT == synchronized) + ); + + if (HWREG16(baseAddress + captureCompareRegister) & synchronized) + return TIMER_D_CAPTURECOMPARE_INPUT_HIGH; + else + return TIMER_D_CAPTURECOMPARE_INPUT_LOW; +} +//***************************************************************************** +// +//! \brief Get output bit for output mode +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! \param captureCompareRegister selects the Capture register being used. +//! Valid values are: +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_6 +//! +//! \return One of the following: +//! - \b TIMER_D_OUTPUTMODE_OUTBITVALUE_HIGH +//! - \b TIMER_D_OUTPUTMODE_OUTBITVALUE_LOW +// +//***************************************************************************** + +uint8_t TIMER_D_getOutputForOutputModeOutBitValue + (uint16_t baseAddress, + uint16_t captureCompareRegister + ) +{ + assert((TIMER_D_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_1 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_2 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_3 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_4 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_5 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_6 == captureCompareRegister) + ); + + if (HWREG16(baseAddress + captureCompareRegister) & OUT) + return TIMER_D_OUTPUTMODE_OUTBITVALUE_HIGH; + else + return TIMER_D_OUTPUTMODE_OUTBITVALUE_LOW; +} +//***************************************************************************** +// +//! \brief Get current capturecompare count +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! \param captureCompareRegister selects the Capture register being used. +//! Valid values are: +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_6 +//! +//! \return current count as uint16_t +// +//***************************************************************************** + +uint16_t TIMER_D_getCaptureCompareCount + (uint16_t baseAddress, + uint16_t captureCompareRegister + ) +{ + assert((TIMER_D_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_1 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_2 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_3 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_4 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_5 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_6 == captureCompareRegister) + ); + + return HWREG16(baseAddress + captureCompareRegister + 2); +} +//***************************************************************************** +// +//! \brief Get current capture compare latch register count +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! \param captureCompareRegister selects the Capture register being used. +//! Valid values are: +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_6 +//! +//! \return current count as uint16_t +// +//***************************************************************************** + +uint16_t TIMER_D_getCaptureCompareLatchCount + (uint16_t baseAddress, + uint16_t captureCompareRegister + ) +{ + assert((TIMER_D_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_1 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_2 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_3 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_4 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_5 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_6 == captureCompareRegister) + ); + + return HWREG16(baseAddress + captureCompareRegister + 4); +} +//***************************************************************************** +// +//! \brief Get current capturecompare input signal +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! \param captureCompareRegister selects the Capture register being used. +//! Valid values are: +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_6 +//! +//! \return One of the following: +//! - \b TIMER_D_CAPTURECOMPARE_INPUT +//! - \b 0x00 +//! \n indicating the current input signal +// +//***************************************************************************** + +uint8_t TIMER_D_getCaptureCompareInputSignal + (uint16_t baseAddress, + uint16_t captureCompareRegister + ) +{ + assert((TIMER_D_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_1 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_2 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_3 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_4 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_5 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_6 == captureCompareRegister) + ); + + return (HWREG8(baseAddress + captureCompareRegister) & CCI); +} +//***************************************************************************** +// +//! \brief Set output bit for output mode +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! \param captureCompareRegister selects the Capture register being used. +//! Valid values are: +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_6 +//! \param outputModeOutBitValue the value to be set for out bit +//! Valid values are: +//! - \b TIMER_D_OUTPUTMODE_OUTBITVALUE_HIGH +//! - \b TIMER_D_OUTPUTMODE_OUTBITVALUE_LOW +//! +//! Modified bits of \b TDxCCTLn register. +//! +//! \return None +// +//***************************************************************************** + +void TIMER_D_setOutputForOutputModeOutBitValue + (uint16_t baseAddress, + uint16_t captureCompareRegister, + uint8_t outputModeOutBitValue + ) +{ + assert((TIMER_D_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_1 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_2 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_3 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_4 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_5 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_6 == captureCompareRegister) + ); + + assert((TIMER_D_OUTPUTMODE_OUTBITVALUE_HIGH == outputModeOutBitValue) || + (TIMER_D_OUTPUTMODE_OUTBITVALUE_LOW == outputModeOutBitValue) + ); + + HWREG16(baseAddress + captureCompareRegister) &= ~OUT; + HWREG16(baseAddress + captureCompareRegister) |= outputModeOutBitValue; +} +//***************************************************************************** +// +//! \brief Generate a PWM with timer running in up mode +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! \param param is the pointer to struct for PWM configuration. +//! +//! Modified bits of \b TDxCCTLn register, bits of \b TDxCCR0 register, bits of +//! \b TDxCCTL0 register, bits of \b TDxCTL0 register and bits of \b TDxCTL1 +//! register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_D_outputPWM(uint16_t baseAddress, TIMER_D_outputPWMParam *param) +{ + assert(param != 0); + + assert((TIMER_D_CAPTURECOMPARE_REGISTER_0 == param->compareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_1 == param->compareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_2 == param->compareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_3 == param->compareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_4 == param->compareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_5 == param->compareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_6 == param->compareRegister) + ); + + assert( + (TIMER_D_CLOCKSOURCE_EXTERNAL_TDCLK == param->clockSource) || + (TIMER_D_CLOCKSOURCE_ACLK == param->clockSource) || + (TIMER_D_CLOCKSOURCE_SMCLK == param->clockSource) || + (TIMER_D_CLOCKSOURCE_INVERTED_EXTERNAL_TDCLK == param->clockSource) + ); + + assert( + (TIMER_D_CLOCKSOURCE_DIVIDER_1 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_2 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_4 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_8 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_3 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_5 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_6 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_7 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_10 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_12 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_14 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_16 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_20 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_24 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_28 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_32 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_40 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_48 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_56 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_64 == param->clockSourceDivider) + ); + + assert( + (TIMER_D_CLOCKINGMODE_EXTERNAL_CLOCK == param->clockingMode) || + (TIMER_D_CLOCKINGMODE_HIRES_LOCAL_CLOCK == param->clockingMode) || + (TIMER_D_CLOCKINGMODE_AUXILIARY_CLK == param->clockingMode) + ); + + assert((TIMER_D_OUTPUTMODE_OUTBITVALUE == param->compareOutputMode) || + (TIMER_D_OUTPUTMODE_SET == param->compareOutputMode) || + (TIMER_D_OUTPUTMODE_TOGGLE_RESET == param->compareOutputMode) || + (TIMER_D_OUTPUTMODE_SET_RESET == param->compareOutputMode) || + (TIMER_D_OUTPUTMODE_TOGGLE == param->compareOutputMode) || + (TIMER_D_OUTPUTMODE_RESET == param->compareOutputMode) || + (TIMER_D_OUTPUTMODE_TOGGLE_SET == param->compareOutputMode) || + (TIMER_D_OUTPUTMODE_RESET_SET == param->compareOutputMode) + ); + + HWREG16(baseAddress + OFS_TDxCTL1) &= ~(TDCLKM0 + TDCLKM1 + TDIDEX_7); + + HWREG16(baseAddress + OFS_TDxCTL0) &= + ~(TIMER_D_CLOCKSOURCE_INVERTED_EXTERNAL_TDCLK + + TIMER_D_UPDOWN_MODE + TIMER_D_DO_CLEAR + + TIMER_D_TDIE_INTERRUPT_ENABLE + + ID__8 + ); + + HWREG16(baseAddress + OFS_TDxCTL0) |= param->clockSource; + HWREG16(baseAddress + OFS_TDxCTL1) |= (param->clockingMode + + ((param->clockSourceDivider & 0x7) << 8)); + + HWREG16(baseAddress + OFS_TDxCTL0) |= (TIMER_D_UP_MODE + + TIMER_D_DO_CLEAR + + ((param->clockSourceDivider >> 3) << 6)); + + HWREG16(baseAddress + OFS_TDxCCR0) = param->timerPeriod; + + HWREG16(baseAddress + OFS_TDxCCTL0) &= + ~(TIMER_D_CAPTURECOMPARE_INTERRUPT_ENABLE + + TIMER_D_OUTPUTMODE_RESET_SET + ); + HWREG16(baseAddress + param->compareRegister) |= param->compareOutputMode; + + HWREG16(baseAddress + param->compareRegister + 2) = param->dutyCycle; +} + +//***************************************************************************** +// +//! \brief DEPRECATED - Generate a PWM with timer running in up mode +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! \param clockSource selects Clock source. +//! Valid values are: +//! - \b TIMER_D_CLOCKSOURCE_EXTERNAL_TDCLK [Default] +//! - \b TIMER_D_CLOCKSOURCE_ACLK +//! - \b TIMER_D_CLOCKSOURCE_SMCLK +//! - \b TIMER_D_CLOCKSOURCE_INVERTED_EXTERNAL_TDCLK +//! \param clockSourceDivider is the divider for clock source. +//! Valid values are: +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_1 [Default] +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_2 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_3 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_4 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_5 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_6 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_7 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_8 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_10 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_12 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_14 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_16 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_20 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_24 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_28 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_32 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_40 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_48 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_56 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_64 +//! \param clockingMode is the selected clock mode register values. +//! Valid values are: +//! - \b TIMER_D_CLOCKINGMODE_EXTERNAL_CLOCK [Default] +//! - \b TIMER_D_CLOCKINGMODE_HIRES_LOCAL_CLOCK +//! - \b TIMER_D_CLOCKINGMODE_AUXILIARY_CLK +//! \param timerPeriod is the specified timer period +//! \param compareRegister selects the compare register being used. +//! Valid values are: +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_6 +//! \param compareOutputMode specifies the output mode. +//! Valid values are: +//! - \b TIMER_D_OUTPUTMODE_OUTBITVALUE [Default] +//! - \b TIMER_D_OUTPUTMODE_SET +//! - \b TIMER_D_OUTPUTMODE_TOGGLE_RESET +//! - \b TIMER_D_OUTPUTMODE_SET_RESET +//! - \b TIMER_D_OUTPUTMODE_TOGGLE +//! - \b TIMER_D_OUTPUTMODE_RESET +//! - \b TIMER_D_OUTPUTMODE_TOGGLE_SET +//! - \b TIMER_D_OUTPUTMODE_RESET_SET +//! \param dutyCycle specifies the dutycycle for the generated waveform +//! +//! Modified bits of \b TDxCCTLn register, bits of \b TDxCCR0 register, bits of +//! \b TDxCCTL0 register, bits of \b TDxCTL0 register and bits of \b TDxCTL1 +//! register. +//! +//! \return None +// +//***************************************************************************** + +void TIMER_D_generatePWM( uint16_t baseAddress, + uint16_t clockSource, + uint16_t clockSourceDivider, + uint16_t clockingMode, + uint16_t timerPeriod, + uint16_t compareRegister, + uint16_t compareOutputMode, + uint16_t dutyCycle + ) +{ + TIMER_D_outputPWMParam param = { 0 }; + + param.clockSource = clockSource; + param.clockSourceDivider = clockSourceDivider; + param.clockingMode = clockingMode; + param.timerPeriod = timerPeriod; + param.compareRegister = compareRegister; + param.compareOutputMode = compareOutputMode; + param.dutyCycle = dutyCycle; + + TIMER_D_outputPWM(baseAddress, ¶m); +} +//***************************************************************************** +// +//! \brief Stops the timer +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! +//! Modified bits of \b TDxCTL0 register. +//! +//! \return None +// +//***************************************************************************** + +void TIMER_D_stop( uint16_t baseAddress ) +{ + HWREG16(baseAddress + OFS_TDxCTL0) &= ~MC_3; + HWREG16(baseAddress + OFS_TDxCTL0) |= MC_0; +} +//***************************************************************************** +// +//! \brief Sets the value of the capture-compare register +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! \param compareRegister selects the Capture register being used. +//! Valid values are: +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_6 +//! \param compareValue is the count to be compared with in compare mode +//! +//! Modified bits of \b TDxCCRn register. +//! +//! \return None +// +//***************************************************************************** + +void TIMER_D_setCompareValue( uint16_t baseAddress, + uint16_t compareRegister, + uint16_t compareValue + ) +{ + assert((TIMER_D_CAPTURECOMPARE_REGISTER_0 == compareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_1 == compareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_2 == compareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_3 == compareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_4 == compareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_5 == compareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_6 == compareRegister) + ); + + HWREG16(baseAddress + compareRegister + 0x02) = compareValue; +} +//***************************************************************************** +// +//! \brief Clears the Timer TDIFG interrupt flag +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! +//! Modified bits are \b TDIFG of \b TDxCTL0 register. +//! +//! \return None +// +//***************************************************************************** + +void TIMER_D_clearTimerInterruptFlag(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_TDxCTL0) &= ~TDIFG; +} +//***************************************************************************** +// +//! \brief Clears the capture-compare interrupt flag +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! \param captureCompareRegister selects the Capture-compare register being +//! used. +//! Valid values are: +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_6 +//! +//! Modified bits are \b CCIFG of \b TDxCCTLn register. +//! +//! \return None +// +//***************************************************************************** + +void TIMER_D_clearCaptureCompareInterruptFlag(uint16_t baseAddress, + uint16_t captureCompareRegister + ) +{ + assert((TIMER_D_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_1 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_2 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_3 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_4 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_5 == captureCompareRegister) || + (TIMER_D_CAPTURECOMPARE_REGISTER_6 == captureCompareRegister) + ); + + HWREG16(baseAddress + captureCompareRegister) &= ~CCIFG; +} +//***************************************************************************** +// +//! \brief Configures TIMER_D in free running mode +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! \param desiredHighResFrequency selects the desired High Resolution +//! frequency used. +//! Valid values are: +//! - \b TIMER_D_HIGHRES_64MHZ +//! - \b TIMER_D_HIGHRES_128MHZ +//! - \b TIMER_D_HIGHRES_200MHZ +//! - \b TIMER_D_HIGHRES_256MHZ +//! +//! Modified bits of \b TDxHCTL1 register, bits of \b TDxHCTL0 register and +//! bits of \b TDxCTL1 register. +//! +//! \return STATUS_SUCCESS or STATUS_FAIL +// +//***************************************************************************** + +uint8_t TIMER_D_initHighResGeneratorInFreeRunningMode + (uint16_t baseAddress, + uint8_t desiredHighResFrequency + ) +{ + struct s_TLV_Timer_D_Cal_Data * pTD0CAL; + uint8_t TD0CAL_bytes; + + assert((TIMER_D_HIGHRES_64MHZ == desiredHighResFrequency) || + (TIMER_D_HIGHRES_128MHZ == desiredHighResFrequency) || + (TIMER_D_HIGHRES_200MHZ == desiredHighResFrequency) || + (TIMER_D_HIGHRES_256MHZ == desiredHighResFrequency) + ); + + // Read the TimerD TLV Data + TLV_getInfo(TLV_TAG_TIMER_D_CAL, + 0, + &TD0CAL_bytes, + (uint16_t**)&pTD0CAL + ); + + if (0x00 == TD0CAL_bytes) + // No TimerD free running cal data found + return STATUS_FAIL; + + HWREG16(baseAddress + OFS_TDxHCTL1) = TDHCLKTRIM6; + HWREG16(baseAddress + OFS_TDxCTL1) = 0x00; + HWREG16(baseAddress + OFS_TDxHCTL0) = 0x00; + + switch ( desiredHighResFrequency ) { + case TIMER_D_HIGHRES_64MHZ: + HWREG16(baseAddress + OFS_TDxHCTL1) = pTD0CAL->TDH0CTL1_64; + break; + + case TIMER_D_HIGHRES_128MHZ: + HWREG16(baseAddress + OFS_TDxHCTL1) = pTD0CAL->TDH0CTL1_128; + break; + + case TIMER_D_HIGHRES_200MHZ: + HWREG16(baseAddress + OFS_TDxHCTL1) = pTD0CAL->TDH0CTL1_200; + break; + + case TIMER_D_HIGHRES_256MHZ: + HWREG16(baseAddress + OFS_TDxHCTL1) = pTD0CAL->TDH0CTL1_256; + break; + } + + // Select Hi-res local clock + HWREG16(baseAddress + OFS_TDxCTL1) |= TDCLKM_1; + + // CALEN=0 => free running mode; enable Hi-res mode + if (TIMER_D_HIGHRES_256MHZ == desiredHighResFrequency) + HWREG16(baseAddress + OFS_TDxHCTL0) |= TDHM_1; + + HWREG16(baseAddress + OFS_TDxHCTL0) |= TDHEN; + + return STATUS_SUCCESS; + +} +//***************************************************************************** +// +//! \brief Configures TIMER_D in Regulated mode +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! \param param is the pointer to struct for high resolution generator in +//! regulated mode. +//! +//! Modified bits of \b TDxHCTL0 register, bits of \b TDxCTL0 register and bits +//! of \b TDxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_D_initHighResGeneratorInRegulatedMode(uint16_t baseAddress, + TIMER_D_initHighResGeneratorInRegulatedModeParam *param) +{ + assert(param != 0); + + assert( + (TIMER_D_CLOCKSOURCE_EXTERNAL_TDCLK == param->clockSource) || + (TIMER_D_CLOCKSOURCE_ACLK == param->clockSource) || + (TIMER_D_CLOCKSOURCE_SMCLK == param->clockSource) || + (TIMER_D_CLOCKSOURCE_INVERTED_EXTERNAL_TDCLK == param->clockSource) + ); + + assert( + (TIMER_D_CLOCKSOURCE_DIVIDER_1 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_2 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_4 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_8 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_3 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_5 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_6 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_7 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_10 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_12 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_14 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_16 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_20 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_24 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_28 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_32 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_40 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_48 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_56 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_64 == param->clockSourceDivider) + ); + + assert( + (TIMER_D_CLOCKINGMODE_EXTERNAL_CLOCK == param->clockingMode) || + (TIMER_D_CLOCKINGMODE_HIRES_LOCAL_CLOCK == param->clockingMode) || + (TIMER_D_CLOCKINGMODE_AUXILIARY_CLK == param->clockingMode) + ); + + assert((TIMER_D_HIGHRES_CLK_MULTIPLY_FACTOR_8x == param->highResClockMultiplyFactor) || + (TIMER_D_HIGHRES_CLK_MULTIPLY_FACTOR_16x == param->highResClockMultiplyFactor) + ); + + assert((TIMER_D_HIGHRES_CLK_DIVIDER_1 == param->highResClockDivider) || + (TIMER_D_HIGHRES_CLK_DIVIDER_2 == param->highResClockDivider) || + (TIMER_D_HIGHRES_CLK_DIVIDER_4 == param->highResClockDivider) || + (TIMER_D_HIGHRES_CLK_DIVIDER_8 == param->highResClockDivider) + ); + + /**********how abt MCx and TDCLGRPx and CNTLx*/ + HWREG16(baseAddress + OFS_TDxCTL0) &= ~(TDSSEL_3 + TDHD_3 + TDCLR + ID__8); + HWREG16(baseAddress + OFS_TDxCTL1) &= ~(TDCLKM0 + TDCLKM1 + TDIDEX_7); + + HWREG16(baseAddress + OFS_TDxCTL0) |= (param->clockSource + + ((param->clockSourceDivider >> 3) << 6)); + HWREG16(baseAddress + OFS_TDxCTL1) |= (param->clockingMode + + ((param->clockSourceDivider & 0x7) << 8)); + + // Select Hi-res local clock + // Calibration and Hi-res mode enable + HWREG16(baseAddress + OFS_TDxCTL1) |= TDCLKM_1; + // Select Hi-res local clock + HWREG16(baseAddress + OFS_TDxHCTL0) = TDHREGEN + TDHEN; + HWREG16(baseAddress + OFS_TDxHCTL0) |= param->highResClockMultiplyFactor + + param->highResClockDivider; +} + +//***************************************************************************** +// +//! \brief DEPRECATED - Configures TIMER_D in Regulated mode +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! \param clockSource selects Clock source. +//! Valid values are: +//! - \b TIMER_D_CLOCKSOURCE_EXTERNAL_TDCLK [Default] +//! - \b TIMER_D_CLOCKSOURCE_ACLK +//! - \b TIMER_D_CLOCKSOURCE_SMCLK +//! - \b TIMER_D_CLOCKSOURCE_INVERTED_EXTERNAL_TDCLK +//! \param clockSourceDivider is the divider for clock source. +//! Valid values are: +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_1 [Default] +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_2 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_3 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_4 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_5 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_6 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_7 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_8 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_10 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_12 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_14 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_16 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_20 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_24 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_28 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_32 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_40 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_48 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_56 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_64 +//! \param clockingMode is the selected clock mode register values. +//! Valid values are: +//! - \b TIMER_D_CLOCKINGMODE_EXTERNAL_CLOCK [Default] +//! - \b TIMER_D_CLOCKINGMODE_HIRES_LOCAL_CLOCK +//! - \b TIMER_D_CLOCKINGMODE_AUXILIARY_CLK +//! \param highResClockMultiplyFactor selects the high resolution multiply +//! factor. +//! Valid values are: +//! - \b TIMER_D_HIGHRES_CLK_MULTIPLY_FACTOR_8x +//! - \b TIMER_D_HIGHRES_CLK_MULTIPLY_FACTOR_16x +//! \param highResClockDivider selects the high resolution divider. +//! Valid values are: +//! - \b TIMER_D_HIGHRES_CLK_DIVIDER_1 +//! - \b TIMER_D_HIGHRES_CLK_DIVIDER_2 +//! - \b TIMER_D_HIGHRES_CLK_DIVIDER_4 +//! - \b TIMER_D_HIGHRES_CLK_DIVIDER_8 +//! +//! Modified bits of \b TDxHCTL0 register, bits of \b TDxCTL0 register and bits +//! of \b TDxCTL1 register. +//! +//! \return None +// +//***************************************************************************** + +void TIMER_D_configureHighResGeneratorInRegulatedMode(uint16_t baseAddress, + uint16_t clockSource, + uint16_t clockSourceDivider, + uint16_t clockingMode, + uint8_t highResClockMultiplyFactor, + uint8_t highResClockDivider + ) +{ + TIMER_D_initHighResGeneratorInRegulatedModeParam param = { 0 }; + + param.clockSource = clockSource; + param.clockSourceDivider = clockSourceDivider; + param.clockingMode = clockingMode; + param.highResClockMultiplyFactor = highResClockMultiplyFactor; + param.highResClockDivider = highResClockDivider; + + TIMER_D_initHighResGeneratorInRegulatedMode(baseAddress, ¶m); + +} +//***************************************************************************** +// +//! \brief Combine TDCCR to get PWM +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! \param param is the pointer to struct for PWM generation using two CCRs. +//! +//! Modified bits of \b TDxCCTLn register, bits of \b TDxCCR0 register, bits of +//! \b TDxCCTL0 register, bits of \b TDxCTL0 register and bits of \b TDxCTL1 +//! register. +//! +//! \return None +// +//***************************************************************************** +void TIMER_D_combineTDCCRToOutputPWM(uint16_t baseAddress, + TIMER_D_combineTDCCRToOutputPWMParam *param) +{ + assert(param != 0); + + assert( + (TIMER_D_COMBINE_CCR1_CCR2 == param->combineCCRRegistersCombination) || + (TIMER_D_COMBINE_CCR3_CCR4 == param->combineCCRRegistersCombination) || + (TIMER_D_COMBINE_CCR5_CCR6 == param->combineCCRRegistersCombination) + ); + + assert( + (TIMER_D_CLOCKSOURCE_EXTERNAL_TDCLK == param->clockSource) || + (TIMER_D_CLOCKSOURCE_ACLK == param->clockSource) || + (TIMER_D_CLOCKSOURCE_SMCLK == param->clockSource) || + (TIMER_D_CLOCKSOURCE_INVERTED_EXTERNAL_TDCLK == param->clockSource) + ); + + assert( + (TIMER_D_CLOCKSOURCE_DIVIDER_1 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_2 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_4 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_8 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_3 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_5 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_6 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_7 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_10 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_12 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_14 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_16 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_20 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_24 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_28 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_32 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_40 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_48 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_56 == param->clockSourceDivider) || + (TIMER_D_CLOCKSOURCE_DIVIDER_64 == param->clockSourceDivider) + ); + + assert( + (TIMER_D_CLOCKINGMODE_EXTERNAL_CLOCK == param->clockingMode) || + (TIMER_D_CLOCKINGMODE_HIRES_LOCAL_CLOCK == param->clockingMode) || + (TIMER_D_CLOCKINGMODE_AUXILIARY_CLK == param->clockingMode) + ); + + assert((TIMER_D_OUTPUTMODE_OUTBITVALUE == param->compareOutputMode) || + (TIMER_D_OUTPUTMODE_SET == param->compareOutputMode) || + (TIMER_D_OUTPUTMODE_TOGGLE_RESET == param->compareOutputMode) || + (TIMER_D_OUTPUTMODE_SET_RESET == param->compareOutputMode) || + (TIMER_D_OUTPUTMODE_TOGGLE == param->compareOutputMode) || + (TIMER_D_OUTPUTMODE_RESET == param->compareOutputMode) || + (TIMER_D_OUTPUTMODE_TOGGLE_SET == param->compareOutputMode) || + (TIMER_D_OUTPUTMODE_RESET_SET == param->compareOutputMode) + ); + + HWREG16(baseAddress + OFS_TDxCCTL2) &= ~OUTMOD_7; + HWREG16(baseAddress + OFS_TDxCCTL2) |= param->compareOutputMode; + + HWREG16(baseAddress + OFS_TDxCCR0) = param->timerPeriod; + + HWREG16(baseAddress + OFS_TDxCCR1 + (0x05 * + (param->combineCCRRegistersCombination - TIMER_D_COMBINE_CCR1_CCR2))) = param->dutyCycle1; + HWREG16(baseAddress + OFS_TDxCCR2 + (0x05 * + (param->combineCCRRegistersCombination - TIMER_D_COMBINE_CCR1_CCR2))) = param->dutyCycle2; + + HWREG16(baseAddress + OFS_TDxCTL0) &= ~ID__8; + HWREG16(baseAddress + OFS_TDxCTL1) &= ~(TDCLKM0 + TDCLKM1 + TDIDEX_7); + + HWREG16(baseAddress + OFS_TDxCTL0) |= (param->clockSource + + ((param->clockSourceDivider >> 3) << 6)); + HWREG16(baseAddress + OFS_TDxCTL1) |= (param->clockingMode + + ((param->clockSourceDivider & 0x7) << 8)); + HWREG16(baseAddress + OFS_TDxCTL1) |= + (TD2CMB << (param->combineCCRRegistersCombination - TIMER_D_COMBINE_CCR1_CCR2)); +} //***************************************************************************** +// +//! \brief DEPRECATED - Combine TDCCR to get PWM +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! \param clockSource selects Clock source. +//! Valid values are: +//! - \b TIMER_D_CLOCKSOURCE_EXTERNAL_TDCLK [Default] +//! - \b TIMER_D_CLOCKSOURCE_ACLK +//! - \b TIMER_D_CLOCKSOURCE_SMCLK +//! - \b TIMER_D_CLOCKSOURCE_INVERTED_EXTERNAL_TDCLK +//! \param clockSourceDivider is the divider for clock source. +//! Valid values are: +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_1 [Default] +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_2 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_3 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_4 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_5 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_6 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_7 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_8 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_10 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_12 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_14 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_16 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_20 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_24 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_28 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_32 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_40 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_48 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_56 +//! - \b TIMER_D_CLOCKSOURCE_DIVIDER_64 +//! \param clockingMode is the selected clock mode register values. +//! Valid values are: +//! - \b TIMER_D_CLOCKINGMODE_EXTERNAL_CLOCK [Default] +//! - \b TIMER_D_CLOCKINGMODE_HIRES_LOCAL_CLOCK +//! - \b TIMER_D_CLOCKINGMODE_AUXILIARY_CLK +//! \param timerPeriod is the specified timer period +//! \param combineCCRRegistersCombination selects desired CCR registers to +//! combine +//! Valid values are: +//! - \b TIMER_D_COMBINE_CCR1_CCR2 +//! - \b TIMER_D_COMBINE_CCR3_CCR4 - (available on TIMER_D5, TIMER_D7) +//! - \b TIMER_D_COMBINE_CCR5_CCR6 - (available only on TIMER_D7) +//! \param compareOutputMode specifies the output mode. +//! Valid values are: +//! - \b TIMER_D_OUTPUTMODE_OUTBITVALUE [Default] +//! - \b TIMER_D_OUTPUTMODE_SET +//! - \b TIMER_D_OUTPUTMODE_TOGGLE_RESET +//! - \b TIMER_D_OUTPUTMODE_SET_RESET +//! - \b TIMER_D_OUTPUTMODE_TOGGLE +//! - \b TIMER_D_OUTPUTMODE_RESET +//! - \b TIMER_D_OUTPUTMODE_TOGGLE_SET +//! - \b TIMER_D_OUTPUTMODE_RESET_SET +//! \param dutyCycle1 specifies the dutycycle for the generated waveform +//! \param dutyCycle2 specifies the dutycycle for the generated waveform +//! +//! Modified bits of \b TDxCCTLn register, bits of \b TDxCCR0 register, bits of +//! \b TDxCCTL0 register, bits of \b TDxCTL0 register and bits of \b TDxCTL1 +//! register. +//! +//! \return None +// +//***************************************************************************** + +void TIMER_D_combineTDCCRToGeneratePWM( uint16_t baseAddress, + uint16_t clockSource, + uint16_t clockSourceDivider, + uint16_t clockingMode, + uint16_t timerPeriod, + uint16_t combineCCRRegistersCombination, + uint16_t compareOutputMode, + uint16_t dutyCycle1, + uint16_t dutyCycle2 + ) +{ + TIMER_D_combineTDCCRToOutputPWMParam param = { 0 }; + + param.clockSource = clockSource; + param.clockSourceDivider = clockSourceDivider; + param.clockingMode = clockingMode; + param.timerPeriod = timerPeriod; + param.combineCCRRegistersCombination = combineCCRRegistersCombination; + param.compareOutputMode = compareOutputMode; + param.dutyCycle1 = dutyCycle1; + param.dutyCycle2 = dutyCycle2; + + TIMER_D_combineTDCCRToOutputPWM(baseAddress, ¶m); +} +//***************************************************************************** +// +//! \brief Selects TIMER_D Latching Group +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! \param groupLatch selects the group latch +//! Valid values are: +//! - \b TIMER_D_GROUP_NONE [Default] +//! - \b TIMER_D_GROUP_CL12_CL23_CL56 +//! - \b TIMER_D_GROUP_CL123_CL456 +//! - \b TIMER_D_GROUP_ALL +//! +//! Modified bits are \b TDCLGRP of \b TDxCTL0 register. +//! +//! \return None +// +//***************************************************************************** + +void TIMER_D_selectLatchingGroup(uint16_t baseAddress, + uint16_t groupLatch) +{ + assert((TIMER_D_GROUP_NONE == groupLatch) || + (TIMER_D_GROUP_CL12_CL23_CL56 == groupLatch) || + (TIMER_D_GROUP_CL123_CL456 == groupLatch) || + (TIMER_D_GROUP_ALL == groupLatch) + ); + + HWREG16(baseAddress + OFS_TDxCTL0) &= ~TDCLGRP_3; + HWREG16(baseAddress + OFS_TDxCTL0) |= groupLatch; +} +//***************************************************************************** +// +//! \brief Selects TIMER_D counter length +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! \param counterLength selects the value of counter length. +//! Valid values are: +//! - \b TIMER_D_COUNTER_16BIT [Default] +//! - \b TIMER_D_COUNTER_12BIT +//! - \b TIMER_D_COUNTER_10BIT +//! - \b TIMER_D_COUNTER_8BIT +//! +//! Modified bits are \b CNTL of \b TDxCTL0 register. +//! +//! \return None +// +//***************************************************************************** + +void TIMER_D_selectCounterLength(uint16_t baseAddress, + uint16_t counterLength + ) +{ + assert((TIMER_D_COUNTER_8BIT == counterLength) || + (TIMER_D_COUNTER_10BIT == counterLength) || + (TIMER_D_COUNTER_12BIT == counterLength) || + (TIMER_D_COUNTER_16BIT == counterLength) + ); + + HWREG16(baseAddress + OFS_TDxCTL0) &= ~CNTL_3; + HWREG16(baseAddress + OFS_TDxCTL0) |= counterLength; +} +//***************************************************************************** +// +//! \brief Selects Compare Latch Load Event +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! \param compareRegister selects the compare register being used. +//! Valid values are: +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_D_CAPTURECOMPARE_REGISTER_6 +//! \param compareLatchLoadEvent selects the latch load event +//! Valid values are: +//! - \b TIMER_D_LATCH_ON_WRITE_TO_TDxCCRn_COMPARE_REGISTER [Default] +//! - \b TIMER_D_LATCH_WHEN_COUNTER_COUNTS_TO_0_IN_UP_OR_CONT_MODE +//! - \b TIMER_D_LATCH_WHEN_COUNTER_COUNTS_TO_0_IN_UPDOWN_MODE +//! - \b +//! TIMER_D_LATCH_WHEN_COUNTER_COUNTS_TO_CURRENT_COMPARE_LATCH_VALUE +//! +//! Modified bits are \b CLLD of \b TDxCCTLn register. +//! +//! \return None +// +//***************************************************************************** + +void TIMER_D_initCompareLatchLoadEvent(uint16_t baseAddress, + uint16_t compareRegister, + uint16_t compareLatchLoadEvent + ) +{ + assert((TIMER_D_LATCH_ON_WRITE_TO_TDxCCRn_COMPARE_REGISTER == compareLatchLoadEvent) || + (TIMER_D_LATCH_WHEN_COUNTER_COUNTS_TO_0_IN_UP_OR_CONT_MODE == compareLatchLoadEvent) || + (TIMER_D_LATCH_WHEN_COUNTER_COUNTS_TO_0_IN_UPDOWN_MODE == compareLatchLoadEvent) || + (TIMER_D_LATCH_WHEN_COUNTER_COUNTS_TO_CURRENT_COMPARE_LATCH_VALUE + == compareLatchLoadEvent) + ); + + HWREG16(baseAddress + compareRegister) &= ~CLLD_3; + HWREG16(baseAddress + compareRegister) |= compareLatchLoadEvent; +} +//***************************************************************************** +// +//! \brief Disable High Resolution fast wakeup +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! +//! Modified bits are \b TDHFW of \b TDxHCTL0 register. +//! +//! \return None +// +//***************************************************************************** + +void TIMER_D_disableHighResFastWakeup(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_TDxHCTL0) &= ~TDHFW; +} +//***************************************************************************** +// +//! \brief Enable High Resolution fast wakeup +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! +//! Modified bits are \b TDHFW of \b TDxHCTL0 register. +//! +//! \return None +// +//***************************************************************************** + +void TIMER_D_enableHighResFastWakeup(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_TDxHCTL0) |= TDHFW; +} +//***************************************************************************** +// +//! \brief Disable High Resolution Clock Enhanced Accuracy +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! +//! Modified bits are \b TDHEAEN of \b TDxHCTL0 register. +//! +//! \return None +// +//***************************************************************************** + +void TIMER_D_disableHighResClockEnhancedAccuracy(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_TDxHCTL0) &= ~TDHEAEN; +} +//***************************************************************************** +// +//! \brief Enable High Resolution Clock Enhanced Accuracy +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! +//! Modified bits are \b TDHEAEN of \b TDxHCTL0 register. +//! +//! \return None +// +//***************************************************************************** + +void TIMER_D_enableHighResClockEnhancedAccuracy(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_TDxHCTL0) |= TDHEAEN; +} +//***************************************************************************** +// +//! \brief Disable High Resolution Clock Enhanced Accuracy +//! +//! High-resolution generator is on if the TIMER_D counter +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! +//! Modified bits are \b TDHRON of \b TDxHCTL0 register. +//! +//! \return None +// +//***************************************************************************** + +void TIMER_D_DisableHighResGeneratorForceON(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_TDxHCTL0) &= ~TDHRON; +} +//***************************************************************************** +// +//! \brief Enable High Resolution Clock Enhanced Accuracy +//! +//! High-resolution generator is on in all TIMER_D MCx modes. The PMM remains +//! in high-current mode. +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! +//! Modified bits are \b TDHRON of \b TDxHCTL0 register. +//! +//! \return None +// +//***************************************************************************** + +void TIMER_D_EnableHighResGeneratorForceON(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_TDxHCTL0) |= TDHRON; +} +//***************************************************************************** +// +//! \brief Select High Resolution Coarse Clock Range +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! \param highResCoarseClockRange selects the High Resolution Coarse Clock +//! Range +//! Valid values are: +//! - \b TIMER_D_HIGHRES_BELOW_15MHz [Default] +//! - \b TIMER_D_HIGHRES_ABOVE_15MHz +//! +//! Modified bits are \b TDHCLKCR of \b TDxHCTL1 register. +//! +//! \return None +// +//***************************************************************************** + +void TIMER_D_selectHighResCoarseClockRange(uint16_t baseAddress, + uint16_t highResCoarseClockRange + ) +{ + assert((TIMER_D_HIGHRES_BELOW_15MHz == highResCoarseClockRange) || + (TIMER_D_HIGHRES_ABOVE_15MHz == highResCoarseClockRange) + ); + HWREG16(baseAddress + OFS_TDxHCTL1) &= ~TDHCLKCR; + HWREG16(baseAddress + OFS_TDxHCTL1) |= highResCoarseClockRange; +} +//***************************************************************************** +// +//! \brief Select High Resolution Clock Range Selection +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! \param highResClockRange selects the High Resolution Clock Range. Refer to +//! datasheet for frequency details +//! Valid values are: +//! - \b TIMER_D_CLOCK_RANGE0 [Default] +//! - \b TIMER_D_CLOCK_RANGE1 +//! - \b TIMER_D_CLOCK_RANGE2 +//! +//! \return None +// +//***************************************************************************** + +void TIMER_D_selectHighResClockRange(uint16_t baseAddress, + uint16_t highResClockRange + ) +{ + assert((TIMER_D_CLOCK_RANGE0 == highResClockRange) || + (TIMER_D_CLOCK_RANGE1 == highResClockRange) || + (TIMER_D_CLOCK_RANGE2 == highResClockRange) + ); + HWREG16(baseAddress + OFS_TDxHCTL1) &= ~TDHCLKCR; + HWREG16(baseAddress + OFS_TDxHCTL1) |= highResClockRange; +} +//***************************************************************************** +// +//! \brief Reads the current timer count value +//! +//! Reads the current count value of the timer. There is a majority vote system +//! in place to confirm an accurate value is returned. The TIMER_D_THRESHOLD +//! #define in the corresponding header file can be modified so that the votes +//! must be closer together for a consensus to occur. +//! +//! \param baseAddress is the base address of the TIMER_D module. +//! +//! \return Majority vote of timer count value +// +//***************************************************************************** + +uint16_t TIMER_D_getCounterValue(uint16_t baseAddress) +{ + uint16_t voteOne, voteTwo, res; + + voteTwo = HWREG16(baseAddress + OFS_TDxR); + + do { + voteOne = voteTwo; + voteTwo = HWREG16(baseAddress + OFS_TDxR); + + if (voteTwo > voteOne) + res = voteTwo - voteOne; + else if (voteOne > voteTwo) + res = voteOne - voteTwo; + else + res = 0; + + } while ( res > TIMER_D_THRESHOLD); + + return voteTwo; +} + +#endif +//***************************************************************************** +// +//! Close the doxygen group for timer_d_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/timer_d.h b/source/driverlib/MSP430F5xx_6xx/timer_d.h new file mode 100644 index 0000000..26deba1 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/timer_d.h @@ -0,0 +1,751 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// timer_d.h - Driver for the TIMER_D Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_TIMER_D_H__ +#define __MSP430WARE_TIMER_D_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_TxD7__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//****************************************************************************** +// +// The following is a struct that is passed to TIMER_D_initContinuousMode() +// +//****************************************************************************** +typedef struct TIMER_D_initContinuousModeParam { + uint16_t clockSource; + uint16_t clockSourceDivider; + uint16_t clockingMode; + uint16_t timerInterruptEnable_TDIE; + uint16_t timerClear; +} TIMER_D_initContinuousModeParam; + +//****************************************************************************** +// +// The following is a struct that is passed to TIMER_D_initUpMode() +// +//****************************************************************************** +typedef struct TIMER_D_initUpModeParam { + uint16_t clockSource; + uint16_t clockSourceDivider; + uint16_t clockingMode; + uint16_t timerPeriod; + uint16_t timerInterruptEnable_TDIE; + uint16_t captureCompareInterruptEnable_CCR0_CCIE; + uint16_t timerClear; +} TIMER_D_initUpModeParam; + +//****************************************************************************** +// +// The following is a struct that is passed to TIMER_D_initUpDownMode() +// +//****************************************************************************** +typedef struct TIMER_D_initUpDownModeParam { + uint16_t clockSource; + uint16_t clockSourceDivider; + uint16_t clockingMode; + uint16_t timerPeriod; + uint16_t timerInterruptEnable_TDIE; + uint16_t captureCompareInterruptEnable_CCR0_CCIE; + uint16_t timerClear; +} TIMER_D_initUpDownModeParam; + +//****************************************************************************** +// +// The following is a struct that is passed to TIMER_D_initCaptureMode() +// +//****************************************************************************** +typedef struct TIMER_D_initCaptureModeParam { + uint16_t captureRegister; + uint16_t captureMode; + uint16_t captureInputSelect; + uint16_t synchronizeCaptureSource; + uint16_t captureInterruptEnable; + uint16_t captureOutputMode; + uint8_t channelCaptureMode; +} TIMER_D_initCaptureModeParam; + +//****************************************************************************** +// +// The following is a struct that is passed to TIMER_D_initCompareMode() +// +//****************************************************************************** +typedef struct TIMER_D_initCompareModeParam { + uint16_t compareRegister; + uint16_t compareInterruptEnable; + uint16_t compareOutputMode; + uint16_t compareValue; +} TIMER_D_initCompareModeParam; + +//****************************************************************************** +// +// The following is a struct that is passed to TIMER_D_outputPWM() +// +//****************************************************************************** +typedef struct TIMER_D_outputPWMParam { + uint16_t clockSource; + uint16_t clockSourceDivider; + uint16_t clockingMode; + uint16_t timerPeriod; + uint16_t compareRegister; + uint16_t compareOutputMode; + uint16_t dutyCycle; +} TIMER_D_outputPWMParam; + +//****************************************************************************** +// +// The following is a struct that is passed to +// TIMER_D_initHighResGeneratorInRegulatedMode() +// +//****************************************************************************** +typedef struct TIMER_D_initHighResGeneratorInRegulatedModeParam { + uint16_t clockSource; + uint16_t clockSourceDivider; + uint16_t clockingMode; + uint8_t highResClockMultiplyFactor; + uint8_t highResClockDivider; +} TIMER_D_initHighResGeneratorInRegulatedModeParam; + +//****************************************************************************** +// +// The following is a struct that is passed to +// TIMER_D_combineTDCCRToOutputPWM() +// +//****************************************************************************** +typedef struct TIMER_D_combineTDCCRToOutputPWMParam { + uint16_t clockSource; + uint16_t clockSourceDivider; + uint16_t clockingMode; + uint16_t timerPeriod; + uint16_t combineCCRRegistersCombination; + uint16_t compareOutputMode; + uint16_t dutyCycle1; + uint16_t dutyCycle2; +} TIMER_D_combineTDCCRToOutputPWMParam; + +//***************************************************************************** +// +// The following is a parameter used for TIMER_D_getCounterValue that +// determines the maximum difference in counts of the TDxR register for a +// majority vote. +// +//***************************************************************************** +#define TIMER_D_THRESHOLD 50 + +//***************************************************************************** +// +// The following are values that can be passed to the clockSourceDivider +// parameter for functions: TIMER_D_configureContinuousMode(), +// TIMER_D_configureUpMode(), TIMER_D_configureUpDownMode(), +// TIMER_D_generatePWM(), TIMER_D_configureHighResGeneratorInRegulatedMode(), +// and TIMER_D_combineTDCCRToGeneratePWM(). +// +//***************************************************************************** +#define TIMER_D_CLOCKSOURCE_DIVIDER_1 0x00 +#define TIMER_D_CLOCKSOURCE_DIVIDER_2 0x08 +#define TIMER_D_CLOCKSOURCE_DIVIDER_3 0x02 +#define TIMER_D_CLOCKSOURCE_DIVIDER_4 0x10 +#define TIMER_D_CLOCKSOURCE_DIVIDER_5 0x04 +#define TIMER_D_CLOCKSOURCE_DIVIDER_6 0x05 +#define TIMER_D_CLOCKSOURCE_DIVIDER_7 0x06 +#define TIMER_D_CLOCKSOURCE_DIVIDER_8 0x18 +#define TIMER_D_CLOCKSOURCE_DIVIDER_10 0x0C +#define TIMER_D_CLOCKSOURCE_DIVIDER_12 0x0D +#define TIMER_D_CLOCKSOURCE_DIVIDER_14 0x0E +#define TIMER_D_CLOCKSOURCE_DIVIDER_16 0x0F +#define TIMER_D_CLOCKSOURCE_DIVIDER_20 0x14 +#define TIMER_D_CLOCKSOURCE_DIVIDER_24 0x15 +#define TIMER_D_CLOCKSOURCE_DIVIDER_28 0x16 +#define TIMER_D_CLOCKSOURCE_DIVIDER_32 0x17 +#define TIMER_D_CLOCKSOURCE_DIVIDER_40 0x1C +#define TIMER_D_CLOCKSOURCE_DIVIDER_48 0x1D +#define TIMER_D_CLOCKSOURCE_DIVIDER_56 0x1E +#define TIMER_D_CLOCKSOURCE_DIVIDER_64 0x1F + +//***************************************************************************** +// +// The following are values that can be passed to the timerMode parameter for +// functions: TIMER_D_startCounter(). +// +//***************************************************************************** +#define TIMER_D_STOP_MODE MC_0 +#define TIMER_D_UP_MODE MC_1 +#define TIMER_D_CONTINUOUS_MODE MC_2 +#define TIMER_D_UPDOWN_MODE MC_3 + +//***************************************************************************** +// +// The following are values that can be passed to the timerClear parameter for +// functions: TIMER_D_configureContinuousMode(), TIMER_D_configureUpMode(), and +// TIMER_D_configureUpDownMode(). +// +//***************************************************************************** +#define TIMER_D_DO_CLEAR TDCLR +#define TIMER_D_SKIP_CLEAR 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the clockSource parameter for +// functions: TIMER_D_configureContinuousMode(), TIMER_D_configureUpMode(), +// TIMER_D_configureUpDownMode(), TIMER_D_generatePWM(), +// TIMER_D_configureHighResGeneratorInRegulatedMode(), and +// TIMER_D_combineTDCCRToGeneratePWM(). +// +//***************************************************************************** +#define TIMER_D_CLOCKSOURCE_EXTERNAL_TDCLK TDSSEL__TACLK +#define TIMER_D_CLOCKSOURCE_ACLK TDSSEL__ACLK +#define TIMER_D_CLOCKSOURCE_SMCLK TDSSEL__SMCLK +#define TIMER_D_CLOCKSOURCE_INVERTED_EXTERNAL_TDCLK TDSSEL__INCLK + +//***************************************************************************** +// +// The following are values that can be passed to the clockingMode parameter +// for functions: TIMER_D_configureContinuousMode(), TIMER_D_configureUpMode(), +// TIMER_D_configureUpDownMode(), TIMER_D_generatePWM(), +// TIMER_D_configureHighResGeneratorInRegulatedMode(), and +// TIMER_D_combineTDCCRToGeneratePWM(). +// +//***************************************************************************** +#define TIMER_D_CLOCKINGMODE_EXTERNAL_CLOCK TDCLKM_0 +#define TIMER_D_CLOCKINGMODE_HIRES_LOCAL_CLOCK TDCLKM_1 +#define TIMER_D_CLOCKINGMODE_AUXILIARY_CLK TDCLKM_2 + +//***************************************************************************** +// +// The following are values that can be passed to the timerInterruptEnable_TDIE +// parameter for functions: TIMER_D_configureContinuousMode(), +// TIMER_D_configureUpMode(), and TIMER_D_configureUpDownMode(). +// +//***************************************************************************** +#define TIMER_D_TDIE_INTERRUPT_ENABLE TDIE +#define TIMER_D_TDIE_INTERRUPT_DISABLE 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the +// captureCompareInterruptEnable_CCR0_CCIE parameter for functions: +// TIMER_D_configureUpMode(), and TIMER_D_configureUpDownMode(). +// +//***************************************************************************** +#define TIMER_D_CCIE_CCR0_INTERRUPT_ENABLE CCIE +#define TIMER_D_CCIE_CCR0_INTERRUPT_DISABLE 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the channelCaptureMode +// parameter for functions: TIMER_D_initCapture(). +// +//***************************************************************************** +#define TIMER_D_SINGLE_CAPTURE_MODE 0x00 +#define TIMER_D_DUAL_CAPTURE_MODE 0x01 + +//***************************************************************************** +// +// The following are values that can be passed to the captureInputSelect +// parameter for functions: TIMER_D_initCapture(). +// +//***************************************************************************** +#define TIMER_D_CAPTURE_INPUTSELECT_CCIxA CCIS_0 +#define TIMER_D_CAPTURE_INPUTSELECT_CCIxB CCIS_1 +#define TIMER_D_CAPTURE_INPUTSELECT_GND CCIS_2 +#define TIMER_D_CAPTURE_INPUTSELECT_Vcc CCIS_3 + +//***************************************************************************** +// +// The following are values that can be passed to the compareOutputMode +// parameter for functions: TIMER_D_initCompare(), TIMER_D_generatePWM(), and +// TIMER_D_combineTDCCRToGeneratePWM(); the captureOutputMode parameter for +// functions: TIMER_D_initCapture(). +// +//***************************************************************************** +#define TIMER_D_OUTPUTMODE_OUTBITVALUE OUTMOD_0 +#define TIMER_D_OUTPUTMODE_SET OUTMOD_1 +#define TIMER_D_OUTPUTMODE_TOGGLE_RESET OUTMOD_2 +#define TIMER_D_OUTPUTMODE_SET_RESET OUTMOD_3 +#define TIMER_D_OUTPUTMODE_TOGGLE OUTMOD_4 +#define TIMER_D_OUTPUTMODE_RESET OUTMOD_5 +#define TIMER_D_OUTPUTMODE_TOGGLE_SET OUTMOD_6 +#define TIMER_D_OUTPUTMODE_RESET_SET OUTMOD_7 + +//***************************************************************************** +// +// The following are values that can be passed to the compareRegister parameter +// for functions: TIMER_D_generatePWM(), TIMER_D_setCompareValue(), +// TIMER_D_initCompareLatchLoadEvent(), and TIMER_D_initCompare(); the +// captureCompareRegister parameter for functions: +// TIMER_D_enableCaptureCompareInterrupt(), +// TIMER_D_disableCaptureCompareInterrupt(), +// TIMER_D_getCaptureCompareInterruptStatus(), +// TIMER_D_getSynchronizedCaptureCompareInput(), +// TIMER_D_getOutputForOutputModeOutBitValue(), +// TIMER_D_getCaptureCompareCount(), TIMER_D_getCaptureCompareLatchCount(), +// TIMER_D_getCaptureCompareInputSignal(), +// TIMER_D_setOutputForOutputModeOutBitValue(), and +// TIMER_D_clearCaptureCompareInterruptFlag(); the captureRegister parameter +// for functions: TIMER_D_initCapture(). +// +//***************************************************************************** +#define TIMER_D_CAPTURECOMPARE_REGISTER_0 0x08 +#define TIMER_D_CAPTURECOMPARE_REGISTER_1 0x0E +#define TIMER_D_CAPTURECOMPARE_REGISTER_2 0x14 +#define TIMER_D_CAPTURECOMPARE_REGISTER_3 0x1A +#define TIMER_D_CAPTURECOMPARE_REGISTER_4 0x20 +#define TIMER_D_CAPTURECOMPARE_REGISTER_5 0x28 +#define TIMER_D_CAPTURECOMPARE_REGISTER_6 0x2E + +//***************************************************************************** +// +// The following are values that can be passed to the captureMode parameter for +// functions: TIMER_D_initCapture(). +// +//***************************************************************************** +#define TIMER_D_CAPTUREMODE_NO_CAPTURE CM_0 +#define TIMER_D_CAPTUREMODE_RISING_EDGE CM_1 +#define TIMER_D_CAPTUREMODE_FALLING_EDGE CM_2 +#define TIMER_D_CAPTUREMODE_RISING_AND_FALLING_EDGE CM_3 + +//***************************************************************************** +// +// The following are values that can be passed to the synchronizeCaptureSource +// parameter for functions: TIMER_D_initCapture(). +// +//***************************************************************************** +#define TIMER_D_CAPTURE_ASYNCHRONOUS 0x00 +#define TIMER_D_CAPTURE_SYNCHRONOUS SCS + +//***************************************************************************** +// +// The following are values that can be passed to the compareInterruptEnable +// parameter for functions: TIMER_D_initCompare(). +// +//***************************************************************************** +#define TIMER_D_CAPTURECOMPARE_INTERRUPT_ENABLE CCIE +#define TIMER_D_CAPTURECOMPARE_INTERRUPT_DISABLE 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the mask parameter for +// functions: TIMER_D_enableHighResInterrupt(), +// TIMER_D_disableHighResInterrupt(), TIMER_D_getHighResInterruptStatus(), and +// TIMER_D_clearHighResInterruptStatus() as well as returned by the +// TIMER_D_getHighResInterruptStatus() function. +// +//***************************************************************************** +#define TIMER_D_HIGH_RES_FREQUENCY_UNLOCK TDHUNLKIE +#define TIMER_D_HIGH_RES_FREQUENCY_LOCK TDHLKIE +#define TIMER_D_HIGH_RES_FAIL_HIGH TDHFHIE +#define TIMER_D_HIGH_RES_FAIL_LOW TDHFLIE + +//***************************************************************************** +// +// The following are values that can be passed to the mask parameter for +// functions: TIMER_D_getCaptureCompareInterruptStatus() as well as returned by +// the TIMER_D_getCaptureCompareInterruptStatus() function. +// +//***************************************************************************** +#define TIMER_D_CAPTURE_OVERFLOW COV +#define TIMER_D_CAPTURECOMPARE_INTERRUPT_FLAG CCIFG + +//***************************************************************************** +// +// The following are values that can be passed to the synchronized parameter +// for functions: TIMER_D_getSynchronizedCaptureCompareInput(). +// +//***************************************************************************** +#define TIMER_D_READ_SYNCHRONIZED_CAPTURECOMPAREINPUT SCCI +#define TIMER_D_READ_CAPTURE_COMPARE_INPUT CCI + +//***************************************************************************** +// +// The following are values that can be passed to the outputModeOutBitValue +// parameter for functions: TIMER_D_setOutputForOutputModeOutBitValue() as well +// as returned by the TIMER_D_getOutputForOutputModeOutBitValue() function. +// +//***************************************************************************** +#define TIMER_D_OUTPUTMODE_OUTBITVALUE_HIGH OUT +#define TIMER_D_OUTPUTMODE_OUTBITVALUE_LOW 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the desiredHighResFrequency +// parameter for functions: TIMER_D_initHighResGeneratorInFreeRunningMode(). +// +//***************************************************************************** +#define TIMER_D_HIGHRES_64MHZ 0x00 +#define TIMER_D_HIGHRES_128MHZ 0x01 +#define TIMER_D_HIGHRES_200MHZ 0x02 +#define TIMER_D_HIGHRES_256MHZ 0x03 + +//***************************************************************************** +// +// The following are values that can be passed to the highResClockDivider +// parameter for functions: TIMER_D_configureHighResGeneratorInRegulatedMode(). +// +//***************************************************************************** +#define TIMER_D_HIGHRES_CLK_DIVIDER_1 TDHD__1 +#define TIMER_D_HIGHRES_CLK_DIVIDER_2 TDHD__2 +#define TIMER_D_HIGHRES_CLK_DIVIDER_4 TDHD__4 +#define TIMER_D_HIGHRES_CLK_DIVIDER_8 TDHD__8 + +//***************************************************************************** +// +// The following are values that can be passed to the +// highResClockMultiplyFactor parameter for functions: +// TIMER_D_configureHighResGeneratorInRegulatedMode(). +// +//***************************************************************************** +#define TIMER_D_HIGHRES_CLK_MULTIPLY_FACTOR_8x TDHM_0 +#define TIMER_D_HIGHRES_CLK_MULTIPLY_FACTOR_16x TDHM_1 + +//***************************************************************************** +// +// The following are values that can be passed to the +// combineCCRRegistersCombination parameter for functions: +// TIMER_D_combineTDCCRToGeneratePWM(). +// +//***************************************************************************** +#define TIMER_D_COMBINE_CCR1_CCR2 2 +#define TIMER_D_COMBINE_CCR3_CCR4 4 +#define TIMER_D_COMBINE_CCR5_CCR6 6 + +//***************************************************************************** +// +// The following are values that can be passed to the groupLatch parameter for +// functions: TIMER_D_selectLatchingGroup(). +// +//***************************************************************************** +#define TIMER_D_GROUP_NONE TDCLGRP_0 +#define TIMER_D_GROUP_CL12_CL23_CL56 TDCLGRP_1 +#define TIMER_D_GROUP_CL123_CL456 TDCLGRP_2 +#define TIMER_D_GROUP_ALL TDCLGRP_3 + +//***************************************************************************** +// +// The following are values that can be passed to the counterLength parameter +// for functions: TIMER_D_selectCounterLength(). +// +//***************************************************************************** +#define TIMER_D_COUNTER_16BIT CNTL_0 +#define TIMER_D_COUNTER_12BIT CNTL_1 +#define TIMER_D_COUNTER_10BIT CNTL_2 +#define TIMER_D_COUNTER_8BIT CNTL_3 + +//***************************************************************************** +// +// The following are values that can be passed to the compareLatchLoadEvent +// parameter for functions: TIMER_D_initCompareLatchLoadEvent(). +// +//***************************************************************************** +#define TIMER_D_LATCH_ON_WRITE_TO_TDxCCRn_COMPARE_REGISTER CLLD_0 +#define TIMER_D_LATCH_WHEN_COUNTER_COUNTS_TO_0_IN_UP_OR_CONT_MODE CLLD_1 +#define TIMER_D_LATCH_WHEN_COUNTER_COUNTS_TO_0_IN_UPDOWN_MODE CLLD_2 +#define TIMER_D_LATCH_WHEN_COUNTER_COUNTS_TO_CURRENT_COMPARE_LATCH_VALUE CLLD_3 + +//***************************************************************************** +// +// The following are values that can be passed to the highResCoarseClockRange +// parameter for functions: TIMER_D_selectHighResCoarseClockRange(). +// +//***************************************************************************** +#define TIMER_D_HIGHRES_BELOW_15MHz 0x00 +#define TIMER_D_HIGHRES_ABOVE_15MHz TDHCLKCR + +//***************************************************************************** +// +// The following are values that can be passed to the highResClockRange +// parameter for functions: TIMER_D_selectHighResClockRange(). +// +//***************************************************************************** +#define TIMER_D_CLOCK_RANGE0 0x0000 +#define TIMER_D_CLOCK_RANGE1 0x2000 +#define TIMER_D_CLOCK_RANGE2 0x4000 + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the TIMER_D_getSynchronizedCaptureCompareInput() +// function. +// +//***************************************************************************** +#define TIMER_D_CAPTURECOMPARE_INPUT_HIGH 0x01 +#define TIMER_D_CAPTURECOMPARE_INPUT_LOW 0x00 + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the TIMER_D_getTimerInterruptStatus() function. +// +//***************************************************************************** +#define TIMER_D_INTERRUPT_NOT_PENDING 0x00 +#define TIMER_D_INTERRUPT_PENDING 0x01 + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the TIMER_D_getCaptureCompareInputSignal() function. +// +//***************************************************************************** +#define TIMER_D_CAPTURECOMPARE_INPUT CCI + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void TIMER_D_startCounter(uint16_t baseAddress, + uint16_t timerMode); + +extern void TIMER_D_initContinuousMode(uint16_t baseAddress, + TIMER_D_initContinuousModeParam *param); + +extern void TIMER_D_initUpMode(uint16_t baseAddress, + TIMER_D_initUpModeParam *param); + +extern void TIMER_D_initUpDownMode(uint16_t baseAddress, + TIMER_D_initUpDownModeParam *param); + +extern void TIMER_D_initCaptureMode(uint16_t baseAddress, + TIMER_D_initCaptureModeParam *param); + +extern void TIMER_D_initCompareMode(uint16_t baseAddress, + TIMER_D_initCompareModeParam *param); + +extern void TIMER_D_enableTimerInterrupt(uint16_t baseAddress); + +extern void TIMER_D_enableHighResInterrupt(uint16_t baseAddress, + uint16_t mask); + +extern void TIMER_D_disableTimerInterrupt(uint16_t baseAddress); + +extern void TIMER_D_disableHighResInterrupt(uint16_t baseAddress, + uint16_t mask); + +extern uint32_t TIMER_D_getTimerInterruptStatus(uint16_t baseAddress); + +extern void TIMER_D_enableCaptureCompareInterrupt(uint16_t baseAddress, + uint16_t captureCompareRegister); + +extern void TIMER_D_disableCaptureCompareInterrupt(uint16_t baseAddress, + uint16_t captureCompareRegister); + +extern uint32_t TIMER_D_getCaptureCompareInterruptStatus(uint16_t baseAddress, + uint16_t captureCompareRegister, + uint16_t mask); + +extern uint16_t TIMER_D_getHighResInterruptStatus(uint16_t baseAddress, + uint16_t mask); + +extern void TIMER_D_clear(uint16_t baseAddress); + +extern void TIMER_D_clearHighResInterruptStatus(uint16_t baseAddress, + uint16_t mask); + +extern uint8_t TIMER_D_getSynchronizedCaptureCompareInput(uint16_t baseAddress, + uint16_t captureCompareRegister, + uint16_t synchronized); + +extern uint8_t TIMER_D_getOutputForOutputModeOutBitValue(uint16_t baseAddress, + uint16_t captureCompareRegister); + +extern uint16_t TIMER_D_getCaptureCompareCount(uint16_t baseAddress, + uint16_t captureCompareRegister); + +extern uint16_t TIMER_D_getCaptureCompareLatchCount(uint16_t baseAddress, + uint16_t captureCompareRegister); + +extern uint8_t TIMER_D_getCaptureCompareInputSignal(uint16_t baseAddress, + uint16_t captureCompareRegister); + +extern void TIMER_D_setOutputForOutputModeOutBitValue(uint16_t baseAddress, + uint16_t captureCompareRegister, + uint8_t outputModeOutBitValue); + +extern void TIMER_D_outputPWM(uint16_t baseAddress, + TIMER_D_outputPWMParam *param); + +extern void TIMER_D_stop(uint16_t baseAddress); + +extern void TIMER_D_setCompareValue(uint16_t baseAddress, + uint16_t compareRegister, + uint16_t compareValue); + +extern void TIMER_D_clearTimerInterruptFlag(uint16_t baseAddress); + +extern void TIMER_D_clearCaptureCompareInterruptFlag(uint16_t baseAddress, + uint16_t captureCompareRegister); + +extern uint8_t TIMER_D_initHighResGeneratorInFreeRunningMode(uint16_t baseAddress, + uint8_t desiredHighResFrequency); + +extern void TIMER_D_initHighResGeneratorInRegulatedMode(uint16_t baseAddress, + TIMER_D_initHighResGeneratorInRegulatedModeParam *param); + +extern void TIMER_D_combineTDCCRToOutputPWM(uint16_t baseAddress, + TIMER_D_combineTDCCRToOutputPWMParam *param); + +extern void TIMER_D_selectLatchingGroup(uint16_t baseAddress, + uint16_t groupLatch); + +extern void TIMER_D_selectCounterLength(uint16_t baseAddress, + uint16_t counterLength); + +extern void TIMER_D_initCompareLatchLoadEvent(uint16_t baseAddress, + uint16_t compareRegister, + uint16_t compareLatchLoadEvent); + +extern void TIMER_D_disableHighResFastWakeup(uint16_t baseAddress); + +extern void TIMER_D_enableHighResFastWakeup(uint16_t baseAddress); + +extern void TIMER_D_disableHighResClockEnhancedAccuracy(uint16_t baseAddress); + +extern void TIMER_D_enableHighResClockEnhancedAccuracy(uint16_t baseAddress); + +extern void TIMER_D_DisableHighResGeneratorForceON(uint16_t baseAddress); + +extern void TIMER_D_EnableHighResGeneratorForceON(uint16_t baseAddress); + +extern void TIMER_D_selectHighResCoarseClockRange(uint16_t baseAddress, + uint16_t highResCoarseClockRange); + +extern void TIMER_D_selectHighResClockRange(uint16_t baseAddress, + uint16_t highResClockRange); + +extern uint16_t TIMER_D_getCounterValue(uint16_t baseAddress); + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +#define TIMER_D_configureHighResGeneratorInFreeRunningMode \ + TIMER_D_initHighResGeneratorInFreeRunningMode + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +extern void TIMER_D_configureContinuousMode(uint16_t baseAddress, + uint16_t clockSource, + uint16_t clockSourceDivider, + uint16_t clockingMode, + uint16_t timerInterruptEnable_TDIE, + uint16_t timerClear); + +extern void TIMER_D_configureUpMode(uint16_t baseAddress, + uint16_t clockSource, + uint16_t clockSourceDivider, + uint16_t clockingMode, + uint16_t timerPeriod, + uint16_t timerInterruptEnable_TDIE, + uint16_t captureCompareInterruptEnable_CCR0_CCIE, + uint16_t timerClear); + +extern void TIMER_D_configureUpDownMode(uint16_t baseAddress, + uint16_t clockSource, + uint16_t clockSourceDivider, + uint16_t clockingMode, + uint16_t timerPeriod, + uint16_t timerInterruptEnable_TDIE, + uint16_t captureCompareInterruptEnable_CCR0_CCIE, + uint16_t timerClear); + +extern void TIMER_D_initCapture(uint16_t baseAddress, + uint16_t captureRegister, + uint16_t captureMode, + uint16_t captureInputSelect, + uint16_t synchronizeCaptureSource, + uint16_t captureInterruptEnable, + uint16_t captureOutputMode, + uint8_t channelCaptureMode); + +extern void TIMER_D_initCompare(uint16_t baseAddress, + uint16_t compareRegister, + uint16_t compareInterruptEnable, + uint16_t compareOutputMode, + uint16_t compareValue); + +extern void TIMER_D_generatePWM(uint16_t baseAddress, + uint16_t clockSource, + uint16_t clockSourceDivider, + uint16_t clockingMode, + uint16_t timerPeriod, + uint16_t compareRegister, + uint16_t compareOutputMode, + uint16_t dutyCycle); + +extern void TIMER_D_configureHighResGeneratorInRegulatedMode(uint16_t baseAddress, + uint16_t clockSource, + uint16_t clockSourceDivider, + uint16_t clockingMode, + uint8_t highResClockMultiplyFactor, + uint8_t highResClockDivider); + +extern void TIMER_D_combineTDCCRToGeneratePWM(uint16_t baseAddress, + uint16_t clockSource, + uint16_t clockSourceDivider, + uint16_t clockingMode, + uint16_t timerPeriod, + uint16_t combineCCRRegistersCombination, + uint16_t compareOutputMode, + uint16_t dutyCycle1, + uint16_t dutyCycle2); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_TIMER_D_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/tlv.c b/source/driverlib/MSP430F5xx_6xx/tlv.c new file mode 100644 index 0000000..b09f72e --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/tlv.c @@ -0,0 +1,414 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// tlv.c - Driver for the tlv Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup tlv_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_TLV__ +#include "tlv.h" + +#include + +//***************************************************************************** +// +//! \brief Gets TLV Info +//! +//! The TLV structure uses a tag or base address to identify segments of the +//! table where information is stored. Some examples of TLV tags are Peripheral +//! Descriptor, Interrupts, Info Block and Die Record. This function retrieves +//! the value of a tag and the length of the tag. +//! +//! \param tag represents the tag for which the information needs to be +//! retrieved. +//! Valid values are: +//! - \b TLV_TAG_LDTAG +//! - \b TLV_TAG_PDTAG +//! - \b TLV_TAG_Reserved3 +//! - \b TLV_TAG_Reserved4 +//! - \b TLV_TAG_BLANK +//! - \b TLV_TAG_Reserved6 +//! - \b TLV_TAG_Reserved7 +//! - \b TLV_TAG_TAGEND +//! - \b TLV_TAG_TAGEXT +//! - \b TLV_TAG_TIMER_D_CAL +//! - \b TLV_DEVICE_ID_0 +//! - \b TLV_DEVICE_ID_1 +//! - \b TLV_TAG_DIERECORD +//! - \b TLV_TAG_ADCCAL +//! - \b TLV_TAG_ADC12CAL +//! - \b TLV_TAG_ADC10CAL +//! - \b TLV_TAG_REFCAL +//! \param instance In some cases a specific tag may have more than one +//! instance. For example there may be multiple instances of timer +//! calibration data present under a single Timer Cal tag. This variable +//! specifies the instance for which information is to be retrieved (0, +//! 1, etc.). When only one instance exists; 0 is passed. +//! \param length Acts as a return through indirect reference. The function +//! retrieves the value of the TLV tag length. This value is pointed to +//! by *length and can be used by the application level once the +//! function is called. If the specified tag is not found then the +//! pointer is null 0. +//! \param data_address acts as a return through indirect reference. Once the +//! function is called data_address points to the pointer that holds the +//! value retrieved from the specified TLV tag. If the specified tag is +//! not found then the pointer is null 0. +//! +//! \return None +// +//***************************************************************************** +void TLV_getInfo(uint8_t tag, + uint8_t instance, + uint8_t *length, + uint16_t **data_address + ) +{ + // TLV Structure Start Address + char *TLV_address = (char*)TLV_START; + + while ((TLV_address < (char*)TLV_END) + && ((*TLV_address != tag) || instance) // check for tag and instance + && (*TLV_address != TLV_TAGEND)) { // do range check first + if (*TLV_address == tag) + // repeat till requested instance is reached + instance--; + // add (Current TAG address + LENGTH) + 2 + TLV_address += *(TLV_address + 1) + 2; + } + + // Check if Tag match happened.. + if (*TLV_address == tag) { + // Return length = Address + 1 + *length = *(TLV_address + 1); + // Return address of first data/value info = Address + 2 + *data_address = (uint16_t*)(TLV_address + 2); + } + // If there was no tag match and the end of TLV structure was reached.. + else{ + // Return 0 for TAG not found + *length = 0; + // Return 0 for TAG not found + *data_address = 0; + } +} + +//***************************************************************************** +// +//! \brief Retrieves the unique device ID from the TLV structure. +//! +//! +//! \return The device ID is returned as type uint16_t. +// +//***************************************************************************** +uint16_t TLV_getDeviceType() +{ + uint16_t *pDeviceType = (uint16_t*)TLV_DEVICE_ID_0; + + // Return Value from TLV Table + return pDeviceType[0]; +} + +//***************************************************************************** +// +//! \brief Gets memory information +//! +//! The Peripheral Descriptor tag is split into two portions a list of the +//! available flash memory blocks followed by a list of available peripherals. +//! This function is used to parse through the first portion and calculate the +//! total flash memory available in a device. The typical usage is to call the +//! TLV_getMemory which returns a non-zero value until the entire memory list +//! has been parsed. When a zero is returned, it indicates that all the memory +//! blocks have been counted and the next address holds the beginning of the +//! device peripheral list. +//! +//! \param instance In some cases a specific tag may have more than one +//! instance. This variable specifies the instance for which information +//! is to be retrieved (0, 1 etc). When only one instance exists; 0 is +//! passed. +//! +//! \return The returned value is zero if the end of the memory list is +//! reached. +// +//***************************************************************************** +uint16_t TLV_getMemory(uint8_t instance) +{ + uint8_t *pPDTAG; + uint8_t bPDTAG_bytes; + uint16_t count; + + // set tag for word access comparison + instance *= 2; + + // TLV access Function Call + // Get Peripheral data pointer + TLV_getInfo(TLV_PDTAG, + 0, + &bPDTAG_bytes, + (uint16_t**)&pPDTAG + ); + + for (count = 0; count <= instance; count += 2) { + if (pPDTAG[count] == 0) + // Return 0 if end reached + return 0; + if (count == instance) + return pPDTAG[count] | pPDTAG[count + 1] << 8; + } + + // Return 0: not found + return 0; +} + +//***************************************************************************** +// +//! \brief Gets peripheral information from the TLV +//! +//! he Peripheral Descriptor tag is split into two portions a list of the +//! available flash memory blocks followed by a list of available peripherals. +//! This function is used to parse through the second portion and can be used +//! to check if a specific peripheral is present in a device. The function +//! calls TLV_getPeripheral() recursively until the end of the memory list and +//! consequently the beginning of the peripheral list is reached. < +//! +//! \param tag represents represents the tag for a specific peripheral for +//! which the information needs to be retrieved. In the header file tlv. +//! h specific peripheral tags are pre-defined, for example USCIA_B and +//! TA0 are defined as TLV_PID_USCI_AB and TLV_PID_TA2 respectively. +//! Valid values are: +//! - \b TLV_PID_NO_MODULE - No Module +//! - \b TLV_PID_PORTMAPPING - Port Mapping +//! - \b TLV_PID_MSP430CPUXV2 - MSP430CPUXV2 +//! - \b TLV_PID_JTAG - JTAG +//! - \b TLV_PID_SBW - SBW +//! - \b TLV_PID_EEM_XS - EEM X-Small +//! - \b TLV_PID_EEM_S - EEM Small +//! - \b TLV_PID_EEM_M - EEM Medium +//! - \b TLV_PID_EEM_L - EEM Large +//! - \b TLV_PID_PMM - PMM +//! - \b TLV_PID_PMM_FR - PMM FRAM +//! - \b TLV_PID_FCTL - Flash +//! - \b TLV_PID_CRC16 - CRC16 +//! - \b TLV_PID_CRC16_RB - CRC16 Reverse +//! - \b TLV_PID_WDT_A - WDT_A +//! - \b TLV_PID_SFR - SFR +//! - \b TLV_PID_SYS - SYS +//! - \b TLV_PID_RAMCTL - RAMCTL +//! - \b TLV_PID_DMA_1 - DMA 1 +//! - \b TLV_PID_DMA_3 - DMA 3 +//! - \b TLV_PID_UCS - UCS +//! - \b TLV_PID_DMA_6 - DMA 6 +//! - \b TLV_PID_DMA_2 - DMA 2 +//! - \b TLV_PID_PORT1_2 - Port 1 + 2 / A +//! - \b TLV_PID_PORT3_4 - Port 3 + 4 / B +//! - \b TLV_PID_PORT5_6 - Port 5 + 6 / C +//! - \b TLV_PID_PORT7_8 - Port 7 + 8 / D +//! - \b TLV_PID_PORT9_10 - Port 9 + 10 / E +//! - \b TLV_PID_PORT11_12 - Port 11 + 12 / F +//! - \b TLV_PID_PORTU - Port U +//! - \b TLV_PID_PORTJ - Port J +//! - \b TLV_PID_TA2 - Timer A2 +//! - \b TLV_PID_TA3 - Timer A1 +//! - \b TLV_PID_TA5 - Timer A5 +//! - \b TLV_PID_TA7 - Timer A7 +//! - \b TLV_PID_TB3 - Timer B3 +//! - \b TLV_PID_TB5 - Timer B5 +//! - \b TLV_PID_TB7 - Timer B7 +//! - \b TLV_PID_RTC - RTC +//! - \b TLV_PID_BT_RTC - BT + RTC +//! - \b TLV_PID_BBS - Battery Backup Switch +//! - \b TLV_PID_RTC_B - RTC_B +//! - \b TLV_PID_TD2 - Timer D2 +//! - \b TLV_PID_TD3 - Timer D1 +//! - \b TLV_PID_TD5 - Timer D5 +//! - \b TLV_PID_TD7 - Timer D7 +//! - \b TLV_PID_TEC - Timer Event Control +//! - \b TLV_PID_RTC_C - RTC_C +//! - \b TLV_PID_AES - AES +//! - \b TLV_PID_MPY16 - MPY16 +//! - \b TLV_PID_MPY32 - MPY32 +//! - \b TLV_PID_MPU - MPU +//! - \b TLV_PID_USCI_AB - USCI_AB +//! - \b TLV_PID_USCI_A - USCI_A +//! - \b TLV_PID_USCI_B - USCI_B +//! - \b TLV_PID_EUSCI_A - eUSCI_A +//! - \b TLV_PID_EUSCI_B - eUSCI_B +//! - \b TLV_PID_REF - Shared Reference +//! - \b TLV_PID_COMP_B - COMP_B +//! - \b TLV_PID_COMP_D - COMP_D +//! - \b TLV_PID_USB - USB +//! - \b TLV_PID_LCD_B - LCD_B +//! - \b TLV_PID_LCD_C - LCD_C +//! - \b TLV_PID_DAC12_A - DAC12_A +//! - \b TLV_PID_SD16_B_1 - SD16_B 1 Channel +//! - \b TLV_PID_SD16_B_2 - SD16_B 2 Channel +//! - \b TLV_PID_SD16_B_3 - SD16_B 3 Channel +//! - \b TLV_PID_SD16_B_4 - SD16_B 4 Channel +//! - \b TLV_PID_SD16_B_5 - SD16_B 5 Channel +//! - \b TLV_PID_SD16_B_6 - SD16_B 6 Channel +//! - \b TLV_PID_SD16_B_7 - SD16_B 7 Channel +//! - \b TLV_PID_SD16_B_8 - SD16_B 8 Channel +//! - \b TLV_PID_ADC12_A - ADC12_A +//! - \b TLV_PID_ADC10_A - ADC10_A +//! - \b TLV_PID_ADC10_B - ADC10_B +//! - \b TLV_PID_SD16_A - SD16_A +//! - \b TLV_PID_TI_BSL - BSL +//! \param instance In some cases a specific tag may have more than one +//! instance. For example a device may have more than a single USCI +//! module, each of which is defined by an instance number 0, 1, 2, etc. +//! When only one instance exists; 0 is passed. +//! +//! \return The returned value is zero if the specified tag value (peripheral) +//! is not available in the device. +// +//***************************************************************************** +uint16_t TLV_getPeripheral(uint8_t tag, + uint8_t instance + ) +{ + uint8_t *pPDTAG; + uint8_t bPDTAG_bytes; + uint16_t count = 0; + uint16_t pcount = 0; + + // Get Peripheral data pointer + TLV_getInfo(TLV_PDTAG, + 0, + &bPDTAG_bytes, + (uint16_t**)&pPDTAG + ); + + // read memory configuration from TLV to get offset for Peripherals + while (TLV_getMemory(count)) + count++; + // get number of Peripheral entries + pcount = pPDTAG[count * 2 + 1]; + // inc count to first Periperal + count++; + // adjust point to first address of Peripheral + pPDTAG += count * 2; + // set counter back to 0 + count = 0; + // align pcount for work comparision + pcount *= 2; + + // TLV access Function Call + for (count = 0; count <= pcount; count += 2) { + if (pPDTAG[count + 1] == tag) { + // test if required Peripheral is found + if (instance > 0) + // test if required instance is found + instance--; + else + // Return found data + return pPDTAG[count] | pPDTAG[count + 1] << 8; + } + } + + // Return 0: not found + return 0; +} + +//***************************************************************************** +// +//! \brief Get interrupt information from the TLV +//! +//! This function is used to retrieve information on available interrupt +//! vectors. It allows the user to check if a specific interrupt vector is +//! defined in a given device. +//! +//! \param tag represents the tag for the interrupt vector. Interrupt vector +//! tags number from 0 to N depending on the number of available +//! interrupts. Refer to the device datasheet for a list of available +//! interrupts. +//! +//! \return The returned value is zero is the specified interrupt vector is not +//! defined. +// +//***************************************************************************** +uint8_t TLV_getInterrupt(uint8_t tag) +{ + uint8_t *pPDTAG; + uint8_t bPDTAG_bytes; + uint16_t count = 0; + uint16_t pcount = 0; + + // Get Peripheral data pointer + TLV_getInfo(TLV_PDTAG, + 0, + &bPDTAG_bytes, + (uint16_t**)&pPDTAG + ); + + // read memory configuration from TLV to get offset for Peripherals + while (TLV_getMemory(count)) + count++; + + pcount = pPDTAG[count * 2 + 1]; + // inc count to first Periperal + count++; + // adjust point to first address of Peripheral + pPDTAG += (pcount + count) * 2; + // set counter back to 0 + count = 0; + + // TLV access Function Call + for (count = 0; count <= tag; count += 2) { + if (pPDTAG[count] == 0) + // Return 0: not found/end of table + return 0; + if (count == tag) + // Return found data + return pPDTAG[count]; + } + + // Return 0: not found + return 0; +} + +#endif +//***************************************************************************** +// +//! Close the doxygen group for tlv_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/tlv.h b/source/driverlib/MSP430F5xx_6xx/tlv.h new file mode 100644 index 0000000..8d11d4b --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/tlv.h @@ -0,0 +1,236 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// tlv.h - Driver for the TLV Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_TLV_H__ +#define __MSP430WARE_TLV_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_TLV__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//****************************************************************************** +// +// TLV Data Types +// +//****************************************************************************** +struct s_TLV_Die_Record { + uint32_t wafer_id; + uint16_t die_x_position; + uint16_t die_y_position; + uint16_t test_results; +}; + +struct s_TLV_ADC_Cal_Data { + uint16_t adc_gain_factor; + int16_t adc_offset; + uint16_t adc_ref15_30_temp; + uint16_t adc_ref15_85_temp; + uint16_t adc_ref20_30_temp; + uint16_t adc_ref20_85_temp; + uint16_t adc_ref25_30_temp; + uint16_t adc_ref25_85_temp; +}; + +struct s_TLV_Timer_D_Cal_Data { + uint16_t TDH0CTL1_64; + uint16_t TDH0CTL1_128; + uint16_t TDH0CTL1_200; + uint16_t TDH0CTL1_256; +}; + +struct s_TLV_REF_Cal_Data { + uint16_t ref_ref15; + uint16_t ref_ref20; + uint16_t ref_ref25; +}; + +struct s_Peripheral_Memory_Data { + uint16_t memory_1; + uint16_t memory_2; + uint16_t memory_3; + uint16_t memory_4; +}; + +//***************************************************************************** +// +// The following are values that can be passed to the tag parameter for +// functions: TLV_getInfo(). +// +//***************************************************************************** +#define TLV_TAG_LDTAG TLV_LDTAG +#define TLV_TAG_PDTAG TLV_PDTAG +#define TLV_TAG_Reserved3 TLV_Reserved3 +#define TLV_TAG_Reserved4 TLV_Reserved4 +#define TLV_TAG_BLANK TLV_BLANK +#define TLV_TAG_Reserved6 TLV_Reserved6 +#define TLV_TAG_Reserved7 TLV_Reserved7 +#define TLV_TAG_TAGEND TLV_TAGEND +#define TLV_TAG_TAGEXT TLV_TAGEXT +#define TLV_TAG_TIMER_D_CAL 0x15 +#define TLV_DEVICE_ID_0 0x1A04 +#define TLV_DEVICE_ID_1 0x1A05 +#define TLV_TAG_DIERECORD TLV_DIERECORD +#define TLV_TAG_ADCCAL TLV_ADCCAL +#define TLV_TAG_ADC12CAL TLV_ADC12CAL +#define TLV_TAG_ADC10CAL TLV_ADC10CAL +#define TLV_TAG_REFCAL TLV_REFCAL + +//***************************************************************************** +// +// The following are values that can be passed to the tag parameter for +// functions: TLV_getPeripheral(). +// +//***************************************************************************** +#define TLV_PID_NO_MODULE (0x00) +#define TLV_PID_PORTMAPPING (0x10) +#define TLV_PID_MSP430CPUXV2 (0x23) +#define TLV_PID_JTAG (0x09) +#define TLV_PID_SBW (0x0F) +#define TLV_PID_EEM_XS (0x02) +#define TLV_PID_EEM_S (0x03) +#define TLV_PID_EEM_M (0x04) +#define TLV_PID_EEM_L (0x05) +#define TLV_PID_PMM (0x30) +#define TLV_PID_PMM_FR (0x32) +#define TLV_PID_FCTL (0x39) +#define TLV_PID_CRC16 (0x3C) +#define TLV_PID_CRC16_RB (0x3D) +#define TLV_PID_WDT_A (0x40) +#define TLV_PID_SFR (0x41) +#define TLV_PID_SYS (0x42) +#define TLV_PID_RAMCTL (0x44) +#define TLV_PID_DMA_1 (0x46) +#define TLV_PID_DMA_3 (0x47) +#define TLV_PID_UCS (0x48) +#define TLV_PID_DMA_6 (0x4A) +#define TLV_PID_DMA_2 (0x4B) +#define TLV_PID_PORT1_2 (0x51) +#define TLV_PID_PORT3_4 (0x52) +#define TLV_PID_PORT5_6 (0x53) +#define TLV_PID_PORT7_8 (0x54) +#define TLV_PID_PORT9_10 (0x55) +#define TLV_PID_PORT11_12 (0x56) +#define TLV_PID_PORTU (0x5E) +#define TLV_PID_PORTJ (0x5F) +#define TLV_PID_TA2 (0x60) +#define TLV_PID_TA3 (0x61) +#define TLV_PID_TA5 (0x62) +#define TLV_PID_TA7 (0x63) +#define TLV_PID_TB3 (0x65) +#define TLV_PID_TB5 (0x66) +#define TLV_PID_TB7 (0x67) +#define TLV_PID_RTC (0x68) +#define TLV_PID_BT_RTC (0x69) +#define TLV_PID_BBS (0x6A) +#define TLV_PID_RTC_B (0x6B) +#define TLV_PID_TD2 (0x6C) +#define TLV_PID_TD3 (0x6D) +#define TLV_PID_TD5 (0x6E) +#define TLV_PID_TD7 (0x6F) +#define TLV_PID_TEC (0x70) +#define TLV_PID_RTC_C (0x71) +#define TLV_PID_AES (0x80) +#define TLV_PID_MPY16 (0x84) +#define TLV_PID_MPY32 (0x85) +#define TLV_PID_MPU (0x86) +#define TLV_PID_USCI_AB (0x90) +#define TLV_PID_USCI_A (0x91) +#define TLV_PID_USCI_B (0x92) +#define TLV_PID_EUSCI_A (0x94) +#define TLV_PID_EUSCI_B (0x95) +#define TLV_PID_REF (0xA0) +#define TLV_PID_COMP_B (0xA8) +#define TLV_PID_COMP_D (0xA9) +#define TLV_PID_USB (0x98) +#define TLV_PID_LCD_B (0xB1) +#define TLV_PID_LCD_C (0xB2) +#define TLV_PID_DAC12_A (0xC0) +#define TLV_PID_SD16_B_1 (0xC8) +#define TLV_PID_SD16_B_2 (0xC9) +#define TLV_PID_SD16_B_3 (0xCA) +#define TLV_PID_SD16_B_4 (0xCB) +#define TLV_PID_SD16_B_5 (0xCC) +#define TLV_PID_SD16_B_6 (0xCD) +#define TLV_PID_SD16_B_7 (0xCE) +#define TLV_PID_SD16_B_8 (0xCF) +#define TLV_PID_ADC12_A (0xD1) +#define TLV_PID_ADC10_A (0xD3) +#define TLV_PID_ADC10_B (0xD4) +#define TLV_PID_SD16_A (0xD8) +#define TLV_PID_TI_BSL (0xFC) + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void TLV_getInfo(uint8_t tag, + uint8_t instance, + uint8_t *length, + uint16_t **data_address); + +extern uint16_t TLV_getDeviceType(void); + +extern uint16_t TLV_getMemory(uint8_t instance); + +extern uint16_t TLV_getPeripheral(uint8_t tag, + uint8_t instance); + +extern uint8_t TLV_getInterrupt(uint8_t tag); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_TLV_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/ucs.c b/source/driverlib/MSP430F5xx_6xx/ucs.c new file mode 100644 index 0000000..0aa3abf --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/ucs.c @@ -0,0 +1,1474 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// ucs.c - Driver for the ucs Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup ucs_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifndef DRIVERLIB_LEGACY_MODE + +#ifdef __MSP430_HAS_UCS__ +#include "ucs.h" + +#include + +#ifdef __GNUC__ +#define __delay_cycles(x) \ + ({ \ + volatile unsigned int j; \ + for (j = 0; j < x; j++) \ + { \ + __no_operation(); \ + } \ + }) + +#endif +//****************************************************************************** +// +// The XT1 crystal frequency. Should be set with +// UCS_setExternalClockSource if XT1 is used and user intends to +// invoke UCS_getSMCLK, UCS_getMCLK or UCS_getACLK +// +//****************************************************************************** +uint32_t UCS_XT1ClockFrequency = 0; + +//****************************************************************************** +// +// The XT2 crystal frequency. Should be set with +// UCS_setExternalClockSource if XT1 is used and user intends to invoke +// UCS_getSMCLK, UCS_getMCLK or UCS_getACLK +// +//****************************************************************************** +uint32_t UCS_XT2ClockFrequency = 0; + +//***************************************************************************** +// +//! \brief Compute the clock frequency when clock is sourced from DCO +//! +//! \param FLLRefCLKSource is clock source for FLL reference +//! +//! \return Calculated clock frequency in Hz +// +//***************************************************************************** +static uint32_t privateUCSSourceClockFromDCO(uint16_t FLLRefCLKSource + ) +{ + assert((SELM__DCOCLKDIV == FLLRefCLKSource) || + (SELM__DCOCLK == FLLRefCLKSource) + ); + uint16_t D_value = 1; + uint16_t N_value; + uint16_t n_value = 1; + uint32_t Fref_value; + uint8_t i; + + N_value = (HWREG16(UCS_BASE + OFS_UCSCTL2)) & 0x03FF; + uint16_t tempDivider = HWREG8(UCS_BASE + OFS_UCSCTL3) & FLLREFDIV_7; + + if (tempDivider < 4) + n_value <<= tempDivider; + else if (tempDivider == 4) + n_value = 12; + else if (tempDivider == 5) + n_value = 16; + + switch ( (HWREG8(UCS_BASE + OFS_UCSCTL3)) & SELREF_7) { + case SELREF__XT1CLK: + Fref_value = UCS_XT1ClockFrequency; + + if (XTS != (HWREG16(UCS_BASE + OFS_UCSCTL6) & XTS)) { + if (HWREG8(UCS_BASE + OFS_UCSCTL7) & XT1LFOFFG) { + HWREG8(UCS_BASE + OFS_UCSCTL7) &= ~(XT1LFOFFG); + //Clear OFIFG fault flag + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + + if (HWREG8(UCS_BASE + OFS_UCSCTL7) & XT1LFOFFG) + Fref_value = UCS_REFOCLK_FREQUENCY; + } + }else { + if (HWREG8(UCS_BASE + OFS_UCSCTL7) & XT1HFOFFG) { + HWREG8(UCS_BASE + OFS_UCSCTL7) &= ~(XT1HFOFFG); + //Clear OFIFG fault flag + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + + if (HWREG8(UCS_BASE + OFS_UCSCTL7) & XT1HFOFFG) + Fref_value = UCS_REFOCLK_FREQUENCY; + } + } + + break; + case SELREF__REFOCLK: + Fref_value = UCS_REFOCLK_FREQUENCY; + break; + case SELREF__XT2CLK: + Fref_value = UCS_XT2ClockFrequency; + + if (HWREG8(UCS_BASE + OFS_UCSCTL7) & XT2OFFG) { + HWREG8(UCS_BASE + OFS_UCSCTL7) &= ~(XT2OFFG); + + //Clear OFIFG fault flag + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + + if (HWREG8(UCS_BASE + OFS_UCSCTL7) & XT2OFFG) + Fref_value = UCS_REFOCLK_FREQUENCY; + } + + break; + default: assert(0); + } + + uint32_t CLKFrequency = Fref_value * ( N_value + 1) / n_value; + + if (SELM__DCOCLK == FLLRefCLKSource) { + tempDivider = (HWREG16(UCS_BASE + OFS_UCSCTL2)) & FLLD_7; + tempDivider = tempDivider >> 12; + + for (i = 0; i < tempDivider; i++) + D_value = D_value * 2; + + CLKFrequency *= D_value; + } + return CLKFrequency; +} + +//***************************************************************************** +// +//! \brief Compute the clock frequency given the clock source and divider +//! +//! \param CLKSource is the clock source +//! \param CLKSourceDivider is the clock source divider +//! +//! \return Calculated clock frequency in Hz +// +//***************************************************************************** +static uint32_t privateUCSComputeCLKFrequency(uint16_t CLKSource, + uint16_t CLKSourceDivider + ) +{ + uint32_t CLKFrequency; + uint8_t CLKSourceFrequencyDivider = 1; + uint8_t i = 0; + + for ( i = 0; i < CLKSourceDivider; i++) + CLKSourceFrequencyDivider *= 2; + + switch (CLKSource) { + case SELM__XT1CLK: + CLKFrequency = (UCS_XT1ClockFrequency / + CLKSourceFrequencyDivider); + + if (XTS != (HWREG16(UCS_BASE + OFS_UCSCTL6) & XTS)) { + if (HWREG8(UCS_BASE + OFS_UCSCTL7) & XT1LFOFFG) { + HWREG8(UCS_BASE + OFS_UCSCTL7) &= ~(XT1LFOFFG); + //Clear OFIFG fault flag + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + + if (HWREG8(UCS_BASE + OFS_UCSCTL7) & XT1LFOFFG) + CLKFrequency = UCS_REFOCLK_FREQUENCY; + } + }else { + if (HWREG8(UCS_BASE + OFS_UCSCTL7) & XT1HFOFFG) { + HWREG8(UCS_BASE + OFS_UCSCTL7) &= ~(XT1HFOFFG); + //Clear OFIFG fault flag + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + + if (HWREG8(UCS_BASE + OFS_UCSCTL7) & XT1HFOFFG) + CLKFrequency = UCS_REFOCLK_FREQUENCY; + } + } + break; + + case SELM__VLOCLK: + CLKFrequency = + (UCS_VLOCLK_FREQUENCY / CLKSourceFrequencyDivider); + break; + case SELM__REFOCLK: + CLKFrequency = + (UCS_REFOCLK_FREQUENCY / CLKSourceFrequencyDivider); + break; + case SELM__XT2CLK: + CLKFrequency = + (UCS_XT2ClockFrequency / CLKSourceFrequencyDivider); + + if (HWREG8(UCS_BASE + OFS_UCSCTL7) & XT2OFFG) { + + HWREG8(UCS_BASE + OFS_UCSCTL7) &= ~XT2OFFG; + //Clear OFIFG fault flag + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + } + + if (HWREG8(UCS_BASE + OFS_UCSCTL7) & XT2OFFG) + CLKFrequency = + privateUCSSourceClockFromDCO( SELM__DCOCLKDIV); + break; + case SELM__DCOCLK: + case SELM__DCOCLKDIV: + CLKFrequency = privateUCSSourceClockFromDCO( + CLKSource) / CLKSourceFrequencyDivider; + break; + } + + return CLKFrequency; +} + +//***************************************************************************** +// +//! \brief Sets the external clock source +//! +//! This function sets the external clock sources XT1 and XT2 crystal +//! oscillator frequency values. This function must be called if an external +//! crystal XT1 or XT2 is used and the user intends to call UCS_getMCLK, +//! UCS_getSMCLK or UCS_getACLK APIs. If not, it is not necessary to invoke +//! this API. +//! +//! \param XT1CLK_frequency is the XT1 crystal frequencies in Hz +//! \param XT2CLK_frequency is the XT2 crystal frequencies in Hz +//! +//! \return None +// +//***************************************************************************** +void UCS_setExternalClockSource(uint32_t XT1CLK_frequency, + uint32_t XT2CLK_frequency + ) +{ + UCS_XT1ClockFrequency = XT1CLK_frequency; + UCS_XT2ClockFrequency = XT2CLK_frequency; +} + +//***************************************************************************** +// +//! \brief Initializes a clock signal +//! +//! This function initializes each of the clock signals. The user must ensure +//! that this function is called for each clock signal. If not, the default +//! state is assumed for the particular clock signal. Refer MSP430Ware +//! documentation for UCS module or Device Family User's Guide for details of +//! default clock signal states. +//! +//! \param selectedClockSignal selected clock signal +//! Valid values are: +//! - \b UCS_ACLK +//! - \b UCS_MCLK +//! - \b UCS_SMCLK +//! - \b UCS_FLLREF +//! \param clockSource is clock source for the selectedClockSignal +//! Valid values are: +//! - \b UCS_XT1CLK_SELECT +//! - \b UCS_VLOCLK_SELECT +//! - \b UCS_REFOCLK_SELECT +//! - \b UCS_DCOCLK_SELECT +//! - \b UCS_DCOCLKDIV_SELECT +//! - \b UCS_XT2CLK_SELECT +//! \param clockSourceDivider selected the clock divider to calculate +//! clocksignal from clock source. +//! Valid values are: +//! - \b UCS_CLOCK_DIVIDER_1 [Default] +//! - \b UCS_CLOCK_DIVIDER_2 +//! - \b UCS_CLOCK_DIVIDER_4 +//! - \b UCS_CLOCK_DIVIDER_8 +//! - \b UCS_CLOCK_DIVIDER_12 - [Valid only for UCS_FLLREF] +//! - \b UCS_CLOCK_DIVIDER_16 +//! - \b UCS_CLOCK_DIVIDER_32 - [Not valid for UCS_FLLREF] +//! +//! Modified bits of \b UCSCTL5 register, bits of \b UCSCTL4 register and bits +//! of \b UCSCTL3 register. +//! +//! \return None +// +//***************************************************************************** +void UCS_clockSignalInit(uint8_t selectedClockSignal, + uint16_t clockSource, + uint16_t clockSourceDivider + ) +{ + assert( + (UCS_XT1CLK_SELECT == clockSource) || + (UCS_VLOCLK_SELECT == clockSource) || + (UCS_REFOCLK_SELECT == clockSource) || + (UCS_DCOCLK_SELECT == clockSource) || + (UCS_DCOCLKDIV_SELECT == clockSource) || + (UCS_XT2CLK_SELECT == clockSource) + ); + + assert( + (UCS_CLOCK_DIVIDER_1 == clockSourceDivider) || + (UCS_CLOCK_DIVIDER_2 == clockSourceDivider) || + (UCS_CLOCK_DIVIDER_4 == clockSourceDivider) || + (UCS_CLOCK_DIVIDER_8 == clockSourceDivider) || + (UCS_CLOCK_DIVIDER_16 == clockSourceDivider) || + (UCS_CLOCK_DIVIDER_32 == clockSourceDivider) + ); + + switch (selectedClockSignal) { + case UCS_ACLK: + HWREG16(UCS_BASE + OFS_UCSCTL4) &= ~(SELA_7); + clockSource = clockSource << 8; + HWREG16(UCS_BASE + OFS_UCSCTL4) |= (clockSource); + + HWREG16(UCS_BASE + OFS_UCSCTL5) &= ~(DIVA_7); + clockSourceDivider = clockSourceDivider << 8; + HWREG16(UCS_BASE + OFS_UCSCTL5) |= clockSourceDivider; + break; + case UCS_SMCLK: + HWREG16(UCS_BASE + OFS_UCSCTL4) &= ~(SELS_7); + clockSource = clockSource << 4; + HWREG16(UCS_BASE + OFS_UCSCTL4) |= (clockSource); + + HWREG16(UCS_BASE + OFS_UCSCTL5) &= ~(DIVS_7); + clockSourceDivider = clockSourceDivider << 4; + HWREG16(UCS_BASE + OFS_UCSCTL5) |= clockSourceDivider; + break; + case UCS_MCLK: + HWREG16(UCS_BASE + OFS_UCSCTL4) &= ~(SELM_7); + HWREG16(UCS_BASE + OFS_UCSCTL4) |= (clockSource); + + HWREG16(UCS_BASE + OFS_UCSCTL5) &= ~(DIVM_7); + HWREG16(UCS_BASE + OFS_UCSCTL5) |= clockSourceDivider; + break; + case UCS_FLLREF: + assert(clockSource <= SELA_5); + HWREG8(UCS_BASE + OFS_UCSCTL3) &= ~(SELREF_7); + + clockSource = clockSource << 4; + HWREG8(UCS_BASE + OFS_UCSCTL3) |= (clockSource); + + HWREG8(UCS_BASE + OFS_UCSCTL3) &= ~(FLLREFDIV_7); + //Note that dividers for FLLREF are slightly different + //Hence handled differently from other CLK signals + switch (clockSourceDivider) { + case UCS_CLOCK_DIVIDER_12: + HWREG8(UCS_BASE + OFS_UCSCTL3) |= FLLREFDIV__12; + break; + case UCS_CLOCK_DIVIDER_16: + HWREG8(UCS_BASE + OFS_UCSCTL3) |= FLLREFDIV__16; + break; + default: + HWREG8(UCS_BASE + OFS_UCSCTL3) |= clockSourceDivider; + break; + } + + break; + } +} + +//***************************************************************************** +// +//! \brief Initializes the XT1 crystal oscillator in low frequency mode +//! +//! Initializes the XT1 crystal oscillator in low frequency mode. Loops until +//! all oscillator fault flags are cleared, with no timeout. See the device- +//! specific data sheet for appropriate drive settings. +//! +//! \param xt1drive is the target drive strength for the XT1 crystal +//! oscillator. +//! Valid values are: +//! - \b UCS_XT1_DRIVE0 +//! - \b UCS_XT1_DRIVE1 +//! - \b UCS_XT1_DRIVE2 +//! - \b UCS_XT1_DRIVE3 [Default] +//! \n Modified bits are \b XT1DRIVE of \b UCSCTL6 register. +//! \param xcap is the selected capacitor value. This parameter selects the +//! capacitors applied to the LF crystal (XT1) or resonator in the LF +//! mode. The effective capacitance (seen by the crystal) is Ceff. (CXIN +//! + 2 pF)/2. It is assumed that CXIN = CXOUT and that a parasitic +//! capacitance of 2 pF is added by the package and the printed circuit +//! board. For details about the typical internal and the effective +//! capacitors, refer to the device-specific data sheet. +//! Valid values are: +//! - \b UCS_XCAP_0 +//! - \b UCS_XCAP_1 +//! - \b UCS_XCAP_2 +//! - \b UCS_XCAP_3 [Default] +//! +//! Modified bits are \b XCAP of \b UCSCTL6 register. +//! +//! \return None +// +//***************************************************************************** +void UCS_LFXT1Start(uint16_t xt1drive, + uint8_t xcap + ) +{ + assert((xcap == UCS_XCAP_0) || + (xcap == UCS_XCAP_1) || + (xcap == UCS_XCAP_2) || + (xcap == UCS_XCAP_3) ); + + assert((xt1drive == UCS_XT1_DRIVE0 ) || + (xt1drive == UCS_XT1_DRIVE1 ) || + (xt1drive == UCS_XT1_DRIVE2 ) || + (xt1drive == UCS_XT1_DRIVE3 )); + + //If the drive setting is not already set to maximum + //Set it to max for LFXT startup + if ((HWREG16(UCS_BASE + OFS_UCSCTL6) & XT1DRIVE_3) != XT1DRIVE_3) + //Highest drive setting for XT1startup + HWREG16(UCS_BASE + OFS_UCSCTL6_L) |= XT1DRIVE1_L + XT1DRIVE0_L; + + //Enable LF mode and clear xcap and bypass + HWREG16(UCS_BASE + OFS_UCSCTL6) &= ~(XTS + XCAP_3 + XT1BYPASS); + HWREG16(UCS_BASE + OFS_UCSCTL6) |= xcap; + + while (HWREG8(UCS_BASE + OFS_UCSCTL7) & XT1LFOFFG) { + //Clear OSC flaut Flags fault flags + HWREG8(UCS_BASE + OFS_UCSCTL7) &= ~(XT1LFOFFG); + + //Clear OFIFG fault flag + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + } + + //set requested Drive mode + HWREG16(UCS_BASE + OFS_UCSCTL6) = ( HWREG16(UCS_BASE + OFS_UCSCTL6) & + ~(XT1DRIVE_3) + ) | + (xt1drive); + + //Switch ON XT1 oscillator + HWREG16(UCS_BASE + OFS_UCSCTL6) &= ~XT1OFF; +} + +//***************************************************************************** +// +//! \brief Initializes the XT1 crystal oscillator in low frequency mode +//! +//! Initializes the XT1 crystal oscillator in high frequency mode. Loops until +//! all oscillator fault flags are cleared, with no timeout. See the device- +//! specific data sheet for appropriate drive settings. +//! +//! \param xt1drive is the target drive strength for the XT1 crystal +//! oscillator. +//! Valid values are: +//! - \b UCS_XT1_DRIVE0 +//! - \b UCS_XT1_DRIVE1 +//! - \b UCS_XT1_DRIVE2 +//! - \b UCS_XT1_DRIVE3 [Default] +//! +//! Modified bits of \b UCSCTL7 register, bits of \b UCSCTL6 register and bits +//! of \b SFRIFG register. +//! +//! \return None +// +//***************************************************************************** +void UCS_HFXT1Start(uint16_t xt1drive + ) +{ + //Check if drive value is the expected one + if ((HWREG16(UCS_BASE + OFS_UCSCTL6) & XT1DRIVE_3) != xt1drive) { + //Clear XT1drive field + HWREG16(UCS_BASE + OFS_UCSCTL6) &= ~XT1DRIVE_3; + + //Set requested value + HWREG16(UCS_BASE + OFS_UCSCTL6) |= xt1drive; + } + + //Enable HF mode + HWREG16(UCS_BASE + OFS_UCSCTL6) |= XTS; + + HWREG16(UCS_BASE + OFS_UCSCTL6) &= ~XT1BYPASS; + + // Check XT1 fault flags + while ((HWREG8(UCS_BASE + OFS_UCSCTL7) & (XT1HFOFFG))) { + //Clear OSC flaut Flags fault flags + HWREG8(UCS_BASE + OFS_UCSCTL7) &= ~(XT1HFOFFG); + + //Clear OFIFG fault flag + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + } + + //Switch ON XT1 oscillator + HWREG16(UCS_BASE + OFS_UCSCTL6) &= ~XT1OFF; +} + +//***************************************************************************** +// +//! \brief Bypass the XT1 crystal oscillator +//! +//! Bypasses the XT1 crystal oscillator. Loops until all oscillator fault flags +//! are cleared, with no timeout. +//! +//! \param highOrLowFrequency selects high frequency or low frequency mode for +//! XT1. +//! Valid values are: +//! - \b UCS_XT1_HIGH_FREQUENCY +//! - \b UCS_XT1_LOW_FREQUENCY [Default] +//! +//! Modified bits of \b UCSCTL7 register, bits of \b UCSCTL6 register and bits +//! of \b SFRIFG register. +//! +//! \return None +// +//***************************************************************************** +void UCS_bypassXT1(uint8_t highOrLowFrequency + ) +{ + assert((UCS_XT1_LOW_FREQUENCY == highOrLowFrequency) || + (UCS_XT1_HIGH_FREQUENCY == highOrLowFrequency ) + ); + + //Enable HF/LF mode + HWREG16(UCS_BASE + OFS_UCSCTL6) &= ~XTS; + HWREG16(UCS_BASE + OFS_UCSCTL6) |= highOrLowFrequency; + + //Switch OFF XT1 oscillator and enable BYPASS mode + HWREG16(UCS_BASE + OFS_UCSCTL6) |= (XT1BYPASS + XT1OFF); + + if (UCS_XT1_LOW_FREQUENCY == highOrLowFrequency) { + while (HWREG8(UCS_BASE + OFS_UCSCTL7) & (XT1LFOFFG)) { + //Clear OSC flaut Flags fault flags + HWREG8(UCS_BASE + OFS_UCSCTL7) &= ~(XT1LFOFFG); + + // Clear the global fault flag. In case the XT1 caused the global fault + // flag to get set this will clear the global error condition. If any + // error condition persists, global flag will get again. + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + } + } else { + while (HWREG8(UCS_BASE + OFS_UCSCTL7) & (XT1HFOFFG)) { + //Clear OSC flaut Flags fault flags + HWREG8(UCS_BASE + OFS_UCSCTL7) &= ~(XT1HFOFFG); + + //Clear the global fault flag. In case the XT1 caused the global fault + //flag to get set this will clear the global error condition. If any + //error condition persists, global flag will get again. + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + } + } + +} + +//***************************************************************************** +// +//! \brief Initializes the XT1 crystal oscillator in low frequency mode with +//! timeout +//! +//! Initializes the XT1 crystal oscillator in low frequency mode with timeout. +//! Loops until all oscillator fault flags are cleared or until a timeout +//! counter is decremented and equals to zero. See the device-specific +//! datasheet for appropriate drive settings. +//! +//! \param xt1drive is the target drive strength for the XT1 crystal +//! oscillator. +//! Valid values are: +//! - \b UCS_XT1_DRIVE0 +//! - \b UCS_XT1_DRIVE1 +//! - \b UCS_XT1_DRIVE2 +//! - \b UCS_XT1_DRIVE3 [Default] +//! \param xcap is the selected capacitor value. This parameter selects the +//! capacitors applied to the LF crystal (XT1) or resonator in the LF +//! mode. The effective capacitance (seen by the crystal) is Ceff. (CXIN +//! + 2 pF)/2. It is assumed that CXIN = CXOUT and that a parasitic +//! capacitance of 2 pF is added by the package and the printed circuit +//! board. For details about the typical internal and the effective +//! capacitors, refer to the device-specific data sheet. +//! Valid values are: +//! - \b UCS_XCAP_0 +//! - \b UCS_XCAP_1 +//! - \b UCS_XCAP_2 +//! - \b UCS_XCAP_3 [Default] +//! \param timeout is the count value that gets decremented every time the loop +//! that clears oscillator fault flags gets executed. +//! +//! Modified bits of \b UCSCTL7 register, bits of \b UCSCTL6 register and bits +//! of \b SFRIFG register. +//! +//! \return STATUS_SUCCESS or STATUS_FAIL +// +//***************************************************************************** +bool UCS_LFXT1StartWithTimeout(uint16_t xt1drive, + uint8_t xcap, + uint16_t timeout + ) +{ + assert((xcap == UCS_XCAP_0) || + (xcap == UCS_XCAP_1) || + (xcap == UCS_XCAP_2) || + (xcap == UCS_XCAP_3) ); + + assert((xt1drive == UCS_XT1_DRIVE0 ) || + (xt1drive == UCS_XT1_DRIVE1 ) || + (xt1drive == UCS_XT1_DRIVE2 ) || + (xt1drive == UCS_XT1_DRIVE3 )); + + assert(timeout > 0); + + //If the drive setting is not already set to maximum + //Set it to max for LFXT startup + if ((HWREG16(UCS_BASE + OFS_UCSCTL6) & XT1DRIVE_3) != XT1DRIVE_3) + //Highest drive setting for XT1startup + HWREG16(UCS_BASE + OFS_UCSCTL6_L) |= XT1DRIVE1_L + XT1DRIVE0_L; + + //Enable LF mode and clear xcap and bypass + HWREG16(UCS_BASE + OFS_UCSCTL6) &= ~(XTS + XCAP_3 + XT1BYPASS); + HWREG16(UCS_BASE + OFS_UCSCTL6) |= xcap; + + do { + HWREG8(UCS_BASE + OFS_UCSCTL7) &= ~(XT1LFOFFG); + + //Clear OFIFG fault flag + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + } while ((HWREG8(UCS_BASE + OFS_UCSCTL7) & XT1LFOFFG) && --timeout); + + if (timeout) { + //set requested Drive mode + HWREG16(UCS_BASE + OFS_UCSCTL6) = ( HWREG16(UCS_BASE + OFS_UCSCTL6) & + ~(XT1DRIVE_3) + ) | + (xt1drive); + //Switch ON XT1 oscillator + HWREG16(UCS_BASE + OFS_UCSCTL6) &= ~XT1OFF; + + return STATUS_SUCCESS; + } else + return STATUS_FAIL; +} + +//***************************************************************************** +// +//! \brief Initializes the XT1 crystal oscillator in high frequency mode with +//! timeout +//! +//! Initializes the XT1 crystal oscillator in high frequency mode with timeout. +//! Loops until all oscillator fault flags are cleared or until a timeout +//! counter is decremented and equals to zero. See the device-specific data +//! sheet for appropriate drive settings. +//! +//! \param xt1drive is the target drive strength for the XT1 crystal +//! oscillator. +//! Valid values are: +//! - \b UCS_XT1_DRIVE0 +//! - \b UCS_XT1_DRIVE1 +//! - \b UCS_XT1_DRIVE2 +//! - \b UCS_XT1_DRIVE3 [Default] +//! \param timeout is the count value that gets decremented every time the loop +//! that clears oscillator fault flags gets executed. +//! +//! Modified bits of \b UCSCTL7 register, bits of \b UCSCTL6 register and bits +//! of \b SFRIFG register. +//! +//! \return STATUS_SUCCESS or STATUS_FAIL +// +//***************************************************************************** +bool UCS_HFXT1StartWithTimeout(uint16_t xt1drive, + uint16_t timeout + ) +{ + assert((xt1drive == UCS_XT1_DRIVE0 ) || + (xt1drive == UCS_XT1_DRIVE1 ) || + (xt1drive == UCS_XT1_DRIVE2 ) || + (xt1drive == UCS_XT1_DRIVE3 )); + + assert(timeout > 0); + + //Check if drive value is the expected one + if ((HWREG16(UCS_BASE + OFS_UCSCTL6) & XT1DRIVE_3) != xt1drive) { + //Clear XT1drive field + HWREG16(UCS_BASE + OFS_UCSCTL6) &= ~XT1DRIVE_3; + + //Set requested value + HWREG16(UCS_BASE + OFS_UCSCTL6) |= xt1drive; + } + + //Enable HF mode + HWREG16(UCS_BASE + OFS_UCSCTL6) |= XTS; + + HWREG16(UCS_BASE + OFS_UCSCTL6) &= ~XT1BYPASS; + + // Check XT1 fault flags + do { + HWREG8(UCS_BASE + OFS_UCSCTL7) &= ~(XT1HFOFFG); + + //Clear OFIFG fault flag + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + } while ((HWREG8(UCS_BASE + OFS_UCSCTL7) & ( XT1HFOFFG)) + && --timeout); + + if (timeout) { + //Switch ON XT1 oscillator + HWREG16(UCS_BASE + OFS_UCSCTL6) &= ~XT1OFF; + + return STATUS_SUCCESS; + } else + return STATUS_FAIL; +} + +//***************************************************************************** +// +//! \brief Bypasses the XT1 crystal oscillator with time out +//! +//! Bypasses the XT1 crystal oscillator with time out. Loops until all +//! oscillator fault flags are cleared or until a timeout counter is +//! decremented and equals to zero. +//! +//! \param highOrLowFrequency selects high frequency or low frequency mode for +//! XT1. +//! Valid values are: +//! - \b UCS_XT1_HIGH_FREQUENCY +//! - \b UCS_XT1_LOW_FREQUENCY [Default] +//! \param timeout is the count value that gets decremented every time the loop +//! that clears oscillator fault flags gets executed. +//! +//! Modified bits of \b UCSCTL7 register, bits of \b UCSCTL6 register and bits +//! of \b SFRIFG register. +//! +//! \return STATUS_SUCCESS or STATUS_FAIL +// +//***************************************************************************** +bool UCS_bypassXT1WithTimeout(uint8_t highOrLowFrequency, + uint16_t timeout + ) +{ + assert((UCS_XT1_LOW_FREQUENCY == highOrLowFrequency) || + (UCS_XT1_HIGH_FREQUENCY == highOrLowFrequency ) + ); + + assert(timeout > 0); + + //Enable HF/LF mode + HWREG16(UCS_BASE + OFS_UCSCTL6) &= ~XTS; + HWREG16(UCS_BASE + OFS_UCSCTL6) |= highOrLowFrequency; + + //Switch OFF XT1 oscillator and enable bypass + HWREG16(UCS_BASE + OFS_UCSCTL6) |= (XT1BYPASS + XT1OFF); + + if (UCS_XT1_LOW_FREQUENCY == highOrLowFrequency) { + do { + //Clear OSC flaut Flags fault flags + HWREG8(UCS_BASE + OFS_UCSCTL7) &= ~(XT1LFOFFG); + + // Clear the global fault flag. In case the XT1 caused the global fault + // flag to get set this will clear the global error condition. If any + // error condition persists, global flag will get again. + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + } while ((HWREG8(UCS_BASE + OFS_UCSCTL7) & (XT1LFOFFG)) && --timeout); + + } else { + do { + //Clear OSC flaut Flags fault flags + HWREG8(UCS_BASE + OFS_UCSCTL7) &= ~(XT1HFOFFG); + + //Clear the global fault flag. In case the XT1 caused the global fault + //flag to get set this will clear the global error condition. If any + //error condition persists, global flag will get again. + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + } while ((HWREG8(UCS_BASE + OFS_UCSCTL7) & (XT1HFOFFG)) && --timeout); + } + + if (timeout) + return STATUS_SUCCESS; + else + return STATUS_FAIL; +} + +//***************************************************************************** +// +//! \brief Stops the XT1 oscillator using the XT1OFF bit. +//! +//! +//! \return None +// +//***************************************************************************** +void UCS_XT1Off(void) +{ + //Switch off XT1 oscillator + HWREG16(UCS_BASE + OFS_UCSCTL6) |= XT1OFF; +} + +//***************************************************************************** +// +//! \brief Initializes the XT2 crystal oscillator +//! +//! Initializes the XT2 crystal oscillator, which supports crystal frequencies +//! between 4 MHz and 32 MHz, depending on the selected drive strength. Loops +//! until all oscillator fault flags are cleared, with no timeout. See the +//! device-specific data sheet for appropriate drive settings. +//! +//! \param xt2drive is the target drive strength for the XT2 crystal +//! oscillator. +//! Valid values are: +//! - \b UCS_XT2DRIVE_4MHZ_8MHZ +//! - \b UCS_XT2DRIVE_8MHZ_16MHZ +//! - \b UCS_XT2DRIVE_16MHZ_24MHZ +//! - \b UCS_XT2DRIVE_24MHZ_32MHZ [Default] +//! +//! Modified bits of \b UCSCTL7 register, bits of \b UCSCTL6 register and bits +//! of \b SFRIFG register. +//! +//! \return None +// +//***************************************************************************** +void UCS_XT2Start(uint16_t xt2drive + ) +{ +#if !defined (__CC430F5133__) || (__CC430F5135__) || (__CC430F5137__) || \ + (__CC430F6125__) || (__CC430F6126__) || (__CC430F6127__) || \ + (__CC430F6135__) || (__CC430F6137__) || (__CC430F5123__) || \ + (__CC430F5125__) || (__CC430F5143__) || (__CC430F5145__) || \ + (__CC430F5147__) || (__CC430F6143__) || (__CC430F6145__) || \ + (__CC430F6147__) + + //Check if drive value is the expected one + if ((HWREG16(UCS_BASE + OFS_UCSCTL6) & XT2DRIVE_3) != xt2drive) { + //Clear XT2drive field + HWREG16(UCS_BASE + OFS_UCSCTL6) &= ~XT2DRIVE_3; + + //Set requested value + HWREG16(UCS_BASE + OFS_UCSCTL6) |= xt2drive; + } +#endif + + //Enable XT2 and Switch on XT2 oscillator + HWREG16(UCS_BASE + OFS_UCSCTL6) &= ~XT2BYPASS; + HWREG16(UCS_BASE + OFS_UCSCTL6) &= ~XT2OFF; + + while (HWREG8(UCS_BASE + OFS_UCSCTL7) & XT2OFFG) { + //Clear OSC flaut Flags + HWREG8(UCS_BASE + OFS_UCSCTL7) &= ~(XT2OFFG); + +#if defined (__CC430F5133__) || (__CC430F5135__) || (__CC430F5137__) || \ + (__CC430F6125__) || (__CC430F6126__) || (__CC430F6127__) || \ + (__CC430F6135__) || (__CC430F6137__) || (__CC430F5123__) || \ + (__CC430F5125__) || (__CC430F5143__) || (__CC430F5145__) || \ + (__CC430F5147__) || (__CC430F6143__) || (__CC430F6145__) || \ + (__CC430F6147__) + // CC430 uses a different fault mechanism. It requires 3 VLO clock + // cycles delay.If 20MHz CPU, 5000 clock cycles are required in worst + // case. + __delay_cycles(5000); +#endif + + //Clear OFIFG fault flag + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + } +} + +//***************************************************************************** +// +//! \brief Bypasses the XT2 crystal oscillator +//! +//! Bypasses the XT2 crystal oscillator, which supports crystal frequencies +//! between 4 MHz and 32 MHz. Loops until all oscillator fault flags are +//! cleared, with no timeout. +//! +//! +//! Modified bits of \b UCSCTL7 register, bits of \b UCSCTL6 register and bits +//! of \b SFRIFG register. +//! +//! \return None +// +//***************************************************************************** +void UCS_bypassXT2(void) +{ + //Switch on XT2 oscillator + HWREG16(UCS_BASE + OFS_UCSCTL6) |= ( XT2BYPASS + XT2OFF ); + + while (HWREG8(UCS_BASE + OFS_UCSCTL7) & XT2OFFG) { + //Clear OSC flaut Flags + HWREG8(UCS_BASE + OFS_UCSCTL7) &= ~(XT2OFFG); + +#if defined (__CC430F5133__) || (__CC430F5135__) || (__CC430F5137__) || \ + (__CC430F6125__) || (__CC430F6126__) || (__CC430F6127__) || \ + (__CC430F6135__) || (__CC430F6137__) || (__CC430F5123__) || \ + (__CC430F5125__) || (__CC430F5143__) || (__CC430F5145__) || \ + (__CC430F5147__) || (__CC430F6143__) || (__CC430F6145__) || \ + (__CC430F6147__) + // CC430 uses a different fault mechanism. It requires 3 VLO clock + // cycles delay.If 20MHz CPU, 5000 clock cycles are required in worst + // case. + __delay_cycles(5000); +#endif + + //Clear OFIFG fault flag + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + } +} + +//***************************************************************************** +// +//! \brief Initializes the XT2 crystal oscillator with timeout +//! +//! Initializes the XT2 crystal oscillator, which supports crystal frequencies +//! between 4 MHz and 32 MHz, depending on the selected drive strength. Loops +//! until all oscillator fault flags are cleared or until a timeout counter is +//! decremented and equals to zero. See the device-specific data sheet for +//! appropriate drive settings. +//! +//! \param xt2drive is the target drive strength for the XT2 crystal +//! oscillator. +//! Valid values are: +//! - \b UCS_XT2DRIVE_4MHZ_8MHZ +//! - \b UCS_XT2DRIVE_8MHZ_16MHZ +//! - \b UCS_XT2DRIVE_16MHZ_24MHZ +//! - \b UCS_XT2DRIVE_24MHZ_32MHZ [Default] +//! \param timeout is the count value that gets decremented every time the loop +//! that clears oscillator fault flags gets executed. +//! +//! Modified bits of \b UCSCTL7 register, bits of \b UCSCTL6 register and bits +//! of \b SFRIFG register. +//! +//! \return STATUS_SUCCESS or STATUS_FAIL +// +//***************************************************************************** +bool UCS_XT2StartWithTimeout(uint16_t xt2drive, + uint16_t timeout + ) +{ + assert(timeout > 0); + +#if !defined (__CC430F5133__) || (__CC430F5135__) || (__CC430F5137__) || \ + (__CC430F6125__) || (__CC430F6126__) || (__CC430F6127__) || \ + (__CC430F6135__) || (__CC430F6137__) || (__CC430F5123__) || \ + (__CC430F5125__) || (__CC430F5143__) || (__CC430F5145__) || \ + (__CC430F5147__) || (__CC430F6143__) || (__CC430F6145__) || \ + (__CC430F6147__) + //Check if drive value is the expected one + if ((HWREG16(UCS_BASE + OFS_UCSCTL6) & XT2DRIVE_3) != xt2drive) { + //Clear XT2drive field + HWREG16(UCS_BASE + OFS_UCSCTL6) &= ~XT2DRIVE_3; + + //Set requested value + HWREG16(UCS_BASE + OFS_UCSCTL6) |= xt2drive; + } + +#endif + + HWREG16(UCS_BASE + OFS_UCSCTL6) &= ~XT2BYPASS; + + //Switch on XT2 oscillator + HWREG16(UCS_BASE + OFS_UCSCTL6) &= ~XT2OFF; + + do { + //Clear OSC flaut Flags + HWREG8(UCS_BASE + OFS_UCSCTL7) &= ~(XT2OFFG); + +#if defined (__CC430F5133__) || (__CC430F5135__) || (__CC430F5137__) || \ + (__CC430F6125__) || (__CC430F6126__) || (__CC430F6127__) || \ + (__CC430F6135__) || (__CC430F6137__) || (__CC430F5123__) || \ + (__CC430F5125__) || (__CC430F5143__) || (__CC430F5145__) || \ + (__CC430F5147__) || (__CC430F6143__) || (__CC430F6145__) || \ + (__CC430F6147__) + // CC430 uses a different fault mechanism. It requires 3 VLO clock + // cycles delay.If 20MHz CPU, 5000 clock cycles are required in worst + // case. + __delay_cycles(5000); +#endif + + //Clear OFIFG fault flag + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + } while ((HWREG8(UCS_BASE + OFS_UCSCTL7) & XT2OFFG) && --timeout); + + if (timeout) + return STATUS_SUCCESS; + else + return STATUS_FAIL; +} + +//***************************************************************************** +// +//! \brief Bypasses the XT2 crystal oscillator with timeout +//! +//! Bypasses the XT2 crystal oscillator, which supports crystal frequencies +//! between 4 MHz and 32 MHz. Loops until all oscillator fault flags are +//! cleared or until a timeout counter is decremented and equals to zero. +//! +//! \param timeout is the count value that gets decremented every time the loop +//! that clears oscillator fault flags gets executed. +//! +//! Modified bits of \b UCSCTL7 register, bits of \b UCSCTL6 register and bits +//! of \b SFRIFG register. +//! +//! \return STATUS_SUCCESS or STATUS_FAIL +// +//***************************************************************************** +bool UCS_bypassXT2WithTimeout(uint16_t timeout + ) +{ + assert(timeout > 0); + + //Switch off XT2 oscillator and enable BYPASS mode + HWREG16(UCS_BASE + OFS_UCSCTL6) |= (XT2BYPASS + XT2OFF ); + + do { + //Clear OSC flaut Flags + HWREG8(UCS_BASE + OFS_UCSCTL7) &= ~(XT2OFFG); + +#if defined (__CC430F5133__) || (__CC430F5135__) || (__CC430F5137__) || \ + (__CC430F6125__) || (__CC430F6126__) || (__CC430F6127__) || \ + (__CC430F6135__) || (__CC430F6137__) || (__CC430F5123__) || \ + (__CC430F5125__) || (__CC430F5143__) || (__CC430F5145__) || \ + (__CC430F5147__) || (__CC430F6143__) || (__CC430F6145__) || \ + (__CC430F6147__) + // CC430 uses a different fault mechanism. It requires 3 VLO clock + // cycles delay.If 20MHz CPU, 5000 clock cycles are required in worst + // case. + __delay_cycles(5000); +#endif + + //Clear OFIFG fault flag + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + } while ((HWREG8(UCS_BASE + OFS_UCSCTL7) & XT2OFFG) && --timeout); + + if (timeout) + return STATUS_SUCCESS; + else + return STATUS_FAIL; +} + +//***************************************************************************** +// +//! \brief Stops the XT2 oscillator using the XT2OFF bit. +//! +//! +//! Modified bits of \b UCSCTL6 register. +//! +//! \return None +// +//***************************************************************************** +void UCS_XT2Off(void) +{ + //Switch off XT2 oscillator + HWREG16(UCS_BASE + OFS_UCSCTL6) |= XT2OFF; +} + +//***************************************************************************** +// +//! \brief Initializes the DCO to operate a frequency that is a multiple of the +//! reference frequency into the FLL +//! +//! Initializes the DCO to operate a frequency that is a multiple of the +//! reference frequency into the FLL. Loops until all oscillator fault flags +//! are cleared, with a timeout. If the frequency is greater than 16 MHz, the +//! function sets the MCLK and SMCLK source to the undivided DCO frequency. +//! Otherwise, the function sets the MCLK and SMCLK source to the DCOCLKDIV +//! frequency. This function executes a software delay that is proportional in +//! length to the ratio of the target FLL frequency and the FLL reference. +//! +//! \param fsystem is the target frequency for MCLK in kHz +//! \param ratio is the ratio x/y, where x = fsystem and y = FLL reference +//! frequency. +//! +//! Modified bits of \b UCSCTL0 register, bits of \b UCSCTL4 register, bits of +//! \b UCSCTL7 register, bits of \b UCSCTL1 register, bits of \b SFRIFG1 +//! register and bits of \b UCSCTL2 register. +//! +//! \return None +// +//***************************************************************************** +void UCS_initFLLSettle(uint16_t fsystem, + uint16_t ratio + ) +{ + volatile uint16_t x = ratio * 32; + + UCS_initFLL(fsystem, ratio); + + while (x--) + __delay_cycles(30); +} + +//***************************************************************************** +// +//! \brief Initializes the DCO to operate a frequency that is a multiple of the +//! reference frequency into the FLL +//! +//! Initializes the DCO to operate a frequency that is a multiple of the +//! reference frequency into the FLL. Loops until all oscillator fault flags +//! are cleared, with no timeout. If the frequency is greater than 16 MHz, the +//! function sets the MCLK and SMCLK source to the undivided DCO frequency. +//! Otherwise, the function sets the MCLK and SMCLK source to the DCOCLKDIV +//! frequency. +//! +//! \param fsystem is the target frequency for MCLK in kHz +//! \param ratio is the ratio x/y, where x = fsystem and y = FLL reference +//! frequency. +//! +//! Modified bits of \b UCSCTL0 register, bits of \b UCSCTL4 register, bits of +//! \b UCSCTL7 register, bits of \b UCSCTL1 register, bits of \b SFRIFG1 +//! register and bits of \b UCSCTL2 register. +//! +//! \return None +// +//***************************************************************************** +void UCS_initFLL(uint16_t fsystem, + uint16_t ratio + ) +{ + uint16_t d, dco_div_bits; + uint16_t mode = 0; + + //Save actual state of FLL loop control, then disable it. This is needed to + //prevent the FLL from acting as we are making fundamental modifications to + //the clock setup. + uint16_t srRegisterState = __get_SR_register() & SCG0; + + d = ratio; + //Have at least a divider of 2 + dco_div_bits = FLLD__2; + + if (fsystem > 16000) { + d >>= 1; + mode = 1; + } else + //fsystem = fsystem * 2 + fsystem <<= 1; + + while (d > 512) { + //Set next higher div level + dco_div_bits = dco_div_bits + FLLD0; + d >>= 1; + } + + // Disable FLL + __bis_SR_register(SCG0); + + //Set DCO to lowest Tap + HWREG8(UCS_BASE + OFS_UCSCTL0_H) = 0x0000; + + //Reset FN bits + HWREG16(UCS_BASE + OFS_UCSCTL2) &= ~(0x03FF); + HWREG16(UCS_BASE + OFS_UCSCTL2) = dco_div_bits | (d - 1); + + if (fsystem <= 630) //fsystem < 0.63MHz + HWREG8(UCS_BASE + OFS_UCSCTL1) = DCORSEL_0; + else if (fsystem < 1250) //0.63MHz < fsystem < 1.25MHz + HWREG8(UCS_BASE + OFS_UCSCTL1) = DCORSEL_1; + else if (fsystem < 2500) //1.25MHz < fsystem < 2.5MHz + HWREG8(UCS_BASE + OFS_UCSCTL1) = DCORSEL_2; + else if (fsystem < 5000) //2.5MHz < fsystem < 5MHz + HWREG8(UCS_BASE + OFS_UCSCTL1) = DCORSEL_3; + else if (fsystem < 10000) //5MHz < fsystem < 10MHz + HWREG8(UCS_BASE + OFS_UCSCTL1) = DCORSEL_4; + else if (fsystem < 20000) //10MHz < fsystem < 20MHz + HWREG8(UCS_BASE + OFS_UCSCTL1) = DCORSEL_5; + else if (fsystem < 40000) //20MHz < fsystem < 40MHz + HWREG8(UCS_BASE + OFS_UCSCTL1) = DCORSEL_6; + else + HWREG8(UCS_BASE + OFS_UCSCTL1) = DCORSEL_7; + + // Re-enable FLL + __bic_SR_register(SCG0); + + while (HWREG8(UCS_BASE + OFS_UCSCTL7_L) & DCOFFG) { + //Clear OSC flaut Flags + HWREG8(UCS_BASE + OFS_UCSCTL7_L) &= ~(DCOFFG); + + //Clear OFIFG fault flag + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + } + + // Restore previous SCG0 + __bis_SR_register(srRegisterState); + + if (mode == 1) { + //fsystem > 16000 + //Select DCOCLK + HWREG16(UCS_BASE + OFS_UCSCTL4) &= ~(SELM_7 + SELS_7); + HWREG16(UCS_BASE + OFS_UCSCTL4) |= SELM__DCOCLK + SELS__DCOCLK; + } else { + //Select DCODIVCLK + HWREG16(UCS_BASE + OFS_UCSCTL4) &= ~(SELM_7 + SELS_7); + HWREG16(UCS_BASE + OFS_UCSCTL4) |= SELM__DCOCLKDIV + SELS__DCOCLKDIV; + } + +} + +//***************************************************************************** +// +//! \brief Enables conditional module requests +//! +//! \param selectClock selects specific request enables +//! Valid values are: +//! - \b UCS_ACLK +//! - \b UCS_SMCLK +//! - \b UCS_MCLK +//! - \b UCS_MODOSC +//! +//! Modified bits of \b UCSCTL8 register. +//! +//! \return None +// +//***************************************************************************** +void UCS_enableClockRequest(uint8_t selectClock + ) +{ + HWREG8(UCS_BASE + OFS_UCSCTL8) |= selectClock; +} + +//***************************************************************************** +// +//! \brief Disables conditional module requests +//! +//! \param selectClock selects specific request disable +//! Valid values are: +//! - \b UCS_ACLK +//! - \b UCS_SMCLK +//! - \b UCS_MCLK +//! - \b UCS_MODOSC +//! +//! Modified bits of \b UCSCTL8 register. +//! +//! \return None +// +//***************************************************************************** +void UCS_disableClockRequest(uint8_t selectClock + ) +{ + HWREG8(UCS_BASE + OFS_UCSCTL8) &= ~selectClock; +} + +//***************************************************************************** +// +//! \brief Gets the current UCS fault flag status. +//! +//! \param mask is the masked interrupt flag status to be returned. Mask +//! parameter can be either any of the following selection. +//! Valid values are: +//! - \b UCS_XT2OFFG - XT2 oscillator fault flag +//! - \b UCS_XT1HFOFFG - XT1 oscillator fault flag (HF mode) +//! - \b UCS_XT1LFOFFG - XT1 oscillator fault flag (LF mode) +//! - \b UCS_DCOFFG - DCO fault flag +//! +// +//***************************************************************************** +uint8_t UCS_faultFlagStatus(uint8_t mask + ) +{ + assert(mask <= UCS_XT2OFFG ); + return HWREG8(UCS_BASE + OFS_UCSCTL7) & mask; +} + +//***************************************************************************** +// +//! \brief Clears the current UCS fault flag status for the masked bit. +//! +//! \param mask is the masked interrupt flag status to be returned. mask +//! parameter can be any one of the following +//! Valid values are: +//! - \b UCS_XT2OFFG - XT2 oscillator fault flag +//! - \b UCS_XT1HFOFFG - XT1 oscillator fault flag (HF mode) +//! - \b UCS_XT1LFOFFG - XT1 oscillator fault flag (LF mode) +//! - \b UCS_DCOFFG - DCO fault flag +//! +//! Modified bits of \b UCSCTL7 register. +//! +//! \return None +// +//***************************************************************************** +void UCS_clearFaultFlag(uint8_t mask + ) +{ + assert(mask <= UCS_XT2OFFG ); + HWREG8(UCS_BASE + OFS_UCSCTL7) &= ~mask; +} + +//***************************************************************************** +// +//! \brief Turns off SMCLK using the SMCLKOFF bit +//! +//! +//! Modified bits of \b UCSCTL6 register. +//! +//! \return None +// +//***************************************************************************** +void UCS_SMCLKOff(void) +{ + HWREG16(UCS_BASE + OFS_UCSCTL6) |= SMCLKOFF; +} + +//***************************************************************************** +// +//! \brief Turns ON SMCLK using the SMCLKOFF bit +//! +//! +//! Modified bits of \b UCSCTL6 register. +//! +//! \return None +// +//***************************************************************************** +void UCS_SMCLKOn(void) +{ + HWREG16(UCS_BASE + OFS_UCSCTL6) &= ~SMCLKOFF; +} + +//***************************************************************************** +// +//! \brief Get the current ACLK frequency +//! +//! Get the current ACLK frequency. The user of this API must ensure that +//! UCS_setExternalClockSource API was invoked before in case XT1 or XT2 is +//! being used. +//! +//! +//! \return Current ACLK frequency in Hz +// +//***************************************************************************** +uint32_t UCS_getACLK(void) +{ + //Find ACLK source + uint16_t ACLKSource = (HWREG16(UCS_BASE + OFS_UCSCTL4) & SELA_7); + + ACLKSource = ACLKSource >> 8; + + uint16_t ACLKSourceDivider = HWREG16(UCS_BASE + OFS_UCSCTL5) & DIVA_7; + ACLKSourceDivider = ACLKSourceDivider >> 8; + + return privateUCSComputeCLKFrequency( + ACLKSource, + ACLKSourceDivider + ); +} + +//***************************************************************************** +// +//! \brief Get the current SMCLK frequency +//! +//! Get the current SMCLK frequency. The user of this API must ensure that +//! UCS_setExternalClockSource API was invoked before in case XT1 or XT2 is +//! being used. +//! +//! +//! \return Current SMCLK frequency in Hz +// +//***************************************************************************** +uint32_t UCS_getSMCLK(void) +{ + uint16_t SMCLKSource = HWREG8(UCS_BASE + OFS_UCSCTL4_L) & SELS_7; + + SMCLKSource = SMCLKSource >> 4; + + uint16_t SMCLKSourceDivider = + HWREG16(UCS_BASE + OFS_UCSCTL5) & DIVS_7; + SMCLKSourceDivider = SMCLKSourceDivider >> 4; + + return privateUCSComputeCLKFrequency( + SMCLKSource, + SMCLKSourceDivider ) + ; +} + +//***************************************************************************** +// +//! \brief Get the current MCLK frequency +//! +//! Get the current MCLK frequency. The user of this API must ensure that +//! UCS_setExternalClockSource API was invoked before in case XT1 or XT2 is +//! being used. +//! +//! +//! \return Current MCLK frequency in Hz +// +//***************************************************************************** +uint32_t UCS_getMCLK(void) +{ + //Find AMCLK source + uint16_t MCLKSource = (HWREG16(UCS_BASE + OFS_UCSCTL4) & SELM_7); + + uint16_t MCLKSourceDivider = HWREG16(UCS_BASE + OFS_UCSCTL5) & DIVM_7; + + return privateUCSComputeCLKFrequency( + MCLKSource, + MCLKSourceDivider ) + ; +} + +//***************************************************************************** +// +//! \brief Clears all the Oscillator Flags +//! +//! \param timeout is the count value that gets decremented every time the loop +//! that clears oscillator fault flags gets executed. +//! +//! \return Logical OR of any of the following: +//! - \b UCS_XT2OFFG XT2 oscillator fault flag +//! - \b UCS_XT1HFOFFG XT1 oscillator fault flag (HF mode) +//! - \b UCS_XT1LFOFFG XT1 oscillator fault flag (LF mode) +//! - \b UCS_DCOFFG DCO fault flag +//! \n indicating the status of the oscillator fault flags +// +//***************************************************************************** +uint16_t UCS_clearAllOscFlagsWithTimeout(uint16_t timeout + ) +{ + assert(timeout > 0); + + do { + // Clear all osc fault flags + HWREG8(UCS_BASE + OFS_UCSCTL7) &= ~(DCOFFG + + XT1LFOFFG + + XT1HFOFFG + + XT2OFFG + ); + +#if defined (__CC430F5133__) || (__CC430F5135__) || (__CC430F5137__) || \ + (__CC430F6125__) || (__CC430F6126__) || (__CC430F6127__) || \ + (__CC430F6135__) || (__CC430F6137__) || (__CC430F5123__) || \ + (__CC430F5125__) || (__CC430F5143__) || (__CC430F5145__) || \ + (__CC430F5147__) || (__CC430F6143__) || (__CC430F6145__) || \ + (__CC430F6147__) + // CC430 uses a different fault mechanism. It requires 3 VLO clock + // cycles delay.If 20MHz CPU, 5000 clock cycles are required in worst + // case. + __delay_cycles(5000); +#endif + + // Clear the global osc fault flag. + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + + // Check XT1 fault flags + } while ((HWREG8(SFR_BASE + OFS_SFRIFG1) & OFIFG) && --timeout); + + return HWREG8(UCS_BASE + OFS_UCSCTL7) & (DCOFFG + + XT1LFOFFG + + XT1HFOFFG + + XT2OFFG) + ; +} + +#endif +#endif +//***************************************************************************** +// +//! Close the doxygen group for ucs_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/ucs.h b/source/driverlib/MSP430F5xx_6xx/ucs.h new file mode 100644 index 0000000..46fe68d --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/ucs.h @@ -0,0 +1,253 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// ucs.h - Driver for the UCS Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_UCS_H__ +#define __MSP430WARE_UCS_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_UCS__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Internal very low power VLOCLK, low frequency oscillator with 10 kHz typical +// frequency +// +//***************************************************************************** +#define UCS_VLOCLK_FREQUENCY 10000 + +//***************************************************************************** +// +// Internal, trimmed, low-frequency oscillator with 32768 Hz typical frequency +// +//***************************************************************************** +#define UCS_REFOCLK_FREQUENCY 32768 + +//***************************************************************************** +// +// The following are values that can be passed to the clockSourceDivider +// parameter for functions: UCS_clockSignalInit(). +// +//***************************************************************************** +#define UCS_CLOCK_DIVIDER_1 DIVM__1 +#define UCS_CLOCK_DIVIDER_2 DIVM__2 +#define UCS_CLOCK_DIVIDER_4 DIVM__4 +#define UCS_CLOCK_DIVIDER_8 DIVM__8 +#define UCS_CLOCK_DIVIDER_12 DIVM__32 +#define UCS_CLOCK_DIVIDER_16 DIVM__16 +#define UCS_CLOCK_DIVIDER_32 DIVM__32 + +//***************************************************************************** +// +// The following are values that can be passed to the selectedClockSignal +// parameter for functions: UCS_clockSignalInit(). +// +//***************************************************************************** +#define UCS_ACLK 0x01 +#define UCS_MCLK 0x02 +#define UCS_SMCLK 0x04 +#define UCS_FLLREF 0x08 + +//***************************************************************************** +// +// The following are values that can be passed to the clockSource parameter for +// functions: UCS_clockSignalInit(). +// +//***************************************************************************** +#define UCS_XT1CLK_SELECT SELM__XT1CLK +#define UCS_VLOCLK_SELECT SELM__VLOCLK +#define UCS_REFOCLK_SELECT SELM__REFOCLK +#define UCS_DCOCLK_SELECT SELM__DCOCLK +#define UCS_DCOCLKDIV_SELECT SELM__DCOCLKDIV +#define UCS_XT2CLK_SELECT SELM__XT2CLK + +//***************************************************************************** +// +// The following are values that can be passed to the xcap parameter for +// functions: UCS_LFXT1Start(), and UCS_LFXT1StartWithTimeout(). +// +//***************************************************************************** +#define UCS_XCAP_0 XCAP_0 +#define UCS_XCAP_1 XCAP_1 +#define UCS_XCAP_2 XCAP_2 +#define UCS_XCAP_3 XCAP_3 + +//***************************************************************************** +// +// The following are values that can be passed to the xt1drive parameter for +// functions: UCS_LFXT1Start(), UCS_HFXT1Start(), UCS_LFXT1StartWithTimeout(), +// and UCS_HFXT1StartWithTimeout(). +// +//***************************************************************************** +#define UCS_XT1_DRIVE0 XT1DRIVE_0 +#define UCS_XT1_DRIVE1 XT1DRIVE_1 +#define UCS_XT1_DRIVE2 XT1DRIVE_2 +#define UCS_XT1_DRIVE3 XT1DRIVE_3 + +//***************************************************************************** +// +// The following are values that can be passed to the highOrLowFrequency +// parameter for functions: UCS_bypassXT1(), and UCS_bypassXT1WithTimeout(). +// +//***************************************************************************** +#define UCS_XT1_HIGH_FREQUENCY XTS +#define UCS_XT1_LOW_FREQUENCY 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the xt2drive parameter for +// functions: UCS_XT2Start(), and UCS_XT2StartWithTimeout(). +// +//***************************************************************************** +#define UCS_XT2DRIVE_4MHZ_8MHZ XT2DRIVE_0 +#define UCS_XT2DRIVE_8MHZ_16MHZ XT2DRIVE_1 +#define UCS_XT2DRIVE_16MHZ_24MHZ XT2DRIVE_2 +#define UCS_XT2DRIVE_24MHZ_32MHZ XT2DRIVE_3 + +//***************************************************************************** +// +// The following are values that can be passed to the selectClock parameter for +// functions: UCS_enableClockRequest(), and UCS_disableClockRequest(). +// +//***************************************************************************** +#define UCS_ACLK 0x01 +#define UCS_SMCLK 0x04 +#define UCS_MCLK 0x02 +#define UCS_MODOSC MODOSCREQEN + +//***************************************************************************** +// +// The following are values that can be passed to the mask parameter for +// functions: UCS_faultFlagStatus(), and UCS_clearFaultFlag() as well as +// returned by the UCS_clearAllOscFlagsWithTimeout() function. +// +//***************************************************************************** +#define UCS_XT2OFFG XT2OFFG +#define UCS_XT1HFOFFG XT1HFOFFG +#define UCS_XT1LFOFFG XT1LFOFFG +#define UCS_DCOFFG DCOFFG + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void UCS_setExternalClockSource(uint32_t XT1CLK_frequency, + uint32_t XT2CLK_frequency); + +extern void UCS_clockSignalInit(uint8_t selectedClockSignal, + uint16_t clockSource, + uint16_t clockSourceDivider); + +extern void UCS_LFXT1Start(uint16_t xt1drive, + uint8_t xcap); + +extern void UCS_HFXT1Start(uint16_t xt1drive); + +extern void UCS_bypassXT1(uint8_t highOrLowFrequency); + +extern bool UCS_LFXT1StartWithTimeout(uint16_t xt1drive, + uint8_t xcap, + uint16_t timeout); + +extern bool UCS_HFXT1StartWithTimeout(uint16_t xt1drive, + uint16_t timeout); + +extern bool UCS_bypassXT1WithTimeout(uint8_t highOrLowFrequency, + uint16_t timeout); + +extern void UCS_XT1Off(void); + +extern void UCS_XT2Start(uint16_t xt2drive); + +extern void UCS_bypassXT2(void); + +extern bool UCS_XT2StartWithTimeout(uint16_t xt2drive, + uint16_t timeout); + +extern bool UCS_bypassXT2WithTimeout(uint16_t timeout); + +extern void UCS_XT2Off(void); + +extern void UCS_initFLLSettle(uint16_t fsystem, + uint16_t ratio); + +extern void UCS_initFLL(uint16_t fsystem, + uint16_t ratio); + +extern void UCS_enableClockRequest(uint8_t selectClock); + +extern void UCS_disableClockRequest(uint8_t selectClock); + +extern uint8_t UCS_faultFlagStatus(uint8_t mask); + +extern void UCS_clearFaultFlag(uint8_t mask); + +extern void UCS_SMCLKOff(void); + +extern void UCS_SMCLKOn(void); + +extern uint32_t UCS_getACLK(void); + +extern uint32_t UCS_getSMCLK(void); + +extern uint32_t UCS_getMCLK(void); + +extern uint16_t UCS_clearAllOscFlagsWithTimeout(uint16_t timeout); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_UCS_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/usci_a_spi.c b/source/driverlib/MSP430F5xx_6xx/usci_a_spi.c new file mode 100644 index 0000000..a719f62 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/usci_a_spi.c @@ -0,0 +1,614 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// usci_a_spi.c - Driver for the usci_a_spi Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup usci_a_spi_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_USCI_Ax__ +#include "usci_a_spi.h" + +#include + +//***************************************************************************** +// +//! \brief DEPRECATED - Initializes the SPI Master block. +//! +//! Upon successful initialization of the SPI master block, this function will +//! have set the bus speed for the master, but the SPI Master block still +//! remains disabled and must be enabled with USCI_A_SPI_enable() +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param selectClockSource selects Clock source. +//! Valid values are: +//! - \b USCI_A_SPI_CLOCKSOURCE_ACLK +//! - \b USCI_A_SPI_CLOCKSOURCE_SMCLK +//! \param clockSourceFrequency is the frequency of the selected clock source +//! \param desiredSpiClock is the desired clock rate for SPI communication +//! \param msbFirst controls the direction of the receive and transmit shift +//! register. +//! Valid values are: +//! - \b USCI_A_SPI_MSB_FIRST +//! - \b USCI_A_SPI_LSB_FIRST [Default] +//! \param clockPhase is clock phase select. +//! Valid values are: +//! - \b USCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT +//! [Default] +//! - \b USCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT +//! \param clockPolarity +//! Valid values are: +//! - \b USCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH +//! - \b USCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default] +//! +//! Modified bits are \b UCCKPH, \b UCCKPL, \b UC7BIT and \b UCMSB of \b +//! UCAxCTL0 register; bits \b UCSSELx and \b UCSWRST of \b UCAxCTL1 register. +//! +//! \return STATUS_SUCCESS +// +//***************************************************************************** +bool USCI_A_SPI_masterInit(uint16_t baseAddress, + uint8_t selectClockSource, + uint32_t clockSourceFrequency, + uint32_t desiredSpiClock, + uint8_t msbFirst, + uint8_t clockPhase, + uint8_t clockPolarity + ) +{ + USCI_A_SPI_initMasterParam param = { 0 }; + + param.selectClockSource = selectClockSource; + param.clockSourceFrequency = clockSourceFrequency; + param.desiredSpiClock = desiredSpiClock; + param.msbFirst = msbFirst; + param.clockPhase = clockPhase; + param.clockPolarity = clockPolarity; + + return USCI_A_SPI_initMaster(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Initializes the SPI Master block. +//! +//! Upon successful initialization of the SPI master block, this function will +//! have set the bus speed for the master, but the SPI Master block still +//! remains disabled and must be enabled with USCI_A_SPI_enable() +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param param is the pointer to struct for master initialization. +//! +//! Modified bits are \b UCCKPH, \b UCCKPL, \b UC7BIT and \b UCMSB of \b +//! UCAxCTL0 register; bits \b UCSSELx and \b UCSWRST of \b UCAxCTL1 register. +//! +//! \return STATUS_SUCCESS +// +//***************************************************************************** +bool USCI_A_SPI_initMaster(uint16_t baseAddress, USCI_A_SPI_initMasterParam *param) +{ + assert(param != 0); + + assert( + (USCI_A_SPI_CLOCKSOURCE_ACLK == param->selectClockSource) || + (USCI_A_SPI_CLOCKSOURCE_SMCLK == param->selectClockSource) + ); + + assert((USCI_A_SPI_MSB_FIRST == param->msbFirst) || + (USCI_A_SPI_LSB_FIRST == param->msbFirst) + ); + + assert( (USCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT == param->clockPhase) || + (USCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT == param->clockPhase) + ); + + assert( (USCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == param->clockPolarity) || + (USCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW == param->clockPolarity) + ); + + //Disable the USCI Module + HWREG8(baseAddress + OFS_UCAxCTL1) |= UCSWRST; + + //Reset OFS_UCAxCTL0 values + HWREG8(baseAddress + OFS_UCAxCTL0) &= ~(UCCKPH + UCCKPL + UC7BIT + UCMSB + + UCMST + UCMODE_3 + UCSYNC); + + //Reset OFS_UCAxCTL1 values + HWREG8(baseAddress + OFS_UCAxCTL1) &= ~(UCSSEL_3); + + //Select Clock + HWREG8(baseAddress + OFS_UCAxCTL1) |= param->selectClockSource; + + HWREG16(baseAddress + OFS_UCAxBRW) = + (uint16_t)(param->clockSourceFrequency / param->desiredSpiClock); + + /* + * Configure as SPI master mode. + * Clock phase select, polarity, msb + * UCMST = Master mode + * UCSYNC = Synchronous mode + * UCMODE_0 = 3-pin SPI + */ + HWREG8(baseAddress + OFS_UCAxCTL0) |= ( + param->msbFirst + + param->clockPhase + + param->clockPolarity + + UCMST + + UCSYNC + + UCMODE_0 + ); + //No modulation + HWREG8(baseAddress + OFS_UCAxMCTL) = 0; + + return STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! \brief DEPRECATED - Initializes the SPI Master clock.At the end of this +//! function call, SPI module is left enabled. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param clockSourceFrequency is the frequency of the selected clock source +//! \param desiredSpiClock is the desired clock rate for SPI communication +//! +//! Modified bits of \b UCAxBRW register. +//! +//! \return None +// +//***************************************************************************** +void USCI_A_SPI_masterChangeClock(uint16_t baseAddress, + uint32_t clockSourceFrequency, + uint32_t desiredSpiClock + ) +{ + USCI_A_SPI_changeMasterClockParam param = { 0 }; + + param.clockSourceFrequency = clockSourceFrequency; + param.desiredSpiClock = desiredSpiClock; + + USCI_A_SPI_changeMasterClock(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Initializes the SPI Master clock.At the end of this function call, +//! SPI module is left enabled. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param param is the pointer to struct for master clock setting. +//! +//! Modified bits of \b UCAxBRW register. +//! +//! \return None +// +//***************************************************************************** +void USCI_A_SPI_changeMasterClock(uint16_t baseAddress, + USCI_A_SPI_changeMasterClockParam *param) +{ + assert(param != 0); + + //Disable the USCI Module + HWREG8(baseAddress + OFS_UCAxCTL1) |= UCSWRST; + + HWREG8(baseAddress + OFS_UCAxBRW) = + (uint16_t)(param->clockSourceFrequency / param->desiredSpiClock); + + //Reset the UCSWRST bit to enable the USCI Module + HWREG8(baseAddress + OFS_UCAxCTL1) &= ~(UCSWRST); +} +//***************************************************************************** +// +//! \brief Initializes the SPI Slave block. +//! +//! Upon successful initialization of the SPI slave block, this function will +//! have initialized the slave block, but the SPI Slave block still remains +//! disabled and must be enabled with USCI_A_SPI_enable() +//! +//! \param baseAddress is the base address of the SPI Slave module. +//! \param msbFirst controls the direction of the receive and transmit shift +//! register. +//! Valid values are: +//! - \b USCI_A_SPI_MSB_FIRST +//! - \b USCI_A_SPI_LSB_FIRST [Default] +//! \param clockPhase is clock phase select. +//! Valid values are: +//! - \b USCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT +//! [Default] +//! - \b USCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT +//! \param clockPolarity +//! Valid values are: +//! - \b USCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH +//! - \b USCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default] +//! +//! Modified bits are \b UCMSB, \b UCMST, \b UC7BIT, \b UCCKPL, \b UCCKPH and +//! \b UCMODE of \b UCAxCTL0 register; bits \b UCSWRST of \b UCAxCTL1 register. +//! +//! \return STATUS_SUCCESS +// +//***************************************************************************** +bool USCI_A_SPI_slaveInit(uint16_t baseAddress, + uint8_t msbFirst, + uint8_t clockPhase, + uint8_t clockPolarity + ) +{ + assert( + (USCI_A_SPI_MSB_FIRST == msbFirst) || + (USCI_A_SPI_LSB_FIRST == msbFirst) + ); + + assert( + (USCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT == clockPhase) || + (USCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT == clockPhase) + ); + + assert( + (USCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == clockPolarity) || + (USCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW == clockPolarity) + ); + + //Disable USCI Module + HWREG8(baseAddress + OFS_UCAxCTL1) |= UCSWRST; + + //Reset OFS_UCAxCTL0 register + HWREG8(baseAddress + OFS_UCAxCTL0) &= ~(UCMSB + + UC7BIT + + UCMST + + UCCKPL + + UCCKPH + + UCMODE_3 + ); + + //Clock polarity, phase select, msbFirst, SYNC, Mode0 + HWREG8(baseAddress + OFS_UCAxCTL0) |= (clockPhase + + clockPolarity + + msbFirst + + UCSYNC + + UCMODE_0 + ); + + return STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! \brief Changes the SPI clock phase and polarity.At the end of this function +//! call, SPI module is left enabled. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param clockPhase is clock phase select. +//! Valid values are: +//! - \b USCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT +//! [Default] +//! - \b USCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT +//! \param clockPolarity +//! Valid values are: +//! - \b USCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH +//! - \b USCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default] +//! +//! Modified bits are \b UCCKPL and \b UCCKPH of \b UCAxCTL0 register. +//! +//! \return None +// +//***************************************************************************** +void USCI_A_SPI_changeClockPhasePolarity(uint16_t baseAddress, + uint8_t clockPhase, + uint8_t clockPolarity + ) +{ + + assert( (USCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == clockPolarity) || + (USCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW == clockPolarity) + ); + + //Disable the USCI Module + HWREG8(baseAddress + OFS_UCAxCTL1) |= UCSWRST; + + HWREG8(baseAddress + OFS_UCAxCTL0) &= ~(UCCKPH + UCCKPL); + + HWREG8(baseAddress + OFS_UCAxCTL0) |= ( + clockPhase + + clockPolarity + ); + + //Reset the UCSWRST bit to enable the USCI Module + HWREG8(baseAddress + OFS_UCAxCTL1) &= ~(UCSWRST); +} + +//***************************************************************************** +// +//! \brief Transmits a byte from the SPI Module. +//! +//! This function will place the supplied data into SPI transmit data register +//! to start transmission +//! +//! \param baseAddress is the base address of the SPI module. +//! \param transmitData data to be transmitted from the SPI module +//! +//! \return None +// +//***************************************************************************** +void USCI_A_SPI_transmitData( uint16_t baseAddress, + uint8_t transmitData + ) +{ + HWREG8(baseAddress + OFS_UCAxTXBUF) = transmitData; +} + +//***************************************************************************** +// +//! \brief Receives a byte that has been sent to the SPI Module. +//! +//! This function reads a byte of data from the SPI receive data Register. +//! +//! \param baseAddress is the base address of the SPI module. +//! +//! \return Returns the byte received from by the SPI module, cast as an +//! uint8_t. +// +//***************************************************************************** +uint8_t USCI_A_SPI_receiveData(uint16_t baseAddress) +{ + return HWREG8(baseAddress + OFS_UCAxRXBUF); +} + +//***************************************************************************** +// +//! \brief Enables individual SPI interrupt sources. +//! +//! Enables the indicated SPI interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. Does not clear interrupt flags. +//! +//! \param baseAddress is the base address of the SPI module. +//! \param mask is the bit mask of the interrupt sources to be enabled. +//! Mask value is the logical OR of any of the following: +//! - \b USCI_A_SPI_TRANSMIT_INTERRUPT +//! - \b USCI_A_SPI_RECEIVE_INTERRUPT +//! +//! Modified bits of \b UCAxIE register. +//! +//! \return None +// +//***************************************************************************** +void USCI_A_SPI_enableInterrupt(uint16_t baseAddress, + uint8_t mask + ) +{ + assert( 0x00 != mask && (USCI_A_SPI_RECEIVE_INTERRUPT + + USCI_A_SPI_TRANSMIT_INTERRUPT + )); + + HWREG8(baseAddress + OFS_UCAxIE) |= mask; +} + +//***************************************************************************** +// +//! \brief Disables individual SPI interrupt sources. +//! +//! Disables the indicated SPI interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! \param baseAddress is the base address of the SPI module. +//! \param mask is the bit mask of the interrupt sources to be disabled. +//! Mask value is the logical OR of any of the following: +//! - \b USCI_A_SPI_TRANSMIT_INTERRUPT +//! - \b USCI_A_SPI_RECEIVE_INTERRUPT +//! +//! Modified bits of \b UCAxIE register. +//! +//! \return None +// +//***************************************************************************** +void USCI_A_SPI_disableInterrupt(uint16_t baseAddress, + uint8_t mask + ) +{ + assert( 0x00 != mask && (USCI_A_SPI_RECEIVE_INTERRUPT + + USCI_A_SPI_TRANSMIT_INTERRUPT + )); + + HWREG8(baseAddress + OFS_UCAxIE) &= ~mask; +} + +//***************************************************************************** +// +//! \brief Gets the current SPI interrupt status. +//! +//! This returns the interrupt status for the SPI module based on which flag is +//! passed. +//! +//! \param baseAddress is the base address of the SPI module. +//! \param mask is the masked interrupt flag status to be returned. +//! Mask value is the logical OR of any of the following: +//! - \b USCI_A_SPI_TRANSMIT_INTERRUPT +//! - \b USCI_A_SPI_RECEIVE_INTERRUPT +//! +//! \return The current interrupt status as the mask of the set flags +//! Return Logical OR of any of the following: +//! - \b USCI_A_SPI_TRANSMIT_INTERRUPT +//! - \b USCI_A_SPI_RECEIVE_INTERRUPT +//! \n indicating the status of the masked interrupts +// +//***************************************************************************** +uint8_t USCI_A_SPI_getInterruptStatus(uint16_t baseAddress, + uint8_t mask + ) +{ + assert( 0x00 != mask && (USCI_A_SPI_RECEIVE_INTERRUPT + + USCI_A_SPI_TRANSMIT_INTERRUPT + )); + + return HWREG8(baseAddress + OFS_UCAxIFG) & mask; +} + +//***************************************************************************** +// +//! \brief Clears the selected SPI interrupt status flag. +//! +//! \param baseAddress is the base address of the SPI module. +//! \param mask is the masked interrupt flag to be cleared. +//! Mask value is the logical OR of any of the following: +//! - \b USCI_A_SPI_TRANSMIT_INTERRUPT +//! - \b USCI_A_SPI_RECEIVE_INTERRUPT +//! +//! Modified bits of \b UCAxIFG register. +//! +//! \return None +// +//***************************************************************************** +void USCI_A_SPI_clearInterruptFlag(uint16_t baseAddress, + uint8_t mask + ) +{ + assert( 0x00 != mask && (USCI_A_SPI_RECEIVE_INTERRUPT + + USCI_A_SPI_TRANSMIT_INTERRUPT + )); + + HWREG8(baseAddress + OFS_UCAxIFG) &= ~mask; +} + +//***************************************************************************** +// +//! \brief Enables the SPI block. +//! +//! This will enable operation of the SPI block. +//! +//! \param baseAddress is the base address of the USCI SPI module. +//! +//! Modified bits are \b UCSWRST of \b UCAxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void USCI_A_SPI_enable(uint16_t baseAddress) +{ + //Reset the UCSWRST bit to enable the USCI Module + HWREG8(baseAddress + OFS_UCAxCTL1) &= ~(UCSWRST); +} + +//***************************************************************************** +// +//! \brief Disables the SPI block. +//! +//! This will disable operation of the SPI block. +//! +//! \param baseAddress is the base address of the USCI SPI module. +//! +//! Modified bits are \b UCSWRST of \b UCAxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void USCI_A_SPI_disable(uint16_t baseAddress) +{ + //Set the UCSWRST bit to disable the USCI Module + HWREG8(baseAddress + OFS_UCAxCTL1) |= UCSWRST; +} + +//***************************************************************************** +// +//! \brief Returns the address of the RX Buffer of the SPI for the DMA module. +//! +//! Returns the address of the SPI RX Buffer. This can be used in conjunction +//! with the DMA to store the received data directly to memory. +//! +//! \param baseAddress is the base address of the SPI module. +//! +//! \return the address of the RX Buffer +// +//***************************************************************************** +uint32_t USCI_A_SPI_getReceiveBufferAddressForDMA(uint16_t baseAddress) +{ + return baseAddress + OFS_UCAxRXBUF; +} + +//***************************************************************************** +// +//! \brief Returns the address of the TX Buffer of the SPI for the DMA module. +//! +//! Returns the address of the SPI TX Buffer. This can be used in conjunction +//! with the DMA to obtain transmitted data directly from memory. +//! +//! \param baseAddress is the base address of the SPI module. +//! +//! \return the address of the TX Buffer +// +//***************************************************************************** +uint32_t USCI_A_SPI_getTransmitBufferAddressForDMA(uint16_t baseAddress) +{ + return baseAddress + OFS_UCAxTXBUF; +} + +//***************************************************************************** +// +//! \brief Indicates whether or not the SPI bus is busy. +//! +//! This function returns an indication of whether or not the SPI bus is +//! busy.This function checks the status of the bus via UCBBUSY bit +//! +//! \param baseAddress is the base address of the SPI module. +//! +//! \return USCI_A_SPI_BUSY if the SPI module transmitting or receiving is +//! busy; otherwise, returns USCI_A_SPI_NOT_BUSY. +//! Return one of the following: +//! - \b USCI_A_SPI_BUSY +//! - \b USCI_A_SPI_NOT_BUSY +//! \n indicating if the USCI_A_SPI is busy +// +//***************************************************************************** +uint8_t USCI_A_SPI_isBusy(uint16_t baseAddress) +{ + //Return the bus busy status. + return HWREG8(baseAddress + OFS_UCAxSTAT) & UCBUSY; +} + + +#endif +//***************************************************************************** +// +//! Close the doxygen group for usci_a_spi_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/usci_a_spi.h b/source/driverlib/MSP430F5xx_6xx/usci_a_spi.h new file mode 100644 index 0000000..ffe1d9f --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/usci_a_spi.h @@ -0,0 +1,212 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// usci_a_spi.h - Driver for the USCI_A_SPI Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_USCI_A_SPI_H__ +#define __MSP430WARE_USCI_A_SPI_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_USCI_Ax__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//****************************************************************************** +// +// The following is a struct that is passed to USCI_A_SPI_initMaster() +// +//****************************************************************************** +typedef struct USCI_A_SPI_initMasterParam { + uint8_t selectClockSource; + uint32_t clockSourceFrequency; + uint32_t desiredSpiClock; + uint8_t msbFirst; + uint8_t clockPhase; + uint8_t clockPolarity; +} USCI_A_SPI_initMasterParam; + +//****************************************************************************** +// +// The following is a struct that is passed to USCI_A_SPI_changeMasterParam() +// +//****************************************************************************** +typedef struct USCI_A_SPI_ChangeMasterClockParam { + uint32_t clockSourceFrequency; + uint32_t desiredSpiClock; +} USCI_A_SPI_changeMasterClockParam; + +//***************************************************************************** +// +// The following are values that can be passed to the clockPhase parameter for +// functions: USCI_A_SPI_masterInit(), USCI_A_SPI_slaveInit(), and +// USCI_A_SPI_changeClockPhasePolarity(). +// +//***************************************************************************** +#define USCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT 0x00 +#define USCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT UCCKPH + +//***************************************************************************** +// +// The following are values that can be passed to the msbFirst parameter for +// functions: USCI_A_SPI_masterInit(), and USCI_A_SPI_slaveInit(). +// +//***************************************************************************** +#define USCI_A_SPI_MSB_FIRST UCMSB +#define USCI_A_SPI_LSB_FIRST 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the clockPolarity parameter +// for functions: USCI_A_SPI_masterInit(), USCI_A_SPI_slaveInit(), and +// USCI_A_SPI_changeClockPhasePolarity(). +// +//***************************************************************************** +#define USCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH UCCKPL +#define USCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the selectClockSource +// parameter for functions: USCI_A_SPI_masterInit(). +// +//***************************************************************************** +#define USCI_A_SPI_CLOCKSOURCE_ACLK UCSSEL__ACLK +#define USCI_A_SPI_CLOCKSOURCE_SMCLK UCSSEL__SMCLK + +//***************************************************************************** +// +// The following are values that can be passed to the mask parameter for +// functions: USCI_A_SPI_enableInterrupt(), USCI_A_SPI_disableInterrupt(), +// USCI_A_SPI_getInterruptStatus(), and USCI_A_SPI_clearInterruptFlag() as well +// as returned by the USCI_A_SPI_getInterruptStatus() function. +// +//***************************************************************************** +#define USCI_A_SPI_TRANSMIT_INTERRUPT UCTXIE +#define USCI_A_SPI_RECEIVE_INTERRUPT UCRXIE + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the USCI_A_SPI_isBusy() function. +// +//***************************************************************************** +#define USCI_A_SPI_BUSY UCBUSY +#define USCI_A_SPI_NOT_BUSY 0x00 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern bool USCI_A_SPI_initMaster(uint16_t baseAddress, + USCI_A_SPI_initMasterParam *param); + +extern void USCI_A_SPI_changeMasterClock(uint16_t baseAddress, + USCI_A_SPI_changeMasterClockParam *param); + +extern bool USCI_A_SPI_slaveInit(uint16_t baseAddress, + uint8_t msbFirst, + uint8_t clockPhase, + uint8_t clockPolarity); + +extern void USCI_A_SPI_changeClockPhasePolarity(uint16_t baseAddress, + uint8_t clockPhase, + uint8_t clockPolarity); + +extern void USCI_A_SPI_transmitData(uint16_t baseAddress, + uint8_t transmitData); + +extern uint8_t USCI_A_SPI_receiveData(uint16_t baseAddress); + +extern void USCI_A_SPI_enableInterrupt(uint16_t baseAddress, + uint8_t mask); + +extern void USCI_A_SPI_disableInterrupt(uint16_t baseAddress, + uint8_t mask); + +extern uint8_t USCI_A_SPI_getInterruptStatus(uint16_t baseAddress, + uint8_t mask); + +extern void USCI_A_SPI_clearInterruptFlag(uint16_t baseAddress, + uint8_t mask); + +extern void USCI_A_SPI_enable(uint16_t baseAddress); + +extern void USCI_A_SPI_disable(uint16_t baseAddress); + +extern uint32_t USCI_A_SPI_getReceiveBufferAddressForDMA(uint16_t baseAddress); + +extern uint32_t USCI_A_SPI_getTransmitBufferAddressForDMA(uint16_t baseAddress); + +extern uint8_t USCI_A_SPI_isBusy(uint16_t baseAddress); + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +extern bool USCI_A_SPI_masterInit(uint16_t baseAddress, + uint8_t selectClockSource, + uint32_t clockSourceFrequency, + uint32_t desiredSpiClock, + uint8_t msbFirst, + uint8_t clockPhase, + uint8_t clockPolarity); + +extern void USCI_A_SPI_masterChangeClock(uint16_t baseAddress, + uint32_t clockSourceFrequency, + uint32_t desiredSpiClock); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_USCI_A_SPI_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/usci_a_uart.c b/source/driverlib/MSP430F5xx_6xx/usci_a_uart.c new file mode 100644 index 0000000..e4851b8 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/usci_a_uart.c @@ -0,0 +1,676 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// usci_a_uart.c - Driver for the usci_a_uart Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup usci_a_uart_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_USCI_Ax__ +#include "usci_a_uart.h" + +#include + +//***************************************************************************** +// +//! \brief DEPRECATED - Advanced initialization routine for the UART block. The +//! values to be written into the clockPrescalar, firstModReg, secondModReg and +//! overSampling parameters should be pre-computed and passed into the +//! initialization function. +//! +//! Upon successful initialization of the UART block, this function will have +//! initialized the module, but the UART block still remains disabled and must +//! be enabled with USCI_A_UART_enable(). To calculate values for +//! clockPrescalar, firstModReg, secondModReg and overSampling please use the +//! link below. +//! +//! http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSP430BaudRateConverter/index.html +//! +//! \param baseAddress is the base address of the USCI_A_UART module. +//! \param selectClockSource selects Clock source. +//! Valid values are: +//! - \b USCI_A_UART_CLOCKSOURCE_SMCLK +//! - \b USCI_A_UART_CLOCKSOURCE_ACLK +//! \param clockPrescalar is the value to be written into UCBRx bits +//! \param firstModReg is First modulation stage register setting. This value +//! is a pre-calculated value which can be obtained from the Device +//! Users Guide. This value is written into UCBRFx bits of UCAxMCTLW. +//! \param secondModReg is Second modulation stage register setting. This value +//! is a pre-calculated value which can be obtained from the Device +//! Users Guide. This value is written into UCBRSx bits of UCAxMCTLW. +//! \param parity is the desired parity. +//! Valid values are: +//! - \b USCI_A_UART_NO_PARITY [Default] +//! - \b USCI_A_UART_ODD_PARITY +//! - \b USCI_A_UART_EVEN_PARITY +//! \param msborLsbFirst controls direction of receive and transmit shift +//! register. +//! Valid values are: +//! - \b USCI_A_UART_MSB_FIRST +//! - \b USCI_A_UART_LSB_FIRST [Default] +//! \param numberofStopBits indicates one/two STOP bits +//! Valid values are: +//! - \b USCI_A_UART_ONE_STOP_BIT [Default] +//! - \b USCI_A_UART_TWO_STOP_BITS +//! \param uartMode selects the mode of operation +//! Valid values are: +//! - \b USCI_A_UART_MODE [Default] +//! - \b USCI_A_UART_IDLE_LINE_MULTI_PROCESSOR_MODE +//! - \b USCI_A_UART_ADDRESS_BIT_MULTI_PROCESSOR_MODE +//! - \b USCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE +//! \param overSampling indicates low frequency or oversampling baud generation +//! Valid values are: +//! - \b USCI_A_UART_OVERSAMPLING_BAUDRATE_GENERATION +//! - \b USCI_A_UART_LOW_FREQUENCY_BAUDRATE_GENERATION +//! +//! Modified bits are \b UCPEN, \b UCPAR, \b UCMSB, \b UC7BIT, \b UCSPB, \b +//! UCMODEx and \b UCSYNC of \b UCAxCTL0 register; bits \b UCSSELx and \b +//! UCSWRST of \b UCAxCTL1 register. +//! +//! \return STATUS_SUCCESS or STATUS_FAIL of the initialization process +// +//***************************************************************************** +bool USCI_A_UART_initAdvance( uint16_t baseAddress, + uint8_t selectClockSource, + uint16_t clockPrescalar, + uint8_t firstModReg, + uint8_t secondModReg, + uint8_t parity, + uint8_t msborLsbFirst, + uint8_t numberofStopBits, + uint8_t uartMode, + uint8_t overSampling + ) +{ + USCI_A_UART_initParam param = { 0 }; + + param.selectClockSource = selectClockSource; + param.clockPrescalar = clockPrescalar; + param.firstModReg = firstModReg; + param.secondModReg = secondModReg; + param.parity = parity; + param.msborLsbFirst = msborLsbFirst; + param.numberofStopBits = numberofStopBits; + param.uartMode = uartMode; + param.overSampling = overSampling; + + return USCI_A_UART_init(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Advanced initialization routine for the UART block. The values to be +//! written into the clockPrescalar, firstModReg, secondModReg and overSampling +//! parameters should be pre-computed and passed into the initialization +//! function. +//! +//! Upon successful initialization of the UART block, this function will have +//! initialized the module, but the UART block still remains disabled and must +//! be enabled with USCI_A_UART_enable(). To calculate values for +//! clockPrescalar, firstModReg, secondModReg and overSampling please use the +//! link below. +//! +//! http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSP430BaudRateConverter/index.html +//! +//! \param baseAddress is the base address of the USCI_A_UART module. +//! \param param is the pointer to struct for initialization. +//! +//! Modified bits are \b UCPEN, \b UCPAR, \b UCMSB, \b UC7BIT, \b UCSPB, \b +//! UCMODEx and \b UCSYNC of \b UCAxCTL0 register; bits \b UCSSELx and \b +//! UCSWRST of \b UCAxCTL1 register. +//! +//! \return STATUS_SUCCESS or STATUS_FAIL of the initialization process +// +//***************************************************************************** +bool USCI_A_UART_init(uint16_t baseAddress, USCI_A_UART_initParam *param) +{ + assert(param != 0); + + assert( + (USCI_A_UART_MODE == param->uartMode) || + (USCI_A_UART_IDLE_LINE_MULTI_PROCESSOR_MODE == param->uartMode) || + (USCI_A_UART_ADDRESS_BIT_MULTI_PROCESSOR_MODE == param->uartMode) || + (USCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE == param->uartMode) + ); + + assert( + (USCI_A_UART_CLOCKSOURCE_ACLK == param->selectClockSource) || + (USCI_A_UART_CLOCKSOURCE_SMCLK == param->selectClockSource) + ); + + assert( + (USCI_A_UART_MSB_FIRST == param->msborLsbFirst) || + (USCI_A_UART_LSB_FIRST == param->msborLsbFirst) + ); + + assert( + (USCI_A_UART_ONE_STOP_BIT == param->numberofStopBits) || + (USCI_A_UART_TWO_STOP_BITS == param->numberofStopBits) + ); + + assert( + (USCI_A_UART_NO_PARITY == param->parity) || + (USCI_A_UART_ODD_PARITY == param->parity) || + (USCI_A_UART_EVEN_PARITY == param->parity) + ); + + bool retVal = STATUS_SUCCESS; + + //Disable the USCI Module + HWREG8(baseAddress + OFS_UCAxCTL1) |= UCSWRST; + + //Clock source select + HWREG8(baseAddress + OFS_UCAxCTL1) &= ~UCSSEL_3; + HWREG8(baseAddress + OFS_UCAxCTL1) |= param->selectClockSource; + + //MSB, LSB select + HWREG8(baseAddress + OFS_UCAxCTL0) &= ~UCMSB; + HWREG8(baseAddress + OFS_UCAxCTL0) |= param->msborLsbFirst; + + //UCSPB = 0(1 stop bit) OR 1(2 stop bits) + HWREG8(baseAddress + OFS_UCAxCTL0) &= ~UCSPB; + HWREG8(baseAddress + OFS_UCAxCTL0) |= param->numberofStopBits; + + //Parity + switch (param->parity) { + case USCI_A_UART_NO_PARITY: + //No Parity + HWREG8(baseAddress + OFS_UCAxCTL0) &= ~UCPEN; + break; + case USCI_A_UART_ODD_PARITY: + //Odd Parity + HWREG8(baseAddress + OFS_UCAxCTL0) |= UCPEN; + HWREG8(baseAddress + OFS_UCAxCTL0) &= ~UCPAR; + break; + case USCI_A_UART_EVEN_PARITY: + //Even Parity + HWREG8(baseAddress + OFS_UCAxCTL0) |= UCPEN; + HWREG8(baseAddress + OFS_UCAxCTL0) |= UCPAR; + break; + } + + //Modulation Control Registers + HWREG16(baseAddress + OFS_UCAxBRW ) = param->clockPrescalar; + HWREG8(baseAddress + OFS_UCAxMCTL) = ((param->firstModReg << 4) + + (param->secondModReg << 1) + + param->overSampling ); + + //Asynchronous mode & 8 bit character select & clear mode + HWREG8(baseAddress + OFS_UCAxCTL0) &= ~(UCSYNC + + UC7BIT + + UCMODE_3 + ); + + //Configure UART mode. + HWREG8(baseAddress + OFS_UCAxCTL0) |= param->uartMode; + + //Reset UCRXIE, UCBRKIE, UCDORM, UCTXADDR, UCTXBRK + HWREG8(baseAddress + OFS_UCAxCTL1) &= ~(UCRXEIE + UCBRKIE + UCDORM + + UCTXADDR + UCTXBRK + ); + + return retVal; +} //***************************************************************************** +// +//! \brief Transmits a byte from the UART Module. +//! +//! This function will place the supplied data into UART transmit data register +//! to start transmission +//! +//! \param baseAddress is the base address of the USCI_A_UART module. +//! \param transmitData data to be transmitted from the UART module +//! +//! Modified bits of \b UCAxTXBUF register. +//! +//! \return None +// +//***************************************************************************** +void USCI_A_UART_transmitData( uint16_t baseAddress, + uint8_t transmitData + ) +{ + //If interrupts are not used, poll for flags + if (!(HWREG8(baseAddress + OFS_UCAxIE) & UCTXIE)) + //Poll for transmit interrupt flag + while (!(HWREG8(baseAddress + OFS_UCAxIFG) & UCTXIFG)) ; + + HWREG8(baseAddress + OFS_UCAxTXBUF) = transmitData; +} + +//***************************************************************************** +// +//! \brief Receives a byte that has been sent to the UART Module. +//! +//! This function reads a byte of data from the UART receive data Register. +//! +//! \param baseAddress is the base address of the USCI_A_UART module. +//! +//! Modified bits of \b UCAxRXBUF register. +//! +//! \return Returns the byte received from by the UART module, cast as an +//! uint8_t. +// +//***************************************************************************** +uint8_t USCI_A_UART_receiveData(uint16_t baseAddress) +{ + //If interrupts are not used, poll for flags + if (!(HWREG8(baseAddress + OFS_UCAxIE) & UCRXIE)) + //Poll for receive interrupt flag + while (!(HWREG8(baseAddress + OFS_UCAxIFG) & UCRXIFG)) ; + + return HWREG8(baseAddress + OFS_UCAxRXBUF); +} + +//***************************************************************************** +// +//! \brief Enables individual UART interrupt sources. +//! +//! Enables the indicated UART interrupt sources. The interrupt flag is first +//! and then the corresponding interrupt is enabled. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. Does not clear interrupt flags. +//! +//! \param baseAddress is the base address of the USCI_A_UART module. +//! \param mask is the bit mask of the interrupt sources to be enabled. +//! Mask value is the logical OR of any of the following: +//! - \b USCI_A_UART_RECEIVE_INTERRUPT - Receive interrupt +//! - \b USCI_A_UART_TRANSMIT_INTERRUPT - Transmit interrupt +//! - \b USCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT - Receive +//! erroneous-character interrupt enable +//! - \b USCI_A_UART_BREAKCHAR_INTERRUPT - Receive break character +//! interrupt enable +//! +//! Modified bits of \b UCAxCTL1 register and bits of \b UCAxIE register. +//! +//! \return None +// +//***************************************************************************** +void USCI_A_UART_enableInterrupt(uint16_t baseAddress, + uint8_t mask + ) +{ + assert(!(mask & ~(USCI_A_UART_RECEIVE_INTERRUPT + | USCI_A_UART_TRANSMIT_INTERRUPT + | USCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT + | USCI_A_UART_BREAKCHAR_INTERRUPT))); + + uint8_t locMask; + + locMask = (mask & (USCI_A_UART_RECEIVE_INTERRUPT + | USCI_A_UART_TRANSMIT_INTERRUPT)); + HWREG8(baseAddress + OFS_UCAxIE) |= locMask; + + locMask = (mask & (USCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT + | USCI_A_UART_BREAKCHAR_INTERRUPT)); + HWREG8(baseAddress + OFS_UCAxCTL1) |= locMask; +} + +//***************************************************************************** +// +//! \brief Disables individual UART interrupt sources. +//! +//! Disables the indicated UART interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! \param baseAddress is the base address of the USCI_A_UART module. +//! \param mask is the bit mask of the interrupt sources to be disabled. +//! Mask value is the logical OR of any of the following: +//! - \b USCI_A_UART_RECEIVE_INTERRUPT - Receive interrupt +//! - \b USCI_A_UART_TRANSMIT_INTERRUPT - Transmit interrupt +//! - \b USCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT - Receive +//! erroneous-character interrupt enable +//! - \b USCI_A_UART_BREAKCHAR_INTERRUPT - Receive break character +//! interrupt enable +//! +//! Modified bits of \b UCAxCTL1 register and bits of \b UCAxIE register. +//! +//! \return None +// +//***************************************************************************** +void USCI_A_UART_disableInterrupt(uint16_t baseAddress, + uint8_t mask + ) +{ + assert(!(mask & ~(USCI_A_UART_RECEIVE_INTERRUPT + | USCI_A_UART_TRANSMIT_INTERRUPT + | USCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT + | USCI_A_UART_BREAKCHAR_INTERRUPT))); + + uint8_t locMask; + + if (locMask = (mask & (USCI_A_UART_RECEIVE_INTERRUPT + | USCI_A_UART_TRANSMIT_INTERRUPT))) + HWREG8(baseAddress + OFS_UCAxIE) &= ~locMask; + + if (locMask = (mask & (USCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT + | USCI_A_UART_BREAKCHAR_INTERRUPT))) + HWREG8(baseAddress + OFS_UCAxCTL1) &= ~locMask; +} + +//***************************************************************************** +// +//! \brief Gets the current UART interrupt status. +//! +//! This returns the interrupt status for the UART module based on which flag +//! is passed. +//! +//! \param baseAddress is the base address of the USCI_A_UART module. +//! \param mask is the masked interrupt flag status to be returned. +//! Mask value is the logical OR of any of the following: +//! - \b USCI_A_UART_RECEIVE_INTERRUPT_FLAG - Receive interrupt flag +//! - \b USCI_A_UART_TRANSMIT_INTERRUPT_FLAG - Transmit interrupt flag +//! +//! Modified bits of \b UCAxIFG register. +//! +//! \return Logical OR of any of the following: +//! - \b USCI_A_UART_RECEIVE_INTERRUPT_FLAG Receive interrupt flag +//! - \b USCI_A_UART_TRANSMIT_INTERRUPT_FLAG Transmit interrupt flag +//! \n indicating the status of the masked flags +// +//***************************************************************************** +uint8_t USCI_A_UART_getInterruptStatus(uint16_t baseAddress, + uint8_t mask) +{ + assert(!(mask & ~(USCI_A_UART_RECEIVE_INTERRUPT_FLAG + | USCI_A_UART_TRANSMIT_INTERRUPT_FLAG))); + + return HWREG8(baseAddress + OFS_UCAxIFG) & mask; +} + +//***************************************************************************** +// +//! \brief Clears UART interrupt sources. +//! +//! The UART interrupt source is cleared, so that it no longer asserts. The +//! highest interrupt flag is automatically cleared when an interrupt vector +//! generator is used. +//! +//! \param baseAddress is the base address of the USCI_A_UART module. +//! \param mask is a bit mask of the interrupt sources to be cleared. +//! Mask value is the logical OR of any of the following: +//! - \b USCI_A_UART_RECEIVE_INTERRUPT_FLAG - Receive interrupt flag +//! - \b USCI_A_UART_TRANSMIT_INTERRUPT_FLAG - Transmit interrupt flag +//! +//! Modified bits of \b UCAxIFG register. +//! +//! \return None +// +//***************************************************************************** +void USCI_A_UART_clearInterruptFlag(uint16_t baseAddress, uint8_t mask) +{ + assert(!(mask & ~(USCI_A_UART_RECEIVE_INTERRUPT_FLAG + | USCI_A_UART_TRANSMIT_INTERRUPT_FLAG))); + + //Clear the UART interrupt source. + HWREG8(baseAddress + OFS_UCAxIFG) &= ~(mask); +} + +//***************************************************************************** +// +//! \brief Enables the UART block. +//! +//! This will enable operation of the UART block. +//! +//! \param baseAddress is the base address of the USCI_A_UART module. +//! +//! Modified bits are \b UCSWRST of \b UCAxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void USCI_A_UART_enable(uint16_t baseAddress) +{ + //Reset the UCSWRST bit to enable the USCI Module + HWREG8(baseAddress + OFS_UCAxCTL1) &= ~(UCSWRST); +} + +//***************************************************************************** +// +//! \brief Disables the UART block. +//! +//! This will disable operation of the UART block. +//! +//! \param baseAddress is the base address of the USCI_A_UART module. +//! +//! Modified bits are \b UCSWRST of \b UCAxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void USCI_A_UART_disable(uint16_t baseAddress) +{ + //Set the UCSWRST bit to disable the USCI Module + HWREG8(baseAddress + OFS_UCAxCTL1) |= UCSWRST; +} + +//***************************************************************************** +// +//! \brief Gets the current UART status flags. +//! +//! This returns the status for the UART module based on which flag is passed. +//! +//! \param baseAddress is the base address of the USCI_A_UART module. +//! \param mask is the masked interrupt flag status to be returned. +//! Mask value is the logical OR of any of the following: +//! - \b USCI_A_UART_LISTEN_ENABLE +//! - \b USCI_A_UART_FRAMING_ERROR +//! - \b USCI_A_UART_OVERRUN_ERROR +//! - \b USCI_A_UART_PARITY_ERROR +//! - \b USCI_A_UART_BREAK_DETECT +//! - \b USCI_A_UART_RECEIVE_ERROR +//! - \b USCI_A_UART_ADDRESS_RECEIVED +//! - \b USCI_A_UART_IDLELINE +//! - \b USCI_A_UART_BUSY +//! +//! Modified bits of \b UCAxSTAT register. +//! +//! \return Logical OR of any of the following: +//! - \b USCI_A_UART_LISTEN_ENABLE +//! - \b USCI_A_UART_FRAMING_ERROR +//! - \b USCI_A_UART_OVERRUN_ERROR +//! - \b USCI_A_UART_PARITY_ERROR +//! - \b USCI_A_UART_BREAK_DETECT +//! - \b USCI_A_UART_RECEIVE_ERROR +//! - \b USCI_A_UART_ADDRESS_RECEIVED +//! - \b USCI_A_UART_IDLELINE +//! - \b USCI_A_UART_BUSY +//! \n indicating the status of the masked interrupt flags +// +//***************************************************************************** +uint8_t USCI_A_UART_queryStatusFlags(uint16_t baseAddress, + uint8_t mask) +{ + assert(0x00 != mask && (USCI_A_UART_LISTEN_ENABLE + + USCI_A_UART_FRAMING_ERROR + + USCI_A_UART_OVERRUN_ERROR + + USCI_A_UART_PARITY_ERROR + + USCI_A_UART_BREAK_DETECT + + USCI_A_UART_RECEIVE_ERROR + + USCI_A_UART_ADDRESS_RECEIVED + + USCI_A_UART_IDLELINE + + USCI_A_UART_BUSY + )); + + return HWREG8(baseAddress + OFS_UCAxSTAT) & mask; +} + +//***************************************************************************** +// +//! \brief Sets the UART module in dormant mode +//! +//! Puts USCI in sleep mode. Only characters that are preceded by an idle-line +//! or with address bit set UCRXIFG. In UART mode with automatic baud-rate +//! detection, only the combination of a break and sync field sets UCRXIFG. +//! +//! \param baseAddress is the base address of the USCI_A_UART module. +//! +//! Modified bits of \b UCAxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void USCI_A_UART_setDormant(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_UCAxCTL1) |= UCDORM; +} + +//***************************************************************************** +// +//! \brief Re-enables UART module from dormant mode +//! +//! Not dormant. All received characters set UCRXIFG. +//! +//! \param baseAddress is the base address of the USCI_A_UART module. +//! +//! Modified bits are \b UCDORM of \b UCAxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void USCI_A_UART_resetDormant(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_UCAxCTL1) &= ~UCDORM; +} + +//***************************************************************************** +// +//! \brief Transmits the next byte to be transmitted marked as address +//! depending on selected multiprocessor mode +//! +//! \param baseAddress is the base address of the USCI_A_UART module. +//! \param transmitAddress is the next byte to be transmitted +//! +//! Modified bits of \b UCAxTXBUF register and bits of \b UCAxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void USCI_A_UART_transmitAddress(uint16_t baseAddress, + uint8_t transmitAddress) +{ + //Set UCTXADDR bit + HWREG8(baseAddress + OFS_UCAxCTL1) |= UCTXADDR; + + //Place next byte to be sent into the transmit buffer + HWREG8(baseAddress + OFS_UCAxTXBUF) = transmitAddress; +} + +//***************************************************************************** +// +//! \brief Transmit break. +//! +//! Transmits a break with the next write to the transmit buffer. In UART mode +//! with automatic baud-rate detection, +//! USCI_A_UART_AUTOMATICBAUDRATE_SYNC(0x55) must be written into UCAxTXBUF to +//! generate the required break/sync fields. Otherwise, DEFAULT_SYNC(0x00) must +//! be written into the transmit buffer. Also ensures module is ready for +//! transmitting the next data. +//! +//! \param baseAddress is the base address of the USCI_A_UART module. +//! +//! Modified bits of \b UCAxTXBUF register and bits of \b UCAxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void USCI_A_UART_transmitBreak(uint16_t baseAddress) +{ + //Set UCTXADDR bit + HWREG8(baseAddress + OFS_UCAxCTL1) |= UCTXBRK; + + //If current mode is automatic baud-rate detection + if (USCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE == + (HWREG8(baseAddress + OFS_UCAxCTL0) & + USCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE)) + HWREG8(baseAddress + OFS_UCAxTXBUF) = USCI_A_UART_AUTOMATICBAUDRATE_SYNC; + else + HWREG8(baseAddress + OFS_UCAxTXBUF) = DEFAULT_SYNC; + + //If interrupts are not used, poll for flags + if (!(HWREG8(baseAddress + OFS_UCAxIE) & UCTXIE)) + //Poll for transmit interrupt flag + while (!(HWREG8(baseAddress + OFS_UCAxIFG) & UCTXIFG)) ; +} + +//***************************************************************************** +// +//! \brief Returns the address of the RX Buffer of the UART for the DMA module. +//! +//! Returns the address of the UART RX Buffer. This can be used in conjunction +//! with the DMA to store the received data directly to memory. +//! +//! \param baseAddress is the base address of the USCI_A_UART module. +//! +//! \return Address of RX Buffer +// +//***************************************************************************** +uint32_t USCI_A_UART_getReceiveBufferAddressForDMA(uint16_t baseAddress) +{ + return baseAddress + OFS_UCAxRXBUF; +} + +//***************************************************************************** +// +//! \brief Returns the address of the TX Buffer of the UART for the DMA module. +//! +//! Returns the address of the UART TX Buffer. This can be used in conjunction +//! with the DMA to obtain transmitted data directly from memory. +//! +//! \param baseAddress is the base address of the USCI_A_UART module. +//! +//! \return Address of TX Buffer +// +//***************************************************************************** +uint32_t USCI_A_UART_getTransmitBufferAddressForDMA(uint16_t baseAddress) +{ + return baseAddress + OFS_UCAxTXBUF; +} + + +#endif +//***************************************************************************** +// +//! Close the doxygen group for usci_a_uart_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/usci_a_uart.h b/source/driverlib/MSP430F5xx_6xx/usci_a_uart.h new file mode 100644 index 0000000..0b600f9 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/usci_a_uart.h @@ -0,0 +1,256 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// usci_a_uart.h - Driver for the USCI_A_UART Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_USCI_A_UART_H__ +#define __MSP430WARE_USCI_A_UART_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_USCI_Ax__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//****************************************************************************** +// +// The following is a struct that is passed to USCI_A_UART_init() +// +//****************************************************************************** +typedef struct USCI_A_UART_InitParam { + uint8_t selectClockSource; + uint16_t clockPrescalar; + uint8_t firstModReg; + uint8_t secondModReg; + uint8_t parity; + uint8_t msborLsbFirst; + uint8_t numberofStopBits; + uint8_t uartMode; + uint8_t overSampling; +} USCI_A_UART_initParam; + +//***************************************************************************** +// +// The following values are the sync characters possible +// +//***************************************************************************** +#define DEFAULT_SYNC 0x00 +#define USCI_A_UART_AUTOMATICBAUDRATE_SYNC 0x55 + +//***************************************************************************** +// +// The following are values that can be passed to the parity parameter for +// functions: USCI_A_UART_initAdvance(). +// +//***************************************************************************** +#define USCI_A_UART_NO_PARITY 0x00 +#define USCI_A_UART_ODD_PARITY 0x01 +#define USCI_A_UART_EVEN_PARITY 0x02 + +//***************************************************************************** +// +// The following are values that can be passed to the msborLsbFirst parameter +// for functions: USCI_A_UART_initAdvance(). +// +//***************************************************************************** +#define USCI_A_UART_MSB_FIRST UCMSB +#define USCI_A_UART_LSB_FIRST 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the uartMode parameter for +// functions: USCI_A_UART_initAdvance(). +// +//***************************************************************************** +#define USCI_A_UART_MODE UCMODE_0 +#define USCI_A_UART_IDLE_LINE_MULTI_PROCESSOR_MODE UCMODE_1 +#define USCI_A_UART_ADDRESS_BIT_MULTI_PROCESSOR_MODE UCMODE_2 +#define USCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE UCMODE_3 + +//***************************************************************************** +// +// The following are values that can be passed to the selectClockSource +// parameter for functions: USCI_A_UART_initAdvance(). +// +//***************************************************************************** +#define USCI_A_UART_CLOCKSOURCE_SMCLK UCSSEL__SMCLK +#define USCI_A_UART_CLOCKSOURCE_ACLK UCSSEL__ACLK + +//***************************************************************************** +// +// The following are values that can be passed to the numberofStopBits +// parameter for functions: USCI_A_UART_initAdvance(). +// +//***************************************************************************** +#define USCI_A_UART_ONE_STOP_BIT 0x00 +#define USCI_A_UART_TWO_STOP_BITS UCSPB + +//***************************************************************************** +// +// The following are values that can be passed to the overSampling parameter +// for functions: USCI_A_UART_initAdvance(). +// +//***************************************************************************** +#define USCI_A_UART_OVERSAMPLING_BAUDRATE_GENERATION 0x01 +#define USCI_A_UART_LOW_FREQUENCY_BAUDRATE_GENERATION 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the mask parameter for +// functions: USCI_A_UART_enableInterrupt(), and +// USCI_A_UART_disableInterrupt(). +// +//***************************************************************************** +#define USCI_A_UART_RECEIVE_INTERRUPT UCRXIE +#define USCI_A_UART_TRANSMIT_INTERRUPT UCTXIE +#define USCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT UCRXEIE +#define USCI_A_UART_BREAKCHAR_INTERRUPT UCBRKIE + +//***************************************************************************** +// +// The following are values that can be passed to the mask parameter for +// functions: USCI_A_UART_getInterruptStatus(), and +// USCI_A_UART_clearInterruptFlag() as well as returned by the +// USCI_A_UART_getInterruptStatus() function. +// +//***************************************************************************** +#define USCI_A_UART_RECEIVE_INTERRUPT_FLAG UCRXIFG +#define USCI_A_UART_TRANSMIT_INTERRUPT_FLAG UCTXIFG + +//***************************************************************************** +// +// The following are values that can be passed to the mask parameter for +// functions: USCI_A_UART_queryStatusFlags() as well as returned by the +// USCI_A_UART_queryStatusFlags() function. +// +//***************************************************************************** +#define USCI_A_UART_LISTEN_ENABLE UCLISTEN +#define USCI_A_UART_FRAMING_ERROR UCFE +#define USCI_A_UART_OVERRUN_ERROR UCOE +#define USCI_A_UART_PARITY_ERROR UCPE +#define USCI_A_UART_BREAK_DETECT UCBRK +#define USCI_A_UART_RECEIVE_ERROR UCRXERR +#define USCI_A_UART_ADDRESS_RECEIVED UCADDR +#define USCI_A_UART_IDLELINE UCIDLE +#define USCI_A_UART_BUSY UCBUSY + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern bool USCI_A_UART_init(uint16_t baseAddress, + USCI_A_UART_initParam *param); + +extern void USCI_A_UART_transmitData(uint16_t baseAddress, + uint8_t transmitData); + +extern uint8_t USCI_A_UART_receiveData(uint16_t baseAddress); + +extern void USCI_A_UART_enableInterrupt(uint16_t baseAddress, + uint8_t mask); + +extern void USCI_A_UART_disableInterrupt(uint16_t baseAddress, + uint8_t mask); + +extern uint8_t USCI_A_UART_getInterruptStatus(uint16_t baseAddress, + uint8_t mask); + +extern void USCI_A_UART_clearInterruptFlag(uint16_t baseAddress, + uint8_t mask); + +extern void USCI_A_UART_enable(uint16_t baseAddress); + +extern void USCI_A_UART_disable(uint16_t baseAddress); + +extern uint8_t USCI_A_UART_queryStatusFlags(uint16_t baseAddress, + uint8_t mask); + +extern void USCI_A_UART_setDormant(uint16_t baseAddress); + +extern void USCI_A_UART_resetDormant(uint16_t baseAddress); + +extern void USCI_A_UART_transmitAddress(uint16_t baseAddress, + uint8_t transmitAddress); + +extern void USCI_A_UART_transmitBreak(uint16_t baseAddress); + +extern uint32_t USCI_A_UART_getReceiveBufferAddressForDMA(uint16_t baseAddress); + +extern uint32_t USCI_A_UART_getTransmitBufferAddressForDMA(uint16_t baseAddress); + +//***************************************************************************** +// +// DEPRECATED +// +//***************************************************************************** +#define UARTBREAK_DETECT UCBRK + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +extern bool USCI_A_UART_initAdvance(uint16_t baseAddress, + uint8_t selectClockSource, + uint16_t clockPrescalar, + uint8_t firstModReg, + uint8_t secondModReg, + uint8_t parity, + uint8_t msborLsbFirst, + uint8_t numberofStopBits, + uint8_t uartMode, + uint8_t overSampling); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_USCI_A_UART_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/usci_b_i2c.c b/source/driverlib/MSP430F5xx_6xx/usci_b_i2c.c new file mode 100644 index 0000000..d765c20 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/usci_b_i2c.c @@ -0,0 +1,1329 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// usci_b_i2c.c - Driver for the usci_b_i2c Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup usci_b_i2c_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_USCI_Bx__ +#include "usci_b_i2c.h" + +#include + +//***************************************************************************** +// +//! \brief DEPRECATED - Initializes the I2C Master block. +//! +//! This function initializes operation of the I2C Master block. Upon +//! successful initialization of the I2C block, this function will have set the +//! bus speed for the master; however I2C module is still disabled till +//! USCI_B_I2C_enable is invoked. If the parameter \e dataRate is +//! USCI_B_I2C_SET_DATA_RATE_400KBPS, then the master block will be set up to +//! transfer data at 400 kbps; otherwise, it will be set up to transfer data at +//! 100 kbps. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param selectClockSource is the clocksource. +//! Valid values are: +//! - \b USCI_B_I2C_CLOCKSOURCE_ACLK +//! - \b USCI_B_I2C_CLOCKSOURCE_SMCLK +//! \param i2cClk is the rate of the clock supplied to the I2C module. +//! \param dataRate set up for selecting data transfer rate. +//! Valid values are: +//! - \b USCI_B_I2C_SET_DATA_RATE_400KBPS +//! - \b USCI_B_I2C_SET_DATA_RATE_100KBPS +//! +//! Modified bits are \b UCBxBR0 of \b UCBxBR1 register; bits \b UCSSELx and \b +//! UCSWRST of \b UCBxCTL1 register; bits \b UCMST, \b UCMODE_3 and \b UCSYNC +//! of \b UCBxCTL0 register. +//! +//! \return None +// +//***************************************************************************** +void USCI_B_I2C_masterInit(uint16_t baseAddress, + uint8_t selectClockSource, + uint32_t i2cClk, + uint32_t dataRate) +{ + USCI_B_I2C_initMasterParam param = { 0 }; + + param.selectClockSource = selectClockSource; + param.i2cClk = i2cClk; + param.dataRate = dataRate; + + USCI_B_I2C_initMaster(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Initializes the I2C Master block. +//! +//! This function initializes operation of the I2C Master block. Upon +//! successful initialization of the I2C block, this function will have set the +//! bus speed for the master; however I2C module is still disabled till +//! USCI_B_I2C_enable is invoked. If the parameter \e dataRate is +//! USCI_B_I2C_SET_DATA_RATE_400KBPS, then the master block will be set up to +//! transfer data at 400 kbps; otherwise, it will be set up to transfer data at +//! 100 kbps. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param param is the pointe to struct for master initialization. +//! +//! Modified bits are \b UCBxBR0 of \b UCBxBR1 register; bits \b UCSSELx and \b +//! UCSWRST of \b UCBxCTL1 register; bits \b UCMST, \b UCMODE_3 and \b UCSYNC +//! of \b UCBxCTL0 register. +//! +//! \return None +// +//***************************************************************************** +void USCI_B_I2C_initMaster(uint16_t baseAddress, USCI_B_I2C_initMasterParam *param) +{ + uint16_t preScalarValue; + + assert(param != 0); + + assert((USCI_B_I2C_CLOCKSOURCE_ACLK == param->selectClockSource) || + (USCI_B_I2C_CLOCKSOURCE_SMCLK == param->selectClockSource) + ); + + assert((USCI_B_I2C_SET_DATA_RATE_400KBPS == param->dataRate) || + (USCI_B_I2C_SET_DATA_RATE_100KBPS == param->dataRate) + ); + + //Disable the USCI module and clears the other bits of control register + HWREG8(baseAddress + OFS_UCBxCTL1) = UCSWRST; + + /* + * Configure as I2C master mode. + * UCMST = Master mode + * UCMODE_3 = I2C mode + * UCSYNC = Synchronous mode + */ + HWREG8(baseAddress + OFS_UCBxCTL0) = UCMST + UCMODE_3 + UCSYNC; + + //Configure I2C clock source + HWREG8(baseAddress + OFS_UCBxCTL1) = (param->selectClockSource + UCSWRST ); + + /* + * Compute the clock divider that achieves the fastest speed less than or + * equal to the desired speed. The numerator is biased to favor a larger + * clock divider so that the resulting clock is always less than or equal + * to the desired clock, never greater. + */ + preScalarValue = (unsigned short)(param->i2cClk / param->dataRate); + HWREG16(baseAddress + OFS_UCBxBRW) = preScalarValue; +} //***************************************************************************** +// +//! \brief Initializes the I2C Slave block. +//! +//! This function initializes operation of the I2C as a Slave mode. Upon +//! successful initialization of the I2C blocks, this function will have set +//! the slave address but the I2C module is still disabled till +//! USCI_B_I2C_enable is invoked. +//! +//! \param baseAddress is the base address of the I2C Slave module. +//! \param slaveAddress 7-bit slave address +//! +//! Modified bits of \b UCBxI2COA register; bits \b UCSWRST of \b UCBxCTL1 +//! register; bits \b UCMODE_3 and \b UCSYNC of \b UCBxCTL0 register. +//! +//! \return None +// +//***************************************************************************** +void USCI_B_I2C_slaveInit(uint16_t baseAddress, + uint8_t slaveAddress + ) +{ + //Disable the USCI module + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCSWRST; + + //Clear USCI master mode + HWREG8(baseAddress + OFS_UCBxCTL0) &= ~UCMST; + + //Confiugre I2C as Slave and Synchronous mode + HWREG8(baseAddress + OFS_UCBxCTL0) = UCMODE_3 + UCSYNC; + + //Set up the slave address. + HWREG16(baseAddress + OFS_UCBxI2COA) = slaveAddress; +} + +//***************************************************************************** +// +//! \brief Enables the I2C block. +//! +//! This will enable operation of the I2C block. +//! +//! \param baseAddress is the base address of the USCI I2C module. +//! +//! Modified bits are \b UCSWRST of \b UCBxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void USCI_B_I2C_enable(uint16_t baseAddress) +{ + //Reset the UCSWRST bit to enable the USCI Module + HWREG8(baseAddress + OFS_UCBxCTL1) &= ~(UCSWRST); +} + +//***************************************************************************** +// +//! \brief Disables the I2C block. +//! +//! This will disable operation of the I2C block. +//! +//! \param baseAddress is the base address of the USCI I2C module. +//! +//! Modified bits are \b UCSWRST of \b UCBxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void USCI_B_I2C_disable(uint16_t baseAddress) +{ + //Set the UCSWRST bit to disable the USCI Module + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCSWRST; +} + +//***************************************************************************** +// +//! \brief Sets the address that the I2C Master will place on the bus. +//! +//! This function will set the address that the I2C Master will place on the +//! bus when initiating a transaction. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param slaveAddress 7-bit slave address +//! +//! Modified bits of \b UCBxI2CSA register; bits \b UCSWRST of \b UCBxCTL1 +//! register. +//! +//! \return None +// +//***************************************************************************** +void USCI_B_I2C_setSlaveAddress(uint16_t baseAddress, + uint8_t slaveAddress + ) +{ + //Set the address of the slave with which the master will communicate. + HWREG16(baseAddress + OFS_UCBxI2CSA) = (slaveAddress); +} + +//***************************************************************************** +// +//! \brief Sets the mode of the I2C device +//! +//! When the receive parameter is set to USCI_B_I2C_TRANSMIT_MODE, the address +//! will indicate that the I2C module is in receive mode; otherwise, the I2C +//! module is in send mode. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param mode indicates whether module is in transmit/receive mode +//! Valid values are: +//! - \b USCI_B_I2C_TRANSMIT_MODE +//! - \b USCI_B_I2C_RECEIVE_MODE [Default] +//! +//! \return None +// +//***************************************************************************** +void USCI_B_I2C_setMode(uint16_t baseAddress, + uint8_t mode + ) +{ + assert((USCI_B_I2C_TRANSMIT_MODE == mode) || + (USCI_B_I2C_RECEIVE_MODE == mode) + ); + + HWREG8(baseAddress + OFS_UCBxCTL1) &= ~USCI_B_I2C_TRANSMIT_MODE; + HWREG8(baseAddress + OFS_UCBxCTL1) |= mode; +} + +//***************************************************************************** +// +//! \brief Transmits a byte from the I2C Module. +//! +//! This function will place the supplied data into I2C transmit data register +//! to start transmission Modified bit is UCBxTXBUF register +//! +//! \param baseAddress is the base address of the I2C module. +//! \param transmitData data to be transmitted from the I2C module +//! +//! Modified bits of \b UCBxTXBUF register. +//! +//! \return None +// +//***************************************************************************** +void USCI_B_I2C_slaveDataPut(uint16_t baseAddress, + uint8_t transmitData + ) +{ + //Send single byte data. + HWREG8(baseAddress + OFS_UCBxTXBUF) = transmitData; +} + +//***************************************************************************** +// +//! \brief Receives a byte that has been sent to the I2C Module. +//! +//! This function reads a byte of data from the I2C receive data Register. +//! +//! \param baseAddress is the base address of the I2C module. +//! +//! \return Returns the byte received from by the I2C module, cast as an +//! uint8_t. +// +//***************************************************************************** +uint8_t USCI_B_I2C_slaveDataGet(uint16_t baseAddress) +{ + //Read a byte. + return HWREG8(baseAddress + OFS_UCBxRXBUF); +} + +//***************************************************************************** +// +//! \brief Indicates whether or not the I2C bus is busy. +//! +//! This function returns an indication of whether or not the I2C bus is +//! busy.This function checks the status of the bus via UCBBUSY bit in UCBxSTAT +//! register. +//! +//! \param baseAddress is the base address of the I2C module. +//! +//! \return Returns USCI_B_I2C_BUS_BUSY if the I2C Master is busy; otherwise, +//! returns USCI_B_I2C_BUS_NOT_BUSY. +//! Return one of the following: +//! - \b USCI_B_I2C_BUS_BUSY +//! - \b USCI_B_I2C_BUS_NOT_BUSY +//! \n indicating if the USCI_B_I2C is busy +// +//***************************************************************************** +uint8_t USCI_B_I2C_isBusBusy(uint16_t baseAddress) +{ + //Return the bus busy status. + return HWREG8(baseAddress + OFS_UCBxSTAT) & UCBBUSY; +} + +//***************************************************************************** +// +//! \brief DEPRECATED - Function may be removed in future release. Indicates +//! whether or not the I2C module is busy. +//! +//! This function returns an indication of whether or not the I2C module is +//! busy transmitting or receiving data. This function checks if the Transmit +//! or receive flag is set. +//! +//! \param baseAddress is the base address of the I2C module. +//! +//! \return Returns USCI_B_I2C_BUS_BUSY if the I2C module is busy; otherwise, +//! returns USCI_B_I2C_BUS_NOT_BUSY. +//! Return one of the following: +//! - \b USCI_B_I2C_BUS_BUSY +//! - \b USCI_B_I2C_BUS_NOT_BUSY +//! \n indicating if the USCI_B_I2C is busy +// +//***************************************************************************** +uint8_t USCI_B_I2C_isBusy(uint16_t baseAddress) +{ + //Return the busy status. + if ((HWREG8(baseAddress + OFS_UCBxIFG) & (UCTXIFG + UCRXIFG))) + return USCI_B_I2C_BUS_BUSY; + else + return USCI_B_I2C_BUS_NOT_BUSY; +} + +//***************************************************************************** +// +//! \brief Indicates whether STOP got sent. +//! +//! This function returns an indication of whether or not STOP got sent This +//! function checks the status of the bus via UCTXSTP bit in UCBxCTL1 register. +//! +//! \param baseAddress is the base address of the I2C module. +//! +//! \return Returns USCI_B_I2C_STOP_SEND_COMPLETE if the I2C Master finished +//! sending STOP; otherwise, returns USCI_B_I2C_SENDING_STOP. +//! Return one of the following: +//! - \b USCI_B_I2C_SENDING_STOP +//! - \b USCI_B_I2C_STOP_SEND_COMPLETE +// +//***************************************************************************** +uint8_t USCI_B_I2C_masterIsStopSent(uint16_t baseAddress) +{ + //Return the bus busy status. + return HWREG8(baseAddress + OFS_UCBxCTL1) & UCTXSTP; +} + +//***************************************************************************** +// +//! \brief Indicates whether START got sent. +//! +//! This function returns an indication of whether or not START got sent This +//! function checks the status of the bus via UCTXSTT bit in UCBxCTL1 register. +//! +//! \param baseAddress is the base address of the I2C module. +//! +//! \return Returns USCI_B_I2C_START_SEND_COMPLETE if the I2C Master finished +//! sending START; otherwise, returns USCI_B_I2C_SENDING_START. +//! Return one of the following: +//! - \b USCI_B_I2C_SENDING_START +//! - \b USCI_B_I2C_START_SEND_COMPLETE +// +//***************************************************************************** +uint8_t USCI_B_I2C_masterIsStartSent(uint16_t baseAddress) +{ + //Return if master has sent start + return HWREG8(baseAddress + OFS_UCBxCTL1) & UCTXSTT; +} + +//***************************************************************************** +// +//! \brief This function is used by the Master module to initiate START +//! +//! This function is used by the Master module to initiate STOP +//! +//! \param baseAddress is the base address of the I2C Master module. +//! +//! \return None +// +//***************************************************************************** +void USCI_B_I2C_masterSendStart(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCTXSTT; +} + +//***************************************************************************** +// +//! \brief Enables individual I2C interrupt sources. +//! +//! Enables the indicated I2C interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. Does not clear interrupt flags. +//! +//! \param baseAddress is the base address of the I2C module. +//! \param mask is the bit mask of the interrupt sources to be enabled. +//! Mask value is the logical OR of any of the following: +//! - \b USCI_B_I2C_STOP_INTERRUPT - STOP condition interrupt +//! - \b USCI_B_I2C_START_INTERRUPT - START condition interrupt +//! - \b USCI_B_I2C_RECEIVE_INTERRUPT - Receive interrupt +//! - \b USCI_B_I2C_TRANSMIT_INTERRUPT - Transmit interrupt +//! - \b USCI_B_I2C_NAK_INTERRUPT - Not-acknowledge interrupt +//! - \b USCI_B_I2C_ARBITRATIONLOST_INTERRUPT - Arbitration lost +//! interrupt +//! +//! Modified bits of \b UCBxIE register. +//! +//! \return None +// +//***************************************************************************** +void USCI_B_I2C_enableInterrupt(uint16_t baseAddress, + uint8_t mask + ) +{ + assert( 0x00 == ( mask & ~(USCI_B_I2C_STOP_INTERRUPT + + USCI_B_I2C_START_INTERRUPT + + USCI_B_I2C_RECEIVE_INTERRUPT + + USCI_B_I2C_TRANSMIT_INTERRUPT + + USCI_B_I2C_NAK_INTERRUPT + + USCI_B_I2C_ARBITRATIONLOST_INTERRUPT)) + ); + + //Enable the interrupt masked bit + HWREG8(baseAddress + OFS_UCBxIE) |= mask; +} + +//***************************************************************************** +// +//! \brief Disables individual I2C interrupt sources. +//! +//! Disables the indicated I2C interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! \param baseAddress is the base address of the I2C module. +//! \param mask is the bit mask of the interrupt sources to be disabled. +//! Mask value is the logical OR of any of the following: +//! - \b USCI_B_I2C_STOP_INTERRUPT - STOP condition interrupt +//! - \b USCI_B_I2C_START_INTERRUPT - START condition interrupt +//! - \b USCI_B_I2C_RECEIVE_INTERRUPT - Receive interrupt +//! - \b USCI_B_I2C_TRANSMIT_INTERRUPT - Transmit interrupt +//! - \b USCI_B_I2C_NAK_INTERRUPT - Not-acknowledge interrupt +//! - \b USCI_B_I2C_ARBITRATIONLOST_INTERRUPT - Arbitration lost +//! interrupt +//! +//! Modified bits of \b UCBxIE register. +//! +//! \return None +// +//***************************************************************************** +void USCI_B_I2C_disableInterrupt(uint16_t baseAddress, + uint8_t mask + ) +{ + assert( 0x00 == ( mask & ~(USCI_B_I2C_STOP_INTERRUPT + + USCI_B_I2C_START_INTERRUPT + + USCI_B_I2C_RECEIVE_INTERRUPT + + USCI_B_I2C_TRANSMIT_INTERRUPT + + USCI_B_I2C_NAK_INTERRUPT + + USCI_B_I2C_ARBITRATIONLOST_INTERRUPT)) + ); + + //Disable the interrupt masked bit + HWREG8(baseAddress + OFS_UCBxIE) &= ~(mask); +} + +//***************************************************************************** +// +//! \brief Clears I2C interrupt sources. +//! +//! The I2C interrupt source is cleared, so that it no longer asserts. The +//! highest interrupt flag is automatically cleared when an interrupt vector +//! generator is used. +//! +//! \param baseAddress is the base address of the I2C Slave module. +//! \param mask is a bit mask of the interrupt sources to be cleared. +//! Mask value is the logical OR of any of the following: +//! - \b USCI_B_I2C_STOP_INTERRUPT - STOP condition interrupt +//! - \b USCI_B_I2C_START_INTERRUPT - START condition interrupt +//! - \b USCI_B_I2C_RECEIVE_INTERRUPT - Receive interrupt +//! - \b USCI_B_I2C_TRANSMIT_INTERRUPT - Transmit interrupt +//! - \b USCI_B_I2C_NAK_INTERRUPT - Not-acknowledge interrupt +//! - \b USCI_B_I2C_ARBITRATIONLOST_INTERRUPT - Arbitration lost +//! interrupt +//! +//! Modified bits of \b UCBxIFG register. +//! +//! \return None +// +//***************************************************************************** +void USCI_B_I2C_clearInterruptFlag(uint16_t baseAddress, + uint8_t mask + ) +{ + assert( 0x00 == ( mask & ~(USCI_B_I2C_STOP_INTERRUPT + + USCI_B_I2C_START_INTERRUPT + + USCI_B_I2C_RECEIVE_INTERRUPT + + USCI_B_I2C_TRANSMIT_INTERRUPT + + USCI_B_I2C_NAK_INTERRUPT + + USCI_B_I2C_ARBITRATIONLOST_INTERRUPT)) + ); + //Clear the I2C interrupt source. + HWREG8(baseAddress + OFS_UCBxIFG) &= ~(mask); +} + +//***************************************************************************** +// +//! \brief Gets the current I2C interrupt status. +//! +//! This returns the interrupt status for the I2C module based on which flag is +//! passed. mask parameter can be logic OR of any of the following selection. +//! +//! \param baseAddress is the base address of the I2C module. +//! \param mask is the masked interrupt flag status to be returned. +//! Mask value is the logical OR of any of the following: +//! - \b USCI_B_I2C_STOP_INTERRUPT - STOP condition interrupt +//! - \b USCI_B_I2C_START_INTERRUPT - START condition interrupt +//! - \b USCI_B_I2C_RECEIVE_INTERRUPT - Receive interrupt +//! - \b USCI_B_I2C_TRANSMIT_INTERRUPT - Transmit interrupt +//! - \b USCI_B_I2C_NAK_INTERRUPT - Not-acknowledge interrupt +//! - \b USCI_B_I2C_ARBITRATIONLOST_INTERRUPT - Arbitration lost +//! interrupt +//! +//! \return the masked status of the interrupt flag +//! Return Logical OR of any of the following: +//! - \b USCI_B_I2C_STOP_INTERRUPT STOP condition interrupt +//! - \b USCI_B_I2C_START_INTERRUPT START condition interrupt +//! - \b USCI_B_I2C_RECEIVE_INTERRUPT Receive interrupt +//! - \b USCI_B_I2C_TRANSMIT_INTERRUPT Transmit interrupt +//! - \b USCI_B_I2C_NAK_INTERRUPT Not-acknowledge interrupt +//! - \b USCI_B_I2C_ARBITRATIONLOST_INTERRUPT Arbitration lost +//! interrupt +//! \n indicating the status of the masked interrupts +// +//***************************************************************************** +uint8_t USCI_B_I2C_getInterruptStatus(uint16_t baseAddress, + uint8_t mask + ) +{ + assert( 0x00 == ( mask & ~(USCI_B_I2C_STOP_INTERRUPT + + USCI_B_I2C_START_INTERRUPT + + USCI_B_I2C_RECEIVE_INTERRUPT + + USCI_B_I2C_TRANSMIT_INTERRUPT + + USCI_B_I2C_NAK_INTERRUPT + + USCI_B_I2C_ARBITRATIONLOST_INTERRUPT)) + ); + //Return the interrupt status of the request masked bit. + return HWREG8(baseAddress + OFS_UCBxIFG) & mask; +} + +//***************************************************************************** +// +//! \brief Does single byte transmission from Master to Slave +//! +//! This function is used by the Master module to send a single byte.This +//! function does the following: - Sends START; - Transmits the byte to the +//! Slave; - Sends STOP +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param txData is the data byte to be transmitted +//! +//! Modified bits of \b UCBxTXBUF register, bits of \b UCBxIFG register, bits +//! of \b UCBxCTL1 register and bits of \b UCBxIE register. +//! +//! \return None +// +//***************************************************************************** +void USCI_B_I2C_masterSendSingleByte(uint16_t baseAddress, + uint8_t txData + ) +{ + //Store current TXIE status + uint8_t txieStatus = HWREG8(baseAddress + OFS_UCBxIE) & UCTXIE; + + //Disable transmit interrupt enable + HWREG8(baseAddress + OFS_UCBxIE) &= ~(UCTXIE); + + //Send start condition. + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCTR + UCTXSTT; + + //Poll for transmit interrupt flag. + while (!(HWREG8(baseAddress + OFS_UCBxIFG) & UCTXIFG)) ; + + //Send single byte data. + HWREG8(baseAddress + OFS_UCBxTXBUF) = txData; + + //Poll for transmit interrupt flag. + while (!(HWREG8(baseAddress + OFS_UCBxIFG) & UCTXIFG)) ; + + //Send stop condition. + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCTXSTP; + + //Clear transmit interrupt flag before enabling interrupt again + HWREG8(baseAddress + OFS_UCBxIFG) &= ~(UCTXIFG); + + //Reinstate transmit interrupt enable + HWREG8(baseAddress + OFS_UCBxIE) |= txieStatus; +} + +//***************************************************************************** +// +//! \brief Does single byte transmission from Master to Slave with timeout +//! +//! This function is used by the Master module to send a single byte. This +//! function does the following: - Sends START; - Transmits the byte to the +//! Slave; - Sends STOP +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param txData is the data byte to be transmitted +//! \param timeout is the amount of time to wait until giving up +//! +//! Modified bits of \b UCBxTXBUF register, bits of \b UCBxIFG register, bits +//! of \b UCBxCTL1 register and bits of \b UCBxIE register. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the transmission process. +// +//***************************************************************************** +bool USCI_B_I2C_masterSendSingleByteWithTimeout(uint16_t baseAddress, + uint8_t txData, + uint32_t timeout + ) +{ + assert(timeout > 0); + + // Creating variable for second timeout scenario + uint32_t timeout2 = timeout; + + assert(timeout > 0); + + //Store current TXIE status + uint8_t txieStatus = HWREG8(baseAddress + OFS_UCBxIE) & UCTXIE; + + //Disable transmit interrupt enable + HWREG8(baseAddress + OFS_UCBxIE) &= ~(UCTXIE); + + //Send start condition. + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCTR + UCTXSTT; + + //Poll for transmit interrupt flag. + while ((!(HWREG8(baseAddress + OFS_UCBxIFG) & UCTXIFG)) && --timeout) ; + + //Check if transfer timed out + if (timeout == 0) + return STATUS_FAIL; + + //Send single byte data. + HWREG8(baseAddress + OFS_UCBxTXBUF) = txData; + + //Poll for transmit interrupt flag. + while ((!(HWREG8(baseAddress + OFS_UCBxIFG) & UCTXIFG)) && --timeout2) ; + + //Check if transfer timed out + if (timeout2 == 0) + return STATUS_FAIL; + + //Send stop condition. + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCTXSTP; + + //Clear transmit interrupt flag before enabling interrupt again + HWREG8(baseAddress + OFS_UCBxIFG) &= ~(UCTXIFG); + + //Reinstate transmit interrupt enable + HWREG8(baseAddress + OFS_UCBxIE) |= txieStatus; + + return STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! \brief Starts multi-byte transmission from Master to Slave +//! +//! This function is used by the Master module to send a single byte. This +//! function does the following: - Sends START; - Transmits the first data byte +//! of a multi-byte transmission to the Slave +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param txData is the first data byte to be transmitted +//! +//! Modified bits of \b UCBxTXBUF register, bits of \b UCBxIFG register, bits +//! of \b UCBxCTL1 register and bits of \b UCBxIE register. +//! +//! \return None +// +//***************************************************************************** +void USCI_B_I2C_masterMultiByteSendStart(uint16_t baseAddress, + uint8_t txData + ) +{ + //Store current transmit interrupt enable + uint8_t txieStatus = HWREG8(baseAddress + OFS_UCBxIE) & UCTXIE; + + //Disable transmit interrupt enable + HWREG8(baseAddress + OFS_UCBxIE) &= ~(UCTXIE); + + //Send start condition. + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCTR + UCTXSTT; + + //Poll for transmit interrupt flag. + while (!(HWREG8(baseAddress + OFS_UCBxIFG) & UCTXIFG)) ; + + //Send single byte data. + HWREG8(baseAddress + OFS_UCBxTXBUF) = txData; + + //Reinstate transmit interrupt enable + HWREG8(baseAddress + OFS_UCBxIE) |= txieStatus; +} + +//***************************************************************************** +// +//! \brief Starts multi-byte transmission from Master to Slave with timeout +//! +//! This function is used by the Master module to send a single byte. This +//! function does the following: - Sends START; - Transmits the first data byte +//! of a multi-byte transmission to the Slave +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param txData is the first data byte to be transmitted +//! \param timeout is the amount of time to wait until giving up +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the transmission process. +// +//***************************************************************************** +bool USCI_B_I2C_masterMultiByteSendStartWithTimeout(uint16_t baseAddress, + uint8_t txData, + uint32_t timeout + ) +{ + assert(timeout > 0); + + //Store current transmit interrupt enable + uint8_t txieStatus = HWREG8(baseAddress + OFS_UCBxIE) & UCTXIE; + + //Disable transmit interrupt enable + HWREG8(baseAddress + OFS_UCBxIE) &= ~(UCTXIE); + + //Send start condition. + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCTR + UCTXSTT; + + //Poll for transmit interrupt flag. + while ((!(HWREG8(baseAddress + OFS_UCBxIFG) & UCTXIFG)) && --timeout) ; + + //Check if transfer timed out + if (timeout == 0) + return STATUS_FAIL; + + //Send single byte data. + HWREG8(baseAddress + OFS_UCBxTXBUF) = txData; + + //Reinstate transmit interrupt enable + HWREG8(baseAddress + OFS_UCBxIE) |= txieStatus; + + return STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! \brief Continues multi-byte transmission from Master to Slave +//! +//! This function is used by the Master module continue each byte of a multi- +//! byte transmission. This function does the following: -Transmits each data +//! byte of a multi-byte transmission to the Slave +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param txData is the next data byte to be transmitted +//! +//! Modified bits of \b UCBxTXBUF register. +//! +//! \return None +// +//***************************************************************************** +void USCI_B_I2C_masterMultiByteSendNext(uint16_t baseAddress, + uint8_t txData + ) +{ + //If interrupts are not used, poll for flags + if (!(HWREG8(baseAddress + OFS_UCBxIE) & UCTXIE)) + //Poll for transmit interrupt flag. + while (!(HWREG8(baseAddress + OFS_UCBxIFG) & UCTXIFG)) ; + + //Send single byte data. + HWREG8(baseAddress + OFS_UCBxTXBUF) = txData; +} + +//***************************************************************************** +// +//! \brief Continues multi-byte transmission from Master to Slave with timeout +//! +//! This function is used by the Master module continue each byte of a multi- +//! byte transmission. This function does the following: -Transmits each data +//! byte of a multi-byte transmission to the Slave +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param txData is the next data byte to be transmitted +//! \param timeout is the amount of time to wait until giving up +//! +//! Modified bits of \b UCBxTXBUF register. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the transmission process. +// +//***************************************************************************** +bool USCI_B_I2C_masterMultiByteSendNextWithTimeout(uint16_t baseAddress, + uint8_t txData, + uint32_t timeout + ) +{ + assert(timeout > 0); + + //If interrupts are not used, poll for flags + if (!(HWREG8(baseAddress + OFS_UCBxIE) & UCTXIE)) { + //Poll for transmit interrupt flag. + while ((!(HWREG8(baseAddress + OFS_UCBxIFG) & UCTXIFG)) && --timeout) ; + + //Check if transfer timed out + if (timeout == 0) + return STATUS_FAIL; + } + + //Send single byte data. + HWREG8(baseAddress + OFS_UCBxTXBUF) = txData; + + return STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! \brief Finishes multi-byte transmission from Master to Slave +//! +//! This function is used by the Master module to send the last byte and STOP. +//! This function does the following: - Transmits the last data byte of a +//! multi-byte transmission to the Slave; - Sends STOP +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param txData is the last data byte to be transmitted in a multi-byte +//! transmission +//! +//! Modified bits of \b UCBxTXBUF register and bits of \b UCBxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void USCI_B_I2C_masterMultiByteSendFinish(uint16_t baseAddress, + uint8_t txData + ) +{ + //If interrupts are not used, poll for flags + if (!(HWREG8(baseAddress + OFS_UCBxIE) & UCTXIE)) + //Poll for transmit interrupt flag. + while (!(HWREG8(baseAddress + OFS_UCBxIFG) & UCTXIFG)) ; + + //Send single byte data. + HWREG8(baseAddress + OFS_UCBxTXBUF) = txData; + + //Poll for transmit interrupt flag. + while (!(HWREG8(baseAddress + OFS_UCBxIFG) & UCTXIFG)) ; + + //Send stop condition. + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCTXSTP; +} + +//***************************************************************************** +// +//! \brief Finishes multi-byte transmission from Master to Slave with timeout +//! +//! This function is used by the Master module to send the last byte and STOP. +//! This function does the following: - Transmits the last data byte of a +//! multi-byte transmission to the Slave; - Sends STOP +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param txData is the last data byte to be transmitted in a multi-byte +//! transmission +//! \param timeout is the amount of time to wait until giving up +//! +//! Modified bits of \b UCBxTXBUF register and bits of \b UCBxCTL1 register. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the transmission process. +// +//***************************************************************************** +bool USCI_B_I2C_masterMultiByteSendFinishWithTimeout(uint16_t baseAddress, + uint8_t txData, + uint32_t timeout + ) +{ + assert(timeout > 0); + + uint32_t timeout2 = timeout; + + //If interrupts are not used, poll for flags + if (!(HWREG8(baseAddress + OFS_UCBxIE) & UCTXIE)) { + //Poll for transmit interrupt flag. + while ((!(HWREG8(baseAddress + OFS_UCBxIFG) & UCTXIFG)) && --timeout) ; + + //Check if transfer timed out + if (timeout == 0) + return STATUS_FAIL; + } + + //Send single byte data. + HWREG8(baseAddress + OFS_UCBxTXBUF) = txData; + + //Poll for transmit interrupt flag. + while ((!(HWREG8(baseAddress + OFS_UCBxIFG) & UCTXIFG)) && --timeout2) ; + + //Check if transfer timed out + if (timeout2 == 0) + return STATUS_FAIL; + + //Send stop condition. + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCTXSTP; + + return STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! \brief Send STOP byte at the end of a multi-byte transmission from Master +//! to Slave +//! +//! This function is used by the Master module send STOP at the end of a multi- +//! byte transmission. This function does the following: - Sends a STOP after +//! current transmission is complete +//! +//! \param baseAddress is the base address of the I2C Master module. +//! +//! Modified bits are \b UCTXSTP of \b UCBxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void USCI_B_I2C_masterMultiByteSendStop(uint16_t baseAddress) +{ + //If interrupts are not used, poll for flags + if (!(HWREG8(baseAddress + OFS_UCBxIE) & UCTXIE)) + //Poll for transmit interrupt flag. + while (!(HWREG8(baseAddress + OFS_UCBxIFG) & UCTXIFG)) ; + + //Send stop condition. + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCTXSTP; +} + +//***************************************************************************** +// +//! \brief Send STOP byte at the end of a multi-byte transmission from Master +//! to Slave with timeout +//! +//! This function is used by the Master module send STOP at the end of a multi- +//! byte transmission. This function does the following: - Sends a STOP after +//! current transmission is complete +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param timeout is the amount of time to wait until giving up +//! +//! Modified bits are \b UCTXSTP of \b UCBxCTL1 register. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the transmission process. +// +//***************************************************************************** +bool USCI_B_I2C_masterMultiByteSendStopWithTimeout(uint16_t baseAddress, + uint32_t timeout) +{ + + assert(timeout > 0); + + //If interrupts are not used, poll for flags + if (!(HWREG8(baseAddress + OFS_UCBxIE) & UCTXIE)) { + //Poll for transmit interrupt flag. + while ((!(HWREG8(baseAddress + OFS_UCBxIFG) & UCTXIFG)) && --timeout) ; + + //Check if transfer timed out + if (timeout == 0) + return STATUS_FAIL; + } + + //Send stop condition. + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCTXSTP; + + return STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! \brief Starts multi-byte reception at the Master end +//! +//! This function is used by the Master module initiate reception of a single +//! byte. This function does the following: - Sends START +//! +//! \param baseAddress is the base address of the I2C Master module. +//! +//! Modified bits are \b UCTXSTT of \b UCBxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void USCI_B_I2C_masterMultiByteReceiveStart(uint16_t baseAddress) +{ + //Set USCI in Receive mode + HWREG8(baseAddress + OFS_UCBxCTL1) &= ~UCTR; + //Send start + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCTXSTT; +} + +//***************************************************************************** +// +//! \brief Starts multi-byte reception at the Master end one byte at a time +//! +//! This function is used by the Master module to receive each byte of a multi- +//! byte reception. This function reads currently received byte +//! +//! \param baseAddress is the base address of the I2C Master module. +//! +//! \return Received byte at Master end. +// +//***************************************************************************** +uint8_t USCI_B_I2C_masterMultiByteReceiveNext(uint16_t baseAddress) +{ + return HWREG8(baseAddress + OFS_UCBxRXBUF); +} + +//***************************************************************************** +// +//! \brief Finishes multi-byte reception at the Master end +//! +//! This function is used by the Master module to initiate completion of a +//! multi-byte reception. This function does the following: - Receives the +//! current byte and initiates the STOP from Master to Slave +//! +//! \param baseAddress is the base address of the I2C Master module. +//! +//! Modified bits are \b UCTXSTP of \b UCBxCTL1 register. +//! +//! \return Received byte at Master end. +// +//***************************************************************************** +uint8_t USCI_B_I2C_masterMultiByteReceiveFinish(uint16_t baseAddress) +{ + uint8_t receiveData; + + //Send stop condition. + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCTXSTP; + + //Capture data from receive buffer after setting stop bit due to + //MSP430 I2C critical timing. + receiveData = HWREG8(baseAddress + OFS_UCBxRXBUF); + + //Wait for Stop to finish + while (HWREG8(baseAddress + OFS_UCBxCTL1) & UCTXSTP) ; + + //Wait for RX buffer + while (!(HWREG8(baseAddress + OFS_UCBxIFG) & UCRXIFG)) ; + + return receiveData; +} + +//***************************************************************************** +// +//! \brief Finishes multi-byte reception at the Master end with timeout +//! +//! This function is used by the Master module to initiate completion of a +//! multi-byte reception. This function does the following: - Receives the +//! current byte and initiates the STOP from Master to Slave +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param rxData is a pointer to the location to store the received byte at +//! master end +//! \param timeout is the amount of time to wait until giving up +//! +//! Modified bits are \b UCTXSTP of \b UCBxCTL1 register. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the transmission process. +// +//***************************************************************************** +bool USCI_B_I2C_masterMultiByteReceiveFinishWithTimeout(uint16_t baseAddress, + uint8_t *rxData, + uint32_t timeout + ) +{ + assert(timeout > 0); + + uint32_t timeout2 = timeout; + + //Send stop condition. + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCTXSTP; + + //Capture data from receive buffer after setting stop bit due to + //MSP430 I2C critical timing. + *rxData = (HWREG8(baseAddress + OFS_UCBxRXBUF)); + + //Wait for Stop to finish + while ((HWREG8(baseAddress + OFS_UCBxCTL1) & UCTXSTP) && --timeout) ; + + //Check if transfer timed out + if (timeout == 0) + return STATUS_FAIL; + + // Wait for RX buffer + while ((!(HWREG8(baseAddress + OFS_UCBxIFG) & UCRXIFG)) && --timeout2) ; + + //Check if transfer timed out + if (timeout2 == 0) + return STATUS_FAIL; + + return STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! \brief Sends the STOP at the end of a multi-byte reception at the Master +//! end +//! +//! This function is used by the Master module to initiate STOP +//! +//! \param baseAddress is the base address of the I2C Master module. +//! +//! Modified bits are \b UCTXSTP of \b UCBxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void USCI_B_I2C_masterMultiByteReceiveStop(uint16_t baseAddress) +{ + //Send stop condition. + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCTXSTP; +} + +//***************************************************************************** +// +//! \brief Initiates a single byte Reception at the Master End +//! +//! This function sends a START and STOP immediately to indicate Single byte +//! reception +//! +//! \param baseAddress is the base address of the I2C Master module. +//! +//! Modified bits are \b GIE of \b SR register; bits \b UCTXSTT and \b UCTXSTP +//! of \b UCBxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void USCI_B_I2C_masterSingleReceiveStart(uint16_t baseAddress) +{ + //local variable to store GIE status + uint16_t gieStatus; + + //Store current SR register + gieStatus = __get_SR_register() & GIE; + + //Disable global interrupt + __disable_interrupt(); + + //Set USCI in Receive mode + HWREG8(baseAddress + OFS_UCBxCTL1) &= ~UCTR; + + //Send start condition. + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCTXSTT; + + //Poll for Start bit to complete + while (HWREG8(baseAddress + OFS_UCBxCTL1) & UCTXSTT) ; + + //Send stop condition. + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCTXSTP; + + //Reinstate SR register + __bis_SR_register(gieStatus); +} + +//***************************************************************************** +// +//! \brief Initiates a single byte Reception at the Master End with timeout +//! +//! This function sends a START and STOP immediately to indicate Single byte +//! reception +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param timeout is the amount of time to wait until giving up +//! +//! Modified bits are \b GIE of \b SR register; bits \b UCTXSTT and \b UCTXSTP +//! of \b UCBxCTL1 register. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the transmission process. +// +//***************************************************************************** +bool USCI_B_I2C_masterSingleReceiveStartWithTimeout(uint16_t baseAddress, + uint32_t timeout + ) +{ + //local variable to store GIE status + uint16_t gieStatus; + + assert(timeout > 0); + + //Store current SR register + gieStatus = __get_SR_register() & GIE; + + //Disable global interrupt + __disable_interrupt(); + + //Set USCI in Receive mode + HWREG8(baseAddress + OFS_UCBxCTL1) &= ~UCTR; + + //Send start condition. + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCTXSTT; + + //Poll for Start bit to complete + while ((!(HWREG8(baseAddress + OFS_UCBxIFG) & UCTXSTT)) && --timeout) ; + + //Check if transfer timed out + if (timeout == 0) + return STATUS_FAIL; + + //Send stop condition. + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCTXSTP; + + //Reinstate SR register + __bis_SR_register(gieStatus); + + return STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! \brief Receives a byte that has been sent to the I2C Master Module. +//! +//! This function reads a byte of data from the I2C receive data Register. +//! +//! \param baseAddress is the base address of the I2C module. +//! +//! \return Returns the byte received from by the I2C module, cast as an +//! uint8_t. +// +//***************************************************************************** +uint8_t USCI_B_I2C_masterSingleReceive(uint16_t baseAddress) +{ + //Polling RXIFG0 if RXIE is not enabled + if (!(HWREG8(baseAddress + OFS_UCBxIE) & UCRXIE)) + while (!(HWREG8(baseAddress + OFS_UCBxIFG) & UCRXIFG)) ; + + //Read a byte. + return HWREG8(baseAddress + OFS_UCBxRXBUF); +} + +//***************************************************************************** +// +//! \brief Returns the address of the RX Buffer of the I2C for the DMA module. +//! +//! Returns the address of the I2C RX Buffer. This can be used in conjunction +//! with the DMA to store the received data directly to memory. +//! +//! \param baseAddress is the base address of the I2C module. +//! +//! \return the address of the RX Buffer +// +//***************************************************************************** +uint32_t USCI_B_I2C_getReceiveBufferAddressForDMA(uint16_t baseAddress) +{ + return baseAddress + OFS_UCBxRXBUF; +} + +//***************************************************************************** +// +//! \brief Returns the address of the TX Buffer of the I2C for the DMA module. +//! +//! Returns the address of the I2C TX Buffer. This can be used in conjunction +//! with the DMA to obtain transmitted data directly from memory. +//! +//! \param baseAddress is the base address of the I2C module. +//! +//! \return the address of the TX Buffer +// +//***************************************************************************** +uint32_t USCI_B_I2C_getTransmitBufferAddressForDMA(uint16_t baseAddress) +{ + return baseAddress + OFS_UCBxTXBUF; +} + + +#endif +//***************************************************************************** +// +//! Close the doxygen group for usci_b_i2c_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/usci_b_i2c.h b/source/driverlib/MSP430F5xx_6xx/usci_b_i2c.h new file mode 100644 index 0000000..84aaa5e --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/usci_b_i2c.h @@ -0,0 +1,268 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// usci_b_i2c.h - Driver for the USCI_B_I2C Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_USCI_B_I2C_H__ +#define __MSP430WARE_USCI_B_I2C_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_USCI_Bx__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//****************************************************************************** +// +// The following is a struct that is passed to USCI_B_I2C_initMaster() +// +//****************************************************************************** +typedef struct USCI_B_I2C_initMasterParam { + uint8_t selectClockSource; + uint32_t i2cClk; + uint32_t dataRate; +} USCI_B_I2C_initMasterParam; + +//***************************************************************************** +// +// The following are values that can be passed to the selectClockSource +// parameter for functions: USCI_B_I2C_masterInit(). +// +//***************************************************************************** +#define USCI_B_I2C_CLOCKSOURCE_ACLK UCSSEL__ACLK +#define USCI_B_I2C_CLOCKSOURCE_SMCLK UCSSEL__SMCLK + +//***************************************************************************** +// +// The following are values that can be passed to the dataRate parameter for +// functions: USCI_B_I2C_masterInit(). +// +//***************************************************************************** +#define USCI_B_I2C_SET_DATA_RATE_400KBPS 400000 +#define USCI_B_I2C_SET_DATA_RATE_100KBPS 100000 + +//***************************************************************************** +// +// The following are values that can be passed to the mode parameter for +// functions: USCI_B_I2C_setMode(). +// +//***************************************************************************** +#define USCI_B_I2C_TRANSMIT_MODE UCTR +#define USCI_B_I2C_RECEIVE_MODE 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the mask parameter for +// functions: USCI_B_I2C_enableInterrupt(), USCI_B_I2C_disableInterrupt(), +// USCI_B_I2C_clearInterruptFlag(), and USCI_B_I2C_getInterruptStatus() as well +// as returned by the USCI_B_I2C_getInterruptStatus() function. +// +//***************************************************************************** +#define USCI_B_I2C_STOP_INTERRUPT UCSTPIE +#define USCI_B_I2C_START_INTERRUPT UCSTTIE +#define USCI_B_I2C_RECEIVE_INTERRUPT UCRXIE +#define USCI_B_I2C_TRANSMIT_INTERRUPT UCTXIE +#define USCI_B_I2C_NAK_INTERRUPT UCNACKIE +#define USCI_B_I2C_ARBITRATIONLOST_INTERRUPT UCALIE + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the USCI_B_I2C_isBusy() function and the +// USCI_B_I2C_isBusBusy() function. +// +//***************************************************************************** +#define USCI_B_I2C_BUS_BUSY UCBBUSY +#define USCI_B_I2C_BUS_NOT_BUSY 0x00 + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the USCI_B_I2C_masterIsStartSent() function. +// +//***************************************************************************** +#define USCI_B_I2C_SENDING_START UCTXSTT +#define USCI_B_I2C_START_SEND_COMPLETE 0x00 + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the USCI_B_I2C_masterIsStopSent() function. +// +//***************************************************************************** +#define USCI_B_I2C_SENDING_STOP UCTXSTP +#define USCI_B_I2C_STOP_SEND_COMPLETE 0x00 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void USCI_B_I2C_initMaster(uint16_t baseAddress, + USCI_B_I2C_initMasterParam *param); + +extern void USCI_B_I2C_slaveInit(uint16_t baseAddress, + uint8_t slaveAddress); + +extern void USCI_B_I2C_enable(uint16_t baseAddress); + +extern void USCI_B_I2C_disable(uint16_t baseAddress); + +extern void USCI_B_I2C_setSlaveAddress(uint16_t baseAddress, + uint8_t slaveAddress); + +extern void USCI_B_I2C_setMode(uint16_t baseAddress, + uint8_t mode); + +extern void USCI_B_I2C_slaveDataPut(uint16_t baseAddress, + uint8_t transmitData); + +extern uint8_t USCI_B_I2C_slaveDataGet(uint16_t baseAddress); + +extern uint8_t USCI_B_I2C_isBusBusy(uint16_t baseAddress); + +extern uint8_t USCI_B_I2C_isBusy(uint16_t baseAddress); + +extern uint8_t USCI_B_I2C_masterIsStopSent(uint16_t baseAddress); + +extern uint8_t USCI_B_I2C_masterIsStartSent(uint16_t baseAddress); + +extern void USCI_B_I2C_masterSendStart(uint16_t baseAddress); + +extern void USCI_B_I2C_enableInterrupt(uint16_t baseAddress, + uint8_t mask); + +extern void USCI_B_I2C_disableInterrupt(uint16_t baseAddress, + uint8_t mask); + +extern void USCI_B_I2C_clearInterruptFlag(uint16_t baseAddress, + uint8_t mask); + +extern uint8_t USCI_B_I2C_getInterruptStatus(uint16_t baseAddress, + uint8_t mask); + +extern void USCI_B_I2C_masterSendSingleByte(uint16_t baseAddress, + uint8_t txData); + +extern bool USCI_B_I2C_masterSendSingleByteWithTimeout(uint16_t baseAddress, + uint8_t txData, + uint32_t timeout); + +extern void USCI_B_I2C_masterMultiByteSendStart(uint16_t baseAddress, + uint8_t txData); + +extern bool USCI_B_I2C_masterMultiByteSendStartWithTimeout(uint16_t baseAddress, + uint8_t txData, + uint32_t timeout); + +extern void USCI_B_I2C_masterMultiByteSendNext(uint16_t baseAddress, + uint8_t txData); + +extern bool USCI_B_I2C_masterMultiByteSendNextWithTimeout(uint16_t baseAddress, + uint8_t txData, + uint32_t timeout); + +extern void USCI_B_I2C_masterMultiByteSendFinish(uint16_t baseAddress, + uint8_t txData); + +extern bool USCI_B_I2C_masterMultiByteSendFinishWithTimeout(uint16_t baseAddress, + uint8_t txData, + uint32_t timeout); + +extern void USCI_B_I2C_masterMultiByteSendStop(uint16_t baseAddress); + +extern bool USCI_B_I2C_masterMultiByteSendStopWithTimeout(uint16_t baseAddress, + uint32_t timeout); + +extern void USCI_B_I2C_masterMultiByteReceiveStart(uint16_t baseAddress); + +extern uint8_t USCI_B_I2C_masterMultiByteReceiveNext(uint16_t baseAddress); + +extern uint8_t USCI_B_I2C_masterMultiByteReceiveFinish(uint16_t baseAddress); + +extern bool USCI_B_I2C_masterMultiByteReceiveFinishWithTimeout(uint16_t baseAddress, + uint8_t *rxData, + uint32_t timeout); + +extern void USCI_B_I2C_masterMultiByteReceiveStop(uint16_t baseAddress); + +extern void USCI_B_I2C_masterSingleReceiveStart(uint16_t baseAddress); + +extern bool USCI_B_I2C_masterSingleReceiveStartWithTimeout(uint16_t baseAddress, + uint32_t timeout); + +extern uint8_t USCI_B_I2C_masterSingleReceive(uint16_t baseAddress); + +extern uint32_t USCI_B_I2C_getReceiveBufferAddressForDMA(uint16_t baseAddress); + +extern uint32_t USCI_B_I2C_getTransmitBufferAddressForDMA(uint16_t baseAddress); + +//***************************************************************************** +// +// DEPRECATED APIS. +// +//***************************************************************************** +#define USCI_B_I2C_masterIsSTOPSent USCI_B_I2C_masterIsStopSent + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +extern void USCI_B_I2C_masterInit(uint16_t baseAddress, + uint8_t selectClockSource, + uint32_t i2cClk, + uint32_t dataRate); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_USCI_B_I2C_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/usci_b_spi.c b/source/driverlib/MSP430F5xx_6xx/usci_b_spi.c new file mode 100644 index 0000000..388f759 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/usci_b_spi.c @@ -0,0 +1,612 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// usci_b_spi.c - Driver for the usci_b_spi Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup usci_b_spi_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_USCI_Bx__ +#include "usci_b_spi.h" + +#include + +//***************************************************************************** +// +//! \brief DEPRECATED - Initializes the SPI Master block. +//! +//! Upon successful initialization of the SPI master block, this function will +//! have set the bus speed for the master, but the SPI Master block still +//! remains disabled and must be enabled with USCI_B_SPI_enable() +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param selectClockSource selects Clock source. +//! Valid values are: +//! - \b USCI_B_SPI_CLOCKSOURCE_ACLK +//! - \b USCI_B_SPI_CLOCKSOURCE_SMCLK +//! \param clockSourceFrequency is the frequency of the selected clock source +//! \param desiredSpiClock is the desired clock rate for SPI communication +//! \param msbFirst controls the direction of the receive and transmit shift +//! register. +//! Valid values are: +//! - \b USCI_B_SPI_MSB_FIRST +//! - \b USCI_B_SPI_LSB_FIRST [Default] +//! \param clockPhase is clock phase select. +//! Valid values are: +//! - \b USCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT +//! [Default] +//! - \b USCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT +//! \param clockPolarity +//! Valid values are: +//! - \b USCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH +//! - \b USCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default] +//! +//! Modified bits are \b UCSSELx and \b UCSWRST of \b UCBxCTL1 register; bits +//! \b UCCKPH, \b UCCKPL, \b UC7BIT and \b UCMSB of \b UCBxCTL0 register. +//! +//! \return STATUS_SUCCESS +// +//***************************************************************************** +bool USCI_B_SPI_masterInit(uint16_t baseAddress, + uint8_t selectClockSource, + uint32_t clockSourceFrequency, + uint32_t desiredSpiClock, + uint8_t msbFirst, + uint8_t clockPhase, + uint8_t clockPolarity + ) +{ + USCI_B_SPI_initMasterParam param = { 0 }; + + param.selectClockSource = selectClockSource; + param.clockSourceFrequency = clockSourceFrequency; + param.desiredSpiClock = desiredSpiClock; + param.msbFirst = msbFirst; + param.clockPhase = clockPhase; + param.clockPolarity = clockPolarity; + + return USCI_B_SPI_initMaster(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Initializes the SPI Master block. +//! +//! Upon successful initialization of the SPI master block, this function will +//! have set the bus speed for the master, but the SPI Master block still +//! remains disabled and must be enabled with USCI_B_SPI_enable() +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param param is the pointer to struct for master initialization. +//! +//! Modified bits are \b UCSSELx and \b UCSWRST of \b UCBxCTL1 register; bits +//! \b UCCKPH, \b UCCKPL, \b UC7BIT and \b UCMSB of \b UCBxCTL0 register. +//! +//! \return STATUS_SUCCESS +// +//***************************************************************************** +bool USCI_B_SPI_initMaster(uint16_t baseAddress, USCI_B_SPI_initMasterParam *param) +{ + assert(param != 0); + + assert( + (USCI_B_SPI_CLOCKSOURCE_ACLK == param->selectClockSource) || + (USCI_B_SPI_CLOCKSOURCE_SMCLK == param->selectClockSource) + ); + + assert((USCI_B_SPI_MSB_FIRST == param->msbFirst) || + (USCI_B_SPI_LSB_FIRST == param->msbFirst) + ); + + assert((USCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT == param->clockPhase) || + (USCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT == param->clockPhase) + ); + + assert( (USCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == param->clockPolarity) || + (USCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW == param->clockPolarity) + ); + + //Disable the USCI Module + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCSWRST; + + //Reset OFS_UCBxCTL0 values + HWREG8(baseAddress + OFS_UCBxCTL0) &= ~(UCCKPH + UCCKPL + UC7BIT + UCMSB + + UCMST + UCMODE_3 + UCSYNC); + + //Reset OFS_UCBxCTL1 values + HWREG8(baseAddress + OFS_UCBxCTL1) &= ~(UCSSEL_3); + + //Select Clock + HWREG8(baseAddress + OFS_UCBxCTL1) |= param->selectClockSource; + + HWREG16(baseAddress + OFS_UCBxBRW) = + (uint16_t)(param->clockSourceFrequency / param->desiredSpiClock); + + /* + * Configure as SPI master mode. + * Clock phase select, polarity, msb + * UCMST = Master mode + * UCSYNC = Synchronous mode + * UCMODE_0 = 3-pin SPI + */ + HWREG8(baseAddress + OFS_UCBxCTL0) |= ( + param->msbFirst + + param->clockPhase + + param->clockPolarity + + UCMST + + UCSYNC + + UCMODE_0 + ); + + return STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! \brief DEPRECATED - Initializes the SPI Master clock.At the end of this +//! function call, SPI module is left enabled. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param clockSourceFrequency is the frequency of the selected clock source +//! \param desiredSpiClock is the desired clock rate for SPI communication +//! +//! Modified bits of \b UCAxBRW register. +//! +//! \return None +// +//***************************************************************************** +void USCI_B_SPI_masterChangeClock(uint16_t baseAddress, + uint32_t clockSourceFrequency, + uint32_t desiredSpiClock + ) +{ + USCI_B_SPI_changeMasterClockParam param = { 0 }; + + param.clockSourceFrequency = clockSourceFrequency; + param.desiredSpiClock = desiredSpiClock; + + USCI_B_SPI_changeMasterClock(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Initializes the SPI Master clock.At the end of this function call, +//! SPI module is left enabled. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param param is the pointer to struct for master clock setting. +//! +//! Modified bits of \b UCAxBRW register. +//! +//! \return None +// +//***************************************************************************** +void USCI_B_SPI_changeMasterClock(uint16_t baseAddress, + USCI_B_SPI_changeMasterClockParam *param) +{ + assert(param != 0); + + //Disable the USCI Module + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCSWRST; + + HWREG8(baseAddress + OFS_UCBxBRW) = + (uint16_t)(param->clockSourceFrequency / param->desiredSpiClock); + + //Reset the UCSWRST bit to enable the USCI Module + HWREG8(baseAddress + OFS_UCBxCTL1) &= ~(UCSWRST); +} //***************************************************************************** +// +//! \brief Initializes the SPI Slave block. +//! +//! Upon successful initialization of the SPI slave block, this function will +//! have initialized the slave block, but the SPI Slave block still remains +//! disabled and must be enabled with USCI_B_SPI_enable() +//! +//! \param baseAddress is the base address of the SPI Slave module. +//! \param msbFirst controls the direction of the receive and transmit shift +//! register. +//! Valid values are: +//! - \b USCI_B_SPI_MSB_FIRST +//! - \b USCI_B_SPI_LSB_FIRST [Default] +//! \param clockPhase is clock phase select. +//! Valid values are: +//! - \b USCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT +//! [Default] +//! - \b USCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT +//! \param clockPolarity +//! Valid values are: +//! - \b USCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH +//! - \b USCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default] +//! +//! Modified bits are \b UCSWRST of \b UCBxCTL1 register; bits \b UCMSB, \b +//! UCMST, \b UC7BIT, \b UCCKPL, \b UCCKPH and \b UCMODE of \b UCBxCTL0 +//! register. +//! +//! \return STATUS_SUCCESS +// +//***************************************************************************** +bool USCI_B_SPI_slaveInit(uint16_t baseAddress, + uint8_t msbFirst, + uint8_t clockPhase, + uint8_t clockPolarity + ) +{ + assert( + (USCI_B_SPI_MSB_FIRST == msbFirst) || + (USCI_B_SPI_LSB_FIRST == msbFirst) + ); + + assert( + (USCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT == clockPhase) || + (USCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT == clockPhase) + ); + + assert( + (USCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == clockPolarity) || + (USCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW == clockPolarity) + ); + + //Disable USCI Module + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCSWRST; + + //Reset OFS_UCBxCTL0 register + HWREG8(baseAddress + OFS_UCBxCTL0) &= ~(UCMSB + + UC7BIT + + UCMST + + UCCKPL + + UCCKPH + + UCMODE_3 + ); + + //Clock polarity, phase select, msbFirst, SYNC, Mode0 + HWREG8(baseAddress + OFS_UCBxCTL0) |= ( clockPhase + + clockPolarity + + msbFirst + + UCSYNC + + UCMODE_0 + ); + + return STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! \brief Changes the SPI clock phase and polarity.At the end of this function +//! call, SPI module is left enabled. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param clockPhase is clock phase select. +//! Valid values are: +//! - \b USCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT +//! [Default] +//! - \b USCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT +//! \param clockPolarity +//! Valid values are: +//! - \b USCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH +//! - \b USCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default] +//! +//! Modified bits are \b UCCKPL and \b UCCKPH of \b UCAxCTL0 register. +//! +//! \return None +// +//***************************************************************************** +void USCI_B_SPI_changeClockPhasePolarity(uint16_t baseAddress, + uint8_t clockPhase, + uint8_t clockPolarity + ) +{ + + assert( (USCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == clockPolarity) || + (USCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW == clockPolarity) + ); + + //Disable the USCI Module + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCSWRST; + + HWREG8(baseAddress + OFS_UCBxCTL0) &= ~(UCCKPH + UCCKPL); + + HWREG8(baseAddress + OFS_UCBxCTL0) |= ( + clockPhase + + clockPolarity + ); + + //Reset the UCSWRST bit to enable the USCI Module + HWREG8(baseAddress + OFS_UCBxCTL1) &= ~(UCSWRST); +} + +//***************************************************************************** +// +//! \brief Transmits a byte from the SPI Module. +//! +//! This function will place the supplied data into SPI transmit data register +//! to start transmission +//! +//! \param baseAddress is the base address of the SPI module. +//! \param transmitData data to be transmitted from the SPI module +//! +//! \return None +// +//***************************************************************************** +void USCI_B_SPI_transmitData( uint16_t baseAddress, + uint8_t transmitData + ) +{ + HWREG8(baseAddress + OFS_UCBxTXBUF) = transmitData; +} + +//***************************************************************************** +// +//! \brief Receives a byte that has been sent to the SPI Module. +//! +//! This function reads a byte of data from the SPI receive data Register. +//! +//! \param baseAddress is the base address of the SPI module. +//! +//! \return Returns the byte received from by the SPI module, cast as an +//! uint8_t. +// +//***************************************************************************** +uint8_t USCI_B_SPI_receiveData(uint16_t baseAddress) +{ + return HWREG8(baseAddress + OFS_UCBxRXBUF); +} + +//***************************************************************************** +// +//! \brief Enables individual SPI interrupt sources. +//! +//! Enables the indicated SPI interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. Does not clear interrupt flags. +//! +//! \param baseAddress is the base address of the SPI module. +//! \param mask is the bit mask of the interrupt sources to be enabled. +//! Valid values are: +//! - \b USCI_B_SPI_TRANSMIT_INTERRUPT +//! - \b USCI_B_SPI_RECEIVE_INTERRUPT +//! +//! Modified bits of \b UCBxIE register. +//! +//! \return None +// +//***************************************************************************** +void USCI_B_SPI_enableInterrupt(uint16_t baseAddress, + uint8_t mask + ) +{ + assert( 0x00 != mask && (USCI_B_SPI_RECEIVE_INTERRUPT + + USCI_B_SPI_TRANSMIT_INTERRUPT + )); + + HWREG8(baseAddress + OFS_UCBxIE) |= mask; +} + +//***************************************************************************** +// +//! \brief Disables individual SPI interrupt sources. +//! +//! Disables the indicated SPI interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! \param baseAddress is the base address of the SPI module. +//! \param mask is the bit mask of the interrupt sources to be disabled. +//! Valid values are: +//! - \b USCI_B_SPI_TRANSMIT_INTERRUPT +//! - \b USCI_B_SPI_RECEIVE_INTERRUPT +//! +//! Modified bits of \b UCBxIE register. +//! +//! \return None +// +//***************************************************************************** +void USCI_B_SPI_disableInterrupt(uint16_t baseAddress, + uint8_t mask + ) +{ + assert( 0x00 != mask && (USCI_B_SPI_RECEIVE_INTERRUPT + + USCI_B_SPI_TRANSMIT_INTERRUPT + )); + + HWREG8(baseAddress + OFS_UCBxIE) &= ~mask; +} + +//***************************************************************************** +// +//! \brief Gets the current SPI interrupt status. +//! +//! This returns the interrupt status for the SPI module based on which flag is +//! passed. +//! +//! \param baseAddress is the base address of the SPI module. +//! \param mask is the masked interrupt flag status to be returned. +//! Valid values are: +//! - \b USCI_B_SPI_TRANSMIT_INTERRUPT +//! - \b USCI_B_SPI_RECEIVE_INTERRUPT +//! +//! \return The current interrupt status as the mask of the set flags +//! Return Logical OR of any of the following: +//! - \b USCI_B_SPI_TRANSMIT_INTERRUPT +//! - \b USCI_B_SPI_RECEIVE_INTERRUPT +//! \n indicating the status of the masked interrupts +// +//***************************************************************************** +uint8_t USCI_B_SPI_getInterruptStatus(uint16_t baseAddress, + uint8_t mask + ) +{ + assert( 0x00 != mask && (USCI_B_SPI_RECEIVE_INTERRUPT + + USCI_B_SPI_TRANSMIT_INTERRUPT + )); + + return HWREG8(baseAddress + OFS_UCBxIFG) & mask; +} + +//***************************************************************************** +// +//! \brief Clears the selected SPI interrupt status flag. +//! +//! \param baseAddress is the base address of the SPI module. +//! \param mask is the masked interrupt flag to be cleared. +//! Valid values are: +//! - \b USCI_B_SPI_TRANSMIT_INTERRUPT +//! - \b USCI_B_SPI_RECEIVE_INTERRUPT +//! +//! Modified bits of \b UCBxIFG register. +//! +//! \return None +// +//***************************************************************************** +void USCI_B_SPI_clearInterruptFlag(uint16_t baseAddress, + uint8_t mask + ) +{ + assert( 0x00 != mask && (USCI_B_SPI_RECEIVE_INTERRUPT + + USCI_B_SPI_TRANSMIT_INTERRUPT + )); + + HWREG8(baseAddress + OFS_UCBxIFG) &= ~mask; +} + +//***************************************************************************** +// +//! \brief Enables the SPI block. +//! +//! This will enable operation of the SPI block. +//! +//! \param baseAddress is the base address of the USCI SPI module. +//! +//! Modified bits are \b UCSWRST of \b UCBxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void USCI_B_SPI_enable(uint16_t baseAddress) +{ + //Reset the UCSWRST bit to enable the USCI Module + HWREG8(baseAddress + OFS_UCBxCTL1) &= ~(UCSWRST); +} + +//***************************************************************************** +// +//! \brief Disables the SPI block. +//! +//! This will disable operation of the SPI block. +//! +//! \param baseAddress is the base address of the USCI SPI module. +//! +//! Modified bits are \b UCSWRST of \b UCBxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void USCI_B_SPI_disable(uint16_t baseAddress) +{ + //Set the UCSWRST bit to disable the USCI Module + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCSWRST; +} + +//***************************************************************************** +// +//! \brief Returns the address of the RX Buffer of the SPI for the DMA module. +//! +//! Returns the address of the SPI RX Buffer. This can be used in conjunction +//! with the DMA to store the received data directly to memory. +//! +//! \param baseAddress is the base address of the SPI module. +//! +//! \return The address of the SPI RX buffer +// +//***************************************************************************** +uint32_t USCI_B_SPI_getReceiveBufferAddressForDMA(uint16_t baseAddress) +{ + return baseAddress + OFS_UCBxRXBUF; +} + +//***************************************************************************** +// +//! \brief Returns the address of the TX Buffer of the SPI for the DMA module. +//! +//! Returns the address of the SPI TX Buffer. This can be used in conjunction +//! with the DMA to obtain transmitted data directly from memory. +//! +//! \param baseAddress is the base address of the SPI module. +//! +//! \return The address of the SPI TX buffer +// +//***************************************************************************** +uint32_t USCI_B_SPI_getTransmitBufferAddressForDMA(uint16_t baseAddress) +{ + return baseAddress + OFS_UCBxTXBUF; +} + +//***************************************************************************** +// +//! \brief Indicates whether or not the SPI bus is busy. +//! +//! This function returns an indication of whether or not the SPI bus is +//! busy.This function checks the status of the bus via UCBBUSY bit +//! +//! \param baseAddress is the base address of the SPI module. +//! +//! \return USCI_B_SPI_BUSY if the SPI module transmitting or receiving is +//! busy; otherwise, returns USCI_B_SPI_NOT_BUSY. +//! Return one of the following: +//! - \b USCI_B_SPI_BUSY +//! - \b USCI_B_SPI_NOT_BUSY +//! \n indicating if the USCI_B_SPI is busy +// +//***************************************************************************** +uint8_t USCI_B_SPI_isBusy(uint16_t baseAddress) +{ + //Return the bus busy status. + return HWREG8(baseAddress + OFS_UCBxSTAT) & UCBUSY; +} + + +#endif +//***************************************************************************** +// +//! Close the doxygen group for usci_b_spi_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/usci_b_spi.h b/source/driverlib/MSP430F5xx_6xx/usci_b_spi.h new file mode 100644 index 0000000..b3dc6a2 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/usci_b_spi.h @@ -0,0 +1,212 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// usci_b_spi.h - Driver for the USCI_B_SPI Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_USCI_B_SPI_H__ +#define __MSP430WARE_USCI_B_SPI_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_USCI_Bx__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//****************************************************************************** +// +// The following is a struct that is passed to USCI_B_SPI_initMaster() +// +//****************************************************************************** +typedef struct USCI_B_SPI_initMasterParam { + uint8_t selectClockSource; + uint32_t clockSourceFrequency; + uint32_t desiredSpiClock; + uint8_t msbFirst; + uint8_t clockPhase; + uint8_t clockPolarity; +} USCI_B_SPI_initMasterParam; + +//****************************************************************************** +// +// The following is a struct that is passed to USCI_B_SPI_changeMasterParam() +// +//****************************************************************************** +typedef struct USCI_B_SPI_ChangeMasterClockParam { + uint32_t clockSourceFrequency; + uint32_t desiredSpiClock; +} USCI_B_SPI_changeMasterClockParam; + +//***************************************************************************** +// +// The following are values that can be passed to the clockPhase parameter for +// functions: USCI_B_SPI_masterInit(), USCI_B_SPI_slaveInit(), and +// USCI_B_SPI_changeClockPhasePolarity(). +// +//***************************************************************************** +#define USCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT 0x00 +#define USCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT UCCKPH + +//***************************************************************************** +// +// The following are values that can be passed to the msbFirst parameter for +// functions: USCI_B_SPI_masterInit(), and USCI_B_SPI_slaveInit(). +// +//***************************************************************************** +#define USCI_B_SPI_MSB_FIRST UCMSB +#define USCI_B_SPI_LSB_FIRST 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the clockPolarity parameter +// for functions: USCI_B_SPI_masterInit(), USCI_B_SPI_slaveInit(), and +// USCI_B_SPI_changeClockPhasePolarity(). +// +//***************************************************************************** +#define USCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH UCCKPL +#define USCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the selectClockSource +// parameter for functions: USCI_B_SPI_masterInit(). +// +//***************************************************************************** +#define USCI_B_SPI_CLOCKSOURCE_ACLK UCSSEL__ACLK +#define USCI_B_SPI_CLOCKSOURCE_SMCLK UCSSEL__SMCLK + +//***************************************************************************** +// +// The following are values that can be passed to the mask parameter for +// functions: USCI_B_SPI_enableInterrupt(), USCI_B_SPI_disableInterrupt(), +// USCI_B_SPI_getInterruptStatus(), and USCI_B_SPI_clearInterruptFlag() as well +// as returned by the USCI_B_SPI_getInterruptStatus() function. +// +//***************************************************************************** +#define USCI_B_SPI_TRANSMIT_INTERRUPT UCTXIE +#define USCI_B_SPI_RECEIVE_INTERRUPT UCRXIE + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the USCI_B_SPI_isBusy() function. +// +//***************************************************************************** +#define USCI_B_SPI_BUSY UCBUSY +#define USCI_B_SPI_NOT_BUSY 0x00 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern bool USCI_B_SPI_initMaster(uint16_t baseAddress, + USCI_B_SPI_initMasterParam *param); + +extern void USCI_B_SPI_changeMasterClock(uint16_t baseAddress, + USCI_B_SPI_changeMasterClockParam *param); + +extern bool USCI_B_SPI_slaveInit(uint16_t baseAddress, + uint8_t msbFirst, + uint8_t clockPhase, + uint8_t clockPolarity); + +extern void USCI_B_SPI_changeClockPhasePolarity(uint16_t baseAddress, + uint8_t clockPhase, + uint8_t clockPolarity); + +extern void USCI_B_SPI_transmitData(uint16_t baseAddress, + uint8_t transmitData); + +extern uint8_t USCI_B_SPI_receiveData(uint16_t baseAddress); + +extern void USCI_B_SPI_enableInterrupt(uint16_t baseAddress, + uint8_t mask); + +extern void USCI_B_SPI_disableInterrupt(uint16_t baseAddress, + uint8_t mask); + +extern uint8_t USCI_B_SPI_getInterruptStatus(uint16_t baseAddress, + uint8_t mask); + +extern void USCI_B_SPI_clearInterruptFlag(uint16_t baseAddress, + uint8_t mask); + +extern void USCI_B_SPI_enable(uint16_t baseAddress); + +extern void USCI_B_SPI_disable(uint16_t baseAddress); + +extern uint32_t USCI_B_SPI_getReceiveBufferAddressForDMA(uint16_t baseAddress); + +extern uint32_t USCI_B_SPI_getTransmitBufferAddressForDMA(uint16_t baseAddress); + +extern uint8_t USCI_B_SPI_isBusy(uint16_t baseAddress); + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +extern bool USCI_B_SPI_masterInit(uint16_t baseAddress, + uint8_t selectClockSource, + uint32_t clockSourceFrequency, + uint32_t desiredSpiClock, + uint8_t msbFirst, + uint8_t clockPhase, + uint8_t clockPolarity); + +extern void USCI_B_SPI_masterChangeClock(uint16_t baseAddress, + uint32_t clockSourceFrequency, + uint32_t desiredSpiClock); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_USCI_B_SPI_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/usci_i2c.c b/source/driverlib/MSP430F5xx_6xx/usci_i2c.c new file mode 100644 index 0000000..11abe4f --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/usci_i2c.c @@ -0,0 +1,1324 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// usci_i2c.c - Driver for the usci_i2c Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup usci_i2c_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_USCI_Bx__ +#include "usci_i2c.h" + +#include + +//***************************************************************************** +// +//! \brief DEPRECATED - Initializes the I2C Master block. +//! +//! This function initializes operation of the I2C Master block. Upon +//! successful initialization of the I2C block, this function will have set the +//! bus speed for the master; however I2C module is still disabled till +//! USCI_I2C_enable is invoked. If the parameter \e dataRate is +//! USCI_I2C_SET_DATA_RATE_400KBPS, then the master block will be set up to +//! transfer data at 400 kbps; otherwise, it will be set up to transfer data at +//! 100 kbps. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param selectClockSource is the clocksource. +//! Valid values are: +//! - \b USCI_I2C_CLOCKSOURCE_ACLK +//! - \b USCI_I2C_CLOCKSOURCE_SMCLK +//! \param i2cClk is the rate of the clock supplied to the I2C module. +//! \param dataRate set up for selecting data transfer rate. +//! Valid values are: +//! - \b USCI_I2C_SET_DATA_RATE_400KBPS +//! - \b USCI_I2C_SET_DATA_RATE_100KBPS +//! +//! Modified bits are \b UCBxBR0 of \b UCBxBR1 register; bits \b UCSSELx and \b +//! UCSWRST of \b UCBxCTL1 register; bits \b UCMST, \b UCMODE_3 and \b UCSYNC +//! of \b UCBxCTL0 register. +//! +//! \return None +// +//***************************************************************************** +void USCI_I2C_masterInit(uint16_t baseAddress, + uint8_t selectClockSource, + uint32_t i2cClk, + uint32_t dataRate) +{ + USCI_I2C_initMasterParam param = { 0 }; + + param.selectClockSource = selectClockSource; + param.i2cClk = i2cClk; + param.dataRate = dataRate; + + USCI_I2C_initMaster(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Initializes the I2C Master block. +//! +//! This function initializes operation of the I2C Master block. Upon +//! successful initialization of the I2C block, this function will have set the +//! bus speed for the master; however I2C module is still disabled till +//! USCI_I2C_enable is invoked. If the parameter \e dataRate is +//! USCI_I2C_SET_DATA_RATE_400KBPS, then the master block will be set up to +//! transfer data at 400 kbps; otherwise, it will be set up to transfer data at +//! 100 kbps. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param param is the pointe to struct for master initialization. +//! +//! Modified bits are \b UCBxBR0 of \b UCBxBR1 register; bits \b UCSSELx and \b +//! UCSWRST of \b UCBxCTL1 register; bits \b UCMST, \b UCMODE_3 and \b UCSYNC +//! of \b UCBxCTL0 register. +//! +//! \return None +// +//***************************************************************************** +void USCI_I2C_initMaster(uint16_t baseAddress, USCI_I2C_initMasterParam *param) +{ + uint16_t preScalarValue; + + assert(param != 0); + + assert((USCI_I2C_CLOCKSOURCE_ACLK == param->selectClockSource) || + (USCI_I2C_CLOCKSOURCE_SMCLK == param->selectClockSource) + ); + + assert((USCI_I2C_SET_DATA_RATE_400KBPS == param->dataRate) || + (USCI_I2C_SET_DATA_RATE_100KBPS == param->dataRate) + ); + + //Disable the USCI module and clears the other bits of control register + HWREG8(baseAddress + OFS_UCBxCTL1) = UCSWRST; + + /* + * Configure as I2C master mode. + * UCMST = Master mode + * UCMODE_3 = I2C mode + * UCSYNC = Synchronous mode + */ + HWREG8(baseAddress + OFS_UCBxCTL0) = UCMST + UCMODE_3 + UCSYNC; + + //Configure I2C clock source + HWREG8(baseAddress + OFS_UCBxCTL1) = (param->selectClockSource + UCSWRST ); + + /* + * Compute the clock divider that achieves the fastest speed less than or + * equal to the desired speed. The numerator is biased to favor a larger + * clock divider so that the resulting clock is always less than or equal + * to the desired clock, never greater. + */ + preScalarValue = (unsigned short)(param->i2cClk / param->dataRate); + HWREG16(baseAddress + OFS_UCBxBRW) = preScalarValue; +} //***************************************************************************** +// +//! \brief Initializes the I2C Slave block. +//! +//! This function initializes operation of the I2C as a Slave mode. Upon +//! successful initialization of the I2C blocks, this function will have set +//! the slave address but the I2C module is still disabled till USCI_I2C_enable +//! is invoked. +//! +//! \param baseAddress is the base address of the I2C Slave module. +//! \param slaveAddress 7-bit slave address +//! +//! Modified bits of \b UCBxI2COA register; bits \b UCSWRST of \b UCBxCTL1 +//! register; bits \b UCMODE_3 and \b UCSYNC of \b UCBxCTL0 register. +//! +//! \return None +// +//***************************************************************************** +void USCI_I2C_slaveInit(uint16_t baseAddress, + uint8_t slaveAddress + ) +{ + //Disable the USCI module + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCSWRST; + + //Clear USCI master mode + HWREG8(baseAddress + OFS_UCBxCTL0) &= ~UCMST; + + //Confiugre I2C as Slave and Synchronous mode + HWREG8(baseAddress + OFS_UCBxCTL0) = UCMODE_3 + UCSYNC; + + //Set up the slave address. + HWREG16(baseAddress + OFS_UCBxI2COA) = slaveAddress; +} + +//***************************************************************************** +// +//! \brief Enables the I2C block. +//! +//! This will enable operation of the I2C block. +//! +//! \param baseAddress is the base address of the USCI I2C module. +//! +//! Modified bits are \b UCSWRST of \b UCBxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void USCI_I2C_enable(uint16_t baseAddress) +{ + //Reset the UCSWRST bit to enable the USCI Module + HWREG8(baseAddress + OFS_UCBxCTL1) &= ~(UCSWRST); +} + +//***************************************************************************** +// +//! \brief Disables the I2C block. +//! +//! This will disable operation of the I2C block. +//! +//! \param baseAddress is the base address of the USCI I2C module. +//! +//! Modified bits are \b UCSWRST of \b UCBxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void USCI_I2C_disable(uint16_t baseAddress) +{ + //Set the UCSWRST bit to disable the USCI Module + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCSWRST; +} + +//***************************************************************************** +// +//! \brief Sets the address that the I2C Master will place on the bus. +//! +//! This function will set the address that the I2C Master will place on the +//! bus when initiating a transaction. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param slaveAddress 7-bit slave address +//! +//! Modified bits of \b UCBxI2CSA register; bits \b UCSWRST of \b UCBxCTL1 +//! register. +//! +//! \return None +// +//***************************************************************************** +void USCI_I2C_setSlaveAddress(uint16_t baseAddress, + uint8_t slaveAddress + ) +{ + //Set the address of the slave with which the master will communicate. + HWREG16(baseAddress + OFS_UCBxI2CSA) = (slaveAddress); +} + +//***************************************************************************** +// +//! \brief Sets the mode of the I2C device +//! +//! When the receive parameter is set to USCI_I2C_TRANSMIT_MODE, the address +//! will indicate that the I2C module is in receive mode; otherwise, the I2C +//! module is in send mode. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param mode indicates whether module is in transmit/receive mode +//! Valid values are: +//! - \b USCI_I2C_TRANSMIT_MODE +//! - \b USCI_I2C_RECEIVE_MODE [Default] +//! +//! \return None +// +//***************************************************************************** +void USCI_I2C_setMode(uint16_t baseAddress, + uint8_t mode + ) +{ + assert((USCI_I2C_TRANSMIT_MODE == mode) || + (USCI_I2C_RECEIVE_MODE == mode) + ); + + HWREG8(baseAddress + OFS_UCBxCTL1) &= ~USCI_I2C_TRANSMIT_MODE; + HWREG8(baseAddress + OFS_UCBxCTL1) |= mode; +} + +//***************************************************************************** +// +//! \brief Transmits a byte from the I2C Module. +//! +//! This function will place the supplied data into I2C transmit data register +//! to start transmission Modified bit is UCBxTXBUF register +//! +//! \param baseAddress is the base address of the I2C module. +//! \param transmitData data to be transmitted from the I2C module +//! +//! Modified bits of \b UCBxTXBUF register. +//! +//! \return None +// +//***************************************************************************** +void USCI_I2C_slaveDataPut(uint16_t baseAddress, + uint8_t transmitData + ) +{ + //Send single byte data. + HWREG8(baseAddress + OFS_UCBxTXBUF) = transmitData; +} + +//***************************************************************************** +// +//! \brief Receives a byte that has been sent to the I2C Module. +//! +//! This function reads a byte of data from the I2C receive data Register. +//! +//! \param baseAddress is the base address of the I2C module. +//! +//! \return Returns the byte received from by the I2C module, cast as an +//! uint8_t. +// +//***************************************************************************** +uint8_t USCI_I2C_slaveDataGet(uint16_t baseAddress) +{ + //Read a byte. + return HWREG8(baseAddress + OFS_UCBxRXBUF); +} + +//***************************************************************************** +// +//! \brief Indicates whether or not the I2C bus is busy. +//! +//! This function returns an indication of whether or not the I2C bus is +//! busy.This function checks the status of the bus via UCBBUSY bit in UCBxSTAT +//! register. +//! +//! \param baseAddress is the base address of the I2C module. +//! +//! \return Returns USCI_I2C_BUS_BUSY if the I2C Master is busy; otherwise, +//! returns USCI_I2C_BUS_NOT_BUSY. +//! Return one of the following: +//! - \b USCI_I2C_BUS_BUSY +//! - \b USCI_I2C_BUS_NOT_BUSY +//! \n indicating if the USCI_I2C is busy +// +//***************************************************************************** +uint8_t USCI_I2C_isBusBusy(uint16_t baseAddress) +{ + //Return the bus busy status. + return HWREG8(baseAddress + OFS_UCBxSTAT) & UCBBUSY; +} + +//***************************************************************************** +// +//! \brief DEPRECATED - Function may be removed in future release. Indicates +//! whether or not the I2C module is busy. +//! +//! This function returns an indication of whether or not the I2C module is +//! busy transmitting or receiving data. This function checks if the Transmit +//! or receive flag is set. +//! +//! \param baseAddress is the base address of the I2C module. +//! +//! \return Returns USCI_I2C_BUS_BUSY if the I2C module is busy; otherwise, +//! returns USCI_I2C_BUS_NOT_BUSY. +//! Return one of the following: +//! - \b USCI_I2C_BUS_BUSY +//! - \b USCI_I2C_BUS_NOT_BUSY +//! \n indicating if the USCI_I2C is busy +// +//***************************************************************************** +uint8_t USCI_I2C_isBusy(uint16_t baseAddress) +{ + //Return the busy status. + if ((HWREG8(baseAddress + OFS_UCBxIFG) & (UCTXIFG + UCRXIFG))) + return USCI_I2C_BUS_BUSY; + else + return USCI_I2C_BUS_NOT_BUSY; +} + +//***************************************************************************** +// +//! \brief Indicates whether STOP got sent. +//! +//! This function returns an indication of whether or not STOP got sent This +//! function checks the status of the bus via UCTXSTP bit in UCBxCTL1 register. +//! +//! \param baseAddress is the base address of the I2C module. +//! +//! \return Returns USCI_I2C_STOP_SEND_COMPLETE if the I2C Master finished +//! sending STOP; otherwise, returns USCI_I2C_SENDING_STOP. +//! Return one of the following: +//! - \b USCI_I2C_SENDING_STOP +//! - \b USCI_I2C_STOP_SEND_COMPLETE +// +//***************************************************************************** +uint8_t USCI_I2C_masterIsStopSent(uint16_t baseAddress) +{ + //Return the bus busy status. + return HWREG8(baseAddress + OFS_UCBxCTL1) & UCTXSTP; +} + +//***************************************************************************** +// +//! \brief Indicates whether START got sent. +//! +//! This function returns an indication of whether or not START got sent This +//! function checks the status of the bus via UCTXSTT bit in UCBxCTL1 register. +//! +//! \param baseAddress is the base address of the I2C module. +//! +//! \return Returns USCI_I2C_START_SEND_COMPLETE if the I2C Master finished +//! sending START; otherwise, returns USCI_I2C_SENDING_START. +//! Return one of the following: +//! - \b USCI_I2C_SENDING_START +//! - \b USCI_I2C_START_SEND_COMPLETE +// +//***************************************************************************** +uint8_t USCI_I2C_masterIsStartSent(uint16_t baseAddress) +{ + //Return if master has sent start + return HWREG8(baseAddress + OFS_UCBxCTL1) & UCTXSTT; +} + +//***************************************************************************** +// +//! \brief This function is used by the Master module to initiate START +//! +//! This function is used by the Master module to initiate STOP +//! +//! \param baseAddress is the base address of the I2C Master module. +//! +//! \return None +// +//***************************************************************************** +void USCI_I2C_masterSendStart(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCTXSTT; +} + +//***************************************************************************** +// +//! \brief Enables individual I2C interrupt sources. +//! +//! Enables the indicated I2C interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. Does not clear interrupt flags. +//! +//! \param baseAddress is the base address of the I2C module. +//! \param mask is the bit mask of the interrupt sources to be enabled. +//! Mask value is the logical OR of any of the following: +//! - \b USCI_I2C_STOP_INTERRUPT - STOP condition interrupt +//! - \b USCI_I2C_START_INTERRUPT - START condition interrupt +//! - \b USCI_I2C_RECEIVE_INTERRUPT - Receive interrupt +//! - \b USCI_I2C_TRANSMIT_INTERRUPT - Transmit interrupt +//! - \b USCI_I2C_NAK_INTERRUPT - Not-acknowledge interrupt +//! - \b USCI_I2C_ARBITRATIONLOST_INTERRUPT - Arbitration lost interrupt +//! +//! Modified bits of \b UCBxIE register. +//! +//! \return None +// +//***************************************************************************** +void USCI_I2C_enableInterrupt(uint16_t baseAddress, + uint8_t mask + ) +{ + assert( 0x00 == ( mask & ~(USCI_I2C_STOP_INTERRUPT + + USCI_I2C_START_INTERRUPT + + USCI_I2C_RECEIVE_INTERRUPT + + USCI_I2C_TRANSMIT_INTERRUPT + + USCI_I2C_NAK_INTERRUPT + + USCI_I2C_ARBITRATIONLOST_INTERRUPT)) + ); + + //Enable the interrupt masked bit + HWREG8(baseAddress + OFS_UCBxIE) |= mask; +} + +//***************************************************************************** +// +//! \brief Disables individual I2C interrupt sources. +//! +//! Disables the indicated I2C interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! \param baseAddress is the base address of the I2C module. +//! \param mask is the bit mask of the interrupt sources to be disabled. +//! Mask value is the logical OR of any of the following: +//! - \b USCI_I2C_STOP_INTERRUPT - STOP condition interrupt +//! - \b USCI_I2C_START_INTERRUPT - START condition interrupt +//! - \b USCI_I2C_RECEIVE_INTERRUPT - Receive interrupt +//! - \b USCI_I2C_TRANSMIT_INTERRUPT - Transmit interrupt +//! - \b USCI_I2C_NAK_INTERRUPT - Not-acknowledge interrupt +//! - \b USCI_I2C_ARBITRATIONLOST_INTERRUPT - Arbitration lost interrupt +//! +//! Modified bits of \b UCBxIE register. +//! +//! \return None +// +//***************************************************************************** +void USCI_I2C_disableInterrupt(uint16_t baseAddress, + uint8_t mask + ) +{ + assert( 0x00 == ( mask & ~(USCI_I2C_STOP_INTERRUPT + + USCI_I2C_START_INTERRUPT + + USCI_I2C_RECEIVE_INTERRUPT + + USCI_I2C_TRANSMIT_INTERRUPT + + USCI_I2C_NAK_INTERRUPT + + USCI_I2C_ARBITRATIONLOST_INTERRUPT)) + ); + + //Disable the interrupt masked bit + HWREG8(baseAddress + OFS_UCBxIE) &= ~(mask); +} + +//***************************************************************************** +// +//! \brief Clears I2C interrupt sources. +//! +//! The I2C interrupt source is cleared, so that it no longer asserts. The +//! highest interrupt flag is automatically cleared when an interrupt vector +//! generator is used. +//! +//! \param baseAddress is the base address of the I2C Slave module. +//! \param mask is a bit mask of the interrupt sources to be cleared. +//! Mask value is the logical OR of any of the following: +//! - \b USCI_I2C_STOP_INTERRUPT - STOP condition interrupt +//! - \b USCI_I2C_START_INTERRUPT - START condition interrupt +//! - \b USCI_I2C_RECEIVE_INTERRUPT - Receive interrupt +//! - \b USCI_I2C_TRANSMIT_INTERRUPT - Transmit interrupt +//! - \b USCI_I2C_NAK_INTERRUPT - Not-acknowledge interrupt +//! - \b USCI_I2C_ARBITRATIONLOST_INTERRUPT - Arbitration lost interrupt +//! +//! Modified bits of \b UCBxIFG register. +//! +//! \return None +// +//***************************************************************************** +void USCI_I2C_clearInterruptFlag(uint16_t baseAddress, + uint8_t mask + ) +{ + assert( 0x00 == ( mask & ~(USCI_I2C_STOP_INTERRUPT + + USCI_I2C_START_INTERRUPT + + USCI_I2C_RECEIVE_INTERRUPT + + USCI_I2C_TRANSMIT_INTERRUPT + + USCI_I2C_NAK_INTERRUPT + + USCI_I2C_ARBITRATIONLOST_INTERRUPT)) + ); + //Clear the I2C interrupt source. + HWREG8(baseAddress + OFS_UCBxIFG) &= ~(mask); +} + +//***************************************************************************** +// +//! \brief Gets the current I2C interrupt status. +//! +//! This returns the interrupt status for the I2C module based on which flag is +//! passed. mask parameter can be logic OR of any of the following selection. +//! +//! \param baseAddress is the base address of the I2C module. +//! \param mask is the masked interrupt flag status to be returned. +//! Mask value is the logical OR of any of the following: +//! - \b USCI_I2C_STOP_INTERRUPT - STOP condition interrupt +//! - \b USCI_I2C_START_INTERRUPT - START condition interrupt +//! - \b USCI_I2C_RECEIVE_INTERRUPT - Receive interrupt +//! - \b USCI_I2C_TRANSMIT_INTERRUPT - Transmit interrupt +//! - \b USCI_I2C_NAK_INTERRUPT - Not-acknowledge interrupt +//! - \b USCI_I2C_ARBITRATIONLOST_INTERRUPT - Arbitration lost interrupt +//! +//! \return the masked status of the interrupt flag +//! Return Logical OR of any of the following: +//! - \b USCI_I2C_STOP_INTERRUPT STOP condition interrupt +//! - \b USCI_I2C_START_INTERRUPT START condition interrupt +//! - \b USCI_I2C_RECEIVE_INTERRUPT Receive interrupt +//! - \b USCI_I2C_TRANSMIT_INTERRUPT Transmit interrupt +//! - \b USCI_I2C_NAK_INTERRUPT Not-acknowledge interrupt +//! - \b USCI_I2C_ARBITRATIONLOST_INTERRUPT Arbitration lost interrupt +//! \n indicating the status of the masked interrupts +// +//***************************************************************************** +uint8_t USCI_I2C_getInterruptStatus(uint16_t baseAddress, + uint8_t mask + ) +{ + assert( 0x00 == ( mask & ~(USCI_I2C_STOP_INTERRUPT + + USCI_I2C_START_INTERRUPT + + USCI_I2C_RECEIVE_INTERRUPT + + USCI_I2C_TRANSMIT_INTERRUPT + + USCI_I2C_NAK_INTERRUPT + + USCI_I2C_ARBITRATIONLOST_INTERRUPT)) + ); + //Return the interrupt status of the request masked bit. + return HWREG8(baseAddress + OFS_UCBxIFG) & mask; +} + +//***************************************************************************** +// +//! \brief Does single byte transmission from Master to Slave +//! +//! This function is used by the Master module to send a single byte.This +//! function does the following: - Sends START; - Transmits the byte to the +//! Slave; - Sends STOP +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param txData is the data byte to be transmitted +//! +//! Modified bits of \b UCBxTXBUF register, bits of \b UCBxIFG register, bits +//! of \b UCBxCTL1 register and bits of \b UCBxIE register. +//! +//! \return None +// +//***************************************************************************** +void USCI_I2C_masterSendSingleByte(uint16_t baseAddress, + uint8_t txData + ) +{ + //Store current TXIE status + uint8_t txieStatus = HWREG8(baseAddress + OFS_UCBxIE) & UCTXIE; + + //Disable transmit interrupt enable + HWREG8(baseAddress + OFS_UCBxIE) &= ~(UCTXIE); + + //Send start condition. + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCTR + UCTXSTT; + + //Poll for transmit interrupt flag. + while (!(HWREG8(baseAddress + OFS_UCBxIFG) & UCTXIFG)) ; + + //Send single byte data. + HWREG8(baseAddress + OFS_UCBxTXBUF) = txData; + + //Poll for transmit interrupt flag. + while (!(HWREG8(baseAddress + OFS_UCBxIFG) & UCTXIFG)) ; + + //Send stop condition. + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCTXSTP; + + //Clear transmit interrupt flag before enabling interrupt again + HWREG8(baseAddress + OFS_UCBxIFG) &= ~(UCTXIFG); + + //Reinstate transmit interrupt enable + HWREG8(baseAddress + OFS_UCBxIE) |= txieStatus; +} + +//***************************************************************************** +// +//! \brief Does single byte transmission from Master to Slave with timeout +//! +//! This function is used by the Master module to send a single byte. This +//! function does the following: - Sends START; - Transmits the byte to the +//! Slave; - Sends STOP +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param txData is the data byte to be transmitted +//! \param timeout is the amount of time to wait until giving up +//! +//! Modified bits of \b UCBxTXBUF register, bits of \b UCBxIFG register, bits +//! of \b UCBxCTL1 register and bits of \b UCBxIE register. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the transmission process. +// +//***************************************************************************** +bool USCI_I2C_masterSendSingleByteWithTimeout(uint16_t baseAddress, + uint8_t txData, + uint32_t timeout + ) +{ + assert(timeout > 0); + + // Creating variable for second timeout scenario + uint32_t timeout2 = timeout; + + assert(timeout > 0); + + //Store current TXIE status + uint8_t txieStatus = HWREG8(baseAddress + OFS_UCBxIE) & UCTXIE; + + //Disable transmit interrupt enable + HWREG8(baseAddress + OFS_UCBxIE) &= ~(UCTXIE); + + //Send start condition. + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCTR + UCTXSTT; + + //Poll for transmit interrupt flag. + while ((!(HWREG8(baseAddress + OFS_UCBxIFG) & UCTXIFG)) && --timeout) ; + + //Check if transfer timed out + if (timeout == 0) + return STATUS_FAIL; + + //Send single byte data. + HWREG8(baseAddress + OFS_UCBxTXBUF) = txData; + + //Poll for transmit interrupt flag. + while ((!(HWREG8(baseAddress + OFS_UCBxIFG) & UCTXIFG)) && --timeout2) ; + + //Check if transfer timed out + if (timeout2 == 0) + return STATUS_FAIL; + + //Send stop condition. + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCTXSTP; + + //Clear transmit interrupt flag before enabling interrupt again + HWREG8(baseAddress + OFS_UCBxIFG) &= ~(UCTXIFG); + + //Reinstate transmit interrupt enable + HWREG8(baseAddress + OFS_UCBxIE) |= txieStatus; + + return STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! \brief Starts multi-byte transmission from Master to Slave +//! +//! This function is used by the Master module to send a single byte. This +//! function does the following: - Sends START; - Transmits the first data byte +//! of a multi-byte transmission to the Slave +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param txData is the first data byte to be transmitted +//! +//! Modified bits of \b UCBxTXBUF register, bits of \b UCBxIFG register, bits +//! of \b UCBxCTL1 register and bits of \b UCBxIE register. +//! +//! \return None +// +//***************************************************************************** +void USCI_I2C_masterMultiByteSendStart(uint16_t baseAddress, + uint8_t txData + ) +{ + //Store current transmit interrupt enable + uint8_t txieStatus = HWREG8(baseAddress + OFS_UCBxIE) & UCTXIE; + + //Disable transmit interrupt enable + HWREG8(baseAddress + OFS_UCBxIE) &= ~(UCTXIE); + + //Send start condition. + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCTR + UCTXSTT; + + //Poll for transmit interrupt flag. + while (!(HWREG8(baseAddress + OFS_UCBxIFG) & UCTXIFG)) ; + + //Send single byte data. + HWREG8(baseAddress + OFS_UCBxTXBUF) = txData; + + //Reinstate transmit interrupt enable + HWREG8(baseAddress + OFS_UCBxIE) |= txieStatus; +} + +//***************************************************************************** +// +//! \brief Starts multi-byte transmission from Master to Slave with timeout +//! +//! This function is used by the Master module to send a single byte. This +//! function does the following: - Sends START; - Transmits the first data byte +//! of a multi-byte transmission to the Slave +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param txData is the first data byte to be transmitted +//! \param timeout is the amount of time to wait until giving up +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the transmission process. +// +//***************************************************************************** +bool USCI_I2C_masterMultiByteSendStartWithTimeout(uint16_t baseAddress, + uint8_t txData, + uint32_t timeout + ) +{ + assert(timeout > 0); + + //Store current transmit interrupt enable + uint8_t txieStatus = HWREG8(baseAddress + OFS_UCBxIE) & UCTXIE; + + //Disable transmit interrupt enable + HWREG8(baseAddress + OFS_UCBxIE) &= ~(UCTXIE); + + //Send start condition. + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCTR + UCTXSTT; + + //Poll for transmit interrupt flag. + while ((!(HWREG8(baseAddress + OFS_UCBxIFG) & UCTXIFG)) && --timeout) ; + + //Check if transfer timed out + if (timeout == 0) + return STATUS_FAIL; + + //Send single byte data. + HWREG8(baseAddress + OFS_UCBxTXBUF) = txData; + + //Reinstate transmit interrupt enable + HWREG8(baseAddress + OFS_UCBxIE) |= txieStatus; + + return STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! \brief Continues multi-byte transmission from Master to Slave +//! +//! This function is used by the Master module continue each byte of a multi- +//! byte transmission. This function does the following: -Transmits each data +//! byte of a multi-byte transmission to the Slave +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param txData is the next data byte to be transmitted +//! +//! Modified bits of \b UCBxTXBUF register. +//! +//! \return None +// +//***************************************************************************** +void USCI_I2C_masterMultiByteSendNext(uint16_t baseAddress, + uint8_t txData + ) +{ + //If interrupts are not used, poll for flags + if (!(HWREG8(baseAddress + OFS_UCBxIE) & UCTXIE)) + //Poll for transmit interrupt flag. + while (!(HWREG8(baseAddress + OFS_UCBxIFG) & UCTXIFG)) ; + + //Send single byte data. + HWREG8(baseAddress + OFS_UCBxTXBUF) = txData; +} + +//***************************************************************************** +// +//! \brief Continues multi-byte transmission from Master to Slave with timeout +//! +//! This function is used by the Master module continue each byte of a multi- +//! byte transmission. This function does the following: -Transmits each data +//! byte of a multi-byte transmission to the Slave +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param txData is the next data byte to be transmitted +//! \param timeout is the amount of time to wait until giving up +//! +//! Modified bits of \b UCBxTXBUF register. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the transmission process. +// +//***************************************************************************** +bool USCI_I2C_masterMultiByteSendNextWithTimeout(uint16_t baseAddress, + uint8_t txData, + uint32_t timeout + ) +{ + assert(timeout > 0); + + //If interrupts are not used, poll for flags + if (!(HWREG8(baseAddress + OFS_UCBxIE) & UCTXIE)) { + //Poll for transmit interrupt flag. + while ((!(HWREG8(baseAddress + OFS_UCBxIFG) & UCTXIFG)) && --timeout) ; + + //Check if transfer timed out + if (timeout == 0) + return STATUS_FAIL; + } + + //Send single byte data. + HWREG8(baseAddress + OFS_UCBxTXBUF) = txData; + + return STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! \brief Finishes multi-byte transmission from Master to Slave +//! +//! This function is used by the Master module to send the last byte and STOP. +//! This function does the following: - Transmits the last data byte of a +//! multi-byte transmission to the Slave; - Sends STOP +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param txData is the last data byte to be transmitted in a multi-byte +//! transmission +//! +//! Modified bits of \b UCBxTXBUF register and bits of \b UCBxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void USCI_I2C_masterMultiByteSendFinish(uint16_t baseAddress, + uint8_t txData + ) +{ + //If interrupts are not used, poll for flags + if (!(HWREG8(baseAddress + OFS_UCBxIE) & UCTXIE)) + //Poll for transmit interrupt flag. + while (!(HWREG8(baseAddress + OFS_UCBxIFG) & UCTXIFG)) ; + + //Send single byte data. + HWREG8(baseAddress + OFS_UCBxTXBUF) = txData; + + //Poll for transmit interrupt flag. + while (!(HWREG8(baseAddress + OFS_UCBxIFG) & UCTXIFG)) ; + + //Send stop condition. + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCTXSTP; +} + +//***************************************************************************** +// +//! \brief Finishes multi-byte transmission from Master to Slave with timeout +//! +//! This function is used by the Master module to send the last byte and STOP. +//! This function does the following: - Transmits the last data byte of a +//! multi-byte transmission to the Slave; - Sends STOP +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param txData is the last data byte to be transmitted in a multi-byte +//! transmission +//! \param timeout is the amount of time to wait until giving up +//! +//! Modified bits of \b UCBxTXBUF register and bits of \b UCBxCTL1 register. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the transmission process. +// +//***************************************************************************** +bool USCI_I2C_masterMultiByteSendFinishWithTimeout(uint16_t baseAddress, + uint8_t txData, + uint32_t timeout + ) +{ + assert(timeout > 0); + + uint32_t timeout2 = timeout; + + //If interrupts are not used, poll for flags + if (!(HWREG8(baseAddress + OFS_UCBxIE) & UCTXIE)) { + //Poll for transmit interrupt flag. + while ((!(HWREG8(baseAddress + OFS_UCBxIFG) & UCTXIFG)) && --timeout) ; + + //Check if transfer timed out + if (timeout == 0) + return STATUS_FAIL; + } + + //Send single byte data. + HWREG8(baseAddress + OFS_UCBxTXBUF) = txData; + + //Poll for transmit interrupt flag. + while ((!(HWREG8(baseAddress + OFS_UCBxIFG) & UCTXIFG)) && --timeout2) ; + + //Check if transfer timed out + if (timeout2 == 0) + return STATUS_FAIL; + + //Send stop condition. + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCTXSTP; + + return STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! \brief Send STOP byte at the end of a multi-byte transmission from Master +//! to Slave +//! +//! This function is used by the Master module send STOP at the end of a multi- +//! byte transmission. This function does the following: - Sends a STOP after +//! current transmission is complete +//! +//! \param baseAddress is the base address of the I2C Master module. +//! +//! Modified bits are \b UCTXSTP of \b UCBxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void USCI_I2C_masterMultiByteSendStop(uint16_t baseAddress) +{ + //If interrupts are not used, poll for flags + if (!(HWREG8(baseAddress + OFS_UCBxIE) & UCTXIE)) + //Poll for transmit interrupt flag. + while (!(HWREG8(baseAddress + OFS_UCBxIFG) & UCTXIFG)) ; + + //Send stop condition. + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCTXSTP; +} + +//***************************************************************************** +// +//! \brief Send STOP byte at the end of a multi-byte transmission from Master +//! to Slave with timeout +//! +//! This function is used by the Master module send STOP at the end of a multi- +//! byte transmission. This function does the following: - Sends a STOP after +//! current transmission is complete +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param timeout is the amount of time to wait until giving up +//! +//! Modified bits are \b UCTXSTP of \b UCBxCTL1 register. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the transmission process. +// +//***************************************************************************** +bool USCI_I2C_masterMultiByteSendStopWithTimeout(uint16_t baseAddress, + uint32_t timeout) +{ + + assert(timeout > 0); + + //If interrupts are not used, poll for flags + if (!(HWREG8(baseAddress + OFS_UCBxIE) & UCTXIE)) { + //Poll for transmit interrupt flag. + while ((!(HWREG8(baseAddress + OFS_UCBxIFG) & UCTXIFG)) && --timeout) ; + + //Check if transfer timed out + if (timeout == 0) + return STATUS_FAIL; + } + + //Send stop condition. + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCTXSTP; + + return STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! \brief Starts multi-byte reception at the Master end +//! +//! This function is used by the Master module initiate reception of a single +//! byte. This function does the following: - Sends START +//! +//! \param baseAddress is the base address of the I2C Master module. +//! +//! Modified bits are \b UCTXSTT of \b UCBxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void USCI_I2C_masterMultiByteReceiveStart(uint16_t baseAddress) +{ + //Set USCI in Receive mode + HWREG8(baseAddress + OFS_UCBxCTL1) &= ~UCTR; + //Send start + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCTXSTT; +} + +//***************************************************************************** +// +//! \brief Starts multi-byte reception at the Master end one byte at a time +//! +//! This function is used by the Master module to receive each byte of a multi- +//! byte reception. This function reads currently received byte +//! +//! \param baseAddress is the base address of the I2C Master module. +//! +//! \return Received byte at Master end. +// +//***************************************************************************** +uint8_t USCI_I2C_masterMultiByteReceiveNext(uint16_t baseAddress) +{ + return HWREG8(baseAddress + OFS_UCBxRXBUF); +} + +//***************************************************************************** +// +//! \brief Finishes multi-byte reception at the Master end +//! +//! This function is used by the Master module to initiate completion of a +//! multi-byte reception. This function does the following: - Receives the +//! current byte and initiates the STOP from Master to Slave +//! +//! \param baseAddress is the base address of the I2C Master module. +//! +//! Modified bits are \b UCTXSTP of \b UCBxCTL1 register. +//! +//! \return Received byte at Master end. +// +//***************************************************************************** +uint8_t USCI_I2C_masterMultiByteReceiveFinish(uint16_t baseAddress) +{ + uint8_t receiveData; + + //Send stop condition. + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCTXSTP; + + //Capture data from receive buffer after setting stop bit due to + //MSP430 I2C critical timing. + receiveData = HWREG8(baseAddress + OFS_UCBxRXBUF); + + //Wait for Stop to finish + while (HWREG8(baseAddress + OFS_UCBxCTL1) & UCTXSTP) ; + + //Wait for RX buffer + while (!(HWREG8(baseAddress + OFS_UCBxIFG) & UCRXIFG)) ; + + return receiveData; +} + +//***************************************************************************** +// +//! \brief Finishes multi-byte reception at the Master end with timeout +//! +//! This function is used by the Master module to initiate completion of a +//! multi-byte reception. This function does the following: - Receives the +//! current byte and initiates the STOP from Master to Slave +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param rxData is a pointer to the location to store the received byte at +//! master end +//! \param timeout is the amount of time to wait until giving up +//! +//! Modified bits are \b UCTXSTP of \b UCBxCTL1 register. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the transmission process. +// +//***************************************************************************** +bool USCI_I2C_masterMultiByteReceiveFinishWithTimeout(uint16_t baseAddress, + uint8_t *rxData, + uint32_t timeout + ) +{ + assert(timeout > 0); + + uint32_t timeout2 = timeout; + + //Send stop condition. + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCTXSTP; + + //Capture data from receive buffer after setting stop bit due to + //MSP430 I2C critical timing. + *rxData = (HWREG8(baseAddress + OFS_UCBxRXBUF)); + + //Wait for Stop to finish + while ((HWREG8(baseAddress + OFS_UCBxCTL1) & UCTXSTP) && --timeout) ; + + //Check if transfer timed out + if (timeout == 0) + return STATUS_FAIL; + + // Wait for RX buffer + while ((!(HWREG8(baseAddress + OFS_UCBxIFG) & UCRXIFG)) && --timeout2) ; + + //Check if transfer timed out + if (timeout2 == 0) + return STATUS_FAIL; + + return STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! \brief Sends the STOP at the end of a multi-byte reception at the Master +//! end +//! +//! This function is used by the Master module to initiate STOP +//! +//! \param baseAddress is the base address of the I2C Master module. +//! +//! Modified bits are \b UCTXSTP of \b UCBxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void USCI_I2C_masterMultiByteReceiveStop(uint16_t baseAddress) +{ + //Send stop condition. + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCTXSTP; +} + +//***************************************************************************** +// +//! \brief Initiates a single byte Reception at the Master End +//! +//! This function sends a START and STOP immediately to indicate Single byte +//! reception +//! +//! \param baseAddress is the base address of the I2C Master module. +//! +//! Modified bits are \b GIE of \b SR register; bits \b UCTXSTT and \b UCTXSTP +//! of \b UCBxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void USCI_I2C_masterSingleReceiveStart(uint16_t baseAddress) +{ + //local variable to store GIE status + uint16_t gieStatus; + + //Store current SR register + gieStatus = __get_SR_register() & GIE; + + //Disable global interrupt + __disable_interrupt(); + + //Set USCI in Receive mode + HWREG8(baseAddress + OFS_UCBxCTL1) &= ~UCTR; + + //Send start condition. + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCTXSTT; + + //Poll for Start bit to complete + while (HWREG8(baseAddress + OFS_UCBxCTL1) & UCTXSTT) ; + + //Send stop condition. + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCTXSTP; + + //Reinstate SR register + __bis_SR_register(gieStatus); +} + +//***************************************************************************** +// +//! \brief Initiates a single byte Reception at the Master End with timeout +//! +//! This function sends a START and STOP immediately to indicate Single byte +//! reception +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param timeout is the amount of time to wait until giving up +//! +//! Modified bits are \b GIE of \b SR register; bits \b UCTXSTT and \b UCTXSTP +//! of \b UCBxCTL1 register. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the transmission process. +// +//***************************************************************************** +bool USCI_I2C_masterSingleReceiveStartWithTimeout(uint16_t baseAddress, + uint32_t timeout + ) +{ + //local variable to store GIE status + uint16_t gieStatus; + + assert(timeout > 0); + + //Store current SR register + gieStatus = __get_SR_register() & GIE; + + //Disable global interrupt + __disable_interrupt(); + + //Set USCI in Receive mode + HWREG8(baseAddress + OFS_UCBxCTL1) &= ~UCTR; + + //Send start condition. + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCTXSTT; + + //Poll for Start bit to complete + while ((!(HWREG8(baseAddress + OFS_UCBxIFG) & UCTXSTT)) && --timeout) ; + + //Check if transfer timed out + if (timeout == 0) + return STATUS_FAIL; + + //Send stop condition. + HWREG8(baseAddress + OFS_UCBxCTL1) |= UCTXSTP; + + //Reinstate SR register + __bis_SR_register(gieStatus); + + return STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! \brief Receives a byte that has been sent to the I2C Master Module. +//! +//! This function reads a byte of data from the I2C receive data Register. +//! +//! \param baseAddress is the base address of the I2C module. +//! +//! \return Returns the byte received from by the I2C module, cast as an +//! uint8_t. +// +//***************************************************************************** +uint8_t USCI_I2C_masterSingleReceive(uint16_t baseAddress) +{ + //Polling RXIFG0 if RXIE is not enabled + if (!(HWREG8(baseAddress + OFS_UCBxIE) & UCRXIE)) + while (!(HWREG8(baseAddress + OFS_UCBxIFG) & UCRXIFG)) ; + + //Read a byte. + return HWREG8(baseAddress + OFS_UCBxRXBUF); +} + +//***************************************************************************** +// +//! \brief Returns the address of the RX Buffer of the I2C for the DMA module. +//! +//! Returns the address of the I2C RX Buffer. This can be used in conjunction +//! with the DMA to store the received data directly to memory. +//! +//! \param baseAddress is the base address of the I2C module. +//! +//! \return the address of the RX Buffer +// +//***************************************************************************** +uint32_t USCI_I2C_getReceiveBufferAddressForDMA(uint16_t baseAddress) +{ + return baseAddress + OFS_UCBxRXBUF; +} + +//***************************************************************************** +// +//! \brief Returns the address of the TX Buffer of the I2C for the DMA module. +//! +//! Returns the address of the I2C TX Buffer. This can be used in conjunction +//! with the DMA to obtain transmitted data directly from memory. +//! +//! \param baseAddress is the base address of the I2C module. +//! +//! \return the address of the TX Buffer +// +//***************************************************************************** +uint32_t USCI_I2C_getTransmitBufferAddressForDMA(uint16_t baseAddress) +{ + return baseAddress + OFS_UCBxTXBUF; +} + + +#endif +//***************************************************************************** +// +//! Close the doxygen group for usci_i2c_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/usci_i2c.h b/source/driverlib/MSP430F5xx_6xx/usci_i2c.h new file mode 100644 index 0000000..9b930c2 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/usci_i2c.h @@ -0,0 +1,268 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// usci_i2c.h - Driver for the USCI_I2C Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_USCI_I2C_H__ +#define __MSP430WARE_USCI_I2C_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_USCI_Bx__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//****************************************************************************** +// +// The following is a struct that is passed to USCI_I2C_initMaster() +// +//****************************************************************************** +typedef struct USCI_I2C_initMasterParam { + uint8_t selectClockSource; + uint32_t i2cClk; + uint32_t dataRate; +} USCI_I2C_initMasterParam; + +//***************************************************************************** +// +// The following are values that can be passed to the selectClockSource +// parameter for functions: USCI_I2C_masterInit(). +// +//***************************************************************************** +#define USCI_I2C_CLOCKSOURCE_ACLK UCSSEL__ACLK +#define USCI_I2C_CLOCKSOURCE_SMCLK UCSSEL__SMCLK + +//***************************************************************************** +// +// The following are values that can be passed to the dataRate parameter for +// functions: USCI_I2C_masterInit(). +// +//***************************************************************************** +#define USCI_I2C_SET_DATA_RATE_400KBPS 400000 +#define USCI_I2C_SET_DATA_RATE_100KBPS 100000 + +//***************************************************************************** +// +// The following are values that can be passed to the mode parameter for +// functions: USCI_I2C_setMode(). +// +//***************************************************************************** +#define USCI_I2C_TRANSMIT_MODE UCTR +#define USCI_I2C_RECEIVE_MODE 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the mask parameter for +// functions: USCI_I2C_enableInterrupt(), USCI_I2C_disableInterrupt(), +// USCI_I2C_clearInterruptFlag(), and USCI_I2C_getInterruptStatus() as well as +// returned by the USCI_I2C_getInterruptStatus() function. +// +//***************************************************************************** +#define USCI_I2C_STOP_INTERRUPT UCSTPIE +#define USCI_I2C_START_INTERRUPT UCSTTIE +#define USCI_I2C_RECEIVE_INTERRUPT UCRXIE +#define USCI_I2C_TRANSMIT_INTERRUPT UCTXIE +#define USCI_I2C_NAK_INTERRUPT UCNACKIE +#define USCI_I2C_ARBITRATIONLOST_INTERRUPT UCALIE + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the USCI_I2C_isBusy() function and the +// USCI_I2C_isBusBusy() function. +// +//***************************************************************************** +#define USCI_I2C_BUS_BUSY UCBBUSY +#define USCI_I2C_BUS_NOT_BUSY 0x00 + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the USCI_I2C_masterIsStartSent() function. +// +//***************************************************************************** +#define USCI_I2C_SENDING_START UCTXSTT +#define USCI_I2C_START_SEND_COMPLETE 0x00 + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the USCI_I2C_masterIsStopSent() function. +// +//***************************************************************************** +#define USCI_I2C_SENDING_STOP UCTXSTP +#define USCI_I2C_STOP_SEND_COMPLETE 0x00 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void USCI_I2C_initMaster(uint16_t baseAddress, + USCI_I2C_initMasterParam *param); + +extern void USCI_I2C_slaveInit(uint16_t baseAddress, + uint8_t slaveAddress); + +extern void USCI_I2C_enable(uint16_t baseAddress); + +extern void USCI_I2C_disable(uint16_t baseAddress); + +extern void USCI_I2C_setSlaveAddress(uint16_t baseAddress, + uint8_t slaveAddress); + +extern void USCI_I2C_setMode(uint16_t baseAddress, + uint8_t mode); + +extern void USCI_I2C_slaveDataPut(uint16_t baseAddress, + uint8_t transmitData); + +extern uint8_t USCI_I2C_slaveDataGet(uint16_t baseAddress); + +extern uint8_t USCI_I2C_isBusBusy(uint16_t baseAddress); + +extern uint8_t USCI_I2C_isBusy(uint16_t baseAddress); + +extern uint8_t USCI_I2C_masterIsStopSent(uint16_t baseAddress); + +extern uint8_t USCI_I2C_masterIsStartSent(uint16_t baseAddress); + +extern void USCI_I2C_masterSendStart(uint16_t baseAddress); + +extern void USCI_I2C_enableInterrupt(uint16_t baseAddress, + uint8_t mask); + +extern void USCI_I2C_disableInterrupt(uint16_t baseAddress, + uint8_t mask); + +extern void USCI_I2C_clearInterruptFlag(uint16_t baseAddress, + uint8_t mask); + +extern uint8_t USCI_I2C_getInterruptStatus(uint16_t baseAddress, + uint8_t mask); + +extern void USCI_I2C_masterSendSingleByte(uint16_t baseAddress, + uint8_t txData); + +extern bool USCI_I2C_masterSendSingleByteWithTimeout(uint16_t baseAddress, + uint8_t txData, + uint32_t timeout); + +extern void USCI_I2C_masterMultiByteSendStart(uint16_t baseAddress, + uint8_t txData); + +extern bool USCI_I2C_masterMultiByteSendStartWithTimeout(uint16_t baseAddress, + uint8_t txData, + uint32_t timeout); + +extern void USCI_I2C_masterMultiByteSendNext(uint16_t baseAddress, + uint8_t txData); + +extern bool USCI_I2C_masterMultiByteSendNextWithTimeout(uint16_t baseAddress, + uint8_t txData, + uint32_t timeout); + +extern void USCI_I2C_masterMultiByteSendFinish(uint16_t baseAddress, + uint8_t txData); + +extern bool USCI_I2C_masterMultiByteSendFinishWithTimeout(uint16_t baseAddress, + uint8_t txData, + uint32_t timeout); + +extern void USCI_I2C_masterMultiByteSendStop(uint16_t baseAddress); + +extern bool USCI_I2C_masterMultiByteSendStopWithTimeout(uint16_t baseAddress, + uint32_t timeout); + +extern void USCI_I2C_masterMultiByteReceiveStart(uint16_t baseAddress); + +extern uint8_t USCI_I2C_masterMultiByteReceiveNext(uint16_t baseAddress); + +extern uint8_t USCI_I2C_masterMultiByteReceiveFinish(uint16_t baseAddress); + +extern bool USCI_I2C_masterMultiByteReceiveFinishWithTimeout(uint16_t baseAddress, + uint8_t *rxData, + uint32_t timeout); + +extern void USCI_I2C_masterMultiByteReceiveStop(uint16_t baseAddress); + +extern void USCI_I2C_masterSingleReceiveStart(uint16_t baseAddress); + +extern bool USCI_I2C_masterSingleReceiveStartWithTimeout(uint16_t baseAddress, + uint32_t timeout); + +extern uint8_t USCI_I2C_masterSingleReceive(uint16_t baseAddress); + +extern uint32_t USCI_I2C_getReceiveBufferAddressForDMA(uint16_t baseAddress); + +extern uint32_t USCI_I2C_getTransmitBufferAddressForDMA(uint16_t baseAddress); + +//***************************************************************************** +// +// DEPRECATED APIS. +// +//***************************************************************************** +#define USCI_I2C_masterIsSTOPSent USCI_I2C_masterIsStopSent + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +extern void USCI_I2C_masterInit(uint16_t baseAddress, + uint8_t selectClockSource, + uint32_t i2cClk, + uint32_t dataRate); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_USCI_I2C_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/usci_spi.c b/source/driverlib/MSP430F5xx_6xx/usci_spi.c new file mode 100644 index 0000000..1762ef7 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/usci_spi.c @@ -0,0 +1,611 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// usci_spi.c - Driver for the usci_spi Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup usci_spi_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_USCI_Ax__ +#include "usci_spi.h" + +#include + +//***************************************************************************** +// +//! \brief DEPRECATED - Initializes the SPI Master block. +//! +//! Upon successful initialization of the SPI master block, this function will +//! have set the bus speed for the master, but the SPI Master block still +//! remains disabled and must be enabled with USCI_SPI_enable() +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param selectClockSource selects Clock source. +//! Valid values are: +//! - \b USCI_SPI_CLOCKSOURCE_ACLK +//! - \b USCI_SPI_CLOCKSOURCE_SMCLK +//! \param clockSourceFrequency is the frequency of the selected clock source +//! \param desiredSpiClock is the desired clock rate for SPI communication +//! \param msbFirst controls the direction of the receive and transmit shift +//! register. +//! Valid values are: +//! - \b USCI_SPI_MSB_FIRST +//! - \b USCI_SPI_LSB_FIRST [Default] +//! \param clockPhase is clock phase select. +//! Valid values are: +//! - \b USCI_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT [Default] +//! - \b USCI_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT +//! \param clockPolarity +//! Valid values are: +//! - \b USCI_SPI_CLOCKPOLARITY_INACTIVITY_HIGH +//! - \b USCI_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default] +//! +//! Modified bits are \b UCCKPH, \b UCCKPL, \b UC7BIT and \b UCMSB of \b +//! UCAxCTL0 register; bits \b UCSSELx and \b UCSWRST of \b UCAxCTL1 register. +//! +//! \return STATUS_SUCCESS +// +//***************************************************************************** +bool USCI_SPI_masterInit(uint16_t baseAddress, + uint8_t selectClockSource, + uint32_t clockSourceFrequency, + uint32_t desiredSpiClock, + uint8_t msbFirst, + uint8_t clockPhase, + uint8_t clockPolarity + ) +{ + USCI_SPI_initMasterParam param = { 0 }; + + param.selectClockSource = selectClockSource; + param.clockSourceFrequency = clockSourceFrequency; + param.desiredSpiClock = desiredSpiClock; + param.msbFirst = msbFirst; + param.clockPhase = clockPhase; + param.clockPolarity = clockPolarity; + + return USCI_SPI_initMaster(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Initializes the SPI Master block. +//! +//! Upon successful initialization of the SPI master block, this function will +//! have set the bus speed for the master, but the SPI Master block still +//! remains disabled and must be enabled with USCI_SPI_enable() +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param param is the pointer to struct for master initialization. +//! +//! Modified bits are \b UCCKPH, \b UCCKPL, \b UC7BIT and \b UCMSB of \b +//! UCAxCTL0 register; bits \b UCSSELx and \b UCSWRST of \b UCAxCTL1 register. +//! +//! \return STATUS_SUCCESS +// +//***************************************************************************** +bool USCI_SPI_initMaster(uint16_t baseAddress, USCI_SPI_initMasterParam *param) +{ + assert(param != 0); + + assert( + (USCI_SPI_CLOCKSOURCE_ACLK == param->selectClockSource) || + (USCI_SPI_CLOCKSOURCE_SMCLK == param->selectClockSource) + ); + + assert((USCI_SPI_MSB_FIRST == param->msbFirst) || + (USCI_SPI_LSB_FIRST == param->msbFirst) + ); + + assert( (USCI_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT == param->clockPhase) || + (USCI_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT == param->clockPhase) + ); + + assert( (USCI_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == param->clockPolarity) || + (USCI_SPI_CLOCKPOLARITY_INACTIVITY_LOW == param->clockPolarity) + ); + + //Disable the USCI Module + HWREG8(baseAddress + OFS_UCAxCTL1) |= UCSWRST; + + //Reset OFS_UCAxCTL0 values + HWREG8(baseAddress + OFS_UCAxCTL0) &= ~(UCCKPH + UCCKPL + UC7BIT + UCMSB + + UCMST + UCMODE_3 + UCSYNC); + + //Reset OFS_UCAxCTL1 values + HWREG8(baseAddress + OFS_UCAxCTL1) &= ~(UCSSEL_3); + + //Select Clock + HWREG8(baseAddress + OFS_UCAxCTL1) |= param->selectClockSource; + + HWREG16(baseAddress + OFS_UCAxBRW) = + (uint16_t)(param->clockSourceFrequency / param->desiredSpiClock); + + /* + * Configure as SPI master mode. + * Clock phase select, polarity, msb + * UCMST = Master mode + * UCSYNC = Synchronous mode + * UCMODE_0 = 3-pin SPI + */ + HWREG8(baseAddress + OFS_UCAxCTL0) |= ( + param->msbFirst + + param->clockPhase + + param->clockPolarity + + UCMST + + UCSYNC + + UCMODE_0 + ); + //No modulation + HWREG8(baseAddress + OFS_UCAxMCTL) = 0; + + return STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! \brief DEPRECATED - Initializes the SPI Master clock.At the end of this +//! function call, SPI module is left enabled. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param clockSourceFrequency is the frequency of the selected clock source +//! \param desiredSpiClock is the desired clock rate for SPI communication +//! +//! Modified bits of \b UCAxBRW register. +//! +//! \return None +// +//***************************************************************************** +void USCI_SPI_masterChangeClock(uint16_t baseAddress, + uint32_t clockSourceFrequency, + uint32_t desiredSpiClock + ) +{ + USCI_SPI_changeMasterClockParam param = { 0 }; + + param.clockSourceFrequency = clockSourceFrequency; + param.desiredSpiClock = desiredSpiClock; + + USCI_SPI_changeMasterClock(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Initializes the SPI Master clock.At the end of this function call, +//! SPI module is left enabled. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param param is the pointer to struct for master clock setting. +//! +//! Modified bits of \b UCAxBRW register. +//! +//! \return None +// +//***************************************************************************** +void USCI_SPI_changeMasterClock(uint16_t baseAddress, + USCI_SPI_changeMasterClockParam *param) +{ + assert(param != 0); + + //Disable the USCI Module + HWREG8(baseAddress + OFS_UCAxCTL1) |= UCSWRST; + + HWREG8(baseAddress + OFS_UCAxBRW) = + (uint16_t)(param->clockSourceFrequency / param->desiredSpiClock); + + //Reset the UCSWRST bit to enable the USCI Module + HWREG8(baseAddress + OFS_UCAxCTL1) &= ~(UCSWRST); +} +//***************************************************************************** +// +//! \brief Initializes the SPI Slave block. +//! +//! Upon successful initialization of the SPI slave block, this function will +//! have initialized the slave block, but the SPI Slave block still remains +//! disabled and must be enabled with USCI_SPI_enable() +//! +//! \param baseAddress is the base address of the SPI Slave module. +//! \param msbFirst controls the direction of the receive and transmit shift +//! register. +//! Valid values are: +//! - \b USCI_SPI_MSB_FIRST +//! - \b USCI_SPI_LSB_FIRST [Default] +//! \param clockPhase is clock phase select. +//! Valid values are: +//! - \b USCI_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT [Default] +//! - \b USCI_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT +//! \param clockPolarity +//! Valid values are: +//! - \b USCI_SPI_CLOCKPOLARITY_INACTIVITY_HIGH +//! - \b USCI_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default] +//! +//! Modified bits are \b UCMSB, \b UCMST, \b UC7BIT, \b UCCKPL, \b UCCKPH and +//! \b UCMODE of \b UCAxCTL0 register; bits \b UCSWRST of \b UCAxCTL1 register. +//! +//! \return STATUS_SUCCESS +// +//***************************************************************************** +bool USCI_SPI_slaveInit(uint16_t baseAddress, + uint8_t msbFirst, + uint8_t clockPhase, + uint8_t clockPolarity + ) +{ + assert( + (USCI_SPI_MSB_FIRST == msbFirst) || + (USCI_SPI_LSB_FIRST == msbFirst) + ); + + assert( + (USCI_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT == clockPhase) || + (USCI_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT == clockPhase) + ); + + assert( + (USCI_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == clockPolarity) || + (USCI_SPI_CLOCKPOLARITY_INACTIVITY_LOW == clockPolarity) + ); + + //Disable USCI Module + HWREG8(baseAddress + OFS_UCAxCTL1) |= UCSWRST; + + //Reset OFS_UCAxCTL0 register + HWREG8(baseAddress + OFS_UCAxCTL0) &= ~(UCMSB + + UC7BIT + + UCMST + + UCCKPL + + UCCKPH + + UCMODE_3 + ); + + //Clock polarity, phase select, msbFirst, SYNC, Mode0 + HWREG8(baseAddress + OFS_UCAxCTL0) |= (clockPhase + + clockPolarity + + msbFirst + + UCSYNC + + UCMODE_0 + ); + + return STATUS_SUCCESS; +} + +//***************************************************************************** +// +//! \brief Changes the SPI clock phase and polarity.At the end of this function +//! call, SPI module is left enabled. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param clockPhase is clock phase select. +//! Valid values are: +//! - \b USCI_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT [Default] +//! - \b USCI_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT +//! \param clockPolarity +//! Valid values are: +//! - \b USCI_SPI_CLOCKPOLARITY_INACTIVITY_HIGH +//! - \b USCI_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default] +//! +//! Modified bits are \b UCCKPL and \b UCCKPH of \b UCAxCTL0 register. +//! +//! \return None +// +//***************************************************************************** +void USCI_SPI_changeClockPhasePolarity(uint16_t baseAddress, + uint8_t clockPhase, + uint8_t clockPolarity + ) +{ + + assert( (USCI_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == clockPolarity) || + (USCI_SPI_CLOCKPOLARITY_INACTIVITY_LOW == clockPolarity) + ); + + //Disable the USCI Module + HWREG8(baseAddress + OFS_UCAxCTL1) |= UCSWRST; + + HWREG8(baseAddress + OFS_UCAxCTL0) &= ~(UCCKPH + UCCKPL); + + HWREG8(baseAddress + OFS_UCAxCTL0) |= ( + clockPhase + + clockPolarity + ); + + //Reset the UCSWRST bit to enable the USCI Module + HWREG8(baseAddress + OFS_UCAxCTL1) &= ~(UCSWRST); +} + +//***************************************************************************** +// +//! \brief Transmits a byte from the SPI Module. +//! +//! This function will place the supplied data into SPI transmit data register +//! to start transmission +//! +//! \param baseAddress is the base address of the SPI module. +//! \param transmitData data to be transmitted from the SPI module +//! +//! \return None +// +//***************************************************************************** +void USCI_SPI_transmitData( uint16_t baseAddress, + uint8_t transmitData + ) +{ + HWREG8(baseAddress + OFS_UCAxTXBUF) = transmitData; +} + +//***************************************************************************** +// +//! \brief Receives a byte that has been sent to the SPI Module. +//! +//! This function reads a byte of data from the SPI receive data Register. +//! +//! \param baseAddress is the base address of the SPI module. +//! +//! \return Returns the byte received from by the SPI module, cast as an +//! uint8_t. +// +//***************************************************************************** +uint8_t USCI_SPI_receiveData(uint16_t baseAddress) +{ + return HWREG8(baseAddress + OFS_UCAxRXBUF); +} + +//***************************************************************************** +// +//! \brief Enables individual SPI interrupt sources. +//! +//! Enables the indicated SPI interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. Does not clear interrupt flags. +//! +//! \param baseAddress is the base address of the SPI module. +//! \param mask is the bit mask of the interrupt sources to be enabled. +//! Mask value is the logical OR of any of the following: +//! - \b USCI_SPI_TRANSMIT_INTERRUPT +//! - \b USCI_SPI_RECEIVE_INTERRUPT +//! +//! Modified bits of \b UCAxIE register. +//! +//! \return None +// +//***************************************************************************** +void USCI_SPI_enableInterrupt(uint16_t baseAddress, + uint8_t mask + ) +{ + assert( 0x00 != mask && (USCI_SPI_RECEIVE_INTERRUPT + + USCI_SPI_TRANSMIT_INTERRUPT + )); + + HWREG8(baseAddress + OFS_UCAxIE) |= mask; +} + +//***************************************************************************** +// +//! \brief Disables individual SPI interrupt sources. +//! +//! Disables the indicated SPI interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! \param baseAddress is the base address of the SPI module. +//! \param mask is the bit mask of the interrupt sources to be disabled. +//! Mask value is the logical OR of any of the following: +//! - \b USCI_SPI_TRANSMIT_INTERRUPT +//! - \b USCI_SPI_RECEIVE_INTERRUPT +//! +//! Modified bits of \b UCAxIE register. +//! +//! \return None +// +//***************************************************************************** +void USCI_SPI_disableInterrupt(uint16_t baseAddress, + uint8_t mask + ) +{ + assert( 0x00 != mask && (USCI_SPI_RECEIVE_INTERRUPT + + USCI_SPI_TRANSMIT_INTERRUPT + )); + + HWREG8(baseAddress + OFS_UCAxIE) &= ~mask; +} + +//***************************************************************************** +// +//! \brief Gets the current SPI interrupt status. +//! +//! This returns the interrupt status for the SPI module based on which flag is +//! passed. +//! +//! \param baseAddress is the base address of the SPI module. +//! \param mask is the masked interrupt flag status to be returned. +//! Mask value is the logical OR of any of the following: +//! - \b USCI_SPI_TRANSMIT_INTERRUPT +//! - \b USCI_SPI_RECEIVE_INTERRUPT +//! +//! \return The current interrupt status as the mask of the set flags +//! Return Logical OR of any of the following: +//! - \b USCI_SPI_TRANSMIT_INTERRUPT +//! - \b USCI_SPI_RECEIVE_INTERRUPT +//! \n indicating the status of the masked interrupts +// +//***************************************************************************** +uint8_t USCI_SPI_getInterruptStatus(uint16_t baseAddress, + uint8_t mask + ) +{ + assert( 0x00 != mask && (USCI_SPI_RECEIVE_INTERRUPT + + USCI_SPI_TRANSMIT_INTERRUPT + )); + + return HWREG8(baseAddress + OFS_UCAxIFG) & mask; +} + +//***************************************************************************** +// +//! \brief Clears the selected SPI interrupt status flag. +//! +//! \param baseAddress is the base address of the SPI module. +//! \param mask is the masked interrupt flag to be cleared. +//! Mask value is the logical OR of any of the following: +//! - \b USCI_SPI_TRANSMIT_INTERRUPT +//! - \b USCI_SPI_RECEIVE_INTERRUPT +//! +//! Modified bits of \b UCAxIFG register. +//! +//! \return None +// +//***************************************************************************** +void USCI_SPI_clearInterruptFlag(uint16_t baseAddress, + uint8_t mask + ) +{ + assert( 0x00 != mask && (USCI_SPI_RECEIVE_INTERRUPT + + USCI_SPI_TRANSMIT_INTERRUPT + )); + + HWREG8(baseAddress + OFS_UCAxIFG) &= ~mask; +} + +//***************************************************************************** +// +//! \brief Enables the SPI block. +//! +//! This will enable operation of the SPI block. +//! +//! \param baseAddress is the base address of the USCI SPI module. +//! +//! Modified bits are \b UCSWRST of \b UCAxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void USCI_SPI_enable(uint16_t baseAddress) +{ + //Reset the UCSWRST bit to enable the USCI Module + HWREG8(baseAddress + OFS_UCAxCTL1) &= ~(UCSWRST); +} + +//***************************************************************************** +// +//! \brief Disables the SPI block. +//! +//! This will disable operation of the SPI block. +//! +//! \param baseAddress is the base address of the USCI SPI module. +//! +//! Modified bits are \b UCSWRST of \b UCAxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void USCI_SPI_disable(uint16_t baseAddress) +{ + //Set the UCSWRST bit to disable the USCI Module + HWREG8(baseAddress + OFS_UCAxCTL1) |= UCSWRST; +} + +//***************************************************************************** +// +//! \brief Returns the address of the RX Buffer of the SPI for the DMA module. +//! +//! Returns the address of the SPI RX Buffer. This can be used in conjunction +//! with the DMA to store the received data directly to memory. +//! +//! \param baseAddress is the base address of the SPI module. +//! +//! \return the address of the RX Buffer +// +//***************************************************************************** +uint32_t USCI_SPI_getReceiveBufferAddressForDMA(uint16_t baseAddress) +{ + return baseAddress + OFS_UCAxRXBUF; +} + +//***************************************************************************** +// +//! \brief Returns the address of the TX Buffer of the SPI for the DMA module. +//! +//! Returns the address of the SPI TX Buffer. This can be used in conjunction +//! with the DMA to obtain transmitted data directly from memory. +//! +//! \param baseAddress is the base address of the SPI module. +//! +//! \return the address of the TX Buffer +// +//***************************************************************************** +uint32_t USCI_SPI_getTransmitBufferAddressForDMA(uint16_t baseAddress) +{ + return baseAddress + OFS_UCAxTXBUF; +} + +//***************************************************************************** +// +//! \brief Indicates whether or not the SPI bus is busy. +//! +//! This function returns an indication of whether or not the SPI bus is +//! busy.This function checks the status of the bus via UCBBUSY bit +//! +//! \param baseAddress is the base address of the SPI module. +//! +//! \return USCI_SPI_BUSY if the SPI module transmitting or receiving is busy; +//! otherwise, returns USCI_SPI_NOT_BUSY. +//! Return one of the following: +//! - \b USCI_SPI_BUSY +//! - \b USCI_SPI_NOT_BUSY +//! \n indicating if the USCI_SPI is busy +// +//***************************************************************************** +uint8_t USCI_SPI_isBusy(uint16_t baseAddress) +{ + //Return the bus busy status. + return HWREG8(baseAddress + OFS_UCAxSTAT) & UCBUSY; +} + + +#endif +//***************************************************************************** +// +//! Close the doxygen group for usci_spi_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/usci_spi.h b/source/driverlib/MSP430F5xx_6xx/usci_spi.h new file mode 100644 index 0000000..e176fa8 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/usci_spi.h @@ -0,0 +1,212 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// usci_spi.h - Driver for the USCI_SPI Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_USCI_SPI_H__ +#define __MSP430WARE_USCI_SPI_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_USCI_Ax__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//****************************************************************************** +// +// The following is a struct that is passed to USCI_SPI_initMaster() +// +//****************************************************************************** +typedef struct USCI_SPI_initMasterParam { + uint8_t selectClockSource; + uint32_t clockSourceFrequency; + uint32_t desiredSpiClock; + uint8_t msbFirst; + uint8_t clockPhase; + uint8_t clockPolarity; +} USCI_SPI_initMasterParam; + +//****************************************************************************** +// +// The following is a struct that is passed to USCI_SPI_changeMasterParam() +// +//****************************************************************************** +typedef struct USCI_SPI_ChangeMasterClockParam { + uint32_t clockSourceFrequency; + uint32_t desiredSpiClock; +} USCI_SPI_changeMasterClockParam; + +//***************************************************************************** +// +// The following are values that can be passed to the clockPhase parameter for +// functions: USCI_SPI_masterInit(), USCI_SPI_slaveInit(), and +// USCI_SPI_changeClockPhasePolarity(). +// +//***************************************************************************** +#define USCI_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT 0x00 +#define USCI_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT UCCKPH + +//***************************************************************************** +// +// The following are values that can be passed to the msbFirst parameter for +// functions: USCI_SPI_masterInit(), and USCI_SPI_slaveInit(). +// +//***************************************************************************** +#define USCI_SPI_MSB_FIRST UCMSB +#define USCI_SPI_LSB_FIRST 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the clockPolarity parameter +// for functions: USCI_SPI_masterInit(), USCI_SPI_slaveInit(), and +// USCI_SPI_changeClockPhasePolarity(). +// +//***************************************************************************** +#define USCI_SPI_CLOCKPOLARITY_INACTIVITY_HIGH UCCKPL +#define USCI_SPI_CLOCKPOLARITY_INACTIVITY_LOW 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the selectClockSource +// parameter for functions: USCI_SPI_masterInit(). +// +//***************************************************************************** +#define USCI_SPI_CLOCKSOURCE_ACLK UCSSEL__ACLK +#define USCI_SPI_CLOCKSOURCE_SMCLK UCSSEL__SMCLK + +//***************************************************************************** +// +// The following are values that can be passed to the mask parameter for +// functions: USCI_SPI_enableInterrupt(), USCI_SPI_disableInterrupt(), +// USCI_SPI_getInterruptStatus(), and USCI_SPI_clearInterruptFlag() as well as +// returned by the USCI_SPI_getInterruptStatus() function. +// +//***************************************************************************** +#define USCI_SPI_TRANSMIT_INTERRUPT UCTXIE +#define USCI_SPI_RECEIVE_INTERRUPT UCRXIE + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the USCI_SPI_isBusy() function. +// +//***************************************************************************** +#define USCI_SPI_BUSY UCBUSY +#define USCI_SPI_NOT_BUSY 0x00 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern bool USCI_SPI_initMaster(uint16_t baseAddress, + USCI_SPI_initMasterParam *param); + +extern void USCI_SPI_changeMasterClock(uint16_t baseAddress, + USCI_SPI_changeMasterClockParam *param); + +extern bool USCI_SPI_slaveInit(uint16_t baseAddress, + uint8_t msbFirst, + uint8_t clockPhase, + uint8_t clockPolarity); + +extern void USCI_SPI_changeClockPhasePolarity(uint16_t baseAddress, + uint8_t clockPhase, + uint8_t clockPolarity); + +extern void USCI_SPI_transmitData(uint16_t baseAddress, + uint8_t transmitData); + +extern uint8_t USCI_SPI_receiveData(uint16_t baseAddress); + +extern void USCI_SPI_enableInterrupt(uint16_t baseAddress, + uint8_t mask); + +extern void USCI_SPI_disableInterrupt(uint16_t baseAddress, + uint8_t mask); + +extern uint8_t USCI_SPI_getInterruptStatus(uint16_t baseAddress, + uint8_t mask); + +extern void USCI_SPI_clearInterruptFlag(uint16_t baseAddress, + uint8_t mask); + +extern void USCI_SPI_enable(uint16_t baseAddress); + +extern void USCI_SPI_disable(uint16_t baseAddress); + +extern uint32_t USCI_SPI_getReceiveBufferAddressForDMA(uint16_t baseAddress); + +extern uint32_t USCI_SPI_getTransmitBufferAddressForDMA(uint16_t baseAddress); + +extern uint8_t USCI_SPI_isBusy(uint16_t baseAddress); + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +extern bool USCI_SPI_masterInit(uint16_t baseAddress, + uint8_t selectClockSource, + uint32_t clockSourceFrequency, + uint32_t desiredSpiClock, + uint8_t msbFirst, + uint8_t clockPhase, + uint8_t clockPolarity); + +extern void USCI_SPI_masterChangeClock(uint16_t baseAddress, + uint32_t clockSourceFrequency, + uint32_t desiredSpiClock); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_USCI_SPI_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/usci_uart.c b/source/driverlib/MSP430F5xx_6xx/usci_uart.c new file mode 100644 index 0000000..6281e7d --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/usci_uart.c @@ -0,0 +1,673 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// usci_uart.c - Driver for the usci_uart Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup usci_uart_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_USCI_Ax__ +#include "usci_uart.h" + +#include + +//***************************************************************************** +// +//! \brief DEPRECATED - Advanced initialization routine for the UART block. The +//! values to be written into the clockPrescalar, firstModReg, secondModReg and +//! overSampling parameters should be pre-computed and passed into the +//! initialization function. +//! +//! Upon successful initialization of the UART block, this function will have +//! initialized the module, but the UART block still remains disabled and must +//! be enabled with USCI_UART_enable(). To calculate values for clockPrescalar, +//! firstModReg, secondModReg and overSampling please use the link below. +//! +//! http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSP430BaudRateConverter/index.html +//! +//! \param baseAddress is the base address of the USCI_UART module. +//! \param selectClockSource selects Clock source. +//! Valid values are: +//! - \b USCI_UART_CLOCKSOURCE_SMCLK +//! - \b USCI_UART_CLOCKSOURCE_ACLK +//! \param clockPrescalar is the value to be written into UCBRx bits +//! \param firstModReg is First modulation stage register setting. This value +//! is a pre-calculated value which can be obtained from the Device +//! Users Guide. This value is written into UCBRFx bits of UCAxMCTLW. +//! \param secondModReg is Second modulation stage register setting. This value +//! is a pre-calculated value which can be obtained from the Device +//! Users Guide. This value is written into UCBRSx bits of UCAxMCTLW. +//! \param parity is the desired parity. +//! Valid values are: +//! - \b USCI_UART_NO_PARITY [Default] +//! - \b USCI_UART_ODD_PARITY +//! - \b USCI_UART_EVEN_PARITY +//! \param msborLsbFirst controls direction of receive and transmit shift +//! register. +//! Valid values are: +//! - \b USCI_UART_MSB_FIRST +//! - \b USCI_UART_LSB_FIRST [Default] +//! \param numberofStopBits indicates one/two STOP bits +//! Valid values are: +//! - \b USCI_UART_ONE_STOP_BIT [Default] +//! - \b USCI_UART_TWO_STOP_BITS +//! \param uartMode selects the mode of operation +//! Valid values are: +//! - \b USCI_UART_MODE [Default] +//! - \b USCI_UART_IDLE_LINE_MULTI_PROCESSOR_MODE +//! - \b USCI_UART_ADDRESS_BIT_MULTI_PROCESSOR_MODE +//! - \b USCI_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE +//! \param overSampling indicates low frequency or oversampling baud generation +//! Valid values are: +//! - \b USCI_UART_OVERSAMPLING_BAUDRATE_GENERATION +//! - \b USCI_UART_LOW_FREQUENCY_BAUDRATE_GENERATION +//! +//! Modified bits are \b UCPEN, \b UCPAR, \b UCMSB, \b UC7BIT, \b UCSPB, \b +//! UCMODEx and \b UCSYNC of \b UCAxCTL0 register; bits \b UCSSELx and \b +//! UCSWRST of \b UCAxCTL1 register. +//! +//! \return STATUS_SUCCESS or STATUS_FAIL of the initialization process +// +//***************************************************************************** +bool USCI_UART_initAdvance( uint16_t baseAddress, + uint8_t selectClockSource, + uint16_t clockPrescalar, + uint8_t firstModReg, + uint8_t secondModReg, + uint8_t parity, + uint8_t msborLsbFirst, + uint8_t numberofStopBits, + uint8_t uartMode, + uint8_t overSampling + ) +{ + USCI_UART_initParam param = { 0 }; + + param.selectClockSource = selectClockSource; + param.clockPrescalar = clockPrescalar; + param.firstModReg = firstModReg; + param.secondModReg = secondModReg; + param.parity = parity; + param.msborLsbFirst = msborLsbFirst; + param.numberofStopBits = numberofStopBits; + param.uartMode = uartMode; + param.overSampling = overSampling; + + return USCI_UART_init(baseAddress, ¶m); +} + +//***************************************************************************** +// +//! \brief Advanced initialization routine for the UART block. The values to be +//! written into the clockPrescalar, firstModReg, secondModReg and overSampling +//! parameters should be pre-computed and passed into the initialization +//! function. +//! +//! Upon successful initialization of the UART block, this function will have +//! initialized the module, but the UART block still remains disabled and must +//! be enabled with USCI_UART_enable(). To calculate values for clockPrescalar, +//! firstModReg, secondModReg and overSampling please use the link below. +//! +//! http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSP430BaudRateConverter/index.html +//! +//! \param baseAddress is the base address of the USCI_UART module. +//! \param param is the pointer to struct for initialization. +//! +//! Modified bits are \b UCPEN, \b UCPAR, \b UCMSB, \b UC7BIT, \b UCSPB, \b +//! UCMODEx and \b UCSYNC of \b UCAxCTL0 register; bits \b UCSSELx and \b +//! UCSWRST of \b UCAxCTL1 register. +//! +//! \return STATUS_SUCCESS or STATUS_FAIL of the initialization process +// +//***************************************************************************** +bool USCI_UART_init(uint16_t baseAddress, USCI_UART_initParam *param) +{ + assert(param != 0); + + assert( + (USCI_UART_MODE == param->uartMode) || + (USCI_UART_IDLE_LINE_MULTI_PROCESSOR_MODE == param->uartMode) || + (USCI_UART_ADDRESS_BIT_MULTI_PROCESSOR_MODE == param->uartMode) || + (USCI_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE == param->uartMode) + ); + + assert( + (USCI_UART_CLOCKSOURCE_ACLK == param->selectClockSource) || + (USCI_UART_CLOCKSOURCE_SMCLK == param->selectClockSource) + ); + + assert( + (USCI_UART_MSB_FIRST == param->msborLsbFirst) || + (USCI_UART_LSB_FIRST == param->msborLsbFirst) + ); + + assert( + (USCI_UART_ONE_STOP_BIT == param->numberofStopBits) || + (USCI_UART_TWO_STOP_BITS == param->numberofStopBits) + ); + + assert( + (USCI_UART_NO_PARITY == param->parity) || + (USCI_UART_ODD_PARITY == param->parity) || + (USCI_UART_EVEN_PARITY == param->parity) + ); + + bool retVal = STATUS_SUCCESS; + + //Disable the USCI Module + HWREG8(baseAddress + OFS_UCAxCTL1) |= UCSWRST; + + //Clock source select + HWREG8(baseAddress + OFS_UCAxCTL1) &= ~UCSSEL_3; + HWREG8(baseAddress + OFS_UCAxCTL1) |= param->selectClockSource; + + //MSB, LSB select + HWREG8(baseAddress + OFS_UCAxCTL0) &= ~UCMSB; + HWREG8(baseAddress + OFS_UCAxCTL0) |= param->msborLsbFirst; + + //UCSPB = 0(1 stop bit) OR 1(2 stop bits) + HWREG8(baseAddress + OFS_UCAxCTL0) &= ~UCSPB; + HWREG8(baseAddress + OFS_UCAxCTL0) |= param->numberofStopBits; + + //Parity + switch (param->parity) { + case USCI_UART_NO_PARITY: + //No Parity + HWREG8(baseAddress + OFS_UCAxCTL0) &= ~UCPEN; + break; + case USCI_UART_ODD_PARITY: + //Odd Parity + HWREG8(baseAddress + OFS_UCAxCTL0) |= UCPEN; + HWREG8(baseAddress + OFS_UCAxCTL0) &= ~UCPAR; + break; + case USCI_UART_EVEN_PARITY: + //Even Parity + HWREG8(baseAddress + OFS_UCAxCTL0) |= UCPEN; + HWREG8(baseAddress + OFS_UCAxCTL0) |= UCPAR; + break; + } + + //Modulation Control Registers + HWREG16(baseAddress + OFS_UCAxBRW ) = param->clockPrescalar; + HWREG8(baseAddress + OFS_UCAxMCTL) = ((param->firstModReg << 4) + + (param->secondModReg << 1) + + param->overSampling ); + + //Asynchronous mode & 8 bit character select & clear mode + HWREG8(baseAddress + OFS_UCAxCTL0) &= ~(UCSYNC + + UC7BIT + + UCMODE_3 + ); + + //Configure UART mode. + HWREG8(baseAddress + OFS_UCAxCTL0) |= param->uartMode; + + //Reset UCRXIE, UCBRKIE, UCDORM, UCTXADDR, UCTXBRK + HWREG8(baseAddress + OFS_UCAxCTL1) &= ~(UCRXEIE + UCBRKIE + UCDORM + + UCTXADDR + UCTXBRK + ); + + return retVal; +} //***************************************************************************** +// +//! \brief Transmits a byte from the UART Module. +//! +//! This function will place the supplied data into UART transmit data register +//! to start transmission +//! +//! \param baseAddress is the base address of the USCI_UART module. +//! \param transmitData data to be transmitted from the UART module +//! +//! Modified bits of \b UCAxTXBUF register. +//! +//! \return None +// +//***************************************************************************** +void USCI_UART_transmitData( uint16_t baseAddress, + uint8_t transmitData + ) +{ + //If interrupts are not used, poll for flags + if (!(HWREG8(baseAddress + OFS_UCAxIE) & UCTXIE)) + //Poll for transmit interrupt flag + while (!(HWREG8(baseAddress + OFS_UCAxIFG) & UCTXIFG)) ; + + HWREG8(baseAddress + OFS_UCAxTXBUF) = transmitData; +} + +//***************************************************************************** +// +//! \brief Receives a byte that has been sent to the UART Module. +//! +//! This function reads a byte of data from the UART receive data Register. +//! +//! \param baseAddress is the base address of the USCI_UART module. +//! +//! Modified bits of \b UCAxRXBUF register. +//! +//! \return Returns the byte received from by the UART module, cast as an +//! uint8_t. +// +//***************************************************************************** +uint8_t USCI_UART_receiveData(uint16_t baseAddress) +{ + //If interrupts are not used, poll for flags + if (!(HWREG8(baseAddress + OFS_UCAxIE) & UCRXIE)) + //Poll for receive interrupt flag + while (!(HWREG8(baseAddress + OFS_UCAxIFG) & UCRXIFG)) ; + + return HWREG8(baseAddress + OFS_UCAxRXBUF); +} + +//***************************************************************************** +// +//! \brief Enables individual UART interrupt sources. +//! +//! Enables the indicated UART interrupt sources. The interrupt flag is first +//! and then the corresponding interrupt is enabled. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. Does not clear interrupt flags. +//! +//! \param baseAddress is the base address of the USCI_UART module. +//! \param mask is the bit mask of the interrupt sources to be enabled. +//! Mask value is the logical OR of any of the following: +//! - \b USCI_UART_RECEIVE_INTERRUPT - Receive interrupt +//! - \b USCI_UART_TRANSMIT_INTERRUPT - Transmit interrupt +//! - \b USCI_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT - Receive erroneous- +//! character interrupt enable +//! - \b USCI_UART_BREAKCHAR_INTERRUPT - Receive break character +//! interrupt enable +//! +//! Modified bits of \b UCAxCTL1 register and bits of \b UCAxIE register. +//! +//! \return None +// +//***************************************************************************** +void USCI_UART_enableInterrupt(uint16_t baseAddress, + uint8_t mask + ) +{ + assert(!(mask & ~(USCI_UART_RECEIVE_INTERRUPT + | USCI_UART_TRANSMIT_INTERRUPT + | USCI_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT + | USCI_UART_BREAKCHAR_INTERRUPT))); + + uint8_t locMask; + + locMask = (mask & (USCI_UART_RECEIVE_INTERRUPT + | USCI_UART_TRANSMIT_INTERRUPT)); + HWREG8(baseAddress + OFS_UCAxIE) |= locMask; + + locMask = (mask & (USCI_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT + | USCI_UART_BREAKCHAR_INTERRUPT)); + HWREG8(baseAddress + OFS_UCAxCTL1) |= locMask; +} + +//***************************************************************************** +// +//! \brief Disables individual UART interrupt sources. +//! +//! Disables the indicated UART interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! \param baseAddress is the base address of the USCI_UART module. +//! \param mask is the bit mask of the interrupt sources to be disabled. +//! Mask value is the logical OR of any of the following: +//! - \b USCI_UART_RECEIVE_INTERRUPT - Receive interrupt +//! - \b USCI_UART_TRANSMIT_INTERRUPT - Transmit interrupt +//! - \b USCI_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT - Receive erroneous- +//! character interrupt enable +//! - \b USCI_UART_BREAKCHAR_INTERRUPT - Receive break character +//! interrupt enable +//! +//! Modified bits of \b UCAxCTL1 register and bits of \b UCAxIE register. +//! +//! \return None +// +//***************************************************************************** +void USCI_UART_disableInterrupt(uint16_t baseAddress, + uint8_t mask + ) +{ + assert(!(mask & ~(USCI_UART_RECEIVE_INTERRUPT + | USCI_UART_TRANSMIT_INTERRUPT + | USCI_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT + | USCI_UART_BREAKCHAR_INTERRUPT))); + + uint8_t locMask; + + if (locMask = (mask & (USCI_UART_RECEIVE_INTERRUPT + | USCI_UART_TRANSMIT_INTERRUPT))) + HWREG8(baseAddress + OFS_UCAxIE) &= ~locMask; + + if (locMask = (mask & (USCI_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT + | USCI_UART_BREAKCHAR_INTERRUPT))) + HWREG8(baseAddress + OFS_UCAxCTL1) &= ~locMask; +} + +//***************************************************************************** +// +//! \brief Gets the current UART interrupt status. +//! +//! This returns the interrupt status for the UART module based on which flag +//! is passed. +//! +//! \param baseAddress is the base address of the USCI_UART module. +//! \param mask is the masked interrupt flag status to be returned. +//! Mask value is the logical OR of any of the following: +//! - \b USCI_UART_RECEIVE_INTERRUPT_FLAG - Receive interrupt flag +//! - \b USCI_UART_TRANSMIT_INTERRUPT_FLAG - Transmit interrupt flag +//! +//! Modified bits of \b UCAxIFG register. +//! +//! \return Logical OR of any of the following: +//! - \b USCI_UART_RECEIVE_INTERRUPT_FLAG Receive interrupt flag +//! - \b USCI_UART_TRANSMIT_INTERRUPT_FLAG Transmit interrupt flag +//! \n indicating the status of the masked flags +// +//***************************************************************************** +uint8_t USCI_UART_getInterruptStatus(uint16_t baseAddress, + uint8_t mask) +{ + assert(!(mask & ~(USCI_UART_RECEIVE_INTERRUPT_FLAG + | USCI_UART_TRANSMIT_INTERRUPT_FLAG))); + + return HWREG8(baseAddress + OFS_UCAxIFG) & mask; +} + +//***************************************************************************** +// +//! \brief Clears UART interrupt sources. +//! +//! The UART interrupt source is cleared, so that it no longer asserts. The +//! highest interrupt flag is automatically cleared when an interrupt vector +//! generator is used. +//! +//! \param baseAddress is the base address of the USCI_UART module. +//! \param mask is a bit mask of the interrupt sources to be cleared. +//! Mask value is the logical OR of any of the following: +//! - \b USCI_UART_RECEIVE_INTERRUPT_FLAG - Receive interrupt flag +//! - \b USCI_UART_TRANSMIT_INTERRUPT_FLAG - Transmit interrupt flag +//! +//! Modified bits of \b UCAxIFG register. +//! +//! \return None +// +//***************************************************************************** +void USCI_UART_clearInterruptFlag(uint16_t baseAddress, uint8_t mask) +{ + assert(!(mask & ~(USCI_UART_RECEIVE_INTERRUPT_FLAG + | USCI_UART_TRANSMIT_INTERRUPT_FLAG))); + + //Clear the UART interrupt source. + HWREG8(baseAddress + OFS_UCAxIFG) &= ~(mask); +} + +//***************************************************************************** +// +//! \brief Enables the UART block. +//! +//! This will enable operation of the UART block. +//! +//! \param baseAddress is the base address of the USCI_UART module. +//! +//! Modified bits are \b UCSWRST of \b UCAxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void USCI_UART_enable(uint16_t baseAddress) +{ + //Reset the UCSWRST bit to enable the USCI Module + HWREG8(baseAddress + OFS_UCAxCTL1) &= ~(UCSWRST); +} + +//***************************************************************************** +// +//! \brief Disables the UART block. +//! +//! This will disable operation of the UART block. +//! +//! \param baseAddress is the base address of the USCI_UART module. +//! +//! Modified bits are \b UCSWRST of \b UCAxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void USCI_UART_disable(uint16_t baseAddress) +{ + //Set the UCSWRST bit to disable the USCI Module + HWREG8(baseAddress + OFS_UCAxCTL1) |= UCSWRST; +} + +//***************************************************************************** +// +//! \brief Gets the current UART status flags. +//! +//! This returns the status for the UART module based on which flag is passed. +//! +//! \param baseAddress is the base address of the USCI_UART module. +//! \param mask is the masked interrupt flag status to be returned. +//! Mask value is the logical OR of any of the following: +//! - \b USCI_UART_LISTEN_ENABLE +//! - \b USCI_UART_FRAMING_ERROR +//! - \b USCI_UART_OVERRUN_ERROR +//! - \b USCI_UART_PARITY_ERROR +//! - \b USCI_UART_BREAK_DETECT +//! - \b USCI_UART_RECEIVE_ERROR +//! - \b USCI_UART_ADDRESS_RECEIVED +//! - \b USCI_UART_IDLELINE +//! - \b USCI_UART_BUSY +//! +//! Modified bits of \b UCAxSTAT register. +//! +//! \return Logical OR of any of the following: +//! - \b USCI_UART_LISTEN_ENABLE +//! - \b USCI_UART_FRAMING_ERROR +//! - \b USCI_UART_OVERRUN_ERROR +//! - \b USCI_UART_PARITY_ERROR +//! - \b USCI_UART_BREAK_DETECT +//! - \b USCI_UART_RECEIVE_ERROR +//! - \b USCI_UART_ADDRESS_RECEIVED +//! - \b USCI_UART_IDLELINE +//! - \b USCI_UART_BUSY +//! \n indicating the status of the masked interrupt flags +// +//***************************************************************************** +uint8_t USCI_UART_queryStatusFlags(uint16_t baseAddress, + uint8_t mask) +{ + assert(0x00 != mask && (USCI_UART_LISTEN_ENABLE + + USCI_UART_FRAMING_ERROR + + USCI_UART_OVERRUN_ERROR + + USCI_UART_PARITY_ERROR + + USCI_UART_BREAK_DETECT + + USCI_UART_RECEIVE_ERROR + + USCI_UART_ADDRESS_RECEIVED + + USCI_UART_IDLELINE + + USCI_UART_BUSY + )); + + return HWREG8(baseAddress + OFS_UCAxSTAT) & mask; +} + +//***************************************************************************** +// +//! \brief Sets the UART module in dormant mode +//! +//! Puts USCI in sleep mode. Only characters that are preceded by an idle-line +//! or with address bit set UCRXIFG. In UART mode with automatic baud-rate +//! detection, only the combination of a break and sync field sets UCRXIFG. +//! +//! \param baseAddress is the base address of the USCI_UART module. +//! +//! Modified bits of \b UCAxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void USCI_UART_setDormant(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_UCAxCTL1) |= UCDORM; +} + +//***************************************************************************** +// +//! \brief Re-enables UART module from dormant mode +//! +//! Not dormant. All received characters set UCRXIFG. +//! +//! \param baseAddress is the base address of the USCI_UART module. +//! +//! Modified bits are \b UCDORM of \b UCAxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void USCI_UART_resetDormant(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_UCAxCTL1) &= ~UCDORM; +} + +//***************************************************************************** +// +//! \brief Transmits the next byte to be transmitted marked as address +//! depending on selected multiprocessor mode +//! +//! \param baseAddress is the base address of the USCI_UART module. +//! \param transmitAddress is the next byte to be transmitted +//! +//! Modified bits of \b UCAxTXBUF register and bits of \b UCAxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void USCI_UART_transmitAddress(uint16_t baseAddress, + uint8_t transmitAddress) +{ + //Set UCTXADDR bit + HWREG8(baseAddress + OFS_UCAxCTL1) |= UCTXADDR; + + //Place next byte to be sent into the transmit buffer + HWREG8(baseAddress + OFS_UCAxTXBUF) = transmitAddress; +} + +//***************************************************************************** +// +//! \brief Transmit break. +//! +//! Transmits a break with the next write to the transmit buffer. In UART mode +//! with automatic baud-rate detection, USCI_UART_AUTOMATICBAUDRATE_SYNC(0x55) +//! must be written into UCAxTXBUF to generate the required break/sync fields. +//! Otherwise, DEFAULT_SYNC(0x00) must be written into the transmit buffer. +//! Also ensures module is ready for transmitting the next data. +//! +//! \param baseAddress is the base address of the USCI_UART module. +//! +//! Modified bits of \b UCAxTXBUF register and bits of \b UCAxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +void USCI_UART_transmitBreak(uint16_t baseAddress) +{ + //Set UCTXADDR bit + HWREG8(baseAddress + OFS_UCAxCTL1) |= UCTXBRK; + + //If current mode is automatic baud-rate detection + if (USCI_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE == + (HWREG8(baseAddress + OFS_UCAxCTL0) & + USCI_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE)) + HWREG8(baseAddress + OFS_UCAxTXBUF) = USCI_UART_AUTOMATICBAUDRATE_SYNC; + else + HWREG8(baseAddress + OFS_UCAxTXBUF) = DEFAULT_SYNC; + + //If interrupts are not used, poll for flags + if (!(HWREG8(baseAddress + OFS_UCAxIE) & UCTXIE)) + //Poll for transmit interrupt flag + while (!(HWREG8(baseAddress + OFS_UCAxIFG) & UCTXIFG)) ; +} + +//***************************************************************************** +// +//! \brief Returns the address of the RX Buffer of the UART for the DMA module. +//! +//! Returns the address of the UART RX Buffer. This can be used in conjunction +//! with the DMA to store the received data directly to memory. +//! +//! \param baseAddress is the base address of the USCI_UART module. +//! +//! \return Address of RX Buffer +// +//***************************************************************************** +uint32_t USCI_UART_getReceiveBufferAddressForDMA(uint16_t baseAddress) +{ + return baseAddress + OFS_UCAxRXBUF; +} + +//***************************************************************************** +// +//! \brief Returns the address of the TX Buffer of the UART for the DMA module. +//! +//! Returns the address of the UART TX Buffer. This can be used in conjunction +//! with the DMA to obtain transmitted data directly from memory. +//! +//! \param baseAddress is the base address of the USCI_UART module. +//! +//! \return Address of TX Buffer +// +//***************************************************************************** +uint32_t USCI_UART_getTransmitBufferAddressForDMA(uint16_t baseAddress) +{ + return baseAddress + OFS_UCAxTXBUF; +} + + +#endif +//***************************************************************************** +// +//! Close the doxygen group for usci_uart_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/usci_uart.h b/source/driverlib/MSP430F5xx_6xx/usci_uart.h new file mode 100644 index 0000000..4f3a388 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/usci_uart.h @@ -0,0 +1,255 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// usci_uart.h - Driver for the USCI_UART Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_USCI_UART_H__ +#define __MSP430WARE_USCI_UART_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_USCI_Ax__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//****************************************************************************** +// +// The following is a struct that is passed to USCI_UART_init() +// +//****************************************************************************** +typedef struct USCI_UART_InitParam { + uint8_t selectClockSource; + uint16_t clockPrescalar; + uint8_t firstModReg; + uint8_t secondModReg; + uint8_t parity; + uint8_t msborLsbFirst; + uint8_t numberofStopBits; + uint8_t uartMode; + uint8_t overSampling; +} USCI_UART_initParam; + +//***************************************************************************** +// +// The following values are the sync characters possible +// +//***************************************************************************** +#define DEFAULT_SYNC 0x00 +#define USCI_UART_AUTOMATICBAUDRATE_SYNC 0x55 + +//***************************************************************************** +// +// The following are values that can be passed to the parity parameter for +// functions: USCI_UART_initAdvance(). +// +//***************************************************************************** +#define USCI_UART_NO_PARITY 0x00 +#define USCI_UART_ODD_PARITY 0x01 +#define USCI_UART_EVEN_PARITY 0x02 + +//***************************************************************************** +// +// The following are values that can be passed to the msborLsbFirst parameter +// for functions: USCI_UART_initAdvance(). +// +//***************************************************************************** +#define USCI_UART_MSB_FIRST UCMSB +#define USCI_UART_LSB_FIRST 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the uartMode parameter for +// functions: USCI_UART_initAdvance(). +// +//***************************************************************************** +#define USCI_UART_MODE UCMODE_0 +#define USCI_UART_IDLE_LINE_MULTI_PROCESSOR_MODE UCMODE_1 +#define USCI_UART_ADDRESS_BIT_MULTI_PROCESSOR_MODE UCMODE_2 +#define USCI_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE UCMODE_3 + +//***************************************************************************** +// +// The following are values that can be passed to the selectClockSource +// parameter for functions: USCI_UART_initAdvance(). +// +//***************************************************************************** +#define USCI_UART_CLOCKSOURCE_SMCLK UCSSEL__SMCLK +#define USCI_UART_CLOCKSOURCE_ACLK UCSSEL__ACLK + +//***************************************************************************** +// +// The following are values that can be passed to the numberofStopBits +// parameter for functions: USCI_UART_initAdvance(). +// +//***************************************************************************** +#define USCI_UART_ONE_STOP_BIT 0x00 +#define USCI_UART_TWO_STOP_BITS UCSPB + +//***************************************************************************** +// +// The following are values that can be passed to the overSampling parameter +// for functions: USCI_UART_initAdvance(). +// +//***************************************************************************** +#define USCI_UART_OVERSAMPLING_BAUDRATE_GENERATION 0x01 +#define USCI_UART_LOW_FREQUENCY_BAUDRATE_GENERATION 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the mask parameter for +// functions: USCI_UART_enableInterrupt(), and USCI_UART_disableInterrupt(). +// +//***************************************************************************** +#define USCI_UART_RECEIVE_INTERRUPT UCRXIE +#define USCI_UART_TRANSMIT_INTERRUPT UCTXIE +#define USCI_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT UCRXEIE +#define USCI_UART_BREAKCHAR_INTERRUPT UCBRKIE + +//***************************************************************************** +// +// The following are values that can be passed to the mask parameter for +// functions: USCI_UART_getInterruptStatus(), and +// USCI_UART_clearInterruptFlag() as well as returned by the +// USCI_UART_getInterruptStatus() function. +// +//***************************************************************************** +#define USCI_UART_RECEIVE_INTERRUPT_FLAG UCRXIFG +#define USCI_UART_TRANSMIT_INTERRUPT_FLAG UCTXIFG + +//***************************************************************************** +// +// The following are values that can be passed to the mask parameter for +// functions: USCI_UART_queryStatusFlags() as well as returned by the +// USCI_UART_queryStatusFlags() function. +// +//***************************************************************************** +#define USCI_UART_LISTEN_ENABLE UCLISTEN +#define USCI_UART_FRAMING_ERROR UCFE +#define USCI_UART_OVERRUN_ERROR UCOE +#define USCI_UART_PARITY_ERROR UCPE +#define USCI_UART_BREAK_DETECT UCBRK +#define USCI_UART_RECEIVE_ERROR UCRXERR +#define USCI_UART_ADDRESS_RECEIVED UCADDR +#define USCI_UART_IDLELINE UCIDLE +#define USCI_UART_BUSY UCBUSY + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern bool USCI_UART_init(uint16_t baseAddress, + USCI_UART_initParam *param); + +extern void USCI_UART_transmitData(uint16_t baseAddress, + uint8_t transmitData); + +extern uint8_t USCI_UART_receiveData(uint16_t baseAddress); + +extern void USCI_UART_enableInterrupt(uint16_t baseAddress, + uint8_t mask); + +extern void USCI_UART_disableInterrupt(uint16_t baseAddress, + uint8_t mask); + +extern uint8_t USCI_UART_getInterruptStatus(uint16_t baseAddress, + uint8_t mask); + +extern void USCI_UART_clearInterruptFlag(uint16_t baseAddress, + uint8_t mask); + +extern void USCI_UART_enable(uint16_t baseAddress); + +extern void USCI_UART_disable(uint16_t baseAddress); + +extern uint8_t USCI_UART_queryStatusFlags(uint16_t baseAddress, + uint8_t mask); + +extern void USCI_UART_setDormant(uint16_t baseAddress); + +extern void USCI_UART_resetDormant(uint16_t baseAddress); + +extern void USCI_UART_transmitAddress(uint16_t baseAddress, + uint8_t transmitAddress); + +extern void USCI_UART_transmitBreak(uint16_t baseAddress); + +extern uint32_t USCI_UART_getReceiveBufferAddressForDMA(uint16_t baseAddress); + +extern uint32_t USCI_UART_getTransmitBufferAddressForDMA(uint16_t baseAddress); + +//***************************************************************************** +// +// DEPRECATED +// +//***************************************************************************** +#define UARTBREAK_DETECT UCBRK + +//***************************************************************************** +// +// The following are deprecated APIs. +// +//***************************************************************************** +extern bool USCI_UART_initAdvance(uint16_t baseAddress, + uint8_t selectClockSource, + uint16_t clockPrescalar, + uint8_t firstModReg, + uint8_t secondModReg, + uint8_t parity, + uint8_t msborLsbFirst, + uint8_t numberofStopBits, + uint8_t uartMode, + uint8_t overSampling); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_USCI_UART_H__ diff --git a/source/driverlib/MSP430F5xx_6xx/wdt_a.c b/source/driverlib/MSP430F5xx_6xx/wdt_a.c new file mode 100644 index 0000000..8c65349 --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/wdt_a.c @@ -0,0 +1,200 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// wdt_a.c - Driver for the wdt_a Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup wdt_a_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_WDT_A__ +#include "wdt_a.h" + +#include + +//***************************************************************************** +// +//! \brief Holds the Watchdog Timer. +//! +//! This function stops the watchdog timer from running, that way no interrupt +//! or PUC is asserted. +//! +//! \param baseAddress is the base address of the WDT_A module. +//! +//! \return None +// +//***************************************************************************** +void WDT_A_hold(uint16_t baseAddress) +{ + // Set Hold bit + uint8_t newWDTStatus = + ((HWREG16(baseAddress + OFS_WDTCTL) & 0x00FF) | WDTHOLD); + + HWREG16(baseAddress + OFS_WDTCTL) = WDTPW + newWDTStatus; +} + +//***************************************************************************** +// +//! \brief Starts the Watchdog Timer. +//! +//! This function starts the watchdog timer functionality to start counting +//! again. +//! +//! \param baseAddress is the base address of the WDT_A module. +//! +//! \return None +// +//***************************************************************************** +void WDT_A_start(uint16_t baseAddress) +{ + // Reset Hold bit + uint8_t newWDTStatus = + ((HWREG16(baseAddress + OFS_WDTCTL) & 0x00FF) & ~(WDTHOLD)); + + HWREG16(baseAddress + OFS_WDTCTL) = WDTPW + newWDTStatus; +} + +//***************************************************************************** +// +//! \brief Resets the timer counter of the Watchdog Timer. +//! +//! This function resets the watchdog timer to 0x0000h. +//! +//! \param baseAddress is the base address of the WDT_A module. +//! +//! \return None +// +//***************************************************************************** +void WDT_A_resetTimer(uint16_t baseAddress) +{ + // Set Counter Clear bit + uint8_t newWDTStatus = + ((HWREG16(baseAddress + OFS_WDTCTL) & 0x00FF) | WDTCNTCL); + + HWREG16(baseAddress + OFS_WDTCTL) = WDTPW + newWDTStatus; +} + +//***************************************************************************** +// +//! \brief Sets the clock source for the Watchdog Timer in watchdog mode. +//! +//! This function sets the watchdog timer in watchdog mode, which will cause a +//! PUC when the timer overflows. When in the mode, a PUC can be avoided with a +//! call to WDT_A_resetTimer() before the timer runs out. +//! +//! \param baseAddress is the base address of the WDT_A module. +//! \param clockSelect is the clock source that the watchdog timer will use. +//! Valid values are: +//! - \b WDT_A_CLOCKSOURCE_SMCLK [Default] +//! - \b WDT_A_CLOCKSOURCE_ACLK +//! - \b WDT_A_CLOCKSOURCE_VLOCLK +//! - \b WDT_A_CLOCKSOURCE_XCLK +//! \n Modified bits are \b WDTSSEL of \b WDTCTL register. +//! \param clockDivider is the divider of the clock source, in turn setting the +//! watchdog timer interval. +//! Valid values are: +//! - \b WDT_A_CLOCKDIVIDER_2G +//! - \b WDT_A_CLOCKDIVIDER_128M +//! - \b WDT_A_CLOCKDIVIDER_8192K +//! - \b WDT_A_CLOCKDIVIDER_512K +//! - \b WDT_A_CLOCKDIVIDER_32K [Default] +//! - \b WDT_A_CLOCKDIVIDER_8192 +//! - \b WDT_A_CLOCKDIVIDER_512 +//! - \b WDT_A_CLOCKDIVIDER_64 +//! \n Modified bits are \b WDTIS and \b WDTHOLD of \b WDTCTL register. +//! +//! \return None +// +//***************************************************************************** +void WDT_A_watchdogTimerInit(uint16_t baseAddress, + uint8_t clockSelect, + uint8_t clockDivider) +{ + HWREG16(baseAddress + OFS_WDTCTL) = + WDTPW + WDTCNTCL + WDTHOLD + clockSelect + clockDivider; +} + +//***************************************************************************** +// +//! \brief Sets the clock source for the Watchdog Timer in timer interval mode. +//! +//! This function sets the watchdog timer as timer interval mode, which will +//! assert an interrupt without causing a PUC. +//! +//! \param baseAddress is the base address of the WDT_A module. +//! \param clockSelect is the clock source that the watchdog timer will use. +//! Valid values are: +//! - \b WDT_A_CLOCKSOURCE_SMCLK [Default] +//! - \b WDT_A_CLOCKSOURCE_ACLK +//! - \b WDT_A_CLOCKSOURCE_VLOCLK +//! - \b WDT_A_CLOCKSOURCE_XCLK +//! \n Modified bits are \b WDTSSEL of \b WDTCTL register. +//! \param clockDivider is the divider of the clock source, in turn setting the +//! watchdog timer interval. +//! Valid values are: +//! - \b WDT_A_CLOCKDIVIDER_2G +//! - \b WDT_A_CLOCKDIVIDER_128M +//! - \b WDT_A_CLOCKDIVIDER_8192K +//! - \b WDT_A_CLOCKDIVIDER_512K +//! - \b WDT_A_CLOCKDIVIDER_32K [Default] +//! - \b WDT_A_CLOCKDIVIDER_8192 +//! - \b WDT_A_CLOCKDIVIDER_512 +//! - \b WDT_A_CLOCKDIVIDER_64 +//! \n Modified bits are \b WDTIS and \b WDTHOLD of \b WDTCTL register. +//! +//! \return None +// +//***************************************************************************** +void WDT_A_intervalTimerInit(uint16_t baseAddress, + uint8_t clockSelect, + uint8_t clockDivider) +{ + HWREG16(baseAddress + OFS_WDTCTL) = + WDTPW + WDTCNTCL + WDTHOLD + WDTTMSEL + clockSelect + clockDivider; +} + +#endif +//***************************************************************************** +// +//! Close the doxygen group for wdt_a_api +//! @} +// +//***************************************************************************** diff --git a/source/driverlib/MSP430F5xx_6xx/wdt_a.h b/source/driverlib/MSP430F5xx_6xx/wdt_a.h new file mode 100644 index 0000000..244446e --- /dev/null +++ b/source/driverlib/MSP430F5xx_6xx/wdt_a.h @@ -0,0 +1,111 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// wdt_a.h - Driver for the WDT_A Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_WDT_A_H__ +#define __MSP430WARE_WDT_A_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_WDT_A__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the clockSelect parameter for +// functions: WDT_A_watchdogTimerInit(), and WDT_A_intervalTimerInit(). +// +//***************************************************************************** +#define WDT_A_CLOCKSOURCE_SMCLK (WDTSSEL_0) +#define WDT_A_CLOCKSOURCE_ACLK (WDTSSEL_1) +#define WDT_A_CLOCKSOURCE_VLOCLK (WDTSSEL_2) +#define WDT_A_CLOCKSOURCE_XCLK (WDTSSEL_3) + +//***************************************************************************** +// +// The following are values that can be passed to the clockDivider parameter +// for functions: WDT_A_watchdogTimerInit(), and WDT_A_intervalTimerInit(). +// +//***************************************************************************** +#define WDT_A_CLOCKDIVIDER_2G (WDTIS_0) +#define WDT_A_CLOCKDIVIDER_128M (WDTIS_1) +#define WDT_A_CLOCKDIVIDER_8192K (WDTIS_2) +#define WDT_A_CLOCKDIVIDER_512K (WDTIS_3) +#define WDT_A_CLOCKDIVIDER_32K (WDTIS_4) +#define WDT_A_CLOCKDIVIDER_8192 (WDTIS_5) +#define WDT_A_CLOCKDIVIDER_512 (WDTIS_6) +#define WDT_A_CLOCKDIVIDER_64 (WDTIS_7) + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void WDT_A_hold(uint16_t baseAddress); + +extern void WDT_A_start(uint16_t baseAddress); + +extern void WDT_A_resetTimer(uint16_t baseAddress); + +extern void WDT_A_watchdogTimerInit(uint16_t baseAddress, + uint8_t clockSelect, + uint8_t clockDivider); + +extern void WDT_A_intervalTimerInit(uint16_t baseAddress, + uint8_t clockSelect, + uint8_t clockDivider); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_WDT_A_H__ diff --git a/source/hal.c b/source/hal.c new file mode 100644 index 0000000..f7b71ee --- /dev/null +++ b/source/hal.c @@ -0,0 +1,163 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +/* + * ======== hal.c ======== + * + */ +#include "msp430.h" + +#include "driverlib.h" + +#include "USB_API/USB_Common/device.h" +#include "USB_config/descriptors.h" + +#include "hal.h" + +#define GPIO_ALL GPIO_PIN0|GPIO_PIN1|GPIO_PIN2|GPIO_PIN3| \ + GPIO_PIN4|GPIO_PIN5|GPIO_PIN6|GPIO_PIN7 + + + +/* +* This function drives all the I/O's as output-low, to avoid floating inputs +* (which cause extra power to be consumed). This setting is compatible with + * TI FET target boards, the F5529 Launchpad, and F5529 Experimenters Board; + * but may not be compatible with custom hardware, which may have components + * attached to the I/Os that could be affected by these settings. So if using +* other boards, this function may need to be modified. +*/ +void initPorts(void) +{ +PMAPPWD = PMAPKEY; // Enable Write-access to modify port mapping registers +PMAPCTL = PMAPRECFG; // Allow reconfiguration during runtime +PMAPPWD = 0; // Disable Write-access to port mapping registers + +#ifdef __MSP430_HAS_PORT1_R__ + GPIO_setOutputLowOnPin(GPIO_PORT_P1, GPIO_ALL); + GPIO_setAsOutputPin(GPIO_PORT_P1, GPIO_ALL); +#endif + +#ifdef __MSP430_HAS_PORT2_R__ + GPIO_setOutputLowOnPin(GPIO_PORT_P2, GPIO_ALL); + GPIO_setAsOutputPin(GPIO_PORT_P2, GPIO_ALL); +#endif + +#ifdef __MSP430_HAS_PORT3_R__ + GPIO_setOutputLowOnPin(GPIO_PORT_P3, GPIO_ALL); + GPIO_setAsOutputPin(GPIO_PORT_P3, GPIO_ALL); +#endif + +#ifdef __MSP430_HAS_PORT4_R__ + GPIO_setOutputLowOnPin(GPIO_PORT_P4, GPIO_ALL); + GPIO_setAsOutputPin(GPIO_PORT_P4, GPIO_ALL); +#endif + +#ifdef __MSP430_HAS_PORT5_R__ + GPIO_setOutputLowOnPin(GPIO_PORT_P5, GPIO_ALL); + GPIO_setAsOutputPin(GPIO_PORT_P5, GPIO_ALL); +#endif + +#ifdef __MSP430_HAS_PORT6_R__ + GPIO_setOutputLowOnPin(GPIO_PORT_P6, GPIO_ALL); + GPIO_setAsOutputPin(GPIO_PORT_P6, GPIO_ALL); +#endif + +#ifdef __MSP430_HAS_PORT7_R__ + GPIO_setOutputLowOnPin(GPIO_PORT_P7, GPIO_ALL); + GPIO_setAsOutputPin(GPIO_PORT_P7, GPIO_ALL); +#endif + +#ifdef __MSP430_HAS_PORT8_R__ + GPIO_setOutputLowOnPin(GPIO_PORT_P8, GPIO_ALL); + GPIO_setAsOutputPin(GPIO_PORT_P8, GPIO_ALL); +#endif + +#ifdef __MSP430_HAS_PORT9_R__ + GPIO_setOutputLowOnPin(GPIO_PORT_P9, GPIO_ALL); + GPIO_setAsOutputPin(GPIO_PORT_P9, GPIO_ALL); +#endif + +#ifdef __MSP430_HAS_PORTJ_R__ + GPIO_setOutputLowOnPin(GPIO_PORT_PJ, GPIO_ALL); + GPIO_setAsOutputPin(GPIO_PORT_PJ, GPIO_ALL); +#endif +} + +/* Configures the system clocks: +* MCLK = SMCLK = DCO/FLL = mclkFreq (expected to be expressed in Hz) +* ACLK = FLLref = REFO=32kHz +* +* XT2 is not configured here. Instead, the USB API automatically starts XT2 +* when beginning USB communication, and optionally disables it during USB +* suspend. It's left running after the USB host is disconnected, at which +* point you're free to disable it. You need to configure the XT2 frequency +* in the Descriptor Tool (currently set to 4MHz in this example). +* See the Programmer's Guide for more information. +*/ +void initClocks(uint32_t mclkFreq) +{ +#ifndef DRIVERLIB_LEGACY_MODE + UCS_clockSignalInit( + UCS_FLLREF, + UCS_REFOCLK_SELECT, + UCS_CLOCK_DIVIDER_1); + + UCS_clockSignalInit( + UCS_ACLK, + UCS_XT2CLK_SELECT, + UCS_CLOCK_DIVIDER_1); + + UCS_initFLLSettle( + mclkFreq/1000, + mclkFreq/32768); +#else + UCS_clockSignalInit( + UCS_BASE, + UCS_FLLREF, + UCS_REFOCLK_SELECT, + UCS_CLOCK_DIVIDER_1); + + UCS_clockSignalInit( + UCS_BASE, + UCS_ACLK, + UCS_REFOCLK_SELECT, + UCS_CLOCK_DIVIDER_1); + + UCS_initFLLSettle( + UCS_BASE, + mclkFreq/1000, + mclkFreq/32768); + +#endif + +} +//Released_Version_4_10_02 diff --git a/source/hal.h b/source/hal.h new file mode 100644 index 0000000..9c00380 --- /dev/null +++ b/source/hal.h @@ -0,0 +1,42 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +/* + * ======== hal.h ======== + * + * Device and board specific pins need to be configured here + * + */ + + +void initPorts(void); +void initClocks(uint32_t mclkFreq); +//Released_Version_4_10_02 diff --git a/source/main.c b/source/main.c new file mode 100644 index 0000000..2887bd0 --- /dev/null +++ b/source/main.c @@ -0,0 +1,172 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +/* + * ======== main.c ======== + */ +#include + +#include "driverlib.h" + +#include "USB_config/descriptors.h" +#include "USB_API/USB_Common/device.h" +#include "USB_API/USB_Common/usb.h" +#include "USB_API/USB_CDC_API/UsbCdc.h" +#include "USB_app/usbConstructs.h" + +/* + * NOTE: Modify hal.h to select a specific evaluation board and customize for + * your own board. + */ +#include "hal.h" +#include "peripherals.h" + +void main (void) +{ + // Set up clocks/IOs. initPorts()/initClocks() will need to be customized + // for your application, but MCLK should be between 4-25MHz. Using the + // DCO/FLL for MCLK is recommended, instead of the crystal. For examples + // of these functions, see the complete USB code examples. Also see the + // Programmer's Guide for discussion on clocks/power. + WDT_A_hold(WDT_A_BASE); // Stop watchdog timer + + // Minimum Vcore setting required for the USB API is PMM_CORE_LEVEL_2 . +#ifndef DRIVERLIB_LEGACY_MODE + PMM_setVCore(PMM_CORE_LEVEL_2); +#else + PMM_setVCore(PMM_BASE, PMM_CORE_LEVEL_2); +#endif + + initPorts(); // Configure all GPIOs + initClocks(20000000); // Configure clocks + USB_setup(TRUE,TRUE); // Init USB & events; if a host is present, connect + + startup_led_sequence(); // Blink the LEDs + + __enable_interrupt(); // Enable interrupts globally + + while (1) + { + // This switch() creates separate main loops, depending on whether USB + // is enumerated and active on the host, or disconnected/suspended. If + // you prefer, you can eliminate the switch, and just call + // USB_connectionState() prior to sending data (to ensure the state is + // ST_ENUM_ACTIVE). + switch(USB_connectionState()) + { + // This case is executed while your device is connected to the USB + // host, enumerated, and communication is active. Never enter + // LPM3/4/5 in this mode; the MCU must be active or LPM0 during USB + // communication. + case ST_ENUM_ACTIVE: + if(active_peripheral == UART) + { + uartControl(); + } + else if (active_peripheral == I2C) + { + i2cControl(); + } + else if (active_peripheral == SPI) + { + spiControl(); + } + break; + + // These cases are executed while your device is: + case ST_USB_DISCONNECTED: // physically disconnected from the host + case ST_ENUM_SUSPENDED: // connected/enumerated, but suspended + case ST_NOENUM_SUSPENDED: // connected, enum started, but the host is unresponsive + + // In this example, for all of these states we enter LPM3. If + // the host performs a "USB resume" from suspend, the CPU will + // automatically wake. Other events can also wake the + // CPU, if their event handlers in eventHandlers.c are + // configured to return TRUE. + __bis_SR_register(LPM3_bits + GIE); + break; + + // The default is executed for the momentary state + // ST_ENUM_IN_PROGRESS. Almost always, this state lasts no more than a + // few seconds. Be sure not to enter LPM3 in this state; USB + // communication is taking place, so mode must be LPM0 or active. + case ST_ENUM_IN_PROGRESS: + default:; + } + } //while(1) +} //main() + + +/* + * ======== UNMI_ISR ======== + */ +#if defined(__TI_COMPILER_VERSION__) || (__IAR_SYSTEMS_ICC__) +#pragma vector = UNMI_VECTOR +__interrupt void UNMI_ISR (void) +#elif defined(__GNUC__) && (__MSP430__) +void __attribute__ ((interrupt(UNMI_VECTOR))) UNMI_ISR (void) +#else +#error Compiler not found! +#endif +{ + switch (__even_in_range(SYSUNIV, SYSUNIV_BUSIFG)) + { + case SYSUNIV_NONE: + __no_operation(); + break; + case SYSUNIV_NMIIFG: + __no_operation(); + break; + case SYSUNIV_OFIFG: +#ifndef DRIVERLIB_LEGACY_MODE + UCS_clearAllOscFlagsWithTimeout(0); + SFR_clearInterrupt(SFR_OSCILLATOR_FAULT_INTERRUPT); +#else + UCS_clearAllOscFlagsWithTimeout(UCS_BASE, 0); + SFR_clearInterrupt(SFR_BASE, SFR_OSCILLATOR_FAULT_INTERRUPT); + +#endif + break; + case SYSUNIV_ACCVIFG: + __no_operation(); + break; + case SYSUNIV_BUSIFG: + // If the CPU accesses USB memory while the USB module is + // suspended, a "bus error" can occur. This generates an NMI, and + // execution enters this case. This should never occur. If USB is + // automatically disconnecting in your software, set a breakpoint + // here and see if execution hits it. See the Programmer's + // Guide for more information. + SYSBERRIV = 0; // Clear bus error flag + USB_disable(); // Disable USB -- USB must be reset after a bus error + } +} +//Released_Version_4_10_02 diff --git a/source/peripherals.c b/source/peripherals.c new file mode 100644 index 0000000..0521427 --- /dev/null +++ b/source/peripherals.c @@ -0,0 +1,1191 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +/* + * ======== hal.c ======== + * + */ +#include "peripherals.h" +#include "USB_API/USB_CDC_API/UsbCdc.h" +#include "USB_app/usbConstructs.h" + +enum active_peripherals active_peripheral = None; + +uint8_t rxBuffer[RX_BUFFER_SIZE]; +uint8_t txBuffer[TX_BUFFER_SIZE]; +uint8_t *txBuffer_read_ptr = txBuffer; +uint8_t *txBuffer_write_ptr = txBuffer; +#define BUFFER_SIZE 266 +uint8_t UARTtoCDC_CircularBuffer[BUFFER_SIZE]; +uint16_t UARTtoCDC_RXPtr = 0; +uint16_t UARTtoCDC_TXPtr = 0; + +uint32_t current_baudrate = 0; + +/* Blink the LEDs */ +void startup_led_sequence() +{ + uint8_t led_blink_count; + for(led_blink_count = LED_BLINK_COUNT; led_blink_count > 0; --led_blink_count) + { + LED1_ON + LED2_ON + __delay_cycles(LED_BLINK_DELAY); + LED1_OFF + LED2_OFF + __delay_cycles(LED_BLINK_DELAY); + } +} + + +/*** BSL entry sequence ******************************************************/ + +/* BSL entry sequence: Toggle RST/TEST/TCK pins for BSL invoke */ +void BSL_invoke_sequence() +{ + /* BSL invoke sequence + * + * H --------+ +----------- + * RST L +-----------+ + * + * H --------+ +--+ +-----+ + * TEST L +--+ +--+ +-------- + * + * H -----------+ +--+ +-------- + * TCK L +--+ +-----+ + */ + + // Set RST, TST and TCK pin to output + ENTRY_SEQ_PDIR |= (RESET_PIN + TEST_PIN + TCK_PIN); + + /* Start with RST, TEST and TCK high */ + ENTRY_SEQ_POUT = RESET_PIN + TEST_PIN + TCK_PIN; + __delay_cycles(INVOKE_DELAY); + __delay_cycles(INVOKE_DELAY); + __delay_cycles(INVOKE_DELAY); + + /* RST low, TEST low, TCK high */ + ENTRY_SEQ_POUT = TCK_PIN; + __delay_cycles(INVOKE_DELAY); + + /* RST low, TEST high, TCK low */ + ENTRY_SEQ_POUT = TEST_PIN; + __delay_cycles(INVOKE_DELAY); + + /* RST low, TEST low, TCK high */ + ENTRY_SEQ_POUT = TCK_PIN; + __delay_cycles(INVOKE_DELAY); + + /* RST low, TEST high, TCK low */ + ENTRY_SEQ_POUT = TEST_PIN; + __delay_cycles(INVOKE_DELAY); + + /* RST high, TEST high, TCK low */ + ENTRY_SEQ_POUT = RESET_PIN + TEST_PIN; + __delay_cycles(INVOKE_DELAY); + + /* RST high, TEST low, TCK high */ + ENTRY_SEQ_POUT = RESET_PIN + TCK_PIN; + __delay_cycles(INVOKE_DELAY); + __delay_cycles(INVOKE_DELAY); + __delay_cycles(INVOKE_DELAY); + + // Set RST, TST and TCK pin to input + ENTRY_SEQ_PDIR &= ~(RESET_PIN + TEST_PIN + TCK_PIN); +} + + +/* Reset sequence to leave BSL (JTAG20 workaround) */ +void BSL_reset_sequence() +{ + /* BSL reset sequence (JTAG20 workaround) + * + * H --------+ +--------- + * RST L +--------------+ + * + * H --------+ +--+ +--+ + * TEST L +--+ +--+ +------------ + */ + + // Set RST, TST and TCK pin to output + ENTRY_SEQ_PDIR |= (RESET_PIN + TEST_PIN + TCK_PIN); + + /* Start with RST and TEST high */ + ENTRY_SEQ_POUT = RESET_PIN + TEST_PIN; + __delay_cycles(INVOKE_DELAY); + __delay_cycles(INVOKE_DELAY); + __delay_cycles(INVOKE_DELAY); + + /* RST low, TEST low */ + ENTRY_SEQ_POUT = 0; + __delay_cycles(INVOKE_DELAY); + + /* RST low, TEST high */ + ENTRY_SEQ_POUT = TEST_PIN; + __delay_cycles(INVOKE_DELAY); + + /* RST low, TEST low */ + ENTRY_SEQ_POUT = 0; + __delay_cycles(INVOKE_DELAY); + + /* RST low, TEST high */ + ENTRY_SEQ_POUT = TEST_PIN; + __delay_cycles(INVOKE_DELAY); + + /* RST low, TEST low */ + ENTRY_SEQ_POUT = 0; + __delay_cycles(INVOKE_DELAY); + + /* RST high, TEST low */ + ENTRY_SEQ_POUT = RESET_PIN; + __delay_cycles(INVOKE_DELAY); + __delay_cycles(INVOKE_DELAY); + __delay_cycles(INVOKE_DELAY); + + // Set RST, TST and TCK pin to input + ENTRY_SEQ_PDIR &= ~(RESET_PIN + TEST_PIN + TCK_PIN); +} + + +/* BaudrateSelect + * Handles configuration of UART, I2C and SPI peripheral on baud rate change */ +uint8_t BaudrateSelect(uint32_t lBaudrate) +{ + if(current_baudrate == lBaudrate) + { + return 0; + } + + current_baudrate = lBaudrate; + + // Reset peripheral communication pins to input + P4DIR &= ~(BIT0 + BIT3 + BIT4 + BIT5); + // Set RST, TST and TCK pin to input + ENTRY_SEQ_PDIR &= ~(RESET_PIN + TEST_PIN + TCK_PIN); + + LED1_OFF + __delay_cycles(1000000); + LED1_ON + + uint8_t baudIndex; + + switch(lBaudrate) + { + /* UART peripheral */ + case 1200: + active_peripheral = UART; + baudIndex = InitUart(lBaudrate); + break; + case 2400: + active_peripheral = UART; + baudIndex = InitUart(lBaudrate); + break; + case 4800: + active_peripheral = UART; + baudIndex = InitUart(lBaudrate); + break; + case 4801: + active_peripheral = UART; + baudIndex = InitUart(lBaudrate); + break; + case 4802: + active_peripheral = UART; + baudIndex = InitUart(lBaudrate); + break; + case 9600: + active_peripheral = UART; + baudIndex = InitUart(lBaudrate); + break; + case 9601: + active_peripheral = UART; + baudIndex = InitUart(lBaudrate); + break; + case 19200: + active_peripheral = UART; + baudIndex = InitUart(lBaudrate); + break; + case 38400: + active_peripheral = UART; + baudIndex = InitUart(lBaudrate); + break; + case 57600: + active_peripheral = UART; + baudIndex = InitUart(lBaudrate); + break; + case 115200: + active_peripheral = UART; + baudIndex = InitUart(lBaudrate); + break; + case 230400: + active_peripheral = UART; + baudIndex = InitUart(lBaudrate); + break; + case 460800: + active_peripheral = UART; + baudIndex = InitUart(lBaudrate); + break; + case 921600: + active_peripheral = UART; + baudIndex = InitUart(lBaudrate); + break; + + /* I2C peripheral */ + case 100000: + active_peripheral = I2C; + baudIndex = InitI2C(BSL_SLAVE_ADDR, lBaudrate); + break; + case 100001: + active_peripheral = I2C; + baudIndex = InitI2C(BSL_SLAVE_ADDR, lBaudrate); + break; + case 400000: + active_peripheral = I2C; + baudIndex = InitI2C(BSL_SLAVE_ADDR, lBaudrate); + break; + case 400001: + active_peripheral = I2C; + baudIndex = InitI2C(BSL_SLAVE_ADDR, lBaudrate); + break; + + /* SPI */ + case 125000: + active_peripheral = SPI; + baudIndex = spiInit(lBaudrate); + break; + case 125001: + active_peripheral = SPI; + baudIndex = spiInit(lBaudrate); + break; + case 250000: + active_peripheral = SPI; + baudIndex = spiInit(lBaudrate); + break; + case 250001: + active_peripheral = SPI; + baudIndex = spiInit(lBaudrate); + break; + case 500000: + active_peripheral = SPI; + baudIndex = spiInit(lBaudrate); + break; + case 500001: + active_peripheral = SPI; + baudIndex = spiInit(lBaudrate); + break; + case 1000000: + active_peripheral = SPI; + baudIndex = spiInit(lBaudrate); + break; + case 1000001: + active_peripheral = SPI; + baudIndex = spiInit(lBaudrate); + break; + + default: + baudIndex = 0; + break; + + } + + return baudIndex; +} + + +/*** UART ********************************************************************/ +// List of standard baudrates +const struct _BaudrateList{ + uint8_t ucaBR0, ucaBR1, ucaMCTL; +}BaudrateList[] = { // CLK 20MHz + {0x00, 0x00, 0x00}, + {0x1A, 0x41, UCBRS_5}, // 1.2 kb/s + {0x8D, 0x20, UCBRS_3}, // 2.4 kb/s + {0x46, 0x10, UCBRS_5}, // 4.8 kb/s + {0x82, 0x00, 0x30 + UCOS16}, // 9.6 kb/s + {0x41, 0x00, (UCBRF_2+UCOS16)}, // 19.2 kb/s + {0x20, 0x00, (UCBRF_9+UCOS16)}, // 38.4 kb/s + {0x15, 0x00, (UCBRF_11+UCOS16)}, // 57.6 kb/s + {0x0A, 0x00, (UCBRF_14+UCOS16)}, // 115.2 kbit/s + {0x05, 0x00, (UCBRF_7+UCOS16)}, // 230.4 kbit/s + {0x02, 0x00, (UCBRS_6+UCBRF_10+UCOS16)}, // 460.8 kbit/s + {0x15, 0x00, (UCBRS_6)} // 921.6 kbit/s +}; + +// Baudrate indexes +enum baud{BAUD_ERROR, BAUD_1200, BAUD_2400, BAUD_4800, BAUD_9600, BAUD_19200, + BAUD_38400, BAUD_57600, BAUD_115200, BAUD_230400, BAUD_460800, BAUD_921600}; + +uint8_t InitUart(uint32_t lBaudrate) +{ + uint8_t baudIndex; + + //Simple port mapping + __disable_interrupt(); // Disable Interrupts before altering Port Mapping registers + PMAPKEYID = PMAPKEY; + P4MAP0 = PM_NONE; + P4MAP3 = PM_NONE; + P4MAP4 = PM_UCA0TXD; + P4MAP5 = PM_UCA0RXD; + PMAPKEYID = 0; + __enable_interrupt(); + + P4SEL |= BIT0 + BIT3 + BIT4 + BIT5; + + // configure USCI_A0 UART + UCA0CTL1 |= UCSWRST; // **Put state machine in reset** + UCA0CTL1 |= UCSSEL__SMCLK; // SMCLK + UCA0CTL0 = UCPEN+UCPAR; + + switch(lBaudrate) + { + #if (RX_BUFFER_SIZE > (1200*SYS_DELAY/1000/8)) + case 1200: baudIndex = BAUD_1200; break; + #endif + #if (RX_BUFFER_SIZE > (2400*SYS_DELAY/1000/8)) + case 2400: baudIndex = BAUD_2400; break; + #endif + #if(RX_BUFFER_SIZE > (4800*SYS_DELAY/1000/8)) + case 4800: baudIndex = BAUD_4800; break; + #endif + case 4801: // Invoke Rocket's BSL + __disable_interrupt(); + USB_disable(); + __delay_cycles(500000); + ((void(*)(void))0x1000)(); // Call #0x1000, enter BSL + break; + + case 4802: + BSL_reset_sequence(); + baudIndex = BAUD_9600; + break; + #if(RX_BUFFER_SIZE > (9600*SYS_DELAY/1000/8)) + case 9600: baudIndex = BAUD_9600; break; + #endif + case 9601: + BSL_invoke_sequence(); + baudIndex = BAUD_9600; + break; + #if(RX_BUFFER_SIZE > (19200*SYS_DELAY/1000/8)) + case 19200: baudIndex = BAUD_19200; break; + #endif + #if(RX_BUFFER_SIZE > (38400*SYS_DELAY/1000/8)) + case 38400: baudIndex = BAUD_38400; break; + #endif + #if(RX_BUFFER_SIZE > (57600*SYS_DELAY/1000/8)) + case 57600: baudIndex = BAUD_57600; break; + #endif + #if(RX_BUFFER_SIZE > (115200*SYS_DELAY/1000/8)) + case 115200: baudIndex = BAUD_115200; break; + #endif + #if(RX_BUFFER_SIZE > (230400*SYS_DELAY/1000/8)) + case 230400: baudIndex = BAUD_230400; break; + #endif + #if(RX_BUFFER_SIZE > (460800*SYS_DELAY/1000/8)) + case 460800: baudIndex = BAUD_460800; break; + #endif + #if(RX_BUFFER_SIZE > (921600*SYS_DELAY/1000/8)) + case 921600: baudIndex = BAUD_921600; break; + #endif + default: baudIndex = BAUD_ERROR; break; + } + + if(baudIndex != BAUD_ERROR) + { + UCA0BR0 = BaudrateList[baudIndex].ucaBR0; + UCA0BR1 = BaudrateList[baudIndex].ucaBR1; + UCA0MCTL = BaudrateList[baudIndex].ucaMCTL; + } + + UCA0CTL1 &= ~UCSWRST; // Initialize USCI state machine + + UCA0IE |= UCRXIE; + + return baudIndex; +} + +void uartControl() +{ + /* Send data from USB buffer to UART */ + if(USBCDC_bytesInUSBBuffer(CDC0_INTFNUM) > 0) + { + if(UCA0IFG & UCTXIFG) + { + USBCDC_receiveData((uint8_t *)&UCA0TXBUF, 1, CDC0_INTFNUM); + LED2_TOGGLE + } + } + + if(UARTtoCDC_TXPtr != UARTtoCDC_RXPtr) + { + while(cdcSendDataWaitTilDone((uint8_t*)&UARTtoCDC_CircularBuffer[UARTtoCDC_TXPtr], 1, CDC0_INTFNUM, 100000) != 0); + UARTtoCDC_TXPtr++; + if (UARTtoCDC_TXPtr == BUFFER_SIZE) + { + UARTtoCDC_TXPtr = 0; + } + } +} + +#pragma vector=USCI_A0_VECTOR +__interrupt void USCI_A0_ISR(void) +{ + switch(__even_in_range(UCA0IV,4)) + { + case 0: // Vector 0 - no interrupt + break; + case 2: // Vector 2 - RXIFG + // Store received byte in TX buffer + UARTtoCDC_CircularBuffer[UARTtoCDC_RXPtr++] = UCA0RXBUF; + if (UARTtoCDC_RXPtr == BUFFER_SIZE) + { + UARTtoCDC_RXPtr = 0; + } + break; + case 4: // Vector 4 - TXIFG + __no_operation(); // used for debugging + break; + default: break; + } +} + + +/*** I2C *********************************************************************/ +#define UART_HEADER 0x80 +#define UART_CMD_HEADER 0xA0 +#define UART_HEADER_LENGTH 1 // length in byte +#define UART_LENGTH_LENGTH 2 // length in byte +#define UART_CRC_LENGTH 2 // length in byte +#define UART_CMD_LENGTH 1 // length in byte + +#define TIMEOUT_RECEPTION 1000000 + +#define BSL_RESPONSE_ACK 0x00 + +// define STATES +#define SWAIT 0x00 +#define SSTART 0x01 +#define SLENGTH 0x02 +#define SDATA 0x03 +#define SSEND 0x04 +#define SCMD 0x05 + +unsigned char ret; +unsigned int bytes_sent, bytes_received; +int16_t sendDataLength = 0; +unsigned int BSLCommandLength = 0; +int16_t requireSlaveAnswer = 1; +unsigned char dataBuffer[300]; +volatile unsigned char bDataSendCompleted_event[CDC_NUM_INTERFACES] = {FALSE}; +volatile unsigned char bDataReceiveCompleted_event[CDC_NUM_INTERFACES] = {FALSE}; // data receive completed event +unsigned char *PTxData; // Pointer to TX data +int TXByteCtr; +unsigned char *PRxData; // Pointer to RX data +int RXByteCtr; +unsigned char RxBuffer[256]; + +unsigned char ACK = 0; +unsigned int rxlength = 0; + +unsigned int length = 0; +unsigned char state = SWAIT; + +unsigned char CoreCommand[256]; +unsigned char i = 0; + +extern volatile unsigned char bDataReceiveCompleted_event[]; // data receive completed event + +enum +{ + I2C_IDLE, + I2C_RECEIVING, + I2C_RECEIVE_COMPLETE, + I2C_TRANSMITTING, + I2C_TRANSMIT_COMPLETE, + I2C_ERROR +} I2C_Status_e; + + +//! Initialization of the USCI Module for I2C +int8_t InitI2C(unsigned char eeprom_i2c_address, uint32_t bitrate) +{ + int8_t ret = 1; + + //Simple port mapping + __disable_interrupt(); // Disable Interrupts before altering Port Mapping registers + PMAPKEYID = PMAPKEY; + P4MAP0 = PM_UCB0SCL; + P4MAP3 = PM_NONE; + P4MAP4 = PM_NONE; + P4MAP5 = PM_UCB0SDA; + PMAPKEYID = 0; + __enable_interrupt(); + + P4SEL |= BIT0 + BIT3 + BIT4 + BIT5; + + UCB0CTL1 = UCSWRST; // Enable SW reset + + UCB0CTL0 = UCMST + UCMODE_3 + UCSYNC; // I2C Master, synchronous mode + UCB0CTL1 = UCSSEL_2 + UCSWRST; // Use SMCLK, keep SW reset + + switch(bitrate) + { + case 100001: + P1OUT ^= (BIT0|BIT1); + BSL_invoke_sequence(); + P1OUT |= (BIT0); + UCB0BR0 = SCL_CLOCK_DIV(100000); // set prescaler + break; + case 100000: + P1OUT |= (BIT0); + UCB0BR0 = SCL_CLOCK_DIV(100000); // set prescaler + break; + case 400001: + P1OUT ^= (BIT0|BIT1); + BSL_invoke_sequence(); + P1OUT |= (BIT1); + UCB0BR0 = SCL_CLOCK_DIV(400000); // set prescaler + break; + case 400000: + P1OUT |= (BIT1); + UCB0BR0 = SCL_CLOCK_DIV(400000); // set prescaler + break; + default: + ret = 1; + } + + UCB0BR1 = 0; + UCB0I2CSA = eeprom_i2c_address; // Set slave address + + I2C_PORT_SEL |= SDA_PIN + SCL_PIN; // select module function for the used I2C pins + + UCB0CTL1 &= ~UCSWRST; // Clear SW reset, resume operation + + PRxData = RxBuffer; // Incase no receive buffer is assigned + + if(UCB0STAT & UCBBUSY) // test if bus to be free + { // otherwise a manual Clock on is generated + I2C_PORT_SEL &= ~SCL_PIN; // Select Port function for SCL + I2C_PORT_OUT &= ~SCL_PIN; // + I2C_PORT_DIR |= SCL_PIN; // drive SCL low + I2C_PORT_SEL |= SDA_PIN + SCL_PIN; // select module function for the used I2C pins + }; + + I2C_Status_e = I2C_IDLE; + + return ret; +} + +int16_t i2cSendMessage(unsigned char* I2cMessage, int messageLength) +{ + UCB0IE &= ~UCRXIE; // disable RX ready interrupt + UCB0IFG &= ~(UCTXIFG + UCSTPIFG + UCNACKIFG); // clear TX ready and stop interrupt flag + UCB0IE |= UCTXIE | UCNACKIE; // enable TX ready interrupt + + PTxData = (unsigned char *)I2cMessage; // TX array start address + + TXByteCtr = messageLength ; // Load TX byte counter + + I2C_Status_e = I2C_TRANSMITTING; + UCB0CTL1 |= UCTR + UCTXSTT; // I2C TX, start condition + // while (UCB0CTL1 & UCTXSTT); // Start condition sent? + // while (UCB0STAT & UCBBUSY); // wait for bus to be free !!!!! + // UCB0IE &= ~UCSTPIE; // disable STOP interrupt + + while(I2C_Status_e == I2C_TRANSMITTING); + + if(I2C_Status_e == I2C_TRANSMIT_COMPLETE) + { + // check for commands that doesn't require an ack + PTxData = (unsigned char *)I2cMessage; // TX array start address + + if((*(PTxData + UART_HEADER_LENGTH + UART_LENGTH_LENGTH) == 0x1B)) + return 0; + else + return 1; + } + else if(I2C_Status_e == I2C_ERROR) + { + return -1; + } + + return -1; + +} + + +// returns number of received bytes +int16_t i2cReceiveMessage(unsigned char* I2cMessage) +{ + uint32_t timeout; + + UCB0CTL1 &= ~UCTR; + UCB0IE |= UCRXIE; // Enable RX interrupt + + PRxData = (unsigned char *)I2cMessage; // Start of RX buffer + RXByteCtr = 1; // Load RX byte counter + + ACK = 0; + I2C_Status_e = I2C_RECEIVING; + UCB0CTL1 |= UCTXSTT; + //__bis_SR_register(LPM0_bits + GIE); // Enter LPM0, enable interrupts + // Remain in LPM0 until all data + // is RX'd + timeout = TIMEOUT_RECEPTION; + while((I2C_Status_e == I2C_RECEIVING) && (timeout-- != 0x00)); + + if((timeout == 0) || (I2C_Status_e == I2C_ERROR)) + { + i2cStopSending(); + timeout = TIMEOUT_RECEPTION; + while((UCB0CTL1 & UCTXSTP) && (timeout-- != 0)); + } + + if(I2C_Status_e == I2C_RECEIVE_COMPLETE) + { + return (rxlength > 0) ? 1 + I2C_HEADER_LENGTH + I2C_LENGTH_LENGTH + rxlength + I2C_CRC_LENGTH : 1 + I2C_HEADER_LENGTH + I2C_LENGTH_LENGTH; + } + else + { + return -1; + } +} + + +void i2cStopSending(void) +{ + UCB0CTL1 |= UCTXSTP; +} + + +void i2cControl() +{ + ret = USBCDC_intfStatus(CDC0_INTFNUM, &bytes_sent, &bytes_received); + if (ret & kUSBCDC_dataWaiting) + { + BSLCommandLength = UART_FSM(dataBuffer); + } + if (BSLCommandLength > 0) + { + // Special command to just get data + if (BSLCommandLength == 0x01) + { + // If response is OK, request response from Slave + sendDataLength = i2cReceiveMessage(dataBuffer); + if ((requireSlaveAnswer < 0) || (sendDataLength < 0)) + { + // If there was an error, report to PC + sendDataLength = 1; + dataBuffer[0] = 0x55; // Temporary error code + } + } + else + { + requireSlaveAnswer = i2cSendMessage(dataBuffer, BSLCommandLength); + i2cStopSending(); + __delay_cycles(10000); + + if (requireSlaveAnswer == 0x00) + { + sendDataLength = 0; // Don't send response to PC + } + else if(requireSlaveAnswer > 0) + { + // If response is OK, request response from Slave + sendDataLength = i2cReceiveMessage(dataBuffer); + } + + if ((requireSlaveAnswer < 0) || (sendDataLength < 0)) + { + // If there was an error, report to PC + sendDataLength = 1; + dataBuffer[0] = 0x55; // Temporary error code + } + BSLCommandLength = 0; + } + } + + if (sendDataLength > 0) + { + //send data back to PC + bDataSendCompleted_event[0] = FALSE; + ret = USBCDC_sendData((unsigned char*)&dataBuffer, sendDataLength, CDC0_INTFNUM); + while (bDataSendCompleted_event == FALSE){}; + sendDataLength = 0; + } +} + + +unsigned int UART_FSM(unsigned char* dataBuffer) +{ + unsigned int retvalue = 0; + + switch(state) + { + case(SWAIT): // wait for UART_HEADER to start the data sequence + USBCDC_receiveData(dataBuffer, UART_HEADER_LENGTH, CDC0_INTFNUM); + if(dataBuffer[0] == UART_HEADER) + { + length = 0; + state = SSTART; + } + else if (dataBuffer[0] == UART_CMD_HEADER) + { + state = SCMD; + } + + retvalue = 0; + break; + case(SSTART): // read in length bytes + bDataReceiveCompleted_event[0] = FALSE; + USBCDC_receiveData(dataBuffer + UART_HEADER_LENGTH, UART_LENGTH_LENGTH, CDC0_INTFNUM); + while (bDataReceiveCompleted_event[0] == FALSE){}; // wait until data received + length = ((unsigned char) dataBuffer[1 + UART_HEADER_LENGTH] << 8) | dataBuffer[0 + UART_HEADER_LENGTH]; + state = SDATA; + retvalue = 0; + break; + case(SDATA): // read in all data (length bytes) plus CRC + bDataReceiveCompleted_event[0] = FALSE; + USBCDC_receiveData(dataBuffer + UART_HEADER_LENGTH + UART_LENGTH_LENGTH, length + UART_CRC_LENGTH, CDC0_INTFNUM); + while (bDataReceiveCompleted_event[0] == FALSE){}; + + USBCDC_rejectData(CDC0_INTFNUM); // discard leftover bytes + + state = SWAIT; + retvalue = UART_HEADER_LENGTH + UART_LENGTH_LENGTH + length + UART_CRC_LENGTH; + break; + + case SCMD: + USBCDC_receiveData(dataBuffer, UART_CMD_LENGTH, CDC0_INTFNUM); + retvalue = dataBuffer[0]; + state = SWAIT; + break; + + default: + state = SWAIT; + retvalue = 0; + break; + } + return retvalue; +} + + +// ISR for I2C +#pragma vector = USCI_B0_VECTOR +__interrupt void USCI_B0_ISR(void) +{ + switch(__even_in_range(UCB0IV,USCI_I2C_UCTXIFG)) + { + case USCI_NONE: break; // Vector 0: No interrupts + case USCI_I2C_UCALIFG: break; // Vector 2: UCALIFG + case USCI_I2C_UCNACKIFG: + I2C_Status_e = I2C_ERROR; + break; // Vector 4: NACKIFG + case USCI_I2C_UCSTTIFG: break; // Vector 6: STTIFG + case USCI_I2C_UCSTPIFG: break; // Vector 8: STPIFG + case USCI_I2C_UCRXIFG: // Vector 10: RXIFG + + if (ACK == 0) + { + *PRxData++ = UCB0RXBUF; // Move RX data to address PRxData + if(*(PRxData-1) != BSL_RESPONSE_ACK) + { + UCB0CTL1 |= UCTXSTP; // Generate I2C stop condition + } + else + { + ACK = 1; + RXByteCtr = I2C_HEADER_LENGTH + I2C_LENGTH_LENGTH; // receives the next three bytes + rxlength = 0; + } + } + else + { + RXByteCtr--; // Decrement RX byte counter + if(RXByteCtr) + { + *PRxData++ = UCB0RXBUF; // Move RX data to address PRxData + if((RXByteCtr == 1) && (rxlength > 0)) // Only one byte left? + { + UCB0CTL1 |= UCTXSTP; // Generate I2C stop condition + } + } + else if(rxlength == 0) + { + *PRxData++ = UCB0RXBUF; // Move RX data to address PRxData + rxlength = ((unsigned int) *(PRxData-1) << 8) | *(PRxData-2); + if(rxlength == 0) UCB0CTL1 |= UCTXSTP; // stop receiving if no bytes required + { + RXByteCtr = rxlength + I2C_CRC_LENGTH; + } + } + else + { + *PRxData = UCB0RXBUF; // Move final RX data to PRxData + I2C_Status_e = I2C_RECEIVE_COMPLETE; + //__bic_SR_register_on_exit(LPM0_bits); // Exit active CPU + } + } + break; + case USCI_I2C_UCTXIFG: // Vector 12: TXIFG + if(TXByteCtr) // Check TX byte counter + { + UCB0TXBUF = *PTxData++; // Load TX buffer + TXByteCtr--; // Decrement TX byte counter + } + else + { + //UCB0CTL1 |= UCTXSTP; // Generate I2C stop condition + I2C_Status_e = I2C_TRANSMIT_COMPLETE; + //__bic_SR_register_on_exit(LPM0_bits); // Exit active CPU + } + break; + default: + break; + } +} + + +/*** SPI *********************************************************************/ +uint8_t spiInit(uint32_t lBaudrate) +{ + //Simple port mapping + __disable_interrupt(); // Disable Interrupts before altering Port Mapping registers + PMAPKEYID = PMAPKEY; + P4MAP0 = PM_UCB1CLK; + P4MAP3 = PM_NONE; // STE is driven by I/O pin (see below) + P4MAP4 = PM_UCB1SIMO; + P4MAP5 = PM_UCB1SOMI; + PMAPKEYID = 0; + __enable_interrupt(); + + P4SEL = BIT0 + BIT4 + BIT5; + + // Use P4.3 as (active low) STE signal + P4DIR |= BIT3; + P4OUT |= BIT3; // Disable SPI slave + + // configure USCI_B1 SPI + UCB1CTL1 = UCSWRST; // **Put state machine in reset** + UCB1CTL1 |= UCSSEL__ACLK; + // CKPH=0, idle high (CKPL=1), MSB first, master, 3-pin SPI, synchronous mode + UCB1CTL0 |= UCCKPL + UCMSB + UCMST + UCMODE_0 + UCSYNC; + + switch(lBaudrate) + { + case 125000: + UCB1BRW = 32; + break; + case 125001: + BSL_invoke_sequence(); + UCB1BRW = 32; + break; + case 250000: + UCB1BRW = 16; + break; + case 250001: + BSL_invoke_sequence(); + UCB1BRW = 16; + break; + case 500000: + UCB1BRW = 8; + break; + case 500001: + BSL_invoke_sequence(); + UCB1BRW = 8; + break; + case 1000000: + UCB1BRW = 4; + break; + case 1000001: + BSL_invoke_sequence(); + UCB1BRW = 4; + break; + default: + return 1; + break; + } + + UCB1CTL1 &= ~UCSWRST; // Initialize USCI state machine + + return 0; +} + +void spiControl() +{ + static uint16_t TXresponseLength = 0; + static uint16_t TXresponseIndex = 0; + static uint16_t RXresponseLength = 0; + static uint16_t RXresponseIndex = 0; + static enum spiStates spiState = idle; + + switch(spiState) + { + case idle: + { + P4OUT |= BIT3; // Disable SPI slave + /* Send data from USB buffer to SPI */ + if(USBCDC_bytesInUSBBuffer(CDC0_INTFNUM) > 0) + { + P4OUT &= ~BIT3; // Disable SPI slave + uint8_t txChar = 0; + UCB1IFG &= ~UCRXIFG; // Clear RX IRQ flag + USBCDC_receiveData(&txChar, 1, CDC0_INTFNUM); + while(!(UCB1IFG & UCTXIFG)); + UCB1TXBUF = txChar; + LED2_TOGGLE + if(txChar == 0x80) // Check for BSL header from host + { + UCB1IFG &= ~UCRXIFG; // Clear RX IRQ flag + spiState = TXlengthLow; + } + else + { + while(!(UCB1IFG & UCRXIFG)); + // Store received byte in TX buffer + *txBuffer_write_ptr = UCB1RXBUF; + txBuffer_write_ptr++; + if(txBuffer_write_ptr - txBuffer == TX_BUFFER_SIZE) + { + txBuffer_write_ptr = txBuffer; + } + } + } + break; + } + case TXlengthLow: + { + if(USBCDC_bytesInUSBBuffer(CDC0_INTFNUM) > 0) + { + uint8_t txChar = 0; + UCB1IFG &= ~UCRXIFG; // Clear RX IRQ flag + USBCDC_receiveData(&txChar, 1, CDC0_INTFNUM); + while(!(UCB1IFG & UCTXIFG)); + UCB1TXBUF = txChar; + LED2_TOGGLE + TXresponseLength = (uint16_t)txChar; + spiState = TXlengthHigh; + } + break; + } + case TXlengthHigh: + { + if(USBCDC_bytesInUSBBuffer(CDC0_INTFNUM) > 0) + { + uint8_t txChar = 0; + UCB1IFG &= ~UCRXIFG; // Clear RX IRQ flag + USBCDC_receiveData(&txChar, 1, CDC0_INTFNUM); + while(!(UCB1IFG & UCTXIFG)); + UCB1TXBUF = txChar; + LED2_TOGGLE + TXresponseLength |= (uint16_t)txChar << 8; + spiState = TXreceive; + } + break; + } + case TXreceive: + { + while(TXresponseIndex < TXresponseLength + SPI_CRC_LENGTH) // Wait for BSL command to be send from host completely + { + /* Send data from USB buffer to SPI */ + if(USBCDC_bytesInUSBBuffer(CDC0_INTFNUM) > 0) + { + UCB1IFG &= ~UCRXIFG; // Clear RX IRQ flag + while(!(UCB1IFG & UCTXIFG)); + USBCDC_receiveData((uint8_t *)&UCB1TXBUF, 1, CDC0_INTFNUM); + LED2_TOGGLE + TXresponseIndex++; + } + } + if(TXresponseIndex == TXresponseLength + SPI_CRC_LENGTH) + { + __delay_cycles(500000); // Wait for target + UCB1IFG &= ~UCRXIFG; // Clear RX IRQ flag + // Shift SPI to receive BSL response + while(!(UCB1IFG & UCTXIFG)); + UCB1TXBUF = 0xFF; + while(UCB1STAT & UCBUSY); // Wait for completed send operation + // Send response to host + while(!(UCB1IFG & UCRXIFG)); + uint8_t rxChar = UCB1RXBUF; + // Store received byte in TX buffer + *txBuffer_write_ptr = rxChar; + txBuffer_write_ptr++; + if(txBuffer_write_ptr - txBuffer == TX_BUFFER_SIZE) + { + txBuffer_write_ptr = txBuffer; + } + if(rxChar != 0x00) // BSL NACK + { + spiState = idle; + } + else // BSL ACK Retrieve and send BSL core response + { + spiState = RXheader; + } + TXresponseLength = 0; + TXresponseIndex = 0; + } + break; + } + case RXheader: + { + // Shift SPI to receive BSL response + while(!(UCB1IFG & UCTXIFG)); + UCB1TXBUF = 0xFF; + while(UCB1STAT & UCBUSY); // Wait for completed send operation + // Send response to host + while(!(UCB1IFG & UCRXIFG)); + uint8_t rxChar = UCB1RXBUF; + for(uint8_t retryIndex = 50; retryIndex > 0; retryIndex--) + { + if(rxChar != 0x80) + { + __delay_cycles(250000); // Wait ~10ms for BSL response + // Shift SPI to receive BSL response + while(!(UCB1IFG & UCTXIFG)); + UCB1TXBUF = 0xFF; + while(UCB1STAT & UCBUSY); // Wait for completed send operation + // Send response to host + while(!(UCB1IFG & UCRXIFG)); + rxChar = UCB1RXBUF; + } else { + break; + } + } + // Store received byte in TX buffer + *txBuffer_write_ptr = rxChar; + txBuffer_write_ptr++; + if(txBuffer_write_ptr - txBuffer == TX_BUFFER_SIZE) + { + txBuffer_write_ptr = txBuffer; + } + spiState = RXlengthLow; + break; + } + case RXlengthLow: + { + // Shift SPI to receive BSL response + while(!(UCB1IFG & UCTXIFG)); + UCB1TXBUF = 0xFF; + while(UCB1STAT & UCBUSY); // Wait for completed send operation + // Send response to host + while(!(UCB1IFG & UCRXIFG)); + uint8_t rxChar = UCB1RXBUF; + RXresponseLength = (uint16_t)rxChar; + // Store received byte in TX buffer + *txBuffer_write_ptr = rxChar; + txBuffer_write_ptr++; + if(txBuffer_write_ptr - txBuffer == TX_BUFFER_SIZE) + { + txBuffer_write_ptr = txBuffer; + } + spiState = RXlengthHigh; + break; + } + case RXlengthHigh: + { + // Shift SPI to receive BSL response + while(!(UCB1IFG & UCTXIFG)); + UCB1TXBUF = 0xFF; + while(UCB1STAT & UCBUSY); // Wait for completed send operation + // Send response to host + while(!(UCB1IFG & UCRXIFG)); + uint8_t rxChar = UCB1RXBUF; + RXresponseLength |= (uint16_t)rxChar << 8; + // Store received byte in TX buffer + *txBuffer_write_ptr = rxChar; + txBuffer_write_ptr++; + if(txBuffer_write_ptr - txBuffer == TX_BUFFER_SIZE) + { + txBuffer_write_ptr = txBuffer; + } + spiState = RXreceive; + break; + } + case RXreceive: + { + if(RXresponseIndex < RXresponseLength + SPI_CRC_LENGTH) // Wait for BSL response to be received completely + { + // Shift SPI to receive BSL response + while(!(UCB1IFG & UCTXIFG)); + UCB1TXBUF = 0xFF; + while(UCB1STAT & UCBUSY); // Wait for completed send operation + // Send response to host + while(!(UCB1IFG & UCRXIFG)); + // Store received byte in TX buffer + *txBuffer_write_ptr = UCB1RXBUF; + txBuffer_write_ptr++; + if(txBuffer_write_ptr - txBuffer == TX_BUFFER_SIZE) + { + txBuffer_write_ptr = txBuffer; + } + RXresponseIndex++; + } + if(RXresponseIndex == RXresponseLength + SPI_CRC_LENGTH) + { + RXresponseLength = 0; + RXresponseIndex = 0; + spiState = idle; + } + break; + } + default: + break; + } + + /* Send data from USB buffer to host */ + if(txBuffer_read_ptr - txBuffer == TX_BUFFER_SIZE) + { + txBuffer_read_ptr = txBuffer; + } + if(txBuffer_read_ptr != txBuffer_write_ptr) + { + /* New data in txBuffer, send it */ + uint16_t bytes_to_send = 0; + // In case the write ptr < the read ptr sent till end of buffer... + if(txBuffer_write_ptr < txBuffer_read_ptr) + { + bytes_to_send = TX_BUFFER_SIZE - (txBuffer_read_ptr - txBuffer); + if(kUSBCDC_sendStarted == USBCDC_sendData(txBuffer_read_ptr, bytes_to_send, CDC0_INTFNUM)) + { + txBuffer_read_ptr += bytes_to_send; + } + } + // ... else sent till catching up with the write pts. + else + { + bytes_to_send = txBuffer_write_ptr - txBuffer_read_ptr; + if(kUSBCDC_sendStarted == USBCDC_sendData(txBuffer_read_ptr, bytes_to_send, CDC0_INTFNUM)) + { + txBuffer_read_ptr += bytes_to_send; + } + } + } +} diff --git a/source/peripherals.h b/source/peripherals.h new file mode 100644 index 0000000..942d488 --- /dev/null +++ b/source/peripherals.h @@ -0,0 +1,160 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +/* + * ======== hal.c ======== + * + */ +#include +#include +#include "descriptors.h" + +#ifndef _PERIPHERALS_H_ +#define _PERIPHERALS_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +// Maximal host system delay +#define MAX_SYS_DELAY 20 // ms + +// Size of Rx/Tx UART Buffers +// Value should be big enough to cover max system delay +#define RX_BUFFER_SIZE 1280 // max_baud * SYS_DELAY ms/1000/8bit +#define TX_BUFFER_SIZE MAX_PACKET_SIZE // Don't modyfy this value!!! + + +enum active_peripherals{None, UART, I2C, SPI}; +extern enum active_peripherals active_peripheral; +extern uint8_t rxBuffer[RX_BUFFER_SIZE]; +extern uint8_t txBuffer[TX_BUFFER_SIZE]; +extern uint8_t *txBuffer_read_ptr; +extern uint8_t *txBuffer_write_ptr; + +uint8_t BaudrateSelect(uint32_t lBaudrate); + +extern uint32_t current_baudrate; + +void disable_peripherals(); + +void startup_led_sequence(); // Blink the LEDs +#define LED_POUT P1OUT +#define LED1_PIN BIT0 +#define LED2_PIN BIT1 +#define LED1_ON {LED_POUT |= LED1_PIN;} +#define LED1_OFF {LED_POUT &= ~LED1_PIN;} +#define LED1_TOGGLE {LED_POUT ^= LED1_PIN;} +#define LED2_ON {LED_POUT |= LED2_PIN;} +#define LED2_OFF {LED_POUT &= ~LED2_PIN;} +#define LED2_TOGGLE {LED_POUT ^= LED2_PIN;} + +#define LED_BLINK_DELAY 5000000 +#define LED_BLINK_COUNT 3 + +/*** BSL entry sequence ******************************************************/ + +#define ENTRY_SEQ_PDIR PJDIR +#define ENTRY_SEQ_POUT PJOUT +#define RESET_PIN BIT1 +#define TEST_PIN BIT2 +#define TCK_PIN BIT3 + +#define RESET_HIGH {ENTRY_SEQ_POUT |= RESET_PIN;} +#define RESET_LOW {ENTRY_SEQ_POUT &= ~RESET_PIN;} +#define TEST_HIGH {ENTRY_SEQ_POUT |= TEST_PIN;} +#define TEST_LOW {ENTRY_SEQ_POUT &= ~TEST_PIN;} +#define TCK_HIGH {ENTRY_SEQ_POUT |= TCK_PIN;} +#define TCK_LOW {ENTRY_SEQ_POUT &= ~TCK_PIN;} + +#define INVOKE_DELAY 10000 + +// Timing for Pin Toggling during BSL Entry Sequence +// TEST PIN reset time = 10us (must be less than 15us) +#define BSL_ENTRY_SEQUENCE_TIME 50 + +void BSL_invoke_sequence(); // Toggle RST/TST/TCK pins for BSL invoke +void BSL_reset_sequence(); // Reset sequence to leave BSL (JTAG20 workaround) + + +/*** UART ********************************************************************/ +uint8_t InitUart(uint32_t lBaudrate); +void uartControl(); + +/*** I2C *********************************************************************/ +#define BSL_SLAVE_ADDR 0x48 + +#define I2C_PORT_SEL P4SEL +#define I2C_PORT_OUT P4OUT +#define I2C_PORT_REN P4REN +#define I2C_PORT_DIR P4DIR + +#define SDA_PIN BIT5 +#define SCL_PIN BIT0 +#define SCL_CLOCK_DIV(X) (USB_MCLK_FREQ/X) + +#define BSL_NO_RESPONSE_REQUIRED 0xAE +#define BSL_ERROR_HEADER_INCORRECT 0x51 +#define BSL_ERROR_INCORRECT_RESPONSE_CRC 0xA0 +#define BSL_ERROR_OK 0x00 + +#define I2C_HEADER 0x80 +#define I2C_HEADER_LENGTH 1 // length in byte +#define I2C_LENGTH_LENGTH 2 // length in byte +#define I2C_CRC_LENGTH 2 // length in byte + +// Init I2C module B0 and according port settings +int8_t InitI2C(unsigned char eeprom_i2c_address, uint32_t bitrate); +int16_t i2cSendMessage(unsigned char* I2cMessage, int messageLength); +int16_t i2cReceiveMessage(unsigned char* I2cMessage); +void i2cBslEntrySequence(void); +void i2cStopSending(void); +unsigned int UART_FSM(unsigned char *dataBuffer); + +void i2cControl(void); + + +/*** SPI *********************************************************************/ +#define SPI_CRC_LENGTH 2 // length in byte + +enum spiStates {idle, TXheader, TXlengthLow, TXlengthHigh, TXreceive, RXheader, RXlengthLow, RXlengthHigh, RXreceive}; + +// Future enhancement for SPI + +uint8_t spiInit(uint32_t lBaudrate); +void spiControl(); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/timer.c b/timer.c deleted file mode 100644 index f4a6fd0..0000000 --- a/timer.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * timer.c - * - * Generates period for checking UART buffer and Task Queue. - * - * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include -#include "USB_API/USB_Common/types.h" -#include "main.h" - -#include "descriptors.h" -#include "uart.h" - -//---------------------------------------------------------------------------- -// TimerA2 Init -VOID Init_TimerA2(VOID) -{ - TA2CCTL0 = CCIE; // CCR0 interrupt enabled - TA2CTL = TASSEL_1 + TACLR; // ACLK, clear TAR - - TA2CTL &= ~MC_1; // Turn off Timer - TA2CCR0 = 33; // Set Timer Period = 1 ms - TA2CTL |= MC_1; // Start Timer -} - -//----------------------------------------------------------------------------- -// Timer1 A0 interrupt service routine -#pragma vector=TIMER2_A0_VECTOR -__interrupt void TIMER2_A0_ISR(void) -{ - #ifdef UART0_INTFNUM - UartToCdc(UART0_INTFNUM, CDC0_INTFNUM); - #endif - #ifdef UART1_INTFNUM - UartToCdc(UART1_INTFNUM, CDC1_INTFNUM); - #endif - - //BlinkLed(); -} - -//============================================================================== -// End of file timer.c -//============================================================================== diff --git a/timer.h b/timer.h deleted file mode 100644 index 360da6f..0000000 --- a/timer.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * timer.h - * - * Generates period for checking UART buffer and Task Queue. - * - * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef TIMER_H_ -#define TIMER_H_ - -// Initialize TimerA2 -VOID Init_TimerA2(VOID); - -#endif //TIMER_H_ \ No newline at end of file diff --git a/uart.c b/uart.c deleted file mode 100644 index a0d9ebd..0000000 --- a/uart.c +++ /dev/null @@ -1,993 +0,0 @@ -/* - * uart.c - * - * Implementation of UART Bridge. - * - * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include -#include - -#include "USB_API/USB_Common/types.h" -#include "main.h" -#include "USB_API/USB_Common/types.h" -#include "USB_API/USB_Common/defMSP430USB.h" -#include "USB_API/USB_Common/usb.h" // USB-specific Data Structures -#include "USB_API/USB_CDC_API/UsbCdc.h" -#include "uart.h" - -#include -//function pointers -extern VOID *(*USB_RX_memcpy)(VOID * dest, const VOID * source, size_t count); -extern VOID *(*USB_TX_memcpy)(VOID * dest, const VOID * source, size_t count); - -//------------------------------------------------------------------------------ -// Global Variables -//------------------------------------------------------------------------------ -extern __no_init tEDB __data16 tInputEndPointDescriptorBlock[]; -extern __no_init tEDB __data16 tOutputEndPointDescriptorBlock[]; - -//------------------------------------------------------------------------------ - -// List of standard baudrates -const struct _BaudrateList{ - BYTE ucaBR0, ucaBR1, ucaMCTL; -}BaudrateList[] = { // CLK 20MHz - {0x00, 0x00, 0x00}, - {0x1A, 0x41, UCBRS_5}, // 1.2 kb/s - {0x8D, 0x20, UCBRS_3}, // 2.4 kb/s - {0x46, 0x10, UCBRS_5}, // 4.8 kb/s - {0x82, 0x00, 0x30 + UCOS16}, // 9.6 kb/s - {0x41, 0x00, (UCBRF_2+UCOS16)}, // 19.2 kb/s - {0x20, 0x00, (UCBRF_9+UCOS16)}, // 38.4 kb/s - {0x15, 0x00, (UCBRF_11+UCOS16)}, // 57.6 kb/s - {0x0A, 0x00, (UCBRF_14+UCOS16)}, // 115.2 kbit/s - {0x05, 0x00, (UCBRF_7+UCOS16)}, // 230.4 kbit/s - {0x02, 0x00, (UCBRS_6+UCBRF_10+UCOS16)}, // 460.8 kbit/s - {0x15, 0x00, (UCBRS_6)} // 921.6 kbit/s -}; - -// Baudrate indexes -enum baud{ BAUD_ERROR, BAUD_1200, BAUD_2400, BAUD_4800, BAUD_9600, BAUD_19200, - BAUD_38400, BAUD_57600, BAUD_115200, BAUD_230400, BAUD_460800, BAUD_921600}; - -// Macro gets number of UART channels -#ifdef UART0_INTFNUM - #ifdef UART1_INTFNUM - #define UART_NUM_INTERFACES 2 - #else - #define UART_NUM_INTERFACES 1 - #endif -#else - #ifdef UART1_INTFNUM - #define UART_NUM_INTERFACES 1 - #endif -#endif - -// Rx/Tx Buffers -#if ( UART_NUM_INTERFACES ) -static struct _UartBridge -{ - // indicates which buffer is used by host to receive/transmit data - BYTE inpCurrentBufferXY; - BYTE outpCurrentBufferXY; - - BYTE txInProgress; - UINT rxBufferOffset; - - BYTE txBuffer[TX_BUFFER_SIZE]; - BYTE rxBuffer[RX_BUFFER_SIZE]; -}UartBridge[UART_NUM_INTERFACES]; -#endif - -//Local functions prototypes -VOID SetupDmaForUart0(VOID); -VOID SetupDmaForUart1(VOID); - -BYTE InitUart(ULONG lBaudrate) -{ - BYTE baudIndex; - - #ifdef __MSP430F550x - //SelectPin(3,3); // Assign P3.3 to UCA0TXD and.. - //SelectPin(3,4); // P3.4 to UCA0RXD - - SelectPin(4,4); // Assign P4.4 to UCA0TXD and.. - //SetPinOut(4,4); - SelectPin(4,5); // P4.5 to UCA0RXD - //SetPinOut(4,5); - - PJDIR |= (RESET_PIN | TEST_PIN); - -#ifdef JTAG_RELEASE - PJDIR = BIT2+BIT1; - PJOUT = BIT2+BIT1; -#endif - - - //Simple port mapping - __disable_interrupt(); // Disable Interrupts before altering Port Mapping registers - PMAPKEYID = PMAPKEY; - P4MAP4 = PM_UCA0TXD; - P4MAP5 = PM_UCA0RXD; - PMAPKEYID = 0; - __enable_interrupt(); - - #endif - #ifdef __MSP430F563x_F663x - SelectPin(2,0); // Assign P2.0 to UCA0TXD and.. - SelectPin(2,1); // P2.1 to UCA0RXD - #endif - - - // configure USCI_A0 UART - UCA0CTL1 |= UCSWRST; // **Put state machine in reset** - UCA0CTL1 |= UCSSEL__SMCLK; // SMCLK - UCA0CTL0 = UCPEN+UCPAR; - - switch(lBaudrate) - { - #if (RX_BUFFER_SIZE > (1200*SYS_DELAY/1000/8)) - case 1200: baudIndex = BAUD_1200; break; - #endif - #if (RX_BUFFER_SIZE > (2400*SYS_DELAY/1000/8)) - case 2400: baudIndex = BAUD_2400; break; - #endif - #if(RX_BUFFER_SIZE > (4800*SYS_DELAY/1000/8)) - case 4800: baudIndex = BAUD_4800; break; - #endif - case 4801: - __disable_interrupt(); - USB_disable(); - Delay(100000); - ((void(*)(void))0x1000)(); // Call #0x1000, enter BSL - break; - - case 4802: - P1OUT |= BIT0; - // JTAG 20 work around - // start, all high - PJOUT = RESET_PIN+TEST_PIN; - Delay(INVOKE_DELAY); - Delay(INVOKE_DELAY); - Delay(INVOKE_DELAY); - - //Step 1 - //RESET LOW - //TEST LOW - PJOUT = 0; - Delay(INVOKE_DELAY); - - //Step 2 - //RESET LOW - //TEST HIGH - PJOUT = TEST_PIN; - Delay(INVOKE_DELAY); - - //Step 3 - //RESET LOW - //TEST LOW - PJOUT = 0; - Delay(INVOKE_DELAY); - - //Step 4 - //RESET LOW - //TEST HIGH - PJOUT = TEST_PIN; - Delay(INVOKE_DELAY); - - //Step 5 - //RESET LOW - //TEST LOW - PJOUT = 0; - Delay(INVOKE_DELAY); - - //Step 6 - //RESET HIGH - //TEST LOW - PJOUT = RESET_PIN; - Delay(INVOKE_DELAY); - Delay(INVOKE_DELAY); - Delay(INVOKE_DELAY); - - baudIndex = BAUD_9600; - break; - #if(RX_BUFFER_SIZE > (9600*SYS_DELAY/1000/8)) - case 9600: baudIndex = BAUD_9600; break; - #endif - case 9601: - P1OUT |= BIT1; - // invoke BSL, classic - //Start: all high - PJOUT = RESET_PIN+TEST_PIN+TCK_PIN; - Delay(INVOKE_DELAY); - Delay(INVOKE_DELAY); - Delay(INVOKE_DELAY); - - //Step 1 - //RESET LOW - //TEST LOW - //TCK HIGHT - PJOUT = TCK_PIN; - Delay(INVOKE_DELAY); - - //Step 2 - //RESET LOW - //TEST HIGH - //TCK LOW - PJOUT = TEST_PIN; - Delay(INVOKE_DELAY); - - //Step 3 - //RESET LOW - //TEST LOW - //TCK HIGH - PJOUT = TCK_PIN; - Delay(20); - - //Step 4 - //RESET LOW - //TEST HIGH - //TCK LOW - PJOUT = TEST_PIN; - Delay(INVOKE_DELAY); - - //Step 5 - //RESET HIGH - //TEST HIGH - //TCK LOW - PJOUT = TEST_PIN + RESET_PIN; - Delay(INVOKE_DELAY); - - //Step 6 - //RESET HIGH - //TEST LOW - //TCK HIGH - PJOUT = TCK_PIN + RESET_PIN; - Delay(INVOKE_DELAY); - Delay(INVOKE_DELAY); - Delay(INVOKE_DELAY); - - baudIndex = BAUD_9600; - break; - /* reserved for future devices invoke sequence - case 9602: newInvoke(2); break; - case 9603: newInvoke(3); break; - case 9604: newInvoke(4); break; - case 9605: newInvoke(5); break; - case 9606: newInvoke(6); break; - case 9607: newInvoke(7); break; - case 9608: newInvoke(8); break; - case 9609: newInvoke(9); break; - case 9610: newInvoke(10); break; - case 9611: newInvoke(11); break; - case 9612: newInvoke(12); break; - case 9613: newInvoke(13); break; - case 9614: newInvoke(14); break; - case 9615: newInvoke(15); break; - case 9616: newInvoke(16); break; - case 9617: newInvoke(17); break; - case 9618: newInvoke(18); break; - */ - #if(RX_BUFFER_SIZE > (19200*SYS_DELAY/1000/8)) - case 19200: baudIndex = BAUD_19200; break; - #endif - #if(RX_BUFFER_SIZE > (38400*SYS_DELAY/1000/8)) - case 38400: baudIndex = BAUD_38400; break; - #endif - #if(RX_BUFFER_SIZE > (57600*SYS_DELAY/1000/8)) - case 57600: baudIndex = BAUD_57600; break; - #endif - #if(RX_BUFFER_SIZE > (115200*SYS_DELAY/1000/8)) - case 115200:baudIndex = BAUD_115200; break; - #endif - #if(RX_BUFFER_SIZE > (230400*SYS_DELAY/1000/8)) - case 230400:baudIndex = BAUD_230400; break; - #endif - #if(RX_BUFFER_SIZE > (460800*SYS_DELAY/1000/8)) - case 460800:baudIndex = BAUD_460800; break; - #endif - #if(RX_BUFFER_SIZE > (921600*SYS_DELAY/1000/8)) - case 921600:baudIndex = BAUD_921600; break; - #endif - default: baudIndex = BAUD_ERROR; break; - } - - if(baudIndex != BAUD_ERROR) - { - UCA0BR0 = BaudrateList[baudIndex].ucaBR0; - UCA0BR1 = BaudrateList[baudIndex].ucaBR1; - UCA0MCTL = BaudrateList[baudIndex].ucaMCTL; - } - - //UCA0STAT |= 0x80; // Enable internal loopback - - UCA0CTL1 &= ~UCSWRST; // **Initialize USCI state machine** - //UCA0IE |= UCRXIE;// + UCTXIE; // Enable USCI_A0 Rx/Tx interrupt - - // SetupDmaForUart0(); - - UCA0IE |= UCRXIE; - - return baudIndex; -} - -#pragma vector=USCI_A0_VECTOR -__interrupt void USCI_A0_ISR(void) -{ - extern volatile BYTE bDataSendCompleted_event[]; - switch(__even_in_range(UCA0IV,4)) - { - case 0:break; // Vector 0 - no interrupt - case 2: // Vector 2 - RXIFG - _NOP(); // Send data received from UART to USB - bDataSendCompleted_event[0] = FALSE; - USBCDC_sendData((BYTE*)&UCA0RXBUF, 1, CDC0_INTFNUM); - while (bDataSendCompleted_event == FALSE){}; - UCA0IFG &= ~UCRXIFG; - break; - case 4: // Vector 4 - TXIFG - __no_operation(); // used for debugging - break; - default: break; - } -} - -#ifdef UART0_INTFNUM -//------------------------------------------------------------------------------ -BYTE InitUart0(ULONG lBaudrate) -{ - BYTE baudIndex; - - #ifdef __MSP430F550x - //SelectPin(3,3); // Assign P3.3 to UCA0TXD and.. - //SelectPin(3,4); // P3.4 to UCA0RXD - - SelectPin(4,4); // Assign P4.4 to UCA0TXD and.. - //SetPinOut(4,4); - SelectPin(4,5); // P4.5 to UCA0RXD - //SetPinOut(4,5); - -#ifdef JTAG_RELEASE - PJDIR = BIT2+BIT1; - PJOUT = BIT2+BIT1; -#endif - - - //Simple port mapping - __disable_interrupt(); // Disable Interrupts before altering Port Mapping registers - PMAPKEYID = PMAPKEY; - P4MAP4 = PM_UCA0TXD; - P4MAP5 = PM_UCA0RXD; - PMAPKEYID = 0; - __enable_interrupt(); - - #endif - #ifdef __MSP430F563x_F663x - SelectPin(2,0); // Assign P2.0 to UCA0TXD and.. - SelectPin(2,1); // P2.1 to UCA0RXD - #endif - - - // configure USCI_A0 UART - UCA0CTL1 |= UCSWRST; // **Put state machine in reset** - UCA0CTL1 |= UCSSEL__SMCLK; // SMCLK - UCA0CTL0 = UCPEN+UCPAR; - - switch(lBaudrate) - { - #if (RX_BUFFER_SIZE > (1200*SYS_DELAY/1000/8)) - case 1200: baudIndex = BAUD_1200; break; - #endif - #if (RX_BUFFER_SIZE > (2400*SYS_DELAY/1000/8)) - case 2400: baudIndex = BAUD_2400; break; - #endif - #if(RX_BUFFER_SIZE > (4800*SYS_DELAY/1000/8)) - case 4800: baudIndex = BAUD_4800; break; - #endif - case 4801: - __disable_interrupt(); - USB_disable(); - Delay(100000); - ((void(*)(void))0x1000)(); // Call #0x1000, enter BSL - break; - - case 4802: - P1OUT |= BIT0; - // JTAG 20 work around - // start, all high - PJOUT = RESET_PIN+TEST_PIN; - Delay(INVOKE_DELAY); - Delay(INVOKE_DELAY); - Delay(INVOKE_DELAY); - - //Step 1 - //RESET LOW - //TEST LOW - PJOUT = 0; - Delay(INVOKE_DELAY); - - //Step 2 - //RESET LOW - //TEST HIGH - PJOUT = TEST_PIN; - Delay(INVOKE_DELAY); - - //Step 3 - //RESET LOW - //TEST LOW - PJOUT = 0; - Delay(INVOKE_DELAY); - - //Step 4 - //RESET LOW - //TEST HIGH - PJOUT = TEST_PIN; - Delay(INVOKE_DELAY); - - //Step 5 - //RESET LOW - //TEST LOW - PJOUT = 0; - Delay(INVOKE_DELAY); - - //Step 6 - //RESET HIGH - //TEST LOW - PJOUT = RESET_PIN; - Delay(INVOKE_DELAY); - Delay(INVOKE_DELAY); - Delay(INVOKE_DELAY); - - baudIndex = BAUD_9600; - break; - #if(RX_BUFFER_SIZE > (9600*SYS_DELAY/1000/8)) - case 9600: baudIndex = BAUD_9600; break; - #endif - case 9601: - P1OUT |= BIT1; - // invoke BSL, classic - //Start: all high - PJOUT = RESET_PIN+TEST_PIN+TCK_PIN; - Delay(INVOKE_DELAY); - Delay(INVOKE_DELAY); - Delay(INVOKE_DELAY); - - //Step 1 - //RESET LOW - //TEST LOW - //TCK HIGHT - PJOUT = TCK_PIN; - Delay(INVOKE_DELAY); - - //Step 2 - //RESET LOW - //TEST HIGH - //TCK LOW - PJOUT = TEST_PIN; - Delay(INVOKE_DELAY); - - //Step 3 - //RESET LOW - //TEST LOW - //TCK HIGH - PJOUT = TCK_PIN; - Delay(20); - - //Step 4 - //RESET LOW - //TEST HIGH - //TCK LOW - PJOUT = TEST_PIN; - Delay(INVOKE_DELAY); - - //Step 5 - //RESET HIGH - //TEST HIGH - //TCK LOW - PJOUT = TEST_PIN + RESET_PIN; - Delay(INVOKE_DELAY); - - //Step 6 - //RESET HIGH - //TEST LOW - //TCK HIGH - PJOUT = TCK_PIN + RESET_PIN; - Delay(INVOKE_DELAY); - Delay(INVOKE_DELAY); - Delay(INVOKE_DELAY); - - baudIndex = BAUD_9600; - break; - /* reserved for future devices invoke sequence - case 9602: newInvoke(2); break; - case 9603: newInvoke(3); break; - case 9604: newInvoke(4); break; - case 9605: newInvoke(5); break; - case 9606: newInvoke(6); break; - case 9607: newInvoke(7); break; - case 9608: newInvoke(8); break; - case 9609: newInvoke(9); break; - case 9610: newInvoke(10); break; - case 9611: newInvoke(11); break; - case 9612: newInvoke(12); break; - case 9613: newInvoke(13); break; - case 9614: newInvoke(14); break; - case 9615: newInvoke(15); break; - case 9616: newInvoke(16); break; - case 9617: newInvoke(17); break; - case 9618: newInvoke(18); break; - */ - #if(RX_BUFFER_SIZE > (19200*SYS_DELAY/1000/8)) - case 19200: baudIndex = BAUD_19200; break; - #endif - #if(RX_BUFFER_SIZE > (38400*SYS_DELAY/1000/8)) - case 38400: baudIndex = BAUD_38400; break; - #endif - #if(RX_BUFFER_SIZE > (57600*SYS_DELAY/1000/8)) - case 57600: baudIndex = BAUD_57600; break; - #endif - #if(RX_BUFFER_SIZE > (115200*SYS_DELAY/1000/8)) - case 115200:baudIndex = BAUD_115200; break; - #endif - #if(RX_BUFFER_SIZE > (230400*SYS_DELAY/1000/8)) - case 230400:baudIndex = BAUD_230400; break; - #endif - #if(RX_BUFFER_SIZE > (460800*SYS_DELAY/1000/8)) - case 460800:baudIndex = BAUD_460800; break; - #endif - #if(RX_BUFFER_SIZE > (921600*SYS_DELAY/1000/8)) - case 921600:baudIndex = BAUD_921600; break; - #endif - default: baudIndex = BAUD_ERROR; break; - } - - if(baudIndex != BAUD_ERROR) - { - UCA0BR0 = BaudrateList[baudIndex].ucaBR0; - UCA0BR1 = BaudrateList[baudIndex].ucaBR1; - UCA0MCTL = BaudrateList[baudIndex].ucaMCTL; - } - - //UCA0STAT |= 0x80; // Enable internal loopback - - UCA0CTL1 &= ~UCSWRST; // **Initialize USCI state machine** - //UCA0IE |= UCRXIE;// + UCTXIE; // Enable USCI_A0 Rx/Tx interrupt - - SetupDmaForUart0(); - - return baudIndex; -} - -void newInvoke( BYTE invokeParam ) -{ -// TBD for new devices -} - -//------------------------------------------------------------------------------ -#pragma vector=USCI_A0_VECTOR -__interrupt void USCI_A0_ISR(void) -{ - switch(__even_in_range(UCA0IV,4)) - { - case 0:break; // Vector 0 - no interrupt - case 2:break; // Vector 2 - RXIFG - case 4: // Vector 4 - TXIFG - __no_operation(); // used for debugging - break; - default: break; - } -} - - -//------------------------------------------------------------------------------ -VOID SetupDmaForUart0(VOID) -{ - // configure DMA2 - DMACTL4 |= ROUNDROBIN;// + DMARMWDIS + ENNMI; - - DMACTL1 |= DMA2TSEL__USCIA0RX; // triger on USCIA0 receive - __data16_write_addr((unsigned short) &DMA2SA,(unsigned long) &UCA0RXBUF); - // Source block address - __data16_write_addr((unsigned short) &DMA2DA,// Destination single address - (unsigned long) UartBridge[UART0_INTFNUM].rxBuffer); - DMA2SZ = RX_BUFFER_SIZE; // Block size - DMA2CTL = DMADT_4 + DMADSTINCR_3 + DMALEVEL + - DMASBDB + DMAEN + DMAIE; // Rpt, inc dst, enable - - // configure DMA1 - DMACTL0 |= DMA1TSEL__USCIA0TX; // triger on USCIA0 transmit - __data16_write_addr((unsigned short) &DMA1SA,// Source block address - (unsigned long) UartBridge[UART0_INTFNUM].txBuffer); - __data16_write_addr((unsigned short) &DMA1DA,(unsigned long) &UCA0TXBUF); - // Destination single address - DMA1CTL = DMADT_0 + DMASRCINCR_3 + DMALEVEL + - DMASBDB + DMAIE; // inc src, int -} -#endif - -#ifdef UART1_INTFNUM -//------------------------------------------------------------------------------ -BYTE InitUart1(ULONG lBaudrate) -{ - BYTE baudIndex; - - #ifdef __MSP430F550x - SelectPin(4,4); // Assign P4.4 to UCA0TXD and.. - SelectPin(4,5); // P4.5 to UCA0RXD - #endif - #ifdef __MSP430F563x_F663x - SelectPin(8,2); // Assign P8.2 to UCA1TXD and.. - SelectPin(8,3); // P8.3 to UCA1RXD - #endif - - // configure USCI_A1 UART - UCA1CTL1 |= UCSWRST; // **Put state machine in reset** - UCA1CTL1 = UCSSEL__SMCLK; // SMCLK - - switch(lBaudrate) - { - #if (RX_BUFFER_SIZE > (1200*SYS_DELAY/1000/8)) - case 1200: baudIndex = BAUD_1200; break; - #endif - #if (RX_BUFFER_SIZE > (2400*SYS_DELAY/1000/8)) - case 2400: baudIndex = BAUD_2400; break; - #endif - #if(RX_BUFFER_SIZE > (4800*SYS_DELAY/1000/8)) - case 4800: baudIndex = BAUD_4800; break; - #endif - #if(RX_BUFFER_SIZE > (9600*SYS_DELAY/1000/8)) - case 9600: baudIndex = BAUD_9600; break; - #endif - #if(RX_BUFFER_SIZE > (19200*SYS_DELAY/1000/8)) - case 19200: baudIndex = BAUD_19200; break; - #endif - #if(RX_BUFFER_SIZE > (38400*SYS_DELAY/1000/8)) - case 38400: baudIndex = BAUD_38400; break; - #endif - #if(RX_BUFFER_SIZE > (57600*SYS_DELAY/1000/8)) - case 57600: baudIndex = BAUD_57600; break; - #endif - #if(RX_BUFFER_SIZE > (115200*SYS_DELAY/1000/8)) - case 115200:baudIndex = BAUD_115200; break; - #endif - #if(RX_BUFFER_SIZE > (230400*SYS_DELAY/1000/8)) - case 230400:baudIndex = BAUD_230400; break; - #endif - #if(RX_BUFFER_SIZE > (460800*SYS_DELAY/1000/8)) - case 460800:baudIndex = BAUD_460800; break; - #endif - //#if(RX_BUFFER_SIZE > (921600*SYS_DELAY/1000/8)) - //case 921600:baudIndex = BAUD_921600; break; - //#endif - default: baudIndex = BAUD_ERROR; break; - } - - if(baudIndex != BAUD_ERROR) - { - UCA1BR0 = BaudrateList[baudIndex].ucaBR0; - UCA1BR1 = BaudrateList[baudIndex].ucaBR1; - UCA1MCTL = BaudrateList[baudIndex].ucaMCTL; - } - - //UCA1STAT |= 0x80; // Enable internal loopback - - UCA1CTL1 &= ~UCSWRST; // **Initialize USCI state machine** - //UCA1IE |= UCRXIE + UCTXIE; // Enable USCI_A1 Rx/Tx interrupt - - SetupDmaForUart1(); - - return baudIndex; -} - -/* -//------------------------------------------------------------------------------ -#pragma vector=USCI_A1_VECTOR -__interrupt void USCI_A1_ISR(void) -{ - //BYTE tmp = 0x00; - switch(__even_in_range(UCA1IV,4)) - { - case 0:break; // Vector 0 - no interrupt - case 2: // Vector 2 - RXIFG - __no_operation(); // used for debugging - break; - case 4: // Vector 4 - TXIFG - __no_operation(); // used for debugging - break; - default: break; - } -} -*/ - -//------------------------------------------------------------------------------ -VOID SetupDmaForUart1(VOID) -{ - // configure DMA4 - DMACTL4 |= ROUNDROBIN;// + DMARMWDIS + ENNMI; - - DMACTL2 |= DMA4TSEL__USCIA1RX; // triger on USCIA1 receive - __data16_write_addr((unsigned short) &DMA4SA,(unsigned long) &UCA1RXBUF); - // Source block address - __data16_write_addr((unsigned short) &DMA4DA,// Destination single address - (unsigned long) UartBridge[UART1_INTFNUM].rxBuffer); - DMA4SZ = RX_BUFFER_SIZE; // Block size - DMA4CTL = DMADT_4 + DMADSTINCR_3 + DMALEVEL + - DMASBDB + DMAEN + DMAIE; // Rpt, inc dst, enable - - // configure DMA5 - DMACTL2 |= DMA5TSEL__USCIA1TX; // triger on USCIA1 transmit - __data16_write_addr((unsigned short) &DMA5SA,// Source block address - (unsigned long) UartBridge[UART1_INTFNUM].txBuffer); - __data16_write_addr((unsigned short) &DMA5DA,(unsigned long) &UCA1TXBUF); - // Destination single address - DMA5CTL = DMADT_0 + DMASRCINCR_3 + DMALEVEL + - DMASBDB + DMAIE; // inc src, int -} -#endif - -//------------------------------------------------------------------------------ -// DMA Interrupt Service Routine -//------------------------------------------------------------------------------ -#pragma vector=DMA_VECTOR -__interrupt void DMA_ISR(void) -{ - switch(__even_in_range(DMAIV,16)) - { - case 0: break; - case 2: break; // DMA0IFG = DMA Channel 0 - case 4: // DMA1IFG = DMA Channel 1 - #ifdef UART0_INTFNUM - UartBridge[UART0_INTFNUM].txInProgress = FALSE; - CdcToUart(CDC0_INTFNUM, UART0_INTFNUM); - #endif - break; - case 6: // DMA2IFG = DMA Channel 2 - #ifdef UART0_INTFNUM - UartToCdc(UART0_INTFNUM, CDC0_INTFNUM); - #endif - break; - case 8: // DMA3IFG = DMA Channel 3 -// #ifdef UART0_INTFNUM -// UartBridge[UART0_INTFNUM].txInProgress = FALSE; -// CdcToUart(CDC0_INTFNUM, UART0_INTFNUM); -// #endif - break; - case 10: // DMA4IFG = DMA Channel 4 - #ifdef UART1_INTFNUM - UartToCdc(UART1_INTFNUM, CDC1_INTFNUM); - #endif - break; - case 12: // DMA5IFG = DMA Channel 5 - #ifdef UART1_INTFNUM - UartBridge[UART1_INTFNUM].txInProgress = FALSE; - CdcToUart(CDC1_INTFNUM, UART1_INTFNUM); - #endif - break; - case 14: break; // DMA6IFG = DMA Channel 6 - case 16: break; // DMA7IFG = DMA Channel 7 - default: break; - } -} - -#if ( UART_NUM_INTERFACES ) -//------------------------------------------------------------------------------ -// Transfers data from the UART buffer to USB_CDC -//------------------------------------------------------------------------------ -BYTE UartToCdc(BYTE uartNum, BYTE cdcNum) -{ - BYTE nTmp; - UINT nCount, size; - PBYTE pPacket; - PBYTE pEP1, pEP2; - PBYTE pCT1, pCT2; - BYTE edbIndex = stUsbHandle[cdcNum].edb_Index; - - // do not access USB memory if suspended (PLL off). It may produce BUS_ERROR - if ((bFunctionSuspended) || - (bEnumerationStatus != ENUMERATION_COMPLETE)) - return FALSE; - - if (UartBridge[uartNum].inpCurrentBufferXY == X_BUFFER) //get current buffer - { // X_BUFFER is the active EP buffer - pEP1 = (PBYTE)stUsbHandle[cdcNum].iep_X_Buffer; - pCT1 = &tInputEndPointDescriptorBlock[edbIndex].bEPBCTX; - // second EP buffer - pEP2 = (PBYTE)stUsbHandle[cdcNum].iep_Y_Buffer; - pCT2 = &tInputEndPointDescriptorBlock[edbIndex].bEPBCTY; - } - else - { - // Y_BUFFER is the active EP buffer - pEP1 = (PBYTE)stUsbHandle[cdcNum].iep_Y_Buffer; - pCT1 = &tInputEndPointDescriptorBlock[edbIndex].bEPBCTY; - // second EP buffer - pEP2 = (PBYTE)stUsbHandle[cdcNum].iep_X_Buffer; - pCT2 = &tInputEndPointDescriptorBlock[edbIndex].bEPBCTX; - } - - // get DMA counter - #ifdef UART0_INTFNUM - if(uartNum == UART0_INTFNUM) - nCount = RX_BUFFER_SIZE - DMA2SZ; - #endif - - #ifdef UART1_INTFNUM - if(uartNum == UART1_INTFNUM) - nCount = RX_BUFFER_SIZE - DMA4SZ; - #endif - - if(UartBridge[uartNum].rxBufferOffset >= RX_BUFFER_SIZE) - UartBridge[uartNum].rxBufferOffset = 0; - - if(UartBridge[uartNum].rxBufferOffset > nCount) - nCount = RX_BUFFER_SIZE; - - nTmp = *pCT1; - if(nTmp & EPBCNT_NAK) - { - size = nCount - UartBridge[uartNum].rxBufferOffset; - if(size) - { - TogglePin(1,1); // LED2 = RX blink - // get packet pointer - pPacket = UartBridge[uartNum].rxBuffer + UartBridge[uartNum].rxBufferOffset; - - if(size > (MAX_PACKET_SIZE-1)) // check packet size - size = (MAX_PACKET_SIZE-1); - UartBridge[uartNum].rxBufferOffset += size; // update offset - - - USB_RX_memcpy(pEP1, pPacket, size); // copy data into EP X or Y buffer - *pCT1 = (BYTE)size; - - // switch current buffer - UartBridge[uartNum].inpCurrentBufferXY = (UartBridge[uartNum].inpCurrentBufferXY+1) &0x01; - } - } - - nTmp = *pCT2; - if(nTmp & EPBCNT_NAK) - { - size = nCount - UartBridge[uartNum].rxBufferOffset; - if(size) - { - // get packet pointer - pPacket = UartBridge[uartNum].rxBuffer + UartBridge[uartNum].rxBufferOffset; - - if(size > (MAX_PACKET_SIZE-1)) // check packet size - size = (MAX_PACKET_SIZE-1); - UartBridge[uartNum].rxBufferOffset += size; // update offset - - - USB_RX_memcpy(pEP2, pPacket, size); // copy data into EP X or Y buffer - *pCT2 = (BYTE)size; - - //switch current buffer - UartBridge[uartNum].inpCurrentBufferXY = (UartBridge[uartNum].inpCurrentBufferXY+1) &0x01; - } - } - - - return FALSE; -} - -//------------------------------------------------------------------------------ -// Transfers data from the USB_CDC buffer to UART -//------------------------------------------------------------------------------ -BYTE CdcToUart(BYTE cdcNum, BYTE uartNum) -{ - BYTE nCount; - PBYTE pEP, pCT; - BYTE edbIndex = stUsbHandle[cdcNum].edb_Index; - - - // Is transmit in progress? - if(UartBridge[uartNum].txInProgress) - return FALSE; - - // do not access USB memory if suspended (PLL off). It may produce BUS_ERROR - if ((bFunctionSuspended) || - (bEnumerationStatus != ENUMERATION_COMPLETE)) - return FALSE; - - // No data to transfer... - if (!((tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX | - tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY) & EPBCNT_NAK)) - return FALSE; - - if (UartBridge[uartNum].outpCurrentBufferXY == X_BUFFER)//get current buffer - { - //this is the active EP buffer - pEP = (PBYTE)stUsbHandle[cdcNum].oep_X_Buffer; - // how many byte we can get from endpoint buffer - pCT = &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTX; - } - else - { - //this is the active EP buffer - pEP = (PBYTE)stUsbHandle[cdcNum].oep_Y_Buffer; - // how many byte we can get from endpoint buffer - pCT = &tOutputEndPointDescriptorBlock[edbIndex].bEPBCTY; - } - - nCount = *pCT; - if(nCount & EPBCNT_NAK) - { - nCount &= ~EPBCNT_NAK; // clear NAK bit - if(nCount) - { - // copy data from EP X or Y buffer - USB_TX_memcpy(UartBridge[uartNum].txBuffer, pEP, nCount); - - // configure DMA - - #ifdef UART0_INTFNUM - if(uartNum == UART0_INTFNUM) - { - DMA1SZ = nCount; // set size - DMA1CTL |= DMAEN; // enable - } - #endif - - #ifdef UART1_INTFNUM - if(uartNum == UART1_INTFNUM) - { - DMA5SZ = nCount; // set size - DMA5CTL |= DMAEN; // enable - } - #endif - - // set tx status - UartBridge[uartNum].txInProgress = TRUE; - } - else - UartBridge[uartNum].txInProgress = FALSE; - - //clear NAK, EP ready to receive data - *pCT = 0x00; - - //switch current buffer - UartBridge[uartNum].outpCurrentBufferXY = (UartBridge[uartNum].outpCurrentBufferXY+1) &0x01; - } - - TogglePin(1,0); // LED1 = TX blink - - return FALSE; -} -#endif - -//============================================================================== -// End of file uart.c -//============================================================================== diff --git a/uart.h b/uart.h deleted file mode 100644 index 27dc417..0000000 --- a/uart.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * uart.h - * - * Implementation of UART Bridge. - * - * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef UART_H_ -#define UART_H_ - -#include "USB_config/descriptors.h" - -#ifdef UART_BASED - -// Enable/disable UART Bridge -// Comment definition for disabling the channel -#define UART0_INTFNUM 0 -#if CDC_NUM_INTERFACES >= 2 -#define UART1_INTFNUM 1 -#endif - -#endif // #define UART_BASED - -#if defined (__MSP430F6638__) -#define CLR_DTR0 P2OUT |= 0x04 -#define SET_DTR0 P2OUT &= ~0x04 -#define CLR_RTS0 P2OUT |= 0x08 -#define SET_RTS0 P2OUT &= ~0x08 -#define CLR_DTR1 P8OUT |= 0x01 -#define SET_DTR1 P8OUT &= ~0x01 -#define CLR_RTS1 P8OUT |= 0x02 -#define SET_RTS1 P8OUT &= ~0x02 -#endif - -#if defined (__MSP430F5509__) -#define SET_DTR0 P4OUT |= 0x08 -#define CLR_DTR0 P4OUT &= ~0x08 -#define CLR_RTS0 {P4OUT |= 0x04 ;P2OUT &= ~0x01;} -#define SET_RTS0 {P4OUT &= ~0x04;P2OUT |= 0x01;} -#endif - -#define RESET_HIGH {PJOUT |= BIT1;} -#define RESET_LOW {PJOUT &= ~BIT1;} -#define TEST_HIGH {PJOUT |= BIT2;} -#define TEST_LOW {PJOUT &= ~BIT2;} -#define RESET_PIN BIT1 -#define TEST_PIN BIT2 -#define TCK_PIN BIT3 - -// Maximal host system delay -#define MAX_SYS_DELAY 20 // ms - -// Size of Rx/Tx UART Buffers -// Value should be big enough to cover max system delay -#define RX_BUFFER_SIZE 1280 // max_baud * SYS_DELAY ms/1000/ 8bit -#define TX_BUFFER_SIZE MAX_PACKET_SIZE // Don't modyfy this value!!! - -// Initialize UART -BYTE InitUart(ULONG lBaudrate); -BYTE InitUart0(ULONG lBaudrate); -BYTE InitUart1(ULONG lBaudrate); - -// Transfers data from the UART buffer to USB_CDC. -BYTE UartToCdc(BYTE uartNum, BYTE cdcNum); - -// Transfers data from the USB_CDC buffer to UART. -BYTE CdcToUart(BYTE cdcNum, BYTE uartNum); - -void newInvoke( BYTE invokeParam ); -//#define INVOKE_DELAY 30000 -#define INVOKE_DELAY 1000 - -#endif //UART_H_ diff --git a/usb/usbConstructs.c b/usb/usbConstructs.c deleted file mode 100644 index 5f03fd1..0000000 --- a/usb/usbConstructs.c +++ /dev/null @@ -1,253 +0,0 @@ -#include "USB_API/USB_Common/device.h" -#include "USB_API/USB_Common/types.h" // Basic Type declarations - -#include "USB_config/descriptors.h" -#include "USB_API/USB_Common/usb.h" // USB-specific functions - -#ifdef _CDC_ - #include "USB_API/USB_CDC_API/UsbCdc.h" -#endif -#ifdef _HID_ - #include "USB_API/USB_HID_API/UsbHid.h" -#endif - -#include -#include "usbConstructs.h" - - -/************************************************************************************************** -These are example, user-editable construct functions for calling the API. - -In cases where fast development is the priority, it's usually best to use these sending -construct functions, rather than calling USBCDC_sendData() or USBHID_sendData() -directly. This is because they put boundaries on the "background execution" of sends, -simplfying the application. - -xxxsendDataWaitTilDone() essentially eliminates background processing altogether, always -polling after the call to send and not allowing execution to resume until it's done. This -allows simpler coding at the expense of wasted MCU cycles, and MCU execution being "locked" -to the host (also called "synchronous" operation). - -xxxsendDataInBackground() takes advantage of background processing ("asynchronous" operation) -by allowing sending to happen during application execution; while at the same time ensuring -that the sending always definitely occurs. It provides most of the simplicity of -xxxsendDataWaitTilDone() while minimizing wasted cycles. It's probably the best choice -for most applications. - -A true, asynchronous implementation would be the most cycle-efficient, but is the most -difficult to code; and can't be "contained" in an example function as these other approaches -are. Such an implementation might be advantageous in RTOS-based implementations or those -requiring the highest levels of efficiency. - -These functions take into account all the pertinent return codes, toward ensuring fully -robust operation. The send functions implement a timeout feature, using a loose "number of -retries" approach. This was done in order to avoid using additional hardware resources. A -more sophisticated approach, which the developer might want to implement, would be to use a -hardware timer. - -Please see the MSP430 CDC/HID/MSC USB API Programmer's Guide for a full description of these -functions, how they work, and how to use them. -**************************************************************************************************/ - - - -#ifdef _HID_ -/* This construct implements post-call polling to ensure the sending completes before the function - returns. It provides the simplest coding, at the expense of wasted cycles and potentially - allowing MCU execution to become "locked" to the host, a disadvantage if the host (or bus) is - slow. The function also checks all valid return codes, and returns non-zero if an error occurred. - It assumes no previous send operation is underway; also assumes size is non-zero. */ -BYTE hidSendDataWaitTilDone(BYTE* dataBuf, WORD size, BYTE intfNum, ULONG ulTimeout) -{ - ULONG sendCounter = 0; - WORD bytesSent, bytesReceived; - - switch(USBHID_sendData(dataBuf,size,intfNum)) { - case kUSBHID_sendStarted: - break; - case kUSBHID_busNotAvailable: - return 2; - case kUSBHID_intfBusyError: - return 3; - case kUSBHID_generalError: - return 4; - default:; - } - - /* If execution reaches this point, then the operation successfully started. Now wait til it's finished. */ - while(1) { - BYTE ret = USBHID_intfStatus(intfNum,&bytesSent,&bytesReceived); - if(ret & kUSBHID_busNotAvailable) /* This may happen at any time */ - return 2; - if(ret & kUSBHID_waitingForSend) - { - if(ulTimeout && (sendCounter++ >= ulTimeout)) /* Incr counter & try again */ - return 1 ; /* Timed out */ - } - else - return 0; /* If neither busNotAvailable nor waitingForSend, it succeeded */ - } -} - - -/* This construct implements pre-call polling to ensure the sending completes before the function -returns. It provides simple coding while also taking advantage of the efficiencies of background -processing. If a previous send operation is underway, this function does waste cycles polling, -like xxxsendDataWaitTilDone(); however it's less likely to do so since much of the sending -presumably took place in the background since the last call to xxxsendDataInBackground(). -The function also checks all valid return codes, and returns non-zero if an error occurred. -It assumes no previous send operation is underway; also assumes size is non-zero. -This call assumes a previous send operation might be underway; also assumes size is non-zero. -Returns zero if send completed; non-zero if it failed, with 1 = timeout and 2 = bus is gone. */ -BYTE hidSendDataInBackground(BYTE* dataBuf, WORD size, BYTE intfNum, ULONG ulTimeout) -{ - ULONG sendCounter = 0; - WORD bytesSent, bytesReceived; - - while(USBHID_intfStatus(intfNum,&bytesSent,&bytesReceived) & kUSBHID_waitingForSend) { - if(ulTimeout && ((sendCounter++)>ulTimeout)) /* A send operation is underway; incr counter & try again */ - return 1; /* Timed out */ - } - - /* The interface is now clear. Call sendData(). */ - switch(USBHID_sendData(dataBuf,size,intfNum)) { - case kUSBHID_sendStarted: - return 0; - case kUSBHID_busNotAvailable: - return 2; - default: - return 4; - } -} - - - -/* This call only retrieves data that is already waiting in the USB buffer -- that is, data that has -already been received by the MCU. It assumes a previous, open receive operation (began by a direct -call to USBxxx_receiveData()) is NOT underway on this interface; and no receive operation remains -open after this call returns. It doesn't check for kUSBxxx_busNotAvailable, because it doesn't -matter if it's not. size is the maximum that is allowed to be received before exiting; i.e., it -is the size allotted to dataBuf. Returns the number of bytes received. */ -WORD hidReceiveDataInBuffer(BYTE* dataBuf, WORD size, BYTE intfNum) -{ - WORD bytesInBuf,rxCount; - BYTE* currentPos=dataBuf; - - while(bytesInBuf = USBHID_bytesInUSBBuffer(intfNum)) - { - if((WORD)(currentPos-dataBuf+bytesInBuf) <= size) { - rxCount = bytesInBuf; - } - else { - rxCount = size; - } - - USBHID_receiveData(currentPos,rxCount,intfNum); - currentPos += bytesInBuf; - } - return (currentPos-dataBuf); -} -#endif - -/********************************************************************************************* -Please see the MSP430 USB CDC API Programmer's Guide Sec. 9 for a full description of these -functions, how they work, and how to use them. -**********************************************************************************************/ - -#ifdef _CDC_ -/* This construct implements post-call polling to ensure the sending completes before the function -returns. It provides the simplest coding, at the expense of wasted cycles and potentially -allowing MCU execution to become "locked" to the host, a disadvantage if the host (or bus) is -slow. The function also checks all valid return codes, and returns non-zero if an error occurred. -It assumes no previous send operation is underway; also assumes size is non-zero. */ -BYTE cdcSendDataWaitTilDone(BYTE* dataBuf, WORD size, BYTE intfNum, ULONG ulTimeout) -{ - ULONG sendCounter = 0; - WORD bytesSent, bytesReceived; - - switch(USBCDC_sendData(dataBuf,size,intfNum)) - { - case kUSBCDC_sendStarted: - break; - case kUSBCDC_busNotAvailable: - return 2; - case kUSBCDC_intfBusyError: - return 3; - case kUSBCDC_generalError: - return 4; - default:; - } - - /* If execution reaches this point, then the operation successfully started. Now wait til it's finished. */ - while(1) { - BYTE ret = USBCDC_intfStatus(intfNum,&bytesSent,&bytesReceived); - if(ret & kUSBCDC_busNotAvailable) /* This may happen at any time */ - return 2; - if(ret & kUSBCDC_waitingForSend) { - if(ulTimeout && (sendCounter++ >= ulTimeout)) /* Incr counter & try again */ - return 1 ; /* Timed out */ - } - else - return 0; /* If neither busNotAvailable nor waitingForSend, it succeeded */ - } -} - - - -/* This construct implements pre-call polling to ensure the sending completes before the function -returns. It provides simple coding while also taking advantage of the efficiencies of background -processing. If a previous send operation is underway, this function does waste cycles polling, -like xxxsendDataWaitTilDone(); however it's less likely to do so since much of the sending -presumably took place in the background since the last call to xxxsendDataInBackground(). -The function also checks all valid return codes, and returns non-zero if an error occurred. -It assumes no previous send operation is underway; also assumes size is non-zero. -This call assumes a previous send operation might be underway; also assumes size is non-zero. -Returns zero if send completed; non-zero if it failed, with 1 = timeout and 2 = bus is gone. */ -BYTE cdcSendDataInBackground(BYTE* dataBuf, WORD size, BYTE intfNum, ULONG ulTimeout) -{ - ULONG sendCounter = 0; - WORD bytesSent, bytesReceived; - - while(USBCDC_intfStatus(intfNum,&bytesSent,&bytesReceived) & kUSBCDC_waitingForSend) { - if(ulTimeout && ((sendCounter++)>ulTimeout)) /* A send operation is underway; incr counter & try again */ - return 1; /* Timed out */ - } - - /* The interface is now clear. Call sendData(). */ - switch(USBCDC_sendData(dataBuf,size,intfNum)) { - case kUSBCDC_sendStarted: - return 0; - case kUSBCDC_busNotAvailable: - return 2; - default: - return 4; - } -} - - - -/* This call only retrieves data that is already waiting in the USB buffer -- that is, data that has -already been received by the MCU. It assumes a previous, open receive operation (began by a direct -call to USBxxx_receiveData()) is NOT underway on this interface; and no receive operation remains -open after this call returns. It doesn't check for kUSBxxx_busNotAvailable, because it doesn't -matter if it's not. size is the maximum that is allowed to be received before exiting; i.e., it -is the size allotted to dataBuf. Returns the number of bytes received. */ -WORD cdcReceiveDataInBuffer(BYTE* dataBuf, WORD size, BYTE intfNum) -{ - WORD bytesInBuf,rxCount; - BYTE* currentPos=dataBuf; - - while(bytesInBuf = USBCDC_bytesInUSBBuffer(intfNum)) { - if((WORD)(currentPos-dataBuf+bytesInBuf) <= size) { - rxCount = bytesInBuf; - } - else { - rxCount = size; - } - - USBCDC_receiveData(currentPos,rxCount,intfNum); - currentPos += bytesInBuf; - } - return (currentPos-dataBuf); -} -#endif diff --git a/usb/usbConstructs.h b/usb/usbConstructs.h deleted file mode 100644 index 70b6636..0000000 --- a/usb/usbConstructs.h +++ /dev/null @@ -1,7 +0,0 @@ -BYTE hidSendDataWaitTilDone(BYTE* dataBuf, WORD size, BYTE intfNum, ULONG ulTimeout); -BYTE hidSendDataInBackground(BYTE* dataBuf, WORD size, BYTE intfNum, ULONG ulTimeout); -WORD hidReceiveDataInBuffer(BYTE*,WORD,BYTE); - -BYTE cdcSendDataWaitTilDone(BYTE* dataBuf, WORD size, BYTE intfNum, ULONG ulTimeout); -BYTE cdcSendDataInBackground(BYTE* dataBuf, WORD size, BYTE intfNum, ULONG ulTimeout); -WORD cdcReceiveDataInBuffer(BYTE*,WORD,BYTE); diff --git a/usb/usbEventHandling.c b/usb/usbEventHandling.c deleted file mode 100644 index 07b4df4..0000000 --- a/usb/usbEventHandling.c +++ /dev/null @@ -1,242 +0,0 @@ -// (c)2009 by Texas Instruments Incorporated, All Rights Reserved. -/*----------------------------------------------------------------------------+ -| | -| Texas Instruments | -| | -| MSP430 USB-Example (CDC/HID Driver) | -| | -+-----------------------------------------------------------------------------+ -| Source: usbEventHandling.c, File Version 1.00 2009/12/03 | -| Author: RSTO | -| | -| Description: | -| Event-handling placeholder functions. | -| All functios are called in interrupt context. | -| | -+----------------------------------------------------------------------------*/ - -#include "USB_API/USB_Common/device.h" -#include "USB_API/USB_Common/types.h" -#include "USB_API/USB_Common/defMSP430USB.h" -#include "USB_config/descriptors.h" -#include "USB_API/USB_Common/usb.h" -#include "F5xx_F6xx_Core_Lib/HAL_UCS.h" - -#ifdef _CDC_ -#include "USB_API/USB_CDC_API/UsbCdc.h" -#endif - -#ifdef _HID_ -#include "USB_API/USB_HID_API/UsbHid.h" -#endif - -#ifdef _MSC_ -#include "USB_API/USB_MSC_API/UsbMsc.h" -#endif - -#include "main.h" - -// These variables are only example, they are not needed for stack - -#if CDC_NUM_INTERFACES == 1 -volatile BYTE bDataReceived_event[CDC_NUM_INTERFACES] = {FALSE}; -#endif -#if CDC_NUM_INTERFACES == 2 -volatile BYTE bDataReceived_event[CDC_NUM_INTERFACES] = {FALSE, FALSE}; -#endif -#if CDC_NUM_INTERFACES == 3 -volatile BYTE bDataReceived_event[CDC_NUM_INTERFACES] = {FALSE, FALSE, FALSE}; -#endif -//volatile BYTE bDataReceived_event0 = FALSE; -//volatile BYTE bDataReceived_event1 = FALSE; -//volatile BYTE bDataReceived_event2 = FALSE; - -/* -If this function gets executed, it's a sign that the output of the USB PLL has failed. -returns TRUE to keep CPU awake -*/ -BYTE USB_handleClockEvent() -{ - //TO DO: You can place your code here - - return TRUE; //return TRUE to wake the main loop (in the case the CPU slept before interrupt) -} - -/* -If this function gets executed, it indicates that a valid voltage has just been applied to the VBUS pin. -returns TRUE to keep CPU awake -*/ -BYTE USB_handleVbusOnEvent() -{ - //TO DO: You can place your code here - - //We switch on USB and connect to the BUS - if (USB_enable() == kUSB_succeed) - { - USB_reset(); - USB_connect(); // generate rising edge on DP -> the host enumerates our device as full speed device - } - return TRUE; //return TRUE to wake the main loop (in the case the CPU slept before interrupt) -} - -/* -If this function gets executed, it indicates that a valid voltage has just been removed from the VBUS pin. -returns TRUE to keep CPU awake -*/ -BYTE USB_handleVbusOffEvent() -{ - //TO DO: You can place your code here - - XT2_Stop(); - - return TRUE; //return TRUE to wake the main loop (in the case the CPU slept before interrupt) -} - -/* -If this function gets executed, it indicates that the USB host has issued a USB reset event to the device. -returns TRUE to keep CPU awake -*/ -BYTE USB_handleResetEvent() -{ - //TO DO: You can place your code here - - return TRUE; //return TRUE to wake the main loop (in the case the CPU slept before interrupt) -} - -/* -If this function gets executed, it indicates that the USB host has chosen to suspend this device after a period of active operation. -returns TRUE to keep CPU awake -*/ -BYTE USB_handleSuspendEvent() -{ - //TO DO: You can place your code here - - return TRUE; //return TRUE to wake the main loop (in the case the CPU slept before interrupt) -} - -/* -If this function gets executed, it indicates that the USB host has chosen to resume this device after a period of suspended operation. -returns TRUE to keep CPU awake -*/ -BYTE USB_handleResumeEvent() -{ - //TO DO: You can place your code here - - return TRUE; //return TRUE to wake the main loop (in the case the CPU slept before interrupt) -} - -/* -If this function gets executed, it indicates that the USB host has enumerated this device : -after host assigned the address to the device. -returns TRUE to keep CPU awake -*/ -BYTE USB_handleEnumCompleteEvent() -{ - //TO DO: You can place your code here - - return TRUE; //return TRUE to wake the main loop (in the case the CPU slept before interrupt) -} - - -#ifdef _CDC_ - -/* -This event indicates that data has been received for interface intfNum, but no data receive operation is underway. -returns TRUE to keep CPU awake -*/ -BYTE USBCDC_handleDataReceived(BYTE intfNum) -{ - - if(!USBCDC_bytesInUSBBuffer(intfNum)) - return TRUE; - - if(!bDataReceived_event[intfNum]) - { - bDataReceived_event[intfNum] = TRUE; - - //TO DO: You can place your code here - } - - // data received event - - return TRUE; //return FALSE to go asleep after interrupt (in the case the CPU slept before interrupt) -} - -/* -This event indicates that a send operation on interface intfNum has just been completed. -returns TRUE to keep CPU awake -*/ -BYTE USBCDC_handleSendCompleted(BYTE intfNum) -{ - extern volatile BYTE bDataSendCompleted_event[]; // data send completed event - //TO DO: You can place your code here - - bDataSendCompleted_event[intfNum] = TRUE; - - return FALSE; //return FALSE to go asleep after interrupt (in the case the CPU slept before interrupt) -} - -/* -This event indicates that a receive operation on interface intfNum has just been completed. -*/ -BYTE USBCDC_handleReceiveCompleted(BYTE intfNum) -{ - //TO DO: You can place your code here - extern volatile BYTE bDataReceiveCompleted_event[]; - - bDataReceiveCompleted_event[intfNum] = TRUE; - - return FALSE; //return FALSE to go asleep after interrupt (in the case the CPU slept before interrupt) -} - -#endif // _CDC_ - -#ifdef _HID_ -/* -This event indicates that data has been received for interface intfNum, but no data receive operation is underway. -returns TRUE to keep CPU awake -*/ -BYTE USBHID_handleDataReceived(BYTE intfNum) -{ - //TO DO: You can place your code here - - return FALSE; //return FALSE to go asleep after interrupt (in the case the CPU slept before interrupt) -} - -/* -This event indicates that a send operation on interface intfNum has just been completed. -returns TRUE to keep CPU awake -*/ -BYTE USBHID_handleSendCompleted(BYTE intfNum) -{ - //TO DO: You can place your code here - - return FALSE; //return FALSE to go asleep after interrupt (in the case the CPU slept before interrupt) -} - -/* -This event indicates that a receive operation on interface intfNum has just been completed. -*/ -BYTE USBHID_handleReceiveCompleted(BYTE intfNum) -{ - //TO DO: You can place your code here - - return FALSE; //return FALSE to go asleep after interrupt (in the case the CPU slept before interrupt) -} - -#endif // _HID_ - -#ifdef _MSC_ -BYTE USBMSC_handleBufferEvent(VOID) -{ - - return FALSE; //return FALSE to go asleep after interrupt (in the case the CPU slept before interrupt) - -} -#endif // _MSC_ - - -/*----------------------------------------------------------------------------+ -| End of source file | -+----------------------------------------------------------------------------*/ -/*------------------------ Nothing Below This Line --------------------------*/