1 //===-- LiveIntervalAnalysis.h - Live Interval Analysis ---------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the LiveInterval analysis pass. Given some numbering of
11 // each the machine instructions (in this implemention depth-first order) an
12 // interval [i, j) is said to be a live interval for register v if there is no
13 // instruction with number j' > j such that v is live at j' and there is no
14 // instruction with number i' < i such that v is live at i'. In this
15 // implementation intervals can have holes, i.e. an interval might look like
16 // [1,20), [50,65), [1000,1001).
17 //
18 //===----------------------------------------------------------------------===//
20 #ifndef LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
21 #define LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
23 #include "llvm/CodeGen/MachineBasicBlock.h"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/LiveInterval.h"
26 #include "llvm/CodeGen/SlotIndexes.h"
27 #include "llvm/ADT/BitVector.h"
28 #include "llvm/ADT/DenseMap.h"
29 #include "llvm/ADT/SmallPtrSet.h"
30 #include "llvm/ADT/SmallVector.h"
31 #include "llvm/Support/Allocator.h"
32 #include <cmath>
33 #include <iterator>
35 namespace llvm {
37 class AliasAnalysis;
38 class LiveVariables;
39 class MachineLoopInfo;
40 class TargetRegisterInfo;
41 class MachineRegisterInfo;
42 class TargetInstrInfo;
43 class TargetRegisterClass;
44 class VirtRegMap;
46 class LiveIntervals : public MachineFunctionPass {
47 MachineFunction* mf_;
48 MachineRegisterInfo* mri_;
49 const TargetMachine* tm_;
50 const TargetRegisterInfo* tri_;
51 const TargetInstrInfo* tii_;
52 AliasAnalysis *aa_;
53 LiveVariables* lv_;
54 SlotIndexes* indexes_;
56 /// Special pool allocator for VNInfo's (LiveInterval val#).
57 ///
58 VNInfo::Allocator VNInfoAllocator;
60 typedef DenseMap<unsigned, LiveInterval*> Reg2IntervalMap;
61 Reg2IntervalMap r2iMap_;
63 /// allocatableRegs_ - A bit vector of allocatable registers.
64 BitVector allocatableRegs_;
66 /// CloneMIs - A list of clones as result of re-materialization.
67 std::vector<MachineInstr*> CloneMIs;
69 public:
70 static char ID; // Pass identification, replacement for typeid
71 LiveIntervals() : MachineFunctionPass(ID) {
72 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
73 }
75 // Calculate the spill weight to assign to a single instruction.
76 static float getSpillWeight(bool isDef, bool isUse, unsigned loopDepth);
78 // After summing the spill weights of all defs and uses, the final weight
79 // should be normalized, dividing the weight of the interval by its size.
80 // This encourages spilling of intervals that are large and have few uses,
81 // and discourages spilling of small intervals with many uses.
82 void normalizeSpillWeight(LiveInterval &li) {
83 li.weight /= getApproximateInstructionCount(li) + 25;
84 }
86 typedef Reg2IntervalMap::iterator iterator;
87 typedef Reg2IntervalMap::const_iterator const_iterator;
88 const_iterator begin() const { return r2iMap_.begin(); }
89 const_iterator end() const { return r2iMap_.end(); }
90 iterator begin() { return r2iMap_.begin(); }
91 iterator end() { return r2iMap_.end(); }
92 unsigned getNumIntervals() const { return (unsigned)r2iMap_.size(); }
94 LiveInterval &getInterval(unsigned reg) {
95 Reg2IntervalMap::iterator I = r2iMap_.find(reg);
96 assert(I != r2iMap_.end() && "Interval does not exist for register");
97 return *I->second;
98 }
100 const LiveInterval &getInterval(unsigned reg) const {
101 Reg2IntervalMap::const_iterator I = r2iMap_.find(reg);
102 assert(I != r2iMap_.end() && "Interval does not exist for register");
103 return *I->second;
104 }
106 bool hasInterval(unsigned reg) const {
107 return r2iMap_.count(reg);
108 }
110 /// isAllocatable - is the physical register reg allocatable in the current
111 /// function?
112 bool isAllocatable(unsigned reg) const {
113 return allocatableRegs_.test(reg);
114 }
116 /// getScaledIntervalSize - get the size of an interval in "units,"
117 /// where every function is composed of one thousand units. This
118 /// measure scales properly with empty index slots in the function.
119 double getScaledIntervalSize(LiveInterval& I) {
120 return (1000.0 * I.getSize()) / indexes_->getIndexesLength();
121 }
123 /// getFuncInstructionCount - Return the number of instructions in the
124 /// current function.
125 unsigned getFuncInstructionCount() {
126 return indexes_->getFunctionSize();
127 }
129 /// getApproximateInstructionCount - computes an estimate of the number
130 /// of instructions in a given LiveInterval.
131 unsigned getApproximateInstructionCount(LiveInterval& I) {
132 double IntervalPercentage = getScaledIntervalSize(I) / 1000.0;
133 return (unsigned)(IntervalPercentage * indexes_->getFunctionSize());
134 }
136 /// conflictsWithPhysReg - Returns true if the specified register is used or
137 /// defined during the duration of the specified interval. Copies to and
138 /// from li.reg are allowed. This method is only able to analyze simple
139 /// ranges that stay within a single basic block. Anything else is
140 /// considered a conflict.
141 bool conflictsWithPhysReg(const LiveInterval &li, VirtRegMap &vrm,
142 unsigned reg);
144 /// conflictsWithAliasRef - Similar to conflictsWithPhysRegRef except
145 /// it checks for alias uses and defs.
146 bool conflictsWithAliasRef(LiveInterval &li, unsigned Reg,
147 SmallPtrSet<MachineInstr*,32> &JoinedCopies);
149 // Interval creation
150 LiveInterval &getOrCreateInterval(unsigned reg) {
151 Reg2IntervalMap::iterator I = r2iMap_.find(reg);
152 if (I == r2iMap_.end())
153 I = r2iMap_.insert(std::make_pair(reg, createInterval(reg))).first;
154 return *I->second;
155 }
157 /// dupInterval - Duplicate a live interval. The caller is responsible for
158 /// managing the allocated memory.
159 LiveInterval *dupInterval(LiveInterval *li);
161 /// addLiveRangeToEndOfBlock - Given a register and an instruction,
162 /// adds a live range from that instruction to the end of its MBB.
163 LiveRange addLiveRangeToEndOfBlock(unsigned reg,
164 MachineInstr* startInst);
166 /// shrinkToUses - After removing some uses of a register, shrink its live
167 /// range to just the remaining uses. This method does not compute reaching
168 /// defs for new uses, and it doesn't remove dead defs.
169 /// Dead PHIDef values are marked as unused.
170 void shrinkToUses(LiveInterval *li);
172 // Interval removal
174 void removeInterval(unsigned Reg) {
175 DenseMap<unsigned, LiveInterval*>::iterator I = r2iMap_.find(Reg);
176 delete I->second;
177 r2iMap_.erase(I);
178 }
180 SlotIndexes *getSlotIndexes() const {
181 return indexes_;
182 }
184 SlotIndex getZeroIndex() const {
185 return indexes_->getZeroIndex();
186 }
188 SlotIndex getInvalidIndex() const {
189 return indexes_->getInvalidIndex();
190 }
192 /// isNotInMIMap - returns true if the specified machine instr has been
193 /// removed or was never entered in the map.
194 bool isNotInMIMap(const MachineInstr* Instr) const {
195 return !indexes_->hasIndex(Instr);
196 }
198 /// Returns the base index of the given instruction.
199 SlotIndex getInstructionIndex(const MachineInstr *instr) const {
200 return indexes_->getInstructionIndex(instr);
201 }
203 /// Returns the instruction associated with the given index.
204 MachineInstr* getInstructionFromIndex(SlotIndex index) const {
205 return indexes_->getInstructionFromIndex(index);
206 }
208 /// Return the first index in the given basic block.
209 SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const {
210 return indexes_->getMBBStartIdx(mbb);
211 }
213 /// Return the last index in the given basic block.
214 SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const {
215 return indexes_->getMBBEndIdx(mbb);
216 }
218 bool isLiveInToMBB(const LiveInterval &li,
219 const MachineBasicBlock *mbb) const {
220 return li.liveAt(getMBBStartIdx(mbb));
221 }
223 LiveRange* findEnteringRange(LiveInterval &li,
224 const MachineBasicBlock *mbb) {
225 return li.getLiveRangeContaining(getMBBStartIdx(mbb));
226 }
228 bool isLiveOutOfMBB(const LiveInterval &li,
229 const MachineBasicBlock *mbb) const {
230 return li.liveAt(getMBBEndIdx(mbb).getPrevSlot());
231 }
233 LiveRange* findExitingRange(LiveInterval &li,
234 const MachineBasicBlock *mbb) {
235 return li.getLiveRangeContaining(getMBBEndIdx(mbb).getPrevSlot());
236 }
238 MachineBasicBlock* getMBBFromIndex(SlotIndex index) const {
239 return indexes_->getMBBFromIndex(index);
240 }
242 SlotIndex InsertMachineInstrInMaps(MachineInstr *MI) {
243 return indexes_->insertMachineInstrInMaps(MI);
244 }
246 void RemoveMachineInstrFromMaps(MachineInstr *MI) {
247 indexes_->removeMachineInstrFromMaps(MI);
248 }
250 void ReplaceMachineInstrInMaps(MachineInstr *MI, MachineInstr *NewMI) {
251 indexes_->replaceMachineInstrInMaps(MI, NewMI);
252 }
254 void InsertMBBInMaps(MachineBasicBlock *MBB) {
255 indexes_->insertMBBInMaps(MBB);
256 }
258 bool findLiveInMBBs(SlotIndex Start, SlotIndex End,
259 SmallVectorImpl<MachineBasicBlock*> &MBBs) const {
260 return indexes_->findLiveInMBBs(Start, End, MBBs);
261 }
263 void renumber() {
264 indexes_->renumberIndexes();
265 }
267 VNInfo::Allocator& getVNInfoAllocator() { return VNInfoAllocator; }
269 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
270 virtual void releaseMemory();
272 /// runOnMachineFunction - pass entry point
273 virtual bool runOnMachineFunction(MachineFunction&);
275 /// print - Implement the dump method.
276 virtual void print(raw_ostream &O, const Module* = 0) const;
278 /// addIntervalsForSpills - Create new intervals for spilled defs / uses of
279 /// the given interval. FIXME: It also returns the weight of the spill slot
280 /// (if any is created) by reference. This is temporary.
281 std::vector<LiveInterval*>
282 addIntervalsForSpills(const LiveInterval& i,
283 const SmallVectorImpl<LiveInterval*> &SpillIs,
284 const MachineLoopInfo *loopInfo, VirtRegMap& vrm);
286 /// spillPhysRegAroundRegDefsUses - Spill the specified physical register
287 /// around all defs and uses of the specified interval. Return true if it
288 /// was able to cut its interval.
289 bool spillPhysRegAroundRegDefsUses(const LiveInterval &li,
290 unsigned PhysReg, VirtRegMap &vrm);
292 /// isReMaterializable - Returns true if every definition of MI of every
293 /// val# of the specified interval is re-materializable. Also returns true
294 /// by reference if all of the defs are load instructions.
295 bool isReMaterializable(const LiveInterval &li,
296 const SmallVectorImpl<LiveInterval*> &SpillIs,
297 bool &isLoad);
299 /// isReMaterializable - Returns true if the definition MI of the specified
300 /// val# of the specified interval is re-materializable.
301 bool isReMaterializable(const LiveInterval &li, const VNInfo *ValNo,
302 MachineInstr *MI);
304 /// getRepresentativeReg - Find the largest super register of the specified
305 /// physical register.
306 unsigned getRepresentativeReg(unsigned Reg) const;
308 /// getNumConflictsWithPhysReg - Return the number of uses and defs of the
309 /// specified interval that conflicts with the specified physical register.
310 unsigned getNumConflictsWithPhysReg(const LiveInterval &li,
311 unsigned PhysReg) const;
313 /// intervalIsInOneMBB - Returns true if the specified interval is entirely
314 /// within a single basic block.
315 bool intervalIsInOneMBB(const LiveInterval &li) const;
317 /// getLastSplitPoint - Return the last possible insertion point in mbb for
318 /// spilling and splitting code. This is the first terminator, or the call
319 /// instruction if li is live into a landing pad successor.
320 MachineBasicBlock::iterator getLastSplitPoint(const LiveInterval &li,
321 MachineBasicBlock *mbb);
323 /// addKillFlags - Add kill flags to any instruction that kills a virtual
324 /// register.
325 void addKillFlags();
327 private:
328 /// computeIntervals - Compute live intervals.
329 void computeIntervals();
331 /// handleRegisterDef - update intervals for a register def
332 /// (calls handlePhysicalRegisterDef and
333 /// handleVirtualRegisterDef)
334 void handleRegisterDef(MachineBasicBlock *MBB,
335 MachineBasicBlock::iterator MI,
336 SlotIndex MIIdx,
337 MachineOperand& MO, unsigned MOIdx);
339 /// isPartialRedef - Return true if the specified def at the specific index
340 /// is partially re-defining the specified live interval. A common case of
341 /// this is a definition of the sub-register.
342 bool isPartialRedef(SlotIndex MIIdx, MachineOperand &MO,
343 LiveInterval &interval);
345 /// handleVirtualRegisterDef - update intervals for a virtual
346 /// register def
347 void handleVirtualRegisterDef(MachineBasicBlock *MBB,
348 MachineBasicBlock::iterator MI,
349 SlotIndex MIIdx, MachineOperand& MO,
350 unsigned MOIdx,
351 LiveInterval& interval);
353 /// handlePhysicalRegisterDef - update intervals for a physical register
354 /// def.
355 void handlePhysicalRegisterDef(MachineBasicBlock* mbb,
356 MachineBasicBlock::iterator mi,
357 SlotIndex MIIdx, MachineOperand& MO,
358 LiveInterval &interval,
359 MachineInstr *CopyMI);
361 /// handleLiveInRegister - Create interval for a livein register.
362 void handleLiveInRegister(MachineBasicBlock* mbb,
363 SlotIndex MIIdx,
364 LiveInterval &interval, bool isAlias = false);
366 /// getReMatImplicitUse - If the remat definition MI has one (for now, we
367 /// only allow one) virtual register operand, then its uses are implicitly
368 /// using the register. Returns the virtual register.
369 unsigned getReMatImplicitUse(const LiveInterval &li,
370 MachineInstr *MI) const;
372 /// isValNoAvailableAt - Return true if the val# of the specified interval
373 /// which reaches the given instruction also reaches the specified use
374 /// index.
375 bool isValNoAvailableAt(const LiveInterval &li, MachineInstr *MI,
376 SlotIndex UseIdx) const;
378 /// isReMaterializable - Returns true if the definition MI of the specified
379 /// val# of the specified interval is re-materializable. Also returns true
380 /// by reference if the def is a load.
381 bool isReMaterializable(const LiveInterval &li, const VNInfo *ValNo,
382 MachineInstr *MI,
383 const SmallVectorImpl<LiveInterval*> &SpillIs,
384 bool &isLoad);
386 /// tryFoldMemoryOperand - Attempts to fold either a spill / restore from
387 /// slot / to reg or any rematerialized load into ith operand of specified
388 /// MI. If it is successul, MI is updated with the newly created MI and
389 /// returns true.
390 bool tryFoldMemoryOperand(MachineInstr* &MI, VirtRegMap &vrm,
391 MachineInstr *DefMI, SlotIndex InstrIdx,
392 SmallVector<unsigned, 2> &Ops,
393 bool isSS, int FrameIndex, unsigned Reg);
395 /// canFoldMemoryOperand - Return true if the specified load / store
396 /// folding is possible.
397 bool canFoldMemoryOperand(MachineInstr *MI,
398 SmallVector<unsigned, 2> &Ops,
399 bool ReMatLoadSS) const;
401 /// anyKillInMBBAfterIdx - Returns true if there is a kill of the specified
402 /// VNInfo that's after the specified index but is within the basic block.
403 bool anyKillInMBBAfterIdx(const LiveInterval &li, const VNInfo *VNI,
404 MachineBasicBlock *MBB,
405 SlotIndex Idx) const;
407 /// hasAllocatableSuperReg - Return true if the specified physical register
408 /// has any super register that's allocatable.
409 bool hasAllocatableSuperReg(unsigned Reg) const;
411 /// SRInfo - Spill / restore info.
412 struct SRInfo {
413 SlotIndex index;
414 unsigned vreg;
415 bool canFold;
416 SRInfo(SlotIndex i, unsigned vr, bool f)
417 : index(i), vreg(vr), canFold(f) {}
418 };
420 bool alsoFoldARestore(int Id, SlotIndex index, unsigned vr,
421 BitVector &RestoreMBBs,
422 DenseMap<unsigned,std::vector<SRInfo> >&RestoreIdxes);
423 void eraseRestoreInfo(int Id, SlotIndex index, unsigned vr,
424 BitVector &RestoreMBBs,
425 DenseMap<unsigned,std::vector<SRInfo> >&RestoreIdxes);
427 /// handleSpilledImpDefs - Remove IMPLICIT_DEF instructions which are being
428 /// spilled and create empty intervals for their uses.
429 void handleSpilledImpDefs(const LiveInterval &li, VirtRegMap &vrm,
430 const TargetRegisterClass* rc,
431 std::vector<LiveInterval*> &NewLIs);
433 /// rewriteImplicitOps - Rewrite implicit use operands of MI (i.e. uses of
434 /// interval on to-be re-materialized operands of MI) with new register.
435 void rewriteImplicitOps(const LiveInterval &li,
436 MachineInstr *MI, unsigned NewVReg, VirtRegMap &vrm);
438 /// rewriteInstructionForSpills, rewriteInstructionsForSpills - Helper
439 /// functions for addIntervalsForSpills to rewrite uses / defs for the given
440 /// live range.
441 bool rewriteInstructionForSpills(const LiveInterval &li, const VNInfo *VNI,
442 bool TrySplit, SlotIndex index, SlotIndex end,
443 MachineInstr *MI, MachineInstr *OrigDefMI, MachineInstr *DefMI,
444 unsigned Slot, int LdSlot,
445 bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
446 VirtRegMap &vrm, const TargetRegisterClass* rc,
447 SmallVector<int, 4> &ReMatIds, const MachineLoopInfo *loopInfo,
448 unsigned &NewVReg, unsigned ImpUse, bool &HasDef, bool &HasUse,
449 DenseMap<unsigned,unsigned> &MBBVRegsMap,
450 std::vector<LiveInterval*> &NewLIs);
451 void rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit,
452 LiveInterval::Ranges::const_iterator &I,
453 MachineInstr *OrigDefMI, MachineInstr *DefMI, unsigned Slot, int LdSlot,
454 bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
455 VirtRegMap &vrm, const TargetRegisterClass* rc,
456 SmallVector<int, 4> &ReMatIds, const MachineLoopInfo *loopInfo,
457 BitVector &SpillMBBs,
458 DenseMap<unsigned,std::vector<SRInfo> > &SpillIdxes,
459 BitVector &RestoreMBBs,
460 DenseMap<unsigned,std::vector<SRInfo> > &RestoreIdxes,
461 DenseMap<unsigned,unsigned> &MBBVRegsMap,
462 std::vector<LiveInterval*> &NewLIs);
464 // Normalize the spill weight of all the intervals in NewLIs.
465 void normalizeSpillWeights(std::vector<LiveInterval*> &NewLIs);
467 static LiveInterval* createInterval(unsigned Reg);
469 void printInstrs(raw_ostream &O) const;
470 void dumpInstrs() const;
471 };
472 } // End llvm namespace
474 #endif