1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
12 // the back end.
13 //
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/ADT/DenseMapInfo.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/ADT/ilist.h"
24 #include "llvm/ADT/ilist_node.h"
25 #include "llvm/ADT/iterator_range.h"
26 #include "llvm/CodeGen/MachineOperand.h"
27 #include "llvm/IR/DebugInfo.h"
28 #include "llvm/IR/DebugLoc.h"
29 #include "llvm/IR/InlineAsm.h"
30 #include "llvm/MC/MCInstrDesc.h"
31 #include "llvm/Support/ArrayRecycler.h"
32 #include "llvm/Target/TargetOpcodes.h"
34 namespace llvm {
36 template <typename T> class SmallVectorImpl;
37 class AliasAnalysis;
38 class TargetInstrInfo;
39 class TargetRegisterClass;
40 class TargetRegisterInfo;
41 class MachineFunction;
42 class MachineMemOperand;
44 //===----------------------------------------------------------------------===//
45 /// MachineInstr - Representation of each machine instruction.
46 ///
47 /// This class isn't a POD type, but it must have a trivial destructor. When a
48 /// MachineFunction is deleted, all the contained MachineInstrs are deallocated
49 /// without having their destructor called.
50 ///
51 class MachineInstr : public ilist_node<MachineInstr> {
52 public:
53 typedef MachineMemOperand **mmo_iterator;
55 /// Flags to specify different kinds of comments to output in
56 /// assembly code. These flags carry semantic information not
57 /// otherwise easily derivable from the IR text.
58 ///
59 enum CommentFlag {
60 ReloadReuse = 0x1
61 };
63 enum MIFlag {
64 NoFlags = 0,
65 FrameSetup = 1 << 0, // Instruction is used as a part of
66 // function frame setup code.
67 BundledPred = 1 << 1, // Instruction has bundled predecessors.
68 BundledSucc = 1 << 2 // Instruction has bundled successors.
69 };
70 private:
71 const MCInstrDesc *MCID; // Instruction descriptor.
72 MachineBasicBlock *Parent; // Pointer to the owning basic block.
74 // Operands are allocated by an ArrayRecycler.
75 MachineOperand *Operands; // Pointer to the first operand.
76 unsigned NumOperands; // Number of operands on instruction.
77 typedef ArrayRecycler<MachineOperand>::Capacity OperandCapacity;
78 OperandCapacity CapOperands; // Capacity of the Operands array.
80 uint8_t Flags; // Various bits of additional
81 // information about machine
82 // instruction.
84 uint8_t AsmPrinterFlags; // Various bits of information used by
85 // the AsmPrinter to emit helpful
86 // comments. This is *not* semantic
87 // information. Do not use this for
88 // anything other than to convey comment
89 // information to AsmPrinter.
91 uint8_t NumMemRefs; // Information on memory references.
92 mmo_iterator MemRefs;
94 DebugLoc debugLoc; // Source line information.
96 MachineInstr(const MachineInstr&) LLVM_DELETED_FUNCTION;
97 void operator=(const MachineInstr&) LLVM_DELETED_FUNCTION;
98 // Use MachineFunction::DeleteMachineInstr() instead.
99 ~MachineInstr() LLVM_DELETED_FUNCTION;
101 // Intrusive list support
102 friend struct ilist_traits<MachineInstr>;
103 friend struct ilist_traits<MachineBasicBlock>;
104 void setParent(MachineBasicBlock *P) { Parent = P; }
106 /// MachineInstr ctor - This constructor creates a copy of the given
107 /// MachineInstr in the given MachineFunction.
108 MachineInstr(MachineFunction &, const MachineInstr &);
110 /// MachineInstr ctor - This constructor create a MachineInstr and add the
111 /// implicit operands. It reserves space for number of operands specified by
112 /// MCInstrDesc. An explicit DebugLoc is supplied.
113 MachineInstr(MachineFunction&, const MCInstrDesc &MCID,
114 const DebugLoc dl, bool NoImp = false);
116 // MachineInstrs are pool-allocated and owned by MachineFunction.
117 friend class MachineFunction;
119 public:
120 const MachineBasicBlock* getParent() const { return Parent; }
121 MachineBasicBlock* getParent() { return Parent; }
123 /// getAsmPrinterFlags - Return the asm printer flags bitvector.
124 ///
125 uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
127 /// clearAsmPrinterFlags - clear the AsmPrinter bitvector
128 ///
129 void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
131 /// getAsmPrinterFlag - Return whether an AsmPrinter flag is set.
132 ///
133 bool getAsmPrinterFlag(CommentFlag Flag) const {
134 return AsmPrinterFlags & Flag;
135 }
137 /// setAsmPrinterFlag - Set a flag for the AsmPrinter.
138 ///
139 void setAsmPrinterFlag(CommentFlag Flag) {
140 AsmPrinterFlags |= (uint8_t)Flag;
141 }
143 /// clearAsmPrinterFlag - clear specific AsmPrinter flags
144 ///
145 void clearAsmPrinterFlag(CommentFlag Flag) {
146 AsmPrinterFlags &= ~Flag;
147 }
149 /// getFlags - Return the MI flags bitvector.
150 uint8_t getFlags() const {
151 return Flags;
152 }
154 /// getFlag - Return whether an MI flag is set.
155 bool getFlag(MIFlag Flag) const {
156 return Flags & Flag;
157 }
159 /// setFlag - Set a MI flag.
160 void setFlag(MIFlag Flag) {
161 Flags |= (uint8_t)Flag;
162 }
164 void setFlags(unsigned flags) {
165 // Filter out the automatically maintained flags.
166 unsigned Mask = BundledPred | BundledSucc;
167 Flags = (Flags & Mask) | (flags & ~Mask);
168 }
170 /// clearFlag - Clear a MI flag.
171 void clearFlag(MIFlag Flag) {
172 Flags &= ~((uint8_t)Flag);
173 }
175 /// isInsideBundle - Return true if MI is in a bundle (but not the first MI
176 /// in a bundle).
177 ///
178 /// A bundle looks like this before it's finalized:
179 /// ----------------
180 /// | MI |
181 /// ----------------
182 /// |
183 /// ----------------
184 /// | MI * |
185 /// ----------------
186 /// |
187 /// ----------------
188 /// | MI * |
189 /// ----------------
190 /// In this case, the first MI starts a bundle but is not inside a bundle, the
191 /// next 2 MIs are considered "inside" the bundle.
192 ///
193 /// After a bundle is finalized, it looks like this:
194 /// ----------------
195 /// | Bundle |
196 /// ----------------
197 /// |
198 /// ----------------
199 /// | MI * |
200 /// ----------------
201 /// |
202 /// ----------------
203 /// | MI * |
204 /// ----------------
205 /// |
206 /// ----------------
207 /// | MI * |
208 /// ----------------
209 /// The first instruction has the special opcode "BUNDLE". It's not "inside"
210 /// a bundle, but the next three MIs are.
211 bool isInsideBundle() const {
212 return getFlag(BundledPred);
213 }
215 /// isBundled - Return true if this instruction part of a bundle. This is true
216 /// if either itself or its following instruction is marked "InsideBundle".
217 bool isBundled() const {
218 return isBundledWithPred() || isBundledWithSucc();
219 }
221 /// Return true if this instruction is part of a bundle, and it is not the
222 /// first instruction in the bundle.
223 bool isBundledWithPred() const { return getFlag(BundledPred); }
225 /// Return true if this instruction is part of a bundle, and it is not the
226 /// last instruction in the bundle.
227 bool isBundledWithSucc() const { return getFlag(BundledSucc); }
229 /// Bundle this instruction with its predecessor. This can be an unbundled
230 /// instruction, or it can be the first instruction in a bundle.
231 void bundleWithPred();
233 /// Bundle this instruction with its successor. This can be an unbundled
234 /// instruction, or it can be the last instruction in a bundle.
235 void bundleWithSucc();
237 /// Break bundle above this instruction.
238 void unbundleFromPred();
240 /// Break bundle below this instruction.
241 void unbundleFromSucc();
243 /// getDebugLoc - Returns the debug location id of this MachineInstr.
244 ///
245 DebugLoc getDebugLoc() const { return debugLoc; }
247 /// getDebugVariable() - Return the debug variable referenced by
248 /// this DBG_VALUE instruction.
249 DIVariable getDebugVariable() const {
250 assert(isDebugValue() && "not a DBG_VALUE");
251 const MDNode *Var = getOperand(getNumOperands() - 1).getMetadata();
252 return DIVariable(Var);
253 }
255 /// emitError - Emit an error referring to the source location of this
256 /// instruction. This should only be used for inline assembly that is somehow
257 /// impossible to compile. Other errors should have been handled much
258 /// earlier.
259 ///
260 /// If this method returns, the caller should try to recover from the error.
261 ///
262 void emitError(StringRef Msg) const;
264 /// getDesc - Returns the target instruction descriptor of this
265 /// MachineInstr.
266 const MCInstrDesc &getDesc() const { return *MCID; }
268 /// getOpcode - Returns the opcode of this MachineInstr.
269 ///
270 int getOpcode() const { return MCID->Opcode; }
272 /// Access to explicit operands of the instruction.
273 ///
274 unsigned getNumOperands() const { return NumOperands; }
276 const MachineOperand& getOperand(unsigned i) const {
277 assert(i < getNumOperands() && "getOperand() out of range!");
278 return Operands[i];
279 }
280 MachineOperand& getOperand(unsigned i) {
281 assert(i < getNumOperands() && "getOperand() out of range!");
282 return Operands[i];
283 }
285 /// getNumExplicitOperands - Returns the number of non-implicit operands.
286 ///
287 unsigned getNumExplicitOperands() const;
289 /// iterator/begin/end - Iterate over all operands of a machine instruction.
290 typedef MachineOperand *mop_iterator;
291 typedef const MachineOperand *const_mop_iterator;
293 mop_iterator operands_begin() { return Operands; }
294 mop_iterator operands_end() { return Operands + NumOperands; }
296 const_mop_iterator operands_begin() const { return Operands; }
297 const_mop_iterator operands_end() const { return Operands + NumOperands; }
299 iterator_range<mop_iterator> operands() {
300 return iterator_range<mop_iterator>(operands_begin(), operands_end());
301 }
302 iterator_range<const_mop_iterator> operands() const {
303 return iterator_range<const_mop_iterator>(operands_begin(), operands_end());
304 }
305 iterator_range<mop_iterator> explicit_operands() {
306 return iterator_range<mop_iterator>(
307 operands_begin(), operands_begin() + getNumExplicitOperands());
308 }
309 iterator_range<const_mop_iterator> explicit_operands() const {
310 return iterator_range<const_mop_iterator>(
311 operands_begin(), operands_begin() + getNumExplicitOperands());
312 }
313 iterator_range<mop_iterator> implicit_operands() {
314 return iterator_range<mop_iterator>(explicit_operands().end(),
315 operands_end());
316 }
317 iterator_range<const_mop_iterator> implicit_operands() const {
318 return iterator_range<const_mop_iterator>(explicit_operands().end(),
319 operands_end());
320 }
322 /// Access to memory operands of the instruction
323 mmo_iterator memoperands_begin() const { return MemRefs; }
324 mmo_iterator memoperands_end() const { return MemRefs + NumMemRefs; }
325 bool memoperands_empty() const { return NumMemRefs == 0; }
327 iterator_range<mmo_iterator> memoperands() {
328 return iterator_range<mmo_iterator>(memoperands_begin(), memoperands_end());
329 }
330 iterator_range<mmo_iterator> memoperands() const {
331 return iterator_range<mmo_iterator>(memoperands_begin(), memoperands_end());
332 }
334 /// hasOneMemOperand - Return true if this instruction has exactly one
335 /// MachineMemOperand.
336 bool hasOneMemOperand() const {
337 return NumMemRefs == 1;
338 }
340 /// API for querying MachineInstr properties. They are the same as MCInstrDesc
341 /// queries but they are bundle aware.
343 enum QueryType {
344 IgnoreBundle, // Ignore bundles
345 AnyInBundle, // Return true if any instruction in bundle has property
346 AllInBundle // Return true if all instructions in bundle have property
347 };
349 /// hasProperty - Return true if the instruction (or in the case of a bundle,
350 /// the instructions inside the bundle) has the specified property.
351 /// The first argument is the property being queried.
352 /// The second argument indicates whether the query should look inside
353 /// instruction bundles.
354 bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
355 // Inline the fast path for unbundled or bundle-internal instructions.
356 if (Type == IgnoreBundle || !isBundled() || isBundledWithPred())
357 return getDesc().getFlags() & (1 << MCFlag);
359 // If this is the first instruction in a bundle, take the slow path.
360 return hasPropertyInBundle(1 << MCFlag, Type);
361 }
363 /// isVariadic - Return true if this instruction can have a variable number of
364 /// operands. In this case, the variable operands will be after the normal
365 /// operands but before the implicit definitions and uses (if any are
366 /// present).
367 bool isVariadic(QueryType Type = IgnoreBundle) const {
368 return hasProperty(MCID::Variadic, Type);
369 }
371 /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
372 /// ARM instructions which can set condition code if 's' bit is set.
373 bool hasOptionalDef(QueryType Type = IgnoreBundle) const {
374 return hasProperty(MCID::HasOptionalDef, Type);
375 }
377 /// isPseudo - Return true if this is a pseudo instruction that doesn't
378 /// correspond to a real machine instruction.
379 ///
380 bool isPseudo(QueryType Type = IgnoreBundle) const {
381 return hasProperty(MCID::Pseudo, Type);
382 }
384 bool isReturn(QueryType Type = AnyInBundle) const {
385 return hasProperty(MCID::Return, Type);
386 }
388 bool isCall(QueryType Type = AnyInBundle) const {
389 return hasProperty(MCID::Call, Type);
390 }
392 /// isBarrier - Returns true if the specified instruction stops control flow
393 /// from executing the instruction immediately following it. Examples include
394 /// unconditional branches and return instructions.
395 bool isBarrier(QueryType Type = AnyInBundle) const {
396 return hasProperty(MCID::Barrier, Type);
397 }
399 /// isTerminator - Returns true if this instruction part of the terminator for
400 /// a basic block. Typically this is things like return and branch
401 /// instructions.
402 ///
403 /// Various passes use this to insert code into the bottom of a basic block,
404 /// but before control flow occurs.
405 bool isTerminator(QueryType Type = AnyInBundle) const {
406 return hasProperty(MCID::Terminator, Type);
407 }
409 /// isBranch - Returns true if this is a conditional, unconditional, or
410 /// indirect branch. Predicates below can be used to discriminate between
411 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
412 /// get more information.
413 bool isBranch(QueryType Type = AnyInBundle) const {
414 return hasProperty(MCID::Branch, Type);
415 }
417 /// isIndirectBranch - Return true if this is an indirect branch, such as a
418 /// branch through a register.
419 bool isIndirectBranch(QueryType Type = AnyInBundle) const {
420 return hasProperty(MCID::IndirectBranch, Type);
421 }
423 /// isConditionalBranch - Return true if this is a branch which may fall
424 /// through to the next instruction or may transfer control flow to some other
425 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
426 /// information about this branch.
427 bool isConditionalBranch(QueryType Type = AnyInBundle) const {
428 return isBranch(Type) & !isBarrier(Type) & !isIndirectBranch(Type);
429 }
431 /// isUnconditionalBranch - Return true if this is a branch which always
432 /// transfers control flow to some other block. The
433 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
434 /// about this branch.
435 bool isUnconditionalBranch(QueryType Type = AnyInBundle) const {
436 return isBranch(Type) & isBarrier(Type) & !isIndirectBranch(Type);
437 }
439 /// Return true if this instruction has a predicate operand that
440 /// controls execution. It may be set to 'always', or may be set to other
441 /// values. There are various methods in TargetInstrInfo that can be used to
442 /// control and modify the predicate in this instruction.
443 bool isPredicable(QueryType Type = AllInBundle) const {
444 // If it's a bundle than all bundled instructions must be predicable for this
445 // to return true.
446 return hasProperty(MCID::Predicable, Type);
447 }
449 /// isCompare - Return true if this instruction is a comparison.
450 bool isCompare(QueryType Type = IgnoreBundle) const {
451 return hasProperty(MCID::Compare, Type);
452 }
454 /// isMoveImmediate - Return true if this instruction is a move immediate
455 /// (including conditional moves) instruction.
456 bool isMoveImmediate(QueryType Type = IgnoreBundle) const {
457 return hasProperty(MCID::MoveImm, Type);
458 }
460 /// isBitcast - Return true if this instruction is a bitcast instruction.
461 ///
462 bool isBitcast(QueryType Type = IgnoreBundle) const {
463 return hasProperty(MCID::Bitcast, Type);
464 }
466 /// isSelect - Return true if this instruction is a select instruction.
467 ///
468 bool isSelect(QueryType Type = IgnoreBundle) const {
469 return hasProperty(MCID::Select, Type);
470 }
472 /// isNotDuplicable - Return true if this instruction cannot be safely
473 /// duplicated. For example, if the instruction has a unique labels attached
474 /// to it, duplicating it would cause multiple definition errors.
475 bool isNotDuplicable(QueryType Type = AnyInBundle) const {
476 return hasProperty(MCID::NotDuplicable, Type);
477 }
479 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
480 /// which must be filled by the code generator.
481 bool hasDelaySlot(QueryType Type = AnyInBundle) const {
482 return hasProperty(MCID::DelaySlot, Type);
483 }
485 /// canFoldAsLoad - Return true for instructions that can be folded as
486 /// memory operands in other instructions. The most common use for this
487 /// is instructions that are simple loads from memory that don't modify
488 /// the loaded value in any way, but it can also be used for instructions
489 /// that can be expressed as constant-pool loads, such as V_SETALLONES
490 /// on x86, to allow them to be folded when it is beneficial.
491 /// This should only be set on instructions that return a value in their
492 /// only virtual register definition.
493 bool canFoldAsLoad(QueryType Type = IgnoreBundle) const {
494 return hasProperty(MCID::FoldableAsLoad, Type);
495 }
497 //===--------------------------------------------------------------------===//
498 // Side Effect Analysis
499 //===--------------------------------------------------------------------===//
501 /// mayLoad - Return true if this instruction could possibly read memory.
502 /// Instructions with this flag set are not necessarily simple load
503 /// instructions, they may load a value and modify it, for example.
504 bool mayLoad(QueryType Type = AnyInBundle) const {
505 if (isInlineAsm()) {
506 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
507 if (ExtraInfo & InlineAsm::Extra_MayLoad)
508 return true;
509 }
510 return hasProperty(MCID::MayLoad, Type);
511 }
514 /// mayStore - Return true if this instruction could possibly modify memory.
515 /// Instructions with this flag set are not necessarily simple store
516 /// instructions, they may store a modified value based on their operands, or
517 /// may not actually modify anything, for example.
518 bool mayStore(QueryType Type = AnyInBundle) const {
519 if (isInlineAsm()) {
520 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
521 if (ExtraInfo & InlineAsm::Extra_MayStore)
522 return true;
523 }
524 return hasProperty(MCID::MayStore, Type);
525 }
527 //===--------------------------------------------------------------------===//
528 // Flags that indicate whether an instruction can be modified by a method.
529 //===--------------------------------------------------------------------===//
531 /// isCommutable - Return true if this may be a 2- or 3-address
532 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
533 /// result if Y and Z are exchanged. If this flag is set, then the
534 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
535 /// instruction.
536 ///
537 /// Note that this flag may be set on instructions that are only commutable
538 /// sometimes. In these cases, the call to commuteInstruction will fail.
539 /// Also note that some instructions require non-trivial modification to
540 /// commute them.
541 bool isCommutable(QueryType Type = IgnoreBundle) const {
542 return hasProperty(MCID::Commutable, Type);
543 }
545 /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
546 /// which can be changed into a 3-address instruction if needed. Doing this
547 /// transformation can be profitable in the register allocator, because it
548 /// means that the instruction can use a 2-address form if possible, but
549 /// degrade into a less efficient form if the source and dest register cannot
550 /// be assigned to the same register. For example, this allows the x86
551 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
552 /// is the same speed as the shift but has bigger code size.
553 ///
554 /// If this returns true, then the target must implement the
555 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
556 /// is allowed to fail if the transformation isn't valid for this specific
557 /// instruction (e.g. shl reg, 4 on x86).
558 ///
559 bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const {
560 return hasProperty(MCID::ConvertibleTo3Addr, Type);
561 }
563 /// usesCustomInsertionHook - Return true if this instruction requires
564 /// custom insertion support when the DAG scheduler is inserting it into a
565 /// machine basic block. If this is true for the instruction, it basically
566 /// means that it is a pseudo instruction used at SelectionDAG time that is
567 /// expanded out into magic code by the target when MachineInstrs are formed.
568 ///
569 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
570 /// is used to insert this into the MachineBasicBlock.
571 bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const {
572 return hasProperty(MCID::UsesCustomInserter, Type);
573 }
575 /// hasPostISelHook - Return true if this instruction requires *adjustment*
576 /// after instruction selection by calling a target hook. For example, this
577 /// can be used to fill in ARM 's' optional operand depending on whether
578 /// the conditional flag register is used.
579 bool hasPostISelHook(QueryType Type = IgnoreBundle) const {
580 return hasProperty(MCID::HasPostISelHook, Type);
581 }
583 /// isRematerializable - Returns true if this instruction is a candidate for
584 /// remat. This flag is deprecated, please don't use it anymore. If this
585 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
586 /// verify the instruction is really rematable.
587 bool isRematerializable(QueryType Type = AllInBundle) const {
588 // It's only possible to re-mat a bundle if all bundled instructions are
589 // re-materializable.
590 return hasProperty(MCID::Rematerializable, Type);
591 }
593 /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or
594 /// less) than a move instruction. This is useful during certain types of
595 /// optimizations (e.g., remat during two-address conversion or machine licm)
596 /// where we would like to remat or hoist the instruction, but not if it costs
597 /// more than moving the instruction into the appropriate register. Note, we
598 /// are not marking copies from and to the same register class with this flag.
599 bool isAsCheapAsAMove(QueryType Type = AllInBundle) const {
600 // Only returns true for a bundle if all bundled instructions are cheap.
601 // FIXME: This probably requires a target hook.
602 return hasProperty(MCID::CheapAsAMove, Type);
603 }
605 /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands
606 /// have special register allocation requirements that are not captured by the
607 /// operand register classes. e.g. ARM::STRD's two source registers must be an
608 /// even / odd pair, ARM::STM registers have to be in ascending order.
609 /// Post-register allocation passes should not attempt to change allocations
610 /// for sources of instructions with this flag.
611 bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const {
612 return hasProperty(MCID::ExtraSrcRegAllocReq, Type);
613 }
615 /// hasExtraDefRegAllocReq - Returns true if this instruction def operands
616 /// have special register allocation requirements that are not captured by the
617 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
618 /// even / odd pair, ARM::LDM registers have to be in ascending order.
619 /// Post-register allocation passes should not attempt to change allocations
620 /// for definitions of instructions with this flag.
621 bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const {
622 return hasProperty(MCID::ExtraDefRegAllocReq, Type);
623 }
626 enum MICheckType {
627 CheckDefs, // Check all operands for equality
628 CheckKillDead, // Check all operands including kill / dead markers
629 IgnoreDefs, // Ignore all definitions
630 IgnoreVRegDefs // Ignore virtual register definitions
631 };
633 /// isIdenticalTo - Return true if this instruction is identical to (same
634 /// opcode and same operands as) the specified instruction.
635 bool isIdenticalTo(const MachineInstr *Other,
636 MICheckType Check = CheckDefs) const;
638 /// Unlink 'this' from the containing basic block, and return it without
639 /// deleting it.
640 ///
641 /// This function can not be used on bundled instructions, use
642 /// removeFromBundle() to remove individual instructions from a bundle.
643 MachineInstr *removeFromParent();
645 /// Unlink this instruction from its basic block and return it without
646 /// deleting it.
647 ///
648 /// If the instruction is part of a bundle, the other instructions in the
649 /// bundle remain bundled.
650 MachineInstr *removeFromBundle();
652 /// Unlink 'this' from the containing basic block and delete it.
653 ///
654 /// If this instruction is the header of a bundle, the whole bundle is erased.
655 /// This function can not be used for instructions inside a bundle, use
656 /// eraseFromBundle() to erase individual bundled instructions.
657 void eraseFromParent();
659 /// Unlink 'this' form its basic block and delete it.
660 ///
661 /// If the instruction is part of a bundle, the other instructions in the
662 /// bundle remain bundled.
663 void eraseFromBundle();
665 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
666 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
668 /// isLabel - Returns true if the MachineInstr represents a label.
669 ///
670 bool isLabel() const { return isEHLabel() || isGCLabel(); }
671 bool isCFIInstruction() const {
672 return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
673 }
675 // True if the instruction represents a position in the function.
676 bool isPosition() const { return isLabel() || isCFIInstruction(); }
678 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
679 /// A DBG_VALUE is indirect iff the first operand is a register and
680 /// the second operand is an immediate.
681 bool isIndirectDebugValue() const {
682 return isDebugValue()
683 && getOperand(0).isReg()
684 && getOperand(1).isImm();
685 }
687 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
688 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
689 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
690 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
691 bool isMSInlineAsm() const {
692 return getOpcode() == TargetOpcode::INLINEASM && getInlineAsmDialect();
693 }
694 bool isStackAligningInlineAsm() const;
695 InlineAsm::AsmDialect getInlineAsmDialect() const;
696 bool isInsertSubreg() const {
697 return getOpcode() == TargetOpcode::INSERT_SUBREG;
698 }
699 bool isSubregToReg() const {
700 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
701 }
702 bool isRegSequence() const {
703 return getOpcode() == TargetOpcode::REG_SEQUENCE;
704 }
705 bool isBundle() const {
706 return getOpcode() == TargetOpcode::BUNDLE;
707 }
708 bool isCopy() const {
709 return getOpcode() == TargetOpcode::COPY;
710 }
711 bool isFullCopy() const {
712 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
713 }
715 /// isCopyLike - Return true if the instruction behaves like a copy.
716 /// This does not include native copy instructions.
717 bool isCopyLike() const {
718 return isCopy() || isSubregToReg();
719 }
721 /// isIdentityCopy - Return true is the instruction is an identity copy.
722 bool isIdentityCopy() const {
723 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
724 getOperand(0).getSubReg() == getOperand(1).getSubReg();
725 }
727 /// isTransient - Return true if this is a transient instruction that is
728 /// either very likely to be eliminated during register allocation (such as
729 /// copy-like instructions), or if this instruction doesn't have an
730 /// execution-time cost.
731 bool isTransient() const {
732 switch(getOpcode()) {
733 default: return false;
734 // Copy-like instructions are usually eliminated during register allocation.
735 case TargetOpcode::PHI:
736 case TargetOpcode::COPY:
737 case TargetOpcode::INSERT_SUBREG:
738 case TargetOpcode::SUBREG_TO_REG:
739 case TargetOpcode::REG_SEQUENCE:
740 // Pseudo-instructions that don't produce any real output.
741 case TargetOpcode::IMPLICIT_DEF:
742 case TargetOpcode::KILL:
743 case TargetOpcode::CFI_INSTRUCTION:
744 case TargetOpcode::EH_LABEL:
745 case TargetOpcode::GC_LABEL:
746 case TargetOpcode::DBG_VALUE:
747 return true;
748 }
749 }
751 /// Return the number of instructions inside the MI bundle, excluding the
752 /// bundle header.
753 ///
754 /// This is the number of instructions that MachineBasicBlock::iterator
755 /// skips, 0 for unbundled instructions.
756 unsigned getBundleSize() const;
758 /// readsRegister - Return true if the MachineInstr reads the specified
759 /// register. If TargetRegisterInfo is passed, then it also checks if there
760 /// is a read of a super-register.
761 /// This does not count partial redefines of virtual registers as reads:
762 /// %reg1024:6 = OP.
763 bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
764 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
765 }
767 /// readsVirtualRegister - Return true if the MachineInstr reads the specified
768 /// virtual register. Take into account that a partial define is a
769 /// read-modify-write operation.
770 bool readsVirtualRegister(unsigned Reg) const {
771 return readsWritesVirtualRegister(Reg).first;
772 }
774 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
775 /// indicating if this instruction reads or writes Reg. This also considers
776 /// partial defines.
777 /// If Ops is not null, all operand indices for Reg are added.
778 std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg,
779 SmallVectorImpl<unsigned> *Ops = 0) const;
781 /// killsRegister - Return true if the MachineInstr kills the specified
782 /// register. If TargetRegisterInfo is passed, then it also checks if there is
783 /// a kill of a super-register.
784 bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
785 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
786 }
788 /// definesRegister - Return true if the MachineInstr fully defines the
789 /// specified register. If TargetRegisterInfo is passed, then it also checks
790 /// if there is a def of a super-register.
791 /// NOTE: It's ignoring subreg indices on virtual registers.
792 bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=NULL) const {
793 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
794 }
796 /// modifiesRegister - Return true if the MachineInstr modifies (fully define
797 /// or partially define) the specified register.
798 /// NOTE: It's ignoring subreg indices on virtual registers.
799 bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
800 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
801 }
803 /// registerDefIsDead - Returns true if the register is dead in this machine
804 /// instruction. If TargetRegisterInfo is passed, then it also checks
805 /// if there is a dead def of a super-register.
806 bool registerDefIsDead(unsigned Reg,
807 const TargetRegisterInfo *TRI = NULL) const {
808 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
809 }
811 /// findRegisterUseOperandIdx() - Returns the operand index that is a use of
812 /// the specific register or -1 if it is not found. It further tightens
813 /// the search criteria to a use that kills the register if isKill is true.
814 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
815 const TargetRegisterInfo *TRI = NULL) const;
817 /// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns
818 /// a pointer to the MachineOperand rather than an index.
819 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
820 const TargetRegisterInfo *TRI = NULL) {
821 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
822 return (Idx == -1) ? NULL : &getOperand(Idx);
823 }
825 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
826 /// the specified register or -1 if it is not found. If isDead is true, defs
827 /// that are not dead are skipped. If Overlap is true, then it also looks for
828 /// defs that merely overlap the specified register. If TargetRegisterInfo is
829 /// non-null, then it also checks if there is a def of a super-register.
830 /// This may also return a register mask operand when Overlap is true.
831 int findRegisterDefOperandIdx(unsigned Reg,
832 bool isDead = false, bool Overlap = false,
833 const TargetRegisterInfo *TRI = NULL) const;
835 /// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns
836 /// a pointer to the MachineOperand rather than an index.
837 MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
838 const TargetRegisterInfo *TRI = NULL) {
839 int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
840 return (Idx == -1) ? NULL : &getOperand(Idx);
841 }
843 /// findFirstPredOperandIdx() - Find the index of the first operand in the
844 /// operand list that is used to represent the predicate. It returns -1 if
845 /// none is found.
846 int findFirstPredOperandIdx() const;
848 /// findInlineAsmFlagIdx() - Find the index of the flag word operand that
849 /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
850 /// getOperand(OpIdx) does not belong to an inline asm operand group.
851 ///
852 /// If GroupNo is not NULL, it will receive the number of the operand group
853 /// containing OpIdx.
854 ///
855 /// The flag operand is an immediate that can be decoded with methods like
856 /// InlineAsm::hasRegClassConstraint().
857 ///
858 int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = 0) const;
860 /// getRegClassConstraint - Compute the static register class constraint for
861 /// operand OpIdx. For normal instructions, this is derived from the
862 /// MCInstrDesc. For inline assembly it is derived from the flag words.
863 ///
864 /// Returns NULL if the static register classs constraint cannot be
865 /// determined.
866 ///
867 const TargetRegisterClass*
868 getRegClassConstraint(unsigned OpIdx,
869 const TargetInstrInfo *TII,
870 const TargetRegisterInfo *TRI) const;
872 /// \brief Applies the constraints (def/use) implied by this MI on \p Reg to
873 /// the given \p CurRC.
874 /// If \p ExploreBundle is set and MI is part of a bundle, all the
875 /// instructions inside the bundle will be taken into account. In other words,
876 /// this method accumulates all the constrains of the operand of this MI and
877 /// the related bundle if MI is a bundle or inside a bundle.
878 ///
879 /// Returns the register class that statisfies both \p CurRC and the
880 /// constraints set by MI. Returns NULL if such a register class does not
881 /// exist.
882 ///
883 /// \pre CurRC must not be NULL.
884 const TargetRegisterClass *getRegClassConstraintEffectForVReg(
885 unsigned Reg, const TargetRegisterClass *CurRC,
886 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
887 bool ExploreBundle = false) const;
889 /// \brief Applies the constraints (def/use) implied by the \p OpIdx operand
890 /// to the given \p CurRC.
891 ///
892 /// Returns the register class that statisfies both \p CurRC and the
893 /// constraints set by \p OpIdx MI. Returns NULL if such a register class
894 /// does not exist.
895 ///
896 /// \pre CurRC must not be NULL.
897 /// \pre The operand at \p OpIdx must be a register.
898 const TargetRegisterClass *
899 getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC,
900 const TargetInstrInfo *TII,
901 const TargetRegisterInfo *TRI) const;
903 /// tieOperands - Add a tie between the register operands at DefIdx and
904 /// UseIdx. The tie will cause the register allocator to ensure that the two
905 /// operands are assigned the same physical register.
906 ///
907 /// Tied operands are managed automatically for explicit operands in the
908 /// MCInstrDesc. This method is for exceptional cases like inline asm.
909 void tieOperands(unsigned DefIdx, unsigned UseIdx);
911 /// findTiedOperandIdx - Given the index of a tied register operand, find the
912 /// operand it is tied to. Defs are tied to uses and vice versa. Returns the
913 /// index of the tied operand which must exist.
914 unsigned findTiedOperandIdx(unsigned OpIdx) const;
916 /// isRegTiedToUseOperand - Given the index of a register def operand,
917 /// check if the register def is tied to a source operand, due to either
918 /// two-address elimination or inline assembly constraints. Returns the
919 /// first tied use operand index by reference if UseOpIdx is not null.
920 bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx = 0) const {
921 const MachineOperand &MO = getOperand(DefOpIdx);
922 if (!MO.isReg() || !MO.isDef() || !MO.isTied())
923 return false;
924 if (UseOpIdx)
925 *UseOpIdx = findTiedOperandIdx(DefOpIdx);
926 return true;
927 }
929 /// isRegTiedToDefOperand - Return true if the use operand of the specified
930 /// index is tied to an def operand. It also returns the def operand index by
931 /// reference if DefOpIdx is not null.
932 bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx = 0) const {
933 const MachineOperand &MO = getOperand(UseOpIdx);
934 if (!MO.isReg() || !MO.isUse() || !MO.isTied())
935 return false;
936 if (DefOpIdx)
937 *DefOpIdx = findTiedOperandIdx(UseOpIdx);
938 return true;
939 }
941 /// clearKillInfo - Clears kill flags on all operands.
942 ///
943 void clearKillInfo();
945 /// substituteRegister - Replace all occurrences of FromReg with ToReg:SubIdx,
946 /// properly composing subreg indices where necessary.
947 void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
948 const TargetRegisterInfo &RegInfo);
950 /// addRegisterKilled - We have determined MI kills a register. Look for the
951 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
952 /// add a implicit operand if it's not found. Returns true if the operand
953 /// exists / is added.
954 bool addRegisterKilled(unsigned IncomingReg,
955 const TargetRegisterInfo *RegInfo,
956 bool AddIfNotFound = false);
958 /// clearRegisterKills - Clear all kill flags affecting Reg. If RegInfo is
959 /// provided, this includes super-register kills.
960 void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo);
962 /// addRegisterDead - We have determined MI defined a register without a use.
963 /// Look for the operand that defines it and mark it as IsDead. If
964 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
965 /// true if the operand exists / is added.
966 bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo,
967 bool AddIfNotFound = false);
969 /// addRegisterDefined - We have determined MI defines a register. Make sure
970 /// there is an operand defining Reg.
971 void addRegisterDefined(unsigned Reg, const TargetRegisterInfo *RegInfo = 0);
973 /// setPhysRegsDeadExcept - Mark every physreg used by this instruction as
974 /// dead except those in the UsedRegs list.
975 ///
976 /// On instructions with register mask operands, also add implicit-def
977 /// operands for all registers in UsedRegs.
978 void setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
979 const TargetRegisterInfo &TRI);
981 /// isSafeToMove - Return true if it is safe to move this instruction. If
982 /// SawStore is set to true, it means that there is a store (or call) between
983 /// the instruction's location and its intended destination.
984 bool isSafeToMove(const TargetInstrInfo *TII, AliasAnalysis *AA,
985 bool &SawStore) const;
987 /// hasOrderedMemoryRef - Return true if this instruction may have an ordered
988 /// or volatile memory reference, or if the information describing the memory
989 /// reference is not available. Return false if it is known to have no
990 /// ordered or volatile memory references.
991 bool hasOrderedMemoryRef() const;
993 /// isInvariantLoad - Return true if this instruction is loading from a
994 /// location whose value is invariant across the function. For example,
995 /// loading a value from the constant pool or from the argument area of
996 /// a function if it does not change. This should only return true of *all*
997 /// loads the instruction does are invariant (if it does multiple loads).
998 bool isInvariantLoad(AliasAnalysis *AA) const;
1000 /// isConstantValuePHI - If the specified instruction is a PHI that always
1001 /// merges together the same virtual register, return the register, otherwise
1002 /// return 0.
1003 unsigned isConstantValuePHI() const;
1005 /// hasUnmodeledSideEffects - Return true if this instruction has side
1006 /// effects that are not modeled by mayLoad / mayStore, etc.
1007 /// For all instructions, the property is encoded in MCInstrDesc::Flags
1008 /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
1009 /// INLINEASM instruction, in which case the side effect property is encoded
1010 /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
1011 ///
1012 bool hasUnmodeledSideEffects() const;
1014 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
1015 ///
1016 bool allDefsAreDead() const;
1018 /// copyImplicitOps - Copy implicit register operands from specified
1019 /// instruction to this instruction.
1020 void copyImplicitOps(MachineFunction &MF, const MachineInstr *MI);
1022 //
1023 // Debugging support
1024 //
1025 void print(raw_ostream &OS, const TargetMachine *TM = 0,
1026 bool SkipOpers = false) const;
1027 void dump() const;
1029 //===--------------------------------------------------------------------===//
1030 // Accessors used to build up machine instructions.
1032 /// Add the specified operand to the instruction. If it is an implicit
1033 /// operand, it is added to the end of the operand list. If it is an
1034 /// explicit operand it is added at the end of the explicit operand list
1035 /// (before the first implicit operand).
1036 ///
1037 /// MF must be the machine function that was used to allocate this
1038 /// instruction.
1039 ///
1040 /// MachineInstrBuilder provides a more convenient interface for creating
1041 /// instructions and adding operands.
1042 void addOperand(MachineFunction &MF, const MachineOperand &Op);
1044 /// Add an operand without providing an MF reference. This only works for
1045 /// instructions that are inserted in a basic block.
1046 ///
1047 /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be
1048 /// preferred.
1049 void addOperand(const MachineOperand &Op);
1051 /// setDesc - Replace the instruction descriptor (thus opcode) of
1052 /// the current instruction with a new one.
1053 ///
1054 void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
1056 /// setDebugLoc - Replace current source information with new such.
1057 /// Avoid using this, the constructor argument is preferable.
1058 ///
1059 void setDebugLoc(const DebugLoc dl) { debugLoc = dl; }
1061 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
1062 /// fewer operand than it started with.
1063 ///
1064 void RemoveOperand(unsigned i);
1066 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
1067 /// This function should be used only occasionally. The setMemRefs function
1068 /// is the primary method for setting up a MachineInstr's MemRefs list.
1069 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
1071 /// setMemRefs - Assign this MachineInstr's memory reference descriptor
1072 /// list. This does not transfer ownership.
1073 void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
1074 MemRefs = NewMemRefs;
1075 NumMemRefs = uint8_t(NewMemRefsEnd - NewMemRefs);
1076 assert(NumMemRefs == NewMemRefsEnd - NewMemRefs && "Too many memrefs");
1077 }
1079 private:
1080 /// getRegInfo - If this instruction is embedded into a MachineFunction,
1081 /// return the MachineRegisterInfo object for the current function, otherwise
1082 /// return null.
1083 MachineRegisterInfo *getRegInfo();
1085 /// untieRegOperand - Break any tie involving OpIdx.
1086 void untieRegOperand(unsigned OpIdx) {
1087 MachineOperand &MO = getOperand(OpIdx);
1088 if (MO.isReg() && MO.isTied()) {
1089 getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
1090 MO.TiedTo = 0;
1091 }
1092 }
1094 /// addImplicitDefUseOperands - Add all implicit def and use operands to
1095 /// this instruction.
1096 void addImplicitDefUseOperands(MachineFunction &MF);
1098 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
1099 /// this instruction from their respective use lists. This requires that the
1100 /// operands already be on their use lists.
1101 void RemoveRegOperandsFromUseLists(MachineRegisterInfo&);
1103 /// AddRegOperandsToUseLists - Add all of the register operands in
1104 /// this instruction from their respective use lists. This requires that the
1105 /// operands not be on their use lists yet.
1106 void AddRegOperandsToUseLists(MachineRegisterInfo&);
1108 /// hasPropertyInBundle - Slow path for hasProperty when we're dealing with a
1109 /// bundle.
1110 bool hasPropertyInBundle(unsigned Mask, QueryType Type) const;
1112 /// \brief Implements the logic of getRegClassConstraintEffectForVReg for the
1113 /// this MI and the given operand index \p OpIdx.
1114 /// If the related operand does not constrained Reg, this returns CurRC.
1115 const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl(
1116 unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC,
1117 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const;
1118 };
1120 /// MachineInstrExpressionTrait - Special DenseMapInfo traits to compare
1121 /// MachineInstr* by *value* of the instruction rather than by pointer value.
1122 /// The hashing and equality testing functions ignore definitions so this is
1123 /// useful for CSE, etc.
1124 struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
1125 static inline MachineInstr *getEmptyKey() {
1126 return 0;
1127 }
1129 static inline MachineInstr *getTombstoneKey() {
1130 return reinterpret_cast<MachineInstr*>(-1);
1131 }
1133 static unsigned getHashValue(const MachineInstr* const &MI);
1135 static bool isEqual(const MachineInstr* const &LHS,
1136 const MachineInstr* const &RHS) {
1137 if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
1138 LHS == getEmptyKey() || LHS == getTombstoneKey())
1139 return LHS == RHS;
1140 return LHS->isIdenticalTo(RHS, MachineInstr::IgnoreVRegDefs);
1141 }
1142 };
1144 //===----------------------------------------------------------------------===//
1145 // Debugging Support
1147 inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
1148 MI.print(OS);
1149 return OS;
1150 }
1152 } // End llvm namespace
1154 #endif