1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
12 // the back end.
13 //
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/ADT/DenseMapInfo.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/ADT/ilist.h"
24 #include "llvm/ADT/ilist_node.h"
25 #include "llvm/CodeGen/MachineOperand.h"
26 #include "llvm/IR/InlineAsm.h"
27 #include "llvm/MC/MCInstrDesc.h"
28 #include "llvm/Support/ArrayRecycler.h"
29 #include "llvm/Support/DebugLoc.h"
30 #include "llvm/Target/TargetOpcodes.h"
31 #include <vector>
33 namespace llvm {
35 template <typename T> class SmallVectorImpl;
36 class AliasAnalysis;
37 class TargetInstrInfo;
38 class TargetRegisterClass;
39 class TargetRegisterInfo;
40 class MachineFunction;
41 class MachineMemOperand;
43 //===----------------------------------------------------------------------===//
44 /// MachineInstr - Representation of each machine instruction.
45 ///
46 /// This class isn't a POD type, but it must have a trivial destructor. When a
47 /// MachineFunction is deleted, all the contained MachineInstrs are deallocated
48 /// without having their destructor called.
49 ///
50 class MachineInstr : public ilist_node<MachineInstr> {
51 public:
52 typedef MachineMemOperand **mmo_iterator;
54 /// Flags to specify different kinds of comments to output in
55 /// assembly code. These flags carry semantic information not
56 /// otherwise easily derivable from the IR text.
57 ///
58 enum CommentFlag {
59 ReloadReuse = 0x1
60 };
62 enum MIFlag {
63 NoFlags = 0,
64 FrameSetup = 1 << 0, // Instruction is used as a part of
65 // function frame setup code.
66 BundledPred = 1 << 1, // Instruction has bundled predecessors.
67 BundledSucc = 1 << 2 // Instruction has bundled successors.
68 };
69 private:
70 const MCInstrDesc *MCID; // Instruction descriptor.
71 MachineBasicBlock *Parent; // Pointer to the owning basic block.
73 // Operands are allocated by an ArrayRecycler.
74 MachineOperand *Operands; // Pointer to the first operand.
75 unsigned NumOperands; // Number of operands on instruction.
76 typedef ArrayRecycler<MachineOperand>::Capacity OperandCapacity;
77 OperandCapacity CapOperands; // Capacity of the Operands array.
79 uint8_t Flags; // Various bits of additional
80 // information about machine
81 // instruction.
83 uint8_t AsmPrinterFlags; // Various bits of information used by
84 // the AsmPrinter to emit helpful
85 // comments. This is *not* semantic
86 // information. Do not use this for
87 // anything other than to convey comment
88 // information to AsmPrinter.
90 uint8_t NumMemRefs; // Information on memory references.
91 mmo_iterator MemRefs;
93 DebugLoc debugLoc; // Source line information.
95 MachineInstr(const MachineInstr&) LLVM_DELETED_FUNCTION;
96 void operator=(const MachineInstr&) LLVM_DELETED_FUNCTION;
97 // Use MachineFunction::DeleteMachineInstr() instead.
98 ~MachineInstr() LLVM_DELETED_FUNCTION;
100 // Intrusive list support
101 friend struct ilist_traits<MachineInstr>;
102 friend struct ilist_traits<MachineBasicBlock>;
103 void setParent(MachineBasicBlock *P) { Parent = P; }
105 /// MachineInstr ctor - This constructor creates a copy of the given
106 /// MachineInstr in the given MachineFunction.
107 MachineInstr(MachineFunction &, const MachineInstr &);
109 /// MachineInstr ctor - This constructor create a MachineInstr and add the
110 /// implicit operands. It reserves space for number of operands specified by
111 /// MCInstrDesc. An explicit DebugLoc is supplied.
112 MachineInstr(MachineFunction&, const MCInstrDesc &MCID,
113 const DebugLoc dl, bool NoImp = false);
115 // MachineInstrs are pool-allocated and owned by MachineFunction.
116 friend class MachineFunction;
118 public:
119 const MachineBasicBlock* getParent() const { return Parent; }
120 MachineBasicBlock* getParent() { return Parent; }
122 /// getAsmPrinterFlags - Return the asm printer flags bitvector.
123 ///
124 uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
126 /// clearAsmPrinterFlags - clear the AsmPrinter bitvector
127 ///
128 void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
130 /// getAsmPrinterFlag - Return whether an AsmPrinter flag is set.
131 ///
132 bool getAsmPrinterFlag(CommentFlag Flag) const {
133 return AsmPrinterFlags & Flag;
134 }
136 /// setAsmPrinterFlag - Set a flag for the AsmPrinter.
137 ///
138 void setAsmPrinterFlag(CommentFlag Flag) {
139 AsmPrinterFlags |= (uint8_t)Flag;
140 }
142 /// clearAsmPrinterFlag - clear specific AsmPrinter flags
143 ///
144 void clearAsmPrinterFlag(CommentFlag Flag) {
145 AsmPrinterFlags &= ~Flag;
146 }
148 /// getFlags - Return the MI flags bitvector.
149 uint8_t getFlags() const {
150 return Flags;
151 }
153 /// getFlag - Return whether an MI flag is set.
154 bool getFlag(MIFlag Flag) const {
155 return Flags & Flag;
156 }
158 /// setFlag - Set a MI flag.
159 void setFlag(MIFlag Flag) {
160 Flags |= (uint8_t)Flag;
161 }
163 void setFlags(unsigned flags) {
164 // Filter out the automatically maintained flags.
165 unsigned Mask = BundledPred | BundledSucc;
166 Flags = (Flags & Mask) | (flags & ~Mask);
167 }
169 /// clearFlag - Clear a MI flag.
170 void clearFlag(MIFlag Flag) {
171 Flags &= ~((uint8_t)Flag);
172 }
174 /// isInsideBundle - Return true if MI is in a bundle (but not the first MI
175 /// in a bundle).
176 ///
177 /// A bundle looks like this before it's finalized:
178 /// ----------------
179 /// | MI |
180 /// ----------------
181 /// |
182 /// ----------------
183 /// | MI * |
184 /// ----------------
185 /// |
186 /// ----------------
187 /// | MI * |
188 /// ----------------
189 /// In this case, the first MI starts a bundle but is not inside a bundle, the
190 /// next 2 MIs are considered "inside" the bundle.
191 ///
192 /// After a bundle is finalized, it looks like this:
193 /// ----------------
194 /// | Bundle |
195 /// ----------------
196 /// |
197 /// ----------------
198 /// | MI * |
199 /// ----------------
200 /// |
201 /// ----------------
202 /// | MI * |
203 /// ----------------
204 /// |
205 /// ----------------
206 /// | MI * |
207 /// ----------------
208 /// The first instruction has the special opcode "BUNDLE". It's not "inside"
209 /// a bundle, but the next three MIs are.
210 bool isInsideBundle() const {
211 return getFlag(BundledPred);
212 }
214 /// isBundled - Return true if this instruction part of a bundle. This is true
215 /// if either itself or its following instruction is marked "InsideBundle".
216 bool isBundled() const {
217 return isBundledWithPred() || isBundledWithSucc();
218 }
220 /// Return true if this instruction is part of a bundle, and it is not the
221 /// first instruction in the bundle.
222 bool isBundledWithPred() const { return getFlag(BundledPred); }
224 /// Return true if this instruction is part of a bundle, and it is not the
225 /// last instruction in the bundle.
226 bool isBundledWithSucc() const { return getFlag(BundledSucc); }
228 /// Bundle this instruction with its predecessor. This can be an unbundled
229 /// instruction, or it can be the first instruction in a bundle.
230 void bundleWithPred();
232 /// Bundle this instruction with its successor. This can be an unbundled
233 /// instruction, or it can be the last instruction in a bundle.
234 void bundleWithSucc();
236 /// Break bundle above this instruction.
237 void unbundleFromPred();
239 /// Break bundle below this instruction.
240 void unbundleFromSucc();
242 /// getDebugLoc - Returns the debug location id of this MachineInstr.
243 ///
244 DebugLoc getDebugLoc() const { return debugLoc; }
246 /// emitError - Emit an error referring to the source location of this
247 /// instruction. This should only be used for inline assembly that is somehow
248 /// impossible to compile. Other errors should have been handled much
249 /// earlier.
250 ///
251 /// If this method returns, the caller should try to recover from the error.
252 ///
253 void emitError(StringRef Msg) const;
255 /// getDesc - Returns the target instruction descriptor of this
256 /// MachineInstr.
257 const MCInstrDesc &getDesc() const { return *MCID; }
259 /// getOpcode - Returns the opcode of this MachineInstr.
260 ///
261 int getOpcode() const { return MCID->Opcode; }
263 /// Access to explicit operands of the instruction.
264 ///
265 unsigned getNumOperands() const { return NumOperands; }
267 const MachineOperand& getOperand(unsigned i) const {
268 assert(i < getNumOperands() && "getOperand() out of range!");
269 return Operands[i];
270 }
271 MachineOperand& getOperand(unsigned i) {
272 assert(i < getNumOperands() && "getOperand() out of range!");
273 return Operands[i];
274 }
276 /// getNumExplicitOperands - Returns the number of non-implicit operands.
277 ///
278 unsigned getNumExplicitOperands() const;
280 /// iterator/begin/end - Iterate over all operands of a machine instruction.
281 typedef MachineOperand *mop_iterator;
282 typedef const MachineOperand *const_mop_iterator;
284 mop_iterator operands_begin() { return Operands; }
285 mop_iterator operands_end() { return Operands + NumOperands; }
287 const_mop_iterator operands_begin() const { return Operands; }
288 const_mop_iterator operands_end() const { return Operands + NumOperands; }
290 /// Access to memory operands of the instruction
291 mmo_iterator memoperands_begin() const { return MemRefs; }
292 mmo_iterator memoperands_end() const { return MemRefs + NumMemRefs; }
293 bool memoperands_empty() const { return NumMemRefs == 0; }
295 /// hasOneMemOperand - Return true if this instruction has exactly one
296 /// MachineMemOperand.
297 bool hasOneMemOperand() const {
298 return NumMemRefs == 1;
299 }
301 /// API for querying MachineInstr properties. They are the same as MCInstrDesc
302 /// queries but they are bundle aware.
304 enum QueryType {
305 IgnoreBundle, // Ignore bundles
306 AnyInBundle, // Return true if any instruction in bundle has property
307 AllInBundle // Return true if all instructions in bundle have property
308 };
310 /// hasProperty - Return true if the instruction (or in the case of a bundle,
311 /// the instructions inside the bundle) has the specified property.
312 /// The first argument is the property being queried.
313 /// The second argument indicates whether the query should look inside
314 /// instruction bundles.
315 bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
316 // Inline the fast path for unbundled or bundle-internal instructions.
317 if (Type == IgnoreBundle || !isBundled() || isBundledWithPred())
318 return getDesc().getFlags() & (1 << MCFlag);
320 // If this is the first instruction in a bundle, take the slow path.
321 return hasPropertyInBundle(1 << MCFlag, Type);
322 }
324 /// isVariadic - Return true if this instruction can have a variable number of
325 /// operands. In this case, the variable operands will be after the normal
326 /// operands but before the implicit definitions and uses (if any are
327 /// present).
328 bool isVariadic(QueryType Type = IgnoreBundle) const {
329 return hasProperty(MCID::Variadic, Type);
330 }
332 /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
333 /// ARM instructions which can set condition code if 's' bit is set.
334 bool hasOptionalDef(QueryType Type = IgnoreBundle) const {
335 return hasProperty(MCID::HasOptionalDef, Type);
336 }
338 /// isPseudo - Return true if this is a pseudo instruction that doesn't
339 /// correspond to a real machine instruction.
340 ///
341 bool isPseudo(QueryType Type = IgnoreBundle) const {
342 return hasProperty(MCID::Pseudo, Type);
343 }
345 bool isReturn(QueryType Type = AnyInBundle) const {
346 return hasProperty(MCID::Return, Type);
347 }
349 bool isCall(QueryType Type = AnyInBundle) const {
350 return hasProperty(MCID::Call, Type);
351 }
353 /// isBarrier - Returns true if the specified instruction stops control flow
354 /// from executing the instruction immediately following it. Examples include
355 /// unconditional branches and return instructions.
356 bool isBarrier(QueryType Type = AnyInBundle) const {
357 return hasProperty(MCID::Barrier, Type);
358 }
360 /// isTerminator - Returns true if this instruction part of the terminator for
361 /// a basic block. Typically this is things like return and branch
362 /// instructions.
363 ///
364 /// Various passes use this to insert code into the bottom of a basic block,
365 /// but before control flow occurs.
366 bool isTerminator(QueryType Type = AnyInBundle) const {
367 return hasProperty(MCID::Terminator, Type);
368 }
370 /// isBranch - Returns true if this is a conditional, unconditional, or
371 /// indirect branch. Predicates below can be used to discriminate between
372 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
373 /// get more information.
374 bool isBranch(QueryType Type = AnyInBundle) const {
375 return hasProperty(MCID::Branch, Type);
376 }
378 /// isIndirectBranch - Return true if this is an indirect branch, such as a
379 /// branch through a register.
380 bool isIndirectBranch(QueryType Type = AnyInBundle) const {
381 return hasProperty(MCID::IndirectBranch, Type);
382 }
384 /// isConditionalBranch - Return true if this is a branch which may fall
385 /// through to the next instruction or may transfer control flow to some other
386 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
387 /// information about this branch.
388 bool isConditionalBranch(QueryType Type = AnyInBundle) const {
389 return isBranch(Type) & !isBarrier(Type) & !isIndirectBranch(Type);
390 }
392 /// isUnconditionalBranch - Return true if this is a branch which always
393 /// transfers control flow to some other block. The
394 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
395 /// about this branch.
396 bool isUnconditionalBranch(QueryType Type = AnyInBundle) const {
397 return isBranch(Type) & isBarrier(Type) & !isIndirectBranch(Type);
398 }
400 // isPredicable - Return true if this instruction has a predicate operand that
401 // controls execution. It may be set to 'always', or may be set to other
402 /// values. There are various methods in TargetInstrInfo that can be used to
403 /// control and modify the predicate in this instruction.
404 bool isPredicable(QueryType Type = AllInBundle) const {
405 // If it's a bundle than all bundled instructions must be predicable for this
406 // to return true.
407 return hasProperty(MCID::Predicable, Type);
408 }
410 /// isCompare - Return true if this instruction is a comparison.
411 bool isCompare(QueryType Type = IgnoreBundle) const {
412 return hasProperty(MCID::Compare, Type);
413 }
415 /// isMoveImmediate - Return true if this instruction is a move immediate
416 /// (including conditional moves) instruction.
417 bool isMoveImmediate(QueryType Type = IgnoreBundle) const {
418 return hasProperty(MCID::MoveImm, Type);
419 }
421 /// isBitcast - Return true if this instruction is a bitcast instruction.
422 ///
423 bool isBitcast(QueryType Type = IgnoreBundle) const {
424 return hasProperty(MCID::Bitcast, Type);
425 }
427 /// isSelect - Return true if this instruction is a select instruction.
428 ///
429 bool isSelect(QueryType Type = IgnoreBundle) const {
430 return hasProperty(MCID::Select, Type);
431 }
433 /// isNotDuplicable - Return true if this instruction cannot be safely
434 /// duplicated. For example, if the instruction has a unique labels attached
435 /// to it, duplicating it would cause multiple definition errors.
436 bool isNotDuplicable(QueryType Type = AnyInBundle) const {
437 return hasProperty(MCID::NotDuplicable, Type);
438 }
440 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
441 /// which must be filled by the code generator.
442 bool hasDelaySlot(QueryType Type = AnyInBundle) const {
443 return hasProperty(MCID::DelaySlot, Type);
444 }
446 /// canFoldAsLoad - Return true for instructions that can be folded as
447 /// memory operands in other instructions. The most common use for this
448 /// is instructions that are simple loads from memory that don't modify
449 /// the loaded value in any way, but it can also be used for instructions
450 /// that can be expressed as constant-pool loads, such as V_SETALLONES
451 /// on x86, to allow them to be folded when it is beneficial.
452 /// This should only be set on instructions that return a value in their
453 /// only virtual register definition.
454 bool canFoldAsLoad(QueryType Type = IgnoreBundle) const {
455 return hasProperty(MCID::FoldableAsLoad, Type);
456 }
458 //===--------------------------------------------------------------------===//
459 // Side Effect Analysis
460 //===--------------------------------------------------------------------===//
462 /// mayLoad - Return true if this instruction could possibly read memory.
463 /// Instructions with this flag set are not necessarily simple load
464 /// instructions, they may load a value and modify it, for example.
465 bool mayLoad(QueryType Type = AnyInBundle) const {
466 if (isInlineAsm()) {
467 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
468 if (ExtraInfo & InlineAsm::Extra_MayLoad)
469 return true;
470 }
471 return hasProperty(MCID::MayLoad, Type);
472 }
475 /// mayStore - Return true if this instruction could possibly modify memory.
476 /// Instructions with this flag set are not necessarily simple store
477 /// instructions, they may store a modified value based on their operands, or
478 /// may not actually modify anything, for example.
479 bool mayStore(QueryType Type = AnyInBundle) const {
480 if (isInlineAsm()) {
481 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
482 if (ExtraInfo & InlineAsm::Extra_MayStore)
483 return true;
484 }
485 return hasProperty(MCID::MayStore, Type);
486 }
488 //===--------------------------------------------------------------------===//
489 // Flags that indicate whether an instruction can be modified by a method.
490 //===--------------------------------------------------------------------===//
492 /// isCommutable - Return true if this may be a 2- or 3-address
493 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
494 /// result if Y and Z are exchanged. If this flag is set, then the
495 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
496 /// instruction.
497 ///
498 /// Note that this flag may be set on instructions that are only commutable
499 /// sometimes. In these cases, the call to commuteInstruction will fail.
500 /// Also note that some instructions require non-trivial modification to
501 /// commute them.
502 bool isCommutable(QueryType Type = IgnoreBundle) const {
503 return hasProperty(MCID::Commutable, Type);
504 }
506 /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
507 /// which can be changed into a 3-address instruction if needed. Doing this
508 /// transformation can be profitable in the register allocator, because it
509 /// means that the instruction can use a 2-address form if possible, but
510 /// degrade into a less efficient form if the source and dest register cannot
511 /// be assigned to the same register. For example, this allows the x86
512 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
513 /// is the same speed as the shift but has bigger code size.
514 ///
515 /// If this returns true, then the target must implement the
516 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
517 /// is allowed to fail if the transformation isn't valid for this specific
518 /// instruction (e.g. shl reg, 4 on x86).
519 ///
520 bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const {
521 return hasProperty(MCID::ConvertibleTo3Addr, Type);
522 }
524 /// usesCustomInsertionHook - Return true if this instruction requires
525 /// custom insertion support when the DAG scheduler is inserting it into a
526 /// machine basic block. If this is true for the instruction, it basically
527 /// means that it is a pseudo instruction used at SelectionDAG time that is
528 /// expanded out into magic code by the target when MachineInstrs are formed.
529 ///
530 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
531 /// is used to insert this into the MachineBasicBlock.
532 bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const {
533 return hasProperty(MCID::UsesCustomInserter, Type);
534 }
536 /// hasPostISelHook - Return true if this instruction requires *adjustment*
537 /// after instruction selection by calling a target hook. For example, this
538 /// can be used to fill in ARM 's' optional operand depending on whether
539 /// the conditional flag register is used.
540 bool hasPostISelHook(QueryType Type = IgnoreBundle) const {
541 return hasProperty(MCID::HasPostISelHook, Type);
542 }
544 /// isRematerializable - Returns true if this instruction is a candidate for
545 /// remat. This flag is deprecated, please don't use it anymore. If this
546 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
547 /// verify the instruction is really rematable.
548 bool isRematerializable(QueryType Type = AllInBundle) const {
549 // It's only possible to re-mat a bundle if all bundled instructions are
550 // re-materializable.
551 return hasProperty(MCID::Rematerializable, Type);
552 }
554 /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or
555 /// less) than a move instruction. This is useful during certain types of
556 /// optimizations (e.g., remat during two-address conversion or machine licm)
557 /// where we would like to remat or hoist the instruction, but not if it costs
558 /// more than moving the instruction into the appropriate register. Note, we
559 /// are not marking copies from and to the same register class with this flag.
560 bool isAsCheapAsAMove(QueryType Type = AllInBundle) const {
561 // Only returns true for a bundle if all bundled instructions are cheap.
562 // FIXME: This probably requires a target hook.
563 return hasProperty(MCID::CheapAsAMove, Type);
564 }
566 /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands
567 /// have special register allocation requirements that are not captured by the
568 /// operand register classes. e.g. ARM::STRD's two source registers must be an
569 /// even / odd pair, ARM::STM registers have to be in ascending order.
570 /// Post-register allocation passes should not attempt to change allocations
571 /// for sources of instructions with this flag.
572 bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const {
573 return hasProperty(MCID::ExtraSrcRegAllocReq, Type);
574 }
576 /// hasExtraDefRegAllocReq - Returns true if this instruction def operands
577 /// have special register allocation requirements that are not captured by the
578 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
579 /// even / odd pair, ARM::LDM registers have to be in ascending order.
580 /// Post-register allocation passes should not attempt to change allocations
581 /// for definitions of instructions with this flag.
582 bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const {
583 return hasProperty(MCID::ExtraDefRegAllocReq, Type);
584 }
587 enum MICheckType {
588 CheckDefs, // Check all operands for equality
589 CheckKillDead, // Check all operands including kill / dead markers
590 IgnoreDefs, // Ignore all definitions
591 IgnoreVRegDefs // Ignore virtual register definitions
592 };
594 /// isIdenticalTo - Return true if this instruction is identical to (same
595 /// opcode and same operands as) the specified instruction.
596 bool isIdenticalTo(const MachineInstr *Other,
597 MICheckType Check = CheckDefs) const;
599 /// Unlink 'this' from the containing basic block, and return it without
600 /// deleting it.
601 ///
602 /// This function can not be used on bundled instructions, use
603 /// removeFromBundle() to remove individual instructions from a bundle.
604 MachineInstr *removeFromParent();
606 /// Unlink this instruction from its basic block and return it without
607 /// deleting it.
608 ///
609 /// If the instruction is part of a bundle, the other instructions in the
610 /// bundle remain bundled.
611 MachineInstr *removeFromBundle();
613 /// Unlink 'this' from the containing basic block and delete it.
614 ///
615 /// If this instruction is the header of a bundle, the whole bundle is erased.
616 /// This function can not be used for instructions inside a bundle, use
617 /// eraseFromBundle() to erase individual bundled instructions.
618 void eraseFromParent();
620 /// Unlink 'this' form its basic block and delete it.
621 ///
622 /// If the instruction is part of a bundle, the other instructions in the
623 /// bundle remain bundled.
624 void eraseFromBundle();
626 /// isLabel - Returns true if the MachineInstr represents a label.
627 ///
628 bool isLabel() const {
629 return getOpcode() == TargetOpcode::PROLOG_LABEL ||
630 getOpcode() == TargetOpcode::EH_LABEL ||
631 getOpcode() == TargetOpcode::GC_LABEL;
632 }
634 bool isPrologLabel() const {
635 return getOpcode() == TargetOpcode::PROLOG_LABEL;
636 }
637 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
638 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
639 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
641 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
642 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
643 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
644 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
645 bool isStackAligningInlineAsm() const;
646 InlineAsm::AsmDialect getInlineAsmDialect() const;
647 bool isInsertSubreg() const {
648 return getOpcode() == TargetOpcode::INSERT_SUBREG;
649 }
650 bool isSubregToReg() const {
651 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
652 }
653 bool isRegSequence() const {
654 return getOpcode() == TargetOpcode::REG_SEQUENCE;
655 }
656 bool isBundle() const {
657 return getOpcode() == TargetOpcode::BUNDLE;
658 }
659 bool isCopy() const {
660 return getOpcode() == TargetOpcode::COPY;
661 }
662 bool isFullCopy() const {
663 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
664 }
666 /// isCopyLike - Return true if the instruction behaves like a copy.
667 /// This does not include native copy instructions.
668 bool isCopyLike() const {
669 return isCopy() || isSubregToReg();
670 }
672 /// isIdentityCopy - Return true is the instruction is an identity copy.
673 bool isIdentityCopy() const {
674 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
675 getOperand(0).getSubReg() == getOperand(1).getSubReg();
676 }
678 /// isTransient - Return true if this is a transient instruction that is
679 /// either very likely to be eliminated during register allocation (such as
680 /// copy-like instructions), or if this instruction doesn't have an
681 /// execution-time cost.
682 bool isTransient() const {
683 switch(getOpcode()) {
684 default: return false;
685 // Copy-like instructions are usually eliminated during register allocation.
686 case TargetOpcode::PHI:
687 case TargetOpcode::COPY:
688 case TargetOpcode::INSERT_SUBREG:
689 case TargetOpcode::SUBREG_TO_REG:
690 case TargetOpcode::REG_SEQUENCE:
691 // Pseudo-instructions that don't produce any real output.
692 case TargetOpcode::IMPLICIT_DEF:
693 case TargetOpcode::KILL:
694 case TargetOpcode::PROLOG_LABEL:
695 case TargetOpcode::EH_LABEL:
696 case TargetOpcode::GC_LABEL:
697 case TargetOpcode::DBG_VALUE:
698 return true;
699 }
700 }
702 /// Return the number of instructions inside the MI bundle, excluding the
703 /// bundle header.
704 ///
705 /// This is the number of instructions that MachineBasicBlock::iterator
706 /// skips, 0 for unbundled instructions.
707 unsigned getBundleSize() const;
709 /// readsRegister - Return true if the MachineInstr reads the specified
710 /// register. If TargetRegisterInfo is passed, then it also checks if there
711 /// is a read of a super-register.
712 /// This does not count partial redefines of virtual registers as reads:
713 /// %reg1024:6 = OP.
714 bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
715 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
716 }
718 /// readsVirtualRegister - Return true if the MachineInstr reads the specified
719 /// virtual register. Take into account that a partial define is a
720 /// read-modify-write operation.
721 bool readsVirtualRegister(unsigned Reg) const {
722 return readsWritesVirtualRegister(Reg).first;
723 }
725 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
726 /// indicating if this instruction reads or writes Reg. This also considers
727 /// partial defines.
728 /// If Ops is not null, all operand indices for Reg are added.
729 std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg,
730 SmallVectorImpl<unsigned> *Ops = 0) const;
732 /// killsRegister - Return true if the MachineInstr kills the specified
733 /// register. If TargetRegisterInfo is passed, then it also checks if there is
734 /// a kill of a super-register.
735 bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
736 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
737 }
739 /// definesRegister - Return true if the MachineInstr fully defines the
740 /// specified register. If TargetRegisterInfo is passed, then it also checks
741 /// if there is a def of a super-register.
742 /// NOTE: It's ignoring subreg indices on virtual registers.
743 bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=NULL) const {
744 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
745 }
747 /// modifiesRegister - Return true if the MachineInstr modifies (fully define
748 /// or partially define) the specified register.
749 /// NOTE: It's ignoring subreg indices on virtual registers.
750 bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
751 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
752 }
754 /// registerDefIsDead - Returns true if the register is dead in this machine
755 /// instruction. If TargetRegisterInfo is passed, then it also checks
756 /// if there is a dead def of a super-register.
757 bool registerDefIsDead(unsigned Reg,
758 const TargetRegisterInfo *TRI = NULL) const {
759 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
760 }
762 /// findRegisterUseOperandIdx() - Returns the operand index that is a use of
763 /// the specific register or -1 if it is not found. It further tightens
764 /// the search criteria to a use that kills the register if isKill is true.
765 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
766 const TargetRegisterInfo *TRI = NULL) const;
768 /// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns
769 /// a pointer to the MachineOperand rather than an index.
770 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
771 const TargetRegisterInfo *TRI = NULL) {
772 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
773 return (Idx == -1) ? NULL : &getOperand(Idx);
774 }
776 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
777 /// the specified register or -1 if it is not found. If isDead is true, defs
778 /// that are not dead are skipped. If Overlap is true, then it also looks for
779 /// defs that merely overlap the specified register. If TargetRegisterInfo is
780 /// non-null, then it also checks if there is a def of a super-register.
781 /// This may also return a register mask operand when Overlap is true.
782 int findRegisterDefOperandIdx(unsigned Reg,
783 bool isDead = false, bool Overlap = false,
784 const TargetRegisterInfo *TRI = NULL) const;
786 /// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns
787 /// a pointer to the MachineOperand rather than an index.
788 MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
789 const TargetRegisterInfo *TRI = NULL) {
790 int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
791 return (Idx == -1) ? NULL : &getOperand(Idx);
792 }
794 /// findFirstPredOperandIdx() - Find the index of the first operand in the
795 /// operand list that is used to represent the predicate. It returns -1 if
796 /// none is found.
797 int findFirstPredOperandIdx() const;
799 /// findInlineAsmFlagIdx() - Find the index of the flag word operand that
800 /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
801 /// getOperand(OpIdx) does not belong to an inline asm operand group.
802 ///
803 /// If GroupNo is not NULL, it will receive the number of the operand group
804 /// containing OpIdx.
805 ///
806 /// The flag operand is an immediate that can be decoded with methods like
807 /// InlineAsm::hasRegClassConstraint().
808 ///
809 int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = 0) const;
811 /// getRegClassConstraint - Compute the static register class constraint for
812 /// operand OpIdx. For normal instructions, this is derived from the
813 /// MCInstrDesc. For inline assembly it is derived from the flag words.
814 ///
815 /// Returns NULL if the static register classs constraint cannot be
816 /// determined.
817 ///
818 const TargetRegisterClass*
819 getRegClassConstraint(unsigned OpIdx,
820 const TargetInstrInfo *TII,
821 const TargetRegisterInfo *TRI) const;
823 /// tieOperands - Add a tie between the register operands at DefIdx and
824 /// UseIdx. The tie will cause the register allocator to ensure that the two
825 /// operands are assigned the same physical register.
826 ///
827 /// Tied operands are managed automatically for explicit operands in the
828 /// MCInstrDesc. This method is for exceptional cases like inline asm.
829 void tieOperands(unsigned DefIdx, unsigned UseIdx);
831 /// findTiedOperandIdx - Given the index of a tied register operand, find the
832 /// operand it is tied to. Defs are tied to uses and vice versa. Returns the
833 /// index of the tied operand which must exist.
834 unsigned findTiedOperandIdx(unsigned OpIdx) const;
836 /// isRegTiedToUseOperand - Given the index of a register def operand,
837 /// check if the register def is tied to a source operand, due to either
838 /// two-address elimination or inline assembly constraints. Returns the
839 /// first tied use operand index by reference if UseOpIdx is not null.
840 bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx = 0) const {
841 const MachineOperand &MO = getOperand(DefOpIdx);
842 if (!MO.isReg() || !MO.isDef() || !MO.isTied())
843 return false;
844 if (UseOpIdx)
845 *UseOpIdx = findTiedOperandIdx(DefOpIdx);
846 return true;
847 }
849 /// isRegTiedToDefOperand - Return true if the use operand of the specified
850 /// index is tied to an def operand. It also returns the def operand index by
851 /// reference if DefOpIdx is not null.
852 bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx = 0) const {
853 const MachineOperand &MO = getOperand(UseOpIdx);
854 if (!MO.isReg() || !MO.isUse() || !MO.isTied())
855 return false;
856 if (DefOpIdx)
857 *DefOpIdx = findTiedOperandIdx(UseOpIdx);
858 return true;
859 }
861 /// clearKillInfo - Clears kill flags on all operands.
862 ///
863 void clearKillInfo();
865 /// substituteRegister - Replace all occurrences of FromReg with ToReg:SubIdx,
866 /// properly composing subreg indices where necessary.
867 void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
868 const TargetRegisterInfo &RegInfo);
870 /// addRegisterKilled - We have determined MI kills a register. Look for the
871 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
872 /// add a implicit operand if it's not found. Returns true if the operand
873 /// exists / is added.
874 bool addRegisterKilled(unsigned IncomingReg,
875 const TargetRegisterInfo *RegInfo,
876 bool AddIfNotFound = false);
878 /// clearRegisterKills - Clear all kill flags affecting Reg. If RegInfo is
879 /// provided, this includes super-register kills.
880 void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo);
882 /// addRegisterDead - We have determined MI defined a register without a use.
883 /// Look for the operand that defines it and mark it as IsDead. If
884 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
885 /// true if the operand exists / is added.
886 bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo,
887 bool AddIfNotFound = false);
889 /// addRegisterDefined - We have determined MI defines a register. Make sure
890 /// there is an operand defining Reg.
891 void addRegisterDefined(unsigned IncomingReg,
892 const TargetRegisterInfo *RegInfo = 0);
894 /// setPhysRegsDeadExcept - Mark every physreg used by this instruction as
895 /// dead except those in the UsedRegs list.
896 ///
897 /// On instructions with register mask operands, also add implicit-def
898 /// operands for all registers in UsedRegs.
899 void setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
900 const TargetRegisterInfo &TRI);
902 /// isSafeToMove - Return true if it is safe to move this instruction. If
903 /// SawStore is set to true, it means that there is a store (or call) between
904 /// the instruction's location and its intended destination.
905 bool isSafeToMove(const TargetInstrInfo *TII, AliasAnalysis *AA,
906 bool &SawStore) const;
908 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
909 /// instruction which defined the specified register instead of copying it.
910 bool isSafeToReMat(const TargetInstrInfo *TII, AliasAnalysis *AA,
911 unsigned DstReg) const;
913 /// hasOrderedMemoryRef - Return true if this instruction may have an ordered
914 /// or volatile memory reference, or if the information describing the memory
915 /// reference is not available. Return false if it is known to have no
916 /// ordered or volatile memory references.
917 bool hasOrderedMemoryRef() const;
919 /// isInvariantLoad - Return true if this instruction is loading from a
920 /// location whose value is invariant across the function. For example,
921 /// loading a value from the constant pool or from the argument area of
922 /// a function if it does not change. This should only return true of *all*
923 /// loads the instruction does are invariant (if it does multiple loads).
924 bool isInvariantLoad(AliasAnalysis *AA) const;
926 /// isConstantValuePHI - If the specified instruction is a PHI that always
927 /// merges together the same virtual register, return the register, otherwise
928 /// return 0.
929 unsigned isConstantValuePHI() const;
931 /// hasUnmodeledSideEffects - Return true if this instruction has side
932 /// effects that are not modeled by mayLoad / mayStore, etc.
933 /// For all instructions, the property is encoded in MCInstrDesc::Flags
934 /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
935 /// INLINEASM instruction, in which case the side effect property is encoded
936 /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
937 ///
938 bool hasUnmodeledSideEffects() const;
940 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
941 ///
942 bool allDefsAreDead() const;
944 /// copyImplicitOps - Copy implicit register operands from specified
945 /// instruction to this instruction.
946 void copyImplicitOps(MachineFunction &MF, const MachineInstr *MI);
948 //
949 // Debugging support
950 //
951 void print(raw_ostream &OS, const TargetMachine *TM = 0,
952 bool SkipOpers = false) const;
953 void dump() const;
955 //===--------------------------------------------------------------------===//
956 // Accessors used to build up machine instructions.
958 /// Add the specified operand to the instruction. If it is an implicit
959 /// operand, it is added to the end of the operand list. If it is an
960 /// explicit operand it is added at the end of the explicit operand list
961 /// (before the first implicit operand).
962 ///
963 /// MF must be the machine function that was used to allocate this
964 /// instruction.
965 ///
966 /// MachineInstrBuilder provides a more convenient interface for creating
967 /// instructions and adding operands.
968 void addOperand(MachineFunction &MF, const MachineOperand &Op);
970 /// Add an operand without providing an MF reference. This only works for
971 /// instructions that are inserted in a basic block.
972 ///
973 /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be
974 /// preferred.
975 void addOperand(const MachineOperand &Op);
977 /// setDesc - Replace the instruction descriptor (thus opcode) of
978 /// the current instruction with a new one.
979 ///
980 void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
982 /// setDebugLoc - Replace current source information with new such.
983 /// Avoid using this, the constructor argument is preferable.
984 ///
985 void setDebugLoc(const DebugLoc dl) { debugLoc = dl; }
987 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
988 /// fewer operand than it started with.
989 ///
990 void RemoveOperand(unsigned i);
992 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
993 /// This function should be used only occasionally. The setMemRefs function
994 /// is the primary method for setting up a MachineInstr's MemRefs list.
995 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
997 /// setMemRefs - Assign this MachineInstr's memory reference descriptor
998 /// list. This does not transfer ownership.
999 void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
1000 MemRefs = NewMemRefs;
1001 NumMemRefs = uint8_t(NewMemRefsEnd - NewMemRefs);
1002 assert(NumMemRefs == NewMemRefsEnd - NewMemRefs && "Too many memrefs");
1003 }
1005 private:
1006 /// getRegInfo - If this instruction is embedded into a MachineFunction,
1007 /// return the MachineRegisterInfo object for the current function, otherwise
1008 /// return null.
1009 MachineRegisterInfo *getRegInfo();
1011 /// untieRegOperand - Break any tie involving OpIdx.
1012 void untieRegOperand(unsigned OpIdx) {
1013 MachineOperand &MO = getOperand(OpIdx);
1014 if (MO.isReg() && MO.isTied()) {
1015 getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
1016 MO.TiedTo = 0;
1017 }
1018 }
1020 /// addImplicitDefUseOperands - Add all implicit def and use operands to
1021 /// this instruction.
1022 void addImplicitDefUseOperands(MachineFunction &MF);
1024 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
1025 /// this instruction from their respective use lists. This requires that the
1026 /// operands already be on their use lists.
1027 void RemoveRegOperandsFromUseLists(MachineRegisterInfo&);
1029 /// AddRegOperandsToUseLists - Add all of the register operands in
1030 /// this instruction from their respective use lists. This requires that the
1031 /// operands not be on their use lists yet.
1032 void AddRegOperandsToUseLists(MachineRegisterInfo&);
1034 /// hasPropertyInBundle - Slow path for hasProperty when we're dealing with a
1035 /// bundle.
1036 bool hasPropertyInBundle(unsigned Mask, QueryType Type) const;
1037 };
1039 /// MachineInstrExpressionTrait - Special DenseMapInfo traits to compare
1040 /// MachineInstr* by *value* of the instruction rather than by pointer value.
1041 /// The hashing and equality testing functions ignore definitions so this is
1042 /// useful for CSE, etc.
1043 struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
1044 static inline MachineInstr *getEmptyKey() {
1045 return 0;
1046 }
1048 static inline MachineInstr *getTombstoneKey() {
1049 return reinterpret_cast<MachineInstr*>(-1);
1050 }
1052 static unsigned getHashValue(const MachineInstr* const &MI);
1054 static bool isEqual(const MachineInstr* const &LHS,
1055 const MachineInstr* const &RHS) {
1056 if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
1057 LHS == getEmptyKey() || LHS == getTombstoneKey())
1058 return LHS == RHS;
1059 return LHS->isIdenticalTo(RHS, MachineInstr::IgnoreVRegDefs);
1060 }
1061 };
1063 //===----------------------------------------------------------------------===//
1064 // Debugging Support
1066 inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
1067 MI.print(OS);
1068 return OS;
1069 }
1071 } // End llvm namespace
1073 #endif