cae3e916cd4642ce1185c4358281f18fff138bc6
1 //===-- llvm/CodeGen/AsmPrinter/DbgValueHistoryCalculator.cpp -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
10 #include "DbgValueHistoryCalculator.h"
11 #include "llvm/CodeGen/MachineBasicBlock.h"
12 #include "llvm/CodeGen/MachineFunction.h"
13 #include "llvm/Support/Debug.h"
14 #include "llvm/Target/TargetRegisterInfo.h"
16 #define DEBUG_TYPE "dwarfdebug"
18 namespace llvm {
20 // Return true if debug value, encoded by DBG_VALUE instruction, is in a
21 // defined reg.
22 static bool isDbgValueInDefinedReg(const MachineInstr *MI) {
23 assert(MI->isDebugValue() && "Invalid DBG_VALUE machine instruction!");
24 return MI->getNumOperands() == 3 && MI->getOperand(0).isReg() &&
25 MI->getOperand(0).getReg() &&
26 (MI->getOperand(1).isImm() ||
27 (MI->getOperand(1).isReg() && MI->getOperand(1).getReg() == 0U));
28 }
30 void calculateDbgValueHistory(const MachineFunction *MF,
31 const TargetRegisterInfo *TRI,
32 DbgValueHistoryMap &Result) {
33 // LiveUserVar - Map physreg numbers to the MDNode they contain.
34 std::vector<const MDNode *> LiveUserVar(TRI->getNumRegs());
36 for (MachineFunction::const_iterator I = MF->begin(), E = MF->end(); I != E;
37 ++I) {
38 bool AtBlockEntry = true;
39 for (MachineBasicBlock::const_iterator II = I->begin(), IE = I->end();
40 II != IE; ++II) {
41 const MachineInstr *MI = II;
43 if (MI->isDebugValue()) {
44 assert(MI->getNumOperands() > 1 && "Invalid machine instruction!");
46 // Keep track of user variables.
47 const MDNode *Var = MI->getDebugVariable();
49 // Variable is in a register, we need to check for clobbers.
50 if (isDbgValueInDefinedReg(MI))
51 LiveUserVar[MI->getOperand(0).getReg()] = Var;
53 // Check the history of this variable.
54 SmallVectorImpl<const MachineInstr *> &History = Result[Var];
55 if (!History.empty()) {
56 // We have seen this variable before. Try to coalesce DBG_VALUEs.
57 const MachineInstr *Prev = History.back();
58 if (Prev->isDebugValue()) {
59 // Coalesce identical entries at the end of History.
60 if (History.size() >= 2 &&
61 Prev->isIdenticalTo(History[History.size() - 2])) {
62 DEBUG(dbgs() << "Coalescing identical DBG_VALUE entries:\n"
63 << "\t" << *Prev << "\t"
64 << *History[History.size() - 2] << "\n");
65 History.pop_back();
66 }
68 // Terminate old register assignments that don't reach MI;
69 MachineFunction::const_iterator PrevMBB = Prev->getParent();
70 if (PrevMBB != I && (!AtBlockEntry || std::next(PrevMBB) != I) &&
71 isDbgValueInDefinedReg(Prev)) {
72 // Previous register assignment needs to terminate at the end of
73 // its basic block.
74 MachineBasicBlock::const_iterator LastMI =
75 PrevMBB->getLastNonDebugInstr();
76 if (LastMI == PrevMBB->end()) {
77 // Drop DBG_VALUE for empty range.
78 DEBUG(dbgs() << "Dropping DBG_VALUE for empty range:\n"
79 << "\t" << *Prev << "\n");
80 History.pop_back();
81 } else if (std::next(PrevMBB) != PrevMBB->getParent()->end())
82 // Terminate after LastMI.
83 History.push_back(LastMI);
84 }
85 }
86 }
87 History.push_back(MI);
88 } else {
89 // Not a DBG_VALUE instruction.
90 if (!MI->isPosition())
91 AtBlockEntry = false;
93 // Check if the instruction clobbers any registers with debug vars.
94 for (const MachineOperand &MO : MI->operands()) {
95 if (!MO.isReg() || !MO.isDef() || !MO.getReg())
96 continue;
97 for (MCRegAliasIterator AI(MO.getReg(), TRI, true); AI.isValid();
98 ++AI) {
99 unsigned Reg = *AI;
100 const MDNode *Var = LiveUserVar[Reg];
101 if (!Var)
102 continue;
103 // Reg is now clobbered.
104 LiveUserVar[Reg] = nullptr;
106 // Was MD last defined by a DBG_VALUE referring to Reg?
107 auto HistI = Result.find(Var);
108 if (HistI == Result.end())
109 continue;
110 SmallVectorImpl<const MachineInstr *> &History = HistI->second;
111 if (History.empty())
112 continue;
113 const MachineInstr *Prev = History.back();
114 // Sanity-check: Register assignments are terminated at the end of
115 // their block.
116 if (!Prev->isDebugValue() || Prev->getParent() != MI->getParent())
117 continue;
118 // Is the variable still in Reg?
119 if (!isDbgValueInDefinedReg(Prev) ||
120 Prev->getOperand(0).getReg() != Reg)
121 continue;
122 // Var is clobbered. Make sure the next instruction gets a label.
123 History.push_back(MI);
124 }
125 }
126 }
127 }
128 }
130 // Make sure the final register assignments are terminated.
131 for (auto &I : Result) {
132 SmallVectorImpl<const MachineInstr *> &History = I.second;
133 if (History.empty())
134 continue;
136 const MachineInstr *Prev = History.back();
137 if (Prev->isDebugValue() && isDbgValueInDefinedReg(Prev)) {
138 const MachineBasicBlock *PrevMBB = Prev->getParent();
139 MachineBasicBlock::const_iterator LastMI =
140 PrevMBB->getLastNonDebugInstr();
141 if (LastMI == PrevMBB->end())
142 // Drop DBG_VALUE for empty range.
143 History.pop_back();
144 else if (PrevMBB != &PrevMBB->getParent()->back()) {
145 // Terminate after LastMI.
146 History.push_back(LastMI);
147 }
148 }
149 }
150 }
152 }