26c2a20dea19f7c51bc77c05ce72895bd82e0d56
1 //===-- llvm/CodeGen/DwarfExpression.cpp - Dwarf Debug Framework ----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains support for writing dwarf debug info into asm files.
11 //
12 //===----------------------------------------------------------------------===//
14 #include "DwarfExpression.h"
16 #include "DwarfDebug.h"
17 #include "llvm/ADT/SmallBitVector.h"
18 #include "llvm/CodeGen/AsmPrinter.h"
19 #include "llvm/Support/Dwarf.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetRegisterInfo.h"
22 #include "llvm/Target/TargetSubtargetInfo.h"
24 using namespace llvm;
26 const TargetRegisterInfo *DwarfExpression::getTRI() const {
27 return AP.TM.getSubtargetImpl()->getRegisterInfo();
28 }
30 unsigned DwarfExpression::getDwarfVersion() const {
31 return AP.getDwarfDebug()->getDwarfVersion();
32 }
34 void DwarfExpression::AddReg(int DwarfReg, const char *Comment) {
35 assert(DwarfReg >= 0 && "invalid negative dwarf register number");
36 if (DwarfReg < 32) {
37 EmitOp(dwarf::DW_OP_reg0 + DwarfReg, Comment);
38 } else {
39 EmitOp(dwarf::DW_OP_regx, Comment);
40 EmitUnsigned(DwarfReg);
41 }
42 }
44 void DwarfExpression::AddRegIndirect(int DwarfReg, int Offset, bool Deref) {
45 assert(DwarfReg >= 0 && "invalid negative dwarf register number");
46 if (DwarfReg < 32) {
47 EmitOp(dwarf::DW_OP_breg0 + DwarfReg);
48 } else {
49 EmitOp(dwarf::DW_OP_bregx);
50 EmitUnsigned(DwarfReg);
51 }
52 EmitSigned(Offset);
53 if (Deref)
54 EmitOp(dwarf::DW_OP_deref);
55 }
57 void DwarfExpression::AddOpPiece(unsigned SizeInBits, unsigned OffsetInBits) {
58 assert(SizeInBits > 0 && "piece has size zero");
59 const unsigned SizeOfByte = 8;
60 if (OffsetInBits > 0 || SizeInBits % SizeOfByte) {
61 EmitOp(dwarf::DW_OP_bit_piece);
62 EmitUnsigned(SizeInBits);
63 EmitUnsigned(OffsetInBits);
64 } else {
65 EmitOp(dwarf::DW_OP_piece);
66 unsigned ByteSize = SizeInBits / SizeOfByte;
67 EmitUnsigned(ByteSize);
68 }
69 }
71 void DwarfExpression::AddShr(unsigned ShiftBy) {
72 EmitOp(dwarf::DW_OP_constu);
73 EmitUnsigned(ShiftBy);
74 EmitOp(dwarf::DW_OP_shr);
75 }
77 bool DwarfExpression::AddMachineRegIndirect(unsigned MachineReg, int Offset) {
78 int DwarfReg = getTRI()->getDwarfRegNum(MachineReg, false);
79 if (DwarfReg < 0)
80 return false;
82 if (isFrameRegister(MachineReg)) {
83 // If variable offset is based in frame register then use fbreg.
84 EmitOp(dwarf::DW_OP_fbreg);
85 EmitSigned(Offset);
86 } else {
87 AddRegIndirect(DwarfReg, Offset);
88 }
89 return true;
90 }
92 void DwarfExpression::AddMachineRegPiece(unsigned MachineReg,
93 unsigned PieceSizeInBits,
94 unsigned PieceOffsetInBits) {
95 const TargetRegisterInfo *TRI = getTRI();
96 if (!TRI->isPhysicalRegister(MachineReg)) {
97 // FIXME: We have no reasonable way of handling errors in here.
98 EmitOp(dwarf::DW_OP_nop, "nop (could not find a dwarf register number)");
99 return;
100 }
102 int Reg = TRI->getDwarfRegNum(MachineReg, false);
104 // If this is a valid register number, emit it.
105 if (Reg >= 0) {
106 AddReg(Reg);
107 if (PieceSizeInBits)
108 AddOpPiece(PieceSizeInBits, PieceOffsetInBits);
109 return;
110 }
112 // Walk up the super-register chain until we find a valid number.
113 // For example, EAX on x86_64 is a 32-bit piece of RAX with offset 0.
114 for (MCSuperRegIterator SR(MachineReg, TRI); SR.isValid(); ++SR) {
115 Reg = TRI->getDwarfRegNum(*SR, false);
116 if (Reg >= 0) {
117 unsigned Idx = TRI->getSubRegIndex(*SR, MachineReg);
118 unsigned Size = TRI->getSubRegIdxSize(Idx);
119 unsigned RegOffset = TRI->getSubRegIdxOffset(Idx);
120 AddReg(Reg, "super-register");
121 if (PieceOffsetInBits == RegOffset) {
122 AddOpPiece(Size, RegOffset);
123 } else {
124 // If this is part of a variable in a sub-register at a
125 // non-zero offset, we need to manually shift the value into
126 // place, since the DW_OP_piece describes the part of the
127 // variable, not the position of the subregister.
128 if (RegOffset)
129 AddShr(RegOffset);
130 AddOpPiece(Size, PieceOffsetInBits);
131 }
132 return;
133 }
134 }
136 // Otherwise, attempt to find a covering set of sub-register numbers.
137 // For example, Q0 on ARM is a composition of D0+D1.
138 //
139 // Keep track of the current position so we can emit the more
140 // efficient DW_OP_piece.
141 unsigned CurPos = PieceOffsetInBits;
142 // The size of the register in bits, assuming 8 bits per byte.
143 unsigned RegSize = TRI->getMinimalPhysRegClass(MachineReg)->getSize() * 8;
144 // Keep track of the bits in the register we already emitted, so we
145 // can avoid emitting redundant aliasing subregs.
146 SmallBitVector Coverage(RegSize, false);
147 for (MCSubRegIterator SR(MachineReg, TRI); SR.isValid(); ++SR) {
148 unsigned Idx = TRI->getSubRegIndex(MachineReg, *SR);
149 unsigned Size = TRI->getSubRegIdxSize(Idx);
150 unsigned Offset = TRI->getSubRegIdxOffset(Idx);
151 Reg = TRI->getDwarfRegNum(*SR, false);
153 // Intersection between the bits we already emitted and the bits
154 // covered by this subregister.
155 SmallBitVector Intersection(RegSize, false);
156 Intersection.set(Offset, Offset + Size);
157 Intersection ^= Coverage;
159 // If this sub-register has a DWARF number and we haven't covered
160 // its range, emit a DWARF piece for it.
161 if (Reg >= 0 && Intersection.any()) {
162 AddReg(Reg, "sub-register");
163 AddOpPiece(Size, Offset == CurPos ? 0 : Offset);
164 CurPos = Offset + Size;
166 // Mark it as emitted.
167 Coverage.set(Offset, Offset + Size);
168 }
169 }
171 if (CurPos == PieceOffsetInBits)
172 // FIXME: We have no reasonable way of handling errors in here.
173 EmitOp(dwarf::DW_OP_nop, "nop (could not find a dwarf register number)");
174 }
176 void DwarfExpression::AddSignedConstant(int Value) {
177 EmitOp(dwarf::DW_OP_consts);
178 EmitSigned(Value);
179 // The proper way to describe a constant value is
180 // DW_OP_constu <const>, DW_OP_stack_value.
181 // Unfortunately, DW_OP_stack_value was not available until DWARF-4,
182 // so we will continue to generate DW_OP_constu <const> for DWARF-2
183 // and DWARF-3. Technically, this is incorrect since DW_OP_const <const>
184 // actually describes a value at a constant addess, not a constant value.
185 // However, in the past there was no better way to describe a constant
186 // value, so the producers and consumers started to rely on heuristics
187 // to disambiguate the value vs. location status of the expression.
188 // See PR21176 for more details.
189 if (getDwarfVersion() >= 4)
190 EmitOp(dwarf::DW_OP_stack_value);
191 }
193 void DwarfExpression::AddUnsignedConstant(unsigned Value) {
194 EmitOp(dwarf::DW_OP_constu);
195 EmitUnsigned(Value);
196 // cf. comment in DwarfExpression::AddSignedConstant().
197 if (getDwarfVersion() >= 4)
198 EmitOp(dwarf::DW_OP_stack_value);
199 }
201 static unsigned getOffsetOrZero(unsigned OffsetInBits,
202 unsigned PieceOffsetInBits) {
203 if (OffsetInBits == PieceOffsetInBits)
204 return 0;
205 assert(OffsetInBits >= PieceOffsetInBits && "overlapping pieces");
206 return OffsetInBits;
207 }
209 void DwarfExpression::AddMachineRegExpression(DIExpression Expr,
210 unsigned MachineReg,
211 unsigned PieceOffsetInBits) {
212 unsigned N = Expr.getNumElements();
213 unsigned I = 0;
214 // Pattern-match combinations for which more efficient representations exist
215 // first.
216 if (N >= 3 && Expr.getElement(0) == dwarf::DW_OP_piece) {
217 unsigned SizeOfByte = 8;
218 unsigned OffsetInBits = Expr.getElement(1) * SizeOfByte;
219 unsigned SizeInBits = Expr.getElement(2) * SizeOfByte;
220 AddMachineRegPiece(MachineReg, SizeInBits,
221 getOffsetOrZero(OffsetInBits, PieceOffsetInBits));
222 I = 3;
223 } else if (N >= 3 && Expr.getElement(0) == dwarf::DW_OP_plus &&
224 Expr.getElement(2) == dwarf::DW_OP_deref) {
225 // [DW_OP_reg,Offset,DW_OP_plus,DW_OP_deref] --> [DW_OP_breg,Offset].
226 unsigned Offset = Expr.getElement(1);
227 AddMachineRegIndirect(MachineReg, Offset);
228 I = 3;
229 } else if (N >= 1 && Expr.getElement(0) == dwarf::DW_OP_deref) {
230 // [DW_OP_reg,DW_OP_deref] --> [DW_OP_breg].
231 AddMachineRegIndirect(MachineReg);
232 I = 1;
233 } else
234 AddMachineRegPiece(MachineReg);
236 // Emit remaining elements of the expression.
237 AddExpression(Expr, I);
238 }
240 void DwarfExpression::AddExpression(DIExpression Expr, unsigned I,
241 unsigned PieceOffsetInBits) {
242 unsigned N = Expr.getNumElements();
243 for (; I < N; ++I) {
244 switch (Expr.getElement(I)) {
245 case dwarf::DW_OP_piece: {
246 unsigned SizeOfByte = 8;
247 unsigned OffsetInBits = Expr.getElement(++I) * SizeOfByte;
248 unsigned SizeInBits = Expr.getElement(++I) * SizeOfByte;
249 AddOpPiece(SizeInBits, getOffsetOrZero(OffsetInBits, PieceOffsetInBits));
250 break;
251 }
252 case dwarf::DW_OP_plus:
253 EmitOp(dwarf::DW_OP_plus_uconst);
254 EmitUnsigned(Expr.getElement(++I));
255 break;
256 case dwarf::DW_OP_deref:
257 EmitOp(dwarf::DW_OP_deref);
258 break;
259 default:
260 llvm_unreachable("unhandled opcode found in DIExpression");
261 }
262 }
263 }