1 //===-- llvm/CodeGen/DwarfExpression.cpp - Dwarf Debug Framework ----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains support for writing dwarf debug info into asm files.
11 //
12 //===----------------------------------------------------------------------===//
14 #include "DwarfExpression.h"
15 #include "llvm/ADT/SmallBitVector.h"
16 #include "llvm/Support/Dwarf.h"
17 #include "llvm/Target/TargetMachine.h"
18 #include "llvm/Target/TargetRegisterInfo.h"
19 #include "llvm/Target/TargetSubtargetInfo.h"
22 using namespace llvm;
24 void DwarfExpression::AddReg(int DwarfReg, const char* Comment) {
25 assert(DwarfReg >= 0 && "invalid negative dwarf register number");
26 if (DwarfReg < 32) {
27 EmitOp(dwarf::DW_OP_reg0 + DwarfReg, Comment);
28 } else {
29 EmitOp(dwarf::DW_OP_regx, Comment);
30 EmitUnsigned(DwarfReg);
31 }
32 }
34 void DwarfExpression::AddRegIndirect(int DwarfReg, int Offset, bool Deref) {
35 assert(DwarfReg >= 0 && "invalid negative dwarf register number");
36 if (DwarfReg < 32) {
37 EmitOp(dwarf::DW_OP_breg0 + DwarfReg);
38 } else {
39 EmitOp(dwarf::DW_OP_bregx);
40 EmitUnsigned(DwarfReg);
41 }
42 EmitSigned(Offset);
43 if (Deref)
44 EmitOp(dwarf::DW_OP_deref);
45 }
47 void DwarfExpression::AddOpPiece(unsigned SizeInBits,
48 unsigned OffsetInBits) {
49 assert(SizeInBits > 0 && "piece has size zero");
50 const unsigned SizeOfByte = 8;
51 if (OffsetInBits > 0 || SizeInBits % SizeOfByte) {
52 EmitOp(dwarf::DW_OP_bit_piece);
53 EmitUnsigned(SizeInBits);
54 EmitUnsigned(OffsetInBits);
55 } else {
56 EmitOp(dwarf::DW_OP_piece);
57 unsigned ByteSize = SizeInBits / SizeOfByte;
58 EmitUnsigned(ByteSize);
59 }
60 }
62 void DwarfExpression::AddShr(unsigned ShiftBy) {
63 EmitOp(dwarf::DW_OP_constu);
64 EmitUnsigned(ShiftBy);
65 EmitOp(dwarf::DW_OP_shr);
66 }
68 bool DwarfExpression::AddMachineRegIndirect(unsigned MachineReg, int Offset) {
69 const TargetRegisterInfo *TRI = TM.getSubtargetImpl()->getRegisterInfo();
70 int DwarfReg = TRI->getDwarfRegNum(MachineReg, false);
71 if (DwarfReg < 0)
72 return false;
74 if (MachineReg == getFrameRegister()) {
75 // If variable offset is based in frame register then use fbreg.
76 EmitOp(dwarf::DW_OP_fbreg);
77 EmitSigned(Offset);
78 } else {
79 AddRegIndirect(DwarfReg, Offset);
80 }
81 return true;
82 }
84 void DwarfExpression::AddMachineRegPiece(unsigned MachineReg,
85 unsigned PieceSizeInBits,
86 unsigned PieceOffsetInBits) {
87 const TargetRegisterInfo *TRI = TM.getSubtargetImpl()->getRegisterInfo();
88 int Reg = TRI->getDwarfRegNum(MachineReg, false);
90 // If this is a valid register number, emit it.
91 if (Reg >= 0) {
92 AddReg(Reg);
93 AddOpPiece(PieceSizeInBits, PieceOffsetInBits);
94 return;
95 }
97 // Walk up the super-register chain until we find a valid number.
98 // For example, EAX on x86_64 is a 32-bit piece of RAX with offset 0.
99 for (MCSuperRegIterator SR(MachineReg, TRI); SR.isValid(); ++SR) {
100 Reg = TRI->getDwarfRegNum(*SR, false);
101 if (Reg >= 0) {
102 unsigned Idx = TRI->getSubRegIndex(*SR, MachineReg);
103 unsigned Size = TRI->getSubRegIdxSize(Idx);
104 unsigned RegOffset = TRI->getSubRegIdxOffset(Idx);
105 AddReg(Reg, "super-register");
106 if (PieceOffsetInBits == RegOffset) {
107 AddOpPiece(Size, RegOffset);
108 } else {
109 // If this is part of a variable in a sub-register at a
110 // non-zero offset, we need to manually shift the value into
111 // place, since the DW_OP_piece describes the part of the
112 // variable, not the position of the subregister.
113 if (RegOffset)
114 AddShr(RegOffset);
115 AddOpPiece(Size, PieceOffsetInBits);
116 }
117 return;
118 }
119 }
121 // Otherwise, attempt to find a covering set of sub-register numbers.
122 // For example, Q0 on ARM is a composition of D0+D1.
123 //
124 // Keep track of the current position so we can emit the more
125 // efficient DW_OP_piece.
126 unsigned CurPos = PieceOffsetInBits;
127 // The size of the register in bits, assuming 8 bits per byte.
128 unsigned RegSize = TRI->getMinimalPhysRegClass(MachineReg)->getSize() * 8;
129 // Keep track of the bits in the register we already emitted, so we
130 // can avoid emitting redundant aliasing subregs.
131 SmallBitVector Coverage(RegSize, false);
132 for (MCSubRegIterator SR(MachineReg, TRI); SR.isValid(); ++SR) {
133 unsigned Idx = TRI->getSubRegIndex(MachineReg, *SR);
134 unsigned Size = TRI->getSubRegIdxSize(Idx);
135 unsigned Offset = TRI->getSubRegIdxOffset(Idx);
136 Reg = TRI->getDwarfRegNum(*SR, false);
138 // Intersection between the bits we already emitted and the bits
139 // covered by this subregister.
140 SmallBitVector Intersection(RegSize, false);
141 Intersection.set(Offset, Offset + Size);
142 Intersection ^= Coverage;
144 // If this sub-register has a DWARF number and we haven't covered
145 // its range, emit a DWARF piece for it.
146 if (Reg >= 0 && Intersection.any()) {
147 AddReg(Reg, "sub-register");
148 AddOpPiece(Size, Offset == CurPos ? 0 : Offset);
149 CurPos = Offset + Size;
151 // Mark it as emitted.
152 Coverage.set(Offset, Offset + Size);
153 }
154 }
156 if (CurPos == PieceOffsetInBits)
157 // FIXME: We have no reasonable way of handling errors in here.
158 EmitOp(dwarf::DW_OP_nop, "nop (could not find a dwarf register number)");
159 }