1 //===-- llvm/CodeGen/DwarfExpression.cpp - Dwarf Debug Framework ----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains support for writing dwarf debug info into asm files.
11 //
12 //===----------------------------------------------------------------------===//
14 #include "DwarfExpression.h"
15 #include "llvm/ADT/SmallBitVector.h"
16 #include "llvm/Support/Dwarf.h"
17 #include "llvm/Target/TargetMachine.h"
18 #include "llvm/Target/TargetRegisterInfo.h"
19 #include "llvm/Target/TargetSubtargetInfo.h"
22 using namespace llvm;
24 void DwarfExpression::AddReg(int DwarfReg, const char* Comment) {
25 assert(DwarfReg >= 0 && "invalid negative dwarf register number");
26 if (DwarfReg < 32) {
27 EmitOp(dwarf::DW_OP_reg0 + DwarfReg, Comment);
28 } else {
29 EmitOp(dwarf::DW_OP_regx, Comment);
30 EmitUnsigned(DwarfReg);
31 }
32 }
34 void DwarfExpression::AddRegIndirect(int DwarfReg, int Offset, bool Deref) {
35 assert(DwarfReg >= 0 && "invalid negative dwarf register number");
36 if (DwarfReg < 32) {
37 EmitOp(dwarf::DW_OP_breg0 + DwarfReg);
38 } else {
39 EmitOp(dwarf::DW_OP_bregx);
40 EmitUnsigned(DwarfReg);
41 }
42 EmitSigned(Offset);
43 if (Deref)
44 EmitOp(dwarf::DW_OP_deref);
45 }
47 void DwarfExpression::AddOpPiece(unsigned SizeInBits,
48 unsigned OffsetInBits) {
49 assert(SizeInBits > 0 && "piece has size zero");
50 const unsigned SizeOfByte = 8;
51 if (OffsetInBits > 0 || SizeInBits % SizeOfByte) {
52 EmitOp(dwarf::DW_OP_bit_piece);
53 EmitUnsigned(SizeInBits);
54 EmitUnsigned(OffsetInBits);
55 } else {
56 EmitOp(dwarf::DW_OP_piece);
57 unsigned ByteSize = SizeInBits / SizeOfByte;
58 EmitUnsigned(ByteSize);
59 }
60 }
62 void DwarfExpression::AddShr(unsigned ShiftBy) {
63 EmitOp(dwarf::DW_OP_constu);
64 EmitUnsigned(ShiftBy);
65 EmitOp(dwarf::DW_OP_shr);
66 }
68 void DwarfExpression::AddMachineRegPiece(unsigned MachineReg,
69 unsigned PieceSizeInBits,
70 unsigned PieceOffsetInBits) {
71 const TargetRegisterInfo *TRI = TM.getSubtargetImpl()->getRegisterInfo();
72 int Reg = TRI->getDwarfRegNum(MachineReg, false);
74 // If this is a valid register number, emit it.
75 if (Reg >= 0) {
76 AddReg(Reg);
77 AddOpPiece(PieceSizeInBits, PieceOffsetInBits);
78 return;
79 }
81 // Walk up the super-register chain until we find a valid number.
82 // For example, EAX on x86_64 is a 32-bit piece of RAX with offset 0.
83 for (MCSuperRegIterator SR(MachineReg, TRI); SR.isValid(); ++SR) {
84 Reg = TRI->getDwarfRegNum(*SR, false);
85 if (Reg >= 0) {
86 unsigned Idx = TRI->getSubRegIndex(*SR, MachineReg);
87 unsigned Size = TRI->getSubRegIdxSize(Idx);
88 unsigned RegOffset = TRI->getSubRegIdxOffset(Idx);
89 AddReg(Reg, "super-register");
90 if (PieceOffsetInBits == RegOffset) {
91 AddOpPiece(Size, RegOffset);
92 } else {
93 // If this is part of a variable in a sub-register at a
94 // non-zero offset, we need to manually shift the value into
95 // place, since the DW_OP_piece describes the part of the
96 // variable, not the position of the subregister.
97 if (RegOffset)
98 AddShr(RegOffset);
99 AddOpPiece(Size, PieceOffsetInBits);
100 }
101 return;
102 }
103 }
105 // Otherwise, attempt to find a covering set of sub-register numbers.
106 // For example, Q0 on ARM is a composition of D0+D1.
107 //
108 // Keep track of the current position so we can emit the more
109 // efficient DW_OP_piece.
110 unsigned CurPos = PieceOffsetInBits;
111 // The size of the register in bits, assuming 8 bits per byte.
112 unsigned RegSize = TRI->getMinimalPhysRegClass(MachineReg)->getSize() * 8;
113 // Keep track of the bits in the register we already emitted, so we
114 // can avoid emitting redundant aliasing subregs.
115 SmallBitVector Coverage(RegSize, false);
116 for (MCSubRegIterator SR(MachineReg, TRI); SR.isValid(); ++SR) {
117 unsigned Idx = TRI->getSubRegIndex(MachineReg, *SR);
118 unsigned Size = TRI->getSubRegIdxSize(Idx);
119 unsigned Offset = TRI->getSubRegIdxOffset(Idx);
120 Reg = TRI->getDwarfRegNum(*SR, false);
122 // Intersection between the bits we already emitted and the bits
123 // covered by this subregister.
124 SmallBitVector Intersection(RegSize, false);
125 Intersection.set(Offset, Offset + Size);
126 Intersection ^= Coverage;
128 // If this sub-register has a DWARF number and we haven't covered
129 // its range, emit a DWARF piece for it.
130 if (Reg >= 0 && Intersection.any()) {
131 AddReg(Reg, "sub-register");
132 AddOpPiece(Size, Offset == CurPos ? 0 : Offset);
133 CurPos = Offset + Size;
135 // Mark it as emitted.
136 Coverage.set(Offset, Offset + Size);
137 }
138 }
140 if (CurPos == PieceOffsetInBits)
141 // FIXME: We have no reasonable way of handling errors in here.
142 EmitOp(dwarf::DW_OP_nop, "nop (could not find a dwarf register number)");
143 }