1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
12 //
13 // This pass is not a substitute for the LLVM IR instcombine pass. This pass is
14 // primarily intended to handle simplification opportunities that are implicit
15 // in the LLVM IR and exposed by the various codegen lowering phases.
16 //
17 //===----------------------------------------------------------------------===//
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/ADT/SmallBitVector.h"
21 #include "llvm/ADT/SmallPtrSet.h"
22 #include "llvm/ADT/SetVector.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/Analysis/AliasAnalysis.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/IR/DataLayout.h"
28 #include "llvm/IR/DerivedTypes.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/LLVMContext.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetLowering.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetSubtargetInfo.h"
40 #include <algorithm>
41 using namespace llvm;
43 #define DEBUG_TYPE "dagcombine"
45 STATISTIC(NodesCombined , "Number of dag nodes combined");
46 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
47 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
48 STATISTIC(OpsNarrowed , "Number of load/op/store narrowed");
49 STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int");
50 STATISTIC(SlicedLoads, "Number of load sliced");
52 namespace {
53 static cl::opt<bool>
54 CombinerAA("combiner-alias-analysis", cl::Hidden,
55 cl::desc("Enable DAG combiner alias-analysis heuristics"));
57 static cl::opt<bool>
58 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
59 cl::desc("Enable DAG combiner's use of IR alias analysis"));
61 static cl::opt<bool>
62 UseTBAA("combiner-use-tbaa", cl::Hidden, cl::init(true),
63 cl::desc("Enable DAG combiner's use of TBAA"));
65 #ifndef NDEBUG
66 static cl::opt<std::string>
67 CombinerAAOnlyFunc("combiner-aa-only-func", cl::Hidden,
68 cl::desc("Only use DAG-combiner alias analysis in this"
69 " function"));
70 #endif
72 /// Hidden option to stress test load slicing, i.e., when this option
73 /// is enabled, load slicing bypasses most of its profitability guards.
74 static cl::opt<bool>
75 StressLoadSlicing("combiner-stress-load-slicing", cl::Hidden,
76 cl::desc("Bypass the profitability model of load "
77 "slicing"),
78 cl::init(false));
80 static cl::opt<bool>
81 MaySplitLoadIndex("combiner-split-load-index", cl::Hidden, cl::init(true),
82 cl::desc("DAG combiner may split indexing from loads"));
84 //------------------------------ DAGCombiner ---------------------------------//
86 class DAGCombiner {
87 SelectionDAG &DAG;
88 const TargetLowering &TLI;
89 CombineLevel Level;
90 CodeGenOpt::Level OptLevel;
91 bool LegalOperations;
92 bool LegalTypes;
93 bool ForCodeSize;
95 /// \brief Worklist of all of the nodes that need to be simplified.
96 ///
97 /// This must behave as a stack -- new nodes to process are pushed onto the
98 /// back and when processing we pop off of the back.
99 ///
100 /// The worklist will not contain duplicates but may contain null entries
101 /// due to nodes being deleted from the underlying DAG.
102 SmallVector<SDNode *, 64> Worklist;
104 /// \brief Mapping from an SDNode to its position on the worklist.
105 ///
106 /// This is used to find and remove nodes from the worklist (by nulling
107 /// them) when they are deleted from the underlying DAG. It relies on
108 /// stable indices of nodes within the worklist.
109 DenseMap<SDNode *, unsigned> WorklistMap;
111 /// \brief Set of nodes which have been combined (at least once).
112 ///
113 /// This is used to allow us to reliably add any operands of a DAG node
114 /// which have not yet been combined to the worklist.
115 SmallPtrSet<SDNode *, 64> CombinedNodes;
117 // AA - Used for DAG load/store alias analysis.
118 AliasAnalysis &AA;
120 /// When an instruction is simplified, add all users of the instruction to
121 /// the work lists because they might get more simplified now.
122 void AddUsersToWorklist(SDNode *N) {
123 for (SDNode *Node : N->uses())
124 AddToWorklist(Node);
125 }
127 /// Call the node-specific routine that folds each particular type of node.
128 SDValue visit(SDNode *N);
130 public:
131 /// Add to the worklist making sure its instance is at the back (next to be
132 /// processed.)
133 void AddToWorklist(SDNode *N) {
134 // Skip handle nodes as they can't usefully be combined and confuse the
135 // zero-use deletion strategy.
136 if (N->getOpcode() == ISD::HANDLENODE)
137 return;
139 if (WorklistMap.insert(std::make_pair(N, Worklist.size())).second)
140 Worklist.push_back(N);
141 }
143 /// Remove all instances of N from the worklist.
144 void removeFromWorklist(SDNode *N) {
145 CombinedNodes.erase(N);
147 auto It = WorklistMap.find(N);
148 if (It == WorklistMap.end())
149 return; // Not in the worklist.
151 // Null out the entry rather than erasing it to avoid a linear operation.
152 Worklist[It->second] = nullptr;
153 WorklistMap.erase(It);
154 }
156 void deleteAndRecombine(SDNode *N);
157 bool recursivelyDeleteUnusedNodes(SDNode *N);
159 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
160 bool AddTo = true);
162 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
163 return CombineTo(N, &Res, 1, AddTo);
164 }
166 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
167 bool AddTo = true) {
168 SDValue To[] = { Res0, Res1 };
169 return CombineTo(N, To, 2, AddTo);
170 }
172 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
174 private:
176 /// Check the specified integer node value to see if it can be simplified or
177 /// if things it uses can be simplified by bit propagation.
178 /// If so, return true.
179 bool SimplifyDemandedBits(SDValue Op) {
180 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits();
181 APInt Demanded = APInt::getAllOnesValue(BitWidth);
182 return SimplifyDemandedBits(Op, Demanded);
183 }
185 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
187 bool CombineToPreIndexedLoadStore(SDNode *N);
188 bool CombineToPostIndexedLoadStore(SDNode *N);
189 SDValue SplitIndexingFromLoad(LoadSDNode *LD);
190 bool SliceUpLoad(SDNode *N);
192 /// \brief Replace an ISD::EXTRACT_VECTOR_ELT of a load with a narrowed
193 /// load.
194 ///
195 /// \param EVE ISD::EXTRACT_VECTOR_ELT to be replaced.
196 /// \param InVecVT type of the input vector to EVE with bitcasts resolved.
197 /// \param EltNo index of the vector element to load.
198 /// \param OriginalLoad load that EVE came from to be replaced.
199 /// \returns EVE on success SDValue() on failure.
200 SDValue ReplaceExtractVectorEltOfLoadWithNarrowedLoad(
201 SDNode *EVE, EVT InVecVT, SDValue EltNo, LoadSDNode *OriginalLoad);
202 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad);
203 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace);
204 SDValue SExtPromoteOperand(SDValue Op, EVT PVT);
205 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT);
206 SDValue PromoteIntBinOp(SDValue Op);
207 SDValue PromoteIntShiftOp(SDValue Op);
208 SDValue PromoteExtend(SDValue Op);
209 bool PromoteLoad(SDValue Op);
211 void ExtendSetCCUses(const SmallVectorImpl<SDNode *> &SetCCs,
212 SDValue Trunc, SDValue ExtLoad, SDLoc DL,
213 ISD::NodeType ExtType);
215 /// Call the node-specific routine that knows how to fold each
216 /// particular type of node. If that doesn't do anything, try the
217 /// target-specific DAG combines.
218 SDValue combine(SDNode *N);
220 // Visitation implementation - Implement dag node combining for different
221 // node types. The semantics are as follows:
222 // Return Value:
223 // SDValue.getNode() == 0 - No change was made
224 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
225 // otherwise - N should be replaced by the returned Operand.
226 //
227 SDValue visitTokenFactor(SDNode *N);
228 SDValue visitMERGE_VALUES(SDNode *N);
229 SDValue visitADD(SDNode *N);
230 SDValue visitSUB(SDNode *N);
231 SDValue visitADDC(SDNode *N);
232 SDValue visitSUBC(SDNode *N);
233 SDValue visitADDE(SDNode *N);
234 SDValue visitSUBE(SDNode *N);
235 SDValue visitMUL(SDNode *N);
236 SDValue visitSDIV(SDNode *N);
237 SDValue visitUDIV(SDNode *N);
238 SDValue visitSREM(SDNode *N);
239 SDValue visitUREM(SDNode *N);
240 SDValue visitMULHU(SDNode *N);
241 SDValue visitMULHS(SDNode *N);
242 SDValue visitSMUL_LOHI(SDNode *N);
243 SDValue visitUMUL_LOHI(SDNode *N);
244 SDValue visitSMULO(SDNode *N);
245 SDValue visitUMULO(SDNode *N);
246 SDValue visitSDIVREM(SDNode *N);
247 SDValue visitUDIVREM(SDNode *N);
248 SDValue visitAND(SDNode *N);
249 SDValue visitOR(SDNode *N);
250 SDValue visitXOR(SDNode *N);
251 SDValue SimplifyVBinOp(SDNode *N);
252 SDValue SimplifyVUnaryOp(SDNode *N);
253 SDValue visitSHL(SDNode *N);
254 SDValue visitSRA(SDNode *N);
255 SDValue visitSRL(SDNode *N);
256 SDValue visitRotate(SDNode *N);
257 SDValue visitCTLZ(SDNode *N);
258 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N);
259 SDValue visitCTTZ(SDNode *N);
260 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N);
261 SDValue visitCTPOP(SDNode *N);
262 SDValue visitSELECT(SDNode *N);
263 SDValue visitVSELECT(SDNode *N);
264 SDValue visitSELECT_CC(SDNode *N);
265 SDValue visitSETCC(SDNode *N);
266 SDValue visitSIGN_EXTEND(SDNode *N);
267 SDValue visitZERO_EXTEND(SDNode *N);
268 SDValue visitANY_EXTEND(SDNode *N);
269 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
270 SDValue visitTRUNCATE(SDNode *N);
271 SDValue visitBITCAST(SDNode *N);
272 SDValue visitBUILD_PAIR(SDNode *N);
273 SDValue visitFADD(SDNode *N);
274 SDValue visitFSUB(SDNode *N);
275 SDValue visitFMUL(SDNode *N);
276 SDValue visitFMA(SDNode *N);
277 SDValue visitFDIV(SDNode *N);
278 SDValue visitFREM(SDNode *N);
279 SDValue visitFSQRT(SDNode *N);
280 SDValue visitFCOPYSIGN(SDNode *N);
281 SDValue visitSINT_TO_FP(SDNode *N);
282 SDValue visitUINT_TO_FP(SDNode *N);
283 SDValue visitFP_TO_SINT(SDNode *N);
284 SDValue visitFP_TO_UINT(SDNode *N);
285 SDValue visitFP_ROUND(SDNode *N);
286 SDValue visitFP_ROUND_INREG(SDNode *N);
287 SDValue visitFP_EXTEND(SDNode *N);
288 SDValue visitFNEG(SDNode *N);
289 SDValue visitFABS(SDNode *N);
290 SDValue visitFCEIL(SDNode *N);
291 SDValue visitFTRUNC(SDNode *N);
292 SDValue visitFFLOOR(SDNode *N);
293 SDValue visitFMINNUM(SDNode *N);
294 SDValue visitFMAXNUM(SDNode *N);
295 SDValue visitBRCOND(SDNode *N);
296 SDValue visitBR_CC(SDNode *N);
297 SDValue visitLOAD(SDNode *N);
298 SDValue visitSTORE(SDNode *N);
299 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
300 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
301 SDValue visitBUILD_VECTOR(SDNode *N);
302 SDValue visitCONCAT_VECTORS(SDNode *N);
303 SDValue visitEXTRACT_SUBVECTOR(SDNode *N);
304 SDValue visitVECTOR_SHUFFLE(SDNode *N);
305 SDValue visitINSERT_SUBVECTOR(SDNode *N);
306 SDValue visitMLOAD(SDNode *N);
307 SDValue visitMSTORE(SDNode *N);
309 SDValue XformToShuffleWithZero(SDNode *N);
310 SDValue ReassociateOps(unsigned Opc, SDLoc DL, SDValue LHS, SDValue RHS);
312 SDValue visitShiftByConstant(SDNode *N, ConstantSDNode *Amt);
314 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
315 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
316 SDValue SimplifySelect(SDLoc DL, SDValue N0, SDValue N1, SDValue N2);
317 SDValue SimplifySelectCC(SDLoc DL, SDValue N0, SDValue N1, SDValue N2,
318 SDValue N3, ISD::CondCode CC,
319 bool NotExtCompare = false);
320 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
321 SDLoc DL, bool foldBooleans = true);
323 bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
324 SDValue &CC) const;
325 bool isOneUseSetCC(SDValue N) const;
327 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
328 unsigned HiOp);
329 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
330 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT);
331 SDValue BuildSDIV(SDNode *N);
332 SDValue BuildSDIVPow2(SDNode *N);
333 SDValue BuildUDIV(SDNode *N);
334 SDValue BuildReciprocalEstimate(SDValue Op);
335 SDValue BuildRsqrtEstimate(SDValue Op);
336 SDValue BuildRsqrtNROneConst(SDValue Op, SDValue Est, unsigned Iterations);
337 SDValue BuildRsqrtNRTwoConst(SDValue Op, SDValue Est, unsigned Iterations);
338 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
339 bool DemandHighBits = true);
340 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1);
341 SDNode *MatchRotatePosNeg(SDValue Shifted, SDValue Pos, SDValue Neg,
342 SDValue InnerPos, SDValue InnerNeg,
343 unsigned PosOpcode, unsigned NegOpcode,
344 SDLoc DL);
345 SDNode *MatchRotate(SDValue LHS, SDValue RHS, SDLoc DL);
346 SDValue ReduceLoadWidth(SDNode *N);
347 SDValue ReduceLoadOpStoreWidth(SDNode *N);
348 SDValue TransformFPLoadStorePair(SDNode *N);
349 SDValue reduceBuildVecExtToExtBuildVec(SDNode *N);
350 SDValue reduceBuildVecConvertToConvertBuildVec(SDNode *N);
352 SDValue GetDemandedBits(SDValue V, const APInt &Mask);
354 /// Walk up chain skipping non-aliasing memory nodes,
355 /// looking for aliasing nodes and adding them to the Aliases vector.
356 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
357 SmallVectorImpl<SDValue> &Aliases);
359 /// Return true if there is any possibility that the two addresses overlap.
360 bool isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1) const;
362 /// Walk up chain skipping non-aliasing memory nodes, looking for a better
363 /// chain (aliasing node.)
364 SDValue FindBetterChain(SDNode *N, SDValue Chain);
366 /// Merge consecutive store operations into a wide store.
367 /// This optimization uses wide integers or vectors when possible.
368 /// \return True if some memory operations were changed.
369 bool MergeConsecutiveStores(StoreSDNode *N);
371 /// \brief Try to transform a truncation where C is a constant:
372 /// (trunc (and X, C)) -> (and (trunc X), (trunc C))
373 ///
374 /// \p N needs to be a truncation and its first operand an AND. Other
375 /// requirements are checked by the function (e.g. that trunc is
376 /// single-use) and if missed an empty SDValue is returned.
377 SDValue distributeTruncateThroughAnd(SDNode *N);
379 public:
380 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL)
381 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes),
382 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {
383 AttributeSet FnAttrs =
384 DAG.getMachineFunction().getFunction()->getAttributes();
385 ForCodeSize =
386 FnAttrs.hasAttribute(AttributeSet::FunctionIndex,
387 Attribute::OptimizeForSize) ||
388 FnAttrs.hasAttribute(AttributeSet::FunctionIndex, Attribute::MinSize);
389 }
391 /// Runs the dag combiner on all nodes in the work list
392 void Run(CombineLevel AtLevel);
394 SelectionDAG &getDAG() const { return DAG; }
396 /// Returns a type large enough to hold any valid shift amount - before type
397 /// legalization these can be huge.
398 EVT getShiftAmountTy(EVT LHSTy) {
399 assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
400 if (LHSTy.isVector())
401 return LHSTy;
402 return LegalTypes ? TLI.getScalarShiftAmountTy(LHSTy)
403 : TLI.getPointerTy();
404 }
406 /// This method returns true if we are running before type legalization or
407 /// if the specified VT is legal.
408 bool isTypeLegal(const EVT &VT) {
409 if (!LegalTypes) return true;
410 return TLI.isTypeLegal(VT);
411 }
413 /// Convenience wrapper around TargetLowering::getSetCCResultType
414 EVT getSetCCResultType(EVT VT) const {
415 return TLI.getSetCCResultType(*DAG.getContext(), VT);
416 }
417 };
418 }
421 namespace {
422 /// This class is a DAGUpdateListener that removes any deleted
423 /// nodes from the worklist.
424 class WorklistRemover : public SelectionDAG::DAGUpdateListener {
425 DAGCombiner &DC;
426 public:
427 explicit WorklistRemover(DAGCombiner &dc)
428 : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {}
430 void NodeDeleted(SDNode *N, SDNode *E) override {
431 DC.removeFromWorklist(N);
432 }
433 };
434 }
436 //===----------------------------------------------------------------------===//
437 // TargetLowering::DAGCombinerInfo implementation
438 //===----------------------------------------------------------------------===//
440 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
441 ((DAGCombiner*)DC)->AddToWorklist(N);
442 }
444 void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) {
445 ((DAGCombiner*)DC)->removeFromWorklist(N);
446 }
448 SDValue TargetLowering::DAGCombinerInfo::
449 CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) {
450 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
451 }
453 SDValue TargetLowering::DAGCombinerInfo::
454 CombineTo(SDNode *N, SDValue Res, bool AddTo) {
455 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
456 }
459 SDValue TargetLowering::DAGCombinerInfo::
460 CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
461 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
462 }
464 void TargetLowering::DAGCombinerInfo::
465 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
466 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
467 }
469 //===----------------------------------------------------------------------===//
470 // Helper Functions
471 //===----------------------------------------------------------------------===//
473 void DAGCombiner::deleteAndRecombine(SDNode *N) {
474 removeFromWorklist(N);
476 // If the operands of this node are only used by the node, they will now be
477 // dead. Make sure to re-visit them and recursively delete dead nodes.
478 for (const SDValue &Op : N->ops())
479 // For an operand generating multiple values, one of the values may
480 // become dead allowing further simplification (e.g. split index
481 // arithmetic from an indexed load).
482 if (Op->hasOneUse() || Op->getNumValues() > 1)
483 AddToWorklist(Op.getNode());
485 DAG.DeleteNode(N);
486 }
488 /// Return 1 if we can compute the negated form of the specified expression for
489 /// the same cost as the expression itself, or 2 if we can compute the negated
490 /// form more cheaply than the expression itself.
491 static char isNegatibleForFree(SDValue Op, bool LegalOperations,
492 const TargetLowering &TLI,
493 const TargetOptions *Options,
494 unsigned Depth = 0) {
495 // fneg is removable even if it has multiple uses.
496 if (Op.getOpcode() == ISD::FNEG) return 2;
498 // Don't allow anything with multiple uses.
499 if (!Op.hasOneUse()) return 0;
501 // Don't recurse exponentially.
502 if (Depth > 6) return 0;
504 switch (Op.getOpcode()) {
505 default: return false;
506 case ISD::ConstantFP:
507 // Don't invert constant FP values after legalize. The negated constant
508 // isn't necessarily legal.
509 return LegalOperations ? 0 : 1;
510 case ISD::FADD:
511 // FIXME: determine better conditions for this xform.
512 if (!Options->UnsafeFPMath) return 0;
514 // After operation legalization, it might not be legal to create new FSUBs.
515 if (LegalOperations &&
516 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType()))
517 return 0;
519 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
520 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
521 Options, Depth + 1))
522 return V;
523 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
524 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
525 Depth + 1);
526 case ISD::FSUB:
527 // We can't turn -(A-B) into B-A when we honor signed zeros.
528 if (!Options->UnsafeFPMath) return 0;
530 // fold (fneg (fsub A, B)) -> (fsub B, A)
531 return 1;
533 case ISD::FMUL:
534 case ISD::FDIV:
535 if (Options->HonorSignDependentRoundingFPMath()) return 0;
537 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
538 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
539 Options, Depth + 1))
540 return V;
542 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
543 Depth + 1);
545 case ISD::FP_EXTEND:
546 case ISD::FP_ROUND:
547 case ISD::FSIN:
548 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options,
549 Depth + 1);
550 }
551 }
553 /// If isNegatibleForFree returns true, return the newly negated expression.
554 static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
555 bool LegalOperations, unsigned Depth = 0) {
556 const TargetOptions &Options = DAG.getTarget().Options;
557 // fneg is removable even if it has multiple uses.
558 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
560 // Don't allow anything with multiple uses.
561 assert(Op.hasOneUse() && "Unknown reuse!");
563 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
564 switch (Op.getOpcode()) {
565 default: llvm_unreachable("Unknown code");
566 case ISD::ConstantFP: {
567 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
568 V.changeSign();
569 return DAG.getConstantFP(V, Op.getValueType());
570 }
571 case ISD::FADD:
572 // FIXME: determine better conditions for this xform.
573 assert(Options.UnsafeFPMath);
575 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
576 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
577 DAG.getTargetLoweringInfo(), &Options, Depth+1))
578 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
579 GetNegatedExpression(Op.getOperand(0), DAG,
580 LegalOperations, Depth+1),
581 Op.getOperand(1));
582 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
583 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
584 GetNegatedExpression(Op.getOperand(1), DAG,
585 LegalOperations, Depth+1),
586 Op.getOperand(0));
587 case ISD::FSUB:
588 // We can't turn -(A-B) into B-A when we honor signed zeros.
589 assert(Options.UnsafeFPMath);
591 // fold (fneg (fsub 0, B)) -> B
592 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
593 if (N0CFP->getValueAPF().isZero())
594 return Op.getOperand(1);
596 // fold (fneg (fsub A, B)) -> (fsub B, A)
597 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
598 Op.getOperand(1), Op.getOperand(0));
600 case ISD::FMUL:
601 case ISD::FDIV:
602 assert(!Options.HonorSignDependentRoundingFPMath());
604 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
605 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
606 DAG.getTargetLoweringInfo(), &Options, Depth+1))
607 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
608 GetNegatedExpression(Op.getOperand(0), DAG,
609 LegalOperations, Depth+1),
610 Op.getOperand(1));
612 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
613 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
614 Op.getOperand(0),
615 GetNegatedExpression(Op.getOperand(1), DAG,
616 LegalOperations, Depth+1));
618 case ISD::FP_EXTEND:
619 case ISD::FSIN:
620 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
621 GetNegatedExpression(Op.getOperand(0), DAG,
622 LegalOperations, Depth+1));
623 case ISD::FP_ROUND:
624 return DAG.getNode(ISD::FP_ROUND, SDLoc(Op), Op.getValueType(),
625 GetNegatedExpression(Op.getOperand(0), DAG,
626 LegalOperations, Depth+1),
627 Op.getOperand(1));
628 }
629 }
631 // Return true if this node is a setcc, or is a select_cc
632 // that selects between the target values used for true and false, making it
633 // equivalent to a setcc. Also, set the incoming LHS, RHS, and CC references to
634 // the appropriate nodes based on the type of node we are checking. This
635 // simplifies life a bit for the callers.
636 bool DAGCombiner::isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
637 SDValue &CC) const {
638 if (N.getOpcode() == ISD::SETCC) {
639 LHS = N.getOperand(0);
640 RHS = N.getOperand(1);
641 CC = N.getOperand(2);
642 return true;
643 }
645 if (N.getOpcode() != ISD::SELECT_CC ||
646 !TLI.isConstTrueVal(N.getOperand(2).getNode()) ||
647 !TLI.isConstFalseVal(N.getOperand(3).getNode()))
648 return false;
650 if (TLI.getBooleanContents(N.getValueType()) ==
651 TargetLowering::UndefinedBooleanContent)
652 return false;
654 LHS = N.getOperand(0);
655 RHS = N.getOperand(1);
656 CC = N.getOperand(4);
657 return true;
658 }
660 /// Return true if this is a SetCC-equivalent operation with only one use.
661 /// If this is true, it allows the users to invert the operation for free when
662 /// it is profitable to do so.
663 bool DAGCombiner::isOneUseSetCC(SDValue N) const {
664 SDValue N0, N1, N2;
665 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
666 return true;
667 return false;
668 }
670 /// Returns true if N is a BUILD_VECTOR node whose
671 /// elements are all the same constant or undefined.
672 static bool isConstantSplatVector(SDNode *N, APInt& SplatValue) {
673 BuildVectorSDNode *C = dyn_cast<BuildVectorSDNode>(N);
674 if (!C)
675 return false;
677 APInt SplatUndef;
678 unsigned SplatBitSize;
679 bool HasAnyUndefs;
680 EVT EltVT = N->getValueType(0).getVectorElementType();
681 return (C->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
682 HasAnyUndefs) &&
683 EltVT.getSizeInBits() >= SplatBitSize);
684 }
686 // \brief Returns the SDNode if it is a constant BuildVector or constant.
687 static SDNode *isConstantBuildVectorOrConstantInt(SDValue N) {
688 if (isa<ConstantSDNode>(N))
689 return N.getNode();
690 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N);
691 if (BV && BV->isConstant())
692 return BV;
693 return nullptr;
694 }
696 // \brief Returns the SDNode if it is a constant splat BuildVector or constant
697 // int.
698 static ConstantSDNode *isConstOrConstSplat(SDValue N) {
699 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N))
700 return CN;
702 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N)) {
703 BitVector UndefElements;
704 ConstantSDNode *CN = BV->getConstantSplatNode(&UndefElements);
706 // BuildVectors can truncate their operands. Ignore that case here.
707 // FIXME: We blindly ignore splats which include undef which is overly
708 // pessimistic.
709 if (CN && UndefElements.none() &&
710 CN->getValueType(0) == N.getValueType().getScalarType())
711 return CN;
712 }
714 return nullptr;
715 }
717 // \brief Returns the SDNode if it is a constant splat BuildVector or constant
718 // float.
719 static ConstantFPSDNode *isConstOrConstSplatFP(SDValue N) {
720 if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N))
721 return CN;
723 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N)) {
724 BitVector UndefElements;
725 ConstantFPSDNode *CN = BV->getConstantFPSplatNode(&UndefElements);
727 if (CN && UndefElements.none())
728 return CN;
729 }
731 return nullptr;
732 }
734 SDValue DAGCombiner::ReassociateOps(unsigned Opc, SDLoc DL,
735 SDValue N0, SDValue N1) {
736 EVT VT = N0.getValueType();
737 if (N0.getOpcode() == Opc) {
738 if (SDNode *L = isConstantBuildVectorOrConstantInt(N0.getOperand(1))) {
739 if (SDNode *R = isConstantBuildVectorOrConstantInt(N1)) {
740 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
741 SDValue OpNode = DAG.FoldConstantArithmetic(Opc, VT, L, R);
742 if (!OpNode.getNode())
743 return SDValue();
744 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
745 }
746 if (N0.hasOneUse()) {
747 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one
748 // use
749 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N0.getOperand(0), N1);
750 if (!OpNode.getNode())
751 return SDValue();
752 AddToWorklist(OpNode.getNode());
753 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
754 }
755 }
756 }
758 if (N1.getOpcode() == Opc) {
759 if (SDNode *R = isConstantBuildVectorOrConstantInt(N1.getOperand(1))) {
760 if (SDNode *L = isConstantBuildVectorOrConstantInt(N0)) {
761 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
762 SDValue OpNode = DAG.FoldConstantArithmetic(Opc, VT, R, L);
763 if (!OpNode.getNode())
764 return SDValue();
765 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
766 }
767 if (N1.hasOneUse()) {
768 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one
769 // use
770 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N1.getOperand(0), N0);
771 if (!OpNode.getNode())
772 return SDValue();
773 AddToWorklist(OpNode.getNode());
774 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
775 }
776 }
777 }
779 return SDValue();
780 }
782 SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
783 bool AddTo) {
784 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
785 ++NodesCombined;
786 DEBUG(dbgs() << "\nReplacing.1 ";
787 N->dump(&DAG);
788 dbgs() << "\nWith: ";
789 To[0].getNode()->dump(&DAG);
790 dbgs() << " and " << NumTo-1 << " other values\n");
791 for (unsigned i = 0, e = NumTo; i != e; ++i)
792 assert((!To[i].getNode() ||
793 N->getValueType(i) == To[i].getValueType()) &&
794 "Cannot combine value to value of different type!");
796 WorklistRemover DeadNodes(*this);
797 DAG.ReplaceAllUsesWith(N, To);
798 if (AddTo) {
799 // Push the new nodes and any users onto the worklist
800 for (unsigned i = 0, e = NumTo; i != e; ++i) {
801 if (To[i].getNode()) {
802 AddToWorklist(To[i].getNode());
803 AddUsersToWorklist(To[i].getNode());
804 }
805 }
806 }
808 // Finally, if the node is now dead, remove it from the graph. The node
809 // may not be dead if the replacement process recursively simplified to
810 // something else needing this node.
811 if (N->use_empty())
812 deleteAndRecombine(N);
813 return SDValue(N, 0);
814 }
816 void DAGCombiner::
817 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
818 // Replace all uses. If any nodes become isomorphic to other nodes and
819 // are deleted, make sure to remove them from our worklist.
820 WorklistRemover DeadNodes(*this);
821 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New);
823 // Push the new node and any (possibly new) users onto the worklist.
824 AddToWorklist(TLO.New.getNode());
825 AddUsersToWorklist(TLO.New.getNode());
827 // Finally, if the node is now dead, remove it from the graph. The node
828 // may not be dead if the replacement process recursively simplified to
829 // something else needing this node.
830 if (TLO.Old.getNode()->use_empty())
831 deleteAndRecombine(TLO.Old.getNode());
832 }
834 /// Check the specified integer node value to see if it can be simplified or if
835 /// things it uses can be simplified by bit propagation. If so, return true.
836 bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
837 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
838 APInt KnownZero, KnownOne;
839 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
840 return false;
842 // Revisit the node.
843 AddToWorklist(Op.getNode());
845 // Replace the old value with the new one.
846 ++NodesCombined;
847 DEBUG(dbgs() << "\nReplacing.2 ";
848 TLO.Old.getNode()->dump(&DAG);
849 dbgs() << "\nWith: ";
850 TLO.New.getNode()->dump(&DAG);
851 dbgs() << '\n');
853 CommitTargetLoweringOpt(TLO);
854 return true;
855 }
857 void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) {
858 SDLoc dl(Load);
859 EVT VT = Load->getValueType(0);
860 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0));
862 DEBUG(dbgs() << "\nReplacing.9 ";
863 Load->dump(&DAG);
864 dbgs() << "\nWith: ";
865 Trunc.getNode()->dump(&DAG);
866 dbgs() << '\n');
867 WorklistRemover DeadNodes(*this);
868 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc);
869 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1));
870 deleteAndRecombine(Load);
871 AddToWorklist(Trunc.getNode());
872 }
874 SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) {
875 Replace = false;
876 SDLoc dl(Op);
877 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) {
878 EVT MemVT = LD->getMemoryVT();
879 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
880 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, PVT, MemVT) ? ISD::ZEXTLOAD
881 : ISD::EXTLOAD)
882 : LD->getExtensionType();
883 Replace = true;
884 return DAG.getExtLoad(ExtType, dl, PVT,
885 LD->getChain(), LD->getBasePtr(),
886 MemVT, LD->getMemOperand());
887 }
889 unsigned Opc = Op.getOpcode();
890 switch (Opc) {
891 default: break;
892 case ISD::AssertSext:
893 return DAG.getNode(ISD::AssertSext, dl, PVT,
894 SExtPromoteOperand(Op.getOperand(0), PVT),
895 Op.getOperand(1));
896 case ISD::AssertZext:
897 return DAG.getNode(ISD::AssertZext, dl, PVT,
898 ZExtPromoteOperand(Op.getOperand(0), PVT),
899 Op.getOperand(1));
900 case ISD::Constant: {
901 unsigned ExtOpc =
902 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
903 return DAG.getNode(ExtOpc, dl, PVT, Op);
904 }
905 }
907 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT))
908 return SDValue();
909 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op);
910 }
912 SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) {
913 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
914 return SDValue();
915 EVT OldVT = Op.getValueType();
916 SDLoc dl(Op);
917 bool Replace = false;
918 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
919 if (!NewOp.getNode())
920 return SDValue();
921 AddToWorklist(NewOp.getNode());
923 if (Replace)
924 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
925 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp,
926 DAG.getValueType(OldVT));
927 }
929 SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) {
930 EVT OldVT = Op.getValueType();
931 SDLoc dl(Op);
932 bool Replace = false;
933 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
934 if (!NewOp.getNode())
935 return SDValue();
936 AddToWorklist(NewOp.getNode());
938 if (Replace)
939 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
940 return DAG.getZeroExtendInReg(NewOp, dl, OldVT);
941 }
943 /// Promote the specified integer binary operation if the target indicates it is
944 /// beneficial. e.g. On x86, it's usually better to promote i16 operations to
945 /// i32 since i16 instructions are longer.
946 SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
947 if (!LegalOperations)
948 return SDValue();
950 EVT VT = Op.getValueType();
951 if (VT.isVector() || !VT.isInteger())
952 return SDValue();
954 // If operation type is 'undesirable', e.g. i16 on x86, consider
955 // promoting it.
956 unsigned Opc = Op.getOpcode();
957 if (TLI.isTypeDesirableForOp(Opc, VT))
958 return SDValue();
960 EVT PVT = VT;
961 // Consult target whether it is a good idea to promote this operation and
962 // what's the right type to promote it to.
963 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
964 assert(PVT != VT && "Don't know what type to promote to!");
966 bool Replace0 = false;
967 SDValue N0 = Op.getOperand(0);
968 SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
969 if (!NN0.getNode())
970 return SDValue();
972 bool Replace1 = false;
973 SDValue N1 = Op.getOperand(1);
974 SDValue NN1;
975 if (N0 == N1)
976 NN1 = NN0;
977 else {
978 NN1 = PromoteOperand(N1, PVT, Replace1);
979 if (!NN1.getNode())
980 return SDValue();
981 }
983 AddToWorklist(NN0.getNode());
984 if (NN1.getNode())
985 AddToWorklist(NN1.getNode());
987 if (Replace0)
988 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
989 if (Replace1)
990 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode());
992 DEBUG(dbgs() << "\nPromoting ";
993 Op.getNode()->dump(&DAG));
994 SDLoc dl(Op);
995 return DAG.getNode(ISD::TRUNCATE, dl, VT,
996 DAG.getNode(Opc, dl, PVT, NN0, NN1));
997 }
998 return SDValue();
999 }
1001 /// Promote the specified integer shift operation if the target indicates it is
1002 /// beneficial. e.g. On x86, it's usually better to promote i16 operations to
1003 /// i32 since i16 instructions are longer.
1004 SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) {
1005 if (!LegalOperations)
1006 return SDValue();
1008 EVT VT = Op.getValueType();
1009 if (VT.isVector() || !VT.isInteger())
1010 return SDValue();
1012 // If operation type is 'undesirable', e.g. i16 on x86, consider
1013 // promoting it.
1014 unsigned Opc = Op.getOpcode();
1015 if (TLI.isTypeDesirableForOp(Opc, VT))
1016 return SDValue();
1018 EVT PVT = VT;
1019 // Consult target whether it is a good idea to promote this operation and
1020 // what's the right type to promote it to.
1021 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1022 assert(PVT != VT && "Don't know what type to promote to!");
1024 bool Replace = false;
1025 SDValue N0 = Op.getOperand(0);
1026 if (Opc == ISD::SRA)
1027 N0 = SExtPromoteOperand(Op.getOperand(0), PVT);
1028 else if (Opc == ISD::SRL)
1029 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT);
1030 else
1031 N0 = PromoteOperand(N0, PVT, Replace);
1032 if (!N0.getNode())
1033 return SDValue();
1035 AddToWorklist(N0.getNode());
1036 if (Replace)
1037 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
1039 DEBUG(dbgs() << "\nPromoting ";
1040 Op.getNode()->dump(&DAG));
1041 SDLoc dl(Op);
1042 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1043 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1)));
1044 }
1045 return SDValue();
1046 }
1048 SDValue DAGCombiner::PromoteExtend(SDValue Op) {
1049 if (!LegalOperations)
1050 return SDValue();
1052 EVT VT = Op.getValueType();
1053 if (VT.isVector() || !VT.isInteger())
1054 return SDValue();
1056 // If operation type is 'undesirable', e.g. i16 on x86, consider
1057 // promoting it.
1058 unsigned Opc = Op.getOpcode();
1059 if (TLI.isTypeDesirableForOp(Opc, VT))
1060 return SDValue();
1062 EVT PVT = VT;
1063 // Consult target whether it is a good idea to promote this operation and
1064 // what's the right type to promote it to.
1065 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1066 assert(PVT != VT && "Don't know what type to promote to!");
1067 // fold (aext (aext x)) -> (aext x)
1068 // fold (aext (zext x)) -> (zext x)
1069 // fold (aext (sext x)) -> (sext x)
1070 DEBUG(dbgs() << "\nPromoting ";
1071 Op.getNode()->dump(&DAG));
1072 return DAG.getNode(Op.getOpcode(), SDLoc(Op), VT, Op.getOperand(0));
1073 }
1074 return SDValue();
1075 }
1077 bool DAGCombiner::PromoteLoad(SDValue Op) {
1078 if (!LegalOperations)
1079 return false;
1081 EVT VT = Op.getValueType();
1082 if (VT.isVector() || !VT.isInteger())
1083 return false;
1085 // If operation type is 'undesirable', e.g. i16 on x86, consider
1086 // promoting it.
1087 unsigned Opc = Op.getOpcode();
1088 if (TLI.isTypeDesirableForOp(Opc, VT))
1089 return false;
1091 EVT PVT = VT;
1092 // Consult target whether it is a good idea to promote this operation and
1093 // what's the right type to promote it to.
1094 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1095 assert(PVT != VT && "Don't know what type to promote to!");
1097 SDLoc dl(Op);
1098 SDNode *N = Op.getNode();
1099 LoadSDNode *LD = cast<LoadSDNode>(N);
1100 EVT MemVT = LD->getMemoryVT();
1101 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
1102 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, PVT, MemVT) ? ISD::ZEXTLOAD
1103 : ISD::EXTLOAD)
1104 : LD->getExtensionType();
1105 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT,
1106 LD->getChain(), LD->getBasePtr(),
1107 MemVT, LD->getMemOperand());
1108 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD);
1110 DEBUG(dbgs() << "\nPromoting ";
1111 N->dump(&DAG);
1112 dbgs() << "\nTo: ";
1113 Result.getNode()->dump(&DAG);
1114 dbgs() << '\n');
1115 WorklistRemover DeadNodes(*this);
1116 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
1117 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1));
1118 deleteAndRecombine(N);
1119 AddToWorklist(Result.getNode());
1120 return true;
1121 }
1122 return false;
1123 }
1125 /// \brief Recursively delete a node which has no uses and any operands for
1126 /// which it is the only use.
1127 ///
1128 /// Note that this both deletes the nodes and removes them from the worklist.
1129 /// It also adds any nodes who have had a user deleted to the worklist as they
1130 /// may now have only one use and subject to other combines.
1131 bool DAGCombiner::recursivelyDeleteUnusedNodes(SDNode *N) {
1132 if (!N->use_empty())
1133 return false;
1135 SmallSetVector<SDNode *, 16> Nodes;
1136 Nodes.insert(N);
1137 do {
1138 N = Nodes.pop_back_val();
1139 if (!N)
1140 continue;
1142 if (N->use_empty()) {
1143 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1144 Nodes.insert(N->getOperand(i).getNode());
1146 removeFromWorklist(N);
1147 DAG.DeleteNode(N);
1148 } else {
1149 AddToWorklist(N);
1150 }
1151 } while (!Nodes.empty());
1152 return true;
1153 }
1155 //===----------------------------------------------------------------------===//
1156 // Main DAG Combiner implementation
1157 //===----------------------------------------------------------------------===//
1159 void DAGCombiner::Run(CombineLevel AtLevel) {
1160 // set the instance variables, so that the various visit routines may use it.
1161 Level = AtLevel;
1162 LegalOperations = Level >= AfterLegalizeVectorOps;
1163 LegalTypes = Level >= AfterLegalizeTypes;
1165 // Early exit if this basic block is in an optnone function.
1166 AttributeSet FnAttrs =
1167 DAG.getMachineFunction().getFunction()->getAttributes();
1168 if (FnAttrs.hasAttribute(AttributeSet::FunctionIndex,
1169 Attribute::OptimizeNone))
1170 return;
1172 // Add all the dag nodes to the worklist.
1173 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
1174 E = DAG.allnodes_end(); I != E; ++I)
1175 AddToWorklist(I);
1177 // Create a dummy node (which is not added to allnodes), that adds a reference
1178 // to the root node, preventing it from being deleted, and tracking any
1179 // changes of the root.
1180 HandleSDNode Dummy(DAG.getRoot());
1182 // while the worklist isn't empty, find a node and
1183 // try and combine it.
1184 while (!WorklistMap.empty()) {
1185 SDNode *N;
1186 // The Worklist holds the SDNodes in order, but it may contain null entries.
1187 do {
1188 N = Worklist.pop_back_val();
1189 } while (!N);
1191 bool GoodWorklistEntry = WorklistMap.erase(N);
1192 (void)GoodWorklistEntry;
1193 assert(GoodWorklistEntry &&
1194 "Found a worklist entry without a corresponding map entry!");
1196 // If N has no uses, it is dead. Make sure to revisit all N's operands once
1197 // N is deleted from the DAG, since they too may now be dead or may have a
1198 // reduced number of uses, allowing other xforms.
1199 if (recursivelyDeleteUnusedNodes(N))
1200 continue;
1202 WorklistRemover DeadNodes(*this);
1204 // If this combine is running after legalizing the DAG, re-legalize any
1205 // nodes pulled off the worklist.
1206 if (Level == AfterLegalizeDAG) {
1207 SmallSetVector<SDNode *, 16> UpdatedNodes;
1208 bool NIsValid = DAG.LegalizeOp(N, UpdatedNodes);
1210 for (SDNode *LN : UpdatedNodes) {
1211 AddToWorklist(LN);
1212 AddUsersToWorklist(LN);
1213 }
1214 if (!NIsValid)
1215 continue;
1216 }
1218 DEBUG(dbgs() << "\nCombining: "; N->dump(&DAG));
1220 // Add any operands of the new node which have not yet been combined to the
1221 // worklist as well. Because the worklist uniques things already, this
1222 // won't repeatedly process the same operand.
1223 CombinedNodes.insert(N);
1224 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1225 if (!CombinedNodes.count(N->getOperand(i).getNode()))
1226 AddToWorklist(N->getOperand(i).getNode());
1228 SDValue RV = combine(N);
1230 if (!RV.getNode())
1231 continue;
1233 ++NodesCombined;
1235 // If we get back the same node we passed in, rather than a new node or
1236 // zero, we know that the node must have defined multiple values and
1237 // CombineTo was used. Since CombineTo takes care of the worklist
1238 // mechanics for us, we have no work to do in this case.
1239 if (RV.getNode() == N)
1240 continue;
1242 assert(N->getOpcode() != ISD::DELETED_NODE &&
1243 RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
1244 "Node was deleted but visit returned new node!");
1246 DEBUG(dbgs() << " ... into: ";
1247 RV.getNode()->dump(&DAG));
1249 // Transfer debug value.
1250 DAG.TransferDbgValues(SDValue(N, 0), RV);
1251 if (N->getNumValues() == RV.getNode()->getNumValues())
1252 DAG.ReplaceAllUsesWith(N, RV.getNode());
1253 else {
1254 assert(N->getValueType(0) == RV.getValueType() &&
1255 N->getNumValues() == 1 && "Type mismatch");
1256 SDValue OpV = RV;
1257 DAG.ReplaceAllUsesWith(N, &OpV);
1258 }
1260 // Push the new node and any users onto the worklist
1261 AddToWorklist(RV.getNode());
1262 AddUsersToWorklist(RV.getNode());
1264 // Finally, if the node is now dead, remove it from the graph. The node
1265 // may not be dead if the replacement process recursively simplified to
1266 // something else needing this node. This will also take care of adding any
1267 // operands which have lost a user to the worklist.
1268 recursivelyDeleteUnusedNodes(N);
1269 }
1271 // If the root changed (e.g. it was a dead load, update the root).
1272 DAG.setRoot(Dummy.getValue());
1273 DAG.RemoveDeadNodes();
1274 }
1276 SDValue DAGCombiner::visit(SDNode *N) {
1277 switch (N->getOpcode()) {
1278 default: break;
1279 case ISD::TokenFactor: return visitTokenFactor(N);
1280 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
1281 case ISD::ADD: return visitADD(N);
1282 case ISD::SUB: return visitSUB(N);
1283 case ISD::ADDC: return visitADDC(N);
1284 case ISD::SUBC: return visitSUBC(N);
1285 case ISD::ADDE: return visitADDE(N);
1286 case ISD::SUBE: return visitSUBE(N);
1287 case ISD::MUL: return visitMUL(N);
1288 case ISD::SDIV: return visitSDIV(N);
1289 case ISD::UDIV: return visitUDIV(N);
1290 case ISD::SREM: return visitSREM(N);
1291 case ISD::UREM: return visitUREM(N);
1292 case ISD::MULHU: return visitMULHU(N);
1293 case ISD::MULHS: return visitMULHS(N);
1294 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
1295 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
1296 case ISD::SMULO: return visitSMULO(N);
1297 case ISD::UMULO: return visitUMULO(N);
1298 case ISD::SDIVREM: return visitSDIVREM(N);
1299 case ISD::UDIVREM: return visitUDIVREM(N);
1300 case ISD::AND: return visitAND(N);
1301 case ISD::OR: return visitOR(N);
1302 case ISD::XOR: return visitXOR(N);
1303 case ISD::SHL: return visitSHL(N);
1304 case ISD::SRA: return visitSRA(N);
1305 case ISD::SRL: return visitSRL(N);
1306 case ISD::ROTR:
1307 case ISD::ROTL: return visitRotate(N);
1308 case ISD::CTLZ: return visitCTLZ(N);
1309 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N);
1310 case ISD::CTTZ: return visitCTTZ(N);
1311 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N);
1312 case ISD::CTPOP: return visitCTPOP(N);
1313 case ISD::SELECT: return visitSELECT(N);
1314 case ISD::VSELECT: return visitVSELECT(N);
1315 case ISD::SELECT_CC: return visitSELECT_CC(N);
1316 case ISD::SETCC: return visitSETCC(N);
1317 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
1318 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
1319 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
1320 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
1321 case ISD::TRUNCATE: return visitTRUNCATE(N);
1322 case ISD::BITCAST: return visitBITCAST(N);
1323 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
1324 case ISD::FADD: return visitFADD(N);
1325 case ISD::FSUB: return visitFSUB(N);
1326 case ISD::FMUL: return visitFMUL(N);
1327 case ISD::FMA: return visitFMA(N);
1328 case ISD::FDIV: return visitFDIV(N);
1329 case ISD::FREM: return visitFREM(N);
1330 case ISD::FSQRT: return visitFSQRT(N);
1331 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
1332 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
1333 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
1334 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
1335 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
1336 case ISD::FP_ROUND: return visitFP_ROUND(N);
1337 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
1338 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
1339 case ISD::FNEG: return visitFNEG(N);
1340 case ISD::FABS: return visitFABS(N);
1341 case ISD::FFLOOR: return visitFFLOOR(N);
1342 case ISD::FMINNUM: return visitFMINNUM(N);
1343 case ISD::FMAXNUM: return visitFMAXNUM(N);
1344 case ISD::FCEIL: return visitFCEIL(N);
1345 case ISD::FTRUNC: return visitFTRUNC(N);
1346 case ISD::BRCOND: return visitBRCOND(N);
1347 case ISD::BR_CC: return visitBR_CC(N);
1348 case ISD::LOAD: return visitLOAD(N);
1349 case ISD::STORE: return visitSTORE(N);
1350 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
1351 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
1352 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
1353 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
1354 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N);
1355 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
1356 case ISD::INSERT_SUBVECTOR: return visitINSERT_SUBVECTOR(N);
1357 case ISD::MLOAD: return visitMLOAD(N);
1358 case ISD::MSTORE: return visitMSTORE(N);
1359 }
1360 return SDValue();
1361 }
1363 SDValue DAGCombiner::combine(SDNode *N) {
1364 SDValue RV = visit(N);
1366 // If nothing happened, try a target-specific DAG combine.
1367 if (!RV.getNode()) {
1368 assert(N->getOpcode() != ISD::DELETED_NODE &&
1369 "Node was deleted but visit returned NULL!");
1371 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
1372 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
1374 // Expose the DAG combiner to the target combiner impls.
1375 TargetLowering::DAGCombinerInfo
1376 DagCombineInfo(DAG, Level, false, this);
1378 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
1379 }
1380 }
1382 // If nothing happened still, try promoting the operation.
1383 if (!RV.getNode()) {
1384 switch (N->getOpcode()) {
1385 default: break;
1386 case ISD::ADD:
1387 case ISD::SUB:
1388 case ISD::MUL:
1389 case ISD::AND:
1390 case ISD::OR:
1391 case ISD::XOR:
1392 RV = PromoteIntBinOp(SDValue(N, 0));
1393 break;
1394 case ISD::SHL:
1395 case ISD::SRA:
1396 case ISD::SRL:
1397 RV = PromoteIntShiftOp(SDValue(N, 0));
1398 break;
1399 case ISD::SIGN_EXTEND:
1400 case ISD::ZERO_EXTEND:
1401 case ISD::ANY_EXTEND:
1402 RV = PromoteExtend(SDValue(N, 0));
1403 break;
1404 case ISD::LOAD:
1405 if (PromoteLoad(SDValue(N, 0)))
1406 RV = SDValue(N, 0);
1407 break;
1408 }
1409 }
1411 // If N is a commutative binary node, try commuting it to enable more
1412 // sdisel CSE.
1413 if (!RV.getNode() && SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
1414 N->getNumValues() == 1) {
1415 SDValue N0 = N->getOperand(0);
1416 SDValue N1 = N->getOperand(1);
1418 // Constant operands are canonicalized to RHS.
1419 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
1420 SDValue Ops[] = {N1, N0};
1421 SDNode *CSENode;
1422 if (const BinaryWithFlagsSDNode *BinNode =
1423 dyn_cast<BinaryWithFlagsSDNode>(N)) {
1424 CSENode = DAG.getNodeIfExists(
1425 N->getOpcode(), N->getVTList(), Ops, BinNode->hasNoUnsignedWrap(),
1426 BinNode->hasNoSignedWrap(), BinNode->isExact());
1427 } else {
1428 CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), Ops);
1429 }
1430 if (CSENode)
1431 return SDValue(CSENode, 0);
1432 }
1433 }
1435 return RV;
1436 }
1438 /// Given a node, return its input chain if it has one, otherwise return a null
1439 /// sd operand.
1440 static SDValue getInputChainForNode(SDNode *N) {
1441 if (unsigned NumOps = N->getNumOperands()) {
1442 if (N->getOperand(0).getValueType() == MVT::Other)
1443 return N->getOperand(0);
1444 if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
1445 return N->getOperand(NumOps-1);
1446 for (unsigned i = 1; i < NumOps-1; ++i)
1447 if (N->getOperand(i).getValueType() == MVT::Other)
1448 return N->getOperand(i);
1449 }
1450 return SDValue();
1451 }
1453 SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
1454 // If N has two operands, where one has an input chain equal to the other,
1455 // the 'other' chain is redundant.
1456 if (N->getNumOperands() == 2) {
1457 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
1458 return N->getOperand(0);
1459 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
1460 return N->getOperand(1);
1461 }
1463 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
1464 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
1465 SmallPtrSet<SDNode*, 16> SeenOps;
1466 bool Changed = false; // If we should replace this token factor.
1468 // Start out with this token factor.
1469 TFs.push_back(N);
1471 // Iterate through token factors. The TFs grows when new token factors are
1472 // encountered.
1473 for (unsigned i = 0; i < TFs.size(); ++i) {
1474 SDNode *TF = TFs[i];
1476 // Check each of the operands.
1477 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
1478 SDValue Op = TF->getOperand(i);
1480 switch (Op.getOpcode()) {
1481 case ISD::EntryToken:
1482 // Entry tokens don't need to be added to the list. They are
1483 // rededundant.
1484 Changed = true;
1485 break;
1487 case ISD::TokenFactor:
1488 if (Op.hasOneUse() &&
1489 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
1490 // Queue up for processing.
1491 TFs.push_back(Op.getNode());
1492 // Clean up in case the token factor is removed.
1493 AddToWorklist(Op.getNode());
1494 Changed = true;
1495 break;
1496 }
1497 // Fall thru
1499 default:
1500 // Only add if it isn't already in the list.
1501 if (SeenOps.insert(Op.getNode()).second)
1502 Ops.push_back(Op);
1503 else
1504 Changed = true;
1505 break;
1506 }
1507 }
1508 }
1510 SDValue Result;
1512 // If we've change things around then replace token factor.
1513 if (Changed) {
1514 if (Ops.empty()) {
1515 // The entry token is the only possible outcome.
1516 Result = DAG.getEntryNode();
1517 } else {
1518 // New and improved token factor.
1519 Result = DAG.getNode(ISD::TokenFactor, SDLoc(N), MVT::Other, Ops);
1520 }
1522 // Don't add users to work list.
1523 return CombineTo(N, Result, false);
1524 }
1526 return Result;
1527 }
1529 /// MERGE_VALUES can always be eliminated.
1530 SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
1531 WorklistRemover DeadNodes(*this);
1532 // Replacing results may cause a different MERGE_VALUES to suddenly
1533 // be CSE'd with N, and carry its uses with it. Iterate until no
1534 // uses remain, to ensure that the node can be safely deleted.
1535 // First add the users of this node to the work list so that they
1536 // can be tried again once they have new operands.
1537 AddUsersToWorklist(N);
1538 do {
1539 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1540 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i));
1541 } while (!N->use_empty());
1542 deleteAndRecombine(N);
1543 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1544 }
1546 SDValue DAGCombiner::visitADD(SDNode *N) {
1547 SDValue N0 = N->getOperand(0);
1548 SDValue N1 = N->getOperand(1);
1549 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1550 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1551 EVT VT = N0.getValueType();
1553 // fold vector ops
1554 if (VT.isVector()) {
1555 SDValue FoldedVOp = SimplifyVBinOp(N);
1556 if (FoldedVOp.getNode()) return FoldedVOp;
1558 // fold (add x, 0) -> x, vector edition
1559 if (ISD::isBuildVectorAllZeros(N1.getNode()))
1560 return N0;
1561 if (ISD::isBuildVectorAllZeros(N0.getNode()))
1562 return N1;
1563 }
1565 // fold (add x, undef) -> undef
1566 if (N0.getOpcode() == ISD::UNDEF)
1567 return N0;
1568 if (N1.getOpcode() == ISD::UNDEF)
1569 return N1;
1570 // fold (add c1, c2) -> c1+c2
1571 if (N0C && N1C)
1572 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
1573 // canonicalize constant to RHS
1574 if (N0C && !N1C)
1575 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N1, N0);
1576 // fold (add x, 0) -> x
1577 if (N1C && N1C->isNullValue())
1578 return N0;
1579 // fold (add Sym, c) -> Sym+c
1580 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1581 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C &&
1582 GA->getOpcode() == ISD::GlobalAddress)
1583 return DAG.getGlobalAddress(GA->getGlobal(), SDLoc(N1C), VT,
1584 GA->getOffset() +
1585 (uint64_t)N1C->getSExtValue());
1586 // fold ((c1-A)+c2) -> (c1+c2)-A
1587 if (N1C && N0.getOpcode() == ISD::SUB)
1588 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
1589 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1590 DAG.getConstant(N1C->getAPIntValue()+
1591 N0C->getAPIntValue(), VT),
1592 N0.getOperand(1));
1593 // reassociate add
1594 SDValue RADD = ReassociateOps(ISD::ADD, SDLoc(N), N0, N1);
1595 if (RADD.getNode())
1596 return RADD;
1597 // fold ((0-A) + B) -> B-A
1598 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
1599 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
1600 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1, N0.getOperand(1));
1601 // fold (A + (0-B)) -> A-B
1602 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
1603 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
1604 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, N1.getOperand(1));
1605 // fold (A+(B-A)) -> B
1606 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1607 return N1.getOperand(0);
1608 // fold ((B-A)+A) -> B
1609 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1610 return N0.getOperand(0);
1611 // fold (A+(B-(A+C))) to (B-C)
1612 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1613 N0 == N1.getOperand(1).getOperand(0))
1614 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1.getOperand(0),
1615 N1.getOperand(1).getOperand(1));
1616 // fold (A+(B-(C+A))) to (B-C)
1617 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1618 N0 == N1.getOperand(1).getOperand(1))
1619 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1.getOperand(0),
1620 N1.getOperand(1).getOperand(0));
1621 // fold (A+((B-A)+or-C)) to (B+or-C)
1622 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
1623 N1.getOperand(0).getOpcode() == ISD::SUB &&
1624 N0 == N1.getOperand(0).getOperand(1))
1625 return DAG.getNode(N1.getOpcode(), SDLoc(N), VT,
1626 N1.getOperand(0).getOperand(0), N1.getOperand(1));
1628 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
1629 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1630 SDValue N00 = N0.getOperand(0);
1631 SDValue N01 = N0.getOperand(1);
1632 SDValue N10 = N1.getOperand(0);
1633 SDValue N11 = N1.getOperand(1);
1635 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10))
1636 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1637 DAG.getNode(ISD::ADD, SDLoc(N0), VT, N00, N10),
1638 DAG.getNode(ISD::ADD, SDLoc(N1), VT, N01, N11));
1639 }
1641 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
1642 return SDValue(N, 0);
1644 // fold (a+b) -> (a|b) iff a and b share no bits.
1645 if (VT.isInteger() && !VT.isVector()) {
1646 APInt LHSZero, LHSOne;
1647 APInt RHSZero, RHSOne;
1648 DAG.computeKnownBits(N0, LHSZero, LHSOne);
1650 if (LHSZero.getBoolValue()) {
1651 DAG.computeKnownBits(N1, RHSZero, RHSOne);
1653 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1654 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1655 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero){
1656 if (!LegalOperations || TLI.isOperationLegal(ISD::OR, VT))
1657 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N1);
1658 }
1659 }
1660 }
1662 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
1663 if (N1.getOpcode() == ISD::SHL &&
1664 N1.getOperand(0).getOpcode() == ISD::SUB)
1665 if (ConstantSDNode *C =
1666 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0)))
1667 if (C->getAPIntValue() == 0)
1668 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N0,
1669 DAG.getNode(ISD::SHL, SDLoc(N), VT,
1670 N1.getOperand(0).getOperand(1),
1671 N1.getOperand(1)));
1672 if (N0.getOpcode() == ISD::SHL &&
1673 N0.getOperand(0).getOpcode() == ISD::SUB)
1674 if (ConstantSDNode *C =
1675 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0)))
1676 if (C->getAPIntValue() == 0)
1677 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1,
1678 DAG.getNode(ISD::SHL, SDLoc(N), VT,
1679 N0.getOperand(0).getOperand(1),
1680 N0.getOperand(1)));
1682 if (N1.getOpcode() == ISD::AND) {
1683 SDValue AndOp0 = N1.getOperand(0);
1684 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1));
1685 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0);
1686 unsigned DestBits = VT.getScalarType().getSizeInBits();
1688 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x))
1689 // and similar xforms where the inner op is either ~0 or 0.
1690 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) {
1691 SDLoc DL(N);
1692 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0);
1693 }
1694 }
1696 // add (sext i1), X -> sub X, (zext i1)
1697 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
1698 N0.getOperand(0).getValueType() == MVT::i1 &&
1699 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) {
1700 SDLoc DL(N);
1701 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
1702 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt);
1703 }
1705 // add X, (sextinreg Y i1) -> sub X, (and Y 1)
1706 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
1707 VTSDNode *TN = cast<VTSDNode>(N1.getOperand(1));
1708 if (TN->getVT() == MVT::i1) {
1709 SDLoc DL(N);
1710 SDValue ZExt = DAG.getNode(ISD::AND, DL, VT, N1.getOperand(0),
1711 DAG.getConstant(1, VT));
1712 return DAG.getNode(ISD::SUB, DL, VT, N0, ZExt);
1713 }
1714 }
1716 return SDValue();
1717 }
1719 SDValue DAGCombiner::visitADDC(SDNode *N) {
1720 SDValue N0 = N->getOperand(0);
1721 SDValue N1 = N->getOperand(1);
1722 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1723 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1724 EVT VT = N0.getValueType();
1726 // If the flag result is dead, turn this into an ADD.
1727 if (!N->hasAnyUseOfValue(1))
1728 return CombineTo(N, DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N1),
1729 DAG.getNode(ISD::CARRY_FALSE,
1730 SDLoc(N), MVT::Glue));
1732 // canonicalize constant to RHS.
1733 if (N0C && !N1C)
1734 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N1, N0);
1736 // fold (addc x, 0) -> x + no carry out
1737 if (N1C && N1C->isNullValue())
1738 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1739 SDLoc(N), MVT::Glue));
1741 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1742 APInt LHSZero, LHSOne;
1743 APInt RHSZero, RHSOne;
1744 DAG.computeKnownBits(N0, LHSZero, LHSOne);
1746 if (LHSZero.getBoolValue()) {
1747 DAG.computeKnownBits(N1, RHSZero, RHSOne);
1749 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1750 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1751 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero)
1752 return CombineTo(N, DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N1),
1753 DAG.getNode(ISD::CARRY_FALSE,
1754 SDLoc(N), MVT::Glue));
1755 }
1757 return SDValue();
1758 }
1760 SDValue DAGCombiner::visitADDE(SDNode *N) {
1761 SDValue N0 = N->getOperand(0);
1762 SDValue N1 = N->getOperand(1);
1763 SDValue CarryIn = N->getOperand(2);
1764 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1765 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1767 // canonicalize constant to RHS
1768 if (N0C && !N1C)
1769 return DAG.getNode(ISD::ADDE, SDLoc(N), N->getVTList(),
1770 N1, N0, CarryIn);
1772 // fold (adde x, y, false) -> (addc x, y)
1773 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1774 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N0, N1);
1776 return SDValue();
1777 }
1779 // Since it may not be valid to emit a fold to zero for vector initializers
1780 // check if we can before folding.
1781 static SDValue tryFoldToZero(SDLoc DL, const TargetLowering &TLI, EVT VT,
1782 SelectionDAG &DAG,
1783 bool LegalOperations, bool LegalTypes) {
1784 if (!VT.isVector())
1785 return DAG.getConstant(0, VT);
1786 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
1787 return DAG.getConstant(0, VT);
1788 return SDValue();
1789 }
1791 SDValue DAGCombiner::visitSUB(SDNode *N) {
1792 SDValue N0 = N->getOperand(0);
1793 SDValue N1 = N->getOperand(1);
1794 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1795 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1796 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? nullptr :
1797 dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode());
1798 EVT VT = N0.getValueType();
1800 // fold vector ops
1801 if (VT.isVector()) {
1802 SDValue FoldedVOp = SimplifyVBinOp(N);
1803 if (FoldedVOp.getNode()) return FoldedVOp;
1805 // fold (sub x, 0) -> x, vector edition
1806 if (ISD::isBuildVectorAllZeros(N1.getNode()))
1807 return N0;
1808 }
1810 // fold (sub x, x) -> 0
1811 // FIXME: Refactor this and xor and other similar operations together.
1812 if (N0 == N1)
1813 return tryFoldToZero(SDLoc(N), TLI, VT, DAG, LegalOperations, LegalTypes);
1814 // fold (sub c1, c2) -> c1-c2
1815 if (N0C && N1C)
1816 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C);
1817 // fold (sub x, c) -> (add x, -c)
1818 if (N1C)
1819 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0,
1820 DAG.getConstant(-N1C->getAPIntValue(), VT));
1821 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
1822 if (N0C && N0C->isAllOnesValue())
1823 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0);
1824 // fold A-(A-B) -> B
1825 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
1826 return N1.getOperand(1);
1827 // fold (A+B)-A -> B
1828 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1829 return N0.getOperand(1);
1830 // fold (A+B)-B -> A
1831 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1832 return N0.getOperand(0);
1833 // fold C2-(A+C1) -> (C2-C1)-A
1834 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) {
1835 SDValue NewC = DAG.getConstant(N0C->getAPIntValue() - N1C1->getAPIntValue(),
1836 VT);
1837 return DAG.getNode(ISD::SUB, SDLoc(N), VT, NewC,
1838 N1.getOperand(0));
1839 }
1840 // fold ((A+(B+or-C))-B) -> A+or-C
1841 if (N0.getOpcode() == ISD::ADD &&
1842 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1843 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1844 N0.getOperand(1).getOperand(0) == N1)
1845 return DAG.getNode(N0.getOperand(1).getOpcode(), SDLoc(N), VT,
1846 N0.getOperand(0), N0.getOperand(1).getOperand(1));
1847 // fold ((A+(C+B))-B) -> A+C
1848 if (N0.getOpcode() == ISD::ADD &&
1849 N0.getOperand(1).getOpcode() == ISD::ADD &&
1850 N0.getOperand(1).getOperand(1) == N1)
1851 return DAG.getNode(ISD::ADD, SDLoc(N), VT,
1852 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1853 // fold ((A-(B-C))-C) -> A-B
1854 if (N0.getOpcode() == ISD::SUB &&
1855 N0.getOperand(1).getOpcode() == ISD::SUB &&
1856 N0.getOperand(1).getOperand(1) == N1)
1857 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1858 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1860 // If either operand of a sub is undef, the result is undef
1861 if (N0.getOpcode() == ISD::UNDEF)
1862 return N0;
1863 if (N1.getOpcode() == ISD::UNDEF)
1864 return N1;
1866 // If the relocation model supports it, consider symbol offsets.
1867 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1868 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
1869 // fold (sub Sym, c) -> Sym-c
1870 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
1871 return DAG.getGlobalAddress(GA->getGlobal(), SDLoc(N1C), VT,
1872 GA->getOffset() -
1873 (uint64_t)N1C->getSExtValue());
1874 // fold (sub Sym+c1, Sym+c2) -> c1-c2
1875 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
1876 if (GA->getGlobal() == GB->getGlobal())
1877 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
1878 VT);
1879 }
1881 // sub X, (sextinreg Y i1) -> add X, (and Y 1)
1882 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
1883 VTSDNode *TN = cast<VTSDNode>(N1.getOperand(1));
1884 if (TN->getVT() == MVT::i1) {
1885 SDLoc DL(N);
1886 SDValue ZExt = DAG.getNode(ISD::AND, DL, VT, N1.getOperand(0),
1887 DAG.getConstant(1, VT));
1888 return DAG.getNode(ISD::ADD, DL, VT, N0, ZExt);
1889 }
1890 }
1892 return SDValue();
1893 }
1895 SDValue DAGCombiner::visitSUBC(SDNode *N) {
1896 SDValue N0 = N->getOperand(0);
1897 SDValue N1 = N->getOperand(1);
1898 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1899 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1900 EVT VT = N0.getValueType();
1902 // If the flag result is dead, turn this into an SUB.
1903 if (!N->hasAnyUseOfValue(1))
1904 return CombineTo(N, DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, N1),
1905 DAG.getNode(ISD::CARRY_FALSE, SDLoc(N),
1906 MVT::Glue));
1908 // fold (subc x, x) -> 0 + no borrow
1909 if (N0 == N1)
1910 return CombineTo(N, DAG.getConstant(0, VT),
1911 DAG.getNode(ISD::CARRY_FALSE, SDLoc(N),
1912 MVT::Glue));
1914 // fold (subc x, 0) -> x + no borrow
1915 if (N1C && N1C->isNullValue())
1916 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, SDLoc(N),
1917 MVT::Glue));
1919 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow
1920 if (N0C && N0C->isAllOnesValue())
1921 return CombineTo(N, DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0),
1922 DAG.getNode(ISD::CARRY_FALSE, SDLoc(N),
1923 MVT::Glue));
1925 return SDValue();
1926 }
1928 SDValue DAGCombiner::visitSUBE(SDNode *N) {
1929 SDValue N0 = N->getOperand(0);
1930 SDValue N1 = N->getOperand(1);
1931 SDValue CarryIn = N->getOperand(2);
1933 // fold (sube x, y, false) -> (subc x, y)
1934 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1935 return DAG.getNode(ISD::SUBC, SDLoc(N), N->getVTList(), N0, N1);
1937 return SDValue();
1938 }
1940 SDValue DAGCombiner::visitMUL(SDNode *N) {
1941 SDValue N0 = N->getOperand(0);
1942 SDValue N1 = N->getOperand(1);
1943 EVT VT = N0.getValueType();
1945 // fold (mul x, undef) -> 0
1946 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1947 return DAG.getConstant(0, VT);
1949 bool N0IsConst = false;
1950 bool N1IsConst = false;
1951 APInt ConstValue0, ConstValue1;
1952 // fold vector ops
1953 if (VT.isVector()) {
1954 SDValue FoldedVOp = SimplifyVBinOp(N);
1955 if (FoldedVOp.getNode()) return FoldedVOp;
1957 N0IsConst = isConstantSplatVector(N0.getNode(), ConstValue0);
1958 N1IsConst = isConstantSplatVector(N1.getNode(), ConstValue1);
1959 } else {
1960 N0IsConst = dyn_cast<ConstantSDNode>(N0) != nullptr;
1961 ConstValue0 = N0IsConst ? (dyn_cast<ConstantSDNode>(N0))->getAPIntValue()
1962 : APInt();
1963 N1IsConst = dyn_cast<ConstantSDNode>(N1) != nullptr;
1964 ConstValue1 = N1IsConst ? (dyn_cast<ConstantSDNode>(N1))->getAPIntValue()
1965 : APInt();
1966 }
1968 // fold (mul c1, c2) -> c1*c2
1969 if (N0IsConst && N1IsConst)
1970 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0.getNode(), N1.getNode());
1972 // canonicalize constant to RHS
1973 if (N0IsConst && !N1IsConst)
1974 return DAG.getNode(ISD::MUL, SDLoc(N), VT, N1, N0);
1975 // fold (mul x, 0) -> 0
1976 if (N1IsConst && ConstValue1 == 0)
1977 return N1;
1978 // We require a splat of the entire scalar bit width for non-contiguous
1979 // bit patterns.
1980 bool IsFullSplat =
1981 ConstValue1.getBitWidth() == VT.getScalarType().getSizeInBits();
1982 // fold (mul x, 1) -> x
1983 if (N1IsConst && ConstValue1 == 1 && IsFullSplat)
1984 return N0;
1985 // fold (mul x, -1) -> 0-x
1986 if (N1IsConst && ConstValue1.isAllOnesValue())
1987 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1988 DAG.getConstant(0, VT), N0);
1989 // fold (mul x, (1 << c)) -> x << c
1990 if (N1IsConst && ConstValue1.isPowerOf2() && IsFullSplat)
1991 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0,
1992 DAG.getConstant(ConstValue1.logBase2(),
1993 getShiftAmountTy(N0.getValueType())));
1994 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1995 if (N1IsConst && (-ConstValue1).isPowerOf2() && IsFullSplat) {
1996 unsigned Log2Val = (-ConstValue1).logBase2();
1997 // FIXME: If the input is something that is easily negated (e.g. a
1998 // single-use add), we should put the negate there.
1999 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
2000 DAG.getConstant(0, VT),
2001 DAG.getNode(ISD::SHL, SDLoc(N), VT, N0,
2002 DAG.getConstant(Log2Val,
2003 getShiftAmountTy(N0.getValueType()))));
2004 }
2006 APInt Val;
2007 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
2008 if (N1IsConst && N0.getOpcode() == ISD::SHL &&
2009 (isConstantSplatVector(N0.getOperand(1).getNode(), Val) ||
2010 isa<ConstantSDNode>(N0.getOperand(1)))) {
2011 SDValue C3 = DAG.getNode(ISD::SHL, SDLoc(N), VT,
2012 N1, N0.getOperand(1));
2013 AddToWorklist(C3.getNode());
2014 return DAG.getNode(ISD::MUL, SDLoc(N), VT,
2015 N0.getOperand(0), C3);
2016 }
2018 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
2019 // use.
2020 {
2021 SDValue Sh(nullptr,0), Y(nullptr,0);
2022 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
2023 if (N0.getOpcode() == ISD::SHL &&
2024 (isConstantSplatVector(N0.getOperand(1).getNode(), Val) ||
2025 isa<ConstantSDNode>(N0.getOperand(1))) &&
2026 N0.getNode()->hasOneUse()) {
2027 Sh = N0; Y = N1;
2028 } else if (N1.getOpcode() == ISD::SHL &&
2029 isa<ConstantSDNode>(N1.getOperand(1)) &&
2030 N1.getNode()->hasOneUse()) {
2031 Sh = N1; Y = N0;
2032 }
2034 if (Sh.getNode()) {
2035 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT,
2036 Sh.getOperand(0), Y);
2037 return DAG.getNode(ISD::SHL, SDLoc(N), VT,
2038 Mul, Sh.getOperand(1));
2039 }
2040 }
2042 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
2043 if (N1IsConst && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
2044 (isConstantSplatVector(N0.getOperand(1).getNode(), Val) ||
2045 isa<ConstantSDNode>(N0.getOperand(1))))
2046 return DAG.getNode(ISD::ADD, SDLoc(N), VT,
2047 DAG.getNode(ISD::MUL, SDLoc(N0), VT,
2048 N0.getOperand(0), N1),
2049 DAG.getNode(ISD::MUL, SDLoc(N1), VT,
2050 N0.getOperand(1), N1));
2052 // reassociate mul
2053 SDValue RMUL = ReassociateOps(ISD::MUL, SDLoc(N), N0, N1);
2054 if (RMUL.getNode())
2055 return RMUL;
2057 return SDValue();
2058 }
2060 SDValue DAGCombiner::visitSDIV(SDNode *N) {
2061 SDValue N0 = N->getOperand(0);
2062 SDValue N1 = N->getOperand(1);
2063 ConstantSDNode *N0C = isConstOrConstSplat(N0);
2064 ConstantSDNode *N1C = isConstOrConstSplat(N1);
2065 EVT VT = N->getValueType(0);
2067 // fold vector ops
2068 if (VT.isVector()) {
2069 SDValue FoldedVOp = SimplifyVBinOp(N);
2070 if (FoldedVOp.getNode()) return FoldedVOp;
2071 }
2073 // fold (sdiv c1, c2) -> c1/c2
2074 if (N0C && N1C && !N1C->isNullValue())
2075 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
2076 // fold (sdiv X, 1) -> X
2077 if (N1C && N1C->getAPIntValue() == 1LL)
2078 return N0;
2079 // fold (sdiv X, -1) -> 0-X
2080 if (N1C && N1C->isAllOnesValue())
2081 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
2082 DAG.getConstant(0, VT), N0);
2083 // If we know the sign bits of both operands are zero, strength reduce to a
2084 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
2085 if (!VT.isVector()) {
2086 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
2087 return DAG.getNode(ISD::UDIV, SDLoc(N), N1.getValueType(),
2088 N0, N1);
2089 }
2091 // fold (sdiv X, pow2) -> simple ops after legalize
2092 if (N1C && !N1C->isNullValue() && (N1C->getAPIntValue().isPowerOf2() ||
2093 (-N1C->getAPIntValue()).isPowerOf2())) {
2094 // If dividing by powers of two is cheap, then don't perform the following
2095 // fold.
2096 if (TLI.isPow2SDivCheap())
2097 return SDValue();
2099 // Target-specific implementation of sdiv x, pow2.
2100 SDValue Res = BuildSDIVPow2(N);
2101 if (Res.getNode())
2102 return Res;
2104 unsigned lg2 = N1C->getAPIntValue().countTrailingZeros();
2106 // Splat the sign bit into the register
2107 SDValue SGN =
2108 DAG.getNode(ISD::SRA, SDLoc(N), VT, N0,
2109 DAG.getConstant(VT.getScalarSizeInBits() - 1,
2110 getShiftAmountTy(N0.getValueType())));
2111 AddToWorklist(SGN.getNode());
2113 // Add (N0 < 0) ? abs2 - 1 : 0;
2114 SDValue SRL =
2115 DAG.getNode(ISD::SRL, SDLoc(N), VT, SGN,
2116 DAG.getConstant(VT.getScalarSizeInBits() - lg2,
2117 getShiftAmountTy(SGN.getValueType())));
2118 SDValue ADD = DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, SRL);
2119 AddToWorklist(SRL.getNode());
2120 AddToWorklist(ADD.getNode()); // Divide by pow2
2121 SDValue SRA = DAG.getNode(ISD::SRA, SDLoc(N), VT, ADD,
2122 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType())));
2124 // If we're dividing by a positive value, we're done. Otherwise, we must
2125 // negate the result.
2126 if (N1C->getAPIntValue().isNonNegative())
2127 return SRA;
2129 AddToWorklist(SRA.getNode());
2130 return DAG.getNode(ISD::SUB, SDLoc(N), VT, DAG.getConstant(0, VT), SRA);
2131 }
2133 // if integer divide is expensive and we satisfy the requirements, emit an
2134 // alternate sequence.
2135 if (N1C && !TLI.isIntDivCheap()) {
2136 SDValue Op = BuildSDIV(N);
2137 if (Op.getNode()) return Op;
2138 }
2140 // undef / X -> 0
2141 if (N0.getOpcode() == ISD::UNDEF)
2142 return DAG.getConstant(0, VT);
2143 // X / undef -> undef
2144 if (N1.getOpcode() == ISD::UNDEF)
2145 return N1;
2147 return SDValue();
2148 }
2150 SDValue DAGCombiner::visitUDIV(SDNode *N) {
2151 SDValue N0 = N->getOperand(0);
2152 SDValue N1 = N->getOperand(1);
2153 ConstantSDNode *N0C = isConstOrConstSplat(N0);
2154 ConstantSDNode *N1C = isConstOrConstSplat(N1);
2155 EVT VT = N->getValueType(0);
2157 // fold vector ops
2158 if (VT.isVector()) {
2159 SDValue FoldedVOp = SimplifyVBinOp(N);
2160 if (FoldedVOp.getNode()) return FoldedVOp;
2161 }
2163 // fold (udiv c1, c2) -> c1/c2
2164 if (N0C && N1C && !N1C->isNullValue())
2165 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C);
2166 // fold (udiv x, (1 << c)) -> x >>u c
2167 if (N1C && N1C->getAPIntValue().isPowerOf2())
2168 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0,
2169 DAG.getConstant(N1C->getAPIntValue().logBase2(),
2170 getShiftAmountTy(N0.getValueType())));
2171 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
2172 if (N1.getOpcode() == ISD::SHL) {
2173 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
2174 if (SHC->getAPIntValue().isPowerOf2()) {
2175 EVT ADDVT = N1.getOperand(1).getValueType();
2176 SDValue Add = DAG.getNode(ISD::ADD, SDLoc(N), ADDVT,
2177 N1.getOperand(1),
2178 DAG.getConstant(SHC->getAPIntValue()
2179 .logBase2(),
2180 ADDVT));
2181 AddToWorklist(Add.getNode());
2182 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, Add);
2183 }
2184 }
2185 }
2186 // fold (udiv x, c) -> alternate
2187 if (N1C && !TLI.isIntDivCheap()) {
2188 SDValue Op = BuildUDIV(N);
2189 if (Op.getNode()) return Op;
2190 }
2192 // undef / X -> 0
2193 if (N0.getOpcode() == ISD::UNDEF)
2194 return DAG.getConstant(0, VT);
2195 // X / undef -> undef
2196 if (N1.getOpcode() == ISD::UNDEF)
2197 return N1;
2199 return SDValue();
2200 }
2202 SDValue DAGCombiner::visitSREM(SDNode *N) {
2203 SDValue N0 = N->getOperand(0);
2204 SDValue N1 = N->getOperand(1);
2205 ConstantSDNode *N0C = isConstOrConstSplat(N0);
2206 ConstantSDNode *N1C = isConstOrConstSplat(N1);
2207 EVT VT = N->getValueType(0);
2209 // fold (srem c1, c2) -> c1%c2
2210 if (N0C && N1C && !N1C->isNullValue())
2211 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C);
2212 // If we know the sign bits of both operands are zero, strength reduce to a
2213 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
2214 if (!VT.isVector()) {
2215 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
2216 return DAG.getNode(ISD::UREM, SDLoc(N), VT, N0, N1);
2217 }
2219 // If X/C can be simplified by the division-by-constant logic, lower
2220 // X%C to the equivalent of X-X/C*C.
2221 if (N1C && !N1C->isNullValue()) {
2222 SDValue Div = DAG.getNode(ISD::SDIV, SDLoc(N), VT, N0, N1);
2223 AddToWorklist(Div.getNode());
2224 SDValue OptimizedDiv = combine(Div.getNode());
2225 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
2226 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT,
2227 OptimizedDiv, N1);
2228 SDValue Sub = DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, Mul);
2229 AddToWorklist(Mul.getNode());
2230 return Sub;
2231 }
2232 }
2234 // undef % X -> 0
2235 if (N0.getOpcode() == ISD::UNDEF)
2236 return DAG.getConstant(0, VT);
2237 // X % undef -> undef
2238 if (N1.getOpcode() == ISD::UNDEF)
2239 return N1;
2241 return SDValue();
2242 }
2244 SDValue DAGCombiner::visitUREM(SDNode *N) {
2245 SDValue N0 = N->getOperand(0);
2246 SDValue N1 = N->getOperand(1);
2247 ConstantSDNode *N0C = isConstOrConstSplat(N0);
2248 ConstantSDNode *N1C = isConstOrConstSplat(N1);
2249 EVT VT = N->getValueType(0);
2251 // fold (urem c1, c2) -> c1%c2
2252 if (N0C && N1C && !N1C->isNullValue())
2253 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C);
2254 // fold (urem x, pow2) -> (and x, pow2-1)
2255 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2())
2256 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0,
2257 DAG.getConstant(N1C->getAPIntValue()-1,VT));
2258 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
2259 if (N1.getOpcode() == ISD::SHL) {
2260 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
2261 if (SHC->getAPIntValue().isPowerOf2()) {
2262 SDValue Add =
2263 DAG.getNode(ISD::ADD, SDLoc(N), VT, N1,
2264 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
2265 VT));
2266 AddToWorklist(Add.getNode());
2267 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0, Add);
2268 }
2269 }
2270 }
2272 // If X/C can be simplified by the division-by-constant logic, lower
2273 // X%C to the equivalent of X-X/C*C.
2274 if (N1C && !N1C->isNullValue()) {
2275 SDValue Div = DAG.getNode(ISD::UDIV, SDLoc(N), VT, N0, N1);
2276 AddToWorklist(Div.getNode());
2277 SDValue OptimizedDiv = combine(Div.getNode());
2278 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
2279 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT,
2280 OptimizedDiv, N1);
2281 SDValue Sub = DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, Mul);
2282 AddToWorklist(Mul.getNode());
2283 return Sub;
2284 }
2285 }
2287 // undef % X -> 0
2288 if (N0.getOpcode() == ISD::UNDEF)
2289 return DAG.getConstant(0, VT);
2290 // X % undef -> undef
2291 if (N1.getOpcode() == ISD::UNDEF)
2292 return N1;
2294 return SDValue();
2295 }
2297 SDValue DAGCombiner::visitMULHS(SDNode *N) {
2298 SDValue N0 = N->getOperand(0);
2299 SDValue N1 = N->getOperand(1);
2300 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2301 EVT VT = N->getValueType(0);
2302 SDLoc DL(N);
2304 // fold (mulhs x, 0) -> 0
2305 if (N1C && N1C->isNullValue())
2306 return N1;
2307 // fold (mulhs x, 1) -> (sra x, size(x)-1)
2308 if (N1C && N1C->getAPIntValue() == 1)
2309 return DAG.getNode(ISD::SRA, SDLoc(N), N0.getValueType(), N0,
2310 DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
2311 getShiftAmountTy(N0.getValueType())));
2312 // fold (mulhs x, undef) -> 0
2313 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2314 return DAG.getConstant(0, VT);
2316 // If the type twice as wide is legal, transform the mulhs to a wider multiply
2317 // plus a shift.
2318 if (VT.isSimple() && !VT.isVector()) {
2319 MVT Simple = VT.getSimpleVT();
2320 unsigned SimpleSize = Simple.getSizeInBits();
2321 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2322 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2323 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
2324 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
2325 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2326 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2327 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2328 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2329 }
2330 }
2332 return SDValue();
2333 }
2335 SDValue DAGCombiner::visitMULHU(SDNode *N) {
2336 SDValue N0 = N->getOperand(0);
2337 SDValue N1 = N->getOperand(1);
2338 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2339 EVT VT = N->getValueType(0);
2340 SDLoc DL(N);
2342 // fold (mulhu x, 0) -> 0
2343 if (N1C && N1C->isNullValue())
2344 return N1;
2345 // fold (mulhu x, 1) -> 0
2346 if (N1C && N1C->getAPIntValue() == 1)
2347 return DAG.getConstant(0, N0.getValueType());
2348 // fold (mulhu x, undef) -> 0
2349 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2350 return DAG.getConstant(0, VT);
2352 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2353 // plus a shift.
2354 if (VT.isSimple() && !VT.isVector()) {
2355 MVT Simple = VT.getSimpleVT();
2356 unsigned SimpleSize = Simple.getSizeInBits();
2357 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2358 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2359 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
2360 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1);
2361 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2362 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2363 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2364 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2365 }
2366 }
2368 return SDValue();
2369 }
2371 /// Perform optimizations common to nodes that compute two values. LoOp and HiOp
2372 /// give the opcodes for the two computations that are being performed. Return
2373 /// true if a simplification was made.
2374 SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
2375 unsigned HiOp) {
2376 // If the high half is not needed, just compute the low half.
2377 bool HiExists = N->hasAnyUseOfValue(1);
2378 if (!HiExists &&
2379 (!LegalOperations ||
2380 TLI.isOperationLegalOrCustom(LoOp, N->getValueType(0)))) {
2381 SDValue Res = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0), N->ops());
2382 return CombineTo(N, Res, Res);
2383 }
2385 // If the low half is not needed, just compute the high half.
2386 bool LoExists = N->hasAnyUseOfValue(0);
2387 if (!LoExists &&
2388 (!LegalOperations ||
2389 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
2390 SDValue Res = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1), N->ops());
2391 return CombineTo(N, Res, Res);
2392 }
2394 // If both halves are used, return as it is.
2395 if (LoExists && HiExists)
2396 return SDValue();
2398 // If the two computed results can be simplified separately, separate them.
2399 if (LoExists) {
2400 SDValue Lo = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0), N->ops());
2401 AddToWorklist(Lo.getNode());
2402 SDValue LoOpt = combine(Lo.getNode());
2403 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
2404 (!LegalOperations ||
2405 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
2406 return CombineTo(N, LoOpt, LoOpt);
2407 }
2409 if (HiExists) {
2410 SDValue Hi = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1), N->ops());
2411 AddToWorklist(Hi.getNode());
2412 SDValue HiOpt = combine(Hi.getNode());
2413 if (HiOpt.getNode() && HiOpt != Hi &&
2414 (!LegalOperations ||
2415 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
2416 return CombineTo(N, HiOpt, HiOpt);
2417 }
2419 return SDValue();
2420 }
2422 SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
2423 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
2424 if (Res.getNode()) return Res;
2426 EVT VT = N->getValueType(0);
2427 SDLoc DL(N);
2429 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2430 // plus a shift.
2431 if (VT.isSimple() && !VT.isVector()) {
2432 MVT Simple = VT.getSimpleVT();
2433 unsigned SimpleSize = Simple.getSizeInBits();
2434 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2435 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2436 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0));
2437 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1));
2438 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2439 // Compute the high part as N1.
2440 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2441 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2442 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2443 // Compute the low part as N0.
2444 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2445 return CombineTo(N, Lo, Hi);
2446 }
2447 }
2449 return SDValue();
2450 }
2452 SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
2453 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
2454 if (Res.getNode()) return Res;
2456 EVT VT = N->getValueType(0);
2457 SDLoc DL(N);
2459 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2460 // plus a shift.
2461 if (VT.isSimple() && !VT.isVector()) {
2462 MVT Simple = VT.getSimpleVT();
2463 unsigned SimpleSize = Simple.getSizeInBits();
2464 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2465 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2466 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0));
2467 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1));
2468 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2469 // Compute the high part as N1.
2470 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2471 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2472 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2473 // Compute the low part as N0.
2474 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2475 return CombineTo(N, Lo, Hi);
2476 }
2477 }
2479 return SDValue();
2480 }
2482 SDValue DAGCombiner::visitSMULO(SDNode *N) {
2483 // (smulo x, 2) -> (saddo x, x)
2484 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2485 if (C2->getAPIntValue() == 2)
2486 return DAG.getNode(ISD::SADDO, SDLoc(N), N->getVTList(),
2487 N->getOperand(0), N->getOperand(0));
2489 return SDValue();
2490 }
2492 SDValue DAGCombiner::visitUMULO(SDNode *N) {
2493 // (umulo x, 2) -> (uaddo x, x)
2494 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2495 if (C2->getAPIntValue() == 2)
2496 return DAG.getNode(ISD::UADDO, SDLoc(N), N->getVTList(),
2497 N->getOperand(0), N->getOperand(0));
2499 return SDValue();
2500 }
2502 SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
2503 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
2504 if (Res.getNode()) return Res;
2506 return SDValue();
2507 }
2509 SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
2510 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
2511 if (Res.getNode()) return Res;
2513 return SDValue();
2514 }
2516 /// If this is a binary operator with two operands of the same opcode, try to
2517 /// simplify it.
2518 SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
2519 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2520 EVT VT = N0.getValueType();
2521 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
2523 // Bail early if none of these transforms apply.
2524 if (N0.getNode()->getNumOperands() == 0) return SDValue();
2526 // For each of OP in AND/OR/XOR:
2527 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
2528 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
2529 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
2530 // fold (OP (bswap x), (bswap y)) -> (bswap (OP x, y))
2531 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free)
2532 //
2533 // do not sink logical op inside of a vector extend, since it may combine
2534 // into a vsetcc.
2535 EVT Op0VT = N0.getOperand(0).getValueType();
2536 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
2537 N0.getOpcode() == ISD::SIGN_EXTEND ||
2538 N0.getOpcode() == ISD::BSWAP ||
2539 // Avoid infinite looping with PromoteIntBinOp.
2540 (N0.getOpcode() == ISD::ANY_EXTEND &&
2541 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) ||
2542 (N0.getOpcode() == ISD::TRUNCATE &&
2543 (!TLI.isZExtFree(VT, Op0VT) ||
2544 !TLI.isTruncateFree(Op0VT, VT)) &&
2545 TLI.isTypeLegal(Op0VT))) &&
2546 !VT.isVector() &&
2547 Op0VT == N1.getOperand(0).getValueType() &&
2548 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) {
2549 SDValue ORNode = DAG.getNode(N->getOpcode(), SDLoc(N0),
2550 N0.getOperand(0).getValueType(),
2551 N0.getOperand(0), N1.getOperand(0));
2552 AddToWorklist(ORNode.getNode());
2553 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, ORNode);
2554 }
2556 // For each of OP in SHL/SRL/SRA/AND...
2557 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
2558 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
2559 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
2560 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
2561 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
2562 N0.getOperand(1) == N1.getOperand(1)) {
2563 SDValue ORNode = DAG.getNode(N->getOpcode(), SDLoc(N0),
2564 N0.getOperand(0).getValueType(),
2565 N0.getOperand(0), N1.getOperand(0));
2566 AddToWorklist(ORNode.getNode());
2567 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
2568 ORNode, N0.getOperand(1));
2569 }
2571 // Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B))
2572 // Only perform this optimization after type legalization and before
2573 // LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by
2574 // adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and
2575 // we don't want to undo this promotion.
2576 // We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper
2577 // on scalars.
2578 if ((N0.getOpcode() == ISD::BITCAST ||
2579 N0.getOpcode() == ISD::SCALAR_TO_VECTOR) &&
2580 Level == AfterLegalizeTypes) {
2581 SDValue In0 = N0.getOperand(0);
2582 SDValue In1 = N1.getOperand(0);
2583 EVT In0Ty = In0.getValueType();
2584 EVT In1Ty = In1.getValueType();
2585 SDLoc DL(N);
2586 // If both incoming values are integers, and the original types are the
2587 // same.
2588 if (In0Ty.isInteger() && In1Ty.isInteger() && In0Ty == In1Ty) {
2589 SDValue Op = DAG.getNode(N->getOpcode(), DL, In0Ty, In0, In1);
2590 SDValue BC = DAG.getNode(N0.getOpcode(), DL, VT, Op);
2591 AddToWorklist(Op.getNode());
2592 return BC;
2593 }
2594 }
2596 // Xor/and/or are indifferent to the swizzle operation (shuffle of one value).
2597 // Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A,B))
2598 // If both shuffles use the same mask, and both shuffle within a single
2599 // vector, then it is worthwhile to move the swizzle after the operation.
2600 // The type-legalizer generates this pattern when loading illegal
2601 // vector types from memory. In many cases this allows additional shuffle
2602 // optimizations.
2603 // There are other cases where moving the shuffle after the xor/and/or
2604 // is profitable even if shuffles don't perform a swizzle.
2605 // If both shuffles use the same mask, and both shuffles have the same first
2606 // or second operand, then it might still be profitable to move the shuffle
2607 // after the xor/and/or operation.
2608 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG) {
2609 ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(N0);
2610 ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(N1);
2612 assert(N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType() &&
2613 "Inputs to shuffles are not the same type");
2615 // Check that both shuffles use the same mask. The masks are known to be of
2616 // the same length because the result vector type is the same.
2617 // Check also that shuffles have only one use to avoid introducing extra
2618 // instructions.
2619 if (SVN0->hasOneUse() && SVN1->hasOneUse() &&
2620 SVN0->getMask().equals(SVN1->getMask())) {
2621 SDValue ShOp = N0->getOperand(1);
2623 // Don't try to fold this node if it requires introducing a
2624 // build vector of all zeros that might be illegal at this stage.
2625 if (N->getOpcode() == ISD::XOR && ShOp.getOpcode() != ISD::UNDEF) {
2626 if (!LegalTypes)
2627 ShOp = DAG.getConstant(0, VT);
2628 else
2629 ShOp = SDValue();
2630 }
2632 // (AND (shuf (A, C), shuf (B, C)) -> shuf (AND (A, B), C)
2633 // (OR (shuf (A, C), shuf (B, C)) -> shuf (OR (A, B), C)
2634 // (XOR (shuf (A, C), shuf (B, C)) -> shuf (XOR (A, B), V_0)
2635 if (N0.getOperand(1) == N1.getOperand(1) && ShOp.getNode()) {
2636 SDValue NewNode = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
2637 N0->getOperand(0), N1->getOperand(0));
2638 AddToWorklist(NewNode.getNode());
2639 return DAG.getVectorShuffle(VT, SDLoc(N), NewNode, ShOp,
2640 &SVN0->getMask()[0]);
2641 }
2643 // Don't try to fold this node if it requires introducing a
2644 // build vector of all zeros that might be illegal at this stage.
2645 ShOp = N0->getOperand(0);
2646 if (N->getOpcode() == ISD::XOR && ShOp.getOpcode() != ISD::UNDEF) {
2647 if (!LegalTypes)
2648 ShOp = DAG.getConstant(0, VT);
2649 else
2650 ShOp = SDValue();
2651 }
2653 // (AND (shuf (C, A), shuf (C, B)) -> shuf (C, AND (A, B))
2654 // (OR (shuf (C, A), shuf (C, B)) -> shuf (C, OR (A, B))
2655 // (XOR (shuf (C, A), shuf (C, B)) -> shuf (V_0, XOR (A, B))
2656 if (N0->getOperand(0) == N1->getOperand(0) && ShOp.getNode()) {
2657 SDValue NewNode = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
2658 N0->getOperand(1), N1->getOperand(1));
2659 AddToWorklist(NewNode.getNode());
2660 return DAG.getVectorShuffle(VT, SDLoc(N), ShOp, NewNode,
2661 &SVN0->getMask()[0]);
2662 }
2663 }
2664 }
2666 return SDValue();
2667 }
2669 SDValue DAGCombiner::visitAND(SDNode *N) {
2670 SDValue N0 = N->getOperand(0);
2671 SDValue N1 = N->getOperand(1);
2672 SDValue LL, LR, RL, RR, CC0, CC1;
2673 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2674 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2675 EVT VT = N1.getValueType();
2676 unsigned BitWidth = VT.getScalarType().getSizeInBits();
2678 // fold vector ops
2679 if (VT.isVector()) {
2680 SDValue FoldedVOp = SimplifyVBinOp(N);
2681 if (FoldedVOp.getNode()) return FoldedVOp;
2683 // fold (and x, 0) -> 0, vector edition
2684 if (ISD::isBuildVectorAllZeros(N0.getNode()))
2685 // do not return N0, because undef node may exist in N0
2686 return DAG.getConstant(
2687 APInt::getNullValue(
2688 N0.getValueType().getScalarType().getSizeInBits()),
2689 N0.getValueType());
2690 if (ISD::isBuildVectorAllZeros(N1.getNode()))
2691 // do not return N1, because undef node may exist in N1
2692 return DAG.getConstant(
2693 APInt::getNullValue(
2694 N1.getValueType().getScalarType().getSizeInBits()),
2695 N1.getValueType());
2697 // fold (and x, -1) -> x, vector edition
2698 if (ISD::isBuildVectorAllOnes(N0.getNode()))
2699 return N1;
2700 if (ISD::isBuildVectorAllOnes(N1.getNode()))
2701 return N0;
2702 }
2704 // fold (and x, undef) -> 0
2705 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2706 return DAG.getConstant(0, VT);
2707 // fold (and c1, c2) -> c1&c2
2708 if (N0C && N1C)
2709 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C);
2710 // canonicalize constant to RHS
2711 if (N0C && !N1C)
2712 return DAG.getNode(ISD::AND, SDLoc(N), VT, N1, N0);
2713 // fold (and x, -1) -> x
2714 if (N1C && N1C->isAllOnesValue())
2715 return N0;
2716 // if (and x, c) is known to be zero, return 0
2717 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
2718 APInt::getAllOnesValue(BitWidth)))
2719 return DAG.getConstant(0, VT);
2720 // reassociate and
2721 SDValue RAND = ReassociateOps(ISD::AND, SDLoc(N), N0, N1);
2722 if (RAND.getNode())
2723 return RAND;
2724 // fold (and (or x, C), D) -> D if (C & D) == D
2725 if (N1C && N0.getOpcode() == ISD::OR)
2726 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2727 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
2728 return N1;
2729 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
2730 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2731 SDValue N0Op0 = N0.getOperand(0);
2732 APInt Mask = ~N1C->getAPIntValue();
2733 Mask = Mask.trunc(N0Op0.getValueSizeInBits());
2734 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
2735 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N),
2736 N0.getValueType(), N0Op0);
2738 // Replace uses of the AND with uses of the Zero extend node.
2739 CombineTo(N, Zext);
2741 // We actually want to replace all uses of the any_extend with the
2742 // zero_extend, to avoid duplicating things. This will later cause this
2743 // AND to be folded.
2744 CombineTo(N0.getNode(), Zext);
2745 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2746 }
2747 }
2748 // similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) ->
2749 // (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must
2750 // already be zero by virtue of the width of the base type of the load.
2751 //
2752 // the 'X' node here can either be nothing or an extract_vector_elt to catch
2753 // more cases.
2754 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
2755 N0.getOperand(0).getOpcode() == ISD::LOAD) ||
2756 N0.getOpcode() == ISD::LOAD) {
2757 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ?
2758 N0 : N0.getOperand(0) );
2760 // Get the constant (if applicable) the zero'th operand is being ANDed with.
2761 // This can be a pure constant or a vector splat, in which case we treat the
2762 // vector as a scalar and use the splat value.
2763 APInt Constant = APInt::getNullValue(1);
2764 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
2765 Constant = C->getAPIntValue();
2766 } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) {
2767 APInt SplatValue, SplatUndef;
2768 unsigned SplatBitSize;
2769 bool HasAnyUndefs;
2770 bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef,
2771 SplatBitSize, HasAnyUndefs);
2772 if (IsSplat) {
2773 // Undef bits can contribute to a possible optimisation if set, so
2774 // set them.
2775 SplatValue |= SplatUndef;
2777 // The splat value may be something like "0x00FFFFFF", which means 0 for
2778 // the first vector value and FF for the rest, repeating. We need a mask
2779 // that will apply equally to all members of the vector, so AND all the
2780 // lanes of the constant together.
2781 EVT VT = Vector->getValueType(0);
2782 unsigned BitWidth = VT.getVectorElementType().getSizeInBits();
2784 // If the splat value has been compressed to a bitlength lower
2785 // than the size of the vector lane, we need to re-expand it to
2786 // the lane size.
2787 if (BitWidth > SplatBitSize)
2788 for (SplatValue = SplatValue.zextOrTrunc(BitWidth);
2789 SplatBitSize < BitWidth;
2790 SplatBitSize = SplatBitSize * 2)
2791 SplatValue |= SplatValue.shl(SplatBitSize);
2793 Constant = APInt::getAllOnesValue(BitWidth);
2794 for (unsigned i = 0, n = SplatBitSize/BitWidth; i < n; ++i)
2795 Constant &= SplatValue.lshr(i*BitWidth).zextOrTrunc(BitWidth);
2796 }
2797 }
2799 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is
2800 // actually legal and isn't going to get expanded, else this is a false
2801 // optimisation.
2802 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD,
2803 Load->getValueType(0),
2804 Load->getMemoryVT());
2806 // Resize the constant to the same size as the original memory access before
2807 // extension. If it is still the AllOnesValue then this AND is completely
2808 // unneeded.
2809 Constant =
2810 Constant.zextOrTrunc(Load->getMemoryVT().getScalarType().getSizeInBits());
2812 bool B;
2813 switch (Load->getExtensionType()) {
2814 default: B = false; break;
2815 case ISD::EXTLOAD: B = CanZextLoadProfitably; break;
2816 case ISD::ZEXTLOAD:
2817 case ISD::NON_EXTLOAD: B = true; break;
2818 }
2820 if (B && Constant.isAllOnesValue()) {
2821 // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to
2822 // preserve semantics once we get rid of the AND.
2823 SDValue NewLoad(Load, 0);
2824 if (Load->getExtensionType() == ISD::EXTLOAD) {
2825 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD,
2826 Load->getValueType(0), SDLoc(Load),
2827 Load->getChain(), Load->getBasePtr(),
2828 Load->getOffset(), Load->getMemoryVT(),
2829 Load->getMemOperand());
2830 // Replace uses of the EXTLOAD with the new ZEXTLOAD.
2831 if (Load->getNumValues() == 3) {
2832 // PRE/POST_INC loads have 3 values.
2833 SDValue To[] = { NewLoad.getValue(0), NewLoad.getValue(1),
2834 NewLoad.getValue(2) };
2835 CombineTo(Load, To, 3, true);
2836 } else {
2837 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1));
2838 }
2839 }
2841 // Fold the AND away, taking care not to fold to the old load node if we
2842 // replaced it.
2843 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0);
2845 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2846 }
2847 }
2848 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
2849 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2850 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2851 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2853 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2854 LL.getValueType().isInteger()) {
2855 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
2856 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
2857 SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(N0),
2858 LR.getValueType(), LL, RL);
2859 AddToWorklist(ORNode.getNode());
2860 return DAG.getSetCC(SDLoc(N), VT, ORNode, LR, Op1);
2861 }
2862 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
2863 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
2864 SDValue ANDNode = DAG.getNode(ISD::AND, SDLoc(N0),
2865 LR.getValueType(), LL, RL);
2866 AddToWorklist(ANDNode.getNode());
2867 return DAG.getSetCC(SDLoc(N), VT, ANDNode, LR, Op1);
2868 }
2869 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1)
2870 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
2871 SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(N0),
2872 LR.getValueType(), LL, RL);
2873 AddToWorklist(ORNode.getNode());
2874 return DAG.getSetCC(SDLoc(N), VT, ORNode, LR, Op1);
2875 }
2876 }
2877 // Simplify (and (setne X, 0), (setne X, -1)) -> (setuge (add X, 1), 2)
2878 if (LL == RL && isa<ConstantSDNode>(LR) && isa<ConstantSDNode>(RR) &&
2879 Op0 == Op1 && LL.getValueType().isInteger() &&
2880 Op0 == ISD::SETNE && ((cast<ConstantSDNode>(LR)->isNullValue() &&
2881 cast<ConstantSDNode>(RR)->isAllOnesValue()) ||
2882 (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
2883 cast<ConstantSDNode>(RR)->isNullValue()))) {
2884 SDValue ADDNode = DAG.getNode(ISD::ADD, SDLoc(N0), LL.getValueType(),
2885 LL, DAG.getConstant(1, LL.getValueType()));
2886 AddToWorklist(ADDNode.getNode());
2887 return DAG.getSetCC(SDLoc(N), VT, ADDNode,
2888 DAG.getConstant(2, LL.getValueType()), ISD::SETUGE);
2889 }
2890 // canonicalize equivalent to ll == rl
2891 if (LL == RR && LR == RL) {
2892 Op1 = ISD::getSetCCSwappedOperands(Op1);
2893 std::swap(RL, RR);
2894 }
2895 if (LL == RL && LR == RR) {
2896 bool isInteger = LL.getValueType().isInteger();
2897 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
2898 if (Result != ISD::SETCC_INVALID &&
2899 (!LegalOperations ||
2900 (TLI.isCondCodeLegal(Result, LL.getSimpleValueType()) &&
2901 TLI.isOperationLegal(ISD::SETCC,
2902 getSetCCResultType(N0.getSimpleValueType())))))
2903 return DAG.getSetCC(SDLoc(N), N0.getValueType(),
2904 LL, LR, Result);
2905 }
2906 }
2908 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
2909 if (N0.getOpcode() == N1.getOpcode()) {
2910 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2911 if (Tmp.getNode()) return Tmp;
2912 }
2914 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
2915 // fold (and (sra)) -> (and (srl)) when possible.
2916 if (!VT.isVector() &&
2917 SimplifyDemandedBits(SDValue(N, 0)))
2918 return SDValue(N, 0);
2920 // fold (zext_inreg (extload x)) -> (zextload x)
2921 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
2922 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2923 EVT MemVT = LN0->getMemoryVT();
2924 // If we zero all the possible extended bits, then we can turn this into
2925 // a zextload if we are running before legalize or the operation is legal.
2926 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2927 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2928 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2929 ((!LegalOperations && !LN0->isVolatile()) ||
2930 TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, MemVT))) {
2931 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT,
2932 LN0->getChain(), LN0->getBasePtr(),
2933 MemVT, LN0->getMemOperand());
2934 AddToWorklist(N);
2935 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2936 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2937 }
2938 }
2939 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
2940 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
2941 N0.hasOneUse()) {
2942 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2943 EVT MemVT = LN0->getMemoryVT();
2944 // If we zero all the possible extended bits, then we can turn this into
2945 // a zextload if we are running before legalize or the operation is legal.
2946 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2947 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2948 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2949 ((!LegalOperations && !LN0->isVolatile()) ||
2950 TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, MemVT))) {
2951 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT,
2952 LN0->getChain(), LN0->getBasePtr(),
2953 MemVT, LN0->getMemOperand());
2954 AddToWorklist(N);
2955 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2956 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2957 }
2958 }
2960 // fold (and (load x), 255) -> (zextload x, i8)
2961 // fold (and (extload x, i16), 255) -> (zextload x, i8)
2962 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8)
2963 if (N1C && (N0.getOpcode() == ISD::LOAD ||
2964 (N0.getOpcode() == ISD::ANY_EXTEND &&
2965 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
2966 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND;
2967 LoadSDNode *LN0 = HasAnyExt
2968 ? cast<LoadSDNode>(N0.getOperand(0))
2969 : cast<LoadSDNode>(N0);
2970 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
2971 LN0->isUnindexed() && N0.hasOneUse() && SDValue(LN0, 0).hasOneUse()) {
2972 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
2973 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){
2974 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
2975 EVT LoadedVT = LN0->getMemoryVT();
2976 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2978 if (ExtVT == LoadedVT &&
2979 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy,
2980 ExtVT))) {
2982 SDValue NewLoad =
2983 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), LoadResultTy,
2984 LN0->getChain(), LN0->getBasePtr(), ExtVT,
2985 LN0->getMemOperand());
2986 AddToWorklist(N);
2987 CombineTo(LN0, NewLoad, NewLoad.getValue(1));
2988 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2989 }
2991 // Do not change the width of a volatile load.
2992 // Do not generate loads of non-round integer types since these can
2993 // be expensive (and would be wrong if the type is not byte sized).
2994 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
2995 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy,
2996 ExtVT))) {
2997 EVT PtrType = LN0->getOperand(1).getValueType();
2999 unsigned Alignment = LN0->getAlignment();
3000 SDValue NewPtr = LN0->getBasePtr();
3002 // For big endian targets, we need to add an offset to the pointer
3003 // to load the correct bytes. For little endian systems, we merely
3004 // need to read fewer bytes from the same pointer.
3005 if (TLI.isBigEndian()) {
3006 unsigned LVTStoreBytes = LoadedVT.getStoreSize();
3007 unsigned EVTStoreBytes = ExtVT.getStoreSize();
3008 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
3009 NewPtr = DAG.getNode(ISD::ADD, SDLoc(LN0), PtrType,
3010 NewPtr, DAG.getConstant(PtrOff, PtrType));
3011 Alignment = MinAlign(Alignment, PtrOff);
3012 }
3014 AddToWorklist(NewPtr.getNode());
3016 SDValue Load =
3017 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), LoadResultTy,
3018 LN0->getChain(), NewPtr,
3019 LN0->getPointerInfo(),
3020 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
3021 LN0->isInvariant(), Alignment, LN0->getAAInfo());
3022 AddToWorklist(N);
3023 CombineTo(LN0, Load, Load.getValue(1));
3024 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3025 }
3026 }
3027 }
3028 }
3030 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
3031 VT.getSizeInBits() <= 64) {
3032 if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3033 APInt ADDC = ADDI->getAPIntValue();
3034 if (!TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
3035 // Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal
3036 // immediate for an add, but it is legal if its top c2 bits are set,
3037 // transform the ADD so the immediate doesn't need to be materialized
3038 // in a register.
3039 if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) {
3040 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
3041 SRLI->getZExtValue());
3042 if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) {
3043 ADDC |= Mask;
3044 if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
3045 SDValue NewAdd =
3046 DAG.getNode(ISD::ADD, SDLoc(N0), VT,
3047 N0.getOperand(0), DAG.getConstant(ADDC, VT));
3048 CombineTo(N0.getNode(), NewAdd);
3049 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3050 }
3051 }
3052 }
3053 }
3054 }
3055 }
3057 // fold (and (or (srl N, 8), (shl N, 8)), 0xffff) -> (srl (bswap N), const)
3058 if (N1C && N1C->getAPIntValue() == 0xffff && N0.getOpcode() == ISD::OR) {
3059 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
3060 N0.getOperand(1), false);
3061 if (BSwap.getNode())
3062 return BSwap;
3063 }
3065 return SDValue();
3066 }
3068 /// Match (a >> 8) | (a << 8) as (bswap a) >> 16.
3069 SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
3070 bool DemandHighBits) {
3071 if (!LegalOperations)
3072 return SDValue();
3074 EVT VT = N->getValueType(0);
3075 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16)
3076 return SDValue();
3077 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
3078 return SDValue();
3080 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00)
3081 bool LookPassAnd0 = false;
3082 bool LookPassAnd1 = false;
3083 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
3084 std::swap(N0, N1);
3085 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL)
3086 std::swap(N0, N1);
3087 if (N0.getOpcode() == ISD::AND) {
3088 if (!N0.getNode()->hasOneUse())
3089 return SDValue();
3090 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3091 if (!N01C || N01C->getZExtValue() != 0xFF00)
3092 return SDValue();
3093 N0 = N0.getOperand(0);
3094 LookPassAnd0 = true;
3095 }
3097 if (N1.getOpcode() == ISD::AND) {
3098 if (!N1.getNode()->hasOneUse())
3099 return SDValue();
3100 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
3101 if (!N11C || N11C->getZExtValue() != 0xFF)
3102 return SDValue();
3103 N1 = N1.getOperand(0);
3104 LookPassAnd1 = true;
3105 }
3107 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
3108 std::swap(N0, N1);
3109 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
3110 return SDValue();
3111 if (!N0.getNode()->hasOneUse() ||
3112 !N1.getNode()->hasOneUse())
3113 return SDValue();
3115 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3116 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
3117 if (!N01C || !N11C)
3118 return SDValue();
3119 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8)
3120 return SDValue();
3122 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8)
3123 SDValue N00 = N0->getOperand(0);
3124 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) {
3125 if (!N00.getNode()->hasOneUse())
3126 return SDValue();
3127 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1));
3128 if (!N001C || N001C->getZExtValue() != 0xFF)
3129 return SDValue();
3130 N00 = N00.getOperand(0);
3131 LookPassAnd0 = true;
3132 }
3134 SDValue N10 = N1->getOperand(0);
3135 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) {
3136 if (!N10.getNode()->hasOneUse())
3137 return SDValue();
3138 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1));
3139 if (!N101C || N101C->getZExtValue() != 0xFF00)
3140 return SDValue();
3141 N10 = N10.getOperand(0);
3142 LookPassAnd1 = true;
3143 }
3145 if (N00 != N10)
3146 return SDValue();
3148 // Make sure everything beyond the low halfword gets set to zero since the SRL
3149 // 16 will clear the top bits.
3150 unsigned OpSizeInBits = VT.getSizeInBits();
3151 if (DemandHighBits && OpSizeInBits > 16) {
3152 // If the left-shift isn't masked out then the only way this is a bswap is
3153 // if all bits beyond the low 8 are 0. In that case the entire pattern
3154 // reduces to a left shift anyway: leave it for other parts of the combiner.
3155 if (!LookPassAnd0)
3156 return SDValue();
3158 // However, if the right shift isn't masked out then it might be because
3159 // it's not needed. See if we can spot that too.
3160 if (!LookPassAnd1 &&
3161 !DAG.MaskedValueIsZero(
3162 N10, APInt::getHighBitsSet(OpSizeInBits, OpSizeInBits - 16)))
3163 return SDValue();
3164 }
3166 SDValue Res = DAG.getNode(ISD::BSWAP, SDLoc(N), VT, N00);
3167 if (OpSizeInBits > 16)
3168 Res = DAG.getNode(ISD::SRL, SDLoc(N), VT, Res,
3169 DAG.getConstant(OpSizeInBits-16, getShiftAmountTy(VT)));
3170 return Res;
3171 }
3173 /// Return true if the specified node is an element that makes up a 32-bit
3174 /// packed halfword byteswap.
3175 /// ((x & 0x000000ff) << 8) |
3176 /// ((x & 0x0000ff00) >> 8) |
3177 /// ((x & 0x00ff0000) << 8) |
3178 /// ((x & 0xff000000) >> 8)
3179 static bool isBSwapHWordElement(SDValue N, MutableArrayRef<SDNode *> Parts) {
3180 if (!N.getNode()->hasOneUse())
3181 return false;
3183 unsigned Opc = N.getOpcode();
3184 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
3185 return false;
3187 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1));
3188 if (!N1C)
3189 return false;
3191 unsigned Num;
3192 switch (N1C->getZExtValue()) {
3193 default:
3194 return false;
3195 case 0xFF: Num = 0; break;
3196 case 0xFF00: Num = 1; break;
3197 case 0xFF0000: Num = 2; break;
3198 case 0xFF000000: Num = 3; break;
3199 }
3201 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00).
3202 SDValue N0 = N.getOperand(0);
3203 if (Opc == ISD::AND) {
3204 if (Num == 0 || Num == 2) {
3205 // (x >> 8) & 0xff
3206 // (x >> 8) & 0xff0000
3207 if (N0.getOpcode() != ISD::SRL)
3208 return false;
3209 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3210 if (!C || C->getZExtValue() != 8)
3211 return false;
3212 } else {
3213 // (x << 8) & 0xff00
3214 // (x << 8) & 0xff000000
3215 if (N0.getOpcode() != ISD::SHL)
3216 return false;
3217 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3218 if (!C || C->getZExtValue() != 8)
3219 return false;
3220 }
3221 } else if (Opc == ISD::SHL) {
3222 // (x & 0xff) << 8
3223 // (x & 0xff0000) << 8
3224 if (Num != 0 && Num != 2)
3225 return false;
3226 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
3227 if (!C || C->getZExtValue() != 8)
3228 return false;
3229 } else { // Opc == ISD::SRL
3230 // (x & 0xff00) >> 8
3231 // (x & 0xff000000) >> 8
3232 if (Num != 1 && Num != 3)
3233 return false;
3234 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
3235 if (!C || C->getZExtValue() != 8)
3236 return false;
3237 }
3239 if (Parts[Num])
3240 return false;
3242 Parts[Num] = N0.getOperand(0).getNode();
3243 return true;
3244 }
3246 /// Match a 32-bit packed halfword bswap. That is
3247 /// ((x & 0x000000ff) << 8) |
3248 /// ((x & 0x0000ff00) >> 8) |
3249 /// ((x & 0x00ff0000) << 8) |
3250 /// ((x & 0xff000000) >> 8)
3251 /// => (rotl (bswap x), 16)
3252 SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) {
3253 if (!LegalOperations)
3254 return SDValue();
3256 EVT VT = N->getValueType(0);
3257 if (VT != MVT::i32)
3258 return SDValue();
3259 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
3260 return SDValue();
3262 // Look for either
3263 // (or (or (and), (and)), (or (and), (and)))
3264 // (or (or (or (and), (and)), (and)), (and))
3265 if (N0.getOpcode() != ISD::OR)
3266 return SDValue();
3267 SDValue N00 = N0.getOperand(0);
3268 SDValue N01 = N0.getOperand(1);
3269 SDNode *Parts[4] = {};
3271 if (N1.getOpcode() == ISD::OR &&
3272 N00.getNumOperands() == 2 && N01.getNumOperands() == 2) {
3273 // (or (or (and), (and)), (or (and), (and)))
3274 SDValue N000 = N00.getOperand(0);
3275 if (!isBSwapHWordElement(N000, Parts))
3276 return SDValue();
3278 SDValue N001 = N00.getOperand(1);
3279 if (!isBSwapHWordElement(N001, Parts))
3280 return SDValue();
3281 SDValue N010 = N01.getOperand(0);
3282 if (!isBSwapHWordElement(N010, Parts))
3283 return SDValue();
3284 SDValue N011 = N01.getOperand(1);
3285 if (!isBSwapHWordElement(N011, Parts))
3286 return SDValue();
3287 } else {
3288 // (or (or (or (and), (and)), (and)), (and))
3289 if (!isBSwapHWordElement(N1, Parts))
3290 return SDValue();
3291 if (!isBSwapHWordElement(N01, Parts))
3292 return SDValue();
3293 if (N00.getOpcode() != ISD::OR)
3294 return SDValue();
3295 SDValue N000 = N00.getOperand(0);
3296 if (!isBSwapHWordElement(N000, Parts))
3297 return SDValue();
3298 SDValue N001 = N00.getOperand(1);
3299 if (!isBSwapHWordElement(N001, Parts))
3300 return SDValue();
3301 }
3303 // Make sure the parts are all coming from the same node.
3304 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3])
3305 return SDValue();
3307 SDValue BSwap = DAG.getNode(ISD::BSWAP, SDLoc(N), VT,
3308 SDValue(Parts[0],0));
3310 // Result of the bswap should be rotated by 16. If it's not legal, then
3311 // do (x << 16) | (x >> 16).
3312 SDValue ShAmt = DAG.getConstant(16, getShiftAmountTy(VT));
3313 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT))
3314 return DAG.getNode(ISD::ROTL, SDLoc(N), VT, BSwap, ShAmt);
3315 if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT))
3316 return DAG.getNode(ISD::ROTR, SDLoc(N), VT, BSwap, ShAmt);
3317 return DAG.getNode(ISD::OR, SDLoc(N), VT,
3318 DAG.getNode(ISD::SHL, SDLoc(N), VT, BSwap, ShAmt),
3319 DAG.getNode(ISD::SRL, SDLoc(N), VT, BSwap, ShAmt));
3320 }
3322 SDValue DAGCombiner::visitOR(SDNode *N) {
3323 SDValue N0 = N->getOperand(0);
3324 SDValue N1 = N->getOperand(1);
3325 SDValue LL, LR, RL, RR, CC0, CC1;
3326 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3327 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3328 EVT VT = N1.getValueType();
3330 // fold vector ops
3331 if (VT.isVector()) {
3332 SDValue FoldedVOp = SimplifyVBinOp(N);
3333 if (FoldedVOp.getNode()) return FoldedVOp;
3335 // fold (or x, 0) -> x, vector edition
3336 if (ISD::isBuildVectorAllZeros(N0.getNode()))
3337 return N1;
3338 if (ISD::isBuildVectorAllZeros(N1.getNode()))
3339 return N0;
3341 // fold (or x, -1) -> -1, vector edition
3342 if (ISD::isBuildVectorAllOnes(N0.getNode()))
3343 // do not return N0, because undef node may exist in N0
3344 return DAG.getConstant(
3345 APInt::getAllOnesValue(
3346 N0.getValueType().getScalarType().getSizeInBits()),
3347 N0.getValueType());
3348 if (ISD::isBuildVectorAllOnes(N1.getNode()))
3349 // do not return N1, because undef node may exist in N1
3350 return DAG.getConstant(
3351 APInt::getAllOnesValue(
3352 N1.getValueType().getScalarType().getSizeInBits()),
3353 N1.getValueType());
3355 // fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask1)
3356 // fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf B, A, Mask2)
3357 // Do this only if the resulting shuffle is legal.
3358 if (isa<ShuffleVectorSDNode>(N0) &&
3359 isa<ShuffleVectorSDNode>(N1) &&
3360 // Avoid folding a node with illegal type.
3361 TLI.isTypeLegal(VT) &&
3362 N0->getOperand(1) == N1->getOperand(1) &&
3363 ISD::isBuildVectorAllZeros(N0.getOperand(1).getNode())) {
3364 bool CanFold = true;
3365 unsigned NumElts = VT.getVectorNumElements();
3366 const ShuffleVectorSDNode *SV0 = cast<ShuffleVectorSDNode>(N0);
3367 const ShuffleVectorSDNode *SV1 = cast<ShuffleVectorSDNode>(N1);
3368 // We construct two shuffle masks:
3369 // - Mask1 is a shuffle mask for a shuffle with N0 as the first operand
3370 // and N1 as the second operand.
3371 // - Mask2 is a shuffle mask for a shuffle with N1 as the first operand
3372 // and N0 as the second operand.
3373 // We do this because OR is commutable and therefore there might be
3374 // two ways to fold this node into a shuffle.
3375 SmallVector<int,4> Mask1;
3376 SmallVector<int,4> Mask2;
3378 for (unsigned i = 0; i != NumElts && CanFold; ++i) {
3379 int M0 = SV0->getMaskElt(i);
3380 int M1 = SV1->getMaskElt(i);
3382 // Both shuffle indexes are undef. Propagate Undef.
3383 if (M0 < 0 && M1 < 0) {
3384 Mask1.push_back(M0);
3385 Mask2.push_back(M0);
3386 continue;
3387 }
3389 if (M0 < 0 || M1 < 0 ||
3390 (M0 < (int)NumElts && M1 < (int)NumElts) ||
3391 (M0 >= (int)NumElts && M1 >= (int)NumElts)) {
3392 CanFold = false;
3393 break;
3394 }
3396 Mask1.push_back(M0 < (int)NumElts ? M0 : M1 + NumElts);
3397 Mask2.push_back(M1 < (int)NumElts ? M1 : M0 + NumElts);
3398 }
3400 if (CanFold) {
3401 // Fold this sequence only if the resulting shuffle is 'legal'.
3402 if (TLI.isShuffleMaskLegal(Mask1, VT))
3403 return DAG.getVectorShuffle(VT, SDLoc(N), N0->getOperand(0),
3404 N1->getOperand(0), &Mask1[0]);
3405 if (TLI.isShuffleMaskLegal(Mask2, VT))
3406 return DAG.getVectorShuffle(VT, SDLoc(N), N1->getOperand(0),
3407 N0->getOperand(0), &Mask2[0]);
3408 }
3409 }
3410 }
3412 // fold (or x, undef) -> -1
3413 if (!LegalOperations &&
3414 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) {
3415 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
3416 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT);
3417 }
3418 // fold (or c1, c2) -> c1|c2
3419 if (N0C && N1C)
3420 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C);
3421 // canonicalize constant to RHS
3422 if (N0C && !N1C)
3423 return DAG.getNode(ISD::OR, SDLoc(N), VT, N1, N0);
3424 // fold (or x, 0) -> x
3425 if (N1C && N1C->isNullValue())
3426 return N0;
3427 // fold (or x, -1) -> -1
3428 if (N1C && N1C->isAllOnesValue())
3429 return N1;
3430 // fold (or x, c) -> c iff (x & ~c) == 0
3431 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
3432 return N1;
3434 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16)
3435 SDValue BSwap = MatchBSwapHWord(N, N0, N1);
3436 if (BSwap.getNode())
3437 return BSwap;
3438 BSwap = MatchBSwapHWordLow(N, N0, N1);
3439 if (BSwap.getNode())
3440 return BSwap;
3442 // reassociate or
3443 SDValue ROR = ReassociateOps(ISD::OR, SDLoc(N), N0, N1);
3444 if (ROR.getNode())
3445 return ROR;
3446 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
3447 // iff (c1 & c2) == 0.
3448 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
3449 isa<ConstantSDNode>(N0.getOperand(1))) {
3450 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
3451 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0) {
3452 SDValue COR = DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1);
3453 if (!COR.getNode())
3454 return SDValue();
3455 return DAG.getNode(ISD::AND, SDLoc(N), VT,
3456 DAG.getNode(ISD::OR, SDLoc(N0), VT,
3457 N0.getOperand(0), N1), COR);
3458 }
3459 }
3460 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
3461 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
3462 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
3463 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
3465 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
3466 LL.getValueType().isInteger()) {
3467 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0)
3468 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0)
3469 if (cast<ConstantSDNode>(LR)->isNullValue() &&
3470 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
3471 SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(LR),
3472 LR.getValueType(), LL, RL);
3473 AddToWorklist(ORNode.getNode());
3474 return DAG.getSetCC(SDLoc(N), VT, ORNode, LR, Op1);
3475 }
3476 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1)
3477 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1)
3478 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
3479 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
3480 SDValue ANDNode = DAG.getNode(ISD::AND, SDLoc(LR),
3481 LR.getValueType(), LL, RL);
3482 AddToWorklist(ANDNode.getNode());
3483 return DAG.getSetCC(SDLoc(N), VT, ANDNode, LR, Op1);
3484 }
3485 }
3486 // canonicalize equivalent to ll == rl
3487 if (LL == RR && LR == RL) {
3488 Op1 = ISD::getSetCCSwappedOperands(Op1);
3489 std::swap(RL, RR);
3490 }
3491 if (LL == RL && LR == RR) {
3492 bool isInteger = LL.getValueType().isInteger();
3493 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
3494 if (Result != ISD::SETCC_INVALID &&
3495 (!LegalOperations ||
3496 (TLI.isCondCodeLegal(Result, LL.getSimpleValueType()) &&
3497 TLI.isOperationLegal(ISD::SETCC,
3498 getSetCCResultType(N0.getValueType())))))
3499 return DAG.getSetCC(SDLoc(N), N0.getValueType(),
3500 LL, LR, Result);
3501 }
3502 }
3504 // Simplify: (or (op x...), (op y...)) -> (op (or x, y))
3505 if (N0.getOpcode() == N1.getOpcode()) {
3506 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
3507 if (Tmp.getNode()) return Tmp;
3508 }
3510 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
3511 if (N0.getOpcode() == ISD::AND &&
3512 N1.getOpcode() == ISD::AND &&
3513 N0.getOperand(1).getOpcode() == ISD::Constant &&
3514 N1.getOperand(1).getOpcode() == ISD::Constant &&
3515 // Don't increase # computations.
3516 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
3517 // We can only do this xform if we know that bits from X that are set in C2
3518 // but not in C1 are already zero. Likewise for Y.
3519 const APInt &LHSMask =
3520 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3521 const APInt &RHSMask =
3522 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue();
3524 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
3525 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
3526 SDValue X = DAG.getNode(ISD::OR, SDLoc(N0), VT,
3527 N0.getOperand(0), N1.getOperand(0));
3528 return DAG.getNode(ISD::AND, SDLoc(N), VT, X,
3529 DAG.getConstant(LHSMask | RHSMask, VT));
3530 }
3531 }
3533 // See if this is some rotate idiom.
3534 if (SDNode *Rot = MatchRotate(N0, N1, SDLoc(N)))
3535 return SDValue(Rot, 0);
3537 // Simplify the operands using demanded-bits information.
3538 if (!VT.isVector() &&
3539 SimplifyDemandedBits(SDValue(N, 0)))
3540 return SDValue(N, 0);
3542 return SDValue();
3543 }
3545 /// Match "(X shl/srl V1) & V2" where V2 may not be present.
3546 static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
3547 if (Op.getOpcode() == ISD::AND) {
3548 if (isa<ConstantSDNode>(Op.getOperand(1))) {
3549 Mask = Op.getOperand(1);
3550 Op = Op.getOperand(0);
3551 } else {
3552 return false;
3553 }
3554 }
3556 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
3557 Shift = Op;
3558 return true;
3559 }
3561 return false;
3562 }
3564 // Return true if we can prove that, whenever Neg and Pos are both in the
3565 // range [0, OpSize), Neg == (Pos == 0 ? 0 : OpSize - Pos). This means that
3566 // for two opposing shifts shift1 and shift2 and a value X with OpBits bits:
3567 //
3568 // (or (shift1 X, Neg), (shift2 X, Pos))
3569 //
3570 // reduces to a rotate in direction shift2 by Pos or (equivalently) a rotate
3571 // in direction shift1 by Neg. The range [0, OpSize) means that we only need
3572 // to consider shift amounts with defined behavior.
3573 static bool matchRotateSub(SDValue Pos, SDValue Neg, unsigned OpSize) {
3574 // If OpSize is a power of 2 then:
3575 //
3576 // (a) (Pos == 0 ? 0 : OpSize - Pos) == (OpSize - Pos) & (OpSize - 1)
3577 // (b) Neg == Neg & (OpSize - 1) whenever Neg is in [0, OpSize).
3578 //
3579 // So if OpSize is a power of 2 and Neg is (and Neg', OpSize-1), we check
3580 // for the stronger condition:
3581 //
3582 // Neg & (OpSize - 1) == (OpSize - Pos) & (OpSize - 1) [A]
3583 //
3584 // for all Neg and Pos. Since Neg & (OpSize - 1) == Neg' & (OpSize - 1)
3585 // we can just replace Neg with Neg' for the rest of the function.
3586 //
3587 // In other cases we check for the even stronger condition:
3588 //
3589 // Neg == OpSize - Pos [B]
3590 //
3591 // for all Neg and Pos. Note that the (or ...) then invokes undefined
3592 // behavior if Pos == 0 (and consequently Neg == OpSize).
3593 //
3594 // We could actually use [A] whenever OpSize is a power of 2, but the
3595 // only extra cases that it would match are those uninteresting ones
3596 // where Neg and Pos are never in range at the same time. E.g. for
3597 // OpSize == 32, using [A] would allow a Neg of the form (sub 64, Pos)
3598 // as well as (sub 32, Pos), but:
3599 //
3600 // (or (shift1 X, (sub 64, Pos)), (shift2 X, Pos))
3601 //
3602 // always invokes undefined behavior for 32-bit X.
3603 //
3604 // Below, Mask == OpSize - 1 when using [A] and is all-ones otherwise.
3605 unsigned MaskLoBits = 0;
3606 if (Neg.getOpcode() == ISD::AND &&
3607 isPowerOf2_64(OpSize) &&
3608 Neg.getOperand(1).getOpcode() == ISD::Constant &&
3609 cast<ConstantSDNode>(Neg.getOperand(1))->getAPIntValue() == OpSize - 1) {
3610 Neg = Neg.getOperand(0);
3611 MaskLoBits = Log2_64(OpSize);
3612 }
3614 // Check whether Neg has the form (sub NegC, NegOp1) for some NegC and NegOp1.
3615 if (Neg.getOpcode() != ISD::SUB)
3616 return 0;
3617 ConstantSDNode *NegC = dyn_cast<ConstantSDNode>(Neg.getOperand(0));
3618 if (!NegC)
3619 return 0;
3620 SDValue NegOp1 = Neg.getOperand(1);
3622 // On the RHS of [A], if Pos is Pos' & (OpSize - 1), just replace Pos with
3623 // Pos'. The truncation is redundant for the purpose of the equality.
3624 if (MaskLoBits &&
3625 Pos.getOpcode() == ISD::AND &&
3626 Pos.getOperand(1).getOpcode() == ISD::Constant &&
3627 cast<ConstantSDNode>(Pos.getOperand(1))->getAPIntValue() == OpSize - 1)
3628 Pos = Pos.getOperand(0);
3630 // The condition we need is now:
3631 //
3632 // (NegC - NegOp1) & Mask == (OpSize - Pos) & Mask
3633 //
3634 // If NegOp1 == Pos then we need:
3635 //
3636 // OpSize & Mask == NegC & Mask
3637 //
3638 // (because "x & Mask" is a truncation and distributes through subtraction).
3639 APInt Width;
3640 if (Pos == NegOp1)
3641 Width = NegC->getAPIntValue();
3642 // Check for cases where Pos has the form (add NegOp1, PosC) for some PosC.
3643 // Then the condition we want to prove becomes:
3644 //
3645 // (NegC - NegOp1) & Mask == (OpSize - (NegOp1 + PosC)) & Mask
3646 //
3647 // which, again because "x & Mask" is a truncation, becomes:
3648 //
3649 // NegC & Mask == (OpSize - PosC) & Mask
3650 // OpSize & Mask == (NegC + PosC) & Mask
3651 else if (Pos.getOpcode() == ISD::ADD &&
3652 Pos.getOperand(0) == NegOp1 &&
3653 Pos.getOperand(1).getOpcode() == ISD::Constant)
3654 Width = (cast<ConstantSDNode>(Pos.getOperand(1))->getAPIntValue() +
3655 NegC->getAPIntValue());
3656 else
3657 return false;
3659 // Now we just need to check that OpSize & Mask == Width & Mask.
3660 if (MaskLoBits)
3661 // Opsize & Mask is 0 since Mask is Opsize - 1.
3662 return Width.getLoBits(MaskLoBits) == 0;
3663 return Width == OpSize;
3664 }
3666 // A subroutine of MatchRotate used once we have found an OR of two opposite
3667 // shifts of Shifted. If Neg == <operand size> - Pos then the OR reduces
3668 // to both (PosOpcode Shifted, Pos) and (NegOpcode Shifted, Neg), with the
3669 // former being preferred if supported. InnerPos and InnerNeg are Pos and
3670 // Neg with outer conversions stripped away.
3671 SDNode *DAGCombiner::MatchRotatePosNeg(SDValue Shifted, SDValue Pos,
3672 SDValue Neg, SDValue InnerPos,
3673 SDValue InnerNeg, unsigned PosOpcode,
3674 unsigned NegOpcode, SDLoc DL) {
3675 // fold (or (shl x, (*ext y)),
3676 // (srl x, (*ext (sub 32, y)))) ->
3677 // (rotl x, y) or (rotr x, (sub 32, y))
3678 //
3679 // fold (or (shl x, (*ext (sub 32, y))),
3680 // (srl x, (*ext y))) ->
3681 // (rotr x, y) or (rotl x, (sub 32, y))
3682 EVT VT = Shifted.getValueType();
3683 if (matchRotateSub(InnerPos, InnerNeg, VT.getSizeInBits())) {
3684 bool HasPos = TLI.isOperationLegalOrCustom(PosOpcode, VT);
3685 return DAG.getNode(HasPos ? PosOpcode : NegOpcode, DL, VT, Shifted,
3686 HasPos ? Pos : Neg).getNode();
3687 }
3689 return nullptr;
3690 }
3692 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
3693 // idioms for rotate, and if the target supports rotation instructions, generate
3694 // a rot[lr].
3695 SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, SDLoc DL) {
3696 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
3697 EVT VT = LHS.getValueType();
3698 if (!TLI.isTypeLegal(VT)) return nullptr;
3700 // The target must have at least one rotate flavor.
3701 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
3702 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
3703 if (!HasROTL && !HasROTR) return nullptr;
3705 // Match "(X shl/srl V1) & V2" where V2 may not be present.
3706 SDValue LHSShift; // The shift.
3707 SDValue LHSMask; // AND value if any.
3708 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
3709 return nullptr; // Not part of a rotate.
3711 SDValue RHSShift; // The shift.
3712 SDValue RHSMask; // AND value if any.
3713 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
3714 return nullptr; // Not part of a rotate.
3716 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
3717 return nullptr; // Not shifting the same value.
3719 if (LHSShift.getOpcode() == RHSShift.getOpcode())
3720 return nullptr; // Shifts must disagree.
3722 // Canonicalize shl to left side in a shl/srl pair.
3723 if (RHSShift.getOpcode() == ISD::SHL) {
3724 std::swap(LHS, RHS);
3725 std::swap(LHSShift, RHSShift);
3726 std::swap(LHSMask , RHSMask );
3727 }
3729 unsigned OpSizeInBits = VT.getSizeInBits();
3730 SDValue LHSShiftArg = LHSShift.getOperand(0);
3731 SDValue LHSShiftAmt = LHSShift.getOperand(1);
3732 SDValue RHSShiftArg = RHSShift.getOperand(0);
3733 SDValue RHSShiftAmt = RHSShift.getOperand(1);
3735 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
3736 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
3737 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
3738 RHSShiftAmt.getOpcode() == ISD::Constant) {
3739 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue();
3740 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue();
3741 if ((LShVal + RShVal) != OpSizeInBits)
3742 return nullptr;
3744 SDValue Rot = DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
3745 LHSShiftArg, HasROTL ? LHSShiftAmt : RHSShiftAmt);
3747 // If there is an AND of either shifted operand, apply it to the result.
3748 if (LHSMask.getNode() || RHSMask.getNode()) {
3749 APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
3751 if (LHSMask.getNode()) {
3752 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
3753 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
3754 }
3755 if (RHSMask.getNode()) {
3756 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
3757 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
3758 }
3760 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT));
3761 }
3763 return Rot.getNode();
3764 }
3766 // If there is a mask here, and we have a variable shift, we can't be sure
3767 // that we're masking out the right stuff.
3768 if (LHSMask.getNode() || RHSMask.getNode())
3769 return nullptr;
3771 // If the shift amount is sign/zext/any-extended just peel it off.
3772 SDValue LExtOp0 = LHSShiftAmt;
3773 SDValue RExtOp0 = RHSShiftAmt;
3774 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
3775 LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
3776 LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND ||
3777 LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
3778 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
3779 RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
3780 RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND ||
3781 RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
3782 LExtOp0 = LHSShiftAmt.getOperand(0);
3783 RExtOp0 = RHSShiftAmt.getOperand(0);
3784 }
3786 SDNode *TryL = MatchRotatePosNeg(LHSShiftArg, LHSShiftAmt, RHSShiftAmt,
3787 LExtOp0, RExtOp0, ISD::ROTL, ISD::ROTR, DL);
3788 if (TryL)
3789 return TryL;
3791 SDNode *TryR = MatchRotatePosNeg(RHSShiftArg, RHSShiftAmt, LHSShiftAmt,
3792 RExtOp0, LExtOp0, ISD::ROTR, ISD::ROTL, DL);
3793 if (TryR)
3794 return TryR;
3796 return nullptr;
3797 }
3799 SDValue DAGCombiner::visitXOR(SDNode *N) {
3800 SDValue N0 = N->getOperand(0);
3801 SDValue N1 = N->getOperand(1);
3802 SDValue LHS, RHS, CC;
3803 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3804 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3805 EVT VT = N0.getValueType();
3807 // fold vector ops
3808 if (VT.isVector()) {
3809 SDValue FoldedVOp = SimplifyVBinOp(N);
3810 if (FoldedVOp.getNode()) return FoldedVOp;
3812 // fold (xor x, 0) -> x, vector edition
3813 if (ISD::isBuildVectorAllZeros(N0.getNode()))
3814 return N1;
3815 if (ISD::isBuildVectorAllZeros(N1.getNode()))
3816 return N0;
3817 }
3819 // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
3820 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
3821 return DAG.getConstant(0, VT);
3822 // fold (xor x, undef) -> undef
3823 if (N0.getOpcode() == ISD::UNDEF)
3824 return N0;
3825 if (N1.getOpcode() == ISD::UNDEF)
3826 return N1;
3827 // fold (xor c1, c2) -> c1^c2
3828 if (N0C && N1C)
3829 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
3830 // canonicalize constant to RHS
3831 if (N0C && !N1C)
3832 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0);
3833 // fold (xor x, 0) -> x
3834 if (N1C && N1C->isNullValue())
3835 return N0;
3836 // reassociate xor
3837 SDValue RXOR = ReassociateOps(ISD::XOR, SDLoc(N), N0, N1);
3838 if (RXOR.getNode())
3839 return RXOR;
3841 // fold !(x cc y) -> (x !cc y)
3842 if (TLI.isConstTrueVal(N1.getNode()) && isSetCCEquivalent(N0, LHS, RHS, CC)) {
3843 bool isInt = LHS.getValueType().isInteger();
3844 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
3845 isInt);
3847 if (!LegalOperations ||
3848 TLI.isCondCodeLegal(NotCC, LHS.getSimpleValueType())) {
3849 switch (N0.getOpcode()) {
3850 default:
3851 llvm_unreachable("Unhandled SetCC Equivalent!");
3852 case ISD::SETCC:
3853 return DAG.getSetCC(SDLoc(N), VT, LHS, RHS, NotCC);
3854 case ISD::SELECT_CC:
3855 return DAG.getSelectCC(SDLoc(N), LHS, RHS, N0.getOperand(2),
3856 N0.getOperand(3), NotCC);
3857 }
3858 }
3859 }
3861 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
3862 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
3863 N0.getNode()->hasOneUse() &&
3864 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
3865 SDValue V = N0.getOperand(0);
3866 V = DAG.getNode(ISD::XOR, SDLoc(N0), V.getValueType(), V,
3867 DAG.getConstant(1, V.getValueType()));
3868 AddToWorklist(V.getNode());
3869 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, V);
3870 }
3872 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
3873 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
3874 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3875 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3876 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
3877 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3878 LHS = DAG.getNode(ISD::XOR, SDLoc(LHS), VT, LHS, N1); // LHS = ~LHS
3879 RHS = DAG.getNode(ISD::XOR, SDLoc(RHS), VT, RHS, N1); // RHS = ~RHS
3880 AddToWorklist(LHS.getNode()); AddToWorklist(RHS.getNode());
3881 return DAG.getNode(NewOpcode, SDLoc(N), VT, LHS, RHS);
3882 }
3883 }
3884 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants
3885 if (N1C && N1C->isAllOnesValue() &&
3886 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3887 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3888 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
3889 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3890 LHS = DAG.getNode(ISD::XOR, SDLoc(LHS), VT, LHS, N1); // LHS = ~LHS
3891 RHS = DAG.getNode(ISD::XOR, SDLoc(RHS), VT, RHS, N1); // RHS = ~RHS
3892 AddToWorklist(LHS.getNode()); AddToWorklist(RHS.getNode());
3893 return DAG.getNode(NewOpcode, SDLoc(N), VT, LHS, RHS);
3894 }
3895 }
3896 // fold (xor (and x, y), y) -> (and (not x), y)
3897 if (N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
3898 N0->getOperand(1) == N1) {
3899 SDValue X = N0->getOperand(0);
3900 SDValue NotX = DAG.getNOT(SDLoc(X), X, VT);
3901 AddToWorklist(NotX.getNode());
3902 return DAG.getNode(ISD::AND, SDLoc(N), VT, NotX, N1);
3903 }
3904 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2))
3905 if (N1C && N0.getOpcode() == ISD::XOR) {
3906 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
3907 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3908 if (N00C)
3909 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N0.getOperand(1),
3910 DAG.getConstant(N1C->getAPIntValue() ^
3911 N00C->getAPIntValue(), VT));
3912 if (N01C)
3913 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N0.getOperand(0),
3914 DAG.getConstant(N1C->getAPIntValue() ^
3915 N01C->getAPIntValue(), VT));
3916 }
3917 // fold (xor x, x) -> 0
3918 if (N0 == N1)
3919 return tryFoldToZero(SDLoc(N), TLI, VT, DAG, LegalOperations, LegalTypes);
3921 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
3922 if (N0.getOpcode() == N1.getOpcode()) {
3923 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
3924 if (Tmp.getNode()) return Tmp;
3925 }
3927 // Simplify the expression using non-local knowledge.
3928 if (!VT.isVector() &&
3929 SimplifyDemandedBits(SDValue(N, 0)))
3930 return SDValue(N, 0);
3932 return SDValue();
3933 }
3935 /// Handle transforms common to the three shifts, when the shift amount is a
3936 /// constant.
3937 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, ConstantSDNode *Amt) {
3938 // We can't and shouldn't fold opaque constants.
3939 if (Amt->isOpaque())
3940 return SDValue();
3942 SDNode *LHS = N->getOperand(0).getNode();
3943 if (!LHS->hasOneUse()) return SDValue();
3945 // We want to pull some binops through shifts, so that we have (and (shift))
3946 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
3947 // thing happens with address calculations, so it's important to canonicalize
3948 // it.
3949 bool HighBitSet = false; // Can we transform this if the high bit is set?
3951 switch (LHS->getOpcode()) {
3952 default: return SDValue();
3953 case ISD::OR:
3954 case ISD::XOR:
3955 HighBitSet = false; // We can only transform sra if the high bit is clear.
3956 break;
3957 case ISD::AND:
3958 HighBitSet = true; // We can only transform sra if the high bit is set.
3959 break;
3960 case ISD::ADD:
3961 if (N->getOpcode() != ISD::SHL)
3962 return SDValue(); // only shl(add) not sr[al](add).
3963 HighBitSet = false; // We can only transform sra if the high bit is clear.
3964 break;
3965 }
3967 // We require the RHS of the binop to be a constant and not opaque as well.
3968 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
3969 if (!BinOpCst || BinOpCst->isOpaque()) return SDValue();
3971 // FIXME: disable this unless the input to the binop is a shift by a constant.
3972 // If it is not a shift, it pessimizes some common cases like:
3973 //
3974 // void foo(int *X, int i) { X[i & 1235] = 1; }
3975 // int bar(int *X, int i) { return X[i & 255]; }
3976 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
3977 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
3978 BinOpLHSVal->getOpcode() != ISD::SRA &&
3979 BinOpLHSVal->getOpcode() != ISD::SRL) ||
3980 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
3981 return SDValue();
3983 EVT VT = N->getValueType(0);
3985 // If this is a signed shift right, and the high bit is modified by the
3986 // logical operation, do not perform the transformation. The highBitSet
3987 // boolean indicates the value of the high bit of the constant which would
3988 // cause it to be modified for this operation.
3989 if (N->getOpcode() == ISD::SRA) {
3990 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
3991 if (BinOpRHSSignSet != HighBitSet)
3992 return SDValue();
3993 }
3995 if (!TLI.isDesirableToCommuteWithShift(LHS))
3996 return SDValue();
3998 // Fold the constants, shifting the binop RHS by the shift amount.
3999 SDValue NewRHS = DAG.getNode(N->getOpcode(), SDLoc(LHS->getOperand(1)),
4000 N->getValueType(0),
4001 LHS->getOperand(1), N->getOperand(1));
4002 assert(isa<ConstantSDNode>(NewRHS) && "Folding was not successful!");
4004 // Create the new shift.
4005 SDValue NewShift = DAG.getNode(N->getOpcode(),
4006 SDLoc(LHS->getOperand(0)),
4007 VT, LHS->getOperand(0), N->getOperand(1));
4009 // Create the new binop.
4010 return DAG.getNode(LHS->getOpcode(), SDLoc(N), VT, NewShift, NewRHS);
4011 }
4013 SDValue DAGCombiner::distributeTruncateThroughAnd(SDNode *N) {
4014 assert(N->getOpcode() == ISD::TRUNCATE);
4015 assert(N->getOperand(0).getOpcode() == ISD::AND);
4017 // (truncate:TruncVT (and N00, N01C)) -> (and (truncate:TruncVT N00), TruncC)
4018 if (N->hasOneUse() && N->getOperand(0).hasOneUse()) {
4019 SDValue N01 = N->getOperand(0).getOperand(1);
4021 if (ConstantSDNode *N01C = isConstOrConstSplat(N01)) {
4022 EVT TruncVT = N->getValueType(0);
4023 SDValue N00 = N->getOperand(0).getOperand(0);
4024 APInt TruncC = N01C->getAPIntValue();
4025 TruncC = TruncC.trunc(TruncVT.getScalarSizeInBits());
4027 return DAG.getNode(ISD::AND, SDLoc(N), TruncVT,
4028 DAG.getNode(ISD::TRUNCATE, SDLoc(N), TruncVT, N00),
4029 DAG.getConstant(TruncC, TruncVT));
4030 }
4031 }
4033 return SDValue();
4034 }
4036 SDValue DAGCombiner::visitRotate(SDNode *N) {
4037 // fold (rot* x, (trunc (and y, c))) -> (rot* x, (and (trunc y), (trunc c))).
4038 if (N->getOperand(1).getOpcode() == ISD::TRUNCATE &&
4039 N->getOperand(1).getOperand(0).getOpcode() == ISD::AND) {
4040 SDValue NewOp1 = distributeTruncateThroughAnd(N->getOperand(1).getNode());
4041 if (NewOp1.getNode())
4042 return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0),
4043 N->getOperand(0), NewOp1);
4044 }
4045 return SDValue();
4046 }
4048 SDValue DAGCombiner::visitSHL(SDNode *N) {
4049 SDValue N0 = N->getOperand(0);
4050 SDValue N1 = N->getOperand(1);
4051 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4052 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4053 EVT VT = N0.getValueType();
4054 unsigned OpSizeInBits = VT.getScalarSizeInBits();
4056 // fold vector ops
4057 if (VT.isVector()) {
4058 SDValue FoldedVOp = SimplifyVBinOp(N);
4059 if (FoldedVOp.getNode()) return FoldedVOp;
4061 BuildVectorSDNode *N1CV = dyn_cast<BuildVectorSDNode>(N1);
4062 // If setcc produces all-one true value then:
4063 // (shl (and (setcc) N01CV) N1CV) -> (and (setcc) N01CV<<N1CV)
4064 if (N1CV && N1CV->isConstant()) {
4065 if (N0.getOpcode() == ISD::AND) {
4066 SDValue N00 = N0->getOperand(0);
4067 SDValue N01 = N0->getOperand(1);
4068 BuildVectorSDNode *N01CV = dyn_cast<BuildVectorSDNode>(N01);
4070 if (N01CV && N01CV->isConstant() && N00.getOpcode() == ISD::SETCC &&
4071 TLI.getBooleanContents(N00.getOperand(0).getValueType()) ==
4072 TargetLowering::ZeroOrNegativeOneBooleanContent) {
4073 SDValue C = DAG.FoldConstantArithmetic(ISD::SHL, VT, N01CV, N1CV);
4074 if (C.getNode())
4075 return DAG.getNode(ISD::AND, SDLoc(N), VT, N00, C);
4076 }
4077 } else {
4078 N1C = isConstOrConstSplat(N1);
4079 }
4080 }
4081 }
4083 // fold (shl c1, c2) -> c1<<c2
4084 if (N0C && N1C)
4085 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C);
4086 // fold (shl 0, x) -> 0
4087 if (N0C && N0C->isNullValue())
4088 return N0;
4089 // fold (shl x, c >= size(x)) -> undef
4090 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
4091 return DAG.getUNDEF(VT);
4092 // fold (shl x, 0) -> x
4093 if (N1C && N1C->isNullValue())
4094 return N0;
4095 // fold (shl undef, x) -> 0
4096 if (N0.getOpcode() == ISD::UNDEF)
4097 return DAG.getConstant(0, VT);
4098 // if (shl x, c) is known to be zero, return 0
4099 if (DAG.MaskedValueIsZero(SDValue(N, 0),
4100 APInt::getAllOnesValue(OpSizeInBits)))
4101 return DAG.getConstant(0, VT);
4102 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
4103 if (N1.getOpcode() == ISD::TRUNCATE &&
4104 N1.getOperand(0).getOpcode() == ISD::AND) {
4105 SDValue NewOp1 = distributeTruncateThroughAnd(N1.getNode());
4106 if (NewOp1.getNode())
4107 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0, NewOp1);
4108 }
4110 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
4111 return SDValue(N, 0);
4113 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2))
4114 if (N1C && N0.getOpcode() == ISD::SHL) {
4115 if (ConstantSDNode *N0C1 = isConstOrConstSplat(N0.getOperand(1))) {
4116 uint64_t c1 = N0C1->getZExtValue();
4117 uint64_t c2 = N1C->getZExtValue();
4118 if (c1 + c2 >= OpSizeInBits)
4119 return DAG.getConstant(0, VT);
4120 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0.getOperand(0),
4121 DAG.getConstant(c1 + c2, N1.getValueType()));
4122 }
4123 }
4125 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2)))
4126 // For this to be valid, the second form must not preserve any of the bits
4127 // that are shifted out by the inner shift in the first form. This means
4128 // the outer shift size must be >= the number of bits added by the ext.
4129 // As a corollary, we don't care what kind of ext it is.
4130 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND ||
4131 N0.getOpcode() == ISD::ANY_EXTEND ||
4132 N0.getOpcode() == ISD::SIGN_EXTEND) &&
4133 N0.getOperand(0).getOpcode() == ISD::SHL) {
4134 SDValue N0Op0 = N0.getOperand(0);
4135 if (ConstantSDNode *N0Op0C1 = isConstOrConstSplat(N0Op0.getOperand(1))) {
4136 uint64_t c1 = N0Op0C1->getZExtValue();
4137 uint64_t c2 = N1C->getZExtValue();
4138 EVT InnerShiftVT = N0Op0.getValueType();
4139 uint64_t InnerShiftSize = InnerShiftVT.getScalarSizeInBits();
4140 if (c2 >= OpSizeInBits - InnerShiftSize) {
4141 if (c1 + c2 >= OpSizeInBits)
4142 return DAG.getConstant(0, VT);
4143 return DAG.getNode(ISD::SHL, SDLoc(N0), VT,
4144 DAG.getNode(N0.getOpcode(), SDLoc(N0), VT,
4145 N0Op0->getOperand(0)),
4146 DAG.getConstant(c1 + c2, N1.getValueType()));
4147 }
4148 }
4149 }
4151 // fold (shl (zext (srl x, C)), C) -> (zext (shl (srl x, C), C))
4152 // Only fold this if the inner zext has no other uses to avoid increasing
4153 // the total number of instructions.
4154 if (N1C && N0.getOpcode() == ISD::ZERO_EXTEND && N0.hasOneUse() &&
4155 N0.getOperand(0).getOpcode() == ISD::SRL) {
4156 SDValue N0Op0 = N0.getOperand(0);
4157 if (ConstantSDNode *N0Op0C1 = isConstOrConstSplat(N0Op0.getOperand(1))) {
4158 uint64_t c1 = N0Op0C1->getZExtValue();
4159 if (c1 < VT.getScalarSizeInBits()) {
4160 uint64_t c2 = N1C->getZExtValue();
4161 if (c1 == c2) {
4162 SDValue NewOp0 = N0.getOperand(0);
4163 EVT CountVT = NewOp0.getOperand(1).getValueType();
4164 SDValue NewSHL = DAG.getNode(ISD::SHL, SDLoc(N), NewOp0.getValueType(),
4165 NewOp0, DAG.getConstant(c2, CountVT));
4166 AddToWorklist(NewSHL.getNode());
4167 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N0), VT, NewSHL);
4168 }
4169 }
4170 }
4171 }
4173 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or
4174 // (and (srl x, (sub c1, c2), MASK)
4175 // Only fold this if the inner shift has no other uses -- if it does, folding
4176 // this will increase the total number of instructions.
4177 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
4178 if (ConstantSDNode *N0C1 = isConstOrConstSplat(N0.getOperand(1))) {
4179 uint64_t c1 = N0C1->getZExtValue();
4180 if (c1 < OpSizeInBits) {
4181 uint64_t c2 = N1C->getZExtValue();
4182 APInt Mask = APInt::getHighBitsSet(OpSizeInBits, OpSizeInBits - c1);
4183 SDValue Shift;
4184 if (c2 > c1) {
4185 Mask = Mask.shl(c2 - c1);
4186 Shift = DAG.getNode(ISD::SHL, SDLoc(N), VT, N0.getOperand(0),
4187 DAG.getConstant(c2 - c1, N1.getValueType()));
4188 } else {
4189 Mask = Mask.lshr(c1 - c2);
4190 Shift = DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0),
4191 DAG.getConstant(c1 - c2, N1.getValueType()));
4192 }
4193 return DAG.getNode(ISD::AND, SDLoc(N0), VT, Shift,
4194 DAG.getConstant(Mask, VT));
4195 }
4196 }
4197 }
4198 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
4199 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) {
4200 unsigned BitSize = VT.getScalarSizeInBits();
4201 SDValue HiBitsMask =
4202 DAG.getConstant(APInt::getHighBitsSet(BitSize,
4203 BitSize - N1C->getZExtValue()), VT);
4204 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0.getOperand(0),
4205 HiBitsMask);
4206 }
4208 // fold (shl (add x, c1), c2) -> (add (shl x, c2), c1 << c2)
4209 // Variant of version done on multiply, except mul by a power of 2 is turned
4210 // into a shift.
4211 APInt Val;
4212 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
4213 (isa<ConstantSDNode>(N0.getOperand(1)) ||
4214 isConstantSplatVector(N0.getOperand(1).getNode(), Val))) {
4215 SDValue Shl0 = DAG.getNode(ISD::SHL, SDLoc(N0), VT, N0.getOperand(0), N1);
4216 SDValue Shl1 = DAG.getNode(ISD::SHL, SDLoc(N1), VT, N0.getOperand(1), N1);
4217 return DAG.getNode(ISD::ADD, SDLoc(N), VT, Shl0, Shl1);
4218 }
4220 if (N1C) {
4221 SDValue NewSHL = visitShiftByConstant(N, N1C);
4222 if (NewSHL.getNode())
4223 return NewSHL;
4224 }
4226 return SDValue();
4227 }
4229 SDValue DAGCombiner::visitSRA(SDNode *N) {
4230 SDValue N0 = N->getOperand(0);
4231 SDValue N1 = N->getOperand(1);
4232 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4233 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4234 EVT VT = N0.getValueType();
4235 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
4237 // fold vector ops
4238 if (VT.isVector()) {
4239 SDValue FoldedVOp = SimplifyVBinOp(N);
4240 if (FoldedVOp.getNode()) return FoldedVOp;
4242 N1C = isConstOrConstSplat(N1);
4243 }
4245 // fold (sra c1, c2) -> (sra c1, c2)
4246 if (N0C && N1C)
4247 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C);
4248 // fold (sra 0, x) -> 0
4249 if (N0C && N0C->isNullValue())
4250 return N0;
4251 // fold (sra -1, x) -> -1
4252 if (N0C && N0C->isAllOnesValue())
4253 return N0;
4254 // fold (sra x, (setge c, size(x))) -> undef
4255 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
4256 return DAG.getUNDEF(VT);
4257 // fold (sra x, 0) -> x
4258 if (N1C && N1C->isNullValue())
4259 return N0;
4260 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
4261 // sext_inreg.
4262 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
4263 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue();
4264 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits);
4265 if (VT.isVector())
4266 ExtVT = EVT::getVectorVT(*DAG.getContext(),
4267 ExtVT, VT.getVectorNumElements());
4268 if ((!LegalOperations ||
4269 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT)))
4270 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT,
4271 N0.getOperand(0), DAG.getValueType(ExtVT));
4272 }
4274 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
4275 if (N1C && N0.getOpcode() == ISD::SRA) {
4276 if (ConstantSDNode *C1 = isConstOrConstSplat(N0.getOperand(1))) {
4277 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue();
4278 if (Sum >= OpSizeInBits)
4279 Sum = OpSizeInBits - 1;
4280 return DAG.getNode(ISD::SRA, SDLoc(N), VT, N0.getOperand(0),
4281 DAG.getConstant(Sum, N1.getValueType()));
4282 }
4283 }
4285 // fold (sra (shl X, m), (sub result_size, n))
4286 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for
4287 // result_size - n != m.
4288 // If truncate is free for the target sext(shl) is likely to result in better
4289 // code.
4290 if (N0.getOpcode() == ISD::SHL && N1C) {
4291 // Get the two constanst of the shifts, CN0 = m, CN = n.
4292 const ConstantSDNode *N01C = isConstOrConstSplat(N0.getOperand(1));
4293 if (N01C) {
4294 LLVMContext &Ctx = *DAG.getContext();
4295 // Determine what the truncate's result bitsize and type would be.
4296 EVT TruncVT = EVT::getIntegerVT(Ctx, OpSizeInBits - N1C->getZExtValue());
4298 if (VT.isVector())
4299 TruncVT = EVT::getVectorVT(Ctx, TruncVT, VT.getVectorNumElements());
4301 // Determine the residual right-shift amount.
4302 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
4304 // If the shift is not a no-op (in which case this should be just a sign
4305 // extend already), the truncated to type is legal, sign_extend is legal
4306 // on that type, and the truncate to that type is both legal and free,
4307 // perform the transform.
4308 if ((ShiftAmt > 0) &&
4309 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
4310 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
4311 TLI.isTruncateFree(VT, TruncVT)) {
4313 SDValue Amt = DAG.getConstant(ShiftAmt,
4314 getShiftAmountTy(N0.getOperand(0).getValueType()));
4315 SDValue Shift = DAG.getNode(ISD::SRL, SDLoc(N0), VT,
4316 N0.getOperand(0), Amt);
4317 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0), TruncVT,
4318 Shift);
4319 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N),
4320 N->getValueType(0), Trunc);
4321 }
4322 }
4323 }
4325 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
4326 if (N1.getOpcode() == ISD::TRUNCATE &&
4327 N1.getOperand(0).getOpcode() == ISD::AND) {
4328 SDValue NewOp1 = distributeTruncateThroughAnd(N1.getNode());
4329 if (NewOp1.getNode())
4330 return DAG.getNode(ISD::SRA, SDLoc(N), VT, N0, NewOp1);
4331 }
4333 // fold (sra (trunc (srl x, c1)), c2) -> (trunc (sra x, c1 + c2))
4334 // if c1 is equal to the number of bits the trunc removes
4335 if (N0.getOpcode() == ISD::TRUNCATE &&
4336 (N0.getOperand(0).getOpcode() == ISD::SRL ||
4337 N0.getOperand(0).getOpcode() == ISD::SRA) &&
4338 N0.getOperand(0).hasOneUse() &&
4339 N0.getOperand(0).getOperand(1).hasOneUse() &&
4340 N1C) {
4341 SDValue N0Op0 = N0.getOperand(0);
4342 if (ConstantSDNode *LargeShift = isConstOrConstSplat(N0Op0.getOperand(1))) {
4343 unsigned LargeShiftVal = LargeShift->getZExtValue();
4344 EVT LargeVT = N0Op0.getValueType();
4346 if (LargeVT.getScalarSizeInBits() - OpSizeInBits == LargeShiftVal) {
4347 SDValue Amt =
4348 DAG.getConstant(LargeShiftVal + N1C->getZExtValue(),
4349 getShiftAmountTy(N0Op0.getOperand(0).getValueType()));
4350 SDValue SRA = DAG.getNode(ISD::SRA, SDLoc(N), LargeVT,
4351 N0Op0.getOperand(0), Amt);
4352 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, SRA);
4353 }
4354 }
4355 }
4357 // Simplify, based on bits shifted out of the LHS.
4358 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
4359 return SDValue(N, 0);
4362 // If the sign bit is known to be zero, switch this to a SRL.
4363 if (DAG.SignBitIsZero(N0))
4364 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, N1);
4366 if (N1C) {
4367 SDValue NewSRA = visitShiftByConstant(N, N1C);
4368 if (NewSRA.getNode())
4369 return NewSRA;
4370 }
4372 return SDValue();
4373 }
4375 SDValue DAGCombiner::visitSRL(SDNode *N) {
4376 SDValue N0 = N->getOperand(0);
4377 SDValue N1 = N->getOperand(1);
4378 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4379 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4380 EVT VT = N0.getValueType();
4381 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
4383 // fold vector ops
4384 if (VT.isVector()) {
4385 SDValue FoldedVOp = SimplifyVBinOp(N);
4386 if (FoldedVOp.getNode()) return FoldedVOp;
4388 N1C = isConstOrConstSplat(N1);
4389 }
4391 // fold (srl c1, c2) -> c1 >>u c2
4392 if (N0C && N1C)
4393 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
4394 // fold (srl 0, x) -> 0
4395 if (N0C && N0C->isNullValue())
4396 return N0;
4397 // fold (srl x, c >= size(x)) -> undef
4398 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
4399 return DAG.getUNDEF(VT);
4400 // fold (srl x, 0) -> x
4401 if (N1C && N1C->isNullValue())
4402 return N0;
4403 // if (srl x, c) is known to be zero, return 0
4404 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
4405 APInt::getAllOnesValue(OpSizeInBits)))
4406 return DAG.getConstant(0, VT);
4408 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
4409 if (N1C && N0.getOpcode() == ISD::SRL) {
4410 if (ConstantSDNode *N01C = isConstOrConstSplat(N0.getOperand(1))) {
4411 uint64_t c1 = N01C->getZExtValue();
4412 uint64_t c2 = N1C->getZExtValue();
4413 if (c1 + c2 >= OpSizeInBits)
4414 return DAG.getConstant(0, VT);
4415 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0),
4416 DAG.getConstant(c1 + c2, N1.getValueType()));
4417 }
4418 }
4420 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2)))
4421 if (N1C && N0.getOpcode() == ISD::TRUNCATE &&
4422 N0.getOperand(0).getOpcode() == ISD::SRL &&
4423 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
4424 uint64_t c1 =
4425 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
4426 uint64_t c2 = N1C->getZExtValue();
4427 EVT InnerShiftVT = N0.getOperand(0).getValueType();
4428 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType();
4429 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
4430 // This is only valid if the OpSizeInBits + c1 = size of inner shift.
4431 if (c1 + OpSizeInBits == InnerShiftSize) {
4432 if (c1 + c2 >= InnerShiftSize)
4433 return DAG.getConstant(0, VT);
4434 return DAG.getNode(ISD::TRUNCATE, SDLoc(N0), VT,
4435 DAG.getNode(ISD::SRL, SDLoc(N0), InnerShiftVT,
4436 N0.getOperand(0)->getOperand(0),
4437 DAG.getConstant(c1 + c2, ShiftCountVT)));
4438 }
4439 }
4441 // fold (srl (shl x, c), c) -> (and x, cst2)
4442 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1) {
4443 unsigned BitSize = N0.getScalarValueSizeInBits();
4444 if (BitSize <= 64) {
4445 uint64_t ShAmt = N1C->getZExtValue() + 64 - BitSize;
4446 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0.getOperand(0),
4447 DAG.getConstant(~0ULL >> ShAmt, VT));
4448 }
4449 }
4451 // fold (srl (anyextend x), c) -> (and (anyextend (srl x, c)), mask)
4452 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
4453 // Shifting in all undef bits?
4454 EVT SmallVT = N0.getOperand(0).getValueType();
4455 unsigned BitSize = SmallVT.getScalarSizeInBits();
4456 if (N1C->getZExtValue() >= BitSize)
4457 return DAG.getUNDEF(VT);
4459 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) {
4460 uint64_t ShiftAmt = N1C->getZExtValue();
4461 SDValue SmallShift = DAG.getNode(ISD::SRL, SDLoc(N0), SmallVT,
4462 N0.getOperand(0),
4463 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT)));
4464 AddToWorklist(SmallShift.getNode());
4465 APInt Mask = APInt::getAllOnesValue(OpSizeInBits).lshr(ShiftAmt);
4466 return DAG.getNode(ISD::AND, SDLoc(N), VT,
4467 DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, SmallShift),
4468 DAG.getConstant(Mask, VT));
4469 }
4470 }
4472 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
4473 // bit, which is unmodified by sra.
4474 if (N1C && N1C->getZExtValue() + 1 == OpSizeInBits) {
4475 if (N0.getOpcode() == ISD::SRA)
4476 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0), N1);
4477 }
4479 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
4480 if (N1C && N0.getOpcode() == ISD::CTLZ &&
4481 N1C->getAPIntValue() == Log2_32(OpSizeInBits)) {
4482 APInt KnownZero, KnownOne;
4483 DAG.computeKnownBits(N0.getOperand(0), KnownZero, KnownOne);
4485 // If any of the input bits are KnownOne, then the input couldn't be all
4486 // zeros, thus the result of the srl will always be zero.
4487 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT);
4489 // If all of the bits input the to ctlz node are known to be zero, then
4490 // the result of the ctlz is "32" and the result of the shift is one.
4491 APInt UnknownBits = ~KnownZero;
4492 if (UnknownBits == 0) return DAG.getConstant(1, VT);
4494 // Otherwise, check to see if there is exactly one bit input to the ctlz.
4495 if ((UnknownBits & (UnknownBits - 1)) == 0) {
4496 // Okay, we know that only that the single bit specified by UnknownBits
4497 // could be set on input to the CTLZ node. If this bit is set, the SRL
4498 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
4499 // to an SRL/XOR pair, which is likely to simplify more.
4500 unsigned ShAmt = UnknownBits.countTrailingZeros();
4501 SDValue Op = N0.getOperand(0);
4503 if (ShAmt) {
4504 Op = DAG.getNode(ISD::SRL, SDLoc(N0), VT, Op,
4505 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType())));
4506 AddToWorklist(Op.getNode());
4507 }
4509 return DAG.getNode(ISD::XOR, SDLoc(N), VT,
4510 Op, DAG.getConstant(1, VT));
4511 }
4512 }
4514 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
4515 if (N1.getOpcode() == ISD::TRUNCATE &&
4516 N1.getOperand(0).getOpcode() == ISD::AND) {
4517 SDValue NewOp1 = distributeTruncateThroughAnd(N1.getNode());
4518 if (NewOp1.getNode())
4519 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, NewOp1);
4520 }
4522 // fold operands of srl based on knowledge that the low bits are not
4523 // demanded.
4524 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
4525 return SDValue(N, 0);
4527 if (N1C) {
4528 SDValue NewSRL = visitShiftByConstant(N, N1C);
4529 if (NewSRL.getNode())
4530 return NewSRL;
4531 }
4533 // Attempt to convert a srl of a load into a narrower zero-extending load.
4534 SDValue NarrowLoad = ReduceLoadWidth(N);
4535 if (NarrowLoad.getNode())
4536 return NarrowLoad;
4538 // Here is a common situation. We want to optimize:
4539 //
4540 // %a = ...
4541 // %b = and i32 %a, 2
4542 // %c = srl i32 %b, 1
4543 // brcond i32 %c ...
4544 //
4545 // into
4546 //
4547 // %a = ...
4548 // %b = and %a, 2
4549 // %c = setcc eq %b, 0
4550 // brcond %c ...
4551 //
4552 // However when after the source operand of SRL is optimized into AND, the SRL
4553 // itself may not be optimized further. Look for it and add the BRCOND into
4554 // the worklist.
4555 if (N->hasOneUse()) {
4556 SDNode *Use = *N->use_begin();
4557 if (Use->getOpcode() == ISD::BRCOND)
4558 AddToWorklist(Use);
4559 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) {
4560 // Also look pass the truncate.
4561 Use = *Use->use_begin();
4562 if (Use->getOpcode() == ISD::BRCOND)
4563 AddToWorklist(Use);
4564 }
4565 }
4567 return SDValue();
4568 }
4570 SDValue DAGCombiner::visitCTLZ(SDNode *N) {
4571 SDValue N0 = N->getOperand(0);
4572 EVT VT = N->getValueType(0);
4574 // fold (ctlz c1) -> c2
4575 if (isa<ConstantSDNode>(N0))
4576 return DAG.getNode(ISD::CTLZ, SDLoc(N), VT, N0);
4577 return SDValue();
4578 }
4580 SDValue DAGCombiner::visitCTLZ_ZERO_UNDEF(SDNode *N) {
4581 SDValue N0 = N->getOperand(0);
4582 EVT VT = N->getValueType(0);
4584 // fold (ctlz_zero_undef c1) -> c2
4585 if (isa<ConstantSDNode>(N0))
4586 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SDLoc(N), VT, N0);
4587 return SDValue();
4588 }
4590 SDValue DAGCombiner::visitCTTZ(SDNode *N) {
4591 SDValue N0 = N->getOperand(0);
4592 EVT VT = N->getValueType(0);
4594 // fold (cttz c1) -> c2
4595 if (isa<ConstantSDNode>(N0))
4596 return DAG.getNode(ISD::CTTZ, SDLoc(N), VT, N0);
4597 return SDValue();
4598 }
4600 SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) {
4601 SDValue N0 = N->getOperand(0);
4602 EVT VT = N->getValueType(0);
4604 // fold (cttz_zero_undef c1) -> c2
4605 if (isa<ConstantSDNode>(N0))
4606 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, SDLoc(N), VT, N0);
4607 return SDValue();
4608 }
4610 SDValue DAGCombiner::visitCTPOP(SDNode *N) {
4611 SDValue N0 = N->getOperand(0);
4612 EVT VT = N->getValueType(0);
4614 // fold (ctpop c1) -> c2
4615 if (isa<ConstantSDNode>(N0))
4616 return DAG.getNode(ISD::CTPOP, SDLoc(N), VT, N0);
4617 return SDValue();
4618 }
4620 SDValue DAGCombiner::visitSELECT(SDNode *N) {
4621 SDValue N0 = N->getOperand(0);
4622 SDValue N1 = N->getOperand(1);
4623 SDValue N2 = N->getOperand(2);
4624 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4625 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4626 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
4627 EVT VT = N->getValueType(0);
4628 EVT VT0 = N0.getValueType();
4630 // fold (select C, X, X) -> X
4631 if (N1 == N2)
4632 return N1;
4633 // fold (select true, X, Y) -> X
4634 if (N0C && !N0C->isNullValue())
4635 return N1;
4636 // fold (select false, X, Y) -> Y
4637 if (N0C && N0C->isNullValue())
4638 return N2;
4639 // fold (select C, 1, X) -> (or C, X)
4640 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
4641 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N2);
4642 // fold (select C, 0, 1) -> (xor C, 1)
4643 // We can't do this reliably if integer based booleans have different contents
4644 // to floating point based booleans. This is because we can't tell whether we
4645 // have an integer-based boolean or a floating-point-based boolean unless we
4646 // can find the SETCC that produced it and inspect its operands. This is
4647 // fairly easy if C is the SETCC node, but it can potentially be
4648 // undiscoverable (or not reasonably discoverable). For example, it could be
4649 // in another basic block or it could require searching a complicated
4650 // expression.
4651 if (VT.isInteger() &&
4652 (VT0 == MVT::i1 || (VT0.isInteger() &&
4653 TLI.getBooleanContents(false, false) ==
4654 TLI.getBooleanContents(false, true) &&
4655 TLI.getBooleanContents(false, false) ==
4656 TargetLowering::ZeroOrOneBooleanContent)) &&
4657 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
4658 SDValue XORNode;
4659 if (VT == VT0)
4660 return DAG.getNode(ISD::XOR, SDLoc(N), VT0,
4661 N0, DAG.getConstant(1, VT0));
4662 XORNode = DAG.getNode(ISD::XOR, SDLoc(N0), VT0,
4663 N0, DAG.getConstant(1, VT0));
4664 AddToWorklist(XORNode.getNode());
4665 if (VT.bitsGT(VT0))
4666 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, XORNode);
4667 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, XORNode);
4668 }
4669 // fold (select C, 0, X) -> (and (not C), X)
4670 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
4671 SDValue NOTNode = DAG.getNOT(SDLoc(N0), N0, VT);
4672 AddToWorklist(NOTNode.getNode());
4673 return DAG.getNode(ISD::AND, SDLoc(N), VT, NOTNode, N2);
4674 }
4675 // fold (select C, X, 1) -> (or (not C), X)
4676 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
4677 SDValue NOTNode = DAG.getNOT(SDLoc(N0), N0, VT);
4678 AddToWorklist(NOTNode.getNode());
4679 return DAG.getNode(ISD::OR, SDLoc(N), VT, NOTNode, N1);
4680 }
4681 // fold (select C, X, 0) -> (and C, X)
4682 if (VT == MVT::i1 && N2C && N2C->isNullValue())
4683 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0, N1);
4684 // fold (select X, X, Y) -> (or X, Y)
4685 // fold (select X, 1, Y) -> (or X, Y)
4686 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
4687 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N2);
4688 // fold (select X, Y, X) -> (and X, Y)
4689 // fold (select X, Y, 0) -> (and X, Y)
4690 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
4691 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0, N1);
4693 // If we can fold this based on the true/false value, do so.
4694 if (SimplifySelectOps(N, N1, N2))
4695 return SDValue(N, 0); // Don't revisit N.
4697 // fold selects based on a setcc into other things, such as min/max/abs
4698 if (N0.getOpcode() == ISD::SETCC) {
4699 if ((!LegalOperations &&
4700 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) ||
4701 TLI.isOperationLegal(ISD::SELECT_CC, VT))
4702 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT,
4703 N0.getOperand(0), N0.getOperand(1),
4704 N1, N2, N0.getOperand(2));
4705 return SimplifySelect(SDLoc(N), N0, N1, N2);
4706 }
4708 return SDValue();
4709 }
4711 static
4712 std::pair<SDValue, SDValue> SplitVSETCC(const SDNode *N, SelectionDAG &DAG) {
4713 SDLoc DL(N);
4714 EVT LoVT, HiVT;
4715 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
4717 // Split the inputs.
4718 SDValue Lo, Hi, LL, LH, RL, RH;
4719 std::tie(LL, LH) = DAG.SplitVectorOperand(N, 0);
4720 std::tie(RL, RH) = DAG.SplitVectorOperand(N, 1);
4722 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
4723 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
4725 return std::make_pair(Lo, Hi);
4726 }
4728 // This function assumes all the vselect's arguments are CONCAT_VECTOR
4729 // nodes and that the condition is a BV of ConstantSDNodes (or undefs).
4730 static SDValue ConvertSelectToConcatVector(SDNode *N, SelectionDAG &DAG) {
4731 SDLoc dl(N);
4732 SDValue Cond = N->getOperand(0);
4733 SDValue LHS = N->getOperand(1);
4734 SDValue RHS = N->getOperand(2);
4735 EVT VT = N->getValueType(0);
4736 int NumElems = VT.getVectorNumElements();
4737 assert(LHS.getOpcode() == ISD::CONCAT_VECTORS &&
4738 RHS.getOpcode() == ISD::CONCAT_VECTORS &&
4739 Cond.getOpcode() == ISD::BUILD_VECTOR);
4741 // CONCAT_VECTOR can take an arbitrary number of arguments. We only care about
4742 // binary ones here.
4743 if (LHS->getNumOperands() != 2 || RHS->getNumOperands() != 2)
4744 return SDValue();
4746 // We're sure we have an even number of elements due to the
4747 // concat_vectors we have as arguments to vselect.
4748 // Skip BV elements until we find one that's not an UNDEF
4749 // After we find an UNDEF element, keep looping until we get to half the
4750 // length of the BV and see if all the non-undef nodes are the same.
4751 ConstantSDNode *BottomHalf = nullptr;
4752 for (int i = 0; i < NumElems / 2; ++i) {
4753 if (Cond->getOperand(i)->getOpcode() == ISD::UNDEF)
4754 continue;
4756 if (BottomHalf == nullptr)
4757 BottomHalf = cast<ConstantSDNode>(Cond.getOperand(i));
4758 else if (Cond->getOperand(i).getNode() != BottomHalf)
4759 return SDValue();
4760 }
4762 // Do the same for the second half of the BuildVector
4763 ConstantSDNode *TopHalf = nullptr;
4764 for (int i = NumElems / 2; i < NumElems; ++i) {
4765 if (Cond->getOperand(i)->getOpcode() == ISD::UNDEF)
4766 continue;
4768 if (TopHalf == nullptr)
4769 TopHalf = cast<ConstantSDNode>(Cond.getOperand(i));
4770 else if (Cond->getOperand(i).getNode() != TopHalf)
4771 return SDValue();
4772 }
4774 assert(TopHalf && BottomHalf &&
4775 "One half of the selector was all UNDEFs and the other was all the "
4776 "same value. This should have been addressed before this function.");
4777 return DAG.getNode(
4778 ISD::CONCAT_VECTORS, dl, VT,
4779 BottomHalf->isNullValue() ? RHS->getOperand(0) : LHS->getOperand(0),
4780 TopHalf->isNullValue() ? RHS->getOperand(1) : LHS->getOperand(1));
4781 }
4783 SDValue DAGCombiner::visitMSTORE(SDNode *N) {
4785 if (Level >= AfterLegalizeTypes)
4786 return SDValue();
4788 MaskedStoreSDNode *MST = dyn_cast<MaskedStoreSDNode>(N);
4789 SDValue Mask = MST->getMask();
4790 SDValue Data = MST->getData();
4791 SDLoc DL(N);
4793 // If the MSTORE data type requires splitting and the mask is provided by a
4794 // SETCC, then split both nodes and its operands before legalization. This
4795 // prevents the type legalizer from unrolling SETCC into scalar comparisons
4796 // and enables future optimizations (e.g. min/max pattern matching on X86).
4797 if (Mask.getOpcode() == ISD::SETCC) {
4799 // Check if any splitting is required.
4800 if (TLI.getTypeAction(*DAG.getContext(), Data.getValueType()) !=
4801 TargetLowering::TypeSplitVector)
4802 return SDValue();
4804 SDValue MaskLo, MaskHi, Lo, Hi;
4805 std::tie(MaskLo, MaskHi) = SplitVSETCC(Mask.getNode(), DAG);
4807 EVT LoVT, HiVT;
4808 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MST->getValueType(0));
4810 SDValue Chain = MST->getChain();
4811 SDValue Ptr = MST->getBasePtr();
4813 EVT MemoryVT = MST->getMemoryVT();
4814 unsigned Alignment = MST->getOriginalAlignment();
4816 // if Alignment is equal to the vector size,
4817 // take the half of it for the second part
4818 unsigned SecondHalfAlignment =
4819 (Alignment == Data->getValueType(0).getSizeInBits()/8) ?
4820 Alignment/2 : Alignment;
4822 EVT LoMemVT, HiMemVT;
4823 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
4825 SDValue DataLo, DataHi;
4826 std::tie(DataLo, DataHi) = DAG.SplitVector(Data, DL);
4828 MachineMemOperand *MMO = DAG.getMachineFunction().
4829 getMachineMemOperand(MST->getPointerInfo(),
4830 MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
4831 Alignment, MST->getAAInfo(), MST->getRanges());
4833 Lo = DAG.getMaskedStore(Chain, DL, DataLo, Ptr, MaskLo, MMO);
4835 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
4836 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
4837 DAG.getConstant(IncrementSize, Ptr.getValueType()));
4839 MMO = DAG.getMachineFunction().
4840 getMachineMemOperand(MST->getPointerInfo(),
4841 MachineMemOperand::MOStore, HiMemVT.getStoreSize(),
4842 SecondHalfAlignment, MST->getAAInfo(),
4843 MST->getRanges());
4845 Hi = DAG.getMaskedStore(Chain, DL, DataHi, Ptr, MaskHi, MMO);
4847 AddToWorklist(Lo.getNode());
4848 AddToWorklist(Hi.getNode());
4850 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
4851 }
4852 return SDValue();
4853 }
4855 SDValue DAGCombiner::visitMLOAD(SDNode *N) {
4857 if (Level >= AfterLegalizeTypes)
4858 return SDValue();
4860 MaskedLoadSDNode *MLD = dyn_cast<MaskedLoadSDNode>(N);
4861 SDValue Mask = MLD->getMask();
4862 SDLoc DL(N);
4864 // If the MLOAD result requires splitting and the mask is provided by a
4865 // SETCC, then split both nodes and its operands before legalization. This
4866 // prevents the type legalizer from unrolling SETCC into scalar comparisons
4867 // and enables future optimizations (e.g. min/max pattern matching on X86).
4869 if (Mask.getOpcode() == ISD::SETCC) {
4870 EVT VT = N->getValueType(0);
4872 // Check if any splitting is required.
4873 if (TLI.getTypeAction(*DAG.getContext(), VT) !=
4874 TargetLowering::TypeSplitVector)
4875 return SDValue();
4877 SDValue MaskLo, MaskHi, Lo, Hi;
4878 std::tie(MaskLo, MaskHi) = SplitVSETCC(Mask.getNode(), DAG);
4880 SDValue Src0 = MLD->getSrc0();
4881 SDValue Src0Lo, Src0Hi;
4882 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, DL);
4884 EVT LoVT, HiVT;
4885 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MLD->getValueType(0));
4887 SDValue Chain = MLD->getChain();
4888 SDValue Ptr = MLD->getBasePtr();
4889 EVT MemoryVT = MLD->getMemoryVT();
4890 unsigned Alignment = MLD->getOriginalAlignment();
4892 // if Alignment is equal to the vector size,
4893 // take the half of it for the second part
4894 unsigned SecondHalfAlignment =
4895 (Alignment == MLD->getValueType(0).getSizeInBits()/8) ?
4896 Alignment/2 : Alignment;
4898 EVT LoMemVT, HiMemVT;
4899 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
4901 MachineMemOperand *MMO = DAG.getMachineFunction().
4902 getMachineMemOperand(MLD->getPointerInfo(),
4903 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
4904 Alignment, MLD->getAAInfo(), MLD->getRanges());
4906 Lo = DAG.getMaskedLoad(LoVT, DL, Chain, Ptr, MaskLo, Src0Lo, MMO);
4908 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
4909 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
4910 DAG.getConstant(IncrementSize, Ptr.getValueType()));
4912 MMO = DAG.getMachineFunction().
4913 getMachineMemOperand(MLD->getPointerInfo(),
4914 MachineMemOperand::MOLoad, HiMemVT.getStoreSize(),
4915 SecondHalfAlignment, MLD->getAAInfo(), MLD->getRanges());
4917 Hi = DAG.getMaskedLoad(HiVT, DL, Chain, Ptr, MaskHi, Src0Hi, MMO);
4919 AddToWorklist(Lo.getNode());
4920 AddToWorklist(Hi.getNode());
4922 // Build a factor node to remember that this load is independent of the
4923 // other one.
4924 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo.getValue(1),
4925 Hi.getValue(1));
4927 // Legalized the chain result - switch anything that used the old chain to
4928 // use the new one.
4929 DAG.ReplaceAllUsesOfValueWith(SDValue(MLD, 1), Chain);
4931 SDValue LoadRes = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
4933 SDValue RetOps[] = { LoadRes, Chain };
4934 return DAG.getMergeValues(RetOps, DL);
4935 }
4936 return SDValue();
4937 }
4939 SDValue DAGCombiner::visitVSELECT(SDNode *N) {
4940 SDValue N0 = N->getOperand(0);
4941 SDValue N1 = N->getOperand(1);
4942 SDValue N2 = N->getOperand(2);
4943 SDLoc DL(N);
4945 // Canonicalize integer abs.
4946 // vselect (setg[te] X, 0), X, -X ->
4947 // vselect (setgt X, -1), X, -X ->
4948 // vselect (setl[te] X, 0), -X, X ->
4949 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
4950 if (N0.getOpcode() == ISD::SETCC) {
4951 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
4952 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
4953 bool isAbs = false;
4954 bool RHSIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
4956 if (((RHSIsAllZeros && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
4957 (ISD::isBuildVectorAllOnes(RHS.getNode()) && CC == ISD::SETGT)) &&
4958 N1 == LHS && N2.getOpcode() == ISD::SUB && N1 == N2.getOperand(1))
4959 isAbs = ISD::isBuildVectorAllZeros(N2.getOperand(0).getNode());
4960 else if ((RHSIsAllZeros && (CC == ISD::SETLT || CC == ISD::SETLE)) &&
4961 N2 == LHS && N1.getOpcode() == ISD::SUB && N2 == N1.getOperand(1))
4962 isAbs = ISD::isBuildVectorAllZeros(N1.getOperand(0).getNode());
4964 if (isAbs) {
4965 EVT VT = LHS.getValueType();
4966 SDValue Shift = DAG.getNode(
4967 ISD::SRA, DL, VT, LHS,
4968 DAG.getConstant(VT.getScalarType().getSizeInBits() - 1, VT));
4969 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, LHS, Shift);
4970 AddToWorklist(Shift.getNode());
4971 AddToWorklist(Add.getNode());
4972 return DAG.getNode(ISD::XOR, DL, VT, Add, Shift);
4973 }
4974 }
4976 // If the VSELECT result requires splitting and the mask is provided by a
4977 // SETCC, then split both nodes and its operands before legalization. This
4978 // prevents the type legalizer from unrolling SETCC into scalar comparisons
4979 // and enables future optimizations (e.g. min/max pattern matching on X86).
4980 if (N0.getOpcode() == ISD::SETCC) {
4981 EVT VT = N->getValueType(0);
4983 // Check if any splitting is required.
4984 if (TLI.getTypeAction(*DAG.getContext(), VT) !=
4985 TargetLowering::TypeSplitVector)
4986 return SDValue();
4988 SDValue Lo, Hi, CCLo, CCHi, LL, LH, RL, RH;
4989 std::tie(CCLo, CCHi) = SplitVSETCC(N0.getNode(), DAG);
4990 std::tie(LL, LH) = DAG.SplitVectorOperand(N, 1);
4991 std::tie(RL, RH) = DAG.SplitVectorOperand(N, 2);
4993 Lo = DAG.getNode(N->getOpcode(), DL, LL.getValueType(), CCLo, LL, RL);
4994 Hi = DAG.getNode(N->getOpcode(), DL, LH.getValueType(), CCHi, LH, RH);
4996 // Add the new VSELECT nodes to the work list in case they need to be split
4997 // again.
4998 AddToWorklist(Lo.getNode());
4999 AddToWorklist(Hi.getNode());
5001 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
5002 }
5004 // Fold (vselect (build_vector all_ones), N1, N2) -> N1
5005 if (ISD::isBuildVectorAllOnes(N0.getNode()))
5006 return N1;
5007 // Fold (vselect (build_vector all_zeros), N1, N2) -> N2
5008 if (ISD::isBuildVectorAllZeros(N0.getNode()))
5009 return N2;
5011 // The ConvertSelectToConcatVector function is assuming both the above
5012 // checks for (vselect (build_vector all{ones,zeros) ...) have been made
5013 // and addressed.
5014 if (N1.getOpcode() == ISD::CONCAT_VECTORS &&
5015 N2.getOpcode() == ISD::CONCAT_VECTORS &&
5016 ISD::isBuildVectorOfConstantSDNodes(N0.getNode())) {
5017 SDValue CV = ConvertSelectToConcatVector(N, DAG);
5018 if (CV.getNode())
5019 return CV;
5020 }
5022 return SDValue();
5023 }
5025 SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
5026 SDValue N0 = N->getOperand(0);
5027 SDValue N1 = N->getOperand(1);
5028 SDValue N2 = N->getOperand(2);
5029 SDValue N3 = N->getOperand(3);
5030 SDValue N4 = N->getOperand(4);
5031 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
5033 // fold select_cc lhs, rhs, x, x, cc -> x
5034 if (N2 == N3)
5035 return N2;
5037 // Determine if the condition we're dealing with is constant
5038 SDValue SCC = SimplifySetCC(getSetCCResultType(N0.getValueType()),
5039 N0, N1, CC, SDLoc(N), false);
5040 if (SCC.getNode()) {
5041 AddToWorklist(SCC.getNode());
5043 if (ConstantSDNode *SCCC = dyn_cast<ConstantSDNode>(SCC.getNode())) {
5044 if (!SCCC->isNullValue())
5045 return N2; // cond always true -> true val
5046 else
5047 return N3; // cond always false -> false val
5048 }
5050 // Fold to a simpler select_cc
5051 if (SCC.getOpcode() == ISD::SETCC)
5052 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N2.getValueType(),
5053 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
5054 SCC.getOperand(2));
5055 }
5057 // If we can fold this based on the true/false value, do so.
5058 if (SimplifySelectOps(N, N2, N3))
5059 return SDValue(N, 0); // Don't revisit N.
5061 // fold select_cc into other things, such as min/max/abs
5062 return SimplifySelectCC(SDLoc(N), N0, N1, N2, N3, CC);
5063 }
5065 SDValue DAGCombiner::visitSETCC(SDNode *N) {
5066 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
5067 cast<CondCodeSDNode>(N->getOperand(2))->get(),
5068 SDLoc(N));
5069 }
5071 // tryToFoldExtendOfConstant - Try to fold a sext/zext/aext
5072 // dag node into a ConstantSDNode or a build_vector of constants.
5073 // This function is called by the DAGCombiner when visiting sext/zext/aext
5074 // dag nodes (see for example method DAGCombiner::visitSIGN_EXTEND).
5075 // Vector extends are not folded if operations are legal; this is to
5076 // avoid introducing illegal build_vector dag nodes.
5077 static SDNode *tryToFoldExtendOfConstant(SDNode *N, const TargetLowering &TLI,
5078 SelectionDAG &DAG, bool LegalTypes,
5079 bool LegalOperations) {
5080 unsigned Opcode = N->getOpcode();
5081 SDValue N0 = N->getOperand(0);
5082 EVT VT = N->getValueType(0);
5084 assert((Opcode == ISD::SIGN_EXTEND || Opcode == ISD::ZERO_EXTEND ||
5085 Opcode == ISD::ANY_EXTEND) && "Expected EXTEND dag node in input!");
5087 // fold (sext c1) -> c1
5088 // fold (zext c1) -> c1
5089 // fold (aext c1) -> c1
5090 if (isa<ConstantSDNode>(N0))
5091 return DAG.getNode(Opcode, SDLoc(N), VT, N0).getNode();
5093 // fold (sext (build_vector AllConstants) -> (build_vector AllConstants)
5094 // fold (zext (build_vector AllConstants) -> (build_vector AllConstants)
5095 // fold (aext (build_vector AllConstants) -> (build_vector AllConstants)
5096 EVT SVT = VT.getScalarType();
5097 if (!(VT.isVector() &&
5098 (!LegalTypes || (!LegalOperations && TLI.isTypeLegal(SVT))) &&
5099 ISD::isBuildVectorOfConstantSDNodes(N0.getNode())))
5100 return nullptr;
5102 // We can fold this node into a build_vector.
5103 unsigned VTBits = SVT.getSizeInBits();
5104 unsigned EVTBits = N0->getValueType(0).getScalarType().getSizeInBits();
5105 unsigned ShAmt = VTBits - EVTBits;
5106 SmallVector<SDValue, 8> Elts;
5107 unsigned NumElts = N0->getNumOperands();
5108 SDLoc DL(N);
5110 for (unsigned i=0; i != NumElts; ++i) {
5111 SDValue Op = N0->getOperand(i);
5112 if (Op->getOpcode() == ISD::UNDEF) {
5113 Elts.push_back(DAG.getUNDEF(SVT));
5114 continue;
5115 }
5117 ConstantSDNode *CurrentND = cast<ConstantSDNode>(Op);
5118 const APInt &C = APInt(VTBits, CurrentND->getAPIntValue().getZExtValue());
5119 if (Opcode == ISD::SIGN_EXTEND)
5120 Elts.push_back(DAG.getConstant(C.shl(ShAmt).ashr(ShAmt).getZExtValue(),
5121 SVT));
5122 else
5123 Elts.push_back(DAG.getConstant(C.shl(ShAmt).lshr(ShAmt).getZExtValue(),
5124 SVT));
5125 }
5127 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Elts).getNode();
5128 }
5130 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
5131 // "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))"
5132 // transformation. Returns true if extension are possible and the above
5133 // mentioned transformation is profitable.
5134 static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
5135 unsigned ExtOpc,
5136 SmallVectorImpl<SDNode *> &ExtendNodes,
5137 const TargetLowering &TLI) {
5138 bool HasCopyToRegUses = false;
5139 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
5140 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
5141 UE = N0.getNode()->use_end();
5142 UI != UE; ++UI) {
5143 SDNode *User = *UI;
5144 if (User == N)
5145 continue;
5146 if (UI.getUse().getResNo() != N0.getResNo())
5147 continue;
5148 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
5149 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
5150 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
5151 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
5152 // Sign bits will be lost after a zext.
5153 return false;
5154 bool Add = false;
5155 for (unsigned i = 0; i != 2; ++i) {
5156 SDValue UseOp = User->getOperand(i);
5157 if (UseOp == N0)
5158 continue;
5159 if (!isa<ConstantSDNode>(UseOp))
5160 return false;
5161 Add = true;
5162 }
5163 if (Add)
5164 ExtendNodes.push_back(User);
5165 continue;
5166 }
5167 // If truncates aren't free and there are users we can't
5168 // extend, it isn't worthwhile.
5169 if (!isTruncFree)
5170 return false;
5171 // Remember if this value is live-out.
5172 if (User->getOpcode() == ISD::CopyToReg)
5173 HasCopyToRegUses = true;
5174 }
5176 if (HasCopyToRegUses) {
5177 bool BothLiveOut = false;
5178 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
5179 UI != UE; ++UI) {
5180 SDUse &Use = UI.getUse();
5181 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
5182 BothLiveOut = true;
5183 break;
5184 }
5185 }
5186 if (BothLiveOut)
5187 // Both unextended and extended values are live out. There had better be
5188 // a good reason for the transformation.
5189 return ExtendNodes.size();
5190 }
5191 return true;
5192 }
5194 void DAGCombiner::ExtendSetCCUses(const SmallVectorImpl<SDNode *> &SetCCs,
5195 SDValue Trunc, SDValue ExtLoad, SDLoc DL,
5196 ISD::NodeType ExtType) {
5197 // Extend SetCC uses if necessary.
5198 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
5199 SDNode *SetCC = SetCCs[i];
5200 SmallVector<SDValue, 4> Ops;
5202 for (unsigned j = 0; j != 2; ++j) {
5203 SDValue SOp = SetCC->getOperand(j);
5204 if (SOp == Trunc)
5205 Ops.push_back(ExtLoad);
5206 else
5207 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp));
5208 }
5210 Ops.push_back(SetCC->getOperand(2));
5211 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), Ops));
5212 }
5213 }
5215 SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
5216 SDValue N0 = N->getOperand(0);
5217 EVT VT = N->getValueType(0);
5219 if (SDNode *Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes,
5220 LegalOperations))
5221 return SDValue(Res, 0);
5223 // fold (sext (sext x)) -> (sext x)
5224 // fold (sext (aext x)) -> (sext x)
5225 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
5226 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT,
5227 N0.getOperand(0));
5229 if (N0.getOpcode() == ISD::TRUNCATE) {
5230 // fold (sext (truncate (load x))) -> (sext (smaller load x))
5231 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
5232 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
5233 if (NarrowLoad.getNode()) {
5234 SDNode* oye = N0.getNode()->getOperand(0).getNode();
5235 if (NarrowLoad.getNode() != N0.getNode()) {
5236 CombineTo(N0.getNode(), NarrowLoad);
5237 // CombineTo deleted the truncate, if needed, but not what's under it.
5238 AddToWorklist(oye);
5239 }
5240 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5241 }
5243 // See if the value being truncated is already sign extended. If so, just
5244 // eliminate the trunc/sext pair.
5245 SDValue Op = N0.getOperand(0);
5246 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits();
5247 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits();
5248 unsigned DestBits = VT.getScalarType().getSizeInBits();
5249 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
5251 if (OpBits == DestBits) {
5252 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
5253 // bits, it is already ready.
5254 if (NumSignBits > DestBits-MidBits)
5255 return Op;
5256 } else if (OpBits < DestBits) {
5257 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
5258 // bits, just sext from i32.
5259 if (NumSignBits > OpBits-MidBits)
5260 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, Op);
5261 } else {
5262 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
5263 // bits, just truncate to i32.
5264 if (NumSignBits > OpBits-MidBits)
5265 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Op);
5266 }
5268 // fold (sext (truncate x)) -> (sextinreg x).
5269 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
5270 N0.getValueType())) {
5271 if (OpBits < DestBits)
5272 Op = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N0), VT, Op);
5273 else if (OpBits > DestBits)
5274 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N0), VT, Op);
5275 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, Op,
5276 DAG.getValueType(N0.getValueType()));
5277 }
5278 }
5280 // fold (sext (load x)) -> (sext (truncate (sextload x)))
5281 // None of the supported targets knows how to perform load and sign extend
5282 // on vectors in one instruction. We only perform this transformation on
5283 // scalars.
5284 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
5285 ISD::isUNINDEXEDLoad(N0.getNode()) &&
5286 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5287 TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, N0.getValueType()))) {
5288 bool DoXform = true;
5289 SmallVector<SDNode*, 4> SetCCs;
5290 if (!N0.hasOneUse())
5291 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
5292 if (DoXform) {
5293 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5294 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
5295 LN0->getChain(),
5296 LN0->getBasePtr(), N0.getValueType(),
5297 LN0->getMemOperand());
5298 CombineTo(N, ExtLoad);
5299 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
5300 N0.getValueType(), ExtLoad);
5301 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
5302 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
5303 ISD::SIGN_EXTEND);
5304 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5305 }
5306 }
5308 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
5309 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
5310 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
5311 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
5312 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5313 EVT MemVT = LN0->getMemoryVT();
5314 if ((!LegalOperations && !LN0->isVolatile()) ||
5315 TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, MemVT)) {
5316 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
5317 LN0->getChain(),
5318 LN0->getBasePtr(), MemVT,
5319 LN0->getMemOperand());
5320 CombineTo(N, ExtLoad);
5321 CombineTo(N0.getNode(),
5322 DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
5323 N0.getValueType(), ExtLoad),
5324 ExtLoad.getValue(1));
5325 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5326 }
5327 }
5329 // fold (sext (and/or/xor (load x), cst)) ->
5330 // (and/or/xor (sextload x), (sext cst))
5331 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
5332 N0.getOpcode() == ISD::XOR) &&
5333 isa<LoadSDNode>(N0.getOperand(0)) &&
5334 N0.getOperand(1).getOpcode() == ISD::Constant &&
5335 TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, N0.getValueType()) &&
5336 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
5337 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
5338 if (LN0->getExtensionType() != ISD::ZEXTLOAD && LN0->isUnindexed()) {
5339 bool DoXform = true;
5340 SmallVector<SDNode*, 4> SetCCs;
5341 if (!N0.hasOneUse())
5342 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND,
5343 SetCCs, TLI);
5344 if (DoXform) {
5345 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(LN0), VT,
5346 LN0->getChain(), LN0->getBasePtr(),
5347 LN0->getMemoryVT(),
5348 LN0->getMemOperand());
5349 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
5350 Mask = Mask.sext(VT.getSizeInBits());
5351 SDValue And = DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
5352 ExtLoad, DAG.getConstant(Mask, VT));
5353 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
5354 SDLoc(N0.getOperand(0)),
5355 N0.getOperand(0).getValueType(), ExtLoad);
5356 CombineTo(N, And);
5357 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
5358 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
5359 ISD::SIGN_EXTEND);
5360 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5361 }
5362 }
5363 }
5365 if (N0.getOpcode() == ISD::SETCC) {
5366 EVT N0VT = N0.getOperand(0).getValueType();
5367 // sext(setcc) -> sext_in_reg(vsetcc) for vectors.
5368 // Only do this before legalize for now.
5369 if (VT.isVector() && !LegalOperations &&
5370 TLI.getBooleanContents(N0VT) ==
5371 TargetLowering::ZeroOrNegativeOneBooleanContent) {
5372 // On some architectures (such as SSE/NEON/etc) the SETCC result type is
5373 // of the same size as the compared operands. Only optimize sext(setcc())
5374 // if this is the case.
5375 EVT SVT = getSetCCResultType(N0VT);
5377 // We know that the # elements of the results is the same as the
5378 // # elements of the compare (and the # elements of the compare result
5379 // for that matter). Check to see that they are the same size. If so,
5380 // we know that the element size of the sext'd result matches the
5381 // element size of the compare operands.
5382 if (VT.getSizeInBits() == SVT.getSizeInBits())
5383 return DAG.getSetCC(SDLoc(N), VT, N0.getOperand(0),
5384 N0.getOperand(1),
5385 cast<CondCodeSDNode>(N0.getOperand(2))->get());
5387 // If the desired elements are smaller or larger than the source
5388 // elements we can use a matching integer vector type and then
5389 // truncate/sign extend
5390 EVT MatchingVectorType = N0VT.changeVectorElementTypeToInteger();
5391 if (SVT == MatchingVectorType) {
5392 SDValue VsetCC = DAG.getSetCC(SDLoc(N), MatchingVectorType,
5393 N0.getOperand(0), N0.getOperand(1),
5394 cast<CondCodeSDNode>(N0.getOperand(2))->get());
5395 return DAG.getSExtOrTrunc(VsetCC, SDLoc(N), VT);
5396 }
5397 }
5399 // sext(setcc x, y, cc) -> (select (setcc x, y, cc), -1, 0)
5400 unsigned ElementWidth = VT.getScalarType().getSizeInBits();
5401 SDValue NegOne =
5402 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT);
5403 SDValue SCC =
5404 SimplifySelectCC(SDLoc(N), N0.getOperand(0), N0.getOperand(1),
5405 NegOne, DAG.getConstant(0, VT),
5406 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
5407 if (SCC.getNode()) return SCC;
5409 if (!VT.isVector()) {
5410 EVT SetCCVT = getSetCCResultType(N0.getOperand(0).getValueType());
5411 if (!LegalOperations || TLI.isOperationLegal(ISD::SETCC, SetCCVT)) {
5412 SDLoc DL(N);
5413 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
5414 SDValue SetCC = DAG.getSetCC(DL, SetCCVT,
5415 N0.getOperand(0), N0.getOperand(1), CC);
5416 return DAG.getSelect(DL, VT, SetCC,
5417 NegOne, DAG.getConstant(0, VT));
5418 }
5419 }
5420 }
5422 // fold (sext x) -> (zext x) if the sign bit is known zero.
5423 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
5424 DAG.SignBitIsZero(N0))
5425 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, N0);
5427 return SDValue();
5428 }
5430 // isTruncateOf - If N is a truncate of some other value, return true, record
5431 // the value being truncated in Op and which of Op's bits are zero in KnownZero.
5432 // This function computes KnownZero to avoid a duplicated call to
5433 // computeKnownBits in the caller.
5434 static bool isTruncateOf(SelectionDAG &DAG, SDValue N, SDValue &Op,
5435 APInt &KnownZero) {
5436 APInt KnownOne;
5437 if (N->getOpcode() == ISD::TRUNCATE) {
5438 Op = N->getOperand(0);
5439 DAG.computeKnownBits(Op, KnownZero, KnownOne);
5440 return true;
5441 }
5443 if (N->getOpcode() != ISD::SETCC || N->getValueType(0) != MVT::i1 ||
5444 cast<CondCodeSDNode>(N->getOperand(2))->get() != ISD::SETNE)
5445 return false;
5447 SDValue Op0 = N->getOperand(0);
5448 SDValue Op1 = N->getOperand(1);
5449 assert(Op0.getValueType() == Op1.getValueType());
5451 ConstantSDNode *COp0 = dyn_cast<ConstantSDNode>(Op0);
5452 ConstantSDNode *COp1 = dyn_cast<ConstantSDNode>(Op1);
5453 if (COp0 && COp0->isNullValue())
5454 Op = Op1;
5455 else if (COp1 && COp1->isNullValue())
5456 Op = Op0;
5457 else
5458 return false;
5460 DAG.computeKnownBits(Op, KnownZero, KnownOne);
5462 if (!(KnownZero | APInt(Op.getValueSizeInBits(), 1)).isAllOnesValue())
5463 return false;
5465 return true;
5466 }
5468 SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
5469 SDValue N0 = N->getOperand(0);
5470 EVT VT = N->getValueType(0);
5472 if (SDNode *Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes,
5473 LegalOperations))
5474 return SDValue(Res, 0);
5476 // fold (zext (zext x)) -> (zext x)
5477 // fold (zext (aext x)) -> (zext x)
5478 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
5479 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT,
5480 N0.getOperand(0));
5482 // fold (zext (truncate x)) -> (zext x) or
5483 // (zext (truncate x)) -> (truncate x)
5484 // This is valid when the truncated bits of x are already zero.
5485 // FIXME: We should extend this to work for vectors too.
5486 SDValue Op;
5487 APInt KnownZero;
5488 if (!VT.isVector() && isTruncateOf(DAG, N0, Op, KnownZero)) {
5489 APInt TruncatedBits =
5490 (Op.getValueSizeInBits() == N0.getValueSizeInBits()) ?
5491 APInt(Op.getValueSizeInBits(), 0) :
5492 APInt::getBitsSet(Op.getValueSizeInBits(),
5493 N0.getValueSizeInBits(),
5494 std::min(Op.getValueSizeInBits(),
5495 VT.getSizeInBits()));
5496 if (TruncatedBits == (KnownZero & TruncatedBits)) {
5497 if (VT.bitsGT(Op.getValueType()))
5498 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, Op);
5499 if (VT.bitsLT(Op.getValueType()))
5500 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Op);
5502 return Op;
5503 }
5504 }
5506 // fold (zext (truncate (load x))) -> (zext (smaller load x))
5507 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
5508 if (N0.getOpcode() == ISD::TRUNCATE) {
5509 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
5510 if (NarrowLoad.getNode()) {
5511 SDNode* oye = N0.getNode()->getOperand(0).getNode();
5512 if (NarrowLoad.getNode() != N0.getNode()) {
5513 CombineTo(N0.getNode(), NarrowLoad);
5514 // CombineTo deleted the truncate, if needed, but not what's under it.
5515 AddToWorklist(oye);
5516 }
5517 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5518 }
5519 }
5521 // fold (zext (truncate x)) -> (and x, mask)
5522 if (N0.getOpcode() == ISD::TRUNCATE &&
5523 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) {
5525 // fold (zext (truncate (load x))) -> (zext (smaller load x))
5526 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n)))
5527 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
5528 if (NarrowLoad.getNode()) {
5529 SDNode* oye = N0.getNode()->getOperand(0).getNode();
5530 if (NarrowLoad.getNode() != N0.getNode()) {
5531 CombineTo(N0.getNode(), NarrowLoad);
5532 // CombineTo deleted the truncate, if needed, but not what's under it.
5533 AddToWorklist(oye);
5534 }
5535 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5536 }
5538 SDValue Op = N0.getOperand(0);
5539 if (Op.getValueType().bitsLT(VT)) {
5540 Op = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, Op);
5541 AddToWorklist(Op.getNode());
5542 } else if (Op.getValueType().bitsGT(VT)) {
5543 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Op);
5544 AddToWorklist(Op.getNode());
5545 }
5546 return DAG.getZeroExtendInReg(Op, SDLoc(N),
5547 N0.getValueType().getScalarType());
5548 }
5550 // Fold (zext (and (trunc x), cst)) -> (and x, cst),
5551 // if either of the casts is not free.
5552 if (N0.getOpcode() == ISD::AND &&
5553 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
5554 N0.getOperand(1).getOpcode() == ISD::Constant &&
5555 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
5556 N0.getValueType()) ||
5557 !TLI.isZExtFree(N0.getValueType(), VT))) {
5558 SDValue X = N0.getOperand(0).getOperand(0);
5559 if (X.getValueType().bitsLT(VT)) {
5560 X = DAG.getNode(ISD::ANY_EXTEND, SDLoc(X), VT, X);
5561 } else if (X.getValueType().bitsGT(VT)) {
5562 X = DAG.getNode(ISD::TRUNCATE, SDLoc(X), VT, X);
5563 }
5564 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
5565 Mask = Mask.zext(VT.getSizeInBits());
5566 return DAG.getNode(ISD::AND, SDLoc(N), VT,
5567 X, DAG.getConstant(Mask, VT));
5568 }
5570 // fold (zext (load x)) -> (zext (truncate (zextload x)))
5571 // None of the supported targets knows how to perform load and vector_zext
5572 // on vectors in one instruction. We only perform this transformation on
5573 // scalars.
5574 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
5575 ISD::isUNINDEXEDLoad(N0.getNode()) &&
5576 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5577 TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, N0.getValueType()))) {
5578 bool DoXform = true;
5579 SmallVector<SDNode*, 4> SetCCs;
5580 if (!N0.hasOneUse())
5581 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
5582 if (DoXform) {
5583 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5584 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N), VT,
5585 LN0->getChain(),
5586 LN0->getBasePtr(), N0.getValueType(),
5587 LN0->getMemOperand());
5588 CombineTo(N, ExtLoad);
5589 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
5590 N0.getValueType(), ExtLoad);
5591 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
5593 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
5594 ISD::ZERO_EXTEND);
5595 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5596 }
5597 }
5599 // fold (zext (and/or/xor (load x), cst)) ->
5600 // (and/or/xor (zextload x), (zext cst))
5601 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
5602 N0.getOpcode() == ISD::XOR) &&
5603 isa<LoadSDNode>(N0.getOperand(0)) &&
5604 N0.getOperand(1).getOpcode() == ISD::Constant &&
5605 TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, N0.getValueType()) &&
5606 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
5607 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
5608 if (LN0->getExtensionType() != ISD::SEXTLOAD && LN0->isUnindexed()) {
5609 bool DoXform = true;
5610 SmallVector<SDNode*, 4> SetCCs;
5611 if (!N0.hasOneUse())
5612 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND,
5613 SetCCs, TLI);
5614 if (DoXform) {
5615 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), VT,
5616 LN0->getChain(), LN0->getBasePtr(),
5617 LN0->getMemoryVT(),
5618 LN0->getMemOperand());
5619 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
5620 Mask = Mask.zext(VT.getSizeInBits());
5621 SDValue And = DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
5622 ExtLoad, DAG.getConstant(Mask, VT));
5623 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
5624 SDLoc(N0.getOperand(0)),
5625 N0.getOperand(0).getValueType(), ExtLoad);
5626 CombineTo(N, And);
5627 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
5628 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
5629 ISD::ZERO_EXTEND);
5630 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5631 }
5632 }
5633 }
5635 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
5636 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
5637 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
5638 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
5639 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5640 EVT MemVT = LN0->getMemoryVT();
5641 if ((!LegalOperations && !LN0->isVolatile()) ||
5642 TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, MemVT)) {
5643 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N), VT,
5644 LN0->getChain(),
5645 LN0->getBasePtr(), MemVT,
5646 LN0->getMemOperand());
5647 CombineTo(N, ExtLoad);
5648 CombineTo(N0.getNode(),
5649 DAG.getNode(ISD::TRUNCATE, SDLoc(N0), N0.getValueType(),
5650 ExtLoad),
5651 ExtLoad.getValue(1));
5652 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5653 }
5654 }
5656 if (N0.getOpcode() == ISD::SETCC) {
5657 if (!LegalOperations && VT.isVector() &&
5658 N0.getValueType().getVectorElementType() == MVT::i1) {
5659 EVT N0VT = N0.getOperand(0).getValueType();
5660 if (getSetCCResultType(N0VT) == N0.getValueType())
5661 return SDValue();
5663 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors.
5664 // Only do this before legalize for now.
5665 EVT EltVT = VT.getVectorElementType();
5666 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(),
5667 DAG.getConstant(1, EltVT));
5668 if (VT.getSizeInBits() == N0VT.getSizeInBits())
5669 // We know that the # elements of the results is the same as the
5670 // # elements of the compare (and the # elements of the compare result
5671 // for that matter). Check to see that they are the same size. If so,
5672 // we know that the element size of the sext'd result matches the
5673 // element size of the compare operands.
5674 return DAG.getNode(ISD::AND, SDLoc(N), VT,
5675 DAG.getSetCC(SDLoc(N), VT, N0.getOperand(0),
5676 N0.getOperand(1),
5677 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
5678 DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT,
5679 OneOps));
5681 // If the desired elements are smaller or larger than the source
5682 // elements we can use a matching integer vector type and then
5683 // truncate/sign extend
5684 EVT MatchingElementType =
5685 EVT::getIntegerVT(*DAG.getContext(),
5686 N0VT.getScalarType().getSizeInBits());
5687 EVT MatchingVectorType =
5688 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
5689 N0VT.getVectorNumElements());
5690 SDValue VsetCC =
5691 DAG.getSetCC(SDLoc(N), MatchingVectorType, N0.getOperand(0),
5692 N0.getOperand(1),
5693 cast<CondCodeSDNode>(N0.getOperand(2))->get());
5694 return DAG.getNode(ISD::AND, SDLoc(N), VT,
5695 DAG.getSExtOrTrunc(VsetCC, SDLoc(N), VT),
5696 DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, OneOps));
5697 }
5699 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
5700 SDValue SCC =
5701 SimplifySelectCC(SDLoc(N), N0.getOperand(0), N0.getOperand(1),
5702 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
5703 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
5704 if (SCC.getNode()) return SCC;
5705 }
5707 // (zext (shl (zext x), cst)) -> (shl (zext x), cst)
5708 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
5709 isa<ConstantSDNode>(N0.getOperand(1)) &&
5710 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
5711 N0.hasOneUse()) {
5712 SDValue ShAmt = N0.getOperand(1);
5713 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue();
5714 if (N0.getOpcode() == ISD::SHL) {
5715 SDValue InnerZExt = N0.getOperand(0);
5716 // If the original shl may be shifting out bits, do not perform this
5717 // transformation.
5718 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() -
5719 InnerZExt.getOperand(0).getValueType().getSizeInBits();
5720 if (ShAmtVal > KnownZeroBits)
5721 return SDValue();
5722 }
5724 SDLoc DL(N);
5726 // Ensure that the shift amount is wide enough for the shifted value.
5727 if (VT.getSizeInBits() >= 256)
5728 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt);
5730 return DAG.getNode(N0.getOpcode(), DL, VT,
5731 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)),
5732 ShAmt);
5733 }
5735 return SDValue();
5736 }
5738 SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
5739 SDValue N0 = N->getOperand(0);
5740 EVT VT = N->getValueType(0);
5742 if (SDNode *Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes,
5743 LegalOperations))
5744 return SDValue(Res, 0);
5746 // fold (aext (aext x)) -> (aext x)
5747 // fold (aext (zext x)) -> (zext x)
5748 // fold (aext (sext x)) -> (sext x)
5749 if (N0.getOpcode() == ISD::ANY_EXTEND ||
5750 N0.getOpcode() == ISD::ZERO_EXTEND ||
5751 N0.getOpcode() == ISD::SIGN_EXTEND)
5752 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, N0.getOperand(0));
5754 // fold (aext (truncate (load x))) -> (aext (smaller load x))
5755 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
5756 if (N0.getOpcode() == ISD::TRUNCATE) {
5757 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
5758 if (NarrowLoad.getNode()) {
5759 SDNode* oye = N0.getNode()->getOperand(0).getNode();
5760 if (NarrowLoad.getNode() != N0.getNode()) {
5761 CombineTo(N0.getNode(), NarrowLoad);
5762 // CombineTo deleted the truncate, if needed, but not what's under it.
5763 AddToWorklist(oye);
5764 }
5765 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5766 }
5767 }
5769 // fold (aext (truncate x))
5770 if (N0.getOpcode() == ISD::TRUNCATE) {
5771 SDValue TruncOp = N0.getOperand(0);
5772 if (TruncOp.getValueType() == VT)
5773 return TruncOp; // x iff x size == zext size.
5774 if (TruncOp.getValueType().bitsGT(VT))
5775 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, TruncOp);
5776 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, TruncOp);
5777 }
5779 // Fold (aext (and (trunc x), cst)) -> (and x, cst)
5780 // if the trunc is not free.
5781 if (N0.getOpcode() == ISD::AND &&
5782 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
5783 N0.getOperand(1).getOpcode() == ISD::Constant &&
5784 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
5785 N0.getValueType())) {
5786 SDValue X = N0.getOperand(0).getOperand(0);
5787 if (X.getValueType().bitsLT(VT)) {
5788 X = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, X);
5789 } else if (X.getValueType().bitsGT(VT)) {
5790 X = DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, X);
5791 }
5792 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
5793 Mask = Mask.zext(VT.getSizeInBits());
5794 return DAG.getNode(ISD::AND, SDLoc(N), VT,
5795 X, DAG.getConstant(Mask, VT));
5796 }
5798 // fold (aext (load x)) -> (aext (truncate (extload x)))
5799 // None of the supported targets knows how to perform load and any_ext
5800 // on vectors in one instruction. We only perform this transformation on
5801 // scalars.
5802 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
5803 ISD::isUNINDEXEDLoad(N0.getNode()) &&
5804 TLI.isLoadExtLegal(ISD::EXTLOAD, VT, N0.getValueType())) {
5805 bool DoXform = true;
5806 SmallVector<SDNode*, 4> SetCCs;
5807 if (!N0.hasOneUse())
5808 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
5809 if (DoXform) {
5810 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5811 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(N), VT,
5812 LN0->getChain(),
5813 LN0->getBasePtr(), N0.getValueType(),
5814 LN0->getMemOperand());
5815 CombineTo(N, ExtLoad);
5816 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
5817 N0.getValueType(), ExtLoad);
5818 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
5819 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
5820 ISD::ANY_EXTEND);
5821 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5822 }
5823 }
5825 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
5826 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
5827 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
5828 if (N0.getOpcode() == ISD::LOAD &&
5829 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
5830 N0.hasOneUse()) {
5831 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5832 ISD::LoadExtType ExtType = LN0->getExtensionType();
5833 EVT MemVT = LN0->getMemoryVT();
5834 if (!LegalOperations || TLI.isLoadExtLegal(ExtType, VT, MemVT)) {
5835 SDValue ExtLoad = DAG.getExtLoad(ExtType, SDLoc(N),
5836 VT, LN0->getChain(), LN0->getBasePtr(),
5837 MemVT, LN0->getMemOperand());
5838 CombineTo(N, ExtLoad);
5839 CombineTo(N0.getNode(),
5840 DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
5841 N0.getValueType(), ExtLoad),
5842 ExtLoad.getValue(1));
5843 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5844 }
5845 }
5847 if (N0.getOpcode() == ISD::SETCC) {
5848 // For vectors:
5849 // aext(setcc) -> vsetcc
5850 // aext(setcc) -> truncate(vsetcc)
5851 // aext(setcc) -> aext(vsetcc)
5852 // Only do this before legalize for now.
5853 if (VT.isVector() && !LegalOperations) {
5854 EVT N0VT = N0.getOperand(0).getValueType();
5855 // We know that the # elements of the results is the same as the
5856 // # elements of the compare (and the # elements of the compare result
5857 // for that matter). Check to see that they are the same size. If so,
5858 // we know that the element size of the sext'd result matches the
5859 // element size of the compare operands.
5860 if (VT.getSizeInBits() == N0VT.getSizeInBits())
5861 return DAG.getSetCC(SDLoc(N), VT, N0.getOperand(0),
5862 N0.getOperand(1),
5863 cast<CondCodeSDNode>(N0.getOperand(2))->get());
5864 // If the desired elements are smaller or larger than the source
5865 // elements we can use a matching integer vector type and then
5866 // truncate/any extend
5867 else {
5868 EVT MatchingVectorType = N0VT.changeVectorElementTypeToInteger();
5869 SDValue VsetCC =
5870 DAG.getSetCC(SDLoc(N), MatchingVectorType, N0.getOperand(0),
5871 N0.getOperand(1),
5872 cast<CondCodeSDNode>(N0.getOperand(2))->get());
5873 return DAG.getAnyExtOrTrunc(VsetCC, SDLoc(N), VT);
5874 }
5875 }
5877 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
5878 SDValue SCC =
5879 SimplifySelectCC(SDLoc(N), N0.getOperand(0), N0.getOperand(1),
5880 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
5881 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
5882 if (SCC.getNode())
5883 return SCC;
5884 }
5886 return SDValue();
5887 }
5889 /// See if the specified operand can be simplified with the knowledge that only
5890 /// the bits specified by Mask are used. If so, return the simpler operand,
5891 /// otherwise return a null SDValue.
5892 SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
5893 switch (V.getOpcode()) {
5894 default: break;
5895 case ISD::Constant: {
5896 const ConstantSDNode *CV = cast<ConstantSDNode>(V.getNode());
5897 assert(CV && "Const value should be ConstSDNode.");
5898 const APInt &CVal = CV->getAPIntValue();
5899 APInt NewVal = CVal & Mask;
5900 if (NewVal != CVal)
5901 return DAG.getConstant(NewVal, V.getValueType());
5902 break;
5903 }
5904 case ISD::OR:
5905 case ISD::XOR:
5906 // If the LHS or RHS don't contribute bits to the or, drop them.
5907 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
5908 return V.getOperand(1);
5909 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
5910 return V.getOperand(0);
5911 break;
5912 case ISD::SRL:
5913 // Only look at single-use SRLs.
5914 if (!V.getNode()->hasOneUse())
5915 break;
5916 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
5917 // See if we can recursively simplify the LHS.
5918 unsigned Amt = RHSC->getZExtValue();
5920 // Watch out for shift count overflow though.
5921 if (Amt >= Mask.getBitWidth()) break;
5922 APInt NewMask = Mask << Amt;
5923 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
5924 if (SimplifyLHS.getNode())
5925 return DAG.getNode(ISD::SRL, SDLoc(V), V.getValueType(),
5926 SimplifyLHS, V.getOperand(1));
5927 }
5928 }
5929 return SDValue();
5930 }
5932 /// If the result of a wider load is shifted to right of N bits and then
5933 /// truncated to a narrower type and where N is a multiple of number of bits of
5934 /// the narrower type, transform it to a narrower load from address + N / num of
5935 /// bits of new type. If the result is to be extended, also fold the extension
5936 /// to form a extending load.
5937 SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
5938 unsigned Opc = N->getOpcode();
5940 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
5941 SDValue N0 = N->getOperand(0);
5942 EVT VT = N->getValueType(0);
5943 EVT ExtVT = VT;
5945 // This transformation isn't valid for vector loads.
5946 if (VT.isVector())
5947 return SDValue();
5949 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then
5950 // extended to VT.
5951 if (Opc == ISD::SIGN_EXTEND_INREG) {
5952 ExtType = ISD::SEXTLOAD;
5953 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT();
5954 } else if (Opc == ISD::SRL) {
5955 // Another special-case: SRL is basically zero-extending a narrower value.
5956 ExtType = ISD::ZEXTLOAD;
5957 N0 = SDValue(N, 0);
5958 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1));
5959 if (!N01) return SDValue();
5960 ExtVT = EVT::getIntegerVT(*DAG.getContext(),
5961 VT.getSizeInBits() - N01->getZExtValue());
5962 }
5963 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, VT, ExtVT))
5964 return SDValue();
5966 unsigned EVTBits = ExtVT.getSizeInBits();
5968 // Do not generate loads of non-round integer types since these can
5969 // be expensive (and would be wrong if the type is not byte sized).
5970 if (!ExtVT.isRound())
5971 return SDValue();
5973 unsigned ShAmt = 0;
5974 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
5975 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
5976 ShAmt = N01->getZExtValue();
5977 // Is the shift amount a multiple of size of VT?
5978 if ((ShAmt & (EVTBits-1)) == 0) {
5979 N0 = N0.getOperand(0);
5980 // Is the load width a multiple of size of VT?
5981 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0)
5982 return SDValue();
5983 }
5985 // At this point, we must have a load or else we can't do the transform.
5986 if (!isa<LoadSDNode>(N0)) return SDValue();
5988 // Because a SRL must be assumed to *need* to zero-extend the high bits
5989 // (as opposed to anyext the high bits), we can't combine the zextload
5990 // lowering of SRL and an sextload.
5991 if (cast<LoadSDNode>(N0)->getExtensionType() == ISD::SEXTLOAD)
5992 return SDValue();
5994 // If the shift amount is larger than the input type then we're not
5995 // accessing any of the loaded bytes. If the load was a zextload/extload
5996 // then the result of the shift+trunc is zero/undef (handled elsewhere).
5997 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits())
5998 return SDValue();
5999 }
6000 }
6002 // If the load is shifted left (and the result isn't shifted back right),
6003 // we can fold the truncate through the shift.
6004 unsigned ShLeftAmt = 0;
6005 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
6006 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) {
6007 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
6008 ShLeftAmt = N01->getZExtValue();
6009 N0 = N0.getOperand(0);
6010 }
6011 }
6013 // If we haven't found a load, we can't narrow it. Don't transform one with
6014 // multiple uses, this would require adding a new load.
6015 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse())
6016 return SDValue();
6018 // Don't change the width of a volatile load.
6019 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6020 if (LN0->isVolatile())
6021 return SDValue();
6023 // Verify that we are actually reducing a load width here.
6024 if (LN0->getMemoryVT().getSizeInBits() < EVTBits)
6025 return SDValue();
6027 // For the transform to be legal, the load must produce only two values
6028 // (the value loaded and the chain). Don't transform a pre-increment
6029 // load, for example, which produces an extra value. Otherwise the
6030 // transformation is not equivalent, and the downstream logic to replace
6031 // uses gets things wrong.
6032 if (LN0->getNumValues() > 2)
6033 return SDValue();
6035 // If the load that we're shrinking is an extload and we're not just
6036 // discarding the extension we can't simply shrink the load. Bail.
6037 // TODO: It would be possible to merge the extensions in some cases.
6038 if (LN0->getExtensionType() != ISD::NON_EXTLOAD &&
6039 LN0->getMemoryVT().getSizeInBits() < ExtVT.getSizeInBits() + ShAmt)
6040 return SDValue();
6042 if (!TLI.shouldReduceLoadWidth(LN0, ExtType, ExtVT))
6043 return SDValue();
6045 EVT PtrType = N0.getOperand(1).getValueType();
6047 if (PtrType == MVT::Untyped || PtrType.isExtended())
6048 // It's not possible to generate a constant of extended or untyped type.
6049 return SDValue();
6051 // For big endian targets, we need to adjust the offset to the pointer to
6052 // load the correct bytes.
6053 if (TLI.isBigEndian()) {
6054 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
6055 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits();
6056 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
6057 }
6059 uint64_t PtrOff = ShAmt / 8;
6060 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
6061 SDValue NewPtr = DAG.getNode(ISD::ADD, SDLoc(LN0),
6062 PtrType, LN0->getBasePtr(),
6063 DAG.getConstant(PtrOff, PtrType));
6064 AddToWorklist(NewPtr.getNode());
6066 SDValue Load;
6067 if (ExtType == ISD::NON_EXTLOAD)
6068 Load = DAG.getLoad(VT, SDLoc(N0), LN0->getChain(), NewPtr,
6069 LN0->getPointerInfo().getWithOffset(PtrOff),
6070 LN0->isVolatile(), LN0->isNonTemporal(),
6071 LN0->isInvariant(), NewAlign, LN0->getAAInfo());
6072 else
6073 Load = DAG.getExtLoad(ExtType, SDLoc(N0), VT, LN0->getChain(),NewPtr,
6074 LN0->getPointerInfo().getWithOffset(PtrOff),
6075 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
6076 LN0->isInvariant(), NewAlign, LN0->getAAInfo());
6078 // Replace the old load's chain with the new load's chain.
6079 WorklistRemover DeadNodes(*this);
6080 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1));
6082 // Shift the result left, if we've swallowed a left shift.
6083 SDValue Result = Load;
6084 if (ShLeftAmt != 0) {
6085 EVT ShImmTy = getShiftAmountTy(Result.getValueType());
6086 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt))
6087 ShImmTy = VT;
6088 // If the shift amount is as large as the result size (but, presumably,
6089 // no larger than the source) then the useful bits of the result are
6090 // zero; we can't simply return the shortened shift, because the result
6091 // of that operation is undefined.
6092 if (ShLeftAmt >= VT.getSizeInBits())
6093 Result = DAG.getConstant(0, VT);
6094 else
6095 Result = DAG.getNode(ISD::SHL, SDLoc(N0), VT,
6096 Result, DAG.getConstant(ShLeftAmt, ShImmTy));
6097 }
6099 // Return the new loaded value.
6100 return Result;
6101 }
6103 SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
6104 SDValue N0 = N->getOperand(0);
6105 SDValue N1 = N->getOperand(1);
6106 EVT VT = N->getValueType(0);
6107 EVT EVT = cast<VTSDNode>(N1)->getVT();
6108 unsigned VTBits = VT.getScalarType().getSizeInBits();
6109 unsigned EVTBits = EVT.getScalarType().getSizeInBits();
6111 // fold (sext_in_reg c1) -> c1
6112 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
6113 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, N0, N1);
6115 // If the input is already sign extended, just drop the extension.
6116 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1)
6117 return N0;
6119 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
6120 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
6121 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT()))
6122 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT,
6123 N0.getOperand(0), N1);
6125 // fold (sext_in_reg (sext x)) -> (sext x)
6126 // fold (sext_in_reg (aext x)) -> (sext x)
6127 // if x is small enough.
6128 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
6129 SDValue N00 = N0.getOperand(0);
6130 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits &&
6131 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)))
6132 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, N00, N1);
6133 }
6135 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
6136 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
6137 return DAG.getZeroExtendInReg(N0, SDLoc(N), EVT);
6139 // fold operands of sext_in_reg based on knowledge that the top bits are not
6140 // demanded.
6141 if (SimplifyDemandedBits(SDValue(N, 0)))
6142 return SDValue(N, 0);
6144 // fold (sext_in_reg (load x)) -> (smaller sextload x)
6145 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
6146 SDValue NarrowLoad = ReduceLoadWidth(N);
6147 if (NarrowLoad.getNode())
6148 return NarrowLoad;
6150 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24)
6151 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
6152 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
6153 if (N0.getOpcode() == ISD::SRL) {
6154 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
6155 if (ShAmt->getZExtValue()+EVTBits <= VTBits) {
6156 // We can turn this into an SRA iff the input to the SRL is already sign
6157 // extended enough.
6158 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
6159 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
6160 return DAG.getNode(ISD::SRA, SDLoc(N), VT,
6161 N0.getOperand(0), N0.getOperand(1));
6162 }
6163 }
6165 // fold (sext_inreg (extload x)) -> (sextload x)
6166 if (ISD::isEXTLoad(N0.getNode()) &&
6167 ISD::isUNINDEXEDLoad(N0.getNode()) &&
6168 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
6169 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
6170 TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, EVT))) {
6171 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6172 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
6173 LN0->getChain(),
6174 LN0->getBasePtr(), EVT,
6175 LN0->getMemOperand());
6176 CombineTo(N, ExtLoad);
6177 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
6178 AddToWorklist(ExtLoad.getNode());
6179 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6180 }
6181 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
6182 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
6183 N0.hasOneUse() &&
6184 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
6185 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
6186 TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, EVT))) {
6187 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6188 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
6189 LN0->getChain(),
6190 LN0->getBasePtr(), EVT,
6191 LN0->getMemOperand());
6192 CombineTo(N, ExtLoad);
6193 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
6194 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6195 }
6197 // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16))
6198 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) {
6199 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
6200 N0.getOperand(1), false);
6201 if (BSwap.getNode())
6202 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT,
6203 BSwap, N1);
6204 }
6206 // Fold a sext_inreg of a build_vector of ConstantSDNodes or undefs
6207 // into a build_vector.
6208 if (ISD::isBuildVectorOfConstantSDNodes(N0.getNode())) {
6209 SmallVector<SDValue, 8> Elts;
6210 unsigned NumElts = N0->getNumOperands();
6211 unsigned ShAmt = VTBits - EVTBits;
6213 for (unsigned i = 0; i != NumElts; ++i) {
6214 SDValue Op = N0->getOperand(i);
6215 if (Op->getOpcode() == ISD::UNDEF) {
6216 Elts.push_back(Op);
6217 continue;
6218 }
6220 ConstantSDNode *CurrentND = cast<ConstantSDNode>(Op);
6221 const APInt &C = APInt(VTBits, CurrentND->getAPIntValue().getZExtValue());
6222 Elts.push_back(DAG.getConstant(C.shl(ShAmt).ashr(ShAmt).getZExtValue(),
6223 Op.getValueType()));
6224 }
6226 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, Elts);
6227 }
6229 return SDValue();
6230 }
6232 SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
6233 SDValue N0 = N->getOperand(0);
6234 EVT VT = N->getValueType(0);
6235 bool isLE = TLI.isLittleEndian();
6237 // noop truncate
6238 if (N0.getValueType() == N->getValueType(0))
6239 return N0;
6240 // fold (truncate c1) -> c1
6241 if (isa<ConstantSDNode>(N0))
6242 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0);
6243 // fold (truncate (truncate x)) -> (truncate x)
6244 if (N0.getOpcode() == ISD::TRUNCATE)
6245 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0.getOperand(0));
6246 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
6247 if (N0.getOpcode() == ISD::ZERO_EXTEND ||
6248 N0.getOpcode() == ISD::SIGN_EXTEND ||
6249 N0.getOpcode() == ISD::ANY_EXTEND) {
6250 if (N0.getOperand(0).getValueType().bitsLT(VT))
6251 // if the source is smaller than the dest, we still need an extend
6252 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
6253 N0.getOperand(0));
6254 if (N0.getOperand(0).getValueType().bitsGT(VT))
6255 // if the source is larger than the dest, than we just need the truncate
6256 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0.getOperand(0));
6257 // if the source and dest are the same type, we can drop both the extend
6258 // and the truncate.
6259 return N0.getOperand(0);
6260 }
6262 // Fold extract-and-trunc into a narrow extract. For example:
6263 // i64 x = EXTRACT_VECTOR_ELT(v2i64 val, i32 1)
6264 // i32 y = TRUNCATE(i64 x)
6265 // -- becomes --
6266 // v16i8 b = BITCAST (v2i64 val)
6267 // i8 x = EXTRACT_VECTOR_ELT(v16i8 b, i32 8)
6268 //
6269 // Note: We only run this optimization after type legalization (which often
6270 // creates this pattern) and before operation legalization after which
6271 // we need to be more careful about the vector instructions that we generate.
6272 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6273 LegalTypes && !LegalOperations && N0->hasOneUse() && VT != MVT::i1) {
6275 EVT VecTy = N0.getOperand(0).getValueType();
6276 EVT ExTy = N0.getValueType();
6277 EVT TrTy = N->getValueType(0);
6279 unsigned NumElem = VecTy.getVectorNumElements();
6280 unsigned SizeRatio = ExTy.getSizeInBits()/TrTy.getSizeInBits();
6282 EVT NVT = EVT::getVectorVT(*DAG.getContext(), TrTy, SizeRatio * NumElem);
6283 assert(NVT.getSizeInBits() == VecTy.getSizeInBits() && "Invalid Size");
6285 SDValue EltNo = N0->getOperand(1);
6286 if (isa<ConstantSDNode>(EltNo) && isTypeLegal(NVT)) {
6287 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6288 EVT IndexTy = TLI.getVectorIdxTy();
6289 int Index = isLE ? (Elt*SizeRatio) : (Elt*SizeRatio + (SizeRatio-1));
6291 SDValue V = DAG.getNode(ISD::BITCAST, SDLoc(N),
6292 NVT, N0.getOperand(0));
6294 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
6295 SDLoc(N), TrTy, V,
6296 DAG.getConstant(Index, IndexTy));
6297 }
6298 }
6300 // trunc (select c, a, b) -> select c, (trunc a), (trunc b)
6301 if (N0.getOpcode() == ISD::SELECT) {
6302 EVT SrcVT = N0.getValueType();
6303 if ((!LegalOperations || TLI.isOperationLegal(ISD::SELECT, SrcVT)) &&
6304 TLI.isTruncateFree(SrcVT, VT)) {
6305 SDLoc SL(N0);
6306 SDValue Cond = N0.getOperand(0);
6307 SDValue TruncOp0 = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(1));
6308 SDValue TruncOp1 = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(2));
6309 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, Cond, TruncOp0, TruncOp1);
6310 }
6311 }
6313 // Fold a series of buildvector, bitcast, and truncate if possible.
6314 // For example fold
6315 // (2xi32 trunc (bitcast ((4xi32)buildvector x, x, y, y) 2xi64)) to
6316 // (2xi32 (buildvector x, y)).
6317 if (Level == AfterLegalizeVectorOps && VT.isVector() &&
6318 N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() &&
6319 N0.getOperand(0).getOpcode() == ISD::BUILD_VECTOR &&
6320 N0.getOperand(0).hasOneUse()) {
6322 SDValue BuildVect = N0.getOperand(0);
6323 EVT BuildVectEltTy = BuildVect.getValueType().getVectorElementType();
6324 EVT TruncVecEltTy = VT.getVectorElementType();
6326 // Check that the element types match.
6327 if (BuildVectEltTy == TruncVecEltTy) {
6328 // Now we only need to compute the offset of the truncated elements.
6329 unsigned BuildVecNumElts = BuildVect.getNumOperands();
6330 unsigned TruncVecNumElts = VT.getVectorNumElements();
6331 unsigned TruncEltOffset = BuildVecNumElts / TruncVecNumElts;
6333 assert((BuildVecNumElts % TruncVecNumElts) == 0 &&
6334 "Invalid number of elements");
6336 SmallVector<SDValue, 8> Opnds;
6337 for (unsigned i = 0, e = BuildVecNumElts; i != e; i += TruncEltOffset)
6338 Opnds.push_back(BuildVect.getOperand(i));
6340 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, Opnds);
6341 }
6342 }
6344 // See if we can simplify the input to this truncate through knowledge that
6345 // only the low bits are being used.
6346 // For example "trunc (or (shl x, 8), y)" // -> trunc y
6347 // Currently we only perform this optimization on scalars because vectors
6348 // may have different active low bits.
6349 if (!VT.isVector()) {
6350 SDValue Shorter =
6351 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
6352 VT.getSizeInBits()));
6353 if (Shorter.getNode())
6354 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Shorter);
6355 }
6356 // fold (truncate (load x)) -> (smaller load x)
6357 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
6358 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) {
6359 SDValue Reduced = ReduceLoadWidth(N);
6360 if (Reduced.getNode())
6361 return Reduced;
6362 // Handle the case where the load remains an extending load even
6363 // after truncation.
6364 if (N0.hasOneUse() && ISD::isUNINDEXEDLoad(N0.getNode())) {
6365 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6366 if (!LN0->isVolatile() &&
6367 LN0->getMemoryVT().getStoreSizeInBits() < VT.getSizeInBits()) {
6368 SDValue NewLoad = DAG.getExtLoad(LN0->getExtensionType(), SDLoc(LN0),
6369 VT, LN0->getChain(), LN0->getBasePtr(),
6370 LN0->getMemoryVT(),
6371 LN0->getMemOperand());
6372 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLoad.getValue(1));
6373 return NewLoad;
6374 }
6375 }
6376 }
6377 // fold (trunc (concat ... x ...)) -> (concat ..., (trunc x), ...)),
6378 // where ... are all 'undef'.
6379 if (N0.getOpcode() == ISD::CONCAT_VECTORS && !LegalTypes) {
6380 SmallVector<EVT, 8> VTs;
6381 SDValue V;
6382 unsigned Idx = 0;
6383 unsigned NumDefs = 0;
6385 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) {
6386 SDValue X = N0.getOperand(i);
6387 if (X.getOpcode() != ISD::UNDEF) {
6388 V = X;
6389 Idx = i;
6390 NumDefs++;
6391 }
6392 // Stop if more than one members are non-undef.
6393 if (NumDefs > 1)
6394 break;
6395 VTs.push_back(EVT::getVectorVT(*DAG.getContext(),
6396 VT.getVectorElementType(),
6397 X.getValueType().getVectorNumElements()));
6398 }
6400 if (NumDefs == 0)
6401 return DAG.getUNDEF(VT);
6403 if (NumDefs == 1) {
6404 assert(V.getNode() && "The single defined operand is empty!");
6405 SmallVector<SDValue, 8> Opnds;
6406 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
6407 if (i != Idx) {
6408 Opnds.push_back(DAG.getUNDEF(VTs[i]));
6409 continue;
6410 }
6411 SDValue NV = DAG.getNode(ISD::TRUNCATE, SDLoc(V), VTs[i], V);
6412 AddToWorklist(NV.getNode());
6413 Opnds.push_back(NV);
6414 }
6415 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Opnds);
6416 }
6417 }
6419 // Simplify the operands using demanded-bits information.
6420 if (!VT.isVector() &&
6421 SimplifyDemandedBits(SDValue(N, 0)))
6422 return SDValue(N, 0);
6424 return SDValue();
6425 }
6427 static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
6428 SDValue Elt = N->getOperand(i);
6429 if (Elt.getOpcode() != ISD::MERGE_VALUES)
6430 return Elt.getNode();
6431 return Elt.getOperand(Elt.getResNo()).getNode();
6432 }
6434 /// build_pair (load, load) -> load
6435 /// if load locations are consecutive.
6436 SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) {
6437 assert(N->getOpcode() == ISD::BUILD_PAIR);
6439 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0));
6440 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1));
6441 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() ||
6442 LD1->getAddressSpace() != LD2->getAddressSpace())
6443 return SDValue();
6444 EVT LD1VT = LD1->getValueType(0);
6446 if (ISD::isNON_EXTLoad(LD2) &&
6447 LD2->hasOneUse() &&
6448 // If both are volatile this would reduce the number of volatile loads.
6449 // If one is volatile it might be ok, but play conservative and bail out.
6450 !LD1->isVolatile() &&
6451 !LD2->isVolatile() &&
6452 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) {
6453 unsigned Align = LD1->getAlignment();
6454 unsigned NewAlign = TLI.getDataLayout()->
6455 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
6457 if (NewAlign <= Align &&
6458 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
6459 return DAG.getLoad(VT, SDLoc(N), LD1->getChain(),
6460 LD1->getBasePtr(), LD1->getPointerInfo(),
6461 false, false, false, Align);
6462 }
6464 return SDValue();
6465 }
6467 SDValue DAGCombiner::visitBITCAST(SDNode *N) {
6468 SDValue N0 = N->getOperand(0);
6469 EVT VT = N->getValueType(0);
6471 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
6472 // Only do this before legalize, since afterward the target may be depending
6473 // on the bitconvert.
6474 // First check to see if this is all constant.
6475 if (!LegalTypes &&
6476 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
6477 VT.isVector()) {
6478 bool isSimple = cast<BuildVectorSDNode>(N0)->isConstant();
6480 EVT DestEltVT = N->getValueType(0).getVectorElementType();
6481 assert(!DestEltVT.isVector() &&
6482 "Element type of vector ValueType must not be vector!");
6483 if (isSimple)
6484 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT);
6485 }
6487 // If the input is a constant, let getNode fold it.
6488 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
6489 SDValue Res = DAG.getNode(ISD::BITCAST, SDLoc(N), VT, N0);
6490 if (Res.getNode() != N) {
6491 if (!LegalOperations ||
6492 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT))
6493 return Res;
6495 // Folding it resulted in an illegal node, and it's too late to
6496 // do that. Clean up the old node and forego the transformation.
6497 // Ideally this won't happen very often, because instcombine
6498 // and the earlier dagcombine runs (where illegal nodes are
6499 // permitted) should have folded most of them already.
6500 deleteAndRecombine(Res.getNode());
6501 }
6502 }
6504 // (conv (conv x, t1), t2) -> (conv x, t2)
6505 if (N0.getOpcode() == ISD::BITCAST)
6506 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT,
6507 N0.getOperand(0));
6509 // fold (conv (load x)) -> (load (conv*)x)
6510 // If the resultant load doesn't need a higher alignment than the original!
6511 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
6512 // Do not change the width of a volatile load.
6513 !cast<LoadSDNode>(N0)->isVolatile() &&
6514 // Do not remove the cast if the types differ in endian layout.
6515 TLI.hasBigEndianPartOrdering(N0.getValueType()) ==
6516 TLI.hasBigEndianPartOrdering(VT) &&
6517 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)) &&
6518 TLI.isLoadBitCastBeneficial(N0.getValueType(), VT)) {
6519 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6520 unsigned Align = TLI.getDataLayout()->
6521 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
6522 unsigned OrigAlign = LN0->getAlignment();
6524 if (Align <= OrigAlign) {
6525 SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(),
6526 LN0->getBasePtr(), LN0->getPointerInfo(),
6527 LN0->isVolatile(), LN0->isNonTemporal(),
6528 LN0->isInvariant(), OrigAlign,
6529 LN0->getAAInfo());
6530 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1));
6531 return Load;
6532 }
6533 }
6535 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
6536 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
6537 // This often reduces constant pool loads.
6538 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(N0.getValueType())) ||
6539 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(N0.getValueType()))) &&
6540 N0.getNode()->hasOneUse() && VT.isInteger() &&
6541 !VT.isVector() && !N0.getValueType().isVector()) {
6542 SDValue NewConv = DAG.getNode(ISD::BITCAST, SDLoc(N0), VT,
6543 N0.getOperand(0));
6544 AddToWorklist(NewConv.getNode());
6546 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
6547 if (N0.getOpcode() == ISD::FNEG)
6548 return DAG.getNode(ISD::XOR, SDLoc(N), VT,
6549 NewConv, DAG.getConstant(SignBit, VT));
6550 assert(N0.getOpcode() == ISD::FABS);
6551 return DAG.getNode(ISD::AND, SDLoc(N), VT,
6552 NewConv, DAG.getConstant(~SignBit, VT));
6553 }
6555 // fold (bitconvert (fcopysign cst, x)) ->
6556 // (or (and (bitconvert x), sign), (and cst, (not sign)))
6557 // Note that we don't handle (copysign x, cst) because this can always be
6558 // folded to an fneg or fabs.
6559 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
6560 isa<ConstantFPSDNode>(N0.getOperand(0)) &&
6561 VT.isInteger() && !VT.isVector()) {
6562 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
6563 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth);
6564 if (isTypeLegal(IntXVT)) {
6565 SDValue X = DAG.getNode(ISD::BITCAST, SDLoc(N0),
6566 IntXVT, N0.getOperand(1));
6567 AddToWorklist(X.getNode());
6569 // If X has a different width than the result/lhs, sext it or truncate it.
6570 unsigned VTWidth = VT.getSizeInBits();
6571 if (OrigXWidth < VTWidth) {
6572 X = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, X);
6573 AddToWorklist(X.getNode());
6574 } else if (OrigXWidth > VTWidth) {
6575 // To get the sign bit in the right place, we have to shift it right
6576 // before truncating.
6577 X = DAG.getNode(ISD::SRL, SDLoc(X),
6578 X.getValueType(), X,
6579 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
6580 AddToWorklist(X.getNode());
6581 X = DAG.getNode(ISD::TRUNCATE, SDLoc(X), VT, X);
6582 AddToWorklist(X.getNode());
6583 }
6585 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
6586 X = DAG.getNode(ISD::AND, SDLoc(X), VT,
6587 X, DAG.getConstant(SignBit, VT));
6588 AddToWorklist(X.getNode());
6590 SDValue Cst = DAG.getNode(ISD::BITCAST, SDLoc(N0),
6591 VT, N0.getOperand(0));
6592 Cst = DAG.getNode(ISD::AND, SDLoc(Cst), VT,
6593 Cst, DAG.getConstant(~SignBit, VT));
6594 AddToWorklist(Cst.getNode());
6596 return DAG.getNode(ISD::OR, SDLoc(N), VT, X, Cst);
6597 }
6598 }
6600 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
6601 if (N0.getOpcode() == ISD::BUILD_PAIR) {
6602 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
6603 if (CombineLD.getNode())
6604 return CombineLD;
6605 }
6607 return SDValue();
6608 }
6610 SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
6611 EVT VT = N->getValueType(0);
6612 return CombineConsecutiveLoads(N, VT);
6613 }
6615 /// We know that BV is a build_vector node with Constant, ConstantFP or Undef
6616 /// operands. DstEltVT indicates the destination element value type.
6617 SDValue DAGCombiner::
6618 ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
6619 EVT SrcEltVT = BV->getValueType(0).getVectorElementType();
6621 // If this is already the right type, we're done.
6622 if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
6624 unsigned SrcBitSize = SrcEltVT.getSizeInBits();
6625 unsigned DstBitSize = DstEltVT.getSizeInBits();
6627 // If this is a conversion of N elements of one type to N elements of another
6628 // type, convert each element. This handles FP<->INT cases.
6629 if (SrcBitSize == DstBitSize) {
6630 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
6631 BV->getValueType(0).getVectorNumElements());
6633 // Due to the FP element handling below calling this routine recursively,
6634 // we can end up with a scalar-to-vector node here.
6635 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR)
6636 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(BV), VT,
6637 DAG.getNode(ISD::BITCAST, SDLoc(BV),
6638 DstEltVT, BV->getOperand(0)));
6640 SmallVector<SDValue, 8> Ops;
6641 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
6642 SDValue Op = BV->getOperand(i);
6643 // If the vector element type is not legal, the BUILD_VECTOR operands
6644 // are promoted and implicitly truncated. Make that explicit here.
6645 if (Op.getValueType() != SrcEltVT)
6646 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(BV), SrcEltVT, Op);
6647 Ops.push_back(DAG.getNode(ISD::BITCAST, SDLoc(BV),
6648 DstEltVT, Op));
6649 AddToWorklist(Ops.back().getNode());
6650 }
6651 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(BV), VT, Ops);
6652 }
6654 // Otherwise, we're growing or shrinking the elements. To avoid having to
6655 // handle annoying details of growing/shrinking FP values, we convert them to
6656 // int first.
6657 if (SrcEltVT.isFloatingPoint()) {
6658 // Convert the input float vector to a int vector where the elements are the
6659 // same sizes.
6660 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits());
6661 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode();
6662 SrcEltVT = IntVT;
6663 }
6665 // Now we know the input is an integer vector. If the output is a FP type,
6666 // convert to integer first, then to FP of the right size.
6667 if (DstEltVT.isFloatingPoint()) {
6668 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits());
6669 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode();
6671 // Next, convert to FP elements of the same size.
6672 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT);
6673 }
6675 // Okay, we know the src/dst types are both integers of differing types.
6676 // Handling growing first.
6677 assert(SrcEltVT.isInteger() && DstEltVT.isInteger());
6678 if (SrcBitSize < DstBitSize) {
6679 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
6681 SmallVector<SDValue, 8> Ops;
6682 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
6683 i += NumInputsPerOutput) {
6684 bool isLE = TLI.isLittleEndian();
6685 APInt NewBits = APInt(DstBitSize, 0);
6686 bool EltIsUndef = true;
6687 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
6688 // Shift the previously computed bits over.
6689 NewBits <<= SrcBitSize;
6690 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
6691 if (Op.getOpcode() == ISD::UNDEF) continue;
6692 EltIsUndef = false;
6694 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue().
6695 zextOrTrunc(SrcBitSize).zext(DstBitSize);
6696 }
6698 if (EltIsUndef)
6699 Ops.push_back(DAG.getUNDEF(DstEltVT));
6700 else
6701 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
6702 }
6704 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size());
6705 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(BV), VT, Ops);
6706 }
6708 // Finally, this must be the case where we are shrinking elements: each input
6709 // turns into multiple outputs.
6710 bool isS2V = ISD::isScalarToVector(BV);
6711 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
6712 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
6713 NumOutputsPerInput*BV->getNumOperands());
6714 SmallVector<SDValue, 8> Ops;
6716 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
6717 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
6718 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
6719 Ops.push_back(DAG.getUNDEF(DstEltVT));
6720 continue;
6721 }
6723 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->
6724 getAPIntValue().zextOrTrunc(SrcBitSize);
6726 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
6727 APInt ThisVal = OpVal.trunc(DstBitSize);
6728 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
6729 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal)
6730 // Simply turn this into a SCALAR_TO_VECTOR of the new type.
6731 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(BV), VT,
6732 Ops[0]);
6733 OpVal = OpVal.lshr(DstBitSize);
6734 }
6736 // For big endian targets, swap the order of the pieces of each element.
6737 if (TLI.isBigEndian())
6738 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
6739 }
6741 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(BV), VT, Ops);
6742 }
6744 SDValue DAGCombiner::visitFADD(SDNode *N) {
6745 SDValue N0 = N->getOperand(0);
6746 SDValue N1 = N->getOperand(1);
6747 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6748 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6749 EVT VT = N->getValueType(0);
6750 const TargetOptions &Options = DAG.getTarget().Options;
6752 // fold vector ops
6753 if (VT.isVector()) {
6754 SDValue FoldedVOp = SimplifyVBinOp(N);
6755 if (FoldedVOp.getNode()) return FoldedVOp;
6756 }
6758 // fold (fadd c1, c2) -> c1 + c2
6759 if (N0CFP && N1CFP)
6760 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0, N1);
6762 // canonicalize constant to RHS
6763 if (N0CFP && !N1CFP)
6764 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N1, N0);
6766 // fold (fadd A, (fneg B)) -> (fsub A, B)
6767 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
6768 isNegatibleForFree(N1, LegalOperations, TLI, &Options) == 2)
6769 return DAG.getNode(ISD::FSUB, SDLoc(N), VT, N0,
6770 GetNegatedExpression(N1, DAG, LegalOperations));
6772 // fold (fadd (fneg A), B) -> (fsub B, A)
6773 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
6774 isNegatibleForFree(N0, LegalOperations, TLI, &Options) == 2)
6775 return DAG.getNode(ISD::FSUB, SDLoc(N), VT, N1,
6776 GetNegatedExpression(N0, DAG, LegalOperations));
6778 // If 'unsafe math' is enabled, fold lots of things.
6779 if (Options.UnsafeFPMath) {
6780 // No FP constant should be created after legalization as Instruction
6781 // Selection pass has a hard time dealing with FP constants.
6782 bool AllowNewConst = (Level < AfterLegalizeDAG);
6784 // fold (fadd A, 0) -> A
6785 if (N1CFP && N1CFP->getValueAPF().isZero())
6786 return N0;
6788 // fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
6789 if (N1CFP && N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() &&
6790 isa<ConstantFPSDNode>(N0.getOperand(1)))
6791 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0.getOperand(0),
6792 DAG.getNode(ISD::FADD, SDLoc(N), VT,
6793 N0.getOperand(1), N1));
6795 // If allowed, fold (fadd (fneg x), x) -> 0.0
6796 if (AllowNewConst && N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1)
6797 return DAG.getConstantFP(0.0, VT);
6799 // If allowed, fold (fadd x, (fneg x)) -> 0.0
6800 if (AllowNewConst && N1.getOpcode() == ISD::FNEG && N1.getOperand(0) == N0)
6801 return DAG.getConstantFP(0.0, VT);
6803 // We can fold chains of FADD's of the same value into multiplications.
6804 // This transform is not safe in general because we are reducing the number
6805 // of rounding steps.
6806 if (TLI.isOperationLegalOrCustom(ISD::FMUL, VT) && !N0CFP && !N1CFP) {
6807 if (N0.getOpcode() == ISD::FMUL) {
6808 ConstantFPSDNode *CFP00 = dyn_cast<ConstantFPSDNode>(N0.getOperand(0));
6809 ConstantFPSDNode *CFP01 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1));
6811 // (fadd (fmul x, c), x) -> (fmul x, c+1)
6812 if (CFP01 && !CFP00 && N0.getOperand(0) == N1) {
6813 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
6814 SDValue(CFP01, 0),
6815 DAG.getConstantFP(1.0, VT));
6816 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N1, NewCFP);
6817 }
6819 // (fadd (fmul x, c), (fadd x, x)) -> (fmul x, c+2)
6820 if (CFP01 && !CFP00 && N1.getOpcode() == ISD::FADD &&
6821 N1.getOperand(0) == N1.getOperand(1) &&
6822 N0.getOperand(0) == N1.getOperand(0)) {
6823 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
6824 SDValue(CFP01, 0),
6825 DAG.getConstantFP(2.0, VT));
6826 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6827 N0.getOperand(0), NewCFP);
6828 }
6829 }
6831 if (N1.getOpcode() == ISD::FMUL) {
6832 ConstantFPSDNode *CFP10 = dyn_cast<ConstantFPSDNode>(N1.getOperand(0));
6833 ConstantFPSDNode *CFP11 = dyn_cast<ConstantFPSDNode>(N1.getOperand(1));
6835 // (fadd x, (fmul x, c)) -> (fmul x, c+1)
6836 if (CFP11 && !CFP10 && N1.getOperand(0) == N0) {
6837 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
6838 SDValue(CFP11, 0),
6839 DAG.getConstantFP(1.0, VT));
6840 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0, NewCFP);
6841 }
6843 // (fadd (fadd x, x), (fmul x, c)) -> (fmul x, c+2)
6844 if (CFP11 && !CFP10 && N0.getOpcode() == ISD::FADD &&
6845 N0.getOperand(0) == N0.getOperand(1) &&
6846 N1.getOperand(0) == N0.getOperand(0)) {
6847 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
6848 SDValue(CFP11, 0),
6849 DAG.getConstantFP(2.0, VT));
6850 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N1.getOperand(0), NewCFP);
6851 }
6852 }
6854 if (N0.getOpcode() == ISD::FADD && AllowNewConst) {
6855 ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N0.getOperand(0));
6856 // (fadd (fadd x, x), x) -> (fmul x, 3.0)
6857 if (!CFP && N0.getOperand(0) == N0.getOperand(1) &&
6858 (N0.getOperand(0) == N1))
6859 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6860 N1, DAG.getConstantFP(3.0, VT));
6861 }
6863 if (N1.getOpcode() == ISD::FADD && AllowNewConst) {
6864 ConstantFPSDNode *CFP10 = dyn_cast<ConstantFPSDNode>(N1.getOperand(0));
6865 // (fadd x, (fadd x, x)) -> (fmul x, 3.0)
6866 if (!CFP10 && N1.getOperand(0) == N1.getOperand(1) &&
6867 N1.getOperand(0) == N0)
6868 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6869 N0, DAG.getConstantFP(3.0, VT));
6870 }
6872 // (fadd (fadd x, x), (fadd x, x)) -> (fmul x, 4.0)
6873 if (AllowNewConst &&
6874 N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD &&
6875 N0.getOperand(0) == N0.getOperand(1) &&
6876 N1.getOperand(0) == N1.getOperand(1) &&
6877 N0.getOperand(0) == N1.getOperand(0))
6878 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6879 N0.getOperand(0), DAG.getConstantFP(4.0, VT));
6880 }
6881 } // enable-unsafe-fp-math
6883 // FADD -> FMA combines:
6884 if ((Options.AllowFPOpFusion == FPOpFusion::Fast || Options.UnsafeFPMath) &&
6885 TLI.isFMAFasterThanFMulAndFAdd(VT) &&
6886 (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FMA, VT))) {
6888 // fold (fadd (fmul x, y), z) -> (fma x, y, z)
6889 if (N0.getOpcode() == ISD::FMUL &&
6890 (N0->hasOneUse() || TLI.enableAggressiveFMAFusion(VT)))
6891 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
6892 N0.getOperand(0), N0.getOperand(1), N1);
6894 // fold (fadd x, (fmul y, z)) -> (fma y, z, x)
6895 // Note: Commutes FADD operands.
6896 if (N1.getOpcode() == ISD::FMUL &&
6897 (N1->hasOneUse() || TLI.enableAggressiveFMAFusion(VT)))
6898 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
6899 N1.getOperand(0), N1.getOperand(1), N0);
6901 // More folding opportunities when target permits.
6902 if (TLI.enableAggressiveFMAFusion(VT)) {
6903 // fold (fadd (fma x, y, (fmul u, v)), z) -> (fma x, y (fma u, v, z))
6904 if (N0.getOpcode() == ISD::FMA &&
6905 N0.getOperand(2).getOpcode() == ISD::FMUL)
6906 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
6907 N0.getOperand(0), N0.getOperand(1),
6908 DAG.getNode(ISD::FMA, SDLoc(N), VT,
6909 N0.getOperand(2).getOperand(0),
6910 N0.getOperand(2).getOperand(1),
6911 N1));
6913 // fold (fadd x, (fma y, z, (fmul u, v)) -> (fma y, z (fma u, v, x))
6914 if (N1->getOpcode() == ISD::FMA &&
6915 N1.getOperand(2).getOpcode() == ISD::FMUL)
6916 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
6917 N1.getOperand(0), N1.getOperand(1),
6918 DAG.getNode(ISD::FMA, SDLoc(N), VT,
6919 N1.getOperand(2).getOperand(0),
6920 N1.getOperand(2).getOperand(1),
6921 N0));
6923 // Remove FP_EXTEND when there is an opportunity to combine. This is
6924 // legal here since extra precision is allowed.
6926 // fold (fadd (fpext (fmul x, y)), z) -> (fma x, y, z)
6927 if (N0.getOpcode() == ISD::FP_EXTEND) {
6928 SDValue N00 = N0.getOperand(0);
6929 if (N00.getOpcode() == ISD::FMUL)
6930 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
6931 DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT,
6932 N00.getOperand(0)),
6933 DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT,
6934 N00.getOperand(1)), N1);
6935 }
6937 // fold (fadd x, (fpext (fmul y, z)), z) -> (fma y, z, x)
6938 // Note: Commutes FADD operands.
6939 if (N1.getOpcode() == ISD::FP_EXTEND) {
6940 SDValue N10 = N1.getOperand(0);
6941 if (N10.getOpcode() == ISD::FMUL)
6942 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
6943 DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT,
6944 N10.getOperand(0)),
6945 DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT,
6946 N10.getOperand(1)), N0);
6947 }
6948 }
6949 }
6951 return SDValue();
6952 }
6954 SDValue DAGCombiner::visitFSUB(SDNode *N) {
6955 SDValue N0 = N->getOperand(0);
6956 SDValue N1 = N->getOperand(1);
6957 ConstantFPSDNode *N0CFP = isConstOrConstSplatFP(N0);
6958 ConstantFPSDNode *N1CFP = isConstOrConstSplatFP(N1);
6959 EVT VT = N->getValueType(0);
6960 SDLoc dl(N);
6961 const TargetOptions &Options = DAG.getTarget().Options;
6963 // fold vector ops
6964 if (VT.isVector()) {
6965 SDValue FoldedVOp = SimplifyVBinOp(N);
6966 if (FoldedVOp.getNode()) return FoldedVOp;
6967 }
6969 // fold (fsub c1, c2) -> c1-c2
6970 if (N0CFP && N1CFP)
6971 return DAG.getNode(ISD::FSUB, SDLoc(N), VT, N0, N1);
6973 // fold (fsub A, (fneg B)) -> (fadd A, B)
6974 if (isNegatibleForFree(N1, LegalOperations, TLI, &Options))
6975 return DAG.getNode(ISD::FADD, dl, VT, N0,
6976 GetNegatedExpression(N1, DAG, LegalOperations));
6978 // If 'unsafe math' is enabled, fold lots of things.
6979 if (Options.UnsafeFPMath) {
6980 // (fsub A, 0) -> A
6981 if (N1CFP && N1CFP->getValueAPF().isZero())
6982 return N0;
6984 // (fsub 0, B) -> -B
6985 if (N0CFP && N0CFP->getValueAPF().isZero()) {
6986 if (isNegatibleForFree(N1, LegalOperations, TLI, &Options))
6987 return GetNegatedExpression(N1, DAG, LegalOperations);
6988 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
6989 return DAG.getNode(ISD::FNEG, dl, VT, N1);
6990 }
6992 // (fsub x, x) -> 0.0
6993 if (N0 == N1)
6994 return DAG.getConstantFP(0.0f, VT);
6996 // (fsub x, (fadd x, y)) -> (fneg y)
6997 // (fsub x, (fadd y, x)) -> (fneg y)
6998 if (N1.getOpcode() == ISD::FADD) {
6999 SDValue N10 = N1->getOperand(0);
7000 SDValue N11 = N1->getOperand(1);
7002 if (N10 == N0 && isNegatibleForFree(N11, LegalOperations, TLI, &Options))
7003 return GetNegatedExpression(N11, DAG, LegalOperations);
7005 if (N11 == N0 && isNegatibleForFree(N10, LegalOperations, TLI, &Options))
7006 return GetNegatedExpression(N10, DAG, LegalOperations);
7007 }
7008 }
7010 // FSUB -> FMA combines:
7011 if ((Options.AllowFPOpFusion == FPOpFusion::Fast || Options.UnsafeFPMath) &&
7012 TLI.isFMAFasterThanFMulAndFAdd(VT) &&
7013 (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FMA, VT))) {
7015 // fold (fsub (fmul x, y), z) -> (fma x, y, (fneg z))
7016 if (N0.getOpcode() == ISD::FMUL &&
7017 (N0->hasOneUse() || TLI.enableAggressiveFMAFusion(VT)))
7018 return DAG.getNode(ISD::FMA, dl, VT,
7019 N0.getOperand(0), N0.getOperand(1),
7020 DAG.getNode(ISD::FNEG, dl, VT, N1));
7022 // fold (fsub x, (fmul y, z)) -> (fma (fneg y), z, x)
7023 // Note: Commutes FSUB operands.
7024 if (N1.getOpcode() == ISD::FMUL &&
7025 (N1->hasOneUse() || TLI.enableAggressiveFMAFusion(VT)))
7026 return DAG.getNode(ISD::FMA, dl, VT,
7027 DAG.getNode(ISD::FNEG, dl, VT,
7028 N1.getOperand(0)),
7029 N1.getOperand(1), N0);
7031 // fold (fsub (fneg (fmul, x, y)), z) -> (fma (fneg x), y, (fneg z))
7032 if (N0.getOpcode() == ISD::FNEG &&
7033 N0.getOperand(0).getOpcode() == ISD::FMUL &&
7034 ((N0->hasOneUse() && N0.getOperand(0).hasOneUse()) ||
7035 TLI.enableAggressiveFMAFusion(VT))) {
7036 SDValue N00 = N0.getOperand(0).getOperand(0);
7037 SDValue N01 = N0.getOperand(0).getOperand(1);
7038 return DAG.getNode(ISD::FMA, dl, VT,
7039 DAG.getNode(ISD::FNEG, dl, VT, N00), N01,
7040 DAG.getNode(ISD::FNEG, dl, VT, N1));
7041 }
7043 // More folding opportunities when target permits.
7044 if (TLI.enableAggressiveFMAFusion(VT)) {
7046 // fold (fsub (fma x, y, (fmul u, v)), z)
7047 // -> (fma x, y (fma u, v, (fneg z)))
7048 if (N0.getOpcode() == ISD::FMA &&
7049 N0.getOperand(2).getOpcode() == ISD::FMUL)
7050 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
7051 N0.getOperand(0), N0.getOperand(1),
7052 DAG.getNode(ISD::FMA, SDLoc(N), VT,
7053 N0.getOperand(2).getOperand(0),
7054 N0.getOperand(2).getOperand(1),
7055 DAG.getNode(ISD::FNEG, SDLoc(N), VT,
7056 N1)));
7058 // fold (fsub x, (fma y, z, (fmul u, v)))
7059 // -> (fma (fneg y), z, (fma (fneg u), v, x))
7060 if (N1.getOpcode() == ISD::FMA &&
7061 N1.getOperand(2).getOpcode() == ISD::FMUL) {
7062 SDValue N20 = N1.getOperand(2).getOperand(0);
7063 SDValue N21 = N1.getOperand(2).getOperand(1);
7064 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
7065 DAG.getNode(ISD::FNEG, SDLoc(N), VT,
7066 N1.getOperand(0)),
7067 N1.getOperand(1),
7068 DAG.getNode(ISD::FMA, SDLoc(N), VT,
7069 DAG.getNode(ISD::FNEG, SDLoc(N), VT,
7070 N20),
7071 N21, N0));
7072 }
7074 // Remove FP_EXTEND when there is an opportunity to combine. This is
7075 // legal here since extra precision is allowed.
7077 // fold (fsub (fpext (fmul x, y)), z) -> (fma x, y, (fneg z))
7078 if (N0.getOpcode() == ISD::FP_EXTEND) {
7079 SDValue N00 = N0.getOperand(0);
7080 if (N00.getOpcode() == ISD::FMUL)
7081 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
7082 DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT,
7083 N00.getOperand(0)),
7084 DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT,
7085 N00.getOperand(1)),
7086 DAG.getNode(ISD::FNEG, SDLoc(N), VT, N1));
7087 }
7089 // fold (fsub x, (fpext (fmul y, z))) -> (fma (fneg y), z, x)
7090 // Note: Commutes FSUB operands.
7091 if (N1.getOpcode() == ISD::FP_EXTEND) {
7092 SDValue N10 = N1.getOperand(0);
7093 if (N10.getOpcode() == ISD::FMUL)
7094 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
7095 DAG.getNode(ISD::FNEG, SDLoc(N), VT,
7096 DAG.getNode(ISD::FP_EXTEND, SDLoc(N),
7097 VT, N10.getOperand(0))),
7098 DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT,
7099 N10.getOperand(1)),
7100 N0);
7101 }
7103 // fold (fsub (fpext (fneg (fmul, x, y))), z)
7104 // -> (fma (fneg x), y, (fneg z))
7105 if (N0.getOpcode() == ISD::FP_EXTEND) {
7106 SDValue N00 = N0.getOperand(0);
7107 if (N00.getOpcode() == ISD::FNEG) {
7108 SDValue N000 = N00.getOperand(0);
7109 if (N000.getOpcode() == ISD::FMUL) {
7110 return DAG.getNode(ISD::FMA, dl, VT,
7111 DAG.getNode(ISD::FNEG, dl, VT,
7112 DAG.getNode(ISD::FP_EXTEND, SDLoc(N),
7113 VT, N000.getOperand(0))),
7114 DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT,
7115 N000.getOperand(1)),
7116 DAG.getNode(ISD::FNEG, dl, VT, N1));
7117 }
7118 }
7119 }
7121 // fold (fsub (fneg (fpext (fmul, x, y))), z)
7122 // -> (fma (fneg x), y, (fneg z))
7123 if (N0.getOpcode() == ISD::FNEG) {
7124 SDValue N00 = N0.getOperand(0);
7125 if (N00.getOpcode() == ISD::FP_EXTEND) {
7126 SDValue N000 = N00.getOperand(0);
7127 if (N000.getOpcode() == ISD::FMUL) {
7128 return DAG.getNode(ISD::FMA, dl, VT,
7129 DAG.getNode(ISD::FNEG, dl, VT,
7130 DAG.getNode(ISD::FP_EXTEND, SDLoc(N),
7131 VT, N000.getOperand(0))),
7132 DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT,
7133 N000.getOperand(1)),
7134 DAG.getNode(ISD::FNEG, dl, VT, N1));
7135 }
7136 }
7137 }
7138 }
7139 }
7141 return SDValue();
7142 }
7144 SDValue DAGCombiner::visitFMUL(SDNode *N) {
7145 SDValue N0 = N->getOperand(0);
7146 SDValue N1 = N->getOperand(1);
7147 ConstantFPSDNode *N0CFP = isConstOrConstSplatFP(N0);
7148 ConstantFPSDNode *N1CFP = isConstOrConstSplatFP(N1);
7149 EVT VT = N->getValueType(0);
7150 const TargetOptions &Options = DAG.getTarget().Options;
7152 // fold vector ops
7153 if (VT.isVector()) {
7154 // This just handles C1 * C2 for vectors. Other vector folds are below.
7155 SDValue FoldedVOp = SimplifyVBinOp(N);
7156 if (FoldedVOp.getNode())
7157 return FoldedVOp;
7158 // Canonicalize vector constant to RHS.
7159 if (N0.getOpcode() == ISD::BUILD_VECTOR &&
7160 N1.getOpcode() != ISD::BUILD_VECTOR)
7161 if (auto *BV0 = dyn_cast<BuildVectorSDNode>(N0))
7162 if (BV0->isConstant())
7163 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0);
7164 }
7166 // fold (fmul c1, c2) -> c1*c2
7167 if (N0CFP && N1CFP)
7168 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0, N1);
7170 // canonicalize constant to RHS
7171 if (N0CFP && !N1CFP)
7172 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N1, N0);
7174 // fold (fmul A, 1.0) -> A
7175 if (N1CFP && N1CFP->isExactlyValue(1.0))
7176 return N0;
7178 if (Options.UnsafeFPMath) {
7179 // fold (fmul A, 0) -> 0
7180 if (N1CFP && N1CFP->getValueAPF().isZero())
7181 return N1;
7183 // fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
7184 if (N0.getOpcode() == ISD::FMUL) {
7185 // Fold scalars or any vector constants (not just splats).
7186 // This fold is done in general by InstCombine, but extra fmul insts
7187 // may have been generated during lowering.
7188 SDValue N01 = N0.getOperand(1);
7189 auto *BV1 = dyn_cast<BuildVectorSDNode>(N1);
7190 auto *BV01 = dyn_cast<BuildVectorSDNode>(N01);
7191 if ((N1CFP && isConstOrConstSplatFP(N01)) ||
7192 (BV1 && BV01 && BV1->isConstant() && BV01->isConstant())) {
7193 SDLoc SL(N);
7194 SDValue MulConsts = DAG.getNode(ISD::FMUL, SL, VT, N01, N1);
7195 return DAG.getNode(ISD::FMUL, SL, VT, N0.getOperand(0), MulConsts);
7196 }
7197 }
7199 // fold (fmul (fadd x, x), c) -> (fmul x, (fmul 2.0, c))
7200 // Undo the fmul 2.0, x -> fadd x, x transformation, since if it occurs
7201 // during an early run of DAGCombiner can prevent folding with fmuls
7202 // inserted during lowering.
7203 if (N0.getOpcode() == ISD::FADD && N0.getOperand(0) == N0.getOperand(1)) {
7204 SDLoc SL(N);
7205 const SDValue Two = DAG.getConstantFP(2.0, VT);
7206 SDValue MulConsts = DAG.getNode(ISD::FMUL, SL, VT, Two, N1);
7207 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0.getOperand(0), MulConsts);
7208 }
7209 }
7211 // fold (fmul X, 2.0) -> (fadd X, X)
7212 if (N1CFP && N1CFP->isExactlyValue(+2.0))
7213 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0, N0);
7215 // fold (fmul X, -1.0) -> (fneg X)
7216 if (N1CFP && N1CFP->isExactlyValue(-1.0))
7217 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
7218 return DAG.getNode(ISD::FNEG, SDLoc(N), VT, N0);
7220 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y)
7221 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, &Options)) {
7222 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, &Options)) {
7223 // Both can be negated for free, check to see if at least one is cheaper
7224 // negated.
7225 if (LHSNeg == 2 || RHSNeg == 2)
7226 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
7227 GetNegatedExpression(N0, DAG, LegalOperations),
7228 GetNegatedExpression(N1, DAG, LegalOperations));
7229 }
7230 }
7232 return SDValue();
7233 }
7235 SDValue DAGCombiner::visitFMA(SDNode *N) {
7236 SDValue N0 = N->getOperand(0);
7237 SDValue N1 = N->getOperand(1);
7238 SDValue N2 = N->getOperand(2);
7239 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7240 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
7241 EVT VT = N->getValueType(0);
7242 SDLoc dl(N);
7243 const TargetOptions &Options = DAG.getTarget().Options;
7245 // Constant fold FMA.
7246 if (isa<ConstantFPSDNode>(N0) &&
7247 isa<ConstantFPSDNode>(N1) &&
7248 isa<ConstantFPSDNode>(N2)) {
7249 return DAG.getNode(ISD::FMA, dl, VT, N0, N1, N2);
7250 }
7252 if (Options.UnsafeFPMath) {
7253 if (N0CFP && N0CFP->isZero())
7254 return N2;
7255 if (N1CFP && N1CFP->isZero())
7256 return N2;
7257 }
7258 if (N0CFP && N0CFP->isExactlyValue(1.0))
7259 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N1, N2);
7260 if (N1CFP && N1CFP->isExactlyValue(1.0))
7261 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0, N2);
7263 // Canonicalize (fma c, x, y) -> (fma x, c, y)
7264 if (N0CFP && !N1CFP)
7265 return DAG.getNode(ISD::FMA, SDLoc(N), VT, N1, N0, N2);
7267 // (fma x, c1, (fmul x, c2)) -> (fmul x, c1+c2)
7268 if (Options.UnsafeFPMath && N1CFP &&
7269 N2.getOpcode() == ISD::FMUL &&
7270 N0 == N2.getOperand(0) &&
7271 N2.getOperand(1).getOpcode() == ISD::ConstantFP) {
7272 return DAG.getNode(ISD::FMUL, dl, VT, N0,
7273 DAG.getNode(ISD::FADD, dl, VT, N1, N2.getOperand(1)));
7274 }
7277 // (fma (fmul x, c1), c2, y) -> (fma x, c1*c2, y)
7278 if (Options.UnsafeFPMath &&
7279 N0.getOpcode() == ISD::FMUL && N1CFP &&
7280 N0.getOperand(1).getOpcode() == ISD::ConstantFP) {
7281 return DAG.getNode(ISD::FMA, dl, VT,
7282 N0.getOperand(0),
7283 DAG.getNode(ISD::FMUL, dl, VT, N1, N0.getOperand(1)),
7284 N2);
7285 }
7287 // (fma x, 1, y) -> (fadd x, y)
7288 // (fma x, -1, y) -> (fadd (fneg x), y)
7289 if (N1CFP) {
7290 if (N1CFP->isExactlyValue(1.0))
7291 return DAG.getNode(ISD::FADD, dl, VT, N0, N2);
7293 if (N1CFP->isExactlyValue(-1.0) &&
7294 (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))) {
7295 SDValue RHSNeg = DAG.getNode(ISD::FNEG, dl, VT, N0);
7296 AddToWorklist(RHSNeg.getNode());
7297 return DAG.getNode(ISD::FADD, dl, VT, N2, RHSNeg);
7298 }
7299 }
7301 // (fma x, c, x) -> (fmul x, (c+1))
7302 if (Options.UnsafeFPMath && N1CFP && N0 == N2)
7303 return DAG.getNode(ISD::FMUL, dl, VT, N0,
7304 DAG.getNode(ISD::FADD, dl, VT,
7305 N1, DAG.getConstantFP(1.0, VT)));
7307 // (fma x, c, (fneg x)) -> (fmul x, (c-1))
7308 if (Options.UnsafeFPMath && N1CFP &&
7309 N2.getOpcode() == ISD::FNEG && N2.getOperand(0) == N0)
7310 return DAG.getNode(ISD::FMUL, dl, VT, N0,
7311 DAG.getNode(ISD::FADD, dl, VT,
7312 N1, DAG.getConstantFP(-1.0, VT)));
7315 return SDValue();
7316 }
7318 SDValue DAGCombiner::visitFDIV(SDNode *N) {
7319 SDValue N0 = N->getOperand(0);
7320 SDValue N1 = N->getOperand(1);
7321 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7322 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
7323 EVT VT = N->getValueType(0);
7324 SDLoc DL(N);
7325 const TargetOptions &Options = DAG.getTarget().Options;
7327 // fold vector ops
7328 if (VT.isVector()) {
7329 SDValue FoldedVOp = SimplifyVBinOp(N);
7330 if (FoldedVOp.getNode()) return FoldedVOp;
7331 }
7333 // fold (fdiv c1, c2) -> c1/c2
7334 if (N0CFP && N1CFP)
7335 return DAG.getNode(ISD::FDIV, SDLoc(N), VT, N0, N1);
7337 if (Options.UnsafeFPMath) {
7338 // fold (fdiv X, c2) -> fmul X, 1/c2 if losing precision is acceptable.
7339 if (N1CFP) {
7340 // Compute the reciprocal 1.0 / c2.
7341 APFloat N1APF = N1CFP->getValueAPF();
7342 APFloat Recip(N1APF.getSemantics(), 1); // 1.0
7343 APFloat::opStatus st = Recip.divide(N1APF, APFloat::rmNearestTiesToEven);
7344 // Only do the transform if the reciprocal is a legal fp immediate that
7345 // isn't too nasty (eg NaN, denormal, ...).
7346 if ((st == APFloat::opOK || st == APFloat::opInexact) && // Not too nasty
7347 (!LegalOperations ||
7348 // FIXME: custom lowering of ConstantFP might fail (see e.g. ARM
7349 // backend)... we should handle this gracefully after Legalize.
7350 // TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT) ||
7351 TLI.isOperationLegal(llvm::ISD::ConstantFP, VT) ||
7352 TLI.isFPImmLegal(Recip, VT)))
7353 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0,
7354 DAG.getConstantFP(Recip, VT));
7355 }
7357 // If this FDIV is part of a reciprocal square root, it may be folded
7358 // into a target-specific square root estimate instruction.
7359 if (N1.getOpcode() == ISD::FSQRT) {
7360 if (SDValue RV = BuildRsqrtEstimate(N1.getOperand(0))) {
7361 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV);
7362 }
7363 } else if (N1.getOpcode() == ISD::FP_EXTEND &&
7364 N1.getOperand(0).getOpcode() == ISD::FSQRT) {
7365 if (SDValue RV = BuildRsqrtEstimate(N1.getOperand(0).getOperand(0))) {
7366 RV = DAG.getNode(ISD::FP_EXTEND, SDLoc(N1), VT, RV);
7367 AddToWorklist(RV.getNode());
7368 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV);
7369 }
7370 } else if (N1.getOpcode() == ISD::FP_ROUND &&
7371 N1.getOperand(0).getOpcode() == ISD::FSQRT) {
7372 if (SDValue RV = BuildRsqrtEstimate(N1.getOperand(0).getOperand(0))) {
7373 RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N1), VT, RV, N1.getOperand(1));
7374 AddToWorklist(RV.getNode());
7375 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV);
7376 }
7377 } else if (N1.getOpcode() == ISD::FMUL) {
7378 // Look through an FMUL. Even though this won't remove the FDIV directly,
7379 // it's still worthwhile to get rid of the FSQRT if possible.
7380 SDValue SqrtOp;
7381 SDValue OtherOp;
7382 if (N1.getOperand(0).getOpcode() == ISD::FSQRT) {
7383 SqrtOp = N1.getOperand(0);
7384 OtherOp = N1.getOperand(1);
7385 } else if (N1.getOperand(1).getOpcode() == ISD::FSQRT) {
7386 SqrtOp = N1.getOperand(1);
7387 OtherOp = N1.getOperand(0);
7388 }
7389 if (SqrtOp.getNode()) {
7390 // We found a FSQRT, so try to make this fold:
7391 // x / (y * sqrt(z)) -> x * (rsqrt(z) / y)
7392 if (SDValue RV = BuildRsqrtEstimate(SqrtOp.getOperand(0))) {
7393 RV = DAG.getNode(ISD::FDIV, SDLoc(N1), VT, RV, OtherOp);
7394 AddToWorklist(RV.getNode());
7395 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV);
7396 }
7397 }
7398 }
7400 // Fold into a reciprocal estimate and multiply instead of a real divide.
7401 if (SDValue RV = BuildReciprocalEstimate(N1)) {
7402 AddToWorklist(RV.getNode());
7403 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV);
7404 }
7405 }
7407 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y)
7408 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, &Options)) {
7409 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, &Options)) {
7410 // Both can be negated for free, check to see if at least one is cheaper
7411 // negated.
7412 if (LHSNeg == 2 || RHSNeg == 2)
7413 return DAG.getNode(ISD::FDIV, SDLoc(N), VT,
7414 GetNegatedExpression(N0, DAG, LegalOperations),
7415 GetNegatedExpression(N1, DAG, LegalOperations));
7416 }
7417 }
7419 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
7420 // reciprocal.
7421 // E.g., (a / D; b / D;) -> (recip = 1.0 / D; a * recip; b * recip)
7422 // Notice that this is not always beneficial. One reason is different target
7423 // may have different costs for FDIV and FMUL, so sometimes the cost of two
7424 // FDIVs may be lower than the cost of one FDIV and two FMULs. Another reason
7425 // is the critical path is increased from "one FDIV" to "one FDIV + one FMUL".
7426 if (Options.UnsafeFPMath) {
7427 // Skip if current node is a reciprocal.
7428 if (N0CFP && N0CFP->isExactlyValue(1.0))
7429 return SDValue();
7431 SmallVector<SDNode *, 4> Users;
7432 // Find all FDIV users of the same divisor.
7433 for (SDNode::use_iterator UI = N1.getNode()->use_begin(),
7434 UE = N1.getNode()->use_end();
7435 UI != UE; ++UI) {
7436 SDNode *User = UI.getUse().getUser();
7437 if (User->getOpcode() == ISD::FDIV && User->getOperand(1) == N1)
7438 Users.push_back(User);
7439 }
7441 if (TLI.combineRepeatedFPDivisors(Users.size())) {
7442 SDValue FPOne = DAG.getConstantFP(1.0, VT); // floating point 1.0
7443 SDValue Reciprocal = DAG.getNode(ISD::FDIV, SDLoc(N), VT, FPOne, N1);
7445 // Dividend / Divisor -> Dividend * Reciprocal
7446 for (auto I = Users.begin(), E = Users.end(); I != E; ++I) {
7447 if ((*I)->getOperand(0) != FPOne) {
7448 SDValue NewNode = DAG.getNode(ISD::FMUL, SDLoc(*I), VT,
7449 (*I)->getOperand(0), Reciprocal);
7450 DAG.ReplaceAllUsesWith(*I, NewNode.getNode());
7451 }
7452 }
7453 return SDValue();
7454 }
7455 }
7457 return SDValue();
7458 }
7460 SDValue DAGCombiner::visitFREM(SDNode *N) {
7461 SDValue N0 = N->getOperand(0);
7462 SDValue N1 = N->getOperand(1);
7463 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7464 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
7465 EVT VT = N->getValueType(0);
7467 // fold (frem c1, c2) -> fmod(c1,c2)
7468 if (N0CFP && N1CFP)
7469 return DAG.getNode(ISD::FREM, SDLoc(N), VT, N0, N1);
7471 return SDValue();
7472 }
7474 SDValue DAGCombiner::visitFSQRT(SDNode *N) {
7475 if (DAG.getTarget().Options.UnsafeFPMath) {
7476 // Compute this as X * (1/sqrt(X)) = X * (X ** -0.5)
7477 if (SDValue RV = BuildRsqrtEstimate(N->getOperand(0))) {
7478 EVT VT = RV.getValueType();
7479 RV = DAG.getNode(ISD::FMUL, SDLoc(N), VT, N->getOperand(0), RV);
7480 AddToWorklist(RV.getNode());
7482 // Unfortunately, RV is now NaN if the input was exactly 0.
7483 // Select out this case and force the answer to 0.
7484 SDValue Zero = DAG.getConstantFP(0.0, VT);
7485 SDValue ZeroCmp =
7486 DAG.getSetCC(SDLoc(N), TLI.getSetCCResultType(*DAG.getContext(), VT),
7487 N->getOperand(0), Zero, ISD::SETEQ);
7488 AddToWorklist(ZeroCmp.getNode());
7489 AddToWorklist(RV.getNode());
7491 RV = DAG.getNode(VT.isVector() ? ISD::VSELECT : ISD::SELECT,
7492 SDLoc(N), VT, ZeroCmp, Zero, RV);
7493 return RV;
7494 }
7495 }
7496 return SDValue();
7497 }
7499 SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
7500 SDValue N0 = N->getOperand(0);
7501 SDValue N1 = N->getOperand(1);
7502 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7503 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
7504 EVT VT = N->getValueType(0);
7506 if (N0CFP && N1CFP) // Constant fold
7507 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, N0, N1);
7509 if (N1CFP) {
7510 const APFloat& V = N1CFP->getValueAPF();
7511 // copysign(x, c1) -> fabs(x) iff ispos(c1)
7512 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
7513 if (!V.isNegative()) {
7514 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT))
7515 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0);
7516 } else {
7517 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
7518 return DAG.getNode(ISD::FNEG, SDLoc(N), VT,
7519 DAG.getNode(ISD::FABS, SDLoc(N0), VT, N0));
7520 }
7521 }
7523 // copysign(fabs(x), y) -> copysign(x, y)
7524 // copysign(fneg(x), y) -> copysign(x, y)
7525 // copysign(copysign(x,z), y) -> copysign(x, y)
7526 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
7527 N0.getOpcode() == ISD::FCOPYSIGN)
7528 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT,
7529 N0.getOperand(0), N1);
7531 // copysign(x, abs(y)) -> abs(x)
7532 if (N1.getOpcode() == ISD::FABS)
7533 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0);
7535 // copysign(x, copysign(y,z)) -> copysign(x, z)
7536 if (N1.getOpcode() == ISD::FCOPYSIGN)
7537 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT,
7538 N0, N1.getOperand(1));
7540 // copysign(x, fp_extend(y)) -> copysign(x, y)
7541 // copysign(x, fp_round(y)) -> copysign(x, y)
7542 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
7543 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT,
7544 N0, N1.getOperand(0));
7546 return SDValue();
7547 }
7549 SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
7550 SDValue N0 = N->getOperand(0);
7551 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
7552 EVT VT = N->getValueType(0);
7553 EVT OpVT = N0.getValueType();
7555 // fold (sint_to_fp c1) -> c1fp
7556 if (N0C &&
7557 // ...but only if the target supports immediate floating-point values
7558 (!LegalOperations ||
7559 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
7560 return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0);
7562 // If the input is a legal type, and SINT_TO_FP is not legal on this target,
7563 // but UINT_TO_FP is legal on this target, try to convert.
7564 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
7565 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
7566 // If the sign bit is known to be zero, we can change this to UINT_TO_FP.
7567 if (DAG.SignBitIsZero(N0))
7568 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), VT, N0);
7569 }
7571 // The next optimizations are desirable only if SELECT_CC can be lowered.
7572 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT) || !LegalOperations) {
7573 // fold (sint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc)
7574 if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 &&
7575 !VT.isVector() &&
7576 (!LegalOperations ||
7577 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
7578 SDValue Ops[] =
7579 { N0.getOperand(0), N0.getOperand(1),
7580 DAG.getConstantFP(-1.0, VT) , DAG.getConstantFP(0.0, VT),
7581 N0.getOperand(2) };
7582 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT, Ops);
7583 }
7585 // fold (sint_to_fp (zext (setcc x, y, cc))) ->
7586 // (select_cc x, y, 1.0, 0.0,, cc)
7587 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
7588 N0.getOperand(0).getOpcode() == ISD::SETCC &&!VT.isVector() &&
7589 (!LegalOperations ||
7590 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
7591 SDValue Ops[] =
7592 { N0.getOperand(0).getOperand(0), N0.getOperand(0).getOperand(1),
7593 DAG.getConstantFP(1.0, VT) , DAG.getConstantFP(0.0, VT),
7594 N0.getOperand(0).getOperand(2) };
7595 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT, Ops);
7596 }
7597 }
7599 return SDValue();
7600 }
7602 SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
7603 SDValue N0 = N->getOperand(0);
7604 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
7605 EVT VT = N->getValueType(0);
7606 EVT OpVT = N0.getValueType();
7608 // fold (uint_to_fp c1) -> c1fp
7609 if (N0C &&
7610 // ...but only if the target supports immediate floating-point values
7611 (!LegalOperations ||
7612 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
7613 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), VT, N0);
7615 // If the input is a legal type, and UINT_TO_FP is not legal on this target,
7616 // but SINT_TO_FP is legal on this target, try to convert.
7617 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
7618 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
7619 // If the sign bit is known to be zero, we can change this to SINT_TO_FP.
7620 if (DAG.SignBitIsZero(N0))
7621 return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0);
7622 }
7624 // The next optimizations are desirable only if SELECT_CC can be lowered.
7625 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT) || !LegalOperations) {
7626 // fold (uint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc)
7628 if (N0.getOpcode() == ISD::SETCC && !VT.isVector() &&
7629 (!LegalOperations ||
7630 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
7631 SDValue Ops[] =
7632 { N0.getOperand(0), N0.getOperand(1),
7633 DAG.getConstantFP(1.0, VT), DAG.getConstantFP(0.0, VT),
7634 N0.getOperand(2) };
7635 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT, Ops);
7636 }
7637 }
7639 return SDValue();
7640 }
7642 SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) {
7643 SDValue N0 = N->getOperand(0);
7644 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7645 EVT VT = N->getValueType(0);
7647 // fold (fp_to_sint c1fp) -> c1
7648 if (N0CFP)
7649 return DAG.getNode(ISD::FP_TO_SINT, SDLoc(N), VT, N0);
7651 return SDValue();
7652 }
7654 SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
7655 SDValue N0 = N->getOperand(0);
7656 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7657 EVT VT = N->getValueType(0);
7659 // fold (fp_to_uint c1fp) -> c1
7660 if (N0CFP)
7661 return DAG.getNode(ISD::FP_TO_UINT, SDLoc(N), VT, N0);
7663 return SDValue();
7664 }
7666 SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
7667 SDValue N0 = N->getOperand(0);
7668 SDValue N1 = N->getOperand(1);
7669 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7670 EVT VT = N->getValueType(0);
7672 // fold (fp_round c1fp) -> c1fp
7673 if (N0CFP)
7674 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT, N0, N1);
7676 // fold (fp_round (fp_extend x)) -> x
7677 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
7678 return N0.getOperand(0);
7680 // fold (fp_round (fp_round x)) -> (fp_round x)
7681 if (N0.getOpcode() == ISD::FP_ROUND) {
7682 // This is a value preserving truncation if both round's are.
7683 bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
7684 N0.getNode()->getConstantOperandVal(1) == 1;
7685 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT, N0.getOperand(0),
7686 DAG.getIntPtrConstant(IsTrunc));
7687 }
7689 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
7690 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
7691 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, SDLoc(N0), VT,
7692 N0.getOperand(0), N1);
7693 AddToWorklist(Tmp.getNode());
7694 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT,
7695 Tmp, N0.getOperand(1));
7696 }
7698 return SDValue();
7699 }
7701 SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
7702 SDValue N0 = N->getOperand(0);
7703 EVT VT = N->getValueType(0);
7704 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
7705 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7707 // fold (fp_round_inreg c1fp) -> c1fp
7708 if (N0CFP && isTypeLegal(EVT)) {
7709 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT);
7710 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, Round);
7711 }
7713 return SDValue();
7714 }
7716 SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
7717 SDValue N0 = N->getOperand(0);
7718 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7719 EVT VT = N->getValueType(0);
7721 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
7722 if (N->hasOneUse() &&
7723 N->use_begin()->getOpcode() == ISD::FP_ROUND)
7724 return SDValue();
7726 // fold (fp_extend c1fp) -> c1fp
7727 if (N0CFP)
7728 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, N0);
7730 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
7731 // value of X.
7732 if (N0.getOpcode() == ISD::FP_ROUND
7733 && N0.getNode()->getConstantOperandVal(1) == 1) {
7734 SDValue In = N0.getOperand(0);
7735 if (In.getValueType() == VT) return In;
7736 if (VT.bitsLT(In.getValueType()))
7737 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT,
7738 In, N0.getOperand(1));
7739 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, In);
7740 }
7742 // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
7743 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
7744 TLI.isLoadExtLegal(ISD::EXTLOAD, VT, N0.getValueType())) {
7745 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
7746 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(N), VT,
7747 LN0->getChain(),
7748 LN0->getBasePtr(), N0.getValueType(),
7749 LN0->getMemOperand());
7750 CombineTo(N, ExtLoad);
7751 CombineTo(N0.getNode(),
7752 DAG.getNode(ISD::FP_ROUND, SDLoc(N0),
7753 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)),
7754 ExtLoad.getValue(1));
7755 return SDValue(N, 0); // Return N so it doesn't get rechecked!
7756 }
7758 return SDValue();
7759 }
7761 SDValue DAGCombiner::visitFCEIL(SDNode *N) {
7762 SDValue N0 = N->getOperand(0);
7763 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7764 EVT VT = N->getValueType(0);
7766 // fold (fceil c1) -> fceil(c1)
7767 if (N0CFP)
7768 return DAG.getNode(ISD::FCEIL, SDLoc(N), VT, N0);
7770 return SDValue();
7771 }
7773 SDValue DAGCombiner::visitFTRUNC(SDNode *N) {
7774 SDValue N0 = N->getOperand(0);
7775 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7776 EVT VT = N->getValueType(0);
7778 // fold (ftrunc c1) -> ftrunc(c1)
7779 if (N0CFP)
7780 return DAG.getNode(ISD::FTRUNC, SDLoc(N), VT, N0);
7782 return SDValue();
7783 }
7785 SDValue DAGCombiner::visitFFLOOR(SDNode *N) {
7786 SDValue N0 = N->getOperand(0);
7787 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7788 EVT VT = N->getValueType(0);
7790 // fold (ffloor c1) -> ffloor(c1)
7791 if (N0CFP)
7792 return DAG.getNode(ISD::FFLOOR, SDLoc(N), VT, N0);
7794 return SDValue();
7795 }
7797 // FIXME: FNEG and FABS have a lot in common; refactor.
7798 SDValue DAGCombiner::visitFNEG(SDNode *N) {
7799 SDValue N0 = N->getOperand(0);
7800 EVT VT = N->getValueType(0);
7802 if (VT.isVector()) {
7803 SDValue FoldedVOp = SimplifyVUnaryOp(N);
7804 if (FoldedVOp.getNode()) return FoldedVOp;
7805 }
7807 // Constant fold FNEG.
7808 if (isa<ConstantFPSDNode>(N0))
7809 return DAG.getNode(ISD::FNEG, SDLoc(N), VT, N->getOperand(0));
7811 if (isNegatibleForFree(N0, LegalOperations, DAG.getTargetLoweringInfo(),
7812 &DAG.getTarget().Options))
7813 return GetNegatedExpression(N0, DAG, LegalOperations);
7815 // Transform fneg(bitconvert(x)) -> bitconvert(x ^ sign) to avoid loading
7816 // constant pool values.
7817 if (!TLI.isFNegFree(VT) &&
7818 N0.getOpcode() == ISD::BITCAST &&
7819 N0.getNode()->hasOneUse()) {
7820 SDValue Int = N0.getOperand(0);
7821 EVT IntVT = Int.getValueType();
7822 if (IntVT.isInteger() && !IntVT.isVector()) {
7823 APInt SignMask;
7824 if (N0.getValueType().isVector()) {
7825 // For a vector, get a mask such as 0x80... per scalar element
7826 // and splat it.
7827 SignMask = APInt::getSignBit(N0.getValueType().getScalarSizeInBits());
7828 SignMask = APInt::getSplat(IntVT.getSizeInBits(), SignMask);
7829 } else {
7830 // For a scalar, just generate 0x80...
7831 SignMask = APInt::getSignBit(IntVT.getSizeInBits());
7832 }
7833 Int = DAG.getNode(ISD::XOR, SDLoc(N0), IntVT, Int,
7834 DAG.getConstant(SignMask, IntVT));
7835 AddToWorklist(Int.getNode());
7836 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Int);
7837 }
7838 }
7840 // (fneg (fmul c, x)) -> (fmul -c, x)
7841 if (N0.getOpcode() == ISD::FMUL) {
7842 ConstantFPSDNode *CFP1 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1));
7843 if (CFP1) {
7844 APFloat CVal = CFP1->getValueAPF();
7845 CVal.changeSign();
7846 if (Level >= AfterLegalizeDAG &&
7847 (TLI.isFPImmLegal(CVal, N->getValueType(0)) ||
7848 TLI.isOperationLegal(ISD::ConstantFP, N->getValueType(0))))
7849 return DAG.getNode(
7850 ISD::FMUL, SDLoc(N), VT, N0.getOperand(0),
7851 DAG.getNode(ISD::FNEG, SDLoc(N), VT, N0.getOperand(1)));
7852 }
7853 }
7855 return SDValue();
7856 }
7858 SDValue DAGCombiner::visitFMINNUM(SDNode *N) {
7859 SDValue N0 = N->getOperand(0);
7860 SDValue N1 = N->getOperand(1);
7861 const ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7862 const ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
7864 if (N0CFP && N1CFP) {
7865 const APFloat &C0 = N0CFP->getValueAPF();
7866 const APFloat &C1 = N1CFP->getValueAPF();
7867 return DAG.getConstantFP(minnum(C0, C1), N->getValueType(0));
7868 }
7870 if (N0CFP) {
7871 EVT VT = N->getValueType(0);
7872 // Canonicalize to constant on RHS.
7873 return DAG.getNode(ISD::FMINNUM, SDLoc(N), VT, N1, N0);
7874 }
7876 return SDValue();
7877 }
7879 SDValue DAGCombiner::visitFMAXNUM(SDNode *N) {
7880 SDValue N0 = N->getOperand(0);
7881 SDValue N1 = N->getOperand(1);
7882 const ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7883 const ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
7885 if (N0CFP && N1CFP) {
7886 const APFloat &C0 = N0CFP->getValueAPF();
7887 const APFloat &C1 = N1CFP->getValueAPF();
7888 return DAG.getConstantFP(maxnum(C0, C1), N->getValueType(0));
7889 }
7891 if (N0CFP) {
7892 EVT VT = N->getValueType(0);
7893 // Canonicalize to constant on RHS.
7894 return DAG.getNode(ISD::FMAXNUM, SDLoc(N), VT, N1, N0);
7895 }
7897 return SDValue();
7898 }
7900 SDValue DAGCombiner::visitFABS(SDNode *N) {
7901 SDValue N0 = N->getOperand(0);
7902 EVT VT = N->getValueType(0);
7904 if (VT.isVector()) {
7905 SDValue FoldedVOp = SimplifyVUnaryOp(N);
7906 if (FoldedVOp.getNode()) return FoldedVOp;
7907 }
7909 // fold (fabs c1) -> fabs(c1)
7910 if (isa<ConstantFPSDNode>(N0))
7911 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0);
7913 // fold (fabs (fabs x)) -> (fabs x)
7914 if (N0.getOpcode() == ISD::FABS)
7915 return N->getOperand(0);
7917 // fold (fabs (fneg x)) -> (fabs x)
7918 // fold (fabs (fcopysign x, y)) -> (fabs x)
7919 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
7920 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0.getOperand(0));
7922 // Transform fabs(bitconvert(x)) -> bitconvert(x & ~sign) to avoid loading
7923 // constant pool values.
7924 if (!TLI.isFAbsFree(VT) &&
7925 N0.getOpcode() == ISD::BITCAST &&
7926 N0.getNode()->hasOneUse()) {
7927 SDValue Int = N0.getOperand(0);
7928 EVT IntVT = Int.getValueType();
7929 if (IntVT.isInteger() && !IntVT.isVector()) {
7930 APInt SignMask;
7931 if (N0.getValueType().isVector()) {
7932 // For a vector, get a mask such as 0x7f... per scalar element
7933 // and splat it.
7934 SignMask = ~APInt::getSignBit(N0.getValueType().getScalarSizeInBits());
7935 SignMask = APInt::getSplat(IntVT.getSizeInBits(), SignMask);
7936 } else {
7937 // For a scalar, just generate 0x7f...
7938 SignMask = ~APInt::getSignBit(IntVT.getSizeInBits());
7939 }
7940 Int = DAG.getNode(ISD::AND, SDLoc(N0), IntVT, Int,
7941 DAG.getConstant(SignMask, IntVT));
7942 AddToWorklist(Int.getNode());
7943 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0), Int);
7944 }
7945 }
7947 return SDValue();
7948 }
7950 SDValue DAGCombiner::visitBRCOND(SDNode *N) {
7951 SDValue Chain = N->getOperand(0);
7952 SDValue N1 = N->getOperand(1);
7953 SDValue N2 = N->getOperand(2);
7955 // If N is a constant we could fold this into a fallthrough or unconditional
7956 // branch. However that doesn't happen very often in normal code, because
7957 // Instcombine/SimplifyCFG should have handled the available opportunities.
7958 // If we did this folding here, it would be necessary to update the
7959 // MachineBasicBlock CFG, which is awkward.
7961 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
7962 // on the target.
7963 if (N1.getOpcode() == ISD::SETCC &&
7964 TLI.isOperationLegalOrCustom(ISD::BR_CC,
7965 N1.getOperand(0).getValueType())) {
7966 return DAG.getNode(ISD::BR_CC, SDLoc(N), MVT::Other,
7967 Chain, N1.getOperand(2),
7968 N1.getOperand(0), N1.getOperand(1), N2);
7969 }
7971 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) ||
7972 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) &&
7973 (N1.getOperand(0).hasOneUse() &&
7974 N1.getOperand(0).getOpcode() == ISD::SRL))) {
7975 SDNode *Trunc = nullptr;
7976 if (N1.getOpcode() == ISD::TRUNCATE) {
7977 // Look pass the truncate.
7978 Trunc = N1.getNode();
7979 N1 = N1.getOperand(0);
7980 }
7982 // Match this pattern so that we can generate simpler code:
7983 //
7984 // %a = ...
7985 // %b = and i32 %a, 2
7986 // %c = srl i32 %b, 1
7987 // brcond i32 %c ...
7988 //
7989 // into
7990 //
7991 // %a = ...
7992 // %b = and i32 %a, 2
7993 // %c = setcc eq %b, 0
7994 // brcond %c ...
7995 //
7996 // This applies only when the AND constant value has one bit set and the
7997 // SRL constant is equal to the log2 of the AND constant. The back-end is
7998 // smart enough to convert the result into a TEST/JMP sequence.
7999 SDValue Op0 = N1.getOperand(0);
8000 SDValue Op1 = N1.getOperand(1);
8002 if (Op0.getOpcode() == ISD::AND &&
8003 Op1.getOpcode() == ISD::Constant) {
8004 SDValue AndOp1 = Op0.getOperand(1);
8006 if (AndOp1.getOpcode() == ISD::Constant) {
8007 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue();
8009 if (AndConst.isPowerOf2() &&
8010 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) {
8011 SDValue SetCC =
8012 DAG.getSetCC(SDLoc(N),
8013 getSetCCResultType(Op0.getValueType()),
8014 Op0, DAG.getConstant(0, Op0.getValueType()),
8015 ISD::SETNE);
8017 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, SDLoc(N),
8018 MVT::Other, Chain, SetCC, N2);
8019 // Don't add the new BRCond into the worklist or else SimplifySelectCC
8020 // will convert it back to (X & C1) >> C2.
8021 CombineTo(N, NewBRCond, false);
8022 // Truncate is dead.
8023 if (Trunc)
8024 deleteAndRecombine(Trunc);
8025 // Replace the uses of SRL with SETCC
8026 WorklistRemover DeadNodes(*this);
8027 DAG.ReplaceAllUsesOfValueWith(N1, SetCC);
8028 deleteAndRecombine(N1.getNode());
8029 return SDValue(N, 0); // Return N so it doesn't get rechecked!
8030 }
8031 }
8032 }
8034 if (Trunc)
8035 // Restore N1 if the above transformation doesn't match.
8036 N1 = N->getOperand(1);
8037 }
8039 // Transform br(xor(x, y)) -> br(x != y)
8040 // Transform br(xor(xor(x,y), 1)) -> br (x == y)
8041 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) {
8042 SDNode *TheXor = N1.getNode();
8043 SDValue Op0 = TheXor->getOperand(0);
8044 SDValue Op1 = TheXor->getOperand(1);
8045 if (Op0.getOpcode() == Op1.getOpcode()) {
8046 // Avoid missing important xor optimizations.
8047 SDValue Tmp = visitXOR(TheXor);
8048 if (Tmp.getNode()) {
8049 if (Tmp.getNode() != TheXor) {
8050 DEBUG(dbgs() << "\nReplacing.8 ";
8051 TheXor->dump(&DAG);
8052 dbgs() << "\nWith: ";
8053 Tmp.getNode()->dump(&DAG);
8054 dbgs() << '\n');
8055 WorklistRemover DeadNodes(*this);
8056 DAG.ReplaceAllUsesOfValueWith(N1, Tmp);
8057 deleteAndRecombine(TheXor);
8058 return DAG.getNode(ISD::BRCOND, SDLoc(N),
8059 MVT::Other, Chain, Tmp, N2);
8060 }
8062 // visitXOR has changed XOR's operands or replaced the XOR completely,
8063 // bail out.
8064 return SDValue(N, 0);
8065 }
8066 }
8068 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) {
8069 bool Equal = false;
8070 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0))
8071 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() &&
8072 Op0.getOpcode() == ISD::XOR) {
8073 TheXor = Op0.getNode();
8074 Equal = true;
8075 }
8077 EVT SetCCVT = N1.getValueType();
8078 if (LegalTypes)
8079 SetCCVT = getSetCCResultType(SetCCVT);
8080 SDValue SetCC = DAG.getSetCC(SDLoc(TheXor),
8081 SetCCVT,
8082 Op0, Op1,
8083 Equal ? ISD::SETEQ : ISD::SETNE);
8084 // Replace the uses of XOR with SETCC
8085 WorklistRemover DeadNodes(*this);
8086 DAG.ReplaceAllUsesOfValueWith(N1, SetCC);
8087 deleteAndRecombine(N1.getNode());
8088 return DAG.getNode(ISD::BRCOND, SDLoc(N),
8089 MVT::Other, Chain, SetCC, N2);
8090 }
8091 }
8093 return SDValue();
8094 }
8096 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
8097 //
8098 SDValue DAGCombiner::visitBR_CC(SDNode *N) {
8099 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
8100 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
8102 // If N is a constant we could fold this into a fallthrough or unconditional
8103 // branch. However that doesn't happen very often in normal code, because
8104 // Instcombine/SimplifyCFG should have handled the available opportunities.
8105 // If we did this folding here, it would be necessary to update the
8106 // MachineBasicBlock CFG, which is awkward.
8108 // Use SimplifySetCC to simplify SETCC's.
8109 SDValue Simp = SimplifySetCC(getSetCCResultType(CondLHS.getValueType()),
8110 CondLHS, CondRHS, CC->get(), SDLoc(N),
8111 false);
8112 if (Simp.getNode()) AddToWorklist(Simp.getNode());
8114 // fold to a simpler setcc
8115 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
8116 return DAG.getNode(ISD::BR_CC, SDLoc(N), MVT::Other,
8117 N->getOperand(0), Simp.getOperand(2),
8118 Simp.getOperand(0), Simp.getOperand(1),
8119 N->getOperand(4));
8121 return SDValue();
8122 }
8124 /// Return true if 'Use' is a load or a store that uses N as its base pointer
8125 /// and that N may be folded in the load / store addressing mode.
8126 static bool canFoldInAddressingMode(SDNode *N, SDNode *Use,
8127 SelectionDAG &DAG,
8128 const TargetLowering &TLI) {
8129 EVT VT;
8130 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Use)) {
8131 if (LD->isIndexed() || LD->getBasePtr().getNode() != N)
8132 return false;
8133 VT = Use->getValueType(0);
8134 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(Use)) {
8135 if (ST->isIndexed() || ST->getBasePtr().getNode() != N)
8136 return false;
8137 VT = ST->getValue().getValueType();
8138 } else
8139 return false;
8141 TargetLowering::AddrMode AM;
8142 if (N->getOpcode() == ISD::ADD) {
8143 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
8144 if (Offset)
8145 // [reg +/- imm]
8146 AM.BaseOffs = Offset->getSExtValue();
8147 else
8148 // [reg +/- reg]
8149 AM.Scale = 1;
8150 } else if (N->getOpcode() == ISD::SUB) {
8151 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
8152 if (Offset)
8153 // [reg +/- imm]
8154 AM.BaseOffs = -Offset->getSExtValue();
8155 else
8156 // [reg +/- reg]
8157 AM.Scale = 1;
8158 } else
8159 return false;
8161 return TLI.isLegalAddressingMode(AM, VT.getTypeForEVT(*DAG.getContext()));
8162 }
8164 /// Try turning a load/store into a pre-indexed load/store when the base
8165 /// pointer is an add or subtract and it has other uses besides the load/store.
8166 /// After the transformation, the new indexed load/store has effectively folded
8167 /// the add/subtract in and all of its other uses are redirected to the
8168 /// new load/store.
8169 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
8170 if (Level < AfterLegalizeDAG)
8171 return false;
8173 bool isLoad = true;
8174 SDValue Ptr;
8175 EVT VT;
8176 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
8177 if (LD->isIndexed())
8178 return false;
8179 VT = LD->getMemoryVT();
8180 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
8181 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
8182 return false;
8183 Ptr = LD->getBasePtr();
8184 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
8185 if (ST->isIndexed())
8186 return false;
8187 VT = ST->getMemoryVT();
8188 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
8189 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
8190 return false;
8191 Ptr = ST->getBasePtr();
8192 isLoad = false;
8193 } else {
8194 return false;
8195 }
8197 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
8198 // out. There is no reason to make this a preinc/predec.
8199 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
8200 Ptr.getNode()->hasOneUse())
8201 return false;
8203 // Ask the target to do addressing mode selection.
8204 SDValue BasePtr;
8205 SDValue Offset;
8206 ISD::MemIndexedMode AM = ISD::UNINDEXED;
8207 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
8208 return false;
8210 // Backends without true r+i pre-indexed forms may need to pass a
8211 // constant base with a variable offset so that constant coercion
8212 // will work with the patterns in canonical form.
8213 bool Swapped = false;
8214 if (isa<ConstantSDNode>(BasePtr)) {
8215 std::swap(BasePtr, Offset);
8216 Swapped = true;
8217 }
8219 // Don't create a indexed load / store with zero offset.
8220 if (isa<ConstantSDNode>(Offset) &&
8221 cast<ConstantSDNode>(Offset)->isNullValue())
8222 return false;
8224 // Try turning it into a pre-indexed load / store except when:
8225 // 1) The new base ptr is a frame index.
8226 // 2) If N is a store and the new base ptr is either the same as or is a
8227 // predecessor of the value being stored.
8228 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
8229 // that would create a cycle.
8230 // 4) All uses are load / store ops that use it as old base ptr.
8232 // Check #1. Preinc'ing a frame index would require copying the stack pointer
8233 // (plus the implicit offset) to a register to preinc anyway.
8234 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
8235 return false;
8237 // Check #2.
8238 if (!isLoad) {
8239 SDValue Val = cast<StoreSDNode>(N)->getValue();
8240 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode()))
8241 return false;
8242 }
8244 // If the offset is a constant, there may be other adds of constants that
8245 // can be folded with this one. We should do this to avoid having to keep
8246 // a copy of the original base pointer.
8247 SmallVector<SDNode *, 16> OtherUses;
8248 if (isa<ConstantSDNode>(Offset))
8249 for (SDNode *Use : BasePtr.getNode()->uses()) {
8250 if (Use == Ptr.getNode())
8251 continue;
8253 if (Use->isPredecessorOf(N))
8254 continue;
8256 if (Use->getOpcode() != ISD::ADD && Use->getOpcode() != ISD::SUB) {
8257 OtherUses.clear();
8258 break;
8259 }
8261 SDValue Op0 = Use->getOperand(0), Op1 = Use->getOperand(1);
8262 if (Op1.getNode() == BasePtr.getNode())
8263 std::swap(Op0, Op1);
8264 assert(Op0.getNode() == BasePtr.getNode() &&
8265 "Use of ADD/SUB but not an operand");
8267 if (!isa<ConstantSDNode>(Op1)) {
8268 OtherUses.clear();
8269 break;
8270 }
8272 // FIXME: In some cases, we can be smarter about this.
8273 if (Op1.getValueType() != Offset.getValueType()) {
8274 OtherUses.clear();
8275 break;
8276 }
8278 OtherUses.push_back(Use);
8279 }
8281 if (Swapped)
8282 std::swap(BasePtr, Offset);
8284 // Now check for #3 and #4.
8285 bool RealUse = false;
8287 // Caches for hasPredecessorHelper
8288 SmallPtrSet<const SDNode *, 32> Visited;
8289 SmallVector<const SDNode *, 16> Worklist;
8291 for (SDNode *Use : Ptr.getNode()->uses()) {
8292 if (Use == N)
8293 continue;
8294 if (N->hasPredecessorHelper(Use, Visited, Worklist))
8295 return false;
8297 // If Ptr may be folded in addressing mode of other use, then it's
8298 // not profitable to do this transformation.
8299 if (!canFoldInAddressingMode(Ptr.getNode(), Use, DAG, TLI))
8300 RealUse = true;
8301 }
8303 if (!RealUse)
8304 return false;
8306 SDValue Result;
8307 if (isLoad)
8308 Result = DAG.getIndexedLoad(SDValue(N,0), SDLoc(N),
8309 BasePtr, Offset, AM);
8310 else
8311 Result = DAG.getIndexedStore(SDValue(N,0), SDLoc(N),
8312 BasePtr, Offset, AM);
8313 ++PreIndexedNodes;
8314 ++NodesCombined;
8315 DEBUG(dbgs() << "\nReplacing.4 ";
8316 N->dump(&DAG);
8317 dbgs() << "\nWith: ";
8318 Result.getNode()->dump(&DAG);
8319 dbgs() << '\n');
8320 WorklistRemover DeadNodes(*this);
8321 if (isLoad) {
8322 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0));
8323 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2));
8324 } else {
8325 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1));
8326 }
8328 // Finally, since the node is now dead, remove it from the graph.
8329 deleteAndRecombine(N);
8331 if (Swapped)
8332 std::swap(BasePtr, Offset);
8334 // Replace other uses of BasePtr that can be updated to use Ptr
8335 for (unsigned i = 0, e = OtherUses.size(); i != e; ++i) {
8336 unsigned OffsetIdx = 1;
8337 if (OtherUses[i]->getOperand(OffsetIdx).getNode() == BasePtr.getNode())
8338 OffsetIdx = 0;
8339 assert(OtherUses[i]->getOperand(!OffsetIdx).getNode() ==
8340 BasePtr.getNode() && "Expected BasePtr operand");
8342 // We need to replace ptr0 in the following expression:
8343 // x0 * offset0 + y0 * ptr0 = t0
8344 // knowing that
8345 // x1 * offset1 + y1 * ptr0 = t1 (the indexed load/store)
8346 //
8347 // where x0, x1, y0 and y1 in {-1, 1} are given by the types of the
8348 // indexed load/store and the expresion that needs to be re-written.
8349 //
8350 // Therefore, we have:
8351 // t0 = (x0 * offset0 - x1 * y0 * y1 *offset1) + (y0 * y1) * t1
8353 ConstantSDNode *CN =
8354 cast<ConstantSDNode>(OtherUses[i]->getOperand(OffsetIdx));
8355 int X0, X1, Y0, Y1;
8356 APInt Offset0 = CN->getAPIntValue();
8357 APInt Offset1 = cast<ConstantSDNode>(Offset)->getAPIntValue();
8359 X0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 1) ? -1 : 1;
8360 Y0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 0) ? -1 : 1;
8361 X1 = (AM == ISD::PRE_DEC && !Swapped) ? -1 : 1;
8362 Y1 = (AM == ISD::PRE_DEC && Swapped) ? -1 : 1;
8364 unsigned Opcode = (Y0 * Y1 < 0) ? ISD::SUB : ISD::ADD;
8366 APInt CNV = Offset0;
8367 if (X0 < 0) CNV = -CNV;
8368 if (X1 * Y0 * Y1 < 0) CNV = CNV + Offset1;
8369 else CNV = CNV - Offset1;
8371 // We can now generate the new expression.
8372 SDValue NewOp1 = DAG.getConstant(CNV, CN->getValueType(0));
8373 SDValue NewOp2 = Result.getValue(isLoad ? 1 : 0);
8375 SDValue NewUse = DAG.getNode(Opcode,
8376 SDLoc(OtherUses[i]),
8377 OtherUses[i]->getValueType(0), NewOp1, NewOp2);
8378 DAG.ReplaceAllUsesOfValueWith(SDValue(OtherUses[i], 0), NewUse);
8379 deleteAndRecombine(OtherUses[i]);
8380 }
8382 // Replace the uses of Ptr with uses of the updated base value.
8383 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0));
8384 deleteAndRecombine(Ptr.getNode());
8386 return true;
8387 }
8389 /// Try to combine a load/store with a add/sub of the base pointer node into a
8390 /// post-indexed load/store. The transformation folded the add/subtract into the
8391 /// new indexed load/store effectively and all of its uses are redirected to the
8392 /// new load/store.
8393 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
8394 if (Level < AfterLegalizeDAG)
8395 return false;
8397 bool isLoad = true;
8398 SDValue Ptr;
8399 EVT VT;
8400 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
8401 if (LD->isIndexed())
8402 return false;
8403 VT = LD->getMemoryVT();
8404 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
8405 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
8406 return false;
8407 Ptr = LD->getBasePtr();
8408 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
8409 if (ST->isIndexed())
8410 return false;
8411 VT = ST->getMemoryVT();
8412 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
8413 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
8414 return false;
8415 Ptr = ST->getBasePtr();
8416 isLoad = false;
8417 } else {
8418 return false;
8419 }
8421 if (Ptr.getNode()->hasOneUse())
8422 return false;
8424 for (SDNode *Op : Ptr.getNode()->uses()) {
8425 if (Op == N ||
8426 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
8427 continue;
8429 SDValue BasePtr;
8430 SDValue Offset;
8431 ISD::MemIndexedMode AM = ISD::UNINDEXED;
8432 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
8433 // Don't create a indexed load / store with zero offset.
8434 if (isa<ConstantSDNode>(Offset) &&
8435 cast<ConstantSDNode>(Offset)->isNullValue())
8436 continue;
8438 // Try turning it into a post-indexed load / store except when
8439 // 1) All uses are load / store ops that use it as base ptr (and
8440 // it may be folded as addressing mmode).
8441 // 2) Op must be independent of N, i.e. Op is neither a predecessor
8442 // nor a successor of N. Otherwise, if Op is folded that would
8443 // create a cycle.
8445 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
8446 continue;
8448 // Check for #1.
8449 bool TryNext = false;
8450 for (SDNode *Use : BasePtr.getNode()->uses()) {
8451 if (Use == Ptr.getNode())
8452 continue;
8454 // If all the uses are load / store addresses, then don't do the
8455 // transformation.
8456 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
8457 bool RealUse = false;
8458 for (SDNode *UseUse : Use->uses()) {
8459 if (!canFoldInAddressingMode(Use, UseUse, DAG, TLI))
8460 RealUse = true;
8461 }
8463 if (!RealUse) {
8464 TryNext = true;
8465 break;
8466 }
8467 }
8468 }
8470 if (TryNext)
8471 continue;
8473 // Check for #2
8474 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) {
8475 SDValue Result = isLoad
8476 ? DAG.getIndexedLoad(SDValue(N,0), SDLoc(N),
8477 BasePtr, Offset, AM)
8478 : DAG.getIndexedStore(SDValue(N,0), SDLoc(N),
8479 BasePtr, Offset, AM);
8480 ++PostIndexedNodes;
8481 ++NodesCombined;
8482 DEBUG(dbgs() << "\nReplacing.5 ";
8483 N->dump(&DAG);
8484 dbgs() << "\nWith: ";
8485 Result.getNode()->dump(&DAG);
8486 dbgs() << '\n');
8487 WorklistRemover DeadNodes(*this);
8488 if (isLoad) {
8489 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0));
8490 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2));
8491 } else {
8492 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1));
8493 }
8495 // Finally, since the node is now dead, remove it from the graph.
8496 deleteAndRecombine(N);
8498 // Replace the uses of Use with uses of the updated base value.
8499 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0),
8500 Result.getValue(isLoad ? 1 : 0));
8501 deleteAndRecombine(Op);
8502 return true;
8503 }
8504 }
8505 }
8507 return false;
8508 }
8510 /// \brief Return the base-pointer arithmetic from an indexed \p LD.
8511 SDValue DAGCombiner::SplitIndexingFromLoad(LoadSDNode *LD) {
8512 ISD::MemIndexedMode AM = LD->getAddressingMode();
8513 assert(AM != ISD::UNINDEXED);
8514 SDValue BP = LD->getOperand(1);
8515 SDValue Inc = LD->getOperand(2);
8517 // Some backends use TargetConstants for load offsets, but don't expect
8518 // TargetConstants in general ADD nodes. We can convert these constants into
8519 // regular Constants (if the constant is not opaque).
8520 assert((Inc.getOpcode() != ISD::TargetConstant ||
8521 !cast<ConstantSDNode>(Inc)->isOpaque()) &&
8522 "Cannot split out indexing using opaque target constants");
8523 if (Inc.getOpcode() == ISD::TargetConstant) {
8524 ConstantSDNode *ConstInc = cast<ConstantSDNode>(Inc);
8525 Inc = DAG.getConstant(*ConstInc->getConstantIntValue(),
8526 ConstInc->getValueType(0));
8527 }
8529 unsigned Opc =
8530 (AM == ISD::PRE_INC || AM == ISD::POST_INC ? ISD::ADD : ISD::SUB);
8531 return DAG.getNode(Opc, SDLoc(LD), BP.getSimpleValueType(), BP, Inc);
8532 }
8534 SDValue DAGCombiner::visitLOAD(SDNode *N) {
8535 LoadSDNode *LD = cast<LoadSDNode>(N);
8536 SDValue Chain = LD->getChain();
8537 SDValue Ptr = LD->getBasePtr();
8539 // If load is not volatile and there are no uses of the loaded value (and
8540 // the updated indexed value in case of indexed loads), change uses of the
8541 // chain value into uses of the chain input (i.e. delete the dead load).
8542 if (!LD->isVolatile()) {
8543 if (N->getValueType(1) == MVT::Other) {
8544 // Unindexed loads.
8545 if (!N->hasAnyUseOfValue(0)) {
8546 // It's not safe to use the two value CombineTo variant here. e.g.
8547 // v1, chain2 = load chain1, loc
8548 // v2, chain3 = load chain2, loc
8549 // v3 = add v2, c
8550 // Now we replace use of chain2 with chain1. This makes the second load
8551 // isomorphic to the one we are deleting, and thus makes this load live.
8552 DEBUG(dbgs() << "\nReplacing.6 ";
8553 N->dump(&DAG);
8554 dbgs() << "\nWith chain: ";
8555 Chain.getNode()->dump(&DAG);
8556 dbgs() << "\n");
8557 WorklistRemover DeadNodes(*this);
8558 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain);
8560 if (N->use_empty())
8561 deleteAndRecombine(N);
8563 return SDValue(N, 0); // Return N so it doesn't get rechecked!
8564 }
8565 } else {
8566 // Indexed loads.
8567 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
8569 // If this load has an opaque TargetConstant offset, then we cannot split
8570 // the indexing into an add/sub directly (that TargetConstant may not be
8571 // valid for a different type of node, and we cannot convert an opaque
8572 // target constant into a regular constant).
8573 bool HasOTCInc = LD->getOperand(2).getOpcode() == ISD::TargetConstant &&
8574 cast<ConstantSDNode>(LD->getOperand(2))->isOpaque();
8576 if (!N->hasAnyUseOfValue(0) &&
8577 ((MaySplitLoadIndex && !HasOTCInc) || !N->hasAnyUseOfValue(1))) {
8578 SDValue Undef = DAG.getUNDEF(N->getValueType(0));
8579 SDValue Index;
8580 if (N->hasAnyUseOfValue(1) && MaySplitLoadIndex && !HasOTCInc) {
8581 Index = SplitIndexingFromLoad(LD);
8582 // Try to fold the base pointer arithmetic into subsequent loads and
8583 // stores.
8584 AddUsersToWorklist(N);
8585 } else
8586 Index = DAG.getUNDEF(N->getValueType(1));
8587 DEBUG(dbgs() << "\nReplacing.7 ";
8588 N->dump(&DAG);
8589 dbgs() << "\nWith: ";
8590 Undef.getNode()->dump(&DAG);
8591 dbgs() << " and 2 other values\n");
8592 WorklistRemover DeadNodes(*this);
8593 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef);
8594 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Index);
8595 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain);
8596 deleteAndRecombine(N);
8597 return SDValue(N, 0); // Return N so it doesn't get rechecked!
8598 }
8599 }
8600 }
8602 // If this load is directly stored, replace the load value with the stored
8603 // value.
8604 // TODO: Handle store large -> read small portion.
8605 // TODO: Handle TRUNCSTORE/LOADEXT
8606 if (ISD::isNormalLoad(N) && !LD->isVolatile()) {
8607 if (ISD::isNON_TRUNCStore(Chain.getNode())) {
8608 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
8609 if (PrevST->getBasePtr() == Ptr &&
8610 PrevST->getValue().getValueType() == N->getValueType(0))
8611 return CombineTo(N, Chain.getOperand(1), Chain);
8612 }
8613 }
8615 // Try to infer better alignment information than the load already has.
8616 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
8617 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
8618 if (Align > LD->getMemOperand()->getBaseAlignment()) {
8619 SDValue NewLoad =
8620 DAG.getExtLoad(LD->getExtensionType(), SDLoc(N),
8621 LD->getValueType(0),
8622 Chain, Ptr, LD->getPointerInfo(),
8623 LD->getMemoryVT(),
8624 LD->isVolatile(), LD->isNonTemporal(),
8625 LD->isInvariant(), Align, LD->getAAInfo());
8626 return CombineTo(N, NewLoad, SDValue(NewLoad.getNode(), 1), true);
8627 }
8628 }
8629 }
8631 bool UseAA = CombinerAA.getNumOccurrences() > 0 ? CombinerAA
8632 : DAG.getSubtarget().useAA();
8633 #ifndef NDEBUG
8634 if (CombinerAAOnlyFunc.getNumOccurrences() &&
8635 CombinerAAOnlyFunc != DAG.getMachineFunction().getName())
8636 UseAA = false;
8637 #endif
8638 if (UseAA && LD->isUnindexed()) {
8639 // Walk up chain skipping non-aliasing memory nodes.
8640 SDValue BetterChain = FindBetterChain(N, Chain);
8642 // If there is a better chain.
8643 if (Chain != BetterChain) {
8644 SDValue ReplLoad;
8646 // Replace the chain to void dependency.
8647 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
8648 ReplLoad = DAG.getLoad(N->getValueType(0), SDLoc(LD),
8649 BetterChain, Ptr, LD->getMemOperand());
8650 } else {
8651 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), SDLoc(LD),
8652 LD->getValueType(0),
8653 BetterChain, Ptr, LD->getMemoryVT(),
8654 LD->getMemOperand());
8655 }
8657 // Create token factor to keep old chain connected.
8658 SDValue Token = DAG.getNode(ISD::TokenFactor, SDLoc(N),
8659 MVT::Other, Chain, ReplLoad.getValue(1));
8661 // Make sure the new and old chains are cleaned up.
8662 AddToWorklist(Token.getNode());
8664 // Replace uses with load result and token factor. Don't add users
8665 // to work list.
8666 return CombineTo(N, ReplLoad.getValue(0), Token, false);
8667 }
8668 }
8670 // Try transforming N to an indexed load.
8671 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
8672 return SDValue(N, 0);
8674 // Try to slice up N to more direct loads if the slices are mapped to
8675 // different register banks or pairing can take place.
8676 if (SliceUpLoad(N))
8677 return SDValue(N, 0);
8679 return SDValue();
8680 }
8682 namespace {
8683 /// \brief Helper structure used to slice a load in smaller loads.
8684 /// Basically a slice is obtained from the following sequence:
8685 /// Origin = load Ty1, Base
8686 /// Shift = srl Ty1 Origin, CstTy Amount
8687 /// Inst = trunc Shift to Ty2
8688 ///
8689 /// Then, it will be rewriten into:
8690 /// Slice = load SliceTy, Base + SliceOffset
8691 /// [Inst = zext Slice to Ty2], only if SliceTy <> Ty2
8692 ///
8693 /// SliceTy is deduced from the number of bits that are actually used to
8694 /// build Inst.
8695 struct LoadedSlice {
8696 /// \brief Helper structure used to compute the cost of a slice.
8697 struct Cost {
8698 /// Are we optimizing for code size.
8699 bool ForCodeSize;
8700 /// Various cost.
8701 unsigned Loads;
8702 unsigned Truncates;
8703 unsigned CrossRegisterBanksCopies;
8704 unsigned ZExts;
8705 unsigned Shift;
8707 Cost(bool ForCodeSize = false)
8708 : ForCodeSize(ForCodeSize), Loads(0), Truncates(0),
8709 CrossRegisterBanksCopies(0), ZExts(0), Shift(0) {}
8711 /// \brief Get the cost of one isolated slice.
8712 Cost(const LoadedSlice &LS, bool ForCodeSize = false)
8713 : ForCodeSize(ForCodeSize), Loads(1), Truncates(0),
8714 CrossRegisterBanksCopies(0), ZExts(0), Shift(0) {
8715 EVT TruncType = LS.Inst->getValueType(0);
8716 EVT LoadedType = LS.getLoadedType();
8717 if (TruncType != LoadedType &&
8718 !LS.DAG->getTargetLoweringInfo().isZExtFree(LoadedType, TruncType))
8719 ZExts = 1;
8720 }
8722 /// \brief Account for slicing gain in the current cost.
8723 /// Slicing provide a few gains like removing a shift or a
8724 /// truncate. This method allows to grow the cost of the original
8725 /// load with the gain from this slice.
8726 void addSliceGain(const LoadedSlice &LS) {
8727 // Each slice saves a truncate.
8728 const TargetLowering &TLI = LS.DAG->getTargetLoweringInfo();
8729 if (!TLI.isTruncateFree(LS.Inst->getValueType(0),
8730 LS.Inst->getOperand(0).getValueType()))
8731 ++Truncates;
8732 // If there is a shift amount, this slice gets rid of it.
8733 if (LS.Shift)
8734 ++Shift;
8735 // If this slice can merge a cross register bank copy, account for it.
8736 if (LS.canMergeExpensiveCrossRegisterBankCopy())
8737 ++CrossRegisterBanksCopies;
8738 }
8740 Cost &operator+=(const Cost &RHS) {
8741 Loads += RHS.Loads;
8742 Truncates += RHS.Truncates;
8743 CrossRegisterBanksCopies += RHS.CrossRegisterBanksCopies;
8744 ZExts += RHS.ZExts;
8745 Shift += RHS.Shift;
8746 return *this;
8747 }
8749 bool operator==(const Cost &RHS) const {
8750 return Loads == RHS.Loads && Truncates == RHS.Truncates &&
8751 CrossRegisterBanksCopies == RHS.CrossRegisterBanksCopies &&
8752 ZExts == RHS.ZExts && Shift == RHS.Shift;
8753 }
8755 bool operator!=(const Cost &RHS) const { return !(*this == RHS); }
8757 bool operator<(const Cost &RHS) const {
8758 // Assume cross register banks copies are as expensive as loads.
8759 // FIXME: Do we want some more target hooks?
8760 unsigned ExpensiveOpsLHS = Loads + CrossRegisterBanksCopies;
8761 unsigned ExpensiveOpsRHS = RHS.Loads + RHS.CrossRegisterBanksCopies;
8762 // Unless we are optimizing for code size, consider the
8763 // expensive operation first.
8764 if (!ForCodeSize && ExpensiveOpsLHS != ExpensiveOpsRHS)
8765 return ExpensiveOpsLHS < ExpensiveOpsRHS;
8766 return (Truncates + ZExts + Shift + ExpensiveOpsLHS) <
8767 (RHS.Truncates + RHS.ZExts + RHS.Shift + ExpensiveOpsRHS);
8768 }
8770 bool operator>(const Cost &RHS) const { return RHS < *this; }
8772 bool operator<=(const Cost &RHS) const { return !(RHS < *this); }
8774 bool operator>=(const Cost &RHS) const { return !(*this < RHS); }
8775 };
8776 // The last instruction that represent the slice. This should be a
8777 // truncate instruction.
8778 SDNode *Inst;
8779 // The original load instruction.
8780 LoadSDNode *Origin;
8781 // The right shift amount in bits from the original load.
8782 unsigned Shift;
8783 // The DAG from which Origin came from.
8784 // This is used to get some contextual information about legal types, etc.
8785 SelectionDAG *DAG;
8787 LoadedSlice(SDNode *Inst = nullptr, LoadSDNode *Origin = nullptr,
8788 unsigned Shift = 0, SelectionDAG *DAG = nullptr)
8789 : Inst(Inst), Origin(Origin), Shift(Shift), DAG(DAG) {}
8791 LoadedSlice(const LoadedSlice &LS)
8792 : Inst(LS.Inst), Origin(LS.Origin), Shift(LS.Shift), DAG(LS.DAG) {}
8794 /// \brief Get the bits used in a chunk of bits \p BitWidth large.
8795 /// \return Result is \p BitWidth and has used bits set to 1 and
8796 /// not used bits set to 0.
8797 APInt getUsedBits() const {
8798 // Reproduce the trunc(lshr) sequence:
8799 // - Start from the truncated value.
8800 // - Zero extend to the desired bit width.
8801 // - Shift left.
8802 assert(Origin && "No original load to compare against.");
8803 unsigned BitWidth = Origin->getValueSizeInBits(0);
8804 assert(Inst && "This slice is not bound to an instruction");
8805 assert(Inst->getValueSizeInBits(0) <= BitWidth &&
8806 "Extracted slice is bigger than the whole type!");
8807 APInt UsedBits(Inst->getValueSizeInBits(0), 0);
8808 UsedBits.setAllBits();
8809 UsedBits = UsedBits.zext(BitWidth);
8810 UsedBits <<= Shift;
8811 return UsedBits;
8812 }
8814 /// \brief Get the size of the slice to be loaded in bytes.
8815 unsigned getLoadedSize() const {
8816 unsigned SliceSize = getUsedBits().countPopulation();
8817 assert(!(SliceSize & 0x7) && "Size is not a multiple of a byte.");
8818 return SliceSize / 8;
8819 }
8821 /// \brief Get the type that will be loaded for this slice.
8822 /// Note: This may not be the final type for the slice.
8823 EVT getLoadedType() const {
8824 assert(DAG && "Missing context");
8825 LLVMContext &Ctxt = *DAG->getContext();
8826 return EVT::getIntegerVT(Ctxt, getLoadedSize() * 8);
8827 }
8829 /// \brief Get the alignment of the load used for this slice.
8830 unsigned getAlignment() const {
8831 unsigned Alignment = Origin->getAlignment();
8832 unsigned Offset = getOffsetFromBase();
8833 if (Offset != 0)
8834 Alignment = MinAlign(Alignment, Alignment + Offset);
8835 return Alignment;
8836 }
8838 /// \brief Check if this slice can be rewritten with legal operations.
8839 bool isLegal() const {
8840 // An invalid slice is not legal.
8841 if (!Origin || !Inst || !DAG)
8842 return false;
8844 // Offsets are for indexed load only, we do not handle that.
8845 if (Origin->getOffset().getOpcode() != ISD::UNDEF)
8846 return false;
8848 const TargetLowering &TLI = DAG->getTargetLoweringInfo();
8850 // Check that the type is legal.
8851 EVT SliceType = getLoadedType();
8852 if (!TLI.isTypeLegal(SliceType))
8853 return false;
8855 // Check that the load is legal for this type.
8856 if (!TLI.isOperationLegal(ISD::LOAD, SliceType))
8857 return false;
8859 // Check that the offset can be computed.
8860 // 1. Check its type.
8861 EVT PtrType = Origin->getBasePtr().getValueType();
8862 if (PtrType == MVT::Untyped || PtrType.isExtended())
8863 return false;
8865 // 2. Check that it fits in the immediate.
8866 if (!TLI.isLegalAddImmediate(getOffsetFromBase()))
8867 return false;
8869 // 3. Check that the computation is legal.
8870 if (!TLI.isOperationLegal(ISD::ADD, PtrType))
8871 return false;
8873 // Check that the zext is legal if it needs one.
8874 EVT TruncateType = Inst->getValueType(0);
8875 if (TruncateType != SliceType &&
8876 !TLI.isOperationLegal(ISD::ZERO_EXTEND, TruncateType))
8877 return false;
8879 return true;
8880 }
8882 /// \brief Get the offset in bytes of this slice in the original chunk of
8883 /// bits.
8884 /// \pre DAG != nullptr.
8885 uint64_t getOffsetFromBase() const {
8886 assert(DAG && "Missing context.");
8887 bool IsBigEndian =
8888 DAG->getTargetLoweringInfo().getDataLayout()->isBigEndian();
8889 assert(!(Shift & 0x7) && "Shifts not aligned on Bytes are not supported.");
8890 uint64_t Offset = Shift / 8;
8891 unsigned TySizeInBytes = Origin->getValueSizeInBits(0) / 8;
8892 assert(!(Origin->getValueSizeInBits(0) & 0x7) &&
8893 "The size of the original loaded type is not a multiple of a"
8894 " byte.");
8895 // If Offset is bigger than TySizeInBytes, it means we are loading all
8896 // zeros. This should have been optimized before in the process.
8897 assert(TySizeInBytes > Offset &&
8898 "Invalid shift amount for given loaded size");
8899 if (IsBigEndian)
8900 Offset = TySizeInBytes - Offset - getLoadedSize();
8901 return Offset;
8902 }
8904 /// \brief Generate the sequence of instructions to load the slice
8905 /// represented by this object and redirect the uses of this slice to
8906 /// this new sequence of instructions.
8907 /// \pre this->Inst && this->Origin are valid Instructions and this
8908 /// object passed the legal check: LoadedSlice::isLegal returned true.
8909 /// \return The last instruction of the sequence used to load the slice.
8910 SDValue loadSlice() const {
8911 assert(Inst && Origin && "Unable to replace a non-existing slice.");
8912 const SDValue &OldBaseAddr = Origin->getBasePtr();
8913 SDValue BaseAddr = OldBaseAddr;
8914 // Get the offset in that chunk of bytes w.r.t. the endianess.
8915 int64_t Offset = static_cast<int64_t>(getOffsetFromBase());
8916 assert(Offset >= 0 && "Offset too big to fit in int64_t!");
8917 if (Offset) {
8918 // BaseAddr = BaseAddr + Offset.
8919 EVT ArithType = BaseAddr.getValueType();
8920 BaseAddr = DAG->getNode(ISD::ADD, SDLoc(Origin), ArithType, BaseAddr,
8921 DAG->getConstant(Offset, ArithType));
8922 }
8924 // Create the type of the loaded slice according to its size.
8925 EVT SliceType = getLoadedType();
8927 // Create the load for the slice.
8928 SDValue LastInst = DAG->getLoad(
8929 SliceType, SDLoc(Origin), Origin->getChain(), BaseAddr,
8930 Origin->getPointerInfo().getWithOffset(Offset), Origin->isVolatile(),
8931 Origin->isNonTemporal(), Origin->isInvariant(), getAlignment());
8932 // If the final type is not the same as the loaded type, this means that
8933 // we have to pad with zero. Create a zero extend for that.
8934 EVT FinalType = Inst->getValueType(0);
8935 if (SliceType != FinalType)
8936 LastInst =
8937 DAG->getNode(ISD::ZERO_EXTEND, SDLoc(LastInst), FinalType, LastInst);
8938 return LastInst;
8939 }
8941 /// \brief Check if this slice can be merged with an expensive cross register
8942 /// bank copy. E.g.,
8943 /// i = load i32
8944 /// f = bitcast i32 i to float
8945 bool canMergeExpensiveCrossRegisterBankCopy() const {
8946 if (!Inst || !Inst->hasOneUse())
8947 return false;
8948 SDNode *Use = *Inst->use_begin();
8949 if (Use->getOpcode() != ISD::BITCAST)
8950 return false;
8951 assert(DAG && "Missing context");
8952 const TargetLowering &TLI = DAG->getTargetLoweringInfo();
8953 EVT ResVT = Use->getValueType(0);
8954 const TargetRegisterClass *ResRC = TLI.getRegClassFor(ResVT.getSimpleVT());
8955 const TargetRegisterClass *ArgRC =
8956 TLI.getRegClassFor(Use->getOperand(0).getValueType().getSimpleVT());
8957 if (ArgRC == ResRC || !TLI.isOperationLegal(ISD::LOAD, ResVT))
8958 return false;
8960 // At this point, we know that we perform a cross-register-bank copy.
8961 // Check if it is expensive.
8962 const TargetRegisterInfo *TRI = DAG->getSubtarget().getRegisterInfo();
8963 // Assume bitcasts are cheap, unless both register classes do not
8964 // explicitly share a common sub class.
8965 if (!TRI || TRI->getCommonSubClass(ArgRC, ResRC))
8966 return false;
8968 // Check if it will be merged with the load.
8969 // 1. Check the alignment constraint.
8970 unsigned RequiredAlignment = TLI.getDataLayout()->getABITypeAlignment(
8971 ResVT.getTypeForEVT(*DAG->getContext()));
8973 if (RequiredAlignment > getAlignment())
8974 return false;
8976 // 2. Check that the load is a legal operation for that type.
8977 if (!TLI.isOperationLegal(ISD::LOAD, ResVT))
8978 return false;
8980 // 3. Check that we do not have a zext in the way.
8981 if (Inst->getValueType(0) != getLoadedType())
8982 return false;
8984 return true;
8985 }
8986 };
8987 }
8989 /// \brief Check that all bits set in \p UsedBits form a dense region, i.e.,
8990 /// \p UsedBits looks like 0..0 1..1 0..0.
8991 static bool areUsedBitsDense(const APInt &UsedBits) {
8992 // If all the bits are one, this is dense!
8993 if (UsedBits.isAllOnesValue())
8994 return true;
8996 // Get rid of the unused bits on the right.
8997 APInt NarrowedUsedBits = UsedBits.lshr(UsedBits.countTrailingZeros());
8998 // Get rid of the unused bits on the left.
8999 if (NarrowedUsedBits.countLeadingZeros())
9000 NarrowedUsedBits = NarrowedUsedBits.trunc(NarrowedUsedBits.getActiveBits());
9001 // Check that the chunk of bits is completely used.
9002 return NarrowedUsedBits.isAllOnesValue();
9003 }
9005 /// \brief Check whether or not \p First and \p Second are next to each other
9006 /// in memory. This means that there is no hole between the bits loaded
9007 /// by \p First and the bits loaded by \p Second.
9008 static bool areSlicesNextToEachOther(const LoadedSlice &First,
9009 const LoadedSlice &Second) {
9010 assert(First.Origin == Second.Origin && First.Origin &&
9011 "Unable to match different memory origins.");
9012 APInt UsedBits = First.getUsedBits();
9013 assert((UsedBits & Second.getUsedBits()) == 0 &&
9014 "Slices are not supposed to overlap.");
9015 UsedBits |= Second.getUsedBits();
9016 return areUsedBitsDense(UsedBits);
9017 }
9019 /// \brief Adjust the \p GlobalLSCost according to the target
9020 /// paring capabilities and the layout of the slices.
9021 /// \pre \p GlobalLSCost should account for at least as many loads as
9022 /// there is in the slices in \p LoadedSlices.
9023 static void adjustCostForPairing(SmallVectorImpl<LoadedSlice> &LoadedSlices,
9024 LoadedSlice::Cost &GlobalLSCost) {
9025 unsigned NumberOfSlices = LoadedSlices.size();
9026 // If there is less than 2 elements, no pairing is possible.
9027 if (NumberOfSlices < 2)
9028 return;
9030 // Sort the slices so that elements that are likely to be next to each
9031 // other in memory are next to each other in the list.
9032 std::sort(LoadedSlices.begin(), LoadedSlices.end(),
9033 [](const LoadedSlice &LHS, const LoadedSlice &RHS) {
9034 assert(LHS.Origin == RHS.Origin && "Different bases not implemented.");
9035 return LHS.getOffsetFromBase() < RHS.getOffsetFromBase();
9036 });
9037 const TargetLowering &TLI = LoadedSlices[0].DAG->getTargetLoweringInfo();
9038 // First (resp. Second) is the first (resp. Second) potentially candidate
9039 // to be placed in a paired load.
9040 const LoadedSlice *First = nullptr;
9041 const LoadedSlice *Second = nullptr;
9042 for (unsigned CurrSlice = 0; CurrSlice < NumberOfSlices; ++CurrSlice,
9043 // Set the beginning of the pair.
9044 First = Second) {
9046 Second = &LoadedSlices[CurrSlice];
9048 // If First is NULL, it means we start a new pair.
9049 // Get to the next slice.
9050 if (!First)
9051 continue;
9053 EVT LoadedType = First->getLoadedType();
9055 // If the types of the slices are different, we cannot pair them.
9056 if (LoadedType != Second->getLoadedType())
9057 continue;
9059 // Check if the target supplies paired loads for this type.
9060 unsigned RequiredAlignment = 0;
9061 if (!TLI.hasPairedLoad(LoadedType, RequiredAlignment)) {
9062 // move to the next pair, this type is hopeless.
9063 Second = nullptr;
9064 continue;
9065 }
9066 // Check if we meet the alignment requirement.
9067 if (RequiredAlignment > First->getAlignment())
9068 continue;
9070 // Check that both loads are next to each other in memory.
9071 if (!areSlicesNextToEachOther(*First, *Second))
9072 continue;
9074 assert(GlobalLSCost.Loads > 0 && "We save more loads than we created!");
9075 --GlobalLSCost.Loads;
9076 // Move to the next pair.
9077 Second = nullptr;
9078 }
9079 }
9081 /// \brief Check the profitability of all involved LoadedSlice.
9082 /// Currently, it is considered profitable if there is exactly two
9083 /// involved slices (1) which are (2) next to each other in memory, and
9084 /// whose cost (\see LoadedSlice::Cost) is smaller than the original load (3).
9085 ///
9086 /// Note: The order of the elements in \p LoadedSlices may be modified, but not
9087 /// the elements themselves.
9088 ///
9089 /// FIXME: When the cost model will be mature enough, we can relax
9090 /// constraints (1) and (2).
9091 static bool isSlicingProfitable(SmallVectorImpl<LoadedSlice> &LoadedSlices,
9092 const APInt &UsedBits, bool ForCodeSize) {
9093 unsigned NumberOfSlices = LoadedSlices.size();
9094 if (StressLoadSlicing)
9095 return NumberOfSlices > 1;
9097 // Check (1).
9098 if (NumberOfSlices != 2)
9099 return false;
9101 // Check (2).
9102 if (!areUsedBitsDense(UsedBits))
9103 return false;
9105 // Check (3).
9106 LoadedSlice::Cost OrigCost(ForCodeSize), GlobalSlicingCost(ForCodeSize);
9107 // The original code has one big load.
9108 OrigCost.Loads = 1;
9109 for (unsigned CurrSlice = 0; CurrSlice < NumberOfSlices; ++CurrSlice) {
9110 const LoadedSlice &LS = LoadedSlices[CurrSlice];
9111 // Accumulate the cost of all the slices.
9112 LoadedSlice::Cost SliceCost(LS, ForCodeSize);
9113 GlobalSlicingCost += SliceCost;
9115 // Account as cost in the original configuration the gain obtained
9116 // with the current slices.
9117 OrigCost.addSliceGain(LS);
9118 }
9120 // If the target supports paired load, adjust the cost accordingly.
9121 adjustCostForPairing(LoadedSlices, GlobalSlicingCost);
9122 return OrigCost > GlobalSlicingCost;
9123 }
9125 /// \brief If the given load, \p LI, is used only by trunc or trunc(lshr)
9126 /// operations, split it in the various pieces being extracted.
9127 ///
9128 /// This sort of thing is introduced by SROA.
9129 /// This slicing takes care not to insert overlapping loads.
9130 /// \pre LI is a simple load (i.e., not an atomic or volatile load).
9131 bool DAGCombiner::SliceUpLoad(SDNode *N) {
9132 if (Level < AfterLegalizeDAG)
9133 return false;
9135 LoadSDNode *LD = cast<LoadSDNode>(N);
9136 if (LD->isVolatile() || !ISD::isNormalLoad(LD) ||
9137 !LD->getValueType(0).isInteger())
9138 return false;
9140 // Keep track of already used bits to detect overlapping values.
9141 // In that case, we will just abort the transformation.
9142 APInt UsedBits(LD->getValueSizeInBits(0), 0);
9144 SmallVector<LoadedSlice, 4> LoadedSlices;
9146 // Check if this load is used as several smaller chunks of bits.
9147 // Basically, look for uses in trunc or trunc(lshr) and record a new chain
9148 // of computation for each trunc.
9149 for (SDNode::use_iterator UI = LD->use_begin(), UIEnd = LD->use_end();
9150 UI != UIEnd; ++UI) {
9151 // Skip the uses of the chain.
9152 if (UI.getUse().getResNo() != 0)
9153 continue;
9155 SDNode *User = *UI;
9156 unsigned Shift = 0;
9158 // Check if this is a trunc(lshr).
9159 if (User->getOpcode() == ISD::SRL && User->hasOneUse() &&
9160 isa<ConstantSDNode>(User->getOperand(1))) {
9161 Shift = cast<ConstantSDNode>(User->getOperand(1))->getZExtValue();
9162 User = *User->use_begin();
9163 }
9165 // At this point, User is a Truncate, iff we encountered, trunc or
9166 // trunc(lshr).
9167 if (User->getOpcode() != ISD::TRUNCATE)
9168 return false;
9170 // The width of the type must be a power of 2 and greater than 8-bits.
9171 // Otherwise the load cannot be represented in LLVM IR.
9172 // Moreover, if we shifted with a non-8-bits multiple, the slice
9173 // will be across several bytes. We do not support that.
9174 unsigned Width = User->getValueSizeInBits(0);
9175 if (Width < 8 || !isPowerOf2_32(Width) || (Shift & 0x7))
9176 return 0;
9178 // Build the slice for this chain of computations.
9179 LoadedSlice LS(User, LD, Shift, &DAG);
9180 APInt CurrentUsedBits = LS.getUsedBits();
9182 // Check if this slice overlaps with another.
9183 if ((CurrentUsedBits & UsedBits) != 0)
9184 return false;
9185 // Update the bits used globally.
9186 UsedBits |= CurrentUsedBits;
9188 // Check if the new slice would be legal.
9189 if (!LS.isLegal())
9190 return false;
9192 // Record the slice.
9193 LoadedSlices.push_back(LS);
9194 }
9196 // Abort slicing if it does not seem to be profitable.
9197 if (!isSlicingProfitable(LoadedSlices, UsedBits, ForCodeSize))
9198 return false;
9200 ++SlicedLoads;
9202 // Rewrite each chain to use an independent load.
9203 // By construction, each chain can be represented by a unique load.
9205 // Prepare the argument for the new token factor for all the slices.
9206 SmallVector<SDValue, 8> ArgChains;
9207 for (SmallVectorImpl<LoadedSlice>::const_iterator
9208 LSIt = LoadedSlices.begin(),
9209 LSItEnd = LoadedSlices.end();
9210 LSIt != LSItEnd; ++LSIt) {
9211 SDValue SliceInst = LSIt->loadSlice();
9212 CombineTo(LSIt->Inst, SliceInst, true);
9213 if (SliceInst.getNode()->getOpcode() != ISD::LOAD)
9214 SliceInst = SliceInst.getOperand(0);
9215 assert(SliceInst->getOpcode() == ISD::LOAD &&
9216 "It takes more than a zext to get to the loaded slice!!");
9217 ArgChains.push_back(SliceInst.getValue(1));
9218 }
9220 SDValue Chain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other,
9221 ArgChains);
9222 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain);
9223 return true;
9224 }
9226 /// Check to see if V is (and load (ptr), imm), where the load is having
9227 /// specific bytes cleared out. If so, return the byte size being masked out
9228 /// and the shift amount.
9229 static std::pair<unsigned, unsigned>
9230 CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) {
9231 std::pair<unsigned, unsigned> Result(0, 0);
9233 // Check for the structure we're looking for.
9234 if (V->getOpcode() != ISD::AND ||
9235 !isa<ConstantSDNode>(V->getOperand(1)) ||
9236 !ISD::isNormalLoad(V->getOperand(0).getNode()))
9237 return Result;
9239 // Check the chain and pointer.
9240 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0));
9241 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer.
9243 // The store should be chained directly to the load or be an operand of a
9244 // tokenfactor.
9245 if (LD == Chain.getNode())
9246 ; // ok.
9247 else if (Chain->getOpcode() != ISD::TokenFactor)
9248 return Result; // Fail.
9249 else {
9250 bool isOk = false;
9251 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i)
9252 if (Chain->getOperand(i).getNode() == LD) {
9253 isOk = true;
9254 break;
9255 }
9256 if (!isOk) return Result;
9257 }
9259 // This only handles simple types.
9260 if (V.getValueType() != MVT::i16 &&
9261 V.getValueType() != MVT::i32 &&
9262 V.getValueType() != MVT::i64)
9263 return Result;
9265 // Check the constant mask. Invert it so that the bits being masked out are
9266 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits
9267 // follow the sign bit for uniformity.
9268 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue();
9269 unsigned NotMaskLZ = countLeadingZeros(NotMask);
9270 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte.
9271 unsigned NotMaskTZ = countTrailingZeros(NotMask);
9272 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte.
9273 if (NotMaskLZ == 64) return Result; // All zero mask.
9275 // See if we have a continuous run of bits. If so, we have 0*1+0*
9276 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64)
9277 return Result;
9279 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64.
9280 if (V.getValueType() != MVT::i64 && NotMaskLZ)
9281 NotMaskLZ -= 64-V.getValueSizeInBits();
9283 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8;
9284 switch (MaskedBytes) {
9285 case 1:
9286 case 2:
9287 case 4: break;
9288 default: return Result; // All one mask, or 5-byte mask.
9289 }
9291 // Verify that the first bit starts at a multiple of mask so that the access
9292 // is aligned the same as the access width.
9293 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result;
9295 Result.first = MaskedBytes;
9296 Result.second = NotMaskTZ/8;
9297 return Result;
9298 }
9301 /// Check to see if IVal is something that provides a value as specified by
9302 /// MaskInfo. If so, replace the specified store with a narrower store of
9303 /// truncated IVal.
9304 static SDNode *
9305 ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo,
9306 SDValue IVal, StoreSDNode *St,
9307 DAGCombiner *DC) {
9308 unsigned NumBytes = MaskInfo.first;
9309 unsigned ByteShift = MaskInfo.second;
9310 SelectionDAG &DAG = DC->getDAG();
9312 // Check to see if IVal is all zeros in the part being masked in by the 'or'
9313 // that uses this. If not, this is not a replacement.
9314 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(),
9315 ByteShift*8, (ByteShift+NumBytes)*8);
9316 if (!DAG.MaskedValueIsZero(IVal, Mask)) return nullptr;
9318 // Check that it is legal on the target to do this. It is legal if the new
9319 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type
9320 // legalization.
9321 MVT VT = MVT::getIntegerVT(NumBytes*8);
9322 if (!DC->isTypeLegal(VT))
9323 return nullptr;
9325 // Okay, we can do this! Replace the 'St' store with a store of IVal that is
9326 // shifted by ByteShift and truncated down to NumBytes.
9327 if (ByteShift)
9328 IVal = DAG.getNode(ISD::SRL, SDLoc(IVal), IVal.getValueType(), IVal,
9329 DAG.getConstant(ByteShift*8,
9330 DC->getShiftAmountTy(IVal.getValueType())));
9332 // Figure out the offset for the store and the alignment of the access.
9333 unsigned StOffset;
9334 unsigned NewAlign = St->getAlignment();
9336 if (DAG.getTargetLoweringInfo().isLittleEndian())
9337 StOffset = ByteShift;
9338 else
9339 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes;
9341 SDValue Ptr = St->getBasePtr();
9342 if (StOffset) {
9343 Ptr = DAG.getNode(ISD::ADD, SDLoc(IVal), Ptr.getValueType(),
9344 Ptr, DAG.getConstant(StOffset, Ptr.getValueType()));
9345 NewAlign = MinAlign(NewAlign, StOffset);
9346 }
9348 // Truncate down to the new size.
9349 IVal = DAG.getNode(ISD::TRUNCATE, SDLoc(IVal), VT, IVal);
9351 ++OpsNarrowed;
9352 return DAG.getStore(St->getChain(), SDLoc(St), IVal, Ptr,
9353 St->getPointerInfo().getWithOffset(StOffset),
9354 false, false, NewAlign).getNode();
9355 }
9358 /// Look for sequence of load / op / store where op is one of 'or', 'xor', and
9359 /// 'and' of immediates. If 'op' is only touching some of the loaded bits, try
9360 /// narrowing the load and store if it would end up being a win for performance
9361 /// or code size.
9362 SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
9363 StoreSDNode *ST = cast<StoreSDNode>(N);
9364 if (ST->isVolatile())
9365 return SDValue();
9367 SDValue Chain = ST->getChain();
9368 SDValue Value = ST->getValue();
9369 SDValue Ptr = ST->getBasePtr();
9370 EVT VT = Value.getValueType();
9372 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse())
9373 return SDValue();
9375 unsigned Opc = Value.getOpcode();
9377 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst
9378 // is a byte mask indicating a consecutive number of bytes, check to see if
9379 // Y is known to provide just those bytes. If so, we try to replace the
9380 // load + replace + store sequence with a single (narrower) store, which makes
9381 // the load dead.
9382 if (Opc == ISD::OR) {
9383 std::pair<unsigned, unsigned> MaskedLoad;
9384 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain);
9385 if (MaskedLoad.first)
9386 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
9387 Value.getOperand(1), ST,this))
9388 return SDValue(NewST, 0);
9390 // Or is commutative, so try swapping X and Y.
9391 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain);
9392 if (MaskedLoad.first)
9393 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
9394 Value.getOperand(0), ST,this))
9395 return SDValue(NewST, 0);
9396 }
9398 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) ||
9399 Value.getOperand(1).getOpcode() != ISD::Constant)
9400 return SDValue();
9402 SDValue N0 = Value.getOperand(0);
9403 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
9404 Chain == SDValue(N0.getNode(), 1)) {
9405 LoadSDNode *LD = cast<LoadSDNode>(N0);
9406 if (LD->getBasePtr() != Ptr ||
9407 LD->getPointerInfo().getAddrSpace() !=
9408 ST->getPointerInfo().getAddrSpace())
9409 return SDValue();
9411 // Find the type to narrow it the load / op / store to.
9412 SDValue N1 = Value.getOperand(1);
9413 unsigned BitWidth = N1.getValueSizeInBits();
9414 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue();
9415 if (Opc == ISD::AND)
9416 Imm ^= APInt::getAllOnesValue(BitWidth);
9417 if (Imm == 0 || Imm.isAllOnesValue())
9418 return SDValue();
9419 unsigned ShAmt = Imm.countTrailingZeros();
9420 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
9421 unsigned NewBW = NextPowerOf2(MSB - ShAmt);
9422 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
9423 while (NewBW < BitWidth &&
9424 !(TLI.isOperationLegalOrCustom(Opc, NewVT) &&
9425 TLI.isNarrowingProfitable(VT, NewVT))) {
9426 NewBW = NextPowerOf2(NewBW);
9427 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
9428 }
9429 if (NewBW >= BitWidth)
9430 return SDValue();
9432 // If the lsb changed does not start at the type bitwidth boundary,
9433 // start at the previous one.
9434 if (ShAmt % NewBW)
9435 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW;
9436 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt,
9437 std::min(BitWidth, ShAmt + NewBW));
9438 if ((Imm & Mask) == Imm) {
9439 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW);
9440 if (Opc == ISD::AND)
9441 NewImm ^= APInt::getAllOnesValue(NewBW);
9442 uint64_t PtrOff = ShAmt / 8;
9443 // For big endian targets, we need to adjust the offset to the pointer to
9444 // load the correct bytes.
9445 if (TLI.isBigEndian())
9446 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff;
9448 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff);
9449 Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext());
9450 if (NewAlign < TLI.getDataLayout()->getABITypeAlignment(NewVTTy))
9451 return SDValue();
9453 SDValue NewPtr = DAG.getNode(ISD::ADD, SDLoc(LD),
9454 Ptr.getValueType(), Ptr,
9455 DAG.getConstant(PtrOff, Ptr.getValueType()));
9456 SDValue NewLD = DAG.getLoad(NewVT, SDLoc(N0),
9457 LD->getChain(), NewPtr,
9458 LD->getPointerInfo().getWithOffset(PtrOff),
9459 LD->isVolatile(), LD->isNonTemporal(),
9460 LD->isInvariant(), NewAlign,
9461 LD->getAAInfo());
9462 SDValue NewVal = DAG.getNode(Opc, SDLoc(Value), NewVT, NewLD,
9463 DAG.getConstant(NewImm, NewVT));
9464 SDValue NewST = DAG.getStore(Chain, SDLoc(N),
9465 NewVal, NewPtr,
9466 ST->getPointerInfo().getWithOffset(PtrOff),
9467 false, false, NewAlign);
9469 AddToWorklist(NewPtr.getNode());
9470 AddToWorklist(NewLD.getNode());
9471 AddToWorklist(NewVal.getNode());
9472 WorklistRemover DeadNodes(*this);
9473 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1));
9474 ++OpsNarrowed;
9475 return NewST;
9476 }
9477 }
9479 return SDValue();
9480 }
9482 /// For a given floating point load / store pair, if the load value isn't used
9483 /// by any other operations, then consider transforming the pair to integer
9484 /// load / store operations if the target deems the transformation profitable.
9485 SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) {
9486 StoreSDNode *ST = cast<StoreSDNode>(N);
9487 SDValue Chain = ST->getChain();
9488 SDValue Value = ST->getValue();
9489 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) &&
9490 Value.hasOneUse() &&
9491 Chain == SDValue(Value.getNode(), 1)) {
9492 LoadSDNode *LD = cast<LoadSDNode>(Value);
9493 EVT VT = LD->getMemoryVT();
9494 if (!VT.isFloatingPoint() ||
9495 VT != ST->getMemoryVT() ||
9496 LD->isNonTemporal() ||
9497 ST->isNonTemporal() ||
9498 LD->getPointerInfo().getAddrSpace() != 0 ||
9499 ST->getPointerInfo().getAddrSpace() != 0)
9500 return SDValue();
9502 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
9503 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) ||
9504 !TLI.isOperationLegal(ISD::STORE, IntVT) ||
9505 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) ||
9506 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT))
9507 return SDValue();
9509 unsigned LDAlign = LD->getAlignment();
9510 unsigned STAlign = ST->getAlignment();
9511 Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext());
9512 unsigned ABIAlign = TLI.getDataLayout()->getABITypeAlignment(IntVTTy);
9513 if (LDAlign < ABIAlign || STAlign < ABIAlign)
9514 return SDValue();
9516 SDValue NewLD = DAG.getLoad(IntVT, SDLoc(Value),
9517 LD->getChain(), LD->getBasePtr(),
9518 LD->getPointerInfo(),
9519 false, false, false, LDAlign);
9521 SDValue NewST = DAG.getStore(NewLD.getValue(1), SDLoc(N),
9522 NewLD, ST->getBasePtr(),
9523 ST->getPointerInfo(),
9524 false, false, STAlign);
9526 AddToWorklist(NewLD.getNode());
9527 AddToWorklist(NewST.getNode());
9528 WorklistRemover DeadNodes(*this);
9529 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1));
9530 ++LdStFP2Int;
9531 return NewST;
9532 }
9534 return SDValue();
9535 }
9537 /// Helper struct to parse and store a memory address as base + index + offset.
9538 /// We ignore sign extensions when it is safe to do so.
9539 /// The following two expressions are not equivalent. To differentiate we need
9540 /// to store whether there was a sign extension involved in the index
9541 /// computation.
9542 /// (load (i64 add (i64 copyfromreg %c)
9543 /// (i64 signextend (add (i8 load %index)
9544 /// (i8 1))))
9545 /// vs
9546 ///
9547 /// (load (i64 add (i64 copyfromreg %c)
9548 /// (i64 signextend (i32 add (i32 signextend (i8 load %index))
9549 /// (i32 1)))))
9550 struct BaseIndexOffset {
9551 SDValue Base;
9552 SDValue Index;
9553 int64_t Offset;
9554 bool IsIndexSignExt;
9556 BaseIndexOffset() : Offset(0), IsIndexSignExt(false) {}
9558 BaseIndexOffset(SDValue Base, SDValue Index, int64_t Offset,
9559 bool IsIndexSignExt) :
9560 Base(Base), Index(Index), Offset(Offset), IsIndexSignExt(IsIndexSignExt) {}
9562 bool equalBaseIndex(const BaseIndexOffset &Other) {
9563 return Other.Base == Base && Other.Index == Index &&
9564 Other.IsIndexSignExt == IsIndexSignExt;
9565 }
9567 /// Parses tree in Ptr for base, index, offset addresses.
9568 static BaseIndexOffset match(SDValue Ptr) {
9569 bool IsIndexSignExt = false;
9571 // We only can pattern match BASE + INDEX + OFFSET. If Ptr is not an ADD
9572 // instruction, then it could be just the BASE or everything else we don't
9573 // know how to handle. Just use Ptr as BASE and give up.
9574 if (Ptr->getOpcode() != ISD::ADD)
9575 return BaseIndexOffset(Ptr, SDValue(), 0, IsIndexSignExt);
9577 // We know that we have at least an ADD instruction. Try to pattern match
9578 // the simple case of BASE + OFFSET.
9579 if (isa<ConstantSDNode>(Ptr->getOperand(1))) {
9580 int64_t Offset = cast<ConstantSDNode>(Ptr->getOperand(1))->getSExtValue();
9581 return BaseIndexOffset(Ptr->getOperand(0), SDValue(), Offset,
9582 IsIndexSignExt);
9583 }
9585 // Inside a loop the current BASE pointer is calculated using an ADD and a
9586 // MUL instruction. In this case Ptr is the actual BASE pointer.
9587 // (i64 add (i64 %array_ptr)
9588 // (i64 mul (i64 %induction_var)
9589 // (i64 %element_size)))
9590 if (Ptr->getOperand(1)->getOpcode() == ISD::MUL)
9591 return BaseIndexOffset(Ptr, SDValue(), 0, IsIndexSignExt);
9593 // Look at Base + Index + Offset cases.
9594 SDValue Base = Ptr->getOperand(0);
9595 SDValue IndexOffset = Ptr->getOperand(1);
9597 // Skip signextends.
9598 if (IndexOffset->getOpcode() == ISD::SIGN_EXTEND) {
9599 IndexOffset = IndexOffset->getOperand(0);
9600 IsIndexSignExt = true;
9601 }
9603 // Either the case of Base + Index (no offset) or something else.
9604 if (IndexOffset->getOpcode() != ISD::ADD)
9605 return BaseIndexOffset(Base, IndexOffset, 0, IsIndexSignExt);
9607 // Now we have the case of Base + Index + offset.
9608 SDValue Index = IndexOffset->getOperand(0);
9609 SDValue Offset = IndexOffset->getOperand(1);
9611 if (!isa<ConstantSDNode>(Offset))
9612 return BaseIndexOffset(Ptr, SDValue(), 0, IsIndexSignExt);
9614 // Ignore signextends.
9615 if (Index->getOpcode() == ISD::SIGN_EXTEND) {
9616 Index = Index->getOperand(0);
9617 IsIndexSignExt = true;
9618 } else IsIndexSignExt = false;
9620 int64_t Off = cast<ConstantSDNode>(Offset)->getSExtValue();
9621 return BaseIndexOffset(Base, Index, Off, IsIndexSignExt);
9622 }
9623 };
9625 /// Holds a pointer to an LSBaseSDNode as well as information on where it
9626 /// is located in a sequence of memory operations connected by a chain.
9627 struct MemOpLink {
9628 MemOpLink (LSBaseSDNode *N, int64_t Offset, unsigned Seq):
9629 MemNode(N), OffsetFromBase(Offset), SequenceNum(Seq) { }
9630 // Ptr to the mem node.
9631 LSBaseSDNode *MemNode;
9632 // Offset from the base ptr.
9633 int64_t OffsetFromBase;
9634 // What is the sequence number of this mem node.
9635 // Lowest mem operand in the DAG starts at zero.
9636 unsigned SequenceNum;
9637 };
9639 bool DAGCombiner::MergeConsecutiveStores(StoreSDNode* St) {
9640 EVT MemVT = St->getMemoryVT();
9641 int64_t ElementSizeBytes = MemVT.getSizeInBits()/8;
9642 bool NoVectors = DAG.getMachineFunction().getFunction()->getAttributes().
9643 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
9645 // Don't merge vectors into wider inputs.
9646 if (MemVT.isVector() || !MemVT.isSimple())
9647 return false;
9649 // Perform an early exit check. Do not bother looking at stored values that
9650 // are not constants or loads.
9651 SDValue StoredVal = St->getValue();
9652 bool IsLoadSrc = isa<LoadSDNode>(StoredVal);
9653 if (!isa<ConstantSDNode>(StoredVal) && !isa<ConstantFPSDNode>(StoredVal) &&
9654 !IsLoadSrc)
9655 return false;
9657 // Only look at ends of store sequences.
9658 SDValue Chain = SDValue(St, 0);
9659 if (Chain->hasOneUse() && Chain->use_begin()->getOpcode() == ISD::STORE)
9660 return false;
9662 // This holds the base pointer, index, and the offset in bytes from the base
9663 // pointer.
9664 BaseIndexOffset BasePtr = BaseIndexOffset::match(St->getBasePtr());
9666 // We must have a base and an offset.
9667 if (!BasePtr.Base.getNode())
9668 return false;
9670 // Do not handle stores to undef base pointers.
9671 if (BasePtr.Base.getOpcode() == ISD::UNDEF)
9672 return false;
9674 // Save the LoadSDNodes that we find in the chain.
9675 // We need to make sure that these nodes do not interfere with
9676 // any of the store nodes.
9677 SmallVector<LSBaseSDNode*, 8> AliasLoadNodes;
9679 // Save the StoreSDNodes that we find in the chain.
9680 SmallVector<MemOpLink, 8> StoreNodes;
9682 // Walk up the chain and look for nodes with offsets from the same
9683 // base pointer. Stop when reaching an instruction with a different kind
9684 // or instruction which has a different base pointer.
9685 unsigned Seq = 0;
9686 StoreSDNode *Index = St;
9687 while (Index) {
9688 // If the chain has more than one use, then we can't reorder the mem ops.
9689 if (Index != St && !SDValue(Index, 0)->hasOneUse())
9690 break;
9692 // Find the base pointer and offset for this memory node.
9693 BaseIndexOffset Ptr = BaseIndexOffset::match(Index->getBasePtr());
9695 // Check that the base pointer is the same as the original one.
9696 if (!Ptr.equalBaseIndex(BasePtr))
9697 break;
9699 // Check that the alignment is the same.
9700 if (Index->getAlignment() != St->getAlignment())
9701 break;
9703 // The memory operands must not be volatile.
9704 if (Index->isVolatile() || Index->isIndexed())
9705 break;
9707 // No truncation.
9708 if (StoreSDNode *St = dyn_cast<StoreSDNode>(Index))
9709 if (St->isTruncatingStore())
9710 break;
9712 // The stored memory type must be the same.
9713 if (Index->getMemoryVT() != MemVT)
9714 break;
9716 // We do not allow unaligned stores because we want to prevent overriding
9717 // stores.
9718 if (Index->getAlignment()*8 != MemVT.getSizeInBits())
9719 break;
9721 // We found a potential memory operand to merge.
9722 StoreNodes.push_back(MemOpLink(Index, Ptr.Offset, Seq++));
9724 // Find the next memory operand in the chain. If the next operand in the
9725 // chain is a store then move up and continue the scan with the next
9726 // memory operand. If the next operand is a load save it and use alias
9727 // information to check if it interferes with anything.
9728 SDNode *NextInChain = Index->getChain().getNode();
9729 while (1) {
9730 if (StoreSDNode *STn = dyn_cast<StoreSDNode>(NextInChain)) {
9731 // We found a store node. Use it for the next iteration.
9732 Index = STn;
9733 break;
9734 } else if (LoadSDNode *Ldn = dyn_cast<LoadSDNode>(NextInChain)) {
9735 if (Ldn->isVolatile()) {
9736 Index = nullptr;
9737 break;
9738 }
9740 // Save the load node for later. Continue the scan.
9741 AliasLoadNodes.push_back(Ldn);
9742 NextInChain = Ldn->getChain().getNode();
9743 continue;
9744 } else {
9745 Index = nullptr;
9746 break;
9747 }
9748 }
9749 }
9751 // Check if there is anything to merge.
9752 if (StoreNodes.size() < 2)
9753 return false;
9755 // Sort the memory operands according to their distance from the base pointer.
9756 std::sort(StoreNodes.begin(), StoreNodes.end(),
9757 [](MemOpLink LHS, MemOpLink RHS) {
9758 return LHS.OffsetFromBase < RHS.OffsetFromBase ||
9759 (LHS.OffsetFromBase == RHS.OffsetFromBase &&
9760 LHS.SequenceNum > RHS.SequenceNum);
9761 });
9763 // Scan the memory operations on the chain and find the first non-consecutive
9764 // store memory address.
9765 unsigned LastConsecutiveStore = 0;
9766 int64_t StartAddress = StoreNodes[0].OffsetFromBase;
9767 for (unsigned i = 0, e = StoreNodes.size(); i < e; ++i) {
9769 // Check that the addresses are consecutive starting from the second
9770 // element in the list of stores.
9771 if (i > 0) {
9772 int64_t CurrAddress = StoreNodes[i].OffsetFromBase;
9773 if (CurrAddress - StartAddress != (ElementSizeBytes * i))
9774 break;
9775 }
9777 bool Alias = false;
9778 // Check if this store interferes with any of the loads that we found.
9779 for (unsigned ld = 0, lde = AliasLoadNodes.size(); ld < lde; ++ld)
9780 if (isAlias(AliasLoadNodes[ld], StoreNodes[i].MemNode)) {
9781 Alias = true;
9782 break;
9783 }
9784 // We found a load that alias with this store. Stop the sequence.
9785 if (Alias)
9786 break;
9788 // Mark this node as useful.
9789 LastConsecutiveStore = i;
9790 }
9792 // The node with the lowest store address.
9793 LSBaseSDNode *FirstInChain = StoreNodes[0].MemNode;
9795 // Store the constants into memory as one consecutive store.
9796 if (!IsLoadSrc) {
9797 unsigned LastLegalType = 0;
9798 unsigned LastLegalVectorType = 0;
9799 bool NonZero = false;
9800 for (unsigned i=0; i<LastConsecutiveStore+1; ++i) {
9801 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
9802 SDValue StoredVal = St->getValue();
9804 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(StoredVal)) {
9805 NonZero |= !C->isNullValue();
9806 } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(StoredVal)) {
9807 NonZero |= !C->getConstantFPValue()->isNullValue();
9808 } else {
9809 // Non-constant.
9810 break;
9811 }
9813 // Find a legal type for the constant store.
9814 unsigned StoreBW = (i+1) * ElementSizeBytes * 8;
9815 EVT StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
9816 if (TLI.isTypeLegal(StoreTy))
9817 LastLegalType = i+1;
9818 // Or check whether a truncstore is legal.
9819 else if (TLI.getTypeAction(*DAG.getContext(), StoreTy) ==
9820 TargetLowering::TypePromoteInteger) {
9821 EVT LegalizedStoredValueTy =
9822 TLI.getTypeToTransformTo(*DAG.getContext(), StoredVal.getValueType());
9823 if (TLI.isTruncStoreLegal(LegalizedStoredValueTy, StoreTy))
9824 LastLegalType = i+1;
9825 }
9827 // Find a legal type for the vector store.
9828 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT, i+1);
9829 if (TLI.isTypeLegal(Ty))
9830 LastLegalVectorType = i + 1;
9831 }
9833 // We only use vectors if the constant is known to be zero and the
9834 // function is not marked with the noimplicitfloat attribute.
9835 if (NonZero || NoVectors)
9836 LastLegalVectorType = 0;
9838 // Check if we found a legal integer type to store.
9839 if (LastLegalType == 0 && LastLegalVectorType == 0)
9840 return false;
9842 bool UseVector = (LastLegalVectorType > LastLegalType) && !NoVectors;
9843 unsigned NumElem = UseVector ? LastLegalVectorType : LastLegalType;
9845 // Make sure we have something to merge.
9846 if (NumElem < 2)
9847 return false;
9849 unsigned EarliestNodeUsed = 0;
9850 for (unsigned i=0; i < NumElem; ++i) {
9851 // Find a chain for the new wide-store operand. Notice that some
9852 // of the store nodes that we found may not be selected for inclusion
9853 // in the wide store. The chain we use needs to be the chain of the
9854 // earliest store node which is *used* and replaced by the wide store.
9855 if (StoreNodes[i].SequenceNum > StoreNodes[EarliestNodeUsed].SequenceNum)
9856 EarliestNodeUsed = i;
9857 }
9859 // The earliest Node in the DAG.
9860 LSBaseSDNode *EarliestOp = StoreNodes[EarliestNodeUsed].MemNode;
9861 SDLoc DL(StoreNodes[0].MemNode);
9863 SDValue StoredVal;
9864 if (UseVector) {
9865 // Find a legal type for the vector store.
9866 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT, NumElem);
9867 assert(TLI.isTypeLegal(Ty) && "Illegal vector store");
9868 StoredVal = DAG.getConstant(0, Ty);
9869 } else {
9870 unsigned StoreBW = NumElem * ElementSizeBytes * 8;
9871 APInt StoreInt(StoreBW, 0);
9873 // Construct a single integer constant which is made of the smaller
9874 // constant inputs.
9875 bool IsLE = TLI.isLittleEndian();
9876 for (unsigned i = 0; i < NumElem ; ++i) {
9877 unsigned Idx = IsLE ?(NumElem - 1 - i) : i;
9878 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[Idx].MemNode);
9879 SDValue Val = St->getValue();
9880 StoreInt<<=ElementSizeBytes*8;
9881 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val)) {
9882 StoreInt|=C->getAPIntValue().zext(StoreBW);
9883 } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Val)) {
9884 StoreInt|= C->getValueAPF().bitcastToAPInt().zext(StoreBW);
9885 } else {
9886 llvm_unreachable("Invalid constant element type");
9887 }
9888 }
9890 // Create the new Load and Store operations.
9891 EVT StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
9892 StoredVal = DAG.getConstant(StoreInt, StoreTy);
9893 }
9895 SDValue NewStore = DAG.getStore(EarliestOp->getChain(), DL, StoredVal,
9896 FirstInChain->getBasePtr(),
9897 FirstInChain->getPointerInfo(),
9898 false, false,
9899 FirstInChain->getAlignment());
9901 // Replace the first store with the new store
9902 CombineTo(EarliestOp, NewStore);
9903 // Erase all other stores.
9904 for (unsigned i = 0; i < NumElem ; ++i) {
9905 if (StoreNodes[i].MemNode == EarliestOp)
9906 continue;
9907 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
9908 // ReplaceAllUsesWith will replace all uses that existed when it was
9909 // called, but graph optimizations may cause new ones to appear. For
9910 // example, the case in pr14333 looks like
9911 //
9912 // St's chain -> St -> another store -> X
9913 //
9914 // And the only difference from St to the other store is the chain.
9915 // When we change it's chain to be St's chain they become identical,
9916 // get CSEed and the net result is that X is now a use of St.
9917 // Since we know that St is redundant, just iterate.
9918 while (!St->use_empty())
9919 DAG.ReplaceAllUsesWith(SDValue(St, 0), St->getChain());
9920 deleteAndRecombine(St);
9921 }
9923 return true;
9924 }
9926 // Below we handle the case of multiple consecutive stores that
9927 // come from multiple consecutive loads. We merge them into a single
9928 // wide load and a single wide store.
9930 // Look for load nodes which are used by the stored values.
9931 SmallVector<MemOpLink, 8> LoadNodes;
9933 // Find acceptable loads. Loads need to have the same chain (token factor),
9934 // must not be zext, volatile, indexed, and they must be consecutive.
9935 BaseIndexOffset LdBasePtr;
9936 for (unsigned i=0; i<LastConsecutiveStore+1; ++i) {
9937 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
9938 LoadSDNode *Ld = dyn_cast<LoadSDNode>(St->getValue());
9939 if (!Ld) break;
9941 // Loads must only have one use.
9942 if (!Ld->hasNUsesOfValue(1, 0))
9943 break;
9945 // Check that the alignment is the same as the stores.
9946 if (Ld->getAlignment() != St->getAlignment())
9947 break;
9949 // The memory operands must not be volatile.
9950 if (Ld->isVolatile() || Ld->isIndexed())
9951 break;
9953 // We do not accept ext loads.
9954 if (Ld->getExtensionType() != ISD::NON_EXTLOAD)
9955 break;
9957 // The stored memory type must be the same.
9958 if (Ld->getMemoryVT() != MemVT)
9959 break;
9961 BaseIndexOffset LdPtr = BaseIndexOffset::match(Ld->getBasePtr());
9962 // If this is not the first ptr that we check.
9963 if (LdBasePtr.Base.getNode()) {
9964 // The base ptr must be the same.
9965 if (!LdPtr.equalBaseIndex(LdBasePtr))
9966 break;
9967 } else {
9968 // Check that all other base pointers are the same as this one.
9969 LdBasePtr = LdPtr;
9970 }
9972 // We found a potential memory operand to merge.
9973 LoadNodes.push_back(MemOpLink(Ld, LdPtr.Offset, 0));
9974 }
9976 if (LoadNodes.size() < 2)
9977 return false;
9979 // If we have load/store pair instructions and we only have two values,
9980 // don't bother.
9981 unsigned RequiredAlignment;
9982 if (LoadNodes.size() == 2 && TLI.hasPairedLoad(MemVT, RequiredAlignment) &&
9983 St->getAlignment() >= RequiredAlignment)
9984 return false;
9986 // Scan the memory operations on the chain and find the first non-consecutive
9987 // load memory address. These variables hold the index in the store node
9988 // array.
9989 unsigned LastConsecutiveLoad = 0;
9990 // This variable refers to the size and not index in the array.
9991 unsigned LastLegalVectorType = 0;
9992 unsigned LastLegalIntegerType = 0;
9993 StartAddress = LoadNodes[0].OffsetFromBase;
9994 SDValue FirstChain = LoadNodes[0].MemNode->getChain();
9995 for (unsigned i = 1; i < LoadNodes.size(); ++i) {
9996 // All loads much share the same chain.
9997 if (LoadNodes[i].MemNode->getChain() != FirstChain)
9998 break;
10000 int64_t CurrAddress = LoadNodes[i].OffsetFromBase;
10001 if (CurrAddress - StartAddress != (ElementSizeBytes * i))
10002 break;
10003 LastConsecutiveLoad = i;
10005 // Find a legal type for the vector store.
10006 EVT StoreTy = EVT::getVectorVT(*DAG.getContext(), MemVT, i+1);
10007 if (TLI.isTypeLegal(StoreTy))
10008 LastLegalVectorType = i + 1;
10010 // Find a legal type for the integer store.
10011 unsigned StoreBW = (i+1) * ElementSizeBytes * 8;
10012 StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
10013 if (TLI.isTypeLegal(StoreTy))
10014 LastLegalIntegerType = i + 1;
10015 // Or check whether a truncstore and extload is legal.
10016 else if (TLI.getTypeAction(*DAG.getContext(), StoreTy) ==
10017 TargetLowering::TypePromoteInteger) {
10018 EVT LegalizedStoredValueTy =
10019 TLI.getTypeToTransformTo(*DAG.getContext(), StoreTy);
10020 if (TLI.isTruncStoreLegal(LegalizedStoredValueTy, StoreTy) &&
10021 TLI.isLoadExtLegal(ISD::ZEXTLOAD, LegalizedStoredValueTy, StoreTy) &&
10022 TLI.isLoadExtLegal(ISD::SEXTLOAD, LegalizedStoredValueTy, StoreTy) &&
10023 TLI.isLoadExtLegal(ISD::EXTLOAD, LegalizedStoredValueTy, StoreTy))
10024 LastLegalIntegerType = i+1;
10025 }
10026 }
10028 // Only use vector types if the vector type is larger than the integer type.
10029 // If they are the same, use integers.
10030 bool UseVectorTy = LastLegalVectorType > LastLegalIntegerType && !NoVectors;
10031 unsigned LastLegalType = std::max(LastLegalVectorType, LastLegalIntegerType);
10033 // We add +1 here because the LastXXX variables refer to location while
10034 // the NumElem refers to array/index size.
10035 unsigned NumElem = std::min(LastConsecutiveStore, LastConsecutiveLoad) + 1;
10036 NumElem = std::min(LastLegalType, NumElem);
10038 if (NumElem < 2)
10039 return false;
10041 // The earliest Node in the DAG.
10042 unsigned EarliestNodeUsed = 0;
10043 LSBaseSDNode *EarliestOp = StoreNodes[EarliestNodeUsed].MemNode;
10044 for (unsigned i=1; i<NumElem; ++i) {
10045 // Find a chain for the new wide-store operand. Notice that some
10046 // of the store nodes that we found may not be selected for inclusion
10047 // in the wide store. The chain we use needs to be the chain of the
10048 // earliest store node which is *used* and replaced by the wide store.
10049 if (StoreNodes[i].SequenceNum > StoreNodes[EarliestNodeUsed].SequenceNum)
10050 EarliestNodeUsed = i;
10051 }
10053 // Find if it is better to use vectors or integers to load and store
10054 // to memory.
10055 EVT JointMemOpVT;
10056 if (UseVectorTy) {
10057 JointMemOpVT = EVT::getVectorVT(*DAG.getContext(), MemVT, NumElem);
10058 } else {
10059 unsigned StoreBW = NumElem * ElementSizeBytes * 8;
10060 JointMemOpVT = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
10061 }
10063 SDLoc LoadDL(LoadNodes[0].MemNode);
10064 SDLoc StoreDL(StoreNodes[0].MemNode);
10066 LoadSDNode *FirstLoad = cast<LoadSDNode>(LoadNodes[0].MemNode);
10067 SDValue NewLoad = DAG.getLoad(JointMemOpVT, LoadDL,
10068 FirstLoad->getChain(),
10069 FirstLoad->getBasePtr(),
10070 FirstLoad->getPointerInfo(),
10071 false, false, false,
10072 FirstLoad->getAlignment());
10074 SDValue NewStore = DAG.getStore(EarliestOp->getChain(), StoreDL, NewLoad,
10075 FirstInChain->getBasePtr(),
10076 FirstInChain->getPointerInfo(), false, false,
10077 FirstInChain->getAlignment());
10079 // Replace one of the loads with the new load.
10080 LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[0].MemNode);
10081 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1),
10082 SDValue(NewLoad.getNode(), 1));
10084 // Remove the rest of the load chains.
10085 for (unsigned i = 1; i < NumElem ; ++i) {
10086 // Replace all chain users of the old load nodes with the chain of the new
10087 // load node.
10088 LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[i].MemNode);
10089 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Ld->getChain());
10090 }
10092 // Replace the first store with the new store.
10093 CombineTo(EarliestOp, NewStore);
10094 // Erase all other stores.
10095 for (unsigned i = 0; i < NumElem ; ++i) {
10096 // Remove all Store nodes.
10097 if (StoreNodes[i].MemNode == EarliestOp)
10098 continue;
10099 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
10100 DAG.ReplaceAllUsesOfValueWith(SDValue(St, 0), St->getChain());
10101 deleteAndRecombine(St);
10102 }
10104 return true;
10105 }
10107 SDValue DAGCombiner::visitSTORE(SDNode *N) {
10108 StoreSDNode *ST = cast<StoreSDNode>(N);
10109 SDValue Chain = ST->getChain();
10110 SDValue Value = ST->getValue();
10111 SDValue Ptr = ST->getBasePtr();
10113 // If this is a store of a bit convert, store the input value if the
10114 // resultant store does not need a higher alignment than the original.
10115 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() &&
10116 ST->isUnindexed()) {
10117 unsigned OrigAlign = ST->getAlignment();
10118 EVT SVT = Value.getOperand(0).getValueType();
10119 unsigned Align = TLI.getDataLayout()->
10120 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext()));
10121 if (Align <= OrigAlign &&
10122 ((!LegalOperations && !ST->isVolatile()) ||
10123 TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
10124 return DAG.getStore(Chain, SDLoc(N), Value.getOperand(0),
10125 Ptr, ST->getPointerInfo(), ST->isVolatile(),
10126 ST->isNonTemporal(), OrigAlign,
10127 ST->getAAInfo());
10128 }
10130 // Turn 'store undef, Ptr' -> nothing.
10131 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed())
10132 return Chain;
10134 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
10135 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
10136 // NOTE: If the original store is volatile, this transform must not increase
10137 // the number of stores. For example, on x86-32 an f64 can be stored in one
10138 // processor operation but an i64 (which is not legal) requires two. So the
10139 // transform should not be done in this case.
10140 if (Value.getOpcode() != ISD::TargetConstantFP) {
10141 SDValue Tmp;
10142 switch (CFP->getSimpleValueType(0).SimpleTy) {
10143 default: llvm_unreachable("Unknown FP type");
10144 case MVT::f16: // We don't do this for these yet.
10145 case MVT::f80:
10146 case MVT::f128:
10147 case MVT::ppcf128:
10148 break;
10149 case MVT::f32:
10150 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) ||
10151 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
10152 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
10153 bitcastToAPInt().getZExtValue(), MVT::i32);
10154 return DAG.getStore(Chain, SDLoc(N), Tmp,
10155 Ptr, ST->getMemOperand());
10156 }
10157 break;
10158 case MVT::f64:
10159 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations &&
10160 !ST->isVolatile()) ||
10161 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
10162 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
10163 getZExtValue(), MVT::i64);
10164 return DAG.getStore(Chain, SDLoc(N), Tmp,
10165 Ptr, ST->getMemOperand());
10166 }
10168 if (!ST->isVolatile() &&
10169 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
10170 // Many FP stores are not made apparent until after legalize, e.g. for
10171 // argument passing. Since this is so common, custom legalize the
10172 // 64-bit integer store into two 32-bit stores.
10173 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
10174 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
10175 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
10176 if (TLI.isBigEndian()) std::swap(Lo, Hi);
10178 unsigned Alignment = ST->getAlignment();
10179 bool isVolatile = ST->isVolatile();
10180 bool isNonTemporal = ST->isNonTemporal();
10181 AAMDNodes AAInfo = ST->getAAInfo();
10183 SDValue St0 = DAG.getStore(Chain, SDLoc(ST), Lo,
10184 Ptr, ST->getPointerInfo(),
10185 isVolatile, isNonTemporal,
10186 ST->getAlignment(), AAInfo);
10187 Ptr = DAG.getNode(ISD::ADD, SDLoc(N), Ptr.getValueType(), Ptr,
10188 DAG.getConstant(4, Ptr.getValueType()));
10189 Alignment = MinAlign(Alignment, 4U);
10190 SDValue St1 = DAG.getStore(Chain, SDLoc(ST), Hi,
10191 Ptr, ST->getPointerInfo().getWithOffset(4),
10192 isVolatile, isNonTemporal,
10193 Alignment, AAInfo);
10194 return DAG.getNode(ISD::TokenFactor, SDLoc(N), MVT::Other,
10195 St0, St1);
10196 }
10198 break;
10199 }
10200 }
10201 }
10203 // Try to infer better alignment information than the store already has.
10204 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
10205 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
10206 if (Align > ST->getAlignment())
10207 return DAG.getTruncStore(Chain, SDLoc(N), Value,
10208 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
10209 ST->isVolatile(), ST->isNonTemporal(), Align,
10210 ST->getAAInfo());
10211 }
10212 }
10214 // Try transforming a pair floating point load / store ops to integer
10215 // load / store ops.
10216 SDValue NewST = TransformFPLoadStorePair(N);
10217 if (NewST.getNode())
10218 return NewST;
10220 bool UseAA = CombinerAA.getNumOccurrences() > 0 ? CombinerAA
10221 : DAG.getSubtarget().useAA();
10222 #ifndef NDEBUG
10223 if (CombinerAAOnlyFunc.getNumOccurrences() &&
10224 CombinerAAOnlyFunc != DAG.getMachineFunction().getName())
10225 UseAA = false;
10226 #endif
10227 if (UseAA && ST->isUnindexed()) {
10228 // Walk up chain skipping non-aliasing memory nodes.
10229 SDValue BetterChain = FindBetterChain(N, Chain);
10231 // If there is a better chain.
10232 if (Chain != BetterChain) {
10233 SDValue ReplStore;
10235 // Replace the chain to avoid dependency.
10236 if (ST->isTruncatingStore()) {
10237 ReplStore = DAG.getTruncStore(BetterChain, SDLoc(N), Value, Ptr,
10238 ST->getMemoryVT(), ST->getMemOperand());
10239 } else {
10240 ReplStore = DAG.getStore(BetterChain, SDLoc(N), Value, Ptr,
10241 ST->getMemOperand());
10242 }
10244 // Create token to keep both nodes around.
10245 SDValue Token = DAG.getNode(ISD::TokenFactor, SDLoc(N),
10246 MVT::Other, Chain, ReplStore);
10248 // Make sure the new and old chains are cleaned up.
10249 AddToWorklist(Token.getNode());
10251 // Don't add users to work list.
10252 return CombineTo(N, Token, false);
10253 }
10254 }
10256 // Try transforming N to an indexed store.
10257 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
10258 return SDValue(N, 0);
10260 // FIXME: is there such a thing as a truncating indexed store?
10261 if (ST->isTruncatingStore() && ST->isUnindexed() &&
10262 Value.getValueType().isInteger()) {
10263 // See if we can simplify the input to this truncstore with knowledge that
10264 // only the low bits are being used. For example:
10265 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
10266 SDValue Shorter =
10267 GetDemandedBits(Value,
10268 APInt::getLowBitsSet(
10269 Value.getValueType().getScalarType().getSizeInBits(),
10270 ST->getMemoryVT().getScalarType().getSizeInBits()));
10271 AddToWorklist(Value.getNode());
10272 if (Shorter.getNode())
10273 return DAG.getTruncStore(Chain, SDLoc(N), Shorter,
10274 Ptr, ST->getMemoryVT(), ST->getMemOperand());
10276 // Otherwise, see if we can simplify the operation with
10277 // SimplifyDemandedBits, which only works if the value has a single use.
10278 if (SimplifyDemandedBits(Value,
10279 APInt::getLowBitsSet(
10280 Value.getValueType().getScalarType().getSizeInBits(),
10281 ST->getMemoryVT().getScalarType().getSizeInBits())))
10282 return SDValue(N, 0);
10283 }
10285 // If this is a load followed by a store to the same location, then the store
10286 // is dead/noop.
10287 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
10288 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
10289 ST->isUnindexed() && !ST->isVolatile() &&
10290 // There can't be any side effects between the load and store, such as
10291 // a call or store.
10292 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
10293 // The store is dead, remove it.
10294 return Chain;
10295 }
10296 }
10298 // If this is a store followed by a store with the same value to the same
10299 // location, then the store is dead/noop.
10300 if (StoreSDNode *ST1 = dyn_cast<StoreSDNode>(Chain)) {
10301 if (ST1->getBasePtr() == Ptr && ST->getMemoryVT() == ST1->getMemoryVT() &&
10302 ST1->getValue() == Value && ST->isUnindexed() && !ST->isVolatile() &&
10303 ST1->isUnindexed() && !ST1->isVolatile()) {
10304 // The store is dead, remove it.
10305 return Chain;
10306 }
10307 }
10309 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
10310 // truncating store. We can do this even if this is already a truncstore.
10311 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
10312 && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
10313 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
10314 ST->getMemoryVT())) {
10315 return DAG.getTruncStore(Chain, SDLoc(N), Value.getOperand(0),
10316 Ptr, ST->getMemoryVT(), ST->getMemOperand());
10317 }
10319 // Only perform this optimization before the types are legal, because we
10320 // don't want to perform this optimization on every DAGCombine invocation.
10321 if (!LegalTypes) {
10322 bool EverChanged = false;
10324 do {
10325 // There can be multiple store sequences on the same chain.
10326 // Keep trying to merge store sequences until we are unable to do so
10327 // or until we merge the last store on the chain.
10328 bool Changed = MergeConsecutiveStores(ST);
10329 EverChanged |= Changed;
10330 if (!Changed) break;
10331 } while (ST->getOpcode() != ISD::DELETED_NODE);
10333 if (EverChanged)
10334 return SDValue(N, 0);
10335 }
10337 return ReduceLoadOpStoreWidth(N);
10338 }
10340 SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
10341 SDValue InVec = N->getOperand(0);
10342 SDValue InVal = N->getOperand(1);
10343 SDValue EltNo = N->getOperand(2);
10344 SDLoc dl(N);
10346 // If the inserted element is an UNDEF, just use the input vector.
10347 if (InVal.getOpcode() == ISD::UNDEF)
10348 return InVec;
10350 EVT VT = InVec.getValueType();
10352 // If we can't generate a legal BUILD_VECTOR, exit
10353 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
10354 return SDValue();
10356 // Check that we know which element is being inserted
10357 if (!isa<ConstantSDNode>(EltNo))
10358 return SDValue();
10359 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
10361 // Canonicalize insert_vector_elt dag nodes.
10362 // Example:
10363 // (insert_vector_elt (insert_vector_elt A, Idx0), Idx1)
10364 // -> (insert_vector_elt (insert_vector_elt A, Idx1), Idx0)
10365 //
10366 // Do this only if the child insert_vector node has one use; also
10367 // do this only if indices are both constants and Idx1 < Idx0.
10368 if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT && InVec.hasOneUse()
10369 && isa<ConstantSDNode>(InVec.getOperand(2))) {
10370 unsigned OtherElt =
10371 cast<ConstantSDNode>(InVec.getOperand(2))->getZExtValue();
10372 if (Elt < OtherElt) {
10373 // Swap nodes.
10374 SDValue NewOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), VT,
10375 InVec.getOperand(0), InVal, EltNo);
10376 AddToWorklist(NewOp.getNode());
10377 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(InVec.getNode()),
10378 VT, NewOp, InVec.getOperand(1), InVec.getOperand(2));
10379 }
10380 }
10382 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially
10383 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the
10384 // vector elements.
10385 SmallVector<SDValue, 8> Ops;
10386 // Do not combine these two vectors if the output vector will not replace
10387 // the input vector.
10388 if (InVec.getOpcode() == ISD::BUILD_VECTOR && InVec.hasOneUse()) {
10389 Ops.append(InVec.getNode()->op_begin(),
10390 InVec.getNode()->op_end());
10391 } else if (InVec.getOpcode() == ISD::UNDEF) {
10392 unsigned NElts = VT.getVectorNumElements();
10393 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType()));
10394 } else {
10395 return SDValue();
10396 }
10398 // Insert the element
10399 if (Elt < Ops.size()) {
10400 // All the operands of BUILD_VECTOR must have the same type;
10401 // we enforce that here.
10402 EVT OpVT = Ops[0].getValueType();
10403 if (InVal.getValueType() != OpVT)
10404 InVal = OpVT.bitsGT(InVal.getValueType()) ?
10405 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) :
10406 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal);
10407 Ops[Elt] = InVal;
10408 }
10410 // Return the new vector
10411 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
10412 }
10414 SDValue DAGCombiner::ReplaceExtractVectorEltOfLoadWithNarrowedLoad(
10415 SDNode *EVE, EVT InVecVT, SDValue EltNo, LoadSDNode *OriginalLoad) {
10416 EVT ResultVT = EVE->getValueType(0);
10417 EVT VecEltVT = InVecVT.getVectorElementType();
10418 unsigned Align = OriginalLoad->getAlignment();
10419 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
10420 VecEltVT.getTypeForEVT(*DAG.getContext()));
10422 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VecEltVT))
10423 return SDValue();
10425 Align = NewAlign;
10427 SDValue NewPtr = OriginalLoad->getBasePtr();
10428 SDValue Offset;
10429 EVT PtrType = NewPtr.getValueType();
10430 MachinePointerInfo MPI;
10431 if (auto *ConstEltNo = dyn_cast<ConstantSDNode>(EltNo)) {
10432 int Elt = ConstEltNo->getZExtValue();
10433 unsigned PtrOff = VecEltVT.getSizeInBits() * Elt / 8;
10434 if (TLI.isBigEndian())
10435 PtrOff = InVecVT.getSizeInBits() / 8 - PtrOff;
10436 Offset = DAG.getConstant(PtrOff, PtrType);
10437 MPI = OriginalLoad->getPointerInfo().getWithOffset(PtrOff);
10438 } else {
10439 Offset = DAG.getNode(
10440 ISD::MUL, SDLoc(EVE), EltNo.getValueType(), EltNo,
10441 DAG.getConstant(VecEltVT.getStoreSize(), EltNo.getValueType()));
10442 if (TLI.isBigEndian())
10443 Offset = DAG.getNode(
10444 ISD::SUB, SDLoc(EVE), EltNo.getValueType(),
10445 DAG.getConstant(InVecVT.getStoreSize(), EltNo.getValueType()), Offset);
10446 MPI = OriginalLoad->getPointerInfo();
10447 }
10448 NewPtr = DAG.getNode(ISD::ADD, SDLoc(EVE), PtrType, NewPtr, Offset);
10450 // The replacement we need to do here is a little tricky: we need to
10451 // replace an extractelement of a load with a load.
10452 // Use ReplaceAllUsesOfValuesWith to do the replacement.
10453 // Note that this replacement assumes that the extractvalue is the only
10454 // use of the load; that's okay because we don't want to perform this
10455 // transformation in other cases anyway.
10456 SDValue Load;
10457 SDValue Chain;
10458 if (ResultVT.bitsGT(VecEltVT)) {
10459 // If the result type of vextract is wider than the load, then issue an
10460 // extending load instead.
10461 ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, ResultVT,
10462 VecEltVT)
10463 ? ISD::ZEXTLOAD
10464 : ISD::EXTLOAD;
10465 Load = DAG.getExtLoad(
10466 ExtType, SDLoc(EVE), ResultVT, OriginalLoad->getChain(), NewPtr, MPI,
10467 VecEltVT, OriginalLoad->isVolatile(), OriginalLoad->isNonTemporal(),
10468 OriginalLoad->isInvariant(), Align, OriginalLoad->getAAInfo());
10469 Chain = Load.getValue(1);
10470 } else {
10471 Load = DAG.getLoad(
10472 VecEltVT, SDLoc(EVE), OriginalLoad->getChain(), NewPtr, MPI,
10473 OriginalLoad->isVolatile(), OriginalLoad->isNonTemporal(),
10474 OriginalLoad->isInvariant(), Align, OriginalLoad->getAAInfo());
10475 Chain = Load.getValue(1);
10476 if (ResultVT.bitsLT(VecEltVT))
10477 Load = DAG.getNode(ISD::TRUNCATE, SDLoc(EVE), ResultVT, Load);
10478 else
10479 Load = DAG.getNode(ISD::BITCAST, SDLoc(EVE), ResultVT, Load);
10480 }
10481 WorklistRemover DeadNodes(*this);
10482 SDValue From[] = { SDValue(EVE, 0), SDValue(OriginalLoad, 1) };
10483 SDValue To[] = { Load, Chain };
10484 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
10485 // Since we're explicitly calling ReplaceAllUses, add the new node to the
10486 // worklist explicitly as well.
10487 AddToWorklist(Load.getNode());
10488 AddUsersToWorklist(Load.getNode()); // Add users too
10489 // Make sure to revisit this node to clean it up; it will usually be dead.
10490 AddToWorklist(EVE);
10491 ++OpsNarrowed;
10492 return SDValue(EVE, 0);
10493 }
10495 SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
10496 // (vextract (scalar_to_vector val, 0) -> val
10497 SDValue InVec = N->getOperand(0);
10498 EVT VT = InVec.getValueType();
10499 EVT NVT = N->getValueType(0);
10501 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
10502 // Check if the result type doesn't match the inserted element type. A
10503 // SCALAR_TO_VECTOR may truncate the inserted element and the
10504 // EXTRACT_VECTOR_ELT may widen the extracted vector.
10505 SDValue InOp = InVec.getOperand(0);
10506 if (InOp.getValueType() != NVT) {
10507 assert(InOp.getValueType().isInteger() && NVT.isInteger());
10508 return DAG.getSExtOrTrunc(InOp, SDLoc(InVec), NVT);
10509 }
10510 return InOp;
10511 }
10513 SDValue EltNo = N->getOperand(1);
10514 bool ConstEltNo = isa<ConstantSDNode>(EltNo);
10516 // Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.
10517 // We only perform this optimization before the op legalization phase because
10518 // we may introduce new vector instructions which are not backed by TD
10519 // patterns. For example on AVX, extracting elements from a wide vector
10520 // without using extract_subvector. However, if we can find an underlying
10521 // scalar value, then we can always use that.
10522 if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE
10523 && ConstEltNo) {
10524 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
10525 int NumElem = VT.getVectorNumElements();
10526 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(InVec);
10527 // Find the new index to extract from.
10528 int OrigElt = SVOp->getMaskElt(Elt);
10530 // Extracting an undef index is undef.
10531 if (OrigElt == -1)
10532 return DAG.getUNDEF(NVT);
10534 // Select the right vector half to extract from.
10535 SDValue SVInVec;
10536 if (OrigElt < NumElem) {
10537 SVInVec = InVec->getOperand(0);
10538 } else {
10539 SVInVec = InVec->getOperand(1);
10540 OrigElt -= NumElem;
10541 }
10543 if (SVInVec.getOpcode() == ISD::BUILD_VECTOR) {
10544 SDValue InOp = SVInVec.getOperand(OrigElt);
10545 if (InOp.getValueType() != NVT) {
10546 assert(InOp.getValueType().isInteger() && NVT.isInteger());
10547 InOp = DAG.getSExtOrTrunc(InOp, SDLoc(SVInVec), NVT);
10548 }
10550 return InOp;
10551 }
10553 // FIXME: We should handle recursing on other vector shuffles and
10554 // scalar_to_vector here as well.
10556 if (!LegalOperations) {
10557 EVT IndexTy = TLI.getVectorIdxTy();
10558 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), NVT,
10559 SVInVec, DAG.getConstant(OrigElt, IndexTy));
10560 }
10561 }
10563 bool BCNumEltsChanged = false;
10564 EVT ExtVT = VT.getVectorElementType();
10565 EVT LVT = ExtVT;
10567 // If the result of load has to be truncated, then it's not necessarily
10568 // profitable.
10569 if (NVT.bitsLT(LVT) && !TLI.isTruncateFree(LVT, NVT))
10570 return SDValue();
10572 if (InVec.getOpcode() == ISD::BITCAST) {
10573 // Don't duplicate a load with other uses.
10574 if (!InVec.hasOneUse())
10575 return SDValue();
10577 EVT BCVT = InVec.getOperand(0).getValueType();
10578 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType()))
10579 return SDValue();
10580 if (VT.getVectorNumElements() != BCVT.getVectorNumElements())
10581 BCNumEltsChanged = true;
10582 InVec = InVec.getOperand(0);
10583 ExtVT = BCVT.getVectorElementType();
10584 }
10586 // (vextract (vN[if]M load $addr), i) -> ([if]M load $addr + i * size)
10587 if (!LegalOperations && !ConstEltNo && InVec.hasOneUse() &&
10588 ISD::isNormalLoad(InVec.getNode()) &&
10589 !N->getOperand(1)->hasPredecessor(InVec.getNode())) {
10590 SDValue Index = N->getOperand(1);
10591 if (LoadSDNode *OrigLoad = dyn_cast<LoadSDNode>(InVec))
10592 return ReplaceExtractVectorEltOfLoadWithNarrowedLoad(N, VT, Index,
10593 OrigLoad);
10594 }
10596 // Perform only after legalization to ensure build_vector / vector_shuffle
10597 // optimizations have already been done.
10598 if (!LegalOperations) return SDValue();
10600 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
10601 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
10602 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
10604 if (ConstEltNo) {
10605 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
10607 LoadSDNode *LN0 = nullptr;
10608 const ShuffleVectorSDNode *SVN = nullptr;
10609 if (ISD::isNormalLoad(InVec.getNode())) {
10610 LN0 = cast<LoadSDNode>(InVec);
10611 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
10612 InVec.getOperand(0).getValueType() == ExtVT &&
10613 ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
10614 // Don't duplicate a load with other uses.
10615 if (!InVec.hasOneUse())
10616 return SDValue();
10618 LN0 = cast<LoadSDNode>(InVec.getOperand(0));
10619 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) {
10620 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
10621 // =>
10622 // (load $addr+1*size)
10624 // Don't duplicate a load with other uses.
10625 if (!InVec.hasOneUse())
10626 return SDValue();
10628 // If the bit convert changed the number of elements, it is unsafe
10629 // to examine the mask.
10630 if (BCNumEltsChanged)
10631 return SDValue();
10633 // Select the input vector, guarding against out of range extract vector.
10634 unsigned NumElems = VT.getVectorNumElements();
10635 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt);
10636 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
10638 if (InVec.getOpcode() == ISD::BITCAST) {
10639 // Don't duplicate a load with other uses.
10640 if (!InVec.hasOneUse())
10641 return SDValue();
10643 InVec = InVec.getOperand(0);
10644 }
10645 if (ISD::isNormalLoad(InVec.getNode())) {
10646 LN0 = cast<LoadSDNode>(InVec);
10647 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems;
10648 EltNo = DAG.getConstant(Elt, EltNo.getValueType());
10649 }
10650 }
10652 // Make sure we found a non-volatile load and the extractelement is
10653 // the only use.
10654 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile())
10655 return SDValue();
10657 // If Idx was -1 above, Elt is going to be -1, so just return undef.
10658 if (Elt == -1)
10659 return DAG.getUNDEF(LVT);
10661 return ReplaceExtractVectorEltOfLoadWithNarrowedLoad(N, VT, EltNo, LN0);
10662 }
10664 return SDValue();
10665 }
10667 // Simplify (build_vec (ext )) to (bitcast (build_vec ))
10668 SDValue DAGCombiner::reduceBuildVecExtToExtBuildVec(SDNode *N) {
10669 // We perform this optimization post type-legalization because
10670 // the type-legalizer often scalarizes integer-promoted vectors.
10671 // Performing this optimization before may create bit-casts which
10672 // will be type-legalized to complex code sequences.
10673 // We perform this optimization only before the operation legalizer because we
10674 // may introduce illegal operations.
10675 if (Level != AfterLegalizeVectorOps && Level != AfterLegalizeTypes)
10676 return SDValue();
10678 unsigned NumInScalars = N->getNumOperands();
10679 SDLoc dl(N);
10680 EVT VT = N->getValueType(0);
10682 // Check to see if this is a BUILD_VECTOR of a bunch of values
10683 // which come from any_extend or zero_extend nodes. If so, we can create
10684 // a new BUILD_VECTOR using bit-casts which may enable other BUILD_VECTOR
10685 // optimizations. We do not handle sign-extend because we can't fill the sign
10686 // using shuffles.
10687 EVT SourceType = MVT::Other;
10688 bool AllAnyExt = true;
10690 for (unsigned i = 0; i != NumInScalars; ++i) {
10691 SDValue In = N->getOperand(i);
10692 // Ignore undef inputs.
10693 if (In.getOpcode() == ISD::UNDEF) continue;
10695 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND;
10696 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND;
10698 // Abort if the element is not an extension.
10699 if (!ZeroExt && !AnyExt) {
10700 SourceType = MVT::Other;
10701 break;
10702 }
10704 // The input is a ZeroExt or AnyExt. Check the original type.
10705 EVT InTy = In.getOperand(0).getValueType();
10707 // Check that all of the widened source types are the same.
10708 if (SourceType == MVT::Other)
10709 // First time.
10710 SourceType = InTy;
10711 else if (InTy != SourceType) {
10712 // Multiple income types. Abort.
10713 SourceType = MVT::Other;
10714 break;
10715 }
10717 // Check if all of the extends are ANY_EXTENDs.
10718 AllAnyExt &= AnyExt;
10719 }
10721 // In order to have valid types, all of the inputs must be extended from the
10722 // same source type and all of the inputs must be any or zero extend.
10723 // Scalar sizes must be a power of two.
10724 EVT OutScalarTy = VT.getScalarType();
10725 bool ValidTypes = SourceType != MVT::Other &&
10726 isPowerOf2_32(OutScalarTy.getSizeInBits()) &&
10727 isPowerOf2_32(SourceType.getSizeInBits());
10729 // Create a new simpler BUILD_VECTOR sequence which other optimizations can
10730 // turn into a single shuffle instruction.
10731 if (!ValidTypes)
10732 return SDValue();
10734 bool isLE = TLI.isLittleEndian();
10735 unsigned ElemRatio = OutScalarTy.getSizeInBits()/SourceType.getSizeInBits();
10736 assert(ElemRatio > 1 && "Invalid element size ratio");
10737 SDValue Filler = AllAnyExt ? DAG.getUNDEF(SourceType):
10738 DAG.getConstant(0, SourceType);
10740 unsigned NewBVElems = ElemRatio * VT.getVectorNumElements();
10741 SmallVector<SDValue, 8> Ops(NewBVElems, Filler);
10743 // Populate the new build_vector
10744 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
10745 SDValue Cast = N->getOperand(i);
10746 assert((Cast.getOpcode() == ISD::ANY_EXTEND ||
10747 Cast.getOpcode() == ISD::ZERO_EXTEND ||
10748 Cast.getOpcode() == ISD::UNDEF) && "Invalid cast opcode");
10749 SDValue In;
10750 if (Cast.getOpcode() == ISD::UNDEF)
10751 In = DAG.getUNDEF(SourceType);
10752 else
10753 In = Cast->getOperand(0);
10754 unsigned Index = isLE ? (i * ElemRatio) :
10755 (i * ElemRatio + (ElemRatio - 1));
10757 assert(Index < Ops.size() && "Invalid index");
10758 Ops[Index] = In;
10759 }
10761 // The type of the new BUILD_VECTOR node.
10762 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems);
10763 assert(VecVT.getSizeInBits() == VT.getSizeInBits() &&
10764 "Invalid vector size");
10765 // Check if the new vector type is legal.
10766 if (!isTypeLegal(VecVT)) return SDValue();
10768 // Make the new BUILD_VECTOR.
10769 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
10771 // The new BUILD_VECTOR node has the potential to be further optimized.
10772 AddToWorklist(BV.getNode());
10773 // Bitcast to the desired type.
10774 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
10775 }
10777 SDValue DAGCombiner::reduceBuildVecConvertToConvertBuildVec(SDNode *N) {
10778 EVT VT = N->getValueType(0);
10780 unsigned NumInScalars = N->getNumOperands();
10781 SDLoc dl(N);
10783 EVT SrcVT = MVT::Other;
10784 unsigned Opcode = ISD::DELETED_NODE;
10785 unsigned NumDefs = 0;
10787 for (unsigned i = 0; i != NumInScalars; ++i) {
10788 SDValue In = N->getOperand(i);
10789 unsigned Opc = In.getOpcode();
10791 if (Opc == ISD::UNDEF)
10792 continue;
10794 // If all scalar values are floats and converted from integers.
10795 if (Opcode == ISD::DELETED_NODE &&
10796 (Opc == ISD::UINT_TO_FP || Opc == ISD::SINT_TO_FP)) {
10797 Opcode = Opc;
10798 }
10800 if (Opc != Opcode)
10801 return SDValue();
10803 EVT InVT = In.getOperand(0).getValueType();
10805 // If all scalar values are typed differently, bail out. It's chosen to
10806 // simplify BUILD_VECTOR of integer types.
10807 if (SrcVT == MVT::Other)
10808 SrcVT = InVT;
10809 if (SrcVT != InVT)
10810 return SDValue();
10811 NumDefs++;
10812 }
10814 // If the vector has just one element defined, it's not worth to fold it into
10815 // a vectorized one.
10816 if (NumDefs < 2)
10817 return SDValue();
10819 assert((Opcode == ISD::UINT_TO_FP || Opcode == ISD::SINT_TO_FP)
10820 && "Should only handle conversion from integer to float.");
10821 assert(SrcVT != MVT::Other && "Cannot determine source type!");
10823 EVT NVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumInScalars);
10825 if (!TLI.isOperationLegalOrCustom(Opcode, NVT))
10826 return SDValue();
10828 SmallVector<SDValue, 8> Opnds;
10829 for (unsigned i = 0; i != NumInScalars; ++i) {
10830 SDValue In = N->getOperand(i);
10832 if (In.getOpcode() == ISD::UNDEF)
10833 Opnds.push_back(DAG.getUNDEF(SrcVT));
10834 else
10835 Opnds.push_back(In.getOperand(0));
10836 }
10837 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, Opnds);
10838 AddToWorklist(BV.getNode());
10840 return DAG.getNode(Opcode, dl, VT, BV);
10841 }
10843 SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
10844 unsigned NumInScalars = N->getNumOperands();
10845 SDLoc dl(N);
10846 EVT VT = N->getValueType(0);
10848 // A vector built entirely of undefs is undef.
10849 if (ISD::allOperandsUndef(N))
10850 return DAG.getUNDEF(VT);
10852 SDValue V = reduceBuildVecExtToExtBuildVec(N);
10853 if (V.getNode())
10854 return V;
10856 V = reduceBuildVecConvertToConvertBuildVec(N);
10857 if (V.getNode())
10858 return V;
10860 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
10861 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
10862 // at most two distinct vectors, turn this into a shuffle node.
10864 // Only type-legal BUILD_VECTOR nodes are converted to shuffle nodes.
10865 if (!isTypeLegal(VT))
10866 return SDValue();
10868 // May only combine to shuffle after legalize if shuffle is legal.
10869 if (LegalOperations && !TLI.isOperationLegal(ISD::VECTOR_SHUFFLE, VT))
10870 return SDValue();
10872 SDValue VecIn1, VecIn2;
10873 bool UsesZeroVector = false;
10874 for (unsigned i = 0; i != NumInScalars; ++i) {
10875 SDValue Op = N->getOperand(i);
10876 // Ignore undef inputs.
10877 if (Op.getOpcode() == ISD::UNDEF) continue;
10879 // See if we can combine this build_vector into a blend with a zero vector.
10880 if (!VecIn2.getNode() && ((Op.getOpcode() == ISD::Constant &&
10881 cast<ConstantSDNode>(Op.getNode())->isNullValue()) ||
10882 (Op.getOpcode() == ISD::ConstantFP &&
10883 cast<ConstantFPSDNode>(Op.getNode())->getValueAPF().isZero()))) {
10884 UsesZeroVector = true;
10885 continue;
10886 }
10888 // If this input is something other than a EXTRACT_VECTOR_ELT with a
10889 // constant index, bail out.
10890 if (Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
10891 !isa<ConstantSDNode>(Op.getOperand(1))) {
10892 VecIn1 = VecIn2 = SDValue(nullptr, 0);
10893 break;
10894 }
10896 // We allow up to two distinct input vectors.
10897 SDValue ExtractedFromVec = Op.getOperand(0);
10898 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
10899 continue;
10901 if (!VecIn1.getNode()) {
10902 VecIn1 = ExtractedFromVec;
10903 } else if (!VecIn2.getNode() && !UsesZeroVector) {
10904 VecIn2 = ExtractedFromVec;
10905 } else {
10906 // Too many inputs.
10907 VecIn1 = VecIn2 = SDValue(nullptr, 0);
10908 break;
10909 }
10910 }
10912 // If everything is good, we can make a shuffle operation.
10913 if (VecIn1.getNode()) {
10914 unsigned InNumElements = VecIn1.getValueType().getVectorNumElements();
10915 SmallVector<int, 8> Mask;
10916 for (unsigned i = 0; i != NumInScalars; ++i) {
10917 unsigned Opcode = N->getOperand(i).getOpcode();
10918 if (Opcode == ISD::UNDEF) {
10919 Mask.push_back(-1);
10920 continue;
10921 }
10923 // Operands can also be zero.
10924 if (Opcode != ISD::EXTRACT_VECTOR_ELT) {
10925 assert(UsesZeroVector &&
10926 (Opcode == ISD::Constant || Opcode == ISD::ConstantFP) &&
10927 "Unexpected node found!");
10928 Mask.push_back(NumInScalars+i);
10929 continue;
10930 }
10932 // If extracting from the first vector, just use the index directly.
10933 SDValue Extract = N->getOperand(i);
10934 SDValue ExtVal = Extract.getOperand(1);
10935 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue();
10936 if (Extract.getOperand(0) == VecIn1) {
10937 Mask.push_back(ExtIndex);
10938 continue;
10939 }
10941 // Otherwise, use InIdx + InputVecSize
10942 Mask.push_back(InNumElements + ExtIndex);
10943 }
10945 // Avoid introducing illegal shuffles with zero.
10946 if (UsesZeroVector && !TLI.isVectorClearMaskLegal(Mask, VT))
10947 return SDValue();
10949 // We can't generate a shuffle node with mismatched input and output types.
10950 // Attempt to transform a single input vector to the correct type.
10951 if ((VT != VecIn1.getValueType())) {
10952 // If the input vector type has a different base type to the output
10953 // vector type, bail out.
10954 EVT VTElemType = VT.getVectorElementType();
10955 if ((VecIn1.getValueType().getVectorElementType() != VTElemType) ||
10956 (VecIn2.getNode() &&
10957 (VecIn2.getValueType().getVectorElementType() != VTElemType)))
10958 return SDValue();
10960 // If the input vector is too small, widen it.
10961 // We only support widening of vectors which are half the size of the
10962 // output registers. For example XMM->YMM widening on X86 with AVX.
10963 EVT VecInT = VecIn1.getValueType();
10964 if (VecInT.getSizeInBits() * 2 == VT.getSizeInBits()) {
10965 // If we only have one small input, widen it by adding undef values.
10966 if (!VecIn2.getNode())
10967 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, VecIn1,
10968 DAG.getUNDEF(VecIn1.getValueType()));
10969 else if (VecIn1.getValueType() == VecIn2.getValueType()) {
10970 // If we have two small inputs of the same type, try to concat them.
10971 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, VecIn1, VecIn2);
10972 VecIn2 = SDValue(nullptr, 0);
10973 } else
10974 return SDValue();
10975 } else if (VecInT.getSizeInBits() == VT.getSizeInBits() * 2) {
10976 // If the input vector is too large, try to split it.
10977 // We don't support having two input vectors that are too large.
10978 if (VecIn2.getNode())
10979 return SDValue();
10981 if (!TLI.isExtractSubvectorCheap(VT, VT.getVectorNumElements()))
10982 return SDValue();
10984 // Try to replace VecIn1 with two extract_subvectors
10985 // No need to update the masks, they should still be correct.
10986 VecIn2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, VecIn1,
10987 DAG.getConstant(VT.getVectorNumElements(), TLI.getVectorIdxTy()));
10988 VecIn1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, VecIn1,
10989 DAG.getConstant(0, TLI.getVectorIdxTy()));
10990 UsesZeroVector = false;
10991 } else
10992 return SDValue();
10993 }
10995 if (UsesZeroVector)
10996 VecIn2 = VT.isInteger() ? DAG.getConstant(0, VT) :
10997 DAG.getConstantFP(0.0, VT);
10998 else
10999 // If VecIn2 is unused then change it to undef.
11000 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
11002 // Check that we were able to transform all incoming values to the same
11003 // type.
11004 if (VecIn2.getValueType() != VecIn1.getValueType() ||
11005 VecIn1.getValueType() != VT)
11006 return SDValue();
11008 // Return the new VECTOR_SHUFFLE node.
11009 SDValue Ops[2];
11010 Ops[0] = VecIn1;
11011 Ops[1] = VecIn2;
11012 return DAG.getVectorShuffle(VT, dl, Ops[0], Ops[1], &Mask[0]);
11013 }
11015 return SDValue();
11016 }
11018 SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
11019 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
11020 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
11021 // inputs come from at most two distinct vectors, turn this into a shuffle
11022 // node.
11024 // If we only have one input vector, we don't need to do any concatenation.
11025 if (N->getNumOperands() == 1)
11026 return N->getOperand(0);
11028 // Check if all of the operands are undefs.
11029 EVT VT = N->getValueType(0);
11030 if (ISD::allOperandsUndef(N))
11031 return DAG.getUNDEF(VT);
11033 // Optimize concat_vectors where one of the vectors is undef.
11034 if (N->getNumOperands() == 2 &&
11035 N->getOperand(1)->getOpcode() == ISD::UNDEF) {
11036 SDValue In = N->getOperand(0);
11037 assert(In.getValueType().isVector() && "Must concat vectors");
11039 // Transform: concat_vectors(scalar, undef) -> scalar_to_vector(sclr).
11040 if (In->getOpcode() == ISD::BITCAST &&
11041 !In->getOperand(0)->getValueType(0).isVector()) {
11042 SDValue Scalar = In->getOperand(0);
11043 EVT SclTy = Scalar->getValueType(0);
11045 if (!SclTy.isFloatingPoint() && !SclTy.isInteger())
11046 return SDValue();
11048 EVT NVT = EVT::getVectorVT(*DAG.getContext(), SclTy,
11049 VT.getSizeInBits() / SclTy.getSizeInBits());
11050 if (!TLI.isTypeLegal(NVT) || !TLI.isTypeLegal(Scalar.getValueType()))
11051 return SDValue();
11053 SDLoc dl = SDLoc(N);
11054 SDValue Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NVT, Scalar);
11055 return DAG.getNode(ISD::BITCAST, dl, VT, Res);
11056 }
11057 }
11059 // fold (concat_vectors (BUILD_VECTOR A, B, ...), (BUILD_VECTOR C, D, ...))
11060 // -> (BUILD_VECTOR A, B, ..., C, D, ...)
11061 if (N->getNumOperands() == 2 &&
11062 N->getOperand(0).getOpcode() == ISD::BUILD_VECTOR &&
11063 N->getOperand(1).getOpcode() == ISD::BUILD_VECTOR) {
11064 EVT VT = N->getValueType(0);
11065 SDValue N0 = N->getOperand(0);
11066 SDValue N1 = N->getOperand(1);
11067 SmallVector<SDValue, 8> Opnds;
11068 unsigned BuildVecNumElts = N0.getNumOperands();
11070 EVT SclTy0 = N0.getOperand(0)->getValueType(0);
11071 EVT SclTy1 = N1.getOperand(0)->getValueType(0);
11072 if (SclTy0.isFloatingPoint()) {
11073 for (unsigned i = 0; i != BuildVecNumElts; ++i)
11074 Opnds.push_back(N0.getOperand(i));
11075 for (unsigned i = 0; i != BuildVecNumElts; ++i)
11076 Opnds.push_back(N1.getOperand(i));
11077 } else {
11078 // If BUILD_VECTOR are from built from integer, they may have different
11079 // operand types. Get the smaller type and truncate all operands to it.
11080 EVT MinTy = SclTy0.bitsLE(SclTy1) ? SclTy0 : SclTy1;
11081 for (unsigned i = 0; i != BuildVecNumElts; ++i)
11082 Opnds.push_back(DAG.getNode(ISD::TRUNCATE, SDLoc(N), MinTy,
11083 N0.getOperand(i)));
11084 for (unsigned i = 0; i != BuildVecNumElts; ++i)
11085 Opnds.push_back(DAG.getNode(ISD::TRUNCATE, SDLoc(N), MinTy,
11086 N1.getOperand(i)));
11087 }
11089 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, Opnds);
11090 }
11092 // Type legalization of vectors and DAG canonicalization of SHUFFLE_VECTOR
11093 // nodes often generate nop CONCAT_VECTOR nodes.
11094 // Scan the CONCAT_VECTOR operands and look for a CONCAT operations that
11095 // place the incoming vectors at the exact same location.
11096 SDValue SingleSource = SDValue();
11097 unsigned PartNumElem = N->getOperand(0).getValueType().getVectorNumElements();
11099 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
11100 SDValue Op = N->getOperand(i);
11102 if (Op.getOpcode() == ISD::UNDEF)
11103 continue;
11105 // Check if this is the identity extract:
11106 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR)
11107 return SDValue();
11109 // Find the single incoming vector for the extract_subvector.
11110 if (SingleSource.getNode()) {
11111 if (Op.getOperand(0) != SingleSource)
11112 return SDValue();
11113 } else {
11114 SingleSource = Op.getOperand(0);
11116 // Check the source type is the same as the type of the result.
11117 // If not, this concat may extend the vector, so we can not
11118 // optimize it away.
11119 if (SingleSource.getValueType() != N->getValueType(0))
11120 return SDValue();
11121 }
11123 unsigned IdentityIndex = i * PartNumElem;
11124 ConstantSDNode *CS = dyn_cast<ConstantSDNode>(Op.getOperand(1));
11125 // The extract index must be constant.
11126 if (!CS)
11127 return SDValue();
11129 // Check that we are reading from the identity index.
11130 if (CS->getZExtValue() != IdentityIndex)
11131 return SDValue();
11132 }
11134 if (SingleSource.getNode())
11135 return SingleSource;
11137 return SDValue();
11138 }
11140 SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) {
11141 EVT NVT = N->getValueType(0);
11142 SDValue V = N->getOperand(0);
11144 if (V->getOpcode() == ISD::CONCAT_VECTORS) {
11145 // Combine:
11146 // (extract_subvec (concat V1, V2, ...), i)
11147 // Into:
11148 // Vi if possible
11149 // Only operand 0 is checked as 'concat' assumes all inputs of the same
11150 // type.
11151 if (V->getOperand(0).getValueType() != NVT)
11152 return SDValue();
11153 unsigned Idx = dyn_cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
11154 unsigned NumElems = NVT.getVectorNumElements();
11155 assert((Idx % NumElems) == 0 &&
11156 "IDX in concat is not a multiple of the result vector length.");
11157 return V->getOperand(Idx / NumElems);
11158 }
11160 // Skip bitcasting
11161 if (V->getOpcode() == ISD::BITCAST)
11162 V = V.getOperand(0);
11164 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) {
11165 SDLoc dl(N);
11166 // Handle only simple case where vector being inserted and vector
11167 // being extracted are of same type, and are half size of larger vectors.
11168 EVT BigVT = V->getOperand(0).getValueType();
11169 EVT SmallVT = V->getOperand(1).getValueType();
11170 if (!NVT.bitsEq(SmallVT) || NVT.getSizeInBits()*2 != BigVT.getSizeInBits())
11171 return SDValue();
11173 // Only handle cases where both indexes are constants with the same type.
11174 ConstantSDNode *ExtIdx = dyn_cast<ConstantSDNode>(N->getOperand(1));
11175 ConstantSDNode *InsIdx = dyn_cast<ConstantSDNode>(V->getOperand(2));
11177 if (InsIdx && ExtIdx &&
11178 InsIdx->getValueType(0).getSizeInBits() <= 64 &&
11179 ExtIdx->getValueType(0).getSizeInBits() <= 64) {
11180 // Combine:
11181 // (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx)
11182 // Into:
11183 // indices are equal or bit offsets are equal => V1
11184 // otherwise => (extract_subvec V1, ExtIdx)
11185 if (InsIdx->getZExtValue() * SmallVT.getScalarType().getSizeInBits() ==
11186 ExtIdx->getZExtValue() * NVT.getScalarType().getSizeInBits())
11187 return DAG.getNode(ISD::BITCAST, dl, NVT, V->getOperand(1));
11188 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT,
11189 DAG.getNode(ISD::BITCAST, dl,
11190 N->getOperand(0).getValueType(),
11191 V->getOperand(0)), N->getOperand(1));
11192 }
11193 }
11195 return SDValue();
11196 }
11198 static SDValue simplifyShuffleOperandRecursively(SmallBitVector &UsedElements,
11199 SDValue V, SelectionDAG &DAG) {
11200 SDLoc DL(V);
11201 EVT VT = V.getValueType();
11203 switch (V.getOpcode()) {
11204 default:
11205 return V;
11207 case ISD::CONCAT_VECTORS: {
11208 EVT OpVT = V->getOperand(0).getValueType();
11209 int OpSize = OpVT.getVectorNumElements();
11210 SmallBitVector OpUsedElements(OpSize, false);
11211 bool FoundSimplification = false;
11212 SmallVector<SDValue, 4> NewOps;
11213 NewOps.reserve(V->getNumOperands());
11214 for (int i = 0, NumOps = V->getNumOperands(); i < NumOps; ++i) {
11215 SDValue Op = V->getOperand(i);
11216 bool OpUsed = false;
11217 for (int j = 0; j < OpSize; ++j)
11218 if (UsedElements[i * OpSize + j]) {
11219 OpUsedElements[j] = true;
11220 OpUsed = true;
11221 }
11222 NewOps.push_back(
11223 OpUsed ? simplifyShuffleOperandRecursively(OpUsedElements, Op, DAG)
11224 : DAG.getUNDEF(OpVT));
11225 FoundSimplification |= Op == NewOps.back();
11226 OpUsedElements.reset();
11227 }
11228 if (FoundSimplification)
11229 V = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, NewOps);
11230 return V;
11231 }
11233 case ISD::INSERT_SUBVECTOR: {
11234 SDValue BaseV = V->getOperand(0);
11235 SDValue SubV = V->getOperand(1);
11236 auto *IdxN = dyn_cast<ConstantSDNode>(V->getOperand(2));
11237 if (!IdxN)
11238 return V;
11240 int SubSize = SubV.getValueType().getVectorNumElements();
11241 int Idx = IdxN->getZExtValue();
11242 bool SubVectorUsed = false;
11243 SmallBitVector SubUsedElements(SubSize, false);
11244 for (int i = 0; i < SubSize; ++i)
11245 if (UsedElements[i + Idx]) {
11246 SubVectorUsed = true;
11247 SubUsedElements[i] = true;
11248 UsedElements[i + Idx] = false;
11249 }
11251 // Now recurse on both the base and sub vectors.
11252 SDValue SimplifiedSubV =
11253 SubVectorUsed
11254 ? simplifyShuffleOperandRecursively(SubUsedElements, SubV, DAG)
11255 : DAG.getUNDEF(SubV.getValueType());
11256 SDValue SimplifiedBaseV = simplifyShuffleOperandRecursively(UsedElements, BaseV, DAG);
11257 if (SimplifiedSubV != SubV || SimplifiedBaseV != BaseV)
11258 V = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT,
11259 SimplifiedBaseV, SimplifiedSubV, V->getOperand(2));
11260 return V;
11261 }
11262 }
11263 }
11265 static SDValue simplifyShuffleOperands(ShuffleVectorSDNode *SVN, SDValue N0,
11266 SDValue N1, SelectionDAG &DAG) {
11267 EVT VT = SVN->getValueType(0);
11268 int NumElts = VT.getVectorNumElements();
11269 SmallBitVector N0UsedElements(NumElts, false), N1UsedElements(NumElts, false);
11270 for (int M : SVN->getMask())
11271 if (M >= 0 && M < NumElts)
11272 N0UsedElements[M] = true;
11273 else if (M >= NumElts)
11274 N1UsedElements[M - NumElts] = true;
11276 SDValue S0 = simplifyShuffleOperandRecursively(N0UsedElements, N0, DAG);
11277 SDValue S1 = simplifyShuffleOperandRecursively(N1UsedElements, N1, DAG);
11278 if (S0 == N0 && S1 == N1)
11279 return SDValue();
11281 return DAG.getVectorShuffle(VT, SDLoc(SVN), S0, S1, SVN->getMask());
11282 }
11284 // Tries to turn a shuffle of two CONCAT_VECTORS into a single concat.
11285 static SDValue partitionShuffleOfConcats(SDNode *N, SelectionDAG &DAG) {
11286 EVT VT = N->getValueType(0);
11287 unsigned NumElts = VT.getVectorNumElements();
11289 SDValue N0 = N->getOperand(0);
11290 SDValue N1 = N->getOperand(1);
11291 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
11293 SmallVector<SDValue, 4> Ops;
11294 EVT ConcatVT = N0.getOperand(0).getValueType();
11295 unsigned NumElemsPerConcat = ConcatVT.getVectorNumElements();
11296 unsigned NumConcats = NumElts / NumElemsPerConcat;
11298 // Look at every vector that's inserted. We're looking for exact
11299 // subvector-sized copies from a concatenated vector
11300 for (unsigned I = 0; I != NumConcats; ++I) {
11301 // Make sure we're dealing with a copy.
11302 unsigned Begin = I * NumElemsPerConcat;
11303 bool AllUndef = true, NoUndef = true;
11304 for (unsigned J = Begin; J != Begin + NumElemsPerConcat; ++J) {
11305 if (SVN->getMaskElt(J) >= 0)
11306 AllUndef = false;
11307 else
11308 NoUndef = false;
11309 }
11311 if (NoUndef) {
11312 if (SVN->getMaskElt(Begin) % NumElemsPerConcat != 0)
11313 return SDValue();
11315 for (unsigned J = 1; J != NumElemsPerConcat; ++J)
11316 if (SVN->getMaskElt(Begin + J - 1) + 1 != SVN->getMaskElt(Begin + J))
11317 return SDValue();
11319 unsigned FirstElt = SVN->getMaskElt(Begin) / NumElemsPerConcat;
11320 if (FirstElt < N0.getNumOperands())
11321 Ops.push_back(N0.getOperand(FirstElt));
11322 else
11323 Ops.push_back(N1.getOperand(FirstElt - N0.getNumOperands()));
11325 } else if (AllUndef) {
11326 Ops.push_back(DAG.getUNDEF(N0.getOperand(0).getValueType()));
11327 } else { // Mixed with general masks and undefs, can't do optimization.
11328 return SDValue();
11329 }
11330 }
11332 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Ops);
11333 }
11335 SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
11336 EVT VT = N->getValueType(0);
11337 unsigned NumElts = VT.getVectorNumElements();
11339 SDValue N0 = N->getOperand(0);
11340 SDValue N1 = N->getOperand(1);
11342 assert(N0.getValueType() == VT && "Vector shuffle must be normalized in DAG");
11344 // Canonicalize shuffle undef, undef -> undef
11345 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
11346 return DAG.getUNDEF(VT);
11348 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
11350 // Canonicalize shuffle v, v -> v, undef
11351 if (N0 == N1) {
11352 SmallVector<int, 8> NewMask;
11353 for (unsigned i = 0; i != NumElts; ++i) {
11354 int Idx = SVN->getMaskElt(i);
11355 if (Idx >= (int)NumElts) Idx -= NumElts;
11356 NewMask.push_back(Idx);
11357 }
11358 return DAG.getVectorShuffle(VT, SDLoc(N), N0, DAG.getUNDEF(VT),
11359 &NewMask[0]);
11360 }
11362 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask.
11363 if (N0.getOpcode() == ISD::UNDEF) {
11364 SmallVector<int, 8> NewMask;
11365 for (unsigned i = 0; i != NumElts; ++i) {
11366 int Idx = SVN->getMaskElt(i);
11367 if (Idx >= 0) {
11368 if (Idx >= (int)NumElts)
11369 Idx -= NumElts;
11370 else
11371 Idx = -1; // remove reference to lhs
11372 }
11373 NewMask.push_back(Idx);
11374 }
11375 return DAG.getVectorShuffle(VT, SDLoc(N), N1, DAG.getUNDEF(VT),
11376 &NewMask[0]);
11377 }
11379 // Remove references to rhs if it is undef
11380 if (N1.getOpcode() == ISD::UNDEF) {
11381 bool Changed = false;
11382 SmallVector<int, 8> NewMask;
11383 for (unsigned i = 0; i != NumElts; ++i) {
11384 int Idx = SVN->getMaskElt(i);
11385 if (Idx >= (int)NumElts) {
11386 Idx = -1;
11387 Changed = true;
11388 }
11389 NewMask.push_back(Idx);
11390 }
11391 if (Changed)
11392 return DAG.getVectorShuffle(VT, SDLoc(N), N0, N1, &NewMask[0]);
11393 }
11395 // If it is a splat, check if the argument vector is another splat or a
11396 // build_vector with all scalar elements the same.
11397 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) {
11398 SDNode *V = N0.getNode();
11400 // If this is a bit convert that changes the element type of the vector but
11401 // not the number of vector elements, look through it. Be careful not to
11402 // look though conversions that change things like v4f32 to v2f64.
11403 if (V->getOpcode() == ISD::BITCAST) {
11404 SDValue ConvInput = V->getOperand(0);
11405 if (ConvInput.getValueType().isVector() &&
11406 ConvInput.getValueType().getVectorNumElements() == NumElts)
11407 V = ConvInput.getNode();
11408 }
11410 if (V->getOpcode() == ISD::BUILD_VECTOR) {
11411 assert(V->getNumOperands() == NumElts &&
11412 "BUILD_VECTOR has wrong number of operands");
11413 SDValue Base;
11414 bool AllSame = true;
11415 for (unsigned i = 0; i != NumElts; ++i) {
11416 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
11417 Base = V->getOperand(i);
11418 break;
11419 }
11420 }
11421 // Splat of <u, u, u, u>, return <u, u, u, u>
11422 if (!Base.getNode())
11423 return N0;
11424 for (unsigned i = 0; i != NumElts; ++i) {
11425 if (V->getOperand(i) != Base) {
11426 AllSame = false;
11427 break;
11428 }
11429 }
11430 // Splat of <x, x, x, x>, return <x, x, x, x>
11431 if (AllSame)
11432 return N0;
11433 }
11434 }
11436 // There are various patterns used to build up a vector from smaller vectors,
11437 // subvectors, or elements. Scan chains of these and replace unused insertions
11438 // or components with undef.
11439 if (SDValue S = simplifyShuffleOperands(SVN, N0, N1, DAG))
11440 return S;
11442 if (N0.getOpcode() == ISD::CONCAT_VECTORS &&
11443 Level < AfterLegalizeVectorOps &&
11444 (N1.getOpcode() == ISD::UNDEF ||
11445 (N1.getOpcode() == ISD::CONCAT_VECTORS &&
11446 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()))) {
11447 SDValue V = partitionShuffleOfConcats(N, DAG);
11449 if (V.getNode())
11450 return V;
11451 }
11453 // Canonicalize shuffles according to rules:
11454 // shuffle(A, shuffle(A, B)) -> shuffle(shuffle(A,B), A)
11455 // shuffle(B, shuffle(A, B)) -> shuffle(shuffle(A,B), B)
11456 // shuffle(B, shuffle(A, Undef)) -> shuffle(shuffle(A, Undef), B)
11457 if (N1.getOpcode() == ISD::VECTOR_SHUFFLE &&
11458 N0.getOpcode() != ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
11459 TLI.isTypeLegal(VT)) {
11460 // The incoming shuffle must be of the same type as the result of the
11461 // current shuffle.
11462 assert(N1->getOperand(0).getValueType() == VT &&
11463 "Shuffle types don't match");
11465 SDValue SV0 = N1->getOperand(0);
11466 SDValue SV1 = N1->getOperand(1);
11467 bool HasSameOp0 = N0 == SV0;
11468 bool IsSV1Undef = SV1.getOpcode() == ISD::UNDEF;
11469 if (HasSameOp0 || IsSV1Undef || N0 == SV1)
11470 // Commute the operands of this shuffle so that next rule
11471 // will trigger.
11472 return DAG.getCommutedVectorShuffle(*SVN);
11473 }
11475 // Try to fold according to rules:
11476 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(A, B, M2)
11477 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(A, C, M2)
11478 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(B, C, M2)
11479 // Don't try to fold shuffles with illegal type.
11480 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
11481 TLI.isTypeLegal(VT)) {
11482 ShuffleVectorSDNode *OtherSV = cast<ShuffleVectorSDNode>(N0);
11484 // The incoming shuffle must be of the same type as the result of the
11485 // current shuffle.
11486 assert(OtherSV->getOperand(0).getValueType() == VT &&
11487 "Shuffle types don't match");
11489 SDValue SV0, SV1;
11490 SmallVector<int, 4> Mask;
11491 // Compute the combined shuffle mask for a shuffle with SV0 as the first
11492 // operand, and SV1 as the second operand.
11493 for (unsigned i = 0; i != NumElts; ++i) {
11494 int Idx = SVN->getMaskElt(i);
11495 if (Idx < 0) {
11496 // Propagate Undef.
11497 Mask.push_back(Idx);
11498 continue;
11499 }
11501 SDValue CurrentVec;
11502 if (Idx < (int)NumElts) {
11503 // This shuffle index refers to the inner shuffle N0. Lookup the inner
11504 // shuffle mask to identify which vector is actually referenced.
11505 Idx = OtherSV->getMaskElt(Idx);
11506 if (Idx < 0) {
11507 // Propagate Undef.
11508 Mask.push_back(Idx);
11509 continue;
11510 }
11512 CurrentVec = (Idx < (int) NumElts) ? OtherSV->getOperand(0)
11513 : OtherSV->getOperand(1);
11514 } else {
11515 // This shuffle index references an element within N1.
11516 CurrentVec = N1;
11517 }
11519 // Simple case where 'CurrentVec' is UNDEF.
11520 if (CurrentVec.getOpcode() == ISD::UNDEF) {
11521 Mask.push_back(-1);
11522 continue;
11523 }
11525 // Canonicalize the shuffle index. We don't know yet if CurrentVec
11526 // will be the first or second operand of the combined shuffle.
11527 Idx = Idx % NumElts;
11528 if (!SV0.getNode() || SV0 == CurrentVec) {
11529 // Ok. CurrentVec is the left hand side.
11530 // Update the mask accordingly.
11531 SV0 = CurrentVec;
11532 Mask.push_back(Idx);
11533 continue;
11534 }
11536 // Bail out if we cannot convert the shuffle pair into a single shuffle.
11537 if (SV1.getNode() && SV1 != CurrentVec)
11538 return SDValue();
11540 // Ok. CurrentVec is the right hand side.
11541 // Update the mask accordingly.
11542 SV1 = CurrentVec;
11543 Mask.push_back(Idx + NumElts);
11544 }
11546 // Check if all indices in Mask are Undef. In case, propagate Undef.
11547 bool isUndefMask = true;
11548 for (unsigned i = 0; i != NumElts && isUndefMask; ++i)
11549 isUndefMask &= Mask[i] < 0;
11551 if (isUndefMask)
11552 return DAG.getUNDEF(VT);
11554 if (!SV0.getNode())
11555 SV0 = DAG.getUNDEF(VT);
11556 if (!SV1.getNode())
11557 SV1 = DAG.getUNDEF(VT);
11559 // Avoid introducing shuffles with illegal mask.
11560 if (!TLI.isShuffleMaskLegal(Mask, VT)) {
11561 // Compute the commuted shuffle mask and test again.
11562 for (unsigned i = 0; i != NumElts; ++i) {
11563 int idx = Mask[i];
11564 if (idx < 0)
11565 continue;
11566 else if (idx < (int)NumElts)
11567 Mask[i] = idx + NumElts;
11568 else
11569 Mask[i] = idx - NumElts;
11570 }
11572 if (!TLI.isShuffleMaskLegal(Mask, VT))
11573 return SDValue();
11575 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(B, A, M2)
11576 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(C, A, M2)
11577 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(C, B, M2)
11578 std::swap(SV0, SV1);
11579 }
11581 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(A, B, M2)
11582 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(A, C, M2)
11583 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(B, C, M2)
11584 return DAG.getVectorShuffle(VT, SDLoc(N), SV0, SV1, &Mask[0]);
11585 }
11587 return SDValue();
11588 }
11590 SDValue DAGCombiner::visitINSERT_SUBVECTOR(SDNode *N) {
11591 SDValue N0 = N->getOperand(0);
11592 SDValue N2 = N->getOperand(2);
11594 // If the input vector is a concatenation, and the insert replaces
11595 // one of the halves, we can optimize into a single concat_vectors.
11596 if (N0.getOpcode() == ISD::CONCAT_VECTORS &&
11597 N0->getNumOperands() == 2 && N2.getOpcode() == ISD::Constant) {
11598 APInt InsIdx = cast<ConstantSDNode>(N2)->getAPIntValue();
11599 EVT VT = N->getValueType(0);
11601 // Lower half: fold (insert_subvector (concat_vectors X, Y), Z) ->
11602 // (concat_vectors Z, Y)
11603 if (InsIdx == 0)
11604 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT,
11605 N->getOperand(1), N0.getOperand(1));
11607 // Upper half: fold (insert_subvector (concat_vectors X, Y), Z) ->
11608 // (concat_vectors X, Z)
11609 if (InsIdx == VT.getVectorNumElements()/2)
11610 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT,
11611 N0.getOperand(0), N->getOperand(1));
11612 }
11614 return SDValue();
11615 }
11617 /// Returns a vector_shuffle if it able to transform an AND to a vector_shuffle
11618 /// with the destination vector and a zero vector.
11619 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
11620 /// vector_shuffle V, Zero, <0, 4, 2, 4>
11621 SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
11622 EVT VT = N->getValueType(0);
11623 SDLoc dl(N);
11624 SDValue LHS = N->getOperand(0);
11625 SDValue RHS = N->getOperand(1);
11626 if (N->getOpcode() == ISD::AND) {
11627 if (RHS.getOpcode() == ISD::BITCAST)
11628 RHS = RHS.getOperand(0);
11629 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
11630 SmallVector<int, 8> Indices;
11631 unsigned NumElts = RHS.getNumOperands();
11632 for (unsigned i = 0; i != NumElts; ++i) {
11633 SDValue Elt = RHS.getOperand(i);
11634 if (!isa<ConstantSDNode>(Elt))
11635 return SDValue();
11637 if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
11638 Indices.push_back(i);
11639 else if (cast<ConstantSDNode>(Elt)->isNullValue())
11640 Indices.push_back(NumElts+i);
11641 else
11642 return SDValue();
11643 }
11645 // Let's see if the target supports this vector_shuffle.
11646 EVT RVT = RHS.getValueType();
11647 if (!TLI.isVectorClearMaskLegal(Indices, RVT))
11648 return SDValue();
11650 // Return the new VECTOR_SHUFFLE node.
11651 EVT EltVT = RVT.getVectorElementType();
11652 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(),
11653 DAG.getConstant(0, EltVT));
11654 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), RVT, ZeroOps);
11655 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS);
11656 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]);
11657 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf);
11658 }
11659 }
11661 return SDValue();
11662 }
11664 /// Visit a binary vector operation, like ADD.
11665 SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
11666 assert(N->getValueType(0).isVector() &&
11667 "SimplifyVBinOp only works on vectors!");
11669 SDValue LHS = N->getOperand(0);
11670 SDValue RHS = N->getOperand(1);
11671 SDValue Shuffle = XformToShuffleWithZero(N);
11672 if (Shuffle.getNode()) return Shuffle;
11674 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
11675 // this operation.
11676 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
11677 RHS.getOpcode() == ISD::BUILD_VECTOR) {
11678 // Check if both vectors are constants. If not bail out.
11679 if (!(cast<BuildVectorSDNode>(LHS)->isConstant() &&
11680 cast<BuildVectorSDNode>(RHS)->isConstant()))
11681 return SDValue();
11683 SmallVector<SDValue, 8> Ops;
11684 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
11685 SDValue LHSOp = LHS.getOperand(i);
11686 SDValue RHSOp = RHS.getOperand(i);
11688 // Can't fold divide by zero.
11689 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
11690 N->getOpcode() == ISD::FDIV) {
11691 if ((RHSOp.getOpcode() == ISD::Constant &&
11692 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) ||
11693 (RHSOp.getOpcode() == ISD::ConstantFP &&
11694 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero()))
11695 break;
11696 }
11698 EVT VT = LHSOp.getValueType();
11699 EVT RVT = RHSOp.getValueType();
11700 if (RVT != VT) {
11701 // Integer BUILD_VECTOR operands may have types larger than the element
11702 // size (e.g., when the element type is not legal). Prior to type
11703 // legalization, the types may not match between the two BUILD_VECTORS.
11704 // Truncate one of the operands to make them match.
11705 if (RVT.getSizeInBits() > VT.getSizeInBits()) {
11706 RHSOp = DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, RHSOp);
11707 } else {
11708 LHSOp = DAG.getNode(ISD::TRUNCATE, SDLoc(N), RVT, LHSOp);
11709 VT = RVT;
11710 }
11711 }
11712 SDValue FoldOp = DAG.getNode(N->getOpcode(), SDLoc(LHS), VT,
11713 LHSOp, RHSOp);
11714 if (FoldOp.getOpcode() != ISD::UNDEF &&
11715 FoldOp.getOpcode() != ISD::Constant &&
11716 FoldOp.getOpcode() != ISD::ConstantFP)
11717 break;
11718 Ops.push_back(FoldOp);
11719 AddToWorklist(FoldOp.getNode());
11720 }
11722 if (Ops.size() == LHS.getNumOperands())
11723 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), LHS.getValueType(), Ops);
11724 }
11726 // Type legalization might introduce new shuffles in the DAG.
11727 // Fold (VBinOp (shuffle (A, Undef, Mask)), (shuffle (B, Undef, Mask)))
11728 // -> (shuffle (VBinOp (A, B)), Undef, Mask).
11729 if (LegalTypes && isa<ShuffleVectorSDNode>(LHS) &&
11730 isa<ShuffleVectorSDNode>(RHS) && LHS.hasOneUse() && RHS.hasOneUse() &&
11731 LHS.getOperand(1).getOpcode() == ISD::UNDEF &&
11732 RHS.getOperand(1).getOpcode() == ISD::UNDEF) {
11733 ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(LHS);
11734 ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(RHS);
11736 if (SVN0->getMask().equals(SVN1->getMask())) {
11737 EVT VT = N->getValueType(0);
11738 SDValue UndefVector = LHS.getOperand(1);
11739 SDValue NewBinOp = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
11740 LHS.getOperand(0), RHS.getOperand(0));
11741 AddUsersToWorklist(N);
11742 return DAG.getVectorShuffle(VT, SDLoc(N), NewBinOp, UndefVector,
11743 &SVN0->getMask()[0]);
11744 }
11745 }
11747 return SDValue();
11748 }
11750 /// Visit a binary vector operation, like FABS/FNEG.
11751 SDValue DAGCombiner::SimplifyVUnaryOp(SDNode *N) {
11752 assert(N->getValueType(0).isVector() &&
11753 "SimplifyVUnaryOp only works on vectors!");
11755 SDValue N0 = N->getOperand(0);
11757 if (N0.getOpcode() != ISD::BUILD_VECTOR)
11758 return SDValue();
11760 // Operand is a BUILD_VECTOR node, see if we can constant fold it.
11761 SmallVector<SDValue, 8> Ops;
11762 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) {
11763 SDValue Op = N0.getOperand(i);
11764 if (Op.getOpcode() != ISD::UNDEF &&
11765 Op.getOpcode() != ISD::ConstantFP)
11766 break;
11767 EVT EltVT = Op.getValueType();
11768 SDValue FoldOp = DAG.getNode(N->getOpcode(), SDLoc(N0), EltVT, Op);
11769 if (FoldOp.getOpcode() != ISD::UNDEF &&
11770 FoldOp.getOpcode() != ISD::ConstantFP)
11771 break;
11772 Ops.push_back(FoldOp);
11773 AddToWorklist(FoldOp.getNode());
11774 }
11776 if (Ops.size() != N0.getNumOperands())
11777 return SDValue();
11779 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N0.getValueType(), Ops);
11780 }
11782 SDValue DAGCombiner::SimplifySelect(SDLoc DL, SDValue N0,
11783 SDValue N1, SDValue N2){
11784 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
11786 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
11787 cast<CondCodeSDNode>(N0.getOperand(2))->get());
11789 // If we got a simplified select_cc node back from SimplifySelectCC, then
11790 // break it down into a new SETCC node, and a new SELECT node, and then return
11791 // the SELECT node, since we were called with a SELECT node.
11792 if (SCC.getNode()) {
11793 // Check to see if we got a select_cc back (to turn into setcc/select).
11794 // Otherwise, just return whatever node we got back, like fabs.
11795 if (SCC.getOpcode() == ISD::SELECT_CC) {
11796 SDValue SETCC = DAG.getNode(ISD::SETCC, SDLoc(N0),
11797 N0.getValueType(),
11798 SCC.getOperand(0), SCC.getOperand(1),
11799 SCC.getOperand(4));
11800 AddToWorklist(SETCC.getNode());
11801 return DAG.getSelect(SDLoc(SCC), SCC.getValueType(), SETCC,
11802 SCC.getOperand(2), SCC.getOperand(3));
11803 }
11805 return SCC;
11806 }
11807 return SDValue();
11808 }
11810 /// Given a SELECT or a SELECT_CC node, where LHS and RHS are the two values
11811 /// being selected between, see if we can simplify the select. Callers of this
11812 /// should assume that TheSelect is deleted if this returns true. As such, they
11813 /// should return the appropriate thing (e.g. the node) back to the top-level of
11814 /// the DAG combiner loop to avoid it being looked at.
11815 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
11816 SDValue RHS) {
11818 // Cannot simplify select with vector condition
11819 if (TheSelect->getOperand(0).getValueType().isVector()) return false;
11821 // If this is a select from two identical things, try to pull the operation
11822 // through the select.
11823 if (LHS.getOpcode() != RHS.getOpcode() ||
11824 !LHS.hasOneUse() || !RHS.hasOneUse())
11825 return false;
11827 // If this is a load and the token chain is identical, replace the select
11828 // of two loads with a load through a select of the address to load from.
11829 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
11830 // constants have been dropped into the constant pool.
11831 if (LHS.getOpcode() == ISD::LOAD) {
11832 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
11833 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
11835 // Token chains must be identical.
11836 if (LHS.getOperand(0) != RHS.getOperand(0) ||
11837 // Do not let this transformation reduce the number of volatile loads.
11838 LLD->isVolatile() || RLD->isVolatile() ||
11839 // If this is an EXTLOAD, the VT's must match.
11840 LLD->getMemoryVT() != RLD->getMemoryVT() ||
11841 // If this is an EXTLOAD, the kind of extension must match.
11842 (LLD->getExtensionType() != RLD->getExtensionType() &&
11843 // The only exception is if one of the extensions is anyext.
11844 LLD->getExtensionType() != ISD::EXTLOAD &&
11845 RLD->getExtensionType() != ISD::EXTLOAD) ||
11846 // FIXME: this discards src value information. This is
11847 // over-conservative. It would be beneficial to be able to remember
11848 // both potential memory locations. Since we are discarding
11849 // src value info, don't do the transformation if the memory
11850 // locations are not in the default address space.
11851 LLD->getPointerInfo().getAddrSpace() != 0 ||
11852 RLD->getPointerInfo().getAddrSpace() != 0 ||
11853 !TLI.isOperationLegalOrCustom(TheSelect->getOpcode(),
11854 LLD->getBasePtr().getValueType()))
11855 return false;
11857 // Check that the select condition doesn't reach either load. If so,
11858 // folding this will induce a cycle into the DAG. If not, this is safe to
11859 // xform, so create a select of the addresses.
11860 SDValue Addr;
11861 if (TheSelect->getOpcode() == ISD::SELECT) {
11862 SDNode *CondNode = TheSelect->getOperand(0).getNode();
11863 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) ||
11864 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode)))
11865 return false;
11866 // The loads must not depend on one another.
11867 if (LLD->isPredecessorOf(RLD) ||
11868 RLD->isPredecessorOf(LLD))
11869 return false;
11870 Addr = DAG.getSelect(SDLoc(TheSelect),
11871 LLD->getBasePtr().getValueType(),
11872 TheSelect->getOperand(0), LLD->getBasePtr(),
11873 RLD->getBasePtr());
11874 } else { // Otherwise SELECT_CC
11875 SDNode *CondLHS = TheSelect->getOperand(0).getNode();
11876 SDNode *CondRHS = TheSelect->getOperand(1).getNode();
11878 if ((LLD->hasAnyUseOfValue(1) &&
11879 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) ||
11880 (RLD->hasAnyUseOfValue(1) &&
11881 (RLD->isPredecessorOf(CondLHS) || RLD->isPredecessorOf(CondRHS))))
11882 return false;
11884 Addr = DAG.getNode(ISD::SELECT_CC, SDLoc(TheSelect),
11885 LLD->getBasePtr().getValueType(),
11886 TheSelect->getOperand(0),
11887 TheSelect->getOperand(1),
11888 LLD->getBasePtr(), RLD->getBasePtr(),
11889 TheSelect->getOperand(4));
11890 }
11892 SDValue Load;
11893 // It is safe to replace the two loads if they have different alignments,
11894 // but the new load must be the minimum (most restrictive) alignment of the
11895 // inputs.
11896 bool isInvariant = LLD->isInvariant() & RLD->isInvariant();
11897 unsigned Alignment = std::min(LLD->getAlignment(), RLD->getAlignment());
11898 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
11899 Load = DAG.getLoad(TheSelect->getValueType(0),
11900 SDLoc(TheSelect),
11901 // FIXME: Discards pointer and AA info.
11902 LLD->getChain(), Addr, MachinePointerInfo(),
11903 LLD->isVolatile(), LLD->isNonTemporal(),
11904 isInvariant, Alignment);
11905 } else {
11906 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ?
11907 RLD->getExtensionType() : LLD->getExtensionType(),
11908 SDLoc(TheSelect),
11909 TheSelect->getValueType(0),
11910 // FIXME: Discards pointer and AA info.
11911 LLD->getChain(), Addr, MachinePointerInfo(),
11912 LLD->getMemoryVT(), LLD->isVolatile(),
11913 LLD->isNonTemporal(), isInvariant, Alignment);
11914 }
11916 // Users of the select now use the result of the load.
11917 CombineTo(TheSelect, Load);
11919 // Users of the old loads now use the new load's chain. We know the
11920 // old-load value is dead now.
11921 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
11922 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
11923 return true;
11924 }
11926 return false;
11927 }
11929 /// Simplify an expression of the form (N0 cond N1) ? N2 : N3
11930 /// where 'cond' is the comparison specified by CC.
11931 SDValue DAGCombiner::SimplifySelectCC(SDLoc DL, SDValue N0, SDValue N1,
11932 SDValue N2, SDValue N3,
11933 ISD::CondCode CC, bool NotExtCompare) {
11934 // (x ? y : y) -> y.
11935 if (N2 == N3) return N2;
11937 EVT VT = N2.getValueType();
11938 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
11939 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
11940 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
11942 // Determine if the condition we're dealing with is constant
11943 SDValue SCC = SimplifySetCC(getSetCCResultType(N0.getValueType()),
11944 N0, N1, CC, DL, false);
11945 if (SCC.getNode()) AddToWorklist(SCC.getNode());
11946 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
11948 // fold select_cc true, x, y -> x
11949 if (SCCC && !SCCC->isNullValue())
11950 return N2;
11951 // fold select_cc false, x, y -> y
11952 if (SCCC && SCCC->isNullValue())
11953 return N3;
11955 // Check to see if we can simplify the select into an fabs node
11956 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
11957 // Allow either -0.0 or 0.0
11958 if (CFP->getValueAPF().isZero()) {
11959 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
11960 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
11961 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
11962 N2 == N3.getOperand(0))
11963 return DAG.getNode(ISD::FABS, DL, VT, N0);
11965 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
11966 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
11967 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
11968 N2.getOperand(0) == N3)
11969 return DAG.getNode(ISD::FABS, DL, VT, N3);
11970 }
11971 }
11973 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)"
11974 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0
11975 // in it. This is a win when the constant is not otherwise available because
11976 // it replaces two constant pool loads with one. We only do this if the FP
11977 // type is known to be legal, because if it isn't, then we are before legalize
11978 // types an we want the other legalization to happen first (e.g. to avoid
11979 // messing with soft float) and if the ConstantFP is not legal, because if
11980 // it is legal, we may not need to store the FP constant in a constant pool.
11981 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2))
11982 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) {
11983 if (TLI.isTypeLegal(N2.getValueType()) &&
11984 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) !=
11985 TargetLowering::Legal &&
11986 !TLI.isFPImmLegal(TV->getValueAPF(), TV->getValueType(0)) &&
11987 !TLI.isFPImmLegal(FV->getValueAPF(), FV->getValueType(0))) &&
11988 // If both constants have multiple uses, then we won't need to do an
11989 // extra load, they are likely around in registers for other users.
11990 (TV->hasOneUse() || FV->hasOneUse())) {
11991 Constant *Elts[] = {
11992 const_cast<ConstantFP*>(FV->getConstantFPValue()),
11993 const_cast<ConstantFP*>(TV->getConstantFPValue())
11994 };
11995 Type *FPTy = Elts[0]->getType();
11996 const DataLayout &TD = *TLI.getDataLayout();
11998 // Create a ConstantArray of the two constants.
11999 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts);
12000 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(),
12001 TD.getPrefTypeAlignment(FPTy));
12002 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
12004 // Get the offsets to the 0 and 1 element of the array so that we can
12005 // select between them.
12006 SDValue Zero = DAG.getIntPtrConstant(0);
12007 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType());
12008 SDValue One = DAG.getIntPtrConstant(EltSize);
12010 SDValue Cond = DAG.getSetCC(DL,
12011 getSetCCResultType(N0.getValueType()),
12012 N0, N1, CC);
12013 AddToWorklist(Cond.getNode());
12014 SDValue CstOffset = DAG.getSelect(DL, Zero.getValueType(),
12015 Cond, One, Zero);
12016 AddToWorklist(CstOffset.getNode());
12017 CPIdx = DAG.getNode(ISD::ADD, DL, CPIdx.getValueType(), CPIdx,
12018 CstOffset);
12019 AddToWorklist(CPIdx.getNode());
12020 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx,
12021 MachinePointerInfo::getConstantPool(), false,
12022 false, false, Alignment);
12024 }
12025 }
12027 // Check to see if we can perform the "gzip trick", transforming
12028 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A)
12029 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
12030 (N1C->isNullValue() || // (a < 0) ? b : 0
12031 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
12032 EVT XType = N0.getValueType();
12033 EVT AType = N2.getValueType();
12034 if (XType.bitsGE(AType)) {
12035 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
12036 // single-bit constant.
12037 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) {
12038 unsigned ShCtV = N2C->getAPIntValue().logBase2();
12039 ShCtV = XType.getSizeInBits()-ShCtV-1;
12040 SDValue ShCt = DAG.getConstant(ShCtV,
12041 getShiftAmountTy(N0.getValueType()));
12042 SDValue Shift = DAG.getNode(ISD::SRL, SDLoc(N0),
12043 XType, N0, ShCt);
12044 AddToWorklist(Shift.getNode());
12046 if (XType.bitsGT(AType)) {
12047 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
12048 AddToWorklist(Shift.getNode());
12049 }
12051 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
12052 }
12054 SDValue Shift = DAG.getNode(ISD::SRA, SDLoc(N0),
12055 XType, N0,
12056 DAG.getConstant(XType.getSizeInBits()-1,
12057 getShiftAmountTy(N0.getValueType())));
12058 AddToWorklist(Shift.getNode());
12060 if (XType.bitsGT(AType)) {
12061 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
12062 AddToWorklist(Shift.getNode());
12063 }
12065 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
12066 }
12067 }
12069 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A)
12070 // where y is has a single bit set.
12071 // A plaintext description would be, we can turn the SELECT_CC into an AND
12072 // when the condition can be materialized as an all-ones register. Any
12073 // single bit-test can be materialized as an all-ones register with
12074 // shift-left and shift-right-arith.
12075 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND &&
12076 N0->getValueType(0) == VT &&
12077 N1C && N1C->isNullValue() &&
12078 N2C && N2C->isNullValue()) {
12079 SDValue AndLHS = N0->getOperand(0);
12080 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1));
12081 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) {
12082 // Shift the tested bit over the sign bit.
12083 APInt AndMask = ConstAndRHS->getAPIntValue();
12084 SDValue ShlAmt =
12085 DAG.getConstant(AndMask.countLeadingZeros(),
12086 getShiftAmountTy(AndLHS.getValueType()));
12087 SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(N0), VT, AndLHS, ShlAmt);
12089 // Now arithmetic right shift it all the way over, so the result is either
12090 // all-ones, or zero.
12091 SDValue ShrAmt =
12092 DAG.getConstant(AndMask.getBitWidth()-1,
12093 getShiftAmountTy(Shl.getValueType()));
12094 SDValue Shr = DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl, ShrAmt);
12096 return DAG.getNode(ISD::AND, DL, VT, Shr, N3);
12097 }
12098 }
12100 // fold select C, 16, 0 -> shl C, 4
12101 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
12102 TLI.getBooleanContents(N0.getValueType()) ==
12103 TargetLowering::ZeroOrOneBooleanContent) {
12105 // If the caller doesn't want us to simplify this into a zext of a compare,
12106 // don't do it.
12107 if (NotExtCompare && N2C->getAPIntValue() == 1)
12108 return SDValue();
12110 // Get a SetCC of the condition
12111 // NOTE: Don't create a SETCC if it's not legal on this target.
12112 if (!LegalOperations ||
12113 TLI.isOperationLegal(ISD::SETCC,
12114 LegalTypes ? getSetCCResultType(N0.getValueType()) : MVT::i1)) {
12115 SDValue Temp, SCC;
12116 // cast from setcc result type to select result type
12117 if (LegalTypes) {
12118 SCC = DAG.getSetCC(DL, getSetCCResultType(N0.getValueType()),
12119 N0, N1, CC);
12120 if (N2.getValueType().bitsLT(SCC.getValueType()))
12121 Temp = DAG.getZeroExtendInReg(SCC, SDLoc(N2),
12122 N2.getValueType());
12123 else
12124 Temp = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N2),
12125 N2.getValueType(), SCC);
12126 } else {
12127 SCC = DAG.getSetCC(SDLoc(N0), MVT::i1, N0, N1, CC);
12128 Temp = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N2),
12129 N2.getValueType(), SCC);
12130 }
12132 AddToWorklist(SCC.getNode());
12133 AddToWorklist(Temp.getNode());
12135 if (N2C->getAPIntValue() == 1)
12136 return Temp;
12138 // shl setcc result by log2 n2c
12139 return DAG.getNode(
12140 ISD::SHL, DL, N2.getValueType(), Temp,
12141 DAG.getConstant(N2C->getAPIntValue().logBase2(),
12142 getShiftAmountTy(Temp.getValueType())));
12143 }
12144 }
12146 // Check to see if this is the equivalent of setcc
12147 // FIXME: Turn all of these into setcc if setcc if setcc is legal
12148 // otherwise, go ahead with the folds.
12149 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
12150 EVT XType = N0.getValueType();
12151 if (!LegalOperations ||
12152 TLI.isOperationLegal(ISD::SETCC, getSetCCResultType(XType))) {
12153 SDValue Res = DAG.getSetCC(DL, getSetCCResultType(XType), N0, N1, CC);
12154 if (Res.getValueType() != VT)
12155 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
12156 return Res;
12157 }
12159 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X))))
12160 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
12161 (!LegalOperations ||
12162 TLI.isOperationLegal(ISD::CTLZ, XType))) {
12163 SDValue Ctlz = DAG.getNode(ISD::CTLZ, SDLoc(N0), XType, N0);
12164 return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
12165 DAG.getConstant(Log2_32(XType.getSizeInBits()),
12166 getShiftAmountTy(Ctlz.getValueType())));
12167 }
12168 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1))
12169 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
12170 SDValue NegN0 = DAG.getNode(ISD::SUB, SDLoc(N0),
12171 XType, DAG.getConstant(0, XType), N0);
12172 SDValue NotN0 = DAG.getNOT(SDLoc(N0), N0, XType);
12173 return DAG.getNode(ISD::SRL, DL, XType,
12174 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0),
12175 DAG.getConstant(XType.getSizeInBits()-1,
12176 getShiftAmountTy(XType)));
12177 }
12178 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1))
12179 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
12180 SDValue Sign = DAG.getNode(ISD::SRL, SDLoc(N0), XType, N0,
12181 DAG.getConstant(XType.getSizeInBits()-1,
12182 getShiftAmountTy(N0.getValueType())));
12183 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType));
12184 }
12185 }
12187 // Check to see if this is an integer abs.
12188 // select_cc setg[te] X, 0, X, -X ->
12189 // select_cc setgt X, -1, X, -X ->
12190 // select_cc setl[te] X, 0, -X, X ->
12191 // select_cc setlt X, 1, -X, X ->
12192 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
12193 if (N1C) {
12194 ConstantSDNode *SubC = nullptr;
12195 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
12196 (N1C->isAllOnesValue() && CC == ISD::SETGT)) &&
12197 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1))
12198 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0));
12199 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) ||
12200 (N1C->isOne() && CC == ISD::SETLT)) &&
12201 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1))
12202 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0));
12204 EVT XType = N0.getValueType();
12205 if (SubC && SubC->isNullValue() && XType.isInteger()) {
12206 SDValue Shift = DAG.getNode(ISD::SRA, SDLoc(N0), XType,
12207 N0,
12208 DAG.getConstant(XType.getSizeInBits()-1,
12209 getShiftAmountTy(N0.getValueType())));
12210 SDValue Add = DAG.getNode(ISD::ADD, SDLoc(N0),
12211 XType, N0, Shift);
12212 AddToWorklist(Shift.getNode());
12213 AddToWorklist(Add.getNode());
12214 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
12215 }
12216 }
12218 return SDValue();
12219 }
12221 /// This is a stub for TargetLowering::SimplifySetCC.
12222 SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0,
12223 SDValue N1, ISD::CondCode Cond,
12224 SDLoc DL, bool foldBooleans) {
12225 TargetLowering::DAGCombinerInfo
12226 DagCombineInfo(DAG, Level, false, this);
12227 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
12228 }
12230 /// Given an ISD::SDIV node expressing a divide by constant, return
12231 /// a DAG expression to select that will generate the same value by multiplying
12232 /// by a magic number.
12233 /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
12234 SDValue DAGCombiner::BuildSDIV(SDNode *N) {
12235 ConstantSDNode *C = isConstOrConstSplat(N->getOperand(1));
12236 if (!C)
12237 return SDValue();
12239 // Avoid division by zero.
12240 if (!C->getAPIntValue())
12241 return SDValue();
12243 std::vector<SDNode*> Built;
12244 SDValue S =
12245 TLI.BuildSDIV(N, C->getAPIntValue(), DAG, LegalOperations, &Built);
12247 for (SDNode *N : Built)
12248 AddToWorklist(N);
12249 return S;
12250 }
12252 /// Given an ISD::SDIV node expressing a divide by constant power of 2, return a
12253 /// DAG expression that will generate the same value by right shifting.
12254 SDValue DAGCombiner::BuildSDIVPow2(SDNode *N) {
12255 ConstantSDNode *C = isConstOrConstSplat(N->getOperand(1));
12256 if (!C)
12257 return SDValue();
12259 // Avoid division by zero.
12260 if (!C->getAPIntValue())
12261 return SDValue();
12263 std::vector<SDNode *> Built;
12264 SDValue S = TLI.BuildSDIVPow2(N, C->getAPIntValue(), DAG, &Built);
12266 for (SDNode *N : Built)
12267 AddToWorklist(N);
12268 return S;
12269 }
12271 /// Given an ISD::UDIV node expressing a divide by constant, return a DAG
12272 /// expression that will generate the same value by multiplying by a magic
12273 /// number.
12274 /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
12275 SDValue DAGCombiner::BuildUDIV(SDNode *N) {
12276 ConstantSDNode *C = isConstOrConstSplat(N->getOperand(1));
12277 if (!C)
12278 return SDValue();
12280 // Avoid division by zero.
12281 if (!C->getAPIntValue())
12282 return SDValue();
12284 std::vector<SDNode*> Built;
12285 SDValue S =
12286 TLI.BuildUDIV(N, C->getAPIntValue(), DAG, LegalOperations, &Built);
12288 for (SDNode *N : Built)
12289 AddToWorklist(N);
12290 return S;
12291 }
12293 SDValue DAGCombiner::BuildReciprocalEstimate(SDValue Op) {
12294 if (Level >= AfterLegalizeDAG)
12295 return SDValue();
12297 // Expose the DAG combiner to the target combiner implementations.
12298 TargetLowering::DAGCombinerInfo DCI(DAG, Level, false, this);
12300 unsigned Iterations = 0;
12301 if (SDValue Est = TLI.getRecipEstimate(Op, DCI, Iterations)) {
12302 if (Iterations) {
12303 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
12304 // For the reciprocal, we need to find the zero of the function:
12305 // F(X) = A X - 1 [which has a zero at X = 1/A]
12306 // =>
12307 // X_{i+1} = X_i (2 - A X_i) = X_i + X_i (1 - A X_i) [this second form
12308 // does not require additional intermediate precision]
12309 EVT VT = Op.getValueType();
12310 SDLoc DL(Op);
12311 SDValue FPOne = DAG.getConstantFP(1.0, VT);
12313 AddToWorklist(Est.getNode());
12315 // Newton iterations: Est = Est + Est (1 - Arg * Est)
12316 for (unsigned i = 0; i < Iterations; ++i) {
12317 SDValue NewEst = DAG.getNode(ISD::FMUL, DL, VT, Op, Est);
12318 AddToWorklist(NewEst.getNode());
12320 NewEst = DAG.getNode(ISD::FSUB, DL, VT, FPOne, NewEst);
12321 AddToWorklist(NewEst.getNode());
12323 NewEst = DAG.getNode(ISD::FMUL, DL, VT, Est, NewEst);
12324 AddToWorklist(NewEst.getNode());
12326 Est = DAG.getNode(ISD::FADD, DL, VT, Est, NewEst);
12327 AddToWorklist(Est.getNode());
12328 }
12329 }
12330 return Est;
12331 }
12333 return SDValue();
12334 }
12336 /// Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
12337 /// For the reciprocal sqrt, we need to find the zero of the function:
12338 /// F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)]
12339 /// =>
12340 /// X_{i+1} = X_i (1.5 - A X_i^2 / 2)
12341 /// As a result, we precompute A/2 prior to the iteration loop.
12342 SDValue DAGCombiner::BuildRsqrtNROneConst(SDValue Arg, SDValue Est,
12343 unsigned Iterations) {
12344 EVT VT = Arg.getValueType();
12345 SDLoc DL(Arg);
12346 SDValue ThreeHalves = DAG.getConstantFP(1.5, VT);
12348 // We now need 0.5 * Arg which we can write as (1.5 * Arg - Arg) so that
12349 // this entire sequence requires only one FP constant.
12350 SDValue HalfArg = DAG.getNode(ISD::FMUL, DL, VT, ThreeHalves, Arg);
12351 AddToWorklist(HalfArg.getNode());
12353 HalfArg = DAG.getNode(ISD::FSUB, DL, VT, HalfArg, Arg);
12354 AddToWorklist(HalfArg.getNode());
12356 // Newton iterations: Est = Est * (1.5 - HalfArg * Est * Est)
12357 for (unsigned i = 0; i < Iterations; ++i) {
12358 SDValue NewEst = DAG.getNode(ISD::FMUL, DL, VT, Est, Est);
12359 AddToWorklist(NewEst.getNode());
12361 NewEst = DAG.getNode(ISD::FMUL, DL, VT, HalfArg, NewEst);
12362 AddToWorklist(NewEst.getNode());
12364 NewEst = DAG.getNode(ISD::FSUB, DL, VT, ThreeHalves, NewEst);
12365 AddToWorklist(NewEst.getNode());
12367 Est = DAG.getNode(ISD::FMUL, DL, VT, Est, NewEst);
12368 AddToWorklist(Est.getNode());
12369 }
12370 return Est;
12371 }
12373 /// Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
12374 /// For the reciprocal sqrt, we need to find the zero of the function:
12375 /// F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)]
12376 /// =>
12377 /// X_{i+1} = (-0.5 * X_i) * (A * X_i * X_i + (-3.0))
12378 SDValue DAGCombiner::BuildRsqrtNRTwoConst(SDValue Arg, SDValue Est,
12379 unsigned Iterations) {
12380 EVT VT = Arg.getValueType();
12381 SDLoc DL(Arg);
12382 SDValue MinusThree = DAG.getConstantFP(-3.0, VT);
12383 SDValue MinusHalf = DAG.getConstantFP(-0.5, VT);
12385 // Newton iterations: Est = -0.5 * Est * (-3.0 + Arg * Est * Est)
12386 for (unsigned i = 0; i < Iterations; ++i) {
12387 SDValue HalfEst = DAG.getNode(ISD::FMUL, DL, VT, Est, MinusHalf);
12388 AddToWorklist(HalfEst.getNode());
12390 Est = DAG.getNode(ISD::FMUL, DL, VT, Est, Est);
12391 AddToWorklist(Est.getNode());
12393 Est = DAG.getNode(ISD::FMUL, DL, VT, Est, Arg);
12394 AddToWorklist(Est.getNode());
12396 Est = DAG.getNode(ISD::FADD, DL, VT, Est, MinusThree);
12397 AddToWorklist(Est.getNode());
12399 Est = DAG.getNode(ISD::FMUL, DL, VT, Est, HalfEst);
12400 AddToWorklist(Est.getNode());
12401 }
12402 return Est;
12403 }
12405 SDValue DAGCombiner::BuildRsqrtEstimate(SDValue Op) {
12406 if (Level >= AfterLegalizeDAG)
12407 return SDValue();
12409 // Expose the DAG combiner to the target combiner implementations.
12410 TargetLowering::DAGCombinerInfo DCI(DAG, Level, false, this);
12411 unsigned Iterations = 0;
12412 bool UseOneConstNR = false;
12413 if (SDValue Est = TLI.getRsqrtEstimate(Op, DCI, Iterations, UseOneConstNR)) {
12414 AddToWorklist(Est.getNode());
12415 if (Iterations) {
12416 Est = UseOneConstNR ?
12417 BuildRsqrtNROneConst(Op, Est, Iterations) :
12418 BuildRsqrtNRTwoConst(Op, Est, Iterations);
12419 }
12420 return Est;
12421 }
12423 return SDValue();
12424 }
12426 /// Return true if base is a frame index, which is known not to alias with
12427 /// anything but itself. Provides base object and offset as results.
12428 static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset,
12429 const GlobalValue *&GV, const void *&CV) {
12430 // Assume it is a primitive operation.
12431 Base = Ptr; Offset = 0; GV = nullptr; CV = nullptr;
12433 // If it's an adding a simple constant then integrate the offset.
12434 if (Base.getOpcode() == ISD::ADD) {
12435 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
12436 Base = Base.getOperand(0);
12437 Offset += C->getZExtValue();
12438 }
12439 }
12441 // Return the underlying GlobalValue, and update the Offset. Return false
12442 // for GlobalAddressSDNode since the same GlobalAddress may be represented
12443 // by multiple nodes with different offsets.
12444 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) {
12445 GV = G->getGlobal();
12446 Offset += G->getOffset();
12447 return false;
12448 }
12450 // Return the underlying Constant value, and update the Offset. Return false
12451 // for ConstantSDNodes since the same constant pool entry may be represented
12452 // by multiple nodes with different offsets.
12453 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) {
12454 CV = C->isMachineConstantPoolEntry() ? (const void *)C->getMachineCPVal()
12455 : (const void *)C->getConstVal();
12456 Offset += C->getOffset();
12457 return false;
12458 }
12459 // If it's any of the following then it can't alias with anything but itself.
12460 return isa<FrameIndexSDNode>(Base);
12461 }
12463 /// Return true if there is any possibility that the two addresses overlap.
12464 bool DAGCombiner::isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1) const {
12465 // If they are the same then they must be aliases.
12466 if (Op0->getBasePtr() == Op1->getBasePtr()) return true;
12468 // If they are both volatile then they cannot be reordered.
12469 if (Op0->isVolatile() && Op1->isVolatile()) return true;
12471 // Gather base node and offset information.
12472 SDValue Base1, Base2;
12473 int64_t Offset1, Offset2;
12474 const GlobalValue *GV1, *GV2;
12475 const void *CV1, *CV2;
12476 bool isFrameIndex1 = FindBaseOffset(Op0->getBasePtr(),
12477 Base1, Offset1, GV1, CV1);
12478 bool isFrameIndex2 = FindBaseOffset(Op1->getBasePtr(),
12479 Base2, Offset2, GV2, CV2);
12481 // If they have a same base address then check to see if they overlap.
12482 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2)))
12483 return !((Offset1 + (Op0->getMemoryVT().getSizeInBits() >> 3)) <= Offset2 ||
12484 (Offset2 + (Op1->getMemoryVT().getSizeInBits() >> 3)) <= Offset1);
12486 // It is possible for different frame indices to alias each other, mostly
12487 // when tail call optimization reuses return address slots for arguments.
12488 // To catch this case, look up the actual index of frame indices to compute
12489 // the real alias relationship.
12490 if (isFrameIndex1 && isFrameIndex2) {
12491 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12492 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex());
12493 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex());
12494 return !((Offset1 + (Op0->getMemoryVT().getSizeInBits() >> 3)) <= Offset2 ||
12495 (Offset2 + (Op1->getMemoryVT().getSizeInBits() >> 3)) <= Offset1);
12496 }
12498 // Otherwise, if we know what the bases are, and they aren't identical, then
12499 // we know they cannot alias.
12500 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2))
12501 return false;
12503 // If we know required SrcValue1 and SrcValue2 have relatively large alignment
12504 // compared to the size and offset of the access, we may be able to prove they
12505 // do not alias. This check is conservative for now to catch cases created by
12506 // splitting vector types.
12507 if ((Op0->getOriginalAlignment() == Op1->getOriginalAlignment()) &&
12508 (Op0->getSrcValueOffset() != Op1->getSrcValueOffset()) &&
12509 (Op0->getMemoryVT().getSizeInBits() >> 3 ==
12510 Op1->getMemoryVT().getSizeInBits() >> 3) &&
12511 (Op0->getOriginalAlignment() > Op0->getMemoryVT().getSizeInBits()) >> 3) {
12512 int64_t OffAlign1 = Op0->getSrcValueOffset() % Op0->getOriginalAlignment();
12513 int64_t OffAlign2 = Op1->getSrcValueOffset() % Op1->getOriginalAlignment();
12515 // There is no overlap between these relatively aligned accesses of similar
12516 // size, return no alias.
12517 if ((OffAlign1 + (Op0->getMemoryVT().getSizeInBits() >> 3)) <= OffAlign2 ||
12518 (OffAlign2 + (Op1->getMemoryVT().getSizeInBits() >> 3)) <= OffAlign1)
12519 return false;
12520 }
12522 bool UseAA = CombinerGlobalAA.getNumOccurrences() > 0
12523 ? CombinerGlobalAA
12524 : DAG.getSubtarget().useAA();
12525 #ifndef NDEBUG
12526 if (CombinerAAOnlyFunc.getNumOccurrences() &&
12527 CombinerAAOnlyFunc != DAG.getMachineFunction().getName())
12528 UseAA = false;
12529 #endif
12530 if (UseAA &&
12531 Op0->getMemOperand()->getValue() && Op1->getMemOperand()->getValue()) {
12532 // Use alias analysis information.
12533 int64_t MinOffset = std::min(Op0->getSrcValueOffset(),
12534 Op1->getSrcValueOffset());
12535 int64_t Overlap1 = (Op0->getMemoryVT().getSizeInBits() >> 3) +
12536 Op0->getSrcValueOffset() - MinOffset;
12537 int64_t Overlap2 = (Op1->getMemoryVT().getSizeInBits() >> 3) +
12538 Op1->getSrcValueOffset() - MinOffset;
12539 AliasAnalysis::AliasResult AAResult =
12540 AA.alias(AliasAnalysis::Location(Op0->getMemOperand()->getValue(),
12541 Overlap1,
12542 UseTBAA ? Op0->getAAInfo() : AAMDNodes()),
12543 AliasAnalysis::Location(Op1->getMemOperand()->getValue(),
12544 Overlap2,
12545 UseTBAA ? Op1->getAAInfo() : AAMDNodes()));
12546 if (AAResult == AliasAnalysis::NoAlias)
12547 return false;
12548 }
12550 // Otherwise we have to assume they alias.
12551 return true;
12552 }
12554 /// Walk up chain skipping non-aliasing memory nodes,
12555 /// looking for aliasing nodes and adding them to the Aliases vector.
12556 void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
12557 SmallVectorImpl<SDValue> &Aliases) {
12558 SmallVector<SDValue, 8> Chains; // List of chains to visit.
12559 SmallPtrSet<SDNode *, 16> Visited; // Visited node set.
12561 // Get alias information for node.
12562 bool IsLoad = isa<LoadSDNode>(N) && !cast<LSBaseSDNode>(N)->isVolatile();
12564 // Starting off.
12565 Chains.push_back(OriginalChain);
12566 unsigned Depth = 0;
12568 // Look at each chain and determine if it is an alias. If so, add it to the
12569 // aliases list. If not, then continue up the chain looking for the next
12570 // candidate.
12571 while (!Chains.empty()) {
12572 SDValue Chain = Chains.back();
12573 Chains.pop_back();
12575 // For TokenFactor nodes, look at each operand and only continue up the
12576 // chain until we find two aliases. If we've seen two aliases, assume we'll
12577 // find more and revert to original chain since the xform is unlikely to be
12578 // profitable.
12579 //
12580 // FIXME: The depth check could be made to return the last non-aliasing
12581 // chain we found before we hit a tokenfactor rather than the original
12582 // chain.
12583 if (Depth > 6 || Aliases.size() == 2) {
12584 Aliases.clear();
12585 Aliases.push_back(OriginalChain);
12586 return;
12587 }
12589 // Don't bother if we've been before.
12590 if (!Visited.insert(Chain.getNode()).second)
12591 continue;
12593 switch (Chain.getOpcode()) {
12594 case ISD::EntryToken:
12595 // Entry token is ideal chain operand, but handled in FindBetterChain.
12596 break;
12598 case ISD::LOAD:
12599 case ISD::STORE: {
12600 // Get alias information for Chain.
12601 bool IsOpLoad = isa<LoadSDNode>(Chain.getNode()) &&
12602 !cast<LSBaseSDNode>(Chain.getNode())->isVolatile();
12604 // If chain is alias then stop here.
12605 if (!(IsLoad && IsOpLoad) &&
12606 isAlias(cast<LSBaseSDNode>(N), cast<LSBaseSDNode>(Chain.getNode()))) {
12607 Aliases.push_back(Chain);
12608 } else {
12609 // Look further up the chain.
12610 Chains.push_back(Chain.getOperand(0));
12611 ++Depth;
12612 }
12613 break;
12614 }
12616 case ISD::TokenFactor:
12617 // We have to check each of the operands of the token factor for "small"
12618 // token factors, so we queue them up. Adding the operands to the queue
12619 // (stack) in reverse order maintains the original order and increases the
12620 // likelihood that getNode will find a matching token factor (CSE.)
12621 if (Chain.getNumOperands() > 16) {
12622 Aliases.push_back(Chain);
12623 break;
12624 }
12625 for (unsigned n = Chain.getNumOperands(); n;)
12626 Chains.push_back(Chain.getOperand(--n));
12627 ++Depth;
12628 break;
12630 default:
12631 // For all other instructions we will just have to take what we can get.
12632 Aliases.push_back(Chain);
12633 break;
12634 }
12635 }
12637 // We need to be careful here to also search for aliases through the
12638 // value operand of a store, etc. Consider the following situation:
12639 // Token1 = ...
12640 // L1 = load Token1, %52
12641 // S1 = store Token1, L1, %51
12642 // L2 = load Token1, %52+8
12643 // S2 = store Token1, L2, %51+8
12644 // Token2 = Token(S1, S2)
12645 // L3 = load Token2, %53
12646 // S3 = store Token2, L3, %52
12647 // L4 = load Token2, %53+8
12648 // S4 = store Token2, L4, %52+8
12649 // If we search for aliases of S3 (which loads address %52), and we look
12650 // only through the chain, then we'll miss the trivial dependence on L1
12651 // (which also loads from %52). We then might change all loads and
12652 // stores to use Token1 as their chain operand, which could result in
12653 // copying %53 into %52 before copying %52 into %51 (which should
12654 // happen first).
12655 //
12656 // The problem is, however, that searching for such data dependencies
12657 // can become expensive, and the cost is not directly related to the
12658 // chain depth. Instead, we'll rule out such configurations here by
12659 // insisting that we've visited all chain users (except for users
12660 // of the original chain, which is not necessary). When doing this,
12661 // we need to look through nodes we don't care about (otherwise, things
12662 // like register copies will interfere with trivial cases).
12664 SmallVector<const SDNode *, 16> Worklist;
12665 for (const SDNode *N : Visited)
12666 if (N != OriginalChain.getNode())
12667 Worklist.push_back(N);
12669 while (!Worklist.empty()) {
12670 const SDNode *M = Worklist.pop_back_val();
12672 // We have already visited M, and want to make sure we've visited any uses
12673 // of M that we care about. For uses that we've not visisted, and don't
12674 // care about, queue them to the worklist.
12676 for (SDNode::use_iterator UI = M->use_begin(),
12677 UIE = M->use_end(); UI != UIE; ++UI)
12678 if (UI.getUse().getValueType() == MVT::Other &&
12679 Visited.insert(*UI).second) {
12680 if (isa<MemIntrinsicSDNode>(*UI) || isa<MemSDNode>(*UI)) {
12681 // We've not visited this use, and we care about it (it could have an
12682 // ordering dependency with the original node).
12683 Aliases.clear();
12684 Aliases.push_back(OriginalChain);
12685 return;
12686 }
12688 // We've not visited this use, but we don't care about it. Mark it as
12689 // visited and enqueue it to the worklist.
12690 Worklist.push_back(*UI);
12691 }
12692 }
12693 }
12695 /// Walk up chain skipping non-aliasing memory nodes, looking for a better chain
12696 /// (aliasing node.)
12697 SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
12698 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor.
12700 // Accumulate all the aliases to this node.
12701 GatherAllAliases(N, OldChain, Aliases);
12703 // If no operands then chain to entry token.
12704 if (Aliases.size() == 0)
12705 return DAG.getEntryNode();
12707 // If a single operand then chain to it. We don't need to revisit it.
12708 if (Aliases.size() == 1)
12709 return Aliases[0];
12711 // Construct a custom tailored token factor.
12712 return DAG.getNode(ISD::TokenFactor, SDLoc(N), MVT::Other, Aliases);
12713 }
12715 /// This is the entry point for the file.
12716 void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
12717 CodeGenOpt::Level OptLevel) {
12718 /// This is the main entry point to this class.
12719 DAGCombiner(*this, AA, OptLevel).Run(Level);
12720 }