1 //==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This implements the Emit routines for the SelectionDAG class, which creates
11 // MachineInstrs based on the decisions of the SelectionDAG instruction
12 // selection.
13 //
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "instr-emitter"
17 #include "InstrEmitter.h"
18 #include "SDNodeDbgValue.h"
19 #include "llvm/CodeGen/MachineConstantPool.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/Target/TargetData.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Target/TargetInstrInfo.h"
26 #include "llvm/Target/TargetLowering.h"
27 #include "llvm/ADT/Statistic.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/MathExtras.h"
31 using namespace llvm;
33 /// MinRCSize - Smallest register class we allow when constraining virtual
34 /// registers. If satisfying all register class constraints would require
35 /// using a smaller register class, emit a COPY to a new virtual register
36 /// instead.
37 const unsigned MinRCSize = 4;
39 /// CountResults - The results of target nodes have register or immediate
40 /// operands first, then an optional chain, and optional glue operands (which do
41 /// not go into the resulting MachineInstr).
42 unsigned InstrEmitter::CountResults(SDNode *Node) {
43 unsigned N = Node->getNumValues();
44 while (N && Node->getValueType(N - 1) == MVT::Glue)
45 --N;
46 if (N && Node->getValueType(N - 1) == MVT::Other)
47 --N; // Skip over chain result.
48 return N;
49 }
51 /// CountOperands - The inputs to target nodes have any actual inputs first,
52 /// followed by an optional chain operand, then an optional glue operand.
53 /// Compute the number of actual operands that will go into the resulting
54 /// MachineInstr.
55 unsigned InstrEmitter::CountOperands(SDNode *Node) {
56 unsigned N = Node->getNumOperands();
57 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
58 --N;
59 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
60 --N; // Ignore chain if it exists.
61 return N;
62 }
64 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
65 /// implicit physical register output.
66 void InstrEmitter::
67 EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
68 unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) {
69 unsigned VRBase = 0;
70 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
71 // Just use the input register directly!
72 SDValue Op(Node, ResNo);
73 if (IsClone)
74 VRBaseMap.erase(Op);
75 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
76 (void)isNew; // Silence compiler warning.
77 assert(isNew && "Node emitted out of order - early");
78 return;
79 }
81 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
82 // the CopyToReg'd destination register instead of creating a new vreg.
83 bool MatchReg = true;
84 const TargetRegisterClass *UseRC = NULL;
85 EVT VT = Node->getValueType(ResNo);
87 // Stick to the preferred register classes for legal types.
88 if (TLI->isTypeLegal(VT))
89 UseRC = TLI->getRegClassFor(VT);
91 if (!IsClone && !IsCloned)
92 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
93 UI != E; ++UI) {
94 SDNode *User = *UI;
95 bool Match = true;
96 if (User->getOpcode() == ISD::CopyToReg &&
97 User->getOperand(2).getNode() == Node &&
98 User->getOperand(2).getResNo() == ResNo) {
99 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
100 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
101 VRBase = DestReg;
102 Match = false;
103 } else if (DestReg != SrcReg)
104 Match = false;
105 } else {
106 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
107 SDValue Op = User->getOperand(i);
108 if (Op.getNode() != Node || Op.getResNo() != ResNo)
109 continue;
110 EVT VT = Node->getValueType(Op.getResNo());
111 if (VT == MVT::Other || VT == MVT::Glue)
112 continue;
113 Match = false;
114 if (User->isMachineOpcode()) {
115 const MCInstrDesc &II = TII->get(User->getMachineOpcode());
116 const TargetRegisterClass *RC = 0;
117 if (i+II.getNumDefs() < II.getNumOperands()) {
118 RC = TRI->getAllocatableClass(
119 TII->getRegClass(II, i+II.getNumDefs(), TRI));
120 }
121 if (!UseRC)
122 UseRC = RC;
123 else if (RC) {
124 const TargetRegisterClass *ComRC =
125 TRI->getCommonSubClass(UseRC, RC);
126 // If multiple uses expect disjoint register classes, we emit
127 // copies in AddRegisterOperand.
128 if (ComRC)
129 UseRC = ComRC;
130 }
131 }
132 }
133 }
134 MatchReg &= Match;
135 if (VRBase)
136 break;
137 }
139 const TargetRegisterClass *SrcRC = 0, *DstRC = 0;
140 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
142 // Figure out the register class to create for the destreg.
143 if (VRBase) {
144 DstRC = MRI->getRegClass(VRBase);
145 } else if (UseRC) {
146 assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!");
147 DstRC = UseRC;
148 } else {
149 DstRC = TLI->getRegClassFor(VT);
150 }
152 // If all uses are reading from the src physical register and copying the
153 // register is either impossible or very expensive, then don't create a copy.
154 if (MatchReg && SrcRC->getCopyCost() < 0) {
155 VRBase = SrcReg;
156 } else {
157 // Create the reg, emit the copy.
158 VRBase = MRI->createVirtualRegister(DstRC);
159 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
160 VRBase).addReg(SrcReg);
161 }
163 SDValue Op(Node, ResNo);
164 if (IsClone)
165 VRBaseMap.erase(Op);
166 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
167 (void)isNew; // Silence compiler warning.
168 assert(isNew && "Node emitted out of order - early");
169 }
171 /// getDstOfCopyToRegUse - If the only use of the specified result number of
172 /// node is a CopyToReg, return its destination register. Return 0 otherwise.
173 unsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node,
174 unsigned ResNo) const {
175 if (!Node->hasOneUse())
176 return 0;
178 SDNode *User = *Node->use_begin();
179 if (User->getOpcode() == ISD::CopyToReg &&
180 User->getOperand(2).getNode() == Node &&
181 User->getOperand(2).getResNo() == ResNo) {
182 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
183 if (TargetRegisterInfo::isVirtualRegister(Reg))
184 return Reg;
185 }
186 return 0;
187 }
189 void InstrEmitter::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
190 const MCInstrDesc &II,
191 bool IsClone, bool IsCloned,
192 DenseMap<SDValue, unsigned> &VRBaseMap) {
193 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
194 "IMPLICIT_DEF should have been handled as a special case elsewhere!");
196 for (unsigned i = 0; i < II.getNumDefs(); ++i) {
197 // If the specific node value is only used by a CopyToReg and the dest reg
198 // is a vreg in the same register class, use the CopyToReg'd destination
199 // register instead of creating a new vreg.
200 unsigned VRBase = 0;
201 const TargetRegisterClass *RC =
202 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI));
203 if (II.OpInfo[i].isOptionalDef()) {
204 // Optional def must be a physical register.
205 unsigned NumResults = CountResults(Node);
206 VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg();
207 assert(TargetRegisterInfo::isPhysicalRegister(VRBase));
208 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
209 }
211 if (!VRBase && !IsClone && !IsCloned)
212 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
213 UI != E; ++UI) {
214 SDNode *User = *UI;
215 if (User->getOpcode() == ISD::CopyToReg &&
216 User->getOperand(2).getNode() == Node &&
217 User->getOperand(2).getResNo() == i) {
218 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
219 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
220 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
221 if (RegRC == RC) {
222 VRBase = Reg;
223 MI->addOperand(MachineOperand::CreateReg(Reg, true));
224 break;
225 }
226 }
227 }
228 }
230 // Create the result registers for this node and add the result regs to
231 // the machine instruction.
232 if (VRBase == 0) {
233 assert(RC && "Isn't a register operand!");
234 VRBase = MRI->createVirtualRegister(RC);
235 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
236 }
238 SDValue Op(Node, i);
239 if (IsClone)
240 VRBaseMap.erase(Op);
241 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
242 (void)isNew; // Silence compiler warning.
243 assert(isNew && "Node emitted out of order - early");
244 }
245 }
247 /// getVR - Return the virtual register corresponding to the specified result
248 /// of the specified node.
249 unsigned InstrEmitter::getVR(SDValue Op,
250 DenseMap<SDValue, unsigned> &VRBaseMap) {
251 if (Op.isMachineOpcode() &&
252 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
253 // Add an IMPLICIT_DEF instruction before every use.
254 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo());
255 // IMPLICIT_DEF can produce any type of result so its MCInstrDesc
256 // does not include operand register class info.
257 if (!VReg) {
258 const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType());
259 VReg = MRI->createVirtualRegister(RC);
260 }
261 BuildMI(*MBB, InsertPos, Op.getDebugLoc(),
262 TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
263 return VReg;
264 }
266 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
267 assert(I != VRBaseMap.end() && "Node emitted out of order - late");
268 return I->second;
269 }
272 /// AddRegisterOperand - Add the specified register as an operand to the
273 /// specified machine instr. Insert register copies if the register is
274 /// not in the required register class.
275 void
276 InstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op,
277 unsigned IIOpNum,
278 const MCInstrDesc *II,
279 DenseMap<SDValue, unsigned> &VRBaseMap,
280 bool IsDebug, bool IsClone, bool IsCloned) {
281 assert(Op.getValueType() != MVT::Other &&
282 Op.getValueType() != MVT::Glue &&
283 "Chain and glue operands should occur at end of operand list!");
284 // Get/emit the operand.
285 unsigned VReg = getVR(Op, VRBaseMap);
286 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
288 const MCInstrDesc &MCID = MI->getDesc();
289 bool isOptDef = IIOpNum < MCID.getNumOperands() &&
290 MCID.OpInfo[IIOpNum].isOptionalDef();
292 // If the instruction requires a register in a different class, create
293 // a new virtual register and copy the value into it, but first attempt to
294 // shrink VReg's register class within reason. For example, if VReg == GR32
295 // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
296 if (II) {
297 const TargetRegisterClass *DstRC = 0;
298 if (IIOpNum < II->getNumOperands())
299 DstRC = TRI->getAllocatableClass(TII->getRegClass(*II, IIOpNum, TRI));
300 assert((DstRC || (MI->isVariadic() && IIOpNum >= MCID.getNumOperands())) &&
301 "Don't have operand info for this instruction!");
302 if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) {
303 unsigned NewVReg = MRI->createVirtualRegister(DstRC);
304 BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
305 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
306 VReg = NewVReg;
307 }
308 }
310 // If this value has only one use, that use is a kill. This is a
311 // conservative approximation. InstrEmitter does trivial coalescing
312 // with CopyFromReg nodes, so don't emit kill flags for them.
313 // Avoid kill flags on Schedule cloned nodes, since there will be
314 // multiple uses.
315 // Tied operands are never killed, so we need to check that. And that
316 // means we need to determine the index of the operand.
317 bool isKill = Op.hasOneUse() &&
318 Op.getNode()->getOpcode() != ISD::CopyFromReg &&
319 !IsDebug &&
320 !(IsClone || IsCloned);
321 if (isKill) {
322 unsigned Idx = MI->getNumOperands();
323 while (Idx > 0 &&
324 MI->getOperand(Idx-1).isReg() && MI->getOperand(Idx-1).isImplicit())
325 --Idx;
326 bool isTied = MI->getDesc().getOperandConstraint(Idx, MCOI::TIED_TO) != -1;
327 if (isTied)
328 isKill = false;
329 }
331 MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef,
332 false/*isImp*/, isKill,
333 false/*isDead*/, false/*isUndef*/,
334 false/*isEarlyClobber*/,
335 0/*SubReg*/, IsDebug));
336 }
338 /// AddOperand - Add the specified operand to the specified machine instr. II
339 /// specifies the instruction information for the node, and IIOpNum is the
340 /// operand number (in the II) that we are adding. IIOpNum and II are used for
341 /// assertions only.
342 void InstrEmitter::AddOperand(MachineInstr *MI, SDValue Op,
343 unsigned IIOpNum,
344 const MCInstrDesc *II,
345 DenseMap<SDValue, unsigned> &VRBaseMap,
346 bool IsDebug, bool IsClone, bool IsCloned) {
347 if (Op.isMachineOpcode()) {
348 AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap,
349 IsDebug, IsClone, IsCloned);
350 } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
351 MI->addOperand(MachineOperand::CreateImm(C->getSExtValue()));
352 } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
353 const ConstantFP *CFP = F->getConstantFPValue();
354 MI->addOperand(MachineOperand::CreateFPImm(CFP));
355 } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
356 MI->addOperand(MachineOperand::CreateReg(R->getReg(), false));
357 } else if (RegisterMaskSDNode *RM = dyn_cast<RegisterMaskSDNode>(Op)) {
358 MI->addOperand(MachineOperand::CreateRegMask(RM->getRegMask()));
359 } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
360 MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(), TGA->getOffset(),
361 TGA->getTargetFlags()));
362 } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) {
363 MI->addOperand(MachineOperand::CreateMBB(BBNode->getBasicBlock()));
364 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
365 MI->addOperand(MachineOperand::CreateFI(FI->getIndex()));
366 } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
367 MI->addOperand(MachineOperand::CreateJTI(JT->getIndex(),
368 JT->getTargetFlags()));
369 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
370 int Offset = CP->getOffset();
371 unsigned Align = CP->getAlignment();
372 Type *Type = CP->getType();
373 // MachineConstantPool wants an explicit alignment.
374 if (Align == 0) {
375 Align = TM->getTargetData()->getPrefTypeAlignment(Type);
376 if (Align == 0) {
377 // Alignment of vector types. FIXME!
378 Align = TM->getTargetData()->getTypeAllocSize(Type);
379 }
380 }
382 unsigned Idx;
383 MachineConstantPool *MCP = MF->getConstantPool();
384 if (CP->isMachineConstantPoolEntry())
385 Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align);
386 else
387 Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align);
388 MI->addOperand(MachineOperand::CreateCPI(Idx, Offset,
389 CP->getTargetFlags()));
390 } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
391 MI->addOperand(MachineOperand::CreateES(ES->getSymbol(),
392 ES->getTargetFlags()));
393 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) {
394 MI->addOperand(MachineOperand::CreateBA(BA->getBlockAddress(),
395 BA->getTargetFlags()));
396 } else {
397 assert(Op.getValueType() != MVT::Other &&
398 Op.getValueType() != MVT::Glue &&
399 "Chain and glue operands should occur at end of operand list!");
400 AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap,
401 IsDebug, IsClone, IsCloned);
402 }
403 }
405 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
406 EVT VT, DebugLoc DL) {
407 const TargetRegisterClass *VRC = MRI->getRegClass(VReg);
408 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx);
410 // RC is a sub-class of VRC that supports SubIdx. Try to constrain VReg
411 // within reason.
412 if (RC && RC != VRC)
413 RC = MRI->constrainRegClass(VReg, RC, MinRCSize);
415 // VReg has been adjusted. It can be used with SubIdx operands now.
416 if (RC)
417 return VReg;
419 // VReg couldn't be reasonably constrained. Emit a COPY to a new virtual
420 // register instead.
421 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx);
422 assert(RC && "No legal register class for VT supports that SubIdx");
423 unsigned NewReg = MRI->createVirtualRegister(RC);
424 BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg)
425 .addReg(VReg);
426 return NewReg;
427 }
429 /// EmitSubregNode - Generate machine code for subreg nodes.
430 ///
431 void InstrEmitter::EmitSubregNode(SDNode *Node,
432 DenseMap<SDValue, unsigned> &VRBaseMap,
433 bool IsClone, bool IsCloned) {
434 unsigned VRBase = 0;
435 unsigned Opc = Node->getMachineOpcode();
437 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
438 // the CopyToReg'd destination register instead of creating a new vreg.
439 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
440 UI != E; ++UI) {
441 SDNode *User = *UI;
442 if (User->getOpcode() == ISD::CopyToReg &&
443 User->getOperand(2).getNode() == Node) {
444 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
445 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
446 VRBase = DestReg;
447 break;
448 }
449 }
450 }
452 if (Opc == TargetOpcode::EXTRACT_SUBREG) {
453 // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub. There are no
454 // constraints on the %dst register, COPY can target all legal register
455 // classes.
456 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
457 const TargetRegisterClass *TRC = TLI->getRegClassFor(Node->getValueType(0));
459 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
460 MachineInstr *DefMI = MRI->getVRegDef(VReg);
461 unsigned SrcReg, DstReg, DefSubIdx;
462 if (DefMI &&
463 TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) &&
464 SubIdx == DefSubIdx) {
465 // Optimize these:
466 // r1025 = s/zext r1024, 4
467 // r1026 = extract_subreg r1025, 4
468 // to a copy
469 // r1026 = copy r1024
470 VRBase = MRI->createVirtualRegister(TRC);
471 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
472 TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg);
473 } else {
474 // VReg may not support a SubIdx sub-register, and we may need to
475 // constrain its register class or issue a COPY to a compatible register
476 // class.
477 VReg = ConstrainForSubReg(VReg, SubIdx,
478 Node->getOperand(0).getValueType(),
479 Node->getDebugLoc());
481 // Create the destreg if it is missing.
482 if (VRBase == 0)
483 VRBase = MRI->createVirtualRegister(TRC);
485 // Create the extract_subreg machine instruction.
486 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
487 TII->get(TargetOpcode::COPY), VRBase).addReg(VReg, 0, SubIdx);
488 }
489 } else if (Opc == TargetOpcode::INSERT_SUBREG ||
490 Opc == TargetOpcode::SUBREG_TO_REG) {
491 SDValue N0 = Node->getOperand(0);
492 SDValue N1 = Node->getOperand(1);
493 SDValue N2 = Node->getOperand(2);
494 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
496 // Figure out the register class to create for the destreg. It should be
497 // the largest legal register class supporting SubIdx sub-registers.
498 // RegisterCoalescer will constrain it further if it decides to eliminate
499 // the INSERT_SUBREG instruction.
500 //
501 // %dst = INSERT_SUBREG %src, %sub, SubIdx
502 //
503 // is lowered by TwoAddressInstructionPass to:
504 //
505 // %dst = COPY %src
506 // %dst:SubIdx = COPY %sub
507 //
508 // There is no constraint on the %src register class.
509 //
510 const TargetRegisterClass *SRC = TLI->getRegClassFor(Node->getValueType(0));
511 SRC = TRI->getSubClassWithSubReg(SRC, SubIdx);
512 assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG");
514 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase)))
515 VRBase = MRI->createVirtualRegister(SRC);
517 // Create the insert_subreg or subreg_to_reg machine instruction.
518 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc));
519 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
521 // If creating a subreg_to_reg, then the first input operand
522 // is an implicit value immediate, otherwise it's a register
523 if (Opc == TargetOpcode::SUBREG_TO_REG) {
524 const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
525 MI->addOperand(MachineOperand::CreateImm(SD->getZExtValue()));
526 } else
527 AddOperand(MI, N0, 0, 0, VRBaseMap, /*IsDebug=*/false,
528 IsClone, IsCloned);
529 // Add the subregster being inserted
530 AddOperand(MI, N1, 0, 0, VRBaseMap, /*IsDebug=*/false,
531 IsClone, IsCloned);
532 MI->addOperand(MachineOperand::CreateImm(SubIdx));
533 MBB->insert(InsertPos, MI);
534 } else
535 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
537 SDValue Op(Node, 0);
538 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
539 (void)isNew; // Silence compiler warning.
540 assert(isNew && "Node emitted out of order - early");
541 }
543 /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
544 /// COPY_TO_REGCLASS is just a normal copy, except that the destination
545 /// register is constrained to be in a particular register class.
546 ///
547 void
548 InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
549 DenseMap<SDValue, unsigned> &VRBaseMap) {
550 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
552 // Create the new VReg in the destination class and emit a copy.
553 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
554 const TargetRegisterClass *DstRC =
555 TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx));
556 unsigned NewVReg = MRI->createVirtualRegister(DstRC);
557 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
558 NewVReg).addReg(VReg);
560 SDValue Op(Node, 0);
561 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
562 (void)isNew; // Silence compiler warning.
563 assert(isNew && "Node emitted out of order - early");
564 }
566 /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
567 ///
568 void InstrEmitter::EmitRegSequence(SDNode *Node,
569 DenseMap<SDValue, unsigned> &VRBaseMap,
570 bool IsClone, bool IsCloned) {
571 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
572 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
573 unsigned NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC));
574 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(),
575 TII->get(TargetOpcode::REG_SEQUENCE), NewVReg);
576 unsigned NumOps = Node->getNumOperands();
577 assert((NumOps & 1) == 1 &&
578 "REG_SEQUENCE must have an odd number of operands!");
579 const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
580 for (unsigned i = 1; i != NumOps; ++i) {
581 SDValue Op = Node->getOperand(i);
582 if ((i & 1) == 0) {
583 RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(i-1));
584 // Skip physical registers as they don't have a vreg to get and we'll
585 // insert copies for them in TwoAddressInstructionPass anyway.
586 if (!R || !TargetRegisterInfo::isPhysicalRegister(R->getReg())) {
587 unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue();
588 unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
589 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
590 const TargetRegisterClass *SRC =
591 TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);
592 if (SRC && SRC != RC) {
593 MRI->setRegClass(NewVReg, SRC);
594 RC = SRC;
595 }
596 }
597 }
598 AddOperand(MI, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false,
599 IsClone, IsCloned);
600 }
602 MBB->insert(InsertPos, MI);
603 SDValue Op(Node, 0);
604 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
605 (void)isNew; // Silence compiler warning.
606 assert(isNew && "Node emitted out of order - early");
607 }
609 /// EmitDbgValue - Generate machine instruction for a dbg_value node.
610 ///
611 MachineInstr *
612 InstrEmitter::EmitDbgValue(SDDbgValue *SD,
613 DenseMap<SDValue, unsigned> &VRBaseMap) {
614 uint64_t Offset = SD->getOffset();
615 MDNode* MDPtr = SD->getMDPtr();
616 DebugLoc DL = SD->getDebugLoc();
618 if (SD->getKind() == SDDbgValue::FRAMEIX) {
619 // Stack address; this needs to be lowered in target-dependent fashion.
620 // EmitTargetCodeForFrameDebugValue is responsible for allocation.
621 unsigned FrameIx = SD->getFrameIx();
622 return TII->emitFrameIndexDebugValue(*MF, FrameIx, Offset, MDPtr, DL);
623 }
624 // Otherwise, we're going to create an instruction here.
625 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
626 MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
627 if (SD->getKind() == SDDbgValue::SDNODE) {
628 SDNode *Node = SD->getSDNode();
629 SDValue Op = SDValue(Node, SD->getResNo());
630 // It's possible we replaced this SDNode with other(s) and therefore
631 // didn't generate code for it. It's better to catch these cases where
632 // they happen and transfer the debug info, but trying to guarantee that
633 // in all cases would be very fragile; this is a safeguard for any
634 // that were missed.
635 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
636 if (I==VRBaseMap.end())
637 MIB.addReg(0U); // undef
638 else
639 AddOperand(&*MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap,
640 /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false);
641 } else if (SD->getKind() == SDDbgValue::CONST) {
642 const Value *V = SD->getConst();
643 if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
644 if (CI->getBitWidth() > 64)
645 MIB.addCImm(CI);
646 else
647 MIB.addImm(CI->getSExtValue());
648 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
649 MIB.addFPImm(CF);
650 } else {
651 // Could be an Undef. In any case insert an Undef so we can see what we
652 // dropped.
653 MIB.addReg(0U);
654 }
655 } else {
656 // Insert an Undef so we can see what we dropped.
657 MIB.addReg(0U);
658 }
660 MIB.addImm(Offset).addMetadata(MDPtr);
661 return &*MIB;
662 }
664 /// EmitMachineNode - Generate machine code for a target-specific node and
665 /// needed dependencies.
666 ///
667 void InstrEmitter::
668 EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
669 DenseMap<SDValue, unsigned> &VRBaseMap) {
670 unsigned Opc = Node->getMachineOpcode();
672 // Handle subreg insert/extract specially
673 if (Opc == TargetOpcode::EXTRACT_SUBREG ||
674 Opc == TargetOpcode::INSERT_SUBREG ||
675 Opc == TargetOpcode::SUBREG_TO_REG) {
676 EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned);
677 return;
678 }
680 // Handle COPY_TO_REGCLASS specially.
681 if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
682 EmitCopyToRegClassNode(Node, VRBaseMap);
683 return;
684 }
686 // Handle REG_SEQUENCE specially.
687 if (Opc == TargetOpcode::REG_SEQUENCE) {
688 EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned);
689 return;
690 }
692 if (Opc == TargetOpcode::IMPLICIT_DEF)
693 // We want a unique VR for each IMPLICIT_DEF use.
694 return;
696 const MCInstrDesc &II = TII->get(Opc);
697 unsigned NumResults = CountResults(Node);
698 unsigned NodeOperands = CountOperands(Node);
699 bool HasPhysRegOuts = NumResults > II.getNumDefs() && II.getImplicitDefs()!=0;
700 #ifndef NDEBUG
701 unsigned NumMIOperands = NodeOperands + NumResults;
702 if (II.isVariadic())
703 assert(NumMIOperands >= II.getNumOperands() &&
704 "Too few operands for a variadic node!");
705 else
706 assert(NumMIOperands >= II.getNumOperands() &&
707 NumMIOperands <= II.getNumOperands()+II.getNumImplicitDefs() &&
708 "#operands for dag node doesn't match .td file!");
709 #endif
711 // Create the new machine instruction.
712 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), II);
714 // Add result register values for things that are defined by this
715 // instruction.
716 if (NumResults)
717 CreateVirtualRegisters(Node, MI, II, IsClone, IsCloned, VRBaseMap);
719 // Emit all of the actual operands of this instruction, adding them to the
720 // instruction as appropriate.
721 bool HasOptPRefs = II.getNumDefs() > NumResults;
722 assert((!HasOptPRefs || !HasPhysRegOuts) &&
723 "Unable to cope with optional defs and phys regs defs!");
724 unsigned NumSkip = HasOptPRefs ? II.getNumDefs() - NumResults : 0;
725 for (unsigned i = NumSkip; i != NodeOperands; ++i)
726 AddOperand(MI, Node->getOperand(i), i-NumSkip+II.getNumDefs(), &II,
727 VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned);
729 // Transfer all of the memory reference descriptions of this instruction.
730 MI->setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(),
731 cast<MachineSDNode>(Node)->memoperands_end());
733 // Insert the instruction into position in the block. This needs to
734 // happen before any custom inserter hook is called so that the
735 // hook knows where in the block to insert the replacement code.
736 MBB->insert(InsertPos, MI);
738 // The MachineInstr may also define physregs instead of virtregs. These
739 // physreg values can reach other instructions in different ways:
740 //
741 // 1. When there is a use of a Node value beyond the explicitly defined
742 // virtual registers, we emit a CopyFromReg for one of the implicitly
743 // defined physregs. This only happens when HasPhysRegOuts is true.
744 //
745 // 2. A CopyFromReg reading a physreg may be glued to this instruction.
746 //
747 // 3. A glued instruction may implicitly use a physreg.
748 //
749 // 4. A glued instruction may use a RegisterSDNode operand.
750 //
751 // Collect all the used physreg defs, and make sure that any unused physreg
752 // defs are marked as dead.
753 SmallVector<unsigned, 8> UsedRegs;
755 // Additional results must be physical register defs.
756 if (HasPhysRegOuts) {
757 for (unsigned i = II.getNumDefs(); i < NumResults; ++i) {
758 unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()];
759 if (!Node->hasAnyUseOfValue(i))
760 continue;
761 // This implicitly defined physreg has a use.
762 UsedRegs.push_back(Reg);
763 EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
764 }
765 }
767 // Scan the glue chain for any used physregs.
768 if (Node->getValueType(Node->getNumValues()-1) == MVT::Glue) {
769 for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) {
770 if (F->getOpcode() == ISD::CopyFromReg) {
771 UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg());
772 continue;
773 } else if (F->getOpcode() == ISD::CopyToReg) {
774 // Skip CopyToReg nodes that are internal to the glue chain.
775 continue;
776 }
777 // Collect declared implicit uses.
778 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode());
779 UsedRegs.append(MCID.getImplicitUses(),
780 MCID.getImplicitUses() + MCID.getNumImplicitUses());
781 // In addition to declared implicit uses, we must also check for
782 // direct RegisterSDNode operands.
783 for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i)
784 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) {
785 unsigned Reg = R->getReg();
786 if (TargetRegisterInfo::isPhysicalRegister(Reg))
787 UsedRegs.push_back(Reg);
788 }
789 }
790 }
792 // Finally mark unused registers as dead.
793 if (!UsedRegs.empty() || II.getImplicitDefs())
794 MI->setPhysRegsDeadExcept(UsedRegs, *TRI);
796 // Run post-isel target hook to adjust this instruction if needed.
797 #ifdef NDEBUG
798 if (II.hasPostISelHook())
799 #endif
800 TLI->AdjustInstrPostInstrSelection(MI, Node);
801 }
803 /// EmitSpecialNode - Generate machine code for a target-independent node and
804 /// needed dependencies.
805 void InstrEmitter::
806 EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
807 DenseMap<SDValue, unsigned> &VRBaseMap) {
808 switch (Node->getOpcode()) {
809 default:
810 #ifndef NDEBUG
811 Node->dump();
812 #endif
813 llvm_unreachable("This target-independent node should have been selected!");
814 case ISD::EntryToken:
815 llvm_unreachable("EntryToken should have been excluded from the schedule!");
816 case ISD::MERGE_VALUES:
817 case ISD::TokenFactor: // fall thru
818 break;
819 case ISD::CopyToReg: {
820 unsigned SrcReg;
821 SDValue SrcVal = Node->getOperand(2);
822 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
823 SrcReg = R->getReg();
824 else
825 SrcReg = getVR(SrcVal, VRBaseMap);
827 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
828 if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
829 break;
831 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
832 DestReg).addReg(SrcReg);
833 break;
834 }
835 case ISD::CopyFromReg: {
836 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
837 EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
838 break;
839 }
840 case ISD::EH_LABEL: {
841 MCSymbol *S = cast<EHLabelSDNode>(Node)->getLabel();
842 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
843 TII->get(TargetOpcode::EH_LABEL)).addSym(S);
844 break;
845 }
847 case ISD::INLINEASM: {
848 unsigned NumOps = Node->getNumOperands();
849 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
850 --NumOps; // Ignore the glue operand.
852 // Create the inline asm machine instruction.
853 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(),
854 TII->get(TargetOpcode::INLINEASM));
856 // Add the asm string as an external symbol operand.
857 SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString);
858 const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol();
859 MI->addOperand(MachineOperand::CreateES(AsmStr));
861 // Add the HasSideEffect and isAlignStack bits.
862 int64_t ExtraInfo =
863 cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))->
864 getZExtValue();
865 MI->addOperand(MachineOperand::CreateImm(ExtraInfo));
867 // Add all of the operand registers to the instruction.
868 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
869 unsigned Flags =
870 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
871 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
873 MI->addOperand(MachineOperand::CreateImm(Flags));
874 ++i; // Skip the ID value.
876 switch (InlineAsm::getKind(Flags)) {
877 default: llvm_unreachable("Bad flags!");
878 case InlineAsm::Kind_RegDef:
879 for (; NumVals; --NumVals, ++i) {
880 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
881 // FIXME: Add dead flags for physical and virtual registers defined.
882 // For now, mark physical register defs as implicit to help fast
883 // regalloc. This makes inline asm look a lot like calls.
884 MI->addOperand(MachineOperand::CreateReg(Reg, true,
885 /*isImp=*/ TargetRegisterInfo::isPhysicalRegister(Reg)));
886 }
887 break;
888 case InlineAsm::Kind_RegDefEarlyClobber:
889 case InlineAsm::Kind_Clobber:
890 for (; NumVals; --NumVals, ++i) {
891 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
892 MI->addOperand(MachineOperand::CreateReg(Reg, /*isDef=*/ true,
893 /*isImp=*/ TargetRegisterInfo::isPhysicalRegister(Reg),
894 /*isKill=*/ false,
895 /*isDead=*/ false,
896 /*isUndef=*/false,
897 /*isEarlyClobber=*/ true));
898 }
899 break;
900 case InlineAsm::Kind_RegUse: // Use of register.
901 case InlineAsm::Kind_Imm: // Immediate.
902 case InlineAsm::Kind_Mem: // Addressing mode.
903 // The addressing mode has been selected, just add all of the
904 // operands to the machine instruction.
905 for (; NumVals; --NumVals, ++i)
906 AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap,
907 /*IsDebug=*/false, IsClone, IsCloned);
908 break;
909 }
910 }
912 // Get the mdnode from the asm if it exists and add it to the instruction.
913 SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode);
914 const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD();
915 if (MD)
916 MI->addOperand(MachineOperand::CreateMetadata(MD));
918 MBB->insert(InsertPos, MI);
919 break;
920 }
921 }
922 }
924 /// InstrEmitter - Construct an InstrEmitter and set it to start inserting
925 /// at the given position in the given block.
926 InstrEmitter::InstrEmitter(MachineBasicBlock *mbb,
927 MachineBasicBlock::iterator insertpos)
928 : MF(mbb->getParent()),
929 MRI(&MF->getRegInfo()),
930 TM(&MF->getTarget()),
931 TII(TM->getInstrInfo()),
932 TRI(TM->getRegisterInfo()),
933 TLI(TM->getTargetLowering()),
934 MBB(mbb), InsertPos(insertpos) {
935 }