2ee276fccbe89fd39afedd5268826b2391d7732b
1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
11 //
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/CodeGen/Analysis.h"
26 #include "llvm/CodeGen/FastISel.h"
27 #include "llvm/CodeGen/FunctionLoweringInfo.h"
28 #include "llvm/CodeGen/GCMetadata.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/CodeGen/StackMaps.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/IR/DebugInfo.h"
41 #include "llvm/IR/DerivedTypes.h"
42 #include "llvm/IR/Function.h"
43 #include "llvm/IR/GCStrategy.h"
44 #include "llvm/IR/GlobalVariable.h"
45 #include "llvm/IR/InlineAsm.h"
46 #include "llvm/IR/Instructions.h"
47 #include "llvm/IR/IntrinsicInst.h"
48 #include "llvm/IR/Intrinsics.h"
49 #include "llvm/IR/LLVMContext.h"
50 #include "llvm/IR/Module.h"
51 #include "llvm/IR/Statepoint.h"
52 #include "llvm/MC/MCSymbol.h"
53 #include "llvm/Support/CommandLine.h"
54 #include "llvm/Support/Debug.h"
55 #include "llvm/Support/ErrorHandling.h"
56 #include "llvm/Support/MathExtras.h"
57 #include "llvm/Support/raw_ostream.h"
58 #include "llvm/Target/TargetFrameLowering.h"
59 #include "llvm/Target/TargetInstrInfo.h"
60 #include "llvm/Target/TargetIntrinsicInfo.h"
61 #include "llvm/Target/TargetLowering.h"
62 #include "llvm/Target/TargetOptions.h"
63 #include "llvm/Target/TargetSelectionDAGInfo.h"
64 #include "llvm/Target/TargetSubtargetInfo.h"
65 #include <algorithm>
66 using namespace llvm;
68 #define DEBUG_TYPE "isel"
70 /// LimitFloatPrecision - Generate low-precision inline sequences for
71 /// some float libcalls (6, 8 or 12 bits).
72 static unsigned LimitFloatPrecision;
74 static cl::opt<unsigned, true>
75 LimitFPPrecision("limit-float-precision",
76 cl::desc("Generate low-precision inline sequences "
77 "for some float libcalls"),
78 cl::location(LimitFloatPrecision),
79 cl::init(0));
81 // Limit the width of DAG chains. This is important in general to prevent
82 // prevent DAG-based analysis from blowing up. For example, alias analysis and
83 // load clustering may not complete in reasonable time. It is difficult to
84 // recognize and avoid this situation within each individual analysis, and
85 // future analyses are likely to have the same behavior. Limiting DAG width is
86 // the safe approach, and will be especially important with global DAGs.
87 //
88 // MaxParallelChains default is arbitrarily high to avoid affecting
89 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
90 // sequence over this should have been converted to llvm.memcpy by the
91 // frontend. It easy to induce this behavior with .ll code such as:
92 // %buffer = alloca [4096 x i8]
93 // %data = load [4096 x i8]* %argPtr
94 // store [4096 x i8] %data, [4096 x i8]* %buffer
95 static const unsigned MaxParallelChains = 64;
97 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
98 const SDValue *Parts, unsigned NumParts,
99 MVT PartVT, EVT ValueVT, const Value *V);
101 /// getCopyFromParts - Create a value that contains the specified legal parts
102 /// combined into the value they represent. If the parts combine to a type
103 /// larger then ValueVT then AssertOp can be used to specify whether the extra
104 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
105 /// (ISD::AssertSext).
106 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
107 const SDValue *Parts,
108 unsigned NumParts, MVT PartVT, EVT ValueVT,
109 const Value *V,
110 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
111 if (ValueVT.isVector())
112 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
113 PartVT, ValueVT, V);
115 assert(NumParts > 0 && "No parts to assemble!");
116 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
117 SDValue Val = Parts[0];
119 if (NumParts > 1) {
120 // Assemble the value from multiple parts.
121 if (ValueVT.isInteger()) {
122 unsigned PartBits = PartVT.getSizeInBits();
123 unsigned ValueBits = ValueVT.getSizeInBits();
125 // Assemble the power of 2 part.
126 unsigned RoundParts = NumParts & (NumParts - 1) ?
127 1 << Log2_32(NumParts) : NumParts;
128 unsigned RoundBits = PartBits * RoundParts;
129 EVT RoundVT = RoundBits == ValueBits ?
130 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
131 SDValue Lo, Hi;
133 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
135 if (RoundParts > 2) {
136 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
137 PartVT, HalfVT, V);
138 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
139 RoundParts / 2, PartVT, HalfVT, V);
140 } else {
141 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
142 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
143 }
145 if (TLI.isBigEndian())
146 std::swap(Lo, Hi);
148 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
150 if (RoundParts < NumParts) {
151 // Assemble the trailing non-power-of-2 part.
152 unsigned OddParts = NumParts - RoundParts;
153 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
154 Hi = getCopyFromParts(DAG, DL,
155 Parts + RoundParts, OddParts, PartVT, OddVT, V);
157 // Combine the round and odd parts.
158 Lo = Val;
159 if (TLI.isBigEndian())
160 std::swap(Lo, Hi);
161 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
162 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
163 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
164 DAG.getConstant(Lo.getValueType().getSizeInBits(),
165 TLI.getPointerTy()));
166 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
167 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
168 }
169 } else if (PartVT.isFloatingPoint()) {
170 // FP split into multiple FP parts (for ppcf128)
171 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
172 "Unexpected split");
173 SDValue Lo, Hi;
174 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
175 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
176 if (TLI.hasBigEndianPartOrdering(ValueVT))
177 std::swap(Lo, Hi);
178 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
179 } else {
180 // FP split into integer parts (soft fp)
181 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
182 !PartVT.isVector() && "Unexpected split");
183 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
184 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
185 }
186 }
188 // There is now one part, held in Val. Correct it to match ValueVT.
189 EVT PartEVT = Val.getValueType();
191 if (PartEVT == ValueVT)
192 return Val;
194 if (PartEVT.isInteger() && ValueVT.isInteger()) {
195 if (ValueVT.bitsLT(PartEVT)) {
196 // For a truncate, see if we have any information to
197 // indicate whether the truncated bits will always be
198 // zero or sign-extension.
199 if (AssertOp != ISD::DELETED_NODE)
200 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
201 DAG.getValueType(ValueVT));
202 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
203 }
204 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
205 }
207 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
208 // FP_ROUND's are always exact here.
209 if (ValueVT.bitsLT(Val.getValueType()))
210 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
211 DAG.getTargetConstant(1, TLI.getPointerTy()));
213 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
214 }
216 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
217 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
219 llvm_unreachable("Unknown mismatch!");
220 }
222 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
223 const Twine &ErrMsg) {
224 const Instruction *I = dyn_cast_or_null<Instruction>(V);
225 if (!V)
226 return Ctx.emitError(ErrMsg);
228 const char *AsmError = ", possible invalid constraint for vector type";
229 if (const CallInst *CI = dyn_cast<CallInst>(I))
230 if (isa<InlineAsm>(CI->getCalledValue()))
231 return Ctx.emitError(I, ErrMsg + AsmError);
233 return Ctx.emitError(I, ErrMsg);
234 }
236 /// getCopyFromPartsVector - Create a value that contains the specified legal
237 /// parts combined into the value they represent. If the parts combine to a
238 /// type larger then ValueVT then AssertOp can be used to specify whether the
239 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
240 /// ValueVT (ISD::AssertSext).
241 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
242 const SDValue *Parts, unsigned NumParts,
243 MVT PartVT, EVT ValueVT, const Value *V) {
244 assert(ValueVT.isVector() && "Not a vector value");
245 assert(NumParts > 0 && "No parts to assemble!");
246 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
247 SDValue Val = Parts[0];
249 // Handle a multi-element vector.
250 if (NumParts > 1) {
251 EVT IntermediateVT;
252 MVT RegisterVT;
253 unsigned NumIntermediates;
254 unsigned NumRegs =
255 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
256 NumIntermediates, RegisterVT);
257 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
258 NumParts = NumRegs; // Silence a compiler warning.
259 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
260 assert(RegisterVT == Parts[0].getSimpleValueType() &&
261 "Part type doesn't match part!");
263 // Assemble the parts into intermediate operands.
264 SmallVector<SDValue, 8> Ops(NumIntermediates);
265 if (NumIntermediates == NumParts) {
266 // If the register was not expanded, truncate or copy the value,
267 // as appropriate.
268 for (unsigned i = 0; i != NumParts; ++i)
269 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
270 PartVT, IntermediateVT, V);
271 } else if (NumParts > 0) {
272 // If the intermediate type was expanded, build the intermediate
273 // operands from the parts.
274 assert(NumParts % NumIntermediates == 0 &&
275 "Must expand into a divisible number of parts!");
276 unsigned Factor = NumParts / NumIntermediates;
277 for (unsigned i = 0; i != NumIntermediates; ++i)
278 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
279 PartVT, IntermediateVT, V);
280 }
282 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
283 // intermediate operands.
284 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
285 : ISD::BUILD_VECTOR,
286 DL, ValueVT, Ops);
287 }
289 // There is now one part, held in Val. Correct it to match ValueVT.
290 EVT PartEVT = Val.getValueType();
292 if (PartEVT == ValueVT)
293 return Val;
295 if (PartEVT.isVector()) {
296 // If the element type of the source/dest vectors are the same, but the
297 // parts vector has more elements than the value vector, then we have a
298 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
299 // elements we want.
300 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
301 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
302 "Cannot narrow, it would be a lossy transformation");
303 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
304 DAG.getConstant(0, TLI.getVectorIdxTy()));
305 }
307 // Vector/Vector bitcast.
308 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
309 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
311 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
312 "Cannot handle this kind of promotion");
313 // Promoted vector extract
314 bool Smaller = ValueVT.bitsLE(PartEVT);
315 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
316 DL, ValueVT, Val);
318 }
320 // Trivial bitcast if the types are the same size and the destination
321 // vector type is legal.
322 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
323 TLI.isTypeLegal(ValueVT))
324 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
326 // Handle cases such as i8 -> <1 x i1>
327 if (ValueVT.getVectorNumElements() != 1) {
328 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
329 "non-trivial scalar-to-vector conversion");
330 return DAG.getUNDEF(ValueVT);
331 }
333 if (ValueVT.getVectorNumElements() == 1 &&
334 ValueVT.getVectorElementType() != PartEVT) {
335 bool Smaller = ValueVT.bitsLE(PartEVT);
336 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
337 DL, ValueVT.getScalarType(), Val);
338 }
340 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
341 }
343 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
344 SDValue Val, SDValue *Parts, unsigned NumParts,
345 MVT PartVT, const Value *V);
347 /// getCopyToParts - Create a series of nodes that contain the specified value
348 /// split into legal parts. If the parts contain more bits than Val, then, for
349 /// integers, ExtendKind can be used to specify how to generate the extra bits.
350 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
351 SDValue Val, SDValue *Parts, unsigned NumParts,
352 MVT PartVT, const Value *V,
353 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
354 EVT ValueVT = Val.getValueType();
356 // Handle the vector case separately.
357 if (ValueVT.isVector())
358 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
360 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
361 unsigned PartBits = PartVT.getSizeInBits();
362 unsigned OrigNumParts = NumParts;
363 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
365 if (NumParts == 0)
366 return;
368 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
369 EVT PartEVT = PartVT;
370 if (PartEVT == ValueVT) {
371 assert(NumParts == 1 && "No-op copy with multiple parts!");
372 Parts[0] = Val;
373 return;
374 }
376 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
377 // If the parts cover more bits than the value has, promote the value.
378 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
379 assert(NumParts == 1 && "Do not know what to promote to!");
380 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
381 } else {
382 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
383 ValueVT.isInteger() &&
384 "Unknown mismatch!");
385 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
386 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
387 if (PartVT == MVT::x86mmx)
388 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
389 }
390 } else if (PartBits == ValueVT.getSizeInBits()) {
391 // Different types of the same size.
392 assert(NumParts == 1 && PartEVT != ValueVT);
393 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
394 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
395 // If the parts cover less bits than value has, truncate the value.
396 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
397 ValueVT.isInteger() &&
398 "Unknown mismatch!");
399 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
400 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
401 if (PartVT == MVT::x86mmx)
402 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
403 }
405 // The value may have changed - recompute ValueVT.
406 ValueVT = Val.getValueType();
407 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
408 "Failed to tile the value with PartVT!");
410 if (NumParts == 1) {
411 if (PartEVT != ValueVT)
412 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
413 "scalar-to-vector conversion failed");
415 Parts[0] = Val;
416 return;
417 }
419 // Expand the value into multiple parts.
420 if (NumParts & (NumParts - 1)) {
421 // The number of parts is not a power of 2. Split off and copy the tail.
422 assert(PartVT.isInteger() && ValueVT.isInteger() &&
423 "Do not know what to expand to!");
424 unsigned RoundParts = 1 << Log2_32(NumParts);
425 unsigned RoundBits = RoundParts * PartBits;
426 unsigned OddParts = NumParts - RoundParts;
427 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
428 DAG.getIntPtrConstant(RoundBits));
429 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
431 if (TLI.isBigEndian())
432 // The odd parts were reversed by getCopyToParts - unreverse them.
433 std::reverse(Parts + RoundParts, Parts + NumParts);
435 NumParts = RoundParts;
436 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
437 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
438 }
440 // The number of parts is a power of 2. Repeatedly bisect the value using
441 // EXTRACT_ELEMENT.
442 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
443 EVT::getIntegerVT(*DAG.getContext(),
444 ValueVT.getSizeInBits()),
445 Val);
447 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
448 for (unsigned i = 0; i < NumParts; i += StepSize) {
449 unsigned ThisBits = StepSize * PartBits / 2;
450 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
451 SDValue &Part0 = Parts[i];
452 SDValue &Part1 = Parts[i+StepSize/2];
454 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
455 ThisVT, Part0, DAG.getIntPtrConstant(1));
456 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
457 ThisVT, Part0, DAG.getIntPtrConstant(0));
459 if (ThisBits == PartBits && ThisVT != PartVT) {
460 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
461 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
462 }
463 }
464 }
466 if (TLI.isBigEndian())
467 std::reverse(Parts, Parts + OrigNumParts);
468 }
471 /// getCopyToPartsVector - Create a series of nodes that contain the specified
472 /// value split into legal parts.
473 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
474 SDValue Val, SDValue *Parts, unsigned NumParts,
475 MVT PartVT, const Value *V) {
476 EVT ValueVT = Val.getValueType();
477 assert(ValueVT.isVector() && "Not a vector");
478 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
480 if (NumParts == 1) {
481 EVT PartEVT = PartVT;
482 if (PartEVT == ValueVT) {
483 // Nothing to do.
484 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
485 // Bitconvert vector->vector case.
486 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
487 } else if (PartVT.isVector() &&
488 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
489 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
490 EVT ElementVT = PartVT.getVectorElementType();
491 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
492 // undef elements.
493 SmallVector<SDValue, 16> Ops;
494 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
495 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
496 ElementVT, Val, DAG.getConstant(i,
497 TLI.getVectorIdxTy())));
499 for (unsigned i = ValueVT.getVectorNumElements(),
500 e = PartVT.getVectorNumElements(); i != e; ++i)
501 Ops.push_back(DAG.getUNDEF(ElementVT));
503 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
505 // FIXME: Use CONCAT for 2x -> 4x.
507 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
508 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
509 } else if (PartVT.isVector() &&
510 PartEVT.getVectorElementType().bitsGE(
511 ValueVT.getVectorElementType()) &&
512 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
514 // Promoted vector extract
515 bool Smaller = PartEVT.bitsLE(ValueVT);
516 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
517 DL, PartVT, Val);
518 } else{
519 // Vector -> scalar conversion.
520 assert(ValueVT.getVectorNumElements() == 1 &&
521 "Only trivial vector-to-scalar conversions should get here!");
522 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
523 PartVT, Val, DAG.getConstant(0, TLI.getVectorIdxTy()));
525 bool Smaller = ValueVT.bitsLE(PartVT);
526 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
527 DL, PartVT, Val);
528 }
530 Parts[0] = Val;
531 return;
532 }
534 // Handle a multi-element vector.
535 EVT IntermediateVT;
536 MVT RegisterVT;
537 unsigned NumIntermediates;
538 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
539 IntermediateVT,
540 NumIntermediates, RegisterVT);
541 unsigned NumElements = ValueVT.getVectorNumElements();
543 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
544 NumParts = NumRegs; // Silence a compiler warning.
545 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
547 // Split the vector into intermediate operands.
548 SmallVector<SDValue, 8> Ops(NumIntermediates);
549 for (unsigned i = 0; i != NumIntermediates; ++i) {
550 if (IntermediateVT.isVector())
551 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
552 IntermediateVT, Val,
553 DAG.getConstant(i * (NumElements / NumIntermediates),
554 TLI.getVectorIdxTy()));
555 else
556 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
557 IntermediateVT, Val,
558 DAG.getConstant(i, TLI.getVectorIdxTy()));
559 }
561 // Split the intermediate operands into legal parts.
562 if (NumParts == NumIntermediates) {
563 // If the register was not expanded, promote or copy the value,
564 // as appropriate.
565 for (unsigned i = 0; i != NumParts; ++i)
566 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
567 } else if (NumParts > 0) {
568 // If the intermediate type was expanded, split each the value into
569 // legal parts.
570 assert(NumIntermediates != 0 && "division by zero");
571 assert(NumParts % NumIntermediates == 0 &&
572 "Must expand into a divisible number of parts!");
573 unsigned Factor = NumParts / NumIntermediates;
574 for (unsigned i = 0; i != NumIntermediates; ++i)
575 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
576 }
577 }
579 namespace {
580 /// RegsForValue - This struct represents the registers (physical or virtual)
581 /// that a particular set of values is assigned, and the type information
582 /// about the value. The most common situation is to represent one value at a
583 /// time, but struct or array values are handled element-wise as multiple
584 /// values. The splitting of aggregates is performed recursively, so that we
585 /// never have aggregate-typed registers. The values at this point do not
586 /// necessarily have legal types, so each value may require one or more
587 /// registers of some legal type.
588 ///
589 struct RegsForValue {
590 /// ValueVTs - The value types of the values, which may not be legal, and
591 /// may need be promoted or synthesized from one or more registers.
592 ///
593 SmallVector<EVT, 4> ValueVTs;
595 /// RegVTs - The value types of the registers. This is the same size as
596 /// ValueVTs and it records, for each value, what the type of the assigned
597 /// register or registers are. (Individual values are never synthesized
598 /// from more than one type of register.)
599 ///
600 /// With virtual registers, the contents of RegVTs is redundant with TLI's
601 /// getRegisterType member function, however when with physical registers
602 /// it is necessary to have a separate record of the types.
603 ///
604 SmallVector<MVT, 4> RegVTs;
606 /// Regs - This list holds the registers assigned to the values.
607 /// Each legal or promoted value requires one register, and each
608 /// expanded value requires multiple registers.
609 ///
610 SmallVector<unsigned, 4> Regs;
612 RegsForValue() {}
614 RegsForValue(const SmallVector<unsigned, 4> ®s,
615 MVT regvt, EVT valuevt)
616 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
618 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
619 unsigned Reg, Type *Ty) {
620 ComputeValueVTs(tli, Ty, ValueVTs);
622 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
623 EVT ValueVT = ValueVTs[Value];
624 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
625 MVT RegisterVT = tli.getRegisterType(Context, ValueVT);
626 for (unsigned i = 0; i != NumRegs; ++i)
627 Regs.push_back(Reg + i);
628 RegVTs.push_back(RegisterVT);
629 Reg += NumRegs;
630 }
631 }
633 /// append - Add the specified values to this one.
634 void append(const RegsForValue &RHS) {
635 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
636 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
637 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
638 }
640 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
641 /// this value and returns the result as a ValueVTs value. This uses
642 /// Chain/Flag as the input and updates them for the output Chain/Flag.
643 /// If the Flag pointer is NULL, no flag is used.
644 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
645 SDLoc dl,
646 SDValue &Chain, SDValue *Flag,
647 const Value *V = nullptr) const;
649 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
650 /// specified value into the registers specified by this object. This uses
651 /// Chain/Flag as the input and updates them for the output Chain/Flag.
652 /// If the Flag pointer is NULL, no flag is used.
653 void
654 getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl, SDValue &Chain,
655 SDValue *Flag, const Value *V,
656 ISD::NodeType PreferredExtendType = ISD::ANY_EXTEND) const;
658 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
659 /// operand list. This adds the code marker, matching input operand index
660 /// (if applicable), and includes the number of values added into it.
661 void AddInlineAsmOperands(unsigned Kind,
662 bool HasMatching, unsigned MatchingIdx,
663 SelectionDAG &DAG,
664 std::vector<SDValue> &Ops) const;
665 };
666 }
668 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
669 /// this value and returns the result as a ValueVT value. This uses
670 /// Chain/Flag as the input and updates them for the output Chain/Flag.
671 /// If the Flag pointer is NULL, no flag is used.
672 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
673 FunctionLoweringInfo &FuncInfo,
674 SDLoc dl,
675 SDValue &Chain, SDValue *Flag,
676 const Value *V) const {
677 // A Value with type {} or [0 x %t] needs no registers.
678 if (ValueVTs.empty())
679 return SDValue();
681 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
683 // Assemble the legal parts into the final values.
684 SmallVector<SDValue, 4> Values(ValueVTs.size());
685 SmallVector<SDValue, 8> Parts;
686 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
687 // Copy the legal parts from the registers.
688 EVT ValueVT = ValueVTs[Value];
689 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
690 MVT RegisterVT = RegVTs[Value];
692 Parts.resize(NumRegs);
693 for (unsigned i = 0; i != NumRegs; ++i) {
694 SDValue P;
695 if (!Flag) {
696 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
697 } else {
698 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
699 *Flag = P.getValue(2);
700 }
702 Chain = P.getValue(1);
703 Parts[i] = P;
705 // If the source register was virtual and if we know something about it,
706 // add an assert node.
707 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
708 !RegisterVT.isInteger() || RegisterVT.isVector())
709 continue;
711 const FunctionLoweringInfo::LiveOutInfo *LOI =
712 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
713 if (!LOI)
714 continue;
716 unsigned RegSize = RegisterVT.getSizeInBits();
717 unsigned NumSignBits = LOI->NumSignBits;
718 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
720 if (NumZeroBits == RegSize) {
721 // The current value is a zero.
722 // Explicitly express that as it would be easier for
723 // optimizations to kick in.
724 Parts[i] = DAG.getConstant(0, RegisterVT);
725 continue;
726 }
728 // FIXME: We capture more information than the dag can represent. For
729 // now, just use the tightest assertzext/assertsext possible.
730 bool isSExt = true;
731 EVT FromVT(MVT::Other);
732 if (NumSignBits == RegSize)
733 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
734 else if (NumZeroBits >= RegSize-1)
735 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
736 else if (NumSignBits > RegSize-8)
737 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
738 else if (NumZeroBits >= RegSize-8)
739 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
740 else if (NumSignBits > RegSize-16)
741 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
742 else if (NumZeroBits >= RegSize-16)
743 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
744 else if (NumSignBits > RegSize-32)
745 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
746 else if (NumZeroBits >= RegSize-32)
747 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
748 else
749 continue;
751 // Add an assertion node.
752 assert(FromVT != MVT::Other);
753 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
754 RegisterVT, P, DAG.getValueType(FromVT));
755 }
757 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
758 NumRegs, RegisterVT, ValueVT, V);
759 Part += NumRegs;
760 Parts.clear();
761 }
763 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
764 }
766 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
767 /// specified value into the registers specified by this object. This uses
768 /// Chain/Flag as the input and updates them for the output Chain/Flag.
769 /// If the Flag pointer is NULL, no flag is used.
770 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
771 SDValue &Chain, SDValue *Flag, const Value *V,
772 ISD::NodeType PreferredExtendType) const {
773 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
774 ISD::NodeType ExtendKind = PreferredExtendType;
776 // Get the list of the values's legal parts.
777 unsigned NumRegs = Regs.size();
778 SmallVector<SDValue, 8> Parts(NumRegs);
779 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
780 EVT ValueVT = ValueVTs[Value];
781 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
782 MVT RegisterVT = RegVTs[Value];
784 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
785 ExtendKind = ISD::ZERO_EXTEND;
787 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
788 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
789 Part += NumParts;
790 }
792 // Copy the parts into the registers.
793 SmallVector<SDValue, 8> Chains(NumRegs);
794 for (unsigned i = 0; i != NumRegs; ++i) {
795 SDValue Part;
796 if (!Flag) {
797 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
798 } else {
799 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
800 *Flag = Part.getValue(1);
801 }
803 Chains[i] = Part.getValue(0);
804 }
806 if (NumRegs == 1 || Flag)
807 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
808 // flagged to it. That is the CopyToReg nodes and the user are considered
809 // a single scheduling unit. If we create a TokenFactor and return it as
810 // chain, then the TokenFactor is both a predecessor (operand) of the
811 // user as well as a successor (the TF operands are flagged to the user).
812 // c1, f1 = CopyToReg
813 // c2, f2 = CopyToReg
814 // c3 = TokenFactor c1, c2
815 // ...
816 // = op c3, ..., f2
817 Chain = Chains[NumRegs-1];
818 else
819 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
820 }
822 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
823 /// operand list. This adds the code marker and includes the number of
824 /// values added into it.
825 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
826 unsigned MatchingIdx,
827 SelectionDAG &DAG,
828 std::vector<SDValue> &Ops) const {
829 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
831 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
832 if (HasMatching)
833 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
834 else if (!Regs.empty() &&
835 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
836 // Put the register class of the virtual registers in the flag word. That
837 // way, later passes can recompute register class constraints for inline
838 // assembly as well as normal instructions.
839 // Don't do this for tied operands that can use the regclass information
840 // from the def.
841 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
842 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
843 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
844 }
846 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
847 Ops.push_back(Res);
849 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
850 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
851 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
852 MVT RegisterVT = RegVTs[Value];
853 for (unsigned i = 0; i != NumRegs; ++i) {
854 assert(Reg < Regs.size() && "Mismatch in # registers expected");
855 unsigned TheReg = Regs[Reg++];
856 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
858 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
859 // If we clobbered the stack pointer, MFI should know about it.
860 assert(DAG.getMachineFunction().getFrameInfo()->
861 hasInlineAsmWithSPAdjust());
862 }
863 }
864 }
865 }
867 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
868 const TargetLibraryInfo *li) {
869 AA = &aa;
870 GFI = gfi;
871 LibInfo = li;
872 DL = DAG.getSubtarget().getDataLayout();
873 Context = DAG.getContext();
874 LPadToCallSiteMap.clear();
875 }
877 /// clear - Clear out the current SelectionDAG and the associated
878 /// state and prepare this SelectionDAGBuilder object to be used
879 /// for a new block. This doesn't clear out information about
880 /// additional blocks that are needed to complete switch lowering
881 /// or PHI node updating; that information is cleared out as it is
882 /// consumed.
883 void SelectionDAGBuilder::clear() {
884 NodeMap.clear();
885 UnusedArgNodeMap.clear();
886 PendingLoads.clear();
887 PendingExports.clear();
888 CurInst = nullptr;
889 HasTailCall = false;
890 SDNodeOrder = LowestSDNodeOrder;
891 StatepointLowering.clear();
892 }
894 /// clearDanglingDebugInfo - Clear the dangling debug information
895 /// map. This function is separated from the clear so that debug
896 /// information that is dangling in a basic block can be properly
897 /// resolved in a different basic block. This allows the
898 /// SelectionDAG to resolve dangling debug information attached
899 /// to PHI nodes.
900 void SelectionDAGBuilder::clearDanglingDebugInfo() {
901 DanglingDebugInfoMap.clear();
902 }
904 /// getRoot - Return the current virtual root of the Selection DAG,
905 /// flushing any PendingLoad items. This must be done before emitting
906 /// a store or any other node that may need to be ordered after any
907 /// prior load instructions.
908 ///
909 SDValue SelectionDAGBuilder::getRoot() {
910 if (PendingLoads.empty())
911 return DAG.getRoot();
913 if (PendingLoads.size() == 1) {
914 SDValue Root = PendingLoads[0];
915 DAG.setRoot(Root);
916 PendingLoads.clear();
917 return Root;
918 }
920 // Otherwise, we have to make a token factor node.
921 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
922 PendingLoads);
923 PendingLoads.clear();
924 DAG.setRoot(Root);
925 return Root;
926 }
928 /// getControlRoot - Similar to getRoot, but instead of flushing all the
929 /// PendingLoad items, flush all the PendingExports items. It is necessary
930 /// to do this before emitting a terminator instruction.
931 ///
932 SDValue SelectionDAGBuilder::getControlRoot() {
933 SDValue Root = DAG.getRoot();
935 if (PendingExports.empty())
936 return Root;
938 // Turn all of the CopyToReg chains into one factored node.
939 if (Root.getOpcode() != ISD::EntryToken) {
940 unsigned i = 0, e = PendingExports.size();
941 for (; i != e; ++i) {
942 assert(PendingExports[i].getNode()->getNumOperands() > 1);
943 if (PendingExports[i].getNode()->getOperand(0) == Root)
944 break; // Don't add the root if we already indirectly depend on it.
945 }
947 if (i == e)
948 PendingExports.push_back(Root);
949 }
951 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
952 PendingExports);
953 PendingExports.clear();
954 DAG.setRoot(Root);
955 return Root;
956 }
958 void SelectionDAGBuilder::visit(const Instruction &I) {
959 // Set up outgoing PHI node register values before emitting the terminator.
960 if (isa<TerminatorInst>(&I))
961 HandlePHINodesInSuccessorBlocks(I.getParent());
963 ++SDNodeOrder;
965 CurInst = &I;
967 visit(I.getOpcode(), I);
969 if (!isa<TerminatorInst>(&I) && !HasTailCall)
970 CopyToExportRegsIfNeeded(&I);
972 CurInst = nullptr;
973 }
975 void SelectionDAGBuilder::visitPHI(const PHINode &) {
976 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
977 }
979 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
980 // Note: this doesn't use InstVisitor, because it has to work with
981 // ConstantExpr's in addition to instructions.
982 switch (Opcode) {
983 default: llvm_unreachable("Unknown instruction type encountered!");
984 // Build the switch statement using the Instruction.def file.
985 #define HANDLE_INST(NUM, OPCODE, CLASS) \
986 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
987 #include "llvm/IR/Instruction.def"
988 }
989 }
991 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
992 // generate the debug data structures now that we've seen its definition.
993 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
994 SDValue Val) {
995 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
996 if (DDI.getDI()) {
997 const DbgValueInst *DI = DDI.getDI();
998 DebugLoc dl = DDI.getdl();
999 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
1000 MDNode *Variable = DI->getVariable();
1001 MDNode *Expr = DI->getExpression();
1002 uint64_t Offset = DI->getOffset();
1003 // A dbg.value for an alloca is always indirect.
1004 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
1005 SDDbgValue *SDV;
1006 if (Val.getNode()) {
1007 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, Offset, IsIndirect,
1008 Val)) {
1009 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(),
1010 IsIndirect, Offset, dl, DbgSDNodeOrder);
1011 DAG.AddDbgValue(SDV, Val.getNode(), false);
1012 }
1013 } else
1014 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1015 DanglingDebugInfoMap[V] = DanglingDebugInfo();
1016 }
1017 }
1019 /// getValue - Return an SDValue for the given Value.
1020 SDValue SelectionDAGBuilder::getValue(const Value *V) {
1021 // If we already have an SDValue for this value, use it. It's important
1022 // to do this first, so that we don't create a CopyFromReg if we already
1023 // have a regular SDValue.
1024 SDValue &N = NodeMap[V];
1025 if (N.getNode()) return N;
1027 // If there's a virtual register allocated and initialized for this
1028 // value, use it.
1029 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
1030 if (It != FuncInfo.ValueMap.end()) {
1031 unsigned InReg = It->second;
1032 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(), InReg,
1033 V->getType());
1034 SDValue Chain = DAG.getEntryNode();
1035 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1036 resolveDanglingDebugInfo(V, N);
1037 return N;
1038 }
1040 // Otherwise create a new SDValue and remember it.
1041 SDValue Val = getValueImpl(V);
1042 NodeMap[V] = Val;
1043 resolveDanglingDebugInfo(V, Val);
1044 return Val;
1045 }
1047 /// getNonRegisterValue - Return an SDValue for the given Value, but
1048 /// don't look in FuncInfo.ValueMap for a virtual register.
1049 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1050 // If we already have an SDValue for this value, use it.
1051 SDValue &N = NodeMap[V];
1052 if (N.getNode()) return N;
1054 // Otherwise create a new SDValue and remember it.
1055 SDValue Val = getValueImpl(V);
1056 NodeMap[V] = Val;
1057 resolveDanglingDebugInfo(V, Val);
1058 return Val;
1059 }
1061 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1062 /// Create an SDValue for the given value.
1063 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1064 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1066 if (const Constant *C = dyn_cast<Constant>(V)) {
1067 EVT VT = TLI.getValueType(V->getType(), true);
1069 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1070 return DAG.getConstant(*CI, VT);
1072 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1073 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1075 if (isa<ConstantPointerNull>(C)) {
1076 unsigned AS = V->getType()->getPointerAddressSpace();
1077 return DAG.getConstant(0, TLI.getPointerTy(AS));
1078 }
1080 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1081 return DAG.getConstantFP(*CFP, VT);
1083 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1084 return DAG.getUNDEF(VT);
1086 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1087 visit(CE->getOpcode(), *CE);
1088 SDValue N1 = NodeMap[V];
1089 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1090 return N1;
1091 }
1093 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1094 SmallVector<SDValue, 4> Constants;
1095 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1096 OI != OE; ++OI) {
1097 SDNode *Val = getValue(*OI).getNode();
1098 // If the operand is an empty aggregate, there are no values.
1099 if (!Val) continue;
1100 // Add each leaf value from the operand to the Constants list
1101 // to form a flattened list of all the values.
1102 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1103 Constants.push_back(SDValue(Val, i));
1104 }
1106 return DAG.getMergeValues(Constants, getCurSDLoc());
1107 }
1109 if (const ConstantDataSequential *CDS =
1110 dyn_cast<ConstantDataSequential>(C)) {
1111 SmallVector<SDValue, 4> Ops;
1112 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1113 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1114 // Add each leaf value from the operand to the Constants list
1115 // to form a flattened list of all the values.
1116 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1117 Ops.push_back(SDValue(Val, i));
1118 }
1120 if (isa<ArrayType>(CDS->getType()))
1121 return DAG.getMergeValues(Ops, getCurSDLoc());
1122 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1123 VT, Ops);
1124 }
1126 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1127 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1128 "Unknown struct or array constant!");
1130 SmallVector<EVT, 4> ValueVTs;
1131 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1132 unsigned NumElts = ValueVTs.size();
1133 if (NumElts == 0)
1134 return SDValue(); // empty struct
1135 SmallVector<SDValue, 4> Constants(NumElts);
1136 for (unsigned i = 0; i != NumElts; ++i) {
1137 EVT EltVT = ValueVTs[i];
1138 if (isa<UndefValue>(C))
1139 Constants[i] = DAG.getUNDEF(EltVT);
1140 else if (EltVT.isFloatingPoint())
1141 Constants[i] = DAG.getConstantFP(0, EltVT);
1142 else
1143 Constants[i] = DAG.getConstant(0, EltVT);
1144 }
1146 return DAG.getMergeValues(Constants, getCurSDLoc());
1147 }
1149 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1150 return DAG.getBlockAddress(BA, VT);
1152 VectorType *VecTy = cast<VectorType>(V->getType());
1153 unsigned NumElements = VecTy->getNumElements();
1155 // Now that we know the number and type of the elements, get that number of
1156 // elements into the Ops array based on what kind of constant it is.
1157 SmallVector<SDValue, 16> Ops;
1158 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1159 for (unsigned i = 0; i != NumElements; ++i)
1160 Ops.push_back(getValue(CV->getOperand(i)));
1161 } else {
1162 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1163 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1165 SDValue Op;
1166 if (EltVT.isFloatingPoint())
1167 Op = DAG.getConstantFP(0, EltVT);
1168 else
1169 Op = DAG.getConstant(0, EltVT);
1170 Ops.assign(NumElements, Op);
1171 }
1173 // Create a BUILD_VECTOR node.
1174 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1175 }
1177 // If this is a static alloca, generate it as the frameindex instead of
1178 // computation.
1179 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1180 DenseMap<const AllocaInst*, int>::iterator SI =
1181 FuncInfo.StaticAllocaMap.find(AI);
1182 if (SI != FuncInfo.StaticAllocaMap.end())
1183 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1184 }
1186 // If this is an instruction which fast-isel has deferred, select it now.
1187 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1188 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1189 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1190 SDValue Chain = DAG.getEntryNode();
1191 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1192 }
1194 llvm_unreachable("Can't get register for value!");
1195 }
1197 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1198 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1199 SDValue Chain = getControlRoot();
1200 SmallVector<ISD::OutputArg, 8> Outs;
1201 SmallVector<SDValue, 8> OutVals;
1203 if (!FuncInfo.CanLowerReturn) {
1204 unsigned DemoteReg = FuncInfo.DemoteRegister;
1205 const Function *F = I.getParent()->getParent();
1207 // Emit a store of the return value through the virtual register.
1208 // Leave Outs empty so that LowerReturn won't try to load return
1209 // registers the usual way.
1210 SmallVector<EVT, 1> PtrValueVTs;
1211 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1212 PtrValueVTs);
1214 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1215 SDValue RetOp = getValue(I.getOperand(0));
1217 SmallVector<EVT, 4> ValueVTs;
1218 SmallVector<uint64_t, 4> Offsets;
1219 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1220 unsigned NumValues = ValueVTs.size();
1222 SmallVector<SDValue, 4> Chains(NumValues);
1223 for (unsigned i = 0; i != NumValues; ++i) {
1224 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1225 RetPtr.getValueType(), RetPtr,
1226 DAG.getIntPtrConstant(Offsets[i]));
1227 Chains[i] =
1228 DAG.getStore(Chain, getCurSDLoc(),
1229 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1230 // FIXME: better loc info would be nice.
1231 Add, MachinePointerInfo(), false, false, 0);
1232 }
1234 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1235 MVT::Other, Chains);
1236 } else if (I.getNumOperands() != 0) {
1237 SmallVector<EVT, 4> ValueVTs;
1238 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1239 unsigned NumValues = ValueVTs.size();
1240 if (NumValues) {
1241 SDValue RetOp = getValue(I.getOperand(0));
1243 const Function *F = I.getParent()->getParent();
1245 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1246 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1247 Attribute::SExt))
1248 ExtendKind = ISD::SIGN_EXTEND;
1249 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1250 Attribute::ZExt))
1251 ExtendKind = ISD::ZERO_EXTEND;
1253 LLVMContext &Context = F->getContext();
1254 bool RetInReg = F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1255 Attribute::InReg);
1257 for (unsigned j = 0; j != NumValues; ++j) {
1258 EVT VT = ValueVTs[j];
1260 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1261 VT = TLI.getTypeForExtArgOrReturn(Context, VT, ExtendKind);
1263 unsigned NumParts = TLI.getNumRegisters(Context, VT);
1264 MVT PartVT = TLI.getRegisterType(Context, VT);
1265 SmallVector<SDValue, 4> Parts(NumParts);
1266 getCopyToParts(DAG, getCurSDLoc(),
1267 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1268 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1270 // 'inreg' on function refers to return value
1271 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1272 if (RetInReg)
1273 Flags.setInReg();
1275 // Propagate extension type if any
1276 if (ExtendKind == ISD::SIGN_EXTEND)
1277 Flags.setSExt();
1278 else if (ExtendKind == ISD::ZERO_EXTEND)
1279 Flags.setZExt();
1281 for (unsigned i = 0; i < NumParts; ++i) {
1282 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1283 VT, /*isfixed=*/true, 0, 0));
1284 OutVals.push_back(Parts[i]);
1285 }
1286 }
1287 }
1288 }
1290 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1291 CallingConv::ID CallConv =
1292 DAG.getMachineFunction().getFunction()->getCallingConv();
1293 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1294 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1296 // Verify that the target's LowerReturn behaved as expected.
1297 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1298 "LowerReturn didn't return a valid chain!");
1300 // Update the DAG with the new chain value resulting from return lowering.
1301 DAG.setRoot(Chain);
1302 }
1304 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1305 /// created for it, emit nodes to copy the value into the virtual
1306 /// registers.
1307 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1308 // Skip empty types
1309 if (V->getType()->isEmptyTy())
1310 return;
1312 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1313 if (VMI != FuncInfo.ValueMap.end()) {
1314 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1315 CopyValueToVirtualRegister(V, VMI->second);
1316 }
1317 }
1319 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1320 /// the current basic block, add it to ValueMap now so that we'll get a
1321 /// CopyTo/FromReg.
1322 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1323 // No need to export constants.
1324 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1326 // Already exported?
1327 if (FuncInfo.isExportedInst(V)) return;
1329 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1330 CopyValueToVirtualRegister(V, Reg);
1331 }
1333 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1334 const BasicBlock *FromBB) {
1335 // The operands of the setcc have to be in this block. We don't know
1336 // how to export them from some other block.
1337 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1338 // Can export from current BB.
1339 if (VI->getParent() == FromBB)
1340 return true;
1342 // Is already exported, noop.
1343 return FuncInfo.isExportedInst(V);
1344 }
1346 // If this is an argument, we can export it if the BB is the entry block or
1347 // if it is already exported.
1348 if (isa<Argument>(V)) {
1349 if (FromBB == &FromBB->getParent()->getEntryBlock())
1350 return true;
1352 // Otherwise, can only export this if it is already exported.
1353 return FuncInfo.isExportedInst(V);
1354 }
1356 // Otherwise, constants can always be exported.
1357 return true;
1358 }
1360 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1361 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1362 const MachineBasicBlock *Dst) const {
1363 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1364 if (!BPI)
1365 return 0;
1366 const BasicBlock *SrcBB = Src->getBasicBlock();
1367 const BasicBlock *DstBB = Dst->getBasicBlock();
1368 return BPI->getEdgeWeight(SrcBB, DstBB);
1369 }
1371 void SelectionDAGBuilder::
1372 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1373 uint32_t Weight /* = 0 */) {
1374 if (!Weight)
1375 Weight = getEdgeWeight(Src, Dst);
1376 Src->addSuccessor(Dst, Weight);
1377 }
1380 static bool InBlock(const Value *V, const BasicBlock *BB) {
1381 if (const Instruction *I = dyn_cast<Instruction>(V))
1382 return I->getParent() == BB;
1383 return true;
1384 }
1386 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1387 /// This function emits a branch and is used at the leaves of an OR or an
1388 /// AND operator tree.
1389 ///
1390 void
1391 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1392 MachineBasicBlock *TBB,
1393 MachineBasicBlock *FBB,
1394 MachineBasicBlock *CurBB,
1395 MachineBasicBlock *SwitchBB,
1396 uint32_t TWeight,
1397 uint32_t FWeight) {
1398 const BasicBlock *BB = CurBB->getBasicBlock();
1400 // If the leaf of the tree is a comparison, merge the condition into
1401 // the caseblock.
1402 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1403 // The operands of the cmp have to be in this block. We don't know
1404 // how to export them from some other block. If this is the first block
1405 // of the sequence, no exporting is needed.
1406 if (CurBB == SwitchBB ||
1407 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1408 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1409 ISD::CondCode Condition;
1410 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1411 Condition = getICmpCondCode(IC->getPredicate());
1412 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1413 Condition = getFCmpCondCode(FC->getPredicate());
1414 if (TM.Options.NoNaNsFPMath)
1415 Condition = getFCmpCodeWithoutNaN(Condition);
1416 } else {
1417 (void)Condition; // silence warning.
1418 llvm_unreachable("Unknown compare instruction");
1419 }
1421 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1422 TBB, FBB, CurBB, TWeight, FWeight);
1423 SwitchCases.push_back(CB);
1424 return;
1425 }
1426 }
1428 // Create a CaseBlock record representing this branch.
1429 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1430 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1431 SwitchCases.push_back(CB);
1432 }
1434 /// Scale down both weights to fit into uint32_t.
1435 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1436 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1437 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1438 NewTrue = NewTrue / Scale;
1439 NewFalse = NewFalse / Scale;
1440 }
1442 /// FindMergedConditions - If Cond is an expression like
1443 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1444 MachineBasicBlock *TBB,
1445 MachineBasicBlock *FBB,
1446 MachineBasicBlock *CurBB,
1447 MachineBasicBlock *SwitchBB,
1448 unsigned Opc, uint32_t TWeight,
1449 uint32_t FWeight) {
1450 // If this node is not part of the or/and tree, emit it as a branch.
1451 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1452 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1453 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1454 BOp->getParent() != CurBB->getBasicBlock() ||
1455 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1456 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1457 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1458 TWeight, FWeight);
1459 return;
1460 }
1462 // Create TmpBB after CurBB.
1463 MachineFunction::iterator BBI = CurBB;
1464 MachineFunction &MF = DAG.getMachineFunction();
1465 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1466 CurBB->getParent()->insert(++BBI, TmpBB);
1468 if (Opc == Instruction::Or) {
1469 // Codegen X | Y as:
1470 // BB1:
1471 // jmp_if_X TBB
1472 // jmp TmpBB
1473 // TmpBB:
1474 // jmp_if_Y TBB
1475 // jmp FBB
1476 //
1478 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1479 // The requirement is that
1480 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1481 // = TrueProb for orignal BB.
1482 // Assuming the orignal weights are A and B, one choice is to set BB1's
1483 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1484 // assumes that
1485 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1486 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1487 // TmpBB, but the math is more complicated.
1489 uint64_t NewTrueWeight = TWeight;
1490 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1491 ScaleWeights(NewTrueWeight, NewFalseWeight);
1492 // Emit the LHS condition.
1493 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1494 NewTrueWeight, NewFalseWeight);
1496 NewTrueWeight = TWeight;
1497 NewFalseWeight = 2 * (uint64_t)FWeight;
1498 ScaleWeights(NewTrueWeight, NewFalseWeight);
1499 // Emit the RHS condition into TmpBB.
1500 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1501 NewTrueWeight, NewFalseWeight);
1502 } else {
1503 assert(Opc == Instruction::And && "Unknown merge op!");
1504 // Codegen X & Y as:
1505 // BB1:
1506 // jmp_if_X TmpBB
1507 // jmp FBB
1508 // TmpBB:
1509 // jmp_if_Y TBB
1510 // jmp FBB
1511 //
1512 // This requires creation of TmpBB after CurBB.
1514 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1515 // The requirement is that
1516 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1517 // = FalseProb for orignal BB.
1518 // Assuming the orignal weights are A and B, one choice is to set BB1's
1519 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1520 // assumes that
1521 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1523 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1524 uint64_t NewFalseWeight = FWeight;
1525 ScaleWeights(NewTrueWeight, NewFalseWeight);
1526 // Emit the LHS condition.
1527 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1528 NewTrueWeight, NewFalseWeight);
1530 NewTrueWeight = 2 * (uint64_t)TWeight;
1531 NewFalseWeight = FWeight;
1532 ScaleWeights(NewTrueWeight, NewFalseWeight);
1533 // Emit the RHS condition into TmpBB.
1534 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1535 NewTrueWeight, NewFalseWeight);
1536 }
1537 }
1539 /// If the set of cases should be emitted as a series of branches, return true.
1540 /// If we should emit this as a bunch of and/or'd together conditions, return
1541 /// false.
1542 bool
1543 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1544 if (Cases.size() != 2) return true;
1546 // If this is two comparisons of the same values or'd or and'd together, they
1547 // will get folded into a single comparison, so don't emit two blocks.
1548 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1549 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1550 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1551 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1552 return false;
1553 }
1555 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1556 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1557 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1558 Cases[0].CC == Cases[1].CC &&
1559 isa<Constant>(Cases[0].CmpRHS) &&
1560 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1561 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1562 return false;
1563 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1564 return false;
1565 }
1567 return true;
1568 }
1570 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1571 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1573 // Update machine-CFG edges.
1574 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1576 // Figure out which block is immediately after the current one.
1577 MachineBasicBlock *NextBlock = nullptr;
1578 MachineFunction::iterator BBI = BrMBB;
1579 if (++BBI != FuncInfo.MF->end())
1580 NextBlock = BBI;
1582 if (I.isUnconditional()) {
1583 // Update machine-CFG edges.
1584 BrMBB->addSuccessor(Succ0MBB);
1586 // If this is not a fall-through branch or optimizations are switched off,
1587 // emit the branch.
1588 if (Succ0MBB != NextBlock || TM.getOptLevel() == CodeGenOpt::None)
1589 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1590 MVT::Other, getControlRoot(),
1591 DAG.getBasicBlock(Succ0MBB)));
1593 return;
1594 }
1596 // If this condition is one of the special cases we handle, do special stuff
1597 // now.
1598 const Value *CondVal = I.getCondition();
1599 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1601 // If this is a series of conditions that are or'd or and'd together, emit
1602 // this as a sequence of branches instead of setcc's with and/or operations.
1603 // As long as jumps are not expensive, this should improve performance.
1604 // For example, instead of something like:
1605 // cmp A, B
1606 // C = seteq
1607 // cmp D, E
1608 // F = setle
1609 // or C, F
1610 // jnz foo
1611 // Emit:
1612 // cmp A, B
1613 // je foo
1614 // cmp D, E
1615 // jle foo
1616 //
1617 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1618 if (!DAG.getTargetLoweringInfo().isJumpExpensive() &&
1619 BOp->hasOneUse() && (BOp->getOpcode() == Instruction::And ||
1620 BOp->getOpcode() == Instruction::Or)) {
1621 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1622 BOp->getOpcode(), getEdgeWeight(BrMBB, Succ0MBB),
1623 getEdgeWeight(BrMBB, Succ1MBB));
1624 // If the compares in later blocks need to use values not currently
1625 // exported from this block, export them now. This block should always
1626 // be the first entry.
1627 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1629 // Allow some cases to be rejected.
1630 if (ShouldEmitAsBranches(SwitchCases)) {
1631 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1632 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1633 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1634 }
1636 // Emit the branch for this block.
1637 visitSwitchCase(SwitchCases[0], BrMBB);
1638 SwitchCases.erase(SwitchCases.begin());
1639 return;
1640 }
1642 // Okay, we decided not to do this, remove any inserted MBB's and clear
1643 // SwitchCases.
1644 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1645 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1647 SwitchCases.clear();
1648 }
1649 }
1651 // Create a CaseBlock record representing this branch.
1652 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1653 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1655 // Use visitSwitchCase to actually insert the fast branch sequence for this
1656 // cond branch.
1657 visitSwitchCase(CB, BrMBB);
1658 }
1660 /// visitSwitchCase - Emits the necessary code to represent a single node in
1661 /// the binary search tree resulting from lowering a switch instruction.
1662 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1663 MachineBasicBlock *SwitchBB) {
1664 SDValue Cond;
1665 SDValue CondLHS = getValue(CB.CmpLHS);
1666 SDLoc dl = getCurSDLoc();
1668 // Build the setcc now.
1669 if (!CB.CmpMHS) {
1670 // Fold "(X == true)" to X and "(X == false)" to !X to
1671 // handle common cases produced by branch lowering.
1672 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1673 CB.CC == ISD::SETEQ)
1674 Cond = CondLHS;
1675 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1676 CB.CC == ISD::SETEQ) {
1677 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1678 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1679 } else
1680 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1681 } else {
1682 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1684 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1685 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1687 SDValue CmpOp = getValue(CB.CmpMHS);
1688 EVT VT = CmpOp.getValueType();
1690 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1691 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1692 ISD::SETLE);
1693 } else {
1694 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1695 VT, CmpOp, DAG.getConstant(Low, VT));
1696 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1697 DAG.getConstant(High-Low, VT), ISD::SETULE);
1698 }
1699 }
1701 // Update successor info
1702 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1703 // TrueBB and FalseBB are always different unless the incoming IR is
1704 // degenerate. This only happens when running llc on weird IR.
1705 if (CB.TrueBB != CB.FalseBB)
1706 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1708 // Set NextBlock to be the MBB immediately after the current one, if any.
1709 // This is used to avoid emitting unnecessary branches to the next block.
1710 MachineBasicBlock *NextBlock = nullptr;
1711 MachineFunction::iterator BBI = SwitchBB;
1712 if (++BBI != FuncInfo.MF->end())
1713 NextBlock = BBI;
1715 // If the lhs block is the next block, invert the condition so that we can
1716 // fall through to the lhs instead of the rhs block.
1717 if (CB.TrueBB == NextBlock) {
1718 std::swap(CB.TrueBB, CB.FalseBB);
1719 SDValue True = DAG.getConstant(1, Cond.getValueType());
1720 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1721 }
1723 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1724 MVT::Other, getControlRoot(), Cond,
1725 DAG.getBasicBlock(CB.TrueBB));
1727 // Insert the false branch. Do this even if it's a fall through branch,
1728 // this makes it easier to do DAG optimizations which require inverting
1729 // the branch condition.
1730 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1731 DAG.getBasicBlock(CB.FalseBB));
1733 DAG.setRoot(BrCond);
1734 }
1736 /// visitJumpTable - Emit JumpTable node in the current MBB
1737 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1738 // Emit the code for the jump table
1739 assert(JT.Reg != -1U && "Should lower JT Header first!");
1740 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy();
1741 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1742 JT.Reg, PTy);
1743 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1744 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1745 MVT::Other, Index.getValue(1),
1746 Table, Index);
1747 DAG.setRoot(BrJumpTable);
1748 }
1750 /// visitJumpTableHeader - This function emits necessary code to produce index
1751 /// in the JumpTable from switch case.
1752 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1753 JumpTableHeader &JTH,
1754 MachineBasicBlock *SwitchBB) {
1755 // Subtract the lowest switch case value from the value being switched on and
1756 // conditional branch to default mbb if the result is greater than the
1757 // difference between smallest and largest cases.
1758 SDValue SwitchOp = getValue(JTH.SValue);
1759 EVT VT = SwitchOp.getValueType();
1760 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1761 DAG.getConstant(JTH.First, VT));
1763 // The SDNode we just created, which holds the value being switched on minus
1764 // the smallest case value, needs to be copied to a virtual register so it
1765 // can be used as an index into the jump table in a subsequent basic block.
1766 // This value may be smaller or larger than the target's pointer type, and
1767 // therefore require extension or truncating.
1768 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1769 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), TLI.getPointerTy());
1771 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1772 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1773 JumpTableReg, SwitchOp);
1774 JT.Reg = JumpTableReg;
1776 // Emit the range check for the jump table, and branch to the default block
1777 // for the switch statement if the value being switched on exceeds the largest
1778 // case in the switch.
1779 SDValue CMP =
1780 DAG.getSetCC(getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(),
1781 Sub.getValueType()),
1782 Sub, DAG.getConstant(JTH.Last - JTH.First, VT), ISD::SETUGT);
1784 // Set NextBlock to be the MBB immediately after the current one, if any.
1785 // This is used to avoid emitting unnecessary branches to the next block.
1786 MachineBasicBlock *NextBlock = nullptr;
1787 MachineFunction::iterator BBI = SwitchBB;
1789 if (++BBI != FuncInfo.MF->end())
1790 NextBlock = BBI;
1792 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1793 MVT::Other, CopyTo, CMP,
1794 DAG.getBasicBlock(JT.Default));
1796 if (JT.MBB != NextBlock)
1797 BrCond = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrCond,
1798 DAG.getBasicBlock(JT.MBB));
1800 DAG.setRoot(BrCond);
1801 }
1803 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1804 /// tail spliced into a stack protector check success bb.
1805 ///
1806 /// For a high level explanation of how this fits into the stack protector
1807 /// generation see the comment on the declaration of class
1808 /// StackProtectorDescriptor.
1809 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1810 MachineBasicBlock *ParentBB) {
1812 // First create the loads to the guard/stack slot for the comparison.
1813 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1814 EVT PtrTy = TLI.getPointerTy();
1816 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1817 int FI = MFI->getStackProtectorIndex();
1819 const Value *IRGuard = SPD.getGuard();
1820 SDValue GuardPtr = getValue(IRGuard);
1821 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1823 unsigned Align =
1824 TLI.getDataLayout()->getPrefTypeAlignment(IRGuard->getType());
1826 SDValue Guard;
1828 // If GuardReg is set and useLoadStackGuardNode returns true, retrieve the
1829 // guard value from the virtual register holding the value. Otherwise, emit a
1830 // volatile load to retrieve the stack guard value.
1831 unsigned GuardReg = SPD.getGuardReg();
1833 if (GuardReg && TLI.useLoadStackGuardNode())
1834 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), GuardReg,
1835 PtrTy);
1836 else
1837 Guard = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1838 GuardPtr, MachinePointerInfo(IRGuard, 0),
1839 true, false, false, Align);
1841 SDValue StackSlot = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1842 StackSlotPtr,
1843 MachinePointerInfo::getFixedStack(FI),
1844 true, false, false, Align);
1846 // Perform the comparison via a subtract/getsetcc.
1847 EVT VT = Guard.getValueType();
1848 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, Guard, StackSlot);
1850 SDValue Cmp =
1851 DAG.getSetCC(getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(),
1852 Sub.getValueType()),
1853 Sub, DAG.getConstant(0, VT), ISD::SETNE);
1855 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1856 // branch to failure MBB.
1857 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1858 MVT::Other, StackSlot.getOperand(0),
1859 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1860 // Otherwise branch to success MBB.
1861 SDValue Br = DAG.getNode(ISD::BR, getCurSDLoc(),
1862 MVT::Other, BrCond,
1863 DAG.getBasicBlock(SPD.getSuccessMBB()));
1865 DAG.setRoot(Br);
1866 }
1868 /// Codegen the failure basic block for a stack protector check.
1869 ///
1870 /// A failure stack protector machine basic block consists simply of a call to
1871 /// __stack_chk_fail().
1872 ///
1873 /// For a high level explanation of how this fits into the stack protector
1874 /// generation see the comment on the declaration of class
1875 /// StackProtectorDescriptor.
1876 void
1877 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1878 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1879 SDValue Chain =
1880 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
1881 nullptr, 0, false, getCurSDLoc(), false, false).second;
1882 DAG.setRoot(Chain);
1883 }
1885 /// visitBitTestHeader - This function emits necessary code to produce value
1886 /// suitable for "bit tests"
1887 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1888 MachineBasicBlock *SwitchBB) {
1889 // Subtract the minimum value
1890 SDValue SwitchOp = getValue(B.SValue);
1891 EVT VT = SwitchOp.getValueType();
1892 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1893 DAG.getConstant(B.First, VT));
1895 // Check range
1896 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1897 SDValue RangeCmp =
1898 DAG.getSetCC(getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(),
1899 Sub.getValueType()),
1900 Sub, DAG.getConstant(B.Range, VT), ISD::SETUGT);
1902 // Determine the type of the test operands.
1903 bool UsePtrType = false;
1904 if (!TLI.isTypeLegal(VT))
1905 UsePtrType = true;
1906 else {
1907 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1908 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1909 // Switch table case range are encoded into series of masks.
1910 // Just use pointer type, it's guaranteed to fit.
1911 UsePtrType = true;
1912 break;
1913 }
1914 }
1915 if (UsePtrType) {
1916 VT = TLI.getPointerTy();
1917 Sub = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), VT);
1918 }
1920 B.RegVT = VT.getSimpleVT();
1921 B.Reg = FuncInfo.CreateReg(B.RegVT);
1922 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1923 B.Reg, Sub);
1925 // Set NextBlock to be the MBB immediately after the current one, if any.
1926 // This is used to avoid emitting unnecessary branches to the next block.
1927 MachineBasicBlock *NextBlock = nullptr;
1928 MachineFunction::iterator BBI = SwitchBB;
1929 if (++BBI != FuncInfo.MF->end())
1930 NextBlock = BBI;
1932 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1934 addSuccessorWithWeight(SwitchBB, B.Default);
1935 addSuccessorWithWeight(SwitchBB, MBB);
1937 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1938 MVT::Other, CopyTo, RangeCmp,
1939 DAG.getBasicBlock(B.Default));
1941 if (MBB != NextBlock)
1942 BrRange = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, CopyTo,
1943 DAG.getBasicBlock(MBB));
1945 DAG.setRoot(BrRange);
1946 }
1948 /// visitBitTestCase - this function produces one "bit test"
1949 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1950 MachineBasicBlock* NextMBB,
1951 uint32_t BranchWeightToNext,
1952 unsigned Reg,
1953 BitTestCase &B,
1954 MachineBasicBlock *SwitchBB) {
1955 MVT VT = BB.RegVT;
1956 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1957 Reg, VT);
1958 SDValue Cmp;
1959 unsigned PopCount = CountPopulation_64(B.Mask);
1960 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1961 if (PopCount == 1) {
1962 // Testing for a single bit; just compare the shift count with what it
1963 // would need to be to shift a 1 bit in that position.
1964 Cmp = DAG.getSetCC(
1965 getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(), VT), ShiftOp,
1966 DAG.getConstant(countTrailingZeros(B.Mask), VT), ISD::SETEQ);
1967 } else if (PopCount == BB.Range) {
1968 // There is only one zero bit in the range, test for it directly.
1969 Cmp = DAG.getSetCC(
1970 getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(), VT), ShiftOp,
1971 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT), ISD::SETNE);
1972 } else {
1973 // Make desired shift
1974 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurSDLoc(), VT,
1975 DAG.getConstant(1, VT), ShiftOp);
1977 // Emit bit tests and jumps
1978 SDValue AndOp = DAG.getNode(ISD::AND, getCurSDLoc(),
1979 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1980 Cmp = DAG.getSetCC(getCurSDLoc(),
1981 TLI.getSetCCResultType(*DAG.getContext(), VT), AndOp,
1982 DAG.getConstant(0, VT), ISD::SETNE);
1983 }
1985 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1986 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1987 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
1988 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
1990 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1991 MVT::Other, getControlRoot(),
1992 Cmp, DAG.getBasicBlock(B.TargetBB));
1994 // Set NextBlock to be the MBB immediately after the current one, if any.
1995 // This is used to avoid emitting unnecessary branches to the next block.
1996 MachineBasicBlock *NextBlock = nullptr;
1997 MachineFunction::iterator BBI = SwitchBB;
1998 if (++BBI != FuncInfo.MF->end())
1999 NextBlock = BBI;
2001 if (NextMBB != NextBlock)
2002 BrAnd = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrAnd,
2003 DAG.getBasicBlock(NextMBB));
2005 DAG.setRoot(BrAnd);
2006 }
2008 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
2009 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
2011 // Retrieve successors.
2012 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
2013 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
2015 const Value *Callee(I.getCalledValue());
2016 const Function *Fn = dyn_cast<Function>(Callee);
2017 if (isa<InlineAsm>(Callee))
2018 visitInlineAsm(&I);
2019 else if (Fn && Fn->isIntrinsic()) {
2020 switch (Fn->getIntrinsicID()) {
2021 default:
2022 llvm_unreachable("Cannot invoke this intrinsic");
2023 case Intrinsic::donothing:
2024 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2025 break;
2026 case Intrinsic::experimental_patchpoint_void:
2027 case Intrinsic::experimental_patchpoint_i64:
2028 visitPatchpoint(&I, LandingPad);
2029 break;
2030 }
2031 } else
2032 LowerCallTo(&I, getValue(Callee), false, LandingPad);
2034 // If the value of the invoke is used outside of its defining block, make it
2035 // available as a virtual register.
2036 CopyToExportRegsIfNeeded(&I);
2038 // Update successor info
2039 addSuccessorWithWeight(InvokeMBB, Return);
2040 addSuccessorWithWeight(InvokeMBB, LandingPad);
2042 // Drop into normal successor.
2043 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2044 MVT::Other, getControlRoot(),
2045 DAG.getBasicBlock(Return)));
2046 }
2048 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2049 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2050 }
2052 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2053 assert(FuncInfo.MBB->isLandingPad() &&
2054 "Call to landingpad not in landing pad!");
2056 MachineBasicBlock *MBB = FuncInfo.MBB;
2057 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2058 AddLandingPadInfo(LP, MMI, MBB);
2060 // If there aren't registers to copy the values into (e.g., during SjLj
2061 // exceptions), then don't bother to create these DAG nodes.
2062 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2063 if (TLI.getExceptionPointerRegister() == 0 &&
2064 TLI.getExceptionSelectorRegister() == 0)
2065 return;
2067 SmallVector<EVT, 2> ValueVTs;
2068 ComputeValueVTs(TLI, LP.getType(), ValueVTs);
2069 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2071 // Get the two live-in registers as SDValues. The physregs have already been
2072 // copied into virtual registers.
2073 SDValue Ops[2];
2074 if (FuncInfo.ExceptionPointerVirtReg) {
2075 Ops[0] = DAG.getZExtOrTrunc(
2076 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2077 FuncInfo.ExceptionPointerVirtReg, TLI.getPointerTy()),
2078 getCurSDLoc(), ValueVTs[0]);
2079 } else {
2080 Ops[0] = DAG.getConstant(0, TLI.getPointerTy());
2081 }
2082 Ops[1] = DAG.getZExtOrTrunc(
2083 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2084 FuncInfo.ExceptionSelectorVirtReg, TLI.getPointerTy()),
2085 getCurSDLoc(), ValueVTs[1]);
2087 // Merge into one.
2088 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2089 DAG.getVTList(ValueVTs), Ops);
2090 setValue(&LP, Res);
2091 }
2093 unsigned
2094 SelectionDAGBuilder::visitLandingPadClauseBB(GlobalValue *ClauseGV,
2095 MachineBasicBlock *LPadBB) {
2096 SDValue Chain = getControlRoot();
2098 // Get the typeid that we will dispatch on later.
2099 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2100 const TargetRegisterClass *RC = TLI.getRegClassFor(TLI.getPointerTy());
2101 unsigned VReg = FuncInfo.MF->getRegInfo().createVirtualRegister(RC);
2102 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(ClauseGV);
2103 SDValue Sel = DAG.getConstant(TypeID, TLI.getPointerTy());
2104 Chain = DAG.getCopyToReg(Chain, getCurSDLoc(), VReg, Sel);
2106 // Branch to the main landing pad block.
2107 MachineBasicBlock *ClauseMBB = FuncInfo.MBB;
2108 ClauseMBB->addSuccessor(LPadBB);
2109 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, Chain,
2110 DAG.getBasicBlock(LPadBB)));
2111 return VReg;
2112 }
2114 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
2115 /// small case ranges).
2116 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
2117 CaseRecVector& WorkList,
2118 const Value* SV,
2119 MachineBasicBlock *Default,
2120 MachineBasicBlock *SwitchBB) {
2121 // Size is the number of Cases represented by this range.
2122 size_t Size = CR.Range.second - CR.Range.first;
2123 if (Size > 3)
2124 return false;
2126 // Get the MachineFunction which holds the current MBB. This is used when
2127 // inserting any additional MBBs necessary to represent the switch.
2128 MachineFunction *CurMF = FuncInfo.MF;
2130 // Figure out which block is immediately after the current one.
2131 MachineBasicBlock *NextBlock = nullptr;
2132 MachineFunction::iterator BBI = CR.CaseBB;
2134 if (++BBI != FuncInfo.MF->end())
2135 NextBlock = BBI;
2137 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2138 // If any two of the cases has the same destination, and if one value
2139 // is the same as the other, but has one bit unset that the other has set,
2140 // use bit manipulation to do two compares at once. For example:
2141 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
2142 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
2143 // TODO: Handle cases where CR.CaseBB != SwitchBB.
2144 if (Size == 2 && CR.CaseBB == SwitchBB) {
2145 Case &Small = *CR.Range.first;
2146 Case &Big = *(CR.Range.second-1);
2148 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
2149 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue();
2150 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue();
2152 // Check that there is only one bit different.
2153 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
2154 (SmallValue | BigValue) == BigValue) {
2155 // Isolate the common bit.
2156 APInt CommonBit = BigValue & ~SmallValue;
2157 assert((SmallValue | CommonBit) == BigValue &&
2158 CommonBit.countPopulation() == 1 && "Not a common bit?");
2160 SDValue CondLHS = getValue(SV);
2161 EVT VT = CondLHS.getValueType();
2162 SDLoc DL = getCurSDLoc();
2164 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
2165 DAG.getConstant(CommonBit, VT));
2166 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
2167 Or, DAG.getConstant(BigValue, VT),
2168 ISD::SETEQ);
2170 // Update successor info.
2171 // Both Small and Big will jump to Small.BB, so we sum up the weights.
2172 addSuccessorWithWeight(SwitchBB, Small.BB,
2173 Small.ExtraWeight + Big.ExtraWeight);
2174 addSuccessorWithWeight(SwitchBB, Default,
2175 // The default destination is the first successor in IR.
2176 BPI ? BPI->getEdgeWeight(SwitchBB->getBasicBlock(), (unsigned)0) : 0);
2178 // Insert the true branch.
2179 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
2180 getControlRoot(), Cond,
2181 DAG.getBasicBlock(Small.BB));
2183 // Insert the false branch.
2184 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
2185 DAG.getBasicBlock(Default));
2187 DAG.setRoot(BrCond);
2188 return true;
2189 }
2190 }
2191 }
2193 // Order cases by weight so the most likely case will be checked first.
2194 uint32_t UnhandledWeights = 0;
2195 if (BPI) {
2196 for (CaseItr I = CR.Range.first, IE = CR.Range.second; I != IE; ++I) {
2197 uint32_t IWeight = I->ExtraWeight;
2198 UnhandledWeights += IWeight;
2199 for (CaseItr J = CR.Range.first; J < I; ++J) {
2200 uint32_t JWeight = J->ExtraWeight;
2201 if (IWeight > JWeight)
2202 std::swap(*I, *J);
2203 }
2204 }
2205 }
2206 // Rearrange the case blocks so that the last one falls through if possible.
2207 Case &BackCase = *(CR.Range.second-1);
2208 if (Size > 1 &&
2209 NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
2210 // The last case block won't fall through into 'NextBlock' if we emit the
2211 // branches in this order. See if rearranging a case value would help.
2212 // We start at the bottom as it's the case with the least weight.
2213 for (Case *I = &*(CR.Range.second-2), *E = &*CR.Range.first-1; I != E; --I)
2214 if (I->BB == NextBlock) {
2215 std::swap(*I, BackCase);
2216 break;
2217 }
2218 }
2220 // Create a CaseBlock record representing a conditional branch to
2221 // the Case's target mbb if the value being switched on SV is equal
2222 // to C.
2223 MachineBasicBlock *CurBlock = CR.CaseBB;
2224 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2225 MachineBasicBlock *FallThrough;
2226 if (I != E-1) {
2227 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
2228 CurMF->insert(BBI, FallThrough);
2230 // Put SV in a virtual register to make it available from the new blocks.
2231 ExportFromCurrentBlock(SV);
2232 } else {
2233 // If the last case doesn't match, go to the default block.
2234 FallThrough = Default;
2235 }
2237 const Value *RHS, *LHS, *MHS;
2238 ISD::CondCode CC;
2239 if (I->High == I->Low) {
2240 // This is just small small case range :) containing exactly 1 case
2241 CC = ISD::SETEQ;
2242 LHS = SV; RHS = I->High; MHS = nullptr;
2243 } else {
2244 CC = ISD::SETLE;
2245 LHS = I->Low; MHS = SV; RHS = I->High;
2246 }
2248 // The false weight should be sum of all un-handled cases.
2249 UnhandledWeights -= I->ExtraWeight;
2250 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough,
2251 /* me */ CurBlock,
2252 /* trueweight */ I->ExtraWeight,
2253 /* falseweight */ UnhandledWeights);
2255 // If emitting the first comparison, just call visitSwitchCase to emit the
2256 // code into the current block. Otherwise, push the CaseBlock onto the
2257 // vector to be later processed by SDISel, and insert the node's MBB
2258 // before the next MBB.
2259 if (CurBlock == SwitchBB)
2260 visitSwitchCase(CB, SwitchBB);
2261 else
2262 SwitchCases.push_back(CB);
2264 CurBlock = FallThrough;
2265 }
2267 return true;
2268 }
2270 static inline bool areJTsAllowed(const TargetLowering &TLI) {
2271 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
2272 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
2273 }
2275 static APInt ComputeRange(const APInt &First, const APInt &Last) {
2276 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
2277 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth);
2278 return (LastExt - FirstExt + 1ULL);
2279 }
2281 /// handleJTSwitchCase - Emit jumptable for current switch case range
2282 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR,
2283 CaseRecVector &WorkList,
2284 const Value *SV,
2285 MachineBasicBlock *Default,
2286 MachineBasicBlock *SwitchBB) {
2287 Case& FrontCase = *CR.Range.first;
2288 Case& BackCase = *(CR.Range.second-1);
2290 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2291 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2293 APInt TSize(First.getBitWidth(), 0);
2294 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I)
2295 TSize += I->size();
2297 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2298 if (!areJTsAllowed(TLI) || TSize.ult(TLI.getMinimumJumpTableEntries()))
2299 return false;
2301 APInt Range = ComputeRange(First, Last);
2302 // The density is TSize / Range. Require at least 40%.
2303 // It should not be possible for IntTSize to saturate for sane code, but make
2304 // sure we handle Range saturation correctly.
2305 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10);
2306 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10);
2307 if (IntTSize * 10 < IntRange * 4)
2308 return false;
2310 DEBUG(dbgs() << "Lowering jump table\n"
2311 << "First entry: " << First << ". Last entry: " << Last << '\n'
2312 << "Range: " << Range << ". Size: " << TSize << ".\n\n");
2314 // Get the MachineFunction which holds the current MBB. This is used when
2315 // inserting any additional MBBs necessary to represent the switch.
2316 MachineFunction *CurMF = FuncInfo.MF;
2318 // Figure out which block is immediately after the current one.
2319 MachineFunction::iterator BBI = CR.CaseBB;
2320 ++BBI;
2322 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2324 // Create a new basic block to hold the code for loading the address
2325 // of the jump table, and jumping to it. Update successor information;
2326 // we will either branch to the default case for the switch, or the jump
2327 // table.
2328 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2329 CurMF->insert(BBI, JumpTableBB);
2331 addSuccessorWithWeight(CR.CaseBB, Default);
2332 addSuccessorWithWeight(CR.CaseBB, JumpTableBB);
2334 // Build a vector of destination BBs, corresponding to each target
2335 // of the jump table. If the value of the jump table slot corresponds to
2336 // a case statement, push the case's BB onto the vector, otherwise, push
2337 // the default BB.
2338 std::vector<MachineBasicBlock*> DestBBs;
2339 APInt TEI = First;
2340 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
2341 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
2342 const APInt &High = cast<ConstantInt>(I->High)->getValue();
2344 if (Low.sle(TEI) && TEI.sle(High)) {
2345 DestBBs.push_back(I->BB);
2346 if (TEI==High)
2347 ++I;
2348 } else {
2349 DestBBs.push_back(Default);
2350 }
2351 }
2353 // Calculate weight for each unique destination in CR.
2354 DenseMap<MachineBasicBlock*, uint32_t> DestWeights;
2355 if (FuncInfo.BPI)
2356 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2357 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2358 DestWeights.find(I->BB);
2359 if (Itr != DestWeights.end())
2360 Itr->second += I->ExtraWeight;
2361 else
2362 DestWeights[I->BB] = I->ExtraWeight;
2363 }
2365 // Update successor info. Add one edge to each unique successor.
2366 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
2367 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
2368 E = DestBBs.end(); I != E; ++I) {
2369 if (!SuccsHandled[(*I)->getNumber()]) {
2370 SuccsHandled[(*I)->getNumber()] = true;
2371 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2372 DestWeights.find(*I);
2373 addSuccessorWithWeight(JumpTableBB, *I,
2374 Itr != DestWeights.end() ? Itr->second : 0);
2375 }
2376 }
2378 // Create a jump table index for this jump table.
2379 unsigned JTEncoding = TLI.getJumpTableEncoding();
2380 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
2381 ->createJumpTableIndex(DestBBs);
2383 // Set the jump table information so that we can codegen it as a second
2384 // MachineBasicBlock
2385 JumpTable JT(-1U, JTI, JumpTableBB, Default);
2386 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
2387 if (CR.CaseBB == SwitchBB)
2388 visitJumpTableHeader(JT, JTH, SwitchBB);
2390 JTCases.push_back(JumpTableBlock(JTH, JT));
2391 return true;
2392 }
2394 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2395 /// 2 subtrees.
2396 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
2397 CaseRecVector& WorkList,
2398 const Value* SV,
2399 MachineBasicBlock* SwitchBB) {
2400 Case& FrontCase = *CR.Range.first;
2401 Case& BackCase = *(CR.Range.second-1);
2403 // Size is the number of Cases represented by this range.
2404 unsigned Size = CR.Range.second - CR.Range.first;
2406 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2407 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2408 double FMetric = 0;
2409 CaseItr Pivot = CR.Range.first + Size/2;
2411 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2412 // (heuristically) allow us to emit JumpTable's later.
2413 APInt TSize(First.getBitWidth(), 0);
2414 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2415 I!=E; ++I)
2416 TSize += I->size();
2418 APInt LSize = FrontCase.size();
2419 APInt RSize = TSize-LSize;
2420 DEBUG(dbgs() << "Selecting best pivot: \n"
2421 << "First: " << First << ", Last: " << Last <<'\n'
2422 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2423 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2424 J!=E; ++I, ++J) {
2425 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
2426 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
2427 APInt Range = ComputeRange(LEnd, RBegin);
2428 assert((Range - 2ULL).isNonNegative() &&
2429 "Invalid case distance");
2430 // Use volatile double here to avoid excess precision issues on some hosts,
2431 // e.g. that use 80-bit X87 registers.
2432 volatile double LDensity =
2433 LSize.roundToDouble() / (LEnd - First + 1ULL).roundToDouble();
2434 volatile double RDensity =
2435 RSize.roundToDouble() / (Last - RBegin + 1ULL).roundToDouble();
2436 volatile double Metric = Range.logBase2() * (LDensity + RDensity);
2437 // Should always split in some non-trivial place
2438 DEBUG(dbgs() <<"=>Step\n"
2439 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2440 << "LDensity: " << LDensity
2441 << ", RDensity: " << RDensity << '\n'
2442 << "Metric: " << Metric << '\n');
2443 if (FMetric < Metric) {
2444 Pivot = J;
2445 FMetric = Metric;
2446 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2447 }
2449 LSize += J->size();
2450 RSize -= J->size();
2451 }
2453 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2454 if (areJTsAllowed(TLI)) {
2455 // If our case is dense we *really* should handle it earlier!
2456 assert((FMetric > 0) && "Should handle dense range earlier!");
2457 } else {
2458 Pivot = CR.Range.first + Size/2;
2459 }
2460 splitSwitchCase(CR, Pivot, WorkList, SV, SwitchBB);
2461 return true;
2462 }
2464 void SelectionDAGBuilder::splitSwitchCase(CaseRec &CR, CaseItr Pivot,
2465 CaseRecVector &WorkList,
2466 const Value *SV,
2467 MachineBasicBlock *SwitchBB) {
2468 // Get the MachineFunction which holds the current MBB. This is used when
2469 // inserting any additional MBBs necessary to represent the switch.
2470 MachineFunction *CurMF = FuncInfo.MF;
2472 // Figure out which block is immediately after the current one.
2473 MachineFunction::iterator BBI = CR.CaseBB;
2474 ++BBI;
2476 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2478 CaseRange LHSR(CR.Range.first, Pivot);
2479 CaseRange RHSR(Pivot, CR.Range.second);
2480 const Constant *C = Pivot->Low;
2481 MachineBasicBlock *FalseBB = nullptr, *TrueBB = nullptr;
2483 // We know that we branch to the LHS if the Value being switched on is
2484 // less than the Pivot value, C. We use this to optimize our binary
2485 // tree a bit, by recognizing that if SV is greater than or equal to the
2486 // LHS's Case Value, and that Case Value is exactly one less than the
2487 // Pivot's Value, then we can branch directly to the LHS's Target,
2488 // rather than creating a leaf node for it.
2489 if ((LHSR.second - LHSR.first) == 1 && LHSR.first->High == CR.GE &&
2490 cast<ConstantInt>(C)->getValue() ==
2491 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2492 TrueBB = LHSR.first->BB;
2493 } else {
2494 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2495 CurMF->insert(BBI, TrueBB);
2496 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2498 // Put SV in a virtual register to make it available from the new blocks.
2499 ExportFromCurrentBlock(SV);
2500 }
2502 // Similar to the optimization above, if the Value being switched on is
2503 // known to be less than the Constant CR.LT, and the current Case Value
2504 // is CR.LT - 1, then we can branch directly to the target block for
2505 // the current Case Value, rather than emitting a RHS leaf node for it.
2506 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2507 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2508 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2509 FalseBB = RHSR.first->BB;
2510 } else {
2511 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2512 CurMF->insert(BBI, FalseBB);
2513 WorkList.push_back(CaseRec(FalseBB, CR.LT, C, RHSR));
2515 // Put SV in a virtual register to make it available from the new blocks.
2516 ExportFromCurrentBlock(SV);
2517 }
2519 // Create a CaseBlock record representing a conditional branch to
2520 // the LHS node if the value being switched on SV is less than C.
2521 // Otherwise, branch to LHS.
2522 CaseBlock CB(ISD::SETLT, SV, C, nullptr, TrueBB, FalseBB, CR.CaseBB);
2524 if (CR.CaseBB == SwitchBB)
2525 visitSwitchCase(CB, SwitchBB);
2526 else
2527 SwitchCases.push_back(CB);
2528 }
2530 /// handleBitTestsSwitchCase - if current case range has few destination and
2531 /// range span less, than machine word bitwidth, encode case range into series
2532 /// of masks and emit bit tests with these masks.
2533 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2534 CaseRecVector& WorkList,
2535 const Value* SV,
2536 MachineBasicBlock* Default,
2537 MachineBasicBlock* SwitchBB) {
2538 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2539 EVT PTy = TLI.getPointerTy();
2540 unsigned IntPtrBits = PTy.getSizeInBits();
2542 Case& FrontCase = *CR.Range.first;
2543 Case& BackCase = *(CR.Range.second-1);
2545 // Get the MachineFunction which holds the current MBB. This is used when
2546 // inserting any additional MBBs necessary to represent the switch.
2547 MachineFunction *CurMF = FuncInfo.MF;
2549 // If target does not have legal shift left, do not emit bit tests at all.
2550 if (!TLI.isOperationLegal(ISD::SHL, PTy))
2551 return false;
2553 size_t numCmps = 0;
2554 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2555 // Single case counts one, case range - two.
2556 numCmps += (I->Low == I->High ? 1 : 2);
2557 }
2559 // Count unique destinations
2560 SmallSet<MachineBasicBlock*, 4> Dests;
2561 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2562 Dests.insert(I->BB);
2563 if (Dests.size() > 3)
2564 // Don't bother the code below, if there are too much unique destinations
2565 return false;
2566 }
2567 DEBUG(dbgs() << "Total number of unique destinations: "
2568 << Dests.size() << '\n'
2569 << "Total number of comparisons: " << numCmps << '\n');
2571 // Compute span of values.
2572 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2573 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2574 APInt cmpRange = maxValue - minValue;
2576 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2577 << "Low bound: " << minValue << '\n'
2578 << "High bound: " << maxValue << '\n');
2580 if (cmpRange.uge(IntPtrBits) ||
2581 (!(Dests.size() == 1 && numCmps >= 3) &&
2582 !(Dests.size() == 2 && numCmps >= 5) &&
2583 !(Dests.size() >= 3 && numCmps >= 6)))
2584 return false;
2586 DEBUG(dbgs() << "Emitting bit tests\n");
2587 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2589 // Optimize the case where all the case values fit in a
2590 // word without having to subtract minValue. In this case,
2591 // we can optimize away the subtraction.
2592 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
2593 cmpRange = maxValue;
2594 } else {
2595 lowBound = minValue;
2596 }
2598 CaseBitsVector CasesBits;
2599 unsigned i, count = 0;
2601 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2602 MachineBasicBlock* Dest = I->BB;
2603 for (i = 0; i < count; ++i)
2604 if (Dest == CasesBits[i].BB)
2605 break;
2607 if (i == count) {
2608 assert((count < 3) && "Too much destinations to test!");
2609 CasesBits.push_back(CaseBits(0, Dest, 0, 0/*Weight*/));
2610 count++;
2611 }
2613 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2614 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2616 uint64_t lo = (lowValue - lowBound).getZExtValue();
2617 uint64_t hi = (highValue - lowBound).getZExtValue();
2618 CasesBits[i].ExtraWeight += I->ExtraWeight;
2620 for (uint64_t j = lo; j <= hi; j++) {
2621 CasesBits[i].Mask |= 1ULL << j;
2622 CasesBits[i].Bits++;
2623 }
2625 }
2626 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2628 BitTestInfo BTC;
2630 // Figure out which block is immediately after the current one.
2631 MachineFunction::iterator BBI = CR.CaseBB;
2632 ++BBI;
2634 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2636 DEBUG(dbgs() << "Cases:\n");
2637 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2638 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2639 << ", Bits: " << CasesBits[i].Bits
2640 << ", BB: " << CasesBits[i].BB << '\n');
2642 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2643 CurMF->insert(BBI, CaseBB);
2644 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2645 CaseBB,
2646 CasesBits[i].BB, CasesBits[i].ExtraWeight));
2648 // Put SV in a virtual register to make it available from the new blocks.
2649 ExportFromCurrentBlock(SV);
2650 }
2652 BitTestBlock BTB(lowBound, cmpRange, SV,
2653 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2654 CR.CaseBB, Default, std::move(BTC));
2656 if (CR.CaseBB == SwitchBB)
2657 visitBitTestHeader(BTB, SwitchBB);
2659 BitTestCases.push_back(std::move(BTB));
2661 return true;
2662 }
2664 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2665 void SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2666 const SwitchInst& SI) {
2667 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2668 // Start with "simple" cases.
2669 for (SwitchInst::ConstCaseIt i : SI.cases()) {
2670 const BasicBlock *SuccBB = i.getCaseSuccessor();
2671 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB];
2673 uint32_t ExtraWeight =
2674 BPI ? BPI->getEdgeWeight(SI.getParent(), i.getSuccessorIndex()) : 0;
2676 Cases.push_back(Case(i.getCaseValue(), i.getCaseValue(),
2677 SMBB, ExtraWeight));
2678 }
2679 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2681 // Merge case into clusters
2682 if (Cases.size() >= 2)
2683 // Must recompute end() each iteration because it may be
2684 // invalidated by erase if we hold on to it
2685 for (CaseItr I = Cases.begin(), J = std::next(Cases.begin());
2686 J != Cases.end(); ) {
2687 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2688 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2689 MachineBasicBlock* nextBB = J->BB;
2690 MachineBasicBlock* currentBB = I->BB;
2692 // If the two neighboring cases go to the same destination, merge them
2693 // into a single case.
2694 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2695 I->High = J->High;
2696 I->ExtraWeight += J->ExtraWeight;
2697 J = Cases.erase(J);
2698 } else {
2699 I = J++;
2700 }
2701 }
2703 DEBUG({
2704 size_t numCmps = 0;
2705 for (auto &I : Cases)
2706 // A range counts double, since it requires two compares.
2707 numCmps += I.Low != I.High ? 2 : 1;
2709 dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2710 << ". Total compares: " << numCmps << '\n';
2711 });
2712 }
2714 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2715 MachineBasicBlock *Last) {
2716 // Update JTCases.
2717 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2718 if (JTCases[i].first.HeaderBB == First)
2719 JTCases[i].first.HeaderBB = Last;
2721 // Update BitTestCases.
2722 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2723 if (BitTestCases[i].Parent == First)
2724 BitTestCases[i].Parent = Last;
2725 }
2727 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2728 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2730 // Figure out which block is immediately after the current one.
2731 MachineBasicBlock *NextBlock = nullptr;
2732 if (SwitchMBB + 1 != FuncInfo.MF->end())
2733 NextBlock = SwitchMBB + 1;
2736 // Create a vector of Cases, sorted so that we can efficiently create a binary
2737 // search tree from them.
2738 CaseVector Cases;
2739 Clusterify(Cases, SI);
2741 // Get the default destination MBB.
2742 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2744 if (isa<UnreachableInst>(SI.getDefaultDest()->getFirstNonPHIOrDbg()) &&
2745 !Cases.empty()) {
2746 // Replace an unreachable default destination with the most popular case
2747 // destination.
2748 DenseMap<const BasicBlock *, unsigned> Popularity;
2749 unsigned MaxPop = 0;
2750 const BasicBlock *MaxBB = nullptr;
2751 for (auto I : SI.cases()) {
2752 const BasicBlock *BB = I.getCaseSuccessor();
2753 if (++Popularity[BB] > MaxPop) {
2754 MaxPop = Popularity[BB];
2755 MaxBB = BB;
2756 }
2757 }
2759 // Set new default.
2760 assert(MaxPop > 0);
2761 assert(MaxBB);
2762 Default = FuncInfo.MBBMap[MaxBB];
2764 // Remove cases that were pointing to the destination that is now the default.
2765 Cases.erase(std::remove_if(Cases.begin(), Cases.end(),
2766 [&](const Case &C) { return C.BB == Default; }),
2767 Cases.end());
2768 }
2770 // If there is only the default destination, go there directly.
2771 if (Cases.empty()) {
2772 // Update machine-CFG edges.
2773 SwitchMBB->addSuccessor(Default);
2775 // If this is not a fall-through branch, emit the branch.
2776 if (Default != NextBlock) {
2777 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
2778 getControlRoot(), DAG.getBasicBlock(Default)));
2779 }
2780 return;
2781 }
2783 // Get the Value to be switched on.
2784 const Value *SV = SI.getCondition();
2786 // Push the initial CaseRec onto the worklist
2787 CaseRecVector WorkList;
2788 WorkList.push_back(CaseRec(SwitchMBB,nullptr,nullptr,
2789 CaseRange(Cases.begin(),Cases.end())));
2791 while (!WorkList.empty()) {
2792 // Grab a record representing a case range to process off the worklist
2793 CaseRec CR = WorkList.back();
2794 WorkList.pop_back();
2796 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2797 continue;
2799 // If the range has few cases (two or less) emit a series of specific
2800 // tests.
2801 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2802 continue;
2804 // If the switch has more than N blocks, and is at least 40% dense, and the
2805 // target supports indirect branches, then emit a jump table rather than
2806 // lowering the switch to a binary tree of conditional branches.
2807 // N defaults to 4 and is controlled via TLS.getMinimumJumpTableEntries().
2808 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2809 continue;
2811 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2812 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2813 handleBTSplitSwitchCase(CR, WorkList, SV, SwitchMBB);
2814 }
2815 }
2817 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2818 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2820 // Update machine-CFG edges with unique successors.
2821 SmallSet<BasicBlock*, 32> Done;
2822 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2823 BasicBlock *BB = I.getSuccessor(i);
2824 bool Inserted = Done.insert(BB).second;
2825 if (!Inserted)
2826 continue;
2828 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2829 addSuccessorWithWeight(IndirectBrMBB, Succ);
2830 }
2832 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2833 MVT::Other, getControlRoot(),
2834 getValue(I.getAddress())));
2835 }
2837 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2838 if (DAG.getTarget().Options.TrapUnreachable)
2839 DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2840 }
2842 void SelectionDAGBuilder::visitFSub(const User &I) {
2843 // -0.0 - X --> fneg
2844 Type *Ty = I.getType();
2845 if (isa<Constant>(I.getOperand(0)) &&
2846 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2847 SDValue Op2 = getValue(I.getOperand(1));
2848 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2849 Op2.getValueType(), Op2));
2850 return;
2851 }
2853 visitBinary(I, ISD::FSUB);
2854 }
2856 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2857 SDValue Op1 = getValue(I.getOperand(0));
2858 SDValue Op2 = getValue(I.getOperand(1));
2860 bool nuw = false;
2861 bool nsw = false;
2862 bool exact = false;
2863 if (const OverflowingBinaryOperator *OFBinOp =
2864 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2865 nuw = OFBinOp->hasNoUnsignedWrap();
2866 nsw = OFBinOp->hasNoSignedWrap();
2867 }
2868 if (const PossiblyExactOperator *ExactOp =
2869 dyn_cast<const PossiblyExactOperator>(&I))
2870 exact = ExactOp->isExact();
2872 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2873 Op1, Op2, nuw, nsw, exact);
2874 setValue(&I, BinNodeValue);
2875 }
2877 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2878 SDValue Op1 = getValue(I.getOperand(0));
2879 SDValue Op2 = getValue(I.getOperand(1));
2881 EVT ShiftTy =
2882 DAG.getTargetLoweringInfo().getShiftAmountTy(Op2.getValueType());
2884 // Coerce the shift amount to the right type if we can.
2885 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2886 unsigned ShiftSize = ShiftTy.getSizeInBits();
2887 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2888 SDLoc DL = getCurSDLoc();
2890 // If the operand is smaller than the shift count type, promote it.
2891 if (ShiftSize > Op2Size)
2892 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2894 // If the operand is larger than the shift count type but the shift
2895 // count type has enough bits to represent any shift value, truncate
2896 // it now. This is a common case and it exposes the truncate to
2897 // optimization early.
2898 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2899 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2900 // Otherwise we'll need to temporarily settle for some other convenient
2901 // type. Type legalization will make adjustments once the shiftee is split.
2902 else
2903 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2904 }
2906 bool nuw = false;
2907 bool nsw = false;
2908 bool exact = false;
2910 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2912 if (const OverflowingBinaryOperator *OFBinOp =
2913 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2914 nuw = OFBinOp->hasNoUnsignedWrap();
2915 nsw = OFBinOp->hasNoSignedWrap();
2916 }
2917 if (const PossiblyExactOperator *ExactOp =
2918 dyn_cast<const PossiblyExactOperator>(&I))
2919 exact = ExactOp->isExact();
2920 }
2922 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2923 nuw, nsw, exact);
2924 setValue(&I, Res);
2925 }
2927 void SelectionDAGBuilder::visitSDiv(const User &I) {
2928 SDValue Op1 = getValue(I.getOperand(0));
2929 SDValue Op2 = getValue(I.getOperand(1));
2931 // Turn exact SDivs into multiplications.
2932 // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2933 // exact bit.
2934 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2935 !isa<ConstantSDNode>(Op1) &&
2936 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2937 setValue(&I, DAG.getTargetLoweringInfo()
2938 .BuildExactSDIV(Op1, Op2, getCurSDLoc(), DAG));
2939 else
2940 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(),
2941 Op1, Op2));
2942 }
2944 void SelectionDAGBuilder::visitICmp(const User &I) {
2945 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2946 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2947 predicate = IC->getPredicate();
2948 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2949 predicate = ICmpInst::Predicate(IC->getPredicate());
2950 SDValue Op1 = getValue(I.getOperand(0));
2951 SDValue Op2 = getValue(I.getOperand(1));
2952 ISD::CondCode Opcode = getICmpCondCode(predicate);
2954 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2955 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2956 }
2958 void SelectionDAGBuilder::visitFCmp(const User &I) {
2959 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2960 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2961 predicate = FC->getPredicate();
2962 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2963 predicate = FCmpInst::Predicate(FC->getPredicate());
2964 SDValue Op1 = getValue(I.getOperand(0));
2965 SDValue Op2 = getValue(I.getOperand(1));
2966 ISD::CondCode Condition = getFCmpCondCode(predicate);
2967 if (TM.Options.NoNaNsFPMath)
2968 Condition = getFCmpCodeWithoutNaN(Condition);
2969 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2970 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2971 }
2973 void SelectionDAGBuilder::visitSelect(const User &I) {
2974 SmallVector<EVT, 4> ValueVTs;
2975 ComputeValueVTs(DAG.getTargetLoweringInfo(), I.getType(), ValueVTs);
2976 unsigned NumValues = ValueVTs.size();
2977 if (NumValues == 0) return;
2979 SmallVector<SDValue, 4> Values(NumValues);
2980 SDValue Cond = getValue(I.getOperand(0));
2981 SDValue TrueVal = getValue(I.getOperand(1));
2982 SDValue FalseVal = getValue(I.getOperand(2));
2983 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2984 ISD::VSELECT : ISD::SELECT;
2986 for (unsigned i = 0; i != NumValues; ++i)
2987 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2988 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2989 Cond,
2990 SDValue(TrueVal.getNode(),
2991 TrueVal.getResNo() + i),
2992 SDValue(FalseVal.getNode(),
2993 FalseVal.getResNo() + i));
2995 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2996 DAG.getVTList(ValueVTs), Values));
2997 }
2999 void SelectionDAGBuilder::visitTrunc(const User &I) {
3000 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
3001 SDValue N = getValue(I.getOperand(0));
3002 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3003 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
3004 }
3006 void SelectionDAGBuilder::visitZExt(const User &I) {
3007 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
3008 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
3009 SDValue N = getValue(I.getOperand(0));
3010 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3011 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
3012 }
3014 void SelectionDAGBuilder::visitSExt(const User &I) {
3015 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
3016 // SExt also can't be a cast to bool for same reason. So, nothing much to do
3017 SDValue N = getValue(I.getOperand(0));
3018 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3019 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
3020 }
3022 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
3023 // FPTrunc is never a no-op cast, no need to check
3024 SDValue N = getValue(I.getOperand(0));
3025 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3026 EVT DestVT = TLI.getValueType(I.getType());
3027 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurSDLoc(), DestVT, N,
3028 DAG.getTargetConstant(0, TLI.getPointerTy())));
3029 }
3031 void SelectionDAGBuilder::visitFPExt(const User &I) {
3032 // FPExt is never a no-op cast, no need to check
3033 SDValue N = getValue(I.getOperand(0));
3034 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3035 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
3036 }
3038 void SelectionDAGBuilder::visitFPToUI(const User &I) {
3039 // FPToUI is never a no-op cast, no need to check
3040 SDValue N = getValue(I.getOperand(0));
3041 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3042 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
3043 }
3045 void SelectionDAGBuilder::visitFPToSI(const User &I) {
3046 // FPToSI is never a no-op cast, no need to check
3047 SDValue N = getValue(I.getOperand(0));
3048 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3049 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
3050 }
3052 void SelectionDAGBuilder::visitUIToFP(const User &I) {
3053 // UIToFP is never a no-op cast, no need to check
3054 SDValue N = getValue(I.getOperand(0));
3055 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3056 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
3057 }
3059 void SelectionDAGBuilder::visitSIToFP(const User &I) {
3060 // SIToFP is never a no-op cast, no need to check
3061 SDValue N = getValue(I.getOperand(0));
3062 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3063 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
3064 }
3066 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
3067 // What to do depends on the size of the integer and the size of the pointer.
3068 // We can either truncate, zero extend, or no-op, accordingly.
3069 SDValue N = getValue(I.getOperand(0));
3070 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3071 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
3072 }
3074 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
3075 // What to do depends on the size of the integer and the size of the pointer.
3076 // We can either truncate, zero extend, or no-op, accordingly.
3077 SDValue N = getValue(I.getOperand(0));
3078 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3079 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
3080 }
3082 void SelectionDAGBuilder::visitBitCast(const User &I) {
3083 SDValue N = getValue(I.getOperand(0));
3084 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3086 // BitCast assures us that source and destination are the same size so this is
3087 // either a BITCAST or a no-op.
3088 if (DestVT != N.getValueType())
3089 setValue(&I, DAG.getNode(ISD::BITCAST, getCurSDLoc(),
3090 DestVT, N)); // convert types.
3091 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
3092 // might fold any kind of constant expression to an integer constant and that
3093 // is not what we are looking for. Only regcognize a bitcast of a genuine
3094 // constant integer as an opaque constant.
3095 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
3096 setValue(&I, DAG.getConstant(C->getValue(), DestVT, /*isTarget=*/false,
3097 /*isOpaque*/true));
3098 else
3099 setValue(&I, N); // noop cast.
3100 }
3102 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
3103 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3104 const Value *SV = I.getOperand(0);
3105 SDValue N = getValue(SV);
3106 EVT DestVT = TLI.getValueType(I.getType());
3108 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
3109 unsigned DestAS = I.getType()->getPointerAddressSpace();
3111 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
3112 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
3114 setValue(&I, N);
3115 }
3117 void SelectionDAGBuilder::visitInsertElement(const User &I) {
3118 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3119 SDValue InVec = getValue(I.getOperand(0));
3120 SDValue InVal = getValue(I.getOperand(1));
3121 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)),
3122 getCurSDLoc(), TLI.getVectorIdxTy());
3123 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
3124 TLI.getValueType(I.getType()), InVec, InVal, InIdx));
3125 }
3127 void SelectionDAGBuilder::visitExtractElement(const User &I) {
3128 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3129 SDValue InVec = getValue(I.getOperand(0));
3130 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)),
3131 getCurSDLoc(), TLI.getVectorIdxTy());
3132 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3133 TLI.getValueType(I.getType()), InVec, InIdx));
3134 }
3136 // Utility for visitShuffleVector - Return true if every element in Mask,
3137 // beginning from position Pos and ending in Pos+Size, falls within the
3138 // specified sequential range [L, L+Pos). or is undef.
3139 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
3140 unsigned Pos, unsigned Size, int Low) {
3141 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3142 if (Mask[i] >= 0 && Mask[i] != Low)
3143 return false;
3144 return true;
3145 }
3147 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
3148 SDValue Src1 = getValue(I.getOperand(0));
3149 SDValue Src2 = getValue(I.getOperand(1));
3151 SmallVector<int, 8> Mask;
3152 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
3153 unsigned MaskNumElts = Mask.size();
3155 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3156 EVT VT = TLI.getValueType(I.getType());
3157 EVT SrcVT = Src1.getValueType();
3158 unsigned SrcNumElts = SrcVT.getVectorNumElements();
3160 if (SrcNumElts == MaskNumElts) {
3161 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3162 &Mask[0]));
3163 return;
3164 }
3166 // Normalize the shuffle vector since mask and vector length don't match.
3167 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
3168 // Mask is longer than the source vectors and is a multiple of the source
3169 // vectors. We can use concatenate vector to make the mask and vectors
3170 // lengths match.
3171 if (SrcNumElts*2 == MaskNumElts) {
3172 // First check for Src1 in low and Src2 in high
3173 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
3174 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
3175 // The shuffle is concatenating two vectors together.
3176 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
3177 VT, Src1, Src2));
3178 return;
3179 }
3180 // Then check for Src2 in low and Src1 in high
3181 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
3182 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
3183 // The shuffle is concatenating two vectors together.
3184 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
3185 VT, Src2, Src1));
3186 return;
3187 }
3188 }
3190 // Pad both vectors with undefs to make them the same length as the mask.
3191 unsigned NumConcat = MaskNumElts / SrcNumElts;
3192 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
3193 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
3194 SDValue UndefVal = DAG.getUNDEF(SrcVT);
3196 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
3197 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
3198 MOps1[0] = Src1;
3199 MOps2[0] = Src2;
3201 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
3202 getCurSDLoc(), VT, MOps1);
3203 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
3204 getCurSDLoc(), VT, MOps2);
3206 // Readjust mask for new input vector length.
3207 SmallVector<int, 8> MappedOps;
3208 for (unsigned i = 0; i != MaskNumElts; ++i) {
3209 int Idx = Mask[i];
3210 if (Idx >= (int)SrcNumElts)
3211 Idx -= SrcNumElts - MaskNumElts;
3212 MappedOps.push_back(Idx);
3213 }
3215 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3216 &MappedOps[0]));
3217 return;
3218 }
3220 if (SrcNumElts > MaskNumElts) {
3221 // Analyze the access pattern of the vector to see if we can extract
3222 // two subvectors and do the shuffle. The analysis is done by calculating
3223 // the range of elements the mask access on both vectors.
3224 int MinRange[2] = { static_cast<int>(SrcNumElts),
3225 static_cast<int>(SrcNumElts)};
3226 int MaxRange[2] = {-1, -1};
3228 for (unsigned i = 0; i != MaskNumElts; ++i) {
3229 int Idx = Mask[i];
3230 unsigned Input = 0;
3231 if (Idx < 0)
3232 continue;
3234 if (Idx >= (int)SrcNumElts) {
3235 Input = 1;
3236 Idx -= SrcNumElts;
3237 }
3238 if (Idx > MaxRange[Input])
3239 MaxRange[Input] = Idx;
3240 if (Idx < MinRange[Input])
3241 MinRange[Input] = Idx;
3242 }
3244 // Check if the access is smaller than the vector size and can we find
3245 // a reasonable extract index.
3246 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
3247 // Extract.
3248 int StartIdx[2]; // StartIdx to extract from
3249 for (unsigned Input = 0; Input < 2; ++Input) {
3250 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
3251 RangeUse[Input] = 0; // Unused
3252 StartIdx[Input] = 0;
3253 continue;
3254 }
3256 // Find a good start index that is a multiple of the mask length. Then
3257 // see if the rest of the elements are in range.
3258 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
3259 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
3260 StartIdx[Input] + MaskNumElts <= SrcNumElts)
3261 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
3262 }
3264 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
3265 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
3266 return;
3267 }
3268 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
3269 // Extract appropriate subvector and generate a vector shuffle
3270 for (unsigned Input = 0; Input < 2; ++Input) {
3271 SDValue &Src = Input == 0 ? Src1 : Src2;
3272 if (RangeUse[Input] == 0)
3273 Src = DAG.getUNDEF(VT);
3274 else
3275 Src = DAG.getNode(
3276 ISD::EXTRACT_SUBVECTOR, getCurSDLoc(), VT, Src,
3277 DAG.getConstant(StartIdx[Input], TLI.getVectorIdxTy()));
3278 }
3280 // Calculate new mask.
3281 SmallVector<int, 8> MappedOps;
3282 for (unsigned i = 0; i != MaskNumElts; ++i) {
3283 int Idx = Mask[i];
3284 if (Idx >= 0) {
3285 if (Idx < (int)SrcNumElts)
3286 Idx -= StartIdx[0];
3287 else
3288 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
3289 }
3290 MappedOps.push_back(Idx);
3291 }
3293 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3294 &MappedOps[0]));
3295 return;
3296 }
3297 }
3299 // We can't use either concat vectors or extract subvectors so fall back to
3300 // replacing the shuffle with extract and build vector.
3301 // to insert and build vector.
3302 EVT EltVT = VT.getVectorElementType();
3303 EVT IdxVT = TLI.getVectorIdxTy();
3304 SmallVector<SDValue,8> Ops;
3305 for (unsigned i = 0; i != MaskNumElts; ++i) {
3306 int Idx = Mask[i];
3307 SDValue Res;
3309 if (Idx < 0) {
3310 Res = DAG.getUNDEF(EltVT);
3311 } else {
3312 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
3313 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
3315 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3316 EltVT, Src, DAG.getConstant(Idx, IdxVT));
3317 }
3319 Ops.push_back(Res);
3320 }
3322 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops));
3323 }
3325 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
3326 const Value *Op0 = I.getOperand(0);
3327 const Value *Op1 = I.getOperand(1);
3328 Type *AggTy = I.getType();
3329 Type *ValTy = Op1->getType();
3330 bool IntoUndef = isa<UndefValue>(Op0);
3331 bool FromUndef = isa<UndefValue>(Op1);
3333 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3335 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3336 SmallVector<EVT, 4> AggValueVTs;
3337 ComputeValueVTs(TLI, AggTy, AggValueVTs);
3338 SmallVector<EVT, 4> ValValueVTs;
3339 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3341 unsigned NumAggValues = AggValueVTs.size();
3342 unsigned NumValValues = ValValueVTs.size();
3343 SmallVector<SDValue, 4> Values(NumAggValues);
3345 // Ignore an insertvalue that produces an empty object
3346 if (!NumAggValues) {
3347 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3348 return;
3349 }
3351 SDValue Agg = getValue(Op0);
3352 unsigned i = 0;
3353 // Copy the beginning value(s) from the original aggregate.
3354 for (; i != LinearIndex; ++i)
3355 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3356 SDValue(Agg.getNode(), Agg.getResNo() + i);
3357 // Copy values from the inserted value(s).
3358 if (NumValValues) {
3359 SDValue Val = getValue(Op1);
3360 for (; i != LinearIndex + NumValValues; ++i)
3361 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3362 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
3363 }
3364 // Copy remaining value(s) from the original aggregate.
3365 for (; i != NumAggValues; ++i)
3366 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3367 SDValue(Agg.getNode(), Agg.getResNo() + i);
3369 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3370 DAG.getVTList(AggValueVTs), Values));
3371 }
3373 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
3374 const Value *Op0 = I.getOperand(0);
3375 Type *AggTy = Op0->getType();
3376 Type *ValTy = I.getType();
3377 bool OutOfUndef = isa<UndefValue>(Op0);
3379 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3381 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3382 SmallVector<EVT, 4> ValValueVTs;
3383 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3385 unsigned NumValValues = ValValueVTs.size();
3387 // Ignore a extractvalue that produces an empty object
3388 if (!NumValValues) {
3389 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3390 return;
3391 }
3393 SmallVector<SDValue, 4> Values(NumValValues);
3395 SDValue Agg = getValue(Op0);
3396 // Copy out the selected value(s).
3397 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
3398 Values[i - LinearIndex] =
3399 OutOfUndef ?
3400 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
3401 SDValue(Agg.getNode(), Agg.getResNo() + i);
3403 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3404 DAG.getVTList(ValValueVTs), Values));
3405 }
3407 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
3408 Value *Op0 = I.getOperand(0);
3409 // Note that the pointer operand may be a vector of pointers. Take the scalar
3410 // element which holds a pointer.
3411 Type *Ty = Op0->getType()->getScalarType();
3412 unsigned AS = Ty->getPointerAddressSpace();
3413 SDValue N = getValue(Op0);
3415 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
3416 OI != E; ++OI) {
3417 const Value *Idx = *OI;
3418 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
3419 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
3420 if (Field) {
3421 // N = N + Offset
3422 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
3423 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
3424 DAG.getConstant(Offset, N.getValueType()));
3425 }
3427 Ty = StTy->getElementType(Field);
3428 } else {
3429 Ty = cast<SequentialType>(Ty)->getElementType();
3431 // If this is a constant subscript, handle it quickly.
3432 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3433 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3434 if (CI->isZero()) continue;
3435 uint64_t Offs =
3436 DL->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
3437 SDValue OffsVal;
3438 EVT PTy = TLI.getPointerTy(AS);
3439 unsigned PtrBits = PTy.getSizeInBits();
3440 if (PtrBits < 64)
3441 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), PTy,
3442 DAG.getConstant(Offs, MVT::i64));
3443 else
3444 OffsVal = DAG.getConstant(Offs, PTy);
3446 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
3447 OffsVal);
3448 continue;
3449 }
3451 // N = N + Idx * ElementSize;
3452 APInt ElementSize =
3453 APInt(TLI.getPointerSizeInBits(AS), DL->getTypeAllocSize(Ty));
3454 SDValue IdxN = getValue(Idx);
3456 // If the index is smaller or larger than intptr_t, truncate or extend
3457 // it.
3458 IdxN = DAG.getSExtOrTrunc(IdxN, getCurSDLoc(), N.getValueType());
3460 // If this is a multiply by a power of two, turn it into a shl
3461 // immediately. This is a very common case.
3462 if (ElementSize != 1) {
3463 if (ElementSize.isPowerOf2()) {
3464 unsigned Amt = ElementSize.logBase2();
3465 IdxN = DAG.getNode(ISD::SHL, getCurSDLoc(),
3466 N.getValueType(), IdxN,
3467 DAG.getConstant(Amt, IdxN.getValueType()));
3468 } else {
3469 SDValue Scale = DAG.getConstant(ElementSize, IdxN.getValueType());
3470 IdxN = DAG.getNode(ISD::MUL, getCurSDLoc(),
3471 N.getValueType(), IdxN, Scale);
3472 }
3473 }
3475 N = DAG.getNode(ISD::ADD, getCurSDLoc(),
3476 N.getValueType(), N, IdxN);
3477 }
3478 }
3480 setValue(&I, N);
3481 }
3483 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3484 // If this is a fixed sized alloca in the entry block of the function,
3485 // allocate it statically on the stack.
3486 if (FuncInfo.StaticAllocaMap.count(&I))
3487 return; // getValue will auto-populate this.
3489 Type *Ty = I.getAllocatedType();
3490 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3491 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
3492 unsigned Align =
3493 std::max((unsigned)TLI.getDataLayout()->getPrefTypeAlignment(Ty),
3494 I.getAlignment());
3496 SDValue AllocSize = getValue(I.getArraySize());
3498 EVT IntPtr = TLI.getPointerTy();
3499 if (AllocSize.getValueType() != IntPtr)
3500 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurSDLoc(), IntPtr);
3502 AllocSize = DAG.getNode(ISD::MUL, getCurSDLoc(), IntPtr,
3503 AllocSize,
3504 DAG.getConstant(TySize, IntPtr));
3506 // Handle alignment. If the requested alignment is less than or equal to
3507 // the stack alignment, ignore it. If the size is greater than or equal to
3508 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3509 unsigned StackAlign =
3510 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
3511 if (Align <= StackAlign)
3512 Align = 0;
3514 // Round the size of the allocation up to the stack alignment size
3515 // by add SA-1 to the size.
3516 AllocSize = DAG.getNode(ISD::ADD, getCurSDLoc(),
3517 AllocSize.getValueType(), AllocSize,
3518 DAG.getIntPtrConstant(StackAlign-1));
3520 // Mask out the low bits for alignment purposes.
3521 AllocSize = DAG.getNode(ISD::AND, getCurSDLoc(),
3522 AllocSize.getValueType(), AllocSize,
3523 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
3525 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
3526 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3527 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurSDLoc(), VTs, Ops);
3528 setValue(&I, DSA);
3529 DAG.setRoot(DSA.getValue(1));
3531 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
3532 }
3534 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3535 if (I.isAtomic())
3536 return visitAtomicLoad(I);
3538 const Value *SV = I.getOperand(0);
3539 SDValue Ptr = getValue(SV);
3541 Type *Ty = I.getType();
3543 bool isVolatile = I.isVolatile();
3544 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3545 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr;
3546 unsigned Alignment = I.getAlignment();
3548 AAMDNodes AAInfo;
3549 I.getAAMetadata(AAInfo);
3550 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3552 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3553 SmallVector<EVT, 4> ValueVTs;
3554 SmallVector<uint64_t, 4> Offsets;
3555 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
3556 unsigned NumValues = ValueVTs.size();
3557 if (NumValues == 0)
3558 return;
3560 SDValue Root;
3561 bool ConstantMemory = false;
3562 if (isVolatile || NumValues > MaxParallelChains)
3563 // Serialize volatile loads with other side effects.
3564 Root = getRoot();
3565 else if (AA->pointsToConstantMemory(
3566 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), AAInfo))) {
3567 // Do not serialize (non-volatile) loads of constant memory with anything.
3568 Root = DAG.getEntryNode();
3569 ConstantMemory = true;
3570 } else {
3571 // Do not serialize non-volatile loads against each other.
3572 Root = DAG.getRoot();
3573 }
3575 if (isVolatile)
3576 Root = TLI.prepareVolatileOrAtomicLoad(Root, getCurSDLoc(), DAG);
3578 SmallVector<SDValue, 4> Values(NumValues);
3579 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3580 NumValues));
3581 EVT PtrVT = Ptr.getValueType();
3582 unsigned ChainI = 0;
3583 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3584 // Serializing loads here may result in excessive register pressure, and
3585 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3586 // could recover a bit by hoisting nodes upward in the chain by recognizing
3587 // they are side-effect free or do not alias. The optimizer should really
3588 // avoid this case by converting large object/array copies to llvm.memcpy
3589 // (MaxParallelChains should always remain as failsafe).
3590 if (ChainI == MaxParallelChains) {
3591 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3592 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3593 makeArrayRef(Chains.data(), ChainI));
3594 Root = Chain;
3595 ChainI = 0;
3596 }
3597 SDValue A = DAG.getNode(ISD::ADD, getCurSDLoc(),
3598 PtrVT, Ptr,
3599 DAG.getConstant(Offsets[i], PtrVT));
3600 SDValue L = DAG.getLoad(ValueVTs[i], getCurSDLoc(), Root,
3601 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3602 isNonTemporal, isInvariant, Alignment, AAInfo,
3603 Ranges);
3605 Values[i] = L;
3606 Chains[ChainI] = L.getValue(1);
3607 }
3609 if (!ConstantMemory) {
3610 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3611 makeArrayRef(Chains.data(), ChainI));
3612 if (isVolatile)
3613 DAG.setRoot(Chain);
3614 else
3615 PendingLoads.push_back(Chain);
3616 }
3618 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3619 DAG.getVTList(ValueVTs), Values));
3620 }
3622 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3623 if (I.isAtomic())
3624 return visitAtomicStore(I);
3626 const Value *SrcV = I.getOperand(0);
3627 const Value *PtrV = I.getOperand(1);
3629 SmallVector<EVT, 4> ValueVTs;
3630 SmallVector<uint64_t, 4> Offsets;
3631 ComputeValueVTs(DAG.getTargetLoweringInfo(), SrcV->getType(),
3632 ValueVTs, &Offsets);
3633 unsigned NumValues = ValueVTs.size();
3634 if (NumValues == 0)
3635 return;
3637 // Get the lowered operands. Note that we do this after
3638 // checking if NumResults is zero, because with zero results
3639 // the operands won't have values in the map.
3640 SDValue Src = getValue(SrcV);
3641 SDValue Ptr = getValue(PtrV);
3643 SDValue Root = getRoot();
3644 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3645 NumValues));
3646 EVT PtrVT = Ptr.getValueType();
3647 bool isVolatile = I.isVolatile();
3648 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3649 unsigned Alignment = I.getAlignment();
3651 AAMDNodes AAInfo;
3652 I.getAAMetadata(AAInfo);
3654 unsigned ChainI = 0;
3655 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3656 // See visitLoad comments.
3657 if (ChainI == MaxParallelChains) {
3658 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3659 makeArrayRef(Chains.data(), ChainI));
3660 Root = Chain;
3661 ChainI = 0;
3662 }
3663 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), PtrVT, Ptr,
3664 DAG.getConstant(Offsets[i], PtrVT));
3665 SDValue St = DAG.getStore(Root, getCurSDLoc(),
3666 SDValue(Src.getNode(), Src.getResNo() + i),
3667 Add, MachinePointerInfo(PtrV, Offsets[i]),
3668 isVolatile, isNonTemporal, Alignment, AAInfo);
3669 Chains[ChainI] = St;
3670 }
3672 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3673 makeArrayRef(Chains.data(), ChainI));
3674 DAG.setRoot(StoreNode);
3675 }
3677 void SelectionDAGBuilder::visitMaskedStore(const CallInst &I) {
3678 SDLoc sdl = getCurSDLoc();
3680 // llvm.masked.store.*(Src0, Ptr, alignemt, Mask)
3681 Value *PtrOperand = I.getArgOperand(1);
3682 SDValue Ptr = getValue(PtrOperand);
3683 SDValue Src0 = getValue(I.getArgOperand(0));
3684 SDValue Mask = getValue(I.getArgOperand(3));
3685 EVT VT = Src0.getValueType();
3686 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3687 if (!Alignment)
3688 Alignment = DAG.getEVTAlignment(VT);
3690 AAMDNodes AAInfo;
3691 I.getAAMetadata(AAInfo);
3693 MachineMemOperand *MMO =
3694 DAG.getMachineFunction().
3695 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3696 MachineMemOperand::MOStore, VT.getStoreSize(),
3697 Alignment, AAInfo);
3698 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, MMO);
3699 DAG.setRoot(StoreNode);
3700 setValue(&I, StoreNode);
3701 }
3703 void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I) {
3704 SDLoc sdl = getCurSDLoc();
3706 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
3707 Value *PtrOperand = I.getArgOperand(0);
3708 SDValue Ptr = getValue(PtrOperand);
3709 SDValue Src0 = getValue(I.getArgOperand(3));
3710 SDValue Mask = getValue(I.getArgOperand(2));
3712 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3713 EVT VT = TLI.getValueType(I.getType());
3714 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3715 if (!Alignment)
3716 Alignment = DAG.getEVTAlignment(VT);
3718 AAMDNodes AAInfo;
3719 I.getAAMetadata(AAInfo);
3720 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3722 SDValue InChain = DAG.getRoot();
3723 if (AA->pointsToConstantMemory(
3724 AliasAnalysis::Location(PtrOperand,
3725 AA->getTypeStoreSize(I.getType()),
3726 AAInfo))) {
3727 // Do not serialize (non-volatile) loads of constant memory with anything.
3728 InChain = DAG.getEntryNode();
3729 }
3731 MachineMemOperand *MMO =
3732 DAG.getMachineFunction().
3733 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3734 MachineMemOperand::MOLoad, VT.getStoreSize(),
3735 Alignment, AAInfo, Ranges);
3737 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, MMO);
3738 SDValue OutChain = Load.getValue(1);
3739 DAG.setRoot(OutChain);
3740 setValue(&I, Load);
3741 }
3743 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3744 SDLoc dl = getCurSDLoc();
3745 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3746 AtomicOrdering FailureOrder = I.getFailureOrdering();
3747 SynchronizationScope Scope = I.getSynchScope();
3749 SDValue InChain = getRoot();
3751 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3752 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3753 SDValue L = DAG.getAtomicCmpSwap(
3754 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3755 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3756 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3757 /*Alignment=*/ 0, SuccessOrder, FailureOrder, Scope);
3759 SDValue OutChain = L.getValue(2);
3761 setValue(&I, L);
3762 DAG.setRoot(OutChain);
3763 }
3765 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3766 SDLoc dl = getCurSDLoc();
3767 ISD::NodeType NT;
3768 switch (I.getOperation()) {
3769 default: llvm_unreachable("Unknown atomicrmw operation");
3770 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3771 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3772 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3773 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3774 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3775 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3776 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3777 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3778 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3779 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3780 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3781 }
3782 AtomicOrdering Order = I.getOrdering();
3783 SynchronizationScope Scope = I.getSynchScope();
3785 SDValue InChain = getRoot();
3787 SDValue L =
3788 DAG.getAtomic(NT, dl,
3789 getValue(I.getValOperand()).getSimpleValueType(),
3790 InChain,
3791 getValue(I.getPointerOperand()),
3792 getValue(I.getValOperand()),
3793 I.getPointerOperand(),
3794 /* Alignment=*/ 0, Order, Scope);
3796 SDValue OutChain = L.getValue(1);
3798 setValue(&I, L);
3799 DAG.setRoot(OutChain);
3800 }
3802 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3803 SDLoc dl = getCurSDLoc();
3804 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3805 SDValue Ops[3];
3806 Ops[0] = getRoot();
3807 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy());
3808 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy());
3809 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3810 }
3812 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3813 SDLoc dl = getCurSDLoc();
3814 AtomicOrdering Order = I.getOrdering();
3815 SynchronizationScope Scope = I.getSynchScope();
3817 SDValue InChain = getRoot();
3819 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3820 EVT VT = TLI.getValueType(I.getType());
3822 if (I.getAlignment() < VT.getSizeInBits() / 8)
3823 report_fatal_error("Cannot generate unaligned atomic load");
3825 MachineMemOperand *MMO =
3826 DAG.getMachineFunction().
3827 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3828 MachineMemOperand::MOVolatile |
3829 MachineMemOperand::MOLoad,
3830 VT.getStoreSize(),
3831 I.getAlignment() ? I.getAlignment() :
3832 DAG.getEVTAlignment(VT));
3834 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3835 SDValue L =
3836 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3837 getValue(I.getPointerOperand()), MMO,
3838 Order, Scope);
3840 SDValue OutChain = L.getValue(1);
3842 setValue(&I, L);
3843 DAG.setRoot(OutChain);
3844 }
3846 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3847 SDLoc dl = getCurSDLoc();
3849 AtomicOrdering Order = I.getOrdering();
3850 SynchronizationScope Scope = I.getSynchScope();
3852 SDValue InChain = getRoot();
3854 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3855 EVT VT = TLI.getValueType(I.getValueOperand()->getType());
3857 if (I.getAlignment() < VT.getSizeInBits() / 8)
3858 report_fatal_error("Cannot generate unaligned atomic store");
3860 SDValue OutChain =
3861 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3862 InChain,
3863 getValue(I.getPointerOperand()),
3864 getValue(I.getValueOperand()),
3865 I.getPointerOperand(), I.getAlignment(),
3866 Order, Scope);
3868 DAG.setRoot(OutChain);
3869 }
3871 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3872 /// node.
3873 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3874 unsigned Intrinsic) {
3875 bool HasChain = !I.doesNotAccessMemory();
3876 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3878 // Build the operand list.
3879 SmallVector<SDValue, 8> Ops;
3880 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3881 if (OnlyLoad) {
3882 // We don't need to serialize loads against other loads.
3883 Ops.push_back(DAG.getRoot());
3884 } else {
3885 Ops.push_back(getRoot());
3886 }
3887 }
3889 // Info is set by getTgtMemInstrinsic
3890 TargetLowering::IntrinsicInfo Info;
3891 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3892 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3894 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3895 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3896 Info.opc == ISD::INTRINSIC_W_CHAIN)
3897 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI.getPointerTy()));
3899 // Add all operands of the call to the operand list.
3900 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3901 SDValue Op = getValue(I.getArgOperand(i));
3902 Ops.push_back(Op);
3903 }
3905 SmallVector<EVT, 4> ValueVTs;
3906 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3908 if (HasChain)
3909 ValueVTs.push_back(MVT::Other);
3911 SDVTList VTs = DAG.getVTList(ValueVTs);
3913 // Create the node.
3914 SDValue Result;
3915 if (IsTgtIntrinsic) {
3916 // This is target intrinsic that touches memory
3917 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3918 VTs, Ops, Info.memVT,
3919 MachinePointerInfo(Info.ptrVal, Info.offset),
3920 Info.align, Info.vol,
3921 Info.readMem, Info.writeMem, Info.size);
3922 } else if (!HasChain) {
3923 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3924 } else if (!I.getType()->isVoidTy()) {
3925 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3926 } else {
3927 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3928 }
3930 if (HasChain) {
3931 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3932 if (OnlyLoad)
3933 PendingLoads.push_back(Chain);
3934 else
3935 DAG.setRoot(Chain);
3936 }
3938 if (!I.getType()->isVoidTy()) {
3939 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3940 EVT VT = TLI.getValueType(PTy);
3941 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3942 }
3944 setValue(&I, Result);
3945 }
3946 }
3948 /// GetSignificand - Get the significand and build it into a floating-point
3949 /// number with exponent of 1:
3950 ///
3951 /// Op = (Op & 0x007fffff) | 0x3f800000;
3952 ///
3953 /// where Op is the hexadecimal representation of floating point value.
3954 static SDValue
3955 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3956 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3957 DAG.getConstant(0x007fffff, MVT::i32));
3958 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3959 DAG.getConstant(0x3f800000, MVT::i32));
3960 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3961 }
3963 /// GetExponent - Get the exponent:
3964 ///
3965 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3966 ///
3967 /// where Op is the hexadecimal representation of floating point value.
3968 static SDValue
3969 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3970 SDLoc dl) {
3971 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3972 DAG.getConstant(0x7f800000, MVT::i32));
3973 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3974 DAG.getConstant(23, TLI.getPointerTy()));
3975 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3976 DAG.getConstant(127, MVT::i32));
3977 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3978 }
3980 /// getF32Constant - Get 32-bit floating point constant.
3981 static SDValue
3982 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3983 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)),
3984 MVT::f32);
3985 }
3987 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3988 /// limited-precision mode.
3989 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3990 const TargetLowering &TLI) {
3991 if (Op.getValueType() == MVT::f32 &&
3992 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3994 // Put the exponent in the right bit position for later addition to the
3995 // final result:
3996 //
3997 // #define LOG2OFe 1.4426950f
3998 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3999 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
4000 getF32Constant(DAG, 0x3fb8aa3b));
4001 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
4003 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
4004 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4005 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
4007 // IntegerPartOfX <<= 23;
4008 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4009 DAG.getConstant(23, TLI.getPointerTy()));
4011 SDValue TwoToFracPartOfX;
4012 if (LimitFloatPrecision <= 6) {
4013 // For floating-point precision of 6:
4014 //
4015 // TwoToFractionalPartOfX =
4016 // 0.997535578f +
4017 // (0.735607626f + 0.252464424f * x) * x;
4018 //
4019 // error 0.0144103317, which is 6 bits
4020 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4021 getF32Constant(DAG, 0x3e814304));
4022 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4023 getF32Constant(DAG, 0x3f3c50c8));
4024 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4025 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4026 getF32Constant(DAG, 0x3f7f5e7e));
4027 } else if (LimitFloatPrecision <= 12) {
4028 // For floating-point precision of 12:
4029 //
4030 // TwoToFractionalPartOfX =
4031 // 0.999892986f +
4032 // (0.696457318f +
4033 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4034 //
4035 // 0.000107046256 error, which is 13 to 14 bits
4036 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4037 getF32Constant(DAG, 0x3da235e3));
4038 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4039 getF32Constant(DAG, 0x3e65b8f3));
4040 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4041 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4042 getF32Constant(DAG, 0x3f324b07));
4043 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4044 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4045 getF32Constant(DAG, 0x3f7ff8fd));
4046 } else { // LimitFloatPrecision <= 18
4047 // For floating-point precision of 18:
4048 //
4049 // TwoToFractionalPartOfX =
4050 // 0.999999982f +
4051 // (0.693148872f +
4052 // (0.240227044f +
4053 // (0.554906021e-1f +
4054 // (0.961591928e-2f +
4055 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4056 //
4057 // error 2.47208000*10^(-7), which is better than 18 bits
4058 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4059 getF32Constant(DAG, 0x3924b03e));
4060 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4061 getF32Constant(DAG, 0x3ab24b87));
4062 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4063 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4064 getF32Constant(DAG, 0x3c1d8c17));
4065 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4066 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4067 getF32Constant(DAG, 0x3d634a1d));
4068 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4069 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4070 getF32Constant(DAG, 0x3e75fe14));
4071 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4072 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4073 getF32Constant(DAG, 0x3f317234));
4074 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4075 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4076 getF32Constant(DAG, 0x3f800000));
4077 }
4079 // Add the exponent into the result in integer domain.
4080 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFracPartOfX);
4081 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4082 DAG.getNode(ISD::ADD, dl, MVT::i32,
4083 t13, IntegerPartOfX));
4084 }
4086 // No special expansion.
4087 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
4088 }
4090 /// expandLog - Lower a log intrinsic. Handles the special sequences for
4091 /// limited-precision mode.
4092 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4093 const TargetLowering &TLI) {
4094 if (Op.getValueType() == MVT::f32 &&
4095 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4096 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4098 // Scale the exponent by log(2) [0.69314718f].
4099 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4100 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4101 getF32Constant(DAG, 0x3f317218));
4103 // Get the significand and build it into a floating-point number with
4104 // exponent of 1.
4105 SDValue X = GetSignificand(DAG, Op1, dl);
4107 SDValue LogOfMantissa;
4108 if (LimitFloatPrecision <= 6) {
4109 // For floating-point precision of 6:
4110 //
4111 // LogofMantissa =
4112 // -1.1609546f +
4113 // (1.4034025f - 0.23903021f * x) * x;
4114 //
4115 // error 0.0034276066, which is better than 8 bits
4116 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4117 getF32Constant(DAG, 0xbe74c456));
4118 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4119 getF32Constant(DAG, 0x3fb3a2b1));
4120 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4121 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4122 getF32Constant(DAG, 0x3f949a29));
4123 } else if (LimitFloatPrecision <= 12) {
4124 // For floating-point precision of 12:
4125 //
4126 // LogOfMantissa =
4127 // -1.7417939f +
4128 // (2.8212026f +
4129 // (-1.4699568f +
4130 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
4131 //
4132 // error 0.000061011436, which is 14 bits
4133 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4134 getF32Constant(DAG, 0xbd67b6d6));
4135 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4136 getF32Constant(DAG, 0x3ee4f4b8));
4137 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4138 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4139 getF32Constant(DAG, 0x3fbc278b));
4140 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4141 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4142 getF32Constant(DAG, 0x40348e95));
4143 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4144 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4145 getF32Constant(DAG, 0x3fdef31a));
4146 } else { // LimitFloatPrecision <= 18
4147 // For floating-point precision of 18:
4148 //
4149 // LogOfMantissa =
4150 // -2.1072184f +
4151 // (4.2372794f +
4152 // (-3.7029485f +
4153 // (2.2781945f +
4154 // (-0.87823314f +
4155 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
4156 //
4157 // error 0.0000023660568, which is better than 18 bits
4158 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4159 getF32Constant(DAG, 0xbc91e5ac));
4160 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4161 getF32Constant(DAG, 0x3e4350aa));
4162 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4163 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4164 getF32Constant(DAG, 0x3f60d3e3));
4165 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4166 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4167 getF32Constant(DAG, 0x4011cdf0));
4168 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4169 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4170 getF32Constant(DAG, 0x406cfd1c));
4171 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4172 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4173 getF32Constant(DAG, 0x408797cb));
4174 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4175 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4176 getF32Constant(DAG, 0x4006dcab));
4177 }
4179 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
4180 }
4182 // No special expansion.
4183 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
4184 }
4186 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
4187 /// limited-precision mode.
4188 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4189 const TargetLowering &TLI) {
4190 if (Op.getValueType() == MVT::f32 &&
4191 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4192 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4194 // Get the exponent.
4195 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
4197 // Get the significand and build it into a floating-point number with
4198 // exponent of 1.
4199 SDValue X = GetSignificand(DAG, Op1, dl);
4201 // Different possible minimax approximations of significand in
4202 // floating-point for various degrees of accuracy over [1,2].
4203 SDValue Log2ofMantissa;
4204 if (LimitFloatPrecision <= 6) {
4205 // For floating-point precision of 6:
4206 //
4207 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
4208 //
4209 // error 0.0049451742, which is more than 7 bits
4210 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4211 getF32Constant(DAG, 0xbeb08fe0));
4212 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4213 getF32Constant(DAG, 0x40019463));
4214 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4215 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4216 getF32Constant(DAG, 0x3fd6633d));
4217 } else if (LimitFloatPrecision <= 12) {
4218 // For floating-point precision of 12:
4219 //
4220 // Log2ofMantissa =
4221 // -2.51285454f +
4222 // (4.07009056f +
4223 // (-2.12067489f +
4224 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
4225 //
4226 // error 0.0000876136000, which is better than 13 bits
4227 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4228 getF32Constant(DAG, 0xbda7262e));
4229 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4230 getF32Constant(DAG, 0x3f25280b));
4231 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4232 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4233 getF32Constant(DAG, 0x4007b923));
4234 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4235 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4236 getF32Constant(DAG, 0x40823e2f));
4237 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4238 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4239 getF32Constant(DAG, 0x4020d29c));
4240 } else { // LimitFloatPrecision <= 18
4241 // For floating-point precision of 18:
4242 //
4243 // Log2ofMantissa =
4244 // -3.0400495f +
4245 // (6.1129976f +
4246 // (-5.3420409f +
4247 // (3.2865683f +
4248 // (-1.2669343f +
4249 // (0.27515199f -
4250 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
4251 //
4252 // error 0.0000018516, which is better than 18 bits
4253 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4254 getF32Constant(DAG, 0xbcd2769e));
4255 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4256 getF32Constant(DAG, 0x3e8ce0b9));
4257 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4258 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4259 getF32Constant(DAG, 0x3fa22ae7));
4260 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4261 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4262 getF32Constant(DAG, 0x40525723));
4263 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4264 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4265 getF32Constant(DAG, 0x40aaf200));
4266 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4267 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4268 getF32Constant(DAG, 0x40c39dad));
4269 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4270 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4271 getF32Constant(DAG, 0x4042902c));
4272 }
4274 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
4275 }
4277 // No special expansion.
4278 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
4279 }
4281 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
4282 /// limited-precision mode.
4283 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4284 const TargetLowering &TLI) {
4285 if (Op.getValueType() == MVT::f32 &&
4286 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4287 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4289 // Scale the exponent by log10(2) [0.30102999f].
4290 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4291 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4292 getF32Constant(DAG, 0x3e9a209a));
4294 // Get the significand and build it into a floating-point number with
4295 // exponent of 1.
4296 SDValue X = GetSignificand(DAG, Op1, dl);
4298 SDValue Log10ofMantissa;
4299 if (LimitFloatPrecision <= 6) {
4300 // For floating-point precision of 6:
4301 //
4302 // Log10ofMantissa =
4303 // -0.50419619f +
4304 // (0.60948995f - 0.10380950f * x) * x;
4305 //
4306 // error 0.0014886165, which is 6 bits
4307 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4308 getF32Constant(DAG, 0xbdd49a13));
4309 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4310 getF32Constant(DAG, 0x3f1c0789));
4311 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4312 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4313 getF32Constant(DAG, 0x3f011300));
4314 } else if (LimitFloatPrecision <= 12) {
4315 // For floating-point precision of 12:
4316 //
4317 // Log10ofMantissa =
4318 // -0.64831180f +
4319 // (0.91751397f +
4320 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4321 //
4322 // error 0.00019228036, which is better than 12 bits
4323 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4324 getF32Constant(DAG, 0x3d431f31));
4325 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4326 getF32Constant(DAG, 0x3ea21fb2));
4327 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4328 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4329 getF32Constant(DAG, 0x3f6ae232));
4330 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4331 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4332 getF32Constant(DAG, 0x3f25f7c3));
4333 } else { // LimitFloatPrecision <= 18
4334 // For floating-point precision of 18:
4335 //
4336 // Log10ofMantissa =
4337 // -0.84299375f +
4338 // (1.5327582f +
4339 // (-1.0688956f +
4340 // (0.49102474f +
4341 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4342 //
4343 // error 0.0000037995730, which is better than 18 bits
4344 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4345 getF32Constant(DAG, 0x3c5d51ce));
4346 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4347 getF32Constant(DAG, 0x3e00685a));
4348 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4349 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4350 getF32Constant(DAG, 0x3efb6798));
4351 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4352 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4353 getF32Constant(DAG, 0x3f88d192));
4354 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4355 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4356 getF32Constant(DAG, 0x3fc4316c));
4357 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4358 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4359 getF32Constant(DAG, 0x3f57ce70));
4360 }
4362 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4363 }
4365 // No special expansion.
4366 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4367 }
4369 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4370 /// limited-precision mode.
4371 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4372 const TargetLowering &TLI) {
4373 if (Op.getValueType() == MVT::f32 &&
4374 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4375 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
4377 // FractionalPartOfX = x - (float)IntegerPartOfX;
4378 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4379 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
4381 // IntegerPartOfX <<= 23;
4382 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4383 DAG.getConstant(23, TLI.getPointerTy()));
4385 SDValue TwoToFractionalPartOfX;
4386 if (LimitFloatPrecision <= 6) {
4387 // For floating-point precision of 6:
4388 //
4389 // TwoToFractionalPartOfX =
4390 // 0.997535578f +
4391 // (0.735607626f + 0.252464424f * x) * x;
4392 //
4393 // error 0.0144103317, which is 6 bits
4394 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4395 getF32Constant(DAG, 0x3e814304));
4396 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4397 getF32Constant(DAG, 0x3f3c50c8));
4398 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4399 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4400 getF32Constant(DAG, 0x3f7f5e7e));
4401 } else if (LimitFloatPrecision <= 12) {
4402 // For floating-point precision of 12:
4403 //
4404 // TwoToFractionalPartOfX =
4405 // 0.999892986f +
4406 // (0.696457318f +
4407 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4408 //
4409 // error 0.000107046256, which is 13 to 14 bits
4410 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4411 getF32Constant(DAG, 0x3da235e3));
4412 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4413 getF32Constant(DAG, 0x3e65b8f3));
4414 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4415 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4416 getF32Constant(DAG, 0x3f324b07));
4417 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4418 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4419 getF32Constant(DAG, 0x3f7ff8fd));
4420 } else { // LimitFloatPrecision <= 18
4421 // For floating-point precision of 18:
4422 //
4423 // TwoToFractionalPartOfX =
4424 // 0.999999982f +
4425 // (0.693148872f +
4426 // (0.240227044f +
4427 // (0.554906021e-1f +
4428 // (0.961591928e-2f +
4429 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4430 // error 2.47208000*10^(-7), which is better than 18 bits
4431 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4432 getF32Constant(DAG, 0x3924b03e));
4433 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4434 getF32Constant(DAG, 0x3ab24b87));
4435 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4436 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4437 getF32Constant(DAG, 0x3c1d8c17));
4438 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4439 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4440 getF32Constant(DAG, 0x3d634a1d));
4441 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4442 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4443 getF32Constant(DAG, 0x3e75fe14));
4444 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4445 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4446 getF32Constant(DAG, 0x3f317234));
4447 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4448 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4449 getF32Constant(DAG, 0x3f800000));
4450 }
4452 // Add the exponent into the result in integer domain.
4453 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32,
4454 TwoToFractionalPartOfX);
4455 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4456 DAG.getNode(ISD::ADD, dl, MVT::i32,
4457 t13, IntegerPartOfX));
4458 }
4460 // No special expansion.
4461 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4462 }
4464 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4465 /// limited-precision mode with x == 10.0f.
4466 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
4467 SelectionDAG &DAG, const TargetLowering &TLI) {
4468 bool IsExp10 = false;
4469 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
4470 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4471 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4472 APFloat Ten(10.0f);
4473 IsExp10 = LHSC->isExactlyValue(Ten);
4474 }
4475 }
4477 if (IsExp10) {
4478 // Put the exponent in the right bit position for later addition to the
4479 // final result:
4480 //
4481 // #define LOG2OF10 3.3219281f
4482 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
4483 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4484 getF32Constant(DAG, 0x40549a78));
4485 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
4487 // FractionalPartOfX = x - (float)IntegerPartOfX;
4488 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4489 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
4491 // IntegerPartOfX <<= 23;
4492 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4493 DAG.getConstant(23, TLI.getPointerTy()));
4495 SDValue TwoToFractionalPartOfX;
4496 if (LimitFloatPrecision <= 6) {
4497 // For floating-point precision of 6:
4498 //
4499 // twoToFractionalPartOfX =
4500 // 0.997535578f +
4501 // (0.735607626f + 0.252464424f * x) * x;
4502 //
4503 // error 0.0144103317, which is 6 bits
4504 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4505 getF32Constant(DAG, 0x3e814304));
4506 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4507 getF32Constant(DAG, 0x3f3c50c8));
4508 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4509 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4510 getF32Constant(DAG, 0x3f7f5e7e));
4511 } else if (LimitFloatPrecision <= 12) {
4512 // For floating-point precision of 12:
4513 //
4514 // TwoToFractionalPartOfX =
4515 // 0.999892986f +
4516 // (0.696457318f +
4517 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4518 //
4519 // error 0.000107046256, which is 13 to 14 bits
4520 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4521 getF32Constant(DAG, 0x3da235e3));
4522 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4523 getF32Constant(DAG, 0x3e65b8f3));
4524 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4525 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4526 getF32Constant(DAG, 0x3f324b07));
4527 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4528 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4529 getF32Constant(DAG, 0x3f7ff8fd));
4530 } else { // LimitFloatPrecision <= 18
4531 // For floating-point precision of 18:
4532 //
4533 // TwoToFractionalPartOfX =
4534 // 0.999999982f +
4535 // (0.693148872f +
4536 // (0.240227044f +
4537 // (0.554906021e-1f +
4538 // (0.961591928e-2f +
4539 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4540 // error 2.47208000*10^(-7), which is better than 18 bits
4541 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4542 getF32Constant(DAG, 0x3924b03e));
4543 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4544 getF32Constant(DAG, 0x3ab24b87));
4545 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4546 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4547 getF32Constant(DAG, 0x3c1d8c17));
4548 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4549 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4550 getF32Constant(DAG, 0x3d634a1d));
4551 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4552 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4553 getF32Constant(DAG, 0x3e75fe14));
4554 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4555 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4556 getF32Constant(DAG, 0x3f317234));
4557 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4558 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4559 getF32Constant(DAG, 0x3f800000));
4560 }
4562 SDValue t13 = DAG.getNode(ISD::BITCAST, dl,MVT::i32,TwoToFractionalPartOfX);
4563 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4564 DAG.getNode(ISD::ADD, dl, MVT::i32,
4565 t13, IntegerPartOfX));
4566 }
4568 // No special expansion.
4569 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4570 }
4573 /// ExpandPowI - Expand a llvm.powi intrinsic.
4574 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
4575 SelectionDAG &DAG) {
4576 // If RHS is a constant, we can expand this out to a multiplication tree,
4577 // otherwise we end up lowering to a call to __powidf2 (for example). When
4578 // optimizing for size, we only want to do this if the expansion would produce
4579 // a small number of multiplies, otherwise we do the full expansion.
4580 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4581 // Get the exponent as a positive value.
4582 unsigned Val = RHSC->getSExtValue();
4583 if ((int)Val < 0) Val = -Val;
4585 // powi(x, 0) -> 1.0
4586 if (Val == 0)
4587 return DAG.getConstantFP(1.0, LHS.getValueType());
4589 const Function *F = DAG.getMachineFunction().getFunction();
4590 if (!F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
4591 Attribute::OptimizeForSize) ||
4592 // If optimizing for size, don't insert too many multiplies. This
4593 // inserts up to 5 multiplies.
4594 CountPopulation_32(Val)+Log2_32(Val) < 7) {
4595 // We use the simple binary decomposition method to generate the multiply
4596 // sequence. There are more optimal ways to do this (for example,
4597 // powi(x,15) generates one more multiply than it should), but this has
4598 // the benefit of being both really simple and much better than a libcall.
4599 SDValue Res; // Logically starts equal to 1.0
4600 SDValue CurSquare = LHS;
4601 while (Val) {
4602 if (Val & 1) {
4603 if (Res.getNode())
4604 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4605 else
4606 Res = CurSquare; // 1.0*CurSquare.
4607 }
4609 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4610 CurSquare, CurSquare);
4611 Val >>= 1;
4612 }
4614 // If the original was negative, invert the result, producing 1/(x*x*x).
4615 if (RHSC->getSExtValue() < 0)
4616 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4617 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4618 return Res;
4619 }
4620 }
4622 // Otherwise, expand to a libcall.
4623 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4624 }
4626 // getTruncatedArgReg - Find underlying register used for an truncated
4627 // argument.
4628 static unsigned getTruncatedArgReg(const SDValue &N) {
4629 if (N.getOpcode() != ISD::TRUNCATE)
4630 return 0;
4632 const SDValue &Ext = N.getOperand(0);
4633 if (Ext.getOpcode() == ISD::AssertZext ||
4634 Ext.getOpcode() == ISD::AssertSext) {
4635 const SDValue &CFR = Ext.getOperand(0);
4636 if (CFR.getOpcode() == ISD::CopyFromReg)
4637 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4638 if (CFR.getOpcode() == ISD::TRUNCATE)
4639 return getTruncatedArgReg(CFR);
4640 }
4641 return 0;
4642 }
4644 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4645 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4646 /// At the end of instruction selection, they will be inserted to the entry BB.
4647 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V,
4648 MDNode *Variable,
4649 MDNode *Expr, int64_t Offset,
4650 bool IsIndirect,
4651 const SDValue &N) {
4652 const Argument *Arg = dyn_cast<Argument>(V);
4653 if (!Arg)
4654 return false;
4656 MachineFunction &MF = DAG.getMachineFunction();
4657 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4659 // Ignore inlined function arguments here.
4660 DIVariable DV(Variable);
4661 if (DV.isInlinedFnArgument(MF.getFunction()))
4662 return false;
4664 Optional<MachineOperand> Op;
4665 // Some arguments' frame index is recorded during argument lowering.
4666 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4667 Op = MachineOperand::CreateFI(FI);
4669 if (!Op && N.getNode()) {
4670 unsigned Reg;
4671 if (N.getOpcode() == ISD::CopyFromReg)
4672 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4673 else
4674 Reg = getTruncatedArgReg(N);
4675 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4676 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4677 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4678 if (PR)
4679 Reg = PR;
4680 }
4681 if (Reg)
4682 Op = MachineOperand::CreateReg(Reg, false);
4683 }
4685 if (!Op) {
4686 // Check if ValueMap has reg number.
4687 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4688 if (VMI != FuncInfo.ValueMap.end())
4689 Op = MachineOperand::CreateReg(VMI->second, false);
4690 }
4692 if (!Op && N.getNode())
4693 // Check if frame index is available.
4694 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4695 if (FrameIndexSDNode *FINode =
4696 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4697 Op = MachineOperand::CreateFI(FINode->getIndex());
4699 if (!Op)
4700 return false;
4702 if (Op->isReg())
4703 FuncInfo.ArgDbgValues.push_back(
4704 BuildMI(MF, getCurDebugLoc(), TII->get(TargetOpcode::DBG_VALUE),
4705 IsIndirect, Op->getReg(), Offset, Variable, Expr));
4706 else
4707 FuncInfo.ArgDbgValues.push_back(
4708 BuildMI(MF, getCurDebugLoc(), TII->get(TargetOpcode::DBG_VALUE))
4709 .addOperand(*Op)
4710 .addImm(Offset)
4711 .addMetadata(Variable)
4712 .addMetadata(Expr));
4714 return true;
4715 }
4717 // VisualStudio defines setjmp as _setjmp
4718 #if defined(_MSC_VER) && defined(setjmp) && \
4719 !defined(setjmp_undefined_for_msvc)
4720 # pragma push_macro("setjmp")
4721 # undef setjmp
4722 # define setjmp_undefined_for_msvc
4723 #endif
4725 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4726 /// we want to emit this as a call to a named external function, return the name
4727 /// otherwise lower it and return null.
4728 const char *
4729 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4730 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4731 SDLoc sdl = getCurSDLoc();
4732 DebugLoc dl = getCurDebugLoc();
4733 SDValue Res;
4735 switch (Intrinsic) {
4736 default:
4737 // By default, turn this into a target intrinsic node.
4738 visitTargetIntrinsic(I, Intrinsic);
4739 return nullptr;
4740 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4741 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4742 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4743 case Intrinsic::returnaddress:
4744 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl, TLI.getPointerTy(),
4745 getValue(I.getArgOperand(0))));
4746 return nullptr;
4747 case Intrinsic::frameaddress:
4748 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl, TLI.getPointerTy(),
4749 getValue(I.getArgOperand(0))));
4750 return nullptr;
4751 case Intrinsic::read_register: {
4752 Value *Reg = I.getArgOperand(0);
4753 SDValue RegName =
4754 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4755 EVT VT = TLI.getValueType(I.getType());
4756 setValue(&I, DAG.getNode(ISD::READ_REGISTER, sdl, VT, RegName));
4757 return nullptr;
4758 }
4759 case Intrinsic::write_register: {
4760 Value *Reg = I.getArgOperand(0);
4761 Value *RegValue = I.getArgOperand(1);
4762 SDValue Chain = getValue(RegValue).getOperand(0);
4763 SDValue RegName =
4764 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4765 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4766 RegName, getValue(RegValue)));
4767 return nullptr;
4768 }
4769 case Intrinsic::setjmp:
4770 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4771 case Intrinsic::longjmp:
4772 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4773 case Intrinsic::memcpy: {
4774 // Assert for address < 256 since we support only user defined address
4775 // spaces.
4776 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4777 < 256 &&
4778 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4779 < 256 &&
4780 "Unknown address space");
4781 SDValue Op1 = getValue(I.getArgOperand(0));
4782 SDValue Op2 = getValue(I.getArgOperand(1));
4783 SDValue Op3 = getValue(I.getArgOperand(2));
4784 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4785 if (!Align)
4786 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4787 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4788 DAG.setRoot(DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, false,
4789 MachinePointerInfo(I.getArgOperand(0)),
4790 MachinePointerInfo(I.getArgOperand(1))));
4791 return nullptr;
4792 }
4793 case Intrinsic::memset: {
4794 // Assert for address < 256 since we support only user defined address
4795 // spaces.
4796 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4797 < 256 &&
4798 "Unknown address space");
4799 SDValue Op1 = getValue(I.getArgOperand(0));
4800 SDValue Op2 = getValue(I.getArgOperand(1));
4801 SDValue Op3 = getValue(I.getArgOperand(2));
4802 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4803 if (!Align)
4804 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4805 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4806 DAG.setRoot(DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4807 MachinePointerInfo(I.getArgOperand(0))));
4808 return nullptr;
4809 }
4810 case Intrinsic::memmove: {
4811 // Assert for address < 256 since we support only user defined address
4812 // spaces.
4813 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4814 < 256 &&
4815 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4816 < 256 &&
4817 "Unknown address space");
4818 SDValue Op1 = getValue(I.getArgOperand(0));
4819 SDValue Op2 = getValue(I.getArgOperand(1));
4820 SDValue Op3 = getValue(I.getArgOperand(2));
4821 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4822 if (!Align)
4823 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4824 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4825 DAG.setRoot(DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4826 MachinePointerInfo(I.getArgOperand(0)),
4827 MachinePointerInfo(I.getArgOperand(1))));
4828 return nullptr;
4829 }
4830 case Intrinsic::dbg_declare: {
4831 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4832 MDNode *Variable = DI.getVariable();
4833 MDNode *Expression = DI.getExpression();
4834 const Value *Address = DI.getAddress();
4835 DIVariable DIVar(Variable);
4836 assert((!DIVar || DIVar.isVariable()) &&
4837 "Variable in DbgDeclareInst should be either null or a DIVariable.");
4838 if (!Address || !DIVar) {
4839 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4840 return nullptr;
4841 }
4843 // Check if address has undef value.
4844 if (isa<UndefValue>(Address) ||
4845 (Address->use_empty() && !isa<Argument>(Address))) {
4846 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4847 return nullptr;
4848 }
4850 SDValue &N = NodeMap[Address];
4851 if (!N.getNode() && isa<Argument>(Address))
4852 // Check unused arguments map.
4853 N = UnusedArgNodeMap[Address];
4854 SDDbgValue *SDV;
4855 if (N.getNode()) {
4856 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4857 Address = BCI->getOperand(0);
4858 // Parameters are handled specially.
4859 bool isParameter =
4860 (DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable ||
4861 isa<Argument>(Address));
4863 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4865 if (isParameter && !AI) {
4866 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4867 if (FINode)
4868 // Byval parameter. We have a frame index at this point.
4869 SDV = DAG.getFrameIndexDbgValue(
4870 Variable, Expression, FINode->getIndex(), 0, dl, SDNodeOrder);
4871 else {
4872 // Address is an argument, so try to emit its dbg value using
4873 // virtual register info from the FuncInfo.ValueMap.
4874 EmitFuncArgumentDbgValue(Address, Variable, Expression, 0, false, N);
4875 return nullptr;
4876 }
4877 } else if (AI)
4878 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4879 true, 0, dl, SDNodeOrder);
4880 else {
4881 // Can't do anything with other non-AI cases yet.
4882 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4883 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4884 DEBUG(Address->dump());
4885 return nullptr;
4886 }
4887 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4888 } else {
4889 // If Address is an argument then try to emit its dbg value using
4890 // virtual register info from the FuncInfo.ValueMap.
4891 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, 0, false,
4892 N)) {
4893 // If variable is pinned by a alloca in dominating bb then
4894 // use StaticAllocaMap.
4895 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4896 if (AI->getParent() != DI.getParent()) {
4897 DenseMap<const AllocaInst*, int>::iterator SI =
4898 FuncInfo.StaticAllocaMap.find(AI);
4899 if (SI != FuncInfo.StaticAllocaMap.end()) {
4900 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4901 0, dl, SDNodeOrder);
4902 DAG.AddDbgValue(SDV, nullptr, false);
4903 return nullptr;
4904 }
4905 }
4906 }
4907 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4908 }
4909 }
4910 return nullptr;
4911 }
4912 case Intrinsic::dbg_value: {
4913 const DbgValueInst &DI = cast<DbgValueInst>(I);
4914 DIVariable DIVar(DI.getVariable());
4915 assert((!DIVar || DIVar.isVariable()) &&
4916 "Variable in DbgValueInst should be either null or a DIVariable.");
4917 if (!DIVar)
4918 return nullptr;
4920 MDNode *Variable = DI.getVariable();
4921 MDNode *Expression = DI.getExpression();
4922 uint64_t Offset = DI.getOffset();
4923 const Value *V = DI.getValue();
4924 if (!V)
4925 return nullptr;
4927 SDDbgValue *SDV;
4928 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4929 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
4930 SDNodeOrder);
4931 DAG.AddDbgValue(SDV, nullptr, false);
4932 } else {
4933 // Do not use getValue() in here; we don't want to generate code at
4934 // this point if it hasn't been done yet.
4935 SDValue N = NodeMap[V];
4936 if (!N.getNode() && isa<Argument>(V))
4937 // Check unused arguments map.
4938 N = UnusedArgNodeMap[V];
4939 if (N.getNode()) {
4940 // A dbg.value for an alloca is always indirect.
4941 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4942 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, Offset,
4943 IsIndirect, N)) {
4944 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4945 IsIndirect, Offset, dl, SDNodeOrder);
4946 DAG.AddDbgValue(SDV, N.getNode(), false);
4947 }
4948 } else if (!V->use_empty() ) {
4949 // Do not call getValue(V) yet, as we don't want to generate code.
4950 // Remember it for later.
4951 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4952 DanglingDebugInfoMap[V] = DDI;
4953 } else {
4954 // We may expand this to cover more cases. One case where we have no
4955 // data available is an unreferenced parameter.
4956 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4957 }
4958 }
4960 // Build a debug info table entry.
4961 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4962 V = BCI->getOperand(0);
4963 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4964 // Don't handle byval struct arguments or VLAs, for example.
4965 if (!AI) {
4966 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4967 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4968 return nullptr;
4969 }
4970 DenseMap<const AllocaInst*, int>::iterator SI =
4971 FuncInfo.StaticAllocaMap.find(AI);
4972 if (SI == FuncInfo.StaticAllocaMap.end())
4973 return nullptr; // VLAs.
4974 return nullptr;
4975 }
4977 case Intrinsic::eh_typeid_for: {
4978 // Find the type id for the given typeinfo.
4979 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
4980 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4981 Res = DAG.getConstant(TypeID, MVT::i32);
4982 setValue(&I, Res);
4983 return nullptr;
4984 }
4986 case Intrinsic::eh_return_i32:
4987 case Intrinsic::eh_return_i64:
4988 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4989 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4990 MVT::Other,
4991 getControlRoot(),
4992 getValue(I.getArgOperand(0)),
4993 getValue(I.getArgOperand(1))));
4994 return nullptr;
4995 case Intrinsic::eh_unwind_init:
4996 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4997 return nullptr;
4998 case Intrinsic::eh_dwarf_cfa: {
4999 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
5000 TLI.getPointerTy());
5001 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
5002 CfaArg.getValueType(),
5003 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
5004 CfaArg.getValueType()),
5005 CfaArg);
5006 SDValue FA = DAG.getNode(ISD::FRAMEADDR, sdl, TLI.getPointerTy(),
5007 DAG.getConstant(0, TLI.getPointerTy()));
5008 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
5009 FA, Offset));
5010 return nullptr;
5011 }
5012 case Intrinsic::eh_sjlj_callsite: {
5013 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5014 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
5015 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
5016 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
5018 MMI.setCurrentCallSite(CI->getZExtValue());
5019 return nullptr;
5020 }
5021 case Intrinsic::eh_sjlj_functioncontext: {
5022 // Get and store the index of the function context.
5023 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5024 AllocaInst *FnCtx =
5025 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
5026 int FI = FuncInfo.StaticAllocaMap[FnCtx];
5027 MFI->setFunctionContextIndex(FI);
5028 return nullptr;
5029 }
5030 case Intrinsic::eh_sjlj_setjmp: {
5031 SDValue Ops[2];
5032 Ops[0] = getRoot();
5033 Ops[1] = getValue(I.getArgOperand(0));
5034 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
5035 DAG.getVTList(MVT::i32, MVT::Other), Ops);
5036 setValue(&I, Op.getValue(0));
5037 DAG.setRoot(Op.getValue(1));
5038 return nullptr;
5039 }
5040 case Intrinsic::eh_sjlj_longjmp: {
5041 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
5042 getRoot(), getValue(I.getArgOperand(0))));
5043 return nullptr;
5044 }
5046 case Intrinsic::masked_load:
5047 visitMaskedLoad(I);
5048 return nullptr;
5049 case Intrinsic::masked_store:
5050 visitMaskedStore(I);
5051 return nullptr;
5052 case Intrinsic::x86_mmx_pslli_w:
5053 case Intrinsic::x86_mmx_pslli_d:
5054 case Intrinsic::x86_mmx_pslli_q:
5055 case Intrinsic::x86_mmx_psrli_w:
5056 case Intrinsic::x86_mmx_psrli_d:
5057 case Intrinsic::x86_mmx_psrli_q:
5058 case Intrinsic::x86_mmx_psrai_w:
5059 case Intrinsic::x86_mmx_psrai_d: {
5060 SDValue ShAmt = getValue(I.getArgOperand(1));
5061 if (isa<ConstantSDNode>(ShAmt)) {
5062 visitTargetIntrinsic(I, Intrinsic);
5063 return nullptr;
5064 }
5065 unsigned NewIntrinsic = 0;
5066 EVT ShAmtVT = MVT::v2i32;
5067 switch (Intrinsic) {
5068 case Intrinsic::x86_mmx_pslli_w:
5069 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
5070 break;
5071 case Intrinsic::x86_mmx_pslli_d:
5072 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
5073 break;
5074 case Intrinsic::x86_mmx_pslli_q:
5075 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
5076 break;
5077 case Intrinsic::x86_mmx_psrli_w:
5078 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
5079 break;
5080 case Intrinsic::x86_mmx_psrli_d:
5081 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
5082 break;
5083 case Intrinsic::x86_mmx_psrli_q:
5084 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
5085 break;
5086 case Intrinsic::x86_mmx_psrai_w:
5087 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
5088 break;
5089 case Intrinsic::x86_mmx_psrai_d:
5090 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
5091 break;
5092 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5093 }
5095 // The vector shift intrinsics with scalars uses 32b shift amounts but
5096 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
5097 // to be zero.
5098 // We must do this early because v2i32 is not a legal type.
5099 SDValue ShOps[2];
5100 ShOps[0] = ShAmt;
5101 ShOps[1] = DAG.getConstant(0, MVT::i32);
5102 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
5103 EVT DestVT = TLI.getValueType(I.getType());
5104 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
5105 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
5106 DAG.getConstant(NewIntrinsic, MVT::i32),
5107 getValue(I.getArgOperand(0)), ShAmt);
5108 setValue(&I, Res);
5109 return nullptr;
5110 }
5111 case Intrinsic::x86_avx_vinsertf128_pd_256:
5112 case Intrinsic::x86_avx_vinsertf128_ps_256:
5113 case Intrinsic::x86_avx_vinsertf128_si_256:
5114 case Intrinsic::x86_avx2_vinserti128: {
5115 EVT DestVT = TLI.getValueType(I.getType());
5116 EVT ElVT = TLI.getValueType(I.getArgOperand(1)->getType());
5117 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(2))->getZExtValue() & 1) *
5118 ElVT.getVectorNumElements();
5119 Res =
5120 DAG.getNode(ISD::INSERT_SUBVECTOR, sdl, DestVT,
5121 getValue(I.getArgOperand(0)), getValue(I.getArgOperand(1)),
5122 DAG.getConstant(Idx, TLI.getVectorIdxTy()));
5123 setValue(&I, Res);
5124 return nullptr;
5125 }
5126 case Intrinsic::x86_avx_vextractf128_pd_256:
5127 case Intrinsic::x86_avx_vextractf128_ps_256:
5128 case Intrinsic::x86_avx_vextractf128_si_256:
5129 case Intrinsic::x86_avx2_vextracti128: {
5130 EVT DestVT = TLI.getValueType(I.getType());
5131 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(1))->getZExtValue() & 1) *
5132 DestVT.getVectorNumElements();
5133 Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, sdl, DestVT,
5134 getValue(I.getArgOperand(0)),
5135 DAG.getConstant(Idx, TLI.getVectorIdxTy()));
5136 setValue(&I, Res);
5137 return nullptr;
5138 }
5139 case Intrinsic::convertff:
5140 case Intrinsic::convertfsi:
5141 case Intrinsic::convertfui:
5142 case Intrinsic::convertsif:
5143 case Intrinsic::convertuif:
5144 case Intrinsic::convertss:
5145 case Intrinsic::convertsu:
5146 case Intrinsic::convertus:
5147 case Intrinsic::convertuu: {
5148 ISD::CvtCode Code = ISD::CVT_INVALID;
5149 switch (Intrinsic) {
5150 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5151 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
5152 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
5153 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
5154 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
5155 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
5156 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
5157 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
5158 case Intrinsic::convertus: Code = ISD::CVT_US; break;
5159 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
5160 }
5161 EVT DestVT = TLI.getValueType(I.getType());
5162 const Value *Op1 = I.getArgOperand(0);
5163 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
5164 DAG.getValueType(DestVT),
5165 DAG.getValueType(getValue(Op1).getValueType()),
5166 getValue(I.getArgOperand(1)),
5167 getValue(I.getArgOperand(2)),
5168 Code);
5169 setValue(&I, Res);
5170 return nullptr;
5171 }
5172 case Intrinsic::powi:
5173 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
5174 getValue(I.getArgOperand(1)), DAG));
5175 return nullptr;
5176 case Intrinsic::log:
5177 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5178 return nullptr;
5179 case Intrinsic::log2:
5180 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5181 return nullptr;
5182 case Intrinsic::log10:
5183 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5184 return nullptr;
5185 case Intrinsic::exp:
5186 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5187 return nullptr;
5188 case Intrinsic::exp2:
5189 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5190 return nullptr;
5191 case Intrinsic::pow:
5192 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
5193 getValue(I.getArgOperand(1)), DAG, TLI));
5194 return nullptr;
5195 case Intrinsic::sqrt:
5196 case Intrinsic::fabs:
5197 case Intrinsic::sin:
5198 case Intrinsic::cos:
5199 case Intrinsic::floor:
5200 case Intrinsic::ceil:
5201 case Intrinsic::trunc:
5202 case Intrinsic::rint:
5203 case Intrinsic::nearbyint:
5204 case Intrinsic::round: {
5205 unsigned Opcode;
5206 switch (Intrinsic) {
5207 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5208 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
5209 case Intrinsic::fabs: Opcode = ISD::FABS; break;
5210 case Intrinsic::sin: Opcode = ISD::FSIN; break;
5211 case Intrinsic::cos: Opcode = ISD::FCOS; break;
5212 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
5213 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
5214 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
5215 case Intrinsic::rint: Opcode = ISD::FRINT; break;
5216 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
5217 case Intrinsic::round: Opcode = ISD::FROUND; break;
5218 }
5220 setValue(&I, DAG.getNode(Opcode, sdl,
5221 getValue(I.getArgOperand(0)).getValueType(),
5222 getValue(I.getArgOperand(0))));
5223 return nullptr;
5224 }
5225 case Intrinsic::minnum:
5226 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl,
5227 getValue(I.getArgOperand(0)).getValueType(),
5228 getValue(I.getArgOperand(0)),
5229 getValue(I.getArgOperand(1))));
5230 return nullptr;
5231 case Intrinsic::maxnum:
5232 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl,
5233 getValue(I.getArgOperand(0)).getValueType(),
5234 getValue(I.getArgOperand(0)),
5235 getValue(I.getArgOperand(1))));
5236 return nullptr;
5237 case Intrinsic::copysign:
5238 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
5239 getValue(I.getArgOperand(0)).getValueType(),
5240 getValue(I.getArgOperand(0)),
5241 getValue(I.getArgOperand(1))));
5242 return nullptr;
5243 case Intrinsic::fma:
5244 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5245 getValue(I.getArgOperand(0)).getValueType(),
5246 getValue(I.getArgOperand(0)),
5247 getValue(I.getArgOperand(1)),
5248 getValue(I.getArgOperand(2))));
5249 return nullptr;
5250 case Intrinsic::fmuladd: {
5251 EVT VT = TLI.getValueType(I.getType());
5252 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
5253 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
5254 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5255 getValue(I.getArgOperand(0)).getValueType(),
5256 getValue(I.getArgOperand(0)),
5257 getValue(I.getArgOperand(1)),
5258 getValue(I.getArgOperand(2))));
5259 } else {
5260 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
5261 getValue(I.getArgOperand(0)).getValueType(),
5262 getValue(I.getArgOperand(0)),
5263 getValue(I.getArgOperand(1)));
5264 SDValue Add = DAG.getNode(ISD::FADD, sdl,
5265 getValue(I.getArgOperand(0)).getValueType(),
5266 Mul,
5267 getValue(I.getArgOperand(2)));
5268 setValue(&I, Add);
5269 }
5270 return nullptr;
5271 }
5272 case Intrinsic::convert_to_fp16:
5273 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
5274 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
5275 getValue(I.getArgOperand(0)),
5276 DAG.getTargetConstant(0, MVT::i32))));
5277 return nullptr;
5278 case Intrinsic::convert_from_fp16:
5279 setValue(&I,
5280 DAG.getNode(ISD::FP_EXTEND, sdl, TLI.getValueType(I.getType()),
5281 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
5282 getValue(I.getArgOperand(0)))));
5283 return nullptr;
5284 case Intrinsic::pcmarker: {
5285 SDValue Tmp = getValue(I.getArgOperand(0));
5286 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
5287 return nullptr;
5288 }
5289 case Intrinsic::readcyclecounter: {
5290 SDValue Op = getRoot();
5291 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
5292 DAG.getVTList(MVT::i64, MVT::Other), Op);
5293 setValue(&I, Res);
5294 DAG.setRoot(Res.getValue(1));
5295 return nullptr;
5296 }
5297 case Intrinsic::bswap:
5298 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
5299 getValue(I.getArgOperand(0)).getValueType(),
5300 getValue(I.getArgOperand(0))));
5301 return nullptr;
5302 case Intrinsic::cttz: {
5303 SDValue Arg = getValue(I.getArgOperand(0));
5304 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5305 EVT Ty = Arg.getValueType();
5306 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
5307 sdl, Ty, Arg));
5308 return nullptr;
5309 }
5310 case Intrinsic::ctlz: {
5311 SDValue Arg = getValue(I.getArgOperand(0));
5312 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5313 EVT Ty = Arg.getValueType();
5314 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
5315 sdl, Ty, Arg));
5316 return nullptr;
5317 }
5318 case Intrinsic::ctpop: {
5319 SDValue Arg = getValue(I.getArgOperand(0));
5320 EVT Ty = Arg.getValueType();
5321 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
5322 return nullptr;
5323 }
5324 case Intrinsic::stacksave: {
5325 SDValue Op = getRoot();
5326 Res = DAG.getNode(ISD::STACKSAVE, sdl,
5327 DAG.getVTList(TLI.getPointerTy(), MVT::Other), Op);
5328 setValue(&I, Res);
5329 DAG.setRoot(Res.getValue(1));
5330 return nullptr;
5331 }
5332 case Intrinsic::stackrestore: {
5333 Res = getValue(I.getArgOperand(0));
5334 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
5335 return nullptr;
5336 }
5337 case Intrinsic::stackprotector: {
5338 // Emit code into the DAG to store the stack guard onto the stack.
5339 MachineFunction &MF = DAG.getMachineFunction();
5340 MachineFrameInfo *MFI = MF.getFrameInfo();
5341 EVT PtrTy = TLI.getPointerTy();
5342 SDValue Src, Chain = getRoot();
5343 const Value *Ptr = cast<LoadInst>(I.getArgOperand(0))->getPointerOperand();
5344 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Ptr);
5346 // See if Ptr is a bitcast. If it is, look through it and see if we can get
5347 // global variable __stack_chk_guard.
5348 if (!GV)
5349 if (const Operator *BC = dyn_cast<Operator>(Ptr))
5350 if (BC->getOpcode() == Instruction::BitCast)
5351 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
5353 if (GV && TLI.useLoadStackGuardNode()) {
5354 // Emit a LOAD_STACK_GUARD node.
5355 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
5356 sdl, PtrTy, Chain);
5357 MachinePointerInfo MPInfo(GV);
5358 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
5359 unsigned Flags = MachineMemOperand::MOLoad |
5360 MachineMemOperand::MOInvariant;
5361 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
5362 PtrTy.getSizeInBits() / 8,
5363 DAG.getEVTAlignment(PtrTy));
5364 Node->setMemRefs(MemRefs, MemRefs + 1);
5366 // Copy the guard value to a virtual register so that it can be
5367 // retrieved in the epilogue.
5368 Src = SDValue(Node, 0);
5369 const TargetRegisterClass *RC =
5370 TLI.getRegClassFor(Src.getSimpleValueType());
5371 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
5373 SPDescriptor.setGuardReg(Reg);
5374 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
5375 } else {
5376 Src = getValue(I.getArgOperand(0)); // The guard's value.
5377 }
5379 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
5381 int FI = FuncInfo.StaticAllocaMap[Slot];
5382 MFI->setStackProtectorIndex(FI);
5384 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
5386 // Store the stack protector onto the stack.
5387 Res = DAG.getStore(Chain, sdl, Src, FIN,
5388 MachinePointerInfo::getFixedStack(FI),
5389 true, false, 0);
5390 setValue(&I, Res);
5391 DAG.setRoot(Res);
5392 return nullptr;
5393 }
5394 case Intrinsic::objectsize: {
5395 // If we don't know by now, we're never going to know.
5396 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
5398 assert(CI && "Non-constant type in __builtin_object_size?");
5400 SDValue Arg = getValue(I.getCalledValue());
5401 EVT Ty = Arg.getValueType();
5403 if (CI->isZero())
5404 Res = DAG.getConstant(-1ULL, Ty);
5405 else
5406 Res = DAG.getConstant(0, Ty);
5408 setValue(&I, Res);
5409 return nullptr;
5410 }
5411 case Intrinsic::annotation:
5412 case Intrinsic::ptr_annotation:
5413 // Drop the intrinsic, but forward the value
5414 setValue(&I, getValue(I.getOperand(0)));
5415 return nullptr;
5416 case Intrinsic::assume:
5417 case Intrinsic::var_annotation:
5418 // Discard annotate attributes and assumptions
5419 return nullptr;
5421 case Intrinsic::init_trampoline: {
5422 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5424 SDValue Ops[6];
5425 Ops[0] = getRoot();
5426 Ops[1] = getValue(I.getArgOperand(0));
5427 Ops[2] = getValue(I.getArgOperand(1));
5428 Ops[3] = getValue(I.getArgOperand(2));
5429 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5430 Ops[5] = DAG.getSrcValue(F);
5432 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
5434 DAG.setRoot(Res);
5435 return nullptr;
5436 }
5437 case Intrinsic::adjust_trampoline: {
5438 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
5439 TLI.getPointerTy(),
5440 getValue(I.getArgOperand(0))));
5441 return nullptr;
5442 }
5443 case Intrinsic::gcroot:
5444 if (GFI) {
5445 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
5446 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5448 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5449 GFI->addStackRoot(FI->getIndex(), TypeMap);
5450 }
5451 return nullptr;
5452 case Intrinsic::gcread:
5453 case Intrinsic::gcwrite:
5454 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5455 case Intrinsic::flt_rounds:
5456 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
5457 return nullptr;
5459 case Intrinsic::expect: {
5460 // Just replace __builtin_expect(exp, c) with EXP.
5461 setValue(&I, getValue(I.getArgOperand(0)));
5462 return nullptr;
5463 }
5465 case Intrinsic::debugtrap:
5466 case Intrinsic::trap: {
5467 StringRef TrapFuncName = TM.Options.getTrapFunctionName();
5468 if (TrapFuncName.empty()) {
5469 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
5470 ISD::TRAP : ISD::DEBUGTRAP;
5471 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
5472 return nullptr;
5473 }
5474 TargetLowering::ArgListTy Args;
5476 TargetLowering::CallLoweringInfo CLI(DAG);
5477 CLI.setDebugLoc(sdl).setChain(getRoot())
5478 .setCallee(CallingConv::C, I.getType(),
5479 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()),
5480 std::move(Args), 0);
5482 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5483 DAG.setRoot(Result.second);
5484 return nullptr;
5485 }
5487 case Intrinsic::uadd_with_overflow:
5488 case Intrinsic::sadd_with_overflow:
5489 case Intrinsic::usub_with_overflow:
5490 case Intrinsic::ssub_with_overflow:
5491 case Intrinsic::umul_with_overflow:
5492 case Intrinsic::smul_with_overflow: {
5493 ISD::NodeType Op;
5494 switch (Intrinsic) {
5495 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5496 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5497 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5498 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5499 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5500 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5501 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5502 }
5503 SDValue Op1 = getValue(I.getArgOperand(0));
5504 SDValue Op2 = getValue(I.getArgOperand(1));
5506 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5507 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
5508 return nullptr;
5509 }
5510 case Intrinsic::prefetch: {
5511 SDValue Ops[5];
5512 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5513 Ops[0] = getRoot();
5514 Ops[1] = getValue(I.getArgOperand(0));
5515 Ops[2] = getValue(I.getArgOperand(1));
5516 Ops[3] = getValue(I.getArgOperand(2));
5517 Ops[4] = getValue(I.getArgOperand(3));
5518 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
5519 DAG.getVTList(MVT::Other), Ops,
5520 EVT::getIntegerVT(*Context, 8),
5521 MachinePointerInfo(I.getArgOperand(0)),
5522 0, /* align */
5523 false, /* volatile */
5524 rw==0, /* read */
5525 rw==1)); /* write */
5526 return nullptr;
5527 }
5528 case Intrinsic::lifetime_start:
5529 case Intrinsic::lifetime_end: {
5530 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
5531 // Stack coloring is not enabled in O0, discard region information.
5532 if (TM.getOptLevel() == CodeGenOpt::None)
5533 return nullptr;
5535 SmallVector<Value *, 4> Allocas;
5536 GetUnderlyingObjects(I.getArgOperand(1), Allocas, DL);
5538 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
5539 E = Allocas.end(); Object != E; ++Object) {
5540 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5542 // Could not find an Alloca.
5543 if (!LifetimeObject)
5544 continue;
5546 // First check that the Alloca is static, otherwise it won't have a
5547 // valid frame index.
5548 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
5549 if (SI == FuncInfo.StaticAllocaMap.end())
5550 return nullptr;
5552 int FI = SI->second;
5554 SDValue Ops[2];
5555 Ops[0] = getRoot();
5556 Ops[1] = DAG.getFrameIndex(FI, TLI.getPointerTy(), true);
5557 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5559 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
5560 DAG.setRoot(Res);
5561 }
5562 return nullptr;
5563 }
5564 case Intrinsic::invariant_start:
5565 // Discard region information.
5566 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
5567 return nullptr;
5568 case Intrinsic::invariant_end:
5569 // Discard region information.
5570 return nullptr;
5571 case Intrinsic::stackprotectorcheck: {
5572 // Do not actually emit anything for this basic block. Instead we initialize
5573 // the stack protector descriptor and export the guard variable so we can
5574 // access it in FinishBasicBlock.
5575 const BasicBlock *BB = I.getParent();
5576 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
5577 ExportFromCurrentBlock(SPDescriptor.getGuard());
5579 // Flush our exports since we are going to process a terminator.
5580 (void)getControlRoot();
5581 return nullptr;
5582 }
5583 case Intrinsic::clear_cache:
5584 return TLI.getClearCacheBuiltinName();
5585 case Intrinsic::donothing:
5586 // ignore
5587 return nullptr;
5588 case Intrinsic::experimental_stackmap: {
5589 visitStackmap(I);
5590 return nullptr;
5591 }
5592 case Intrinsic::experimental_patchpoint_void:
5593 case Intrinsic::experimental_patchpoint_i64: {
5594 visitPatchpoint(&I);
5595 return nullptr;
5596 }
5597 case Intrinsic::experimental_gc_statepoint: {
5598 visitStatepoint(I);
5599 return nullptr;
5600 }
5601 case Intrinsic::experimental_gc_result_int:
5602 case Intrinsic::experimental_gc_result_float:
5603 case Intrinsic::experimental_gc_result_ptr: {
5604 visitGCResult(I);
5605 return nullptr;
5606 }
5607 case Intrinsic::experimental_gc_relocate: {
5608 visitGCRelocate(I);
5609 return nullptr;
5610 }
5611 case Intrinsic::instrprof_increment:
5612 llvm_unreachable("instrprof failed to lower an increment");
5614 case Intrinsic::frameallocate: {
5615 MachineFunction &MF = DAG.getMachineFunction();
5616 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
5618 // Do the allocation and map it as a normal value.
5619 // FIXME: Maybe we should add this to the alloca map so that we don't have
5620 // to register allocate it?
5621 uint64_t Size = cast<ConstantInt>(I.getArgOperand(0))->getZExtValue();
5622 int Alloc = MF.getFrameInfo()->CreateFrameAllocation(Size);
5623 MVT PtrVT = TLI.getPointerTy(0);
5624 SDValue FIVal = DAG.getFrameIndex(Alloc, PtrVT);
5625 setValue(&I, FIVal);
5627 // Directly emit a FRAME_ALLOC machine instr. Label assignment emission is
5628 // the same on all targets.
5629 MCSymbol *FrameAllocSym =
5630 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(MF.getName());
5631 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
5632 TII->get(TargetOpcode::FRAME_ALLOC))
5633 .addSym(FrameAllocSym)
5634 .addFrameIndex(Alloc);
5636 return nullptr;
5637 }
5639 case Intrinsic::framerecover: {
5640 // i8* @llvm.framerecover(i8* %fn, i8* %fp)
5641 MachineFunction &MF = DAG.getMachineFunction();
5642 MVT PtrVT = TLI.getPointerTy(0);
5644 // Get the symbol that defines the frame offset.
5645 Function *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts());
5646 MCSymbol *FrameAllocSym =
5647 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(Fn->getName());
5649 // Create a TargetExternalSymbol for the label to avoid any target lowering
5650 // that would make this PC relative.
5651 StringRef Name = FrameAllocSym->getName();
5652 assert(Name.size() == strlen(Name.data()) && "not null terminated");
5653 SDValue OffsetSym = DAG.getTargetExternalSymbol(Name.data(), PtrVT);
5654 SDValue OffsetVal =
5655 DAG.getNode(ISD::FRAME_ALLOC_RECOVER, sdl, PtrVT, OffsetSym);
5657 // Add the offset to the FP.
5658 Value *FP = I.getArgOperand(1);
5659 SDValue FPVal = getValue(FP);
5660 SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
5661 setValue(&I, Add);
5663 return nullptr;
5664 }
5665 }
5666 }
5668 std::pair<SDValue, SDValue>
5669 SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
5670 MachineBasicBlock *LandingPad) {
5671 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5672 MCSymbol *BeginLabel = nullptr;
5674 if (LandingPad) {
5675 // Insert a label before the invoke call to mark the try range. This can be
5676 // used to detect deletion of the invoke via the MachineModuleInfo.
5677 BeginLabel = MMI.getContext().CreateTempSymbol();
5679 // For SjLj, keep track of which landing pads go with which invokes
5680 // so as to maintain the ordering of pads in the LSDA.
5681 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5682 if (CallSiteIndex) {
5683 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5684 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5686 // Now that the call site is handled, stop tracking it.
5687 MMI.setCurrentCallSite(0);
5688 }
5690 // Both PendingLoads and PendingExports must be flushed here;
5691 // this call might not return.
5692 (void)getRoot();
5693 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5695 CLI.setChain(getRoot());
5696 }
5698 const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
5699 std::pair<SDValue, SDValue> Result = TLI->LowerCallTo(CLI);
5701 assert((CLI.IsTailCall || Result.second.getNode()) &&
5702 "Non-null chain expected with non-tail call!");
5703 assert((Result.second.getNode() || !Result.first.getNode()) &&
5704 "Null value expected with tail call!");
5706 if (!Result.second.getNode()) {
5707 // As a special case, a null chain means that a tail call has been emitted
5708 // and the DAG root is already updated.
5709 HasTailCall = true;
5711 // Since there's no actual continuation from this block, nothing can be
5712 // relying on us setting vregs for them.
5713 PendingExports.clear();
5714 } else {
5715 DAG.setRoot(Result.second);
5716 }
5718 if (LandingPad) {
5719 // Insert a label at the end of the invoke call to mark the try range. This
5720 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5721 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
5722 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5724 // Inform MachineModuleInfo of range.
5725 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5726 }
5728 return Result;
5729 }
5731 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5732 bool isTailCall,
5733 MachineBasicBlock *LandingPad) {
5734 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5735 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5736 Type *RetTy = FTy->getReturnType();
5738 TargetLowering::ArgListTy Args;
5739 TargetLowering::ArgListEntry Entry;
5740 Args.reserve(CS.arg_size());
5742 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5743 i != e; ++i) {
5744 const Value *V = *i;
5746 // Skip empty types
5747 if (V->getType()->isEmptyTy())
5748 continue;
5750 SDValue ArgNode = getValue(V);
5751 Entry.Node = ArgNode; Entry.Ty = V->getType();
5753 // Skip the first return-type Attribute to get to params.
5754 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5755 Args.push_back(Entry);
5756 }
5758 // Check if target-independent constraints permit a tail call here.
5759 // Target-dependent constraints are checked within TLI->LowerCallTo.
5760 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5761 isTailCall = false;
5763 TargetLowering::CallLoweringInfo CLI(DAG);
5764 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5765 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
5766 .setTailCall(isTailCall);
5767 std::pair<SDValue,SDValue> Result = lowerInvokable(CLI, LandingPad);
5769 if (Result.first.getNode())
5770 setValue(CS.getInstruction(), Result.first);
5771 }
5773 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5774 /// value is equal or not-equal to zero.
5775 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5776 for (const User *U : V->users()) {
5777 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5778 if (IC->isEquality())
5779 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5780 if (C->isNullValue())
5781 continue;
5782 // Unknown instruction.
5783 return false;
5784 }
5785 return true;
5786 }
5788 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5789 Type *LoadTy,
5790 SelectionDAGBuilder &Builder) {
5792 // Check to see if this load can be trivially constant folded, e.g. if the
5793 // input is from a string literal.
5794 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5795 // Cast pointer to the type we really want to load.
5796 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5797 PointerType::getUnqual(LoadTy));
5799 if (const Constant *LoadCst =
5800 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
5801 Builder.DL))
5802 return Builder.getValue(LoadCst);
5803 }
5805 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5806 // still constant memory, the input chain can be the entry node.
5807 SDValue Root;
5808 bool ConstantMemory = false;
5810 // Do not serialize (non-volatile) loads of constant memory with anything.
5811 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5812 Root = Builder.DAG.getEntryNode();
5813 ConstantMemory = true;
5814 } else {
5815 // Do not serialize non-volatile loads against each other.
5816 Root = Builder.DAG.getRoot();
5817 }
5819 SDValue Ptr = Builder.getValue(PtrVal);
5820 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5821 Ptr, MachinePointerInfo(PtrVal),
5822 false /*volatile*/,
5823 false /*nontemporal*/,
5824 false /*isinvariant*/, 1 /* align=1 */);
5826 if (!ConstantMemory)
5827 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5828 return LoadVal;
5829 }
5831 /// processIntegerCallValue - Record the value for an instruction that
5832 /// produces an integer result, converting the type where necessary.
5833 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5834 SDValue Value,
5835 bool IsSigned) {
5836 EVT VT = DAG.getTargetLoweringInfo().getValueType(I.getType(), true);
5837 if (IsSigned)
5838 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5839 else
5840 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5841 setValue(&I, Value);
5842 }
5844 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5845 /// If so, return true and lower it, otherwise return false and it will be
5846 /// lowered like a normal call.
5847 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5848 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5849 if (I.getNumArgOperands() != 3)
5850 return false;
5852 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5853 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5854 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5855 !I.getType()->isIntegerTy())
5856 return false;
5858 const Value *Size = I.getArgOperand(2);
5859 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5860 if (CSize && CSize->getZExtValue() == 0) {
5861 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(I.getType(), true);
5862 setValue(&I, DAG.getConstant(0, CallVT));
5863 return true;
5864 }
5866 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5867 std::pair<SDValue, SDValue> Res =
5868 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5869 getValue(LHS), getValue(RHS), getValue(Size),
5870 MachinePointerInfo(LHS),
5871 MachinePointerInfo(RHS));
5872 if (Res.first.getNode()) {
5873 processIntegerCallValue(I, Res.first, true);
5874 PendingLoads.push_back(Res.second);
5875 return true;
5876 }
5878 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5879 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5880 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5881 bool ActuallyDoIt = true;
5882 MVT LoadVT;
5883 Type *LoadTy;
5884 switch (CSize->getZExtValue()) {
5885 default:
5886 LoadVT = MVT::Other;
5887 LoadTy = nullptr;
5888 ActuallyDoIt = false;
5889 break;
5890 case 2:
5891 LoadVT = MVT::i16;
5892 LoadTy = Type::getInt16Ty(CSize->getContext());
5893 break;
5894 case 4:
5895 LoadVT = MVT::i32;
5896 LoadTy = Type::getInt32Ty(CSize->getContext());
5897 break;
5898 case 8:
5899 LoadVT = MVT::i64;
5900 LoadTy = Type::getInt64Ty(CSize->getContext());
5901 break;
5902 /*
5903 case 16:
5904 LoadVT = MVT::v4i32;
5905 LoadTy = Type::getInt32Ty(CSize->getContext());
5906 LoadTy = VectorType::get(LoadTy, 4);
5907 break;
5908 */
5909 }
5911 // This turns into unaligned loads. We only do this if the target natively
5912 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5913 // we'll only produce a small number of byte loads.
5915 // Require that we can find a legal MVT, and only do this if the target
5916 // supports unaligned loads of that type. Expanding into byte loads would
5917 // bloat the code.
5918 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5919 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5920 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5921 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5922 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5923 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5924 // TODO: Check alignment of src and dest ptrs.
5925 if (!TLI.isTypeLegal(LoadVT) ||
5926 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5927 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5928 ActuallyDoIt = false;
5929 }
5931 if (ActuallyDoIt) {
5932 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5933 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5935 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5936 ISD::SETNE);
5937 processIntegerCallValue(I, Res, false);
5938 return true;
5939 }
5940 }
5943 return false;
5944 }
5946 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5947 /// form. If so, return true and lower it, otherwise return false and it
5948 /// will be lowered like a normal call.
5949 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5950 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5951 if (I.getNumArgOperands() != 3)
5952 return false;
5954 const Value *Src = I.getArgOperand(0);
5955 const Value *Char = I.getArgOperand(1);
5956 const Value *Length = I.getArgOperand(2);
5957 if (!Src->getType()->isPointerTy() ||
5958 !Char->getType()->isIntegerTy() ||
5959 !Length->getType()->isIntegerTy() ||
5960 !I.getType()->isPointerTy())
5961 return false;
5963 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5964 std::pair<SDValue, SDValue> Res =
5965 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5966 getValue(Src), getValue(Char), getValue(Length),
5967 MachinePointerInfo(Src));
5968 if (Res.first.getNode()) {
5969 setValue(&I, Res.first);
5970 PendingLoads.push_back(Res.second);
5971 return true;
5972 }
5974 return false;
5975 }
5977 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5978 /// optimized form. If so, return true and lower it, otherwise return false
5979 /// and it will be lowered like a normal call.
5980 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5981 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5982 if (I.getNumArgOperands() != 2)
5983 return false;
5985 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5986 if (!Arg0->getType()->isPointerTy() ||
5987 !Arg1->getType()->isPointerTy() ||
5988 !I.getType()->isPointerTy())
5989 return false;
5991 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5992 std::pair<SDValue, SDValue> Res =
5993 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5994 getValue(Arg0), getValue(Arg1),
5995 MachinePointerInfo(Arg0),
5996 MachinePointerInfo(Arg1), isStpcpy);
5997 if (Res.first.getNode()) {
5998 setValue(&I, Res.first);
5999 DAG.setRoot(Res.second);
6000 return true;
6001 }
6003 return false;
6004 }
6006 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
6007 /// If so, return true and lower it, otherwise return false and it will be
6008 /// lowered like a normal call.
6009 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
6010 // Verify that the prototype makes sense. int strcmp(void*,void*)
6011 if (I.getNumArgOperands() != 2)
6012 return false;
6014 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
6015 if (!Arg0->getType()->isPointerTy() ||
6016 !Arg1->getType()->isPointerTy() ||
6017 !I.getType()->isIntegerTy())
6018 return false;
6020 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
6021 std::pair<SDValue, SDValue> Res =
6022 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
6023 getValue(Arg0), getValue(Arg1),
6024 MachinePointerInfo(Arg0),
6025 MachinePointerInfo(Arg1));
6026 if (Res.first.getNode()) {
6027 processIntegerCallValue(I, Res.first, true);
6028 PendingLoads.push_back(Res.second);
6029 return true;
6030 }
6032 return false;
6033 }
6035 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
6036 /// form. If so, return true and lower it, otherwise return false and it
6037 /// will be lowered like a normal call.
6038 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
6039 // Verify that the prototype makes sense. size_t strlen(char *)
6040 if (I.getNumArgOperands() != 1)
6041 return false;
6043 const Value *Arg0 = I.getArgOperand(0);
6044 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
6045 return false;
6047 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
6048 std::pair<SDValue, SDValue> Res =
6049 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
6050 getValue(Arg0), MachinePointerInfo(Arg0));
6051 if (Res.first.getNode()) {
6052 processIntegerCallValue(I, Res.first, false);
6053 PendingLoads.push_back(Res.second);
6054 return true;
6055 }
6057 return false;
6058 }
6060 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
6061 /// form. If so, return true and lower it, otherwise return false and it
6062 /// will be lowered like a normal call.
6063 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
6064 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
6065 if (I.getNumArgOperands() != 2)
6066 return false;
6068 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
6069 if (!Arg0->getType()->isPointerTy() ||
6070 !Arg1->getType()->isIntegerTy() ||
6071 !I.getType()->isIntegerTy())
6072 return false;
6074 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
6075 std::pair<SDValue, SDValue> Res =
6076 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
6077 getValue(Arg0), getValue(Arg1),
6078 MachinePointerInfo(Arg0));
6079 if (Res.first.getNode()) {
6080 processIntegerCallValue(I, Res.first, false);
6081 PendingLoads.push_back(Res.second);
6082 return true;
6083 }
6085 return false;
6086 }
6088 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
6089 /// operation (as expected), translate it to an SDNode with the specified opcode
6090 /// and return true.
6091 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
6092 unsigned Opcode) {
6093 // Sanity check that it really is a unary floating-point call.
6094 if (I.getNumArgOperands() != 1 ||
6095 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
6096 I.getType() != I.getArgOperand(0)->getType() ||
6097 !I.onlyReadsMemory())
6098 return false;
6100 SDValue Tmp = getValue(I.getArgOperand(0));
6101 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
6102 return true;
6103 }
6105 /// visitBinaryFloatCall - If a call instruction is a binary floating-point
6106 /// operation (as expected), translate it to an SDNode with the specified opcode
6107 /// and return true.
6108 bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
6109 unsigned Opcode) {
6110 // Sanity check that it really is a binary floating-point call.
6111 if (I.getNumArgOperands() != 2 ||
6112 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
6113 I.getType() != I.getArgOperand(0)->getType() ||
6114 I.getType() != I.getArgOperand(1)->getType() ||
6115 !I.onlyReadsMemory())
6116 return false;
6118 SDValue Tmp0 = getValue(I.getArgOperand(0));
6119 SDValue Tmp1 = getValue(I.getArgOperand(1));
6120 EVT VT = Tmp0.getValueType();
6121 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
6122 return true;
6123 }
6125 void SelectionDAGBuilder::visitCall(const CallInst &I) {
6126 // Handle inline assembly differently.
6127 if (isa<InlineAsm>(I.getCalledValue())) {
6128 visitInlineAsm(&I);
6129 return;
6130 }
6132 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
6133 ComputeUsesVAFloatArgument(I, &MMI);
6135 const char *RenameFn = nullptr;
6136 if (Function *F = I.getCalledFunction()) {
6137 if (F->isDeclaration()) {
6138 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
6139 if (unsigned IID = II->getIntrinsicID(F)) {
6140 RenameFn = visitIntrinsicCall(I, IID);
6141 if (!RenameFn)
6142 return;
6143 }
6144 }
6145 if (unsigned IID = F->getIntrinsicID()) {
6146 RenameFn = visitIntrinsicCall(I, IID);
6147 if (!RenameFn)
6148 return;
6149 }
6150 }
6152 // Check for well-known libc/libm calls. If the function is internal, it
6153 // can't be a library call.
6154 LibFunc::Func Func;
6155 if (!F->hasLocalLinkage() && F->hasName() &&
6156 LibInfo->getLibFunc(F->getName(), Func) &&
6157 LibInfo->hasOptimizedCodeGen(Func)) {
6158 switch (Func) {
6159 default: break;
6160 case LibFunc::copysign:
6161 case LibFunc::copysignf:
6162 case LibFunc::copysignl:
6163 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
6164 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
6165 I.getType() == I.getArgOperand(0)->getType() &&
6166 I.getType() == I.getArgOperand(1)->getType() &&
6167 I.onlyReadsMemory()) {
6168 SDValue LHS = getValue(I.getArgOperand(0));
6169 SDValue RHS = getValue(I.getArgOperand(1));
6170 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
6171 LHS.getValueType(), LHS, RHS));
6172 return;
6173 }
6174 break;
6175 case LibFunc::fabs:
6176 case LibFunc::fabsf:
6177 case LibFunc::fabsl:
6178 if (visitUnaryFloatCall(I, ISD::FABS))
6179 return;
6180 break;
6181 case LibFunc::fmin:
6182 case LibFunc::fminf:
6183 case LibFunc::fminl:
6184 if (visitBinaryFloatCall(I, ISD::FMINNUM))
6185 return;
6186 break;
6187 case LibFunc::fmax:
6188 case LibFunc::fmaxf:
6189 case LibFunc::fmaxl:
6190 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
6191 return;
6192 break;
6193 case LibFunc::sin:
6194 case LibFunc::sinf:
6195 case LibFunc::sinl:
6196 if (visitUnaryFloatCall(I, ISD::FSIN))
6197 return;
6198 break;
6199 case LibFunc::cos:
6200 case LibFunc::cosf:
6201 case LibFunc::cosl:
6202 if (visitUnaryFloatCall(I, ISD::FCOS))
6203 return;
6204 break;
6205 case LibFunc::sqrt:
6206 case LibFunc::sqrtf:
6207 case LibFunc::sqrtl:
6208 case LibFunc::sqrt_finite:
6209 case LibFunc::sqrtf_finite:
6210 case LibFunc::sqrtl_finite:
6211 if (visitUnaryFloatCall(I, ISD::FSQRT))
6212 return;
6213 break;
6214 case LibFunc::floor:
6215 case LibFunc::floorf:
6216 case LibFunc::floorl:
6217 if (visitUnaryFloatCall(I, ISD::FFLOOR))
6218 return;
6219 break;
6220 case LibFunc::nearbyint:
6221 case LibFunc::nearbyintf:
6222 case LibFunc::nearbyintl:
6223 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
6224 return;
6225 break;
6226 case LibFunc::ceil:
6227 case LibFunc::ceilf:
6228 case LibFunc::ceill:
6229 if (visitUnaryFloatCall(I, ISD::FCEIL))
6230 return;
6231 break;
6232 case LibFunc::rint:
6233 case LibFunc::rintf:
6234 case LibFunc::rintl:
6235 if (visitUnaryFloatCall(I, ISD::FRINT))
6236 return;
6237 break;
6238 case LibFunc::round:
6239 case LibFunc::roundf:
6240 case LibFunc::roundl:
6241 if (visitUnaryFloatCall(I, ISD::FROUND))
6242 return;
6243 break;
6244 case LibFunc::trunc:
6245 case LibFunc::truncf:
6246 case LibFunc::truncl:
6247 if (visitUnaryFloatCall(I, ISD::FTRUNC))
6248 return;
6249 break;
6250 case LibFunc::log2:
6251 case LibFunc::log2f:
6252 case LibFunc::log2l:
6253 if (visitUnaryFloatCall(I, ISD::FLOG2))
6254 return;
6255 break;
6256 case LibFunc::exp2:
6257 case LibFunc::exp2f:
6258 case LibFunc::exp2l:
6259 if (visitUnaryFloatCall(I, ISD::FEXP2))
6260 return;
6261 break;
6262 case LibFunc::memcmp:
6263 if (visitMemCmpCall(I))
6264 return;
6265 break;
6266 case LibFunc::memchr:
6267 if (visitMemChrCall(I))
6268 return;
6269 break;
6270 case LibFunc::strcpy:
6271 if (visitStrCpyCall(I, false))
6272 return;
6273 break;
6274 case LibFunc::stpcpy:
6275 if (visitStrCpyCall(I, true))
6276 return;
6277 break;
6278 case LibFunc::strcmp:
6279 if (visitStrCmpCall(I))
6280 return;
6281 break;
6282 case LibFunc::strlen:
6283 if (visitStrLenCall(I))
6284 return;
6285 break;
6286 case LibFunc::strnlen:
6287 if (visitStrNLenCall(I))
6288 return;
6289 break;
6290 }
6291 }
6292 }
6294 SDValue Callee;
6295 if (!RenameFn)
6296 Callee = getValue(I.getCalledValue());
6297 else
6298 Callee = DAG.getExternalSymbol(RenameFn,
6299 DAG.getTargetLoweringInfo().getPointerTy());
6301 // Check if we can potentially perform a tail call. More detailed checking is
6302 // be done within LowerCallTo, after more information about the call is known.
6303 LowerCallTo(&I, Callee, I.isTailCall());
6304 }
6306 namespace {
6308 /// AsmOperandInfo - This contains information for each constraint that we are
6309 /// lowering.
6310 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
6311 public:
6312 /// CallOperand - If this is the result output operand or a clobber
6313 /// this is null, otherwise it is the incoming operand to the CallInst.
6314 /// This gets modified as the asm is processed.
6315 SDValue CallOperand;
6317 /// AssignedRegs - If this is a register or register class operand, this
6318 /// contains the set of register corresponding to the operand.
6319 RegsForValue AssignedRegs;
6321 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
6322 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
6323 }
6325 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
6326 /// corresponds to. If there is no Value* for this operand, it returns
6327 /// MVT::Other.
6328 EVT getCallOperandValEVT(LLVMContext &Context,
6329 const TargetLowering &TLI,
6330 const DataLayout *DL) const {
6331 if (!CallOperandVal) return MVT::Other;
6333 if (isa<BasicBlock>(CallOperandVal))
6334 return TLI.getPointerTy();
6336 llvm::Type *OpTy = CallOperandVal->getType();
6338 // FIXME: code duplicated from TargetLowering::ParseConstraints().
6339 // If this is an indirect operand, the operand is a pointer to the
6340 // accessed type.
6341 if (isIndirect) {
6342 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
6343 if (!PtrTy)
6344 report_fatal_error("Indirect operand for inline asm not a pointer!");
6345 OpTy = PtrTy->getElementType();
6346 }
6348 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
6349 if (StructType *STy = dyn_cast<StructType>(OpTy))
6350 if (STy->getNumElements() == 1)
6351 OpTy = STy->getElementType(0);
6353 // If OpTy is not a single value, it may be a struct/union that we
6354 // can tile with integers.
6355 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
6356 unsigned BitSize = DL->getTypeSizeInBits(OpTy);
6357 switch (BitSize) {
6358 default: break;
6359 case 1:
6360 case 8:
6361 case 16:
6362 case 32:
6363 case 64:
6364 case 128:
6365 OpTy = IntegerType::get(Context, BitSize);
6366 break;
6367 }
6368 }
6370 return TLI.getValueType(OpTy, true);
6371 }
6372 };
6374 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
6376 } // end anonymous namespace
6378 /// GetRegistersForValue - Assign registers (virtual or physical) for the
6379 /// specified operand. We prefer to assign virtual registers, to allow the
6380 /// register allocator to handle the assignment process. However, if the asm
6381 /// uses features that we can't model on machineinstrs, we have SDISel do the
6382 /// allocation. This produces generally horrible, but correct, code.
6383 ///
6384 /// OpInfo describes the operand.
6385 ///
6386 static void GetRegistersForValue(SelectionDAG &DAG,
6387 const TargetLowering &TLI,
6388 SDLoc DL,
6389 SDISelAsmOperandInfo &OpInfo) {
6390 LLVMContext &Context = *DAG.getContext();
6392 MachineFunction &MF = DAG.getMachineFunction();
6393 SmallVector<unsigned, 4> Regs;
6395 // If this is a constraint for a single physreg, or a constraint for a
6396 // register class, find it.
6397 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
6398 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
6399 OpInfo.ConstraintVT);
6401 unsigned NumRegs = 1;
6402 if (OpInfo.ConstraintVT != MVT::Other) {
6403 // If this is a FP input in an integer register (or visa versa) insert a bit
6404 // cast of the input value. More generally, handle any case where the input
6405 // value disagrees with the register class we plan to stick this in.
6406 if (OpInfo.Type == InlineAsm::isInput &&
6407 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
6408 // Try to convert to the first EVT that the reg class contains. If the
6409 // types are identical size, use a bitcast to convert (e.g. two differing
6410 // vector types).
6411 MVT RegVT = *PhysReg.second->vt_begin();
6412 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
6413 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6414 RegVT, OpInfo.CallOperand);
6415 OpInfo.ConstraintVT = RegVT;
6416 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
6417 // If the input is a FP value and we want it in FP registers, do a
6418 // bitcast to the corresponding integer type. This turns an f64 value
6419 // into i64, which can be passed with two i32 values on a 32-bit
6420 // machine.
6421 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
6422 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6423 RegVT, OpInfo.CallOperand);
6424 OpInfo.ConstraintVT = RegVT;
6425 }
6426 }
6428 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
6429 }
6431 MVT RegVT;
6432 EVT ValueVT = OpInfo.ConstraintVT;
6434 // If this is a constraint for a specific physical register, like {r17},
6435 // assign it now.
6436 if (unsigned AssignedReg = PhysReg.first) {
6437 const TargetRegisterClass *RC = PhysReg.second;
6438 if (OpInfo.ConstraintVT == MVT::Other)
6439 ValueVT = *RC->vt_begin();
6441 // Get the actual register value type. This is important, because the user
6442 // may have asked for (e.g.) the AX register in i32 type. We need to
6443 // remember that AX is actually i16 to get the right extension.
6444 RegVT = *RC->vt_begin();
6446 // This is a explicit reference to a physical register.
6447 Regs.push_back(AssignedReg);
6449 // If this is an expanded reference, add the rest of the regs to Regs.
6450 if (NumRegs != 1) {
6451 TargetRegisterClass::iterator I = RC->begin();
6452 for (; *I != AssignedReg; ++I)
6453 assert(I != RC->end() && "Didn't find reg!");
6455 // Already added the first reg.
6456 --NumRegs; ++I;
6457 for (; NumRegs; --NumRegs, ++I) {
6458 assert(I != RC->end() && "Ran out of registers to allocate!");
6459 Regs.push_back(*I);
6460 }
6461 }
6463 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6464 return;
6465 }
6467 // Otherwise, if this was a reference to an LLVM register class, create vregs
6468 // for this reference.
6469 if (const TargetRegisterClass *RC = PhysReg.second) {
6470 RegVT = *RC->vt_begin();
6471 if (OpInfo.ConstraintVT == MVT::Other)
6472 ValueVT = RegVT;
6474 // Create the appropriate number of virtual registers.
6475 MachineRegisterInfo &RegInfo = MF.getRegInfo();
6476 for (; NumRegs; --NumRegs)
6477 Regs.push_back(RegInfo.createVirtualRegister(RC));
6479 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6480 return;
6481 }
6483 // Otherwise, we couldn't allocate enough registers for this.
6484 }
6486 /// visitInlineAsm - Handle a call to an InlineAsm object.
6487 ///
6488 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
6489 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
6491 /// ConstraintOperands - Information about all of the constraints.
6492 SDISelAsmOperandInfoVector ConstraintOperands;
6494 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6495 TargetLowering::AsmOperandInfoVector
6496 TargetConstraints = TLI.ParseConstraints(CS);
6498 bool hasMemory = false;
6500 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
6501 unsigned ResNo = 0; // ResNo - The result number of the next output.
6502 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6503 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
6504 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
6506 MVT OpVT = MVT::Other;
6508 // Compute the value type for each operand.
6509 switch (OpInfo.Type) {
6510 case InlineAsm::isOutput:
6511 // Indirect outputs just consume an argument.
6512 if (OpInfo.isIndirect) {
6513 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6514 break;
6515 }
6517 // The return value of the call is this value. As such, there is no
6518 // corresponding argument.
6519 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6520 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
6521 OpVT = TLI.getSimpleValueType(STy->getElementType(ResNo));
6522 } else {
6523 assert(ResNo == 0 && "Asm only has one result!");
6524 OpVT = TLI.getSimpleValueType(CS.getType());
6525 }
6526 ++ResNo;
6527 break;
6528 case InlineAsm::isInput:
6529 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6530 break;
6531 case InlineAsm::isClobber:
6532 // Nothing to do.
6533 break;
6534 }
6536 // If this is an input or an indirect output, process the call argument.
6537 // BasicBlocks are labels, currently appearing only in asm's.
6538 if (OpInfo.CallOperandVal) {
6539 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
6540 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
6541 } else {
6542 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
6543 }
6545 OpVT =
6546 OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, DL).getSimpleVT();
6547 }
6549 OpInfo.ConstraintVT = OpVT;
6551 // Indirect operand accesses access memory.
6552 if (OpInfo.isIndirect)
6553 hasMemory = true;
6554 else {
6555 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
6556 TargetLowering::ConstraintType
6557 CType = TLI.getConstraintType(OpInfo.Codes[j]);
6558 if (CType == TargetLowering::C_Memory) {
6559 hasMemory = true;
6560 break;
6561 }
6562 }
6563 }
6564 }
6566 SDValue Chain, Flag;
6568 // We won't need to flush pending loads if this asm doesn't touch
6569 // memory and is nonvolatile.
6570 if (hasMemory || IA->hasSideEffects())
6571 Chain = getRoot();
6572 else
6573 Chain = DAG.getRoot();
6575 // Second pass over the constraints: compute which constraint option to use
6576 // and assign registers to constraints that want a specific physreg.
6577 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6578 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6580 // If this is an output operand with a matching input operand, look up the
6581 // matching input. If their types mismatch, e.g. one is an integer, the
6582 // other is floating point, or their sizes are different, flag it as an
6583 // error.
6584 if (OpInfo.hasMatchingInput()) {
6585 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6587 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
6588 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
6589 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
6590 OpInfo.ConstraintVT);
6591 std::pair<unsigned, const TargetRegisterClass*> InputRC =
6592 TLI.getRegForInlineAsmConstraint(Input.ConstraintCode,
6593 Input.ConstraintVT);
6594 if ((OpInfo.ConstraintVT.isInteger() !=
6595 Input.ConstraintVT.isInteger()) ||
6596 (MatchRC.second != InputRC.second)) {
6597 report_fatal_error("Unsupported asm: input constraint"
6598 " with a matching output constraint of"
6599 " incompatible type!");
6600 }
6601 Input.ConstraintVT = OpInfo.ConstraintVT;
6602 }
6603 }
6605 // Compute the constraint code and ConstraintType to use.
6606 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6608 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6609 OpInfo.Type == InlineAsm::isClobber)
6610 continue;
6612 // If this is a memory input, and if the operand is not indirect, do what we
6613 // need to to provide an address for the memory input.
6614 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6615 !OpInfo.isIndirect) {
6616 assert((OpInfo.isMultipleAlternative ||
6617 (OpInfo.Type == InlineAsm::isInput)) &&
6618 "Can only indirectify direct input operands!");
6620 // Memory operands really want the address of the value. If we don't have
6621 // an indirect input, put it in the constpool if we can, otherwise spill
6622 // it to a stack slot.
6623 // TODO: This isn't quite right. We need to handle these according to
6624 // the addressing mode that the constraint wants. Also, this may take
6625 // an additional register for the computation and we don't want that
6626 // either.
6628 // If the operand is a float, integer, or vector constant, spill to a
6629 // constant pool entry to get its address.
6630 const Value *OpVal = OpInfo.CallOperandVal;
6631 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6632 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6633 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
6634 TLI.getPointerTy());
6635 } else {
6636 // Otherwise, create a stack slot and emit a store to it before the
6637 // asm.
6638 Type *Ty = OpVal->getType();
6639 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
6640 unsigned Align = TLI.getDataLayout()->getPrefTypeAlignment(Ty);
6641 MachineFunction &MF = DAG.getMachineFunction();
6642 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6643 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
6644 Chain = DAG.getStore(Chain, getCurSDLoc(),
6645 OpInfo.CallOperand, StackSlot,
6646 MachinePointerInfo::getFixedStack(SSFI),
6647 false, false, 0);
6648 OpInfo.CallOperand = StackSlot;
6649 }
6651 // There is no longer a Value* corresponding to this operand.
6652 OpInfo.CallOperandVal = nullptr;
6654 // It is now an indirect operand.
6655 OpInfo.isIndirect = true;
6656 }
6658 // If this constraint is for a specific register, allocate it before
6659 // anything else.
6660 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6661 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6662 }
6664 // Second pass - Loop over all of the operands, assigning virtual or physregs
6665 // to register class operands.
6666 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6667 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6669 // C_Register operands have already been allocated, Other/Memory don't need
6670 // to be.
6671 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6672 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6673 }
6675 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6676 std::vector<SDValue> AsmNodeOperands;
6677 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6678 AsmNodeOperands.push_back(
6679 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
6680 TLI.getPointerTy()));
6682 // If we have a !srcloc metadata node associated with it, we want to attach
6683 // this to the ultimately generated inline asm machineinstr. To do this, we
6684 // pass in the third operand as this (potentially null) inline asm MDNode.
6685 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6686 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6688 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6689 // bits as operand 3.
6690 unsigned ExtraInfo = 0;
6691 if (IA->hasSideEffects())
6692 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6693 if (IA->isAlignStack())
6694 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6695 // Set the asm dialect.
6696 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6698 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6699 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6700 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6702 // Compute the constraint code and ConstraintType to use.
6703 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6705 // Ideally, we would only check against memory constraints. However, the
6706 // meaning of an other constraint can be target-specific and we can't easily
6707 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6708 // for other constriants as well.
6709 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6710 OpInfo.ConstraintType == TargetLowering::C_Other) {
6711 if (OpInfo.Type == InlineAsm::isInput)
6712 ExtraInfo |= InlineAsm::Extra_MayLoad;
6713 else if (OpInfo.Type == InlineAsm::isOutput)
6714 ExtraInfo |= InlineAsm::Extra_MayStore;
6715 else if (OpInfo.Type == InlineAsm::isClobber)
6716 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6717 }
6718 }
6720 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
6721 TLI.getPointerTy()));
6723 // Loop over all of the inputs, copying the operand values into the
6724 // appropriate registers and processing the output regs.
6725 RegsForValue RetValRegs;
6727 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6728 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6730 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6731 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6733 switch (OpInfo.Type) {
6734 case InlineAsm::isOutput: {
6735 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6736 OpInfo.ConstraintType != TargetLowering::C_Register) {
6737 // Memory output, or 'other' output (e.g. 'X' constraint).
6738 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6740 // Add information to the INLINEASM node to know about this output.
6741 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6742 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
6743 TLI.getPointerTy()));
6744 AsmNodeOperands.push_back(OpInfo.CallOperand);
6745 break;
6746 }
6748 // Otherwise, this is a register or register class output.
6750 // Copy the output from the appropriate register. Find a register that
6751 // we can use.
6752 if (OpInfo.AssignedRegs.Regs.empty()) {
6753 LLVMContext &Ctx = *DAG.getContext();
6754 Ctx.emitError(CS.getInstruction(),
6755 "couldn't allocate output register for constraint '" +
6756 Twine(OpInfo.ConstraintCode) + "'");
6757 return;
6758 }
6760 // If this is an indirect operand, store through the pointer after the
6761 // asm.
6762 if (OpInfo.isIndirect) {
6763 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6764 OpInfo.CallOperandVal));
6765 } else {
6766 // This is the result value of the call.
6767 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6768 // Concatenate this output onto the outputs list.
6769 RetValRegs.append(OpInfo.AssignedRegs);
6770 }
6772 // Add information to the INLINEASM node to know that this register is
6773 // set.
6774 OpInfo.AssignedRegs
6775 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6776 ? InlineAsm::Kind_RegDefEarlyClobber
6777 : InlineAsm::Kind_RegDef,
6778 false, 0, DAG, AsmNodeOperands);
6779 break;
6780 }
6781 case InlineAsm::isInput: {
6782 SDValue InOperandVal = OpInfo.CallOperand;
6784 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6785 // If this is required to match an output register we have already set,
6786 // just use its register.
6787 unsigned OperandNo = OpInfo.getMatchedOperand();
6789 // Scan until we find the definition we already emitted of this operand.
6790 // When we find it, create a RegsForValue operand.
6791 unsigned CurOp = InlineAsm::Op_FirstOperand;
6792 for (; OperandNo; --OperandNo) {
6793 // Advance to the next operand.
6794 unsigned OpFlag =
6795 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6796 assert((InlineAsm::isRegDefKind(OpFlag) ||
6797 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6798 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6799 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6800 }
6802 unsigned OpFlag =
6803 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6804 if (InlineAsm::isRegDefKind(OpFlag) ||
6805 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6806 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6807 if (OpInfo.isIndirect) {
6808 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6809 LLVMContext &Ctx = *DAG.getContext();
6810 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6811 " don't know how to handle tied "
6812 "indirect register inputs");
6813 return;
6814 }
6816 RegsForValue MatchedRegs;
6817 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6818 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6819 MatchedRegs.RegVTs.push_back(RegVT);
6820 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6821 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6822 i != e; ++i) {
6823 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6824 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6825 else {
6826 LLVMContext &Ctx = *DAG.getContext();
6827 Ctx.emitError(CS.getInstruction(),
6828 "inline asm error: This value"
6829 " type register class is not natively supported!");
6830 return;
6831 }
6832 }
6833 // Use the produced MatchedRegs object to
6834 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6835 Chain, &Flag, CS.getInstruction());
6836 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6837 true, OpInfo.getMatchedOperand(),
6838 DAG, AsmNodeOperands);
6839 break;
6840 }
6842 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6843 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6844 "Unexpected number of operands");
6845 // Add information to the INLINEASM node to know about this input.
6846 // See InlineAsm.h isUseOperandTiedToDef.
6847 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6848 OpInfo.getMatchedOperand());
6849 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
6850 TLI.getPointerTy()));
6851 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6852 break;
6853 }
6855 // Treat indirect 'X' constraint as memory.
6856 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6857 OpInfo.isIndirect)
6858 OpInfo.ConstraintType = TargetLowering::C_Memory;
6860 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6861 std::vector<SDValue> Ops;
6862 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6863 Ops, DAG);
6864 if (Ops.empty()) {
6865 LLVMContext &Ctx = *DAG.getContext();
6866 Ctx.emitError(CS.getInstruction(),
6867 "invalid operand for inline asm constraint '" +
6868 Twine(OpInfo.ConstraintCode) + "'");
6869 return;
6870 }
6872 // Add information to the INLINEASM node to know about this input.
6873 unsigned ResOpType =
6874 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6875 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6876 TLI.getPointerTy()));
6877 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6878 break;
6879 }
6881 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6882 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6883 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
6884 "Memory operands expect pointer values");
6886 // Add information to the INLINEASM node to know about this input.
6887 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6888 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6889 TLI.getPointerTy()));
6890 AsmNodeOperands.push_back(InOperandVal);
6891 break;
6892 }
6894 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6895 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6896 "Unknown constraint type!");
6898 // TODO: Support this.
6899 if (OpInfo.isIndirect) {
6900 LLVMContext &Ctx = *DAG.getContext();
6901 Ctx.emitError(CS.getInstruction(),
6902 "Don't know how to handle indirect register inputs yet "
6903 "for constraint '" +
6904 Twine(OpInfo.ConstraintCode) + "'");
6905 return;
6906 }
6908 // Copy the input into the appropriate registers.
6909 if (OpInfo.AssignedRegs.Regs.empty()) {
6910 LLVMContext &Ctx = *DAG.getContext();
6911 Ctx.emitError(CS.getInstruction(),
6912 "couldn't allocate input reg for constraint '" +
6913 Twine(OpInfo.ConstraintCode) + "'");
6914 return;
6915 }
6917 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6918 Chain, &Flag, CS.getInstruction());
6920 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6921 DAG, AsmNodeOperands);
6922 break;
6923 }
6924 case InlineAsm::isClobber: {
6925 // Add the clobbered value to the operand list, so that the register
6926 // allocator is aware that the physreg got clobbered.
6927 if (!OpInfo.AssignedRegs.Regs.empty())
6928 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6929 false, 0, DAG,
6930 AsmNodeOperands);
6931 break;
6932 }
6933 }
6934 }
6936 // Finish up input operands. Set the input chain and add the flag last.
6937 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6938 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6940 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6941 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6942 Flag = Chain.getValue(1);
6944 // If this asm returns a register value, copy the result from that register
6945 // and set it as the value of the call.
6946 if (!RetValRegs.Regs.empty()) {
6947 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6948 Chain, &Flag, CS.getInstruction());
6950 // FIXME: Why don't we do this for inline asms with MRVs?
6951 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6952 EVT ResultType = TLI.getValueType(CS.getType());
6954 // If any of the results of the inline asm is a vector, it may have the
6955 // wrong width/num elts. This can happen for register classes that can
6956 // contain multiple different value types. The preg or vreg allocated may
6957 // not have the same VT as was expected. Convert it to the right type
6958 // with bit_convert.
6959 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6960 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6961 ResultType, Val);
6963 } else if (ResultType != Val.getValueType() &&
6964 ResultType.isInteger() && Val.getValueType().isInteger()) {
6965 // If a result value was tied to an input value, the computed result may
6966 // have a wider width than the expected result. Extract the relevant
6967 // portion.
6968 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6969 }
6971 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6972 }
6974 setValue(CS.getInstruction(), Val);
6975 // Don't need to use this as a chain in this case.
6976 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6977 return;
6978 }
6980 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6982 // Process indirect outputs, first output all of the flagged copies out of
6983 // physregs.
6984 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6985 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6986 const Value *Ptr = IndirectStoresToEmit[i].second;
6987 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6988 Chain, &Flag, IA);
6989 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6990 }
6992 // Emit the non-flagged stores from the physregs.
6993 SmallVector<SDValue, 8> OutChains;
6994 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6995 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6996 StoresToEmit[i].first,
6997 getValue(StoresToEmit[i].second),
6998 MachinePointerInfo(StoresToEmit[i].second),
6999 false, false, 0);
7000 OutChains.push_back(Val);
7001 }
7003 if (!OutChains.empty())
7004 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
7006 DAG.setRoot(Chain);
7007 }
7009 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
7010 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
7011 MVT::Other, getRoot(),
7012 getValue(I.getArgOperand(0)),
7013 DAG.getSrcValue(I.getArgOperand(0))));
7014 }
7016 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
7017 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7018 const DataLayout &DL = *TLI.getDataLayout();
7019 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurSDLoc(),
7020 getRoot(), getValue(I.getOperand(0)),
7021 DAG.getSrcValue(I.getOperand(0)),
7022 DL.getABITypeAlignment(I.getType()));
7023 setValue(&I, V);
7024 DAG.setRoot(V.getValue(1));
7025 }
7027 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
7028 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
7029 MVT::Other, getRoot(),
7030 getValue(I.getArgOperand(0)),
7031 DAG.getSrcValue(I.getArgOperand(0))));
7032 }
7034 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
7035 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
7036 MVT::Other, getRoot(),
7037 getValue(I.getArgOperand(0)),
7038 getValue(I.getArgOperand(1)),
7039 DAG.getSrcValue(I.getArgOperand(0)),
7040 DAG.getSrcValue(I.getArgOperand(1))));
7041 }
7043 /// \brief Lower an argument list according to the target calling convention.
7044 ///
7045 /// \return A tuple of <return-value, token-chain>
7046 ///
7047 /// This is a helper for lowering intrinsics that follow a target calling
7048 /// convention or require stack pointer adjustment. Only a subset of the
7049 /// intrinsic's operands need to participate in the calling convention.
7050 std::pair<SDValue, SDValue>
7051 SelectionDAGBuilder::lowerCallOperands(ImmutableCallSite CS, unsigned ArgIdx,
7052 unsigned NumArgs, SDValue Callee,
7053 bool UseVoidTy,
7054 MachineBasicBlock *LandingPad,
7055 bool IsPatchPoint) {
7056 TargetLowering::ArgListTy Args;
7057 Args.reserve(NumArgs);
7059 // Populate the argument list.
7060 // Attributes for args start at offset 1, after the return attribute.
7061 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
7062 ArgI != ArgE; ++ArgI) {
7063 const Value *V = CS->getOperand(ArgI);
7065 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
7067 TargetLowering::ArgListEntry Entry;
7068 Entry.Node = getValue(V);
7069 Entry.Ty = V->getType();
7070 Entry.setAttributes(&CS, AttrI);
7071 Args.push_back(Entry);
7072 }
7074 Type *retTy = UseVoidTy ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
7075 TargetLowering::CallLoweringInfo CLI(DAG);
7076 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
7077 .setCallee(CS.getCallingConv(), retTy, Callee, std::move(Args), NumArgs)
7078 .setDiscardResult(CS->use_empty()).setIsPatchPoint(IsPatchPoint);
7080 return lowerInvokable(CLI, LandingPad);
7081 }
7083 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
7084 /// or patchpoint target node's operand list.
7085 ///
7086 /// Constants are converted to TargetConstants purely as an optimization to
7087 /// avoid constant materialization and register allocation.
7088 ///
7089 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
7090 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
7091 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
7092 /// address materialization and register allocation, but may also be required
7093 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
7094 /// alloca in the entry block, then the runtime may assume that the alloca's
7095 /// StackMap location can be read immediately after compilation and that the
7096 /// location is valid at any point during execution (this is similar to the
7097 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
7098 /// only available in a register, then the runtime would need to trap when
7099 /// execution reaches the StackMap in order to read the alloca's location.
7100 static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
7101 SmallVectorImpl<SDValue> &Ops,
7102 SelectionDAGBuilder &Builder) {
7103 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
7104 SDValue OpVal = Builder.getValue(CS.getArgument(i));
7105 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
7106 Ops.push_back(
7107 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, MVT::i64));
7108 Ops.push_back(
7109 Builder.DAG.getTargetConstant(C->getSExtValue(), MVT::i64));
7110 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
7111 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
7112 Ops.push_back(
7113 Builder.DAG.getTargetFrameIndex(FI->getIndex(), TLI.getPointerTy()));
7114 } else
7115 Ops.push_back(OpVal);
7116 }
7117 }
7119 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
7120 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
7121 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
7122 // [live variables...])
7124 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
7126 SDValue Chain, InFlag, Callee, NullPtr;
7127 SmallVector<SDValue, 32> Ops;
7129 SDLoc DL = getCurSDLoc();
7130 Callee = getValue(CI.getCalledValue());
7131 NullPtr = DAG.getIntPtrConstant(0, true);
7133 // The stackmap intrinsic only records the live variables (the arguemnts
7134 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
7135 // intrinsic, this won't be lowered to a function call. This means we don't
7136 // have to worry about calling conventions and target specific lowering code.
7137 // Instead we perform the call lowering right here.
7138 //
7139 // chain, flag = CALLSEQ_START(chain, 0)
7140 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
7141 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
7142 //
7143 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
7144 InFlag = Chain.getValue(1);
7146 // Add the <id> and <numBytes> constants.
7147 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
7148 Ops.push_back(DAG.getTargetConstant(
7149 cast<ConstantSDNode>(IDVal)->getZExtValue(), MVT::i64));
7150 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
7151 Ops.push_back(DAG.getTargetConstant(
7152 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), MVT::i32));
7154 // Push live variables for the stack map.
7155 addStackMapLiveVars(&CI, 2, Ops, *this);
7157 // We are not pushing any register mask info here on the operands list,
7158 // because the stackmap doesn't clobber anything.
7160 // Push the chain and the glue flag.
7161 Ops.push_back(Chain);
7162 Ops.push_back(InFlag);
7164 // Create the STACKMAP node.
7165 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7166 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
7167 Chain = SDValue(SM, 0);
7168 InFlag = Chain.getValue(1);
7170 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
7172 // Stackmaps don't generate values, so nothing goes into the NodeMap.
7174 // Set the root to the target-lowered call chain.
7175 DAG.setRoot(Chain);
7177 // Inform the Frame Information that we have a stackmap in this function.
7178 FuncInfo.MF->getFrameInfo()->setHasStackMap();
7179 }
7181 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
7182 void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
7183 MachineBasicBlock *LandingPad) {
7184 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
7185 // i32 <numBytes>,
7186 // i8* <target>,
7187 // i32 <numArgs>,
7188 // [Args...],
7189 // [live variables...])
7191 CallingConv::ID CC = CS.getCallingConv();
7192 bool IsAnyRegCC = CC == CallingConv::AnyReg;
7193 bool HasDef = !CS->getType()->isVoidTy();
7194 SDValue Callee = getValue(CS->getOperand(2)); // <target>
7196 // Get the real number of arguments participating in the call <numArgs>
7197 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
7198 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
7200 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
7201 // Intrinsics include all meta-operands up to but not including CC.
7202 unsigned NumMetaOpers = PatchPointOpers::CCPos;
7203 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&
7204 "Not enough arguments provided to the patchpoint intrinsic");
7206 // For AnyRegCC the arguments are lowered later on manually.
7207 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
7208 std::pair<SDValue, SDValue> Result =
7209 lowerCallOperands(CS, NumMetaOpers, NumCallArgs, Callee, IsAnyRegCC,
7210 LandingPad, true);
7212 SDNode *CallEnd = Result.second.getNode();
7213 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
7214 CallEnd = CallEnd->getOperand(0).getNode();
7216 /// Get a call instruction from the call sequence chain.
7217 /// Tail calls are not allowed.
7218 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
7219 "Expected a callseq node.");
7220 SDNode *Call = CallEnd->getOperand(0).getNode();
7221 bool HasGlue = Call->getGluedNode();
7223 // Replace the target specific call node with the patchable intrinsic.
7224 SmallVector<SDValue, 8> Ops;
7226 // Add the <id> and <numBytes> constants.
7227 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
7228 Ops.push_back(DAG.getTargetConstant(
7229 cast<ConstantSDNode>(IDVal)->getZExtValue(), MVT::i64));
7230 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
7231 Ops.push_back(DAG.getTargetConstant(
7232 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), MVT::i32));
7234 // Assume that the Callee is a constant address.
7235 // FIXME: handle function symbols in the future.
7236 Ops.push_back(
7237 DAG.getIntPtrConstant(cast<ConstantSDNode>(Callee)->getZExtValue(),
7238 /*isTarget=*/true));
7240 // Adjust <numArgs> to account for any arguments that have been passed on the
7241 // stack instead.
7242 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
7243 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
7244 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
7245 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, MVT::i32));
7247 // Add the calling convention
7248 Ops.push_back(DAG.getTargetConstant((unsigned)CC, MVT::i32));
7250 // Add the arguments we omitted previously. The register allocator should
7251 // place these in any free register.
7252 if (IsAnyRegCC)
7253 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
7254 Ops.push_back(getValue(CS.getArgument(i)));
7256 // Push the arguments from the call instruction up to the register mask.
7257 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
7258 for (SDNode::op_iterator i = Call->op_begin()+2; i != e; ++i)
7259 Ops.push_back(*i);
7261 // Push live variables for the stack map.
7262 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, Ops, *this);
7264 // Push the register mask info.
7265 if (HasGlue)
7266 Ops.push_back(*(Call->op_end()-2));
7267 else
7268 Ops.push_back(*(Call->op_end()-1));
7270 // Push the chain (this is originally the first operand of the call, but
7271 // becomes now the last or second to last operand).
7272 Ops.push_back(*(Call->op_begin()));
7274 // Push the glue flag (last operand).
7275 if (HasGlue)
7276 Ops.push_back(*(Call->op_end()-1));
7278 SDVTList NodeTys;
7279 if (IsAnyRegCC && HasDef) {
7280 // Create the return types based on the intrinsic definition
7281 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7282 SmallVector<EVT, 3> ValueVTs;
7283 ComputeValueVTs(TLI, CS->getType(), ValueVTs);
7284 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
7286 // There is always a chain and a glue type at the end
7287 ValueVTs.push_back(MVT::Other);
7288 ValueVTs.push_back(MVT::Glue);
7289 NodeTys = DAG.getVTList(ValueVTs);
7290 } else
7291 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7293 // Replace the target specific call node with a PATCHPOINT node.
7294 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
7295 getCurSDLoc(), NodeTys, Ops);
7297 // Update the NodeMap.
7298 if (HasDef) {
7299 if (IsAnyRegCC)
7300 setValue(CS.getInstruction(), SDValue(MN, 0));
7301 else
7302 setValue(CS.getInstruction(), Result.first);
7303 }
7305 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
7306 // call sequence. Furthermore the location of the chain and glue can change
7307 // when the AnyReg calling convention is used and the intrinsic returns a
7308 // value.
7309 if (IsAnyRegCC && HasDef) {
7310 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
7311 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
7312 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
7313 } else
7314 DAG.ReplaceAllUsesWith(Call, MN);
7315 DAG.DeleteNode(Call);
7317 // Inform the Frame Information that we have a patchpoint in this function.
7318 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
7319 }
7321 /// Returns an AttributeSet representing the attributes applied to the return
7322 /// value of the given call.
7323 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
7324 SmallVector<Attribute::AttrKind, 2> Attrs;
7325 if (CLI.RetSExt)
7326 Attrs.push_back(Attribute::SExt);
7327 if (CLI.RetZExt)
7328 Attrs.push_back(Attribute::ZExt);
7329 if (CLI.IsInReg)
7330 Attrs.push_back(Attribute::InReg);
7332 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
7333 Attrs);
7334 }
7336 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
7337 /// implementation, which just calls LowerCall.
7338 /// FIXME: When all targets are
7339 /// migrated to using LowerCall, this hook should be integrated into SDISel.
7340 std::pair<SDValue, SDValue>
7341 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
7342 // Handle the incoming return values from the call.
7343 CLI.Ins.clear();
7344 Type *OrigRetTy = CLI.RetTy;
7345 SmallVector<EVT, 4> RetTys;
7346 SmallVector<uint64_t, 4> Offsets;
7347 ComputeValueVTs(*this, CLI.RetTy, RetTys, &Offsets);
7349 SmallVector<ISD::OutputArg, 4> Outs;
7350 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this);
7352 bool CanLowerReturn =
7353 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
7354 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
7356 SDValue DemoteStackSlot;
7357 int DemoteStackIdx = -100;
7358 if (!CanLowerReturn) {
7359 // FIXME: equivalent assert?
7360 // assert(!CS.hasInAllocaArgument() &&
7361 // "sret demotion is incompatible with inalloca");
7362 uint64_t TySize = getDataLayout()->getTypeAllocSize(CLI.RetTy);
7363 unsigned Align = getDataLayout()->getPrefTypeAlignment(CLI.RetTy);
7364 MachineFunction &MF = CLI.DAG.getMachineFunction();
7365 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
7366 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
7368 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy());
7369 ArgListEntry Entry;
7370 Entry.Node = DemoteStackSlot;
7371 Entry.Ty = StackSlotPtrType;
7372 Entry.isSExt = false;
7373 Entry.isZExt = false;
7374 Entry.isInReg = false;
7375 Entry.isSRet = true;
7376 Entry.isNest = false;
7377 Entry.isByVal = false;
7378 Entry.isReturned = false;
7379 Entry.Alignment = Align;
7380 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
7381 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
7382 } else {
7383 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7384 EVT VT = RetTys[I];
7385 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7386 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7387 for (unsigned i = 0; i != NumRegs; ++i) {
7388 ISD::InputArg MyFlags;
7389 MyFlags.VT = RegisterVT;
7390 MyFlags.ArgVT = VT;
7391 MyFlags.Used = CLI.IsReturnValueUsed;
7392 if (CLI.RetSExt)
7393 MyFlags.Flags.setSExt();
7394 if (CLI.RetZExt)
7395 MyFlags.Flags.setZExt();
7396 if (CLI.IsInReg)
7397 MyFlags.Flags.setInReg();
7398 CLI.Ins.push_back(MyFlags);
7399 }
7400 }
7401 }
7403 // Handle all of the outgoing arguments.
7404 CLI.Outs.clear();
7405 CLI.OutVals.clear();
7406 ArgListTy &Args = CLI.getArgs();
7407 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
7408 SmallVector<EVT, 4> ValueVTs;
7409 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
7410 Type *FinalType = Args[i].Ty;
7411 if (Args[i].isByVal)
7412 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
7413 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
7414 FinalType, CLI.CallConv, CLI.IsVarArg);
7415 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
7416 ++Value) {
7417 EVT VT = ValueVTs[Value];
7418 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
7419 SDValue Op = SDValue(Args[i].Node.getNode(),
7420 Args[i].Node.getResNo() + Value);
7421 ISD::ArgFlagsTy Flags;
7422 unsigned OriginalAlignment = getDataLayout()->getABITypeAlignment(ArgTy);
7424 if (Args[i].isZExt)
7425 Flags.setZExt();
7426 if (Args[i].isSExt)
7427 Flags.setSExt();
7428 if (Args[i].isInReg)
7429 Flags.setInReg();
7430 if (Args[i].isSRet)
7431 Flags.setSRet();
7432 if (Args[i].isByVal)
7433 Flags.setByVal();
7434 if (Args[i].isInAlloca) {
7435 Flags.setInAlloca();
7436 // Set the byval flag for CCAssignFn callbacks that don't know about
7437 // inalloca. This way we can know how many bytes we should've allocated
7438 // and how many bytes a callee cleanup function will pop. If we port
7439 // inalloca to more targets, we'll have to add custom inalloca handling
7440 // in the various CC lowering callbacks.
7441 Flags.setByVal();
7442 }
7443 if (Args[i].isByVal || Args[i].isInAlloca) {
7444 PointerType *Ty = cast<PointerType>(Args[i].Ty);
7445 Type *ElementTy = Ty->getElementType();
7446 Flags.setByValSize(getDataLayout()->getTypeAllocSize(ElementTy));
7447 // For ByVal, alignment should come from FE. BE will guess if this
7448 // info is not there but there are cases it cannot get right.
7449 unsigned FrameAlign;
7450 if (Args[i].Alignment)
7451 FrameAlign = Args[i].Alignment;
7452 else
7453 FrameAlign = getByValTypeAlignment(ElementTy);
7454 Flags.setByValAlign(FrameAlign);
7455 }
7456 if (Args[i].isNest)
7457 Flags.setNest();
7458 if (NeedsRegBlock) {
7459 Flags.setInConsecutiveRegs();
7460 if (Value == NumValues - 1)
7461 Flags.setInConsecutiveRegsLast();
7462 }
7463 Flags.setOrigAlign(OriginalAlignment);
7465 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
7466 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
7467 SmallVector<SDValue, 4> Parts(NumParts);
7468 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
7470 if (Args[i].isSExt)
7471 ExtendKind = ISD::SIGN_EXTEND;
7472 else if (Args[i].isZExt)
7473 ExtendKind = ISD::ZERO_EXTEND;
7475 // Conservatively only handle 'returned' on non-vectors for now
7476 if (Args[i].isReturned && !Op.getValueType().isVector()) {
7477 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
7478 "unexpected use of 'returned'");
7479 // Before passing 'returned' to the target lowering code, ensure that
7480 // either the register MVT and the actual EVT are the same size or that
7481 // the return value and argument are extended in the same way; in these
7482 // cases it's safe to pass the argument register value unchanged as the
7483 // return register value (although it's at the target's option whether
7484 // to do so)
7485 // TODO: allow code generation to take advantage of partially preserved
7486 // registers rather than clobbering the entire register when the
7487 // parameter extension method is not compatible with the return
7488 // extension method
7489 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
7490 (ExtendKind != ISD::ANY_EXTEND &&
7491 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
7492 Flags.setReturned();
7493 }
7495 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
7496 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
7498 for (unsigned j = 0; j != NumParts; ++j) {
7499 // if it isn't first piece, alignment must be 1
7500 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7501 i < CLI.NumFixedArgs,
7502 i, j*Parts[j].getValueType().getStoreSize());
7503 if (NumParts > 1 && j == 0)
7504 MyFlags.Flags.setSplit();
7505 else if (j != 0)
7506 MyFlags.Flags.setOrigAlign(1);
7508 CLI.Outs.push_back(MyFlags);
7509 CLI.OutVals.push_back(Parts[j]);
7510 }
7511 }
7512 }
7514 SmallVector<SDValue, 4> InVals;
7515 CLI.Chain = LowerCall(CLI, InVals);
7517 // Verify that the target's LowerCall behaved as expected.
7518 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7519 "LowerCall didn't return a valid chain!");
7520 assert((!CLI.IsTailCall || InVals.empty()) &&
7521 "LowerCall emitted a return value for a tail call!");
7522 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7523 "LowerCall didn't emit the correct number of values!");
7525 // For a tail call, the return value is merely live-out and there aren't
7526 // any nodes in the DAG representing it. Return a special value to
7527 // indicate that a tail call has been emitted and no more Instructions
7528 // should be processed in the current block.
7529 if (CLI.IsTailCall) {
7530 CLI.DAG.setRoot(CLI.Chain);
7531 return std::make_pair(SDValue(), SDValue());
7532 }
7534 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7535 assert(InVals[i].getNode() &&
7536 "LowerCall emitted a null value!");
7537 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7538 "LowerCall emitted a value with the wrong type!");
7539 });
7541 SmallVector<SDValue, 4> ReturnValues;
7542 if (!CanLowerReturn) {
7543 // The instruction result is the result of loading from the
7544 // hidden sret parameter.
7545 SmallVector<EVT, 1> PVTs;
7546 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
7548 ComputeValueVTs(*this, PtrRetTy, PVTs);
7549 assert(PVTs.size() == 1 && "Pointers should fit in one register");
7550 EVT PtrVT = PVTs[0];
7552 unsigned NumValues = RetTys.size();
7553 ReturnValues.resize(NumValues);
7554 SmallVector<SDValue, 4> Chains(NumValues);
7556 for (unsigned i = 0; i < NumValues; ++i) {
7557 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
7558 CLI.DAG.getConstant(Offsets[i], PtrVT));
7559 SDValue L = CLI.DAG.getLoad(
7560 RetTys[i], CLI.DL, CLI.Chain, Add,
7561 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), false,
7562 false, false, 1);
7563 ReturnValues[i] = L;
7564 Chains[i] = L.getValue(1);
7565 }
7567 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
7568 } else {
7569 // Collect the legal value parts into potentially illegal values
7570 // that correspond to the original function's return values.
7571 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7572 if (CLI.RetSExt)
7573 AssertOp = ISD::AssertSext;
7574 else if (CLI.RetZExt)
7575 AssertOp = ISD::AssertZext;
7576 unsigned CurReg = 0;
7577 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7578 EVT VT = RetTys[I];
7579 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7580 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7582 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7583 NumRegs, RegisterVT, VT, nullptr,
7584 AssertOp));
7585 CurReg += NumRegs;
7586 }
7588 // For a function returning void, there is no return value. We can't create
7589 // such a node, so we just return a null return value in that case. In
7590 // that case, nothing will actually look at the value.
7591 if (ReturnValues.empty())
7592 return std::make_pair(SDValue(), CLI.Chain);
7593 }
7595 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7596 CLI.DAG.getVTList(RetTys), ReturnValues);
7597 return std::make_pair(Res, CLI.Chain);
7598 }
7600 void TargetLowering::LowerOperationWrapper(SDNode *N,
7601 SmallVectorImpl<SDValue> &Results,
7602 SelectionDAG &DAG) const {
7603 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7604 if (Res.getNode())
7605 Results.push_back(Res);
7606 }
7608 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7609 llvm_unreachable("LowerOperation not implemented for this target!");
7610 }
7612 void
7613 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7614 SDValue Op = getNonRegisterValue(V);
7615 assert((Op.getOpcode() != ISD::CopyFromReg ||
7616 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7617 "Copy from a reg to the same reg!");
7618 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7620 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7621 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
7622 SDValue Chain = DAG.getEntryNode();
7624 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
7625 FuncInfo.PreferredExtendType.end())
7626 ? ISD::ANY_EXTEND
7627 : FuncInfo.PreferredExtendType[V];
7628 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
7629 PendingExports.push_back(Chain);
7630 }
7632 #include "llvm/CodeGen/SelectionDAGISel.h"
7634 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7635 /// entry block, return true. This includes arguments used by switches, since
7636 /// the switch may expand into multiple basic blocks.
7637 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7638 // With FastISel active, we may be splitting blocks, so force creation
7639 // of virtual registers for all non-dead arguments.
7640 if (FastISel)
7641 return A->use_empty();
7643 const BasicBlock *Entry = A->getParent()->begin();
7644 for (const User *U : A->users())
7645 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
7646 return false; // Use not in entry block.
7648 return true;
7649 }
7651 void SelectionDAGISel::LowerArguments(const Function &F) {
7652 SelectionDAG &DAG = SDB->DAG;
7653 SDLoc dl = SDB->getCurSDLoc();
7654 const DataLayout *DL = TLI->getDataLayout();
7655 SmallVector<ISD::InputArg, 16> Ins;
7657 if (!FuncInfo->CanLowerReturn) {
7658 // Put in an sret pointer parameter before all the other parameters.
7659 SmallVector<EVT, 1> ValueVTs;
7660 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
7662 // NOTE: Assuming that a pointer will never break down to more than one VT
7663 // or one register.
7664 ISD::ArgFlagsTy Flags;
7665 Flags.setSRet();
7666 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7667 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true, 0, 0);
7668 Ins.push_back(RetArg);
7669 }
7671 // Set up the incoming argument description vector.
7672 unsigned Idx = 1;
7673 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7674 I != E; ++I, ++Idx) {
7675 SmallVector<EVT, 4> ValueVTs;
7676 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7677 bool isArgValueUsed = !I->use_empty();
7678 unsigned PartBase = 0;
7679 Type *FinalType = I->getType();
7680 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7681 FinalType = cast<PointerType>(FinalType)->getElementType();
7682 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
7683 FinalType, F.getCallingConv(), F.isVarArg());
7684 for (unsigned Value = 0, NumValues = ValueVTs.size();
7685 Value != NumValues; ++Value) {
7686 EVT VT = ValueVTs[Value];
7687 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7688 ISD::ArgFlagsTy Flags;
7689 unsigned OriginalAlignment = DL->getABITypeAlignment(ArgTy);
7691 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7692 Flags.setZExt();
7693 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7694 Flags.setSExt();
7695 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7696 Flags.setInReg();
7697 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7698 Flags.setSRet();
7699 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7700 Flags.setByVal();
7701 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7702 Flags.setInAlloca();
7703 // Set the byval flag for CCAssignFn callbacks that don't know about
7704 // inalloca. This way we can know how many bytes we should've allocated
7705 // and how many bytes a callee cleanup function will pop. If we port
7706 // inalloca to more targets, we'll have to add custom inalloca handling
7707 // in the various CC lowering callbacks.
7708 Flags.setByVal();
7709 }
7710 if (Flags.isByVal() || Flags.isInAlloca()) {
7711 PointerType *Ty = cast<PointerType>(I->getType());
7712 Type *ElementTy = Ty->getElementType();
7713 Flags.setByValSize(DL->getTypeAllocSize(ElementTy));
7714 // For ByVal, alignment should be passed from FE. BE will guess if
7715 // this info is not there but there are cases it cannot get right.
7716 unsigned FrameAlign;
7717 if (F.getParamAlignment(Idx))
7718 FrameAlign = F.getParamAlignment(Idx);
7719 else
7720 FrameAlign = TLI->getByValTypeAlignment(ElementTy);
7721 Flags.setByValAlign(FrameAlign);
7722 }
7723 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7724 Flags.setNest();
7725 if (NeedsRegBlock) {
7726 Flags.setInConsecutiveRegs();
7727 if (Value == NumValues - 1)
7728 Flags.setInConsecutiveRegsLast();
7729 }
7730 Flags.setOrigAlign(OriginalAlignment);
7732 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7733 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7734 for (unsigned i = 0; i != NumRegs; ++i) {
7735 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7736 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7737 if (NumRegs > 1 && i == 0)
7738 MyFlags.Flags.setSplit();
7739 // if it isn't first piece, alignment must be 1
7740 else if (i > 0)
7741 MyFlags.Flags.setOrigAlign(1);
7742 Ins.push_back(MyFlags);
7743 }
7744 PartBase += VT.getStoreSize();
7745 }
7746 }
7748 // Call the target to set up the argument values.
7749 SmallVector<SDValue, 8> InVals;
7750 SDValue NewRoot = TLI->LowerFormalArguments(
7751 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
7753 // Verify that the target's LowerFormalArguments behaved as expected.
7754 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7755 "LowerFormalArguments didn't return a valid chain!");
7756 assert(InVals.size() == Ins.size() &&
7757 "LowerFormalArguments didn't emit the correct number of values!");
7758 DEBUG({
7759 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7760 assert(InVals[i].getNode() &&
7761 "LowerFormalArguments emitted a null value!");
7762 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7763 "LowerFormalArguments emitted a value with the wrong type!");
7764 }
7765 });
7767 // Update the DAG with the new chain value resulting from argument lowering.
7768 DAG.setRoot(NewRoot);
7770 // Set up the argument values.
7771 unsigned i = 0;
7772 Idx = 1;
7773 if (!FuncInfo->CanLowerReturn) {
7774 // Create a virtual register for the sret pointer, and put in a copy
7775 // from the sret argument into it.
7776 SmallVector<EVT, 1> ValueVTs;
7777 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
7778 MVT VT = ValueVTs[0].getSimpleVT();
7779 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7780 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7781 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7782 RegVT, VT, nullptr, AssertOp);
7784 MachineFunction& MF = SDB->DAG.getMachineFunction();
7785 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7786 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7787 FuncInfo->DemoteRegister = SRetReg;
7788 NewRoot =
7789 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
7790 DAG.setRoot(NewRoot);
7792 // i indexes lowered arguments. Bump it past the hidden sret argument.
7793 // Idx indexes LLVM arguments. Don't touch it.
7794 ++i;
7795 }
7797 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7798 ++I, ++Idx) {
7799 SmallVector<SDValue, 4> ArgValues;
7800 SmallVector<EVT, 4> ValueVTs;
7801 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7802 unsigned NumValues = ValueVTs.size();
7804 // If this argument is unused then remember its value. It is used to generate
7805 // debugging information.
7806 if (I->use_empty() && NumValues) {
7807 SDB->setUnusedArgValue(I, InVals[i]);
7809 // Also remember any frame index for use in FastISel.
7810 if (FrameIndexSDNode *FI =
7811 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7812 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7813 }
7815 for (unsigned Val = 0; Val != NumValues; ++Val) {
7816 EVT VT = ValueVTs[Val];
7817 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7818 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7820 if (!I->use_empty()) {
7821 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7822 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7823 AssertOp = ISD::AssertSext;
7824 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7825 AssertOp = ISD::AssertZext;
7827 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7828 NumParts, PartVT, VT,
7829 nullptr, AssertOp));
7830 }
7832 i += NumParts;
7833 }
7835 // We don't need to do anything else for unused arguments.
7836 if (ArgValues.empty())
7837 continue;
7839 // Note down frame index.
7840 if (FrameIndexSDNode *FI =
7841 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7842 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7844 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7845 SDB->getCurSDLoc());
7847 SDB->setValue(I, Res);
7848 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7849 if (LoadSDNode *LNode =
7850 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7851 if (FrameIndexSDNode *FI =
7852 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7853 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7854 }
7856 // If this argument is live outside of the entry block, insert a copy from
7857 // wherever we got it to the vreg that other BB's will reference it as.
7858 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7859 // If we can, though, try to skip creating an unnecessary vreg.
7860 // FIXME: This isn't very clean... it would be nice to make this more
7861 // general. It's also subtly incompatible with the hacks FastISel
7862 // uses with vregs.
7863 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7864 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7865 FuncInfo->ValueMap[I] = Reg;
7866 continue;
7867 }
7868 }
7869 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
7870 FuncInfo->InitializeRegForValue(I);
7871 SDB->CopyToExportRegsIfNeeded(I);
7872 }
7873 }
7875 assert(i == InVals.size() && "Argument register count mismatch!");
7877 // Finally, if the target has anything special to do, allow it to do so.
7878 // FIXME: this should insert code into the DAG!
7879 EmitFunctionEntryCode();
7880 }
7882 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7883 /// ensure constants are generated when needed. Remember the virtual registers
7884 /// that need to be added to the Machine PHI nodes as input. We cannot just
7885 /// directly add them, because expansion might result in multiple MBB's for one
7886 /// BB. As such, the start of the BB might correspond to a different MBB than
7887 /// the end.
7888 ///
7889 void
7890 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7891 const TerminatorInst *TI = LLVMBB->getTerminator();
7893 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7895 // Check successor nodes' PHI nodes that expect a constant to be available
7896 // from this block.
7897 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7898 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7899 if (!isa<PHINode>(SuccBB->begin())) continue;
7900 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7902 // If this terminator has multiple identical successors (common for
7903 // switches), only handle each succ once.
7904 if (!SuccsHandled.insert(SuccMBB).second)
7905 continue;
7907 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7909 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7910 // nodes and Machine PHI nodes, but the incoming operands have not been
7911 // emitted yet.
7912 for (BasicBlock::const_iterator I = SuccBB->begin();
7913 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7914 // Ignore dead phi's.
7915 if (PN->use_empty()) continue;
7917 // Skip empty types
7918 if (PN->getType()->isEmptyTy())
7919 continue;
7921 unsigned Reg;
7922 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7924 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7925 unsigned &RegOut = ConstantsOut[C];
7926 if (RegOut == 0) {
7927 RegOut = FuncInfo.CreateRegs(C->getType());
7928 CopyValueToVirtualRegister(C, RegOut);
7929 }
7930 Reg = RegOut;
7931 } else {
7932 DenseMap<const Value *, unsigned>::iterator I =
7933 FuncInfo.ValueMap.find(PHIOp);
7934 if (I != FuncInfo.ValueMap.end())
7935 Reg = I->second;
7936 else {
7937 assert(isa<AllocaInst>(PHIOp) &&
7938 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7939 "Didn't codegen value into a register!??");
7940 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7941 CopyValueToVirtualRegister(PHIOp, Reg);
7942 }
7943 }
7945 // Remember that this register needs to added to the machine PHI node as
7946 // the input for this MBB.
7947 SmallVector<EVT, 4> ValueVTs;
7948 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7949 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
7950 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7951 EVT VT = ValueVTs[vti];
7952 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
7953 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7954 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7955 Reg += NumRegisters;
7956 }
7957 }
7958 }
7960 ConstantsOut.clear();
7961 }
7963 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7964 /// is 0.
7965 MachineBasicBlock *
7966 SelectionDAGBuilder::StackProtectorDescriptor::
7967 AddSuccessorMBB(const BasicBlock *BB,
7968 MachineBasicBlock *ParentMBB,
7969 bool IsLikely,
7970 MachineBasicBlock *SuccMBB) {
7971 // If SuccBB has not been created yet, create it.
7972 if (!SuccMBB) {
7973 MachineFunction *MF = ParentMBB->getParent();
7974 MachineFunction::iterator BBI = ParentMBB;
7975 SuccMBB = MF->CreateMachineBasicBlock(BB);
7976 MF->insert(++BBI, SuccMBB);
7977 }
7978 // Add it as a successor of ParentMBB.
7979 ParentMBB->addSuccessor(
7980 SuccMBB, BranchProbabilityInfo::getBranchWeightStackProtector(IsLikely));
7981 return SuccMBB;
7982 }