1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
11 //
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/Analysis/ConstantFolding.h"
22 #include "llvm/Analysis/ValueTracking.h"
23 #include "llvm/CodeGen/Analysis.h"
24 #include "llvm/CodeGen/FastISel.h"
25 #include "llvm/CodeGen/FunctionLoweringInfo.h"
26 #include "llvm/CodeGen/GCMetadata.h"
27 #include "llvm/CodeGen/GCStrategy.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/CodeGen/StackMaps.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DataLayout.h"
39 #include "llvm/IR/DebugInfo.h"
40 #include "llvm/IR/DerivedTypes.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/InlineAsm.h"
44 #include "llvm/IR/Instructions.h"
45 #include "llvm/IR/IntrinsicInst.h"
46 #include "llvm/IR/Intrinsics.h"
47 #include "llvm/IR/LLVMContext.h"
48 #include "llvm/IR/Module.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/TargetFrameLowering.h"
55 #include "llvm/Target/TargetInstrInfo.h"
56 #include "llvm/Target/TargetIntrinsicInfo.h"
57 #include "llvm/Target/TargetLibraryInfo.h"
58 #include "llvm/Target/TargetLowering.h"
59 #include "llvm/Target/TargetOptions.h"
60 #include "llvm/Target/TargetSelectionDAGInfo.h"
61 #include <algorithm>
62 using namespace llvm;
64 #define DEBUG_TYPE "isel"
66 /// LimitFloatPrecision - Generate low-precision inline sequences for
67 /// some float libcalls (6, 8 or 12 bits).
68 static unsigned LimitFloatPrecision;
70 static cl::opt<unsigned, true>
71 LimitFPPrecision("limit-float-precision",
72 cl::desc("Generate low-precision inline sequences "
73 "for some float libcalls"),
74 cl::location(LimitFloatPrecision),
75 cl::init(0));
77 // Limit the width of DAG chains. This is important in general to prevent
78 // prevent DAG-based analysis from blowing up. For example, alias analysis and
79 // load clustering may not complete in reasonable time. It is difficult to
80 // recognize and avoid this situation within each individual analysis, and
81 // future analyses are likely to have the same behavior. Limiting DAG width is
82 // the safe approach, and will be especially important with global DAGs.
83 //
84 // MaxParallelChains default is arbitrarily high to avoid affecting
85 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
86 // sequence over this should have been converted to llvm.memcpy by the
87 // frontend. It easy to induce this behavior with .ll code such as:
88 // %buffer = alloca [4096 x i8]
89 // %data = load [4096 x i8]* %argPtr
90 // store [4096 x i8] %data, [4096 x i8]* %buffer
91 static const unsigned MaxParallelChains = 64;
93 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
94 const SDValue *Parts, unsigned NumParts,
95 MVT PartVT, EVT ValueVT, const Value *V);
97 /// getCopyFromParts - Create a value that contains the specified legal parts
98 /// combined into the value they represent. If the parts combine to a type
99 /// larger then ValueVT then AssertOp can be used to specify whether the extra
100 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
101 /// (ISD::AssertSext).
102 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
103 const SDValue *Parts,
104 unsigned NumParts, MVT PartVT, EVT ValueVT,
105 const Value *V,
106 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
107 if (ValueVT.isVector())
108 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
109 PartVT, ValueVT, V);
111 assert(NumParts > 0 && "No parts to assemble!");
112 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
113 SDValue Val = Parts[0];
115 if (NumParts > 1) {
116 // Assemble the value from multiple parts.
117 if (ValueVT.isInteger()) {
118 unsigned PartBits = PartVT.getSizeInBits();
119 unsigned ValueBits = ValueVT.getSizeInBits();
121 // Assemble the power of 2 part.
122 unsigned RoundParts = NumParts & (NumParts - 1) ?
123 1 << Log2_32(NumParts) : NumParts;
124 unsigned RoundBits = PartBits * RoundParts;
125 EVT RoundVT = RoundBits == ValueBits ?
126 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
127 SDValue Lo, Hi;
129 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
131 if (RoundParts > 2) {
132 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
133 PartVT, HalfVT, V);
134 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
135 RoundParts / 2, PartVT, HalfVT, V);
136 } else {
137 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
138 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
139 }
141 if (TLI.isBigEndian())
142 std::swap(Lo, Hi);
144 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
146 if (RoundParts < NumParts) {
147 // Assemble the trailing non-power-of-2 part.
148 unsigned OddParts = NumParts - RoundParts;
149 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
150 Hi = getCopyFromParts(DAG, DL,
151 Parts + RoundParts, OddParts, PartVT, OddVT, V);
153 // Combine the round and odd parts.
154 Lo = Val;
155 if (TLI.isBigEndian())
156 std::swap(Lo, Hi);
157 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
158 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
159 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
160 DAG.getConstant(Lo.getValueType().getSizeInBits(),
161 TLI.getPointerTy()));
162 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
163 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
164 }
165 } else if (PartVT.isFloatingPoint()) {
166 // FP split into multiple FP parts (for ppcf128)
167 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
168 "Unexpected split");
169 SDValue Lo, Hi;
170 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
171 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
172 if (TLI.isBigEndian())
173 std::swap(Lo, Hi);
174 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
175 } else {
176 // FP split into integer parts (soft fp)
177 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
178 !PartVT.isVector() && "Unexpected split");
179 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
180 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
181 }
182 }
184 // There is now one part, held in Val. Correct it to match ValueVT.
185 EVT PartEVT = Val.getValueType();
187 if (PartEVT == ValueVT)
188 return Val;
190 if (PartEVT.isInteger() && ValueVT.isInteger()) {
191 if (ValueVT.bitsLT(PartEVT)) {
192 // For a truncate, see if we have any information to
193 // indicate whether the truncated bits will always be
194 // zero or sign-extension.
195 if (AssertOp != ISD::DELETED_NODE)
196 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
197 DAG.getValueType(ValueVT));
198 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
199 }
200 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
201 }
203 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
204 // FP_ROUND's are always exact here.
205 if (ValueVT.bitsLT(Val.getValueType()))
206 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
207 DAG.getTargetConstant(1, TLI.getPointerTy()));
209 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
210 }
212 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
213 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
215 llvm_unreachable("Unknown mismatch!");
216 }
218 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
219 const Twine &ErrMsg) {
220 const Instruction *I = dyn_cast_or_null<Instruction>(V);
221 if (!V)
222 return Ctx.emitError(ErrMsg);
224 const char *AsmError = ", possible invalid constraint for vector type";
225 if (const CallInst *CI = dyn_cast<CallInst>(I))
226 if (isa<InlineAsm>(CI->getCalledValue()))
227 return Ctx.emitError(I, ErrMsg + AsmError);
229 return Ctx.emitError(I, ErrMsg);
230 }
232 /// getCopyFromPartsVector - Create a value that contains the specified legal
233 /// parts combined into the value they represent. If the parts combine to a
234 /// type larger then ValueVT then AssertOp can be used to specify whether the
235 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
236 /// ValueVT (ISD::AssertSext).
237 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
238 const SDValue *Parts, unsigned NumParts,
239 MVT PartVT, EVT ValueVT, const Value *V) {
240 assert(ValueVT.isVector() && "Not a vector value");
241 assert(NumParts > 0 && "No parts to assemble!");
242 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
243 SDValue Val = Parts[0];
245 // Handle a multi-element vector.
246 if (NumParts > 1) {
247 EVT IntermediateVT;
248 MVT RegisterVT;
249 unsigned NumIntermediates;
250 unsigned NumRegs =
251 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
252 NumIntermediates, RegisterVT);
253 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
254 NumParts = NumRegs; // Silence a compiler warning.
255 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
256 assert(RegisterVT == Parts[0].getSimpleValueType() &&
257 "Part type doesn't match part!");
259 // Assemble the parts into intermediate operands.
260 SmallVector<SDValue, 8> Ops(NumIntermediates);
261 if (NumIntermediates == NumParts) {
262 // If the register was not expanded, truncate or copy the value,
263 // as appropriate.
264 for (unsigned i = 0; i != NumParts; ++i)
265 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
266 PartVT, IntermediateVT, V);
267 } else if (NumParts > 0) {
268 // If the intermediate type was expanded, build the intermediate
269 // operands from the parts.
270 assert(NumParts % NumIntermediates == 0 &&
271 "Must expand into a divisible number of parts!");
272 unsigned Factor = NumParts / NumIntermediates;
273 for (unsigned i = 0; i != NumIntermediates; ++i)
274 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
275 PartVT, IntermediateVT, V);
276 }
278 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
279 // intermediate operands.
280 Val = DAG.getNode(IntermediateVT.isVector() ?
281 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL,
282 ValueVT, &Ops[0], NumIntermediates);
283 }
285 // There is now one part, held in Val. Correct it to match ValueVT.
286 EVT PartEVT = Val.getValueType();
288 if (PartEVT == ValueVT)
289 return Val;
291 if (PartEVT.isVector()) {
292 // If the element type of the source/dest vectors are the same, but the
293 // parts vector has more elements than the value vector, then we have a
294 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
295 // elements we want.
296 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
297 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
298 "Cannot narrow, it would be a lossy transformation");
299 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
300 DAG.getConstant(0, TLI.getVectorIdxTy()));
301 }
303 // Vector/Vector bitcast.
304 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
305 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
307 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
308 "Cannot handle this kind of promotion");
309 // Promoted vector extract
310 bool Smaller = ValueVT.bitsLE(PartEVT);
311 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
312 DL, ValueVT, Val);
314 }
316 // Trivial bitcast if the types are the same size and the destination
317 // vector type is legal.
318 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
319 TLI.isTypeLegal(ValueVT))
320 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
322 // Handle cases such as i8 -> <1 x i1>
323 if (ValueVT.getVectorNumElements() != 1) {
324 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
325 "non-trivial scalar-to-vector conversion");
326 return DAG.getUNDEF(ValueVT);
327 }
329 if (ValueVT.getVectorNumElements() == 1 &&
330 ValueVT.getVectorElementType() != PartEVT) {
331 bool Smaller = ValueVT.bitsLE(PartEVT);
332 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
333 DL, ValueVT.getScalarType(), Val);
334 }
336 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
337 }
339 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
340 SDValue Val, SDValue *Parts, unsigned NumParts,
341 MVT PartVT, const Value *V);
343 /// getCopyToParts - Create a series of nodes that contain the specified value
344 /// split into legal parts. If the parts contain more bits than Val, then, for
345 /// integers, ExtendKind can be used to specify how to generate the extra bits.
346 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
347 SDValue Val, SDValue *Parts, unsigned NumParts,
348 MVT PartVT, const Value *V,
349 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
350 EVT ValueVT = Val.getValueType();
352 // Handle the vector case separately.
353 if (ValueVT.isVector())
354 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
356 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
357 unsigned PartBits = PartVT.getSizeInBits();
358 unsigned OrigNumParts = NumParts;
359 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
361 if (NumParts == 0)
362 return;
364 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
365 EVT PartEVT = PartVT;
366 if (PartEVT == ValueVT) {
367 assert(NumParts == 1 && "No-op copy with multiple parts!");
368 Parts[0] = Val;
369 return;
370 }
372 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
373 // If the parts cover more bits than the value has, promote the value.
374 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
375 assert(NumParts == 1 && "Do not know what to promote to!");
376 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
377 } else {
378 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
379 ValueVT.isInteger() &&
380 "Unknown mismatch!");
381 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
382 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
383 if (PartVT == MVT::x86mmx)
384 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
385 }
386 } else if (PartBits == ValueVT.getSizeInBits()) {
387 // Different types of the same size.
388 assert(NumParts == 1 && PartEVT != ValueVT);
389 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
390 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
391 // If the parts cover less bits than value has, truncate the value.
392 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
393 ValueVT.isInteger() &&
394 "Unknown mismatch!");
395 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
396 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
397 if (PartVT == MVT::x86mmx)
398 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
399 }
401 // The value may have changed - recompute ValueVT.
402 ValueVT = Val.getValueType();
403 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
404 "Failed to tile the value with PartVT!");
406 if (NumParts == 1) {
407 if (PartEVT != ValueVT)
408 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
409 "scalar-to-vector conversion failed");
411 Parts[0] = Val;
412 return;
413 }
415 // Expand the value into multiple parts.
416 if (NumParts & (NumParts - 1)) {
417 // The number of parts is not a power of 2. Split off and copy the tail.
418 assert(PartVT.isInteger() && ValueVT.isInteger() &&
419 "Do not know what to expand to!");
420 unsigned RoundParts = 1 << Log2_32(NumParts);
421 unsigned RoundBits = RoundParts * PartBits;
422 unsigned OddParts = NumParts - RoundParts;
423 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
424 DAG.getIntPtrConstant(RoundBits));
425 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
427 if (TLI.isBigEndian())
428 // The odd parts were reversed by getCopyToParts - unreverse them.
429 std::reverse(Parts + RoundParts, Parts + NumParts);
431 NumParts = RoundParts;
432 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
433 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
434 }
436 // The number of parts is a power of 2. Repeatedly bisect the value using
437 // EXTRACT_ELEMENT.
438 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
439 EVT::getIntegerVT(*DAG.getContext(),
440 ValueVT.getSizeInBits()),
441 Val);
443 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
444 for (unsigned i = 0; i < NumParts; i += StepSize) {
445 unsigned ThisBits = StepSize * PartBits / 2;
446 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
447 SDValue &Part0 = Parts[i];
448 SDValue &Part1 = Parts[i+StepSize/2];
450 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
451 ThisVT, Part0, DAG.getIntPtrConstant(1));
452 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
453 ThisVT, Part0, DAG.getIntPtrConstant(0));
455 if (ThisBits == PartBits && ThisVT != PartVT) {
456 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
457 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
458 }
459 }
460 }
462 if (TLI.isBigEndian())
463 std::reverse(Parts, Parts + OrigNumParts);
464 }
467 /// getCopyToPartsVector - Create a series of nodes that contain the specified
468 /// value split into legal parts.
469 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
470 SDValue Val, SDValue *Parts, unsigned NumParts,
471 MVT PartVT, const Value *V) {
472 EVT ValueVT = Val.getValueType();
473 assert(ValueVT.isVector() && "Not a vector");
474 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
476 if (NumParts == 1) {
477 EVT PartEVT = PartVT;
478 if (PartEVT == ValueVT) {
479 // Nothing to do.
480 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
481 // Bitconvert vector->vector case.
482 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
483 } else if (PartVT.isVector() &&
484 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
485 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
486 EVT ElementVT = PartVT.getVectorElementType();
487 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
488 // undef elements.
489 SmallVector<SDValue, 16> Ops;
490 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
491 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
492 ElementVT, Val, DAG.getConstant(i,
493 TLI.getVectorIdxTy())));
495 for (unsigned i = ValueVT.getVectorNumElements(),
496 e = PartVT.getVectorNumElements(); i != e; ++i)
497 Ops.push_back(DAG.getUNDEF(ElementVT));
499 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size());
501 // FIXME: Use CONCAT for 2x -> 4x.
503 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
504 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
505 } else if (PartVT.isVector() &&
506 PartEVT.getVectorElementType().bitsGE(
507 ValueVT.getVectorElementType()) &&
508 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
510 // Promoted vector extract
511 bool Smaller = PartEVT.bitsLE(ValueVT);
512 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
513 DL, PartVT, Val);
514 } else{
515 // Vector -> scalar conversion.
516 assert(ValueVT.getVectorNumElements() == 1 &&
517 "Only trivial vector-to-scalar conversions should get here!");
518 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
519 PartVT, Val, DAG.getConstant(0, TLI.getVectorIdxTy()));
521 bool Smaller = ValueVT.bitsLE(PartVT);
522 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
523 DL, PartVT, Val);
524 }
526 Parts[0] = Val;
527 return;
528 }
530 // Handle a multi-element vector.
531 EVT IntermediateVT;
532 MVT RegisterVT;
533 unsigned NumIntermediates;
534 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
535 IntermediateVT,
536 NumIntermediates, RegisterVT);
537 unsigned NumElements = ValueVT.getVectorNumElements();
539 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
540 NumParts = NumRegs; // Silence a compiler warning.
541 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
543 // Split the vector into intermediate operands.
544 SmallVector<SDValue, 8> Ops(NumIntermediates);
545 for (unsigned i = 0; i != NumIntermediates; ++i) {
546 if (IntermediateVT.isVector())
547 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
548 IntermediateVT, Val,
549 DAG.getConstant(i * (NumElements / NumIntermediates),
550 TLI.getVectorIdxTy()));
551 else
552 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
553 IntermediateVT, Val,
554 DAG.getConstant(i, TLI.getVectorIdxTy()));
555 }
557 // Split the intermediate operands into legal parts.
558 if (NumParts == NumIntermediates) {
559 // If the register was not expanded, promote or copy the value,
560 // as appropriate.
561 for (unsigned i = 0; i != NumParts; ++i)
562 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
563 } else if (NumParts > 0) {
564 // If the intermediate type was expanded, split each the value into
565 // legal parts.
566 assert(NumParts % NumIntermediates == 0 &&
567 "Must expand into a divisible number of parts!");
568 unsigned Factor = NumParts / NumIntermediates;
569 for (unsigned i = 0; i != NumIntermediates; ++i)
570 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
571 }
572 }
574 namespace {
575 /// RegsForValue - This struct represents the registers (physical or virtual)
576 /// that a particular set of values is assigned, and the type information
577 /// about the value. The most common situation is to represent one value at a
578 /// time, but struct or array values are handled element-wise as multiple
579 /// values. The splitting of aggregates is performed recursively, so that we
580 /// never have aggregate-typed registers. The values at this point do not
581 /// necessarily have legal types, so each value may require one or more
582 /// registers of some legal type.
583 ///
584 struct RegsForValue {
585 /// ValueVTs - The value types of the values, which may not be legal, and
586 /// may need be promoted or synthesized from one or more registers.
587 ///
588 SmallVector<EVT, 4> ValueVTs;
590 /// RegVTs - The value types of the registers. This is the same size as
591 /// ValueVTs and it records, for each value, what the type of the assigned
592 /// register or registers are. (Individual values are never synthesized
593 /// from more than one type of register.)
594 ///
595 /// With virtual registers, the contents of RegVTs is redundant with TLI's
596 /// getRegisterType member function, however when with physical registers
597 /// it is necessary to have a separate record of the types.
598 ///
599 SmallVector<MVT, 4> RegVTs;
601 /// Regs - This list holds the registers assigned to the values.
602 /// Each legal or promoted value requires one register, and each
603 /// expanded value requires multiple registers.
604 ///
605 SmallVector<unsigned, 4> Regs;
607 RegsForValue() {}
609 RegsForValue(const SmallVector<unsigned, 4> ®s,
610 MVT regvt, EVT valuevt)
611 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
613 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
614 unsigned Reg, Type *Ty) {
615 ComputeValueVTs(tli, Ty, ValueVTs);
617 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
618 EVT ValueVT = ValueVTs[Value];
619 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
620 MVT RegisterVT = tli.getRegisterType(Context, ValueVT);
621 for (unsigned i = 0; i != NumRegs; ++i)
622 Regs.push_back(Reg + i);
623 RegVTs.push_back(RegisterVT);
624 Reg += NumRegs;
625 }
626 }
628 /// append - Add the specified values to this one.
629 void append(const RegsForValue &RHS) {
630 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
631 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
632 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
633 }
635 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
636 /// this value and returns the result as a ValueVTs value. This uses
637 /// Chain/Flag as the input and updates them for the output Chain/Flag.
638 /// If the Flag pointer is NULL, no flag is used.
639 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
640 SDLoc dl,
641 SDValue &Chain, SDValue *Flag,
642 const Value *V = nullptr) const;
644 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
645 /// specified value into the registers specified by this object. This uses
646 /// Chain/Flag as the input and updates them for the output Chain/Flag.
647 /// If the Flag pointer is NULL, no flag is used.
648 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
649 SDValue &Chain, SDValue *Flag, const Value *V) const;
651 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
652 /// operand list. This adds the code marker, matching input operand index
653 /// (if applicable), and includes the number of values added into it.
654 void AddInlineAsmOperands(unsigned Kind,
655 bool HasMatching, unsigned MatchingIdx,
656 SelectionDAG &DAG,
657 std::vector<SDValue> &Ops) const;
658 };
659 }
661 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
662 /// this value and returns the result as a ValueVT value. This uses
663 /// Chain/Flag as the input and updates them for the output Chain/Flag.
664 /// If the Flag pointer is NULL, no flag is used.
665 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
666 FunctionLoweringInfo &FuncInfo,
667 SDLoc dl,
668 SDValue &Chain, SDValue *Flag,
669 const Value *V) const {
670 // A Value with type {} or [0 x %t] needs no registers.
671 if (ValueVTs.empty())
672 return SDValue();
674 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
676 // Assemble the legal parts into the final values.
677 SmallVector<SDValue, 4> Values(ValueVTs.size());
678 SmallVector<SDValue, 8> Parts;
679 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
680 // Copy the legal parts from the registers.
681 EVT ValueVT = ValueVTs[Value];
682 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
683 MVT RegisterVT = RegVTs[Value];
685 Parts.resize(NumRegs);
686 for (unsigned i = 0; i != NumRegs; ++i) {
687 SDValue P;
688 if (!Flag) {
689 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
690 } else {
691 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
692 *Flag = P.getValue(2);
693 }
695 Chain = P.getValue(1);
696 Parts[i] = P;
698 // If the source register was virtual and if we know something about it,
699 // add an assert node.
700 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
701 !RegisterVT.isInteger() || RegisterVT.isVector())
702 continue;
704 const FunctionLoweringInfo::LiveOutInfo *LOI =
705 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
706 if (!LOI)
707 continue;
709 unsigned RegSize = RegisterVT.getSizeInBits();
710 unsigned NumSignBits = LOI->NumSignBits;
711 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
713 if (NumZeroBits == RegSize) {
714 // The current value is a zero.
715 // Explicitly express that as it would be easier for
716 // optimizations to kick in.
717 Parts[i] = DAG.getConstant(0, RegisterVT);
718 continue;
719 }
721 // FIXME: We capture more information than the dag can represent. For
722 // now, just use the tightest assertzext/assertsext possible.
723 bool isSExt = true;
724 EVT FromVT(MVT::Other);
725 if (NumSignBits == RegSize)
726 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
727 else if (NumZeroBits >= RegSize-1)
728 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
729 else if (NumSignBits > RegSize-8)
730 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
731 else if (NumZeroBits >= RegSize-8)
732 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
733 else if (NumSignBits > RegSize-16)
734 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
735 else if (NumZeroBits >= RegSize-16)
736 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
737 else if (NumSignBits > RegSize-32)
738 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
739 else if (NumZeroBits >= RegSize-32)
740 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
741 else
742 continue;
744 // Add an assertion node.
745 assert(FromVT != MVT::Other);
746 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
747 RegisterVT, P, DAG.getValueType(FromVT));
748 }
750 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
751 NumRegs, RegisterVT, ValueVT, V);
752 Part += NumRegs;
753 Parts.clear();
754 }
756 return DAG.getNode(ISD::MERGE_VALUES, dl,
757 DAG.getVTList(ValueVTs),
758 &Values[0], ValueVTs.size());
759 }
761 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
762 /// specified value into the registers specified by this object. This uses
763 /// Chain/Flag as the input and updates them for the output Chain/Flag.
764 /// If the Flag pointer is NULL, no flag is used.
765 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
766 SDValue &Chain, SDValue *Flag,
767 const Value *V) const {
768 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
770 // Get the list of the values's legal parts.
771 unsigned NumRegs = Regs.size();
772 SmallVector<SDValue, 8> Parts(NumRegs);
773 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
774 EVT ValueVT = ValueVTs[Value];
775 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
776 MVT RegisterVT = RegVTs[Value];
777 ISD::NodeType ExtendKind =
778 TLI.isZExtFree(Val, RegisterVT)? ISD::ZERO_EXTEND: ISD::ANY_EXTEND;
780 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
781 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
782 Part += NumParts;
783 }
785 // Copy the parts into the registers.
786 SmallVector<SDValue, 8> Chains(NumRegs);
787 for (unsigned i = 0; i != NumRegs; ++i) {
788 SDValue Part;
789 if (!Flag) {
790 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
791 } else {
792 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
793 *Flag = Part.getValue(1);
794 }
796 Chains[i] = Part.getValue(0);
797 }
799 if (NumRegs == 1 || Flag)
800 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
801 // flagged to it. That is the CopyToReg nodes and the user are considered
802 // a single scheduling unit. If we create a TokenFactor and return it as
803 // chain, then the TokenFactor is both a predecessor (operand) of the
804 // user as well as a successor (the TF operands are flagged to the user).
805 // c1, f1 = CopyToReg
806 // c2, f2 = CopyToReg
807 // c3 = TokenFactor c1, c2
808 // ...
809 // = op c3, ..., f2
810 Chain = Chains[NumRegs-1];
811 else
812 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
813 }
815 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
816 /// operand list. This adds the code marker and includes the number of
817 /// values added into it.
818 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
819 unsigned MatchingIdx,
820 SelectionDAG &DAG,
821 std::vector<SDValue> &Ops) const {
822 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
824 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
825 if (HasMatching)
826 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
827 else if (!Regs.empty() &&
828 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
829 // Put the register class of the virtual registers in the flag word. That
830 // way, later passes can recompute register class constraints for inline
831 // assembly as well as normal instructions.
832 // Don't do this for tied operands that can use the regclass information
833 // from the def.
834 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
835 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
836 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
837 }
839 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
840 Ops.push_back(Res);
842 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
843 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
844 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
845 MVT RegisterVT = RegVTs[Value];
846 for (unsigned i = 0; i != NumRegs; ++i) {
847 assert(Reg < Regs.size() && "Mismatch in # registers expected");
848 unsigned TheReg = Regs[Reg++];
849 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
851 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
852 // If we clobbered the stack pointer, MFI should know about it.
853 assert(DAG.getMachineFunction().getFrameInfo()->
854 hasInlineAsmWithSPAdjust());
855 }
856 }
857 }
858 }
860 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
861 const TargetLibraryInfo *li) {
862 AA = &aa;
863 GFI = gfi;
864 LibInfo = li;
865 DL = DAG.getTarget().getDataLayout();
866 Context = DAG.getContext();
867 LPadToCallSiteMap.clear();
868 }
870 /// clear - Clear out the current SelectionDAG and the associated
871 /// state and prepare this SelectionDAGBuilder object to be used
872 /// for a new block. This doesn't clear out information about
873 /// additional blocks that are needed to complete switch lowering
874 /// or PHI node updating; that information is cleared out as it is
875 /// consumed.
876 void SelectionDAGBuilder::clear() {
877 NodeMap.clear();
878 UnusedArgNodeMap.clear();
879 PendingLoads.clear();
880 PendingExports.clear();
881 CurInst = nullptr;
882 HasTailCall = false;
883 SDNodeOrder = LowestSDNodeOrder;
884 }
886 /// clearDanglingDebugInfo - Clear the dangling debug information
887 /// map. This function is separated from the clear so that debug
888 /// information that is dangling in a basic block can be properly
889 /// resolved in a different basic block. This allows the
890 /// SelectionDAG to resolve dangling debug information attached
891 /// to PHI nodes.
892 void SelectionDAGBuilder::clearDanglingDebugInfo() {
893 DanglingDebugInfoMap.clear();
894 }
896 /// getRoot - Return the current virtual root of the Selection DAG,
897 /// flushing any PendingLoad items. This must be done before emitting
898 /// a store or any other node that may need to be ordered after any
899 /// prior load instructions.
900 ///
901 SDValue SelectionDAGBuilder::getRoot() {
902 if (PendingLoads.empty())
903 return DAG.getRoot();
905 if (PendingLoads.size() == 1) {
906 SDValue Root = PendingLoads[0];
907 DAG.setRoot(Root);
908 PendingLoads.clear();
909 return Root;
910 }
912 // Otherwise, we have to make a token factor node.
913 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
914 &PendingLoads[0], PendingLoads.size());
915 PendingLoads.clear();
916 DAG.setRoot(Root);
917 return Root;
918 }
920 /// getControlRoot - Similar to getRoot, but instead of flushing all the
921 /// PendingLoad items, flush all the PendingExports items. It is necessary
922 /// to do this before emitting a terminator instruction.
923 ///
924 SDValue SelectionDAGBuilder::getControlRoot() {
925 SDValue Root = DAG.getRoot();
927 if (PendingExports.empty())
928 return Root;
930 // Turn all of the CopyToReg chains into one factored node.
931 if (Root.getOpcode() != ISD::EntryToken) {
932 unsigned i = 0, e = PendingExports.size();
933 for (; i != e; ++i) {
934 assert(PendingExports[i].getNode()->getNumOperands() > 1);
935 if (PendingExports[i].getNode()->getOperand(0) == Root)
936 break; // Don't add the root if we already indirectly depend on it.
937 }
939 if (i == e)
940 PendingExports.push_back(Root);
941 }
943 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
944 &PendingExports[0],
945 PendingExports.size());
946 PendingExports.clear();
947 DAG.setRoot(Root);
948 return Root;
949 }
951 void SelectionDAGBuilder::visit(const Instruction &I) {
952 // Set up outgoing PHI node register values before emitting the terminator.
953 if (isa<TerminatorInst>(&I))
954 HandlePHINodesInSuccessorBlocks(I.getParent());
956 ++SDNodeOrder;
958 CurInst = &I;
960 visit(I.getOpcode(), I);
962 if (!isa<TerminatorInst>(&I) && !HasTailCall)
963 CopyToExportRegsIfNeeded(&I);
965 CurInst = nullptr;
966 }
968 void SelectionDAGBuilder::visitPHI(const PHINode &) {
969 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
970 }
972 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
973 // Note: this doesn't use InstVisitor, because it has to work with
974 // ConstantExpr's in addition to instructions.
975 switch (Opcode) {
976 default: llvm_unreachable("Unknown instruction type encountered!");
977 // Build the switch statement using the Instruction.def file.
978 #define HANDLE_INST(NUM, OPCODE, CLASS) \
979 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
980 #include "llvm/IR/Instruction.def"
981 }
982 }
984 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
985 // generate the debug data structures now that we've seen its definition.
986 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
987 SDValue Val) {
988 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
989 if (DDI.getDI()) {
990 const DbgValueInst *DI = DDI.getDI();
991 DebugLoc dl = DDI.getdl();
992 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
993 MDNode *Variable = DI->getVariable();
994 uint64_t Offset = DI->getOffset();
995 // A dbg.value for an alloca is always indirect.
996 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
997 SDDbgValue *SDV;
998 if (Val.getNode()) {
999 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, IsIndirect, Val)) {
1000 SDV = DAG.getDbgValue(Variable, Val.getNode(),
1001 Val.getResNo(), IsIndirect,
1002 Offset, dl, DbgSDNodeOrder);
1003 DAG.AddDbgValue(SDV, Val.getNode(), false);
1004 }
1005 } else
1006 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1007 DanglingDebugInfoMap[V] = DanglingDebugInfo();
1008 }
1009 }
1011 /// getValue - Return an SDValue for the given Value.
1012 SDValue SelectionDAGBuilder::getValue(const Value *V) {
1013 // If we already have an SDValue for this value, use it. It's important
1014 // to do this first, so that we don't create a CopyFromReg if we already
1015 // have a regular SDValue.
1016 SDValue &N = NodeMap[V];
1017 if (N.getNode()) return N;
1019 // If there's a virtual register allocated and initialized for this
1020 // value, use it.
1021 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
1022 if (It != FuncInfo.ValueMap.end()) {
1023 unsigned InReg = It->second;
1024 RegsForValue RFV(*DAG.getContext(), *TM.getTargetLowering(),
1025 InReg, V->getType());
1026 SDValue Chain = DAG.getEntryNode();
1027 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1028 resolveDanglingDebugInfo(V, N);
1029 return N;
1030 }
1032 // Otherwise create a new SDValue and remember it.
1033 SDValue Val = getValueImpl(V);
1034 NodeMap[V] = Val;
1035 resolveDanglingDebugInfo(V, Val);
1036 return Val;
1037 }
1039 /// getNonRegisterValue - Return an SDValue for the given Value, but
1040 /// don't look in FuncInfo.ValueMap for a virtual register.
1041 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1042 // If we already have an SDValue for this value, use it.
1043 SDValue &N = NodeMap[V];
1044 if (N.getNode()) return N;
1046 // Otherwise create a new SDValue and remember it.
1047 SDValue Val = getValueImpl(V);
1048 NodeMap[V] = Val;
1049 resolveDanglingDebugInfo(V, Val);
1050 return Val;
1051 }
1053 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1054 /// Create an SDValue for the given value.
1055 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1056 const TargetLowering *TLI = TM.getTargetLowering();
1058 if (const Constant *C = dyn_cast<Constant>(V)) {
1059 EVT VT = TLI->getValueType(V->getType(), true);
1061 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1062 return DAG.getConstant(*CI, VT);
1064 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1065 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1067 if (isa<ConstantPointerNull>(C)) {
1068 unsigned AS = V->getType()->getPointerAddressSpace();
1069 return DAG.getConstant(0, TLI->getPointerTy(AS));
1070 }
1072 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1073 return DAG.getConstantFP(*CFP, VT);
1075 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1076 return DAG.getUNDEF(VT);
1078 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1079 visit(CE->getOpcode(), *CE);
1080 SDValue N1 = NodeMap[V];
1081 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1082 return N1;
1083 }
1085 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1086 SmallVector<SDValue, 4> Constants;
1087 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1088 OI != OE; ++OI) {
1089 SDNode *Val = getValue(*OI).getNode();
1090 // If the operand is an empty aggregate, there are no values.
1091 if (!Val) continue;
1092 // Add each leaf value from the operand to the Constants list
1093 // to form a flattened list of all the values.
1094 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1095 Constants.push_back(SDValue(Val, i));
1096 }
1098 return DAG.getMergeValues(&Constants[0], Constants.size(),
1099 getCurSDLoc());
1100 }
1102 if (const ConstantDataSequential *CDS =
1103 dyn_cast<ConstantDataSequential>(C)) {
1104 SmallVector<SDValue, 4> Ops;
1105 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1106 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1107 // Add each leaf value from the operand to the Constants list
1108 // to form a flattened list of all the values.
1109 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1110 Ops.push_back(SDValue(Val, i));
1111 }
1113 if (isa<ArrayType>(CDS->getType()))
1114 return DAG.getMergeValues(&Ops[0], Ops.size(), getCurSDLoc());
1115 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1116 VT, &Ops[0], Ops.size());
1117 }
1119 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1120 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1121 "Unknown struct or array constant!");
1123 SmallVector<EVT, 4> ValueVTs;
1124 ComputeValueVTs(*TLI, C->getType(), ValueVTs);
1125 unsigned NumElts = ValueVTs.size();
1126 if (NumElts == 0)
1127 return SDValue(); // empty struct
1128 SmallVector<SDValue, 4> Constants(NumElts);
1129 for (unsigned i = 0; i != NumElts; ++i) {
1130 EVT EltVT = ValueVTs[i];
1131 if (isa<UndefValue>(C))
1132 Constants[i] = DAG.getUNDEF(EltVT);
1133 else if (EltVT.isFloatingPoint())
1134 Constants[i] = DAG.getConstantFP(0, EltVT);
1135 else
1136 Constants[i] = DAG.getConstant(0, EltVT);
1137 }
1139 return DAG.getMergeValues(&Constants[0], NumElts,
1140 getCurSDLoc());
1141 }
1143 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1144 return DAG.getBlockAddress(BA, VT);
1146 VectorType *VecTy = cast<VectorType>(V->getType());
1147 unsigned NumElements = VecTy->getNumElements();
1149 // Now that we know the number and type of the elements, get that number of
1150 // elements into the Ops array based on what kind of constant it is.
1151 SmallVector<SDValue, 16> Ops;
1152 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1153 for (unsigned i = 0; i != NumElements; ++i)
1154 Ops.push_back(getValue(CV->getOperand(i)));
1155 } else {
1156 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1157 EVT EltVT = TLI->getValueType(VecTy->getElementType());
1159 SDValue Op;
1160 if (EltVT.isFloatingPoint())
1161 Op = DAG.getConstantFP(0, EltVT);
1162 else
1163 Op = DAG.getConstant(0, EltVT);
1164 Ops.assign(NumElements, Op);
1165 }
1167 // Create a BUILD_VECTOR node.
1168 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1169 VT, &Ops[0], Ops.size());
1170 }
1172 // If this is a static alloca, generate it as the frameindex instead of
1173 // computation.
1174 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1175 DenseMap<const AllocaInst*, int>::iterator SI =
1176 FuncInfo.StaticAllocaMap.find(AI);
1177 if (SI != FuncInfo.StaticAllocaMap.end())
1178 return DAG.getFrameIndex(SI->second, TLI->getPointerTy());
1179 }
1181 // If this is an instruction which fast-isel has deferred, select it now.
1182 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1183 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1184 RegsForValue RFV(*DAG.getContext(), *TLI, InReg, Inst->getType());
1185 SDValue Chain = DAG.getEntryNode();
1186 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1187 }
1189 llvm_unreachable("Can't get register for value!");
1190 }
1192 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1193 const TargetLowering *TLI = TM.getTargetLowering();
1194 SDValue Chain = getControlRoot();
1195 SmallVector<ISD::OutputArg, 8> Outs;
1196 SmallVector<SDValue, 8> OutVals;
1198 if (!FuncInfo.CanLowerReturn) {
1199 unsigned DemoteReg = FuncInfo.DemoteRegister;
1200 const Function *F = I.getParent()->getParent();
1202 // Emit a store of the return value through the virtual register.
1203 // Leave Outs empty so that LowerReturn won't try to load return
1204 // registers the usual way.
1205 SmallVector<EVT, 1> PtrValueVTs;
1206 ComputeValueVTs(*TLI, PointerType::getUnqual(F->getReturnType()),
1207 PtrValueVTs);
1209 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1210 SDValue RetOp = getValue(I.getOperand(0));
1212 SmallVector<EVT, 4> ValueVTs;
1213 SmallVector<uint64_t, 4> Offsets;
1214 ComputeValueVTs(*TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1215 unsigned NumValues = ValueVTs.size();
1217 SmallVector<SDValue, 4> Chains(NumValues);
1218 for (unsigned i = 0; i != NumValues; ++i) {
1219 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1220 RetPtr.getValueType(), RetPtr,
1221 DAG.getIntPtrConstant(Offsets[i]));
1222 Chains[i] =
1223 DAG.getStore(Chain, getCurSDLoc(),
1224 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1225 // FIXME: better loc info would be nice.
1226 Add, MachinePointerInfo(), false, false, 0);
1227 }
1229 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1230 MVT::Other, &Chains[0], NumValues);
1231 } else if (I.getNumOperands() != 0) {
1232 SmallVector<EVT, 4> ValueVTs;
1233 ComputeValueVTs(*TLI, I.getOperand(0)->getType(), ValueVTs);
1234 unsigned NumValues = ValueVTs.size();
1235 if (NumValues) {
1236 SDValue RetOp = getValue(I.getOperand(0));
1237 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1238 EVT VT = ValueVTs[j];
1240 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1242 const Function *F = I.getParent()->getParent();
1243 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1244 Attribute::SExt))
1245 ExtendKind = ISD::SIGN_EXTEND;
1246 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1247 Attribute::ZExt))
1248 ExtendKind = ISD::ZERO_EXTEND;
1250 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1251 VT = TLI->getTypeForExtArgOrReturn(VT.getSimpleVT(), ExtendKind);
1253 unsigned NumParts = TLI->getNumRegisters(*DAG.getContext(), VT);
1254 MVT PartVT = TLI->getRegisterType(*DAG.getContext(), VT);
1255 SmallVector<SDValue, 4> Parts(NumParts);
1256 getCopyToParts(DAG, getCurSDLoc(),
1257 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1258 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1260 // 'inreg' on function refers to return value
1261 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1262 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1263 Attribute::InReg))
1264 Flags.setInReg();
1266 // Propagate extension type if any
1267 if (ExtendKind == ISD::SIGN_EXTEND)
1268 Flags.setSExt();
1269 else if (ExtendKind == ISD::ZERO_EXTEND)
1270 Flags.setZExt();
1272 for (unsigned i = 0; i < NumParts; ++i) {
1273 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1274 VT, /*isfixed=*/true, 0, 0));
1275 OutVals.push_back(Parts[i]);
1276 }
1277 }
1278 }
1279 }
1281 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1282 CallingConv::ID CallConv =
1283 DAG.getMachineFunction().getFunction()->getCallingConv();
1284 Chain = TM.getTargetLowering()->LowerReturn(Chain, CallConv, isVarArg,
1285 Outs, OutVals, getCurSDLoc(),
1286 DAG);
1288 // Verify that the target's LowerReturn behaved as expected.
1289 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1290 "LowerReturn didn't return a valid chain!");
1292 // Update the DAG with the new chain value resulting from return lowering.
1293 DAG.setRoot(Chain);
1294 }
1296 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1297 /// created for it, emit nodes to copy the value into the virtual
1298 /// registers.
1299 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1300 // Skip empty types
1301 if (V->getType()->isEmptyTy())
1302 return;
1304 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1305 if (VMI != FuncInfo.ValueMap.end()) {
1306 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1307 CopyValueToVirtualRegister(V, VMI->second);
1308 }
1309 }
1311 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1312 /// the current basic block, add it to ValueMap now so that we'll get a
1313 /// CopyTo/FromReg.
1314 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1315 // No need to export constants.
1316 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1318 // Already exported?
1319 if (FuncInfo.isExportedInst(V)) return;
1321 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1322 CopyValueToVirtualRegister(V, Reg);
1323 }
1325 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1326 const BasicBlock *FromBB) {
1327 // The operands of the setcc have to be in this block. We don't know
1328 // how to export them from some other block.
1329 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1330 // Can export from current BB.
1331 if (VI->getParent() == FromBB)
1332 return true;
1334 // Is already exported, noop.
1335 return FuncInfo.isExportedInst(V);
1336 }
1338 // If this is an argument, we can export it if the BB is the entry block or
1339 // if it is already exported.
1340 if (isa<Argument>(V)) {
1341 if (FromBB == &FromBB->getParent()->getEntryBlock())
1342 return true;
1344 // Otherwise, can only export this if it is already exported.
1345 return FuncInfo.isExportedInst(V);
1346 }
1348 // Otherwise, constants can always be exported.
1349 return true;
1350 }
1352 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1353 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1354 const MachineBasicBlock *Dst) const {
1355 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1356 if (!BPI)
1357 return 0;
1358 const BasicBlock *SrcBB = Src->getBasicBlock();
1359 const BasicBlock *DstBB = Dst->getBasicBlock();
1360 return BPI->getEdgeWeight(SrcBB, DstBB);
1361 }
1363 void SelectionDAGBuilder::
1364 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1365 uint32_t Weight /* = 0 */) {
1366 if (!Weight)
1367 Weight = getEdgeWeight(Src, Dst);
1368 Src->addSuccessor(Dst, Weight);
1369 }
1372 static bool InBlock(const Value *V, const BasicBlock *BB) {
1373 if (const Instruction *I = dyn_cast<Instruction>(V))
1374 return I->getParent() == BB;
1375 return true;
1376 }
1378 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1379 /// This function emits a branch and is used at the leaves of an OR or an
1380 /// AND operator tree.
1381 ///
1382 void
1383 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1384 MachineBasicBlock *TBB,
1385 MachineBasicBlock *FBB,
1386 MachineBasicBlock *CurBB,
1387 MachineBasicBlock *SwitchBB,
1388 uint32_t TWeight,
1389 uint32_t FWeight) {
1390 const BasicBlock *BB = CurBB->getBasicBlock();
1392 // If the leaf of the tree is a comparison, merge the condition into
1393 // the caseblock.
1394 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1395 // The operands of the cmp have to be in this block. We don't know
1396 // how to export them from some other block. If this is the first block
1397 // of the sequence, no exporting is needed.
1398 if (CurBB == SwitchBB ||
1399 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1400 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1401 ISD::CondCode Condition;
1402 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1403 Condition = getICmpCondCode(IC->getPredicate());
1404 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1405 Condition = getFCmpCondCode(FC->getPredicate());
1406 if (TM.Options.NoNaNsFPMath)
1407 Condition = getFCmpCodeWithoutNaN(Condition);
1408 } else {
1409 Condition = ISD::SETEQ; // silence warning.
1410 llvm_unreachable("Unknown compare instruction");
1411 }
1413 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1414 TBB, FBB, CurBB, TWeight, FWeight);
1415 SwitchCases.push_back(CB);
1416 return;
1417 }
1418 }
1420 // Create a CaseBlock record representing this branch.
1421 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1422 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1423 SwitchCases.push_back(CB);
1424 }
1426 /// Scale down both weights to fit into uint32_t.
1427 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1428 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1429 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1430 NewTrue = NewTrue / Scale;
1431 NewFalse = NewFalse / Scale;
1432 }
1434 /// FindMergedConditions - If Cond is an expression like
1435 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1436 MachineBasicBlock *TBB,
1437 MachineBasicBlock *FBB,
1438 MachineBasicBlock *CurBB,
1439 MachineBasicBlock *SwitchBB,
1440 unsigned Opc, uint32_t TWeight,
1441 uint32_t FWeight) {
1442 // If this node is not part of the or/and tree, emit it as a branch.
1443 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1444 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1445 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1446 BOp->getParent() != CurBB->getBasicBlock() ||
1447 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1448 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1449 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1450 TWeight, FWeight);
1451 return;
1452 }
1454 // Create TmpBB after CurBB.
1455 MachineFunction::iterator BBI = CurBB;
1456 MachineFunction &MF = DAG.getMachineFunction();
1457 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1458 CurBB->getParent()->insert(++BBI, TmpBB);
1460 if (Opc == Instruction::Or) {
1461 // Codegen X | Y as:
1462 // BB1:
1463 // jmp_if_X TBB
1464 // jmp TmpBB
1465 // TmpBB:
1466 // jmp_if_Y TBB
1467 // jmp FBB
1468 //
1470 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1471 // The requirement is that
1472 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1473 // = TrueProb for orignal BB.
1474 // Assuming the orignal weights are A and B, one choice is to set BB1's
1475 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1476 // assumes that
1477 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1478 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1479 // TmpBB, but the math is more complicated.
1481 uint64_t NewTrueWeight = TWeight;
1482 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1483 ScaleWeights(NewTrueWeight, NewFalseWeight);
1484 // Emit the LHS condition.
1485 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1486 NewTrueWeight, NewFalseWeight);
1488 NewTrueWeight = TWeight;
1489 NewFalseWeight = 2 * (uint64_t)FWeight;
1490 ScaleWeights(NewTrueWeight, NewFalseWeight);
1491 // Emit the RHS condition into TmpBB.
1492 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1493 NewTrueWeight, NewFalseWeight);
1494 } else {
1495 assert(Opc == Instruction::And && "Unknown merge op!");
1496 // Codegen X & Y as:
1497 // BB1:
1498 // jmp_if_X TmpBB
1499 // jmp FBB
1500 // TmpBB:
1501 // jmp_if_Y TBB
1502 // jmp FBB
1503 //
1504 // This requires creation of TmpBB after CurBB.
1506 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1507 // The requirement is that
1508 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1509 // = FalseProb for orignal BB.
1510 // Assuming the orignal weights are A and B, one choice is to set BB1's
1511 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1512 // assumes that
1513 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1515 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1516 uint64_t NewFalseWeight = FWeight;
1517 ScaleWeights(NewTrueWeight, NewFalseWeight);
1518 // Emit the LHS condition.
1519 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1520 NewTrueWeight, NewFalseWeight);
1522 NewTrueWeight = 2 * (uint64_t)TWeight;
1523 NewFalseWeight = FWeight;
1524 ScaleWeights(NewTrueWeight, NewFalseWeight);
1525 // Emit the RHS condition into TmpBB.
1526 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1527 NewTrueWeight, NewFalseWeight);
1528 }
1529 }
1531 /// If the set of cases should be emitted as a series of branches, return true.
1532 /// If we should emit this as a bunch of and/or'd together conditions, return
1533 /// false.
1534 bool
1535 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1536 if (Cases.size() != 2) return true;
1538 // If this is two comparisons of the same values or'd or and'd together, they
1539 // will get folded into a single comparison, so don't emit two blocks.
1540 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1541 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1542 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1543 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1544 return false;
1545 }
1547 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1548 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1549 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1550 Cases[0].CC == Cases[1].CC &&
1551 isa<Constant>(Cases[0].CmpRHS) &&
1552 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1553 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1554 return false;
1555 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1556 return false;
1557 }
1559 return true;
1560 }
1562 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1563 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1565 // Update machine-CFG edges.
1566 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1568 // Figure out which block is immediately after the current one.
1569 MachineBasicBlock *NextBlock = nullptr;
1570 MachineFunction::iterator BBI = BrMBB;
1571 if (++BBI != FuncInfo.MF->end())
1572 NextBlock = BBI;
1574 if (I.isUnconditional()) {
1575 // Update machine-CFG edges.
1576 BrMBB->addSuccessor(Succ0MBB);
1578 // If this is not a fall-through branch or optimizations are switched off,
1579 // emit the branch.
1580 if (Succ0MBB != NextBlock || TM.getOptLevel() == CodeGenOpt::None)
1581 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1582 MVT::Other, getControlRoot(),
1583 DAG.getBasicBlock(Succ0MBB)));
1585 return;
1586 }
1588 // If this condition is one of the special cases we handle, do special stuff
1589 // now.
1590 const Value *CondVal = I.getCondition();
1591 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1593 // If this is a series of conditions that are or'd or and'd together, emit
1594 // this as a sequence of branches instead of setcc's with and/or operations.
1595 // As long as jumps are not expensive, this should improve performance.
1596 // For example, instead of something like:
1597 // cmp A, B
1598 // C = seteq
1599 // cmp D, E
1600 // F = setle
1601 // or C, F
1602 // jnz foo
1603 // Emit:
1604 // cmp A, B
1605 // je foo
1606 // cmp D, E
1607 // jle foo
1608 //
1609 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1610 if (!TM.getTargetLowering()->isJumpExpensive() &&
1611 BOp->hasOneUse() &&
1612 (BOp->getOpcode() == Instruction::And ||
1613 BOp->getOpcode() == Instruction::Or)) {
1614 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1615 BOp->getOpcode(), getEdgeWeight(BrMBB, Succ0MBB),
1616 getEdgeWeight(BrMBB, Succ1MBB));
1617 // If the compares in later blocks need to use values not currently
1618 // exported from this block, export them now. This block should always
1619 // be the first entry.
1620 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1622 // Allow some cases to be rejected.
1623 if (ShouldEmitAsBranches(SwitchCases)) {
1624 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1625 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1626 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1627 }
1629 // Emit the branch for this block.
1630 visitSwitchCase(SwitchCases[0], BrMBB);
1631 SwitchCases.erase(SwitchCases.begin());
1632 return;
1633 }
1635 // Okay, we decided not to do this, remove any inserted MBB's and clear
1636 // SwitchCases.
1637 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1638 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1640 SwitchCases.clear();
1641 }
1642 }
1644 // Create a CaseBlock record representing this branch.
1645 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1646 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1648 // Use visitSwitchCase to actually insert the fast branch sequence for this
1649 // cond branch.
1650 visitSwitchCase(CB, BrMBB);
1651 }
1653 /// visitSwitchCase - Emits the necessary code to represent a single node in
1654 /// the binary search tree resulting from lowering a switch instruction.
1655 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1656 MachineBasicBlock *SwitchBB) {
1657 SDValue Cond;
1658 SDValue CondLHS = getValue(CB.CmpLHS);
1659 SDLoc dl = getCurSDLoc();
1661 // Build the setcc now.
1662 if (!CB.CmpMHS) {
1663 // Fold "(X == true)" to X and "(X == false)" to !X to
1664 // handle common cases produced by branch lowering.
1665 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1666 CB.CC == ISD::SETEQ)
1667 Cond = CondLHS;
1668 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1669 CB.CC == ISD::SETEQ) {
1670 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1671 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1672 } else
1673 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1674 } else {
1675 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1677 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1678 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1680 SDValue CmpOp = getValue(CB.CmpMHS);
1681 EVT VT = CmpOp.getValueType();
1683 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1684 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1685 ISD::SETLE);
1686 } else {
1687 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1688 VT, CmpOp, DAG.getConstant(Low, VT));
1689 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1690 DAG.getConstant(High-Low, VT), ISD::SETULE);
1691 }
1692 }
1694 // Update successor info
1695 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1696 // TrueBB and FalseBB are always different unless the incoming IR is
1697 // degenerate. This only happens when running llc on weird IR.
1698 if (CB.TrueBB != CB.FalseBB)
1699 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1701 // Set NextBlock to be the MBB immediately after the current one, if any.
1702 // This is used to avoid emitting unnecessary branches to the next block.
1703 MachineBasicBlock *NextBlock = nullptr;
1704 MachineFunction::iterator BBI = SwitchBB;
1705 if (++BBI != FuncInfo.MF->end())
1706 NextBlock = BBI;
1708 // If the lhs block is the next block, invert the condition so that we can
1709 // fall through to the lhs instead of the rhs block.
1710 if (CB.TrueBB == NextBlock) {
1711 std::swap(CB.TrueBB, CB.FalseBB);
1712 SDValue True = DAG.getConstant(1, Cond.getValueType());
1713 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1714 }
1716 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1717 MVT::Other, getControlRoot(), Cond,
1718 DAG.getBasicBlock(CB.TrueBB));
1720 // Insert the false branch. Do this even if it's a fall through branch,
1721 // this makes it easier to do DAG optimizations which require inverting
1722 // the branch condition.
1723 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1724 DAG.getBasicBlock(CB.FalseBB));
1726 DAG.setRoot(BrCond);
1727 }
1729 /// visitJumpTable - Emit JumpTable node in the current MBB
1730 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1731 // Emit the code for the jump table
1732 assert(JT.Reg != -1U && "Should lower JT Header first!");
1733 EVT PTy = TM.getTargetLowering()->getPointerTy();
1734 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1735 JT.Reg, PTy);
1736 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1737 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1738 MVT::Other, Index.getValue(1),
1739 Table, Index);
1740 DAG.setRoot(BrJumpTable);
1741 }
1743 /// visitJumpTableHeader - This function emits necessary code to produce index
1744 /// in the JumpTable from switch case.
1745 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1746 JumpTableHeader &JTH,
1747 MachineBasicBlock *SwitchBB) {
1748 // Subtract the lowest switch case value from the value being switched on and
1749 // conditional branch to default mbb if the result is greater than the
1750 // difference between smallest and largest cases.
1751 SDValue SwitchOp = getValue(JTH.SValue);
1752 EVT VT = SwitchOp.getValueType();
1753 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1754 DAG.getConstant(JTH.First, VT));
1756 // The SDNode we just created, which holds the value being switched on minus
1757 // the smallest case value, needs to be copied to a virtual register so it
1758 // can be used as an index into the jump table in a subsequent basic block.
1759 // This value may be smaller or larger than the target's pointer type, and
1760 // therefore require extension or truncating.
1761 const TargetLowering *TLI = TM.getTargetLowering();
1762 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), TLI->getPointerTy());
1764 unsigned JumpTableReg = FuncInfo.CreateReg(TLI->getPointerTy());
1765 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1766 JumpTableReg, SwitchOp);
1767 JT.Reg = JumpTableReg;
1769 // Emit the range check for the jump table, and branch to the default block
1770 // for the switch statement if the value being switched on exceeds the largest
1771 // case in the switch.
1772 SDValue CMP = DAG.getSetCC(getCurSDLoc(),
1773 TLI->getSetCCResultType(*DAG.getContext(),
1774 Sub.getValueType()),
1775 Sub,
1776 DAG.getConstant(JTH.Last - JTH.First,VT),
1777 ISD::SETUGT);
1779 // Set NextBlock to be the MBB immediately after the current one, if any.
1780 // This is used to avoid emitting unnecessary branches to the next block.
1781 MachineBasicBlock *NextBlock = nullptr;
1782 MachineFunction::iterator BBI = SwitchBB;
1784 if (++BBI != FuncInfo.MF->end())
1785 NextBlock = BBI;
1787 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1788 MVT::Other, CopyTo, CMP,
1789 DAG.getBasicBlock(JT.Default));
1791 if (JT.MBB != NextBlock)
1792 BrCond = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrCond,
1793 DAG.getBasicBlock(JT.MBB));
1795 DAG.setRoot(BrCond);
1796 }
1798 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1799 /// tail spliced into a stack protector check success bb.
1800 ///
1801 /// For a high level explanation of how this fits into the stack protector
1802 /// generation see the comment on the declaration of class
1803 /// StackProtectorDescriptor.
1804 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1805 MachineBasicBlock *ParentBB) {
1807 // First create the loads to the guard/stack slot for the comparison.
1808 const TargetLowering *TLI = TM.getTargetLowering();
1809 EVT PtrTy = TLI->getPointerTy();
1811 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1812 int FI = MFI->getStackProtectorIndex();
1814 const Value *IRGuard = SPD.getGuard();
1815 SDValue GuardPtr = getValue(IRGuard);
1816 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1818 unsigned Align =
1819 TLI->getDataLayout()->getPrefTypeAlignment(IRGuard->getType());
1820 SDValue Guard = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1821 GuardPtr, MachinePointerInfo(IRGuard, 0),
1822 true, false, false, Align);
1824 SDValue StackSlot = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1825 StackSlotPtr,
1826 MachinePointerInfo::getFixedStack(FI),
1827 true, false, false, Align);
1829 // Perform the comparison via a subtract/getsetcc.
1830 EVT VT = Guard.getValueType();
1831 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, Guard, StackSlot);
1833 SDValue Cmp = DAG.getSetCC(getCurSDLoc(),
1834 TLI->getSetCCResultType(*DAG.getContext(),
1835 Sub.getValueType()),
1836 Sub, DAG.getConstant(0, VT),
1837 ISD::SETNE);
1839 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1840 // branch to failure MBB.
1841 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1842 MVT::Other, StackSlot.getOperand(0),
1843 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1844 // Otherwise branch to success MBB.
1845 SDValue Br = DAG.getNode(ISD::BR, getCurSDLoc(),
1846 MVT::Other, BrCond,
1847 DAG.getBasicBlock(SPD.getSuccessMBB()));
1849 DAG.setRoot(Br);
1850 }
1852 /// Codegen the failure basic block for a stack protector check.
1853 ///
1854 /// A failure stack protector machine basic block consists simply of a call to
1855 /// __stack_chk_fail().
1856 ///
1857 /// For a high level explanation of how this fits into the stack protector
1858 /// generation see the comment on the declaration of class
1859 /// StackProtectorDescriptor.
1860 void
1861 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1862 const TargetLowering *TLI = TM.getTargetLowering();
1863 SDValue Chain = TLI->makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL,
1864 MVT::isVoid, nullptr, 0, false,
1865 getCurSDLoc(), false, false).second;
1866 DAG.setRoot(Chain);
1867 }
1869 /// visitBitTestHeader - This function emits necessary code to produce value
1870 /// suitable for "bit tests"
1871 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1872 MachineBasicBlock *SwitchBB) {
1873 // Subtract the minimum value
1874 SDValue SwitchOp = getValue(B.SValue);
1875 EVT VT = SwitchOp.getValueType();
1876 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1877 DAG.getConstant(B.First, VT));
1879 // Check range
1880 const TargetLowering *TLI = TM.getTargetLowering();
1881 SDValue RangeCmp = DAG.getSetCC(getCurSDLoc(),
1882 TLI->getSetCCResultType(*DAG.getContext(),
1883 Sub.getValueType()),
1884 Sub, DAG.getConstant(B.Range, VT),
1885 ISD::SETUGT);
1887 // Determine the type of the test operands.
1888 bool UsePtrType = false;
1889 if (!TLI->isTypeLegal(VT))
1890 UsePtrType = true;
1891 else {
1892 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1893 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1894 // Switch table case range are encoded into series of masks.
1895 // Just use pointer type, it's guaranteed to fit.
1896 UsePtrType = true;
1897 break;
1898 }
1899 }
1900 if (UsePtrType) {
1901 VT = TLI->getPointerTy();
1902 Sub = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), VT);
1903 }
1905 B.RegVT = VT.getSimpleVT();
1906 B.Reg = FuncInfo.CreateReg(B.RegVT);
1907 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1908 B.Reg, Sub);
1910 // Set NextBlock to be the MBB immediately after the current one, if any.
1911 // This is used to avoid emitting unnecessary branches to the next block.
1912 MachineBasicBlock *NextBlock = nullptr;
1913 MachineFunction::iterator BBI = SwitchBB;
1914 if (++BBI != FuncInfo.MF->end())
1915 NextBlock = BBI;
1917 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1919 addSuccessorWithWeight(SwitchBB, B.Default);
1920 addSuccessorWithWeight(SwitchBB, MBB);
1922 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1923 MVT::Other, CopyTo, RangeCmp,
1924 DAG.getBasicBlock(B.Default));
1926 if (MBB != NextBlock)
1927 BrRange = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, CopyTo,
1928 DAG.getBasicBlock(MBB));
1930 DAG.setRoot(BrRange);
1931 }
1933 /// visitBitTestCase - this function produces one "bit test"
1934 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1935 MachineBasicBlock* NextMBB,
1936 uint32_t BranchWeightToNext,
1937 unsigned Reg,
1938 BitTestCase &B,
1939 MachineBasicBlock *SwitchBB) {
1940 MVT VT = BB.RegVT;
1941 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1942 Reg, VT);
1943 SDValue Cmp;
1944 unsigned PopCount = CountPopulation_64(B.Mask);
1945 const TargetLowering *TLI = TM.getTargetLowering();
1946 if (PopCount == 1) {
1947 // Testing for a single bit; just compare the shift count with what it
1948 // would need to be to shift a 1 bit in that position.
1949 Cmp = DAG.getSetCC(getCurSDLoc(),
1950 TLI->getSetCCResultType(*DAG.getContext(), VT),
1951 ShiftOp,
1952 DAG.getConstant(countTrailingZeros(B.Mask), VT),
1953 ISD::SETEQ);
1954 } else if (PopCount == BB.Range) {
1955 // There is only one zero bit in the range, test for it directly.
1956 Cmp = DAG.getSetCC(getCurSDLoc(),
1957 TLI->getSetCCResultType(*DAG.getContext(), VT),
1958 ShiftOp,
1959 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT),
1960 ISD::SETNE);
1961 } else {
1962 // Make desired shift
1963 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurSDLoc(), VT,
1964 DAG.getConstant(1, VT), ShiftOp);
1966 // Emit bit tests and jumps
1967 SDValue AndOp = DAG.getNode(ISD::AND, getCurSDLoc(),
1968 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1969 Cmp = DAG.getSetCC(getCurSDLoc(),
1970 TLI->getSetCCResultType(*DAG.getContext(), VT),
1971 AndOp, DAG.getConstant(0, VT),
1972 ISD::SETNE);
1973 }
1975 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1976 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1977 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
1978 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
1980 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1981 MVT::Other, getControlRoot(),
1982 Cmp, DAG.getBasicBlock(B.TargetBB));
1984 // Set NextBlock to be the MBB immediately after the current one, if any.
1985 // This is used to avoid emitting unnecessary branches to the next block.
1986 MachineBasicBlock *NextBlock = nullptr;
1987 MachineFunction::iterator BBI = SwitchBB;
1988 if (++BBI != FuncInfo.MF->end())
1989 NextBlock = BBI;
1991 if (NextMBB != NextBlock)
1992 BrAnd = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrAnd,
1993 DAG.getBasicBlock(NextMBB));
1995 DAG.setRoot(BrAnd);
1996 }
1998 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1999 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
2001 // Retrieve successors.
2002 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
2003 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
2005 const Value *Callee(I.getCalledValue());
2006 const Function *Fn = dyn_cast<Function>(Callee);
2007 if (isa<InlineAsm>(Callee))
2008 visitInlineAsm(&I);
2009 else if (Fn && Fn->isIntrinsic()) {
2010 assert(Fn->getIntrinsicID() == Intrinsic::donothing);
2011 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2012 } else
2013 LowerCallTo(&I, getValue(Callee), false, LandingPad);
2015 // If the value of the invoke is used outside of its defining block, make it
2016 // available as a virtual register.
2017 CopyToExportRegsIfNeeded(&I);
2019 // Update successor info
2020 addSuccessorWithWeight(InvokeMBB, Return);
2021 addSuccessorWithWeight(InvokeMBB, LandingPad);
2023 // Drop into normal successor.
2024 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2025 MVT::Other, getControlRoot(),
2026 DAG.getBasicBlock(Return)));
2027 }
2029 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2030 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2031 }
2033 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2034 assert(FuncInfo.MBB->isLandingPad() &&
2035 "Call to landingpad not in landing pad!");
2037 MachineBasicBlock *MBB = FuncInfo.MBB;
2038 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2039 AddLandingPadInfo(LP, MMI, MBB);
2041 // If there aren't registers to copy the values into (e.g., during SjLj
2042 // exceptions), then don't bother to create these DAG nodes.
2043 const TargetLowering *TLI = TM.getTargetLowering();
2044 if (TLI->getExceptionPointerRegister() == 0 &&
2045 TLI->getExceptionSelectorRegister() == 0)
2046 return;
2048 SmallVector<EVT, 2> ValueVTs;
2049 ComputeValueVTs(*TLI, LP.getType(), ValueVTs);
2050 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2052 // Get the two live-in registers as SDValues. The physregs have already been
2053 // copied into virtual registers.
2054 SDValue Ops[2];
2055 Ops[0] = DAG.getZExtOrTrunc(
2056 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2057 FuncInfo.ExceptionPointerVirtReg, TLI->getPointerTy()),
2058 getCurSDLoc(), ValueVTs[0]);
2059 Ops[1] = DAG.getZExtOrTrunc(
2060 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2061 FuncInfo.ExceptionSelectorVirtReg, TLI->getPointerTy()),
2062 getCurSDLoc(), ValueVTs[1]);
2064 // Merge into one.
2065 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2066 DAG.getVTList(ValueVTs),
2067 &Ops[0], 2);
2068 setValue(&LP, Res);
2069 }
2071 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
2072 /// small case ranges).
2073 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
2074 CaseRecVector& WorkList,
2075 const Value* SV,
2076 MachineBasicBlock *Default,
2077 MachineBasicBlock *SwitchBB) {
2078 // Size is the number of Cases represented by this range.
2079 size_t Size = CR.Range.second - CR.Range.first;
2080 if (Size > 3)
2081 return false;
2083 // Get the MachineFunction which holds the current MBB. This is used when
2084 // inserting any additional MBBs necessary to represent the switch.
2085 MachineFunction *CurMF = FuncInfo.MF;
2087 // Figure out which block is immediately after the current one.
2088 MachineBasicBlock *NextBlock = nullptr;
2089 MachineFunction::iterator BBI = CR.CaseBB;
2091 if (++BBI != FuncInfo.MF->end())
2092 NextBlock = BBI;
2094 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2095 // If any two of the cases has the same destination, and if one value
2096 // is the same as the other, but has one bit unset that the other has set,
2097 // use bit manipulation to do two compares at once. For example:
2098 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
2099 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
2100 // TODO: Handle cases where CR.CaseBB != SwitchBB.
2101 if (Size == 2 && CR.CaseBB == SwitchBB) {
2102 Case &Small = *CR.Range.first;
2103 Case &Big = *(CR.Range.second-1);
2105 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
2106 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue();
2107 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue();
2109 // Check that there is only one bit different.
2110 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
2111 (SmallValue | BigValue) == BigValue) {
2112 // Isolate the common bit.
2113 APInt CommonBit = BigValue & ~SmallValue;
2114 assert((SmallValue | CommonBit) == BigValue &&
2115 CommonBit.countPopulation() == 1 && "Not a common bit?");
2117 SDValue CondLHS = getValue(SV);
2118 EVT VT = CondLHS.getValueType();
2119 SDLoc DL = getCurSDLoc();
2121 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
2122 DAG.getConstant(CommonBit, VT));
2123 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
2124 Or, DAG.getConstant(BigValue, VT),
2125 ISD::SETEQ);
2127 // Update successor info.
2128 // Both Small and Big will jump to Small.BB, so we sum up the weights.
2129 addSuccessorWithWeight(SwitchBB, Small.BB,
2130 Small.ExtraWeight + Big.ExtraWeight);
2131 addSuccessorWithWeight(SwitchBB, Default,
2132 // The default destination is the first successor in IR.
2133 BPI ? BPI->getEdgeWeight(SwitchBB->getBasicBlock(), (unsigned)0) : 0);
2135 // Insert the true branch.
2136 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
2137 getControlRoot(), Cond,
2138 DAG.getBasicBlock(Small.BB));
2140 // Insert the false branch.
2141 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
2142 DAG.getBasicBlock(Default));
2144 DAG.setRoot(BrCond);
2145 return true;
2146 }
2147 }
2148 }
2150 // Order cases by weight so the most likely case will be checked first.
2151 uint32_t UnhandledWeights = 0;
2152 if (BPI) {
2153 for (CaseItr I = CR.Range.first, IE = CR.Range.second; I != IE; ++I) {
2154 uint32_t IWeight = I->ExtraWeight;
2155 UnhandledWeights += IWeight;
2156 for (CaseItr J = CR.Range.first; J < I; ++J) {
2157 uint32_t JWeight = J->ExtraWeight;
2158 if (IWeight > JWeight)
2159 std::swap(*I, *J);
2160 }
2161 }
2162 }
2163 // Rearrange the case blocks so that the last one falls through if possible.
2164 Case &BackCase = *(CR.Range.second-1);
2165 if (Size > 1 &&
2166 NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
2167 // The last case block won't fall through into 'NextBlock' if we emit the
2168 // branches in this order. See if rearranging a case value would help.
2169 // We start at the bottom as it's the case with the least weight.
2170 for (Case *I = &*(CR.Range.second-2), *E = &*CR.Range.first-1; I != E; --I)
2171 if (I->BB == NextBlock) {
2172 std::swap(*I, BackCase);
2173 break;
2174 }
2175 }
2177 // Create a CaseBlock record representing a conditional branch to
2178 // the Case's target mbb if the value being switched on SV is equal
2179 // to C.
2180 MachineBasicBlock *CurBlock = CR.CaseBB;
2181 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2182 MachineBasicBlock *FallThrough;
2183 if (I != E-1) {
2184 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
2185 CurMF->insert(BBI, FallThrough);
2187 // Put SV in a virtual register to make it available from the new blocks.
2188 ExportFromCurrentBlock(SV);
2189 } else {
2190 // If the last case doesn't match, go to the default block.
2191 FallThrough = Default;
2192 }
2194 const Value *RHS, *LHS, *MHS;
2195 ISD::CondCode CC;
2196 if (I->High == I->Low) {
2197 // This is just small small case range :) containing exactly 1 case
2198 CC = ISD::SETEQ;
2199 LHS = SV; RHS = I->High; MHS = nullptr;
2200 } else {
2201 CC = ISD::SETLE;
2202 LHS = I->Low; MHS = SV; RHS = I->High;
2203 }
2205 // The false weight should be sum of all un-handled cases.
2206 UnhandledWeights -= I->ExtraWeight;
2207 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough,
2208 /* me */ CurBlock,
2209 /* trueweight */ I->ExtraWeight,
2210 /* falseweight */ UnhandledWeights);
2212 // If emitting the first comparison, just call visitSwitchCase to emit the
2213 // code into the current block. Otherwise, push the CaseBlock onto the
2214 // vector to be later processed by SDISel, and insert the node's MBB
2215 // before the next MBB.
2216 if (CurBlock == SwitchBB)
2217 visitSwitchCase(CB, SwitchBB);
2218 else
2219 SwitchCases.push_back(CB);
2221 CurBlock = FallThrough;
2222 }
2224 return true;
2225 }
2227 static inline bool areJTsAllowed(const TargetLowering &TLI) {
2228 return TLI.supportJumpTables() &&
2229 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
2230 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
2231 }
2233 static APInt ComputeRange(const APInt &First, const APInt &Last) {
2234 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
2235 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth);
2236 return (LastExt - FirstExt + 1ULL);
2237 }
2239 /// handleJTSwitchCase - Emit jumptable for current switch case range
2240 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR,
2241 CaseRecVector &WorkList,
2242 const Value *SV,
2243 MachineBasicBlock *Default,
2244 MachineBasicBlock *SwitchBB) {
2245 Case& FrontCase = *CR.Range.first;
2246 Case& BackCase = *(CR.Range.second-1);
2248 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2249 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2251 APInt TSize(First.getBitWidth(), 0);
2252 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I)
2253 TSize += I->size();
2255 const TargetLowering *TLI = TM.getTargetLowering();
2256 if (!areJTsAllowed(*TLI) || TSize.ult(TLI->getMinimumJumpTableEntries()))
2257 return false;
2259 APInt Range = ComputeRange(First, Last);
2260 // The density is TSize / Range. Require at least 40%.
2261 // It should not be possible for IntTSize to saturate for sane code, but make
2262 // sure we handle Range saturation correctly.
2263 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10);
2264 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10);
2265 if (IntTSize * 10 < IntRange * 4)
2266 return false;
2268 DEBUG(dbgs() << "Lowering jump table\n"
2269 << "First entry: " << First << ". Last entry: " << Last << '\n'
2270 << "Range: " << Range << ". Size: " << TSize << ".\n\n");
2272 // Get the MachineFunction which holds the current MBB. This is used when
2273 // inserting any additional MBBs necessary to represent the switch.
2274 MachineFunction *CurMF = FuncInfo.MF;
2276 // Figure out which block is immediately after the current one.
2277 MachineFunction::iterator BBI = CR.CaseBB;
2278 ++BBI;
2280 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2282 // Create a new basic block to hold the code for loading the address
2283 // of the jump table, and jumping to it. Update successor information;
2284 // we will either branch to the default case for the switch, or the jump
2285 // table.
2286 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2287 CurMF->insert(BBI, JumpTableBB);
2289 addSuccessorWithWeight(CR.CaseBB, Default);
2290 addSuccessorWithWeight(CR.CaseBB, JumpTableBB);
2292 // Build a vector of destination BBs, corresponding to each target
2293 // of the jump table. If the value of the jump table slot corresponds to
2294 // a case statement, push the case's BB onto the vector, otherwise, push
2295 // the default BB.
2296 std::vector<MachineBasicBlock*> DestBBs;
2297 APInt TEI = First;
2298 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
2299 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
2300 const APInt &High = cast<ConstantInt>(I->High)->getValue();
2302 if (Low.sle(TEI) && TEI.sle(High)) {
2303 DestBBs.push_back(I->BB);
2304 if (TEI==High)
2305 ++I;
2306 } else {
2307 DestBBs.push_back(Default);
2308 }
2309 }
2311 // Calculate weight for each unique destination in CR.
2312 DenseMap<MachineBasicBlock*, uint32_t> DestWeights;
2313 if (FuncInfo.BPI)
2314 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2315 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2316 DestWeights.find(I->BB);
2317 if (Itr != DestWeights.end())
2318 Itr->second += I->ExtraWeight;
2319 else
2320 DestWeights[I->BB] = I->ExtraWeight;
2321 }
2323 // Update successor info. Add one edge to each unique successor.
2324 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
2325 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
2326 E = DestBBs.end(); I != E; ++I) {
2327 if (!SuccsHandled[(*I)->getNumber()]) {
2328 SuccsHandled[(*I)->getNumber()] = true;
2329 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2330 DestWeights.find(*I);
2331 addSuccessorWithWeight(JumpTableBB, *I,
2332 Itr != DestWeights.end() ? Itr->second : 0);
2333 }
2334 }
2336 // Create a jump table index for this jump table.
2337 unsigned JTEncoding = TLI->getJumpTableEncoding();
2338 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
2339 ->createJumpTableIndex(DestBBs);
2341 // Set the jump table information so that we can codegen it as a second
2342 // MachineBasicBlock
2343 JumpTable JT(-1U, JTI, JumpTableBB, Default);
2344 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
2345 if (CR.CaseBB == SwitchBB)
2346 visitJumpTableHeader(JT, JTH, SwitchBB);
2348 JTCases.push_back(JumpTableBlock(JTH, JT));
2349 return true;
2350 }
2352 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2353 /// 2 subtrees.
2354 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
2355 CaseRecVector& WorkList,
2356 const Value* SV,
2357 MachineBasicBlock* Default,
2358 MachineBasicBlock* SwitchBB) {
2359 // Get the MachineFunction which holds the current MBB. This is used when
2360 // inserting any additional MBBs necessary to represent the switch.
2361 MachineFunction *CurMF = FuncInfo.MF;
2363 // Figure out which block is immediately after the current one.
2364 MachineFunction::iterator BBI = CR.CaseBB;
2365 ++BBI;
2367 Case& FrontCase = *CR.Range.first;
2368 Case& BackCase = *(CR.Range.second-1);
2369 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2371 // Size is the number of Cases represented by this range.
2372 unsigned Size = CR.Range.second - CR.Range.first;
2374 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2375 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2376 double FMetric = 0;
2377 CaseItr Pivot = CR.Range.first + Size/2;
2379 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2380 // (heuristically) allow us to emit JumpTable's later.
2381 APInt TSize(First.getBitWidth(), 0);
2382 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2383 I!=E; ++I)
2384 TSize += I->size();
2386 APInt LSize = FrontCase.size();
2387 APInt RSize = TSize-LSize;
2388 DEBUG(dbgs() << "Selecting best pivot: \n"
2389 << "First: " << First << ", Last: " << Last <<'\n'
2390 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2391 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2392 J!=E; ++I, ++J) {
2393 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
2394 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
2395 APInt Range = ComputeRange(LEnd, RBegin);
2396 assert((Range - 2ULL).isNonNegative() &&
2397 "Invalid case distance");
2398 // Use volatile double here to avoid excess precision issues on some hosts,
2399 // e.g. that use 80-bit X87 registers.
2400 volatile double LDensity =
2401 (double)LSize.roundToDouble() /
2402 (LEnd - First + 1ULL).roundToDouble();
2403 volatile double RDensity =
2404 (double)RSize.roundToDouble() /
2405 (Last - RBegin + 1ULL).roundToDouble();
2406 volatile double Metric = Range.logBase2()*(LDensity+RDensity);
2407 // Should always split in some non-trivial place
2408 DEBUG(dbgs() <<"=>Step\n"
2409 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2410 << "LDensity: " << LDensity
2411 << ", RDensity: " << RDensity << '\n'
2412 << "Metric: " << Metric << '\n');
2413 if (FMetric < Metric) {
2414 Pivot = J;
2415 FMetric = Metric;
2416 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2417 }
2419 LSize += J->size();
2420 RSize -= J->size();
2421 }
2423 const TargetLowering *TLI = TM.getTargetLowering();
2424 if (areJTsAllowed(*TLI)) {
2425 // If our case is dense we *really* should handle it earlier!
2426 assert((FMetric > 0) && "Should handle dense range earlier!");
2427 } else {
2428 Pivot = CR.Range.first + Size/2;
2429 }
2431 CaseRange LHSR(CR.Range.first, Pivot);
2432 CaseRange RHSR(Pivot, CR.Range.second);
2433 const Constant *C = Pivot->Low;
2434 MachineBasicBlock *FalseBB = nullptr, *TrueBB = nullptr;
2436 // We know that we branch to the LHS if the Value being switched on is
2437 // less than the Pivot value, C. We use this to optimize our binary
2438 // tree a bit, by recognizing that if SV is greater than or equal to the
2439 // LHS's Case Value, and that Case Value is exactly one less than the
2440 // Pivot's Value, then we can branch directly to the LHS's Target,
2441 // rather than creating a leaf node for it.
2442 if ((LHSR.second - LHSR.first) == 1 &&
2443 LHSR.first->High == CR.GE &&
2444 cast<ConstantInt>(C)->getValue() ==
2445 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2446 TrueBB = LHSR.first->BB;
2447 } else {
2448 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2449 CurMF->insert(BBI, TrueBB);
2450 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2452 // Put SV in a virtual register to make it available from the new blocks.
2453 ExportFromCurrentBlock(SV);
2454 }
2456 // Similar to the optimization above, if the Value being switched on is
2457 // known to be less than the Constant CR.LT, and the current Case Value
2458 // is CR.LT - 1, then we can branch directly to the target block for
2459 // the current Case Value, rather than emitting a RHS leaf node for it.
2460 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2461 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2462 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2463 FalseBB = RHSR.first->BB;
2464 } else {
2465 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2466 CurMF->insert(BBI, FalseBB);
2467 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2469 // Put SV in a virtual register to make it available from the new blocks.
2470 ExportFromCurrentBlock(SV);
2471 }
2473 // Create a CaseBlock record representing a conditional branch to
2474 // the LHS node if the value being switched on SV is less than C.
2475 // Otherwise, branch to LHS.
2476 CaseBlock CB(ISD::SETLT, SV, C, nullptr, TrueBB, FalseBB, CR.CaseBB);
2478 if (CR.CaseBB == SwitchBB)
2479 visitSwitchCase(CB, SwitchBB);
2480 else
2481 SwitchCases.push_back(CB);
2483 return true;
2484 }
2486 /// handleBitTestsSwitchCase - if current case range has few destination and
2487 /// range span less, than machine word bitwidth, encode case range into series
2488 /// of masks and emit bit tests with these masks.
2489 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2490 CaseRecVector& WorkList,
2491 const Value* SV,
2492 MachineBasicBlock* Default,
2493 MachineBasicBlock* SwitchBB) {
2494 const TargetLowering *TLI = TM.getTargetLowering();
2495 EVT PTy = TLI->getPointerTy();
2496 unsigned IntPtrBits = PTy.getSizeInBits();
2498 Case& FrontCase = *CR.Range.first;
2499 Case& BackCase = *(CR.Range.second-1);
2501 // Get the MachineFunction which holds the current MBB. This is used when
2502 // inserting any additional MBBs necessary to represent the switch.
2503 MachineFunction *CurMF = FuncInfo.MF;
2505 // If target does not have legal shift left, do not emit bit tests at all.
2506 if (!TLI->isOperationLegal(ISD::SHL, PTy))
2507 return false;
2509 size_t numCmps = 0;
2510 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2511 I!=E; ++I) {
2512 // Single case counts one, case range - two.
2513 numCmps += (I->Low == I->High ? 1 : 2);
2514 }
2516 // Count unique destinations
2517 SmallSet<MachineBasicBlock*, 4> Dests;
2518 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2519 Dests.insert(I->BB);
2520 if (Dests.size() > 3)
2521 // Don't bother the code below, if there are too much unique destinations
2522 return false;
2523 }
2524 DEBUG(dbgs() << "Total number of unique destinations: "
2525 << Dests.size() << '\n'
2526 << "Total number of comparisons: " << numCmps << '\n');
2528 // Compute span of values.
2529 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2530 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2531 APInt cmpRange = maxValue - minValue;
2533 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2534 << "Low bound: " << minValue << '\n'
2535 << "High bound: " << maxValue << '\n');
2537 if (cmpRange.uge(IntPtrBits) ||
2538 (!(Dests.size() == 1 && numCmps >= 3) &&
2539 !(Dests.size() == 2 && numCmps >= 5) &&
2540 !(Dests.size() >= 3 && numCmps >= 6)))
2541 return false;
2543 DEBUG(dbgs() << "Emitting bit tests\n");
2544 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2546 // Optimize the case where all the case values fit in a
2547 // word without having to subtract minValue. In this case,
2548 // we can optimize away the subtraction.
2549 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
2550 cmpRange = maxValue;
2551 } else {
2552 lowBound = minValue;
2553 }
2555 CaseBitsVector CasesBits;
2556 unsigned i, count = 0;
2558 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2559 MachineBasicBlock* Dest = I->BB;
2560 for (i = 0; i < count; ++i)
2561 if (Dest == CasesBits[i].BB)
2562 break;
2564 if (i == count) {
2565 assert((count < 3) && "Too much destinations to test!");
2566 CasesBits.push_back(CaseBits(0, Dest, 0, 0/*Weight*/));
2567 count++;
2568 }
2570 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2571 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2573 uint64_t lo = (lowValue - lowBound).getZExtValue();
2574 uint64_t hi = (highValue - lowBound).getZExtValue();
2575 CasesBits[i].ExtraWeight += I->ExtraWeight;
2577 for (uint64_t j = lo; j <= hi; j++) {
2578 CasesBits[i].Mask |= 1ULL << j;
2579 CasesBits[i].Bits++;
2580 }
2582 }
2583 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2585 BitTestInfo BTC;
2587 // Figure out which block is immediately after the current one.
2588 MachineFunction::iterator BBI = CR.CaseBB;
2589 ++BBI;
2591 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2593 DEBUG(dbgs() << "Cases:\n");
2594 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2595 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2596 << ", Bits: " << CasesBits[i].Bits
2597 << ", BB: " << CasesBits[i].BB << '\n');
2599 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2600 CurMF->insert(BBI, CaseBB);
2601 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2602 CaseBB,
2603 CasesBits[i].BB, CasesBits[i].ExtraWeight));
2605 // Put SV in a virtual register to make it available from the new blocks.
2606 ExportFromCurrentBlock(SV);
2607 }
2609 BitTestBlock BTB(lowBound, cmpRange, SV,
2610 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2611 CR.CaseBB, Default, BTC);
2613 if (CR.CaseBB == SwitchBB)
2614 visitBitTestHeader(BTB, SwitchBB);
2616 BitTestCases.push_back(BTB);
2618 return true;
2619 }
2621 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2622 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2623 const SwitchInst& SI) {
2624 size_t numCmps = 0;
2626 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2627 // Start with "simple" cases
2628 for (SwitchInst::ConstCaseIt i = SI.case_begin(), e = SI.case_end();
2629 i != e; ++i) {
2630 const BasicBlock *SuccBB = i.getCaseSuccessor();
2631 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB];
2633 uint32_t ExtraWeight =
2634 BPI ? BPI->getEdgeWeight(SI.getParent(), i.getSuccessorIndex()) : 0;
2636 Cases.push_back(Case(i.getCaseValue(), i.getCaseValue(),
2637 SMBB, ExtraWeight));
2638 }
2639 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2641 // Merge case into clusters
2642 if (Cases.size() >= 2)
2643 // Must recompute end() each iteration because it may be
2644 // invalidated by erase if we hold on to it
2645 for (CaseItr I = Cases.begin(), J = std::next(Cases.begin());
2646 J != Cases.end(); ) {
2647 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2648 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2649 MachineBasicBlock* nextBB = J->BB;
2650 MachineBasicBlock* currentBB = I->BB;
2652 // If the two neighboring cases go to the same destination, merge them
2653 // into a single case.
2654 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2655 I->High = J->High;
2656 I->ExtraWeight += J->ExtraWeight;
2657 J = Cases.erase(J);
2658 } else {
2659 I = J++;
2660 }
2661 }
2663 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2664 if (I->Low != I->High)
2665 // A range counts double, since it requires two compares.
2666 ++numCmps;
2667 }
2669 return numCmps;
2670 }
2672 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2673 MachineBasicBlock *Last) {
2674 // Update JTCases.
2675 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2676 if (JTCases[i].first.HeaderBB == First)
2677 JTCases[i].first.HeaderBB = Last;
2679 // Update BitTestCases.
2680 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2681 if (BitTestCases[i].Parent == First)
2682 BitTestCases[i].Parent = Last;
2683 }
2685 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2686 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2688 // Figure out which block is immediately after the current one.
2689 MachineBasicBlock *NextBlock = nullptr;
2690 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2692 // If there is only the default destination, branch to it if it is not the
2693 // next basic block. Otherwise, just fall through.
2694 if (!SI.getNumCases()) {
2695 // Update machine-CFG edges.
2697 // If this is not a fall-through branch, emit the branch.
2698 SwitchMBB->addSuccessor(Default);
2699 if (Default != NextBlock)
2700 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2701 MVT::Other, getControlRoot(),
2702 DAG.getBasicBlock(Default)));
2704 return;
2705 }
2707 // If there are any non-default case statements, create a vector of Cases
2708 // representing each one, and sort the vector so that we can efficiently
2709 // create a binary search tree from them.
2710 CaseVector Cases;
2711 size_t numCmps = Clusterify(Cases, SI);
2712 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2713 << ". Total compares: " << numCmps << '\n');
2714 (void)numCmps;
2716 // Get the Value to be switched on and default basic blocks, which will be
2717 // inserted into CaseBlock records, representing basic blocks in the binary
2718 // search tree.
2719 const Value *SV = SI.getCondition();
2721 // Push the initial CaseRec onto the worklist
2722 CaseRecVector WorkList;
2723 WorkList.push_back(CaseRec(SwitchMBB,nullptr,nullptr,
2724 CaseRange(Cases.begin(),Cases.end())));
2726 while (!WorkList.empty()) {
2727 // Grab a record representing a case range to process off the worklist
2728 CaseRec CR = WorkList.back();
2729 WorkList.pop_back();
2731 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2732 continue;
2734 // If the range has few cases (two or less) emit a series of specific
2735 // tests.
2736 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2737 continue;
2739 // If the switch has more than N blocks, and is at least 40% dense, and the
2740 // target supports indirect branches, then emit a jump table rather than
2741 // lowering the switch to a binary tree of conditional branches.
2742 // N defaults to 4 and is controlled via TLS.getMinimumJumpTableEntries().
2743 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2744 continue;
2746 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2747 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2748 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB);
2749 }
2750 }
2752 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2753 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2755 // Update machine-CFG edges with unique successors.
2756 SmallSet<BasicBlock*, 32> Done;
2757 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2758 BasicBlock *BB = I.getSuccessor(i);
2759 bool Inserted = Done.insert(BB);
2760 if (!Inserted)
2761 continue;
2763 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2764 addSuccessorWithWeight(IndirectBrMBB, Succ);
2765 }
2767 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2768 MVT::Other, getControlRoot(),
2769 getValue(I.getAddress())));
2770 }
2772 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2773 if (DAG.getTarget().Options.TrapUnreachable)
2774 DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2775 }
2777 void SelectionDAGBuilder::visitFSub(const User &I) {
2778 // -0.0 - X --> fneg
2779 Type *Ty = I.getType();
2780 if (isa<Constant>(I.getOperand(0)) &&
2781 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2782 SDValue Op2 = getValue(I.getOperand(1));
2783 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2784 Op2.getValueType(), Op2));
2785 return;
2786 }
2788 visitBinary(I, ISD::FSUB);
2789 }
2791 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2792 SDValue Op1 = getValue(I.getOperand(0));
2793 SDValue Op2 = getValue(I.getOperand(1));
2794 setValue(&I, DAG.getNode(OpCode, getCurSDLoc(),
2795 Op1.getValueType(), Op1, Op2));
2796 }
2798 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2799 SDValue Op1 = getValue(I.getOperand(0));
2800 SDValue Op2 = getValue(I.getOperand(1));
2802 EVT ShiftTy = TM.getTargetLowering()->getShiftAmountTy(Op2.getValueType());
2804 // Coerce the shift amount to the right type if we can.
2805 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2806 unsigned ShiftSize = ShiftTy.getSizeInBits();
2807 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2808 SDLoc DL = getCurSDLoc();
2810 // If the operand is smaller than the shift count type, promote it.
2811 if (ShiftSize > Op2Size)
2812 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2814 // If the operand is larger than the shift count type but the shift
2815 // count type has enough bits to represent any shift value, truncate
2816 // it now. This is a common case and it exposes the truncate to
2817 // optimization early.
2818 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2819 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2820 // Otherwise we'll need to temporarily settle for some other convenient
2821 // type. Type legalization will make adjustments once the shiftee is split.
2822 else
2823 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2824 }
2826 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(),
2827 Op1.getValueType(), Op1, Op2));
2828 }
2830 void SelectionDAGBuilder::visitSDiv(const User &I) {
2831 SDValue Op1 = getValue(I.getOperand(0));
2832 SDValue Op2 = getValue(I.getOperand(1));
2834 // Turn exact SDivs into multiplications.
2835 // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2836 // exact bit.
2837 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2838 !isa<ConstantSDNode>(Op1) &&
2839 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2840 setValue(&I, TM.getTargetLowering()->BuildExactSDIV(Op1, Op2,
2841 getCurSDLoc(), DAG));
2842 else
2843 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(),
2844 Op1, Op2));
2845 }
2847 void SelectionDAGBuilder::visitICmp(const User &I) {
2848 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2849 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2850 predicate = IC->getPredicate();
2851 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2852 predicate = ICmpInst::Predicate(IC->getPredicate());
2853 SDValue Op1 = getValue(I.getOperand(0));
2854 SDValue Op2 = getValue(I.getOperand(1));
2855 ISD::CondCode Opcode = getICmpCondCode(predicate);
2857 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2858 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2859 }
2861 void SelectionDAGBuilder::visitFCmp(const User &I) {
2862 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2863 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2864 predicate = FC->getPredicate();
2865 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2866 predicate = FCmpInst::Predicate(FC->getPredicate());
2867 SDValue Op1 = getValue(I.getOperand(0));
2868 SDValue Op2 = getValue(I.getOperand(1));
2869 ISD::CondCode Condition = getFCmpCondCode(predicate);
2870 if (TM.Options.NoNaNsFPMath)
2871 Condition = getFCmpCodeWithoutNaN(Condition);
2872 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2873 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2874 }
2876 void SelectionDAGBuilder::visitSelect(const User &I) {
2877 SmallVector<EVT, 4> ValueVTs;
2878 ComputeValueVTs(*TM.getTargetLowering(), I.getType(), ValueVTs);
2879 unsigned NumValues = ValueVTs.size();
2880 if (NumValues == 0) return;
2882 SmallVector<SDValue, 4> Values(NumValues);
2883 SDValue Cond = getValue(I.getOperand(0));
2884 SDValue TrueVal = getValue(I.getOperand(1));
2885 SDValue FalseVal = getValue(I.getOperand(2));
2886 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2887 ISD::VSELECT : ISD::SELECT;
2889 for (unsigned i = 0; i != NumValues; ++i)
2890 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2891 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2892 Cond,
2893 SDValue(TrueVal.getNode(),
2894 TrueVal.getResNo() + i),
2895 SDValue(FalseVal.getNode(),
2896 FalseVal.getResNo() + i));
2898 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2899 DAG.getVTList(ValueVTs),
2900 &Values[0], NumValues));
2901 }
2903 void SelectionDAGBuilder::visitTrunc(const User &I) {
2904 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2905 SDValue N = getValue(I.getOperand(0));
2906 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2907 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2908 }
2910 void SelectionDAGBuilder::visitZExt(const User &I) {
2911 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2912 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2913 SDValue N = getValue(I.getOperand(0));
2914 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2915 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2916 }
2918 void SelectionDAGBuilder::visitSExt(const User &I) {
2919 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2920 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2921 SDValue N = getValue(I.getOperand(0));
2922 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2923 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2924 }
2926 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2927 // FPTrunc is never a no-op cast, no need to check
2928 SDValue N = getValue(I.getOperand(0));
2929 const TargetLowering *TLI = TM.getTargetLowering();
2930 EVT DestVT = TLI->getValueType(I.getType());
2931 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurSDLoc(),
2932 DestVT, N,
2933 DAG.getTargetConstant(0, TLI->getPointerTy())));
2934 }
2936 void SelectionDAGBuilder::visitFPExt(const User &I) {
2937 // FPExt is never a no-op cast, no need to check
2938 SDValue N = getValue(I.getOperand(0));
2939 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2940 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2941 }
2943 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2944 // FPToUI is never a no-op cast, no need to check
2945 SDValue N = getValue(I.getOperand(0));
2946 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2947 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2948 }
2950 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2951 // FPToSI is never a no-op cast, no need to check
2952 SDValue N = getValue(I.getOperand(0));
2953 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2954 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2955 }
2957 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2958 // UIToFP is never a no-op cast, no need to check
2959 SDValue N = getValue(I.getOperand(0));
2960 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2961 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2962 }
2964 void SelectionDAGBuilder::visitSIToFP(const User &I) {
2965 // SIToFP is never a no-op cast, no need to check
2966 SDValue N = getValue(I.getOperand(0));
2967 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2968 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
2969 }
2971 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2972 // What to do depends on the size of the integer and the size of the pointer.
2973 // We can either truncate, zero extend, or no-op, accordingly.
2974 SDValue N = getValue(I.getOperand(0));
2975 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2976 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2977 }
2979 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2980 // What to do depends on the size of the integer and the size of the pointer.
2981 // We can either truncate, zero extend, or no-op, accordingly.
2982 SDValue N = getValue(I.getOperand(0));
2983 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2984 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2985 }
2987 void SelectionDAGBuilder::visitBitCast(const User &I) {
2988 SDValue N = getValue(I.getOperand(0));
2989 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2991 // BitCast assures us that source and destination are the same size so this is
2992 // either a BITCAST or a no-op.
2993 if (DestVT != N.getValueType())
2994 setValue(&I, DAG.getNode(ISD::BITCAST, getCurSDLoc(),
2995 DestVT, N)); // convert types.
2996 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
2997 // might fold any kind of constant expression to an integer constant and that
2998 // is not what we are looking for. Only regcognize a bitcast of a genuine
2999 // constant integer as an opaque constant.
3000 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
3001 setValue(&I, DAG.getConstant(C->getValue(), DestVT, /*isTarget=*/false,
3002 /*isOpaque*/true));
3003 else
3004 setValue(&I, N); // noop cast.
3005 }
3007 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
3008 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3009 const Value *SV = I.getOperand(0);
3010 SDValue N = getValue(SV);
3011 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
3013 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
3014 unsigned DestAS = I.getType()->getPointerAddressSpace();
3016 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
3017 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
3019 setValue(&I, N);
3020 }
3022 void SelectionDAGBuilder::visitInsertElement(const User &I) {
3023 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3024 SDValue InVec = getValue(I.getOperand(0));
3025 SDValue InVal = getValue(I.getOperand(1));
3026 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)),
3027 getCurSDLoc(), TLI.getVectorIdxTy());
3028 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
3029 TM.getTargetLowering()->getValueType(I.getType()),
3030 InVec, InVal, InIdx));
3031 }
3033 void SelectionDAGBuilder::visitExtractElement(const User &I) {
3034 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3035 SDValue InVec = getValue(I.getOperand(0));
3036 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)),
3037 getCurSDLoc(), TLI.getVectorIdxTy());
3038 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3039 TM.getTargetLowering()->getValueType(I.getType()),
3040 InVec, InIdx));
3041 }
3043 // Utility for visitShuffleVector - Return true if every element in Mask,
3044 // beginning from position Pos and ending in Pos+Size, falls within the
3045 // specified sequential range [L, L+Pos). or is undef.
3046 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
3047 unsigned Pos, unsigned Size, int Low) {
3048 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3049 if (Mask[i] >= 0 && Mask[i] != Low)
3050 return false;
3051 return true;
3052 }
3054 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
3055 SDValue Src1 = getValue(I.getOperand(0));
3056 SDValue Src2 = getValue(I.getOperand(1));
3058 SmallVector<int, 8> Mask;
3059 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
3060 unsigned MaskNumElts = Mask.size();
3062 const TargetLowering *TLI = TM.getTargetLowering();
3063 EVT VT = TLI->getValueType(I.getType());
3064 EVT SrcVT = Src1.getValueType();
3065 unsigned SrcNumElts = SrcVT.getVectorNumElements();
3067 if (SrcNumElts == MaskNumElts) {
3068 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3069 &Mask[0]));
3070 return;
3071 }
3073 // Normalize the shuffle vector since mask and vector length don't match.
3074 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
3075 // Mask is longer than the source vectors and is a multiple of the source
3076 // vectors. We can use concatenate vector to make the mask and vectors
3077 // lengths match.
3078 if (SrcNumElts*2 == MaskNumElts) {
3079 // First check for Src1 in low and Src2 in high
3080 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
3081 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
3082 // The shuffle is concatenating two vectors together.
3083 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
3084 VT, Src1, Src2));
3085 return;
3086 }
3087 // Then check for Src2 in low and Src1 in high
3088 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
3089 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
3090 // The shuffle is concatenating two vectors together.
3091 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
3092 VT, Src2, Src1));
3093 return;
3094 }
3095 }
3097 // Pad both vectors with undefs to make them the same length as the mask.
3098 unsigned NumConcat = MaskNumElts / SrcNumElts;
3099 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
3100 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
3101 SDValue UndefVal = DAG.getUNDEF(SrcVT);
3103 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
3104 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
3105 MOps1[0] = Src1;
3106 MOps2[0] = Src2;
3108 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
3109 getCurSDLoc(), VT,
3110 &MOps1[0], NumConcat);
3111 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
3112 getCurSDLoc(), VT,
3113 &MOps2[0], NumConcat);
3115 // Readjust mask for new input vector length.
3116 SmallVector<int, 8> MappedOps;
3117 for (unsigned i = 0; i != MaskNumElts; ++i) {
3118 int Idx = Mask[i];
3119 if (Idx >= (int)SrcNumElts)
3120 Idx -= SrcNumElts - MaskNumElts;
3121 MappedOps.push_back(Idx);
3122 }
3124 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3125 &MappedOps[0]));
3126 return;
3127 }
3129 if (SrcNumElts > MaskNumElts) {
3130 // Analyze the access pattern of the vector to see if we can extract
3131 // two subvectors and do the shuffle. The analysis is done by calculating
3132 // the range of elements the mask access on both vectors.
3133 int MinRange[2] = { static_cast<int>(SrcNumElts),
3134 static_cast<int>(SrcNumElts)};
3135 int MaxRange[2] = {-1, -1};
3137 for (unsigned i = 0; i != MaskNumElts; ++i) {
3138 int Idx = Mask[i];
3139 unsigned Input = 0;
3140 if (Idx < 0)
3141 continue;
3143 if (Idx >= (int)SrcNumElts) {
3144 Input = 1;
3145 Idx -= SrcNumElts;
3146 }
3147 if (Idx > MaxRange[Input])
3148 MaxRange[Input] = Idx;
3149 if (Idx < MinRange[Input])
3150 MinRange[Input] = Idx;
3151 }
3153 // Check if the access is smaller than the vector size and can we find
3154 // a reasonable extract index.
3155 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
3156 // Extract.
3157 int StartIdx[2]; // StartIdx to extract from
3158 for (unsigned Input = 0; Input < 2; ++Input) {
3159 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
3160 RangeUse[Input] = 0; // Unused
3161 StartIdx[Input] = 0;
3162 continue;
3163 }
3165 // Find a good start index that is a multiple of the mask length. Then
3166 // see if the rest of the elements are in range.
3167 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
3168 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
3169 StartIdx[Input] + MaskNumElts <= SrcNumElts)
3170 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
3171 }
3173 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
3174 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
3175 return;
3176 }
3177 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
3178 // Extract appropriate subvector and generate a vector shuffle
3179 for (unsigned Input = 0; Input < 2; ++Input) {
3180 SDValue &Src = Input == 0 ? Src1 : Src2;
3181 if (RangeUse[Input] == 0)
3182 Src = DAG.getUNDEF(VT);
3183 else
3184 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurSDLoc(), VT,
3185 Src, DAG.getConstant(StartIdx[Input],
3186 TLI->getVectorIdxTy()));
3187 }
3189 // Calculate new mask.
3190 SmallVector<int, 8> MappedOps;
3191 for (unsigned i = 0; i != MaskNumElts; ++i) {
3192 int Idx = Mask[i];
3193 if (Idx >= 0) {
3194 if (Idx < (int)SrcNumElts)
3195 Idx -= StartIdx[0];
3196 else
3197 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
3198 }
3199 MappedOps.push_back(Idx);
3200 }
3202 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3203 &MappedOps[0]));
3204 return;
3205 }
3206 }
3208 // We can't use either concat vectors or extract subvectors so fall back to
3209 // replacing the shuffle with extract and build vector.
3210 // to insert and build vector.
3211 EVT EltVT = VT.getVectorElementType();
3212 EVT IdxVT = TLI->getVectorIdxTy();
3213 SmallVector<SDValue,8> Ops;
3214 for (unsigned i = 0; i != MaskNumElts; ++i) {
3215 int Idx = Mask[i];
3216 SDValue Res;
3218 if (Idx < 0) {
3219 Res = DAG.getUNDEF(EltVT);
3220 } else {
3221 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
3222 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
3224 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3225 EltVT, Src, DAG.getConstant(Idx, IdxVT));
3226 }
3228 Ops.push_back(Res);
3229 }
3231 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
3232 VT, &Ops[0], Ops.size()));
3233 }
3235 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
3236 const Value *Op0 = I.getOperand(0);
3237 const Value *Op1 = I.getOperand(1);
3238 Type *AggTy = I.getType();
3239 Type *ValTy = Op1->getType();
3240 bool IntoUndef = isa<UndefValue>(Op0);
3241 bool FromUndef = isa<UndefValue>(Op1);
3243 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3245 const TargetLowering *TLI = TM.getTargetLowering();
3246 SmallVector<EVT, 4> AggValueVTs;
3247 ComputeValueVTs(*TLI, AggTy, AggValueVTs);
3248 SmallVector<EVT, 4> ValValueVTs;
3249 ComputeValueVTs(*TLI, ValTy, ValValueVTs);
3251 unsigned NumAggValues = AggValueVTs.size();
3252 unsigned NumValValues = ValValueVTs.size();
3253 SmallVector<SDValue, 4> Values(NumAggValues);
3255 SDValue Agg = getValue(Op0);
3256 unsigned i = 0;
3257 // Copy the beginning value(s) from the original aggregate.
3258 for (; i != LinearIndex; ++i)
3259 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3260 SDValue(Agg.getNode(), Agg.getResNo() + i);
3261 // Copy values from the inserted value(s).
3262 if (NumValValues) {
3263 SDValue Val = getValue(Op1);
3264 for (; i != LinearIndex + NumValValues; ++i)
3265 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3266 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
3267 }
3268 // Copy remaining value(s) from the original aggregate.
3269 for (; i != NumAggValues; ++i)
3270 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3271 SDValue(Agg.getNode(), Agg.getResNo() + i);
3273 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3274 DAG.getVTList(AggValueVTs),
3275 &Values[0], NumAggValues));
3276 }
3278 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
3279 const Value *Op0 = I.getOperand(0);
3280 Type *AggTy = Op0->getType();
3281 Type *ValTy = I.getType();
3282 bool OutOfUndef = isa<UndefValue>(Op0);
3284 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3286 const TargetLowering *TLI = TM.getTargetLowering();
3287 SmallVector<EVT, 4> ValValueVTs;
3288 ComputeValueVTs(*TLI, ValTy, ValValueVTs);
3290 unsigned NumValValues = ValValueVTs.size();
3292 // Ignore a extractvalue that produces an empty object
3293 if (!NumValValues) {
3294 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3295 return;
3296 }
3298 SmallVector<SDValue, 4> Values(NumValValues);
3300 SDValue Agg = getValue(Op0);
3301 // Copy out the selected value(s).
3302 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
3303 Values[i - LinearIndex] =
3304 OutOfUndef ?
3305 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
3306 SDValue(Agg.getNode(), Agg.getResNo() + i);
3308 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3309 DAG.getVTList(ValValueVTs),
3310 &Values[0], NumValValues));
3311 }
3313 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
3314 Value *Op0 = I.getOperand(0);
3315 // Note that the pointer operand may be a vector of pointers. Take the scalar
3316 // element which holds a pointer.
3317 Type *Ty = Op0->getType()->getScalarType();
3318 unsigned AS = Ty->getPointerAddressSpace();
3319 SDValue N = getValue(Op0);
3321 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
3322 OI != E; ++OI) {
3323 const Value *Idx = *OI;
3324 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
3325 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
3326 if (Field) {
3327 // N = N + Offset
3328 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
3329 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
3330 DAG.getConstant(Offset, N.getValueType()));
3331 }
3333 Ty = StTy->getElementType(Field);
3334 } else {
3335 Ty = cast<SequentialType>(Ty)->getElementType();
3337 // If this is a constant subscript, handle it quickly.
3338 const TargetLowering *TLI = TM.getTargetLowering();
3339 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3340 if (CI->isZero()) continue;
3341 uint64_t Offs =
3342 DL->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
3343 SDValue OffsVal;
3344 EVT PTy = TLI->getPointerTy(AS);
3345 unsigned PtrBits = PTy.getSizeInBits();
3346 if (PtrBits < 64)
3347 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), PTy,
3348 DAG.getConstant(Offs, MVT::i64));
3349 else
3350 OffsVal = DAG.getConstant(Offs, PTy);
3352 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
3353 OffsVal);
3354 continue;
3355 }
3357 // N = N + Idx * ElementSize;
3358 APInt ElementSize = APInt(TLI->getPointerSizeInBits(AS),
3359 DL->getTypeAllocSize(Ty));
3360 SDValue IdxN = getValue(Idx);
3362 // If the index is smaller or larger than intptr_t, truncate or extend
3363 // it.
3364 IdxN = DAG.getSExtOrTrunc(IdxN, getCurSDLoc(), N.getValueType());
3366 // If this is a multiply by a power of two, turn it into a shl
3367 // immediately. This is a very common case.
3368 if (ElementSize != 1) {
3369 if (ElementSize.isPowerOf2()) {
3370 unsigned Amt = ElementSize.logBase2();
3371 IdxN = DAG.getNode(ISD::SHL, getCurSDLoc(),
3372 N.getValueType(), IdxN,
3373 DAG.getConstant(Amt, IdxN.getValueType()));
3374 } else {
3375 SDValue Scale = DAG.getConstant(ElementSize, IdxN.getValueType());
3376 IdxN = DAG.getNode(ISD::MUL, getCurSDLoc(),
3377 N.getValueType(), IdxN, Scale);
3378 }
3379 }
3381 N = DAG.getNode(ISD::ADD, getCurSDLoc(),
3382 N.getValueType(), N, IdxN);
3383 }
3384 }
3386 setValue(&I, N);
3387 }
3389 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3390 // If this is a fixed sized alloca in the entry block of the function,
3391 // allocate it statically on the stack.
3392 if (FuncInfo.StaticAllocaMap.count(&I))
3393 return; // getValue will auto-populate this.
3395 Type *Ty = I.getAllocatedType();
3396 const TargetLowering *TLI = TM.getTargetLowering();
3397 uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(Ty);
3398 unsigned Align =
3399 std::max((unsigned)TLI->getDataLayout()->getPrefTypeAlignment(Ty),
3400 I.getAlignment());
3402 SDValue AllocSize = getValue(I.getArraySize());
3404 EVT IntPtr = TLI->getPointerTy();
3405 if (AllocSize.getValueType() != IntPtr)
3406 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurSDLoc(), IntPtr);
3408 AllocSize = DAG.getNode(ISD::MUL, getCurSDLoc(), IntPtr,
3409 AllocSize,
3410 DAG.getConstant(TySize, IntPtr));
3412 // Handle alignment. If the requested alignment is less than or equal to
3413 // the stack alignment, ignore it. If the size is greater than or equal to
3414 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3415 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
3416 if (Align <= StackAlign)
3417 Align = 0;
3419 // Round the size of the allocation up to the stack alignment size
3420 // by add SA-1 to the size.
3421 AllocSize = DAG.getNode(ISD::ADD, getCurSDLoc(),
3422 AllocSize.getValueType(), AllocSize,
3423 DAG.getIntPtrConstant(StackAlign-1));
3425 // Mask out the low bits for alignment purposes.
3426 AllocSize = DAG.getNode(ISD::AND, getCurSDLoc(),
3427 AllocSize.getValueType(), AllocSize,
3428 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
3430 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
3431 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3432 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurSDLoc(),
3433 VTs, Ops, 3);
3434 setValue(&I, DSA);
3435 DAG.setRoot(DSA.getValue(1));
3437 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
3438 }
3440 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3441 if (I.isAtomic())
3442 return visitAtomicLoad(I);
3444 const Value *SV = I.getOperand(0);
3445 SDValue Ptr = getValue(SV);
3447 Type *Ty = I.getType();
3449 bool isVolatile = I.isVolatile();
3450 bool isNonTemporal = I.getMetadata("nontemporal") != nullptr;
3451 bool isInvariant = I.getMetadata("invariant.load") != nullptr;
3452 unsigned Alignment = I.getAlignment();
3453 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3454 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3456 SmallVector<EVT, 4> ValueVTs;
3457 SmallVector<uint64_t, 4> Offsets;
3458 ComputeValueVTs(*TM.getTargetLowering(), Ty, ValueVTs, &Offsets);
3459 unsigned NumValues = ValueVTs.size();
3460 if (NumValues == 0)
3461 return;
3463 SDValue Root;
3464 bool ConstantMemory = false;
3465 if (isVolatile || NumValues > MaxParallelChains)
3466 // Serialize volatile loads with other side effects.
3467 Root = getRoot();
3468 else if (AA->pointsToConstantMemory(
3469 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) {
3470 // Do not serialize (non-volatile) loads of constant memory with anything.
3471 Root = DAG.getEntryNode();
3472 ConstantMemory = true;
3473 } else {
3474 // Do not serialize non-volatile loads against each other.
3475 Root = DAG.getRoot();
3476 }
3478 const TargetLowering *TLI = TM.getTargetLowering();
3479 if (isVolatile)
3480 Root = TLI->prepareVolatileOrAtomicLoad(Root, getCurSDLoc(), DAG);
3482 SmallVector<SDValue, 4> Values(NumValues);
3483 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3484 NumValues));
3485 EVT PtrVT = Ptr.getValueType();
3486 unsigned ChainI = 0;
3487 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3488 // Serializing loads here may result in excessive register pressure, and
3489 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3490 // could recover a bit by hoisting nodes upward in the chain by recognizing
3491 // they are side-effect free or do not alias. The optimizer should really
3492 // avoid this case by converting large object/array copies to llvm.memcpy
3493 // (MaxParallelChains should always remain as failsafe).
3494 if (ChainI == MaxParallelChains) {
3495 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3496 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
3497 MVT::Other, &Chains[0], ChainI);
3498 Root = Chain;
3499 ChainI = 0;
3500 }
3501 SDValue A = DAG.getNode(ISD::ADD, getCurSDLoc(),
3502 PtrVT, Ptr,
3503 DAG.getConstant(Offsets[i], PtrVT));
3504 SDValue L = DAG.getLoad(ValueVTs[i], getCurSDLoc(), Root,
3505 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3506 isNonTemporal, isInvariant, Alignment, TBAAInfo,
3507 Ranges);
3509 Values[i] = L;
3510 Chains[ChainI] = L.getValue(1);
3511 }
3513 if (!ConstantMemory) {
3514 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
3515 MVT::Other, &Chains[0], ChainI);
3516 if (isVolatile)
3517 DAG.setRoot(Chain);
3518 else
3519 PendingLoads.push_back(Chain);
3520 }
3522 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3523 DAG.getVTList(ValueVTs),
3524 &Values[0], NumValues));
3525 }
3527 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3528 if (I.isAtomic())
3529 return visitAtomicStore(I);
3531 const Value *SrcV = I.getOperand(0);
3532 const Value *PtrV = I.getOperand(1);
3534 SmallVector<EVT, 4> ValueVTs;
3535 SmallVector<uint64_t, 4> Offsets;
3536 ComputeValueVTs(*TM.getTargetLowering(), SrcV->getType(), ValueVTs, &Offsets);
3537 unsigned NumValues = ValueVTs.size();
3538 if (NumValues == 0)
3539 return;
3541 // Get the lowered operands. Note that we do this after
3542 // checking if NumResults is zero, because with zero results
3543 // the operands won't have values in the map.
3544 SDValue Src = getValue(SrcV);
3545 SDValue Ptr = getValue(PtrV);
3547 SDValue Root = getRoot();
3548 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3549 NumValues));
3550 EVT PtrVT = Ptr.getValueType();
3551 bool isVolatile = I.isVolatile();
3552 bool isNonTemporal = I.getMetadata("nontemporal") != nullptr;
3553 unsigned Alignment = I.getAlignment();
3554 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3556 unsigned ChainI = 0;
3557 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3558 // See visitLoad comments.
3559 if (ChainI == MaxParallelChains) {
3560 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
3561 MVT::Other, &Chains[0], ChainI);
3562 Root = Chain;
3563 ChainI = 0;
3564 }
3565 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), PtrVT, Ptr,
3566 DAG.getConstant(Offsets[i], PtrVT));
3567 SDValue St = DAG.getStore(Root, getCurSDLoc(),
3568 SDValue(Src.getNode(), Src.getResNo() + i),
3569 Add, MachinePointerInfo(PtrV, Offsets[i]),
3570 isVolatile, isNonTemporal, Alignment, TBAAInfo);
3571 Chains[ChainI] = St;
3572 }
3574 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
3575 MVT::Other, &Chains[0], ChainI);
3576 DAG.setRoot(StoreNode);
3577 }
3579 static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order,
3580 SynchronizationScope Scope,
3581 bool Before, SDLoc dl,
3582 SelectionDAG &DAG,
3583 const TargetLowering &TLI) {
3584 // Fence, if necessary
3585 if (Before) {
3586 if (Order == AcquireRelease || Order == SequentiallyConsistent)
3587 Order = Release;
3588 else if (Order == Acquire || Order == Monotonic)
3589 return Chain;
3590 } else {
3591 if (Order == AcquireRelease)
3592 Order = Acquire;
3593 else if (Order == Release || Order == Monotonic)
3594 return Chain;
3595 }
3596 SDValue Ops[3];
3597 Ops[0] = Chain;
3598 Ops[1] = DAG.getConstant(Order, TLI.getPointerTy());
3599 Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy());
3600 return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3);
3601 }
3603 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3604 SDLoc dl = getCurSDLoc();
3605 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3606 AtomicOrdering FailureOrder = I.getFailureOrdering();
3607 SynchronizationScope Scope = I.getSynchScope();
3609 SDValue InChain = getRoot();
3611 const TargetLowering *TLI = TM.getTargetLowering();
3612 if (TLI->getInsertFencesForAtomic())
3613 InChain = InsertFenceForAtomic(InChain, SuccessOrder, Scope, true, dl,
3614 DAG, *TLI);
3616 SDValue L =
3617 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl,
3618 getValue(I.getCompareOperand()).getSimpleValueType(),
3619 InChain,
3620 getValue(I.getPointerOperand()),
3621 getValue(I.getCompareOperand()),
3622 getValue(I.getNewValOperand()),
3623 MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment */,
3624 TLI->getInsertFencesForAtomic() ? Monotonic : SuccessOrder,
3625 TLI->getInsertFencesForAtomic() ? Monotonic : FailureOrder,
3626 Scope);
3628 SDValue OutChain = L.getValue(1);
3630 if (TLI->getInsertFencesForAtomic())
3631 OutChain = InsertFenceForAtomic(OutChain, SuccessOrder, Scope, false, dl,
3632 DAG, *TLI);
3634 setValue(&I, L);
3635 DAG.setRoot(OutChain);
3636 }
3638 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3639 SDLoc dl = getCurSDLoc();
3640 ISD::NodeType NT;
3641 switch (I.getOperation()) {
3642 default: llvm_unreachable("Unknown atomicrmw operation");
3643 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3644 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3645 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3646 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3647 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3648 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3649 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3650 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3651 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3652 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3653 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3654 }
3655 AtomicOrdering Order = I.getOrdering();
3656 SynchronizationScope Scope = I.getSynchScope();
3658 SDValue InChain = getRoot();
3660 const TargetLowering *TLI = TM.getTargetLowering();
3661 if (TLI->getInsertFencesForAtomic())
3662 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3663 DAG, *TLI);
3665 SDValue L =
3666 DAG.getAtomic(NT, dl,
3667 getValue(I.getValOperand()).getSimpleValueType(),
3668 InChain,
3669 getValue(I.getPointerOperand()),
3670 getValue(I.getValOperand()),
3671 I.getPointerOperand(), 0 /* Alignment */,
3672 TLI->getInsertFencesForAtomic() ? Monotonic : Order,
3673 Scope);
3675 SDValue OutChain = L.getValue(1);
3677 if (TLI->getInsertFencesForAtomic())
3678 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3679 DAG, *TLI);
3681 setValue(&I, L);
3682 DAG.setRoot(OutChain);
3683 }
3685 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3686 SDLoc dl = getCurSDLoc();
3687 const TargetLowering *TLI = TM.getTargetLowering();
3688 SDValue Ops[3];
3689 Ops[0] = getRoot();
3690 Ops[1] = DAG.getConstant(I.getOrdering(), TLI->getPointerTy());
3691 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI->getPointerTy());
3692 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3));
3693 }
3695 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3696 SDLoc dl = getCurSDLoc();
3697 AtomicOrdering Order = I.getOrdering();
3698 SynchronizationScope Scope = I.getSynchScope();
3700 SDValue InChain = getRoot();
3702 const TargetLowering *TLI = TM.getTargetLowering();
3703 EVT VT = TLI->getValueType(I.getType());
3705 if (I.getAlignment() < VT.getSizeInBits() / 8)
3706 report_fatal_error("Cannot generate unaligned atomic load");
3708 MachineMemOperand *MMO =
3709 DAG.getMachineFunction().
3710 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3711 MachineMemOperand::MOVolatile |
3712 MachineMemOperand::MOLoad,
3713 VT.getStoreSize(),
3714 I.getAlignment() ? I.getAlignment() :
3715 DAG.getEVTAlignment(VT));
3717 InChain = TLI->prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3718 SDValue L =
3719 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3720 getValue(I.getPointerOperand()), MMO,
3721 TLI->getInsertFencesForAtomic() ? Monotonic : Order,
3722 Scope);
3724 SDValue OutChain = L.getValue(1);
3726 if (TLI->getInsertFencesForAtomic())
3727 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3728 DAG, *TLI);
3730 setValue(&I, L);
3731 DAG.setRoot(OutChain);
3732 }
3734 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3735 SDLoc dl = getCurSDLoc();
3737 AtomicOrdering Order = I.getOrdering();
3738 SynchronizationScope Scope = I.getSynchScope();
3740 SDValue InChain = getRoot();
3742 const TargetLowering *TLI = TM.getTargetLowering();
3743 EVT VT = TLI->getValueType(I.getValueOperand()->getType());
3745 if (I.getAlignment() < VT.getSizeInBits() / 8)
3746 report_fatal_error("Cannot generate unaligned atomic store");
3748 if (TLI->getInsertFencesForAtomic())
3749 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3750 DAG, *TLI);
3752 SDValue OutChain =
3753 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3754 InChain,
3755 getValue(I.getPointerOperand()),
3756 getValue(I.getValueOperand()),
3757 I.getPointerOperand(), I.getAlignment(),
3758 TLI->getInsertFencesForAtomic() ? Monotonic : Order,
3759 Scope);
3761 if (TLI->getInsertFencesForAtomic())
3762 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3763 DAG, *TLI);
3765 DAG.setRoot(OutChain);
3766 }
3768 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3769 /// node.
3770 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3771 unsigned Intrinsic) {
3772 bool HasChain = !I.doesNotAccessMemory();
3773 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3775 // Build the operand list.
3776 SmallVector<SDValue, 8> Ops;
3777 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3778 if (OnlyLoad) {
3779 // We don't need to serialize loads against other loads.
3780 Ops.push_back(DAG.getRoot());
3781 } else {
3782 Ops.push_back(getRoot());
3783 }
3784 }
3786 // Info is set by getTgtMemInstrinsic
3787 TargetLowering::IntrinsicInfo Info;
3788 const TargetLowering *TLI = TM.getTargetLowering();
3789 bool IsTgtIntrinsic = TLI->getTgtMemIntrinsic(Info, I, Intrinsic);
3791 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3792 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3793 Info.opc == ISD::INTRINSIC_W_CHAIN)
3794 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI->getPointerTy()));
3796 // Add all operands of the call to the operand list.
3797 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3798 SDValue Op = getValue(I.getArgOperand(i));
3799 Ops.push_back(Op);
3800 }
3802 SmallVector<EVT, 4> ValueVTs;
3803 ComputeValueVTs(*TLI, I.getType(), ValueVTs);
3805 if (HasChain)
3806 ValueVTs.push_back(MVT::Other);
3808 SDVTList VTs = DAG.getVTList(ValueVTs);
3810 // Create the node.
3811 SDValue Result;
3812 if (IsTgtIntrinsic) {
3813 // This is target intrinsic that touches memory
3814 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3815 VTs, &Ops[0], Ops.size(),
3816 Info.memVT,
3817 MachinePointerInfo(Info.ptrVal, Info.offset),
3818 Info.align, Info.vol,
3819 Info.readMem, Info.writeMem);
3820 } else if (!HasChain) {
3821 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(),
3822 VTs, &Ops[0], Ops.size());
3823 } else if (!I.getType()->isVoidTy()) {
3824 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(),
3825 VTs, &Ops[0], Ops.size());
3826 } else {
3827 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(),
3828 VTs, &Ops[0], Ops.size());
3829 }
3831 if (HasChain) {
3832 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3833 if (OnlyLoad)
3834 PendingLoads.push_back(Chain);
3835 else
3836 DAG.setRoot(Chain);
3837 }
3839 if (!I.getType()->isVoidTy()) {
3840 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3841 EVT VT = TLI->getValueType(PTy);
3842 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3843 }
3845 setValue(&I, Result);
3846 }
3847 }
3849 /// GetSignificand - Get the significand and build it into a floating-point
3850 /// number with exponent of 1:
3851 ///
3852 /// Op = (Op & 0x007fffff) | 0x3f800000;
3853 ///
3854 /// where Op is the hexadecimal representation of floating point value.
3855 static SDValue
3856 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3857 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3858 DAG.getConstant(0x007fffff, MVT::i32));
3859 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3860 DAG.getConstant(0x3f800000, MVT::i32));
3861 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3862 }
3864 /// GetExponent - Get the exponent:
3865 ///
3866 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3867 ///
3868 /// where Op is the hexadecimal representation of floating point value.
3869 static SDValue
3870 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3871 SDLoc dl) {
3872 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3873 DAG.getConstant(0x7f800000, MVT::i32));
3874 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3875 DAG.getConstant(23, TLI.getPointerTy()));
3876 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3877 DAG.getConstant(127, MVT::i32));
3878 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3879 }
3881 /// getF32Constant - Get 32-bit floating point constant.
3882 static SDValue
3883 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3884 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)),
3885 MVT::f32);
3886 }
3888 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3889 /// limited-precision mode.
3890 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3891 const TargetLowering &TLI) {
3892 if (Op.getValueType() == MVT::f32 &&
3893 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3895 // Put the exponent in the right bit position for later addition to the
3896 // final result:
3897 //
3898 // #define LOG2OFe 1.4426950f
3899 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3900 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3901 getF32Constant(DAG, 0x3fb8aa3b));
3902 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3904 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3905 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3906 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3908 // IntegerPartOfX <<= 23;
3909 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3910 DAG.getConstant(23, TLI.getPointerTy()));
3912 SDValue TwoToFracPartOfX;
3913 if (LimitFloatPrecision <= 6) {
3914 // For floating-point precision of 6:
3915 //
3916 // TwoToFractionalPartOfX =
3917 // 0.997535578f +
3918 // (0.735607626f + 0.252464424f * x) * x;
3919 //
3920 // error 0.0144103317, which is 6 bits
3921 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3922 getF32Constant(DAG, 0x3e814304));
3923 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3924 getF32Constant(DAG, 0x3f3c50c8));
3925 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3926 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3927 getF32Constant(DAG, 0x3f7f5e7e));
3928 } else if (LimitFloatPrecision <= 12) {
3929 // For floating-point precision of 12:
3930 //
3931 // TwoToFractionalPartOfX =
3932 // 0.999892986f +
3933 // (0.696457318f +
3934 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3935 //
3936 // 0.000107046256 error, which is 13 to 14 bits
3937 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3938 getF32Constant(DAG, 0x3da235e3));
3939 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3940 getF32Constant(DAG, 0x3e65b8f3));
3941 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3942 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3943 getF32Constant(DAG, 0x3f324b07));
3944 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3945 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3946 getF32Constant(DAG, 0x3f7ff8fd));
3947 } else { // LimitFloatPrecision <= 18
3948 // For floating-point precision of 18:
3949 //
3950 // TwoToFractionalPartOfX =
3951 // 0.999999982f +
3952 // (0.693148872f +
3953 // (0.240227044f +
3954 // (0.554906021e-1f +
3955 // (0.961591928e-2f +
3956 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3957 //
3958 // error 2.47208000*10^(-7), which is better than 18 bits
3959 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3960 getF32Constant(DAG, 0x3924b03e));
3961 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3962 getF32Constant(DAG, 0x3ab24b87));
3963 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3964 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3965 getF32Constant(DAG, 0x3c1d8c17));
3966 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3967 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3968 getF32Constant(DAG, 0x3d634a1d));
3969 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3970 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3971 getF32Constant(DAG, 0x3e75fe14));
3972 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3973 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3974 getF32Constant(DAG, 0x3f317234));
3975 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3976 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3977 getF32Constant(DAG, 0x3f800000));
3978 }
3980 // Add the exponent into the result in integer domain.
3981 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFracPartOfX);
3982 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3983 DAG.getNode(ISD::ADD, dl, MVT::i32,
3984 t13, IntegerPartOfX));
3985 }
3987 // No special expansion.
3988 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3989 }
3991 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3992 /// limited-precision mode.
3993 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3994 const TargetLowering &TLI) {
3995 if (Op.getValueType() == MVT::f32 &&
3996 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3997 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3999 // Scale the exponent by log(2) [0.69314718f].
4000 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4001 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4002 getF32Constant(DAG, 0x3f317218));
4004 // Get the significand and build it into a floating-point number with
4005 // exponent of 1.
4006 SDValue X = GetSignificand(DAG, Op1, dl);
4008 SDValue LogOfMantissa;
4009 if (LimitFloatPrecision <= 6) {
4010 // For floating-point precision of 6:
4011 //
4012 // LogofMantissa =
4013 // -1.1609546f +
4014 // (1.4034025f - 0.23903021f * x) * x;
4015 //
4016 // error 0.0034276066, which is better than 8 bits
4017 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4018 getF32Constant(DAG, 0xbe74c456));
4019 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4020 getF32Constant(DAG, 0x3fb3a2b1));
4021 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4022 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4023 getF32Constant(DAG, 0x3f949a29));
4024 } else if (LimitFloatPrecision <= 12) {
4025 // For floating-point precision of 12:
4026 //
4027 // LogOfMantissa =
4028 // -1.7417939f +
4029 // (2.8212026f +
4030 // (-1.4699568f +
4031 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
4032 //
4033 // error 0.000061011436, which is 14 bits
4034 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4035 getF32Constant(DAG, 0xbd67b6d6));
4036 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4037 getF32Constant(DAG, 0x3ee4f4b8));
4038 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4039 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4040 getF32Constant(DAG, 0x3fbc278b));
4041 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4042 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4043 getF32Constant(DAG, 0x40348e95));
4044 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4045 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4046 getF32Constant(DAG, 0x3fdef31a));
4047 } else { // LimitFloatPrecision <= 18
4048 // For floating-point precision of 18:
4049 //
4050 // LogOfMantissa =
4051 // -2.1072184f +
4052 // (4.2372794f +
4053 // (-3.7029485f +
4054 // (2.2781945f +
4055 // (-0.87823314f +
4056 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
4057 //
4058 // error 0.0000023660568, which is better than 18 bits
4059 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4060 getF32Constant(DAG, 0xbc91e5ac));
4061 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4062 getF32Constant(DAG, 0x3e4350aa));
4063 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4064 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4065 getF32Constant(DAG, 0x3f60d3e3));
4066 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4067 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4068 getF32Constant(DAG, 0x4011cdf0));
4069 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4070 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4071 getF32Constant(DAG, 0x406cfd1c));
4072 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4073 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4074 getF32Constant(DAG, 0x408797cb));
4075 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4076 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4077 getF32Constant(DAG, 0x4006dcab));
4078 }
4080 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
4081 }
4083 // No special expansion.
4084 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
4085 }
4087 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
4088 /// limited-precision mode.
4089 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4090 const TargetLowering &TLI) {
4091 if (Op.getValueType() == MVT::f32 &&
4092 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4093 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4095 // Get the exponent.
4096 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
4098 // Get the significand and build it into a floating-point number with
4099 // exponent of 1.
4100 SDValue X = GetSignificand(DAG, Op1, dl);
4102 // Different possible minimax approximations of significand in
4103 // floating-point for various degrees of accuracy over [1,2].
4104 SDValue Log2ofMantissa;
4105 if (LimitFloatPrecision <= 6) {
4106 // For floating-point precision of 6:
4107 //
4108 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
4109 //
4110 // error 0.0049451742, which is more than 7 bits
4111 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4112 getF32Constant(DAG, 0xbeb08fe0));
4113 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4114 getF32Constant(DAG, 0x40019463));
4115 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4116 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4117 getF32Constant(DAG, 0x3fd6633d));
4118 } else if (LimitFloatPrecision <= 12) {
4119 // For floating-point precision of 12:
4120 //
4121 // Log2ofMantissa =
4122 // -2.51285454f +
4123 // (4.07009056f +
4124 // (-2.12067489f +
4125 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
4126 //
4127 // error 0.0000876136000, which is better than 13 bits
4128 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4129 getF32Constant(DAG, 0xbda7262e));
4130 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4131 getF32Constant(DAG, 0x3f25280b));
4132 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4133 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4134 getF32Constant(DAG, 0x4007b923));
4135 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4136 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4137 getF32Constant(DAG, 0x40823e2f));
4138 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4139 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4140 getF32Constant(DAG, 0x4020d29c));
4141 } else { // LimitFloatPrecision <= 18
4142 // For floating-point precision of 18:
4143 //
4144 // Log2ofMantissa =
4145 // -3.0400495f +
4146 // (6.1129976f +
4147 // (-5.3420409f +
4148 // (3.2865683f +
4149 // (-1.2669343f +
4150 // (0.27515199f -
4151 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
4152 //
4153 // error 0.0000018516, which is better than 18 bits
4154 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4155 getF32Constant(DAG, 0xbcd2769e));
4156 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4157 getF32Constant(DAG, 0x3e8ce0b9));
4158 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4159 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4160 getF32Constant(DAG, 0x3fa22ae7));
4161 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4162 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4163 getF32Constant(DAG, 0x40525723));
4164 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4165 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4166 getF32Constant(DAG, 0x40aaf200));
4167 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4168 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4169 getF32Constant(DAG, 0x40c39dad));
4170 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4171 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4172 getF32Constant(DAG, 0x4042902c));
4173 }
4175 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
4176 }
4178 // No special expansion.
4179 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
4180 }
4182 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
4183 /// limited-precision mode.
4184 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4185 const TargetLowering &TLI) {
4186 if (Op.getValueType() == MVT::f32 &&
4187 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4188 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4190 // Scale the exponent by log10(2) [0.30102999f].
4191 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4192 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4193 getF32Constant(DAG, 0x3e9a209a));
4195 // Get the significand and build it into a floating-point number with
4196 // exponent of 1.
4197 SDValue X = GetSignificand(DAG, Op1, dl);
4199 SDValue Log10ofMantissa;
4200 if (LimitFloatPrecision <= 6) {
4201 // For floating-point precision of 6:
4202 //
4203 // Log10ofMantissa =
4204 // -0.50419619f +
4205 // (0.60948995f - 0.10380950f * x) * x;
4206 //
4207 // error 0.0014886165, which is 6 bits
4208 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4209 getF32Constant(DAG, 0xbdd49a13));
4210 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4211 getF32Constant(DAG, 0x3f1c0789));
4212 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4213 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4214 getF32Constant(DAG, 0x3f011300));
4215 } else if (LimitFloatPrecision <= 12) {
4216 // For floating-point precision of 12:
4217 //
4218 // Log10ofMantissa =
4219 // -0.64831180f +
4220 // (0.91751397f +
4221 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4222 //
4223 // error 0.00019228036, which is better than 12 bits
4224 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4225 getF32Constant(DAG, 0x3d431f31));
4226 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4227 getF32Constant(DAG, 0x3ea21fb2));
4228 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4229 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4230 getF32Constant(DAG, 0x3f6ae232));
4231 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4232 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4233 getF32Constant(DAG, 0x3f25f7c3));
4234 } else { // LimitFloatPrecision <= 18
4235 // For floating-point precision of 18:
4236 //
4237 // Log10ofMantissa =
4238 // -0.84299375f +
4239 // (1.5327582f +
4240 // (-1.0688956f +
4241 // (0.49102474f +
4242 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4243 //
4244 // error 0.0000037995730, which is better than 18 bits
4245 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4246 getF32Constant(DAG, 0x3c5d51ce));
4247 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4248 getF32Constant(DAG, 0x3e00685a));
4249 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4250 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4251 getF32Constant(DAG, 0x3efb6798));
4252 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4253 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4254 getF32Constant(DAG, 0x3f88d192));
4255 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4256 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4257 getF32Constant(DAG, 0x3fc4316c));
4258 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4259 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4260 getF32Constant(DAG, 0x3f57ce70));
4261 }
4263 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4264 }
4266 // No special expansion.
4267 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4268 }
4270 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4271 /// limited-precision mode.
4272 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4273 const TargetLowering &TLI) {
4274 if (Op.getValueType() == MVT::f32 &&
4275 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4276 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
4278 // FractionalPartOfX = x - (float)IntegerPartOfX;
4279 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4280 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
4282 // IntegerPartOfX <<= 23;
4283 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4284 DAG.getConstant(23, TLI.getPointerTy()));
4286 SDValue TwoToFractionalPartOfX;
4287 if (LimitFloatPrecision <= 6) {
4288 // For floating-point precision of 6:
4289 //
4290 // TwoToFractionalPartOfX =
4291 // 0.997535578f +
4292 // (0.735607626f + 0.252464424f * x) * x;
4293 //
4294 // error 0.0144103317, which is 6 bits
4295 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4296 getF32Constant(DAG, 0x3e814304));
4297 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4298 getF32Constant(DAG, 0x3f3c50c8));
4299 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4300 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4301 getF32Constant(DAG, 0x3f7f5e7e));
4302 } else if (LimitFloatPrecision <= 12) {
4303 // For floating-point precision of 12:
4304 //
4305 // TwoToFractionalPartOfX =
4306 // 0.999892986f +
4307 // (0.696457318f +
4308 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4309 //
4310 // error 0.000107046256, which is 13 to 14 bits
4311 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4312 getF32Constant(DAG, 0x3da235e3));
4313 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4314 getF32Constant(DAG, 0x3e65b8f3));
4315 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4316 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4317 getF32Constant(DAG, 0x3f324b07));
4318 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4319 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4320 getF32Constant(DAG, 0x3f7ff8fd));
4321 } else { // LimitFloatPrecision <= 18
4322 // For floating-point precision of 18:
4323 //
4324 // TwoToFractionalPartOfX =
4325 // 0.999999982f +
4326 // (0.693148872f +
4327 // (0.240227044f +
4328 // (0.554906021e-1f +
4329 // (0.961591928e-2f +
4330 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4331 // error 2.47208000*10^(-7), which is better than 18 bits
4332 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4333 getF32Constant(DAG, 0x3924b03e));
4334 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4335 getF32Constant(DAG, 0x3ab24b87));
4336 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4337 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4338 getF32Constant(DAG, 0x3c1d8c17));
4339 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4340 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4341 getF32Constant(DAG, 0x3d634a1d));
4342 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4343 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4344 getF32Constant(DAG, 0x3e75fe14));
4345 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4346 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4347 getF32Constant(DAG, 0x3f317234));
4348 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4349 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4350 getF32Constant(DAG, 0x3f800000));
4351 }
4353 // Add the exponent into the result in integer domain.
4354 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32,
4355 TwoToFractionalPartOfX);
4356 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4357 DAG.getNode(ISD::ADD, dl, MVT::i32,
4358 t13, IntegerPartOfX));
4359 }
4361 // No special expansion.
4362 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4363 }
4365 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4366 /// limited-precision mode with x == 10.0f.
4367 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
4368 SelectionDAG &DAG, const TargetLowering &TLI) {
4369 bool IsExp10 = false;
4370 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
4371 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4372 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4373 APFloat Ten(10.0f);
4374 IsExp10 = LHSC->isExactlyValue(Ten);
4375 }
4376 }
4378 if (IsExp10) {
4379 // Put the exponent in the right bit position for later addition to the
4380 // final result:
4381 //
4382 // #define LOG2OF10 3.3219281f
4383 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
4384 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4385 getF32Constant(DAG, 0x40549a78));
4386 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
4388 // FractionalPartOfX = x - (float)IntegerPartOfX;
4389 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4390 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
4392 // IntegerPartOfX <<= 23;
4393 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4394 DAG.getConstant(23, TLI.getPointerTy()));
4396 SDValue TwoToFractionalPartOfX;
4397 if (LimitFloatPrecision <= 6) {
4398 // For floating-point precision of 6:
4399 //
4400 // twoToFractionalPartOfX =
4401 // 0.997535578f +
4402 // (0.735607626f + 0.252464424f * x) * x;
4403 //
4404 // error 0.0144103317, which is 6 bits
4405 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4406 getF32Constant(DAG, 0x3e814304));
4407 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4408 getF32Constant(DAG, 0x3f3c50c8));
4409 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4410 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4411 getF32Constant(DAG, 0x3f7f5e7e));
4412 } else if (LimitFloatPrecision <= 12) {
4413 // For floating-point precision of 12:
4414 //
4415 // TwoToFractionalPartOfX =
4416 // 0.999892986f +
4417 // (0.696457318f +
4418 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4419 //
4420 // error 0.000107046256, which is 13 to 14 bits
4421 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4422 getF32Constant(DAG, 0x3da235e3));
4423 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4424 getF32Constant(DAG, 0x3e65b8f3));
4425 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4426 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4427 getF32Constant(DAG, 0x3f324b07));
4428 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4429 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4430 getF32Constant(DAG, 0x3f7ff8fd));
4431 } else { // LimitFloatPrecision <= 18
4432 // For floating-point precision of 18:
4433 //
4434 // TwoToFractionalPartOfX =
4435 // 0.999999982f +
4436 // (0.693148872f +
4437 // (0.240227044f +
4438 // (0.554906021e-1f +
4439 // (0.961591928e-2f +
4440 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4441 // error 2.47208000*10^(-7), which is better than 18 bits
4442 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4443 getF32Constant(DAG, 0x3924b03e));
4444 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4445 getF32Constant(DAG, 0x3ab24b87));
4446 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4447 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4448 getF32Constant(DAG, 0x3c1d8c17));
4449 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4450 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4451 getF32Constant(DAG, 0x3d634a1d));
4452 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4453 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4454 getF32Constant(DAG, 0x3e75fe14));
4455 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4456 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4457 getF32Constant(DAG, 0x3f317234));
4458 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4459 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4460 getF32Constant(DAG, 0x3f800000));
4461 }
4463 SDValue t13 = DAG.getNode(ISD::BITCAST, dl,MVT::i32,TwoToFractionalPartOfX);
4464 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4465 DAG.getNode(ISD::ADD, dl, MVT::i32,
4466 t13, IntegerPartOfX));
4467 }
4469 // No special expansion.
4470 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4471 }
4474 /// ExpandPowI - Expand a llvm.powi intrinsic.
4475 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
4476 SelectionDAG &DAG) {
4477 // If RHS is a constant, we can expand this out to a multiplication tree,
4478 // otherwise we end up lowering to a call to __powidf2 (for example). When
4479 // optimizing for size, we only want to do this if the expansion would produce
4480 // a small number of multiplies, otherwise we do the full expansion.
4481 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4482 // Get the exponent as a positive value.
4483 unsigned Val = RHSC->getSExtValue();
4484 if ((int)Val < 0) Val = -Val;
4486 // powi(x, 0) -> 1.0
4487 if (Val == 0)
4488 return DAG.getConstantFP(1.0, LHS.getValueType());
4490 const Function *F = DAG.getMachineFunction().getFunction();
4491 if (!F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
4492 Attribute::OptimizeForSize) ||
4493 // If optimizing for size, don't insert too many multiplies. This
4494 // inserts up to 5 multiplies.
4495 CountPopulation_32(Val)+Log2_32(Val) < 7) {
4496 // We use the simple binary decomposition method to generate the multiply
4497 // sequence. There are more optimal ways to do this (for example,
4498 // powi(x,15) generates one more multiply than it should), but this has
4499 // the benefit of being both really simple and much better than a libcall.
4500 SDValue Res; // Logically starts equal to 1.0
4501 SDValue CurSquare = LHS;
4502 while (Val) {
4503 if (Val & 1) {
4504 if (Res.getNode())
4505 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4506 else
4507 Res = CurSquare; // 1.0*CurSquare.
4508 }
4510 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4511 CurSquare, CurSquare);
4512 Val >>= 1;
4513 }
4515 // If the original was negative, invert the result, producing 1/(x*x*x).
4516 if (RHSC->getSExtValue() < 0)
4517 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4518 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4519 return Res;
4520 }
4521 }
4523 // Otherwise, expand to a libcall.
4524 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4525 }
4527 // getTruncatedArgReg - Find underlying register used for an truncated
4528 // argument.
4529 static unsigned getTruncatedArgReg(const SDValue &N) {
4530 if (N.getOpcode() != ISD::TRUNCATE)
4531 return 0;
4533 const SDValue &Ext = N.getOperand(0);
4534 if (Ext.getOpcode() == ISD::AssertZext ||
4535 Ext.getOpcode() == ISD::AssertSext) {
4536 const SDValue &CFR = Ext.getOperand(0);
4537 if (CFR.getOpcode() == ISD::CopyFromReg)
4538 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4539 if (CFR.getOpcode() == ISD::TRUNCATE)
4540 return getTruncatedArgReg(CFR);
4541 }
4542 return 0;
4543 }
4545 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4546 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4547 /// At the end of instruction selection, they will be inserted to the entry BB.
4548 bool
4549 SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
4550 int64_t Offset, bool IsIndirect,
4551 const SDValue &N) {
4552 const Argument *Arg = dyn_cast<Argument>(V);
4553 if (!Arg)
4554 return false;
4556 MachineFunction &MF = DAG.getMachineFunction();
4557 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo();
4559 // Ignore inlined function arguments here.
4560 DIVariable DV(Variable);
4561 if (DV.isInlinedFnArgument(MF.getFunction()))
4562 return false;
4564 Optional<MachineOperand> Op;
4565 // Some arguments' frame index is recorded during argument lowering.
4566 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4567 Op = MachineOperand::CreateFI(FI);
4569 if (!Op && N.getNode()) {
4570 unsigned Reg;
4571 if (N.getOpcode() == ISD::CopyFromReg)
4572 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4573 else
4574 Reg = getTruncatedArgReg(N);
4575 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4576 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4577 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4578 if (PR)
4579 Reg = PR;
4580 }
4581 if (Reg)
4582 Op = MachineOperand::CreateReg(Reg, false);
4583 }
4585 if (!Op) {
4586 // Check if ValueMap has reg number.
4587 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4588 if (VMI != FuncInfo.ValueMap.end())
4589 Op = MachineOperand::CreateReg(VMI->second, false);
4590 }
4592 if (!Op && N.getNode())
4593 // Check if frame index is available.
4594 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4595 if (FrameIndexSDNode *FINode =
4596 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4597 Op = MachineOperand::CreateFI(FINode->getIndex());
4599 if (!Op)
4600 return false;
4602 if (Op->isReg())
4603 FuncInfo.ArgDbgValues.push_back(BuildMI(MF, getCurDebugLoc(),
4604 TII->get(TargetOpcode::DBG_VALUE),
4605 IsIndirect,
4606 Op->getReg(), Offset, Variable));
4607 else
4608 FuncInfo.ArgDbgValues.push_back(
4609 BuildMI(MF, getCurDebugLoc(), TII->get(TargetOpcode::DBG_VALUE))
4610 .addOperand(*Op).addImm(Offset).addMetadata(Variable));
4612 return true;
4613 }
4615 // VisualStudio defines setjmp as _setjmp
4616 #if defined(_MSC_VER) && defined(setjmp) && \
4617 !defined(setjmp_undefined_for_msvc)
4618 # pragma push_macro("setjmp")
4619 # undef setjmp
4620 # define setjmp_undefined_for_msvc
4621 #endif
4623 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4624 /// we want to emit this as a call to a named external function, return the name
4625 /// otherwise lower it and return null.
4626 const char *
4627 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4628 const TargetLowering *TLI = TM.getTargetLowering();
4629 SDLoc sdl = getCurSDLoc();
4630 DebugLoc dl = getCurDebugLoc();
4631 SDValue Res;
4633 switch (Intrinsic) {
4634 default:
4635 // By default, turn this into a target intrinsic node.
4636 visitTargetIntrinsic(I, Intrinsic);
4637 return nullptr;
4638 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4639 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4640 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4641 case Intrinsic::returnaddress:
4642 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl, TLI->getPointerTy(),
4643 getValue(I.getArgOperand(0))));
4644 return nullptr;
4645 case Intrinsic::frameaddress:
4646 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl, TLI->getPointerTy(),
4647 getValue(I.getArgOperand(0))));
4648 return nullptr;
4649 case Intrinsic::setjmp:
4650 return &"_setjmp"[!TLI->usesUnderscoreSetJmp()];
4651 case Intrinsic::longjmp:
4652 return &"_longjmp"[!TLI->usesUnderscoreLongJmp()];
4653 case Intrinsic::memcpy: {
4654 // Assert for address < 256 since we support only user defined address
4655 // spaces.
4656 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4657 < 256 &&
4658 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4659 < 256 &&
4660 "Unknown address space");
4661 SDValue Op1 = getValue(I.getArgOperand(0));
4662 SDValue Op2 = getValue(I.getArgOperand(1));
4663 SDValue Op3 = getValue(I.getArgOperand(2));
4664 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4665 if (!Align)
4666 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4667 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4668 DAG.setRoot(DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, false,
4669 MachinePointerInfo(I.getArgOperand(0)),
4670 MachinePointerInfo(I.getArgOperand(1))));
4671 return nullptr;
4672 }
4673 case Intrinsic::memset: {
4674 // Assert for address < 256 since we support only user defined address
4675 // spaces.
4676 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4677 < 256 &&
4678 "Unknown address space");
4679 SDValue Op1 = getValue(I.getArgOperand(0));
4680 SDValue Op2 = getValue(I.getArgOperand(1));
4681 SDValue Op3 = getValue(I.getArgOperand(2));
4682 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4683 if (!Align)
4684 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4685 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4686 DAG.setRoot(DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4687 MachinePointerInfo(I.getArgOperand(0))));
4688 return nullptr;
4689 }
4690 case Intrinsic::memmove: {
4691 // Assert for address < 256 since we support only user defined address
4692 // spaces.
4693 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4694 < 256 &&
4695 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4696 < 256 &&
4697 "Unknown address space");
4698 SDValue Op1 = getValue(I.getArgOperand(0));
4699 SDValue Op2 = getValue(I.getArgOperand(1));
4700 SDValue Op3 = getValue(I.getArgOperand(2));
4701 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4702 if (!Align)
4703 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4704 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4705 DAG.setRoot(DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4706 MachinePointerInfo(I.getArgOperand(0)),
4707 MachinePointerInfo(I.getArgOperand(1))));
4708 return nullptr;
4709 }
4710 case Intrinsic::dbg_declare: {
4711 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4712 MDNode *Variable = DI.getVariable();
4713 const Value *Address = DI.getAddress();
4714 DIVariable DIVar(Variable);
4715 assert((!DIVar || DIVar.isVariable()) &&
4716 "Variable in DbgDeclareInst should be either null or a DIVariable.");
4717 if (!Address || !DIVar) {
4718 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4719 return nullptr;
4720 }
4722 // Check if address has undef value.
4723 if (isa<UndefValue>(Address) ||
4724 (Address->use_empty() && !isa<Argument>(Address))) {
4725 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4726 return nullptr;
4727 }
4729 SDValue &N = NodeMap[Address];
4730 if (!N.getNode() && isa<Argument>(Address))
4731 // Check unused arguments map.
4732 N = UnusedArgNodeMap[Address];
4733 SDDbgValue *SDV;
4734 if (N.getNode()) {
4735 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4736 Address = BCI->getOperand(0);
4737 // Parameters are handled specially.
4738 bool isParameter =
4739 (DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable ||
4740 isa<Argument>(Address));
4742 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4744 if (isParameter && !AI) {
4745 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4746 if (FINode)
4747 // Byval parameter. We have a frame index at this point.
4748 SDV = DAG.getFrameIndexDbgValue(Variable, FINode->getIndex(),
4749 0, dl, SDNodeOrder);
4750 else {
4751 // Address is an argument, so try to emit its dbg value using
4752 // virtual register info from the FuncInfo.ValueMap.
4753 EmitFuncArgumentDbgValue(Address, Variable, 0, false, N);
4754 return nullptr;
4755 }
4756 } else if (AI)
4757 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(),
4758 true, 0, dl, SDNodeOrder);
4759 else {
4760 // Can't do anything with other non-AI cases yet.
4761 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4762 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4763 DEBUG(Address->dump());
4764 return nullptr;
4765 }
4766 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4767 } else {
4768 // If Address is an argument then try to emit its dbg value using
4769 // virtual register info from the FuncInfo.ValueMap.
4770 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, false, N)) {
4771 // If variable is pinned by a alloca in dominating bb then
4772 // use StaticAllocaMap.
4773 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4774 if (AI->getParent() != DI.getParent()) {
4775 DenseMap<const AllocaInst*, int>::iterator SI =
4776 FuncInfo.StaticAllocaMap.find(AI);
4777 if (SI != FuncInfo.StaticAllocaMap.end()) {
4778 SDV = DAG.getFrameIndexDbgValue(Variable, SI->second,
4779 0, dl, SDNodeOrder);
4780 DAG.AddDbgValue(SDV, nullptr, false);
4781 return nullptr;
4782 }
4783 }
4784 }
4785 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4786 }
4787 }
4788 return nullptr;
4789 }
4790 case Intrinsic::dbg_value: {
4791 const DbgValueInst &DI = cast<DbgValueInst>(I);
4792 DIVariable DIVar(DI.getVariable());
4793 assert((!DIVar || DIVar.isVariable()) &&
4794 "Variable in DbgValueInst should be either null or a DIVariable.");
4795 if (!DIVar)
4796 return nullptr;
4798 MDNode *Variable = DI.getVariable();
4799 uint64_t Offset = DI.getOffset();
4800 const Value *V = DI.getValue();
4801 if (!V)
4802 return nullptr;
4804 SDDbgValue *SDV;
4805 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4806 SDV = DAG.getConstantDbgValue(Variable, V, Offset, dl, SDNodeOrder);
4807 DAG.AddDbgValue(SDV, nullptr, false);
4808 } else {
4809 // Do not use getValue() in here; we don't want to generate code at
4810 // this point if it hasn't been done yet.
4811 SDValue N = NodeMap[V];
4812 if (!N.getNode() && isa<Argument>(V))
4813 // Check unused arguments map.
4814 N = UnusedArgNodeMap[V];
4815 if (N.getNode()) {
4816 // A dbg.value for an alloca is always indirect.
4817 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4818 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, IsIndirect, N)) {
4819 SDV = DAG.getDbgValue(Variable, N.getNode(),
4820 N.getResNo(), IsIndirect,
4821 Offset, dl, SDNodeOrder);
4822 DAG.AddDbgValue(SDV, N.getNode(), false);
4823 }
4824 } else if (!V->use_empty() ) {
4825 // Do not call getValue(V) yet, as we don't want to generate code.
4826 // Remember it for later.
4827 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4828 DanglingDebugInfoMap[V] = DDI;
4829 } else {
4830 // We may expand this to cover more cases. One case where we have no
4831 // data available is an unreferenced parameter.
4832 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4833 }
4834 }
4836 // Build a debug info table entry.
4837 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4838 V = BCI->getOperand(0);
4839 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4840 // Don't handle byval struct arguments or VLAs, for example.
4841 if (!AI) {
4842 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4843 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4844 return nullptr;
4845 }
4846 DenseMap<const AllocaInst*, int>::iterator SI =
4847 FuncInfo.StaticAllocaMap.find(AI);
4848 if (SI == FuncInfo.StaticAllocaMap.end())
4849 return nullptr; // VLAs.
4850 return nullptr;
4851 }
4853 case Intrinsic::eh_typeid_for: {
4854 // Find the type id for the given typeinfo.
4855 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0));
4856 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4857 Res = DAG.getConstant(TypeID, MVT::i32);
4858 setValue(&I, Res);
4859 return nullptr;
4860 }
4862 case Intrinsic::eh_return_i32:
4863 case Intrinsic::eh_return_i64:
4864 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4865 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4866 MVT::Other,
4867 getControlRoot(),
4868 getValue(I.getArgOperand(0)),
4869 getValue(I.getArgOperand(1))));
4870 return nullptr;
4871 case Intrinsic::eh_unwind_init:
4872 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4873 return nullptr;
4874 case Intrinsic::eh_dwarf_cfa: {
4875 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4876 TLI->getPointerTy());
4877 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4878 CfaArg.getValueType(),
4879 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4880 CfaArg.getValueType()),
4881 CfaArg);
4882 SDValue FA = DAG.getNode(ISD::FRAMEADDR, sdl,
4883 TLI->getPointerTy(),
4884 DAG.getConstant(0, TLI->getPointerTy()));
4885 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4886 FA, Offset));
4887 return nullptr;
4888 }
4889 case Intrinsic::eh_sjlj_callsite: {
4890 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4891 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4892 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4893 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4895 MMI.setCurrentCallSite(CI->getZExtValue());
4896 return nullptr;
4897 }
4898 case Intrinsic::eh_sjlj_functioncontext: {
4899 // Get and store the index of the function context.
4900 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4901 AllocaInst *FnCtx =
4902 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4903 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4904 MFI->setFunctionContextIndex(FI);
4905 return nullptr;
4906 }
4907 case Intrinsic::eh_sjlj_setjmp: {
4908 SDValue Ops[2];
4909 Ops[0] = getRoot();
4910 Ops[1] = getValue(I.getArgOperand(0));
4911 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4912 DAG.getVTList(MVT::i32, MVT::Other),
4913 Ops, 2);
4914 setValue(&I, Op.getValue(0));
4915 DAG.setRoot(Op.getValue(1));
4916 return nullptr;
4917 }
4918 case Intrinsic::eh_sjlj_longjmp: {
4919 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4920 getRoot(), getValue(I.getArgOperand(0))));
4921 return nullptr;
4922 }
4924 case Intrinsic::x86_mmx_pslli_w:
4925 case Intrinsic::x86_mmx_pslli_d:
4926 case Intrinsic::x86_mmx_pslli_q:
4927 case Intrinsic::x86_mmx_psrli_w:
4928 case Intrinsic::x86_mmx_psrli_d:
4929 case Intrinsic::x86_mmx_psrli_q:
4930 case Intrinsic::x86_mmx_psrai_w:
4931 case Intrinsic::x86_mmx_psrai_d: {
4932 SDValue ShAmt = getValue(I.getArgOperand(1));
4933 if (isa<ConstantSDNode>(ShAmt)) {
4934 visitTargetIntrinsic(I, Intrinsic);
4935 return nullptr;
4936 }
4937 unsigned NewIntrinsic = 0;
4938 EVT ShAmtVT = MVT::v2i32;
4939 switch (Intrinsic) {
4940 case Intrinsic::x86_mmx_pslli_w:
4941 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4942 break;
4943 case Intrinsic::x86_mmx_pslli_d:
4944 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4945 break;
4946 case Intrinsic::x86_mmx_pslli_q:
4947 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4948 break;
4949 case Intrinsic::x86_mmx_psrli_w:
4950 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4951 break;
4952 case Intrinsic::x86_mmx_psrli_d:
4953 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4954 break;
4955 case Intrinsic::x86_mmx_psrli_q:
4956 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4957 break;
4958 case Intrinsic::x86_mmx_psrai_w:
4959 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4960 break;
4961 case Intrinsic::x86_mmx_psrai_d:
4962 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4963 break;
4964 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4965 }
4967 // The vector shift intrinsics with scalars uses 32b shift amounts but
4968 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4969 // to be zero.
4970 // We must do this early because v2i32 is not a legal type.
4971 SDValue ShOps[2];
4972 ShOps[0] = ShAmt;
4973 ShOps[1] = DAG.getConstant(0, MVT::i32);
4974 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, &ShOps[0], 2);
4975 EVT DestVT = TLI->getValueType(I.getType());
4976 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4977 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4978 DAG.getConstant(NewIntrinsic, MVT::i32),
4979 getValue(I.getArgOperand(0)), ShAmt);
4980 setValue(&I, Res);
4981 return nullptr;
4982 }
4983 case Intrinsic::x86_avx_vinsertf128_pd_256:
4984 case Intrinsic::x86_avx_vinsertf128_ps_256:
4985 case Intrinsic::x86_avx_vinsertf128_si_256:
4986 case Intrinsic::x86_avx2_vinserti128: {
4987 EVT DestVT = TLI->getValueType(I.getType());
4988 EVT ElVT = TLI->getValueType(I.getArgOperand(1)->getType());
4989 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(2))->getZExtValue() & 1) *
4990 ElVT.getVectorNumElements();
4991 Res = DAG.getNode(ISD::INSERT_SUBVECTOR, sdl, DestVT,
4992 getValue(I.getArgOperand(0)),
4993 getValue(I.getArgOperand(1)),
4994 DAG.getConstant(Idx, TLI->getVectorIdxTy()));
4995 setValue(&I, Res);
4996 return nullptr;
4997 }
4998 case Intrinsic::x86_avx_vextractf128_pd_256:
4999 case Intrinsic::x86_avx_vextractf128_ps_256:
5000 case Intrinsic::x86_avx_vextractf128_si_256:
5001 case Intrinsic::x86_avx2_vextracti128: {
5002 EVT DestVT = TLI->getValueType(I.getType());
5003 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(1))->getZExtValue() & 1) *
5004 DestVT.getVectorNumElements();
5005 Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, sdl, DestVT,
5006 getValue(I.getArgOperand(0)),
5007 DAG.getConstant(Idx, TLI->getVectorIdxTy()));
5008 setValue(&I, Res);
5009 return nullptr;
5010 }
5011 case Intrinsic::convertff:
5012 case Intrinsic::convertfsi:
5013 case Intrinsic::convertfui:
5014 case Intrinsic::convertsif:
5015 case Intrinsic::convertuif:
5016 case Intrinsic::convertss:
5017 case Intrinsic::convertsu:
5018 case Intrinsic::convertus:
5019 case Intrinsic::convertuu: {
5020 ISD::CvtCode Code = ISD::CVT_INVALID;
5021 switch (Intrinsic) {
5022 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5023 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
5024 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
5025 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
5026 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
5027 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
5028 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
5029 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
5030 case Intrinsic::convertus: Code = ISD::CVT_US; break;
5031 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
5032 }
5033 EVT DestVT = TLI->getValueType(I.getType());
5034 const Value *Op1 = I.getArgOperand(0);
5035 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
5036 DAG.getValueType(DestVT),
5037 DAG.getValueType(getValue(Op1).getValueType()),
5038 getValue(I.getArgOperand(1)),
5039 getValue(I.getArgOperand(2)),
5040 Code);
5041 setValue(&I, Res);
5042 return nullptr;
5043 }
5044 case Intrinsic::powi:
5045 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
5046 getValue(I.getArgOperand(1)), DAG));
5047 return nullptr;
5048 case Intrinsic::log:
5049 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
5050 return nullptr;
5051 case Intrinsic::log2:
5052 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
5053 return nullptr;
5054 case Intrinsic::log10:
5055 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
5056 return nullptr;
5057 case Intrinsic::exp:
5058 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
5059 return nullptr;
5060 case Intrinsic::exp2:
5061 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
5062 return nullptr;
5063 case Intrinsic::pow:
5064 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
5065 getValue(I.getArgOperand(1)), DAG, *TLI));
5066 return nullptr;
5067 case Intrinsic::sqrt:
5068 case Intrinsic::fabs:
5069 case Intrinsic::sin:
5070 case Intrinsic::cos:
5071 case Intrinsic::floor:
5072 case Intrinsic::ceil:
5073 case Intrinsic::trunc:
5074 case Intrinsic::rint:
5075 case Intrinsic::nearbyint:
5076 case Intrinsic::round: {
5077 unsigned Opcode;
5078 switch (Intrinsic) {
5079 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5080 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
5081 case Intrinsic::fabs: Opcode = ISD::FABS; break;
5082 case Intrinsic::sin: Opcode = ISD::FSIN; break;
5083 case Intrinsic::cos: Opcode = ISD::FCOS; break;
5084 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
5085 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
5086 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
5087 case Intrinsic::rint: Opcode = ISD::FRINT; break;
5088 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
5089 case Intrinsic::round: Opcode = ISD::FROUND; break;
5090 }
5092 setValue(&I, DAG.getNode(Opcode, sdl,
5093 getValue(I.getArgOperand(0)).getValueType(),
5094 getValue(I.getArgOperand(0))));
5095 return nullptr;
5096 }
5097 case Intrinsic::copysign:
5098 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
5099 getValue(I.getArgOperand(0)).getValueType(),
5100 getValue(I.getArgOperand(0)),
5101 getValue(I.getArgOperand(1))));
5102 return nullptr;
5103 case Intrinsic::fma:
5104 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5105 getValue(I.getArgOperand(0)).getValueType(),
5106 getValue(I.getArgOperand(0)),
5107 getValue(I.getArgOperand(1)),
5108 getValue(I.getArgOperand(2))));
5109 return nullptr;
5110 case Intrinsic::fmuladd: {
5111 EVT VT = TLI->getValueType(I.getType());
5112 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
5113 TLI->isFMAFasterThanFMulAndFAdd(VT)) {
5114 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5115 getValue(I.getArgOperand(0)).getValueType(),
5116 getValue(I.getArgOperand(0)),
5117 getValue(I.getArgOperand(1)),
5118 getValue(I.getArgOperand(2))));
5119 } else {
5120 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
5121 getValue(I.getArgOperand(0)).getValueType(),
5122 getValue(I.getArgOperand(0)),
5123 getValue(I.getArgOperand(1)));
5124 SDValue Add = DAG.getNode(ISD::FADD, sdl,
5125 getValue(I.getArgOperand(0)).getValueType(),
5126 Mul,
5127 getValue(I.getArgOperand(2)));
5128 setValue(&I, Add);
5129 }
5130 return nullptr;
5131 }
5132 case Intrinsic::convert_to_fp16:
5133 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, sdl,
5134 MVT::i16, getValue(I.getArgOperand(0))));
5135 return nullptr;
5136 case Intrinsic::convert_from_fp16:
5137 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, sdl,
5138 MVT::f32, getValue(I.getArgOperand(0))));
5139 return nullptr;
5140 case Intrinsic::pcmarker: {
5141 SDValue Tmp = getValue(I.getArgOperand(0));
5142 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
5143 return nullptr;
5144 }
5145 case Intrinsic::readcyclecounter: {
5146 SDValue Op = getRoot();
5147 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
5148 DAG.getVTList(MVT::i64, MVT::Other),
5149 &Op, 1);
5150 setValue(&I, Res);
5151 DAG.setRoot(Res.getValue(1));
5152 return nullptr;
5153 }
5154 case Intrinsic::bswap:
5155 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
5156 getValue(I.getArgOperand(0)).getValueType(),
5157 getValue(I.getArgOperand(0))));
5158 return nullptr;
5159 case Intrinsic::cttz: {
5160 SDValue Arg = getValue(I.getArgOperand(0));
5161 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5162 EVT Ty = Arg.getValueType();
5163 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
5164 sdl, Ty, Arg));
5165 return nullptr;
5166 }
5167 case Intrinsic::ctlz: {
5168 SDValue Arg = getValue(I.getArgOperand(0));
5169 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5170 EVT Ty = Arg.getValueType();
5171 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
5172 sdl, Ty, Arg));
5173 return nullptr;
5174 }
5175 case Intrinsic::ctpop: {
5176 SDValue Arg = getValue(I.getArgOperand(0));
5177 EVT Ty = Arg.getValueType();
5178 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
5179 return nullptr;
5180 }
5181 case Intrinsic::stacksave: {
5182 SDValue Op = getRoot();
5183 Res = DAG.getNode(ISD::STACKSAVE, sdl,
5184 DAG.getVTList(TLI->getPointerTy(), MVT::Other), &Op, 1);
5185 setValue(&I, Res);
5186 DAG.setRoot(Res.getValue(1));
5187 return nullptr;
5188 }
5189 case Intrinsic::stackrestore: {
5190 Res = getValue(I.getArgOperand(0));
5191 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
5192 return nullptr;
5193 }
5194 case Intrinsic::stackprotector: {
5195 // Emit code into the DAG to store the stack guard onto the stack.
5196 MachineFunction &MF = DAG.getMachineFunction();
5197 MachineFrameInfo *MFI = MF.getFrameInfo();
5198 EVT PtrTy = TLI->getPointerTy();
5200 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value.
5201 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
5203 int FI = FuncInfo.StaticAllocaMap[Slot];
5204 MFI->setStackProtectorIndex(FI);
5206 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
5208 // Store the stack protector onto the stack.
5209 Res = DAG.getStore(getRoot(), sdl, Src, FIN,
5210 MachinePointerInfo::getFixedStack(FI),
5211 true, false, 0);
5212 setValue(&I, Res);
5213 DAG.setRoot(Res);
5214 return nullptr;
5215 }
5216 case Intrinsic::objectsize: {
5217 // If we don't know by now, we're never going to know.
5218 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
5220 assert(CI && "Non-constant type in __builtin_object_size?");
5222 SDValue Arg = getValue(I.getCalledValue());
5223 EVT Ty = Arg.getValueType();
5225 if (CI->isZero())
5226 Res = DAG.getConstant(-1ULL, Ty);
5227 else
5228 Res = DAG.getConstant(0, Ty);
5230 setValue(&I, Res);
5231 return nullptr;
5232 }
5233 case Intrinsic::annotation:
5234 case Intrinsic::ptr_annotation:
5235 // Drop the intrinsic, but forward the value
5236 setValue(&I, getValue(I.getOperand(0)));
5237 return nullptr;
5238 case Intrinsic::var_annotation:
5239 // Discard annotate attributes
5240 return nullptr;
5242 case Intrinsic::init_trampoline: {
5243 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5245 SDValue Ops[6];
5246 Ops[0] = getRoot();
5247 Ops[1] = getValue(I.getArgOperand(0));
5248 Ops[2] = getValue(I.getArgOperand(1));
5249 Ops[3] = getValue(I.getArgOperand(2));
5250 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5251 Ops[5] = DAG.getSrcValue(F);
5253 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops, 6);
5255 DAG.setRoot(Res);
5256 return nullptr;
5257 }
5258 case Intrinsic::adjust_trampoline: {
5259 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
5260 TLI->getPointerTy(),
5261 getValue(I.getArgOperand(0))));
5262 return nullptr;
5263 }
5264 case Intrinsic::gcroot:
5265 if (GFI) {
5266 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
5267 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5269 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5270 GFI->addStackRoot(FI->getIndex(), TypeMap);
5271 }
5272 return nullptr;
5273 case Intrinsic::gcread:
5274 case Intrinsic::gcwrite:
5275 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5276 case Intrinsic::flt_rounds:
5277 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
5278 return nullptr;
5280 case Intrinsic::expect: {
5281 // Just replace __builtin_expect(exp, c) with EXP.
5282 setValue(&I, getValue(I.getArgOperand(0)));
5283 return nullptr;
5284 }
5286 case Intrinsic::debugtrap:
5287 case Intrinsic::trap: {
5288 StringRef TrapFuncName = TM.Options.getTrapFunctionName();
5289 if (TrapFuncName.empty()) {
5290 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
5291 ISD::TRAP : ISD::DEBUGTRAP;
5292 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
5293 return nullptr;
5294 }
5295 TargetLowering::ArgListTy Args;
5296 TargetLowering::
5297 CallLoweringInfo CLI(getRoot(), I.getType(),
5298 false, false, false, false, 0, CallingConv::C,
5299 /*isTailCall=*/false,
5300 /*doesNotRet=*/false, /*isReturnValueUsed=*/true,
5301 DAG.getExternalSymbol(TrapFuncName.data(),
5302 TLI->getPointerTy()),
5303 Args, DAG, sdl);
5304 std::pair<SDValue, SDValue> Result = TLI->LowerCallTo(CLI);
5305 DAG.setRoot(Result.second);
5306 return nullptr;
5307 }
5309 case Intrinsic::uadd_with_overflow:
5310 case Intrinsic::sadd_with_overflow:
5311 case Intrinsic::usub_with_overflow:
5312 case Intrinsic::ssub_with_overflow:
5313 case Intrinsic::umul_with_overflow:
5314 case Intrinsic::smul_with_overflow: {
5315 ISD::NodeType Op;
5316 switch (Intrinsic) {
5317 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5318 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5319 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5320 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5321 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5322 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5323 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5324 }
5325 SDValue Op1 = getValue(I.getArgOperand(0));
5326 SDValue Op2 = getValue(I.getArgOperand(1));
5328 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5329 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
5330 return nullptr;
5331 }
5332 case Intrinsic::prefetch: {
5333 SDValue Ops[5];
5334 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5335 Ops[0] = getRoot();
5336 Ops[1] = getValue(I.getArgOperand(0));
5337 Ops[2] = getValue(I.getArgOperand(1));
5338 Ops[3] = getValue(I.getArgOperand(2));
5339 Ops[4] = getValue(I.getArgOperand(3));
5340 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
5341 DAG.getVTList(MVT::Other),
5342 &Ops[0], 5,
5343 EVT::getIntegerVT(*Context, 8),
5344 MachinePointerInfo(I.getArgOperand(0)),
5345 0, /* align */
5346 false, /* volatile */
5347 rw==0, /* read */
5348 rw==1)); /* write */
5349 return nullptr;
5350 }
5351 case Intrinsic::lifetime_start:
5352 case Intrinsic::lifetime_end: {
5353 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
5354 // Stack coloring is not enabled in O0, discard region information.
5355 if (TM.getOptLevel() == CodeGenOpt::None)
5356 return nullptr;
5358 SmallVector<Value *, 4> Allocas;
5359 GetUnderlyingObjects(I.getArgOperand(1), Allocas, DL);
5361 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
5362 E = Allocas.end(); Object != E; ++Object) {
5363 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5365 // Could not find an Alloca.
5366 if (!LifetimeObject)
5367 continue;
5369 int FI = FuncInfo.StaticAllocaMap[LifetimeObject];
5371 SDValue Ops[2];
5372 Ops[0] = getRoot();
5373 Ops[1] = DAG.getFrameIndex(FI, TLI->getPointerTy(), true);
5374 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5376 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops, 2);
5377 DAG.setRoot(Res);
5378 }
5379 return nullptr;
5380 }
5381 case Intrinsic::invariant_start:
5382 // Discard region information.
5383 setValue(&I, DAG.getUNDEF(TLI->getPointerTy()));
5384 return nullptr;
5385 case Intrinsic::invariant_end:
5386 // Discard region information.
5387 return nullptr;
5388 case Intrinsic::stackprotectorcheck: {
5389 // Do not actually emit anything for this basic block. Instead we initialize
5390 // the stack protector descriptor and export the guard variable so we can
5391 // access it in FinishBasicBlock.
5392 const BasicBlock *BB = I.getParent();
5393 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
5394 ExportFromCurrentBlock(SPDescriptor.getGuard());
5396 // Flush our exports since we are going to process a terminator.
5397 (void)getControlRoot();
5398 return nullptr;
5399 }
5400 case Intrinsic::clear_cache:
5401 return TLI->getClearCacheBuiltinName();
5402 case Intrinsic::donothing:
5403 // ignore
5404 return nullptr;
5405 case Intrinsic::experimental_stackmap: {
5406 visitStackmap(I);
5407 return nullptr;
5408 }
5409 case Intrinsic::experimental_patchpoint_void:
5410 case Intrinsic::experimental_patchpoint_i64: {
5411 visitPatchpoint(I);
5412 return nullptr;
5413 }
5414 }
5415 }
5417 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5418 bool isTailCall,
5419 MachineBasicBlock *LandingPad) {
5420 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5421 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5422 Type *RetTy = FTy->getReturnType();
5423 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5424 MCSymbol *BeginLabel = nullptr;
5426 TargetLowering::ArgListTy Args;
5427 TargetLowering::ArgListEntry Entry;
5428 Args.reserve(CS.arg_size());
5430 // Check whether the function can return without sret-demotion.
5431 SmallVector<ISD::OutputArg, 4> Outs;
5432 const TargetLowering *TLI = TM.getTargetLowering();
5433 GetReturnInfo(RetTy, CS.getAttributes(), Outs, *TLI);
5435 bool CanLowerReturn = TLI->CanLowerReturn(CS.getCallingConv(),
5436 DAG.getMachineFunction(),
5437 FTy->isVarArg(), Outs,
5438 FTy->getContext());
5440 SDValue DemoteStackSlot;
5441 int DemoteStackIdx = -100;
5443 if (!CanLowerReturn) {
5444 assert(!CS.hasInAllocaArgument() &&
5445 "sret demotion is incompatible with inalloca");
5446 uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(
5447 FTy->getReturnType());
5448 unsigned Align = TLI->getDataLayout()->getPrefTypeAlignment(
5449 FTy->getReturnType());
5450 MachineFunction &MF = DAG.getMachineFunction();
5451 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5452 Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType());
5454 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI->getPointerTy());
5455 Entry.Node = DemoteStackSlot;
5456 Entry.Ty = StackSlotPtrType;
5457 Entry.isSExt = false;
5458 Entry.isZExt = false;
5459 Entry.isInReg = false;
5460 Entry.isSRet = true;
5461 Entry.isNest = false;
5462 Entry.isByVal = false;
5463 Entry.isReturned = false;
5464 Entry.Alignment = Align;
5465 Args.push_back(Entry);
5466 RetTy = Type::getVoidTy(FTy->getContext());
5467 }
5469 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5470 i != e; ++i) {
5471 const Value *V = *i;
5473 // Skip empty types
5474 if (V->getType()->isEmptyTy())
5475 continue;
5477 SDValue ArgNode = getValue(V);
5478 Entry.Node = ArgNode; Entry.Ty = V->getType();
5480 // Skip the first return-type Attribute to get to params.
5481 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5482 Args.push_back(Entry);
5483 }
5485 if (LandingPad) {
5486 // Insert a label before the invoke call to mark the try range. This can be
5487 // used to detect deletion of the invoke via the MachineModuleInfo.
5488 BeginLabel = MMI.getContext().CreateTempSymbol();
5490 // For SjLj, keep track of which landing pads go with which invokes
5491 // so as to maintain the ordering of pads in the LSDA.
5492 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5493 if (CallSiteIndex) {
5494 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5495 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5497 // Now that the call site is handled, stop tracking it.
5498 MMI.setCurrentCallSite(0);
5499 }
5501 // Both PendingLoads and PendingExports must be flushed here;
5502 // this call might not return.
5503 (void)getRoot();
5504 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5505 }
5507 // Check if target-independent constraints permit a tail call here.
5508 // Target-dependent constraints are checked within TLI->LowerCallTo.
5509 if (isTailCall && !isInTailCallPosition(CS, *TLI))
5510 isTailCall = false;
5512 TargetLowering::
5513 CallLoweringInfo CLI(getRoot(), RetTy, FTy, isTailCall, Callee, Args, DAG,
5514 getCurSDLoc(), CS);
5515 std::pair<SDValue,SDValue> Result = TLI->LowerCallTo(CLI);
5516 assert((isTailCall || Result.second.getNode()) &&
5517 "Non-null chain expected with non-tail call!");
5518 assert((Result.second.getNode() || !Result.first.getNode()) &&
5519 "Null value expected with tail call!");
5520 if (Result.first.getNode()) {
5521 setValue(CS.getInstruction(), Result.first);
5522 } else if (!CanLowerReturn && Result.second.getNode()) {
5523 // The instruction result is the result of loading from the
5524 // hidden sret parameter.
5525 SmallVector<EVT, 1> PVTs;
5526 Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType());
5528 ComputeValueVTs(*TLI, PtrRetTy, PVTs);
5529 assert(PVTs.size() == 1 && "Pointers should fit in one register");
5530 EVT PtrVT = PVTs[0];
5532 SmallVector<EVT, 4> RetTys;
5533 SmallVector<uint64_t, 4> Offsets;
5534 RetTy = FTy->getReturnType();
5535 ComputeValueVTs(*TLI, RetTy, RetTys, &Offsets);
5537 unsigned NumValues = RetTys.size();
5538 SmallVector<SDValue, 4> Values(NumValues);
5539 SmallVector<SDValue, 4> Chains(NumValues);
5541 for (unsigned i = 0; i < NumValues; ++i) {
5542 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), PtrVT,
5543 DemoteStackSlot,
5544 DAG.getConstant(Offsets[i], PtrVT));
5545 SDValue L = DAG.getLoad(RetTys[i], getCurSDLoc(), Result.second, Add,
5546 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]),
5547 false, false, false, 1);
5548 Values[i] = L;
5549 Chains[i] = L.getValue(1);
5550 }
5552 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
5553 MVT::Other, &Chains[0], NumValues);
5554 PendingLoads.push_back(Chain);
5556 setValue(CS.getInstruction(),
5557 DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
5558 DAG.getVTList(RetTys),
5559 &Values[0], Values.size()));
5560 }
5562 if (!Result.second.getNode()) {
5563 // As a special case, a null chain means that a tail call has been emitted
5564 // and the DAG root is already updated.
5565 HasTailCall = true;
5567 // Since there's no actual continuation from this block, nothing can be
5568 // relying on us setting vregs for them.
5569 PendingExports.clear();
5570 } else {
5571 DAG.setRoot(Result.second);
5572 }
5574 if (LandingPad) {
5575 // Insert a label at the end of the invoke call to mark the try range. This
5576 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5577 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
5578 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5580 // Inform MachineModuleInfo of range.
5581 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5582 }
5583 }
5585 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5586 /// value is equal or not-equal to zero.
5587 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5588 for (const User *U : V->users()) {
5589 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5590 if (IC->isEquality())
5591 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5592 if (C->isNullValue())
5593 continue;
5594 // Unknown instruction.
5595 return false;
5596 }
5597 return true;
5598 }
5600 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5601 Type *LoadTy,
5602 SelectionDAGBuilder &Builder) {
5604 // Check to see if this load can be trivially constant folded, e.g. if the
5605 // input is from a string literal.
5606 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5607 // Cast pointer to the type we really want to load.
5608 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5609 PointerType::getUnqual(LoadTy));
5611 if (const Constant *LoadCst =
5612 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
5613 Builder.DL))
5614 return Builder.getValue(LoadCst);
5615 }
5617 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5618 // still constant memory, the input chain can be the entry node.
5619 SDValue Root;
5620 bool ConstantMemory = false;
5622 // Do not serialize (non-volatile) loads of constant memory with anything.
5623 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5624 Root = Builder.DAG.getEntryNode();
5625 ConstantMemory = true;
5626 } else {
5627 // Do not serialize non-volatile loads against each other.
5628 Root = Builder.DAG.getRoot();
5629 }
5631 SDValue Ptr = Builder.getValue(PtrVal);
5632 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5633 Ptr, MachinePointerInfo(PtrVal),
5634 false /*volatile*/,
5635 false /*nontemporal*/,
5636 false /*isinvariant*/, 1 /* align=1 */);
5638 if (!ConstantMemory)
5639 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5640 return LoadVal;
5641 }
5643 /// processIntegerCallValue - Record the value for an instruction that
5644 /// produces an integer result, converting the type where necessary.
5645 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5646 SDValue Value,
5647 bool IsSigned) {
5648 EVT VT = TM.getTargetLowering()->getValueType(I.getType(), true);
5649 if (IsSigned)
5650 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5651 else
5652 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5653 setValue(&I, Value);
5654 }
5656 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5657 /// If so, return true and lower it, otherwise return false and it will be
5658 /// lowered like a normal call.
5659 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5660 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5661 if (I.getNumArgOperands() != 3)
5662 return false;
5664 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5665 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5666 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5667 !I.getType()->isIntegerTy())
5668 return false;
5670 const Value *Size = I.getArgOperand(2);
5671 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5672 if (CSize && CSize->getZExtValue() == 0) {
5673 EVT CallVT = TM.getTargetLowering()->getValueType(I.getType(), true);
5674 setValue(&I, DAG.getConstant(0, CallVT));
5675 return true;
5676 }
5678 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5679 std::pair<SDValue, SDValue> Res =
5680 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5681 getValue(LHS), getValue(RHS), getValue(Size),
5682 MachinePointerInfo(LHS),
5683 MachinePointerInfo(RHS));
5684 if (Res.first.getNode()) {
5685 processIntegerCallValue(I, Res.first, true);
5686 PendingLoads.push_back(Res.second);
5687 return true;
5688 }
5690 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5691 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5692 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5693 bool ActuallyDoIt = true;
5694 MVT LoadVT;
5695 Type *LoadTy;
5696 switch (CSize->getZExtValue()) {
5697 default:
5698 LoadVT = MVT::Other;
5699 LoadTy = nullptr;
5700 ActuallyDoIt = false;
5701 break;
5702 case 2:
5703 LoadVT = MVT::i16;
5704 LoadTy = Type::getInt16Ty(CSize->getContext());
5705 break;
5706 case 4:
5707 LoadVT = MVT::i32;
5708 LoadTy = Type::getInt32Ty(CSize->getContext());
5709 break;
5710 case 8:
5711 LoadVT = MVT::i64;
5712 LoadTy = Type::getInt64Ty(CSize->getContext());
5713 break;
5714 /*
5715 case 16:
5716 LoadVT = MVT::v4i32;
5717 LoadTy = Type::getInt32Ty(CSize->getContext());
5718 LoadTy = VectorType::get(LoadTy, 4);
5719 break;
5720 */
5721 }
5723 // This turns into unaligned loads. We only do this if the target natively
5724 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5725 // we'll only produce a small number of byte loads.
5727 // Require that we can find a legal MVT, and only do this if the target
5728 // supports unaligned loads of that type. Expanding into byte loads would
5729 // bloat the code.
5730 const TargetLowering *TLI = TM.getTargetLowering();
5731 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5732 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5733 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5734 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5735 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5736 if (!TLI->isTypeLegal(LoadVT) ||
5737 !TLI->allowsUnalignedMemoryAccesses(LoadVT, SrcAS) ||
5738 !TLI->allowsUnalignedMemoryAccesses(LoadVT, DstAS))
5739 ActuallyDoIt = false;
5740 }
5742 if (ActuallyDoIt) {
5743 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5744 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5746 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5747 ISD::SETNE);
5748 processIntegerCallValue(I, Res, false);
5749 return true;
5750 }
5751 }
5754 return false;
5755 }
5757 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5758 /// form. If so, return true and lower it, otherwise return false and it
5759 /// will be lowered like a normal call.
5760 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5761 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5762 if (I.getNumArgOperands() != 3)
5763 return false;
5765 const Value *Src = I.getArgOperand(0);
5766 const Value *Char = I.getArgOperand(1);
5767 const Value *Length = I.getArgOperand(2);
5768 if (!Src->getType()->isPointerTy() ||
5769 !Char->getType()->isIntegerTy() ||
5770 !Length->getType()->isIntegerTy() ||
5771 !I.getType()->isPointerTy())
5772 return false;
5774 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5775 std::pair<SDValue, SDValue> Res =
5776 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5777 getValue(Src), getValue(Char), getValue(Length),
5778 MachinePointerInfo(Src));
5779 if (Res.first.getNode()) {
5780 setValue(&I, Res.first);
5781 PendingLoads.push_back(Res.second);
5782 return true;
5783 }
5785 return false;
5786 }
5788 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5789 /// optimized form. If so, return true and lower it, otherwise return false
5790 /// and it will be lowered like a normal call.
5791 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5792 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5793 if (I.getNumArgOperands() != 2)
5794 return false;
5796 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5797 if (!Arg0->getType()->isPointerTy() ||
5798 !Arg1->getType()->isPointerTy() ||
5799 !I.getType()->isPointerTy())
5800 return false;
5802 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5803 std::pair<SDValue, SDValue> Res =
5804 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5805 getValue(Arg0), getValue(Arg1),
5806 MachinePointerInfo(Arg0),
5807 MachinePointerInfo(Arg1), isStpcpy);
5808 if (Res.first.getNode()) {
5809 setValue(&I, Res.first);
5810 DAG.setRoot(Res.second);
5811 return true;
5812 }
5814 return false;
5815 }
5817 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5818 /// If so, return true and lower it, otherwise return false and it will be
5819 /// lowered like a normal call.
5820 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5821 // Verify that the prototype makes sense. int strcmp(void*,void*)
5822 if (I.getNumArgOperands() != 2)
5823 return false;
5825 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5826 if (!Arg0->getType()->isPointerTy() ||
5827 !Arg1->getType()->isPointerTy() ||
5828 !I.getType()->isIntegerTy())
5829 return false;
5831 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5832 std::pair<SDValue, SDValue> Res =
5833 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5834 getValue(Arg0), getValue(Arg1),
5835 MachinePointerInfo(Arg0),
5836 MachinePointerInfo(Arg1));
5837 if (Res.first.getNode()) {
5838 processIntegerCallValue(I, Res.first, true);
5839 PendingLoads.push_back(Res.second);
5840 return true;
5841 }
5843 return false;
5844 }
5846 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5847 /// form. If so, return true and lower it, otherwise return false and it
5848 /// will be lowered like a normal call.
5849 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5850 // Verify that the prototype makes sense. size_t strlen(char *)
5851 if (I.getNumArgOperands() != 1)
5852 return false;
5854 const Value *Arg0 = I.getArgOperand(0);
5855 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5856 return false;
5858 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5859 std::pair<SDValue, SDValue> Res =
5860 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5861 getValue(Arg0), MachinePointerInfo(Arg0));
5862 if (Res.first.getNode()) {
5863 processIntegerCallValue(I, Res.first, false);
5864 PendingLoads.push_back(Res.second);
5865 return true;
5866 }
5868 return false;
5869 }
5871 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5872 /// form. If so, return true and lower it, otherwise return false and it
5873 /// will be lowered like a normal call.
5874 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5875 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5876 if (I.getNumArgOperands() != 2)
5877 return false;
5879 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5880 if (!Arg0->getType()->isPointerTy() ||
5881 !Arg1->getType()->isIntegerTy() ||
5882 !I.getType()->isIntegerTy())
5883 return false;
5885 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5886 std::pair<SDValue, SDValue> Res =
5887 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5888 getValue(Arg0), getValue(Arg1),
5889 MachinePointerInfo(Arg0));
5890 if (Res.first.getNode()) {
5891 processIntegerCallValue(I, Res.first, false);
5892 PendingLoads.push_back(Res.second);
5893 return true;
5894 }
5896 return false;
5897 }
5899 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5900 /// operation (as expected), translate it to an SDNode with the specified opcode
5901 /// and return true.
5902 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5903 unsigned Opcode) {
5904 // Sanity check that it really is a unary floating-point call.
5905 if (I.getNumArgOperands() != 1 ||
5906 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5907 I.getType() != I.getArgOperand(0)->getType() ||
5908 !I.onlyReadsMemory())
5909 return false;
5911 SDValue Tmp = getValue(I.getArgOperand(0));
5912 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5913 return true;
5914 }
5916 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5917 // Handle inline assembly differently.
5918 if (isa<InlineAsm>(I.getCalledValue())) {
5919 visitInlineAsm(&I);
5920 return;
5921 }
5923 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5924 ComputeUsesVAFloatArgument(I, &MMI);
5926 const char *RenameFn = nullptr;
5927 if (Function *F = I.getCalledFunction()) {
5928 if (F->isDeclaration()) {
5929 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5930 if (unsigned IID = II->getIntrinsicID(F)) {
5931 RenameFn = visitIntrinsicCall(I, IID);
5932 if (!RenameFn)
5933 return;
5934 }
5935 }
5936 if (unsigned IID = F->getIntrinsicID()) {
5937 RenameFn = visitIntrinsicCall(I, IID);
5938 if (!RenameFn)
5939 return;
5940 }
5941 }
5943 // Check for well-known libc/libm calls. If the function is internal, it
5944 // can't be a library call.
5945 LibFunc::Func Func;
5946 if (!F->hasLocalLinkage() && F->hasName() &&
5947 LibInfo->getLibFunc(F->getName(), Func) &&
5948 LibInfo->hasOptimizedCodeGen(Func)) {
5949 switch (Func) {
5950 default: break;
5951 case LibFunc::copysign:
5952 case LibFunc::copysignf:
5953 case LibFunc::copysignl:
5954 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5955 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5956 I.getType() == I.getArgOperand(0)->getType() &&
5957 I.getType() == I.getArgOperand(1)->getType() &&
5958 I.onlyReadsMemory()) {
5959 SDValue LHS = getValue(I.getArgOperand(0));
5960 SDValue RHS = getValue(I.getArgOperand(1));
5961 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5962 LHS.getValueType(), LHS, RHS));
5963 return;
5964 }
5965 break;
5966 case LibFunc::fabs:
5967 case LibFunc::fabsf:
5968 case LibFunc::fabsl:
5969 if (visitUnaryFloatCall(I, ISD::FABS))
5970 return;
5971 break;
5972 case LibFunc::sin:
5973 case LibFunc::sinf:
5974 case LibFunc::sinl:
5975 if (visitUnaryFloatCall(I, ISD::FSIN))
5976 return;
5977 break;
5978 case LibFunc::cos:
5979 case LibFunc::cosf:
5980 case LibFunc::cosl:
5981 if (visitUnaryFloatCall(I, ISD::FCOS))
5982 return;
5983 break;
5984 case LibFunc::sqrt:
5985 case LibFunc::sqrtf:
5986 case LibFunc::sqrtl:
5987 case LibFunc::sqrt_finite:
5988 case LibFunc::sqrtf_finite:
5989 case LibFunc::sqrtl_finite:
5990 if (visitUnaryFloatCall(I, ISD::FSQRT))
5991 return;
5992 break;
5993 case LibFunc::floor:
5994 case LibFunc::floorf:
5995 case LibFunc::floorl:
5996 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5997 return;
5998 break;
5999 case LibFunc::nearbyint:
6000 case LibFunc::nearbyintf:
6001 case LibFunc::nearbyintl:
6002 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
6003 return;
6004 break;
6005 case LibFunc::ceil:
6006 case LibFunc::ceilf:
6007 case LibFunc::ceill:
6008 if (visitUnaryFloatCall(I, ISD::FCEIL))
6009 return;
6010 break;
6011 case LibFunc::rint:
6012 case LibFunc::rintf:
6013 case LibFunc::rintl:
6014 if (visitUnaryFloatCall(I, ISD::FRINT))
6015 return;
6016 break;
6017 case LibFunc::round:
6018 case LibFunc::roundf:
6019 case LibFunc::roundl:
6020 if (visitUnaryFloatCall(I, ISD::FROUND))
6021 return;
6022 break;
6023 case LibFunc::trunc:
6024 case LibFunc::truncf:
6025 case LibFunc::truncl:
6026 if (visitUnaryFloatCall(I, ISD::FTRUNC))
6027 return;
6028 break;
6029 case LibFunc::log2:
6030 case LibFunc::log2f:
6031 case LibFunc::log2l:
6032 if (visitUnaryFloatCall(I, ISD::FLOG2))
6033 return;
6034 break;
6035 case LibFunc::exp2:
6036 case LibFunc::exp2f:
6037 case LibFunc::exp2l:
6038 if (visitUnaryFloatCall(I, ISD::FEXP2))
6039 return;
6040 break;
6041 case LibFunc::memcmp:
6042 if (visitMemCmpCall(I))
6043 return;
6044 break;
6045 case LibFunc::memchr:
6046 if (visitMemChrCall(I))
6047 return;
6048 break;
6049 case LibFunc::strcpy:
6050 if (visitStrCpyCall(I, false))
6051 return;
6052 break;
6053 case LibFunc::stpcpy:
6054 if (visitStrCpyCall(I, true))
6055 return;
6056 break;
6057 case LibFunc::strcmp:
6058 if (visitStrCmpCall(I))
6059 return;
6060 break;
6061 case LibFunc::strlen:
6062 if (visitStrLenCall(I))
6063 return;
6064 break;
6065 case LibFunc::strnlen:
6066 if (visitStrNLenCall(I))
6067 return;
6068 break;
6069 }
6070 }
6071 }
6073 SDValue Callee;
6074 if (!RenameFn)
6075 Callee = getValue(I.getCalledValue());
6076 else
6077 Callee = DAG.getExternalSymbol(RenameFn,
6078 TM.getTargetLowering()->getPointerTy());
6080 // Check if we can potentially perform a tail call. More detailed checking is
6081 // be done within LowerCallTo, after more information about the call is known.
6082 LowerCallTo(&I, Callee, I.isTailCall());
6083 }
6085 namespace {
6087 /// AsmOperandInfo - This contains information for each constraint that we are
6088 /// lowering.
6089 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
6090 public:
6091 /// CallOperand - If this is the result output operand or a clobber
6092 /// this is null, otherwise it is the incoming operand to the CallInst.
6093 /// This gets modified as the asm is processed.
6094 SDValue CallOperand;
6096 /// AssignedRegs - If this is a register or register class operand, this
6097 /// contains the set of register corresponding to the operand.
6098 RegsForValue AssignedRegs;
6100 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
6101 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
6102 }
6104 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
6105 /// corresponds to. If there is no Value* for this operand, it returns
6106 /// MVT::Other.
6107 EVT getCallOperandValEVT(LLVMContext &Context,
6108 const TargetLowering &TLI,
6109 const DataLayout *DL) const {
6110 if (!CallOperandVal) return MVT::Other;
6112 if (isa<BasicBlock>(CallOperandVal))
6113 return TLI.getPointerTy();
6115 llvm::Type *OpTy = CallOperandVal->getType();
6117 // FIXME: code duplicated from TargetLowering::ParseConstraints().
6118 // If this is an indirect operand, the operand is a pointer to the
6119 // accessed type.
6120 if (isIndirect) {
6121 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
6122 if (!PtrTy)
6123 report_fatal_error("Indirect operand for inline asm not a pointer!");
6124 OpTy = PtrTy->getElementType();
6125 }
6127 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
6128 if (StructType *STy = dyn_cast<StructType>(OpTy))
6129 if (STy->getNumElements() == 1)
6130 OpTy = STy->getElementType(0);
6132 // If OpTy is not a single value, it may be a struct/union that we
6133 // can tile with integers.
6134 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
6135 unsigned BitSize = DL->getTypeSizeInBits(OpTy);
6136 switch (BitSize) {
6137 default: break;
6138 case 1:
6139 case 8:
6140 case 16:
6141 case 32:
6142 case 64:
6143 case 128:
6144 OpTy = IntegerType::get(Context, BitSize);
6145 break;
6146 }
6147 }
6149 return TLI.getValueType(OpTy, true);
6150 }
6151 };
6153 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
6155 } // end anonymous namespace
6157 /// GetRegistersForValue - Assign registers (virtual or physical) for the
6158 /// specified operand. We prefer to assign virtual registers, to allow the
6159 /// register allocator to handle the assignment process. However, if the asm
6160 /// uses features that we can't model on machineinstrs, we have SDISel do the
6161 /// allocation. This produces generally horrible, but correct, code.
6162 ///
6163 /// OpInfo describes the operand.
6164 ///
6165 static void GetRegistersForValue(SelectionDAG &DAG,
6166 const TargetLowering &TLI,
6167 SDLoc DL,
6168 SDISelAsmOperandInfo &OpInfo) {
6169 LLVMContext &Context = *DAG.getContext();
6171 MachineFunction &MF = DAG.getMachineFunction();
6172 SmallVector<unsigned, 4> Regs;
6174 // If this is a constraint for a single physreg, or a constraint for a
6175 // register class, find it.
6176 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
6177 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
6178 OpInfo.ConstraintVT);
6180 unsigned NumRegs = 1;
6181 if (OpInfo.ConstraintVT != MVT::Other) {
6182 // If this is a FP input in an integer register (or visa versa) insert a bit
6183 // cast of the input value. More generally, handle any case where the input
6184 // value disagrees with the register class we plan to stick this in.
6185 if (OpInfo.Type == InlineAsm::isInput &&
6186 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
6187 // Try to convert to the first EVT that the reg class contains. If the
6188 // types are identical size, use a bitcast to convert (e.g. two differing
6189 // vector types).
6190 MVT RegVT = *PhysReg.second->vt_begin();
6191 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
6192 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6193 RegVT, OpInfo.CallOperand);
6194 OpInfo.ConstraintVT = RegVT;
6195 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
6196 // If the input is a FP value and we want it in FP registers, do a
6197 // bitcast to the corresponding integer type. This turns an f64 value
6198 // into i64, which can be passed with two i32 values on a 32-bit
6199 // machine.
6200 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
6201 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6202 RegVT, OpInfo.CallOperand);
6203 OpInfo.ConstraintVT = RegVT;
6204 }
6205 }
6207 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
6208 }
6210 MVT RegVT;
6211 EVT ValueVT = OpInfo.ConstraintVT;
6213 // If this is a constraint for a specific physical register, like {r17},
6214 // assign it now.
6215 if (unsigned AssignedReg = PhysReg.first) {
6216 const TargetRegisterClass *RC = PhysReg.second;
6217 if (OpInfo.ConstraintVT == MVT::Other)
6218 ValueVT = *RC->vt_begin();
6220 // Get the actual register value type. This is important, because the user
6221 // may have asked for (e.g.) the AX register in i32 type. We need to
6222 // remember that AX is actually i16 to get the right extension.
6223 RegVT = *RC->vt_begin();
6225 // This is a explicit reference to a physical register.
6226 Regs.push_back(AssignedReg);
6228 // If this is an expanded reference, add the rest of the regs to Regs.
6229 if (NumRegs != 1) {
6230 TargetRegisterClass::iterator I = RC->begin();
6231 for (; *I != AssignedReg; ++I)
6232 assert(I != RC->end() && "Didn't find reg!");
6234 // Already added the first reg.
6235 --NumRegs; ++I;
6236 for (; NumRegs; --NumRegs, ++I) {
6237 assert(I != RC->end() && "Ran out of registers to allocate!");
6238 Regs.push_back(*I);
6239 }
6240 }
6242 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6243 return;
6244 }
6246 // Otherwise, if this was a reference to an LLVM register class, create vregs
6247 // for this reference.
6248 if (const TargetRegisterClass *RC = PhysReg.second) {
6249 RegVT = *RC->vt_begin();
6250 if (OpInfo.ConstraintVT == MVT::Other)
6251 ValueVT = RegVT;
6253 // Create the appropriate number of virtual registers.
6254 MachineRegisterInfo &RegInfo = MF.getRegInfo();
6255 for (; NumRegs; --NumRegs)
6256 Regs.push_back(RegInfo.createVirtualRegister(RC));
6258 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6259 return;
6260 }
6262 // Otherwise, we couldn't allocate enough registers for this.
6263 }
6265 /// visitInlineAsm - Handle a call to an InlineAsm object.
6266 ///
6267 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
6268 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
6270 /// ConstraintOperands - Information about all of the constraints.
6271 SDISelAsmOperandInfoVector ConstraintOperands;
6273 const TargetLowering *TLI = TM.getTargetLowering();
6274 TargetLowering::AsmOperandInfoVector
6275 TargetConstraints = TLI->ParseConstraints(CS);
6277 bool hasMemory = false;
6279 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
6280 unsigned ResNo = 0; // ResNo - The result number of the next output.
6281 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6282 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
6283 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
6285 MVT OpVT = MVT::Other;
6287 // Compute the value type for each operand.
6288 switch (OpInfo.Type) {
6289 case InlineAsm::isOutput:
6290 // Indirect outputs just consume an argument.
6291 if (OpInfo.isIndirect) {
6292 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6293 break;
6294 }
6296 // The return value of the call is this value. As such, there is no
6297 // corresponding argument.
6298 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6299 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
6300 OpVT = TLI->getSimpleValueType(STy->getElementType(ResNo));
6301 } else {
6302 assert(ResNo == 0 && "Asm only has one result!");
6303 OpVT = TLI->getSimpleValueType(CS.getType());
6304 }
6305 ++ResNo;
6306 break;
6307 case InlineAsm::isInput:
6308 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6309 break;
6310 case InlineAsm::isClobber:
6311 // Nothing to do.
6312 break;
6313 }
6315 // If this is an input or an indirect output, process the call argument.
6316 // BasicBlocks are labels, currently appearing only in asm's.
6317 if (OpInfo.CallOperandVal) {
6318 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
6319 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
6320 } else {
6321 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
6322 }
6324 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), *TLI, DL).
6325 getSimpleVT();
6326 }
6328 OpInfo.ConstraintVT = OpVT;
6330 // Indirect operand accesses access memory.
6331 if (OpInfo.isIndirect)
6332 hasMemory = true;
6333 else {
6334 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
6335 TargetLowering::ConstraintType
6336 CType = TLI->getConstraintType(OpInfo.Codes[j]);
6337 if (CType == TargetLowering::C_Memory) {
6338 hasMemory = true;
6339 break;
6340 }
6341 }
6342 }
6343 }
6345 SDValue Chain, Flag;
6347 // We won't need to flush pending loads if this asm doesn't touch
6348 // memory and is nonvolatile.
6349 if (hasMemory || IA->hasSideEffects())
6350 Chain = getRoot();
6351 else
6352 Chain = DAG.getRoot();
6354 // Second pass over the constraints: compute which constraint option to use
6355 // and assign registers to constraints that want a specific physreg.
6356 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6357 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6359 // If this is an output operand with a matching input operand, look up the
6360 // matching input. If their types mismatch, e.g. one is an integer, the
6361 // other is floating point, or their sizes are different, flag it as an
6362 // error.
6363 if (OpInfo.hasMatchingInput()) {
6364 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6366 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
6367 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
6368 TLI->getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
6369 OpInfo.ConstraintVT);
6370 std::pair<unsigned, const TargetRegisterClass*> InputRC =
6371 TLI->getRegForInlineAsmConstraint(Input.ConstraintCode,
6372 Input.ConstraintVT);
6373 if ((OpInfo.ConstraintVT.isInteger() !=
6374 Input.ConstraintVT.isInteger()) ||
6375 (MatchRC.second != InputRC.second)) {
6376 report_fatal_error("Unsupported asm: input constraint"
6377 " with a matching output constraint of"
6378 " incompatible type!");
6379 }
6380 Input.ConstraintVT = OpInfo.ConstraintVT;
6381 }
6382 }
6384 // Compute the constraint code and ConstraintType to use.
6385 TLI->ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6387 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6388 OpInfo.Type == InlineAsm::isClobber)
6389 continue;
6391 // If this is a memory input, and if the operand is not indirect, do what we
6392 // need to to provide an address for the memory input.
6393 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6394 !OpInfo.isIndirect) {
6395 assert((OpInfo.isMultipleAlternative ||
6396 (OpInfo.Type == InlineAsm::isInput)) &&
6397 "Can only indirectify direct input operands!");
6399 // Memory operands really want the address of the value. If we don't have
6400 // an indirect input, put it in the constpool if we can, otherwise spill
6401 // it to a stack slot.
6402 // TODO: This isn't quite right. We need to handle these according to
6403 // the addressing mode that the constraint wants. Also, this may take
6404 // an additional register for the computation and we don't want that
6405 // either.
6407 // If the operand is a float, integer, or vector constant, spill to a
6408 // constant pool entry to get its address.
6409 const Value *OpVal = OpInfo.CallOperandVal;
6410 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6411 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6412 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
6413 TLI->getPointerTy());
6414 } else {
6415 // Otherwise, create a stack slot and emit a store to it before the
6416 // asm.
6417 Type *Ty = OpVal->getType();
6418 uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(Ty);
6419 unsigned Align = TLI->getDataLayout()->getPrefTypeAlignment(Ty);
6420 MachineFunction &MF = DAG.getMachineFunction();
6421 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6422 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI->getPointerTy());
6423 Chain = DAG.getStore(Chain, getCurSDLoc(),
6424 OpInfo.CallOperand, StackSlot,
6425 MachinePointerInfo::getFixedStack(SSFI),
6426 false, false, 0);
6427 OpInfo.CallOperand = StackSlot;
6428 }
6430 // There is no longer a Value* corresponding to this operand.
6431 OpInfo.CallOperandVal = nullptr;
6433 // It is now an indirect operand.
6434 OpInfo.isIndirect = true;
6435 }
6437 // If this constraint is for a specific register, allocate it before
6438 // anything else.
6439 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6440 GetRegistersForValue(DAG, *TLI, getCurSDLoc(), OpInfo);
6441 }
6443 // Second pass - Loop over all of the operands, assigning virtual or physregs
6444 // to register class operands.
6445 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6446 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6448 // C_Register operands have already been allocated, Other/Memory don't need
6449 // to be.
6450 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6451 GetRegistersForValue(DAG, *TLI, getCurSDLoc(), OpInfo);
6452 }
6454 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6455 std::vector<SDValue> AsmNodeOperands;
6456 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6457 AsmNodeOperands.push_back(
6458 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
6459 TLI->getPointerTy()));
6461 // If we have a !srcloc metadata node associated with it, we want to attach
6462 // this to the ultimately generated inline asm machineinstr. To do this, we
6463 // pass in the third operand as this (potentially null) inline asm MDNode.
6464 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6465 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6467 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6468 // bits as operand 3.
6469 unsigned ExtraInfo = 0;
6470 if (IA->hasSideEffects())
6471 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6472 if (IA->isAlignStack())
6473 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6474 // Set the asm dialect.
6475 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6477 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6478 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6479 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6481 // Compute the constraint code and ConstraintType to use.
6482 TLI->ComputeConstraintToUse(OpInfo, SDValue());
6484 // Ideally, we would only check against memory constraints. However, the
6485 // meaning of an other constraint can be target-specific and we can't easily
6486 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6487 // for other constriants as well.
6488 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6489 OpInfo.ConstraintType == TargetLowering::C_Other) {
6490 if (OpInfo.Type == InlineAsm::isInput)
6491 ExtraInfo |= InlineAsm::Extra_MayLoad;
6492 else if (OpInfo.Type == InlineAsm::isOutput)
6493 ExtraInfo |= InlineAsm::Extra_MayStore;
6494 else if (OpInfo.Type == InlineAsm::isClobber)
6495 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6496 }
6497 }
6499 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
6500 TLI->getPointerTy()));
6502 // Loop over all of the inputs, copying the operand values into the
6503 // appropriate registers and processing the output regs.
6504 RegsForValue RetValRegs;
6506 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6507 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6509 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6510 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6512 switch (OpInfo.Type) {
6513 case InlineAsm::isOutput: {
6514 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6515 OpInfo.ConstraintType != TargetLowering::C_Register) {
6516 // Memory output, or 'other' output (e.g. 'X' constraint).
6517 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6519 // Add information to the INLINEASM node to know about this output.
6520 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6521 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
6522 TLI->getPointerTy()));
6523 AsmNodeOperands.push_back(OpInfo.CallOperand);
6524 break;
6525 }
6527 // Otherwise, this is a register or register class output.
6529 // Copy the output from the appropriate register. Find a register that
6530 // we can use.
6531 if (OpInfo.AssignedRegs.Regs.empty()) {
6532 LLVMContext &Ctx = *DAG.getContext();
6533 Ctx.emitError(CS.getInstruction(),
6534 "couldn't allocate output register for constraint '" +
6535 Twine(OpInfo.ConstraintCode) + "'");
6536 return;
6537 }
6539 // If this is an indirect operand, store through the pointer after the
6540 // asm.
6541 if (OpInfo.isIndirect) {
6542 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6543 OpInfo.CallOperandVal));
6544 } else {
6545 // This is the result value of the call.
6546 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6547 // Concatenate this output onto the outputs list.
6548 RetValRegs.append(OpInfo.AssignedRegs);
6549 }
6551 // Add information to the INLINEASM node to know that this register is
6552 // set.
6553 OpInfo.AssignedRegs
6554 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6555 ? InlineAsm::Kind_RegDefEarlyClobber
6556 : InlineAsm::Kind_RegDef,
6557 false, 0, DAG, AsmNodeOperands);
6558 break;
6559 }
6560 case InlineAsm::isInput: {
6561 SDValue InOperandVal = OpInfo.CallOperand;
6563 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6564 // If this is required to match an output register we have already set,
6565 // just use its register.
6566 unsigned OperandNo = OpInfo.getMatchedOperand();
6568 // Scan until we find the definition we already emitted of this operand.
6569 // When we find it, create a RegsForValue operand.
6570 unsigned CurOp = InlineAsm::Op_FirstOperand;
6571 for (; OperandNo; --OperandNo) {
6572 // Advance to the next operand.
6573 unsigned OpFlag =
6574 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6575 assert((InlineAsm::isRegDefKind(OpFlag) ||
6576 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6577 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6578 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6579 }
6581 unsigned OpFlag =
6582 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6583 if (InlineAsm::isRegDefKind(OpFlag) ||
6584 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6585 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6586 if (OpInfo.isIndirect) {
6587 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6588 LLVMContext &Ctx = *DAG.getContext();
6589 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6590 " don't know how to handle tied "
6591 "indirect register inputs");
6592 return;
6593 }
6595 RegsForValue MatchedRegs;
6596 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6597 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6598 MatchedRegs.RegVTs.push_back(RegVT);
6599 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6600 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6601 i != e; ++i) {
6602 if (const TargetRegisterClass *RC = TLI->getRegClassFor(RegVT))
6603 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6604 else {
6605 LLVMContext &Ctx = *DAG.getContext();
6606 Ctx.emitError(CS.getInstruction(),
6607 "inline asm error: This value"
6608 " type register class is not natively supported!");
6609 return;
6610 }
6611 }
6612 // Use the produced MatchedRegs object to
6613 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6614 Chain, &Flag, CS.getInstruction());
6615 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6616 true, OpInfo.getMatchedOperand(),
6617 DAG, AsmNodeOperands);
6618 break;
6619 }
6621 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6622 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6623 "Unexpected number of operands");
6624 // Add information to the INLINEASM node to know about this input.
6625 // See InlineAsm.h isUseOperandTiedToDef.
6626 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6627 OpInfo.getMatchedOperand());
6628 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
6629 TLI->getPointerTy()));
6630 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6631 break;
6632 }
6634 // Treat indirect 'X' constraint as memory.
6635 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6636 OpInfo.isIndirect)
6637 OpInfo.ConstraintType = TargetLowering::C_Memory;
6639 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6640 std::vector<SDValue> Ops;
6641 TLI->LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6642 Ops, DAG);
6643 if (Ops.empty()) {
6644 LLVMContext &Ctx = *DAG.getContext();
6645 Ctx.emitError(CS.getInstruction(),
6646 "invalid operand for inline asm constraint '" +
6647 Twine(OpInfo.ConstraintCode) + "'");
6648 return;
6649 }
6651 // Add information to the INLINEASM node to know about this input.
6652 unsigned ResOpType =
6653 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6654 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6655 TLI->getPointerTy()));
6656 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6657 break;
6658 }
6660 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6661 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6662 assert(InOperandVal.getValueType() == TLI->getPointerTy() &&
6663 "Memory operands expect pointer values");
6665 // Add information to the INLINEASM node to know about this input.
6666 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6667 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6668 TLI->getPointerTy()));
6669 AsmNodeOperands.push_back(InOperandVal);
6670 break;
6671 }
6673 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6674 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6675 "Unknown constraint type!");
6677 // TODO: Support this.
6678 if (OpInfo.isIndirect) {
6679 LLVMContext &Ctx = *DAG.getContext();
6680 Ctx.emitError(CS.getInstruction(),
6681 "Don't know how to handle indirect register inputs yet "
6682 "for constraint '" +
6683 Twine(OpInfo.ConstraintCode) + "'");
6684 return;
6685 }
6687 // Copy the input into the appropriate registers.
6688 if (OpInfo.AssignedRegs.Regs.empty()) {
6689 LLVMContext &Ctx = *DAG.getContext();
6690 Ctx.emitError(CS.getInstruction(),
6691 "couldn't allocate input reg for constraint '" +
6692 Twine(OpInfo.ConstraintCode) + "'");
6693 return;
6694 }
6696 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6697 Chain, &Flag, CS.getInstruction());
6699 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6700 DAG, AsmNodeOperands);
6701 break;
6702 }
6703 case InlineAsm::isClobber: {
6704 // Add the clobbered value to the operand list, so that the register
6705 // allocator is aware that the physreg got clobbered.
6706 if (!OpInfo.AssignedRegs.Regs.empty())
6707 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6708 false, 0, DAG,
6709 AsmNodeOperands);
6710 break;
6711 }
6712 }
6713 }
6715 // Finish up input operands. Set the input chain and add the flag last.
6716 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6717 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6719 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6720 DAG.getVTList(MVT::Other, MVT::Glue),
6721 &AsmNodeOperands[0], AsmNodeOperands.size());
6722 Flag = Chain.getValue(1);
6724 // If this asm returns a register value, copy the result from that register
6725 // and set it as the value of the call.
6726 if (!RetValRegs.Regs.empty()) {
6727 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6728 Chain, &Flag, CS.getInstruction());
6730 // FIXME: Why don't we do this for inline asms with MRVs?
6731 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6732 EVT ResultType = TLI->getValueType(CS.getType());
6734 // If any of the results of the inline asm is a vector, it may have the
6735 // wrong width/num elts. This can happen for register classes that can
6736 // contain multiple different value types. The preg or vreg allocated may
6737 // not have the same VT as was expected. Convert it to the right type
6738 // with bit_convert.
6739 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6740 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6741 ResultType, Val);
6743 } else if (ResultType != Val.getValueType() &&
6744 ResultType.isInteger() && Val.getValueType().isInteger()) {
6745 // If a result value was tied to an input value, the computed result may
6746 // have a wider width than the expected result. Extract the relevant
6747 // portion.
6748 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6749 }
6751 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6752 }
6754 setValue(CS.getInstruction(), Val);
6755 // Don't need to use this as a chain in this case.
6756 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6757 return;
6758 }
6760 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6762 // Process indirect outputs, first output all of the flagged copies out of
6763 // physregs.
6764 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6765 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6766 const Value *Ptr = IndirectStoresToEmit[i].second;
6767 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6768 Chain, &Flag, IA);
6769 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6770 }
6772 // Emit the non-flagged stores from the physregs.
6773 SmallVector<SDValue, 8> OutChains;
6774 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6775 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6776 StoresToEmit[i].first,
6777 getValue(StoresToEmit[i].second),
6778 MachinePointerInfo(StoresToEmit[i].second),
6779 false, false, 0);
6780 OutChains.push_back(Val);
6781 }
6783 if (!OutChains.empty())
6784 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
6785 &OutChains[0], OutChains.size());
6787 DAG.setRoot(Chain);
6788 }
6790 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6791 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6792 MVT::Other, getRoot(),
6793 getValue(I.getArgOperand(0)),
6794 DAG.getSrcValue(I.getArgOperand(0))));
6795 }
6797 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6798 const TargetLowering *TLI = TM.getTargetLowering();
6799 const DataLayout &DL = *TLI->getDataLayout();
6800 SDValue V = DAG.getVAArg(TLI->getValueType(I.getType()), getCurSDLoc(),
6801 getRoot(), getValue(I.getOperand(0)),
6802 DAG.getSrcValue(I.getOperand(0)),
6803 DL.getABITypeAlignment(I.getType()));
6804 setValue(&I, V);
6805 DAG.setRoot(V.getValue(1));
6806 }
6808 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6809 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6810 MVT::Other, getRoot(),
6811 getValue(I.getArgOperand(0)),
6812 DAG.getSrcValue(I.getArgOperand(0))));
6813 }
6815 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6816 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6817 MVT::Other, getRoot(),
6818 getValue(I.getArgOperand(0)),
6819 getValue(I.getArgOperand(1)),
6820 DAG.getSrcValue(I.getArgOperand(0)),
6821 DAG.getSrcValue(I.getArgOperand(1))));
6822 }
6824 /// \brief Lower an argument list according to the target calling convention.
6825 ///
6826 /// \return A tuple of <return-value, token-chain>
6827 ///
6828 /// This is a helper for lowering intrinsics that follow a target calling
6829 /// convention or require stack pointer adjustment. Only a subset of the
6830 /// intrinsic's operands need to participate in the calling convention.
6831 std::pair<SDValue, SDValue>
6832 SelectionDAGBuilder::LowerCallOperands(const CallInst &CI, unsigned ArgIdx,
6833 unsigned NumArgs, SDValue Callee,
6834 bool useVoidTy) {
6835 TargetLowering::ArgListTy Args;
6836 Args.reserve(NumArgs);
6838 // Populate the argument list.
6839 // Attributes for args start at offset 1, after the return attribute.
6840 ImmutableCallSite CS(&CI);
6841 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6842 ArgI != ArgE; ++ArgI) {
6843 const Value *V = CI.getOperand(ArgI);
6845 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6847 TargetLowering::ArgListEntry Entry;
6848 Entry.Node = getValue(V);
6849 Entry.Ty = V->getType();
6850 Entry.setAttributes(&CS, AttrI);
6851 Args.push_back(Entry);
6852 }
6854 Type *retTy = useVoidTy ? Type::getVoidTy(*DAG.getContext()) : CI.getType();
6855 TargetLowering::CallLoweringInfo CLI(getRoot(), retTy, /*retSExt*/ false,
6856 /*retZExt*/ false, /*isVarArg*/ false, /*isInReg*/ false, NumArgs,
6857 CI.getCallingConv(), /*isTailCall*/ false, /*doesNotReturn*/ false,
6858 /*isReturnValueUsed*/ CI.use_empty(), Callee, Args, DAG, getCurSDLoc());
6860 const TargetLowering *TLI = TM.getTargetLowering();
6861 return TLI->LowerCallTo(CLI);
6862 }
6864 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6865 /// or patchpoint target node's operand list.
6866 ///
6867 /// Constants are converted to TargetConstants purely as an optimization to
6868 /// avoid constant materialization and register allocation.
6869 ///
6870 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6871 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6872 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6873 /// address materialization and register allocation, but may also be required
6874 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6875 /// alloca in the entry block, then the runtime may assume that the alloca's
6876 /// StackMap location can be read immediately after compilation and that the
6877 /// location is valid at any point during execution (this is similar to the
6878 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6879 /// only available in a register, then the runtime would need to trap when
6880 /// execution reaches the StackMap in order to read the alloca's location.
6881 static void addStackMapLiveVars(const CallInst &CI, unsigned StartIdx,
6882 SmallVectorImpl<SDValue> &Ops,
6883 SelectionDAGBuilder &Builder) {
6884 for (unsigned i = StartIdx, e = CI.getNumArgOperands(); i != e; ++i) {
6885 SDValue OpVal = Builder.getValue(CI.getArgOperand(i));
6886 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6887 Ops.push_back(
6888 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, MVT::i64));
6889 Ops.push_back(
6890 Builder.DAG.getTargetConstant(C->getSExtValue(), MVT::i64));
6891 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6892 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6893 Ops.push_back(
6894 Builder.DAG.getTargetFrameIndex(FI->getIndex(), TLI.getPointerTy()));
6895 } else
6896 Ops.push_back(OpVal);
6897 }
6898 }
6900 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6901 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6902 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6903 // [live variables...])
6905 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6907 SDValue Chain, InFlag, Callee, NullPtr;
6908 SmallVector<SDValue, 32> Ops;
6910 SDLoc DL = getCurSDLoc();
6911 Callee = getValue(CI.getCalledValue());
6912 NullPtr = DAG.getIntPtrConstant(0, true);
6914 // The stackmap intrinsic only records the live variables (the arguemnts
6915 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6916 // intrinsic, this won't be lowered to a function call. This means we don't
6917 // have to worry about calling conventions and target specific lowering code.
6918 // Instead we perform the call lowering right here.
6919 //
6920 // chain, flag = CALLSEQ_START(chain, 0)
6921 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6922 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6923 //
6924 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6925 InFlag = Chain.getValue(1);
6927 // Add the <id> and <numBytes> constants.
6928 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6929 Ops.push_back(DAG.getTargetConstant(
6930 cast<ConstantSDNode>(IDVal)->getZExtValue(), MVT::i64));
6931 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6932 Ops.push_back(DAG.getTargetConstant(
6933 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), MVT::i32));
6935 // Push live variables for the stack map.
6936 addStackMapLiveVars(CI, 2, Ops, *this);
6938 // We are not pushing any register mask info here on the operands list,
6939 // because the stackmap doesn't clobber anything.
6941 // Push the chain and the glue flag.
6942 Ops.push_back(Chain);
6943 Ops.push_back(InFlag);
6945 // Create the STACKMAP node.
6946 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6947 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6948 Chain = SDValue(SM, 0);
6949 InFlag = Chain.getValue(1);
6951 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6953 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6955 // Set the root to the target-lowered call chain.
6956 DAG.setRoot(Chain);
6958 // Inform the Frame Information that we have a stackmap in this function.
6959 FuncInfo.MF->getFrameInfo()->setHasStackMap();
6960 }
6962 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
6963 void SelectionDAGBuilder::visitPatchpoint(const CallInst &CI) {
6964 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
6965 // i32 <numBytes>,
6966 // i8* <target>,
6967 // i32 <numArgs>,
6968 // [Args...],
6969 // [live variables...])
6971 CallingConv::ID CC = CI.getCallingConv();
6972 bool isAnyRegCC = CC == CallingConv::AnyReg;
6973 bool hasDef = !CI.getType()->isVoidTy();
6974 SDValue Callee = getValue(CI.getOperand(2)); // <target>
6976 // Get the real number of arguments participating in the call <numArgs>
6977 SDValue NArgVal = getValue(CI.getArgOperand(PatchPointOpers::NArgPos));
6978 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
6980 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
6981 // Intrinsics include all meta-operands up to but not including CC.
6982 unsigned NumMetaOpers = PatchPointOpers::CCPos;
6983 assert(CI.getNumArgOperands() >= NumMetaOpers + NumArgs &&
6984 "Not enough arguments provided to the patchpoint intrinsic");
6986 // For AnyRegCC the arguments are lowered later on manually.
6987 unsigned NumCallArgs = isAnyRegCC ? 0 : NumArgs;
6988 std::pair<SDValue, SDValue> Result =
6989 LowerCallOperands(CI, NumMetaOpers, NumCallArgs, Callee, isAnyRegCC);
6991 // Set the root to the target-lowered call chain.
6992 SDValue Chain = Result.second;
6993 DAG.setRoot(Chain);
6995 SDNode *CallEnd = Chain.getNode();
6996 if (hasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
6997 CallEnd = CallEnd->getOperand(0).getNode();
6999 /// Get a call instruction from the call sequence chain.
7000 /// Tail calls are not allowed.
7001 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
7002 "Expected a callseq node.");
7003 SDNode *Call = CallEnd->getOperand(0).getNode();
7004 bool hasGlue = Call->getGluedNode();
7006 // Replace the target specific call node with the patchable intrinsic.
7007 SmallVector<SDValue, 8> Ops;
7009 // Add the <id> and <numBytes> constants.
7010 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
7011 Ops.push_back(DAG.getTargetConstant(
7012 cast<ConstantSDNode>(IDVal)->getZExtValue(), MVT::i64));
7013 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
7014 Ops.push_back(DAG.getTargetConstant(
7015 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), MVT::i32));
7017 // Assume that the Callee is a constant address.
7018 // FIXME: handle function symbols in the future.
7019 Ops.push_back(
7020 DAG.getIntPtrConstant(cast<ConstantSDNode>(Callee)->getZExtValue(),
7021 /*isTarget=*/true));
7023 // Adjust <numArgs> to account for any arguments that have been passed on the
7024 // stack instead.
7025 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
7026 unsigned NumCallRegArgs = Call->getNumOperands() - (hasGlue ? 4 : 3);
7027 NumCallRegArgs = isAnyRegCC ? NumArgs : NumCallRegArgs;
7028 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, MVT::i32));
7030 // Add the calling convention
7031 Ops.push_back(DAG.getTargetConstant((unsigned)CC, MVT::i32));
7033 // Add the arguments we omitted previously. The register allocator should
7034 // place these in any free register.
7035 if (isAnyRegCC)
7036 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
7037 Ops.push_back(getValue(CI.getArgOperand(i)));
7039 // Push the arguments from the call instruction up to the register mask.
7040 SDNode::op_iterator e = hasGlue ? Call->op_end()-2 : Call->op_end()-1;
7041 for (SDNode::op_iterator i = Call->op_begin()+2; i != e; ++i)
7042 Ops.push_back(*i);
7044 // Push live variables for the stack map.
7045 addStackMapLiveVars(CI, NumMetaOpers + NumArgs, Ops, *this);
7047 // Push the register mask info.
7048 if (hasGlue)
7049 Ops.push_back(*(Call->op_end()-2));
7050 else
7051 Ops.push_back(*(Call->op_end()-1));
7053 // Push the chain (this is originally the first operand of the call, but
7054 // becomes now the last or second to last operand).
7055 Ops.push_back(*(Call->op_begin()));
7057 // Push the glue flag (last operand).
7058 if (hasGlue)
7059 Ops.push_back(*(Call->op_end()-1));
7061 SDVTList NodeTys;
7062 if (isAnyRegCC && hasDef) {
7063 // Create the return types based on the intrinsic definition
7064 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7065 SmallVector<EVT, 3> ValueVTs;
7066 ComputeValueVTs(TLI, CI.getType(), ValueVTs);
7067 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
7069 // There is always a chain and a glue type at the end
7070 ValueVTs.push_back(MVT::Other);
7071 ValueVTs.push_back(MVT::Glue);
7072 NodeTys = DAG.getVTList(ValueVTs);
7073 } else
7074 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7076 // Replace the target specific call node with a PATCHPOINT node.
7077 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
7078 getCurSDLoc(), NodeTys, Ops);
7080 // Update the NodeMap.
7081 if (hasDef) {
7082 if (isAnyRegCC)
7083 setValue(&CI, SDValue(MN, 0));
7084 else
7085 setValue(&CI, Result.first);
7086 }
7088 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
7089 // call sequence. Furthermore the location of the chain and glue can change
7090 // when the AnyReg calling convention is used and the intrinsic returns a
7091 // value.
7092 if (isAnyRegCC && hasDef) {
7093 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
7094 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
7095 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
7096 } else
7097 DAG.ReplaceAllUsesWith(Call, MN);
7098 DAG.DeleteNode(Call);
7100 // Inform the Frame Information that we have a patchpoint in this function.
7101 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
7102 }
7104 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
7105 /// implementation, which just calls LowerCall.
7106 /// FIXME: When all targets are
7107 /// migrated to using LowerCall, this hook should be integrated into SDISel.
7108 std::pair<SDValue, SDValue>
7109 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
7110 // Handle the incoming return values from the call.
7111 CLI.Ins.clear();
7112 SmallVector<EVT, 4> RetTys;
7113 ComputeValueVTs(*this, CLI.RetTy, RetTys);
7114 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7115 EVT VT = RetTys[I];
7116 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7117 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7118 for (unsigned i = 0; i != NumRegs; ++i) {
7119 ISD::InputArg MyFlags;
7120 MyFlags.VT = RegisterVT;
7121 MyFlags.ArgVT = VT;
7122 MyFlags.Used = CLI.IsReturnValueUsed;
7123 if (CLI.RetSExt)
7124 MyFlags.Flags.setSExt();
7125 if (CLI.RetZExt)
7126 MyFlags.Flags.setZExt();
7127 if (CLI.IsInReg)
7128 MyFlags.Flags.setInReg();
7129 CLI.Ins.push_back(MyFlags);
7130 }
7131 }
7133 // Handle all of the outgoing arguments.
7134 CLI.Outs.clear();
7135 CLI.OutVals.clear();
7136 ArgListTy &Args = CLI.Args;
7137 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
7138 SmallVector<EVT, 4> ValueVTs;
7139 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
7140 for (unsigned Value = 0, NumValues = ValueVTs.size();
7141 Value != NumValues; ++Value) {
7142 EVT VT = ValueVTs[Value];
7143 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
7144 SDValue Op = SDValue(Args[i].Node.getNode(),
7145 Args[i].Node.getResNo() + Value);
7146 ISD::ArgFlagsTy Flags;
7147 unsigned OriginalAlignment = getDataLayout()->getABITypeAlignment(ArgTy);
7149 if (Args[i].isZExt)
7150 Flags.setZExt();
7151 if (Args[i].isSExt)
7152 Flags.setSExt();
7153 if (Args[i].isInReg)
7154 Flags.setInReg();
7155 if (Args[i].isSRet)
7156 Flags.setSRet();
7157 if (Args[i].isByVal)
7158 Flags.setByVal();
7159 if (Args[i].isInAlloca) {
7160 Flags.setInAlloca();
7161 // Set the byval flag for CCAssignFn callbacks that don't know about
7162 // inalloca. This way we can know how many bytes we should've allocated
7163 // and how many bytes a callee cleanup function will pop. If we port
7164 // inalloca to more targets, we'll have to add custom inalloca handling
7165 // in the various CC lowering callbacks.
7166 Flags.setByVal();
7167 }
7168 if (Args[i].isByVal || Args[i].isInAlloca) {
7169 PointerType *Ty = cast<PointerType>(Args[i].Ty);
7170 Type *ElementTy = Ty->getElementType();
7171 Flags.setByValSize(getDataLayout()->getTypeAllocSize(ElementTy));
7172 // For ByVal, alignment should come from FE. BE will guess if this
7173 // info is not there but there are cases it cannot get right.
7174 unsigned FrameAlign;
7175 if (Args[i].Alignment)
7176 FrameAlign = Args[i].Alignment;
7177 else
7178 FrameAlign = getByValTypeAlignment(ElementTy);
7179 Flags.setByValAlign(FrameAlign);
7180 }
7181 if (Args[i].isNest)
7182 Flags.setNest();
7183 Flags.setOrigAlign(OriginalAlignment);
7185 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
7186 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
7187 SmallVector<SDValue, 4> Parts(NumParts);
7188 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
7190 if (Args[i].isSExt)
7191 ExtendKind = ISD::SIGN_EXTEND;
7192 else if (Args[i].isZExt)
7193 ExtendKind = ISD::ZERO_EXTEND;
7195 // Conservatively only handle 'returned' on non-vectors for now
7196 if (Args[i].isReturned && !Op.getValueType().isVector()) {
7197 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
7198 "unexpected use of 'returned'");
7199 // Before passing 'returned' to the target lowering code, ensure that
7200 // either the register MVT and the actual EVT are the same size or that
7201 // the return value and argument are extended in the same way; in these
7202 // cases it's safe to pass the argument register value unchanged as the
7203 // return register value (although it's at the target's option whether
7204 // to do so)
7205 // TODO: allow code generation to take advantage of partially preserved
7206 // registers rather than clobbering the entire register when the
7207 // parameter extension method is not compatible with the return
7208 // extension method
7209 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
7210 (ExtendKind != ISD::ANY_EXTEND &&
7211 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
7212 Flags.setReturned();
7213 }
7215 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
7216 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
7218 for (unsigned j = 0; j != NumParts; ++j) {
7219 // if it isn't first piece, alignment must be 1
7220 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7221 i < CLI.NumFixedArgs,
7222 i, j*Parts[j].getValueType().getStoreSize());
7223 if (NumParts > 1 && j == 0)
7224 MyFlags.Flags.setSplit();
7225 else if (j != 0)
7226 MyFlags.Flags.setOrigAlign(1);
7228 CLI.Outs.push_back(MyFlags);
7229 CLI.OutVals.push_back(Parts[j]);
7230 }
7231 }
7232 }
7234 SmallVector<SDValue, 4> InVals;
7235 CLI.Chain = LowerCall(CLI, InVals);
7237 // Verify that the target's LowerCall behaved as expected.
7238 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7239 "LowerCall didn't return a valid chain!");
7240 assert((!CLI.IsTailCall || InVals.empty()) &&
7241 "LowerCall emitted a return value for a tail call!");
7242 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7243 "LowerCall didn't emit the correct number of values!");
7245 // For a tail call, the return value is merely live-out and there aren't
7246 // any nodes in the DAG representing it. Return a special value to
7247 // indicate that a tail call has been emitted and no more Instructions
7248 // should be processed in the current block.
7249 if (CLI.IsTailCall) {
7250 CLI.DAG.setRoot(CLI.Chain);
7251 return std::make_pair(SDValue(), SDValue());
7252 }
7254 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7255 assert(InVals[i].getNode() &&
7256 "LowerCall emitted a null value!");
7257 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7258 "LowerCall emitted a value with the wrong type!");
7259 });
7261 // Collect the legal value parts into potentially illegal values
7262 // that correspond to the original function's return values.
7263 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7264 if (CLI.RetSExt)
7265 AssertOp = ISD::AssertSext;
7266 else if (CLI.RetZExt)
7267 AssertOp = ISD::AssertZext;
7268 SmallVector<SDValue, 4> ReturnValues;
7269 unsigned CurReg = 0;
7270 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7271 EVT VT = RetTys[I];
7272 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7273 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7275 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7276 NumRegs, RegisterVT, VT, nullptr,
7277 AssertOp));
7278 CurReg += NumRegs;
7279 }
7281 // For a function returning void, there is no return value. We can't create
7282 // such a node, so we just return a null return value in that case. In
7283 // that case, nothing will actually look at the value.
7284 if (ReturnValues.empty())
7285 return std::make_pair(SDValue(), CLI.Chain);
7287 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7288 CLI.DAG.getVTList(RetTys),
7289 &ReturnValues[0], ReturnValues.size());
7290 return std::make_pair(Res, CLI.Chain);
7291 }
7293 void TargetLowering::LowerOperationWrapper(SDNode *N,
7294 SmallVectorImpl<SDValue> &Results,
7295 SelectionDAG &DAG) const {
7296 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7297 if (Res.getNode())
7298 Results.push_back(Res);
7299 }
7301 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7302 llvm_unreachable("LowerOperation not implemented for this target!");
7303 }
7305 void
7306 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7307 SDValue Op = getNonRegisterValue(V);
7308 assert((Op.getOpcode() != ISD::CopyFromReg ||
7309 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7310 "Copy from a reg to the same reg!");
7311 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7313 const TargetLowering *TLI = TM.getTargetLowering();
7314 RegsForValue RFV(V->getContext(), *TLI, Reg, V->getType());
7315 SDValue Chain = DAG.getEntryNode();
7316 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V);
7317 PendingExports.push_back(Chain);
7318 }
7320 #include "llvm/CodeGen/SelectionDAGISel.h"
7322 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7323 /// entry block, return true. This includes arguments used by switches, since
7324 /// the switch may expand into multiple basic blocks.
7325 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7326 // With FastISel active, we may be splitting blocks, so force creation
7327 // of virtual registers for all non-dead arguments.
7328 if (FastISel)
7329 return A->use_empty();
7331 const BasicBlock *Entry = A->getParent()->begin();
7332 for (const User *U : A->users())
7333 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
7334 return false; // Use not in entry block.
7336 return true;
7337 }
7339 void SelectionDAGISel::LowerArguments(const Function &F) {
7340 SelectionDAG &DAG = SDB->DAG;
7341 SDLoc dl = SDB->getCurSDLoc();
7342 const TargetLowering *TLI = getTargetLowering();
7343 const DataLayout *DL = TLI->getDataLayout();
7344 SmallVector<ISD::InputArg, 16> Ins;
7346 if (!FuncInfo->CanLowerReturn) {
7347 // Put in an sret pointer parameter before all the other parameters.
7348 SmallVector<EVT, 1> ValueVTs;
7349 ComputeValueVTs(*getTargetLowering(),
7350 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7352 // NOTE: Assuming that a pointer will never break down to more than one VT
7353 // or one register.
7354 ISD::ArgFlagsTy Flags;
7355 Flags.setSRet();
7356 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7357 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true, 0, 0);
7358 Ins.push_back(RetArg);
7359 }
7361 // Set up the incoming argument description vector.
7362 unsigned Idx = 1;
7363 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7364 I != E; ++I, ++Idx) {
7365 SmallVector<EVT, 4> ValueVTs;
7366 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7367 bool isArgValueUsed = !I->use_empty();
7368 unsigned PartBase = 0;
7369 for (unsigned Value = 0, NumValues = ValueVTs.size();
7370 Value != NumValues; ++Value) {
7371 EVT VT = ValueVTs[Value];
7372 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7373 ISD::ArgFlagsTy Flags;
7374 unsigned OriginalAlignment = DL->getABITypeAlignment(ArgTy);
7376 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7377 Flags.setZExt();
7378 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7379 Flags.setSExt();
7380 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7381 Flags.setInReg();
7382 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7383 Flags.setSRet();
7384 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7385 Flags.setByVal();
7386 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7387 Flags.setInAlloca();
7388 // Set the byval flag for CCAssignFn callbacks that don't know about
7389 // inalloca. This way we can know how many bytes we should've allocated
7390 // and how many bytes a callee cleanup function will pop. If we port
7391 // inalloca to more targets, we'll have to add custom inalloca handling
7392 // in the various CC lowering callbacks.
7393 Flags.setByVal();
7394 }
7395 if (Flags.isByVal() || Flags.isInAlloca()) {
7396 PointerType *Ty = cast<PointerType>(I->getType());
7397 Type *ElementTy = Ty->getElementType();
7398 Flags.setByValSize(DL->getTypeAllocSize(ElementTy));
7399 // For ByVal, alignment should be passed from FE. BE will guess if
7400 // this info is not there but there are cases it cannot get right.
7401 unsigned FrameAlign;
7402 if (F.getParamAlignment(Idx))
7403 FrameAlign = F.getParamAlignment(Idx);
7404 else
7405 FrameAlign = TLI->getByValTypeAlignment(ElementTy);
7406 Flags.setByValAlign(FrameAlign);
7407 }
7408 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7409 Flags.setNest();
7410 Flags.setOrigAlign(OriginalAlignment);
7412 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7413 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7414 for (unsigned i = 0; i != NumRegs; ++i) {
7415 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7416 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7417 if (NumRegs > 1 && i == 0)
7418 MyFlags.Flags.setSplit();
7419 // if it isn't first piece, alignment must be 1
7420 else if (i > 0)
7421 MyFlags.Flags.setOrigAlign(1);
7422 Ins.push_back(MyFlags);
7423 }
7424 PartBase += VT.getStoreSize();
7425 }
7426 }
7428 // Call the target to set up the argument values.
7429 SmallVector<SDValue, 8> InVals;
7430 SDValue NewRoot = TLI->LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
7431 F.isVarArg(), Ins,
7432 dl, DAG, InVals);
7434 // Verify that the target's LowerFormalArguments behaved as expected.
7435 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7436 "LowerFormalArguments didn't return a valid chain!");
7437 assert(InVals.size() == Ins.size() &&
7438 "LowerFormalArguments didn't emit the correct number of values!");
7439 DEBUG({
7440 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7441 assert(InVals[i].getNode() &&
7442 "LowerFormalArguments emitted a null value!");
7443 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7444 "LowerFormalArguments emitted a value with the wrong type!");
7445 }
7446 });
7448 // Update the DAG with the new chain value resulting from argument lowering.
7449 DAG.setRoot(NewRoot);
7451 // Set up the argument values.
7452 unsigned i = 0;
7453 Idx = 1;
7454 if (!FuncInfo->CanLowerReturn) {
7455 // Create a virtual register for the sret pointer, and put in a copy
7456 // from the sret argument into it.
7457 SmallVector<EVT, 1> ValueVTs;
7458 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
7459 MVT VT = ValueVTs[0].getSimpleVT();
7460 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7461 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7462 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7463 RegVT, VT, nullptr, AssertOp);
7465 MachineFunction& MF = SDB->DAG.getMachineFunction();
7466 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7467 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7468 FuncInfo->DemoteRegister = SRetReg;
7469 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(),
7470 SRetReg, ArgValue);
7471 DAG.setRoot(NewRoot);
7473 // i indexes lowered arguments. Bump it past the hidden sret argument.
7474 // Idx indexes LLVM arguments. Don't touch it.
7475 ++i;
7476 }
7478 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7479 ++I, ++Idx) {
7480 SmallVector<SDValue, 4> ArgValues;
7481 SmallVector<EVT, 4> ValueVTs;
7482 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7483 unsigned NumValues = ValueVTs.size();
7485 // If this argument is unused then remember its value. It is used to generate
7486 // debugging information.
7487 if (I->use_empty() && NumValues) {
7488 SDB->setUnusedArgValue(I, InVals[i]);
7490 // Also remember any frame index for use in FastISel.
7491 if (FrameIndexSDNode *FI =
7492 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7493 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7494 }
7496 for (unsigned Val = 0; Val != NumValues; ++Val) {
7497 EVT VT = ValueVTs[Val];
7498 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7499 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7501 if (!I->use_empty()) {
7502 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7503 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7504 AssertOp = ISD::AssertSext;
7505 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7506 AssertOp = ISD::AssertZext;
7508 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7509 NumParts, PartVT, VT,
7510 nullptr, AssertOp));
7511 }
7513 i += NumParts;
7514 }
7516 // We don't need to do anything else for unused arguments.
7517 if (ArgValues.empty())
7518 continue;
7520 // Note down frame index.
7521 if (FrameIndexSDNode *FI =
7522 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7523 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7525 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues,
7526 SDB->getCurSDLoc());
7528 SDB->setValue(I, Res);
7529 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7530 if (LoadSDNode *LNode =
7531 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7532 if (FrameIndexSDNode *FI =
7533 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7534 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7535 }
7537 // If this argument is live outside of the entry block, insert a copy from
7538 // wherever we got it to the vreg that other BB's will reference it as.
7539 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7540 // If we can, though, try to skip creating an unnecessary vreg.
7541 // FIXME: This isn't very clean... it would be nice to make this more
7542 // general. It's also subtly incompatible with the hacks FastISel
7543 // uses with vregs.
7544 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7545 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7546 FuncInfo->ValueMap[I] = Reg;
7547 continue;
7548 }
7549 }
7550 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
7551 FuncInfo->InitializeRegForValue(I);
7552 SDB->CopyToExportRegsIfNeeded(I);
7553 }
7554 }
7556 assert(i == InVals.size() && "Argument register count mismatch!");
7558 // Finally, if the target has anything special to do, allow it to do so.
7559 // FIXME: this should insert code into the DAG!
7560 EmitFunctionEntryCode();
7561 }
7563 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7564 /// ensure constants are generated when needed. Remember the virtual registers
7565 /// that need to be added to the Machine PHI nodes as input. We cannot just
7566 /// directly add them, because expansion might result in multiple MBB's for one
7567 /// BB. As such, the start of the BB might correspond to a different MBB than
7568 /// the end.
7569 ///
7570 void
7571 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7572 const TerminatorInst *TI = LLVMBB->getTerminator();
7574 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7576 // Check successor nodes' PHI nodes that expect a constant to be available
7577 // from this block.
7578 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7579 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7580 if (!isa<PHINode>(SuccBB->begin())) continue;
7581 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7583 // If this terminator has multiple identical successors (common for
7584 // switches), only handle each succ once.
7585 if (!SuccsHandled.insert(SuccMBB)) continue;
7587 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7589 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7590 // nodes and Machine PHI nodes, but the incoming operands have not been
7591 // emitted yet.
7592 for (BasicBlock::const_iterator I = SuccBB->begin();
7593 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7594 // Ignore dead phi's.
7595 if (PN->use_empty()) continue;
7597 // Skip empty types
7598 if (PN->getType()->isEmptyTy())
7599 continue;
7601 unsigned Reg;
7602 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7604 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7605 unsigned &RegOut = ConstantsOut[C];
7606 if (RegOut == 0) {
7607 RegOut = FuncInfo.CreateRegs(C->getType());
7608 CopyValueToVirtualRegister(C, RegOut);
7609 }
7610 Reg = RegOut;
7611 } else {
7612 DenseMap<const Value *, unsigned>::iterator I =
7613 FuncInfo.ValueMap.find(PHIOp);
7614 if (I != FuncInfo.ValueMap.end())
7615 Reg = I->second;
7616 else {
7617 assert(isa<AllocaInst>(PHIOp) &&
7618 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7619 "Didn't codegen value into a register!??");
7620 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7621 CopyValueToVirtualRegister(PHIOp, Reg);
7622 }
7623 }
7625 // Remember that this register needs to added to the machine PHI node as
7626 // the input for this MBB.
7627 SmallVector<EVT, 4> ValueVTs;
7628 const TargetLowering *TLI = TM.getTargetLowering();
7629 ComputeValueVTs(*TLI, PN->getType(), ValueVTs);
7630 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7631 EVT VT = ValueVTs[vti];
7632 unsigned NumRegisters = TLI->getNumRegisters(*DAG.getContext(), VT);
7633 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7634 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7635 Reg += NumRegisters;
7636 }
7637 }
7638 }
7640 ConstantsOut.clear();
7641 }
7643 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7644 /// is 0.
7645 MachineBasicBlock *
7646 SelectionDAGBuilder::StackProtectorDescriptor::
7647 AddSuccessorMBB(const BasicBlock *BB,
7648 MachineBasicBlock *ParentMBB,
7649 MachineBasicBlock *SuccMBB) {
7650 // If SuccBB has not been created yet, create it.
7651 if (!SuccMBB) {
7652 MachineFunction *MF = ParentMBB->getParent();
7653 MachineFunction::iterator BBI = ParentMBB;
7654 SuccMBB = MF->CreateMachineBasicBlock(BB);
7655 MF->insert(++BBI, SuccMBB);
7656 }
7657 // Add it as a successor of ParentMBB.
7658 ParentMBB->addSuccessor(SuccMBB);
7659 return SuccMBB;
7660 }