1 //===-- SelectionDAGBuilder.h - Selection-DAG building --------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
11 //
12 //===----------------------------------------------------------------------===//
14 #ifndef SELECTIONDAGBUILDER_H
15 #define SELECTIONDAGBUILDER_H
17 #include "llvm/Constants.h"
18 #include "llvm/CodeGen/SelectionDAG.h"
19 #include "llvm/ADT/APInt.h"
20 #include "llvm/ADT/DenseMap.h"
21 #include "llvm/CodeGen/SelectionDAGNodes.h"
22 #include "llvm/CodeGen/ValueTypes.h"
23 #include "llvm/Support/CallSite.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include <vector>
27 namespace llvm {
29 class AliasAnalysis;
30 class AllocaInst;
31 class BasicBlock;
32 class BitCastInst;
33 class BranchInst;
34 class CallInst;
35 class DbgValueInst;
36 class ExtractElementInst;
37 class ExtractValueInst;
38 class FCmpInst;
39 class FPExtInst;
40 class FPToSIInst;
41 class FPToUIInst;
42 class FPTruncInst;
43 class Function;
44 class FunctionLoweringInfo;
45 class GetElementPtrInst;
46 class GCFunctionInfo;
47 class ICmpInst;
48 class IntToPtrInst;
49 class IndirectBrInst;
50 class InvokeInst;
51 class InsertElementInst;
52 class InsertValueInst;
53 class Instruction;
54 class LoadInst;
55 class MachineBasicBlock;
56 class MachineInstr;
57 class MachineRegisterInfo;
58 class MDNode;
59 class PHINode;
60 class PtrToIntInst;
61 class ReturnInst;
62 class SDDbgValue;
63 class SExtInst;
64 class SelectInst;
65 class ShuffleVectorInst;
66 class SIToFPInst;
67 class StoreInst;
68 class SwitchInst;
69 class TargetData;
70 class TargetLowering;
71 class TruncInst;
72 class UIToFPInst;
73 class UnreachableInst;
74 class UnwindInst;
75 class VAArgInst;
76 class ZExtInst;
78 //===----------------------------------------------------------------------===//
79 /// SelectionDAGBuilder - This is the common target-independent lowering
80 /// implementation that is parameterized by a TargetLowering object.
81 ///
82 class SelectionDAGBuilder {
83 /// CurDebugLoc - current file + line number. Changes as we build the DAG.
84 DebugLoc CurDebugLoc;
86 DenseMap<const Value*, SDValue> NodeMap;
88 /// UnusedArgNodeMap - Maps argument value for unused arguments. This is used
89 /// to preserve debug information for incoming arguments.
90 DenseMap<const Value*, SDValue> UnusedArgNodeMap;
92 /// DanglingDebugInfo - Helper type for DanglingDebugInfoMap.
93 class DanglingDebugInfo {
94 const DbgValueInst* DI;
95 DebugLoc dl;
96 unsigned SDNodeOrder;
97 public:
98 DanglingDebugInfo() : DI(0), dl(DebugLoc()), SDNodeOrder(0) { }
99 DanglingDebugInfo(const DbgValueInst *di, DebugLoc DL, unsigned SDNO) :
100 DI(di), dl(DL), SDNodeOrder(SDNO) { }
101 const DbgValueInst* getDI() { return DI; }
102 DebugLoc getdl() { return dl; }
103 unsigned getSDNodeOrder() { return SDNodeOrder; }
104 };
106 /// DanglingDebugInfoMap - Keeps track of dbg_values for which we have not
107 /// yet seen the referent. We defer handling these until we do see it.
108 DenseMap<const Value*, DanglingDebugInfo> DanglingDebugInfoMap;
110 public:
111 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
112 /// them up and then emit token factor nodes when possible. This allows us to
113 /// get simple disambiguation between loads without worrying about alias
114 /// analysis.
115 SmallVector<SDValue, 8> PendingLoads;
116 private:
118 /// PendingExports - CopyToReg nodes that copy values to virtual registers
119 /// for export to other blocks need to be emitted before any terminator
120 /// instruction, but they have no other ordering requirements. We bunch them
121 /// up and the emit a single tokenfactor for them just before terminator
122 /// instructions.
123 SmallVector<SDValue, 8> PendingExports;
125 /// SDNodeOrder - A unique monotonically increasing number used to order the
126 /// SDNodes we create.
127 unsigned SDNodeOrder;
129 /// Case - A struct to record the Value for a switch case, and the
130 /// case's target basic block.
131 struct Case {
132 Constant* Low;
133 Constant* High;
134 MachineBasicBlock* BB;
135 uint32_t ExtraWeight;
137 Case() : Low(0), High(0), BB(0), ExtraWeight(0) { }
138 Case(Constant* low, Constant* high, MachineBasicBlock* bb,
139 uint32_t extraweight) : Low(low), High(high), BB(bb),
140 ExtraWeight(extraweight) { }
142 APInt size() const {
143 const APInt &rHigh = cast<ConstantInt>(High)->getValue();
144 const APInt &rLow = cast<ConstantInt>(Low)->getValue();
145 return (rHigh - rLow + 1ULL);
146 }
147 };
149 struct CaseBits {
150 uint64_t Mask;
151 MachineBasicBlock* BB;
152 unsigned Bits;
154 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits):
155 Mask(mask), BB(bb), Bits(bits) { }
156 };
158 typedef std::vector<Case> CaseVector;
159 typedef std::vector<CaseBits> CaseBitsVector;
160 typedef CaseVector::iterator CaseItr;
161 typedef std::pair<CaseItr, CaseItr> CaseRange;
163 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
164 /// of conditional branches.
165 struct CaseRec {
166 CaseRec(MachineBasicBlock *bb, const Constant *lt, const Constant *ge,
167 CaseRange r) :
168 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
170 /// CaseBB - The MBB in which to emit the compare and branch
171 MachineBasicBlock *CaseBB;
172 /// LT, GE - If nonzero, we know the current case value must be less-than or
173 /// greater-than-or-equal-to these Constants.
174 const Constant *LT;
175 const Constant *GE;
176 /// Range - A pair of iterators representing the range of case values to be
177 /// processed at this point in the binary search tree.
178 CaseRange Range;
179 };
181 typedef std::vector<CaseRec> CaseRecVector;
183 /// The comparison function for sorting the switch case values in the vector.
184 /// WARNING: Case ranges should be disjoint!
185 struct CaseCmp {
186 bool operator()(const Case &C1, const Case &C2) {
187 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
188 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
189 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
190 return CI1->getValue().slt(CI2->getValue());
191 }
192 };
194 struct CaseBitsCmp {
195 bool operator()(const CaseBits &C1, const CaseBits &C2) {
196 return C1.Bits > C2.Bits;
197 }
198 };
200 size_t Clusterify(CaseVector &Cases, const SwitchInst &SI);
202 /// CaseBlock - This structure is used to communicate between
203 /// SelectionDAGBuilder and SDISel for the code generation of additional basic
204 /// blocks needed by multi-case switch statements.
205 struct CaseBlock {
206 CaseBlock(ISD::CondCode cc, const Value *cmplhs, const Value *cmprhs,
207 const Value *cmpmiddle,
208 MachineBasicBlock *truebb, MachineBasicBlock *falsebb,
209 MachineBasicBlock *me,
210 uint32_t trueweight = 0, uint32_t falseweight = 0)
211 : CC(cc), CmpLHS(cmplhs), CmpMHS(cmpmiddle), CmpRHS(cmprhs),
212 TrueBB(truebb), FalseBB(falsebb), ThisBB(me),
213 TrueWeight(trueweight), FalseWeight(falseweight) { }
215 // CC - the condition code to use for the case block's setcc node
216 ISD::CondCode CC;
218 // CmpLHS/CmpRHS/CmpMHS - The LHS/MHS/RHS of the comparison to emit.
219 // Emit by default LHS op RHS. MHS is used for range comparisons:
220 // If MHS is not null: (LHS <= MHS) and (MHS <= RHS).
221 const Value *CmpLHS, *CmpMHS, *CmpRHS;
223 // TrueBB/FalseBB - the block to branch to if the setcc is true/false.
224 MachineBasicBlock *TrueBB, *FalseBB;
226 // ThisBB - the block into which to emit the code for the setcc and branches
227 MachineBasicBlock *ThisBB;
229 // TrueWeight/FalseWeight - branch weights.
230 uint32_t TrueWeight, FalseWeight;
231 };
233 struct JumpTable {
234 JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
235 MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
237 /// Reg - the virtual register containing the index of the jump table entry
238 //. to jump to.
239 unsigned Reg;
240 /// JTI - the JumpTableIndex for this jump table in the function.
241 unsigned JTI;
242 /// MBB - the MBB into which to emit the code for the indirect jump.
243 MachineBasicBlock *MBB;
244 /// Default - the MBB of the default bb, which is a successor of the range
245 /// check MBB. This is when updating PHI nodes in successors.
246 MachineBasicBlock *Default;
247 };
248 struct JumpTableHeader {
249 JumpTableHeader(APInt F, APInt L, const Value *SV, MachineBasicBlock *H,
250 bool E = false):
251 First(F), Last(L), SValue(SV), HeaderBB(H), Emitted(E) {}
252 APInt First;
253 APInt Last;
254 const Value *SValue;
255 MachineBasicBlock *HeaderBB;
256 bool Emitted;
257 };
258 typedef std::pair<JumpTableHeader, JumpTable> JumpTableBlock;
260 struct BitTestCase {
261 BitTestCase(uint64_t M, MachineBasicBlock* T, MachineBasicBlock* Tr):
262 Mask(M), ThisBB(T), TargetBB(Tr) { }
263 uint64_t Mask;
264 MachineBasicBlock *ThisBB;
265 MachineBasicBlock *TargetBB;
266 };
268 typedef SmallVector<BitTestCase, 3> BitTestInfo;
270 struct BitTestBlock {
271 BitTestBlock(APInt F, APInt R, const Value* SV,
272 unsigned Rg, EVT RgVT, bool E,
273 MachineBasicBlock* P, MachineBasicBlock* D,
274 const BitTestInfo& C):
275 First(F), Range(R), SValue(SV), Reg(Rg), RegVT(RgVT), Emitted(E),
276 Parent(P), Default(D), Cases(C) { }
277 APInt First;
278 APInt Range;
279 const Value *SValue;
280 unsigned Reg;
281 EVT RegVT;
282 bool Emitted;
283 MachineBasicBlock *Parent;
284 MachineBasicBlock *Default;
285 BitTestInfo Cases;
286 };
288 public:
289 // TLI - This is information that describes the available target features we
290 // need for lowering. This indicates when operations are unavailable,
291 // implemented with a libcall, etc.
292 const TargetMachine &TM;
293 const TargetLowering &TLI;
294 SelectionDAG &DAG;
295 const TargetData *TD;
296 AliasAnalysis *AA;
298 /// SwitchCases - Vector of CaseBlock structures used to communicate
299 /// SwitchInst code generation information.
300 std::vector<CaseBlock> SwitchCases;
301 /// JTCases - Vector of JumpTable structures used to communicate
302 /// SwitchInst code generation information.
303 std::vector<JumpTableBlock> JTCases;
304 /// BitTestCases - Vector of BitTestBlock structures used to communicate
305 /// SwitchInst code generation information.
306 std::vector<BitTestBlock> BitTestCases;
308 // Emit PHI-node-operand constants only once even if used by multiple
309 // PHI nodes.
310 DenseMap<const Constant *, unsigned> ConstantsOut;
312 /// FuncInfo - Information about the function as a whole.
313 ///
314 FunctionLoweringInfo &FuncInfo;
316 /// OptLevel - What optimization level we're generating code for.
317 ///
318 CodeGenOpt::Level OptLevel;
320 /// GFI - Garbage collection metadata for the function.
321 GCFunctionInfo *GFI;
323 /// HasTailCall - This is set to true if a call in the current
324 /// block has been translated as a tail call. In this case,
325 /// no subsequent DAG nodes should be created.
326 ///
327 bool HasTailCall;
329 LLVMContext *Context;
331 SelectionDAGBuilder(SelectionDAG &dag, FunctionLoweringInfo &funcinfo,
332 CodeGenOpt::Level ol)
333 : SDNodeOrder(0), TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
334 DAG(dag), FuncInfo(funcinfo), OptLevel(ol),
335 HasTailCall(false), Context(dag.getContext()) {
336 }
338 void init(GCFunctionInfo *gfi, AliasAnalysis &aa);
340 /// clear - Clear out the current SelectionDAG and the associated
341 /// state and prepare this SelectionDAGBuilder object to be used
342 /// for a new block. This doesn't clear out information about
343 /// additional blocks that are needed to complete switch lowering
344 /// or PHI node updating; that information is cleared out as it is
345 /// consumed.
346 void clear();
348 /// clearDanglingDebugInfo - Clear the dangling debug information
349 /// map. This function is seperated from the clear so that debug
350 /// information that is dangling in a basic block can be properly
351 /// resolved in a different basic block. This allows the
352 /// SelectionDAG to resolve dangling debug information attached
353 /// to PHI nodes.
354 void clearDanglingDebugInfo();
356 /// getRoot - Return the current virtual root of the Selection DAG,
357 /// flushing any PendingLoad items. This must be done before emitting
358 /// a store or any other node that may need to be ordered after any
359 /// prior load instructions.
360 ///
361 SDValue getRoot();
363 /// getControlRoot - Similar to getRoot, but instead of flushing all the
364 /// PendingLoad items, flush all the PendingExports items. It is necessary
365 /// to do this before emitting a terminator instruction.
366 ///
367 SDValue getControlRoot();
369 DebugLoc getCurDebugLoc() const { return CurDebugLoc; }
371 unsigned getSDNodeOrder() const { return SDNodeOrder; }
373 void CopyValueToVirtualRegister(const Value *V, unsigned Reg);
375 /// AssignOrderingToNode - Assign an ordering to the node. The order is gotten
376 /// from how the code appeared in the source. The ordering is used by the
377 /// scheduler to effectively turn off scheduling.
378 void AssignOrderingToNode(const SDNode *Node);
380 void visit(const Instruction &I);
382 void visit(unsigned Opcode, const User &I);
384 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
385 // generate the debug data structures now that we've seen its definition.
386 void resolveDanglingDebugInfo(const Value *V, SDValue Val);
387 SDValue getValue(const Value *V);
388 SDValue getNonRegisterValue(const Value *V);
389 SDValue getValueImpl(const Value *V);
391 void setValue(const Value *V, SDValue NewN) {
392 SDValue &N = NodeMap[V];
393 assert(N.getNode() == 0 && "Already set a value for this node!");
394 N = NewN;
395 }
397 void setUnusedArgValue(const Value *V, SDValue NewN) {
398 SDValue &N = UnusedArgNodeMap[V];
399 assert(N.getNode() == 0 && "Already set a value for this node!");
400 N = NewN;
401 }
403 void FindMergedConditions(const Value *Cond, MachineBasicBlock *TBB,
404 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
405 MachineBasicBlock *SwitchBB, unsigned Opc);
406 void EmitBranchForMergedCondition(const Value *Cond, MachineBasicBlock *TBB,
407 MachineBasicBlock *FBB,
408 MachineBasicBlock *CurBB,
409 MachineBasicBlock *SwitchBB);
410 bool ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases);
411 bool isExportableFromCurrentBlock(const Value *V, const BasicBlock *FromBB);
412 void CopyToExportRegsIfNeeded(const Value *V);
413 void ExportFromCurrentBlock(const Value *V);
414 void LowerCallTo(ImmutableCallSite CS, SDValue Callee, bool IsTailCall,
415 MachineBasicBlock *LandingPad = NULL);
417 /// UpdateSplitBlock - When an MBB was split during scheduling, update the
418 /// references that ned to refer to the last resulting block.
419 void UpdateSplitBlock(MachineBasicBlock *First, MachineBasicBlock *Last);
421 private:
422 // Terminator instructions.
423 void visitRet(const ReturnInst &I);
424 void visitBr(const BranchInst &I);
425 void visitSwitch(const SwitchInst &I);
426 void visitIndirectBr(const IndirectBrInst &I);
427 void visitUnreachable(const UnreachableInst &I) { /* noop */ }
429 // Helpers for visitSwitch
430 bool handleSmallSwitchRange(CaseRec& CR,
431 CaseRecVector& WorkList,
432 const Value* SV,
433 MachineBasicBlock* Default,
434 MachineBasicBlock *SwitchBB);
435 bool handleJTSwitchCase(CaseRec& CR,
436 CaseRecVector& WorkList,
437 const Value* SV,
438 MachineBasicBlock* Default,
439 MachineBasicBlock *SwitchBB);
440 bool handleBTSplitSwitchCase(CaseRec& CR,
441 CaseRecVector& WorkList,
442 const Value* SV,
443 MachineBasicBlock* Default,
444 MachineBasicBlock *SwitchBB);
445 bool handleBitTestsSwitchCase(CaseRec& CR,
446 CaseRecVector& WorkList,
447 const Value* SV,
448 MachineBasicBlock* Default,
449 MachineBasicBlock *SwitchBB);
451 uint32_t getEdgeWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst);
452 void addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
453 uint32_t Weight = 0);
454 public:
455 void visitSwitchCase(CaseBlock &CB,
456 MachineBasicBlock *SwitchBB);
457 void visitBitTestHeader(BitTestBlock &B, MachineBasicBlock *SwitchBB);
458 void visitBitTestCase(BitTestBlock &BB,
459 MachineBasicBlock* NextMBB,
460 unsigned Reg,
461 BitTestCase &B,
462 MachineBasicBlock *SwitchBB);
463 void visitJumpTable(JumpTable &JT);
464 void visitJumpTableHeader(JumpTable &JT, JumpTableHeader &JTH,
465 MachineBasicBlock *SwitchBB);
467 private:
468 // These all get lowered before this pass.
469 void visitInvoke(const InvokeInst &I);
470 void visitUnwind(const UnwindInst &I);
472 void visitBinary(const User &I, unsigned OpCode);
473 void visitShift(const User &I, unsigned Opcode);
474 void visitAdd(const User &I) { visitBinary(I, ISD::ADD); }
475 void visitFAdd(const User &I) { visitBinary(I, ISD::FADD); }
476 void visitSub(const User &I) { visitBinary(I, ISD::SUB); }
477 void visitFSub(const User &I);
478 void visitMul(const User &I) { visitBinary(I, ISD::MUL); }
479 void visitFMul(const User &I) { visitBinary(I, ISD::FMUL); }
480 void visitURem(const User &I) { visitBinary(I, ISD::UREM); }
481 void visitSRem(const User &I) { visitBinary(I, ISD::SREM); }
482 void visitFRem(const User &I) { visitBinary(I, ISD::FREM); }
483 void visitUDiv(const User &I) { visitBinary(I, ISD::UDIV); }
484 void visitSDiv(const User &I);
485 void visitFDiv(const User &I) { visitBinary(I, ISD::FDIV); }
486 void visitAnd (const User &I) { visitBinary(I, ISD::AND); }
487 void visitOr (const User &I) { visitBinary(I, ISD::OR); }
488 void visitXor (const User &I) { visitBinary(I, ISD::XOR); }
489 void visitShl (const User &I) { visitShift(I, ISD::SHL); }
490 void visitLShr(const User &I) { visitShift(I, ISD::SRL); }
491 void visitAShr(const User &I) { visitShift(I, ISD::SRA); }
492 void visitICmp(const User &I);
493 void visitFCmp(const User &I);
494 // Visit the conversion instructions
495 void visitTrunc(const User &I);
496 void visitZExt(const User &I);
497 void visitSExt(const User &I);
498 void visitFPTrunc(const User &I);
499 void visitFPExt(const User &I);
500 void visitFPToUI(const User &I);
501 void visitFPToSI(const User &I);
502 void visitUIToFP(const User &I);
503 void visitSIToFP(const User &I);
504 void visitPtrToInt(const User &I);
505 void visitIntToPtr(const User &I);
506 void visitBitCast(const User &I);
508 void visitExtractElement(const User &I);
509 void visitInsertElement(const User &I);
510 void visitShuffleVector(const User &I);
512 void visitExtractValue(const ExtractValueInst &I);
513 void visitInsertValue(const InsertValueInst &I);
515 void visitGetElementPtr(const User &I);
516 void visitSelect(const User &I);
518 void visitAlloca(const AllocaInst &I);
519 void visitLoad(const LoadInst &I);
520 void visitStore(const StoreInst &I);
521 void visitAtomicCmpXchg(const AtomicCmpXchgInst &I);
522 void visitAtomicRMW(const AtomicRMWInst &I);
523 void visitFence(const FenceInst &I);
524 void visitPHI(const PHINode &I);
525 void visitCall(const CallInst &I);
526 bool visitMemCmpCall(const CallInst &I);
528 void visitInlineAsm(ImmutableCallSite CS);
529 const char *visitIntrinsicCall(const CallInst &I, unsigned Intrinsic);
530 void visitTargetIntrinsic(const CallInst &I, unsigned Intrinsic);
532 void visitPow(const CallInst &I);
533 void visitExp2(const CallInst &I);
534 void visitExp(const CallInst &I);
535 void visitLog(const CallInst &I);
536 void visitLog2(const CallInst &I);
537 void visitLog10(const CallInst &I);
539 void visitVAStart(const CallInst &I);
540 void visitVAArg(const VAArgInst &I);
541 void visitVAEnd(const CallInst &I);
542 void visitVACopy(const CallInst &I);
544 void visitUserOp1(const Instruction &I) {
545 llvm_unreachable("UserOp1 should not exist at instruction selection time!");
546 }
547 void visitUserOp2(const Instruction &I) {
548 llvm_unreachable("UserOp2 should not exist at instruction selection time!");
549 }
551 const char *implVisitBinaryAtomic(const CallInst& I, ISD::NodeType Op);
552 const char *implVisitAluOverflow(const CallInst &I, ISD::NodeType Op);
554 void HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
556 /// EmitFuncArgumentDbgValue - If V is an function argument then create
557 /// corresponding DBG_VALUE machine instruction for it now. At the end of
558 /// instruction selection, they will be inserted to the entry BB.
559 bool EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
560 int64_t Offset, const SDValue &N);
561 };
563 } // end namespace llvm
565 #endif