1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This implements the SelectionDAGISel class.
11 //
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/CodeGen/SelectionDAGISel.h"
16 #include "ScheduleDAGSDNodes.h"
17 #include "SelectionDAGBuilder.h"
18 #include "llvm/ADT/PostOrderIterator.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/TargetTransformInfo.h"
23 #include "llvm/CodeGen/FastISel.h"
24 #include "llvm/CodeGen/FunctionLoweringInfo.h"
25 #include "llvm/CodeGen/GCMetadata.h"
26 #include "llvm/CodeGen/GCStrategy.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
33 #include "llvm/CodeGen/SchedulerRegistry.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/DebugInfo.h"
36 #include "llvm/IR/Constants.h"
37 #include "llvm/IR/Function.h"
38 #include "llvm/IR/InlineAsm.h"
39 #include "llvm/IR/Instructions.h"
40 #include "llvm/IR/IntrinsicInst.h"
41 #include "llvm/IR/Intrinsics.h"
42 #include "llvm/IR/LLVMContext.h"
43 #include "llvm/IR/Module.h"
44 #include "llvm/Support/Compiler.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/ErrorHandling.h"
47 #include "llvm/Support/Timer.h"
48 #include "llvm/Support/raw_ostream.h"
49 #include "llvm/Target/TargetInstrInfo.h"
50 #include "llvm/Target/TargetIntrinsicInfo.h"
51 #include "llvm/Target/TargetLibraryInfo.h"
52 #include "llvm/Target/TargetLowering.h"
53 #include "llvm/Target/TargetMachine.h"
54 #include "llvm/Target/TargetOptions.h"
55 #include "llvm/Target/TargetRegisterInfo.h"
56 #include "llvm/Target/TargetSubtargetInfo.h"
57 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
58 #include <algorithm>
59 using namespace llvm;
61 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
62 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
63 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
64 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
65 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
67 #ifndef NDEBUG
68 static cl::opt<bool>
69 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
70 cl::desc("Enable extra verbose messages in the \"fast\" "
71 "instruction selector"));
72 // Terminators
73 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
74 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
75 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
76 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
77 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
78 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
79 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
81 // Standard binary operators...
82 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
83 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
84 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
85 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
86 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
87 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
88 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
89 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
90 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
91 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
92 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
93 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
95 // Logical operators...
96 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
97 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
98 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
100 // Memory instructions...
101 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
102 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
103 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
104 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
105 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
106 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
107 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
109 // Convert instructions...
110 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
111 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
112 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
113 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
114 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
115 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
116 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
117 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
118 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
119 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
120 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
121 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
123 // Other instructions...
124 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
125 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
126 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
127 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
128 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
129 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
130 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
131 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
132 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
133 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
134 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
135 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
136 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
137 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
138 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
139 #endif
141 static cl::opt<bool>
142 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
143 cl::desc("Enable verbose messages in the \"fast\" "
144 "instruction selector"));
145 static cl::opt<bool>
146 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
147 cl::desc("Enable abort calls when \"fast\" instruction selection "
148 "fails to lower an instruction"));
149 static cl::opt<bool>
150 EnableFastISelAbortArgs("fast-isel-abort-args", cl::Hidden,
151 cl::desc("Enable abort calls when \"fast\" instruction selection "
152 "fails to lower a formal argument"));
154 static cl::opt<bool>
155 UseMBPI("use-mbpi",
156 cl::desc("use Machine Branch Probability Info"),
157 cl::init(true), cl::Hidden);
159 #ifndef NDEBUG
160 static cl::opt<bool>
161 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
162 cl::desc("Pop up a window to show dags before the first "
163 "dag combine pass"));
164 static cl::opt<bool>
165 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
166 cl::desc("Pop up a window to show dags before legalize types"));
167 static cl::opt<bool>
168 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
169 cl::desc("Pop up a window to show dags before legalize"));
170 static cl::opt<bool>
171 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
172 cl::desc("Pop up a window to show dags before the second "
173 "dag combine pass"));
174 static cl::opt<bool>
175 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
176 cl::desc("Pop up a window to show dags before the post legalize types"
177 " dag combine pass"));
178 static cl::opt<bool>
179 ViewISelDAGs("view-isel-dags", cl::Hidden,
180 cl::desc("Pop up a window to show isel dags as they are selected"));
181 static cl::opt<bool>
182 ViewSchedDAGs("view-sched-dags", cl::Hidden,
183 cl::desc("Pop up a window to show sched dags as they are processed"));
184 static cl::opt<bool>
185 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
186 cl::desc("Pop up a window to show SUnit dags after they are processed"));
187 #else
188 static const bool ViewDAGCombine1 = false,
189 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
190 ViewDAGCombine2 = false,
191 ViewDAGCombineLT = false,
192 ViewISelDAGs = false, ViewSchedDAGs = false,
193 ViewSUnitDAGs = false;
194 #endif
196 //===---------------------------------------------------------------------===//
197 ///
198 /// RegisterScheduler class - Track the registration of instruction schedulers.
199 ///
200 //===---------------------------------------------------------------------===//
201 MachinePassRegistry RegisterScheduler::Registry;
203 //===---------------------------------------------------------------------===//
204 ///
205 /// ISHeuristic command line option for instruction schedulers.
206 ///
207 //===---------------------------------------------------------------------===//
208 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
209 RegisterPassParser<RegisterScheduler> >
210 ISHeuristic("pre-RA-sched",
211 cl::init(&createDefaultScheduler),
212 cl::desc("Instruction schedulers available (before register"
213 " allocation):"));
215 static RegisterScheduler
216 defaultListDAGScheduler("default", "Best scheduler for the target",
217 createDefaultScheduler);
219 namespace llvm {
220 //===--------------------------------------------------------------------===//
221 /// createDefaultScheduler - This creates an instruction scheduler appropriate
222 /// for the target.
223 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
224 CodeGenOpt::Level OptLevel) {
225 const TargetLowering &TLI = IS->getTargetLowering();
226 const TargetSubtargetInfo &ST = IS->TM.getSubtarget<TargetSubtargetInfo>();
228 if (OptLevel == CodeGenOpt::None || ST.enableMachineScheduler() ||
229 TLI.getSchedulingPreference() == Sched::Source)
230 return createSourceListDAGScheduler(IS, OptLevel);
231 if (TLI.getSchedulingPreference() == Sched::RegPressure)
232 return createBURRListDAGScheduler(IS, OptLevel);
233 if (TLI.getSchedulingPreference() == Sched::Hybrid)
234 return createHybridListDAGScheduler(IS, OptLevel);
235 if (TLI.getSchedulingPreference() == Sched::VLIW)
236 return createVLIWDAGScheduler(IS, OptLevel);
237 assert(TLI.getSchedulingPreference() == Sched::ILP &&
238 "Unknown sched type!");
239 return createILPListDAGScheduler(IS, OptLevel);
240 }
241 }
243 // EmitInstrWithCustomInserter - This method should be implemented by targets
244 // that mark instructions with the 'usesCustomInserter' flag. These
245 // instructions are special in various ways, which require special support to
246 // insert. The specified MachineInstr is created but not inserted into any
247 // basic blocks, and this method is called to expand it into a sequence of
248 // instructions, potentially also creating new basic blocks and control flow.
249 // When new basic blocks are inserted and the edges from MBB to its successors
250 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
251 // DenseMap.
252 MachineBasicBlock *
253 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
254 MachineBasicBlock *MBB) const {
255 #ifndef NDEBUG
256 dbgs() << "If a target marks an instruction with "
257 "'usesCustomInserter', it must implement "
258 "TargetLowering::EmitInstrWithCustomInserter!";
259 #endif
260 llvm_unreachable(0);
261 }
263 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
264 SDNode *Node) const {
265 assert(!MI->hasPostISelHook() &&
266 "If a target marks an instruction with 'hasPostISelHook', "
267 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
268 }
270 //===----------------------------------------------------------------------===//
271 // SelectionDAGISel code
272 //===----------------------------------------------------------------------===//
274 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm,
275 CodeGenOpt::Level OL) :
276 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()),
277 FuncInfo(new FunctionLoweringInfo(TLI)),
278 CurDAG(new SelectionDAG(tm, OL)),
279 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
280 GFI(),
281 OptLevel(OL),
282 DAGSize(0) {
283 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
284 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
285 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
286 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry());
287 }
289 SelectionDAGISel::~SelectionDAGISel() {
290 delete SDB;
291 delete CurDAG;
292 delete FuncInfo;
293 }
295 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
296 AU.addRequired<AliasAnalysis>();
297 AU.addPreserved<AliasAnalysis>();
298 AU.addRequired<GCModuleInfo>();
299 AU.addPreserved<GCModuleInfo>();
300 AU.addRequired<TargetLibraryInfo>();
301 if (UseMBPI && OptLevel != CodeGenOpt::None)
302 AU.addRequired<BranchProbabilityInfo>();
303 MachineFunctionPass::getAnalysisUsage(AU);
304 }
306 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
307 /// may trap on it. In this case we have to split the edge so that the path
308 /// through the predecessor block that doesn't go to the phi block doesn't
309 /// execute the possibly trapping instruction.
310 ///
311 /// This is required for correctness, so it must be done at -O0.
312 ///
313 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) {
314 // Loop for blocks with phi nodes.
315 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
316 PHINode *PN = dyn_cast<PHINode>(BB->begin());
317 if (PN == 0) continue;
319 ReprocessBlock:
320 // For each block with a PHI node, check to see if any of the input values
321 // are potentially trapping constant expressions. Constant expressions are
322 // the only potentially trapping value that can occur as the argument to a
323 // PHI.
324 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
325 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
326 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
327 if (CE == 0 || !CE->canTrap()) continue;
329 // The only case we have to worry about is when the edge is critical.
330 // Since this block has a PHI Node, we assume it has multiple input
331 // edges: check to see if the pred has multiple successors.
332 BasicBlock *Pred = PN->getIncomingBlock(i);
333 if (Pred->getTerminator()->getNumSuccessors() == 1)
334 continue;
336 // Okay, we have to split this edge.
337 SplitCriticalEdge(Pred->getTerminator(),
338 GetSuccessorNumber(Pred, BB), SDISel, true);
339 goto ReprocessBlock;
340 }
341 }
342 }
344 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
345 // Do some sanity-checking on the command-line options.
346 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
347 "-fast-isel-verbose requires -fast-isel");
348 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
349 "-fast-isel-abort requires -fast-isel");
351 const Function &Fn = *mf.getFunction();
352 const TargetInstrInfo &TII = *TM.getInstrInfo();
353 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
355 MF = &mf;
356 RegInfo = &MF->getRegInfo();
357 AA = &getAnalysis<AliasAnalysis>();
358 LibInfo = &getAnalysis<TargetLibraryInfo>();
359 TTI = getAnalysisIfAvailable<TargetTransformInfo>();
360 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
362 TargetSubtargetInfo &ST =
363 const_cast<TargetSubtargetInfo&>(TM.getSubtarget<TargetSubtargetInfo>());
364 ST.resetSubtargetFeatures(MF);
366 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
368 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this);
370 CurDAG->init(*MF, TTI);
371 FuncInfo->set(Fn, *MF);
373 if (UseMBPI && OptLevel != CodeGenOpt::None)
374 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>();
375 else
376 FuncInfo->BPI = 0;
378 SDB->init(GFI, *AA, LibInfo);
380 MF->setHasMSInlineAsm(false);
381 SelectAllBasicBlocks(Fn);
383 // If the first basic block in the function has live ins that need to be
384 // copied into vregs, emit the copies into the top of the block before
385 // emitting the code for the block.
386 MachineBasicBlock *EntryMBB = MF->begin();
387 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
389 DenseMap<unsigned, unsigned> LiveInMap;
390 if (!FuncInfo->ArgDbgValues.empty())
391 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
392 E = RegInfo->livein_end(); LI != E; ++LI)
393 if (LI->second)
394 LiveInMap.insert(std::make_pair(LI->first, LI->second));
396 // Insert DBG_VALUE instructions for function arguments to the entry block.
397 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
398 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
399 unsigned Reg = MI->getOperand(0).getReg();
400 if (TargetRegisterInfo::isPhysicalRegister(Reg))
401 EntryMBB->insert(EntryMBB->begin(), MI);
402 else {
403 MachineInstr *Def = RegInfo->getVRegDef(Reg);
404 MachineBasicBlock::iterator InsertPos = Def;
405 // FIXME: VR def may not be in entry block.
406 Def->getParent()->insert(llvm::next(InsertPos), MI);
407 }
409 // If Reg is live-in then update debug info to track its copy in a vreg.
410 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
411 if (LDI != LiveInMap.end()) {
412 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
413 MachineBasicBlock::iterator InsertPos = Def;
414 const MDNode *Variable =
415 MI->getOperand(MI->getNumOperands()-1).getMetadata();
416 unsigned Offset = MI->getOperand(1).getImm();
417 // Def is never a terminator here, so it is ok to increment InsertPos.
418 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
419 TII.get(TargetOpcode::DBG_VALUE))
420 .addReg(LDI->second, RegState::Debug)
421 .addImm(Offset).addMetadata(Variable);
423 // If this vreg is directly copied into an exported register then
424 // that COPY instructions also need DBG_VALUE, if it is the only
425 // user of LDI->second.
426 MachineInstr *CopyUseMI = NULL;
427 for (MachineRegisterInfo::use_iterator
428 UI = RegInfo->use_begin(LDI->second);
429 MachineInstr *UseMI = UI.skipInstruction();) {
430 if (UseMI->isDebugValue()) continue;
431 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
432 CopyUseMI = UseMI; continue;
433 }
434 // Otherwise this is another use or second copy use.
435 CopyUseMI = NULL; break;
436 }
437 if (CopyUseMI) {
438 MachineInstr *NewMI =
439 BuildMI(*MF, CopyUseMI->getDebugLoc(),
440 TII.get(TargetOpcode::DBG_VALUE))
441 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug)
442 .addImm(Offset).addMetadata(Variable);
443 MachineBasicBlock::iterator Pos = CopyUseMI;
444 EntryMBB->insertAfter(Pos, NewMI);
445 }
446 }
447 }
449 // Determine if there are any calls in this machine function.
450 MachineFrameInfo *MFI = MF->getFrameInfo();
451 for (MachineFunction::const_iterator I = MF->begin(), E = MF->end(); I != E;
452 ++I) {
454 if (MFI->hasCalls() && MF->hasMSInlineAsm())
455 break;
457 const MachineBasicBlock *MBB = I;
458 for (MachineBasicBlock::const_iterator II = MBB->begin(), IE = MBB->end();
459 II != IE; ++II) {
460 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode());
461 if ((MCID.isCall() && !MCID.isReturn()) ||
462 II->isStackAligningInlineAsm()) {
463 MFI->setHasCalls(true);
464 }
465 if (II->isMSInlineAsm()) {
466 MF->setHasMSInlineAsm(true);
467 }
468 }
469 }
471 // Determine if there is a call to setjmp in the machine function.
472 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
474 // Replace forward-declared registers with the registers containing
475 // the desired value.
476 MachineRegisterInfo &MRI = MF->getRegInfo();
477 for (DenseMap<unsigned, unsigned>::iterator
478 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
479 I != E; ++I) {
480 unsigned From = I->first;
481 unsigned To = I->second;
482 // If To is also scheduled to be replaced, find what its ultimate
483 // replacement is.
484 for (;;) {
485 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To);
486 if (J == E) break;
487 To = J->second;
488 }
489 // Replace it.
490 MRI.replaceRegWith(From, To);
491 }
493 // Freeze the set of reserved registers now that MachineFrameInfo has been
494 // set up. All the information required by getReservedRegs() should be
495 // available now.
496 MRI.freezeReservedRegs(*MF);
498 // Release function-specific state. SDB and CurDAG are already cleared
499 // at this point.
500 FuncInfo->clear();
502 return true;
503 }
505 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
506 BasicBlock::const_iterator End,
507 bool &HadTailCall) {
508 // Lower all of the non-terminator instructions. If a call is emitted
509 // as a tail call, cease emitting nodes for this block. Terminators
510 // are handled below.
511 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
512 SDB->visit(*I);
514 // Make sure the root of the DAG is up-to-date.
515 CurDAG->setRoot(SDB->getControlRoot());
516 HadTailCall = SDB->HasTailCall;
517 SDB->clear();
519 // Final step, emit the lowered DAG as machine code.
520 CodeGenAndEmitDAG();
521 }
523 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
524 SmallPtrSet<SDNode*, 128> VisitedNodes;
525 SmallVector<SDNode*, 128> Worklist;
527 Worklist.push_back(CurDAG->getRoot().getNode());
529 APInt KnownZero;
530 APInt KnownOne;
532 do {
533 SDNode *N = Worklist.pop_back_val();
535 // If we've already seen this node, ignore it.
536 if (!VisitedNodes.insert(N))
537 continue;
539 // Otherwise, add all chain operands to the worklist.
540 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
541 if (N->getOperand(i).getValueType() == MVT::Other)
542 Worklist.push_back(N->getOperand(i).getNode());
544 // If this is a CopyToReg with a vreg dest, process it.
545 if (N->getOpcode() != ISD::CopyToReg)
546 continue;
548 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
549 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
550 continue;
552 // Ignore non-scalar or non-integer values.
553 SDValue Src = N->getOperand(2);
554 EVT SrcVT = Src.getValueType();
555 if (!SrcVT.isInteger() || SrcVT.isVector())
556 continue;
558 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
559 CurDAG->ComputeMaskedBits(Src, KnownZero, KnownOne);
560 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
561 } while (!Worklist.empty());
562 }
564 void SelectionDAGISel::CodeGenAndEmitDAG() {
565 std::string GroupName;
566 if (TimePassesIsEnabled)
567 GroupName = "Instruction Selection and Scheduling";
568 std::string BlockName;
569 int BlockNumber = -1;
570 (void)BlockNumber;
571 #ifdef NDEBUG
572 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
573 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
574 ViewSUnitDAGs)
575 #endif
576 {
577 BlockNumber = FuncInfo->MBB->getNumber();
578 BlockName = MF->getName().str() + ":" +
579 FuncInfo->MBB->getBasicBlock()->getName().str();
580 }
581 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
582 << " '" << BlockName << "'\n"; CurDAG->dump());
584 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
586 // Run the DAG combiner in pre-legalize mode.
587 {
588 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
589 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
590 }
592 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
593 << " '" << BlockName << "'\n"; CurDAG->dump());
595 // Second step, hack on the DAG until it only uses operations and types that
596 // the target supports.
597 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
598 BlockName);
600 bool Changed;
601 {
602 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
603 Changed = CurDAG->LegalizeTypes();
604 }
606 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
607 << " '" << BlockName << "'\n"; CurDAG->dump());
609 if (Changed) {
610 if (ViewDAGCombineLT)
611 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
613 // Run the DAG combiner in post-type-legalize mode.
614 {
615 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
616 TimePassesIsEnabled);
617 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
618 }
620 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
621 << " '" << BlockName << "'\n"; CurDAG->dump());
622 }
624 {
625 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
626 Changed = CurDAG->LegalizeVectors();
627 }
629 if (Changed) {
630 {
631 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
632 CurDAG->LegalizeTypes();
633 }
635 if (ViewDAGCombineLT)
636 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
638 // Run the DAG combiner in post-type-legalize mode.
639 {
640 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
641 TimePassesIsEnabled);
642 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
643 }
645 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
646 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
647 }
649 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
651 {
652 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
653 CurDAG->Legalize();
654 }
656 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
657 << " '" << BlockName << "'\n"; CurDAG->dump());
659 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
661 // Run the DAG combiner in post-legalize mode.
662 {
663 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
664 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
665 }
667 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
668 << " '" << BlockName << "'\n"; CurDAG->dump());
670 if (OptLevel != CodeGenOpt::None)
671 ComputeLiveOutVRegInfo();
673 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
675 // Third, instruction select all of the operations to machine code, adding the
676 // code to the MachineBasicBlock.
677 {
678 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
679 DoInstructionSelection();
680 }
682 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
683 << " '" << BlockName << "'\n"; CurDAG->dump());
685 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
687 // Schedule machine code.
688 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
689 {
690 NamedRegionTimer T("Instruction Scheduling", GroupName,
691 TimePassesIsEnabled);
692 Scheduler->Run(CurDAG, FuncInfo->MBB);
693 }
695 if (ViewSUnitDAGs) Scheduler->viewGraph();
697 // Emit machine code to BB. This can change 'BB' to the last block being
698 // inserted into.
699 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
700 {
701 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
703 // FuncInfo->InsertPt is passed by reference and set to the end of the
704 // scheduled instructions.
705 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt);
706 }
708 // If the block was split, make sure we update any references that are used to
709 // update PHI nodes later on.
710 if (FirstMBB != LastMBB)
711 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
713 // Free the scheduler state.
714 {
715 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
716 TimePassesIsEnabled);
717 delete Scheduler;
718 }
720 // Free the SelectionDAG state, now that we're finished with it.
721 CurDAG->clear();
722 }
724 namespace {
725 /// ISelUpdater - helper class to handle updates of the instruction selection
726 /// graph.
727 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
728 SelectionDAG::allnodes_iterator &ISelPosition;
729 public:
730 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp)
731 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
733 /// NodeDeleted - Handle nodes deleted from the graph. If the node being
734 /// deleted is the current ISelPosition node, update ISelPosition.
735 ///
736 virtual void NodeDeleted(SDNode *N, SDNode *E) {
737 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
738 ++ISelPosition;
739 }
740 };
741 } // end anonymous namespace
743 void SelectionDAGISel::DoInstructionSelection() {
744 DEBUG(errs() << "===== Instruction selection begins: BB#"
745 << FuncInfo->MBB->getNumber()
746 << " '" << FuncInfo->MBB->getName() << "'\n");
748 PreprocessISelDAG();
750 // Select target instructions for the DAG.
751 {
752 // Number all nodes with a topological order and set DAGSize.
753 DAGSize = CurDAG->AssignTopologicalOrder();
755 // Create a dummy node (which is not added to allnodes), that adds
756 // a reference to the root node, preventing it from being deleted,
757 // and tracking any changes of the root.
758 HandleSDNode Dummy(CurDAG->getRoot());
759 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode());
760 ++ISelPosition;
762 // Make sure that ISelPosition gets properly updated when nodes are deleted
763 // in calls made from this function.
764 ISelUpdater ISU(*CurDAG, ISelPosition);
766 // The AllNodes list is now topological-sorted. Visit the
767 // nodes by starting at the end of the list (the root of the
768 // graph) and preceding back toward the beginning (the entry
769 // node).
770 while (ISelPosition != CurDAG->allnodes_begin()) {
771 SDNode *Node = --ISelPosition;
772 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
773 // but there are currently some corner cases that it misses. Also, this
774 // makes it theoretically possible to disable the DAGCombiner.
775 if (Node->use_empty())
776 continue;
778 SDNode *ResNode = Select(Node);
780 // FIXME: This is pretty gross. 'Select' should be changed to not return
781 // anything at all and this code should be nuked with a tactical strike.
783 // If node should not be replaced, continue with the next one.
784 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
785 continue;
786 // Replace node.
787 if (ResNode)
788 ReplaceUses(Node, ResNode);
790 // If after the replacement this node is not used any more,
791 // remove this dead node.
792 if (Node->use_empty()) // Don't delete EntryToken, etc.
793 CurDAG->RemoveDeadNode(Node);
794 }
796 CurDAG->setRoot(Dummy.getValue());
797 }
799 DEBUG(errs() << "===== Instruction selection ends:\n");
801 PostprocessISelDAG();
802 }
804 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
805 /// do other setup for EH landing-pad blocks.
806 void SelectionDAGISel::PrepareEHLandingPad() {
807 MachineBasicBlock *MBB = FuncInfo->MBB;
809 // Add a label to mark the beginning of the landing pad. Deletion of the
810 // landing pad can thus be detected via the MachineModuleInfo.
811 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
813 // Assign the call site to the landing pad's begin label.
814 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
816 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
817 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
818 .addSym(Label);
820 // Mark exception register as live in.
821 unsigned Reg = TLI.getExceptionPointerRegister();
822 if (Reg) MBB->addLiveIn(Reg);
824 // Mark exception selector register as live in.
825 Reg = TLI.getExceptionSelectorRegister();
826 if (Reg) MBB->addLiveIn(Reg);
827 }
829 /// TryToFoldFastISelLoad - We're checking to see if we can fold the specified
830 /// load into the specified FoldInst. Note that we could have a sequence where
831 /// multiple LLVM IR instructions are folded into the same machineinstr. For
832 /// example we could have:
833 /// A: x = load i32 *P
834 /// B: y = icmp A, 42
835 /// C: br y, ...
836 ///
837 /// In this scenario, LI is "A", and FoldInst is "C". We know about "B" (and
838 /// any other folded instructions) because it is between A and C.
839 ///
840 /// If we succeed in folding the load into the operation, return true.
841 ///
842 bool SelectionDAGISel::TryToFoldFastISelLoad(const LoadInst *LI,
843 const Instruction *FoldInst,
844 FastISel *FastIS) {
845 // We know that the load has a single use, but don't know what it is. If it
846 // isn't one of the folded instructions, then we can't succeed here. Handle
847 // this by scanning the single-use users of the load until we get to FoldInst.
848 unsigned MaxUsers = 6; // Don't scan down huge single-use chains of instrs.
850 const Instruction *TheUser = LI->use_back();
851 while (TheUser != FoldInst && // Scan up until we find FoldInst.
852 // Stay in the right block.
853 TheUser->getParent() == FoldInst->getParent() &&
854 --MaxUsers) { // Don't scan too far.
855 // If there are multiple or no uses of this instruction, then bail out.
856 if (!TheUser->hasOneUse())
857 return false;
859 TheUser = TheUser->use_back();
860 }
862 // If we didn't find the fold instruction, then we failed to collapse the
863 // sequence.
864 if (TheUser != FoldInst)
865 return false;
867 // Don't try to fold volatile loads. Target has to deal with alignment
868 // constraints.
869 if (LI->isVolatile()) return false;
871 // Figure out which vreg this is going into. If there is no assigned vreg yet
872 // then there actually was no reference to it. Perhaps the load is referenced
873 // by a dead instruction.
874 unsigned LoadReg = FastIS->getRegForValue(LI);
875 if (LoadReg == 0)
876 return false;
878 // Check to see what the uses of this vreg are. If it has no uses, or more
879 // than one use (at the machine instr level) then we can't fold it.
880 MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(LoadReg);
881 if (RI == RegInfo->reg_end())
882 return false;
884 // See if there is exactly one use of the vreg. If there are multiple uses,
885 // then the instruction got lowered to multiple machine instructions or the
886 // use of the loaded value ended up being multiple operands of the result, in
887 // either case, we can't fold this.
888 MachineRegisterInfo::reg_iterator PostRI = RI; ++PostRI;
889 if (PostRI != RegInfo->reg_end())
890 return false;
892 assert(RI.getOperand().isUse() &&
893 "The only use of the vreg must be a use, we haven't emitted the def!");
895 MachineInstr *User = &*RI;
897 // Set the insertion point properly. Folding the load can cause generation of
898 // other random instructions (like sign extends) for addressing modes, make
899 // sure they get inserted in a logical place before the new instruction.
900 FuncInfo->InsertPt = User;
901 FuncInfo->MBB = User->getParent();
903 // Ask the target to try folding the load.
904 return FastIS->TryToFoldLoad(User, RI.getOperandNo(), LI);
905 }
907 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
908 /// side-effect free and is either dead or folded into a generated instruction.
909 /// Return false if it needs to be emitted.
910 static bool isFoldedOrDeadInstruction(const Instruction *I,
911 FunctionLoweringInfo *FuncInfo) {
912 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
913 !isa<TerminatorInst>(I) && // Terminators aren't folded.
914 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
915 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded.
916 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
917 }
919 #ifndef NDEBUG
920 // Collect per Instruction statistics for fast-isel misses. Only those
921 // instructions that cause the bail are accounted for. It does not account for
922 // instructions higher in the block. Thus, summing the per instructions stats
923 // will not add up to what is reported by NumFastIselFailures.
924 static void collectFailStats(const Instruction *I) {
925 switch (I->getOpcode()) {
926 default: assert (0 && "<Invalid operator> ");
928 // Terminators
929 case Instruction::Ret: NumFastIselFailRet++; return;
930 case Instruction::Br: NumFastIselFailBr++; return;
931 case Instruction::Switch: NumFastIselFailSwitch++; return;
932 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
933 case Instruction::Invoke: NumFastIselFailInvoke++; return;
934 case Instruction::Resume: NumFastIselFailResume++; return;
935 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
937 // Standard binary operators...
938 case Instruction::Add: NumFastIselFailAdd++; return;
939 case Instruction::FAdd: NumFastIselFailFAdd++; return;
940 case Instruction::Sub: NumFastIselFailSub++; return;
941 case Instruction::FSub: NumFastIselFailFSub++; return;
942 case Instruction::Mul: NumFastIselFailMul++; return;
943 case Instruction::FMul: NumFastIselFailFMul++; return;
944 case Instruction::UDiv: NumFastIselFailUDiv++; return;
945 case Instruction::SDiv: NumFastIselFailSDiv++; return;
946 case Instruction::FDiv: NumFastIselFailFDiv++; return;
947 case Instruction::URem: NumFastIselFailURem++; return;
948 case Instruction::SRem: NumFastIselFailSRem++; return;
949 case Instruction::FRem: NumFastIselFailFRem++; return;
951 // Logical operators...
952 case Instruction::And: NumFastIselFailAnd++; return;
953 case Instruction::Or: NumFastIselFailOr++; return;
954 case Instruction::Xor: NumFastIselFailXor++; return;
956 // Memory instructions...
957 case Instruction::Alloca: NumFastIselFailAlloca++; return;
958 case Instruction::Load: NumFastIselFailLoad++; return;
959 case Instruction::Store: NumFastIselFailStore++; return;
960 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
961 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
962 case Instruction::Fence: NumFastIselFailFence++; return;
963 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
965 // Convert instructions...
966 case Instruction::Trunc: NumFastIselFailTrunc++; return;
967 case Instruction::ZExt: NumFastIselFailZExt++; return;
968 case Instruction::SExt: NumFastIselFailSExt++; return;
969 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
970 case Instruction::FPExt: NumFastIselFailFPExt++; return;
971 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
972 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
973 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
974 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
975 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
976 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
977 case Instruction::BitCast: NumFastIselFailBitCast++; return;
979 // Other instructions...
980 case Instruction::ICmp: NumFastIselFailICmp++; return;
981 case Instruction::FCmp: NumFastIselFailFCmp++; return;
982 case Instruction::PHI: NumFastIselFailPHI++; return;
983 case Instruction::Select: NumFastIselFailSelect++; return;
984 case Instruction::Call: NumFastIselFailCall++; return;
985 case Instruction::Shl: NumFastIselFailShl++; return;
986 case Instruction::LShr: NumFastIselFailLShr++; return;
987 case Instruction::AShr: NumFastIselFailAShr++; return;
988 case Instruction::VAArg: NumFastIselFailVAArg++; return;
989 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
990 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
991 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
992 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
993 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
994 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
995 }
996 }
997 #endif
999 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
1000 // Initialize the Fast-ISel state, if needed.
1001 FastISel *FastIS = 0;
1002 if (TM.Options.EnableFastISel)
1003 FastIS = TLI.createFastISel(*FuncInfo, LibInfo);
1005 // Iterate over all basic blocks in the function.
1006 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
1007 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
1008 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
1009 const BasicBlock *LLVMBB = *I;
1011 if (OptLevel != CodeGenOpt::None) {
1012 bool AllPredsVisited = true;
1013 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
1014 PI != PE; ++PI) {
1015 if (!FuncInfo->VisitedBBs.count(*PI)) {
1016 AllPredsVisited = false;
1017 break;
1018 }
1019 }
1021 if (AllPredsVisited) {
1022 for (BasicBlock::const_iterator I = LLVMBB->begin();
1023 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1024 FuncInfo->ComputePHILiveOutRegInfo(PN);
1025 } else {
1026 for (BasicBlock::const_iterator I = LLVMBB->begin();
1027 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1028 FuncInfo->InvalidatePHILiveOutRegInfo(PN);
1029 }
1031 FuncInfo->VisitedBBs.insert(LLVMBB);
1032 }
1034 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
1035 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1037 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
1038 BasicBlock::const_iterator const End = LLVMBB->end();
1039 BasicBlock::const_iterator BI = End;
1041 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1043 // Setup an EH landing-pad block.
1044 if (FuncInfo->MBB->isLandingPad())
1045 PrepareEHLandingPad();
1047 // Before doing SelectionDAG ISel, see if FastISel has been requested.
1048 if (FastIS) {
1049 FastIS->startNewBlock();
1051 // Emit code for any incoming arguments. This must happen before
1052 // beginning FastISel on the entry block.
1053 if (LLVMBB == &Fn.getEntryBlock()) {
1054 // Lower any arguments needed in this block if this is the entry block.
1055 if (!FastIS->LowerArguments()) {
1057 if (EnableFastISelAbortArgs)
1058 // The "fast" selector couldn't lower these arguments. For the
1059 // purpose of debugging, just abort.
1060 llvm_unreachable("FastISel didn't lower all arguments");
1062 // Call target indepedent SDISel argument lowering code if the target
1063 // specific routine is not successful.
1064 LowerArguments(LLVMBB);
1065 CurDAG->setRoot(SDB->getControlRoot());
1066 SDB->clear();
1067 CodeGenAndEmitDAG();
1068 }
1070 // If we inserted any instructions at the beginning, make a note of
1071 // where they are, so we can be sure to emit subsequent instructions
1072 // after them.
1073 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1074 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
1075 else
1076 FastIS->setLastLocalValue(0);
1077 }
1079 unsigned NumFastIselRemaining = 0;
1080 NumFastIselRemaining = std::distance(Begin, End);
1081 // Do FastISel on as many instructions as possible.
1082 for (; BI != Begin; --BI) {
1083 const Instruction *Inst = llvm::prior(BI);
1085 // If we no longer require this instruction, skip it.
1086 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1087 --NumFastIselRemaining;
1088 continue;
1089 }
1091 // Bottom-up: reset the insert pos at the top, after any local-value
1092 // instructions.
1093 FastIS->recomputeInsertPt();
1095 // Try to select the instruction with FastISel.
1096 if (FastIS->SelectInstruction(Inst)) {
1097 --NumFastIselRemaining;
1098 DEBUG(++NumFastIselSuccess);
1099 // If fast isel succeeded, skip over all the folded instructions, and
1100 // then see if there is a load right before the selected instructions.
1101 // Try to fold the load if so.
1102 const Instruction *BeforeInst = Inst;
1103 while (BeforeInst != Begin) {
1104 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst));
1105 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1106 break;
1107 }
1108 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1109 BeforeInst->hasOneUse() &&
1110 TryToFoldFastISelLoad(cast<LoadInst>(BeforeInst), Inst, FastIS)) {
1111 // If we succeeded, don't re-select the load.
1112 BI = llvm::next(BasicBlock::const_iterator(BeforeInst));
1113 --NumFastIselRemaining;
1114 DEBUG(++NumFastIselSuccess);
1115 }
1116 continue;
1117 }
1119 #ifndef NDEBUG
1120 if (EnableFastISelVerbose2)
1121 collectFailStats(Inst);
1122 #endif
1124 // Then handle certain instructions as single-LLVM-Instruction blocks.
1125 if (isa<CallInst>(Inst)) {
1127 if (EnableFastISelVerbose || EnableFastISelAbort) {
1128 dbgs() << "FastISel missed call: ";
1129 Inst->dump();
1130 }
1132 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
1133 unsigned &R = FuncInfo->ValueMap[Inst];
1134 if (!R)
1135 R = FuncInfo->CreateRegs(Inst->getType());
1136 }
1138 bool HadTailCall = false;
1139 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt;
1140 SelectBasicBlock(Inst, BI, HadTailCall);
1142 // If the call was emitted as a tail call, we're done with the block.
1143 // We also need to delete any previously emitted instructions.
1144 if (HadTailCall) {
1145 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end());
1146 --BI;
1147 break;
1148 }
1150 // Recompute NumFastIselRemaining as Selection DAG instruction
1151 // selection may have handled the call, input args, etc.
1152 unsigned RemainingNow = std::distance(Begin, BI);
1153 DEBUG(NumFastIselFailures += NumFastIselRemaining - RemainingNow);
1154 DEBUG(NumFastIselRemaining = RemainingNow);
1155 continue;
1156 }
1158 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) {
1159 // Don't abort, and use a different message for terminator misses.
1160 DEBUG(NumFastIselFailures += NumFastIselRemaining);
1161 if (EnableFastISelVerbose || EnableFastISelAbort) {
1162 dbgs() << "FastISel missed terminator: ";
1163 Inst->dump();
1164 }
1165 } else {
1166 DEBUG(NumFastIselFailures += NumFastIselRemaining);
1167 if (EnableFastISelVerbose || EnableFastISelAbort) {
1168 dbgs() << "FastISel miss: ";
1169 Inst->dump();
1170 }
1171 if (EnableFastISelAbort)
1172 // The "fast" selector couldn't handle something and bailed.
1173 // For the purpose of debugging, just abort.
1174 llvm_unreachable("FastISel didn't select the entire block");
1175 }
1176 break;
1177 }
1179 FastIS->recomputeInsertPt();
1180 } else {
1181 // Lower any arguments needed in this block if this is the entry block.
1182 if (LLVMBB == &Fn.getEntryBlock())
1183 LowerArguments(LLVMBB);
1184 }
1186 if (Begin != BI)
1187 ++NumDAGBlocks;
1188 else
1189 ++NumFastIselBlocks;
1191 if (Begin != BI) {
1192 // Run SelectionDAG instruction selection on the remainder of the block
1193 // not handled by FastISel. If FastISel is not run, this is the entire
1194 // block.
1195 bool HadTailCall;
1196 SelectBasicBlock(Begin, BI, HadTailCall);
1197 }
1199 FinishBasicBlock();
1200 FuncInfo->PHINodesToUpdate.clear();
1201 }
1203 delete FastIS;
1204 SDB->clearDanglingDebugInfo();
1205 }
1207 void
1208 SelectionDAGISel::FinishBasicBlock() {
1210 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1211 << FuncInfo->PHINodesToUpdate.size() << "\n";
1212 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1213 dbgs() << "Node " << i << " : ("
1214 << FuncInfo->PHINodesToUpdate[i].first
1215 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1217 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1218 // PHI nodes in successors.
1219 if (SDB->SwitchCases.empty() &&
1220 SDB->JTCases.empty() &&
1221 SDB->BitTestCases.empty()) {
1222 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1223 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1224 assert(PHI->isPHI() &&
1225 "This is not a machine PHI node that we are updating!");
1226 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1227 continue;
1228 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1229 }
1230 return;
1231 }
1233 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1234 // Lower header first, if it wasn't already lowered
1235 if (!SDB->BitTestCases[i].Emitted) {
1236 // Set the current basic block to the mbb we wish to insert the code into
1237 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1238 FuncInfo->InsertPt = FuncInfo->MBB->end();
1239 // Emit the code
1240 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1241 CurDAG->setRoot(SDB->getRoot());
1242 SDB->clear();
1243 CodeGenAndEmitDAG();
1244 }
1246 uint32_t UnhandledWeight = 0;
1247 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j)
1248 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight;
1250 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1251 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight;
1252 // Set the current basic block to the mbb we wish to insert the code into
1253 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1254 FuncInfo->InsertPt = FuncInfo->MBB->end();
1255 // Emit the code
1256 if (j+1 != ej)
1257 SDB->visitBitTestCase(SDB->BitTestCases[i],
1258 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1259 UnhandledWeight,
1260 SDB->BitTestCases[i].Reg,
1261 SDB->BitTestCases[i].Cases[j],
1262 FuncInfo->MBB);
1263 else
1264 SDB->visitBitTestCase(SDB->BitTestCases[i],
1265 SDB->BitTestCases[i].Default,
1266 UnhandledWeight,
1267 SDB->BitTestCases[i].Reg,
1268 SDB->BitTestCases[i].Cases[j],
1269 FuncInfo->MBB);
1272 CurDAG->setRoot(SDB->getRoot());
1273 SDB->clear();
1274 CodeGenAndEmitDAG();
1275 }
1277 // Update PHI Nodes
1278 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1279 pi != pe; ++pi) {
1280 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1281 MachineBasicBlock *PHIBB = PHI->getParent();
1282 assert(PHI->isPHI() &&
1283 "This is not a machine PHI node that we are updating!");
1284 // This is "default" BB. We have two jumps to it. From "header" BB and
1285 // from last "case" BB.
1286 if (PHIBB == SDB->BitTestCases[i].Default)
1287 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1288 .addMBB(SDB->BitTestCases[i].Parent)
1289 .addReg(FuncInfo->PHINodesToUpdate[pi].second)
1290 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB);
1291 // One of "cases" BB.
1292 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1293 j != ej; ++j) {
1294 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1295 if (cBB->isSuccessor(PHIBB))
1296 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB);
1297 }
1298 }
1299 }
1300 SDB->BitTestCases.clear();
1302 // If the JumpTable record is filled in, then we need to emit a jump table.
1303 // Updating the PHI nodes is tricky in this case, since we need to determine
1304 // whether the PHI is a successor of the range check MBB or the jump table MBB
1305 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1306 // Lower header first, if it wasn't already lowered
1307 if (!SDB->JTCases[i].first.Emitted) {
1308 // Set the current basic block to the mbb we wish to insert the code into
1309 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1310 FuncInfo->InsertPt = FuncInfo->MBB->end();
1311 // Emit the code
1312 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1313 FuncInfo->MBB);
1314 CurDAG->setRoot(SDB->getRoot());
1315 SDB->clear();
1316 CodeGenAndEmitDAG();
1317 }
1319 // Set the current basic block to the mbb we wish to insert the code into
1320 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1321 FuncInfo->InsertPt = FuncInfo->MBB->end();
1322 // Emit the code
1323 SDB->visitJumpTable(SDB->JTCases[i].second);
1324 CurDAG->setRoot(SDB->getRoot());
1325 SDB->clear();
1326 CodeGenAndEmitDAG();
1328 // Update PHI Nodes
1329 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1330 pi != pe; ++pi) {
1331 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1332 MachineBasicBlock *PHIBB = PHI->getParent();
1333 assert(PHI->isPHI() &&
1334 "This is not a machine PHI node that we are updating!");
1335 // "default" BB. We can go there only from header BB.
1336 if (PHIBB == SDB->JTCases[i].second.Default)
1337 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1338 .addMBB(SDB->JTCases[i].first.HeaderBB);
1339 // JT BB. Just iterate over successors here
1340 if (FuncInfo->MBB->isSuccessor(PHIBB))
1341 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
1342 }
1343 }
1344 SDB->JTCases.clear();
1346 // If the switch block involved a branch to one of the actual successors, we
1347 // need to update PHI nodes in that block.
1348 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1349 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1350 assert(PHI->isPHI() &&
1351 "This is not a machine PHI node that we are updating!");
1352 if (FuncInfo->MBB->isSuccessor(PHI->getParent()))
1353 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1354 }
1356 // If we generated any switch lowering information, build and codegen any
1357 // additional DAGs necessary.
1358 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1359 // Set the current basic block to the mbb we wish to insert the code into
1360 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1361 FuncInfo->InsertPt = FuncInfo->MBB->end();
1363 // Determine the unique successors.
1364 SmallVector<MachineBasicBlock *, 2> Succs;
1365 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1366 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1367 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1369 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1370 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1371 CurDAG->setRoot(SDB->getRoot());
1372 SDB->clear();
1373 CodeGenAndEmitDAG();
1375 // Remember the last block, now that any splitting is done, for use in
1376 // populating PHI nodes in successors.
1377 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1379 // Handle any PHI nodes in successors of this chunk, as if we were coming
1380 // from the original BB before switch expansion. Note that PHI nodes can
1381 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1382 // handle them the right number of times.
1383 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1384 FuncInfo->MBB = Succs[i];
1385 FuncInfo->InsertPt = FuncInfo->MBB->end();
1386 // FuncInfo->MBB may have been removed from the CFG if a branch was
1387 // constant folded.
1388 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1389 for (MachineBasicBlock::iterator
1390 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end();
1391 MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
1392 MachineInstrBuilder PHI(*MF, MBBI);
1393 // This value for this PHI node is recorded in PHINodesToUpdate.
1394 for (unsigned pn = 0; ; ++pn) {
1395 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1396 "Didn't find PHI entry!");
1397 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) {
1398 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
1399 break;
1400 }
1401 }
1402 }
1403 }
1404 }
1405 }
1406 SDB->SwitchCases.clear();
1407 }
1410 /// Create the scheduler. If a specific scheduler was specified
1411 /// via the SchedulerRegistry, use it, otherwise select the
1412 /// one preferred by the target.
1413 ///
1414 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1415 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1417 if (!Ctor) {
1418 Ctor = ISHeuristic;
1419 RegisterScheduler::setDefault(Ctor);
1420 }
1422 return Ctor(this, OptLevel);
1423 }
1425 //===----------------------------------------------------------------------===//
1426 // Helper functions used by the generated instruction selector.
1427 //===----------------------------------------------------------------------===//
1428 // Calls to these methods are generated by tblgen.
1430 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1431 /// the dag combiner simplified the 255, we still want to match. RHS is the
1432 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1433 /// specified in the .td file (e.g. 255).
1434 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1435 int64_t DesiredMaskS) const {
1436 const APInt &ActualMask = RHS->getAPIntValue();
1437 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1439 // If the actual mask exactly matches, success!
1440 if (ActualMask == DesiredMask)
1441 return true;
1443 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1444 if (ActualMask.intersects(~DesiredMask))
1445 return false;
1447 // Otherwise, the DAG Combiner may have proven that the value coming in is
1448 // either already zero or is not demanded. Check for known zero input bits.
1449 APInt NeededMask = DesiredMask & ~ActualMask;
1450 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1451 return true;
1453 // TODO: check to see if missing bits are just not demanded.
1455 // Otherwise, this pattern doesn't match.
1456 return false;
1457 }
1459 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1460 /// the dag combiner simplified the 255, we still want to match. RHS is the
1461 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1462 /// specified in the .td file (e.g. 255).
1463 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1464 int64_t DesiredMaskS) const {
1465 const APInt &ActualMask = RHS->getAPIntValue();
1466 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1468 // If the actual mask exactly matches, success!
1469 if (ActualMask == DesiredMask)
1470 return true;
1472 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1473 if (ActualMask.intersects(~DesiredMask))
1474 return false;
1476 // Otherwise, the DAG Combiner may have proven that the value coming in is
1477 // either already zero or is not demanded. Check for known zero input bits.
1478 APInt NeededMask = DesiredMask & ~ActualMask;
1480 APInt KnownZero, KnownOne;
1481 CurDAG->ComputeMaskedBits(LHS, KnownZero, KnownOne);
1483 // If all the missing bits in the or are already known to be set, match!
1484 if ((NeededMask & KnownOne) == NeededMask)
1485 return true;
1487 // TODO: check to see if missing bits are just not demanded.
1489 // Otherwise, this pattern doesn't match.
1490 return false;
1491 }
1494 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1495 /// by tblgen. Others should not call it.
1496 void SelectionDAGISel::
1497 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1498 std::vector<SDValue> InOps;
1499 std::swap(InOps, Ops);
1501 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1502 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1503 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1504 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1506 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1507 if (InOps[e-1].getValueType() == MVT::Glue)
1508 --e; // Don't process a glue operand if it is here.
1510 while (i != e) {
1511 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1512 if (!InlineAsm::isMemKind(Flags)) {
1513 // Just skip over this operand, copying the operands verbatim.
1514 Ops.insert(Ops.end(), InOps.begin()+i,
1515 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1516 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1517 } else {
1518 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1519 "Memory operand with multiple values?");
1520 // Otherwise, this is a memory operand. Ask the target to select it.
1521 std::vector<SDValue> SelOps;
1522 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1523 report_fatal_error("Could not match memory address. Inline asm"
1524 " failure!");
1526 // Add this to the output node.
1527 unsigned NewFlags =
1528 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1529 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1530 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1531 i += 2;
1532 }
1533 }
1535 // Add the glue input back if present.
1536 if (e != InOps.size())
1537 Ops.push_back(InOps.back());
1538 }
1540 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1541 /// SDNode.
1542 ///
1543 static SDNode *findGlueUse(SDNode *N) {
1544 unsigned FlagResNo = N->getNumValues()-1;
1545 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1546 SDUse &Use = I.getUse();
1547 if (Use.getResNo() == FlagResNo)
1548 return Use.getUser();
1549 }
1550 return NULL;
1551 }
1553 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1554 /// This function recursively traverses up the operand chain, ignoring
1555 /// certain nodes.
1556 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1557 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1558 bool IgnoreChains) {
1559 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1560 // greater than all of its (recursive) operands. If we scan to a point where
1561 // 'use' is smaller than the node we're scanning for, then we know we will
1562 // never find it.
1563 //
1564 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1565 // happen because we scan down to newly selected nodes in the case of glue
1566 // uses.
1567 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1568 return false;
1570 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1571 // won't fail if we scan it again.
1572 if (!Visited.insert(Use))
1573 return false;
1575 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1576 // Ignore chain uses, they are validated by HandleMergeInputChains.
1577 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1578 continue;
1580 SDNode *N = Use->getOperand(i).getNode();
1581 if (N == Def) {
1582 if (Use == ImmedUse || Use == Root)
1583 continue; // We are not looking for immediate use.
1584 assert(N != Root);
1585 return true;
1586 }
1588 // Traverse up the operand chain.
1589 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1590 return true;
1591 }
1592 return false;
1593 }
1595 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1596 /// operand node N of U during instruction selection that starts at Root.
1597 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1598 SDNode *Root) const {
1599 if (OptLevel == CodeGenOpt::None) return false;
1600 return N.hasOneUse();
1601 }
1603 /// IsLegalToFold - Returns true if the specific operand node N of
1604 /// U can be folded during instruction selection that starts at Root.
1605 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1606 CodeGenOpt::Level OptLevel,
1607 bool IgnoreChains) {
1608 if (OptLevel == CodeGenOpt::None) return false;
1610 // If Root use can somehow reach N through a path that that doesn't contain
1611 // U then folding N would create a cycle. e.g. In the following
1612 // diagram, Root can reach N through X. If N is folded into into Root, then
1613 // X is both a predecessor and a successor of U.
1614 //
1615 // [N*] //
1616 // ^ ^ //
1617 // / \ //
1618 // [U*] [X]? //
1619 // ^ ^ //
1620 // \ / //
1621 // \ / //
1622 // [Root*] //
1623 //
1624 // * indicates nodes to be folded together.
1625 //
1626 // If Root produces glue, then it gets (even more) interesting. Since it
1627 // will be "glued" together with its glue use in the scheduler, we need to
1628 // check if it might reach N.
1629 //
1630 // [N*] //
1631 // ^ ^ //
1632 // / \ //
1633 // [U*] [X]? //
1634 // ^ ^ //
1635 // \ \ //
1636 // \ | //
1637 // [Root*] | //
1638 // ^ | //
1639 // f | //
1640 // | / //
1641 // [Y] / //
1642 // ^ / //
1643 // f / //
1644 // | / //
1645 // [GU] //
1646 //
1647 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1648 // (call it Fold), then X is a predecessor of GU and a successor of
1649 // Fold. But since Fold and GU are glued together, this will create
1650 // a cycle in the scheduling graph.
1652 // If the node has glue, walk down the graph to the "lowest" node in the
1653 // glueged set.
1654 EVT VT = Root->getValueType(Root->getNumValues()-1);
1655 while (VT == MVT::Glue) {
1656 SDNode *GU = findGlueUse(Root);
1657 if (GU == NULL)
1658 break;
1659 Root = GU;
1660 VT = Root->getValueType(Root->getNumValues()-1);
1662 // If our query node has a glue result with a use, we've walked up it. If
1663 // the user (which has already been selected) has a chain or indirectly uses
1664 // the chain, our WalkChainUsers predicate will not consider it. Because of
1665 // this, we cannot ignore chains in this predicate.
1666 IgnoreChains = false;
1667 }
1670 SmallPtrSet<SDNode*, 16> Visited;
1671 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1672 }
1674 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1675 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1676 SelectInlineAsmMemoryOperands(Ops);
1678 std::vector<EVT> VTs;
1679 VTs.push_back(MVT::Other);
1680 VTs.push_back(MVT::Glue);
1681 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1682 VTs, &Ops[0], Ops.size());
1683 New->setNodeId(-1);
1684 return New.getNode();
1685 }
1687 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1688 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1689 }
1691 /// GetVBR - decode a vbr encoding whose top bit is set.
1692 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1693 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1694 assert(Val >= 128 && "Not a VBR");
1695 Val &= 127; // Remove first vbr bit.
1697 unsigned Shift = 7;
1698 uint64_t NextBits;
1699 do {
1700 NextBits = MatcherTable[Idx++];
1701 Val |= (NextBits&127) << Shift;
1702 Shift += 7;
1703 } while (NextBits & 128);
1705 return Val;
1706 }
1709 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1710 /// interior glue and chain results to use the new glue and chain results.
1711 void SelectionDAGISel::
1712 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1713 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1714 SDValue InputGlue,
1715 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1716 bool isMorphNodeTo) {
1717 SmallVector<SDNode*, 4> NowDeadNodes;
1719 // Now that all the normal results are replaced, we replace the chain and
1720 // glue results if present.
1721 if (!ChainNodesMatched.empty()) {
1722 assert(InputChain.getNode() != 0 &&
1723 "Matched input chains but didn't produce a chain");
1724 // Loop over all of the nodes we matched that produced a chain result.
1725 // Replace all the chain results with the final chain we ended up with.
1726 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1727 SDNode *ChainNode = ChainNodesMatched[i];
1729 // If this node was already deleted, don't look at it.
1730 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1731 continue;
1733 // Don't replace the results of the root node if we're doing a
1734 // MorphNodeTo.
1735 if (ChainNode == NodeToMatch && isMorphNodeTo)
1736 continue;
1738 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1739 if (ChainVal.getValueType() == MVT::Glue)
1740 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1741 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1742 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain);
1744 // If the node became dead and we haven't already seen it, delete it.
1745 if (ChainNode->use_empty() &&
1746 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1747 NowDeadNodes.push_back(ChainNode);
1748 }
1749 }
1751 // If the result produces glue, update any glue results in the matched
1752 // pattern with the glue result.
1753 if (InputGlue.getNode() != 0) {
1754 // Handle any interior nodes explicitly marked.
1755 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
1756 SDNode *FRN = GlueResultNodesMatched[i];
1758 // If this node was already deleted, don't look at it.
1759 if (FRN->getOpcode() == ISD::DELETED_NODE)
1760 continue;
1762 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
1763 "Doesn't have a glue result");
1764 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1765 InputGlue);
1767 // If the node became dead and we haven't already seen it, delete it.
1768 if (FRN->use_empty() &&
1769 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1770 NowDeadNodes.push_back(FRN);
1771 }
1772 }
1774 if (!NowDeadNodes.empty())
1775 CurDAG->RemoveDeadNodes(NowDeadNodes);
1777 DEBUG(errs() << "ISEL: Match complete!\n");
1778 }
1780 enum ChainResult {
1781 CR_Simple,
1782 CR_InducesCycle,
1783 CR_LeadsToInteriorNode
1784 };
1786 /// WalkChainUsers - Walk down the users of the specified chained node that is
1787 /// part of the pattern we're matching, looking at all of the users we find.
1788 /// This determines whether something is an interior node, whether we have a
1789 /// non-pattern node in between two pattern nodes (which prevent folding because
1790 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1791 /// between pattern nodes (in which case the TF becomes part of the pattern).
1792 ///
1793 /// The walk we do here is guaranteed to be small because we quickly get down to
1794 /// already selected nodes "below" us.
1795 static ChainResult
1796 WalkChainUsers(const SDNode *ChainedNode,
1797 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1798 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1799 ChainResult Result = CR_Simple;
1801 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1802 E = ChainedNode->use_end(); UI != E; ++UI) {
1803 // Make sure the use is of the chain, not some other value we produce.
1804 if (UI.getUse().getValueType() != MVT::Other) continue;
1806 SDNode *User = *UI;
1808 // If we see an already-selected machine node, then we've gone beyond the
1809 // pattern that we're selecting down into the already selected chunk of the
1810 // DAG.
1811 if (User->isMachineOpcode() ||
1812 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1813 continue;
1815 unsigned UserOpcode = User->getOpcode();
1816 if (UserOpcode == ISD::CopyToReg ||
1817 UserOpcode == ISD::CopyFromReg ||
1818 UserOpcode == ISD::INLINEASM ||
1819 UserOpcode == ISD::EH_LABEL ||
1820 UserOpcode == ISD::LIFETIME_START ||
1821 UserOpcode == ISD::LIFETIME_END) {
1822 // If their node ID got reset to -1 then they've already been selected.
1823 // Treat them like a MachineOpcode.
1824 if (User->getNodeId() == -1)
1825 continue;
1826 }
1828 // If we have a TokenFactor, we handle it specially.
1829 if (User->getOpcode() != ISD::TokenFactor) {
1830 // If the node isn't a token factor and isn't part of our pattern, then it
1831 // must be a random chained node in between two nodes we're selecting.
1832 // This happens when we have something like:
1833 // x = load ptr
1834 // call
1835 // y = x+4
1836 // store y -> ptr
1837 // Because we structurally match the load/store as a read/modify/write,
1838 // but the call is chained between them. We cannot fold in this case
1839 // because it would induce a cycle in the graph.
1840 if (!std::count(ChainedNodesInPattern.begin(),
1841 ChainedNodesInPattern.end(), User))
1842 return CR_InducesCycle;
1844 // Otherwise we found a node that is part of our pattern. For example in:
1845 // x = load ptr
1846 // y = x+4
1847 // store y -> ptr
1848 // This would happen when we're scanning down from the load and see the
1849 // store as a user. Record that there is a use of ChainedNode that is
1850 // part of the pattern and keep scanning uses.
1851 Result = CR_LeadsToInteriorNode;
1852 InteriorChainedNodes.push_back(User);
1853 continue;
1854 }
1856 // If we found a TokenFactor, there are two cases to consider: first if the
1857 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1858 // uses of the TF are in our pattern) we just want to ignore it. Second,
1859 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1860 // [Load chain]
1861 // ^
1862 // |
1863 // [Load]
1864 // ^ ^
1865 // | \ DAG's like cheese
1866 // / \ do you?
1867 // / |
1868 // [TokenFactor] [Op]
1869 // ^ ^
1870 // | |
1871 // \ /
1872 // \ /
1873 // [Store]
1874 //
1875 // In this case, the TokenFactor becomes part of our match and we rewrite it
1876 // as a new TokenFactor.
1877 //
1878 // To distinguish these two cases, do a recursive walk down the uses.
1879 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1880 case CR_Simple:
1881 // If the uses of the TokenFactor are just already-selected nodes, ignore
1882 // it, it is "below" our pattern.
1883 continue;
1884 case CR_InducesCycle:
1885 // If the uses of the TokenFactor lead to nodes that are not part of our
1886 // pattern that are not selected, folding would turn this into a cycle,
1887 // bail out now.
1888 return CR_InducesCycle;
1889 case CR_LeadsToInteriorNode:
1890 break; // Otherwise, keep processing.
1891 }
1893 // Okay, we know we're in the interesting interior case. The TokenFactor
1894 // is now going to be considered part of the pattern so that we rewrite its
1895 // uses (it may have uses that are not part of the pattern) with the
1896 // ultimate chain result of the generated code. We will also add its chain
1897 // inputs as inputs to the ultimate TokenFactor we create.
1898 Result = CR_LeadsToInteriorNode;
1899 ChainedNodesInPattern.push_back(User);
1900 InteriorChainedNodes.push_back(User);
1901 continue;
1902 }
1904 return Result;
1905 }
1907 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1908 /// operation for when the pattern matched at least one node with a chains. The
1909 /// input vector contains a list of all of the chained nodes that we match. We
1910 /// must determine if this is a valid thing to cover (i.e. matching it won't
1911 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1912 /// be used as the input node chain for the generated nodes.
1913 static SDValue
1914 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1915 SelectionDAG *CurDAG) {
1916 // Walk all of the chained nodes we've matched, recursively scanning down the
1917 // users of the chain result. This adds any TokenFactor nodes that are caught
1918 // in between chained nodes to the chained and interior nodes list.
1919 SmallVector<SDNode*, 3> InteriorChainedNodes;
1920 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1921 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1922 InteriorChainedNodes) == CR_InducesCycle)
1923 return SDValue(); // Would induce a cycle.
1924 }
1926 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1927 // that we are interested in. Form our input TokenFactor node.
1928 SmallVector<SDValue, 3> InputChains;
1929 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1930 // Add the input chain of this node to the InputChains list (which will be
1931 // the operands of the generated TokenFactor) if it's not an interior node.
1932 SDNode *N = ChainNodesMatched[i];
1933 if (N->getOpcode() != ISD::TokenFactor) {
1934 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1935 continue;
1937 // Otherwise, add the input chain.
1938 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1939 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1940 InputChains.push_back(InChain);
1941 continue;
1942 }
1944 // If we have a token factor, we want to add all inputs of the token factor
1945 // that are not part of the pattern we're matching.
1946 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1947 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1948 N->getOperand(op).getNode()))
1949 InputChains.push_back(N->getOperand(op));
1950 }
1951 }
1953 SDValue Res;
1954 if (InputChains.size() == 1)
1955 return InputChains[0];
1956 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1957 MVT::Other, &InputChains[0], InputChains.size());
1958 }
1960 /// MorphNode - Handle morphing a node in place for the selector.
1961 SDNode *SelectionDAGISel::
1962 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1963 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1964 // It is possible we're using MorphNodeTo to replace a node with no
1965 // normal results with one that has a normal result (or we could be
1966 // adding a chain) and the input could have glue and chains as well.
1967 // In this case we need to shift the operands down.
1968 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1969 // than the old isel though.
1970 int OldGlueResultNo = -1, OldChainResultNo = -1;
1972 unsigned NTMNumResults = Node->getNumValues();
1973 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
1974 OldGlueResultNo = NTMNumResults-1;
1975 if (NTMNumResults != 1 &&
1976 Node->getValueType(NTMNumResults-2) == MVT::Other)
1977 OldChainResultNo = NTMNumResults-2;
1978 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1979 OldChainResultNo = NTMNumResults-1;
1981 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1982 // that this deletes operands of the old node that become dead.
1983 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1985 // MorphNodeTo can operate in two ways: if an existing node with the
1986 // specified operands exists, it can just return it. Otherwise, it
1987 // updates the node in place to have the requested operands.
1988 if (Res == Node) {
1989 // If we updated the node in place, reset the node ID. To the isel,
1990 // this should be just like a newly allocated machine node.
1991 Res->setNodeId(-1);
1992 }
1994 unsigned ResNumResults = Res->getNumValues();
1995 // Move the glue if needed.
1996 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
1997 (unsigned)OldGlueResultNo != ResNumResults-1)
1998 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
1999 SDValue(Res, ResNumResults-1));
2001 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
2002 --ResNumResults;
2004 // Move the chain reference if needed.
2005 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
2006 (unsigned)OldChainResultNo != ResNumResults-1)
2007 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
2008 SDValue(Res, ResNumResults-1));
2010 // Otherwise, no replacement happened because the node already exists. Replace
2011 // Uses of the old node with the new one.
2012 if (Res != Node)
2013 CurDAG->ReplaceAllUsesWith(Node, Res);
2015 return Res;
2016 }
2018 /// CheckSame - Implements OP_CheckSame.
2019 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2020 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2021 SDValue N,
2022 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2023 // Accept if it is exactly the same as a previously recorded node.
2024 unsigned RecNo = MatcherTable[MatcherIndex++];
2025 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2026 return N == RecordedNodes[RecNo].first;
2027 }
2029 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2030 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2031 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2032 const SelectionDAGISel &SDISel) {
2033 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
2034 }
2036 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
2037 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2038 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2039 const SelectionDAGISel &SDISel, SDNode *N) {
2040 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
2041 }
2043 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2044 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2045 SDNode *N) {
2046 uint16_t Opc = MatcherTable[MatcherIndex++];
2047 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2048 return N->getOpcode() == Opc;
2049 }
2051 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2052 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2053 SDValue N, const TargetLowering &TLI) {
2054 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2055 if (N.getValueType() == VT) return true;
2057 // Handle the case when VT is iPTR.
2058 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
2059 }
2061 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2062 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2063 SDValue N, const TargetLowering &TLI,
2064 unsigned ChildNo) {
2065 if (ChildNo >= N.getNumOperands())
2066 return false; // Match fails if out of range child #.
2067 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
2068 }
2071 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2072 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2073 SDValue N) {
2074 return cast<CondCodeSDNode>(N)->get() ==
2075 (ISD::CondCode)MatcherTable[MatcherIndex++];
2076 }
2078 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2079 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2080 SDValue N, const TargetLowering &TLI) {
2081 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2082 if (cast<VTSDNode>(N)->getVT() == VT)
2083 return true;
2085 // Handle the case when VT is iPTR.
2086 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
2087 }
2089 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2090 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2091 SDValue N) {
2092 int64_t Val = MatcherTable[MatcherIndex++];
2093 if (Val & 128)
2094 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2096 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2097 return C != 0 && C->getSExtValue() == Val;
2098 }
2100 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2101 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2102 SDValue N, const SelectionDAGISel &SDISel) {
2103 int64_t Val = MatcherTable[MatcherIndex++];
2104 if (Val & 128)
2105 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2107 if (N->getOpcode() != ISD::AND) return false;
2109 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2110 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2111 }
2113 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2114 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2115 SDValue N, const SelectionDAGISel &SDISel) {
2116 int64_t Val = MatcherTable[MatcherIndex++];
2117 if (Val & 128)
2118 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2120 if (N->getOpcode() != ISD::OR) return false;
2122 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2123 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2124 }
2126 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2127 /// scope, evaluate the current node. If the current predicate is known to
2128 /// fail, set Result=true and return anything. If the current predicate is
2129 /// known to pass, set Result=false and return the MatcherIndex to continue
2130 /// with. If the current predicate is unknown, set Result=false and return the
2131 /// MatcherIndex to continue with.
2132 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2133 unsigned Index, SDValue N,
2134 bool &Result,
2135 const SelectionDAGISel &SDISel,
2136 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2137 switch (Table[Index++]) {
2138 default:
2139 Result = false;
2140 return Index-1; // Could not evaluate this predicate.
2141 case SelectionDAGISel::OPC_CheckSame:
2142 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2143 return Index;
2144 case SelectionDAGISel::OPC_CheckPatternPredicate:
2145 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2146 return Index;
2147 case SelectionDAGISel::OPC_CheckPredicate:
2148 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2149 return Index;
2150 case SelectionDAGISel::OPC_CheckOpcode:
2151 Result = !::CheckOpcode(Table, Index, N.getNode());
2152 return Index;
2153 case SelectionDAGISel::OPC_CheckType:
2154 Result = !::CheckType(Table, Index, N, SDISel.TLI);
2155 return Index;
2156 case SelectionDAGISel::OPC_CheckChild0Type:
2157 case SelectionDAGISel::OPC_CheckChild1Type:
2158 case SelectionDAGISel::OPC_CheckChild2Type:
2159 case SelectionDAGISel::OPC_CheckChild3Type:
2160 case SelectionDAGISel::OPC_CheckChild4Type:
2161 case SelectionDAGISel::OPC_CheckChild5Type:
2162 case SelectionDAGISel::OPC_CheckChild6Type:
2163 case SelectionDAGISel::OPC_CheckChild7Type:
2164 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
2165 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
2166 return Index;
2167 case SelectionDAGISel::OPC_CheckCondCode:
2168 Result = !::CheckCondCode(Table, Index, N);
2169 return Index;
2170 case SelectionDAGISel::OPC_CheckValueType:
2171 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
2172 return Index;
2173 case SelectionDAGISel::OPC_CheckInteger:
2174 Result = !::CheckInteger(Table, Index, N);
2175 return Index;
2176 case SelectionDAGISel::OPC_CheckAndImm:
2177 Result = !::CheckAndImm(Table, Index, N, SDISel);
2178 return Index;
2179 case SelectionDAGISel::OPC_CheckOrImm:
2180 Result = !::CheckOrImm(Table, Index, N, SDISel);
2181 return Index;
2182 }
2183 }
2185 namespace {
2187 struct MatchScope {
2188 /// FailIndex - If this match fails, this is the index to continue with.
2189 unsigned FailIndex;
2191 /// NodeStack - The node stack when the scope was formed.
2192 SmallVector<SDValue, 4> NodeStack;
2194 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2195 unsigned NumRecordedNodes;
2197 /// NumMatchedMemRefs - The number of matched memref entries.
2198 unsigned NumMatchedMemRefs;
2200 /// InputChain/InputGlue - The current chain/glue
2201 SDValue InputChain, InputGlue;
2203 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2204 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2205 };
2207 }
2209 SDNode *SelectionDAGISel::
2210 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2211 unsigned TableSize) {
2212 // FIXME: Should these even be selected? Handle these cases in the caller?
2213 switch (NodeToMatch->getOpcode()) {
2214 default:
2215 break;
2216 case ISD::EntryToken: // These nodes remain the same.
2217 case ISD::BasicBlock:
2218 case ISD::Register:
2219 case ISD::RegisterMask:
2220 //case ISD::VALUETYPE:
2221 //case ISD::CONDCODE:
2222 case ISD::HANDLENODE:
2223 case ISD::MDNODE_SDNODE:
2224 case ISD::TargetConstant:
2225 case ISD::TargetConstantFP:
2226 case ISD::TargetConstantPool:
2227 case ISD::TargetFrameIndex:
2228 case ISD::TargetExternalSymbol:
2229 case ISD::TargetBlockAddress:
2230 case ISD::TargetJumpTable:
2231 case ISD::TargetGlobalTLSAddress:
2232 case ISD::TargetGlobalAddress:
2233 case ISD::TokenFactor:
2234 case ISD::CopyFromReg:
2235 case ISD::CopyToReg:
2236 case ISD::EH_LABEL:
2237 case ISD::LIFETIME_START:
2238 case ISD::LIFETIME_END:
2239 NodeToMatch->setNodeId(-1); // Mark selected.
2240 return 0;
2241 case ISD::AssertSext:
2242 case ISD::AssertZext:
2243 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2244 NodeToMatch->getOperand(0));
2245 return 0;
2246 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2247 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2248 }
2250 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2252 // Set up the node stack with NodeToMatch as the only node on the stack.
2253 SmallVector<SDValue, 8> NodeStack;
2254 SDValue N = SDValue(NodeToMatch, 0);
2255 NodeStack.push_back(N);
2257 // MatchScopes - Scopes used when matching, if a match failure happens, this
2258 // indicates where to continue checking.
2259 SmallVector<MatchScope, 8> MatchScopes;
2261 // RecordedNodes - This is the set of nodes that have been recorded by the
2262 // state machine. The second value is the parent of the node, or null if the
2263 // root is recorded.
2264 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2266 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2267 // pattern.
2268 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2270 // These are the current input chain and glue for use when generating nodes.
2271 // Various Emit operations change these. For example, emitting a copytoreg
2272 // uses and updates these.
2273 SDValue InputChain, InputGlue;
2275 // ChainNodesMatched - If a pattern matches nodes that have input/output
2276 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2277 // which ones they are. The result is captured into this list so that we can
2278 // update the chain results when the pattern is complete.
2279 SmallVector<SDNode*, 3> ChainNodesMatched;
2280 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2282 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
2283 NodeToMatch->dump(CurDAG);
2284 errs() << '\n');
2286 // Determine where to start the interpreter. Normally we start at opcode #0,
2287 // but if the state machine starts with an OPC_SwitchOpcode, then we
2288 // accelerate the first lookup (which is guaranteed to be hot) with the
2289 // OpcodeOffset table.
2290 unsigned MatcherIndex = 0;
2292 if (!OpcodeOffset.empty()) {
2293 // Already computed the OpcodeOffset table, just index into it.
2294 if (N.getOpcode() < OpcodeOffset.size())
2295 MatcherIndex = OpcodeOffset[N.getOpcode()];
2296 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
2298 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2299 // Otherwise, the table isn't computed, but the state machine does start
2300 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2301 // is the first time we're selecting an instruction.
2302 unsigned Idx = 1;
2303 while (1) {
2304 // Get the size of this case.
2305 unsigned CaseSize = MatcherTable[Idx++];
2306 if (CaseSize & 128)
2307 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2308 if (CaseSize == 0) break;
2310 // Get the opcode, add the index to the table.
2311 uint16_t Opc = MatcherTable[Idx++];
2312 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2313 if (Opc >= OpcodeOffset.size())
2314 OpcodeOffset.resize((Opc+1)*2);
2315 OpcodeOffset[Opc] = Idx;
2316 Idx += CaseSize;
2317 }
2319 // Okay, do the lookup for the first opcode.
2320 if (N.getOpcode() < OpcodeOffset.size())
2321 MatcherIndex = OpcodeOffset[N.getOpcode()];
2322 }
2324 while (1) {
2325 assert(MatcherIndex < TableSize && "Invalid index");
2326 #ifndef NDEBUG
2327 unsigned CurrentOpcodeIndex = MatcherIndex;
2328 #endif
2329 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2330 switch (Opcode) {
2331 case OPC_Scope: {
2332 // Okay, the semantics of this operation are that we should push a scope
2333 // then evaluate the first child. However, pushing a scope only to have
2334 // the first check fail (which then pops it) is inefficient. If we can
2335 // determine immediately that the first check (or first several) will
2336 // immediately fail, don't even bother pushing a scope for them.
2337 unsigned FailIndex;
2339 while (1) {
2340 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2341 if (NumToSkip & 128)
2342 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2343 // Found the end of the scope with no match.
2344 if (NumToSkip == 0) {
2345 FailIndex = 0;
2346 break;
2347 }
2349 FailIndex = MatcherIndex+NumToSkip;
2351 unsigned MatcherIndexOfPredicate = MatcherIndex;
2352 (void)MatcherIndexOfPredicate; // silence warning.
2354 // If we can't evaluate this predicate without pushing a scope (e.g. if
2355 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2356 // push the scope and evaluate the full predicate chain.
2357 bool Result;
2358 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2359 Result, *this, RecordedNodes);
2360 if (!Result)
2361 break;
2363 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2364 << "index " << MatcherIndexOfPredicate
2365 << ", continuing at " << FailIndex << "\n");
2366 DEBUG(++NumDAGIselRetries);
2368 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2369 // move to the next case.
2370 MatcherIndex = FailIndex;
2371 }
2373 // If the whole scope failed to match, bail.
2374 if (FailIndex == 0) break;
2376 // Push a MatchScope which indicates where to go if the first child fails
2377 // to match.
2378 MatchScope NewEntry;
2379 NewEntry.FailIndex = FailIndex;
2380 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2381 NewEntry.NumRecordedNodes = RecordedNodes.size();
2382 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2383 NewEntry.InputChain = InputChain;
2384 NewEntry.InputGlue = InputGlue;
2385 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2386 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2387 MatchScopes.push_back(NewEntry);
2388 continue;
2389 }
2390 case OPC_RecordNode: {
2391 // Remember this node, it may end up being an operand in the pattern.
2392 SDNode *Parent = 0;
2393 if (NodeStack.size() > 1)
2394 Parent = NodeStack[NodeStack.size()-2].getNode();
2395 RecordedNodes.push_back(std::make_pair(N, Parent));
2396 continue;
2397 }
2399 case OPC_RecordChild0: case OPC_RecordChild1:
2400 case OPC_RecordChild2: case OPC_RecordChild3:
2401 case OPC_RecordChild4: case OPC_RecordChild5:
2402 case OPC_RecordChild6: case OPC_RecordChild7: {
2403 unsigned ChildNo = Opcode-OPC_RecordChild0;
2404 if (ChildNo >= N.getNumOperands())
2405 break; // Match fails if out of range child #.
2407 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2408 N.getNode()));
2409 continue;
2410 }
2411 case OPC_RecordMemRef:
2412 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2413 continue;
2415 case OPC_CaptureGlueInput:
2416 // If the current node has an input glue, capture it in InputGlue.
2417 if (N->getNumOperands() != 0 &&
2418 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2419 InputGlue = N->getOperand(N->getNumOperands()-1);
2420 continue;
2422 case OPC_MoveChild: {
2423 unsigned ChildNo = MatcherTable[MatcherIndex++];
2424 if (ChildNo >= N.getNumOperands())
2425 break; // Match fails if out of range child #.
2426 N = N.getOperand(ChildNo);
2427 NodeStack.push_back(N);
2428 continue;
2429 }
2431 case OPC_MoveParent:
2432 // Pop the current node off the NodeStack.
2433 NodeStack.pop_back();
2434 assert(!NodeStack.empty() && "Node stack imbalance!");
2435 N = NodeStack.back();
2436 continue;
2438 case OPC_CheckSame:
2439 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2440 continue;
2441 case OPC_CheckPatternPredicate:
2442 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2443 continue;
2444 case OPC_CheckPredicate:
2445 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2446 N.getNode()))
2447 break;
2448 continue;
2449 case OPC_CheckComplexPat: {
2450 unsigned CPNum = MatcherTable[MatcherIndex++];
2451 unsigned RecNo = MatcherTable[MatcherIndex++];
2452 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2453 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2454 RecordedNodes[RecNo].first, CPNum,
2455 RecordedNodes))
2456 break;
2457 continue;
2458 }
2459 case OPC_CheckOpcode:
2460 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2461 continue;
2463 case OPC_CheckType:
2464 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2465 continue;
2467 case OPC_SwitchOpcode: {
2468 unsigned CurNodeOpcode = N.getOpcode();
2469 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2470 unsigned CaseSize;
2471 while (1) {
2472 // Get the size of this case.
2473 CaseSize = MatcherTable[MatcherIndex++];
2474 if (CaseSize & 128)
2475 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2476 if (CaseSize == 0) break;
2478 uint16_t Opc = MatcherTable[MatcherIndex++];
2479 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2481 // If the opcode matches, then we will execute this case.
2482 if (CurNodeOpcode == Opc)
2483 break;
2485 // Otherwise, skip over this case.
2486 MatcherIndex += CaseSize;
2487 }
2489 // If no cases matched, bail out.
2490 if (CaseSize == 0) break;
2492 // Otherwise, execute the case we found.
2493 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2494 << " to " << MatcherIndex << "\n");
2495 continue;
2496 }
2498 case OPC_SwitchType: {
2499 MVT CurNodeVT = N.getValueType().getSimpleVT();
2500 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2501 unsigned CaseSize;
2502 while (1) {
2503 // Get the size of this case.
2504 CaseSize = MatcherTable[MatcherIndex++];
2505 if (CaseSize & 128)
2506 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2507 if (CaseSize == 0) break;
2509 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2510 if (CaseVT == MVT::iPTR)
2511 CaseVT = TLI.getPointerTy();
2513 // If the VT matches, then we will execute this case.
2514 if (CurNodeVT == CaseVT)
2515 break;
2517 // Otherwise, skip over this case.
2518 MatcherIndex += CaseSize;
2519 }
2521 // If no cases matched, bail out.
2522 if (CaseSize == 0) break;
2524 // Otherwise, execute the case we found.
2525 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2526 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2527 continue;
2528 }
2529 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2530 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2531 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2532 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2533 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2534 Opcode-OPC_CheckChild0Type))
2535 break;
2536 continue;
2537 case OPC_CheckCondCode:
2538 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2539 continue;
2540 case OPC_CheckValueType:
2541 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2542 continue;
2543 case OPC_CheckInteger:
2544 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2545 continue;
2546 case OPC_CheckAndImm:
2547 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2548 continue;
2549 case OPC_CheckOrImm:
2550 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2551 continue;
2553 case OPC_CheckFoldableChainNode: {
2554 assert(NodeStack.size() != 1 && "No parent node");
2555 // Verify that all intermediate nodes between the root and this one have
2556 // a single use.
2557 bool HasMultipleUses = false;
2558 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2559 if (!NodeStack[i].hasOneUse()) {
2560 HasMultipleUses = true;
2561 break;
2562 }
2563 if (HasMultipleUses) break;
2565 // Check to see that the target thinks this is profitable to fold and that
2566 // we can fold it without inducing cycles in the graph.
2567 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2568 NodeToMatch) ||
2569 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2570 NodeToMatch, OptLevel,
2571 true/*We validate our own chains*/))
2572 break;
2574 continue;
2575 }
2576 case OPC_EmitInteger: {
2577 MVT::SimpleValueType VT =
2578 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2579 int64_t Val = MatcherTable[MatcherIndex++];
2580 if (Val & 128)
2581 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2582 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2583 CurDAG->getTargetConstant(Val, VT), (SDNode*)0));
2584 continue;
2585 }
2586 case OPC_EmitRegister: {
2587 MVT::SimpleValueType VT =
2588 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2589 unsigned RegNo = MatcherTable[MatcherIndex++];
2590 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2591 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2592 continue;
2593 }
2594 case OPC_EmitRegister2: {
2595 // For targets w/ more than 256 register names, the register enum
2596 // values are stored in two bytes in the matcher table (just like
2597 // opcodes).
2598 MVT::SimpleValueType VT =
2599 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2600 unsigned RegNo = MatcherTable[MatcherIndex++];
2601 RegNo |= MatcherTable[MatcherIndex++] << 8;
2602 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2603 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2604 continue;
2605 }
2607 case OPC_EmitConvertToTarget: {
2608 // Convert from IMM/FPIMM to target version.
2609 unsigned RecNo = MatcherTable[MatcherIndex++];
2610 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2611 SDValue Imm = RecordedNodes[RecNo].first;
2613 if (Imm->getOpcode() == ISD::Constant) {
2614 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2615 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2616 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2617 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2618 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2619 }
2621 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2622 continue;
2623 }
2625 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2626 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2627 // These are space-optimized forms of OPC_EmitMergeInputChains.
2628 assert(InputChain.getNode() == 0 &&
2629 "EmitMergeInputChains should be the first chain producing node");
2630 assert(ChainNodesMatched.empty() &&
2631 "Should only have one EmitMergeInputChains per match");
2633 // Read all of the chained nodes.
2634 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2635 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2636 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2638 // FIXME: What if other value results of the node have uses not matched
2639 // by this pattern?
2640 if (ChainNodesMatched.back() != NodeToMatch &&
2641 !RecordedNodes[RecNo].first.hasOneUse()) {
2642 ChainNodesMatched.clear();
2643 break;
2644 }
2646 // Merge the input chains if they are not intra-pattern references.
2647 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2649 if (InputChain.getNode() == 0)
2650 break; // Failed to merge.
2651 continue;
2652 }
2654 case OPC_EmitMergeInputChains: {
2655 assert(InputChain.getNode() == 0 &&
2656 "EmitMergeInputChains should be the first chain producing node");
2657 // This node gets a list of nodes we matched in the input that have
2658 // chains. We want to token factor all of the input chains to these nodes
2659 // together. However, if any of the input chains is actually one of the
2660 // nodes matched in this pattern, then we have an intra-match reference.
2661 // Ignore these because the newly token factored chain should not refer to
2662 // the old nodes.
2663 unsigned NumChains = MatcherTable[MatcherIndex++];
2664 assert(NumChains != 0 && "Can't TF zero chains");
2666 assert(ChainNodesMatched.empty() &&
2667 "Should only have one EmitMergeInputChains per match");
2669 // Read all of the chained nodes.
2670 for (unsigned i = 0; i != NumChains; ++i) {
2671 unsigned RecNo = MatcherTable[MatcherIndex++];
2672 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2673 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2675 // FIXME: What if other value results of the node have uses not matched
2676 // by this pattern?
2677 if (ChainNodesMatched.back() != NodeToMatch &&
2678 !RecordedNodes[RecNo].first.hasOneUse()) {
2679 ChainNodesMatched.clear();
2680 break;
2681 }
2682 }
2684 // If the inner loop broke out, the match fails.
2685 if (ChainNodesMatched.empty())
2686 break;
2688 // Merge the input chains if they are not intra-pattern references.
2689 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2691 if (InputChain.getNode() == 0)
2692 break; // Failed to merge.
2694 continue;
2695 }
2697 case OPC_EmitCopyToReg: {
2698 unsigned RecNo = MatcherTable[MatcherIndex++];
2699 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2700 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2702 if (InputChain.getNode() == 0)
2703 InputChain = CurDAG->getEntryNode();
2705 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2706 DestPhysReg, RecordedNodes[RecNo].first,
2707 InputGlue);
2709 InputGlue = InputChain.getValue(1);
2710 continue;
2711 }
2713 case OPC_EmitNodeXForm: {
2714 unsigned XFormNo = MatcherTable[MatcherIndex++];
2715 unsigned RecNo = MatcherTable[MatcherIndex++];
2716 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2717 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
2718 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0));
2719 continue;
2720 }
2722 case OPC_EmitNode:
2723 case OPC_MorphNodeTo: {
2724 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2725 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2726 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2727 // Get the result VT list.
2728 unsigned NumVTs = MatcherTable[MatcherIndex++];
2729 SmallVector<EVT, 4> VTs;
2730 for (unsigned i = 0; i != NumVTs; ++i) {
2731 MVT::SimpleValueType VT =
2732 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2733 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2734 VTs.push_back(VT);
2735 }
2737 if (EmitNodeInfo & OPFL_Chain)
2738 VTs.push_back(MVT::Other);
2739 if (EmitNodeInfo & OPFL_GlueOutput)
2740 VTs.push_back(MVT::Glue);
2742 // This is hot code, so optimize the two most common cases of 1 and 2
2743 // results.
2744 SDVTList VTList;
2745 if (VTs.size() == 1)
2746 VTList = CurDAG->getVTList(VTs[0]);
2747 else if (VTs.size() == 2)
2748 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2749 else
2750 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2752 // Get the operand list.
2753 unsigned NumOps = MatcherTable[MatcherIndex++];
2754 SmallVector<SDValue, 8> Ops;
2755 for (unsigned i = 0; i != NumOps; ++i) {
2756 unsigned RecNo = MatcherTable[MatcherIndex++];
2757 if (RecNo & 128)
2758 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2760 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2761 Ops.push_back(RecordedNodes[RecNo].first);
2762 }
2764 // If there are variadic operands to add, handle them now.
2765 if (EmitNodeInfo & OPFL_VariadicInfo) {
2766 // Determine the start index to copy from.
2767 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2768 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2769 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2770 "Invalid variadic node");
2771 // Copy all of the variadic operands, not including a potential glue
2772 // input.
2773 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2774 i != e; ++i) {
2775 SDValue V = NodeToMatch->getOperand(i);
2776 if (V.getValueType() == MVT::Glue) break;
2777 Ops.push_back(V);
2778 }
2779 }
2781 // If this has chain/glue inputs, add them.
2782 if (EmitNodeInfo & OPFL_Chain)
2783 Ops.push_back(InputChain);
2784 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0)
2785 Ops.push_back(InputGlue);
2787 // Create the node.
2788 SDNode *Res = 0;
2789 if (Opcode != OPC_MorphNodeTo) {
2790 // If this is a normal EmitNode command, just create the new node and
2791 // add the results to the RecordedNodes list.
2792 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2793 VTList, Ops.data(), Ops.size());
2795 // Add all the non-glue/non-chain results to the RecordedNodes list.
2796 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2797 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
2798 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
2799 (SDNode*) 0));
2800 }
2802 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) {
2803 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2804 EmitNodeInfo);
2805 } else {
2806 // NodeToMatch was eliminated by CSE when the target changed the DAG.
2807 // We will visit the equivalent node later.
2808 DEBUG(dbgs() << "Node was eliminated by CSE\n");
2809 return 0;
2810 }
2812 // If the node had chain/glue results, update our notion of the current
2813 // chain and glue.
2814 if (EmitNodeInfo & OPFL_GlueOutput) {
2815 InputGlue = SDValue(Res, VTs.size()-1);
2816 if (EmitNodeInfo & OPFL_Chain)
2817 InputChain = SDValue(Res, VTs.size()-2);
2818 } else if (EmitNodeInfo & OPFL_Chain)
2819 InputChain = SDValue(Res, VTs.size()-1);
2821 // If the OPFL_MemRefs glue is set on this node, slap all of the
2822 // accumulated memrefs onto it.
2823 //
2824 // FIXME: This is vastly incorrect for patterns with multiple outputs
2825 // instructions that access memory and for ComplexPatterns that match
2826 // loads.
2827 if (EmitNodeInfo & OPFL_MemRefs) {
2828 // Only attach load or store memory operands if the generated
2829 // instruction may load or store.
2830 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc);
2831 bool mayLoad = MCID.mayLoad();
2832 bool mayStore = MCID.mayStore();
2834 unsigned NumMemRefs = 0;
2835 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2836 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2837 if ((*I)->isLoad()) {
2838 if (mayLoad)
2839 ++NumMemRefs;
2840 } else if ((*I)->isStore()) {
2841 if (mayStore)
2842 ++NumMemRefs;
2843 } else {
2844 ++NumMemRefs;
2845 }
2846 }
2848 MachineSDNode::mmo_iterator MemRefs =
2849 MF->allocateMemRefsArray(NumMemRefs);
2851 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
2852 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2853 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2854 if ((*I)->isLoad()) {
2855 if (mayLoad)
2856 *MemRefsPos++ = *I;
2857 } else if ((*I)->isStore()) {
2858 if (mayStore)
2859 *MemRefsPos++ = *I;
2860 } else {
2861 *MemRefsPos++ = *I;
2862 }
2863 }
2865 cast<MachineSDNode>(Res)
2866 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
2867 }
2869 DEBUG(errs() << " "
2870 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2871 << " node: "; Res->dump(CurDAG); errs() << "\n");
2873 // If this was a MorphNodeTo then we're completely done!
2874 if (Opcode == OPC_MorphNodeTo) {
2875 // Update chain and glue uses.
2876 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2877 InputGlue, GlueResultNodesMatched, true);
2878 return Res;
2879 }
2881 continue;
2882 }
2884 case OPC_MarkGlueResults: {
2885 unsigned NumNodes = MatcherTable[MatcherIndex++];
2887 // Read and remember all the glue-result nodes.
2888 for (unsigned i = 0; i != NumNodes; ++i) {
2889 unsigned RecNo = MatcherTable[MatcherIndex++];
2890 if (RecNo & 128)
2891 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2893 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2894 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2895 }
2896 continue;
2897 }
2899 case OPC_CompleteMatch: {
2900 // The match has been completed, and any new nodes (if any) have been
2901 // created. Patch up references to the matched dag to use the newly
2902 // created nodes.
2903 unsigned NumResults = MatcherTable[MatcherIndex++];
2905 for (unsigned i = 0; i != NumResults; ++i) {
2906 unsigned ResSlot = MatcherTable[MatcherIndex++];
2907 if (ResSlot & 128)
2908 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2910 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2911 SDValue Res = RecordedNodes[ResSlot].first;
2913 assert(i < NodeToMatch->getNumValues() &&
2914 NodeToMatch->getValueType(i) != MVT::Other &&
2915 NodeToMatch->getValueType(i) != MVT::Glue &&
2916 "Invalid number of results to complete!");
2917 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2918 NodeToMatch->getValueType(i) == MVT::iPTR ||
2919 Res.getValueType() == MVT::iPTR ||
2920 NodeToMatch->getValueType(i).getSizeInBits() ==
2921 Res.getValueType().getSizeInBits()) &&
2922 "invalid replacement");
2923 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2924 }
2926 // If the root node defines glue, add it to the glue nodes to update list.
2927 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
2928 GlueResultNodesMatched.push_back(NodeToMatch);
2930 // Update chain and glue uses.
2931 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2932 InputGlue, GlueResultNodesMatched, false);
2934 assert(NodeToMatch->use_empty() &&
2935 "Didn't replace all uses of the node?");
2937 // FIXME: We just return here, which interacts correctly with SelectRoot
2938 // above. We should fix this to not return an SDNode* anymore.
2939 return 0;
2940 }
2941 }
2943 // If the code reached this point, then the match failed. See if there is
2944 // another child to try in the current 'Scope', otherwise pop it until we
2945 // find a case to check.
2946 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2947 DEBUG(++NumDAGIselRetries);
2948 while (1) {
2949 if (MatchScopes.empty()) {
2950 CannotYetSelect(NodeToMatch);
2951 return 0;
2952 }
2954 // Restore the interpreter state back to the point where the scope was
2955 // formed.
2956 MatchScope &LastScope = MatchScopes.back();
2957 RecordedNodes.resize(LastScope.NumRecordedNodes);
2958 NodeStack.clear();
2959 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2960 N = NodeStack.back();
2962 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2963 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2964 MatcherIndex = LastScope.FailIndex;
2966 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2968 InputChain = LastScope.InputChain;
2969 InputGlue = LastScope.InputGlue;
2970 if (!LastScope.HasChainNodesMatched)
2971 ChainNodesMatched.clear();
2972 if (!LastScope.HasGlueResultNodesMatched)
2973 GlueResultNodesMatched.clear();
2975 // Check to see what the offset is at the new MatcherIndex. If it is zero
2976 // we have reached the end of this scope, otherwise we have another child
2977 // in the current scope to try.
2978 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2979 if (NumToSkip & 128)
2980 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2982 // If we have another child in this scope to match, update FailIndex and
2983 // try it.
2984 if (NumToSkip != 0) {
2985 LastScope.FailIndex = MatcherIndex+NumToSkip;
2986 break;
2987 }
2989 // End of this scope, pop it and try the next child in the containing
2990 // scope.
2991 MatchScopes.pop_back();
2992 }
2993 }
2994 }
2998 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2999 std::string msg;
3000 raw_string_ostream Msg(msg);
3001 Msg << "Cannot select: ";
3003 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
3004 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
3005 N->getOpcode() != ISD::INTRINSIC_VOID) {
3006 N->printrFull(Msg, CurDAG);
3007 Msg << "\nIn function: " << MF->getName();
3008 } else {
3009 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
3010 unsigned iid =
3011 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
3012 if (iid < Intrinsic::num_intrinsics)
3013 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
3014 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
3015 Msg << "target intrinsic %" << TII->getName(iid);
3016 else
3017 Msg << "unknown intrinsic #" << iid;
3018 }
3019 report_fatal_error(Msg.str());
3020 }
3022 char SelectionDAGISel::ID = 0;