1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This implements the SelectionDAGISel class.
11 //
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/CodeGen/FunctionLoweringInfo.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/Analysis/DebugInfo.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/LLVMContext.h"
29 #include "llvm/Module.h"
30 #include "llvm/CodeGen/FastISel.h"
31 #include "llvm/CodeGen/GCStrategy.h"
32 #include "llvm/CodeGen/GCMetadata.h"
33 #include "llvm/CodeGen/MachineFrameInfo.h"
34 #include "llvm/CodeGen/MachineFunction.h"
35 #include "llvm/CodeGen/MachineInstrBuilder.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
39 #include "llvm/CodeGen/SchedulerRegistry.h"
40 #include "llvm/CodeGen/SelectionDAG.h"
41 #include "llvm/Target/TargetRegisterInfo.h"
42 #include "llvm/Target/TargetIntrinsicInfo.h"
43 #include "llvm/Target/TargetInstrInfo.h"
44 #include "llvm/Target/TargetLowering.h"
45 #include "llvm/Target/TargetMachine.h"
46 #include "llvm/Target/TargetOptions.h"
47 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
48 #include "llvm/Support/Compiler.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/Timer.h"
52 #include "llvm/Support/raw_ostream.h"
53 #include "llvm/ADT/PostOrderIterator.h"
54 #include "llvm/ADT/Statistic.h"
55 #include <algorithm>
56 using namespace llvm;
58 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
59 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
60 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
61 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
62 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
64 static cl::opt<bool>
65 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
66 cl::desc("Enable verbose messages in the \"fast\" "
67 "instruction selector"));
68 static cl::opt<bool>
69 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
70 cl::desc("Enable abort calls when \"fast\" instruction fails"));
72 static cl::opt<bool>
73 UseMBPI("use-mbpi",
74 cl::desc("use Machine Branch Probability Info"),
75 cl::init(true), cl::Hidden);
77 #ifndef NDEBUG
78 static cl::opt<bool>
79 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
80 cl::desc("Pop up a window to show dags before the first "
81 "dag combine pass"));
82 static cl::opt<bool>
83 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
84 cl::desc("Pop up a window to show dags before legalize types"));
85 static cl::opt<bool>
86 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
87 cl::desc("Pop up a window to show dags before legalize"));
88 static cl::opt<bool>
89 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
90 cl::desc("Pop up a window to show dags before the second "
91 "dag combine pass"));
92 static cl::opt<bool>
93 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
94 cl::desc("Pop up a window to show dags before the post legalize types"
95 " dag combine pass"));
96 static cl::opt<bool>
97 ViewISelDAGs("view-isel-dags", cl::Hidden,
98 cl::desc("Pop up a window to show isel dags as they are selected"));
99 static cl::opt<bool>
100 ViewSchedDAGs("view-sched-dags", cl::Hidden,
101 cl::desc("Pop up a window to show sched dags as they are processed"));
102 static cl::opt<bool>
103 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
104 cl::desc("Pop up a window to show SUnit dags after they are processed"));
105 #else
106 static const bool ViewDAGCombine1 = false,
107 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
108 ViewDAGCombine2 = false,
109 ViewDAGCombineLT = false,
110 ViewISelDAGs = false, ViewSchedDAGs = false,
111 ViewSUnitDAGs = false;
112 #endif
114 //===---------------------------------------------------------------------===//
115 ///
116 /// RegisterScheduler class - Track the registration of instruction schedulers.
117 ///
118 //===---------------------------------------------------------------------===//
119 MachinePassRegistry RegisterScheduler::Registry;
121 //===---------------------------------------------------------------------===//
122 ///
123 /// ISHeuristic command line option for instruction schedulers.
124 ///
125 //===---------------------------------------------------------------------===//
126 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
127 RegisterPassParser<RegisterScheduler> >
128 ISHeuristic("pre-RA-sched",
129 cl::init(&createDefaultScheduler),
130 cl::desc("Instruction schedulers available (before register"
131 " allocation):"));
133 static RegisterScheduler
134 defaultListDAGScheduler("default", "Best scheduler for the target",
135 createDefaultScheduler);
137 namespace llvm {
138 //===--------------------------------------------------------------------===//
139 /// createDefaultScheduler - This creates an instruction scheduler appropriate
140 /// for the target.
141 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
142 CodeGenOpt::Level OptLevel) {
143 const TargetLowering &TLI = IS->getTargetLowering();
145 if (OptLevel == CodeGenOpt::None)
146 return createSourceListDAGScheduler(IS, OptLevel);
147 if (TLI.getSchedulingPreference() == Sched::RegPressure)
148 return createBURRListDAGScheduler(IS, OptLevel);
149 if (TLI.getSchedulingPreference() == Sched::Hybrid)
150 return createHybridListDAGScheduler(IS, OptLevel);
151 assert(TLI.getSchedulingPreference() == Sched::ILP &&
152 "Unknown sched type!");
153 return createILPListDAGScheduler(IS, OptLevel);
154 }
155 }
157 // EmitInstrWithCustomInserter - This method should be implemented by targets
158 // that mark instructions with the 'usesCustomInserter' flag. These
159 // instructions are special in various ways, which require special support to
160 // insert. The specified MachineInstr is created but not inserted into any
161 // basic blocks, and this method is called to expand it into a sequence of
162 // instructions, potentially also creating new basic blocks and control flow.
163 // When new basic blocks are inserted and the edges from MBB to its successors
164 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
165 // DenseMap.
166 MachineBasicBlock *
167 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
168 MachineBasicBlock *MBB) const {
169 #ifndef NDEBUG
170 dbgs() << "If a target marks an instruction with "
171 "'usesCustomInserter', it must implement "
172 "TargetLowering::EmitInstrWithCustomInserter!";
173 #endif
174 llvm_unreachable(0);
175 return 0;
176 }
178 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
179 SDNode *Node) const {
180 assert(!MI->getDesc().hasPostISelHook() &&
181 "If a target marks an instruction with 'hasPostISelHook', "
182 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
183 }
185 //===----------------------------------------------------------------------===//
186 // SelectionDAGISel code
187 //===----------------------------------------------------------------------===//
189 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm,
190 CodeGenOpt::Level OL) :
191 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()),
192 FuncInfo(new FunctionLoweringInfo(TLI)),
193 CurDAG(new SelectionDAG(tm)),
194 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
195 GFI(),
196 OptLevel(OL),
197 DAGSize(0) {
198 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
199 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
200 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
201 }
203 SelectionDAGISel::~SelectionDAGISel() {
204 delete SDB;
205 delete CurDAG;
206 delete FuncInfo;
207 }
209 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
210 AU.addRequired<AliasAnalysis>();
211 AU.addPreserved<AliasAnalysis>();
212 AU.addRequired<GCModuleInfo>();
213 AU.addPreserved<GCModuleInfo>();
214 if (UseMBPI && OptLevel != CodeGenOpt::None)
215 AU.addRequired<BranchProbabilityInfo>();
216 MachineFunctionPass::getAnalysisUsage(AU);
217 }
219 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
220 /// may trap on it. In this case we have to split the edge so that the path
221 /// through the predecessor block that doesn't go to the phi block doesn't
222 /// execute the possibly trapping instruction.
223 ///
224 /// This is required for correctness, so it must be done at -O0.
225 ///
226 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) {
227 // Loop for blocks with phi nodes.
228 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
229 PHINode *PN = dyn_cast<PHINode>(BB->begin());
230 if (PN == 0) continue;
232 ReprocessBlock:
233 // For each block with a PHI node, check to see if any of the input values
234 // are potentially trapping constant expressions. Constant expressions are
235 // the only potentially trapping value that can occur as the argument to a
236 // PHI.
237 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
238 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
239 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
240 if (CE == 0 || !CE->canTrap()) continue;
242 // The only case we have to worry about is when the edge is critical.
243 // Since this block has a PHI Node, we assume it has multiple input
244 // edges: check to see if the pred has multiple successors.
245 BasicBlock *Pred = PN->getIncomingBlock(i);
246 if (Pred->getTerminator()->getNumSuccessors() == 1)
247 continue;
249 // Okay, we have to split this edge.
250 SplitCriticalEdge(Pred->getTerminator(),
251 GetSuccessorNumber(Pred, BB), SDISel, true);
252 goto ReprocessBlock;
253 }
254 }
255 }
257 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
258 // Do some sanity-checking on the command-line options.
259 assert((!EnableFastISelVerbose || EnableFastISel) &&
260 "-fast-isel-verbose requires -fast-isel");
261 assert((!EnableFastISelAbort || EnableFastISel) &&
262 "-fast-isel-abort requires -fast-isel");
264 const Function &Fn = *mf.getFunction();
265 const TargetInstrInfo &TII = *TM.getInstrInfo();
266 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
268 MF = &mf;
269 RegInfo = &MF->getRegInfo();
270 AA = &getAnalysis<AliasAnalysis>();
271 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
273 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
275 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this);
277 CurDAG->init(*MF);
278 FuncInfo->set(Fn, *MF);
280 if (UseMBPI && OptLevel != CodeGenOpt::None)
281 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>();
282 else
283 FuncInfo->BPI = 0;
285 SDB->init(GFI, *AA);
287 SelectAllBasicBlocks(Fn);
289 // If the first basic block in the function has live ins that need to be
290 // copied into vregs, emit the copies into the top of the block before
291 // emitting the code for the block.
292 MachineBasicBlock *EntryMBB = MF->begin();
293 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
295 DenseMap<unsigned, unsigned> LiveInMap;
296 if (!FuncInfo->ArgDbgValues.empty())
297 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
298 E = RegInfo->livein_end(); LI != E; ++LI)
299 if (LI->second)
300 LiveInMap.insert(std::make_pair(LI->first, LI->second));
302 // Insert DBG_VALUE instructions for function arguments to the entry block.
303 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
304 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
305 unsigned Reg = MI->getOperand(0).getReg();
306 if (TargetRegisterInfo::isPhysicalRegister(Reg))
307 EntryMBB->insert(EntryMBB->begin(), MI);
308 else {
309 MachineInstr *Def = RegInfo->getVRegDef(Reg);
310 MachineBasicBlock::iterator InsertPos = Def;
311 // FIXME: VR def may not be in entry block.
312 Def->getParent()->insert(llvm::next(InsertPos), MI);
313 }
315 // If Reg is live-in then update debug info to track its copy in a vreg.
316 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
317 if (LDI != LiveInMap.end()) {
318 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
319 MachineBasicBlock::iterator InsertPos = Def;
320 const MDNode *Variable =
321 MI->getOperand(MI->getNumOperands()-1).getMetadata();
322 unsigned Offset = MI->getOperand(1).getImm();
323 // Def is never a terminator here, so it is ok to increment InsertPos.
324 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
325 TII.get(TargetOpcode::DBG_VALUE))
326 .addReg(LDI->second, RegState::Debug)
327 .addImm(Offset).addMetadata(Variable);
329 // If this vreg is directly copied into an exported register then
330 // that COPY instructions also need DBG_VALUE, if it is the only
331 // user of LDI->second.
332 MachineInstr *CopyUseMI = NULL;
333 for (MachineRegisterInfo::use_iterator
334 UI = RegInfo->use_begin(LDI->second);
335 MachineInstr *UseMI = UI.skipInstruction();) {
336 if (UseMI->isDebugValue()) continue;
337 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
338 CopyUseMI = UseMI; continue;
339 }
340 // Otherwise this is another use or second copy use.
341 CopyUseMI = NULL; break;
342 }
343 if (CopyUseMI) {
344 MachineInstr *NewMI =
345 BuildMI(*MF, CopyUseMI->getDebugLoc(),
346 TII.get(TargetOpcode::DBG_VALUE))
347 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug)
348 .addImm(Offset).addMetadata(Variable);
349 EntryMBB->insertAfter(CopyUseMI, NewMI);
350 }
351 }
352 }
354 // Determine if there are any calls in this machine function.
355 MachineFrameInfo *MFI = MF->getFrameInfo();
356 if (!MFI->hasCalls()) {
357 for (MachineFunction::const_iterator
358 I = MF->begin(), E = MF->end(); I != E; ++I) {
359 const MachineBasicBlock *MBB = I;
360 for (MachineBasicBlock::const_iterator
361 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) {
362 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode());
364 if ((MCID.isCall() && !MCID.isReturn()) ||
365 II->isStackAligningInlineAsm()) {
366 MFI->setHasCalls(true);
367 goto done;
368 }
369 }
370 }
371 done:;
372 }
374 // Determine if there is a call to setjmp in the machine function.
375 MF->setCallsSetJmp(Fn.callsFunctionThatReturnsTwice());
377 // Replace forward-declared registers with the registers containing
378 // the desired value.
379 MachineRegisterInfo &MRI = MF->getRegInfo();
380 for (DenseMap<unsigned, unsigned>::iterator
381 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
382 I != E; ++I) {
383 unsigned From = I->first;
384 unsigned To = I->second;
385 // If To is also scheduled to be replaced, find what its ultimate
386 // replacement is.
387 for (;;) {
388 DenseMap<unsigned, unsigned>::iterator J =
389 FuncInfo->RegFixups.find(To);
390 if (J == E) break;
391 To = J->second;
392 }
393 // Replace it.
394 MRI.replaceRegWith(From, To);
395 }
397 // Release function-specific state. SDB and CurDAG are already cleared
398 // at this point.
399 FuncInfo->clear();
401 return true;
402 }
404 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
405 BasicBlock::const_iterator End,
406 bool &HadTailCall) {
407 // Lower all of the non-terminator instructions. If a call is emitted
408 // as a tail call, cease emitting nodes for this block. Terminators
409 // are handled below.
410 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
411 SDB->visit(*I);
413 // Make sure the root of the DAG is up-to-date.
414 CurDAG->setRoot(SDB->getControlRoot());
415 HadTailCall = SDB->HasTailCall;
416 SDB->clear();
418 // Final step, emit the lowered DAG as machine code.
419 CodeGenAndEmitDAG();
420 }
422 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
423 SmallPtrSet<SDNode*, 128> VisitedNodes;
424 SmallVector<SDNode*, 128> Worklist;
426 Worklist.push_back(CurDAG->getRoot().getNode());
428 APInt Mask;
429 APInt KnownZero;
430 APInt KnownOne;
432 do {
433 SDNode *N = Worklist.pop_back_val();
435 // If we've already seen this node, ignore it.
436 if (!VisitedNodes.insert(N))
437 continue;
439 // Otherwise, add all chain operands to the worklist.
440 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
441 if (N->getOperand(i).getValueType() == MVT::Other)
442 Worklist.push_back(N->getOperand(i).getNode());
444 // If this is a CopyToReg with a vreg dest, process it.
445 if (N->getOpcode() != ISD::CopyToReg)
446 continue;
448 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
449 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
450 continue;
452 // Ignore non-scalar or non-integer values.
453 SDValue Src = N->getOperand(2);
454 EVT SrcVT = Src.getValueType();
455 if (!SrcVT.isInteger() || SrcVT.isVector())
456 continue;
458 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
459 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
460 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
461 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
462 } while (!Worklist.empty());
463 }
465 void SelectionDAGISel::CodeGenAndEmitDAG() {
466 std::string GroupName;
467 if (TimePassesIsEnabled)
468 GroupName = "Instruction Selection and Scheduling";
469 std::string BlockName;
470 int BlockNumber = -1;
471 (void)BlockNumber;
472 #ifdef NDEBUG
473 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
474 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
475 ViewSUnitDAGs)
476 #endif
477 {
478 BlockNumber = FuncInfo->MBB->getNumber();
479 BlockName = MF->getFunction()->getNameStr() + ":" +
480 FuncInfo->MBB->getBasicBlock()->getNameStr();
481 }
482 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
483 << " '" << BlockName << "'\n"; CurDAG->dump());
485 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
487 // Run the DAG combiner in pre-legalize mode.
488 {
489 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
490 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
491 }
493 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
494 << " '" << BlockName << "'\n"; CurDAG->dump());
496 // Second step, hack on the DAG until it only uses operations and types that
497 // the target supports.
498 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
499 BlockName);
501 bool Changed;
502 {
503 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
504 Changed = CurDAG->LegalizeTypes();
505 }
507 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
508 << " '" << BlockName << "'\n"; CurDAG->dump());
510 if (Changed) {
511 if (ViewDAGCombineLT)
512 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
514 // Run the DAG combiner in post-type-legalize mode.
515 {
516 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
517 TimePassesIsEnabled);
518 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
519 }
521 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
522 << " '" << BlockName << "'\n"; CurDAG->dump());
523 }
525 {
526 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
527 Changed = CurDAG->LegalizeVectors();
528 }
530 if (Changed) {
531 {
532 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
533 CurDAG->LegalizeTypes();
534 }
536 if (ViewDAGCombineLT)
537 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
539 // Run the DAG combiner in post-type-legalize mode.
540 {
541 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
542 TimePassesIsEnabled);
543 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
544 }
546 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
547 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
548 }
550 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
552 {
553 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
554 CurDAG->Legalize();
555 }
557 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
558 << " '" << BlockName << "'\n"; CurDAG->dump());
560 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
562 // Run the DAG combiner in post-legalize mode.
563 {
564 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
565 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
566 }
568 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
569 << " '" << BlockName << "'\n"; CurDAG->dump());
571 if (OptLevel != CodeGenOpt::None)
572 ComputeLiveOutVRegInfo();
574 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
576 // Third, instruction select all of the operations to machine code, adding the
577 // code to the MachineBasicBlock.
578 {
579 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
580 DoInstructionSelection();
581 }
583 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
584 << " '" << BlockName << "'\n"; CurDAG->dump());
586 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
588 // Schedule machine code.
589 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
590 {
591 NamedRegionTimer T("Instruction Scheduling", GroupName,
592 TimePassesIsEnabled);
593 Scheduler->Run(CurDAG, FuncInfo->MBB, FuncInfo->InsertPt);
594 }
596 if (ViewSUnitDAGs) Scheduler->viewGraph();
598 // Emit machine code to BB. This can change 'BB' to the last block being
599 // inserted into.
600 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
601 {
602 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
604 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule();
605 FuncInfo->InsertPt = Scheduler->InsertPos;
606 }
608 // If the block was split, make sure we update any references that are used to
609 // update PHI nodes later on.
610 if (FirstMBB != LastMBB)
611 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
613 // Free the scheduler state.
614 {
615 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
616 TimePassesIsEnabled);
617 delete Scheduler;
618 }
620 // Free the SelectionDAG state, now that we're finished with it.
621 CurDAG->clear();
622 }
624 void SelectionDAGISel::DoInstructionSelection() {
625 DEBUG(errs() << "===== Instruction selection begins: BB#"
626 << FuncInfo->MBB->getNumber()
627 << " '" << FuncInfo->MBB->getName() << "'\n");
629 PreprocessISelDAG();
631 // Select target instructions for the DAG.
632 {
633 // Number all nodes with a topological order and set DAGSize.
634 DAGSize = CurDAG->AssignTopologicalOrder();
636 // Create a dummy node (which is not added to allnodes), that adds
637 // a reference to the root node, preventing it from being deleted,
638 // and tracking any changes of the root.
639 HandleSDNode Dummy(CurDAG->getRoot());
640 ISelPosition = SelectionDAG::allnodes_iterator(CurDAG->getRoot().getNode());
641 ++ISelPosition;
643 // The AllNodes list is now topological-sorted. Visit the
644 // nodes by starting at the end of the list (the root of the
645 // graph) and preceding back toward the beginning (the entry
646 // node).
647 while (ISelPosition != CurDAG->allnodes_begin()) {
648 SDNode *Node = --ISelPosition;
649 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
650 // but there are currently some corner cases that it misses. Also, this
651 // makes it theoretically possible to disable the DAGCombiner.
652 if (Node->use_empty())
653 continue;
655 SDNode *ResNode = Select(Node);
657 // FIXME: This is pretty gross. 'Select' should be changed to not return
658 // anything at all and this code should be nuked with a tactical strike.
660 // If node should not be replaced, continue with the next one.
661 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
662 continue;
663 // Replace node.
664 if (ResNode)
665 ReplaceUses(Node, ResNode);
667 // If after the replacement this node is not used any more,
668 // remove this dead node.
669 if (Node->use_empty()) { // Don't delete EntryToken, etc.
670 ISelUpdater ISU(ISelPosition);
671 CurDAG->RemoveDeadNode(Node, &ISU);
672 }
673 }
675 CurDAG->setRoot(Dummy.getValue());
676 }
678 DEBUG(errs() << "===== Instruction selection ends:\n");
680 PostprocessISelDAG();
681 }
683 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
684 /// do other setup for EH landing-pad blocks.
685 void SelectionDAGISel::PrepareEHLandingPad() {
686 MachineBasicBlock *MBB = FuncInfo->MBB;
688 // Add a label to mark the beginning of the landing pad. Deletion of the
689 // landing pad can thus be detected via the MachineModuleInfo.
690 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
692 // Assign the call site to the landing pad's begin label.
693 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
695 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
696 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
697 .addSym(Label);
699 // Mark exception register as live in.
700 unsigned Reg = TLI.getExceptionAddressRegister();
701 if (Reg) MBB->addLiveIn(Reg);
703 // Mark exception selector register as live in.
704 Reg = TLI.getExceptionSelectorRegister();
705 if (Reg) MBB->addLiveIn(Reg);
707 // FIXME: Hack around an exception handling flaw (PR1508): the personality
708 // function and list of typeids logically belong to the invoke (or, if you
709 // like, the basic block containing the invoke), and need to be associated
710 // with it in the dwarf exception handling tables. Currently however the
711 // information is provided by an intrinsic (eh.selector) that can be moved
712 // to unexpected places by the optimizers: if the unwind edge is critical,
713 // then breaking it can result in the intrinsics being in the successor of
714 // the landing pad, not the landing pad itself. This results
715 // in exceptions not being caught because no typeids are associated with
716 // the invoke. This may not be the only way things can go wrong, but it
717 // is the only way we try to work around for the moment.
718 const BasicBlock *LLVMBB = MBB->getBasicBlock();
719 const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
721 if (Br && Br->isUnconditional()) { // Critical edge?
722 BasicBlock::const_iterator I, E;
723 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
724 if (isa<EHSelectorInst>(I))
725 break;
727 if (I == E)
728 // No catch info found - try to extract some from the successor.
729 CopyCatchInfo(Br->getSuccessor(0), LLVMBB, &MF->getMMI(), *FuncInfo);
730 }
731 }
733 /// TryToFoldFastISelLoad - We're checking to see if we can fold the specified
734 /// load into the specified FoldInst. Note that we could have a sequence where
735 /// multiple LLVM IR instructions are folded into the same machineinstr. For
736 /// example we could have:
737 /// A: x = load i32 *P
738 /// B: y = icmp A, 42
739 /// C: br y, ...
740 ///
741 /// In this scenario, LI is "A", and FoldInst is "C". We know about "B" (and
742 /// any other folded instructions) because it is between A and C.
743 ///
744 /// If we succeed in folding the load into the operation, return true.
745 ///
746 bool SelectionDAGISel::TryToFoldFastISelLoad(const LoadInst *LI,
747 const Instruction *FoldInst,
748 FastISel *FastIS) {
749 // We know that the load has a single use, but don't know what it is. If it
750 // isn't one of the folded instructions, then we can't succeed here. Handle
751 // this by scanning the single-use users of the load until we get to FoldInst.
752 unsigned MaxUsers = 6; // Don't scan down huge single-use chains of instrs.
754 const Instruction *TheUser = LI->use_back();
755 while (TheUser != FoldInst && // Scan up until we find FoldInst.
756 // Stay in the right block.
757 TheUser->getParent() == FoldInst->getParent() &&
758 --MaxUsers) { // Don't scan too far.
759 // If there are multiple or no uses of this instruction, then bail out.
760 if (!TheUser->hasOneUse())
761 return false;
763 TheUser = TheUser->use_back();
764 }
766 // If we didn't find the fold instruction, then we failed to collapse the
767 // sequence.
768 if (TheUser != FoldInst)
769 return false;
771 // Don't try to fold volatile loads. Target has to deal with alignment
772 // constraints.
773 if (LI->isVolatile()) return false;
775 // Figure out which vreg this is going into. If there is no assigned vreg yet
776 // then there actually was no reference to it. Perhaps the load is referenced
777 // by a dead instruction.
778 unsigned LoadReg = FastIS->getRegForValue(LI);
779 if (LoadReg == 0)
780 return false;
782 // Check to see what the uses of this vreg are. If it has no uses, or more
783 // than one use (at the machine instr level) then we can't fold it.
784 MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(LoadReg);
785 if (RI == RegInfo->reg_end())
786 return false;
788 // See if there is exactly one use of the vreg. If there are multiple uses,
789 // then the instruction got lowered to multiple machine instructions or the
790 // use of the loaded value ended up being multiple operands of the result, in
791 // either case, we can't fold this.
792 MachineRegisterInfo::reg_iterator PostRI = RI; ++PostRI;
793 if (PostRI != RegInfo->reg_end())
794 return false;
796 assert(RI.getOperand().isUse() &&
797 "The only use of the vreg must be a use, we haven't emitted the def!");
799 MachineInstr *User = &*RI;
801 // Set the insertion point properly. Folding the load can cause generation of
802 // other random instructions (like sign extends) for addressing modes, make
803 // sure they get inserted in a logical place before the new instruction.
804 FuncInfo->InsertPt = User;
805 FuncInfo->MBB = User->getParent();
807 // Ask the target to try folding the load.
808 return FastIS->TryToFoldLoad(User, RI.getOperandNo(), LI);
809 }
811 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
812 /// side-effect free and is either dead or folded into a generated instruction.
813 /// Return false if it needs to be emitted.
814 static bool isFoldedOrDeadInstruction(const Instruction *I,
815 FunctionLoweringInfo *FuncInfo) {
816 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
817 !isa<TerminatorInst>(I) && // Terminators aren't folded.
818 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
819 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded.
820 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
821 }
823 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
824 // Initialize the Fast-ISel state, if needed.
825 FastISel *FastIS = 0;
826 if (EnableFastISel)
827 FastIS = TLI.createFastISel(*FuncInfo);
829 // Iterate over all basic blocks in the function.
830 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
831 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
832 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
833 const BasicBlock *LLVMBB = *I;
835 if (OptLevel != CodeGenOpt::None) {
836 bool AllPredsVisited = true;
837 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
838 PI != PE; ++PI) {
839 if (!FuncInfo->VisitedBBs.count(*PI)) {
840 AllPredsVisited = false;
841 break;
842 }
843 }
845 if (AllPredsVisited) {
846 for (BasicBlock::const_iterator I = LLVMBB->begin();
847 isa<PHINode>(I); ++I)
848 FuncInfo->ComputePHILiveOutRegInfo(cast<PHINode>(I));
849 } else {
850 for (BasicBlock::const_iterator I = LLVMBB->begin();
851 isa<PHINode>(I); ++I)
852 FuncInfo->InvalidatePHILiveOutRegInfo(cast<PHINode>(I));
853 }
855 FuncInfo->VisitedBBs.insert(LLVMBB);
856 }
858 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
859 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
861 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
862 BasicBlock::const_iterator const End = LLVMBB->end();
863 BasicBlock::const_iterator BI = End;
865 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
867 // Setup an EH landing-pad block.
868 if (FuncInfo->MBB->isLandingPad())
869 PrepareEHLandingPad();
871 // Lower any arguments needed in this block if this is the entry block.
872 if (LLVMBB == &Fn.getEntryBlock())
873 LowerArguments(LLVMBB);
875 // Before doing SelectionDAG ISel, see if FastISel has been requested.
876 if (FastIS) {
877 FastIS->startNewBlock();
879 // Emit code for any incoming arguments. This must happen before
880 // beginning FastISel on the entry block.
881 if (LLVMBB == &Fn.getEntryBlock()) {
882 CurDAG->setRoot(SDB->getControlRoot());
883 SDB->clear();
884 CodeGenAndEmitDAG();
886 // If we inserted any instructions at the beginning, make a note of
887 // where they are, so we can be sure to emit subsequent instructions
888 // after them.
889 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
890 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
891 else
892 FastIS->setLastLocalValue(0);
893 }
895 // Do FastISel on as many instructions as possible.
896 for (; BI != Begin; --BI) {
897 const Instruction *Inst = llvm::prior(BI);
899 // If we no longer require this instruction, skip it.
900 if (isFoldedOrDeadInstruction(Inst, FuncInfo))
901 continue;
903 // Bottom-up: reset the insert pos at the top, after any local-value
904 // instructions.
905 FastIS->recomputeInsertPt();
907 // Try to select the instruction with FastISel.
908 if (FastIS->SelectInstruction(Inst)) {
909 ++NumFastIselSuccess;
910 // If fast isel succeeded, skip over all the folded instructions, and
911 // then see if there is a load right before the selected instructions.
912 // Try to fold the load if so.
913 const Instruction *BeforeInst = Inst;
914 while (BeforeInst != Begin) {
915 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst));
916 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
917 break;
918 }
919 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
920 BeforeInst->hasOneUse() &&
921 TryToFoldFastISelLoad(cast<LoadInst>(BeforeInst), Inst, FastIS))
922 // If we succeeded, don't re-select the load.
923 BI = llvm::next(BasicBlock::const_iterator(BeforeInst));
924 continue;
925 }
927 // Then handle certain instructions as single-LLVM-Instruction blocks.
928 if (isa<CallInst>(Inst)) {
929 ++NumFastIselFailures;
930 if (EnableFastISelVerbose || EnableFastISelAbort) {
931 dbgs() << "FastISel missed call: ";
932 Inst->dump();
933 }
935 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
936 unsigned &R = FuncInfo->ValueMap[Inst];
937 if (!R)
938 R = FuncInfo->CreateRegs(Inst->getType());
939 }
941 bool HadTailCall = false;
942 SelectBasicBlock(Inst, BI, HadTailCall);
944 // If the call was emitted as a tail call, we're done with the block.
945 if (HadTailCall) {
946 --BI;
947 break;
948 }
950 continue;
951 }
953 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) {
954 // Don't abort, and use a different message for terminator misses.
955 ++NumFastIselFailures;
956 if (EnableFastISelVerbose || EnableFastISelAbort) {
957 dbgs() << "FastISel missed terminator: ";
958 Inst->dump();
959 }
960 } else {
961 ++NumFastIselFailures;
962 if (EnableFastISelVerbose || EnableFastISelAbort) {
963 dbgs() << "FastISel miss: ";
964 Inst->dump();
965 }
966 if (EnableFastISelAbort)
967 // The "fast" selector couldn't handle something and bailed.
968 // For the purpose of debugging, just abort.
969 llvm_unreachable("FastISel didn't select the entire block");
970 }
971 break;
972 }
974 FastIS->recomputeInsertPt();
975 }
977 if (Begin != BI)
978 ++NumDAGBlocks;
979 else
980 ++NumFastIselBlocks;
982 if (Begin != BI) {
983 // Run SelectionDAG instruction selection on the remainder of the block
984 // not handled by FastISel. If FastISel is not run, this is the entire
985 // block.
986 bool HadTailCall;
987 SelectBasicBlock(Begin, BI, HadTailCall);
988 }
990 FinishBasicBlock();
991 FuncInfo->PHINodesToUpdate.clear();
992 }
994 delete FastIS;
995 SDB->clearDanglingDebugInfo();
996 }
998 void
999 SelectionDAGISel::FinishBasicBlock() {
1001 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1002 << FuncInfo->PHINodesToUpdate.size() << "\n";
1003 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1004 dbgs() << "Node " << i << " : ("
1005 << FuncInfo->PHINodesToUpdate[i].first
1006 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1008 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1009 // PHI nodes in successors.
1010 if (SDB->SwitchCases.empty() &&
1011 SDB->JTCases.empty() &&
1012 SDB->BitTestCases.empty()) {
1013 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1014 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
1015 assert(PHI->isPHI() &&
1016 "This is not a machine PHI node that we are updating!");
1017 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1018 continue;
1019 PHI->addOperand(
1020 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
1021 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1022 }
1023 return;
1024 }
1026 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1027 // Lower header first, if it wasn't already lowered
1028 if (!SDB->BitTestCases[i].Emitted) {
1029 // Set the current basic block to the mbb we wish to insert the code into
1030 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1031 FuncInfo->InsertPt = FuncInfo->MBB->end();
1032 // Emit the code
1033 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1034 CurDAG->setRoot(SDB->getRoot());
1035 SDB->clear();
1036 CodeGenAndEmitDAG();
1037 }
1039 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1040 // Set the current basic block to the mbb we wish to insert the code into
1041 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1042 FuncInfo->InsertPt = FuncInfo->MBB->end();
1043 // Emit the code
1044 if (j+1 != ej)
1045 SDB->visitBitTestCase(SDB->BitTestCases[i],
1046 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1047 SDB->BitTestCases[i].Reg,
1048 SDB->BitTestCases[i].Cases[j],
1049 FuncInfo->MBB);
1050 else
1051 SDB->visitBitTestCase(SDB->BitTestCases[i],
1052 SDB->BitTestCases[i].Default,
1053 SDB->BitTestCases[i].Reg,
1054 SDB->BitTestCases[i].Cases[j],
1055 FuncInfo->MBB);
1058 CurDAG->setRoot(SDB->getRoot());
1059 SDB->clear();
1060 CodeGenAndEmitDAG();
1061 }
1063 // Update PHI Nodes
1064 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1065 pi != pe; ++pi) {
1066 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
1067 MachineBasicBlock *PHIBB = PHI->getParent();
1068 assert(PHI->isPHI() &&
1069 "This is not a machine PHI node that we are updating!");
1070 // This is "default" BB. We have two jumps to it. From "header" BB and
1071 // from last "case" BB.
1072 if (PHIBB == SDB->BitTestCases[i].Default) {
1073 PHI->addOperand(MachineOperand::
1074 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1075 false));
1076 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent));
1077 PHI->addOperand(MachineOperand::
1078 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1079 false));
1080 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases.
1081 back().ThisBB));
1082 }
1083 // One of "cases" BB.
1084 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1085 j != ej; ++j) {
1086 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1087 if (cBB->isSuccessor(PHIBB)) {
1088 PHI->addOperand(MachineOperand::
1089 CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1090 false));
1091 PHI->addOperand(MachineOperand::CreateMBB(cBB));
1092 }
1093 }
1094 }
1095 }
1096 SDB->BitTestCases.clear();
1098 // If the JumpTable record is filled in, then we need to emit a jump table.
1099 // Updating the PHI nodes is tricky in this case, since we need to determine
1100 // whether the PHI is a successor of the range check MBB or the jump table MBB
1101 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1102 // Lower header first, if it wasn't already lowered
1103 if (!SDB->JTCases[i].first.Emitted) {
1104 // Set the current basic block to the mbb we wish to insert the code into
1105 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1106 FuncInfo->InsertPt = FuncInfo->MBB->end();
1107 // Emit the code
1108 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1109 FuncInfo->MBB);
1110 CurDAG->setRoot(SDB->getRoot());
1111 SDB->clear();
1112 CodeGenAndEmitDAG();
1113 }
1115 // Set the current basic block to the mbb we wish to insert the code into
1116 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1117 FuncInfo->InsertPt = FuncInfo->MBB->end();
1118 // Emit the code
1119 SDB->visitJumpTable(SDB->JTCases[i].second);
1120 CurDAG->setRoot(SDB->getRoot());
1121 SDB->clear();
1122 CodeGenAndEmitDAG();
1124 // Update PHI Nodes
1125 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1126 pi != pe; ++pi) {
1127 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first;
1128 MachineBasicBlock *PHIBB = PHI->getParent();
1129 assert(PHI->isPHI() &&
1130 "This is not a machine PHI node that we are updating!");
1131 // "default" BB. We can go there only from header BB.
1132 if (PHIBB == SDB->JTCases[i].second.Default) {
1133 PHI->addOperand
1134 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1135 false));
1136 PHI->addOperand
1137 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
1138 }
1139 // JT BB. Just iterate over successors here
1140 if (FuncInfo->MBB->isSuccessor(PHIBB)) {
1141 PHI->addOperand
1142 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
1143 false));
1144 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1145 }
1146 }
1147 }
1148 SDB->JTCases.clear();
1150 // If the switch block involved a branch to one of the actual successors, we
1151 // need to update PHI nodes in that block.
1152 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1153 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
1154 assert(PHI->isPHI() &&
1155 "This is not a machine PHI node that we are updating!");
1156 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) {
1157 PHI->addOperand(
1158 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
1159 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
1160 }
1161 }
1163 // If we generated any switch lowering information, build and codegen any
1164 // additional DAGs necessary.
1165 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1166 // Set the current basic block to the mbb we wish to insert the code into
1167 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1168 FuncInfo->InsertPt = FuncInfo->MBB->end();
1170 // Determine the unique successors.
1171 SmallVector<MachineBasicBlock *, 2> Succs;
1172 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1173 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1174 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1176 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1177 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1178 CurDAG->setRoot(SDB->getRoot());
1179 SDB->clear();
1180 CodeGenAndEmitDAG();
1182 // Remember the last block, now that any splitting is done, for use in
1183 // populating PHI nodes in successors.
1184 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1186 // Handle any PHI nodes in successors of this chunk, as if we were coming
1187 // from the original BB before switch expansion. Note that PHI nodes can
1188 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1189 // handle them the right number of times.
1190 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1191 FuncInfo->MBB = Succs[i];
1192 FuncInfo->InsertPt = FuncInfo->MBB->end();
1193 // FuncInfo->MBB may have been removed from the CFG if a branch was
1194 // constant folded.
1195 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1196 for (MachineBasicBlock::iterator Phi = FuncInfo->MBB->begin();
1197 Phi != FuncInfo->MBB->end() && Phi->isPHI();
1198 ++Phi) {
1199 // This value for this PHI node is recorded in PHINodesToUpdate.
1200 for (unsigned pn = 0; ; ++pn) {
1201 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1202 "Didn't find PHI entry!");
1203 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) {
1204 Phi->addOperand(MachineOperand::
1205 CreateReg(FuncInfo->PHINodesToUpdate[pn].second,
1206 false));
1207 Phi->addOperand(MachineOperand::CreateMBB(ThisBB));
1208 break;
1209 }
1210 }
1211 }
1212 }
1213 }
1214 }
1215 SDB->SwitchCases.clear();
1216 }
1219 /// Create the scheduler. If a specific scheduler was specified
1220 /// via the SchedulerRegistry, use it, otherwise select the
1221 /// one preferred by the target.
1222 ///
1223 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1224 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1226 if (!Ctor) {
1227 Ctor = ISHeuristic;
1228 RegisterScheduler::setDefault(Ctor);
1229 }
1231 return Ctor(this, OptLevel);
1232 }
1234 //===----------------------------------------------------------------------===//
1235 // Helper functions used by the generated instruction selector.
1236 //===----------------------------------------------------------------------===//
1237 // Calls to these methods are generated by tblgen.
1239 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1240 /// the dag combiner simplified the 255, we still want to match. RHS is the
1241 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1242 /// specified in the .td file (e.g. 255).
1243 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1244 int64_t DesiredMaskS) const {
1245 const APInt &ActualMask = RHS->getAPIntValue();
1246 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1248 // If the actual mask exactly matches, success!
1249 if (ActualMask == DesiredMask)
1250 return true;
1252 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1253 if (ActualMask.intersects(~DesiredMask))
1254 return false;
1256 // Otherwise, the DAG Combiner may have proven that the value coming in is
1257 // either already zero or is not demanded. Check for known zero input bits.
1258 APInt NeededMask = DesiredMask & ~ActualMask;
1259 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1260 return true;
1262 // TODO: check to see if missing bits are just not demanded.
1264 // Otherwise, this pattern doesn't match.
1265 return false;
1266 }
1268 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1269 /// the dag combiner simplified the 255, we still want to match. RHS is the
1270 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1271 /// specified in the .td file (e.g. 255).
1272 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1273 int64_t DesiredMaskS) const {
1274 const APInt &ActualMask = RHS->getAPIntValue();
1275 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1277 // If the actual mask exactly matches, success!
1278 if (ActualMask == DesiredMask)
1279 return true;
1281 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1282 if (ActualMask.intersects(~DesiredMask))
1283 return false;
1285 // Otherwise, the DAG Combiner may have proven that the value coming in is
1286 // either already zero or is not demanded. Check for known zero input bits.
1287 APInt NeededMask = DesiredMask & ~ActualMask;
1289 APInt KnownZero, KnownOne;
1290 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
1292 // If all the missing bits in the or are already known to be set, match!
1293 if ((NeededMask & KnownOne) == NeededMask)
1294 return true;
1296 // TODO: check to see if missing bits are just not demanded.
1298 // Otherwise, this pattern doesn't match.
1299 return false;
1300 }
1303 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1304 /// by tblgen. Others should not call it.
1305 void SelectionDAGISel::
1306 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1307 std::vector<SDValue> InOps;
1308 std::swap(InOps, Ops);
1310 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1311 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1312 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1313 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1315 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1316 if (InOps[e-1].getValueType() == MVT::Glue)
1317 --e; // Don't process a glue operand if it is here.
1319 while (i != e) {
1320 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1321 if (!InlineAsm::isMemKind(Flags)) {
1322 // Just skip over this operand, copying the operands verbatim.
1323 Ops.insert(Ops.end(), InOps.begin()+i,
1324 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1325 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1326 } else {
1327 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1328 "Memory operand with multiple values?");
1329 // Otherwise, this is a memory operand. Ask the target to select it.
1330 std::vector<SDValue> SelOps;
1331 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1332 report_fatal_error("Could not match memory address. Inline asm"
1333 " failure!");
1335 // Add this to the output node.
1336 unsigned NewFlags =
1337 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1338 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1339 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1340 i += 2;
1341 }
1342 }
1344 // Add the glue input back if present.
1345 if (e != InOps.size())
1346 Ops.push_back(InOps.back());
1347 }
1349 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1350 /// SDNode.
1351 ///
1352 static SDNode *findGlueUse(SDNode *N) {
1353 unsigned FlagResNo = N->getNumValues()-1;
1354 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1355 SDUse &Use = I.getUse();
1356 if (Use.getResNo() == FlagResNo)
1357 return Use.getUser();
1358 }
1359 return NULL;
1360 }
1362 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1363 /// This function recursively traverses up the operand chain, ignoring
1364 /// certain nodes.
1365 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1366 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1367 bool IgnoreChains) {
1368 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1369 // greater than all of its (recursive) operands. If we scan to a point where
1370 // 'use' is smaller than the node we're scanning for, then we know we will
1371 // never find it.
1372 //
1373 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1374 // happen because we scan down to newly selected nodes in the case of glue
1375 // uses.
1376 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1377 return false;
1379 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1380 // won't fail if we scan it again.
1381 if (!Visited.insert(Use))
1382 return false;
1384 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1385 // Ignore chain uses, they are validated by HandleMergeInputChains.
1386 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1387 continue;
1389 SDNode *N = Use->getOperand(i).getNode();
1390 if (N == Def) {
1391 if (Use == ImmedUse || Use == Root)
1392 continue; // We are not looking for immediate use.
1393 assert(N != Root);
1394 return true;
1395 }
1397 // Traverse up the operand chain.
1398 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1399 return true;
1400 }
1401 return false;
1402 }
1404 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1405 /// operand node N of U during instruction selection that starts at Root.
1406 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1407 SDNode *Root) const {
1408 if (OptLevel == CodeGenOpt::None) return false;
1409 return N.hasOneUse();
1410 }
1412 /// IsLegalToFold - Returns true if the specific operand node N of
1413 /// U can be folded during instruction selection that starts at Root.
1414 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1415 CodeGenOpt::Level OptLevel,
1416 bool IgnoreChains) {
1417 if (OptLevel == CodeGenOpt::None) return false;
1419 // If Root use can somehow reach N through a path that that doesn't contain
1420 // U then folding N would create a cycle. e.g. In the following
1421 // diagram, Root can reach N through X. If N is folded into into Root, then
1422 // X is both a predecessor and a successor of U.
1423 //
1424 // [N*] //
1425 // ^ ^ //
1426 // / \ //
1427 // [U*] [X]? //
1428 // ^ ^ //
1429 // \ / //
1430 // \ / //
1431 // [Root*] //
1432 //
1433 // * indicates nodes to be folded together.
1434 //
1435 // If Root produces glue, then it gets (even more) interesting. Since it
1436 // will be "glued" together with its glue use in the scheduler, we need to
1437 // check if it might reach N.
1438 //
1439 // [N*] //
1440 // ^ ^ //
1441 // / \ //
1442 // [U*] [X]? //
1443 // ^ ^ //
1444 // \ \ //
1445 // \ | //
1446 // [Root*] | //
1447 // ^ | //
1448 // f | //
1449 // | / //
1450 // [Y] / //
1451 // ^ / //
1452 // f / //
1453 // | / //
1454 // [GU] //
1455 //
1456 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1457 // (call it Fold), then X is a predecessor of GU and a successor of
1458 // Fold. But since Fold and GU are glued together, this will create
1459 // a cycle in the scheduling graph.
1461 // If the node has glue, walk down the graph to the "lowest" node in the
1462 // glueged set.
1463 EVT VT = Root->getValueType(Root->getNumValues()-1);
1464 while (VT == MVT::Glue) {
1465 SDNode *GU = findGlueUse(Root);
1466 if (GU == NULL)
1467 break;
1468 Root = GU;
1469 VT = Root->getValueType(Root->getNumValues()-1);
1471 // If our query node has a glue result with a use, we've walked up it. If
1472 // the user (which has already been selected) has a chain or indirectly uses
1473 // the chain, our WalkChainUsers predicate will not consider it. Because of
1474 // this, we cannot ignore chains in this predicate.
1475 IgnoreChains = false;
1476 }
1479 SmallPtrSet<SDNode*, 16> Visited;
1480 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1481 }
1483 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1484 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1485 SelectInlineAsmMemoryOperands(Ops);
1487 std::vector<EVT> VTs;
1488 VTs.push_back(MVT::Other);
1489 VTs.push_back(MVT::Glue);
1490 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1491 VTs, &Ops[0], Ops.size());
1492 New->setNodeId(-1);
1493 return New.getNode();
1494 }
1496 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1497 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1498 }
1500 /// GetVBR - decode a vbr encoding whose top bit is set.
1501 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1502 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1503 assert(Val >= 128 && "Not a VBR");
1504 Val &= 127; // Remove first vbr bit.
1506 unsigned Shift = 7;
1507 uint64_t NextBits;
1508 do {
1509 NextBits = MatcherTable[Idx++];
1510 Val |= (NextBits&127) << Shift;
1511 Shift += 7;
1512 } while (NextBits & 128);
1514 return Val;
1515 }
1518 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1519 /// interior glue and chain results to use the new glue and chain results.
1520 void SelectionDAGISel::
1521 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1522 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1523 SDValue InputGlue,
1524 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1525 bool isMorphNodeTo) {
1526 SmallVector<SDNode*, 4> NowDeadNodes;
1528 ISelUpdater ISU(ISelPosition);
1530 // Now that all the normal results are replaced, we replace the chain and
1531 // glue results if present.
1532 if (!ChainNodesMatched.empty()) {
1533 assert(InputChain.getNode() != 0 &&
1534 "Matched input chains but didn't produce a chain");
1535 // Loop over all of the nodes we matched that produced a chain result.
1536 // Replace all the chain results with the final chain we ended up with.
1537 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1538 SDNode *ChainNode = ChainNodesMatched[i];
1540 // If this node was already deleted, don't look at it.
1541 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1542 continue;
1544 // Don't replace the results of the root node if we're doing a
1545 // MorphNodeTo.
1546 if (ChainNode == NodeToMatch && isMorphNodeTo)
1547 continue;
1549 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1550 if (ChainVal.getValueType() == MVT::Glue)
1551 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1552 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1553 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain, &ISU);
1555 // If the node became dead and we haven't already seen it, delete it.
1556 if (ChainNode->use_empty() &&
1557 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1558 NowDeadNodes.push_back(ChainNode);
1559 }
1560 }
1562 // If the result produces glue, update any glue results in the matched
1563 // pattern with the glue result.
1564 if (InputGlue.getNode() != 0) {
1565 // Handle any interior nodes explicitly marked.
1566 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
1567 SDNode *FRN = GlueResultNodesMatched[i];
1569 // If this node was already deleted, don't look at it.
1570 if (FRN->getOpcode() == ISD::DELETED_NODE)
1571 continue;
1573 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
1574 "Doesn't have a glue result");
1575 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1576 InputGlue, &ISU);
1578 // If the node became dead and we haven't already seen it, delete it.
1579 if (FRN->use_empty() &&
1580 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1581 NowDeadNodes.push_back(FRN);
1582 }
1583 }
1585 if (!NowDeadNodes.empty())
1586 CurDAG->RemoveDeadNodes(NowDeadNodes, &ISU);
1588 DEBUG(errs() << "ISEL: Match complete!\n");
1589 }
1591 enum ChainResult {
1592 CR_Simple,
1593 CR_InducesCycle,
1594 CR_LeadsToInteriorNode
1595 };
1597 /// WalkChainUsers - Walk down the users of the specified chained node that is
1598 /// part of the pattern we're matching, looking at all of the users we find.
1599 /// This determines whether something is an interior node, whether we have a
1600 /// non-pattern node in between two pattern nodes (which prevent folding because
1601 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1602 /// between pattern nodes (in which case the TF becomes part of the pattern).
1603 ///
1604 /// The walk we do here is guaranteed to be small because we quickly get down to
1605 /// already selected nodes "below" us.
1606 static ChainResult
1607 WalkChainUsers(SDNode *ChainedNode,
1608 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1609 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1610 ChainResult Result = CR_Simple;
1612 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1613 E = ChainedNode->use_end(); UI != E; ++UI) {
1614 // Make sure the use is of the chain, not some other value we produce.
1615 if (UI.getUse().getValueType() != MVT::Other) continue;
1617 SDNode *User = *UI;
1619 // If we see an already-selected machine node, then we've gone beyond the
1620 // pattern that we're selecting down into the already selected chunk of the
1621 // DAG.
1622 if (User->isMachineOpcode() ||
1623 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1624 continue;
1626 if (User->getOpcode() == ISD::CopyToReg ||
1627 User->getOpcode() == ISD::CopyFromReg ||
1628 User->getOpcode() == ISD::INLINEASM ||
1629 User->getOpcode() == ISD::EH_LABEL) {
1630 // If their node ID got reset to -1 then they've already been selected.
1631 // Treat them like a MachineOpcode.
1632 if (User->getNodeId() == -1)
1633 continue;
1634 }
1636 // If we have a TokenFactor, we handle it specially.
1637 if (User->getOpcode() != ISD::TokenFactor) {
1638 // If the node isn't a token factor and isn't part of our pattern, then it
1639 // must be a random chained node in between two nodes we're selecting.
1640 // This happens when we have something like:
1641 // x = load ptr
1642 // call
1643 // y = x+4
1644 // store y -> ptr
1645 // Because we structurally match the load/store as a read/modify/write,
1646 // but the call is chained between them. We cannot fold in this case
1647 // because it would induce a cycle in the graph.
1648 if (!std::count(ChainedNodesInPattern.begin(),
1649 ChainedNodesInPattern.end(), User))
1650 return CR_InducesCycle;
1652 // Otherwise we found a node that is part of our pattern. For example in:
1653 // x = load ptr
1654 // y = x+4
1655 // store y -> ptr
1656 // This would happen when we're scanning down from the load and see the
1657 // store as a user. Record that there is a use of ChainedNode that is
1658 // part of the pattern and keep scanning uses.
1659 Result = CR_LeadsToInteriorNode;
1660 InteriorChainedNodes.push_back(User);
1661 continue;
1662 }
1664 // If we found a TokenFactor, there are two cases to consider: first if the
1665 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1666 // uses of the TF are in our pattern) we just want to ignore it. Second,
1667 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1668 // [Load chain]
1669 // ^
1670 // |
1671 // [Load]
1672 // ^ ^
1673 // | \ DAG's like cheese
1674 // / \ do you?
1675 // / |
1676 // [TokenFactor] [Op]
1677 // ^ ^
1678 // | |
1679 // \ /
1680 // \ /
1681 // [Store]
1682 //
1683 // In this case, the TokenFactor becomes part of our match and we rewrite it
1684 // as a new TokenFactor.
1685 //
1686 // To distinguish these two cases, do a recursive walk down the uses.
1687 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1688 case CR_Simple:
1689 // If the uses of the TokenFactor are just already-selected nodes, ignore
1690 // it, it is "below" our pattern.
1691 continue;
1692 case CR_InducesCycle:
1693 // If the uses of the TokenFactor lead to nodes that are not part of our
1694 // pattern that are not selected, folding would turn this into a cycle,
1695 // bail out now.
1696 return CR_InducesCycle;
1697 case CR_LeadsToInteriorNode:
1698 break; // Otherwise, keep processing.
1699 }
1701 // Okay, we know we're in the interesting interior case. The TokenFactor
1702 // is now going to be considered part of the pattern so that we rewrite its
1703 // uses (it may have uses that are not part of the pattern) with the
1704 // ultimate chain result of the generated code. We will also add its chain
1705 // inputs as inputs to the ultimate TokenFactor we create.
1706 Result = CR_LeadsToInteriorNode;
1707 ChainedNodesInPattern.push_back(User);
1708 InteriorChainedNodes.push_back(User);
1709 continue;
1710 }
1712 return Result;
1713 }
1715 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1716 /// operation for when the pattern matched at least one node with a chains. The
1717 /// input vector contains a list of all of the chained nodes that we match. We
1718 /// must determine if this is a valid thing to cover (i.e. matching it won't
1719 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1720 /// be used as the input node chain for the generated nodes.
1721 static SDValue
1722 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1723 SelectionDAG *CurDAG) {
1724 // Walk all of the chained nodes we've matched, recursively scanning down the
1725 // users of the chain result. This adds any TokenFactor nodes that are caught
1726 // in between chained nodes to the chained and interior nodes list.
1727 SmallVector<SDNode*, 3> InteriorChainedNodes;
1728 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1729 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1730 InteriorChainedNodes) == CR_InducesCycle)
1731 return SDValue(); // Would induce a cycle.
1732 }
1734 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1735 // that we are interested in. Form our input TokenFactor node.
1736 SmallVector<SDValue, 3> InputChains;
1737 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1738 // Add the input chain of this node to the InputChains list (which will be
1739 // the operands of the generated TokenFactor) if it's not an interior node.
1740 SDNode *N = ChainNodesMatched[i];
1741 if (N->getOpcode() != ISD::TokenFactor) {
1742 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1743 continue;
1745 // Otherwise, add the input chain.
1746 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1747 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1748 InputChains.push_back(InChain);
1749 continue;
1750 }
1752 // If we have a token factor, we want to add all inputs of the token factor
1753 // that are not part of the pattern we're matching.
1754 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1755 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1756 N->getOperand(op).getNode()))
1757 InputChains.push_back(N->getOperand(op));
1758 }
1759 }
1761 SDValue Res;
1762 if (InputChains.size() == 1)
1763 return InputChains[0];
1764 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1765 MVT::Other, &InputChains[0], InputChains.size());
1766 }
1768 /// MorphNode - Handle morphing a node in place for the selector.
1769 SDNode *SelectionDAGISel::
1770 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1771 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1772 // It is possible we're using MorphNodeTo to replace a node with no
1773 // normal results with one that has a normal result (or we could be
1774 // adding a chain) and the input could have glue and chains as well.
1775 // In this case we need to shift the operands down.
1776 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1777 // than the old isel though.
1778 int OldGlueResultNo = -1, OldChainResultNo = -1;
1780 unsigned NTMNumResults = Node->getNumValues();
1781 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
1782 OldGlueResultNo = NTMNumResults-1;
1783 if (NTMNumResults != 1 &&
1784 Node->getValueType(NTMNumResults-2) == MVT::Other)
1785 OldChainResultNo = NTMNumResults-2;
1786 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1787 OldChainResultNo = NTMNumResults-1;
1789 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1790 // that this deletes operands of the old node that become dead.
1791 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1793 // MorphNodeTo can operate in two ways: if an existing node with the
1794 // specified operands exists, it can just return it. Otherwise, it
1795 // updates the node in place to have the requested operands.
1796 if (Res == Node) {
1797 // If we updated the node in place, reset the node ID. To the isel,
1798 // this should be just like a newly allocated machine node.
1799 Res->setNodeId(-1);
1800 }
1802 unsigned ResNumResults = Res->getNumValues();
1803 // Move the glue if needed.
1804 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
1805 (unsigned)OldGlueResultNo != ResNumResults-1)
1806 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
1807 SDValue(Res, ResNumResults-1));
1809 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
1810 --ResNumResults;
1812 // Move the chain reference if needed.
1813 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1814 (unsigned)OldChainResultNo != ResNumResults-1)
1815 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1816 SDValue(Res, ResNumResults-1));
1818 // Otherwise, no replacement happened because the node already exists. Replace
1819 // Uses of the old node with the new one.
1820 if (Res != Node)
1821 CurDAG->ReplaceAllUsesWith(Node, Res);
1823 return Res;
1824 }
1826 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1827 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1828 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1829 SDValue N,
1830 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
1831 // Accept if it is exactly the same as a previously recorded node.
1832 unsigned RecNo = MatcherTable[MatcherIndex++];
1833 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1834 return N == RecordedNodes[RecNo].first;
1835 }
1837 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1838 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1839 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1840 SelectionDAGISel &SDISel) {
1841 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1842 }
1844 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1845 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1846 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1847 SelectionDAGISel &SDISel, SDNode *N) {
1848 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1849 }
1851 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1852 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1853 SDNode *N) {
1854 uint16_t Opc = MatcherTable[MatcherIndex++];
1855 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
1856 return N->getOpcode() == Opc;
1857 }
1859 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1860 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1861 SDValue N, const TargetLowering &TLI) {
1862 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1863 if (N.getValueType() == VT) return true;
1865 // Handle the case when VT is iPTR.
1866 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
1867 }
1869 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1870 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1871 SDValue N, const TargetLowering &TLI,
1872 unsigned ChildNo) {
1873 if (ChildNo >= N.getNumOperands())
1874 return false; // Match fails if out of range child #.
1875 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
1876 }
1879 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1880 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1881 SDValue N) {
1882 return cast<CondCodeSDNode>(N)->get() ==
1883 (ISD::CondCode)MatcherTable[MatcherIndex++];
1884 }
1886 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1887 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1888 SDValue N, const TargetLowering &TLI) {
1889 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1890 if (cast<VTSDNode>(N)->getVT() == VT)
1891 return true;
1893 // Handle the case when VT is iPTR.
1894 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
1895 }
1897 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1898 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1899 SDValue N) {
1900 int64_t Val = MatcherTable[MatcherIndex++];
1901 if (Val & 128)
1902 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1904 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
1905 return C != 0 && C->getSExtValue() == Val;
1906 }
1908 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1909 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1910 SDValue N, SelectionDAGISel &SDISel) {
1911 int64_t Val = MatcherTable[MatcherIndex++];
1912 if (Val & 128)
1913 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1915 if (N->getOpcode() != ISD::AND) return false;
1917 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1918 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
1919 }
1921 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1922 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1923 SDValue N, SelectionDAGISel &SDISel) {
1924 int64_t Val = MatcherTable[MatcherIndex++];
1925 if (Val & 128)
1926 Val = GetVBR(Val, MatcherTable, MatcherIndex);
1928 if (N->getOpcode() != ISD::OR) return false;
1930 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1931 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
1932 }
1934 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
1935 /// scope, evaluate the current node. If the current predicate is known to
1936 /// fail, set Result=true and return anything. If the current predicate is
1937 /// known to pass, set Result=false and return the MatcherIndex to continue
1938 /// with. If the current predicate is unknown, set Result=false and return the
1939 /// MatcherIndex to continue with.
1940 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
1941 unsigned Index, SDValue N,
1942 bool &Result, SelectionDAGISel &SDISel,
1943 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
1944 switch (Table[Index++]) {
1945 default:
1946 Result = false;
1947 return Index-1; // Could not evaluate this predicate.
1948 case SelectionDAGISel::OPC_CheckSame:
1949 Result = !::CheckSame(Table, Index, N, RecordedNodes);
1950 return Index;
1951 case SelectionDAGISel::OPC_CheckPatternPredicate:
1952 Result = !::CheckPatternPredicate(Table, Index, SDISel);
1953 return Index;
1954 case SelectionDAGISel::OPC_CheckPredicate:
1955 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
1956 return Index;
1957 case SelectionDAGISel::OPC_CheckOpcode:
1958 Result = !::CheckOpcode(Table, Index, N.getNode());
1959 return Index;
1960 case SelectionDAGISel::OPC_CheckType:
1961 Result = !::CheckType(Table, Index, N, SDISel.TLI);
1962 return Index;
1963 case SelectionDAGISel::OPC_CheckChild0Type:
1964 case SelectionDAGISel::OPC_CheckChild1Type:
1965 case SelectionDAGISel::OPC_CheckChild2Type:
1966 case SelectionDAGISel::OPC_CheckChild3Type:
1967 case SelectionDAGISel::OPC_CheckChild4Type:
1968 case SelectionDAGISel::OPC_CheckChild5Type:
1969 case SelectionDAGISel::OPC_CheckChild6Type:
1970 case SelectionDAGISel::OPC_CheckChild7Type:
1971 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
1972 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
1973 return Index;
1974 case SelectionDAGISel::OPC_CheckCondCode:
1975 Result = !::CheckCondCode(Table, Index, N);
1976 return Index;
1977 case SelectionDAGISel::OPC_CheckValueType:
1978 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
1979 return Index;
1980 case SelectionDAGISel::OPC_CheckInteger:
1981 Result = !::CheckInteger(Table, Index, N);
1982 return Index;
1983 case SelectionDAGISel::OPC_CheckAndImm:
1984 Result = !::CheckAndImm(Table, Index, N, SDISel);
1985 return Index;
1986 case SelectionDAGISel::OPC_CheckOrImm:
1987 Result = !::CheckOrImm(Table, Index, N, SDISel);
1988 return Index;
1989 }
1990 }
1992 namespace {
1994 struct MatchScope {
1995 /// FailIndex - If this match fails, this is the index to continue with.
1996 unsigned FailIndex;
1998 /// NodeStack - The node stack when the scope was formed.
1999 SmallVector<SDValue, 4> NodeStack;
2001 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2002 unsigned NumRecordedNodes;
2004 /// NumMatchedMemRefs - The number of matched memref entries.
2005 unsigned NumMatchedMemRefs;
2007 /// InputChain/InputGlue - The current chain/glue
2008 SDValue InputChain, InputGlue;
2010 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2011 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2012 };
2014 }
2016 SDNode *SelectionDAGISel::
2017 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2018 unsigned TableSize) {
2019 // FIXME: Should these even be selected? Handle these cases in the caller?
2020 switch (NodeToMatch->getOpcode()) {
2021 default:
2022 break;
2023 case ISD::EntryToken: // These nodes remain the same.
2024 case ISD::BasicBlock:
2025 case ISD::Register:
2026 //case ISD::VALUETYPE:
2027 //case ISD::CONDCODE:
2028 case ISD::HANDLENODE:
2029 case ISD::MDNODE_SDNODE:
2030 case ISD::TargetConstant:
2031 case ISD::TargetConstantFP:
2032 case ISD::TargetConstantPool:
2033 case ISD::TargetFrameIndex:
2034 case ISD::TargetExternalSymbol:
2035 case ISD::TargetBlockAddress:
2036 case ISD::TargetJumpTable:
2037 case ISD::TargetGlobalTLSAddress:
2038 case ISD::TargetGlobalAddress:
2039 case ISD::TokenFactor:
2040 case ISD::CopyFromReg:
2041 case ISD::CopyToReg:
2042 case ISD::EH_LABEL:
2043 NodeToMatch->setNodeId(-1); // Mark selected.
2044 return 0;
2045 case ISD::AssertSext:
2046 case ISD::AssertZext:
2047 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2048 NodeToMatch->getOperand(0));
2049 return 0;
2050 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2051 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2052 }
2054 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2056 // Set up the node stack with NodeToMatch as the only node on the stack.
2057 SmallVector<SDValue, 8> NodeStack;
2058 SDValue N = SDValue(NodeToMatch, 0);
2059 NodeStack.push_back(N);
2061 // MatchScopes - Scopes used when matching, if a match failure happens, this
2062 // indicates where to continue checking.
2063 SmallVector<MatchScope, 8> MatchScopes;
2065 // RecordedNodes - This is the set of nodes that have been recorded by the
2066 // state machine. The second value is the parent of the node, or null if the
2067 // root is recorded.
2068 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2070 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2071 // pattern.
2072 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2074 // These are the current input chain and glue for use when generating nodes.
2075 // Various Emit operations change these. For example, emitting a copytoreg
2076 // uses and updates these.
2077 SDValue InputChain, InputGlue;
2079 // ChainNodesMatched - If a pattern matches nodes that have input/output
2080 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2081 // which ones they are. The result is captured into this list so that we can
2082 // update the chain results when the pattern is complete.
2083 SmallVector<SDNode*, 3> ChainNodesMatched;
2084 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2086 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
2087 NodeToMatch->dump(CurDAG);
2088 errs() << '\n');
2090 // Determine where to start the interpreter. Normally we start at opcode #0,
2091 // but if the state machine starts with an OPC_SwitchOpcode, then we
2092 // accelerate the first lookup (which is guaranteed to be hot) with the
2093 // OpcodeOffset table.
2094 unsigned MatcherIndex = 0;
2096 if (!OpcodeOffset.empty()) {
2097 // Already computed the OpcodeOffset table, just index into it.
2098 if (N.getOpcode() < OpcodeOffset.size())
2099 MatcherIndex = OpcodeOffset[N.getOpcode()];
2100 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
2102 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2103 // Otherwise, the table isn't computed, but the state machine does start
2104 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2105 // is the first time we're selecting an instruction.
2106 unsigned Idx = 1;
2107 while (1) {
2108 // Get the size of this case.
2109 unsigned CaseSize = MatcherTable[Idx++];
2110 if (CaseSize & 128)
2111 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2112 if (CaseSize == 0) break;
2114 // Get the opcode, add the index to the table.
2115 uint16_t Opc = MatcherTable[Idx++];
2116 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2117 if (Opc >= OpcodeOffset.size())
2118 OpcodeOffset.resize((Opc+1)*2);
2119 OpcodeOffset[Opc] = Idx;
2120 Idx += CaseSize;
2121 }
2123 // Okay, do the lookup for the first opcode.
2124 if (N.getOpcode() < OpcodeOffset.size())
2125 MatcherIndex = OpcodeOffset[N.getOpcode()];
2126 }
2128 while (1) {
2129 assert(MatcherIndex < TableSize && "Invalid index");
2130 #ifndef NDEBUG
2131 unsigned CurrentOpcodeIndex = MatcherIndex;
2132 #endif
2133 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2134 switch (Opcode) {
2135 case OPC_Scope: {
2136 // Okay, the semantics of this operation are that we should push a scope
2137 // then evaluate the first child. However, pushing a scope only to have
2138 // the first check fail (which then pops it) is inefficient. If we can
2139 // determine immediately that the first check (or first several) will
2140 // immediately fail, don't even bother pushing a scope for them.
2141 unsigned FailIndex;
2143 while (1) {
2144 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2145 if (NumToSkip & 128)
2146 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2147 // Found the end of the scope with no match.
2148 if (NumToSkip == 0) {
2149 FailIndex = 0;
2150 break;
2151 }
2153 FailIndex = MatcherIndex+NumToSkip;
2155 unsigned MatcherIndexOfPredicate = MatcherIndex;
2156 (void)MatcherIndexOfPredicate; // silence warning.
2158 // If we can't evaluate this predicate without pushing a scope (e.g. if
2159 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2160 // push the scope and evaluate the full predicate chain.
2161 bool Result;
2162 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2163 Result, *this, RecordedNodes);
2164 if (!Result)
2165 break;
2167 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2168 << "index " << MatcherIndexOfPredicate
2169 << ", continuing at " << FailIndex << "\n");
2170 ++NumDAGIselRetries;
2172 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2173 // move to the next case.
2174 MatcherIndex = FailIndex;
2175 }
2177 // If the whole scope failed to match, bail.
2178 if (FailIndex == 0) break;
2180 // Push a MatchScope which indicates where to go if the first child fails
2181 // to match.
2182 MatchScope NewEntry;
2183 NewEntry.FailIndex = FailIndex;
2184 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2185 NewEntry.NumRecordedNodes = RecordedNodes.size();
2186 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2187 NewEntry.InputChain = InputChain;
2188 NewEntry.InputGlue = InputGlue;
2189 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2190 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2191 MatchScopes.push_back(NewEntry);
2192 continue;
2193 }
2194 case OPC_RecordNode: {
2195 // Remember this node, it may end up being an operand in the pattern.
2196 SDNode *Parent = 0;
2197 if (NodeStack.size() > 1)
2198 Parent = NodeStack[NodeStack.size()-2].getNode();
2199 RecordedNodes.push_back(std::make_pair(N, Parent));
2200 continue;
2201 }
2203 case OPC_RecordChild0: case OPC_RecordChild1:
2204 case OPC_RecordChild2: case OPC_RecordChild3:
2205 case OPC_RecordChild4: case OPC_RecordChild5:
2206 case OPC_RecordChild6: case OPC_RecordChild7: {
2207 unsigned ChildNo = Opcode-OPC_RecordChild0;
2208 if (ChildNo >= N.getNumOperands())
2209 break; // Match fails if out of range child #.
2211 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2212 N.getNode()));
2213 continue;
2214 }
2215 case OPC_RecordMemRef:
2216 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2217 continue;
2219 case OPC_CaptureGlueInput:
2220 // If the current node has an input glue, capture it in InputGlue.
2221 if (N->getNumOperands() != 0 &&
2222 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2223 InputGlue = N->getOperand(N->getNumOperands()-1);
2224 continue;
2226 case OPC_MoveChild: {
2227 unsigned ChildNo = MatcherTable[MatcherIndex++];
2228 if (ChildNo >= N.getNumOperands())
2229 break; // Match fails if out of range child #.
2230 N = N.getOperand(ChildNo);
2231 NodeStack.push_back(N);
2232 continue;
2233 }
2235 case OPC_MoveParent:
2236 // Pop the current node off the NodeStack.
2237 NodeStack.pop_back();
2238 assert(!NodeStack.empty() && "Node stack imbalance!");
2239 N = NodeStack.back();
2240 continue;
2242 case OPC_CheckSame:
2243 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2244 continue;
2245 case OPC_CheckPatternPredicate:
2246 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2247 continue;
2248 case OPC_CheckPredicate:
2249 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2250 N.getNode()))
2251 break;
2252 continue;
2253 case OPC_CheckComplexPat: {
2254 unsigned CPNum = MatcherTable[MatcherIndex++];
2255 unsigned RecNo = MatcherTable[MatcherIndex++];
2256 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2257 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2258 RecordedNodes[RecNo].first, CPNum,
2259 RecordedNodes))
2260 break;
2261 continue;
2262 }
2263 case OPC_CheckOpcode:
2264 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2265 continue;
2267 case OPC_CheckType:
2268 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2269 continue;
2271 case OPC_SwitchOpcode: {
2272 unsigned CurNodeOpcode = N.getOpcode();
2273 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2274 unsigned CaseSize;
2275 while (1) {
2276 // Get the size of this case.
2277 CaseSize = MatcherTable[MatcherIndex++];
2278 if (CaseSize & 128)
2279 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2280 if (CaseSize == 0) break;
2282 uint16_t Opc = MatcherTable[MatcherIndex++];
2283 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2285 // If the opcode matches, then we will execute this case.
2286 if (CurNodeOpcode == Opc)
2287 break;
2289 // Otherwise, skip over this case.
2290 MatcherIndex += CaseSize;
2291 }
2293 // If no cases matched, bail out.
2294 if (CaseSize == 0) break;
2296 // Otherwise, execute the case we found.
2297 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2298 << " to " << MatcherIndex << "\n");
2299 continue;
2300 }
2302 case OPC_SwitchType: {
2303 MVT CurNodeVT = N.getValueType().getSimpleVT();
2304 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2305 unsigned CaseSize;
2306 while (1) {
2307 // Get the size of this case.
2308 CaseSize = MatcherTable[MatcherIndex++];
2309 if (CaseSize & 128)
2310 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2311 if (CaseSize == 0) break;
2313 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2314 if (CaseVT == MVT::iPTR)
2315 CaseVT = TLI.getPointerTy();
2317 // If the VT matches, then we will execute this case.
2318 if (CurNodeVT == CaseVT)
2319 break;
2321 // Otherwise, skip over this case.
2322 MatcherIndex += CaseSize;
2323 }
2325 // If no cases matched, bail out.
2326 if (CaseSize == 0) break;
2328 // Otherwise, execute the case we found.
2329 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2330 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2331 continue;
2332 }
2333 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2334 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2335 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2336 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2337 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2338 Opcode-OPC_CheckChild0Type))
2339 break;
2340 continue;
2341 case OPC_CheckCondCode:
2342 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2343 continue;
2344 case OPC_CheckValueType:
2345 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2346 continue;
2347 case OPC_CheckInteger:
2348 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2349 continue;
2350 case OPC_CheckAndImm:
2351 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2352 continue;
2353 case OPC_CheckOrImm:
2354 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2355 continue;
2357 case OPC_CheckFoldableChainNode: {
2358 assert(NodeStack.size() != 1 && "No parent node");
2359 // Verify that all intermediate nodes between the root and this one have
2360 // a single use.
2361 bool HasMultipleUses = false;
2362 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2363 if (!NodeStack[i].hasOneUse()) {
2364 HasMultipleUses = true;
2365 break;
2366 }
2367 if (HasMultipleUses) break;
2369 // Check to see that the target thinks this is profitable to fold and that
2370 // we can fold it without inducing cycles in the graph.
2371 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2372 NodeToMatch) ||
2373 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2374 NodeToMatch, OptLevel,
2375 true/*We validate our own chains*/))
2376 break;
2378 continue;
2379 }
2380 case OPC_EmitInteger: {
2381 MVT::SimpleValueType VT =
2382 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2383 int64_t Val = MatcherTable[MatcherIndex++];
2384 if (Val & 128)
2385 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2386 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2387 CurDAG->getTargetConstant(Val, VT), (SDNode*)0));
2388 continue;
2389 }
2390 case OPC_EmitRegister: {
2391 MVT::SimpleValueType VT =
2392 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2393 unsigned RegNo = MatcherTable[MatcherIndex++];
2394 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2395 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2396 continue;
2397 }
2398 case OPC_EmitRegister2: {
2399 // For targets w/ more than 256 register names, the register enum
2400 // values are stored in two bytes in the matcher table (just like
2401 // opcodes).
2402 MVT::SimpleValueType VT =
2403 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2404 unsigned RegNo = MatcherTable[MatcherIndex++];
2405 RegNo |= MatcherTable[MatcherIndex++] << 8;
2406 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2407 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2408 continue;
2409 }
2411 case OPC_EmitConvertToTarget: {
2412 // Convert from IMM/FPIMM to target version.
2413 unsigned RecNo = MatcherTable[MatcherIndex++];
2414 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2415 SDValue Imm = RecordedNodes[RecNo].first;
2417 if (Imm->getOpcode() == ISD::Constant) {
2418 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2419 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2420 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2421 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2422 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2423 }
2425 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2426 continue;
2427 }
2429 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2430 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2431 // These are space-optimized forms of OPC_EmitMergeInputChains.
2432 assert(InputChain.getNode() == 0 &&
2433 "EmitMergeInputChains should be the first chain producing node");
2434 assert(ChainNodesMatched.empty() &&
2435 "Should only have one EmitMergeInputChains per match");
2437 // Read all of the chained nodes.
2438 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2439 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2440 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2442 // FIXME: What if other value results of the node have uses not matched
2443 // by this pattern?
2444 if (ChainNodesMatched.back() != NodeToMatch &&
2445 !RecordedNodes[RecNo].first.hasOneUse()) {
2446 ChainNodesMatched.clear();
2447 break;
2448 }
2450 // Merge the input chains if they are not intra-pattern references.
2451 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2453 if (InputChain.getNode() == 0)
2454 break; // Failed to merge.
2455 continue;
2456 }
2458 case OPC_EmitMergeInputChains: {
2459 assert(InputChain.getNode() == 0 &&
2460 "EmitMergeInputChains should be the first chain producing node");
2461 // This node gets a list of nodes we matched in the input that have
2462 // chains. We want to token factor all of the input chains to these nodes
2463 // together. However, if any of the input chains is actually one of the
2464 // nodes matched in this pattern, then we have an intra-match reference.
2465 // Ignore these because the newly token factored chain should not refer to
2466 // the old nodes.
2467 unsigned NumChains = MatcherTable[MatcherIndex++];
2468 assert(NumChains != 0 && "Can't TF zero chains");
2470 assert(ChainNodesMatched.empty() &&
2471 "Should only have one EmitMergeInputChains per match");
2473 // Read all of the chained nodes.
2474 for (unsigned i = 0; i != NumChains; ++i) {
2475 unsigned RecNo = MatcherTable[MatcherIndex++];
2476 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2477 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2479 // FIXME: What if other value results of the node have uses not matched
2480 // by this pattern?
2481 if (ChainNodesMatched.back() != NodeToMatch &&
2482 !RecordedNodes[RecNo].first.hasOneUse()) {
2483 ChainNodesMatched.clear();
2484 break;
2485 }
2486 }
2488 // If the inner loop broke out, the match fails.
2489 if (ChainNodesMatched.empty())
2490 break;
2492 // Merge the input chains if they are not intra-pattern references.
2493 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2495 if (InputChain.getNode() == 0)
2496 break; // Failed to merge.
2498 continue;
2499 }
2501 case OPC_EmitCopyToReg: {
2502 unsigned RecNo = MatcherTable[MatcherIndex++];
2503 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2504 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2506 if (InputChain.getNode() == 0)
2507 InputChain = CurDAG->getEntryNode();
2509 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2510 DestPhysReg, RecordedNodes[RecNo].first,
2511 InputGlue);
2513 InputGlue = InputChain.getValue(1);
2514 continue;
2515 }
2517 case OPC_EmitNodeXForm: {
2518 unsigned XFormNo = MatcherTable[MatcherIndex++];
2519 unsigned RecNo = MatcherTable[MatcherIndex++];
2520 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2521 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
2522 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0));
2523 continue;
2524 }
2526 case OPC_EmitNode:
2527 case OPC_MorphNodeTo: {
2528 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2529 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2530 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2531 // Get the result VT list.
2532 unsigned NumVTs = MatcherTable[MatcherIndex++];
2533 SmallVector<EVT, 4> VTs;
2534 for (unsigned i = 0; i != NumVTs; ++i) {
2535 MVT::SimpleValueType VT =
2536 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2537 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2538 VTs.push_back(VT);
2539 }
2541 if (EmitNodeInfo & OPFL_Chain)
2542 VTs.push_back(MVT::Other);
2543 if (EmitNodeInfo & OPFL_GlueOutput)
2544 VTs.push_back(MVT::Glue);
2546 // This is hot code, so optimize the two most common cases of 1 and 2
2547 // results.
2548 SDVTList VTList;
2549 if (VTs.size() == 1)
2550 VTList = CurDAG->getVTList(VTs[0]);
2551 else if (VTs.size() == 2)
2552 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2553 else
2554 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2556 // Get the operand list.
2557 unsigned NumOps = MatcherTable[MatcherIndex++];
2558 SmallVector<SDValue, 8> Ops;
2559 for (unsigned i = 0; i != NumOps; ++i) {
2560 unsigned RecNo = MatcherTable[MatcherIndex++];
2561 if (RecNo & 128)
2562 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2564 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2565 Ops.push_back(RecordedNodes[RecNo].first);
2566 }
2568 // If there are variadic operands to add, handle them now.
2569 if (EmitNodeInfo & OPFL_VariadicInfo) {
2570 // Determine the start index to copy from.
2571 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2572 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2573 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2574 "Invalid variadic node");
2575 // Copy all of the variadic operands, not including a potential glue
2576 // input.
2577 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2578 i != e; ++i) {
2579 SDValue V = NodeToMatch->getOperand(i);
2580 if (V.getValueType() == MVT::Glue) break;
2581 Ops.push_back(V);
2582 }
2583 }
2585 // If this has chain/glue inputs, add them.
2586 if (EmitNodeInfo & OPFL_Chain)
2587 Ops.push_back(InputChain);
2588 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0)
2589 Ops.push_back(InputGlue);
2591 // Create the node.
2592 SDNode *Res = 0;
2593 if (Opcode != OPC_MorphNodeTo) {
2594 // If this is a normal EmitNode command, just create the new node and
2595 // add the results to the RecordedNodes list.
2596 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2597 VTList, Ops.data(), Ops.size());
2599 // Add all the non-glue/non-chain results to the RecordedNodes list.
2600 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2601 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
2602 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
2603 (SDNode*) 0));
2604 }
2606 } else {
2607 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2608 EmitNodeInfo);
2609 }
2611 // If the node had chain/glue results, update our notion of the current
2612 // chain and glue.
2613 if (EmitNodeInfo & OPFL_GlueOutput) {
2614 InputGlue = SDValue(Res, VTs.size()-1);
2615 if (EmitNodeInfo & OPFL_Chain)
2616 InputChain = SDValue(Res, VTs.size()-2);
2617 } else if (EmitNodeInfo & OPFL_Chain)
2618 InputChain = SDValue(Res, VTs.size()-1);
2620 // If the OPFL_MemRefs glue is set on this node, slap all of the
2621 // accumulated memrefs onto it.
2622 //
2623 // FIXME: This is vastly incorrect for patterns with multiple outputs
2624 // instructions that access memory and for ComplexPatterns that match
2625 // loads.
2626 if (EmitNodeInfo & OPFL_MemRefs) {
2627 // Only attach load or store memory operands if the generated
2628 // instruction may load or store.
2629 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc);
2630 bool mayLoad = MCID.mayLoad();
2631 bool mayStore = MCID.mayStore();
2633 unsigned NumMemRefs = 0;
2634 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2635 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2636 if ((*I)->isLoad()) {
2637 if (mayLoad)
2638 ++NumMemRefs;
2639 } else if ((*I)->isStore()) {
2640 if (mayStore)
2641 ++NumMemRefs;
2642 } else {
2643 ++NumMemRefs;
2644 }
2645 }
2647 MachineSDNode::mmo_iterator MemRefs =
2648 MF->allocateMemRefsArray(NumMemRefs);
2650 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
2651 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2652 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2653 if ((*I)->isLoad()) {
2654 if (mayLoad)
2655 *MemRefsPos++ = *I;
2656 } else if ((*I)->isStore()) {
2657 if (mayStore)
2658 *MemRefsPos++ = *I;
2659 } else {
2660 *MemRefsPos++ = *I;
2661 }
2662 }
2664 cast<MachineSDNode>(Res)
2665 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
2666 }
2668 DEBUG(errs() << " "
2669 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2670 << " node: "; Res->dump(CurDAG); errs() << "\n");
2672 // If this was a MorphNodeTo then we're completely done!
2673 if (Opcode == OPC_MorphNodeTo) {
2674 // Update chain and glue uses.
2675 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2676 InputGlue, GlueResultNodesMatched, true);
2677 return Res;
2678 }
2680 continue;
2681 }
2683 case OPC_MarkGlueResults: {
2684 unsigned NumNodes = MatcherTable[MatcherIndex++];
2686 // Read and remember all the glue-result nodes.
2687 for (unsigned i = 0; i != NumNodes; ++i) {
2688 unsigned RecNo = MatcherTable[MatcherIndex++];
2689 if (RecNo & 128)
2690 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2692 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2693 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2694 }
2695 continue;
2696 }
2698 case OPC_CompleteMatch: {
2699 // The match has been completed, and any new nodes (if any) have been
2700 // created. Patch up references to the matched dag to use the newly
2701 // created nodes.
2702 unsigned NumResults = MatcherTable[MatcherIndex++];
2704 for (unsigned i = 0; i != NumResults; ++i) {
2705 unsigned ResSlot = MatcherTable[MatcherIndex++];
2706 if (ResSlot & 128)
2707 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2709 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2710 SDValue Res = RecordedNodes[ResSlot].first;
2712 assert(i < NodeToMatch->getNumValues() &&
2713 NodeToMatch->getValueType(i) != MVT::Other &&
2714 NodeToMatch->getValueType(i) != MVT::Glue &&
2715 "Invalid number of results to complete!");
2716 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2717 NodeToMatch->getValueType(i) == MVT::iPTR ||
2718 Res.getValueType() == MVT::iPTR ||
2719 NodeToMatch->getValueType(i).getSizeInBits() ==
2720 Res.getValueType().getSizeInBits()) &&
2721 "invalid replacement");
2722 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2723 }
2725 // If the root node defines glue, add it to the glue nodes to update list.
2726 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
2727 GlueResultNodesMatched.push_back(NodeToMatch);
2729 // Update chain and glue uses.
2730 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2731 InputGlue, GlueResultNodesMatched, false);
2733 assert(NodeToMatch->use_empty() &&
2734 "Didn't replace all uses of the node?");
2736 // FIXME: We just return here, which interacts correctly with SelectRoot
2737 // above. We should fix this to not return an SDNode* anymore.
2738 return 0;
2739 }
2740 }
2742 // If the code reached this point, then the match failed. See if there is
2743 // another child to try in the current 'Scope', otherwise pop it until we
2744 // find a case to check.
2745 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2746 ++NumDAGIselRetries;
2747 while (1) {
2748 if (MatchScopes.empty()) {
2749 CannotYetSelect(NodeToMatch);
2750 return 0;
2751 }
2753 // Restore the interpreter state back to the point where the scope was
2754 // formed.
2755 MatchScope &LastScope = MatchScopes.back();
2756 RecordedNodes.resize(LastScope.NumRecordedNodes);
2757 NodeStack.clear();
2758 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2759 N = NodeStack.back();
2761 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2762 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2763 MatcherIndex = LastScope.FailIndex;
2765 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2767 InputChain = LastScope.InputChain;
2768 InputGlue = LastScope.InputGlue;
2769 if (!LastScope.HasChainNodesMatched)
2770 ChainNodesMatched.clear();
2771 if (!LastScope.HasGlueResultNodesMatched)
2772 GlueResultNodesMatched.clear();
2774 // Check to see what the offset is at the new MatcherIndex. If it is zero
2775 // we have reached the end of this scope, otherwise we have another child
2776 // in the current scope to try.
2777 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2778 if (NumToSkip & 128)
2779 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2781 // If we have another child in this scope to match, update FailIndex and
2782 // try it.
2783 if (NumToSkip != 0) {
2784 LastScope.FailIndex = MatcherIndex+NumToSkip;
2785 break;
2786 }
2788 // End of this scope, pop it and try the next child in the containing
2789 // scope.
2790 MatchScopes.pop_back();
2791 }
2792 }
2793 }
2797 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2798 std::string msg;
2799 raw_string_ostream Msg(msg);
2800 Msg << "Cannot select: ";
2802 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2803 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2804 N->getOpcode() != ISD::INTRINSIC_VOID) {
2805 N->printrFull(Msg, CurDAG);
2806 } else {
2807 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2808 unsigned iid =
2809 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2810 if (iid < Intrinsic::num_intrinsics)
2811 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2812 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2813 Msg << "target intrinsic %" << TII->getName(iid);
2814 else
2815 Msg << "unknown intrinsic #" << iid;
2816 }
2817 report_fatal_error(Msg.str());
2818 }
2820 char SelectionDAGISel::ID = 0;