1 //==- AArch64RegisterInfo.h - AArch64 Register Information Impl -*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the AArch64 implementation of the MCRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_AARCH64REGISTERINFO_H
15 #define LLVM_TARGET_AARCH64REGISTERINFO_H
17 #include "llvm/Target/TargetRegisterInfo.h"
19 #define GET_REGINFO_HEADER
20 #include "AArch64GenRegisterInfo.inc"
22 namespace llvm {
24 class AArch64InstrInfo;
25 class AArch64Subtarget;
27 struct AArch64RegisterInfo : public AArch64GenRegisterInfo {
28 AArch64RegisterInfo();
30 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF =nullptr) const;
31 const uint32_t *getCallPreservedMask(CallingConv::ID) const;
33 unsigned getCSRFirstUseCost() const {
34 // The cost will be compared against BlockFrequency where entry has the
35 // value of 1 << 14. A value of 5 will choose to spill or split really
36 // cold path instead of using a callee-saved register.
37 return 5;
38 }
40 const uint32_t *getTLSDescCallPreservedMask() const;
42 BitVector getReservedRegs(const MachineFunction &MF) const;
43 unsigned getFrameRegister(const MachineFunction &MF) const;
45 void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
46 unsigned FIOperandNum,
47 RegScavenger *Rs = nullptr) const;
49 /// getCrossCopyRegClass - Returns a legal register class to copy a register
50 /// in the specified class to or from. Returns original class if it is
51 /// possible to copy between a two registers of the specified class.
52 const TargetRegisterClass *
53 getCrossCopyRegClass(const TargetRegisterClass *RC) const;
55 /// getLargestLegalSuperClass - Returns the largest super class of RC that is
56 /// legal to use in the current sub-target and has the same spill size.
57 const TargetRegisterClass*
58 getLargestLegalSuperClass(const TargetRegisterClass *RC) const {
59 if (RC == &AArch64::tcGPR64RegClass)
60 return &AArch64::GPR64RegClass;
62 return RC;
63 }
65 bool requiresRegisterScavenging(const MachineFunction &MF) const {
66 return true;
67 }
69 bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
70 return true;
71 }
73 bool useFPForScavengingIndex(const MachineFunction &MF) const;
74 };
76 } // end namespace llvm
78 #endif // LLVM_TARGET_AARCH64REGISTERINFO_H