f688407d6943fe51d558ff63495598c15edac0f4
1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
12 //
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
16 #include "ARMAsmPrinter.h"
17 #include "ARM.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMFPUName.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMTargetMachine.h"
22 #include "ARMTargetObjectFile.h"
23 #include "InstPrinter/ARMInstPrinter.h"
24 #include "MCTargetDesc/ARMAddressingModes.h"
25 #include "MCTargetDesc/ARMMCExpr.h"
26 #include "llvm/ADT/SetVector.h"
27 #include "llvm/ADT/SmallString.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineJumpTableInfo.h"
30 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
31 #include "llvm/DebugInfo.h"
32 #include "llvm/IR/Constants.h"
33 #include "llvm/IR/DataLayout.h"
34 #include "llvm/IR/Mangler.h"
35 #include "llvm/IR/Module.h"
36 #include "llvm/IR/Type.h"
37 #include "llvm/MC/MCAsmInfo.h"
38 #include "llvm/MC/MCAssembler.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCELFStreamer.h"
41 #include "llvm/MC/MCInst.h"
42 #include "llvm/MC/MCInstBuilder.h"
43 #include "llvm/MC/MCObjectStreamer.h"
44 #include "llvm/MC/MCSectionMachO.h"
45 #include "llvm/MC/MCStreamer.h"
46 #include "llvm/MC/MCSymbol.h"
47 #include "llvm/Support/ARMBuildAttributes.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ELF.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/TargetRegistry.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/TargetMachine.h"
55 #include <cctype>
56 using namespace llvm;
58 /// EmitDwarfRegOp - Emit dwarf register operation.
59 void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc,
60 bool Indirect) const {
61 const TargetRegisterInfo *RI = TM.getRegisterInfo();
62 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1) {
63 AsmPrinter::EmitDwarfRegOp(MLoc, Indirect);
64 return;
65 }
66 assert(MLoc.isReg() && !Indirect &&
67 "This doesn't support offset/indirection - implement it if needed");
68 unsigned Reg = MLoc.getReg();
69 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
70 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
71 // S registers are described as bit-pieces of a register
72 // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
73 // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
75 unsigned SReg = Reg - ARM::S0;
76 bool odd = SReg & 0x1;
77 unsigned Rx = 256 + (SReg >> 1);
79 OutStreamer.AddComment("DW_OP_regx for S register");
80 EmitInt8(dwarf::DW_OP_regx);
82 OutStreamer.AddComment(Twine(SReg));
83 EmitULEB128(Rx);
85 if (odd) {
86 OutStreamer.AddComment("DW_OP_bit_piece 32 32");
87 EmitInt8(dwarf::DW_OP_bit_piece);
88 EmitULEB128(32);
89 EmitULEB128(32);
90 } else {
91 OutStreamer.AddComment("DW_OP_bit_piece 32 0");
92 EmitInt8(dwarf::DW_OP_bit_piece);
93 EmitULEB128(32);
94 EmitULEB128(0);
95 }
96 } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
97 assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
98 // Q registers Q0-Q15 are described by composing two D registers together.
99 // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1)
100 // DW_OP_piece(8)
102 unsigned QReg = Reg - ARM::Q0;
103 unsigned D1 = 256 + 2 * QReg;
104 unsigned D2 = D1 + 1;
106 OutStreamer.AddComment("DW_OP_regx for Q register: D1");
107 EmitInt8(dwarf::DW_OP_regx);
108 EmitULEB128(D1);
109 OutStreamer.AddComment("DW_OP_piece 8");
110 EmitInt8(dwarf::DW_OP_piece);
111 EmitULEB128(8);
113 OutStreamer.AddComment("DW_OP_regx for Q register: D2");
114 EmitInt8(dwarf::DW_OP_regx);
115 EmitULEB128(D2);
116 OutStreamer.AddComment("DW_OP_piece 8");
117 EmitInt8(dwarf::DW_OP_piece);
118 EmitULEB128(8);
119 }
120 }
122 void ARMAsmPrinter::EmitFunctionBodyEnd() {
123 // Make sure to terminate any constant pools that were at the end
124 // of the function.
125 if (!InConstantPool)
126 return;
127 InConstantPool = false;
128 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
129 }
131 void ARMAsmPrinter::EmitFunctionEntryLabel() {
132 if (AFI->isThumbFunction()) {
133 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
134 OutStreamer.EmitThumbFunc(CurrentFnSym);
135 }
137 OutStreamer.EmitLabel(CurrentFnSym);
138 }
140 void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
141 uint64_t Size = TM.getDataLayout()->getTypeAllocSize(CV->getType());
142 assert(Size && "C++ constructor pointer had zero size!");
144 const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
145 assert(GV && "C++ constructor pointer was not a GlobalValue!");
147 const MCExpr *E = MCSymbolRefExpr::Create(getSymbol(GV),
148 (Subtarget->isTargetELF()
149 ? MCSymbolRefExpr::VK_ARM_TARGET1
150 : MCSymbolRefExpr::VK_None),
151 OutContext);
153 OutStreamer.EmitValue(E, Size);
154 }
156 /// runOnMachineFunction - This uses the EmitInstruction()
157 /// method to print assembly for each instruction.
158 ///
159 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
160 AFI = MF.getInfo<ARMFunctionInfo>();
161 MCP = MF.getConstantPool();
163 return AsmPrinter::runOnMachineFunction(MF);
164 }
166 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
167 raw_ostream &O, const char *Modifier) {
168 const MachineOperand &MO = MI->getOperand(OpNum);
169 unsigned TF = MO.getTargetFlags();
171 switch (MO.getType()) {
172 default: llvm_unreachable("<unknown operand type>");
173 case MachineOperand::MO_Register: {
174 unsigned Reg = MO.getReg();
175 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
176 assert(!MO.getSubReg() && "Subregs should be eliminated!");
177 if(ARM::GPRPairRegClass.contains(Reg)) {
178 const MachineFunction &MF = *MI->getParent()->getParent();
179 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
180 Reg = TRI->getSubReg(Reg, ARM::gsub_0);
181 }
182 O << ARMInstPrinter::getRegisterName(Reg);
183 break;
184 }
185 case MachineOperand::MO_Immediate: {
186 int64_t Imm = MO.getImm();
187 O << '#';
188 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
189 (TF == ARMII::MO_LO16))
190 O << ":lower16:";
191 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
192 (TF == ARMII::MO_HI16))
193 O << ":upper16:";
194 O << Imm;
195 break;
196 }
197 case MachineOperand::MO_MachineBasicBlock:
198 O << *MO.getMBB()->getSymbol();
199 return;
200 case MachineOperand::MO_GlobalAddress: {
201 const GlobalValue *GV = MO.getGlobal();
202 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
203 (TF & ARMII::MO_LO16))
204 O << ":lower16:";
205 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
206 (TF & ARMII::MO_HI16))
207 O << ":upper16:";
208 O << *getSymbol(GV);
210 printOffset(MO.getOffset(), O);
211 if (TF == ARMII::MO_PLT)
212 O << "(PLT)";
213 break;
214 }
215 case MachineOperand::MO_ConstantPoolIndex:
216 O << *GetCPISymbol(MO.getIndex());
217 break;
218 }
219 }
221 //===--------------------------------------------------------------------===//
223 MCSymbol *ARMAsmPrinter::
224 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
225 const DataLayout *DL = TM.getDataLayout();
226 SmallString<60> Name;
227 raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "JTI"
228 << getFunctionNumber() << '_' << uid << '_' << uid2;
229 return OutContext.GetOrCreateSymbol(Name.str());
230 }
233 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel() const {
234 const DataLayout *DL = TM.getDataLayout();
235 SmallString<60> Name;
236 raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "SJLJEH"
237 << getFunctionNumber();
238 return OutContext.GetOrCreateSymbol(Name.str());
239 }
241 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
242 unsigned AsmVariant, const char *ExtraCode,
243 raw_ostream &O) {
244 // Does this asm operand have a single letter operand modifier?
245 if (ExtraCode && ExtraCode[0]) {
246 if (ExtraCode[1] != 0) return true; // Unknown modifier.
248 switch (ExtraCode[0]) {
249 default:
250 // See if this is a generic print operand
251 return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
252 case 'a': // Print as a memory address.
253 if (MI->getOperand(OpNum).isReg()) {
254 O << "["
255 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
256 << "]";
257 return false;
258 }
259 // Fallthrough
260 case 'c': // Don't print "#" before an immediate operand.
261 if (!MI->getOperand(OpNum).isImm())
262 return true;
263 O << MI->getOperand(OpNum).getImm();
264 return false;
265 case 'P': // Print a VFP double precision register.
266 case 'q': // Print a NEON quad precision register.
267 printOperand(MI, OpNum, O);
268 return false;
269 case 'y': // Print a VFP single precision register as indexed double.
270 if (MI->getOperand(OpNum).isReg()) {
271 unsigned Reg = MI->getOperand(OpNum).getReg();
272 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
273 // Find the 'd' register that has this 's' register as a sub-register,
274 // and determine the lane number.
275 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
276 if (!ARM::DPRRegClass.contains(*SR))
277 continue;
278 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
279 O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
280 return false;
281 }
282 }
283 return true;
284 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
285 if (!MI->getOperand(OpNum).isImm())
286 return true;
287 O << ~(MI->getOperand(OpNum).getImm());
288 return false;
289 case 'L': // The low 16 bits of an immediate constant.
290 if (!MI->getOperand(OpNum).isImm())
291 return true;
292 O << (MI->getOperand(OpNum).getImm() & 0xffff);
293 return false;
294 case 'M': { // A register range suitable for LDM/STM.
295 if (!MI->getOperand(OpNum).isReg())
296 return true;
297 const MachineOperand &MO = MI->getOperand(OpNum);
298 unsigned RegBegin = MO.getReg();
299 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
300 // already got the operands in registers that are operands to the
301 // inline asm statement.
302 O << "{";
303 if (ARM::GPRPairRegClass.contains(RegBegin)) {
304 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
305 unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
306 O << ARMInstPrinter::getRegisterName(Reg0) << ", ";;
307 RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
308 }
309 O << ARMInstPrinter::getRegisterName(RegBegin);
311 // FIXME: The register allocator not only may not have given us the
312 // registers in sequence, but may not be in ascending registers. This
313 // will require changes in the register allocator that'll need to be
314 // propagated down here if the operands change.
315 unsigned RegOps = OpNum + 1;
316 while (MI->getOperand(RegOps).isReg()) {
317 O << ", "
318 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
319 RegOps++;
320 }
322 O << "}";
324 return false;
325 }
326 case 'R': // The most significant register of a pair.
327 case 'Q': { // The least significant register of a pair.
328 if (OpNum == 0)
329 return true;
330 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
331 if (!FlagsOP.isImm())
332 return true;
333 unsigned Flags = FlagsOP.getImm();
335 // This operand may not be the one that actually provides the register. If
336 // it's tied to a previous one then we should refer instead to that one
337 // for registers and their classes.
338 unsigned TiedIdx;
339 if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
340 for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
341 unsigned OpFlags = MI->getOperand(OpNum).getImm();
342 OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
343 }
344 Flags = MI->getOperand(OpNum).getImm();
346 // Later code expects OpNum to be pointing at the register rather than
347 // the flags.
348 OpNum += 1;
349 }
351 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
352 unsigned RC;
353 InlineAsm::hasRegClassConstraint(Flags, RC);
354 if (RC == ARM::GPRPairRegClassID) {
355 if (NumVals != 1)
356 return true;
357 const MachineOperand &MO = MI->getOperand(OpNum);
358 if (!MO.isReg())
359 return true;
360 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
361 unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
362 ARM::gsub_0 : ARM::gsub_1);
363 O << ARMInstPrinter::getRegisterName(Reg);
364 return false;
365 }
366 if (NumVals != 2)
367 return true;
368 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
369 if (RegOp >= MI->getNumOperands())
370 return true;
371 const MachineOperand &MO = MI->getOperand(RegOp);
372 if (!MO.isReg())
373 return true;
374 unsigned Reg = MO.getReg();
375 O << ARMInstPrinter::getRegisterName(Reg);
376 return false;
377 }
379 case 'e': // The low doubleword register of a NEON quad register.
380 case 'f': { // The high doubleword register of a NEON quad register.
381 if (!MI->getOperand(OpNum).isReg())
382 return true;
383 unsigned Reg = MI->getOperand(OpNum).getReg();
384 if (!ARM::QPRRegClass.contains(Reg))
385 return true;
386 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
387 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
388 ARM::dsub_0 : ARM::dsub_1);
389 O << ARMInstPrinter::getRegisterName(SubReg);
390 return false;
391 }
393 // This modifier is not yet supported.
394 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
395 return true;
396 case 'H': { // The highest-numbered register of a pair.
397 const MachineOperand &MO = MI->getOperand(OpNum);
398 if (!MO.isReg())
399 return true;
400 const MachineFunction &MF = *MI->getParent()->getParent();
401 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
402 unsigned Reg = MO.getReg();
403 if(!ARM::GPRPairRegClass.contains(Reg))
404 return false;
405 Reg = TRI->getSubReg(Reg, ARM::gsub_1);
406 O << ARMInstPrinter::getRegisterName(Reg);
407 return false;
408 }
409 }
410 }
412 printOperand(MI, OpNum, O);
413 return false;
414 }
416 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
417 unsigned OpNum, unsigned AsmVariant,
418 const char *ExtraCode,
419 raw_ostream &O) {
420 // Does this asm operand have a single letter operand modifier?
421 if (ExtraCode && ExtraCode[0]) {
422 if (ExtraCode[1] != 0) return true; // Unknown modifier.
424 switch (ExtraCode[0]) {
425 case 'A': // A memory operand for a VLD1/VST1 instruction.
426 default: return true; // Unknown modifier.
427 case 'm': // The base register of a memory operand.
428 if (!MI->getOperand(OpNum).isReg())
429 return true;
430 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
431 return false;
432 }
433 }
435 const MachineOperand &MO = MI->getOperand(OpNum);
436 assert(MO.isReg() && "unexpected inline asm memory operand");
437 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
438 return false;
439 }
441 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
442 if (Subtarget->isTargetMachO()) {
443 Reloc::Model RelocM = TM.getRelocationModel();
444 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
445 // Declare all the text sections up front (before the DWARF sections
446 // emitted by AsmPrinter::doInitialization) so the assembler will keep
447 // them together at the beginning of the object file. This helps
448 // avoid out-of-range branches that are due a fundamental limitation of
449 // the way symbol offsets are encoded with the current Darwin ARM
450 // relocations.
451 const TargetLoweringObjectFileMachO &TLOFMacho =
452 static_cast<const TargetLoweringObjectFileMachO &>(
453 getObjFileLowering());
455 // Collect the set of sections our functions will go into.
456 SetVector<const MCSection *, SmallVector<const MCSection *, 8>,
457 SmallPtrSet<const MCSection *, 8> > TextSections;
458 // Default text section comes first.
459 TextSections.insert(TLOFMacho.getTextSection());
460 // Now any user defined text sections from function attributes.
461 for (Module::iterator F = M.begin(), e = M.end(); F != e; ++F)
462 if (!F->isDeclaration() && !F->hasAvailableExternallyLinkage())
463 TextSections.insert(TLOFMacho.SectionForGlobal(F, Mang, TM));
464 // Now the coalescable sections.
465 TextSections.insert(TLOFMacho.getTextCoalSection());
466 TextSections.insert(TLOFMacho.getConstTextCoalSection());
468 // Emit the sections in the .s file header to fix the order.
469 for (unsigned i = 0, e = TextSections.size(); i != e; ++i)
470 OutStreamer.SwitchSection(TextSections[i]);
472 if (RelocM == Reloc::DynamicNoPIC) {
473 const MCSection *sect =
474 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
475 MCSectionMachO::S_SYMBOL_STUBS,
476 12, SectionKind::getText());
477 OutStreamer.SwitchSection(sect);
478 } else {
479 const MCSection *sect =
480 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
481 MCSectionMachO::S_SYMBOL_STUBS,
482 16, SectionKind::getText());
483 OutStreamer.SwitchSection(sect);
484 }
485 const MCSection *StaticInitSect =
486 OutContext.getMachOSection("__TEXT", "__StaticInit",
487 MCSectionMachO::S_REGULAR |
488 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
489 SectionKind::getText());
490 OutStreamer.SwitchSection(StaticInitSect);
491 }
493 // Compiling with debug info should not affect the code
494 // generation! Since some of the data sections are first switched
495 // to only in ASMPrinter::doFinalization(), the debug info
496 // sections would come before the data sections in the object
497 // file. This is problematic, since PC-relative loads have to use
498 // different instruction sequences in order to reach global data
499 // in the same object file.
500 OutStreamer.SwitchSection(getObjFileLowering().getCStringSection());
501 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
502 OutStreamer.SwitchSection(getObjFileLowering().getDataCommonSection());
503 OutStreamer.SwitchSection(getObjFileLowering().getDataBSSSection());
504 OutStreamer.SwitchSection(getObjFileLowering().getNonLazySymbolPointerSection());
505 }
507 // Use unified assembler syntax.
508 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
510 // Emit ARM Build Attributes
511 if (Subtarget->isTargetELF())
512 emitAttributes();
513 }
516 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
517 if (Subtarget->isTargetMachO()) {
518 // All darwin targets use mach-o.
519 const TargetLoweringObjectFileMachO &TLOFMacho =
520 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
521 MachineModuleInfoMachO &MMIMacho =
522 MMI->getObjFileInfo<MachineModuleInfoMachO>();
524 // Output non-lazy-pointers for external and common global variables.
525 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
527 if (!Stubs.empty()) {
528 // Switch with ".non_lazy_symbol_pointer" directive.
529 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
530 EmitAlignment(2);
531 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
532 // L_foo$stub:
533 OutStreamer.EmitLabel(Stubs[i].first);
534 // .indirect_symbol _foo
535 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
536 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
538 if (MCSym.getInt())
539 // External to current translation unit.
540 OutStreamer.EmitIntValue(0, 4/*size*/);
541 else
542 // Internal to current translation unit.
543 //
544 // When we place the LSDA into the TEXT section, the type info
545 // pointers need to be indirect and pc-rel. We accomplish this by
546 // using NLPs; however, sometimes the types are local to the file.
547 // We need to fill in the value for the NLP in those cases.
548 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
549 OutContext),
550 4/*size*/);
551 }
553 Stubs.clear();
554 OutStreamer.AddBlankLine();
555 }
557 Stubs = MMIMacho.GetHiddenGVStubList();
558 if (!Stubs.empty()) {
559 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
560 EmitAlignment(2);
561 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
562 // L_foo$stub:
563 OutStreamer.EmitLabel(Stubs[i].first);
564 // .long _foo
565 OutStreamer.EmitValue(MCSymbolRefExpr::
566 Create(Stubs[i].second.getPointer(),
567 OutContext),
568 4/*size*/);
569 }
571 Stubs.clear();
572 OutStreamer.AddBlankLine();
573 }
575 // Funny Darwin hack: This flag tells the linker that no global symbols
576 // contain code that falls through to other global symbols (e.g. the obvious
577 // implementation of multiple entry points). If this doesn't occur, the
578 // linker can safely perform dead code stripping. Since LLVM never
579 // generates code that does this, it is always safe to set.
580 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
581 }
582 }
584 //===----------------------------------------------------------------------===//
585 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
586 // FIXME:
587 // The following seem like one-off assembler flags, but they actually need
588 // to appear in the .ARM.attributes section in ELF.
589 // Instead of subclassing the MCELFStreamer, we do the work here.
591 static ARMBuildAttrs::CPUArch getArchForCPU(StringRef CPU,
592 const ARMSubtarget *Subtarget) {
593 if (CPU == "xscale")
594 return ARMBuildAttrs::v5TEJ;
596 if (Subtarget->hasV8Ops())
597 return ARMBuildAttrs::v8;
598 else if (Subtarget->hasV7Ops()) {
599 if (Subtarget->isMClass() && Subtarget->hasThumb2DSP())
600 return ARMBuildAttrs::v7E_M;
601 return ARMBuildAttrs::v7;
602 } else if (Subtarget->hasV6T2Ops())
603 return ARMBuildAttrs::v6T2;
604 else if (Subtarget->hasV6MOps())
605 return ARMBuildAttrs::v6S_M;
606 else if (Subtarget->hasV6Ops())
607 return ARMBuildAttrs::v6;
608 else if (Subtarget->hasV5TEOps())
609 return ARMBuildAttrs::v5TE;
610 else if (Subtarget->hasV5TOps())
611 return ARMBuildAttrs::v5T;
612 else if (Subtarget->hasV4TOps())
613 return ARMBuildAttrs::v4T;
614 else
615 return ARMBuildAttrs::v4;
616 }
618 void ARMAsmPrinter::emitAttributes() {
619 MCTargetStreamer &TS = *OutStreamer.getTargetStreamer();
620 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
622 ATS.switchVendor("aeabi");
624 std::string CPUString = Subtarget->getCPUString();
626 // FIXME: remove krait check when GNU tools support krait cpu
627 if (CPUString != "generic" && CPUString != "krait")
628 ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
630 ATS.emitAttribute(ARMBuildAttrs::CPU_arch,
631 getArchForCPU(CPUString, Subtarget));
633 // Tag_CPU_arch_profile must have the default value of 0 when "Architecture
634 // profile is not applicable (e.g. pre v7, or cross-profile code)".
635 if (Subtarget->hasV7Ops()) {
636 if (Subtarget->isAClass()) {
637 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
638 ARMBuildAttrs::ApplicationProfile);
639 } else if (Subtarget->isRClass()) {
640 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
641 ARMBuildAttrs::RealTimeProfile);
642 } else if (Subtarget->isMClass()) {
643 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
644 ARMBuildAttrs::MicroControllerProfile);
645 }
646 }
648 ATS.emitAttribute(ARMBuildAttrs::ARM_ISA_use, Subtarget->hasARMOps() ?
649 ARMBuildAttrs::Allowed : ARMBuildAttrs::Not_Allowed);
650 if (Subtarget->isThumb1Only()) {
651 ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
652 ARMBuildAttrs::Allowed);
653 } else if (Subtarget->hasThumb2()) {
654 ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
655 ARMBuildAttrs::AllowThumb32);
656 }
658 if (Subtarget->hasNEON()) {
659 /* NEON is not exactly a VFP architecture, but GAS emit one of
660 * neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
661 if (Subtarget->hasFPARMv8()) {
662 if (Subtarget->hasCrypto())
663 ATS.emitFPU(ARM::CRYPTO_NEON_FP_ARMV8);
664 else
665 ATS.emitFPU(ARM::NEON_FP_ARMV8);
666 }
667 else if (Subtarget->hasVFP4())
668 ATS.emitFPU(ARM::NEON_VFPV4);
669 else
670 ATS.emitFPU(ARM::NEON);
671 // Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
672 if (Subtarget->hasV8Ops())
673 ATS.emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
674 ARMBuildAttrs::AllowNeonARMv8);
675 } else {
676 if (Subtarget->hasFPARMv8())
677 ATS.emitFPU(ARM::FP_ARMV8);
678 else if (Subtarget->hasVFP4())
679 ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV4_D16 : ARM::VFPV4);
680 else if (Subtarget->hasVFP3())
681 ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV3_D16 : ARM::VFPV3);
682 else if (Subtarget->hasVFP2())
683 ATS.emitFPU(ARM::VFPV2);
684 }
686 // Signal various FP modes.
687 if (!TM.Options.UnsafeFPMath) {
688 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal, ARMBuildAttrs::Allowed);
689 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
690 ARMBuildAttrs::Allowed);
691 }
693 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
694 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
695 ARMBuildAttrs::Allowed);
696 else
697 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
698 ARMBuildAttrs::AllowIEE754);
700 // FIXME: add more flags to ARMBuildAttributes.h
701 // 8-bytes alignment stuff.
702 ATS.emitAttribute(ARMBuildAttrs::ABI_align_needed, 1);
703 ATS.emitAttribute(ARMBuildAttrs::ABI_align_preserved, 1);
705 // ABI_HardFP_use attribute to indicate single precision FP.
706 if (Subtarget->isFPOnlySP())
707 ATS.emitAttribute(ARMBuildAttrs::ABI_HardFP_use,
708 ARMBuildAttrs::HardFPSinglePrecision);
710 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
711 if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
712 ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, ARMBuildAttrs::HardFPAAPCS);
714 // FIXME: Should we signal R9 usage?
716 if (Subtarget->hasFP16())
717 ATS.emitAttribute(ARMBuildAttrs::FP_HP_extension, ARMBuildAttrs::AllowHPFP);
719 if (Subtarget->hasMPExtension())
720 ATS.emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP);
722 // Hardware divide in ARM mode is part of base arch, starting from ARMv8.
723 // If only Thumb hwdiv is present, it must also be in base arch (ARMv7-R/M).
724 // It is not possible to produce DisallowDIV: if hwdiv is present in the base
725 // arch, supplying -hwdiv downgrades the effective arch, via ClearImpliedBits.
726 // AllowDIVExt is only emitted if hwdiv isn't available in the base arch;
727 // otherwise, the default value (AllowDIVIfExists) applies.
728 if (Subtarget->hasDivideInARMMode() && !Subtarget->hasV8Ops())
729 ATS.emitAttribute(ARMBuildAttrs::DIV_use, ARMBuildAttrs::AllowDIVExt);
731 if (Subtarget->hasTrustZone() && Subtarget->hasVirtualization())
732 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
733 ARMBuildAttrs::AllowTZVirtualization);
734 else if (Subtarget->hasTrustZone())
735 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
736 ARMBuildAttrs::AllowTZ);
737 else if (Subtarget->hasVirtualization())
738 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
739 ARMBuildAttrs::AllowVirtualization);
741 ATS.finishAttributeSection();
742 }
744 void ARMAsmPrinter::emitARMAttributeSection() {
745 // <format-version>
746 // [ <section-length> "vendor-name"
747 // [ <file-tag> <size> <attribute>*
748 // | <section-tag> <size> <section-number>* 0 <attribute>*
749 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
750 // ]+
751 // ]*
753 if (OutStreamer.hasRawTextSupport())
754 return;
756 const ARMElfTargetObjectFile &TLOFELF =
757 static_cast<const ARMElfTargetObjectFile &>
758 (getObjFileLowering());
760 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
762 // Format version
763 OutStreamer.EmitIntValue(0x41, 1);
764 }
766 //===----------------------------------------------------------------------===//
768 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
769 unsigned LabelId, MCContext &Ctx) {
771 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
772 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
773 return Label;
774 }
776 static MCSymbolRefExpr::VariantKind
777 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
778 switch (Modifier) {
779 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
780 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_TLSGD;
781 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_TPOFF;
782 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_GOTTPOFF;
783 case ARMCP::GOT: return MCSymbolRefExpr::VK_GOT;
784 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_GOTOFF;
785 }
786 llvm_unreachable("Invalid ARMCPModifier!");
787 }
789 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
790 unsigned char TargetFlags) {
791 bool isIndirect = Subtarget->isTargetMachO() &&
792 (TargetFlags & ARMII::MO_NONLAZY) &&
793 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
794 if (!isIndirect)
795 return getSymbol(GV);
797 // FIXME: Remove this when Darwin transition to @GOT like syntax.
798 MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
799 MachineModuleInfoMachO &MMIMachO =
800 MMI->getObjFileInfo<MachineModuleInfoMachO>();
801 MachineModuleInfoImpl::StubValueTy &StubSym =
802 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
803 MMIMachO.getGVStubEntry(MCSym);
804 if (StubSym.getPointer() == 0)
805 StubSym = MachineModuleInfoImpl::
806 StubValueTy(getSymbol(GV), !GV->hasInternalLinkage());
807 return MCSym;
808 }
810 void ARMAsmPrinter::
811 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
812 const DataLayout *DL = TM.getDataLayout();
813 int Size = TM.getDataLayout()->getTypeAllocSize(MCPV->getType());
815 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
817 MCSymbol *MCSym;
818 if (ACPV->isLSDA()) {
819 SmallString<128> Str;
820 raw_svector_ostream OS(Str);
821 OS << DL->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
822 MCSym = OutContext.GetOrCreateSymbol(OS.str());
823 } else if (ACPV->isBlockAddress()) {
824 const BlockAddress *BA =
825 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
826 MCSym = GetBlockAddressSymbol(BA);
827 } else if (ACPV->isGlobalValue()) {
828 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
830 // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
831 // flag the global as MO_NONLAZY.
832 unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
833 MCSym = GetARMGVSymbol(GV, TF);
834 } else if (ACPV->isMachineBasicBlock()) {
835 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
836 MCSym = MBB->getSymbol();
837 } else {
838 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
839 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
840 MCSym = GetExternalSymbolSymbol(Sym);
841 }
843 // Create an MCSymbol for the reference.
844 const MCExpr *Expr =
845 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
846 OutContext);
848 if (ACPV->getPCAdjustment()) {
849 MCSymbol *PCLabel = getPICLabel(DL->getPrivateGlobalPrefix(),
850 getFunctionNumber(),
851 ACPV->getLabelId(),
852 OutContext);
853 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
854 PCRelExpr =
855 MCBinaryExpr::CreateAdd(PCRelExpr,
856 MCConstantExpr::Create(ACPV->getPCAdjustment(),
857 OutContext),
858 OutContext);
859 if (ACPV->mustAddCurrentAddress()) {
860 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
861 // label, so just emit a local label end reference that instead.
862 MCSymbol *DotSym = OutContext.CreateTempSymbol();
863 OutStreamer.EmitLabel(DotSym);
864 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
865 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
866 }
867 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
868 }
869 OutStreamer.EmitValue(Expr, Size);
870 }
872 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
873 unsigned Opcode = MI->getOpcode();
874 int OpNum = 1;
875 if (Opcode == ARM::BR_JTadd)
876 OpNum = 2;
877 else if (Opcode == ARM::BR_JTm)
878 OpNum = 3;
880 const MachineOperand &MO1 = MI->getOperand(OpNum);
881 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
882 unsigned JTI = MO1.getIndex();
884 // Emit a label for the jump table.
885 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
886 OutStreamer.EmitLabel(JTISymbol);
888 // Mark the jump table as data-in-code.
889 OutStreamer.EmitDataRegion(MCDR_DataRegionJT32);
891 // Emit each entry of the table.
892 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
893 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
894 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
896 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
897 MachineBasicBlock *MBB = JTBBs[i];
898 // Construct an MCExpr for the entry. We want a value of the form:
899 // (BasicBlockAddr - TableBeginAddr)
900 //
901 // For example, a table with entries jumping to basic blocks BB0 and BB1
902 // would look like:
903 // LJTI_0_0:
904 // .word (LBB0 - LJTI_0_0)
905 // .word (LBB1 - LJTI_0_0)
906 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
908 if (TM.getRelocationModel() == Reloc::PIC_)
909 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
910 OutContext),
911 OutContext);
912 // If we're generating a table of Thumb addresses in static relocation
913 // model, we need to add one to keep interworking correctly.
914 else if (AFI->isThumbFunction())
915 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
916 OutContext);
917 OutStreamer.EmitValue(Expr, 4);
918 }
919 // Mark the end of jump table data-in-code region.
920 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
921 }
923 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
924 unsigned Opcode = MI->getOpcode();
925 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
926 const MachineOperand &MO1 = MI->getOperand(OpNum);
927 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
928 unsigned JTI = MO1.getIndex();
930 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
931 OutStreamer.EmitLabel(JTISymbol);
933 // Emit each entry of the table.
934 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
935 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
936 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
937 unsigned OffsetWidth = 4;
938 if (MI->getOpcode() == ARM::t2TBB_JT) {
939 OffsetWidth = 1;
940 // Mark the jump table as data-in-code.
941 OutStreamer.EmitDataRegion(MCDR_DataRegionJT8);
942 } else if (MI->getOpcode() == ARM::t2TBH_JT) {
943 OffsetWidth = 2;
944 // Mark the jump table as data-in-code.
945 OutStreamer.EmitDataRegion(MCDR_DataRegionJT16);
946 }
948 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
949 MachineBasicBlock *MBB = JTBBs[i];
950 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
951 OutContext);
952 // If this isn't a TBB or TBH, the entries are direct branch instructions.
953 if (OffsetWidth == 4) {
954 OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2B)
955 .addExpr(MBBSymbolExpr)
956 .addImm(ARMCC::AL)
957 .addReg(0));
958 continue;
959 }
960 // Otherwise it's an offset from the dispatch instruction. Construct an
961 // MCExpr for the entry. We want a value of the form:
962 // (BasicBlockAddr - TableBeginAddr) / 2
963 //
964 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
965 // would look like:
966 // LJTI_0_0:
967 // .byte (LBB0 - LJTI_0_0) / 2
968 // .byte (LBB1 - LJTI_0_0) / 2
969 const MCExpr *Expr =
970 MCBinaryExpr::CreateSub(MBBSymbolExpr,
971 MCSymbolRefExpr::Create(JTISymbol, OutContext),
972 OutContext);
973 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
974 OutContext);
975 OutStreamer.EmitValue(Expr, OffsetWidth);
976 }
977 // Mark the end of jump table data-in-code region. 32-bit offsets use
978 // actual branch instructions here, so we don't mark those as a data-region
979 // at all.
980 if (OffsetWidth != 4)
981 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
982 }
984 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
985 assert(MI->getFlag(MachineInstr::FrameSetup) &&
986 "Only instruction which are involved into frame setup code are allowed");
988 MCTargetStreamer &TS = *OutStreamer.getTargetStreamer();
989 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
990 const MachineFunction &MF = *MI->getParent()->getParent();
991 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
992 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
994 unsigned FramePtr = RegInfo->getFrameRegister(MF);
995 unsigned Opc = MI->getOpcode();
996 unsigned SrcReg, DstReg;
998 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
999 // Two special cases:
1000 // 1) tPUSH does not have src/dst regs.
1001 // 2) for Thumb1 code we sometimes materialize the constant via constpool
1002 // load. Yes, this is pretty fragile, but for now I don't see better
1003 // way... :(
1004 SrcReg = DstReg = ARM::SP;
1005 } else {
1006 SrcReg = MI->getOperand(1).getReg();
1007 DstReg = MI->getOperand(0).getReg();
1008 }
1010 // Try to figure out the unwinding opcode out of src / dst regs.
1011 if (MI->mayStore()) {
1012 // Register saves.
1013 assert(DstReg == ARM::SP &&
1014 "Only stack pointer as a destination reg is supported");
1016 SmallVector<unsigned, 4> RegList;
1017 // Skip src & dst reg, and pred ops.
1018 unsigned StartOp = 2 + 2;
1019 // Use all the operands.
1020 unsigned NumOffset = 0;
1022 switch (Opc) {
1023 default:
1024 MI->dump();
1025 llvm_unreachable("Unsupported opcode for unwinding information");
1026 case ARM::tPUSH:
1027 // Special case here: no src & dst reg, but two extra imp ops.
1028 StartOp = 2; NumOffset = 2;
1029 case ARM::STMDB_UPD:
1030 case ARM::t2STMDB_UPD:
1031 case ARM::VSTMDDB_UPD:
1032 assert(SrcReg == ARM::SP &&
1033 "Only stack pointer as a source reg is supported");
1034 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1035 i != NumOps; ++i) {
1036 const MachineOperand &MO = MI->getOperand(i);
1037 // Actually, there should never be any impdef stuff here. Skip it
1038 // temporary to workaround PR11902.
1039 if (MO.isImplicit())
1040 continue;
1041 RegList.push_back(MO.getReg());
1042 }
1043 break;
1044 case ARM::STR_PRE_IMM:
1045 case ARM::STR_PRE_REG:
1046 case ARM::t2STR_PRE:
1047 assert(MI->getOperand(2).getReg() == ARM::SP &&
1048 "Only stack pointer as a source reg is supported");
1049 RegList.push_back(SrcReg);
1050 break;
1051 }
1052 ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1053 } else {
1054 // Changes of stack / frame pointer.
1055 if (SrcReg == ARM::SP) {
1056 int64_t Offset = 0;
1057 switch (Opc) {
1058 default:
1059 MI->dump();
1060 llvm_unreachable("Unsupported opcode for unwinding information");
1061 case ARM::MOVr:
1062 case ARM::tMOVr:
1063 Offset = 0;
1064 break;
1065 case ARM::ADDri:
1066 Offset = -MI->getOperand(2).getImm();
1067 break;
1068 case ARM::SUBri:
1069 case ARM::t2SUBri:
1070 Offset = MI->getOperand(2).getImm();
1071 break;
1072 case ARM::tSUBspi:
1073 Offset = MI->getOperand(2).getImm()*4;
1074 break;
1075 case ARM::tADDspi:
1076 case ARM::tADDrSPi:
1077 Offset = -MI->getOperand(2).getImm()*4;
1078 break;
1079 case ARM::tLDRpci: {
1080 // Grab the constpool index and check, whether it corresponds to
1081 // original or cloned constpool entry.
1082 unsigned CPI = MI->getOperand(1).getIndex();
1083 const MachineConstantPool *MCP = MF.getConstantPool();
1084 if (CPI >= MCP->getConstants().size())
1085 CPI = AFI.getOriginalCPIdx(CPI);
1086 assert(CPI != -1U && "Invalid constpool index");
1088 // Derive the actual offset.
1089 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1090 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1091 // FIXME: Check for user, it should be "add" instruction!
1092 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1093 break;
1094 }
1095 }
1097 if (DstReg == FramePtr && FramePtr != ARM::SP)
1098 // Set-up of the frame pointer. Positive values correspond to "add"
1099 // instruction.
1100 ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
1101 else if (DstReg == ARM::SP) {
1102 // Change of SP by an offset. Positive values correspond to "sub"
1103 // instruction.
1104 ATS.emitPad(Offset);
1105 } else {
1106 MI->dump();
1107 llvm_unreachable("Unsupported opcode for unwinding information");
1108 }
1109 } else if (DstReg == ARM::SP) {
1110 // FIXME: .movsp goes here
1111 MI->dump();
1112 llvm_unreachable("Unsupported opcode for unwinding information");
1113 }
1114 else {
1115 MI->dump();
1116 llvm_unreachable("Unsupported opcode for unwinding information");
1117 }
1118 }
1119 }
1121 extern cl::opt<bool> EnableARMEHABI;
1123 // Simple pseudo-instructions have their lowering (with expansion to real
1124 // instructions) auto-generated.
1125 #include "ARMGenMCPseudoLowering.inc"
1127 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1128 const DataLayout *DL = TM.getDataLayout();
1130 // If we just ended a constant pool, mark it as such.
1131 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1132 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1133 InConstantPool = false;
1134 }
1136 // Emit unwinding stuff for frame-related instructions
1137 if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup))
1138 EmitUnwindingInstruction(MI);
1140 // Do any auto-generated pseudo lowerings.
1141 if (emitPseudoExpansionLowering(OutStreamer, MI))
1142 return;
1144 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1145 "Pseudo flag setting opcode should be expanded early");
1147 // Check for manual lowerings.
1148 unsigned Opc = MI->getOpcode();
1149 switch (Opc) {
1150 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1151 case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
1152 case ARM::LEApcrel:
1153 case ARM::tLEApcrel:
1154 case ARM::t2LEApcrel: {
1155 // FIXME: Need to also handle globals and externals
1156 MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
1157 OutStreamer.EmitInstruction(MCInstBuilder(MI->getOpcode() ==
1158 ARM::t2LEApcrel ? ARM::t2ADR
1159 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1160 : ARM::ADR))
1161 .addReg(MI->getOperand(0).getReg())
1162 .addExpr(MCSymbolRefExpr::Create(CPISymbol, OutContext))
1163 // Add predicate operands.
1164 .addImm(MI->getOperand(2).getImm())
1165 .addReg(MI->getOperand(3).getReg()));
1166 return;
1167 }
1168 case ARM::LEApcrelJT:
1169 case ARM::tLEApcrelJT:
1170 case ARM::t2LEApcrelJT: {
1171 MCSymbol *JTIPICSymbol =
1172 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1173 MI->getOperand(2).getImm());
1174 OutStreamer.EmitInstruction(MCInstBuilder(MI->getOpcode() ==
1175 ARM::t2LEApcrelJT ? ARM::t2ADR
1176 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1177 : ARM::ADR))
1178 .addReg(MI->getOperand(0).getReg())
1179 .addExpr(MCSymbolRefExpr::Create(JTIPICSymbol, OutContext))
1180 // Add predicate operands.
1181 .addImm(MI->getOperand(3).getImm())
1182 .addReg(MI->getOperand(4).getReg()));
1183 return;
1184 }
1185 // Darwin call instructions are just normal call instructions with different
1186 // clobber semantics (they clobber R9).
1187 case ARM::BX_CALL: {
1188 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1189 .addReg(ARM::LR)
1190 .addReg(ARM::PC)
1191 // Add predicate operands.
1192 .addImm(ARMCC::AL)
1193 .addReg(0)
1194 // Add 's' bit operand (always reg0 for this)
1195 .addReg(0));
1197 OutStreamer.EmitInstruction(MCInstBuilder(ARM::BX)
1198 .addReg(MI->getOperand(0).getReg()));
1199 return;
1200 }
1201 case ARM::tBX_CALL: {
1202 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1203 .addReg(ARM::LR)
1204 .addReg(ARM::PC)
1205 // Add predicate operands.
1206 .addImm(ARMCC::AL)
1207 .addReg(0));
1209 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tBX)
1210 .addReg(MI->getOperand(0).getReg())
1211 // Add predicate operands.
1212 .addImm(ARMCC::AL)
1213 .addReg(0));
1214 return;
1215 }
1216 case ARM::BMOVPCRX_CALL: {
1217 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1218 .addReg(ARM::LR)
1219 .addReg(ARM::PC)
1220 // Add predicate operands.
1221 .addImm(ARMCC::AL)
1222 .addReg(0)
1223 // Add 's' bit operand (always reg0 for this)
1224 .addReg(0));
1226 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1227 .addReg(ARM::PC)
1228 .addReg(MI->getOperand(0).getReg())
1229 // Add predicate operands.
1230 .addImm(ARMCC::AL)
1231 .addReg(0)
1232 // Add 's' bit operand (always reg0 for this)
1233 .addReg(0));
1234 return;
1235 }
1236 case ARM::BMOVPCB_CALL: {
1237 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1238 .addReg(ARM::LR)
1239 .addReg(ARM::PC)
1240 // Add predicate operands.
1241 .addImm(ARMCC::AL)
1242 .addReg(0)
1243 // Add 's' bit operand (always reg0 for this)
1244 .addReg(0));
1246 const GlobalValue *GV = MI->getOperand(0).getGlobal();
1247 MCSymbol *GVSym = getSymbol(GV);
1248 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1249 OutStreamer.EmitInstruction(MCInstBuilder(ARM::Bcc)
1250 .addExpr(GVSymExpr)
1251 // Add predicate operands.
1252 .addImm(ARMCC::AL)
1253 .addReg(0));
1254 return;
1255 }
1256 case ARM::MOVi16_ga_pcrel:
1257 case ARM::t2MOVi16_ga_pcrel: {
1258 MCInst TmpInst;
1259 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1260 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1262 unsigned TF = MI->getOperand(1).getTargetFlags();
1263 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1264 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1265 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1267 MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
1268 getFunctionNumber(),
1269 MI->getOperand(2).getImm(), OutContext);
1270 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1271 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1272 const MCExpr *PCRelExpr =
1273 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1274 MCBinaryExpr::CreateAdd(LabelSymExpr,
1275 MCConstantExpr::Create(PCAdj, OutContext),
1276 OutContext), OutContext), OutContext);
1277 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1279 // Add predicate operands.
1280 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1281 TmpInst.addOperand(MCOperand::CreateReg(0));
1282 // Add 's' bit operand (always reg0 for this)
1283 TmpInst.addOperand(MCOperand::CreateReg(0));
1284 OutStreamer.EmitInstruction(TmpInst);
1285 return;
1286 }
1287 case ARM::MOVTi16_ga_pcrel:
1288 case ARM::t2MOVTi16_ga_pcrel: {
1289 MCInst TmpInst;
1290 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1291 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1292 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1293 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1295 unsigned TF = MI->getOperand(2).getTargetFlags();
1296 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1297 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1298 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1300 MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
1301 getFunctionNumber(),
1302 MI->getOperand(3).getImm(), OutContext);
1303 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1304 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1305 const MCExpr *PCRelExpr =
1306 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1307 MCBinaryExpr::CreateAdd(LabelSymExpr,
1308 MCConstantExpr::Create(PCAdj, OutContext),
1309 OutContext), OutContext), OutContext);
1310 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1311 // Add predicate operands.
1312 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1313 TmpInst.addOperand(MCOperand::CreateReg(0));
1314 // Add 's' bit operand (always reg0 for this)
1315 TmpInst.addOperand(MCOperand::CreateReg(0));
1316 OutStreamer.EmitInstruction(TmpInst);
1317 return;
1318 }
1319 case ARM::tPICADD: {
1320 // This is a pseudo op for a label + instruction sequence, which looks like:
1321 // LPC0:
1322 // add r0, pc
1323 // This adds the address of LPC0 to r0.
1325 // Emit the label.
1326 OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1327 getFunctionNumber(), MI->getOperand(2).getImm(),
1328 OutContext));
1330 // Form and emit the add.
1331 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tADDhirr)
1332 .addReg(MI->getOperand(0).getReg())
1333 .addReg(MI->getOperand(0).getReg())
1334 .addReg(ARM::PC)
1335 // Add predicate operands.
1336 .addImm(ARMCC::AL)
1337 .addReg(0));
1338 return;
1339 }
1340 case ARM::PICADD: {
1341 // This is a pseudo op for a label + instruction sequence, which looks like:
1342 // LPC0:
1343 // add r0, pc, r0
1344 // This adds the address of LPC0 to r0.
1346 // Emit the label.
1347 OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1348 getFunctionNumber(), MI->getOperand(2).getImm(),
1349 OutContext));
1351 // Form and emit the add.
1352 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDrr)
1353 .addReg(MI->getOperand(0).getReg())
1354 .addReg(ARM::PC)
1355 .addReg(MI->getOperand(1).getReg())
1356 // Add predicate operands.
1357 .addImm(MI->getOperand(3).getImm())
1358 .addReg(MI->getOperand(4).getReg())
1359 // Add 's' bit operand (always reg0 for this)
1360 .addReg(0));
1361 return;
1362 }
1363 case ARM::PICSTR:
1364 case ARM::PICSTRB:
1365 case ARM::PICSTRH:
1366 case ARM::PICLDR:
1367 case ARM::PICLDRB:
1368 case ARM::PICLDRH:
1369 case ARM::PICLDRSB:
1370 case ARM::PICLDRSH: {
1371 // This is a pseudo op for a label + instruction sequence, which looks like:
1372 // LPC0:
1373 // OP r0, [pc, r0]
1374 // The LCP0 label is referenced by a constant pool entry in order to get
1375 // a PC-relative address at the ldr instruction.
1377 // Emit the label.
1378 OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1379 getFunctionNumber(), MI->getOperand(2).getImm(),
1380 OutContext));
1382 // Form and emit the load
1383 unsigned Opcode;
1384 switch (MI->getOpcode()) {
1385 default:
1386 llvm_unreachable("Unexpected opcode!");
1387 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1388 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1389 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1390 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1391 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1392 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1393 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1394 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1395 }
1396 OutStreamer.EmitInstruction(MCInstBuilder(Opcode)
1397 .addReg(MI->getOperand(0).getReg())
1398 .addReg(ARM::PC)
1399 .addReg(MI->getOperand(1).getReg())
1400 .addImm(0)
1401 // Add predicate operands.
1402 .addImm(MI->getOperand(3).getImm())
1403 .addReg(MI->getOperand(4).getReg()));
1405 return;
1406 }
1407 case ARM::CONSTPOOL_ENTRY: {
1408 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1409 /// in the function. The first operand is the ID# for this instruction, the
1410 /// second is the index into the MachineConstantPool that this is, the third
1411 /// is the size in bytes of this constant pool entry.
1412 /// The required alignment is specified on the basic block holding this MI.
1413 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1414 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1416 // If this is the first entry of the pool, mark it.
1417 if (!InConstantPool) {
1418 OutStreamer.EmitDataRegion(MCDR_DataRegion);
1419 InConstantPool = true;
1420 }
1422 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1424 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1425 if (MCPE.isMachineConstantPoolEntry())
1426 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1427 else
1428 EmitGlobalConstant(MCPE.Val.ConstVal);
1429 return;
1430 }
1431 case ARM::t2BR_JT: {
1432 // Lower and emit the instruction itself, then the jump table following it.
1433 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1434 .addReg(ARM::PC)
1435 .addReg(MI->getOperand(0).getReg())
1436 // Add predicate operands.
1437 .addImm(ARMCC::AL)
1438 .addReg(0));
1440 // Output the data for the jump table itself
1441 EmitJump2Table(MI);
1442 return;
1443 }
1444 case ARM::t2TBB_JT: {
1445 // Lower and emit the instruction itself, then the jump table following it.
1446 OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2TBB)
1447 .addReg(ARM::PC)
1448 .addReg(MI->getOperand(0).getReg())
1449 // Add predicate operands.
1450 .addImm(ARMCC::AL)
1451 .addReg(0));
1453 // Output the data for the jump table itself
1454 EmitJump2Table(MI);
1455 // Make sure the next instruction is 2-byte aligned.
1456 EmitAlignment(1);
1457 return;
1458 }
1459 case ARM::t2TBH_JT: {
1460 // Lower and emit the instruction itself, then the jump table following it.
1461 OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2TBH)
1462 .addReg(ARM::PC)
1463 .addReg(MI->getOperand(0).getReg())
1464 // Add predicate operands.
1465 .addImm(ARMCC::AL)
1466 .addReg(0));
1468 // Output the data for the jump table itself
1469 EmitJump2Table(MI);
1470 return;
1471 }
1472 case ARM::tBR_JTr:
1473 case ARM::BR_JTr: {
1474 // Lower and emit the instruction itself, then the jump table following it.
1475 // mov pc, target
1476 MCInst TmpInst;
1477 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1478 ARM::MOVr : ARM::tMOVr;
1479 TmpInst.setOpcode(Opc);
1480 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1481 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1482 // Add predicate operands.
1483 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1484 TmpInst.addOperand(MCOperand::CreateReg(0));
1485 // Add 's' bit operand (always reg0 for this)
1486 if (Opc == ARM::MOVr)
1487 TmpInst.addOperand(MCOperand::CreateReg(0));
1488 OutStreamer.EmitInstruction(TmpInst);
1490 // Make sure the Thumb jump table is 4-byte aligned.
1491 if (Opc == ARM::tMOVr)
1492 EmitAlignment(2);
1494 // Output the data for the jump table itself
1495 EmitJumpTable(MI);
1496 return;
1497 }
1498 case ARM::BR_JTm: {
1499 // Lower and emit the instruction itself, then the jump table following it.
1500 // ldr pc, target
1501 MCInst TmpInst;
1502 if (MI->getOperand(1).getReg() == 0) {
1503 // literal offset
1504 TmpInst.setOpcode(ARM::LDRi12);
1505 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1506 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1507 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1508 } else {
1509 TmpInst.setOpcode(ARM::LDRrs);
1510 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1511 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1512 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1513 TmpInst.addOperand(MCOperand::CreateImm(0));
1514 }
1515 // Add predicate operands.
1516 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1517 TmpInst.addOperand(MCOperand::CreateReg(0));
1518 OutStreamer.EmitInstruction(TmpInst);
1520 // Output the data for the jump table itself
1521 EmitJumpTable(MI);
1522 return;
1523 }
1524 case ARM::BR_JTadd: {
1525 // Lower and emit the instruction itself, then the jump table following it.
1526 // add pc, target, idx
1527 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDrr)
1528 .addReg(ARM::PC)
1529 .addReg(MI->getOperand(0).getReg())
1530 .addReg(MI->getOperand(1).getReg())
1531 // Add predicate operands.
1532 .addImm(ARMCC::AL)
1533 .addReg(0)
1534 // Add 's' bit operand (always reg0 for this)
1535 .addReg(0));
1537 // Output the data for the jump table itself
1538 EmitJumpTable(MI);
1539 return;
1540 }
1541 case ARM::TRAP: {
1542 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1543 // FIXME: Remove this special case when they do.
1544 if (!Subtarget->isTargetMachO()) {
1545 //.long 0xe7ffdefe @ trap
1546 uint32_t Val = 0xe7ffdefeUL;
1547 OutStreamer.AddComment("trap");
1548 OutStreamer.EmitIntValue(Val, 4);
1549 return;
1550 }
1551 break;
1552 }
1553 case ARM::TRAPNaCl: {
1554 //.long 0xe7fedef0 @ trap
1555 uint32_t Val = 0xe7fedef0UL;
1556 OutStreamer.AddComment("trap");
1557 OutStreamer.EmitIntValue(Val, 4);
1558 return;
1559 }
1560 case ARM::tTRAP: {
1561 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1562 // FIXME: Remove this special case when they do.
1563 if (!Subtarget->isTargetMachO()) {
1564 //.short 57086 @ trap
1565 uint16_t Val = 0xdefe;
1566 OutStreamer.AddComment("trap");
1567 OutStreamer.EmitIntValue(Val, 2);
1568 return;
1569 }
1570 break;
1571 }
1572 case ARM::t2Int_eh_sjlj_setjmp:
1573 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1574 case ARM::tInt_eh_sjlj_setjmp: {
1575 // Two incoming args: GPR:$src, GPR:$val
1576 // mov $val, pc
1577 // adds $val, #7
1578 // str $val, [$src, #4]
1579 // movs r0, #0
1580 // b 1f
1581 // movs r0, #1
1582 // 1:
1583 unsigned SrcReg = MI->getOperand(0).getReg();
1584 unsigned ValReg = MI->getOperand(1).getReg();
1585 MCSymbol *Label = GetARMSJLJEHLabel();
1586 OutStreamer.AddComment("eh_setjmp begin");
1587 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1588 .addReg(ValReg)
1589 .addReg(ARM::PC)
1590 // Predicate.
1591 .addImm(ARMCC::AL)
1592 .addReg(0));
1594 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tADDi3)
1595 .addReg(ValReg)
1596 // 's' bit operand
1597 .addReg(ARM::CPSR)
1598 .addReg(ValReg)
1599 .addImm(7)
1600 // Predicate.
1601 .addImm(ARMCC::AL)
1602 .addReg(0));
1604 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tSTRi)
1605 .addReg(ValReg)
1606 .addReg(SrcReg)
1607 // The offset immediate is #4. The operand value is scaled by 4 for the
1608 // tSTR instruction.
1609 .addImm(1)
1610 // Predicate.
1611 .addImm(ARMCC::AL)
1612 .addReg(0));
1614 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVi8)
1615 .addReg(ARM::R0)
1616 .addReg(ARM::CPSR)
1617 .addImm(0)
1618 // Predicate.
1619 .addImm(ARMCC::AL)
1620 .addReg(0));
1622 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1623 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tB)
1624 .addExpr(SymbolExpr)
1625 .addImm(ARMCC::AL)
1626 .addReg(0));
1628 OutStreamer.AddComment("eh_setjmp end");
1629 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVi8)
1630 .addReg(ARM::R0)
1631 .addReg(ARM::CPSR)
1632 .addImm(1)
1633 // Predicate.
1634 .addImm(ARMCC::AL)
1635 .addReg(0));
1637 OutStreamer.EmitLabel(Label);
1638 return;
1639 }
1641 case ARM::Int_eh_sjlj_setjmp_nofp:
1642 case ARM::Int_eh_sjlj_setjmp: {
1643 // Two incoming args: GPR:$src, GPR:$val
1644 // add $val, pc, #8
1645 // str $val, [$src, #+4]
1646 // mov r0, #0
1647 // add pc, pc, #0
1648 // mov r0, #1
1649 unsigned SrcReg = MI->getOperand(0).getReg();
1650 unsigned ValReg = MI->getOperand(1).getReg();
1652 OutStreamer.AddComment("eh_setjmp begin");
1653 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDri)
1654 .addReg(ValReg)
1655 .addReg(ARM::PC)
1656 .addImm(8)
1657 // Predicate.
1658 .addImm(ARMCC::AL)
1659 .addReg(0)
1660 // 's' bit operand (always reg0 for this).
1661 .addReg(0));
1663 OutStreamer.EmitInstruction(MCInstBuilder(ARM::STRi12)
1664 .addReg(ValReg)
1665 .addReg(SrcReg)
1666 .addImm(4)
1667 // Predicate.
1668 .addImm(ARMCC::AL)
1669 .addReg(0));
1671 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVi)
1672 .addReg(ARM::R0)
1673 .addImm(0)
1674 // Predicate.
1675 .addImm(ARMCC::AL)
1676 .addReg(0)
1677 // 's' bit operand (always reg0 for this).
1678 .addReg(0));
1680 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDri)
1681 .addReg(ARM::PC)
1682 .addReg(ARM::PC)
1683 .addImm(0)
1684 // Predicate.
1685 .addImm(ARMCC::AL)
1686 .addReg(0)
1687 // 's' bit operand (always reg0 for this).
1688 .addReg(0));
1690 OutStreamer.AddComment("eh_setjmp end");
1691 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVi)
1692 .addReg(ARM::R0)
1693 .addImm(1)
1694 // Predicate.
1695 .addImm(ARMCC::AL)
1696 .addReg(0)
1697 // 's' bit operand (always reg0 for this).
1698 .addReg(0));
1699 return;
1700 }
1701 case ARM::Int_eh_sjlj_longjmp: {
1702 // ldr sp, [$src, #8]
1703 // ldr $scratch, [$src, #4]
1704 // ldr r7, [$src]
1705 // bx $scratch
1706 unsigned SrcReg = MI->getOperand(0).getReg();
1707 unsigned ScratchReg = MI->getOperand(1).getReg();
1708 OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
1709 .addReg(ARM::SP)
1710 .addReg(SrcReg)
1711 .addImm(8)
1712 // Predicate.
1713 .addImm(ARMCC::AL)
1714 .addReg(0));
1716 OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
1717 .addReg(ScratchReg)
1718 .addReg(SrcReg)
1719 .addImm(4)
1720 // Predicate.
1721 .addImm(ARMCC::AL)
1722 .addReg(0));
1724 OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
1725 .addReg(ARM::R7)
1726 .addReg(SrcReg)
1727 .addImm(0)
1728 // Predicate.
1729 .addImm(ARMCC::AL)
1730 .addReg(0));
1732 OutStreamer.EmitInstruction(MCInstBuilder(ARM::BX)
1733 .addReg(ScratchReg)
1734 // Predicate.
1735 .addImm(ARMCC::AL)
1736 .addReg(0));
1737 return;
1738 }
1739 case ARM::tInt_eh_sjlj_longjmp: {
1740 // ldr $scratch, [$src, #8]
1741 // mov sp, $scratch
1742 // ldr $scratch, [$src, #4]
1743 // ldr r7, [$src]
1744 // bx $scratch
1745 unsigned SrcReg = MI->getOperand(0).getReg();
1746 unsigned ScratchReg = MI->getOperand(1).getReg();
1747 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
1748 .addReg(ScratchReg)
1749 .addReg(SrcReg)
1750 // The offset immediate is #8. The operand value is scaled by 4 for the
1751 // tLDR instruction.
1752 .addImm(2)
1753 // Predicate.
1754 .addImm(ARMCC::AL)
1755 .addReg(0));
1757 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1758 .addReg(ARM::SP)
1759 .addReg(ScratchReg)
1760 // Predicate.
1761 .addImm(ARMCC::AL)
1762 .addReg(0));
1764 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
1765 .addReg(ScratchReg)
1766 .addReg(SrcReg)
1767 .addImm(1)
1768 // Predicate.
1769 .addImm(ARMCC::AL)
1770 .addReg(0));
1772 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
1773 .addReg(ARM::R7)
1774 .addReg(SrcReg)
1775 .addImm(0)
1776 // Predicate.
1777 .addImm(ARMCC::AL)
1778 .addReg(0));
1780 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tBX)
1781 .addReg(ScratchReg)
1782 // Predicate.
1783 .addImm(ARMCC::AL)
1784 .addReg(0));
1785 return;
1786 }
1787 }
1789 MCInst TmpInst;
1790 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1792 OutStreamer.EmitInstruction(TmpInst);
1793 }
1795 //===----------------------------------------------------------------------===//
1796 // Target Registry Stuff
1797 //===----------------------------------------------------------------------===//
1799 // Force static initialization.
1800 extern "C" void LLVMInitializeARMAsmPrinter() {
1801 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1802 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1803 }