1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
12 //
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
16 #include "ARM.h"
17 #include "ARMAsmPrinter.h"
18 #include "ARMBuildAttrs.h"
19 #include "ARMBaseRegisterInfo.h"
20 #include "ARMConstantPoolValue.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMTargetMachine.h"
23 #include "ARMTargetObjectFile.h"
24 #include "InstPrinter/ARMInstPrinter.h"
25 #include "MCTargetDesc/ARMAddressingModes.h"
26 #include "MCTargetDesc/ARMMCExpr.h"
27 #include "llvm/Analysis/DebugInfo.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Module.h"
30 #include "llvm/Type.h"
31 #include "llvm/Assembly/Writer.h"
32 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
33 #include "llvm/CodeGen/MachineFunctionPass.h"
34 #include "llvm/CodeGen/MachineJumpTableInfo.h"
35 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/MC/MCAssembler.h"
37 #include "llvm/MC/MCContext.h"
38 #include "llvm/MC/MCExpr.h"
39 #include "llvm/MC/MCInst.h"
40 #include "llvm/MC/MCSectionMachO.h"
41 #include "llvm/MC/MCObjectStreamer.h"
42 #include "llvm/MC/MCStreamer.h"
43 #include "llvm/MC/MCSymbol.h"
44 #include "llvm/Target/Mangler.h"
45 #include "llvm/Target/TargetData.h"
46 #include "llvm/Target/TargetMachine.h"
47 #include "llvm/Target/TargetOptions.h"
48 #include "llvm/ADT/SmallPtrSet.h"
49 #include "llvm/ADT/SmallString.h"
50 #include "llvm/Support/CommandLine.h"
51 #include "llvm/Support/Debug.h"
52 #include "llvm/Support/ErrorHandling.h"
53 #include "llvm/Support/TargetRegistry.h"
54 #include "llvm/Support/raw_ostream.h"
55 #include <cctype>
56 using namespace llvm;
58 namespace {
60 // Per section and per symbol attributes are not supported.
61 // To implement them we would need the ability to delay this emission
62 // until the assembly file is fully parsed/generated as only then do we
63 // know the symbol and section numbers.
64 class AttributeEmitter {
65 public:
66 virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
67 virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
68 virtual void EmitTextAttribute(unsigned Attribute, StringRef String) = 0;
69 virtual void Finish() = 0;
70 virtual ~AttributeEmitter() {}
71 };
73 class AsmAttributeEmitter : public AttributeEmitter {
74 MCStreamer &Streamer;
76 public:
77 AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
78 void MaybeSwitchVendor(StringRef Vendor) { }
80 void EmitAttribute(unsigned Attribute, unsigned Value) {
81 Streamer.EmitRawText("\t.eabi_attribute " +
82 Twine(Attribute) + ", " + Twine(Value));
83 }
85 void EmitTextAttribute(unsigned Attribute, StringRef String) {
86 switch (Attribute) {
87 case ARMBuildAttrs::CPU_name:
88 Streamer.EmitRawText(StringRef("\t.cpu ") + String.lower());
89 break;
90 /* GAS requires .fpu to be emitted regardless of EABI attribute */
91 case ARMBuildAttrs::Advanced_SIMD_arch:
92 case ARMBuildAttrs::VFP_arch:
93 Streamer.EmitRawText(StringRef("\t.fpu ") + String.lower());
94 break;
95 default: assert(0 && "Unsupported Text attribute in ASM Mode"); break;
96 }
97 }
98 void Finish() { }
99 };
101 class ObjectAttributeEmitter : public AttributeEmitter {
102 // This structure holds all attributes, accounting for
103 // their string/numeric value, so we can later emmit them
104 // in declaration order, keeping all in the same vector
105 struct AttributeItemType {
106 enum {
107 HiddenAttribute = 0,
108 NumericAttribute,
109 TextAttribute
110 } Type;
111 unsigned Tag;
112 unsigned IntValue;
113 StringRef StringValue;
114 } AttributeItem;
116 MCObjectStreamer &Streamer;
117 StringRef CurrentVendor;
118 SmallVector<AttributeItemType, 64> Contents;
120 // Account for the ULEB/String size of each item,
121 // not just the number of items
122 size_t ContentsSize;
123 // FIXME: this should be in a more generic place, but
124 // getULEBSize() is in MCAsmInfo and will be moved to MCDwarf
125 size_t getULEBSize(int Value) {
126 size_t Size = 0;
127 do {
128 Value >>= 7;
129 Size += sizeof(int8_t); // Is this really necessary?
130 } while (Value);
131 return Size;
132 }
134 public:
135 ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
136 Streamer(Streamer_), CurrentVendor(""), ContentsSize(0) { }
138 void MaybeSwitchVendor(StringRef Vendor) {
139 assert(!Vendor.empty() && "Vendor cannot be empty.");
141 if (CurrentVendor.empty())
142 CurrentVendor = Vendor;
143 else if (CurrentVendor == Vendor)
144 return;
145 else
146 Finish();
148 CurrentVendor = Vendor;
150 assert(Contents.size() == 0);
151 }
153 void EmitAttribute(unsigned Attribute, unsigned Value) {
154 AttributeItemType attr = {
155 AttributeItemType::NumericAttribute,
156 Attribute,
157 Value,
158 StringRef("")
159 };
160 ContentsSize += getULEBSize(Attribute);
161 ContentsSize += getULEBSize(Value);
162 Contents.push_back(attr);
163 }
165 void EmitTextAttribute(unsigned Attribute, StringRef String) {
166 AttributeItemType attr = {
167 AttributeItemType::TextAttribute,
168 Attribute,
169 0,
170 String
171 };
172 ContentsSize += getULEBSize(Attribute);
173 // String + \0
174 ContentsSize += String.size()+1;
176 Contents.push_back(attr);
177 }
179 void Finish() {
180 // Vendor size + Vendor name + '\0'
181 const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1;
183 // Tag + Tag Size
184 const size_t TagHeaderSize = 1 + 4;
186 Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4);
187 Streamer.EmitBytes(CurrentVendor, 0);
188 Streamer.EmitIntValue(0, 1); // '\0'
190 Streamer.EmitIntValue(ARMBuildAttrs::File, 1);
191 Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4);
193 // Size should have been accounted for already, now
194 // emit each field as its type (ULEB or String)
195 for (unsigned int i=0; i<Contents.size(); ++i) {
196 AttributeItemType item = Contents[i];
197 Streamer.EmitULEB128IntValue(item.Tag, 0);
198 switch (item.Type) {
199 case AttributeItemType::NumericAttribute:
200 Streamer.EmitULEB128IntValue(item.IntValue, 0);
201 break;
202 case AttributeItemType::TextAttribute:
203 Streamer.EmitBytes(item.StringValue.upper(), 0);
204 Streamer.EmitIntValue(0, 1); // '\0'
205 break;
206 default:
207 assert(0 && "Invalid attribute type");
208 }
209 }
211 Contents.clear();
212 }
213 };
215 } // end of anonymous namespace
217 MachineLocation ARMAsmPrinter::
218 getDebugValueLocation(const MachineInstr *MI) const {
219 MachineLocation Location;
220 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
221 // Frame address. Currently handles register +- offset only.
222 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
223 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
224 else {
225 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
226 }
227 return Location;
228 }
230 /// EmitDwarfRegOp - Emit dwarf register operation.
231 void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
232 const TargetRegisterInfo *RI = TM.getRegisterInfo();
233 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1)
234 AsmPrinter::EmitDwarfRegOp(MLoc);
235 else {
236 unsigned Reg = MLoc.getReg();
237 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
238 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
239 // S registers are described as bit-pieces of a register
240 // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
241 // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
243 unsigned SReg = Reg - ARM::S0;
244 bool odd = SReg & 0x1;
245 unsigned Rx = 256 + (SReg >> 1);
247 OutStreamer.AddComment("DW_OP_regx for S register");
248 EmitInt8(dwarf::DW_OP_regx);
250 OutStreamer.AddComment(Twine(SReg));
251 EmitULEB128(Rx);
253 if (odd) {
254 OutStreamer.AddComment("DW_OP_bit_piece 32 32");
255 EmitInt8(dwarf::DW_OP_bit_piece);
256 EmitULEB128(32);
257 EmitULEB128(32);
258 } else {
259 OutStreamer.AddComment("DW_OP_bit_piece 32 0");
260 EmitInt8(dwarf::DW_OP_bit_piece);
261 EmitULEB128(32);
262 EmitULEB128(0);
263 }
264 } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
265 assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
266 // Q registers Q0-Q15 are described by composing two D registers together.
267 // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1)
268 // DW_OP_piece(8)
270 unsigned QReg = Reg - ARM::Q0;
271 unsigned D1 = 256 + 2 * QReg;
272 unsigned D2 = D1 + 1;
274 OutStreamer.AddComment("DW_OP_regx for Q register: D1");
275 EmitInt8(dwarf::DW_OP_regx);
276 EmitULEB128(D1);
277 OutStreamer.AddComment("DW_OP_piece 8");
278 EmitInt8(dwarf::DW_OP_piece);
279 EmitULEB128(8);
281 OutStreamer.AddComment("DW_OP_regx for Q register: D2");
282 EmitInt8(dwarf::DW_OP_regx);
283 EmitULEB128(D2);
284 OutStreamer.AddComment("DW_OP_piece 8");
285 EmitInt8(dwarf::DW_OP_piece);
286 EmitULEB128(8);
287 }
288 }
289 }
291 void ARMAsmPrinter::EmitFunctionEntryLabel() {
292 OutStreamer.ForceCodeRegion();
294 if (AFI->isThumbFunction()) {
295 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
296 OutStreamer.EmitThumbFunc(CurrentFnSym);
297 }
299 OutStreamer.EmitLabel(CurrentFnSym);
300 }
302 /// runOnMachineFunction - This uses the EmitInstruction()
303 /// method to print assembly for each instruction.
304 ///
305 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
306 AFI = MF.getInfo<ARMFunctionInfo>();
307 MCP = MF.getConstantPool();
309 return AsmPrinter::runOnMachineFunction(MF);
310 }
312 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
313 raw_ostream &O, const char *Modifier) {
314 const MachineOperand &MO = MI->getOperand(OpNum);
315 unsigned TF = MO.getTargetFlags();
317 switch (MO.getType()) {
318 default:
319 assert(0 && "<unknown operand type>");
320 case MachineOperand::MO_Register: {
321 unsigned Reg = MO.getReg();
322 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
323 assert(!MO.getSubReg() && "Subregs should be eliminated!");
324 O << ARMInstPrinter::getRegisterName(Reg);
325 break;
326 }
327 case MachineOperand::MO_Immediate: {
328 int64_t Imm = MO.getImm();
329 O << '#';
330 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
331 (TF == ARMII::MO_LO16))
332 O << ":lower16:";
333 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
334 (TF == ARMII::MO_HI16))
335 O << ":upper16:";
336 O << Imm;
337 break;
338 }
339 case MachineOperand::MO_MachineBasicBlock:
340 O << *MO.getMBB()->getSymbol();
341 return;
342 case MachineOperand::MO_GlobalAddress: {
343 const GlobalValue *GV = MO.getGlobal();
344 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
345 (TF & ARMII::MO_LO16))
346 O << ":lower16:";
347 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
348 (TF & ARMII::MO_HI16))
349 O << ":upper16:";
350 O << *Mang->getSymbol(GV);
352 printOffset(MO.getOffset(), O);
353 if (TF == ARMII::MO_PLT)
354 O << "(PLT)";
355 break;
356 }
357 case MachineOperand::MO_ExternalSymbol: {
358 O << *GetExternalSymbolSymbol(MO.getSymbolName());
359 if (TF == ARMII::MO_PLT)
360 O << "(PLT)";
361 break;
362 }
363 case MachineOperand::MO_ConstantPoolIndex:
364 O << *GetCPISymbol(MO.getIndex());
365 break;
366 case MachineOperand::MO_JumpTableIndex:
367 O << *GetJTISymbol(MO.getIndex());
368 break;
369 }
370 }
372 //===--------------------------------------------------------------------===//
374 MCSymbol *ARMAsmPrinter::
375 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
376 const MachineBasicBlock *MBB) const {
377 SmallString<60> Name;
378 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
379 << getFunctionNumber() << '_' << uid << '_' << uid2
380 << "_set_" << MBB->getNumber();
381 return OutContext.GetOrCreateSymbol(Name.str());
382 }
384 MCSymbol *ARMAsmPrinter::
385 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
386 SmallString<60> Name;
387 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
388 << getFunctionNumber() << '_' << uid << '_' << uid2;
389 return OutContext.GetOrCreateSymbol(Name.str());
390 }
393 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const {
394 SmallString<60> Name;
395 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
396 << getFunctionNumber();
397 return OutContext.GetOrCreateSymbol(Name.str());
398 }
400 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
401 unsigned AsmVariant, const char *ExtraCode,
402 raw_ostream &O) {
403 // Does this asm operand have a single letter operand modifier?
404 if (ExtraCode && ExtraCode[0]) {
405 if (ExtraCode[1] != 0) return true; // Unknown modifier.
407 switch (ExtraCode[0]) {
408 default: return true; // Unknown modifier.
409 case 'a': // Print as a memory address.
410 if (MI->getOperand(OpNum).isReg()) {
411 O << "["
412 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
413 << "]";
414 return false;
415 }
416 // Fallthrough
417 case 'c': // Don't print "#" before an immediate operand.
418 if (!MI->getOperand(OpNum).isImm())
419 return true;
420 O << MI->getOperand(OpNum).getImm();
421 return false;
422 case 'P': // Print a VFP double precision register.
423 case 'q': // Print a NEON quad precision register.
424 printOperand(MI, OpNum, O);
425 return false;
426 case 'y': // Print a VFP single precision register as indexed double.
427 // This uses the ordering of the alias table to get the first 'd' register
428 // that overlaps the 's' register. Also, s0 is an odd register, hence the
429 // odd modulus check below.
430 if (MI->getOperand(OpNum).isReg()) {
431 unsigned Reg = MI->getOperand(OpNum).getReg();
432 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
433 O << ARMInstPrinter::getRegisterName(TRI->getAliasSet(Reg)[0]) <<
434 (((Reg % 2) == 1) ? "[0]" : "[1]");
435 return false;
436 }
437 return true;
438 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
439 if (!MI->getOperand(OpNum).isImm())
440 return true;
441 O << ~(MI->getOperand(OpNum).getImm());
442 return false;
443 case 'L': // The low 16 bits of an immediate constant.
444 if (!MI->getOperand(OpNum).isImm())
445 return true;
446 O << (MI->getOperand(OpNum).getImm() & 0xffff);
447 return false;
448 case 'M': { // A register range suitable for LDM/STM.
449 if (!MI->getOperand(OpNum).isReg())
450 return true;
451 const MachineOperand &MO = MI->getOperand(OpNum);
452 unsigned RegBegin = MO.getReg();
453 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
454 // already got the operands in registers that are operands to the
455 // inline asm statement.
457 O << "{" << ARMInstPrinter::getRegisterName(RegBegin);
459 // FIXME: The register allocator not only may not have given us the
460 // registers in sequence, but may not be in ascending registers. This
461 // will require changes in the register allocator that'll need to be
462 // propagated down here if the operands change.
463 unsigned RegOps = OpNum + 1;
464 while (MI->getOperand(RegOps).isReg()) {
465 O << ", "
466 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
467 RegOps++;
468 }
470 O << "}";
472 return false;
473 }
474 case 'R': // The most significant register of a pair.
475 case 'Q': { // The least significant register of a pair.
476 if (OpNum == 0)
477 return true;
478 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
479 if (!FlagsOP.isImm())
480 return true;
481 unsigned Flags = FlagsOP.getImm();
482 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
483 if (NumVals != 2)
484 return true;
485 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
486 if (RegOp >= MI->getNumOperands())
487 return true;
488 const MachineOperand &MO = MI->getOperand(RegOp);
489 if (!MO.isReg())
490 return true;
491 unsigned Reg = MO.getReg();
492 O << ARMInstPrinter::getRegisterName(Reg);
493 return false;
494 }
496 case 'e': // The low doubleword register of a NEON quad register.
497 case 'f': { // The high doubleword register of a NEON quad register.
498 if (!MI->getOperand(OpNum).isReg())
499 return true;
500 unsigned Reg = MI->getOperand(OpNum).getReg();
501 if (!ARM::QPRRegClass.contains(Reg))
502 return true;
503 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
504 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
505 ARM::dsub_0 : ARM::dsub_1);
506 O << ARMInstPrinter::getRegisterName(SubReg);
507 return false;
508 }
510 // These modifiers are not yet supported.
511 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
512 case 'H': // The highest-numbered register of a pair.
513 return true;
514 }
515 }
517 printOperand(MI, OpNum, O);
518 return false;
519 }
521 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
522 unsigned OpNum, unsigned AsmVariant,
523 const char *ExtraCode,
524 raw_ostream &O) {
525 // Does this asm operand have a single letter operand modifier?
526 if (ExtraCode && ExtraCode[0]) {
527 if (ExtraCode[1] != 0) return true; // Unknown modifier.
529 switch (ExtraCode[0]) {
530 case 'A': // A memory operand for a VLD1/VST1 instruction.
531 default: return true; // Unknown modifier.
532 case 'm': // The base register of a memory operand.
533 if (!MI->getOperand(OpNum).isReg())
534 return true;
535 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
536 return false;
537 }
538 }
540 const MachineOperand &MO = MI->getOperand(OpNum);
541 assert(MO.isReg() && "unexpected inline asm memory operand");
542 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
543 return false;
544 }
546 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
547 if (Subtarget->isTargetDarwin()) {
548 Reloc::Model RelocM = TM.getRelocationModel();
549 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
550 // Declare all the text sections up front (before the DWARF sections
551 // emitted by AsmPrinter::doInitialization) so the assembler will keep
552 // them together at the beginning of the object file. This helps
553 // avoid out-of-range branches that are due a fundamental limitation of
554 // the way symbol offsets are encoded with the current Darwin ARM
555 // relocations.
556 const TargetLoweringObjectFileMachO &TLOFMacho =
557 static_cast<const TargetLoweringObjectFileMachO &>(
558 getObjFileLowering());
559 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
560 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
561 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
562 if (RelocM == Reloc::DynamicNoPIC) {
563 const MCSection *sect =
564 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
565 MCSectionMachO::S_SYMBOL_STUBS,
566 12, SectionKind::getText());
567 OutStreamer.SwitchSection(sect);
568 } else {
569 const MCSection *sect =
570 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
571 MCSectionMachO::S_SYMBOL_STUBS,
572 16, SectionKind::getText());
573 OutStreamer.SwitchSection(sect);
574 }
575 const MCSection *StaticInitSect =
576 OutContext.getMachOSection("__TEXT", "__StaticInit",
577 MCSectionMachO::S_REGULAR |
578 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
579 SectionKind::getText());
580 OutStreamer.SwitchSection(StaticInitSect);
581 }
582 }
584 // Use unified assembler syntax.
585 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
587 // Emit ARM Build Attributes
588 if (Subtarget->isTargetELF()) {
590 emitAttributes();
591 }
592 }
595 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
596 if (Subtarget->isTargetDarwin()) {
597 // All darwin targets use mach-o.
598 const TargetLoweringObjectFileMachO &TLOFMacho =
599 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
600 MachineModuleInfoMachO &MMIMacho =
601 MMI->getObjFileInfo<MachineModuleInfoMachO>();
603 // Output non-lazy-pointers for external and common global variables.
604 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
606 if (!Stubs.empty()) {
607 // Switch with ".non_lazy_symbol_pointer" directive.
608 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
609 EmitAlignment(2);
610 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
611 // L_foo$stub:
612 OutStreamer.EmitLabel(Stubs[i].first);
613 // .indirect_symbol _foo
614 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
615 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
617 if (MCSym.getInt())
618 // External to current translation unit.
619 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
620 else
621 // Internal to current translation unit.
622 //
623 // When we place the LSDA into the TEXT section, the type info
624 // pointers need to be indirect and pc-rel. We accomplish this by
625 // using NLPs; however, sometimes the types are local to the file.
626 // We need to fill in the value for the NLP in those cases.
627 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
628 OutContext),
629 4/*size*/, 0/*addrspace*/);
630 }
632 Stubs.clear();
633 OutStreamer.AddBlankLine();
634 }
636 Stubs = MMIMacho.GetHiddenGVStubList();
637 if (!Stubs.empty()) {
638 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
639 EmitAlignment(2);
640 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
641 // L_foo$stub:
642 OutStreamer.EmitLabel(Stubs[i].first);
643 // .long _foo
644 OutStreamer.EmitValue(MCSymbolRefExpr::
645 Create(Stubs[i].second.getPointer(),
646 OutContext),
647 4/*size*/, 0/*addrspace*/);
648 }
650 Stubs.clear();
651 OutStreamer.AddBlankLine();
652 }
654 // Funny Darwin hack: This flag tells the linker that no global symbols
655 // contain code that falls through to other global symbols (e.g. the obvious
656 // implementation of multiple entry points). If this doesn't occur, the
657 // linker can safely perform dead code stripping. Since LLVM never
658 // generates code that does this, it is always safe to set.
659 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
660 }
661 }
663 //===----------------------------------------------------------------------===//
664 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
665 // FIXME:
666 // The following seem like one-off assembler flags, but they actually need
667 // to appear in the .ARM.attributes section in ELF.
668 // Instead of subclassing the MCELFStreamer, we do the work here.
670 void ARMAsmPrinter::emitAttributes() {
672 emitARMAttributeSection();
674 /* GAS expect .fpu to be emitted, regardless of VFP build attribute */
675 bool emitFPU = false;
676 AttributeEmitter *AttrEmitter;
677 if (OutStreamer.hasRawTextSupport()) {
678 AttrEmitter = new AsmAttributeEmitter(OutStreamer);
679 emitFPU = true;
680 } else {
681 MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
682 AttrEmitter = new ObjectAttributeEmitter(O);
683 }
685 AttrEmitter->MaybeSwitchVendor("aeabi");
687 std::string CPUString = Subtarget->getCPUString();
689 if (CPUString == "cortex-a8" ||
690 Subtarget->isCortexA8()) {
691 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a8");
692 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
693 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile,
694 ARMBuildAttrs::ApplicationProfile);
695 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
696 ARMBuildAttrs::Allowed);
697 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
698 ARMBuildAttrs::AllowThumb32);
699 // Fixme: figure out when this is emitted.
700 //AttrEmitter->EmitAttribute(ARMBuildAttrs::WMMX_arch,
701 // ARMBuildAttrs::AllowWMMXv1);
702 //
704 /// ADD additional Else-cases here!
705 } else if (CPUString == "xscale") {
706 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5TEJ);
707 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
708 ARMBuildAttrs::Allowed);
709 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
710 ARMBuildAttrs::Allowed);
711 } else if (CPUString == "generic") {
712 // FIXME: Why these defaults?
713 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
714 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
715 ARMBuildAttrs::Allowed);
716 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
717 ARMBuildAttrs::Allowed);
718 }
720 if (Subtarget->hasNEON() && emitFPU) {
721 /* NEON is not exactly a VFP architecture, but GAS emit one of
722 * neon/vfpv3/vfpv2 for .fpu parameters */
723 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch, "neon");
724 /* If emitted for NEON, omit from VFP below, since you can have both
725 * NEON and VFP in build attributes but only one .fpu */
726 emitFPU = false;
727 }
729 /* VFPv3 + .fpu */
730 if (Subtarget->hasVFP3()) {
731 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
732 ARMBuildAttrs::AllowFPv3A);
733 if (emitFPU)
734 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv3");
736 /* VFPv2 + .fpu */
737 } else if (Subtarget->hasVFP2()) {
738 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
739 ARMBuildAttrs::AllowFPv2);
740 if (emitFPU)
741 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv2");
742 }
744 /* TODO: ARMBuildAttrs::Allowed is not completely accurate,
745 * since NEON can have 1 (allowed) or 2 (MAC operations) */
746 if (Subtarget->hasNEON()) {
747 AttrEmitter->EmitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
748 ARMBuildAttrs::Allowed);
749 }
751 // Signal various FP modes.
752 if (!TM.Options.UnsafeFPMath) {
753 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal,
754 ARMBuildAttrs::Allowed);
755 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
756 ARMBuildAttrs::Allowed);
757 }
759 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
760 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
761 ARMBuildAttrs::Allowed);
762 else
763 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
764 ARMBuildAttrs::AllowIEE754);
766 // FIXME: add more flags to ARMBuildAttrs.h
767 // 8-bytes alignment stuff.
768 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
769 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
771 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
772 if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard) {
773 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
774 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
775 }
776 // FIXME: Should we signal R9 usage?
778 if (Subtarget->hasDivide())
779 AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
781 AttrEmitter->Finish();
782 delete AttrEmitter;
783 }
785 void ARMAsmPrinter::emitARMAttributeSection() {
786 // <format-version>
787 // [ <section-length> "vendor-name"
788 // [ <file-tag> <size> <attribute>*
789 // | <section-tag> <size> <section-number>* 0 <attribute>*
790 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
791 // ]+
792 // ]*
794 if (OutStreamer.hasRawTextSupport())
795 return;
797 const ARMElfTargetObjectFile &TLOFELF =
798 static_cast<const ARMElfTargetObjectFile &>
799 (getObjFileLowering());
801 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
803 // Format version
804 OutStreamer.EmitIntValue(0x41, 1);
805 }
807 //===----------------------------------------------------------------------===//
809 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
810 unsigned LabelId, MCContext &Ctx) {
812 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
813 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
814 return Label;
815 }
817 static MCSymbolRefExpr::VariantKind
818 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
819 switch (Modifier) {
820 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
821 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_ARM_TLSGD;
822 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_ARM_TPOFF;
823 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_ARM_GOTTPOFF;
824 case ARMCP::GOT: return MCSymbolRefExpr::VK_ARM_GOT;
825 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_ARM_GOTOFF;
826 }
827 return MCSymbolRefExpr::VK_None;
828 }
830 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV) {
831 bool isIndirect = Subtarget->isTargetDarwin() &&
832 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
833 if (!isIndirect)
834 return Mang->getSymbol(GV);
836 // FIXME: Remove this when Darwin transition to @GOT like syntax.
837 MCSymbol *MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
838 MachineModuleInfoMachO &MMIMachO =
839 MMI->getObjFileInfo<MachineModuleInfoMachO>();
840 MachineModuleInfoImpl::StubValueTy &StubSym =
841 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
842 MMIMachO.getGVStubEntry(MCSym);
843 if (StubSym.getPointer() == 0)
844 StubSym = MachineModuleInfoImpl::
845 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
846 return MCSym;
847 }
849 void ARMAsmPrinter::
850 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
851 int Size = TM.getTargetData()->getTypeAllocSize(MCPV->getType());
853 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
855 MCSymbol *MCSym;
856 if (ACPV->isLSDA()) {
857 SmallString<128> Str;
858 raw_svector_ostream OS(Str);
859 OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
860 MCSym = OutContext.GetOrCreateSymbol(OS.str());
861 } else if (ACPV->isBlockAddress()) {
862 const BlockAddress *BA =
863 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
864 MCSym = GetBlockAddressSymbol(BA);
865 } else if (ACPV->isGlobalValue()) {
866 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
867 MCSym = GetARMGVSymbol(GV);
868 } else if (ACPV->isMachineBasicBlock()) {
869 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
870 MCSym = MBB->getSymbol();
871 } else {
872 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
873 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
874 MCSym = GetExternalSymbolSymbol(Sym);
875 }
877 // Create an MCSymbol for the reference.
878 const MCExpr *Expr =
879 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
880 OutContext);
882 if (ACPV->getPCAdjustment()) {
883 MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(),
884 getFunctionNumber(),
885 ACPV->getLabelId(),
886 OutContext);
887 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
888 PCRelExpr =
889 MCBinaryExpr::CreateAdd(PCRelExpr,
890 MCConstantExpr::Create(ACPV->getPCAdjustment(),
891 OutContext),
892 OutContext);
893 if (ACPV->mustAddCurrentAddress()) {
894 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
895 // label, so just emit a local label end reference that instead.
896 MCSymbol *DotSym = OutContext.CreateTempSymbol();
897 OutStreamer.EmitLabel(DotSym);
898 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
899 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
900 }
901 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
902 }
903 OutStreamer.EmitValue(Expr, Size);
904 }
906 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
907 unsigned Opcode = MI->getOpcode();
908 int OpNum = 1;
909 if (Opcode == ARM::BR_JTadd)
910 OpNum = 2;
911 else if (Opcode == ARM::BR_JTm)
912 OpNum = 3;
914 const MachineOperand &MO1 = MI->getOperand(OpNum);
915 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
916 unsigned JTI = MO1.getIndex();
918 // Tag the jump table appropriately for precise disassembly.
919 OutStreamer.EmitJumpTable32Region();
921 // Emit a label for the jump table.
922 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
923 OutStreamer.EmitLabel(JTISymbol);
925 // Emit each entry of the table.
926 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
927 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
928 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
930 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
931 MachineBasicBlock *MBB = JTBBs[i];
932 // Construct an MCExpr for the entry. We want a value of the form:
933 // (BasicBlockAddr - TableBeginAddr)
934 //
935 // For example, a table with entries jumping to basic blocks BB0 and BB1
936 // would look like:
937 // LJTI_0_0:
938 // .word (LBB0 - LJTI_0_0)
939 // .word (LBB1 - LJTI_0_0)
940 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
942 if (TM.getRelocationModel() == Reloc::PIC_)
943 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
944 OutContext),
945 OutContext);
946 // If we're generating a table of Thumb addresses in static relocation
947 // model, we need to add one to keep interworking correctly.
948 else if (AFI->isThumbFunction())
949 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
950 OutContext);
951 OutStreamer.EmitValue(Expr, 4);
952 }
953 }
955 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
956 unsigned Opcode = MI->getOpcode();
957 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
958 const MachineOperand &MO1 = MI->getOperand(OpNum);
959 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
960 unsigned JTI = MO1.getIndex();
962 // Emit a label for the jump table.
963 if (MI->getOpcode() == ARM::t2TBB_JT) {
964 OutStreamer.EmitJumpTable8Region();
965 } else if (MI->getOpcode() == ARM::t2TBH_JT) {
966 OutStreamer.EmitJumpTable16Region();
967 } else {
968 OutStreamer.EmitJumpTable32Region();
969 }
971 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
972 OutStreamer.EmitLabel(JTISymbol);
974 // Emit each entry of the table.
975 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
976 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
977 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
978 unsigned OffsetWidth = 4;
979 if (MI->getOpcode() == ARM::t2TBB_JT)
980 OffsetWidth = 1;
981 else if (MI->getOpcode() == ARM::t2TBH_JT)
982 OffsetWidth = 2;
984 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
985 MachineBasicBlock *MBB = JTBBs[i];
986 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
987 OutContext);
988 // If this isn't a TBB or TBH, the entries are direct branch instructions.
989 if (OffsetWidth == 4) {
990 MCInst BrInst;
991 BrInst.setOpcode(ARM::t2B);
992 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
993 BrInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
994 BrInst.addOperand(MCOperand::CreateReg(0));
995 OutStreamer.EmitInstruction(BrInst);
996 continue;
997 }
998 // Otherwise it's an offset from the dispatch instruction. Construct an
999 // MCExpr for the entry. We want a value of the form:
1000 // (BasicBlockAddr - TableBeginAddr) / 2
1001 //
1002 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1003 // would look like:
1004 // LJTI_0_0:
1005 // .byte (LBB0 - LJTI_0_0) / 2
1006 // .byte (LBB1 - LJTI_0_0) / 2
1007 const MCExpr *Expr =
1008 MCBinaryExpr::CreateSub(MBBSymbolExpr,
1009 MCSymbolRefExpr::Create(JTISymbol, OutContext),
1010 OutContext);
1011 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
1012 OutContext);
1013 OutStreamer.EmitValue(Expr, OffsetWidth);
1014 }
1015 }
1017 void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
1018 raw_ostream &OS) {
1019 unsigned NOps = MI->getNumOperands();
1020 assert(NOps==4);
1021 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
1022 // cast away const; DIetc do not take const operands for some reason.
1023 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
1024 OS << V.getName();
1025 OS << " <- ";
1026 // Frame address. Currently handles register +- offset only.
1027 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
1028 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
1029 OS << ']';
1030 OS << "+";
1031 printOperand(MI, NOps-2, OS);
1032 }
1034 static void populateADROperands(MCInst &Inst, unsigned Dest,
1035 const MCSymbol *Label,
1036 unsigned pred, unsigned ccreg,
1037 MCContext &Ctx) {
1038 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, Ctx);
1039 Inst.addOperand(MCOperand::CreateReg(Dest));
1040 Inst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1041 // Add predicate operands.
1042 Inst.addOperand(MCOperand::CreateImm(pred));
1043 Inst.addOperand(MCOperand::CreateReg(ccreg));
1044 }
1046 void ARMAsmPrinter::EmitPatchedInstruction(const MachineInstr *MI,
1047 unsigned Opcode) {
1048 MCInst TmpInst;
1050 // Emit the instruction as usual, just patch the opcode.
1051 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1052 TmpInst.setOpcode(Opcode);
1053 OutStreamer.EmitInstruction(TmpInst);
1054 }
1056 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1057 assert(MI->getFlag(MachineInstr::FrameSetup) &&
1058 "Only instruction which are involved into frame setup code are allowed");
1060 const MachineFunction &MF = *MI->getParent()->getParent();
1061 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
1062 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
1064 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1065 unsigned Opc = MI->getOpcode();
1066 unsigned SrcReg, DstReg;
1068 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1069 // Two special cases:
1070 // 1) tPUSH does not have src/dst regs.
1071 // 2) for Thumb1 code we sometimes materialize the constant via constpool
1072 // load. Yes, this is pretty fragile, but for now I don't see better
1073 // way... :(
1074 SrcReg = DstReg = ARM::SP;
1075 } else {
1076 SrcReg = MI->getOperand(1).getReg();
1077 DstReg = MI->getOperand(0).getReg();
1078 }
1080 // Try to figure out the unwinding opcode out of src / dst regs.
1081 if (MI->mayStore()) {
1082 // Register saves.
1083 assert(DstReg == ARM::SP &&
1084 "Only stack pointer as a destination reg is supported");
1086 SmallVector<unsigned, 4> RegList;
1087 // Skip src & dst reg, and pred ops.
1088 unsigned StartOp = 2 + 2;
1089 // Use all the operands.
1090 unsigned NumOffset = 0;
1092 switch (Opc) {
1093 default:
1094 MI->dump();
1095 assert(0 && "Unsupported opcode for unwinding information");
1096 case ARM::tPUSH:
1097 // Special case here: no src & dst reg, but two extra imp ops.
1098 StartOp = 2; NumOffset = 2;
1099 case ARM::STMDB_UPD:
1100 case ARM::t2STMDB_UPD:
1101 case ARM::VSTMDDB_UPD:
1102 assert(SrcReg == ARM::SP &&
1103 "Only stack pointer as a source reg is supported");
1104 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1105 i != NumOps; ++i)
1106 RegList.push_back(MI->getOperand(i).getReg());
1107 break;
1108 case ARM::STR_PRE_IMM:
1109 case ARM::STR_PRE_REG:
1110 case ARM::t2STR_PRE:
1111 assert(MI->getOperand(2).getReg() == ARM::SP &&
1112 "Only stack pointer as a source reg is supported");
1113 RegList.push_back(SrcReg);
1114 break;
1115 }
1116 OutStreamer.EmitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1117 } else {
1118 // Changes of stack / frame pointer.
1119 if (SrcReg == ARM::SP) {
1120 int64_t Offset = 0;
1121 switch (Opc) {
1122 default:
1123 MI->dump();
1124 assert(0 && "Unsupported opcode for unwinding information");
1125 case ARM::MOVr:
1126 case ARM::tMOVr:
1127 Offset = 0;
1128 break;
1129 case ARM::ADDri:
1130 Offset = -MI->getOperand(2).getImm();
1131 break;
1132 case ARM::SUBri:
1133 case ARM::t2SUBri:
1134 Offset = MI->getOperand(2).getImm();
1135 break;
1136 case ARM::tSUBspi:
1137 Offset = MI->getOperand(2).getImm()*4;
1138 break;
1139 case ARM::tADDspi:
1140 case ARM::tADDrSPi:
1141 Offset = -MI->getOperand(2).getImm()*4;
1142 break;
1143 case ARM::tLDRpci: {
1144 // Grab the constpool index and check, whether it corresponds to
1145 // original or cloned constpool entry.
1146 unsigned CPI = MI->getOperand(1).getIndex();
1147 const MachineConstantPool *MCP = MF.getConstantPool();
1148 if (CPI >= MCP->getConstants().size())
1149 CPI = AFI.getOriginalCPIdx(CPI);
1150 assert(CPI != -1U && "Invalid constpool index");
1152 // Derive the actual offset.
1153 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1154 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1155 // FIXME: Check for user, it should be "add" instruction!
1156 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1157 break;
1158 }
1159 }
1161 if (DstReg == FramePtr && FramePtr != ARM::SP)
1162 // Set-up of the frame pointer. Positive values correspond to "add"
1163 // instruction.
1164 OutStreamer.EmitSetFP(FramePtr, ARM::SP, -Offset);
1165 else if (DstReg == ARM::SP) {
1166 // Change of SP by an offset. Positive values correspond to "sub"
1167 // instruction.
1168 OutStreamer.EmitPad(Offset);
1169 } else {
1170 MI->dump();
1171 assert(0 && "Unsupported opcode for unwinding information");
1172 }
1173 } else if (DstReg == ARM::SP) {
1174 // FIXME: .movsp goes here
1175 MI->dump();
1176 assert(0 && "Unsupported opcode for unwinding information");
1177 }
1178 else {
1179 MI->dump();
1180 assert(0 && "Unsupported opcode for unwinding information");
1181 }
1182 }
1183 }
1185 extern cl::opt<bool> EnableARMEHABI;
1187 // Simple pseudo-instructions have their lowering (with expansion to real
1188 // instructions) auto-generated.
1189 #include "ARMGenMCPseudoLowering.inc"
1191 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1192 if (MI->getOpcode() != ARM::CONSTPOOL_ENTRY)
1193 OutStreamer.EmitCodeRegion();
1195 // Emit unwinding stuff for frame-related instructions
1196 if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup))
1197 EmitUnwindingInstruction(MI);
1199 // Do any auto-generated pseudo lowerings.
1200 if (emitPseudoExpansionLowering(OutStreamer, MI))
1201 return;
1203 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1204 "Pseudo flag setting opcode should be expanded early");
1206 // Check for manual lowerings.
1207 unsigned Opc = MI->getOpcode();
1208 switch (Opc) {
1209 case ARM::t2MOVi32imm: assert(0 && "Should be lowered by thumb2it pass");
1210 case ARM::DBG_VALUE: {
1211 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
1212 SmallString<128> TmpStr;
1213 raw_svector_ostream OS(TmpStr);
1214 PrintDebugValueComment(MI, OS);
1215 OutStreamer.EmitRawText(StringRef(OS.str()));
1216 }
1217 return;
1218 }
1219 case ARM::LEApcrel:
1220 case ARM::tLEApcrel:
1221 case ARM::t2LEApcrel: {
1222 // FIXME: Need to also handle globals and externals
1223 MCInst TmpInst;
1224 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR
1225 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1226 : ARM::ADR));
1227 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1228 GetCPISymbol(MI->getOperand(1).getIndex()),
1229 MI->getOperand(2).getImm(), MI->getOperand(3).getReg(),
1230 OutContext);
1231 OutStreamer.EmitInstruction(TmpInst);
1232 return;
1233 }
1234 case ARM::LEApcrelJT:
1235 case ARM::tLEApcrelJT:
1236 case ARM::t2LEApcrelJT: {
1237 MCInst TmpInst;
1238 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR
1239 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1240 : ARM::ADR));
1241 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1242 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1243 MI->getOperand(2).getImm()),
1244 MI->getOperand(3).getImm(), MI->getOperand(4).getReg(),
1245 OutContext);
1246 OutStreamer.EmitInstruction(TmpInst);
1247 return;
1248 }
1249 // Darwin call instructions are just normal call instructions with different
1250 // clobber semantics (they clobber R9).
1251 case ARM::BXr9_CALL:
1252 case ARM::BX_CALL: {
1253 {
1254 MCInst TmpInst;
1255 TmpInst.setOpcode(ARM::MOVr);
1256 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1257 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1258 // Add predicate operands.
1259 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1260 TmpInst.addOperand(MCOperand::CreateReg(0));
1261 // Add 's' bit operand (always reg0 for this)
1262 TmpInst.addOperand(MCOperand::CreateReg(0));
1263 OutStreamer.EmitInstruction(TmpInst);
1264 }
1265 {
1266 MCInst TmpInst;
1267 TmpInst.setOpcode(ARM::BX);
1268 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1269 OutStreamer.EmitInstruction(TmpInst);
1270 }
1271 return;
1272 }
1273 case ARM::tBXr9_CALL:
1274 case ARM::tBX_CALL: {
1275 {
1276 MCInst TmpInst;
1277 TmpInst.setOpcode(ARM::tMOVr);
1278 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1279 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1280 // Add predicate operands.
1281 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1282 TmpInst.addOperand(MCOperand::CreateReg(0));
1283 OutStreamer.EmitInstruction(TmpInst);
1284 }
1285 {
1286 MCInst TmpInst;
1287 TmpInst.setOpcode(ARM::tBX);
1288 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1289 // Add predicate operands.
1290 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1291 TmpInst.addOperand(MCOperand::CreateReg(0));
1292 OutStreamer.EmitInstruction(TmpInst);
1293 }
1294 return;
1295 }
1296 case ARM::BMOVPCRXr9_CALL:
1297 case ARM::BMOVPCRX_CALL: {
1298 {
1299 MCInst TmpInst;
1300 TmpInst.setOpcode(ARM::MOVr);
1301 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1302 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1303 // Add predicate operands.
1304 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1305 TmpInst.addOperand(MCOperand::CreateReg(0));
1306 // Add 's' bit operand (always reg0 for this)
1307 TmpInst.addOperand(MCOperand::CreateReg(0));
1308 OutStreamer.EmitInstruction(TmpInst);
1309 }
1310 {
1311 MCInst TmpInst;
1312 TmpInst.setOpcode(ARM::MOVr);
1313 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1314 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1315 // Add predicate operands.
1316 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1317 TmpInst.addOperand(MCOperand::CreateReg(0));
1318 // Add 's' bit operand (always reg0 for this)
1319 TmpInst.addOperand(MCOperand::CreateReg(0));
1320 OutStreamer.EmitInstruction(TmpInst);
1321 }
1322 return;
1323 }
1324 case ARM::MOVi16_ga_pcrel:
1325 case ARM::t2MOVi16_ga_pcrel: {
1326 MCInst TmpInst;
1327 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1328 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1330 unsigned TF = MI->getOperand(1).getTargetFlags();
1331 bool isPIC = TF == ARMII::MO_LO16_NONLAZY_PIC;
1332 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1333 MCSymbol *GVSym = GetARMGVSymbol(GV);
1334 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1335 if (isPIC) {
1336 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1337 getFunctionNumber(),
1338 MI->getOperand(2).getImm(), OutContext);
1339 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1340 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1341 const MCExpr *PCRelExpr =
1342 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1343 MCBinaryExpr::CreateAdd(LabelSymExpr,
1344 MCConstantExpr::Create(PCAdj, OutContext),
1345 OutContext), OutContext), OutContext);
1346 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1347 } else {
1348 const MCExpr *RefExpr= ARMMCExpr::CreateLower16(GVSymExpr, OutContext);
1349 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1350 }
1352 // Add predicate operands.
1353 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1354 TmpInst.addOperand(MCOperand::CreateReg(0));
1355 // Add 's' bit operand (always reg0 for this)
1356 TmpInst.addOperand(MCOperand::CreateReg(0));
1357 OutStreamer.EmitInstruction(TmpInst);
1358 return;
1359 }
1360 case ARM::MOVTi16_ga_pcrel:
1361 case ARM::t2MOVTi16_ga_pcrel: {
1362 MCInst TmpInst;
1363 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1364 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1365 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1366 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1368 unsigned TF = MI->getOperand(2).getTargetFlags();
1369 bool isPIC = TF == ARMII::MO_HI16_NONLAZY_PIC;
1370 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1371 MCSymbol *GVSym = GetARMGVSymbol(GV);
1372 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1373 if (isPIC) {
1374 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1375 getFunctionNumber(),
1376 MI->getOperand(3).getImm(), OutContext);
1377 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1378 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1379 const MCExpr *PCRelExpr =
1380 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1381 MCBinaryExpr::CreateAdd(LabelSymExpr,
1382 MCConstantExpr::Create(PCAdj, OutContext),
1383 OutContext), OutContext), OutContext);
1384 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1385 } else {
1386 const MCExpr *RefExpr= ARMMCExpr::CreateUpper16(GVSymExpr, OutContext);
1387 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1388 }
1389 // Add predicate operands.
1390 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1391 TmpInst.addOperand(MCOperand::CreateReg(0));
1392 // Add 's' bit operand (always reg0 for this)
1393 TmpInst.addOperand(MCOperand::CreateReg(0));
1394 OutStreamer.EmitInstruction(TmpInst);
1395 return;
1396 }
1397 case ARM::tPICADD: {
1398 // This is a pseudo op for a label + instruction sequence, which looks like:
1399 // LPC0:
1400 // add r0, pc
1401 // This adds the address of LPC0 to r0.
1403 // Emit the label.
1404 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1405 getFunctionNumber(), MI->getOperand(2).getImm(),
1406 OutContext));
1408 // Form and emit the add.
1409 MCInst AddInst;
1410 AddInst.setOpcode(ARM::tADDhirr);
1411 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1412 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1413 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1414 // Add predicate operands.
1415 AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1416 AddInst.addOperand(MCOperand::CreateReg(0));
1417 OutStreamer.EmitInstruction(AddInst);
1418 return;
1419 }
1420 case ARM::PICADD: {
1421 // This is a pseudo op for a label + instruction sequence, which looks like:
1422 // LPC0:
1423 // add r0, pc, r0
1424 // This adds the address of LPC0 to r0.
1426 // Emit the label.
1427 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1428 getFunctionNumber(), MI->getOperand(2).getImm(),
1429 OutContext));
1431 // Form and emit the add.
1432 MCInst AddInst;
1433 AddInst.setOpcode(ARM::ADDrr);
1434 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1435 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1436 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1437 // Add predicate operands.
1438 AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1439 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1440 // Add 's' bit operand (always reg0 for this)
1441 AddInst.addOperand(MCOperand::CreateReg(0));
1442 OutStreamer.EmitInstruction(AddInst);
1443 return;
1444 }
1445 case ARM::PICSTR:
1446 case ARM::PICSTRB:
1447 case ARM::PICSTRH:
1448 case ARM::PICLDR:
1449 case ARM::PICLDRB:
1450 case ARM::PICLDRH:
1451 case ARM::PICLDRSB:
1452 case ARM::PICLDRSH: {
1453 // This is a pseudo op for a label + instruction sequence, which looks like:
1454 // LPC0:
1455 // OP r0, [pc, r0]
1456 // The LCP0 label is referenced by a constant pool entry in order to get
1457 // a PC-relative address at the ldr instruction.
1459 // Emit the label.
1460 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1461 getFunctionNumber(), MI->getOperand(2).getImm(),
1462 OutContext));
1464 // Form and emit the load
1465 unsigned Opcode;
1466 switch (MI->getOpcode()) {
1467 default:
1468 llvm_unreachable("Unexpected opcode!");
1469 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1470 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1471 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1472 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1473 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1474 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1475 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1476 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1477 }
1478 MCInst LdStInst;
1479 LdStInst.setOpcode(Opcode);
1480 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1481 LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
1482 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1483 LdStInst.addOperand(MCOperand::CreateImm(0));
1484 // Add predicate operands.
1485 LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1486 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1487 OutStreamer.EmitInstruction(LdStInst);
1489 return;
1490 }
1491 case ARM::CONSTPOOL_ENTRY: {
1492 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1493 /// in the function. The first operand is the ID# for this instruction, the
1494 /// second is the index into the MachineConstantPool that this is, the third
1495 /// is the size in bytes of this constant pool entry.
1496 /// The required alignment is specified on the basic block holding this MI.
1497 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1498 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1500 // Mark the constant pool entry as data if we're not already in a data
1501 // region.
1502 OutStreamer.EmitDataRegion();
1503 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1505 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1506 if (MCPE.isMachineConstantPoolEntry())
1507 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1508 else
1509 EmitGlobalConstant(MCPE.Val.ConstVal);
1510 return;
1511 }
1512 case ARM::t2BR_JT: {
1513 // Lower and emit the instruction itself, then the jump table following it.
1514 MCInst TmpInst;
1515 TmpInst.setOpcode(ARM::tMOVr);
1516 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1517 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1518 // Add predicate operands.
1519 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1520 TmpInst.addOperand(MCOperand::CreateReg(0));
1521 OutStreamer.EmitInstruction(TmpInst);
1522 // Output the data for the jump table itself
1523 EmitJump2Table(MI);
1524 return;
1525 }
1526 case ARM::t2TBB_JT: {
1527 // Lower and emit the instruction itself, then the jump table following it.
1528 MCInst TmpInst;
1530 TmpInst.setOpcode(ARM::t2TBB);
1531 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1532 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1533 // Add predicate operands.
1534 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1535 TmpInst.addOperand(MCOperand::CreateReg(0));
1536 OutStreamer.EmitInstruction(TmpInst);
1537 // Output the data for the jump table itself
1538 EmitJump2Table(MI);
1539 // Make sure the next instruction is 2-byte aligned.
1540 EmitAlignment(1);
1541 return;
1542 }
1543 case ARM::t2TBH_JT: {
1544 // Lower and emit the instruction itself, then the jump table following it.
1545 MCInst TmpInst;
1547 TmpInst.setOpcode(ARM::t2TBH);
1548 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1549 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1550 // Add predicate operands.
1551 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1552 TmpInst.addOperand(MCOperand::CreateReg(0));
1553 OutStreamer.EmitInstruction(TmpInst);
1554 // Output the data for the jump table itself
1555 EmitJump2Table(MI);
1556 return;
1557 }
1558 case ARM::tBR_JTr:
1559 case ARM::BR_JTr: {
1560 // Lower and emit the instruction itself, then the jump table following it.
1561 // mov pc, target
1562 MCInst TmpInst;
1563 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1564 ARM::MOVr : ARM::tMOVr;
1565 TmpInst.setOpcode(Opc);
1566 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1567 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1568 // Add predicate operands.
1569 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1570 TmpInst.addOperand(MCOperand::CreateReg(0));
1571 // Add 's' bit operand (always reg0 for this)
1572 if (Opc == ARM::MOVr)
1573 TmpInst.addOperand(MCOperand::CreateReg(0));
1574 OutStreamer.EmitInstruction(TmpInst);
1576 // Make sure the Thumb jump table is 4-byte aligned.
1577 if (Opc == ARM::tMOVr)
1578 EmitAlignment(2);
1580 // Output the data for the jump table itself
1581 EmitJumpTable(MI);
1582 return;
1583 }
1584 case ARM::BR_JTm: {
1585 // Lower and emit the instruction itself, then the jump table following it.
1586 // ldr pc, target
1587 MCInst TmpInst;
1588 if (MI->getOperand(1).getReg() == 0) {
1589 // literal offset
1590 TmpInst.setOpcode(ARM::LDRi12);
1591 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1592 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1593 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1594 } else {
1595 TmpInst.setOpcode(ARM::LDRrs);
1596 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1597 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1598 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1599 TmpInst.addOperand(MCOperand::CreateImm(0));
1600 }
1601 // Add predicate operands.
1602 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1603 TmpInst.addOperand(MCOperand::CreateReg(0));
1604 OutStreamer.EmitInstruction(TmpInst);
1606 // Output the data for the jump table itself
1607 EmitJumpTable(MI);
1608 return;
1609 }
1610 case ARM::BR_JTadd: {
1611 // Lower and emit the instruction itself, then the jump table following it.
1612 // add pc, target, idx
1613 MCInst TmpInst;
1614 TmpInst.setOpcode(ARM::ADDrr);
1615 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1616 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1617 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1618 // Add predicate operands.
1619 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1620 TmpInst.addOperand(MCOperand::CreateReg(0));
1621 // Add 's' bit operand (always reg0 for this)
1622 TmpInst.addOperand(MCOperand::CreateReg(0));
1623 OutStreamer.EmitInstruction(TmpInst);
1625 // Output the data for the jump table itself
1626 EmitJumpTable(MI);
1627 return;
1628 }
1629 case ARM::TRAP: {
1630 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1631 // FIXME: Remove this special case when they do.
1632 if (!Subtarget->isTargetDarwin()) {
1633 //.long 0xe7ffdefe @ trap
1634 uint32_t Val = 0xe7ffdefeUL;
1635 OutStreamer.AddComment("trap");
1636 OutStreamer.EmitIntValue(Val, 4);
1637 return;
1638 }
1639 break;
1640 }
1641 case ARM::tTRAP: {
1642 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1643 // FIXME: Remove this special case when they do.
1644 if (!Subtarget->isTargetDarwin()) {
1645 //.short 57086 @ trap
1646 uint16_t Val = 0xdefe;
1647 OutStreamer.AddComment("trap");
1648 OutStreamer.EmitIntValue(Val, 2);
1649 return;
1650 }
1651 break;
1652 }
1653 case ARM::t2Int_eh_sjlj_setjmp:
1654 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1655 case ARM::tInt_eh_sjlj_setjmp: {
1656 // Two incoming args: GPR:$src, GPR:$val
1657 // mov $val, pc
1658 // adds $val, #7
1659 // str $val, [$src, #4]
1660 // movs r0, #0
1661 // b 1f
1662 // movs r0, #1
1663 // 1:
1664 unsigned SrcReg = MI->getOperand(0).getReg();
1665 unsigned ValReg = MI->getOperand(1).getReg();
1666 MCSymbol *Label = GetARMSJLJEHLabel();
1667 {
1668 MCInst TmpInst;
1669 TmpInst.setOpcode(ARM::tMOVr);
1670 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1671 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1672 // Predicate.
1673 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1674 TmpInst.addOperand(MCOperand::CreateReg(0));
1675 OutStreamer.AddComment("eh_setjmp begin");
1676 OutStreamer.EmitInstruction(TmpInst);
1677 }
1678 {
1679 MCInst TmpInst;
1680 TmpInst.setOpcode(ARM::tADDi3);
1681 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1682 // 's' bit operand
1683 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1684 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1685 TmpInst.addOperand(MCOperand::CreateImm(7));
1686 // Predicate.
1687 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1688 TmpInst.addOperand(MCOperand::CreateReg(0));
1689 OutStreamer.EmitInstruction(TmpInst);
1690 }
1691 {
1692 MCInst TmpInst;
1693 TmpInst.setOpcode(ARM::tSTRi);
1694 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1695 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1696 // The offset immediate is #4. The operand value is scaled by 4 for the
1697 // tSTR instruction.
1698 TmpInst.addOperand(MCOperand::CreateImm(1));
1699 // Predicate.
1700 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1701 TmpInst.addOperand(MCOperand::CreateReg(0));
1702 OutStreamer.EmitInstruction(TmpInst);
1703 }
1704 {
1705 MCInst TmpInst;
1706 TmpInst.setOpcode(ARM::tMOVi8);
1707 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1708 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1709 TmpInst.addOperand(MCOperand::CreateImm(0));
1710 // Predicate.
1711 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1712 TmpInst.addOperand(MCOperand::CreateReg(0));
1713 OutStreamer.EmitInstruction(TmpInst);
1714 }
1715 {
1716 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1717 MCInst TmpInst;
1718 TmpInst.setOpcode(ARM::tB);
1719 TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1720 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1721 TmpInst.addOperand(MCOperand::CreateReg(0));
1722 OutStreamer.EmitInstruction(TmpInst);
1723 }
1724 {
1725 MCInst TmpInst;
1726 TmpInst.setOpcode(ARM::tMOVi8);
1727 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1728 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1729 TmpInst.addOperand(MCOperand::CreateImm(1));
1730 // Predicate.
1731 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1732 TmpInst.addOperand(MCOperand::CreateReg(0));
1733 OutStreamer.AddComment("eh_setjmp end");
1734 OutStreamer.EmitInstruction(TmpInst);
1735 }
1736 OutStreamer.EmitLabel(Label);
1737 return;
1738 }
1740 case ARM::Int_eh_sjlj_setjmp_nofp:
1741 case ARM::Int_eh_sjlj_setjmp: {
1742 // Two incoming args: GPR:$src, GPR:$val
1743 // add $val, pc, #8
1744 // str $val, [$src, #+4]
1745 // mov r0, #0
1746 // add pc, pc, #0
1747 // mov r0, #1
1748 unsigned SrcReg = MI->getOperand(0).getReg();
1749 unsigned ValReg = MI->getOperand(1).getReg();
1751 {
1752 MCInst TmpInst;
1753 TmpInst.setOpcode(ARM::ADDri);
1754 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1755 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1756 TmpInst.addOperand(MCOperand::CreateImm(8));
1757 // Predicate.
1758 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1759 TmpInst.addOperand(MCOperand::CreateReg(0));
1760 // 's' bit operand (always reg0 for this).
1761 TmpInst.addOperand(MCOperand::CreateReg(0));
1762 OutStreamer.AddComment("eh_setjmp begin");
1763 OutStreamer.EmitInstruction(TmpInst);
1764 }
1765 {
1766 MCInst TmpInst;
1767 TmpInst.setOpcode(ARM::STRi12);
1768 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1769 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1770 TmpInst.addOperand(MCOperand::CreateImm(4));
1771 // Predicate.
1772 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1773 TmpInst.addOperand(MCOperand::CreateReg(0));
1774 OutStreamer.EmitInstruction(TmpInst);
1775 }
1776 {
1777 MCInst TmpInst;
1778 TmpInst.setOpcode(ARM::MOVi);
1779 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1780 TmpInst.addOperand(MCOperand::CreateImm(0));
1781 // Predicate.
1782 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1783 TmpInst.addOperand(MCOperand::CreateReg(0));
1784 // 's' bit operand (always reg0 for this).
1785 TmpInst.addOperand(MCOperand::CreateReg(0));
1786 OutStreamer.EmitInstruction(TmpInst);
1787 }
1788 {
1789 MCInst TmpInst;
1790 TmpInst.setOpcode(ARM::ADDri);
1791 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1792 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1793 TmpInst.addOperand(MCOperand::CreateImm(0));
1794 // Predicate.
1795 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1796 TmpInst.addOperand(MCOperand::CreateReg(0));
1797 // 's' bit operand (always reg0 for this).
1798 TmpInst.addOperand(MCOperand::CreateReg(0));
1799 OutStreamer.EmitInstruction(TmpInst);
1800 }
1801 {
1802 MCInst TmpInst;
1803 TmpInst.setOpcode(ARM::MOVi);
1804 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1805 TmpInst.addOperand(MCOperand::CreateImm(1));
1806 // Predicate.
1807 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1808 TmpInst.addOperand(MCOperand::CreateReg(0));
1809 // 's' bit operand (always reg0 for this).
1810 TmpInst.addOperand(MCOperand::CreateReg(0));
1811 OutStreamer.AddComment("eh_setjmp end");
1812 OutStreamer.EmitInstruction(TmpInst);
1813 }
1814 return;
1815 }
1816 case ARM::Int_eh_sjlj_longjmp: {
1817 // ldr sp, [$src, #8]
1818 // ldr $scratch, [$src, #4]
1819 // ldr r7, [$src]
1820 // bx $scratch
1821 unsigned SrcReg = MI->getOperand(0).getReg();
1822 unsigned ScratchReg = MI->getOperand(1).getReg();
1823 {
1824 MCInst TmpInst;
1825 TmpInst.setOpcode(ARM::LDRi12);
1826 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1827 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1828 TmpInst.addOperand(MCOperand::CreateImm(8));
1829 // Predicate.
1830 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1831 TmpInst.addOperand(MCOperand::CreateReg(0));
1832 OutStreamer.EmitInstruction(TmpInst);
1833 }
1834 {
1835 MCInst TmpInst;
1836 TmpInst.setOpcode(ARM::LDRi12);
1837 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1838 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1839 TmpInst.addOperand(MCOperand::CreateImm(4));
1840 // Predicate.
1841 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1842 TmpInst.addOperand(MCOperand::CreateReg(0));
1843 OutStreamer.EmitInstruction(TmpInst);
1844 }
1845 {
1846 MCInst TmpInst;
1847 TmpInst.setOpcode(ARM::LDRi12);
1848 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1849 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1850 TmpInst.addOperand(MCOperand::CreateImm(0));
1851 // Predicate.
1852 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1853 TmpInst.addOperand(MCOperand::CreateReg(0));
1854 OutStreamer.EmitInstruction(TmpInst);
1855 }
1856 {
1857 MCInst TmpInst;
1858 TmpInst.setOpcode(ARM::BX);
1859 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1860 // Predicate.
1861 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1862 TmpInst.addOperand(MCOperand::CreateReg(0));
1863 OutStreamer.EmitInstruction(TmpInst);
1864 }
1865 return;
1866 }
1867 case ARM::tInt_eh_sjlj_longjmp: {
1868 // ldr $scratch, [$src, #8]
1869 // mov sp, $scratch
1870 // ldr $scratch, [$src, #4]
1871 // ldr r7, [$src]
1872 // bx $scratch
1873 unsigned SrcReg = MI->getOperand(0).getReg();
1874 unsigned ScratchReg = MI->getOperand(1).getReg();
1875 {
1876 MCInst TmpInst;
1877 TmpInst.setOpcode(ARM::tLDRi);
1878 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1879 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1880 // The offset immediate is #8. The operand value is scaled by 4 for the
1881 // tLDR instruction.
1882 TmpInst.addOperand(MCOperand::CreateImm(2));
1883 // Predicate.
1884 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1885 TmpInst.addOperand(MCOperand::CreateReg(0));
1886 OutStreamer.EmitInstruction(TmpInst);
1887 }
1888 {
1889 MCInst TmpInst;
1890 TmpInst.setOpcode(ARM::tMOVr);
1891 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1892 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1893 // Predicate.
1894 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1895 TmpInst.addOperand(MCOperand::CreateReg(0));
1896 OutStreamer.EmitInstruction(TmpInst);
1897 }
1898 {
1899 MCInst TmpInst;
1900 TmpInst.setOpcode(ARM::tLDRi);
1901 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1902 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1903 TmpInst.addOperand(MCOperand::CreateImm(1));
1904 // Predicate.
1905 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1906 TmpInst.addOperand(MCOperand::CreateReg(0));
1907 OutStreamer.EmitInstruction(TmpInst);
1908 }
1909 {
1910 MCInst TmpInst;
1911 TmpInst.setOpcode(ARM::tLDRr);
1912 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1913 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1914 TmpInst.addOperand(MCOperand::CreateReg(0));
1915 // Predicate.
1916 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1917 TmpInst.addOperand(MCOperand::CreateReg(0));
1918 OutStreamer.EmitInstruction(TmpInst);
1919 }
1920 {
1921 MCInst TmpInst;
1922 TmpInst.setOpcode(ARM::tBX);
1923 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1924 // Predicate.
1925 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1926 TmpInst.addOperand(MCOperand::CreateReg(0));
1927 OutStreamer.EmitInstruction(TmpInst);
1928 }
1929 return;
1930 }
1931 }
1933 MCInst TmpInst;
1934 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1936 OutStreamer.EmitInstruction(TmpInst);
1937 }
1939 //===----------------------------------------------------------------------===//
1940 // Target Registry Stuff
1941 //===----------------------------------------------------------------------===//
1943 // Force static initialization.
1944 extern "C" void LLVMInitializeARMAsmPrinter() {
1945 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1946 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1947 }