1 //===- ARM64AddressingModes.h - ARM64 Addressing Modes ----------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the ARM64 addressing mode implementation stuff.
11 //
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_ARM64_ARM64ADDRESSINGMODES_H
15 #define LLVM_TARGET_ARM64_ARM64ADDRESSINGMODES_H
17 #include "llvm/ADT/APFloat.h"
18 #include "llvm/ADT/APInt.h"
19 #include "llvm/Support/ErrorHandling.h"
20 #include "llvm/Support/MathExtras.h"
21 #include <cassert>
23 namespace llvm {
25 /// ARM64_AM - ARM64 Addressing Mode Stuff
26 namespace ARM64_AM {
28 //===----------------------------------------------------------------------===//
29 // Shifts
30 //
32 enum ShiftType {
33 InvalidShift = -1,
34 LSL = 0,
35 LSR = 1,
36 ASR = 2,
37 ROR = 3,
38 MSL = 4
39 };
41 /// getShiftName - Get the string encoding for the shift type.
42 static inline const char *getShiftName(ARM64_AM::ShiftType ST) {
43 switch (ST) {
44 default: assert(false && "unhandled shift type!");
45 case ARM64_AM::LSL: return "lsl";
46 case ARM64_AM::LSR: return "lsr";
47 case ARM64_AM::ASR: return "asr";
48 case ARM64_AM::ROR: return "ror";
49 case ARM64_AM::MSL: return "msl";
50 }
51 return nullptr;
52 }
54 /// getShiftType - Extract the shift type.
55 static inline ARM64_AM::ShiftType getShiftType(unsigned Imm) {
56 return ARM64_AM::ShiftType((Imm >> 6) & 0x7);
57 }
59 /// getShiftValue - Extract the shift value.
60 static inline unsigned getShiftValue(unsigned Imm) {
61 return Imm & 0x3f;
62 }
64 /// getShifterImm - Encode the shift type and amount:
65 /// imm: 6-bit shift amount
66 /// shifter: 000 ==> lsl
67 /// 001 ==> lsr
68 /// 010 ==> asr
69 /// 011 ==> ror
70 /// 100 ==> msl
71 /// {8-6} = shifter
72 /// {5-0} = imm
73 static inline unsigned getShifterImm(ARM64_AM::ShiftType ST, unsigned Imm) {
74 assert((Imm & 0x3f) == Imm && "Illegal shifted immedate value!");
75 return (unsigned(ST) << 6) | (Imm & 0x3f);
76 }
78 //===----------------------------------------------------------------------===//
79 // Extends
80 //
82 enum ExtendType {
83 InvalidExtend = -1,
84 UXTB = 0,
85 UXTH = 1,
86 UXTW = 2,
87 UXTX = 3,
88 SXTB = 4,
89 SXTH = 5,
90 SXTW = 6,
91 SXTX = 7
92 };
94 /// getExtendName - Get the string encoding for the extend type.
95 static inline const char *getExtendName(ARM64_AM::ExtendType ET) {
96 switch (ET) {
97 default: assert(false && "unhandled extend type!");
98 case ARM64_AM::UXTB: return "uxtb";
99 case ARM64_AM::UXTH: return "uxth";
100 case ARM64_AM::UXTW: return "uxtw";
101 case ARM64_AM::UXTX: return "uxtx";
102 case ARM64_AM::SXTB: return "sxtb";
103 case ARM64_AM::SXTH: return "sxth";
104 case ARM64_AM::SXTW: return "sxtw";
105 case ARM64_AM::SXTX: return "sxtx";
106 }
107 return nullptr;
108 }
110 /// getArithShiftValue - get the arithmetic shift value.
111 static inline unsigned getArithShiftValue(unsigned Imm) {
112 return Imm & 0x7;
113 }
115 /// getExtendType - Extract the extend type for operands of arithmetic ops.
116 static inline ARM64_AM::ExtendType getArithExtendType(unsigned Imm) {
117 return ARM64_AM::ExtendType((Imm >> 3) & 0x7);
118 }
120 /// getArithExtendImm - Encode the extend type and shift amount for an
121 /// arithmetic instruction:
122 /// imm: 3-bit extend amount
123 /// shifter: 000 ==> uxtb
124 /// 001 ==> uxth
125 /// 010 ==> uxtw
126 /// 011 ==> uxtx
127 /// 100 ==> sxtb
128 /// 101 ==> sxth
129 /// 110 ==> sxtw
130 /// 111 ==> sxtx
131 /// {5-3} = shifter
132 /// {2-0} = imm3
133 static inline unsigned getArithExtendImm(ARM64_AM::ExtendType ET,
134 unsigned Imm) {
135 assert((Imm & 0x7) == Imm && "Illegal shifted immedate value!");
136 return (unsigned(ET) << 3) | (Imm & 0x7);
137 }
139 /// getMemDoShift - Extract the "do shift" flag value for load/store
140 /// instructions.
141 static inline bool getMemDoShift(unsigned Imm) {
142 return (Imm & 0x1) != 0;
143 }
145 /// getExtendType - Extract the extend type for the offset operand of
146 /// loads/stores.
147 static inline ARM64_AM::ExtendType getMemExtendType(unsigned Imm) {
148 return ARM64_AM::ExtendType((Imm >> 1) & 0x7);
149 }
151 /// getExtendImm - Encode the extend type and amount for a load/store inst:
152 /// doshift: should the offset be scaled by the access size
153 /// shifter: 000 ==> uxtb
154 /// 001 ==> uxth
155 /// 010 ==> uxtw
156 /// 011 ==> uxtx
157 /// 100 ==> sxtb
158 /// 101 ==> sxth
159 /// 110 ==> sxtw
160 /// 111 ==> sxtx
161 /// {3-1} = shifter
162 /// {0} = doshift
163 static inline unsigned getMemExtendImm(ARM64_AM::ExtendType ET, bool DoShift) {
164 return (unsigned(ET) << 1) | unsigned(DoShift);
165 }
167 static inline uint64_t ror(uint64_t elt, unsigned size) {
168 return ((elt & 1) << (size-1)) | (elt >> 1);
169 }
171 /// processLogicalImmediate - Determine if an immediate value can be encoded
172 /// as the immediate operand of a logical instruction for the given register
173 /// size. If so, return true with "encoding" set to the encoded value in
174 /// the form N:immr:imms.
175 static inline bool processLogicalImmediate(uint64_t imm, unsigned regSize,
176 uint64_t &encoding) {
177 if (imm == 0ULL || imm == ~0ULL ||
178 (regSize != 64 && (imm >> regSize != 0 || imm == ~0U)))
179 return false;
181 unsigned size = 2;
182 uint64_t eltVal = imm;
184 // First, determine the element size.
185 while (size < regSize) {
186 unsigned numElts = regSize / size;
187 unsigned mask = (1ULL << size) - 1;
188 uint64_t lowestEltVal = imm & mask;
190 bool allMatched = true;
191 for (unsigned i = 1; i < numElts; ++i) {
192 uint64_t currEltVal = (imm >> (i*size)) & mask;
193 if (currEltVal != lowestEltVal) {
194 allMatched = false;
195 break;
196 }
197 }
199 if (allMatched) {
200 eltVal = lowestEltVal;
201 break;
202 }
204 size *= 2;
205 }
207 // Second, determine the rotation to make the element be: 0^m 1^n.
208 for (unsigned i = 0; i < size; ++i) {
209 eltVal = ror(eltVal, size);
210 uint32_t clz = countLeadingZeros(eltVal) - (64 - size);
211 uint32_t cto = CountTrailingOnes_64(eltVal);
213 if (clz + cto == size) {
214 // Encode in immr the number of RORs it would take to get *from* this
215 // element value to our target value, where i+1 is the number of RORs
216 // to go the opposite direction.
217 unsigned immr = size - (i + 1);
219 // If size has a 1 in the n'th bit, create a value that has zeroes in
220 // bits [0, n] and ones above that.
221 uint64_t nimms = ~(size-1) << 1;
223 // Or the CTO value into the low bits, which must be below the Nth bit
224 // bit mentioned above.
225 nimms |= (cto-1);
227 // Extract the seventh bit and toggle it to create the N field.
228 unsigned N = ((nimms >> 6) & 1) ^ 1;
230 encoding = (N << 12) | (immr << 6) | (nimms & 0x3f);
231 return true;
232 }
233 }
235 return false;
236 }
238 /// isLogicalImmediate - Return true if the immediate is valid for a logical
239 /// immediate instruction of the given register size. Return false otherwise.
240 static inline bool isLogicalImmediate(uint64_t imm, unsigned regSize) {
241 uint64_t encoding;
242 return processLogicalImmediate(imm, regSize, encoding);
243 }
245 /// encodeLogicalImmediate - Return the encoded immediate value for a logical
246 /// immediate instruction of the given register size.
247 static inline uint64_t encodeLogicalImmediate(uint64_t imm, unsigned regSize) {
248 uint64_t encoding = 0;
249 bool res = processLogicalImmediate(imm, regSize, encoding);
250 assert(res && "invalid logical immediate");
251 (void)res;
252 return encoding;
253 }
255 /// decodeLogicalImmediate - Decode a logical immediate value in the form
256 /// "N:immr:imms" (where the immr and imms fields are each 6 bits) into the
257 /// integer value it represents with regSize bits.
258 static inline uint64_t decodeLogicalImmediate(uint64_t val, unsigned regSize) {
259 // Extract the N, imms, and immr fields.
260 unsigned N = (val >> 12) & 1;
261 unsigned immr = (val >> 6) & 0x3f;
262 unsigned imms = val & 0x3f;
264 assert((regSize == 64 || N == 0) && "undefined logical immediate encoding");
265 int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f));
266 assert(len >= 0 && "undefined logical immediate encoding");
267 unsigned size = (1 << len);
268 unsigned R = immr & (size - 1);
269 unsigned S = imms & (size - 1);
270 assert(S != size - 1 && "undefined logical immediate encoding");
271 uint64_t pattern = (1ULL << (S + 1)) - 1;
272 for (unsigned i = 0; i < R; ++i)
273 pattern = ror(pattern, size);
275 // Replicate the pattern to fill the regSize.
276 while (size != regSize) {
277 pattern |= (pattern << size);
278 size *= 2;
279 }
280 return pattern;
281 }
283 /// isValidDecodeLogicalImmediate - Check to see if the logical immediate value
284 /// in the form "N:immr:imms" (where the immr and imms fields are each 6 bits)
285 /// is a valid encoding for an integer value with regSize bits.
286 static inline bool isValidDecodeLogicalImmediate(uint64_t val,
287 unsigned regSize) {
288 // Extract the N and imms fields needed for checking.
289 unsigned N = (val >> 12) & 1;
290 unsigned imms = val & 0x3f;
292 if (regSize == 32 && N != 0) // undefined logical immediate encoding
293 return false;
294 int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f));
295 if (len < 0) // undefined logical immediate encoding
296 return false;
297 unsigned size = (1 << len);
298 unsigned S = imms & (size - 1);
299 if (S == size - 1) // undefined logical immediate encoding
300 return false;
302 return true;
303 }
305 //===----------------------------------------------------------------------===//
306 // Floating-point Immediates
307 //
308 static inline float getFPImmFloat(unsigned Imm) {
309 // We expect an 8-bit binary encoding of a floating-point number here.
310 union {
311 uint32_t I;
312 float F;
313 } FPUnion;
315 uint8_t Sign = (Imm >> 7) & 0x1;
316 uint8_t Exp = (Imm >> 4) & 0x7;
317 uint8_t Mantissa = Imm & 0xf;
319 // 8-bit FP iEEEE Float Encoding
320 // abcd efgh aBbbbbbc defgh000 00000000 00000000
321 //
322 // where B = NOT(b);
324 FPUnion.I = 0;
325 FPUnion.I |= Sign << 31;
326 FPUnion.I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30;
327 FPUnion.I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25;
328 FPUnion.I |= (Exp & 0x3) << 23;
329 FPUnion.I |= Mantissa << 19;
330 return FPUnion.F;
331 }
333 /// getFP32Imm - Return an 8-bit floating-point version of the 32-bit
334 /// floating-point value. If the value cannot be represented as an 8-bit
335 /// floating-point value, then return -1.
336 static inline int getFP32Imm(const APInt &Imm) {
337 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
338 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
339 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
341 // We can handle 4 bits of mantissa.
342 // mantissa = (16+UInt(e:f:g:h))/16.
343 if (Mantissa & 0x7ffff)
344 return -1;
345 Mantissa >>= 19;
346 if ((Mantissa & 0xf) != Mantissa)
347 return -1;
349 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
350 if (Exp < -3 || Exp > 4)
351 return -1;
352 Exp = ((Exp+3) & 0x7) ^ 4;
354 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
355 }
357 static inline int getFP32Imm(const APFloat &FPImm) {
358 return getFP32Imm(FPImm.bitcastToAPInt());
359 }
361 /// getFP64Imm - Return an 8-bit floating-point version of the 64-bit
362 /// floating-point value. If the value cannot be represented as an 8-bit
363 /// floating-point value, then return -1.
364 static inline int getFP64Imm(const APInt &Imm) {
365 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
366 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
367 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffULL;
369 // We can handle 4 bits of mantissa.
370 // mantissa = (16+UInt(e:f:g:h))/16.
371 if (Mantissa & 0xffffffffffffULL)
372 return -1;
373 Mantissa >>= 48;
374 if ((Mantissa & 0xf) != Mantissa)
375 return -1;
377 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
378 if (Exp < -3 || Exp > 4)
379 return -1;
380 Exp = ((Exp+3) & 0x7) ^ 4;
382 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
383 }
385 static inline int getFP64Imm(const APFloat &FPImm) {
386 return getFP64Imm(FPImm.bitcastToAPInt());
387 }
389 //===--------------------------------------------------------------------===//
390 // AdvSIMD Modified Immediates
391 //===--------------------------------------------------------------------===//
393 // 0x00 0x00 0x00 abcdefgh 0x00 0x00 0x00 abcdefgh
394 static inline bool isAdvSIMDModImmType1(uint64_t Imm) {
395 return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
396 ((Imm & 0xffffff00ffffff00ULL) == 0);
397 }
399 static inline uint8_t encodeAdvSIMDModImmType1(uint64_t Imm) {
400 return (Imm & 0xffULL);
401 }
403 static inline uint64_t decodeAdvSIMDModImmType1(uint8_t Imm) {
404 uint64_t EncVal = Imm;
405 return (EncVal << 32) | EncVal;
406 }
408 // 0x00 0x00 abcdefgh 0x00 0x00 0x00 abcdefgh 0x00
409 static inline bool isAdvSIMDModImmType2(uint64_t Imm) {
410 return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
411 ((Imm & 0xffff00ffffff00ffULL) == 0);
412 }
414 static inline uint8_t encodeAdvSIMDModImmType2(uint64_t Imm) {
415 return (Imm & 0xff00ULL) >> 8;
416 }
418 static inline uint64_t decodeAdvSIMDModImmType2(uint8_t Imm) {
419 uint64_t EncVal = Imm;
420 return (EncVal << 40) | (EncVal << 8);
421 }
423 // 0x00 abcdefgh 0x00 0x00 0x00 abcdefgh 0x00 0x00
424 static inline bool isAdvSIMDModImmType3(uint64_t Imm) {
425 return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
426 ((Imm & 0xff00ffffff00ffffULL) == 0);
427 }
429 static inline uint8_t encodeAdvSIMDModImmType3(uint64_t Imm) {
430 return (Imm & 0xff0000ULL) >> 16;
431 }
433 static inline uint64_t decodeAdvSIMDModImmType3(uint8_t Imm) {
434 uint64_t EncVal = Imm;
435 return (EncVal << 48) | (EncVal << 16);
436 }
438 // abcdefgh 0x00 0x00 0x00 abcdefgh 0x00 0x00 0x00
439 static inline bool isAdvSIMDModImmType4(uint64_t Imm) {
440 return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
441 ((Imm & 0x00ffffff00ffffffULL) == 0);
442 }
444 static inline uint8_t encodeAdvSIMDModImmType4(uint64_t Imm) {
445 return (Imm & 0xff000000ULL) >> 24;
446 }
448 static inline uint64_t decodeAdvSIMDModImmType4(uint8_t Imm) {
449 uint64_t EncVal = Imm;
450 return (EncVal << 56) | (EncVal << 24);
451 }
453 // 0x00 abcdefgh 0x00 abcdefgh 0x00 abcdefgh 0x00 abcdefgh
454 static inline bool isAdvSIMDModImmType5(uint64_t Imm) {
455 return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
456 (((Imm & 0x00ff0000ULL) >> 16) == (Imm & 0x000000ffULL)) &&
457 ((Imm & 0xff00ff00ff00ff00ULL) == 0);
458 }
460 static inline uint8_t encodeAdvSIMDModImmType5(uint64_t Imm) {
461 return (Imm & 0xffULL);
462 }
464 static inline uint64_t decodeAdvSIMDModImmType5(uint8_t Imm) {
465 uint64_t EncVal = Imm;
466 return (EncVal << 48) | (EncVal << 32) | (EncVal << 16) | EncVal;
467 }
469 // abcdefgh 0x00 abcdefgh 0x00 abcdefgh 0x00 abcdefgh 0x00
470 static inline bool isAdvSIMDModImmType6(uint64_t Imm) {
471 return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
472 (((Imm & 0xff000000ULL) >> 16) == (Imm & 0x0000ff00ULL)) &&
473 ((Imm & 0x00ff00ff00ff00ffULL) == 0);
474 }
476 static inline uint8_t encodeAdvSIMDModImmType6(uint64_t Imm) {
477 return (Imm & 0xff00ULL) >> 8;
478 }
480 static inline uint64_t decodeAdvSIMDModImmType6(uint8_t Imm) {
481 uint64_t EncVal = Imm;
482 return (EncVal << 56) | (EncVal << 40) | (EncVal << 24) | (EncVal << 8);
483 }
485 // 0x00 0x00 abcdefgh 0xFF 0x00 0x00 abcdefgh 0xFF
486 static inline bool isAdvSIMDModImmType7(uint64_t Imm) {
487 return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
488 ((Imm & 0xffff00ffffff00ffULL) == 0x000000ff000000ffULL);
489 }
491 static inline uint8_t encodeAdvSIMDModImmType7(uint64_t Imm) {
492 return (Imm & 0xff00ULL) >> 8;
493 }
495 static inline uint64_t decodeAdvSIMDModImmType7(uint8_t Imm) {
496 uint64_t EncVal = Imm;
497 return (EncVal << 40) | (EncVal << 8) | 0x000000ff000000ffULL;
498 }
500 // 0x00 abcdefgh 0xFF 0xFF 0x00 abcdefgh 0xFF 0xFF
501 static inline bool isAdvSIMDModImmType8(uint64_t Imm) {
502 return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
503 ((Imm & 0xff00ffffff00ffffULL) == 0x0000ffff0000ffffULL);
504 }
506 static inline uint64_t decodeAdvSIMDModImmType8(uint8_t Imm) {
507 uint64_t EncVal = Imm;
508 return (EncVal << 48) | (EncVal << 16) | 0x0000ffff0000ffffULL;
509 }
511 static inline uint8_t encodeAdvSIMDModImmType8(uint64_t Imm) {
512 return (Imm & 0x00ff0000ULL) >> 16;
513 }
515 // abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh
516 static inline bool isAdvSIMDModImmType9(uint64_t Imm) {
517 return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
518 ((Imm >> 48) == (Imm & 0x0000ffffULL)) &&
519 ((Imm >> 56) == (Imm & 0x000000ffULL));
520 }
522 static inline uint8_t encodeAdvSIMDModImmType9(uint64_t Imm) {
523 return (Imm & 0xffULL);
524 }
526 static inline uint64_t decodeAdvSIMDModImmType9(uint8_t Imm) {
527 uint64_t EncVal = Imm;
528 EncVal |= (EncVal << 8);
529 EncVal |= (EncVal << 16);
530 EncVal |= (EncVal << 32);
531 return EncVal;
532 }
534 // aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh
535 // cmode: 1110, op: 1
536 static inline bool isAdvSIMDModImmType10(uint64_t Imm) {
537 uint64_t ByteA = Imm & 0xff00000000000000ULL;
538 uint64_t ByteB = Imm & 0x00ff000000000000ULL;
539 uint64_t ByteC = Imm & 0x0000ff0000000000ULL;
540 uint64_t ByteD = Imm & 0x000000ff00000000ULL;
541 uint64_t ByteE = Imm & 0x00000000ff000000ULL;
542 uint64_t ByteF = Imm & 0x0000000000ff0000ULL;
543 uint64_t ByteG = Imm & 0x000000000000ff00ULL;
544 uint64_t ByteH = Imm & 0x00000000000000ffULL;
546 return (ByteA == 0ULL || ByteA == 0xff00000000000000ULL) &&
547 (ByteB == 0ULL || ByteB == 0x00ff000000000000ULL) &&
548 (ByteC == 0ULL || ByteC == 0x0000ff0000000000ULL) &&
549 (ByteD == 0ULL || ByteD == 0x000000ff00000000ULL) &&
550 (ByteE == 0ULL || ByteE == 0x00000000ff000000ULL) &&
551 (ByteF == 0ULL || ByteF == 0x0000000000ff0000ULL) &&
552 (ByteG == 0ULL || ByteG == 0x000000000000ff00ULL) &&
553 (ByteH == 0ULL || ByteH == 0x00000000000000ffULL);
554 }
556 static inline uint8_t encodeAdvSIMDModImmType10(uint64_t Imm) {
557 uint8_t BitA = (Imm & 0xff00000000000000ULL) != 0;
558 uint8_t BitB = (Imm & 0x00ff000000000000ULL) != 0;
559 uint8_t BitC = (Imm & 0x0000ff0000000000ULL) != 0;
560 uint8_t BitD = (Imm & 0x000000ff00000000ULL) != 0;
561 uint8_t BitE = (Imm & 0x00000000ff000000ULL) != 0;
562 uint8_t BitF = (Imm & 0x0000000000ff0000ULL) != 0;
563 uint8_t BitG = (Imm & 0x000000000000ff00ULL) != 0;
564 uint8_t BitH = (Imm & 0x00000000000000ffULL) != 0;
566 uint8_t EncVal = BitA;
567 EncVal <<= 1;
568 EncVal |= BitB;
569 EncVal <<= 1;
570 EncVal |= BitC;
571 EncVal <<= 1;
572 EncVal |= BitD;
573 EncVal <<= 1;
574 EncVal |= BitE;
575 EncVal <<= 1;
576 EncVal |= BitF;
577 EncVal <<= 1;
578 EncVal |= BitG;
579 EncVal <<= 1;
580 EncVal |= BitH;
581 return EncVal;
582 }
584 static inline uint64_t decodeAdvSIMDModImmType10(uint8_t Imm) {
585 uint64_t EncVal = 0;
586 if (Imm & 0x80) EncVal |= 0xff00000000000000ULL;
587 if (Imm & 0x40) EncVal |= 0x00ff000000000000ULL;
588 if (Imm & 0x20) EncVal |= 0x0000ff0000000000ULL;
589 if (Imm & 0x10) EncVal |= 0x000000ff00000000ULL;
590 if (Imm & 0x08) EncVal |= 0x00000000ff000000ULL;
591 if (Imm & 0x04) EncVal |= 0x0000000000ff0000ULL;
592 if (Imm & 0x02) EncVal |= 0x000000000000ff00ULL;
593 if (Imm & 0x01) EncVal |= 0x00000000000000ffULL;
594 return EncVal;
595 }
597 // aBbbbbbc defgh000 0x00 0x00 aBbbbbbc defgh000 0x00 0x00
598 static inline bool isAdvSIMDModImmType11(uint64_t Imm) {
599 uint64_t BString = (Imm & 0x7E000000ULL) >> 25;
600 return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
601 (BString == 0x1f || BString == 0x20) &&
602 ((Imm & 0x0007ffff0007ffffULL) == 0);
603 }
605 static inline uint8_t encodeAdvSIMDModImmType11(uint64_t Imm) {
606 uint8_t BitA = (Imm & 0x80000000ULL) != 0;
607 uint8_t BitB = (Imm & 0x20000000ULL) != 0;
608 uint8_t BitC = (Imm & 0x01000000ULL) != 0;
609 uint8_t BitD = (Imm & 0x00800000ULL) != 0;
610 uint8_t BitE = (Imm & 0x00400000ULL) != 0;
611 uint8_t BitF = (Imm & 0x00200000ULL) != 0;
612 uint8_t BitG = (Imm & 0x00100000ULL) != 0;
613 uint8_t BitH = (Imm & 0x00080000ULL) != 0;
615 uint8_t EncVal = BitA;
616 EncVal <<= 1;
617 EncVal |= BitB;
618 EncVal <<= 1;
619 EncVal |= BitC;
620 EncVal <<= 1;
621 EncVal |= BitD;
622 EncVal <<= 1;
623 EncVal |= BitE;
624 EncVal <<= 1;
625 EncVal |= BitF;
626 EncVal <<= 1;
627 EncVal |= BitG;
628 EncVal <<= 1;
629 EncVal |= BitH;
630 return EncVal;
631 }
633 static inline uint64_t decodeAdvSIMDModImmType11(uint8_t Imm) {
634 uint64_t EncVal = 0;
635 if (Imm & 0x80) EncVal |= 0x80000000ULL;
636 if (Imm & 0x40) EncVal |= 0x3e000000ULL;
637 else EncVal |= 0x40000000ULL;
638 if (Imm & 0x20) EncVal |= 0x01000000ULL;
639 if (Imm & 0x10) EncVal |= 0x00800000ULL;
640 if (Imm & 0x08) EncVal |= 0x00400000ULL;
641 if (Imm & 0x04) EncVal |= 0x00200000ULL;
642 if (Imm & 0x02) EncVal |= 0x00100000ULL;
643 if (Imm & 0x01) EncVal |= 0x00080000ULL;
644 return (EncVal << 32) | EncVal;
645 }
647 // aBbbbbbb bbcdefgh 0x00 0x00 0x00 0x00 0x00 0x00
648 static inline bool isAdvSIMDModImmType12(uint64_t Imm) {
649 uint64_t BString = (Imm & 0x7fc0000000000000ULL) >> 54;
650 return ((BString == 0xff || BString == 0x100) &&
651 ((Imm & 0x0000ffffffffffffULL) == 0));
652 }
654 static inline uint8_t encodeAdvSIMDModImmType12(uint64_t Imm) {
655 uint8_t BitA = (Imm & 0x8000000000000000ULL) != 0;
656 uint8_t BitB = (Imm & 0x0040000000000000ULL) != 0;
657 uint8_t BitC = (Imm & 0x0020000000000000ULL) != 0;
658 uint8_t BitD = (Imm & 0x0010000000000000ULL) != 0;
659 uint8_t BitE = (Imm & 0x0008000000000000ULL) != 0;
660 uint8_t BitF = (Imm & 0x0004000000000000ULL) != 0;
661 uint8_t BitG = (Imm & 0x0002000000000000ULL) != 0;
662 uint8_t BitH = (Imm & 0x0001000000000000ULL) != 0;
664 uint8_t EncVal = BitA;
665 EncVal <<= 1;
666 EncVal |= BitB;
667 EncVal <<= 1;
668 EncVal |= BitC;
669 EncVal <<= 1;
670 EncVal |= BitD;
671 EncVal <<= 1;
672 EncVal |= BitE;
673 EncVal <<= 1;
674 EncVal |= BitF;
675 EncVal <<= 1;
676 EncVal |= BitG;
677 EncVal <<= 1;
678 EncVal |= BitH;
679 return EncVal;
680 }
682 static inline uint64_t decodeAdvSIMDModImmType12(uint8_t Imm) {
683 uint64_t EncVal = 0;
684 if (Imm & 0x80) EncVal |= 0x8000000000000000ULL;
685 if (Imm & 0x40) EncVal |= 0x3fc0000000000000ULL;
686 else EncVal |= 0x4000000000000000ULL;
687 if (Imm & 0x20) EncVal |= 0x0020000000000000ULL;
688 if (Imm & 0x10) EncVal |= 0x0010000000000000ULL;
689 if (Imm & 0x08) EncVal |= 0x0008000000000000ULL;
690 if (Imm & 0x04) EncVal |= 0x0004000000000000ULL;
691 if (Imm & 0x02) EncVal |= 0x0002000000000000ULL;
692 if (Imm & 0x01) EncVal |= 0x0001000000000000ULL;
693 return (EncVal << 32) | EncVal;
694 }
696 } // end namespace ARM64_AM
698 } // end namespace llvm
700 #endif