00b5068d3f8b9c515e051d273f15f0c040ffa071
1 //==- HexagonRegisterInfo.h - Hexagon Register Information Impl --*- C++ -*-==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Hexagon implementation of the TargetRegisterInfo
11 // class.
12 //
13 //===----------------------------------------------------------------------===//
15 #ifndef HexagonREGISTERINFO_H
16 #define HexagonREGISTERINFO_H
18 #include "llvm/MC/MachineLocation.h"
19 #include "llvm/Target/TargetRegisterInfo.h"
21 #define GET_REGINFO_HEADER
22 #include "HexagonGenRegisterInfo.inc"
24 //
25 // We try not to hard code the reserved registers in our code,
26 // so the following two macros were defined. However, there
27 // are still a few places that R11 and R10 are hard wired.
28 // See below. If, in the future, we decided to change the reserved
29 // register. Don't forget changing the following places.
30 //
31 // 1. the "Defs" set of STriw_pred in HexagonInstrInfo.td
32 // 2. the "Defs" set of LDri_pred in HexagonInstrInfo.td
33 // 3. the definition of "IntRegs" in HexagonRegisterInfo.td
34 // 4. the definition of "DoubleRegs" in HexagonRegisterInfo.td
35 //
36 #define HEXAGON_RESERVED_REG_1 Hexagon::R10
37 #define HEXAGON_RESERVED_REG_2 Hexagon::R11
39 namespace llvm {
41 class HexagonSubtarget;
42 class HexagonInstrInfo;
43 class Type;
45 struct HexagonRegisterInfo : public HexagonGenRegisterInfo {
46 HexagonSubtarget &Subtarget;
48 HexagonRegisterInfo(HexagonSubtarget &st);
50 /// Code Generation virtual methods...
51 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
53 const TargetRegisterClass* const* getCalleeSavedRegClasses(
54 const MachineFunction *MF = 0) const;
56 BitVector getReservedRegs(const MachineFunction &MF) const;
58 void eliminateFrameIndex(MachineBasicBlock::iterator II,
59 int SPAdj, unsigned FIOperandNum,
60 RegScavenger *RS = NULL) const;
62 /// determineFrameLayout - Determine the size of the frame and maximum call
63 /// frame size.
64 void determineFrameLayout(MachineFunction &MF) const;
66 /// requiresRegisterScavenging - returns true since we may need scavenging for
67 /// a temporary register when generating hardware loop instructions.
68 bool requiresRegisterScavenging(const MachineFunction &MF) const {
69 return true;
70 }
72 bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
73 return true;
74 }
76 // Debug information queries.
77 unsigned getRARegister() const;
78 unsigned getFrameRegister(const MachineFunction &MF) const;
79 unsigned getFrameRegister() const;
80 unsigned getStackRegister() const;
81 };
83 } // end namespace llvm
85 #endif