1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that PPC uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
16 #define LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
18 #include "PPC.h"
19 #include "PPCInstrInfo.h"
20 #include "PPCRegisterInfo.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/Target/TargetLowering.h"
25 namespace llvm {
26 namespace PPCISD {
27 enum NodeType {
28 // Start the numbering where the builtin ops and target ops leave off.
29 FIRST_NUMBER = ISD::BUILTIN_OP_END,
31 /// FSEL - Traditional three-operand fsel node.
32 ///
33 FSEL,
35 /// FCFID - The FCFID instruction, taking an f64 operand and producing
36 /// and f64 value containing the FP representation of the integer that
37 /// was temporarily in the f64 operand.
38 FCFID,
40 /// Newer FCFID[US] integer-to-floating-point conversion instructions for
41 /// unsigned integers and single-precision outputs.
42 FCFIDU, FCFIDS, FCFIDUS,
44 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
45 /// operand, producing an f64 value containing the integer representation
46 /// of that FP value.
47 FCTIDZ, FCTIWZ,
49 /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for
50 /// unsigned integers.
51 FCTIDUZ, FCTIWUZ,
53 /// Reciprocal estimate instructions (unary FP ops).
54 FRE, FRSQRTE,
56 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
57 // three v4f32 operands and producing a v4f32 result.
58 VMADDFP, VNMSUBFP,
60 /// VPERM - The PPC VPERM Instruction.
61 ///
62 VPERM,
64 /// The CMPB instruction (takes two operands of i32 or i64).
65 CMPB,
67 /// Hi/Lo - These represent the high and low 16-bit parts of a global
68 /// address respectively. These nodes have two operands, the first of
69 /// which must be a TargetGlobalAddress, and the second of which must be a
70 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
71 /// though these are usually folded into other nodes.
72 Hi, Lo,
74 TOC_ENTRY,
76 /// The following two target-specific nodes are used for calls through
77 /// function pointers in the 64-bit SVR4 ABI.
79 /// Like a regular LOAD but additionally taking/producing a flag.
80 LOAD,
82 /// Like LOAD (taking/producing a flag), but using r2 as hard-coded
83 /// destination.
84 LOAD_TOC,
86 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
87 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
88 /// compute an allocation on the stack.
89 DYNALLOC,
91 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
92 /// at function entry, used for PIC code.
93 GlobalBaseReg,
95 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit
96 /// shift amounts. These nodes are generated by the multi-precision shift
97 /// code.
98 SRL, SRA, SHL,
100 /// The combination of sra[wd]i and addze used to implemented signed
101 /// integer division by a power of 2. The first operand is the dividend,
102 /// and the second is the constant shift amount (representing the
103 /// divisor).
104 SRA_ADDZE,
106 /// CALL - A direct function call.
107 /// CALL_NOP is a call with the special NOP which follows 64-bit
108 /// SVR4 calls.
109 CALL, CALL_NOP,
111 /// CALL_TLS and CALL_NOP_TLS - Versions of CALL and CALL_NOP used
112 /// to access TLS variables.
113 CALL_TLS, CALL_NOP_TLS,
115 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
116 /// MTCTR instruction.
117 MTCTR,
119 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
120 /// BCTRL instruction.
121 BCTRL,
123 /// CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl
124 /// instruction and the TOC reload required on SVR4 PPC64.
125 BCTRL_LOAD_TOC,
127 /// Return with a flag operand, matched by 'blr'
128 RET_FLAG,
130 /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
131 /// This copies the bits corresponding to the specified CRREG into the
132 /// resultant GPR. Bits corresponding to other CR regs are undefined.
133 MFOCRF,
135 // FIXME: Remove these once the ANDI glue bug is fixed:
136 /// i1 = ANDIo_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the
137 /// eq or gt bit of CR0 after executing andi. x, 1. This is used to
138 /// implement truncation of i32 or i64 to i1.
139 ANDIo_1_EQ_BIT, ANDIo_1_GT_BIT,
141 // READ_TIME_BASE - A read of the 64-bit time-base register on a 32-bit
142 // target (returns (Lo, Hi)). It takes a chain operand.
143 READ_TIME_BASE,
145 // EH_SJLJ_SETJMP - SjLj exception handling setjmp.
146 EH_SJLJ_SETJMP,
148 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
149 EH_SJLJ_LONGJMP,
151 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
152 /// instructions. For lack of better number, we use the opcode number
153 /// encoding for the OPC field to identify the compare. For example, 838
154 /// is VCMPGTSH.
155 VCMP,
157 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
158 /// altivec VCMP*o instructions. For lack of better number, we use the
159 /// opcode number encoding for the OPC field to identify the compare. For
160 /// example, 838 is VCMPGTSH.
161 VCMPo,
163 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
164 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
165 /// condition register to branch on, OPC is the branch opcode to use (e.g.
166 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
167 /// an optional input flag argument.
168 COND_BRANCH,
170 /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based
171 /// loops.
172 BDNZ, BDZ,
174 /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding
175 /// towards zero. Used only as part of the long double-to-int
176 /// conversion sequence.
177 FADDRTZ,
179 /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
180 MFFS,
182 /// LARX = This corresponds to PPC l{w|d}arx instrcution: load and
183 /// reserve indexed. This is used to implement atomic operations.
184 LARX,
186 /// STCX = This corresponds to PPC stcx. instrcution: store conditional
187 /// indexed. This is used to implement atomic operations.
188 STCX,
190 /// TC_RETURN - A tail call return.
191 /// operand #0 chain
192 /// operand #1 callee (register or absolute)
193 /// operand #2 stack adjustment
194 /// operand #3 optional in flag
195 TC_RETURN,
197 /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
198 CR6SET,
199 CR6UNSET,
201 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS
202 /// on PPC32.
203 PPC32_GOT,
205 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by general dynamic and
206 /// local dynamic TLS on PPC32.
207 PPC32_PICGOT,
209 /// G8RC = ADDIS_GOT_TPREL_HA %X2, Symbol - Used by the initial-exec
210 /// TLS model, produces an ADDIS8 instruction that adds the GOT
211 /// base to sym\@got\@tprel\@ha.
212 ADDIS_GOT_TPREL_HA,
214 /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec
215 /// TLS model, produces a LD instruction with base register G8RReg
216 /// and offset sym\@got\@tprel\@l. This completes the addition that
217 /// finds the offset of "sym" relative to the thread pointer.
218 LD_GOT_TPREL_L,
220 /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS
221 /// model, produces an ADD instruction that adds the contents of
222 /// G8RReg to the thread pointer. Symbol contains a relocation
223 /// sym\@tls which is to be replaced by the thread pointer and
224 /// identifies to the linker that the instruction is part of a
225 /// TLS sequence.
226 ADD_TLS,
228 /// G8RC = ADDIS_TLSGD_HA %X2, Symbol - For the general-dynamic TLS
229 /// model, produces an ADDIS8 instruction that adds the GOT base
230 /// register to sym\@got\@tlsgd\@ha.
231 ADDIS_TLSGD_HA,
233 /// G8RC = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS
234 /// model, produces an ADDI8 instruction that adds G8RReg to
235 /// sym\@got\@tlsgd\@l.
236 ADDI_TLSGD_L,
238 /// G8RC = ADDIS_TLSLD_HA %X2, Symbol - For the local-dynamic TLS
239 /// model, produces an ADDIS8 instruction that adds the GOT base
240 /// register to sym\@got\@tlsld\@ha.
241 ADDIS_TLSLD_HA,
243 /// G8RC = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS
244 /// model, produces an ADDI8 instruction that adds G8RReg to
245 /// sym\@got\@tlsld\@l.
246 ADDI_TLSLD_L,
248 /// G8RC = ADDIS_DTPREL_HA %X3, Symbol, Chain - For the
249 /// local-dynamic TLS model, produces an ADDIS8 instruction
250 /// that adds X3 to sym\@dtprel\@ha. The Chain operand is needed
251 /// to tie this in place following a copy to %X3 from the result
252 /// of a GET_TLSLD_ADDR.
253 ADDIS_DTPREL_HA,
255 /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS
256 /// model, produces an ADDI8 instruction that adds G8RReg to
257 /// sym\@got\@dtprel\@l.
258 ADDI_DTPREL_L,
260 /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded
261 /// during instruction selection to optimize a BUILD_VECTOR into
262 /// operations on splats. This is necessary to avoid losing these
263 /// optimizations due to constant folding.
264 VADD_SPLAT,
266 /// CHAIN = SC CHAIN, Imm128 - System call. The 7-bit unsigned
267 /// operand identifies the operating system entry point.
268 SC,
270 /// VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little
271 /// endian. Maps to an xxswapd instruction that corrects an lxvd2x
272 /// or stxvd2x instruction. The chain is necessary because the
273 /// sequence replaces a load and needs to provide the same number
274 /// of outputs.
275 XXSWAPD,
277 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
278 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of
279 /// the GPRC input, then stores it through Ptr. Type can be either i16 or
280 /// i32.
281 STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE,
283 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
284 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
285 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16
286 /// or i32.
287 LBRX,
289 /// STFIWX - The STFIWX instruction. The first operand is an input token
290 /// chain, then an f64 value to store, then an address to store it to.
291 STFIWX,
293 /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point
294 /// load which sign-extends from a 32-bit integer value into the
295 /// destination 64-bit register.
296 LFIWAX,
298 /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point
299 /// load which zero-extends from a 32-bit integer value into the
300 /// destination 64-bit register.
301 LFIWZX,
303 /// G8RC = ADDIS_TOC_HA %X2, Symbol - For medium and large code model,
304 /// produces an ADDIS8 instruction that adds the TOC base register to
305 /// sym\@toc\@ha.
306 ADDIS_TOC_HA,
308 /// G8RC = LD_TOC_L Symbol, G8RReg - For medium and large code model,
309 /// produces a LD instruction with base register G8RReg and offset
310 /// sym\@toc\@l. Preceded by an ADDIS_TOC_HA to form a full 32-bit offset.
311 LD_TOC_L,
313 /// G8RC = ADDI_TOC_L G8RReg, Symbol - For medium code model, produces
314 /// an ADDI8 instruction that adds G8RReg to sym\@toc\@l.
315 /// Preceded by an ADDIS_TOC_HA to form a full 32-bit offset.
316 ADDI_TOC_L,
318 /// VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
319 /// Maps directly to an lxvd2x instruction that will be followed by
320 /// an xxswapd.
321 LXVD2X,
323 /// CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
324 /// Maps directly to an stxvd2x instruction that will be preceded by
325 /// an xxswapd.
326 STXVD2X
327 };
328 }
330 /// Define some predicates that are used for node matching.
331 namespace PPC {
332 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
333 /// VPKUHUM instruction.
334 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
335 SelectionDAG &DAG);
337 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
338 /// VPKUWUM instruction.
339 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
340 SelectionDAG &DAG);
342 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
343 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
344 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
345 unsigned ShuffleKind, SelectionDAG &DAG);
347 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
348 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
349 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
350 unsigned ShuffleKind, SelectionDAG &DAG);
352 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the
353 /// shift amount, otherwise return -1.
354 int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
355 SelectionDAG &DAG);
357 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
358 /// specifies a splat of a single element that is suitable for input to
359 /// VSPLTB/VSPLTH/VSPLTW.
360 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
362 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
363 /// are -0.0.
364 bool isAllNegativeZeroVector(SDNode *N);
366 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
367 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
368 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize, SelectionDAG &DAG);
370 /// get_VSPLTI_elt - If this is a build_vector of constants which can be
371 /// formed by using a vspltis[bhw] instruction of the specified element
372 /// size, return the constant being splatted. The ByteSize field indicates
373 /// the number of bytes of each element [124] -> [bhw].
374 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
375 }
377 class PPCSubtarget;
378 class PPCTargetLowering : public TargetLowering {
379 const PPCSubtarget &Subtarget;
381 public:
382 explicit PPCTargetLowering(const PPCTargetMachine &TM);
384 /// getTargetNodeName() - This method returns the name of a target specific
385 /// DAG node.
386 const char *getTargetNodeName(unsigned Opcode) const override;
388 MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; }
390 bool isCheapToSpeculateCttz() const override {
391 return true;
392 }
394 bool isCheapToSpeculateCtlz() const override {
395 return true;
396 }
398 /// getSetCCResultType - Return the ISD::SETCC ValueType
399 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
401 /// Return true if target always beneficiates from combining into FMA for a
402 /// given value type. This must typically return false on targets where FMA
403 /// takes more cycles to execute than FADD.
404 bool enableAggressiveFMAFusion(EVT VT) const override;
406 /// getPreIndexedAddressParts - returns true by value, base pointer and
407 /// offset pointer and addressing mode by reference if the node's address
408 /// can be legally represented as pre-indexed load / store address.
409 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
410 SDValue &Offset,
411 ISD::MemIndexedMode &AM,
412 SelectionDAG &DAG) const override;
414 /// SelectAddressRegReg - Given the specified addressed, check to see if it
415 /// can be represented as an indexed [r+r] operation. Returns false if it
416 /// can be more efficiently represented with [r+imm].
417 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
418 SelectionDAG &DAG) const;
420 /// SelectAddressRegImm - Returns true if the address N can be represented
421 /// by a base register plus a signed 16-bit displacement [r+imm], and if it
422 /// is not better represented as reg+reg. If Aligned is true, only accept
423 /// displacements suitable for STD and friends, i.e. multiples of 4.
424 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
425 SelectionDAG &DAG, bool Aligned) const;
427 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
428 /// represented as an indexed [r+r] operation.
429 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
430 SelectionDAG &DAG) const;
432 Sched::Preference getSchedulingPreference(SDNode *N) const override;
434 /// LowerOperation - Provide custom lowering hooks for some operations.
435 ///
436 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
438 /// ReplaceNodeResults - Replace the results of node with an illegal result
439 /// type with new values built out of custom code.
440 ///
441 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
442 SelectionDAG &DAG) const override;
444 SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const;
445 SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const;
447 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
449 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
450 std::vector<SDNode *> *Created) const override;
452 unsigned getRegisterByName(const char* RegName, EVT VT) const override;
454 void computeKnownBitsForTargetNode(const SDValue Op,
455 APInt &KnownZero,
456 APInt &KnownOne,
457 const SelectionDAG &DAG,
458 unsigned Depth = 0) const override;
460 unsigned getPrefLoopAlignment(MachineLoop *ML) const override;
462 Instruction* emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
463 bool IsStore, bool IsLoad) const override;
464 Instruction* emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
465 bool IsStore, bool IsLoad) const override;
467 MachineBasicBlock *
468 EmitInstrWithCustomInserter(MachineInstr *MI,
469 MachineBasicBlock *MBB) const override;
470 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
471 MachineBasicBlock *MBB, bool is64Bit,
472 unsigned BinOpcode) const;
473 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI,
474 MachineBasicBlock *MBB,
475 bool is8bit, unsigned Opcode) const;
477 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
478 MachineBasicBlock *MBB) const;
480 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
481 MachineBasicBlock *MBB) const;
483 ConstraintType
484 getConstraintType(const std::string &Constraint) const override;
486 /// Examine constraint string and operand type and determine a weight value.
487 /// The operand object must already have been set up with the operand type.
488 ConstraintWeight getSingleConstraintMatchWeight(
489 AsmOperandInfo &info, const char *constraint) const override;
491 std::pair<unsigned, const TargetRegisterClass*>
492 getRegForInlineAsmConstraint(const std::string &Constraint,
493 MVT VT) const override;
495 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
496 /// function arguments in the caller parameter area. This is the actual
497 /// alignment, not its logarithm.
498 unsigned getByValTypeAlignment(Type *Ty) const override;
500 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
501 /// vector. If it is invalid, don't add anything to Ops.
502 void LowerAsmOperandForConstraint(SDValue Op,
503 std::string &Constraint,
504 std::vector<SDValue> &Ops,
505 SelectionDAG &DAG) const override;
507 /// isLegalAddressingMode - Return true if the addressing mode represented
508 /// by AM is legal for this target, for a load/store of the specified type.
509 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
511 /// isLegalICmpImmediate - Return true if the specified immediate is legal
512 /// icmp immediate, that is the target has icmp instructions which can
513 /// compare a register against the immediate without having to materialize
514 /// the immediate into a register.
515 bool isLegalICmpImmediate(int64_t Imm) const override;
517 /// isLegalAddImmediate - Return true if the specified immediate is legal
518 /// add immediate, that is the target has add instructions which can
519 /// add a register and the immediate without having to materialize
520 /// the immediate into a register.
521 bool isLegalAddImmediate(int64_t Imm) const override;
523 /// isTruncateFree - Return true if it's free to truncate a value of
524 /// type Ty1 to type Ty2. e.g. On PPC it's free to truncate a i64 value in
525 /// register X1 to i32 by referencing its sub-register R1.
526 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
527 bool isTruncateFree(EVT VT1, EVT VT2) const override;
529 bool isZExtFree(SDValue Val, EVT VT2) const override;
531 /// \brief Returns true if it is beneficial to convert a load of a constant
532 /// to just the constant itself.
533 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
534 Type *Ty) const override;
536 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
538 bool getTgtMemIntrinsic(IntrinsicInfo &Info,
539 const CallInst &I,
540 unsigned Intrinsic) const override;
542 /// getOptimalMemOpType - Returns the target specific optimal type for load
543 /// and store operations as a result of memset, memcpy, and memmove
544 /// lowering. If DstAlign is zero that means it's safe to destination
545 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
546 /// means there isn't a need to check it against alignment requirement,
547 /// probably because the source does not need to be loaded. If 'IsMemset' is
548 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
549 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
550 /// source is constant so it does not need to be loaded.
551 /// It returns EVT::Other if the type should be determined using generic
552 /// target-independent logic.
553 EVT
554 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
555 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
556 MachineFunction &MF) const override;
558 /// Is unaligned memory access allowed for the given type, and is it fast
559 /// relative to software emulation.
560 bool allowsMisalignedMemoryAccesses(EVT VT,
561 unsigned AddrSpace,
562 unsigned Align = 1,
563 bool *Fast = nullptr) const override;
565 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
566 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
567 /// expanded to FMAs when this method returns true, otherwise fmuladd is
568 /// expanded to fmul + fadd.
569 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
571 // Should we expand the build vector with shuffles?
572 bool
573 shouldExpandBuildVectorWithShuffles(EVT VT,
574 unsigned DefinedValues) const override;
576 /// createFastISel - This method returns a target-specific FastISel object,
577 /// or null if the target does not support "fast" instruction selection.
578 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
579 const TargetLibraryInfo *LibInfo) const override;
581 /// \brief Returns true if an argument of type Ty needs to be passed in a
582 /// contiguous block of registers in calling convention CallConv.
583 bool functionArgumentNeedsConsecutiveRegisters(
584 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override {
585 // We support any array type as "consecutive" block in the parameter
586 // save area. The element type defines the alignment requirement and
587 // whether the argument should go in GPRs, FPRs, or VRs if available.
588 //
589 // Note that clang uses this capability both to implement the ELFv2
590 // homogeneous float/vector aggregate ABI, and to avoid having to use
591 // "byval" when passing aggregates that might fully fit in registers.
592 return Ty->isArrayTy();
593 }
595 private:
597 struct ReuseLoadInfo {
598 SDValue Ptr;
599 SDValue Chain;
600 SDValue ResChain;
601 MachinePointerInfo MPI;
602 bool IsInvariant;
603 unsigned Alignment;
604 AAMDNodes AAInfo;
605 const MDNode *Ranges;
607 ReuseLoadInfo() : IsInvariant(false), Alignment(0), Ranges(nullptr) {}
608 };
610 bool canReuseLoadAddress(SDValue Op, EVT MemVT, ReuseLoadInfo &RLI,
611 SelectionDAG &DAG,
612 ISD::LoadExtType ET = ISD::NON_EXTLOAD) const;
613 void spliceIntoChain(SDValue ResChain, SDValue NewResChain,
614 SelectionDAG &DAG) const;
616 void LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
617 SelectionDAG &DAG, SDLoc dl) const;
619 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
620 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
622 bool
623 IsEligibleForTailCallOptimization(SDValue Callee,
624 CallingConv::ID CalleeCC,
625 bool isVarArg,
626 const SmallVectorImpl<ISD::InputArg> &Ins,
627 SelectionDAG& DAG) const;
629 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
630 int SPDiff,
631 SDValue Chain,
632 SDValue &LROpOut,
633 SDValue &FPOpOut,
634 bool isDarwinABI,
635 SDLoc dl) const;
637 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
638 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
639 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
640 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
641 std::pair<SDValue,SDValue> lowerTLSCall(SDValue Op, SDLoc dl,
642 SelectionDAG &DAG) const;
643 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
644 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
645 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
646 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
647 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
648 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
649 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
650 const PPCSubtarget &Subtarget) const;
651 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG,
652 const PPCSubtarget &Subtarget) const;
653 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG,
654 const PPCSubtarget &Subtarget) const;
655 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
656 const PPCSubtarget &Subtarget) const;
657 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
658 const PPCSubtarget &Subtarget) const;
659 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
660 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
661 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
662 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
663 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, SDLoc dl) const;
664 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
665 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
666 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
667 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
668 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
669 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
670 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
671 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
672 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
673 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
674 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
676 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
677 CallingConv::ID CallConv, bool isVarArg,
678 const SmallVectorImpl<ISD::InputArg> &Ins,
679 SDLoc dl, SelectionDAG &DAG,
680 SmallVectorImpl<SDValue> &InVals) const;
681 SDValue FinishCall(CallingConv::ID CallConv, SDLoc dl, bool isTailCall,
682 bool isVarArg,
683 SelectionDAG &DAG,
684 SmallVector<std::pair<unsigned, SDValue>, 8>
685 &RegsToPass,
686 SDValue InFlag, SDValue Chain,
687 SDValue &Callee,
688 int SPDiff, unsigned NumBytes,
689 const SmallVectorImpl<ISD::InputArg> &Ins,
690 SmallVectorImpl<SDValue> &InVals) const;
692 SDValue
693 LowerFormalArguments(SDValue Chain,
694 CallingConv::ID CallConv, bool isVarArg,
695 const SmallVectorImpl<ISD::InputArg> &Ins,
696 SDLoc dl, SelectionDAG &DAG,
697 SmallVectorImpl<SDValue> &InVals) const override;
699 SDValue
700 LowerCall(TargetLowering::CallLoweringInfo &CLI,
701 SmallVectorImpl<SDValue> &InVals) const override;
703 bool
704 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
705 bool isVarArg,
706 const SmallVectorImpl<ISD::OutputArg> &Outs,
707 LLVMContext &Context) const override;
709 SDValue
710 LowerReturn(SDValue Chain,
711 CallingConv::ID CallConv, bool isVarArg,
712 const SmallVectorImpl<ISD::OutputArg> &Outs,
713 const SmallVectorImpl<SDValue> &OutVals,
714 SDLoc dl, SelectionDAG &DAG) const override;
716 SDValue
717 extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, SelectionDAG &DAG,
718 SDValue ArgVal, SDLoc dl) const;
720 SDValue
721 LowerFormalArguments_Darwin(SDValue Chain,
722 CallingConv::ID CallConv, bool isVarArg,
723 const SmallVectorImpl<ISD::InputArg> &Ins,
724 SDLoc dl, SelectionDAG &DAG,
725 SmallVectorImpl<SDValue> &InVals) const;
726 SDValue
727 LowerFormalArguments_64SVR4(SDValue Chain,
728 CallingConv::ID CallConv, bool isVarArg,
729 const SmallVectorImpl<ISD::InputArg> &Ins,
730 SDLoc dl, SelectionDAG &DAG,
731 SmallVectorImpl<SDValue> &InVals) const;
732 SDValue
733 LowerFormalArguments_32SVR4(SDValue Chain,
734 CallingConv::ID CallConv, bool isVarArg,
735 const SmallVectorImpl<ISD::InputArg> &Ins,
736 SDLoc dl, SelectionDAG &DAG,
737 SmallVectorImpl<SDValue> &InVals) const;
739 SDValue
740 createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
741 SDValue CallSeqStart, ISD::ArgFlagsTy Flags,
742 SelectionDAG &DAG, SDLoc dl) const;
744 SDValue
745 LowerCall_Darwin(SDValue Chain, SDValue Callee,
746 CallingConv::ID CallConv,
747 bool isVarArg, bool isTailCall,
748 const SmallVectorImpl<ISD::OutputArg> &Outs,
749 const SmallVectorImpl<SDValue> &OutVals,
750 const SmallVectorImpl<ISD::InputArg> &Ins,
751 SDLoc dl, SelectionDAG &DAG,
752 SmallVectorImpl<SDValue> &InVals) const;
753 SDValue
754 LowerCall_64SVR4(SDValue Chain, SDValue Callee,
755 CallingConv::ID CallConv,
756 bool isVarArg, bool isTailCall,
757 const SmallVectorImpl<ISD::OutputArg> &Outs,
758 const SmallVectorImpl<SDValue> &OutVals,
759 const SmallVectorImpl<ISD::InputArg> &Ins,
760 SDLoc dl, SelectionDAG &DAG,
761 SmallVectorImpl<SDValue> &InVals) const;
762 SDValue
763 LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
764 bool isVarArg, bool isTailCall,
765 const SmallVectorImpl<ISD::OutputArg> &Outs,
766 const SmallVectorImpl<SDValue> &OutVals,
767 const SmallVectorImpl<ISD::InputArg> &Ins,
768 SDLoc dl, SelectionDAG &DAG,
769 SmallVectorImpl<SDValue> &InVals) const;
771 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
772 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
774 SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const;
775 SDValue DAGCombineTruncBoolExt(SDNode *N, DAGCombinerInfo &DCI) const;
776 SDValue combineFPToIntToFP(SDNode *N, DAGCombinerInfo &DCI) const;
778 SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI,
779 unsigned &RefinementSteps,
780 bool &UseOneConstNR) const override;
781 SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI,
782 unsigned &RefinementSteps) const override;
783 bool combineRepeatedFPDivisors(unsigned NumUsers) const override;
785 CCAssignFn *useFastISelCCs(unsigned Flag) const;
786 };
788 namespace PPC {
789 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
790 const TargetLibraryInfo *LibInfo);
791 }
793 bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
794 CCValAssign::LocInfo &LocInfo,
795 ISD::ArgFlagsTy &ArgFlags,
796 CCState &State);
798 bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
799 MVT &LocVT,
800 CCValAssign::LocInfo &LocInfo,
801 ISD::ArgFlagsTy &ArgFlags,
802 CCState &State);
804 bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
805 MVT &LocVT,
806 CCValAssign::LocInfo &LocInfo,
807 ISD::ArgFlagsTy &ArgFlags,
808 CCState &State);
809 }
811 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H