1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that PPC uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
16 #define LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
18 #include "PPC.h"
19 #include "PPCInstrInfo.h"
20 #include "PPCRegisterInfo.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/Target/TargetLowering.h"
25 namespace llvm {
26 namespace PPCISD {
27 enum NodeType {
28 // Start the numbering where the builtin ops and target ops leave off.
29 FIRST_NUMBER = ISD::BUILTIN_OP_END,
31 /// FSEL - Traditional three-operand fsel node.
32 ///
33 FSEL,
35 /// FCFID - The FCFID instruction, taking an f64 operand and producing
36 /// and f64 value containing the FP representation of the integer that
37 /// was temporarily in the f64 operand.
38 FCFID,
40 /// Newer FCFID[US] integer-to-floating-point conversion instructions for
41 /// unsigned integers and single-precision outputs.
42 FCFIDU, FCFIDS, FCFIDUS,
44 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
45 /// operand, producing an f64 value containing the integer representation
46 /// of that FP value.
47 FCTIDZ, FCTIWZ,
49 /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for
50 /// unsigned integers.
51 FCTIDUZ, FCTIWUZ,
53 /// Reciprocal estimate instructions (unary FP ops).
54 FRE, FRSQRTE,
56 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
57 // three v4f32 operands and producing a v4f32 result.
58 VMADDFP, VNMSUBFP,
60 /// VPERM - The PPC VPERM Instruction.
61 ///
62 VPERM,
64 /// Hi/Lo - These represent the high and low 16-bit parts of a global
65 /// address respectively. These nodes have two operands, the first of
66 /// which must be a TargetGlobalAddress, and the second of which must be a
67 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
68 /// though these are usually folded into other nodes.
69 Hi, Lo,
71 TOC_ENTRY,
73 /// The following two target-specific nodes are used for calls through
74 /// function pointers in the 64-bit SVR4 ABI.
76 /// Like a regular LOAD but additionally taking/producing a flag.
77 LOAD,
79 /// Like LOAD (taking/producing a flag), but using r2 as hard-coded
80 /// destination.
81 LOAD_TOC,
83 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
84 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
85 /// compute an allocation on the stack.
86 DYNALLOC,
88 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
89 /// at function entry, used for PIC code.
90 GlobalBaseReg,
92 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit
93 /// shift amounts. These nodes are generated by the multi-precision shift
94 /// code.
95 SRL, SRA, SHL,
97 /// The combination of sra[wd]i and addze used to implemented signed
98 /// integer division by a power of 2. The first operand is the dividend,
99 /// and the second is the constant shift amount (representing the
100 /// divisor).
101 SRA_ADDZE,
103 /// CALL - A direct function call.
104 /// CALL_NOP is a call with the special NOP which follows 64-bit
105 /// SVR4 calls.
106 CALL, CALL_NOP,
108 /// CALL_TLS and CALL_NOP_TLS - Versions of CALL and CALL_NOP used
109 /// to access TLS variables.
110 CALL_TLS, CALL_NOP_TLS,
112 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
113 /// MTCTR instruction.
114 MTCTR,
116 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
117 /// BCTRL instruction.
118 BCTRL,
120 /// CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl
121 /// instruction and the TOC reload required on SVR4 PPC64.
122 BCTRL_LOAD_TOC,
124 /// Return with a flag operand, matched by 'blr'
125 RET_FLAG,
127 /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
128 /// This copies the bits corresponding to the specified CRREG into the
129 /// resultant GPR. Bits corresponding to other CR regs are undefined.
130 MFOCRF,
132 // FIXME: Remove these once the ANDI glue bug is fixed:
133 /// i1 = ANDIo_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the
134 /// eq or gt bit of CR0 after executing andi. x, 1. This is used to
135 /// implement truncation of i32 or i64 to i1.
136 ANDIo_1_EQ_BIT, ANDIo_1_GT_BIT,
138 // READ_TIME_BASE - A read of the 64-bit time-base register on a 32-bit
139 // target (returns (Lo, Hi)). It takes a chain operand.
140 READ_TIME_BASE,
142 // EH_SJLJ_SETJMP - SjLj exception handling setjmp.
143 EH_SJLJ_SETJMP,
145 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
146 EH_SJLJ_LONGJMP,
148 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
149 /// instructions. For lack of better number, we use the opcode number
150 /// encoding for the OPC field to identify the compare. For example, 838
151 /// is VCMPGTSH.
152 VCMP,
154 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
155 /// altivec VCMP*o instructions. For lack of better number, we use the
156 /// opcode number encoding for the OPC field to identify the compare. For
157 /// example, 838 is VCMPGTSH.
158 VCMPo,
160 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
161 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
162 /// condition register to branch on, OPC is the branch opcode to use (e.g.
163 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
164 /// an optional input flag argument.
165 COND_BRANCH,
167 /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based
168 /// loops.
169 BDNZ, BDZ,
171 /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding
172 /// towards zero. Used only as part of the long double-to-int
173 /// conversion sequence.
174 FADDRTZ,
176 /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
177 MFFS,
179 /// LARX = This corresponds to PPC l{w|d}arx instrcution: load and
180 /// reserve indexed. This is used to implement atomic operations.
181 LARX,
183 /// STCX = This corresponds to PPC stcx. instrcution: store conditional
184 /// indexed. This is used to implement atomic operations.
185 STCX,
187 /// TC_RETURN - A tail call return.
188 /// operand #0 chain
189 /// operand #1 callee (register or absolute)
190 /// operand #2 stack adjustment
191 /// operand #3 optional in flag
192 TC_RETURN,
194 /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
195 CR6SET,
196 CR6UNSET,
198 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS
199 /// on PPC32.
200 PPC32_GOT,
202 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by general dynamic and
203 /// local dynamic TLS on PPC32.
204 PPC32_PICGOT,
206 /// G8RC = ADDIS_GOT_TPREL_HA %X2, Symbol - Used by the initial-exec
207 /// TLS model, produces an ADDIS8 instruction that adds the GOT
208 /// base to sym\@got\@tprel\@ha.
209 ADDIS_GOT_TPREL_HA,
211 /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec
212 /// TLS model, produces a LD instruction with base register G8RReg
213 /// and offset sym\@got\@tprel\@l. This completes the addition that
214 /// finds the offset of "sym" relative to the thread pointer.
215 LD_GOT_TPREL_L,
217 /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS
218 /// model, produces an ADD instruction that adds the contents of
219 /// G8RReg to the thread pointer. Symbol contains a relocation
220 /// sym\@tls which is to be replaced by the thread pointer and
221 /// identifies to the linker that the instruction is part of a
222 /// TLS sequence.
223 ADD_TLS,
225 /// G8RC = ADDIS_TLSGD_HA %X2, Symbol - For the general-dynamic TLS
226 /// model, produces an ADDIS8 instruction that adds the GOT base
227 /// register to sym\@got\@tlsgd\@ha.
228 ADDIS_TLSGD_HA,
230 /// G8RC = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS
231 /// model, produces an ADDI8 instruction that adds G8RReg to
232 /// sym\@got\@tlsgd\@l.
233 ADDI_TLSGD_L,
235 /// G8RC = ADDIS_TLSLD_HA %X2, Symbol - For the local-dynamic TLS
236 /// model, produces an ADDIS8 instruction that adds the GOT base
237 /// register to sym\@got\@tlsld\@ha.
238 ADDIS_TLSLD_HA,
240 /// G8RC = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS
241 /// model, produces an ADDI8 instruction that adds G8RReg to
242 /// sym\@got\@tlsld\@l.
243 ADDI_TLSLD_L,
245 /// G8RC = ADDIS_DTPREL_HA %X3, Symbol, Chain - For the
246 /// local-dynamic TLS model, produces an ADDIS8 instruction
247 /// that adds X3 to sym\@dtprel\@ha. The Chain operand is needed
248 /// to tie this in place following a copy to %X3 from the result
249 /// of a GET_TLSLD_ADDR.
250 ADDIS_DTPREL_HA,
252 /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS
253 /// model, produces an ADDI8 instruction that adds G8RReg to
254 /// sym\@got\@dtprel\@l.
255 ADDI_DTPREL_L,
257 /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded
258 /// during instruction selection to optimize a BUILD_VECTOR into
259 /// operations on splats. This is necessary to avoid losing these
260 /// optimizations due to constant folding.
261 VADD_SPLAT,
263 /// CHAIN = SC CHAIN, Imm128 - System call. The 7-bit unsigned
264 /// operand identifies the operating system entry point.
265 SC,
267 /// VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little
268 /// endian. Maps to an xxswapd instruction that corrects an lxvd2x
269 /// or stxvd2x instruction. The chain is necessary because the
270 /// sequence replaces a load and needs to provide the same number
271 /// of outputs.
272 XXSWAPD,
274 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
275 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of
276 /// the GPRC input, then stores it through Ptr. Type can be either i16 or
277 /// i32.
278 STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE,
280 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
281 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
282 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16
283 /// or i32.
284 LBRX,
286 /// STFIWX - The STFIWX instruction. The first operand is an input token
287 /// chain, then an f64 value to store, then an address to store it to.
288 STFIWX,
290 /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point
291 /// load which sign-extends from a 32-bit integer value into the
292 /// destination 64-bit register.
293 LFIWAX,
295 /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point
296 /// load which zero-extends from a 32-bit integer value into the
297 /// destination 64-bit register.
298 LFIWZX,
300 /// G8RC = ADDIS_TOC_HA %X2, Symbol - For medium and large code model,
301 /// produces an ADDIS8 instruction that adds the TOC base register to
302 /// sym\@toc\@ha.
303 ADDIS_TOC_HA,
305 /// G8RC = LD_TOC_L Symbol, G8RReg - For medium and large code model,
306 /// produces a LD instruction with base register G8RReg and offset
307 /// sym\@toc\@l. Preceded by an ADDIS_TOC_HA to form a full 32-bit offset.
308 LD_TOC_L,
310 /// G8RC = ADDI_TOC_L G8RReg, Symbol - For medium code model, produces
311 /// an ADDI8 instruction that adds G8RReg to sym\@toc\@l.
312 /// Preceded by an ADDIS_TOC_HA to form a full 32-bit offset.
313 ADDI_TOC_L,
315 /// VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
316 /// Maps directly to an lxvd2x instruction that will be followed by
317 /// an xxswapd.
318 LXVD2X,
320 /// CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
321 /// Maps directly to an stxvd2x instruction that will be preceded by
322 /// an xxswapd.
323 STXVD2X
324 };
325 }
327 /// Define some predicates that are used for node matching.
328 namespace PPC {
329 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
330 /// VPKUHUM instruction.
331 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
332 SelectionDAG &DAG);
334 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
335 /// VPKUWUM instruction.
336 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
337 SelectionDAG &DAG);
339 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
340 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
341 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
342 unsigned ShuffleKind, SelectionDAG &DAG);
344 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
345 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
346 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
347 unsigned ShuffleKind, SelectionDAG &DAG);
349 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the
350 /// shift amount, otherwise return -1.
351 int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
352 SelectionDAG &DAG);
354 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
355 /// specifies a splat of a single element that is suitable for input to
356 /// VSPLTB/VSPLTH/VSPLTW.
357 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
359 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
360 /// are -0.0.
361 bool isAllNegativeZeroVector(SDNode *N);
363 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
364 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
365 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize, SelectionDAG &DAG);
367 /// get_VSPLTI_elt - If this is a build_vector of constants which can be
368 /// formed by using a vspltis[bhw] instruction of the specified element
369 /// size, return the constant being splatted. The ByteSize field indicates
370 /// the number of bytes of each element [124] -> [bhw].
371 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
372 }
374 class PPCSubtarget;
375 class PPCTargetLowering : public TargetLowering {
376 const PPCSubtarget &Subtarget;
378 public:
379 explicit PPCTargetLowering(const PPCTargetMachine &TM);
381 /// getTargetNodeName() - This method returns the name of a target specific
382 /// DAG node.
383 const char *getTargetNodeName(unsigned Opcode) const override;
385 MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; }
387 /// getSetCCResultType - Return the ISD::SETCC ValueType
388 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
390 /// Return true if target always beneficiates from combining into FMA for a
391 /// given value type. This must typically return false on targets where FMA
392 /// takes more cycles to execute than FADD.
393 bool enableAggressiveFMAFusion(EVT VT) const override;
395 /// getPreIndexedAddressParts - returns true by value, base pointer and
396 /// offset pointer and addressing mode by reference if the node's address
397 /// can be legally represented as pre-indexed load / store address.
398 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
399 SDValue &Offset,
400 ISD::MemIndexedMode &AM,
401 SelectionDAG &DAG) const override;
403 /// SelectAddressRegReg - Given the specified addressed, check to see if it
404 /// can be represented as an indexed [r+r] operation. Returns false if it
405 /// can be more efficiently represented with [r+imm].
406 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
407 SelectionDAG &DAG) const;
409 /// SelectAddressRegImm - Returns true if the address N can be represented
410 /// by a base register plus a signed 16-bit displacement [r+imm], and if it
411 /// is not better represented as reg+reg. If Aligned is true, only accept
412 /// displacements suitable for STD and friends, i.e. multiples of 4.
413 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
414 SelectionDAG &DAG, bool Aligned) const;
416 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
417 /// represented as an indexed [r+r] operation.
418 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
419 SelectionDAG &DAG) const;
421 Sched::Preference getSchedulingPreference(SDNode *N) const override;
423 /// LowerOperation - Provide custom lowering hooks for some operations.
424 ///
425 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
427 /// ReplaceNodeResults - Replace the results of node with an illegal result
428 /// type with new values built out of custom code.
429 ///
430 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
431 SelectionDAG &DAG) const override;
433 SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const;
434 SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const;
436 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
438 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
439 std::vector<SDNode *> *Created) const override;
441 unsigned getRegisterByName(const char* RegName, EVT VT) const override;
443 void computeKnownBitsForTargetNode(const SDValue Op,
444 APInt &KnownZero,
445 APInt &KnownOne,
446 const SelectionDAG &DAG,
447 unsigned Depth = 0) const override;
449 Instruction* emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
450 bool IsStore, bool IsLoad) const override;
451 Instruction* emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
452 bool IsStore, bool IsLoad) const override;
454 MachineBasicBlock *
455 EmitInstrWithCustomInserter(MachineInstr *MI,
456 MachineBasicBlock *MBB) const override;
457 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
458 MachineBasicBlock *MBB, bool is64Bit,
459 unsigned BinOpcode) const;
460 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI,
461 MachineBasicBlock *MBB,
462 bool is8bit, unsigned Opcode) const;
464 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
465 MachineBasicBlock *MBB) const;
467 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
468 MachineBasicBlock *MBB) const;
470 ConstraintType
471 getConstraintType(const std::string &Constraint) const override;
473 /// Examine constraint string and operand type and determine a weight value.
474 /// The operand object must already have been set up with the operand type.
475 ConstraintWeight getSingleConstraintMatchWeight(
476 AsmOperandInfo &info, const char *constraint) const override;
478 std::pair<unsigned, const TargetRegisterClass*>
479 getRegForInlineAsmConstraint(const std::string &Constraint,
480 MVT VT) const override;
482 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
483 /// function arguments in the caller parameter area. This is the actual
484 /// alignment, not its logarithm.
485 unsigned getByValTypeAlignment(Type *Ty) const override;
487 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
488 /// vector. If it is invalid, don't add anything to Ops.
489 void LowerAsmOperandForConstraint(SDValue Op,
490 std::string &Constraint,
491 std::vector<SDValue> &Ops,
492 SelectionDAG &DAG) const override;
494 /// isLegalAddressingMode - Return true if the addressing mode represented
495 /// by AM is legal for this target, for a load/store of the specified type.
496 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
498 /// isLegalICmpImmediate - Return true if the specified immediate is legal
499 /// icmp immediate, that is the target has icmp instructions which can
500 /// compare a register against the immediate without having to materialize
501 /// the immediate into a register.
502 bool isLegalICmpImmediate(int64_t Imm) const override;
504 /// isLegalAddImmediate - Return true if the specified immediate is legal
505 /// add immediate, that is the target has add instructions which can
506 /// add a register and the immediate without having to materialize
507 /// the immediate into a register.
508 bool isLegalAddImmediate(int64_t Imm) const override;
510 /// isTruncateFree - Return true if it's free to truncate a value of
511 /// type Ty1 to type Ty2. e.g. On PPC it's free to truncate a i64 value in
512 /// register X1 to i32 by referencing its sub-register R1.
513 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
514 bool isTruncateFree(EVT VT1, EVT VT2) const override;
516 /// \brief Returns true if it is beneficial to convert a load of a constant
517 /// to just the constant itself.
518 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
519 Type *Ty) const override;
521 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
523 bool getTgtMemIntrinsic(IntrinsicInfo &Info,
524 const CallInst &I,
525 unsigned Intrinsic) const override;
527 /// getOptimalMemOpType - Returns the target specific optimal type for load
528 /// and store operations as a result of memset, memcpy, and memmove
529 /// lowering. If DstAlign is zero that means it's safe to destination
530 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
531 /// means there isn't a need to check it against alignment requirement,
532 /// probably because the source does not need to be loaded. If 'IsMemset' is
533 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
534 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
535 /// source is constant so it does not need to be loaded.
536 /// It returns EVT::Other if the type should be determined using generic
537 /// target-independent logic.
538 EVT
539 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
540 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
541 MachineFunction &MF) const override;
543 /// Is unaligned memory access allowed for the given type, and is it fast
544 /// relative to software emulation.
545 bool allowsMisalignedMemoryAccesses(EVT VT,
546 unsigned AddrSpace,
547 unsigned Align = 1,
548 bool *Fast = nullptr) const override;
550 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
551 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
552 /// expanded to FMAs when this method returns true, otherwise fmuladd is
553 /// expanded to fmul + fadd.
554 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
556 // Should we expand the build vector with shuffles?
557 bool
558 shouldExpandBuildVectorWithShuffles(EVT VT,
559 unsigned DefinedValues) const override;
561 /// createFastISel - This method returns a target-specific FastISel object,
562 /// or null if the target does not support "fast" instruction selection.
563 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
564 const TargetLibraryInfo *LibInfo) const override;
566 /// \brief Returns true if an argument of type Ty needs to be passed in a
567 /// contiguous block of registers in calling convention CallConv.
568 bool functionArgumentNeedsConsecutiveRegisters(
569 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override {
570 // We support any array type as "consecutive" block in the parameter
571 // save area. The element type defines the alignment requirement and
572 // whether the argument should go in GPRs, FPRs, or VRs if available.
573 //
574 // Note that clang uses this capability both to implement the ELFv2
575 // homogeneous float/vector aggregate ABI, and to avoid having to use
576 // "byval" when passing aggregates that might fully fit in registers.
577 return Ty->isArrayTy();
578 }
580 private:
581 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
582 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
584 bool
585 IsEligibleForTailCallOptimization(SDValue Callee,
586 CallingConv::ID CalleeCC,
587 bool isVarArg,
588 const SmallVectorImpl<ISD::InputArg> &Ins,
589 SelectionDAG& DAG) const;
591 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
592 int SPDiff,
593 SDValue Chain,
594 SDValue &LROpOut,
595 SDValue &FPOpOut,
596 bool isDarwinABI,
597 SDLoc dl) const;
599 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
600 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
601 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
602 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
603 std::pair<SDValue,SDValue> lowerTLSCall(SDValue Op, SDLoc dl,
604 SelectionDAG &DAG) const;
605 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
606 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
607 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
608 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
609 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
610 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
611 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
612 const PPCSubtarget &Subtarget) const;
613 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG,
614 const PPCSubtarget &Subtarget) const;
615 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG,
616 const PPCSubtarget &Subtarget) const;
617 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
618 const PPCSubtarget &Subtarget) const;
619 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
620 const PPCSubtarget &Subtarget) const;
621 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
622 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
623 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
624 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
625 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, SDLoc dl) const;
626 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
627 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
628 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
629 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
630 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
631 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
632 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
633 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
634 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
635 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
636 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
638 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
639 CallingConv::ID CallConv, bool isVarArg,
640 const SmallVectorImpl<ISD::InputArg> &Ins,
641 SDLoc dl, SelectionDAG &DAG,
642 SmallVectorImpl<SDValue> &InVals) const;
643 SDValue FinishCall(CallingConv::ID CallConv, SDLoc dl, bool isTailCall,
644 bool isVarArg,
645 SelectionDAG &DAG,
646 SmallVector<std::pair<unsigned, SDValue>, 8>
647 &RegsToPass,
648 SDValue InFlag, SDValue Chain,
649 SDValue &Callee,
650 int SPDiff, unsigned NumBytes,
651 const SmallVectorImpl<ISD::InputArg> &Ins,
652 SmallVectorImpl<SDValue> &InVals) const;
654 SDValue
655 LowerFormalArguments(SDValue Chain,
656 CallingConv::ID CallConv, bool isVarArg,
657 const SmallVectorImpl<ISD::InputArg> &Ins,
658 SDLoc dl, SelectionDAG &DAG,
659 SmallVectorImpl<SDValue> &InVals) const override;
661 SDValue
662 LowerCall(TargetLowering::CallLoweringInfo &CLI,
663 SmallVectorImpl<SDValue> &InVals) const override;
665 bool
666 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
667 bool isVarArg,
668 const SmallVectorImpl<ISD::OutputArg> &Outs,
669 LLVMContext &Context) const override;
671 SDValue
672 LowerReturn(SDValue Chain,
673 CallingConv::ID CallConv, bool isVarArg,
674 const SmallVectorImpl<ISD::OutputArg> &Outs,
675 const SmallVectorImpl<SDValue> &OutVals,
676 SDLoc dl, SelectionDAG &DAG) const override;
678 SDValue
679 extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, SelectionDAG &DAG,
680 SDValue ArgVal, SDLoc dl) const;
682 SDValue
683 LowerFormalArguments_Darwin(SDValue Chain,
684 CallingConv::ID CallConv, bool isVarArg,
685 const SmallVectorImpl<ISD::InputArg> &Ins,
686 SDLoc dl, SelectionDAG &DAG,
687 SmallVectorImpl<SDValue> &InVals) const;
688 SDValue
689 LowerFormalArguments_64SVR4(SDValue Chain,
690 CallingConv::ID CallConv, bool isVarArg,
691 const SmallVectorImpl<ISD::InputArg> &Ins,
692 SDLoc dl, SelectionDAG &DAG,
693 SmallVectorImpl<SDValue> &InVals) const;
694 SDValue
695 LowerFormalArguments_32SVR4(SDValue Chain,
696 CallingConv::ID CallConv, bool isVarArg,
697 const SmallVectorImpl<ISD::InputArg> &Ins,
698 SDLoc dl, SelectionDAG &DAG,
699 SmallVectorImpl<SDValue> &InVals) const;
701 SDValue
702 createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
703 SDValue CallSeqStart, ISD::ArgFlagsTy Flags,
704 SelectionDAG &DAG, SDLoc dl) const;
706 SDValue
707 LowerCall_Darwin(SDValue Chain, SDValue Callee,
708 CallingConv::ID CallConv,
709 bool isVarArg, bool isTailCall,
710 const SmallVectorImpl<ISD::OutputArg> &Outs,
711 const SmallVectorImpl<SDValue> &OutVals,
712 const SmallVectorImpl<ISD::InputArg> &Ins,
713 SDLoc dl, SelectionDAG &DAG,
714 SmallVectorImpl<SDValue> &InVals) const;
715 SDValue
716 LowerCall_64SVR4(SDValue Chain, SDValue Callee,
717 CallingConv::ID CallConv,
718 bool isVarArg, bool isTailCall,
719 const SmallVectorImpl<ISD::OutputArg> &Outs,
720 const SmallVectorImpl<SDValue> &OutVals,
721 const SmallVectorImpl<ISD::InputArg> &Ins,
722 SDLoc dl, SelectionDAG &DAG,
723 SmallVectorImpl<SDValue> &InVals) const;
724 SDValue
725 LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
726 bool isVarArg, bool isTailCall,
727 const SmallVectorImpl<ISD::OutputArg> &Outs,
728 const SmallVectorImpl<SDValue> &OutVals,
729 const SmallVectorImpl<ISD::InputArg> &Ins,
730 SDLoc dl, SelectionDAG &DAG,
731 SmallVectorImpl<SDValue> &InVals) const;
733 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
734 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
736 SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const;
737 SDValue DAGCombineTruncBoolExt(SDNode *N, DAGCombinerInfo &DCI) const;
739 SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI,
740 unsigned &RefinementSteps,
741 bool &UseOneConstNR) const override;
742 SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI,
743 unsigned &RefinementSteps) const override;
744 bool combineRepeatedFPDivisors(unsigned NumUsers) const override;
746 CCAssignFn *useFastISelCCs(unsigned Flag) const;
747 };
749 namespace PPC {
750 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
751 const TargetLibraryInfo *LibInfo);
752 }
754 bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
755 CCValAssign::LocInfo &LocInfo,
756 ISD::ArgFlagsTy &ArgFlags,
757 CCState &State);
759 bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
760 MVT &LocVT,
761 CCValAssign::LocInfo &LocInfo,
762 ISD::ArgFlagsTy &ArgFlags,
763 CCState &State);
765 bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
766 MVT &LocVT,
767 CCValAssign::LocInfo &LocInfo,
768 ISD::ArgFlagsTy &ArgFlags,
769 CCState &State);
770 }
772 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H