1 //===-- SIInstrInfo.cpp - SI Instruction Information ---------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief SI Implementation of TargetInstrInfo.
12 //
13 //===----------------------------------------------------------------------===//
16 #include "SIInstrInfo.h"
17 #include "AMDGPUTargetMachine.h"
18 #include "SIDefines.h"
19 #include "SIMachineFunctionInfo.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/IR/Function.h"
23 #include "llvm/MC/MCInstrDesc.h"
25 using namespace llvm;
27 SIInstrInfo::SIInstrInfo(const AMDGPUSubtarget &st)
28 : AMDGPUInstrInfo(st),
29 RI(st) { }
31 //===----------------------------------------------------------------------===//
32 // TargetInstrInfo callbacks
33 //===----------------------------------------------------------------------===//
35 static unsigned getNumOperandsNoGlue(SDNode *Node) {
36 unsigned N = Node->getNumOperands();
37 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
38 --N;
39 return N;
40 }
42 static SDValue findChainOperand(SDNode *Load) {
43 SDValue LastOp = Load->getOperand(getNumOperandsNoGlue(Load) - 1);
44 assert(LastOp.getValueType() == MVT::Other && "Chain missing from load node");
45 return LastOp;
46 }
48 /// \brief Returns true if both nodes have the same value for the given
49 /// operand \p Op, or if both nodes do not have this operand.
50 static bool nodesHaveSameOperandValue(SDNode *N0, SDNode* N1, unsigned OpName) {
51 unsigned Opc0 = N0->getMachineOpcode();
52 unsigned Opc1 = N1->getMachineOpcode();
54 int Op0Idx = AMDGPU::getNamedOperandIdx(Opc0, OpName);
55 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName);
57 if (Op0Idx == -1 && Op1Idx == -1)
58 return true;
61 if ((Op0Idx == -1 && Op1Idx != -1) ||
62 (Op1Idx == -1 && Op0Idx != -1))
63 return false;
65 // getNamedOperandIdx returns the index for the MachineInstr's operands,
66 // which includes the result as the first operand. We are indexing into the
67 // MachineSDNode's operands, so we need to skip the result operand to get
68 // the real index.
69 --Op0Idx;
70 --Op1Idx;
72 return N0->getOperand(Op0Idx) == N0->getOperand(Op1Idx);
73 }
75 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,
76 int64_t &Offset0,
77 int64_t &Offset1) const {
78 if (!Load0->isMachineOpcode() || !Load1->isMachineOpcode())
79 return false;
81 unsigned Opc0 = Load0->getMachineOpcode();
82 unsigned Opc1 = Load1->getMachineOpcode();
84 // Make sure both are actually loads.
85 if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad())
86 return false;
88 if (isDS(Opc0) && isDS(Opc1)) {
89 assert(getNumOperandsNoGlue(Load0) == getNumOperandsNoGlue(Load1));
91 // TODO: Also shouldn't see read2st
92 assert(Opc0 != AMDGPU::DS_READ2_B32 &&
93 Opc0 != AMDGPU::DS_READ2_B64 &&
94 Opc1 != AMDGPU::DS_READ2_B32 &&
95 Opc1 != AMDGPU::DS_READ2_B64);
97 // Check base reg.
98 if (Load0->getOperand(1) != Load1->getOperand(1))
99 return false;
101 // Check chain.
102 if (findChainOperand(Load0) != findChainOperand(Load1))
103 return false;
105 Offset0 = cast<ConstantSDNode>(Load0->getOperand(2))->getZExtValue();
106 Offset1 = cast<ConstantSDNode>(Load1->getOperand(2))->getZExtValue();
107 return true;
108 }
110 if (isSMRD(Opc0) && isSMRD(Opc1)) {
111 assert(getNumOperandsNoGlue(Load0) == getNumOperandsNoGlue(Load1));
113 // Check base reg.
114 if (Load0->getOperand(0) != Load1->getOperand(0))
115 return false;
117 // Check chain.
118 if (findChainOperand(Load0) != findChainOperand(Load1))
119 return false;
121 Offset0 = cast<ConstantSDNode>(Load0->getOperand(1))->getZExtValue();
122 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue();
123 return true;
124 }
126 // MUBUF and MTBUF can access the same addresses.
127 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1))) {
129 // MUBUF and MTBUF have vaddr at different indices.
130 if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) ||
131 findChainOperand(Load0) != findChainOperand(Load1) ||
132 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::vaddr) ||
133 !nodesHaveSameOperandValue(Load1, Load1, AMDGPU::OpName::srsrc))
134 return false;
136 int OffIdx0 = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset);
137 int OffIdx1 = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset);
139 if (OffIdx0 == -1 || OffIdx1 == -1)
140 return false;
142 // getNamedOperandIdx returns the index for MachineInstrs. Since they
143 // inlcude the output in the operand list, but SDNodes don't, we need to
144 // subtract the index by one.
145 --OffIdx0;
146 --OffIdx1;
148 SDValue Off0 = Load0->getOperand(OffIdx0);
149 SDValue Off1 = Load1->getOperand(OffIdx1);
151 // The offset might be a FrameIndexSDNode.
152 if (!isa<ConstantSDNode>(Off0) || !isa<ConstantSDNode>(Off1))
153 return false;
155 Offset0 = cast<ConstantSDNode>(Off0)->getZExtValue();
156 Offset1 = cast<ConstantSDNode>(Off1)->getZExtValue();
157 return true;
158 }
160 return false;
161 }
163 bool SIInstrInfo::getLdStBaseRegImmOfs(MachineInstr *LdSt,
164 unsigned &BaseReg, unsigned &Offset,
165 const TargetRegisterInfo *TRI) const {
166 unsigned Opc = LdSt->getOpcode();
167 if (isDS(Opc)) {
168 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
169 AMDGPU::OpName::offset);
170 if (OffsetImm) {
171 // Normal, single offset LDS instruction.
172 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
173 AMDGPU::OpName::addr);
175 BaseReg = AddrReg->getReg();
176 Offset = OffsetImm->getImm();
177 return true;
178 }
180 // The 2 offset instructions use offset0 and offset1 instead. We can treat
181 // these as a load with a single offset if the 2 offsets are consecutive. We
182 // will use this for some partially aligned loads.
183 const MachineOperand *Offset0Imm = getNamedOperand(*LdSt,
184 AMDGPU::OpName::offset0);
185 const MachineOperand *Offset1Imm = getNamedOperand(*LdSt,
186 AMDGPU::OpName::offset1);
188 uint8_t Offset0 = Offset0Imm->getImm();
189 uint8_t Offset1 = Offset1Imm->getImm();
190 assert(Offset1 > Offset0);
192 if (Offset1 - Offset0 == 1) {
193 // Each of these offsets is in element sized units, so we need to convert
194 // to bytes of the individual reads.
196 unsigned EltSize;
197 if (LdSt->mayLoad())
198 EltSize = getOpRegClass(*LdSt, 0)->getSize() / 2;
199 else {
200 assert(LdSt->mayStore());
201 int Data0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
202 EltSize = getOpRegClass(*LdSt, Data0Idx)->getSize();
203 }
205 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
206 AMDGPU::OpName::addr);
207 BaseReg = AddrReg->getReg();
208 Offset = EltSize * Offset0;
209 return true;
210 }
212 return false;
213 }
215 if (isMUBUF(Opc) || isMTBUF(Opc)) {
216 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::soffset) != -1)
217 return false;
219 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
220 AMDGPU::OpName::vaddr);
221 if (!AddrReg)
222 return false;
224 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
225 AMDGPU::OpName::offset);
226 BaseReg = AddrReg->getReg();
227 Offset = OffsetImm->getImm();
228 return true;
229 }
231 if (isSMRD(Opc)) {
232 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
233 AMDGPU::OpName::offset);
234 if (!OffsetImm)
235 return false;
237 const MachineOperand *SBaseReg = getNamedOperand(*LdSt,
238 AMDGPU::OpName::sbase);
239 BaseReg = SBaseReg->getReg();
240 Offset = OffsetImm->getImm();
241 return true;
242 }
244 return false;
245 }
247 void
248 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
249 MachineBasicBlock::iterator MI, DebugLoc DL,
250 unsigned DestReg, unsigned SrcReg,
251 bool KillSrc) const {
253 // If we are trying to copy to or from SCC, there is a bug somewhere else in
254 // the backend. While it may be theoretically possible to do this, it should
255 // never be necessary.
256 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
258 static const int16_t Sub0_15[] = {
259 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
260 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
261 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
262 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, 0
263 };
265 static const int16_t Sub0_7[] = {
266 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
267 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, 0
268 };
270 static const int16_t Sub0_3[] = {
271 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 0
272 };
274 static const int16_t Sub0_2[] = {
275 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, 0
276 };
278 static const int16_t Sub0_1[] = {
279 AMDGPU::sub0, AMDGPU::sub1, 0
280 };
282 unsigned Opcode;
283 const int16_t *SubIndices;
285 if (AMDGPU::M0 == DestReg) {
286 // Check if M0 isn't already set to this value
287 for (MachineBasicBlock::reverse_iterator E = MBB.rend(),
288 I = MachineBasicBlock::reverse_iterator(MI); I != E; ++I) {
290 if (!I->definesRegister(AMDGPU::M0))
291 continue;
293 unsigned Opc = I->getOpcode();
294 if (Opc != TargetOpcode::COPY && Opc != AMDGPU::S_MOV_B32)
295 break;
297 if (!I->readsRegister(SrcReg))
298 break;
300 // The copy isn't necessary
301 return;
302 }
303 }
305 if (AMDGPU::SReg_32RegClass.contains(DestReg)) {
306 assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
307 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
308 .addReg(SrcReg, getKillRegState(KillSrc));
309 return;
311 } else if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
312 assert(AMDGPU::SReg_64RegClass.contains(SrcReg));
313 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
314 .addReg(SrcReg, getKillRegState(KillSrc));
315 return;
317 } else if (AMDGPU::SReg_128RegClass.contains(DestReg)) {
318 assert(AMDGPU::SReg_128RegClass.contains(SrcReg));
319 Opcode = AMDGPU::S_MOV_B32;
320 SubIndices = Sub0_3;
322 } else if (AMDGPU::SReg_256RegClass.contains(DestReg)) {
323 assert(AMDGPU::SReg_256RegClass.contains(SrcReg));
324 Opcode = AMDGPU::S_MOV_B32;
325 SubIndices = Sub0_7;
327 } else if (AMDGPU::SReg_512RegClass.contains(DestReg)) {
328 assert(AMDGPU::SReg_512RegClass.contains(SrcReg));
329 Opcode = AMDGPU::S_MOV_B32;
330 SubIndices = Sub0_15;
332 } else if (AMDGPU::VReg_32RegClass.contains(DestReg)) {
333 assert(AMDGPU::VReg_32RegClass.contains(SrcReg) ||
334 AMDGPU::SReg_32RegClass.contains(SrcReg));
335 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
336 .addReg(SrcReg, getKillRegState(KillSrc));
337 return;
339 } else if (AMDGPU::VReg_64RegClass.contains(DestReg)) {
340 assert(AMDGPU::VReg_64RegClass.contains(SrcReg) ||
341 AMDGPU::SReg_64RegClass.contains(SrcReg));
342 Opcode = AMDGPU::V_MOV_B32_e32;
343 SubIndices = Sub0_1;
345 } else if (AMDGPU::VReg_96RegClass.contains(DestReg)) {
346 assert(AMDGPU::VReg_96RegClass.contains(SrcReg));
347 Opcode = AMDGPU::V_MOV_B32_e32;
348 SubIndices = Sub0_2;
350 } else if (AMDGPU::VReg_128RegClass.contains(DestReg)) {
351 assert(AMDGPU::VReg_128RegClass.contains(SrcReg) ||
352 AMDGPU::SReg_128RegClass.contains(SrcReg));
353 Opcode = AMDGPU::V_MOV_B32_e32;
354 SubIndices = Sub0_3;
356 } else if (AMDGPU::VReg_256RegClass.contains(DestReg)) {
357 assert(AMDGPU::VReg_256RegClass.contains(SrcReg) ||
358 AMDGPU::SReg_256RegClass.contains(SrcReg));
359 Opcode = AMDGPU::V_MOV_B32_e32;
360 SubIndices = Sub0_7;
362 } else if (AMDGPU::VReg_512RegClass.contains(DestReg)) {
363 assert(AMDGPU::VReg_512RegClass.contains(SrcReg) ||
364 AMDGPU::SReg_512RegClass.contains(SrcReg));
365 Opcode = AMDGPU::V_MOV_B32_e32;
366 SubIndices = Sub0_15;
368 } else {
369 llvm_unreachable("Can't copy register!");
370 }
372 while (unsigned SubIdx = *SubIndices++) {
373 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
374 get(Opcode), RI.getSubReg(DestReg, SubIdx));
376 Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc));
378 if (*SubIndices)
379 Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
380 }
381 }
383 unsigned SIInstrInfo::commuteOpcode(unsigned Opcode) const {
384 int NewOpc;
386 // Try to map original to commuted opcode
387 if ((NewOpc = AMDGPU::getCommuteRev(Opcode)) != -1)
388 return NewOpc;
390 // Try to map commuted to original opcode
391 if ((NewOpc = AMDGPU::getCommuteOrig(Opcode)) != -1)
392 return NewOpc;
394 return Opcode;
395 }
397 void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
398 MachineBasicBlock::iterator MI,
399 unsigned SrcReg, bool isKill,
400 int FrameIndex,
401 const TargetRegisterClass *RC,
402 const TargetRegisterInfo *TRI) const {
403 MachineFunction *MF = MBB.getParent();
404 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
405 MachineRegisterInfo &MRI = MF->getRegInfo();
406 DebugLoc DL = MBB.findDebugLoc(MI);
407 unsigned KillFlag = isKill ? RegState::Kill : 0;
409 if (RI.hasVGPRs(RC)) {
410 LLVMContext &Ctx = MF->getFunction()->getContext();
411 Ctx.emitError("SIInstrInfo::storeRegToStackSlot - Can't spill VGPR!");
412 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), AMDGPU::VGPR0)
413 .addReg(SrcReg);
414 } else if (TRI->getCommonSubClass(RC, &AMDGPU::SGPR_32RegClass)) {
415 unsigned Lane = MFI->SpillTracker.reserveLanes(MRI, MF);
416 unsigned TgtReg = MFI->SpillTracker.LaneVGPR;
418 BuildMI(MBB, MI, DL, get(AMDGPU::V_WRITELANE_B32), TgtReg)
419 .addReg(SrcReg, KillFlag)
420 .addImm(Lane);
421 MFI->SpillTracker.addSpilledReg(FrameIndex, TgtReg, Lane);
422 } else if (RI.isSGPRClass(RC)) {
423 // We are only allowed to create one new instruction when spilling
424 // registers, so we need to use pseudo instruction for vector
425 // registers.
426 //
427 // Reserve a spot in the spill tracker for each sub-register of
428 // the vector register.
429 unsigned NumSubRegs = RC->getSize() / 4;
430 unsigned FirstLane = MFI->SpillTracker.reserveLanes(MRI, MF, NumSubRegs);
431 MFI->SpillTracker.addSpilledReg(FrameIndex, MFI->SpillTracker.LaneVGPR,
432 FirstLane);
434 unsigned Opcode;
435 switch (RC->getSize() * 8) {
436 case 64: Opcode = AMDGPU::SI_SPILL_S64_SAVE; break;
437 case 128: Opcode = AMDGPU::SI_SPILL_S128_SAVE; break;
438 case 256: Opcode = AMDGPU::SI_SPILL_S256_SAVE; break;
439 case 512: Opcode = AMDGPU::SI_SPILL_S512_SAVE; break;
440 default: llvm_unreachable("Cannot spill register class");
441 }
443 BuildMI(MBB, MI, DL, get(Opcode), MFI->SpillTracker.LaneVGPR)
444 .addReg(SrcReg)
445 .addImm(FrameIndex);
446 } else {
447 llvm_unreachable("VGPR spilling not supported");
448 }
449 }
451 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
452 MachineBasicBlock::iterator MI,
453 unsigned DestReg, int FrameIndex,
454 const TargetRegisterClass *RC,
455 const TargetRegisterInfo *TRI) const {
456 MachineFunction *MF = MBB.getParent();
457 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
458 DebugLoc DL = MBB.findDebugLoc(MI);
460 if (RI.hasVGPRs(RC)) {
461 LLVMContext &Ctx = MF->getFunction()->getContext();
462 Ctx.emitError("SIInstrInfo::loadRegToStackSlot - Can't retrieve spilled VGPR!");
463 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
464 .addImm(0);
465 } else if (RI.isSGPRClass(RC)){
466 unsigned Opcode;
467 switch(RC->getSize() * 8) {
468 case 32: Opcode = AMDGPU::SI_SPILL_S32_RESTORE; break;
469 case 64: Opcode = AMDGPU::SI_SPILL_S64_RESTORE; break;
470 case 128: Opcode = AMDGPU::SI_SPILL_S128_RESTORE; break;
471 case 256: Opcode = AMDGPU::SI_SPILL_S256_RESTORE; break;
472 case 512: Opcode = AMDGPU::SI_SPILL_S512_RESTORE; break;
473 default: llvm_unreachable("Cannot spill register class");
474 }
476 SIMachineFunctionInfo::SpilledReg Spill =
477 MFI->SpillTracker.getSpilledReg(FrameIndex);
479 BuildMI(MBB, MI, DL, get(Opcode), DestReg)
480 .addReg(Spill.VGPR)
481 .addImm(FrameIndex);
482 } else {
483 llvm_unreachable("VGPR spilling not supported");
484 }
485 }
487 static unsigned getNumSubRegsForSpillOp(unsigned Op) {
489 switch (Op) {
490 case AMDGPU::SI_SPILL_S512_SAVE:
491 case AMDGPU::SI_SPILL_S512_RESTORE:
492 return 16;
493 case AMDGPU::SI_SPILL_S256_SAVE:
494 case AMDGPU::SI_SPILL_S256_RESTORE:
495 return 8;
496 case AMDGPU::SI_SPILL_S128_SAVE:
497 case AMDGPU::SI_SPILL_S128_RESTORE:
498 return 4;
499 case AMDGPU::SI_SPILL_S64_SAVE:
500 case AMDGPU::SI_SPILL_S64_RESTORE:
501 return 2;
502 case AMDGPU::SI_SPILL_S32_RESTORE:
503 return 1;
504 default: llvm_unreachable("Invalid spill opcode");
505 }
506 }
508 void SIInstrInfo::insertNOPs(MachineBasicBlock::iterator MI,
509 int Count) const {
510 while (Count > 0) {
511 int Arg;
512 if (Count >= 8)
513 Arg = 7;
514 else
515 Arg = Count - 1;
516 Count -= 8;
517 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(AMDGPU::S_NOP))
518 .addImm(Arg);
519 }
520 }
522 bool SIInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
523 SIMachineFunctionInfo *MFI =
524 MI->getParent()->getParent()->getInfo<SIMachineFunctionInfo>();
525 MachineBasicBlock &MBB = *MI->getParent();
526 DebugLoc DL = MBB.findDebugLoc(MI);
527 switch (MI->getOpcode()) {
528 default: return AMDGPUInstrInfo::expandPostRAPseudo(MI);
530 // SGPR register spill
531 case AMDGPU::SI_SPILL_S512_SAVE:
532 case AMDGPU::SI_SPILL_S256_SAVE:
533 case AMDGPU::SI_SPILL_S128_SAVE:
534 case AMDGPU::SI_SPILL_S64_SAVE: {
535 unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
536 unsigned FrameIndex = MI->getOperand(2).getImm();
538 for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
539 SIMachineFunctionInfo::SpilledReg Spill;
540 unsigned SubReg = RI.getPhysRegSubReg(MI->getOperand(1).getReg(),
541 &AMDGPU::SGPR_32RegClass, i);
542 Spill = MFI->SpillTracker.getSpilledReg(FrameIndex);
544 BuildMI(MBB, MI, DL, get(AMDGPU::V_WRITELANE_B32),
545 MI->getOperand(0).getReg())
546 .addReg(SubReg)
547 .addImm(Spill.Lane + i);
548 }
549 MI->eraseFromParent();
550 break;
551 }
553 // SGPR register restore
554 case AMDGPU::SI_SPILL_S512_RESTORE:
555 case AMDGPU::SI_SPILL_S256_RESTORE:
556 case AMDGPU::SI_SPILL_S128_RESTORE:
557 case AMDGPU::SI_SPILL_S64_RESTORE:
558 case AMDGPU::SI_SPILL_S32_RESTORE: {
559 unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
561 for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
562 SIMachineFunctionInfo::SpilledReg Spill;
563 unsigned FrameIndex = MI->getOperand(2).getImm();
564 unsigned SubReg = RI.getPhysRegSubReg(MI->getOperand(0).getReg(),
565 &AMDGPU::SGPR_32RegClass, i);
566 Spill = MFI->SpillTracker.getSpilledReg(FrameIndex);
568 BuildMI(MBB, MI, DL, get(AMDGPU::V_READLANE_B32), SubReg)
569 .addReg(MI->getOperand(1).getReg())
570 .addImm(Spill.Lane + i);
571 }
572 insertNOPs(MI, 3);
573 MI->eraseFromParent();
574 break;
575 }
576 case AMDGPU::SI_CONSTDATA_PTR: {
577 unsigned Reg = MI->getOperand(0).getReg();
578 unsigned RegLo = RI.getSubReg(Reg, AMDGPU::sub0);
579 unsigned RegHi = RI.getSubReg(Reg, AMDGPU::sub1);
581 BuildMI(MBB, MI, DL, get(AMDGPU::S_GETPC_B64), Reg);
583 // Add 32-bit offset from this instruction to the start of the constant data.
584 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADD_I32), RegLo)
585 .addReg(RegLo)
586 .addTargetIndex(AMDGPU::TI_CONSTDATA_START)
587 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit);
588 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADDC_U32), RegHi)
589 .addReg(RegHi)
590 .addImm(0)
591 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit)
592 .addReg(AMDGPU::SCC, RegState::Implicit);
593 MI->eraseFromParent();
594 break;
595 }
596 }
597 return true;
598 }
600 MachineInstr *SIInstrInfo::commuteInstruction(MachineInstr *MI,
601 bool NewMI) const {
603 if (MI->getNumOperands() < 3 || !MI->getOperand(1).isReg())
604 return nullptr;
606 // Make sure it s legal to commute operands for VOP2.
607 if (isVOP2(MI->getOpcode()) &&
608 (!isOperandLegal(MI, 1, &MI->getOperand(2)) ||
609 !isOperandLegal(MI, 2, &MI->getOperand(1))))
610 return nullptr;
612 if (!MI->getOperand(2).isReg()) {
613 // XXX: Commute instructions with FPImm operands
614 if (NewMI || MI->getOperand(2).isFPImm() ||
615 (!isVOP2(MI->getOpcode()) && !isVOP3(MI->getOpcode()))) {
616 return nullptr;
617 }
619 // XXX: Commute VOP3 instructions with abs and neg set .
620 const MachineOperand *Abs = getNamedOperand(*MI, AMDGPU::OpName::abs);
621 const MachineOperand *Neg = getNamedOperand(*MI, AMDGPU::OpName::neg);
622 const MachineOperand *Src0Mods = getNamedOperand(*MI,
623 AMDGPU::OpName::src0_modifiers);
624 const MachineOperand *Src1Mods = getNamedOperand(*MI,
625 AMDGPU::OpName::src1_modifiers);
626 const MachineOperand *Src2Mods = getNamedOperand(*MI,
627 AMDGPU::OpName::src2_modifiers);
629 if ((Abs && Abs->getImm()) || (Neg && Neg->getImm()) ||
630 (Src0Mods && Src0Mods->getImm()) || (Src1Mods && Src1Mods->getImm()) ||
631 (Src2Mods && Src2Mods->getImm()))
632 return nullptr;
634 unsigned Reg = MI->getOperand(1).getReg();
635 unsigned SubReg = MI->getOperand(1).getSubReg();
636 MI->getOperand(1).ChangeToImmediate(MI->getOperand(2).getImm());
637 MI->getOperand(2).ChangeToRegister(Reg, false);
638 MI->getOperand(2).setSubReg(SubReg);
639 } else {
640 MI = TargetInstrInfo::commuteInstruction(MI, NewMI);
641 }
643 if (MI)
644 MI->setDesc(get(commuteOpcode(MI->getOpcode())));
646 return MI;
647 }
649 MachineInstr *SIInstrInfo::buildMovInstr(MachineBasicBlock *MBB,
650 MachineBasicBlock::iterator I,
651 unsigned DstReg,
652 unsigned SrcReg) const {
653 return BuildMI(*MBB, I, MBB->findDebugLoc(I), get(AMDGPU::V_MOV_B32_e32),
654 DstReg) .addReg(SrcReg);
655 }
657 bool SIInstrInfo::isMov(unsigned Opcode) const {
658 switch(Opcode) {
659 default: return false;
660 case AMDGPU::S_MOV_B32:
661 case AMDGPU::S_MOV_B64:
662 case AMDGPU::V_MOV_B32_e32:
663 case AMDGPU::V_MOV_B32_e64:
664 return true;
665 }
666 }
668 bool
669 SIInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
670 return RC != &AMDGPU::EXECRegRegClass;
671 }
673 bool
674 SIInstrInfo::isTriviallyReMaterializable(const MachineInstr *MI,
675 AliasAnalysis *AA) const {
676 switch(MI->getOpcode()) {
677 default: return AMDGPUInstrInfo::isTriviallyReMaterializable(MI, AA);
678 case AMDGPU::S_MOV_B32:
679 case AMDGPU::S_MOV_B64:
680 case AMDGPU::V_MOV_B32_e32:
681 return MI->getOperand(1).isImm();
682 }
683 }
685 namespace llvm {
686 namespace AMDGPU {
687 // Helper function generated by tablegen. We are wrapping this with
688 // an SIInstrInfo function that returns bool rather than int.
689 int isDS(uint16_t Opcode);
690 }
691 }
693 bool SIInstrInfo::isDS(uint16_t Opcode) const {
694 return ::AMDGPU::isDS(Opcode) != -1;
695 }
697 bool SIInstrInfo::isMIMG(uint16_t Opcode) const {
698 return get(Opcode).TSFlags & SIInstrFlags::MIMG;
699 }
701 bool SIInstrInfo::isSMRD(uint16_t Opcode) const {
702 return get(Opcode).TSFlags & SIInstrFlags::SMRD;
703 }
705 bool SIInstrInfo::isMUBUF(uint16_t Opcode) const {
706 return get(Opcode).TSFlags & SIInstrFlags::MUBUF;
707 }
709 bool SIInstrInfo::isMTBUF(uint16_t Opcode) const {
710 return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
711 }
713 bool SIInstrInfo::isVOP1(uint16_t Opcode) const {
714 return get(Opcode).TSFlags & SIInstrFlags::VOP1;
715 }
717 bool SIInstrInfo::isVOP2(uint16_t Opcode) const {
718 return get(Opcode).TSFlags & SIInstrFlags::VOP2;
719 }
721 bool SIInstrInfo::isVOP3(uint16_t Opcode) const {
722 return get(Opcode).TSFlags & SIInstrFlags::VOP3;
723 }
725 bool SIInstrInfo::isVOPC(uint16_t Opcode) const {
726 return get(Opcode).TSFlags & SIInstrFlags::VOPC;
727 }
729 bool SIInstrInfo::isSALUInstr(const MachineInstr &MI) const {
730 return get(MI.getOpcode()).TSFlags & SIInstrFlags::SALU;
731 }
733 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {
734 int32_t Val = Imm.getSExtValue();
735 if (Val >= -16 && Val <= 64)
736 return true;
738 // The actual type of the operand does not seem to matter as long
739 // as the bits match one of the inline immediate values. For example:
740 //
741 // -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
742 // so it is a legal inline immediate.
743 //
744 // 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
745 // floating-point, so it is a legal inline immediate.
747 return (APInt::floatToBits(0.0f) == Imm) ||
748 (APInt::floatToBits(1.0f) == Imm) ||
749 (APInt::floatToBits(-1.0f) == Imm) ||
750 (APInt::floatToBits(0.5f) == Imm) ||
751 (APInt::floatToBits(-0.5f) == Imm) ||
752 (APInt::floatToBits(2.0f) == Imm) ||
753 (APInt::floatToBits(-2.0f) == Imm) ||
754 (APInt::floatToBits(4.0f) == Imm) ||
755 (APInt::floatToBits(-4.0f) == Imm);
756 }
758 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO) const {
759 if (MO.isImm())
760 return isInlineConstant(APInt(32, MO.getImm(), true));
762 if (MO.isFPImm()) {
763 APFloat FpImm = MO.getFPImm()->getValueAPF();
764 return isInlineConstant(FpImm.bitcastToAPInt());
765 }
767 return false;
768 }
770 bool SIInstrInfo::isLiteralConstant(const MachineOperand &MO) const {
771 return (MO.isImm() || MO.isFPImm()) && !isInlineConstant(MO);
772 }
774 static bool compareMachineOp(const MachineOperand &Op0,
775 const MachineOperand &Op1) {
776 if (Op0.getType() != Op1.getType())
777 return false;
779 switch (Op0.getType()) {
780 case MachineOperand::MO_Register:
781 return Op0.getReg() == Op1.getReg();
782 case MachineOperand::MO_Immediate:
783 return Op0.getImm() == Op1.getImm();
784 case MachineOperand::MO_FPImmediate:
785 return Op0.getFPImm() == Op1.getFPImm();
786 default:
787 llvm_unreachable("Didn't expect to be comparing these operand types");
788 }
789 }
791 bool SIInstrInfo::isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,
792 const MachineOperand &MO) const {
793 const MCOperandInfo &OpInfo = get(MI->getOpcode()).OpInfo[OpNo];
795 assert(MO.isImm() || MO.isFPImm());
797 if (OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE)
798 return true;
800 if (OpInfo.RegClass < 0)
801 return false;
803 return RI.regClassCanUseImmediate(OpInfo.RegClass);
804 }
806 bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {
807 return AMDGPU::getVOPe32(Opcode) != -1;
808 }
810 bool SIInstrInfo::hasModifiers(unsigned Opcode) const {
811 // The src0_modifier operand is present on all instructions
812 // that have modifiers.
814 return AMDGPU::getNamedOperandIdx(Opcode,
815 AMDGPU::OpName::src0_modifiers) != -1;
816 }
818 bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
819 StringRef &ErrInfo) const {
820 uint16_t Opcode = MI->getOpcode();
821 int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
822 int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
823 int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
825 // Make sure the number of operands is correct.
826 const MCInstrDesc &Desc = get(Opcode);
827 if (!Desc.isVariadic() &&
828 Desc.getNumOperands() != MI->getNumExplicitOperands()) {
829 ErrInfo = "Instruction has wrong number of operands.";
830 return false;
831 }
833 // Make sure the register classes are correct
834 for (int i = 0, e = Desc.getNumOperands(); i != e; ++i) {
835 switch (Desc.OpInfo[i].OperandType) {
836 case MCOI::OPERAND_REGISTER: {
837 int RegClass = Desc.OpInfo[i].RegClass;
838 if (!RI.regClassCanUseImmediate(RegClass) &&
839 (MI->getOperand(i).isImm() || MI->getOperand(i).isFPImm())) {
840 // Handle some special cases:
841 // Src0 can of VOP1, VOP2, VOPC can be an immediate no matter what
842 // the register class.
843 if (i != Src0Idx || (!isVOP1(Opcode) && !isVOP2(Opcode) &&
844 !isVOPC(Opcode))) {
845 ErrInfo = "Expected register, but got immediate";
846 return false;
847 }
848 }
849 }
850 break;
851 case MCOI::OPERAND_IMMEDIATE:
852 // Check if this operand is an immediate.
853 // FrameIndex operands will be replaced by immediates, so they are
854 // allowed.
855 if (!MI->getOperand(i).isImm() && !MI->getOperand(i).isFPImm() &&
856 !MI->getOperand(i).isFI()) {
857 ErrInfo = "Expected immediate, but got non-immediate";
858 return false;
859 }
860 // Fall-through
861 default:
862 continue;
863 }
865 if (!MI->getOperand(i).isReg())
866 continue;
868 int RegClass = Desc.OpInfo[i].RegClass;
869 if (RegClass != -1) {
870 unsigned Reg = MI->getOperand(i).getReg();
871 if (TargetRegisterInfo::isVirtualRegister(Reg))
872 continue;
874 const TargetRegisterClass *RC = RI.getRegClass(RegClass);
875 if (!RC->contains(Reg)) {
876 ErrInfo = "Operand has incorrect register class.";
877 return false;
878 }
879 }
880 }
883 // Verify VOP*
884 if (isVOP1(Opcode) || isVOP2(Opcode) || isVOP3(Opcode) || isVOPC(Opcode)) {
885 unsigned ConstantBusCount = 0;
886 unsigned SGPRUsed = AMDGPU::NoRegister;
887 for (int i = 0, e = MI->getNumOperands(); i != e; ++i) {
888 const MachineOperand &MO = MI->getOperand(i);
889 if (MO.isReg() && MO.isUse() &&
890 !TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
892 // EXEC register uses the constant bus.
893 if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC)
894 ++ConstantBusCount;
896 // SGPRs use the constant bus
897 if (MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||
898 (!MO.isImplicit() &&
899 (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
900 AMDGPU::SGPR_64RegClass.contains(MO.getReg())))) {
901 if (SGPRUsed != MO.getReg()) {
902 ++ConstantBusCount;
903 SGPRUsed = MO.getReg();
904 }
905 }
906 }
907 // Literal constants use the constant bus.
908 if (isLiteralConstant(MO))
909 ++ConstantBusCount;
910 }
911 if (ConstantBusCount > 1) {
912 ErrInfo = "VOP* instruction uses the constant bus more than once";
913 return false;
914 }
915 }
917 // Verify SRC1 for VOP2 and VOPC
918 if (Src1Idx != -1 && (isVOP2(Opcode) || isVOPC(Opcode))) {
919 const MachineOperand &Src1 = MI->getOperand(Src1Idx);
920 if (Src1.isImm() || Src1.isFPImm()) {
921 ErrInfo = "VOP[2C] src1 cannot be an immediate.";
922 return false;
923 }
924 }
926 // Verify VOP3
927 if (isVOP3(Opcode)) {
928 if (Src0Idx != -1 && isLiteralConstant(MI->getOperand(Src0Idx))) {
929 ErrInfo = "VOP3 src0 cannot be a literal constant.";
930 return false;
931 }
932 if (Src1Idx != -1 && isLiteralConstant(MI->getOperand(Src1Idx))) {
933 ErrInfo = "VOP3 src1 cannot be a literal constant.";
934 return false;
935 }
936 if (Src2Idx != -1 && isLiteralConstant(MI->getOperand(Src2Idx))) {
937 ErrInfo = "VOP3 src2 cannot be a literal constant.";
938 return false;
939 }
940 }
942 // Verify misc. restrictions on specific instructions.
943 if (Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F32 ||
944 Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F64) {
945 MI->dump();
947 const MachineOperand &Src0 = MI->getOperand(2);
948 const MachineOperand &Src1 = MI->getOperand(3);
949 const MachineOperand &Src2 = MI->getOperand(4);
950 if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {
951 if (!compareMachineOp(Src0, Src1) &&
952 !compareMachineOp(Src0, Src2)) {
953 ErrInfo = "v_div_scale_{f32|f64} require src0 = src1 or src2";
954 return false;
955 }
956 }
957 }
959 return true;
960 }
962 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) {
963 switch (MI.getOpcode()) {
964 default: return AMDGPU::INSTRUCTION_LIST_END;
965 case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;
966 case AMDGPU::COPY: return AMDGPU::COPY;
967 case AMDGPU::PHI: return AMDGPU::PHI;
968 case AMDGPU::INSERT_SUBREG: return AMDGPU::INSERT_SUBREG;
969 case AMDGPU::S_MOV_B32:
970 return MI.getOperand(1).isReg() ?
971 AMDGPU::COPY : AMDGPU::V_MOV_B32_e32;
972 case AMDGPU::S_ADD_I32: return AMDGPU::V_ADD_I32_e32;
973 case AMDGPU::S_ADDC_U32: return AMDGPU::V_ADDC_U32_e32;
974 case AMDGPU::S_SUB_I32: return AMDGPU::V_SUB_I32_e32;
975 case AMDGPU::S_SUBB_U32: return AMDGPU::V_SUBB_U32_e32;
976 case AMDGPU::S_AND_B32: return AMDGPU::V_AND_B32_e32;
977 case AMDGPU::S_OR_B32: return AMDGPU::V_OR_B32_e32;
978 case AMDGPU::S_XOR_B32: return AMDGPU::V_XOR_B32_e32;
979 case AMDGPU::S_MIN_I32: return AMDGPU::V_MIN_I32_e32;
980 case AMDGPU::S_MIN_U32: return AMDGPU::V_MIN_U32_e32;
981 case AMDGPU::S_MAX_I32: return AMDGPU::V_MAX_I32_e32;
982 case AMDGPU::S_MAX_U32: return AMDGPU::V_MAX_U32_e32;
983 case AMDGPU::S_ASHR_I32: return AMDGPU::V_ASHR_I32_e32;
984 case AMDGPU::S_ASHR_I64: return AMDGPU::V_ASHR_I64;
985 case AMDGPU::S_LSHL_B32: return AMDGPU::V_LSHL_B32_e32;
986 case AMDGPU::S_LSHL_B64: return AMDGPU::V_LSHL_B64;
987 case AMDGPU::S_LSHR_B32: return AMDGPU::V_LSHR_B32_e32;
988 case AMDGPU::S_LSHR_B64: return AMDGPU::V_LSHR_B64;
989 case AMDGPU::S_SEXT_I32_I8: return AMDGPU::V_BFE_I32;
990 case AMDGPU::S_SEXT_I32_I16: return AMDGPU::V_BFE_I32;
991 case AMDGPU::S_BFE_U32: return AMDGPU::V_BFE_U32;
992 case AMDGPU::S_BFE_I32: return AMDGPU::V_BFE_I32;
993 case AMDGPU::S_BREV_B32: return AMDGPU::V_BFREV_B32_e32;
994 case AMDGPU::S_NOT_B32: return AMDGPU::V_NOT_B32_e32;
995 case AMDGPU::S_NOT_B64: return AMDGPU::V_NOT_B32_e32;
996 case AMDGPU::S_CMP_EQ_I32: return AMDGPU::V_CMP_EQ_I32_e32;
997 case AMDGPU::S_CMP_LG_I32: return AMDGPU::V_CMP_NE_I32_e32;
998 case AMDGPU::S_CMP_GT_I32: return AMDGPU::V_CMP_GT_I32_e32;
999 case AMDGPU::S_CMP_GE_I32: return AMDGPU::V_CMP_GE_I32_e32;
1000 case AMDGPU::S_CMP_LT_I32: return AMDGPU::V_CMP_LT_I32_e32;
1001 case AMDGPU::S_CMP_LE_I32: return AMDGPU::V_CMP_LE_I32_e32;
1002 case AMDGPU::S_LOAD_DWORD_IMM:
1003 case AMDGPU::S_LOAD_DWORD_SGPR: return AMDGPU::BUFFER_LOAD_DWORD_ADDR64;
1004 case AMDGPU::S_LOAD_DWORDX2_IMM:
1005 case AMDGPU::S_LOAD_DWORDX2_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
1006 case AMDGPU::S_LOAD_DWORDX4_IMM:
1007 case AMDGPU::S_LOAD_DWORDX4_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
1008 case AMDGPU::S_BCNT1_I32_B32: return AMDGPU::V_BCNT_U32_B32_e32;
1009 case AMDGPU::S_FF1_I32_B32: return AMDGPU::V_FFBL_B32_e32;
1010 case AMDGPU::S_FLBIT_I32_B32: return AMDGPU::V_FFBH_U32_e32;
1011 }
1012 }
1014 bool SIInstrInfo::isSALUOpSupportedOnVALU(const MachineInstr &MI) const {
1015 return getVALUOp(MI) != AMDGPU::INSTRUCTION_LIST_END;
1016 }
1018 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
1019 unsigned OpNo) const {
1020 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
1021 const MCInstrDesc &Desc = get(MI.getOpcode());
1022 if (MI.isVariadic() || OpNo >= Desc.getNumOperands() ||
1023 Desc.OpInfo[OpNo].RegClass == -1)
1024 return MRI.getRegClass(MI.getOperand(OpNo).getReg());
1026 unsigned RCID = Desc.OpInfo[OpNo].RegClass;
1027 return RI.getRegClass(RCID);
1028 }
1030 bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const {
1031 switch (MI.getOpcode()) {
1032 case AMDGPU::COPY:
1033 case AMDGPU::REG_SEQUENCE:
1034 case AMDGPU::PHI:
1035 case AMDGPU::INSERT_SUBREG:
1036 return RI.hasVGPRs(getOpRegClass(MI, 0));
1037 default:
1038 return RI.hasVGPRs(getOpRegClass(MI, OpNo));
1039 }
1040 }
1042 void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const {
1043 MachineBasicBlock::iterator I = MI;
1044 MachineOperand &MO = MI->getOperand(OpIdx);
1045 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1046 unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass;
1047 const TargetRegisterClass *RC = RI.getRegClass(RCID);
1048 unsigned Opcode = AMDGPU::V_MOV_B32_e32;
1049 if (MO.isReg()) {
1050 Opcode = AMDGPU::COPY;
1051 } else if (RI.isSGPRClass(RC)) {
1052 Opcode = AMDGPU::S_MOV_B32;
1053 }
1055 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
1056 unsigned Reg = MRI.createVirtualRegister(VRC);
1057 BuildMI(*MI->getParent(), I, MI->getParent()->findDebugLoc(I), get(Opcode),
1058 Reg).addOperand(MO);
1059 MO.ChangeToRegister(Reg, false);
1060 }
1062 unsigned SIInstrInfo::buildExtractSubReg(MachineBasicBlock::iterator MI,
1063 MachineRegisterInfo &MRI,
1064 MachineOperand &SuperReg,
1065 const TargetRegisterClass *SuperRC,
1066 unsigned SubIdx,
1067 const TargetRegisterClass *SubRC)
1068 const {
1069 assert(SuperReg.isReg());
1071 unsigned NewSuperReg = MRI.createVirtualRegister(SuperRC);
1072 unsigned SubReg = MRI.createVirtualRegister(SubRC);
1074 // Just in case the super register is itself a sub-register, copy it to a new
1075 // value so we don't need to worry about merging its subreg index with the
1076 // SubIdx passed to this function. The register coalescer should be able to
1077 // eliminate this extra copy.
1078 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(TargetOpcode::COPY),
1079 NewSuperReg)
1080 .addOperand(SuperReg);
1082 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(TargetOpcode::COPY),
1083 SubReg)
1084 .addReg(NewSuperReg, 0, SubIdx);
1085 return SubReg;
1086 }
1088 MachineOperand SIInstrInfo::buildExtractSubRegOrImm(
1089 MachineBasicBlock::iterator MII,
1090 MachineRegisterInfo &MRI,
1091 MachineOperand &Op,
1092 const TargetRegisterClass *SuperRC,
1093 unsigned SubIdx,
1094 const TargetRegisterClass *SubRC) const {
1095 if (Op.isImm()) {
1096 // XXX - Is there a better way to do this?
1097 if (SubIdx == AMDGPU::sub0)
1098 return MachineOperand::CreateImm(Op.getImm() & 0xFFFFFFFF);
1099 if (SubIdx == AMDGPU::sub1)
1100 return MachineOperand::CreateImm(Op.getImm() >> 32);
1102 llvm_unreachable("Unhandled register index for immediate");
1103 }
1105 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC,
1106 SubIdx, SubRC);
1107 return MachineOperand::CreateReg(SubReg, false);
1108 }
1110 unsigned SIInstrInfo::split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist,
1111 MachineBasicBlock::iterator MI,
1112 MachineRegisterInfo &MRI,
1113 const TargetRegisterClass *RC,
1114 const MachineOperand &Op) const {
1115 MachineBasicBlock *MBB = MI->getParent();
1116 DebugLoc DL = MI->getDebugLoc();
1117 unsigned LoDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1118 unsigned HiDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1119 unsigned Dst = MRI.createVirtualRegister(RC);
1121 MachineInstr *Lo = BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32),
1122 LoDst)
1123 .addImm(Op.getImm() & 0xFFFFFFFF);
1124 MachineInstr *Hi = BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32),
1125 HiDst)
1126 .addImm(Op.getImm() >> 32);
1128 BuildMI(*MBB, MI, DL, get(TargetOpcode::REG_SEQUENCE), Dst)
1129 .addReg(LoDst)
1130 .addImm(AMDGPU::sub0)
1131 .addReg(HiDst)
1132 .addImm(AMDGPU::sub1);
1134 Worklist.push_back(Lo);
1135 Worklist.push_back(Hi);
1137 return Dst;
1138 }
1140 bool SIInstrInfo::isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
1141 const MachineOperand *MO) const {
1142 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1143 const MCInstrDesc &InstDesc = get(MI->getOpcode());
1144 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx];
1145 const TargetRegisterClass *DefinedRC =
1146 OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;
1147 if (!MO)
1148 MO = &MI->getOperand(OpIdx);
1150 if (MO->isReg()) {
1151 assert(DefinedRC);
1152 const TargetRegisterClass *RC = MRI.getRegClass(MO->getReg());
1153 return RI.getCommonSubClass(RC, RI.getRegClass(OpInfo.RegClass));
1154 }
1157 // Handle non-register types that are treated like immediates.
1158 assert(MO->isImm() || MO->isFPImm() || MO->isTargetIndex() || MO->isFI());
1160 if (!DefinedRC)
1161 // This opperand expects an immediate
1162 return true;
1164 return RI.regClassCanUseImmediate(DefinedRC);
1165 }
1167 void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
1168 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1170 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1171 AMDGPU::OpName::src0);
1172 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1173 AMDGPU::OpName::src1);
1174 int Src2Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1175 AMDGPU::OpName::src2);
1177 // Legalize VOP2
1178 if (isVOP2(MI->getOpcode()) && Src1Idx != -1) {
1179 // Legalize src0
1180 if (!isOperandLegal(MI, Src0Idx))
1181 legalizeOpWithMove(MI, Src0Idx);
1183 // Legalize src1
1184 if (isOperandLegal(MI, Src1Idx))
1185 return;
1187 // Usually src0 of VOP2 instructions allow more types of inputs
1188 // than src1, so try to commute the instruction to decrease our
1189 // chances of having to insert a MOV instruction to legalize src1.
1190 if (MI->isCommutable()) {
1191 if (commuteInstruction(MI))
1192 // If we are successful in commuting, then we know MI is legal, so
1193 // we are done.
1194 return;
1195 }
1197 legalizeOpWithMove(MI, Src1Idx);
1198 return;
1199 }
1201 // XXX - Do any VOP3 instructions read VCC?
1202 // Legalize VOP3
1203 if (isVOP3(MI->getOpcode())) {
1204 int VOP3Idx[3] = {Src0Idx, Src1Idx, Src2Idx};
1205 unsigned SGPRReg = AMDGPU::NoRegister;
1206 for (unsigned i = 0; i < 3; ++i) {
1207 int Idx = VOP3Idx[i];
1208 if (Idx == -1)
1209 continue;
1210 MachineOperand &MO = MI->getOperand(Idx);
1212 if (MO.isReg()) {
1213 if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
1214 continue; // VGPRs are legal
1216 assert(MO.getReg() != AMDGPU::SCC && "SCC operand to VOP3 instruction");
1218 if (SGPRReg == AMDGPU::NoRegister || SGPRReg == MO.getReg()) {
1219 SGPRReg = MO.getReg();
1220 // We can use one SGPR in each VOP3 instruction.
1221 continue;
1222 }
1223 } else if (!isLiteralConstant(MO)) {
1224 // If it is not a register and not a literal constant, then it must be
1225 // an inline constant which is always legal.
1226 continue;
1227 }
1228 // If we make it this far, then the operand is not legal and we must
1229 // legalize it.
1230 legalizeOpWithMove(MI, Idx);
1231 }
1232 }
1234 // Legalize REG_SEQUENCE and PHI
1235 // The register class of the operands much be the same type as the register
1236 // class of the output.
1237 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE ||
1238 MI->getOpcode() == AMDGPU::PHI) {
1239 const TargetRegisterClass *RC = nullptr, *SRC = nullptr, *VRC = nullptr;
1240 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
1241 if (!MI->getOperand(i).isReg() ||
1242 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
1243 continue;
1244 const TargetRegisterClass *OpRC =
1245 MRI.getRegClass(MI->getOperand(i).getReg());
1246 if (RI.hasVGPRs(OpRC)) {
1247 VRC = OpRC;
1248 } else {
1249 SRC = OpRC;
1250 }
1251 }
1253 // If any of the operands are VGPR registers, then they all most be
1254 // otherwise we will create illegal VGPR->SGPR copies when legalizing
1255 // them.
1256 if (VRC || !RI.isSGPRClass(getOpRegClass(*MI, 0))) {
1257 if (!VRC) {
1258 assert(SRC);
1259 VRC = RI.getEquivalentVGPRClass(SRC);
1260 }
1261 RC = VRC;
1262 } else {
1263 RC = SRC;
1264 }
1266 // Update all the operands so they have the same type.
1267 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
1268 if (!MI->getOperand(i).isReg() ||
1269 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
1270 continue;
1271 unsigned DstReg = MRI.createVirtualRegister(RC);
1272 MachineBasicBlock *InsertBB;
1273 MachineBasicBlock::iterator Insert;
1274 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE) {
1275 InsertBB = MI->getParent();
1276 Insert = MI;
1277 } else {
1278 // MI is a PHI instruction.
1279 InsertBB = MI->getOperand(i + 1).getMBB();
1280 Insert = InsertBB->getFirstTerminator();
1281 }
1282 BuildMI(*InsertBB, Insert, MI->getDebugLoc(),
1283 get(AMDGPU::COPY), DstReg)
1284 .addOperand(MI->getOperand(i));
1285 MI->getOperand(i).setReg(DstReg);
1286 }
1287 }
1289 // Legalize INSERT_SUBREG
1290 // src0 must have the same register class as dst
1291 if (MI->getOpcode() == AMDGPU::INSERT_SUBREG) {
1292 unsigned Dst = MI->getOperand(0).getReg();
1293 unsigned Src0 = MI->getOperand(1).getReg();
1294 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
1295 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);
1296 if (DstRC != Src0RC) {
1297 MachineBasicBlock &MBB = *MI->getParent();
1298 unsigned NewSrc0 = MRI.createVirtualRegister(DstRC);
1299 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::COPY), NewSrc0)
1300 .addReg(Src0);
1301 MI->getOperand(1).setReg(NewSrc0);
1302 }
1303 return;
1304 }
1306 // Legalize MUBUF* instructions
1307 // FIXME: If we start using the non-addr64 instructions for compute, we
1308 // may need to legalize them here.
1309 int SRsrcIdx =
1310 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::srsrc);
1311 if (SRsrcIdx != -1) {
1312 // We have an MUBUF instruction
1313 MachineOperand *SRsrc = &MI->getOperand(SRsrcIdx);
1314 unsigned SRsrcRC = get(MI->getOpcode()).OpInfo[SRsrcIdx].RegClass;
1315 if (RI.getCommonSubClass(MRI.getRegClass(SRsrc->getReg()),
1316 RI.getRegClass(SRsrcRC))) {
1317 // The operands are legal.
1318 // FIXME: We may need to legalize operands besided srsrc.
1319 return;
1320 }
1322 MachineBasicBlock &MBB = *MI->getParent();
1323 // Extract the the ptr from the resource descriptor.
1325 // SRsrcPtrLo = srsrc:sub0
1326 unsigned SRsrcPtrLo = buildExtractSubReg(MI, MRI, *SRsrc,
1327 &AMDGPU::VReg_128RegClass, AMDGPU::sub0, &AMDGPU::VReg_32RegClass);
1329 // SRsrcPtrHi = srsrc:sub1
1330 unsigned SRsrcPtrHi = buildExtractSubReg(MI, MRI, *SRsrc,
1331 &AMDGPU::VReg_128RegClass, AMDGPU::sub1, &AMDGPU::VReg_32RegClass);
1333 // Create an empty resource descriptor
1334 unsigned Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
1335 unsigned SRsrcFormatLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1336 unsigned SRsrcFormatHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1337 unsigned NewSRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
1339 // Zero64 = 0
1340 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B64),
1341 Zero64)
1342 .addImm(0);
1344 // SRsrcFormatLo = RSRC_DATA_FORMAT{31-0}
1345 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1346 SRsrcFormatLo)
1347 .addImm(AMDGPU::RSRC_DATA_FORMAT & 0xFFFFFFFF);
1349 // SRsrcFormatHi = RSRC_DATA_FORMAT{63-32}
1350 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1351 SRsrcFormatHi)
1352 .addImm(AMDGPU::RSRC_DATA_FORMAT >> 32);
1354 // NewSRsrc = {Zero64, SRsrcFormat}
1355 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
1356 NewSRsrc)
1357 .addReg(Zero64)
1358 .addImm(AMDGPU::sub0_sub1)
1359 .addReg(SRsrcFormatLo)
1360 .addImm(AMDGPU::sub2)
1361 .addReg(SRsrcFormatHi)
1362 .addImm(AMDGPU::sub3);
1364 MachineOperand *VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr);
1365 unsigned NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
1366 unsigned NewVAddrLo;
1367 unsigned NewVAddrHi;
1368 if (VAddr) {
1369 // This is already an ADDR64 instruction so we need to add the pointer
1370 // extracted from the resource descriptor to the current value of VAddr.
1371 NewVAddrLo = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
1372 NewVAddrHi = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
1374 // NewVaddrLo = SRsrcPtrLo + VAddr:sub0
1375 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADD_I32_e32),
1376 NewVAddrLo)
1377 .addReg(SRsrcPtrLo)
1378 .addReg(VAddr->getReg(), 0, AMDGPU::sub0)
1379 .addReg(AMDGPU::VCC, RegState::ImplicitDefine);
1381 // NewVaddrHi = SRsrcPtrHi + VAddr:sub1
1382 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADDC_U32_e32),
1383 NewVAddrHi)
1384 .addReg(SRsrcPtrHi)
1385 .addReg(VAddr->getReg(), 0, AMDGPU::sub1)
1386 .addReg(AMDGPU::VCC, RegState::ImplicitDefine)
1387 .addReg(AMDGPU::VCC, RegState::Implicit);
1389 } else {
1390 // This instructions is the _OFFSET variant, so we need to convert it to
1391 // ADDR64.
1392 MachineOperand *VData = getNamedOperand(*MI, AMDGPU::OpName::vdata);
1393 MachineOperand *Offset = getNamedOperand(*MI, AMDGPU::OpName::offset);
1394 MachineOperand *SOffset = getNamedOperand(*MI, AMDGPU::OpName::soffset);
1395 assert(SOffset->isImm() && SOffset->getImm() == 0 && "Legalizing MUBUF "
1396 "with non-zero soffset is not implemented");
1397 (void)SOffset;
1399 // Create the new instruction.
1400 unsigned Addr64Opcode = AMDGPU::getAddr64Inst(MI->getOpcode());
1401 MachineInstr *Addr64 =
1402 BuildMI(MBB, MI, MI->getDebugLoc(), get(Addr64Opcode))
1403 .addOperand(*VData)
1404 .addOperand(*SRsrc)
1405 .addReg(AMDGPU::NoRegister) // Dummy value for vaddr.
1406 // This will be replaced later
1407 // with the new value of vaddr.
1408 .addOperand(*Offset);
1410 MI->removeFromParent();
1411 MI = Addr64;
1413 NewVAddrLo = SRsrcPtrLo;
1414 NewVAddrHi = SRsrcPtrHi;
1415 VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr);
1416 SRsrc = getNamedOperand(*MI, AMDGPU::OpName::srsrc);
1417 }
1419 // NewVaddr = {NewVaddrHi, NewVaddrLo}
1420 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
1421 NewVAddr)
1422 .addReg(NewVAddrLo)
1423 .addImm(AMDGPU::sub0)
1424 .addReg(NewVAddrHi)
1425 .addImm(AMDGPU::sub1);
1428 // Update the instruction to use NewVaddr
1429 VAddr->setReg(NewVAddr);
1430 // Update the instruction to use NewSRsrc
1431 SRsrc->setReg(NewSRsrc);
1432 }
1433 }
1435 void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const {
1436 MachineBasicBlock *MBB = MI->getParent();
1437 switch (MI->getOpcode()) {
1438 case AMDGPU::S_LOAD_DWORD_IMM:
1439 case AMDGPU::S_LOAD_DWORD_SGPR:
1440 case AMDGPU::S_LOAD_DWORDX2_IMM:
1441 case AMDGPU::S_LOAD_DWORDX2_SGPR:
1442 case AMDGPU::S_LOAD_DWORDX4_IMM:
1443 case AMDGPU::S_LOAD_DWORDX4_SGPR:
1444 unsigned NewOpcode = getVALUOp(*MI);
1445 unsigned RegOffset;
1446 unsigned ImmOffset;
1448 if (MI->getOperand(2).isReg()) {
1449 RegOffset = MI->getOperand(2).getReg();
1450 ImmOffset = 0;
1451 } else {
1452 assert(MI->getOperand(2).isImm());
1453 // SMRD instructions take a dword offsets and MUBUF instructions
1454 // take a byte offset.
1455 ImmOffset = MI->getOperand(2).getImm() << 2;
1456 RegOffset = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1457 if (isUInt<12>(ImmOffset)) {
1458 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1459 RegOffset)
1460 .addImm(0);
1461 } else {
1462 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1463 RegOffset)
1464 .addImm(ImmOffset);
1465 ImmOffset = 0;
1466 }
1467 }
1469 unsigned SRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
1470 unsigned DWord0 = RegOffset;
1471 unsigned DWord1 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1472 unsigned DWord2 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1473 unsigned DWord3 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1475 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord1)
1476 .addImm(0);
1477 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord2)
1478 .addImm(AMDGPU::RSRC_DATA_FORMAT & 0xFFFFFFFF);
1479 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord3)
1480 .addImm(AMDGPU::RSRC_DATA_FORMAT >> 32);
1481 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), SRsrc)
1482 .addReg(DWord0)
1483 .addImm(AMDGPU::sub0)
1484 .addReg(DWord1)
1485 .addImm(AMDGPU::sub1)
1486 .addReg(DWord2)
1487 .addImm(AMDGPU::sub2)
1488 .addReg(DWord3)
1489 .addImm(AMDGPU::sub3);
1490 MI->setDesc(get(NewOpcode));
1491 if (MI->getOperand(2).isReg()) {
1492 MI->getOperand(2).setReg(MI->getOperand(1).getReg());
1493 } else {
1494 MI->getOperand(2).ChangeToRegister(MI->getOperand(1).getReg(), false);
1495 }
1496 MI->getOperand(1).setReg(SRsrc);
1497 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(ImmOffset));
1498 }
1499 }
1501 void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
1502 SmallVector<MachineInstr *, 128> Worklist;
1503 Worklist.push_back(&TopInst);
1505 while (!Worklist.empty()) {
1506 MachineInstr *Inst = Worklist.pop_back_val();
1507 MachineBasicBlock *MBB = Inst->getParent();
1508 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1510 unsigned Opcode = Inst->getOpcode();
1511 unsigned NewOpcode = getVALUOp(*Inst);
1513 // Handle some special cases
1514 switch (Opcode) {
1515 default:
1516 if (isSMRD(Inst->getOpcode())) {
1517 moveSMRDToVALU(Inst, MRI);
1518 }
1519 break;
1520 case AMDGPU::S_MOV_B64: {
1521 DebugLoc DL = Inst->getDebugLoc();
1523 // If the source operand is a register we can replace this with a
1524 // copy.
1525 if (Inst->getOperand(1).isReg()) {
1526 MachineInstr *Copy = BuildMI(*MBB, Inst, DL, get(TargetOpcode::COPY))
1527 .addOperand(Inst->getOperand(0))
1528 .addOperand(Inst->getOperand(1));
1529 Worklist.push_back(Copy);
1530 } else {
1531 // Otherwise, we need to split this into two movs, because there is
1532 // no 64-bit VALU move instruction.
1533 unsigned Reg = Inst->getOperand(0).getReg();
1534 unsigned Dst = split64BitImm(Worklist,
1535 Inst,
1536 MRI,
1537 MRI.getRegClass(Reg),
1538 Inst->getOperand(1));
1539 MRI.replaceRegWith(Reg, Dst);
1540 }
1541 Inst->eraseFromParent();
1542 continue;
1543 }
1544 case AMDGPU::S_AND_B64:
1545 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_AND_B32);
1546 Inst->eraseFromParent();
1547 continue;
1549 case AMDGPU::S_OR_B64:
1550 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_OR_B32);
1551 Inst->eraseFromParent();
1552 continue;
1554 case AMDGPU::S_XOR_B64:
1555 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_XOR_B32);
1556 Inst->eraseFromParent();
1557 continue;
1559 case AMDGPU::S_NOT_B64:
1560 splitScalar64BitUnaryOp(Worklist, Inst, AMDGPU::S_NOT_B32);
1561 Inst->eraseFromParent();
1562 continue;
1564 case AMDGPU::S_BCNT1_I32_B64:
1565 splitScalar64BitBCNT(Worklist, Inst);
1566 Inst->eraseFromParent();
1567 continue;
1569 case AMDGPU::S_BFE_U64:
1570 case AMDGPU::S_BFE_I64:
1571 case AMDGPU::S_BFM_B64:
1572 llvm_unreachable("Moving this op to VALU not implemented");
1573 }
1575 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) {
1576 // We cannot move this instruction to the VALU, so we should try to
1577 // legalize its operands instead.
1578 legalizeOperands(Inst);
1579 continue;
1580 }
1582 // Use the new VALU Opcode.
1583 const MCInstrDesc &NewDesc = get(NewOpcode);
1584 Inst->setDesc(NewDesc);
1586 // Remove any references to SCC. Vector instructions can't read from it, and
1587 // We're just about to add the implicit use / defs of VCC, and we don't want
1588 // both.
1589 for (unsigned i = Inst->getNumOperands() - 1; i > 0; --i) {
1590 MachineOperand &Op = Inst->getOperand(i);
1591 if (Op.isReg() && Op.getReg() == AMDGPU::SCC)
1592 Inst->RemoveOperand(i);
1593 }
1595 if (Opcode == AMDGPU::S_SEXT_I32_I8 || Opcode == AMDGPU::S_SEXT_I32_I16) {
1596 // We are converting these to a BFE, so we need to add the missing
1597 // operands for the size and offset.
1598 unsigned Size = (Opcode == AMDGPU::S_SEXT_I32_I8) ? 8 : 16;
1599 Inst->addOperand(MachineOperand::CreateImm(0));
1600 Inst->addOperand(MachineOperand::CreateImm(Size));
1602 } else if (Opcode == AMDGPU::S_BCNT1_I32_B32) {
1603 // The VALU version adds the second operand to the result, so insert an
1604 // extra 0 operand.
1605 Inst->addOperand(MachineOperand::CreateImm(0));
1606 }
1608 addDescImplicitUseDef(NewDesc, Inst);
1610 if (Opcode == AMDGPU::S_BFE_I32 || Opcode == AMDGPU::S_BFE_U32) {
1611 const MachineOperand &OffsetWidthOp = Inst->getOperand(2);
1612 // If we need to move this to VGPRs, we need to unpack the second operand
1613 // back into the 2 separate ones for bit offset and width.
1614 assert(OffsetWidthOp.isImm() &&
1615 "Scalar BFE is only implemented for constant width and offset");
1616 uint32_t Imm = OffsetWidthOp.getImm();
1618 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
1619 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
1620 Inst->RemoveOperand(2); // Remove old immediate.
1621 Inst->addOperand(MachineOperand::CreateImm(Offset));
1622 Inst->addOperand(MachineOperand::CreateImm(BitWidth));
1623 }
1625 // Update the destination register class.
1627 const TargetRegisterClass *NewDstRC = getOpRegClass(*Inst, 0);
1629 switch (Opcode) {
1630 // For target instructions, getOpRegClass just returns the virtual
1631 // register class associated with the operand, so we need to find an
1632 // equivalent VGPR register class in order to move the instruction to the
1633 // VALU.
1634 case AMDGPU::COPY:
1635 case AMDGPU::PHI:
1636 case AMDGPU::REG_SEQUENCE:
1637 case AMDGPU::INSERT_SUBREG:
1638 if (RI.hasVGPRs(NewDstRC))
1639 continue;
1640 NewDstRC = RI.getEquivalentVGPRClass(NewDstRC);
1641 if (!NewDstRC)
1642 continue;
1643 break;
1644 default:
1645 break;
1646 }
1648 unsigned DstReg = Inst->getOperand(0).getReg();
1649 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
1650 MRI.replaceRegWith(DstReg, NewDstReg);
1652 // Legalize the operands
1653 legalizeOperands(Inst);
1655 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(NewDstReg),
1656 E = MRI.use_end(); I != E; ++I) {
1657 MachineInstr &UseMI = *I->getParent();
1658 if (!canReadVGPR(UseMI, I.getOperandNo())) {
1659 Worklist.push_back(&UseMI);
1660 }
1661 }
1662 }
1663 }
1665 //===----------------------------------------------------------------------===//
1666 // Indirect addressing callbacks
1667 //===----------------------------------------------------------------------===//
1669 unsigned SIInstrInfo::calculateIndirectAddress(unsigned RegIndex,
1670 unsigned Channel) const {
1671 assert(Channel == 0);
1672 return RegIndex;
1673 }
1675 const TargetRegisterClass *SIInstrInfo::getIndirectAddrRegClass() const {
1676 return &AMDGPU::VReg_32RegClass;
1677 }
1679 void SIInstrInfo::splitScalar64BitUnaryOp(
1680 SmallVectorImpl<MachineInstr *> &Worklist,
1681 MachineInstr *Inst,
1682 unsigned Opcode) const {
1683 MachineBasicBlock &MBB = *Inst->getParent();
1684 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
1686 MachineOperand &Dest = Inst->getOperand(0);
1687 MachineOperand &Src0 = Inst->getOperand(1);
1688 DebugLoc DL = Inst->getDebugLoc();
1690 MachineBasicBlock::iterator MII = Inst;
1692 const MCInstrDesc &InstDesc = get(Opcode);
1693 const TargetRegisterClass *Src0RC = Src0.isReg() ?
1694 MRI.getRegClass(Src0.getReg()) :
1695 &AMDGPU::SGPR_32RegClass;
1697 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
1699 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
1700 AMDGPU::sub0, Src0SubRC);
1702 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
1703 const TargetRegisterClass *DestSubRC = RI.getSubRegClass(DestRC, AMDGPU::sub0);
1705 unsigned DestSub0 = MRI.createVirtualRegister(DestRC);
1706 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
1707 .addOperand(SrcReg0Sub0);
1709 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
1710 AMDGPU::sub1, Src0SubRC);
1712 unsigned DestSub1 = MRI.createVirtualRegister(DestSubRC);
1713 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
1714 .addOperand(SrcReg0Sub1);
1716 unsigned FullDestReg = MRI.createVirtualRegister(DestRC);
1717 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
1718 .addReg(DestSub0)
1719 .addImm(AMDGPU::sub0)
1720 .addReg(DestSub1)
1721 .addImm(AMDGPU::sub1);
1723 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
1725 // Try to legalize the operands in case we need to swap the order to keep it
1726 // valid.
1727 Worklist.push_back(LoHalf);
1728 Worklist.push_back(HiHalf);
1729 }
1731 void SIInstrInfo::splitScalar64BitBinaryOp(
1732 SmallVectorImpl<MachineInstr *> &Worklist,
1733 MachineInstr *Inst,
1734 unsigned Opcode) const {
1735 MachineBasicBlock &MBB = *Inst->getParent();
1736 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
1738 MachineOperand &Dest = Inst->getOperand(0);
1739 MachineOperand &Src0 = Inst->getOperand(1);
1740 MachineOperand &Src1 = Inst->getOperand(2);
1741 DebugLoc DL = Inst->getDebugLoc();
1743 MachineBasicBlock::iterator MII = Inst;
1745 const MCInstrDesc &InstDesc = get(Opcode);
1746 const TargetRegisterClass *Src0RC = Src0.isReg() ?
1747 MRI.getRegClass(Src0.getReg()) :
1748 &AMDGPU::SGPR_32RegClass;
1750 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
1751 const TargetRegisterClass *Src1RC = Src1.isReg() ?
1752 MRI.getRegClass(Src1.getReg()) :
1753 &AMDGPU::SGPR_32RegClass;
1755 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0);
1757 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
1758 AMDGPU::sub0, Src0SubRC);
1759 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
1760 AMDGPU::sub0, Src1SubRC);
1762 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
1763 const TargetRegisterClass *DestSubRC = RI.getSubRegClass(DestRC, AMDGPU::sub0);
1765 unsigned DestSub0 = MRI.createVirtualRegister(DestRC);
1766 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
1767 .addOperand(SrcReg0Sub0)
1768 .addOperand(SrcReg1Sub0);
1770 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
1771 AMDGPU::sub1, Src0SubRC);
1772 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
1773 AMDGPU::sub1, Src1SubRC);
1775 unsigned DestSub1 = MRI.createVirtualRegister(DestSubRC);
1776 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
1777 .addOperand(SrcReg0Sub1)
1778 .addOperand(SrcReg1Sub1);
1780 unsigned FullDestReg = MRI.createVirtualRegister(DestRC);
1781 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
1782 .addReg(DestSub0)
1783 .addImm(AMDGPU::sub0)
1784 .addReg(DestSub1)
1785 .addImm(AMDGPU::sub1);
1787 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
1789 // Try to legalize the operands in case we need to swap the order to keep it
1790 // valid.
1791 Worklist.push_back(LoHalf);
1792 Worklist.push_back(HiHalf);
1793 }
1795 void SIInstrInfo::splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
1796 MachineInstr *Inst) const {
1797 MachineBasicBlock &MBB = *Inst->getParent();
1798 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
1800 MachineBasicBlock::iterator MII = Inst;
1801 DebugLoc DL = Inst->getDebugLoc();
1803 MachineOperand &Dest = Inst->getOperand(0);
1804 MachineOperand &Src = Inst->getOperand(1);
1806 const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e32);
1807 const TargetRegisterClass *SrcRC = Src.isReg() ?
1808 MRI.getRegClass(Src.getReg()) :
1809 &AMDGPU::SGPR_32RegClass;
1811 unsigned MidReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1812 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1814 const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0);
1816 MachineOperand SrcRegSub0 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
1817 AMDGPU::sub0, SrcSubRC);
1818 MachineOperand SrcRegSub1 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
1819 AMDGPU::sub1, SrcSubRC);
1821 MachineInstr *First = BuildMI(MBB, MII, DL, InstDesc, MidReg)
1822 .addOperand(SrcRegSub0)
1823 .addImm(0);
1825 MachineInstr *Second = BuildMI(MBB, MII, DL, InstDesc, ResultReg)
1826 .addOperand(SrcRegSub1)
1827 .addReg(MidReg);
1829 MRI.replaceRegWith(Dest.getReg(), ResultReg);
1831 Worklist.push_back(First);
1832 Worklist.push_back(Second);
1833 }
1835 void SIInstrInfo::addDescImplicitUseDef(const MCInstrDesc &NewDesc,
1836 MachineInstr *Inst) const {
1837 // Add the implict and explicit register definitions.
1838 if (NewDesc.ImplicitUses) {
1839 for (unsigned i = 0; NewDesc.ImplicitUses[i]; ++i) {
1840 unsigned Reg = NewDesc.ImplicitUses[i];
1841 Inst->addOperand(MachineOperand::CreateReg(Reg, false, true));
1842 }
1843 }
1845 if (NewDesc.ImplicitDefs) {
1846 for (unsigned i = 0; NewDesc.ImplicitDefs[i]; ++i) {
1847 unsigned Reg = NewDesc.ImplicitDefs[i];
1848 Inst->addOperand(MachineOperand::CreateReg(Reg, true, true));
1849 }
1850 }
1851 }
1853 MachineInstrBuilder SIInstrInfo::buildIndirectWrite(
1854 MachineBasicBlock *MBB,
1855 MachineBasicBlock::iterator I,
1856 unsigned ValueReg,
1857 unsigned Address, unsigned OffsetReg) const {
1858 const DebugLoc &DL = MBB->findDebugLoc(I);
1859 unsigned IndirectBaseReg = AMDGPU::VReg_32RegClass.getRegister(
1860 getIndirectIndexBegin(*MBB->getParent()));
1862 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_DST_V1))
1863 .addReg(IndirectBaseReg, RegState::Define)
1864 .addOperand(I->getOperand(0))
1865 .addReg(IndirectBaseReg)
1866 .addReg(OffsetReg)
1867 .addImm(0)
1868 .addReg(ValueReg);
1869 }
1871 MachineInstrBuilder SIInstrInfo::buildIndirectRead(
1872 MachineBasicBlock *MBB,
1873 MachineBasicBlock::iterator I,
1874 unsigned ValueReg,
1875 unsigned Address, unsigned OffsetReg) const {
1876 const DebugLoc &DL = MBB->findDebugLoc(I);
1877 unsigned IndirectBaseReg = AMDGPU::VReg_32RegClass.getRegister(
1878 getIndirectIndexBegin(*MBB->getParent()));
1880 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_SRC))
1881 .addOperand(I->getOperand(0))
1882 .addOperand(I->getOperand(1))
1883 .addReg(IndirectBaseReg)
1884 .addReg(OffsetReg)
1885 .addImm(0);
1887 }
1889 void SIInstrInfo::reserveIndirectRegisters(BitVector &Reserved,
1890 const MachineFunction &MF) const {
1891 int End = getIndirectIndexEnd(MF);
1892 int Begin = getIndirectIndexBegin(MF);
1894 if (End == -1)
1895 return;
1898 for (int Index = Begin; Index <= End; ++Index)
1899 Reserved.set(AMDGPU::VReg_32RegClass.getRegister(Index));
1901 for (int Index = std::max(0, Begin - 1); Index <= End; ++Index)
1902 Reserved.set(AMDGPU::VReg_64RegClass.getRegister(Index));
1904 for (int Index = std::max(0, Begin - 2); Index <= End; ++Index)
1905 Reserved.set(AMDGPU::VReg_96RegClass.getRegister(Index));
1907 for (int Index = std::max(0, Begin - 3); Index <= End; ++Index)
1908 Reserved.set(AMDGPU::VReg_128RegClass.getRegister(Index));
1910 for (int Index = std::max(0, Begin - 7); Index <= End; ++Index)
1911 Reserved.set(AMDGPU::VReg_256RegClass.getRegister(Index));
1913 for (int Index = std::max(0, Begin - 15); Index <= End; ++Index)
1914 Reserved.set(AMDGPU::VReg_512RegClass.getRegister(Index));
1915 }
1917 MachineOperand *SIInstrInfo::getNamedOperand(MachineInstr &MI,
1918 unsigned OperandName) const {
1919 int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OperandName);
1920 if (Idx == -1)
1921 return nullptr;
1923 return &MI.getOperand(Idx);
1924 }