1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
54 #include <bitset>
55 #include <numeric>
56 #include <cctype>
57 using namespace llvm;
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
67 cl::Hidden);
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(true),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
72 cl::Hidden);
74 static cl::opt<int> ReciprocalEstimateRefinementSteps(
75 "x86-recip-refinement-steps", cl::init(1),
76 cl::desc("Specify the number of Newton-Raphson iterations applied to the "
77 "result of the hardware reciprocal estimate instruction."),
78 cl::NotHidden);
80 // Forward declarations.
81 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
82 SDValue V2);
84 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
85 SelectionDAG &DAG, SDLoc dl,
86 unsigned vectorWidth) {
87 assert((vectorWidth == 128 || vectorWidth == 256) &&
88 "Unsupported vector width");
89 EVT VT = Vec.getValueType();
90 EVT ElVT = VT.getVectorElementType();
91 unsigned Factor = VT.getSizeInBits()/vectorWidth;
92 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
93 VT.getVectorNumElements()/Factor);
95 // Extract from UNDEF is UNDEF.
96 if (Vec.getOpcode() == ISD::UNDEF)
97 return DAG.getUNDEF(ResultVT);
99 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
100 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
102 // This is the index of the first element of the vectorWidth-bit chunk
103 // we want.
104 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
105 * ElemsPerChunk);
107 // If the input is a buildvector just emit a smaller one.
108 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
109 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
110 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
111 ElemsPerChunk));
113 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
114 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
115 VecIdx);
117 return Result;
118 }
120 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
121 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
122 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
123 /// instructions or a simple subregister reference. Idx is an index in the
124 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
125 /// lowering EXTRACT_VECTOR_ELT operations easier.
126 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
127 SelectionDAG &DAG, SDLoc dl) {
128 assert((Vec.getValueType().is256BitVector() ||
129 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
130 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
131 }
133 /// Generate a DAG to grab 256-bits from a 512-bit vector.
134 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
135 SelectionDAG &DAG, SDLoc dl) {
136 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
137 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
138 }
140 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
141 unsigned IdxVal, SelectionDAG &DAG,
142 SDLoc dl, unsigned vectorWidth) {
143 assert((vectorWidth == 128 || vectorWidth == 256) &&
144 "Unsupported vector width");
145 // Inserting UNDEF is Result
146 if (Vec.getOpcode() == ISD::UNDEF)
147 return Result;
148 EVT VT = Vec.getValueType();
149 EVT ElVT = VT.getVectorElementType();
150 EVT ResultVT = Result.getValueType();
152 // Insert the relevant vectorWidth bits.
153 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
155 // This is the index of the first element of the vectorWidth-bit chunk
156 // we want.
157 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
158 * ElemsPerChunk);
160 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
161 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
162 }
164 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
165 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
166 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
167 /// simple superregister reference. Idx is an index in the 128 bits
168 /// we want. It need not be aligned to a 128-bit boundary. That makes
169 /// lowering INSERT_VECTOR_ELT operations easier.
170 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
171 SelectionDAG &DAG,SDLoc dl) {
172 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
173 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
174 }
176 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
177 SelectionDAG &DAG, SDLoc dl) {
178 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
179 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
180 }
182 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
183 /// instructions. This is used because creating CONCAT_VECTOR nodes of
184 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
185 /// large BUILD_VECTORS.
186 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
187 unsigned NumElems, SelectionDAG &DAG,
188 SDLoc dl) {
189 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
190 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
191 }
193 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
194 unsigned NumElems, SelectionDAG &DAG,
195 SDLoc dl) {
196 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
197 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
198 }
200 // FIXME: This should stop caching the target machine as soon as
201 // we can remove resetOperationActions et al.
202 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM)
203 : TargetLowering(TM) {
204 Subtarget = &TM.getSubtarget<X86Subtarget>();
205 X86ScalarSSEf64 = Subtarget->hasSSE2();
206 X86ScalarSSEf32 = Subtarget->hasSSE1();
207 TD = getDataLayout();
209 resetOperationActions();
210 }
212 void X86TargetLowering::resetOperationActions() {
213 const TargetMachine &TM = getTargetMachine();
214 static bool FirstTimeThrough = true;
216 // If none of the target options have changed, then we don't need to reset the
217 // operation actions.
218 if (!FirstTimeThrough && TO == TM.Options) return;
220 if (!FirstTimeThrough) {
221 // Reinitialize the actions.
222 initActions();
223 FirstTimeThrough = false;
224 }
226 TO = TM.Options;
228 // Set up the TargetLowering object.
229 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
231 // X86 is weird. It always uses i8 for shift amounts and setcc results.
232 setBooleanContents(ZeroOrOneBooleanContent);
233 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
234 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
236 // For 64-bit, since we have so many registers, use the ILP scheduler.
237 // For 32-bit, use the register pressure specific scheduling.
238 // For Atom, always use ILP scheduling.
239 if (Subtarget->isAtom())
240 setSchedulingPreference(Sched::ILP);
241 else if (Subtarget->is64Bit())
242 setSchedulingPreference(Sched::ILP);
243 else
244 setSchedulingPreference(Sched::RegPressure);
245 const X86RegisterInfo *RegInfo =
246 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
247 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
249 // Bypass expensive divides on Atom when compiling with O2.
250 if (TM.getOptLevel() >= CodeGenOpt::Default) {
251 if (Subtarget->hasSlowDivide32())
252 addBypassSlowDiv(32, 8);
253 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
254 addBypassSlowDiv(64, 16);
255 }
257 if (Subtarget->isTargetKnownWindowsMSVC()) {
258 // Setup Windows compiler runtime calls.
259 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
260 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
261 setLibcallName(RTLIB::SREM_I64, "_allrem");
262 setLibcallName(RTLIB::UREM_I64, "_aullrem");
263 setLibcallName(RTLIB::MUL_I64, "_allmul");
264 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
265 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
266 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
267 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
268 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
270 // The _ftol2 runtime function has an unusual calling conv, which
271 // is modeled by a special pseudo-instruction.
272 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
273 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
274 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
275 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
276 }
278 if (Subtarget->isTargetDarwin()) {
279 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
280 setUseUnderscoreSetJmp(false);
281 setUseUnderscoreLongJmp(false);
282 } else if (Subtarget->isTargetWindowsGNU()) {
283 // MS runtime is weird: it exports _setjmp, but longjmp!
284 setUseUnderscoreSetJmp(true);
285 setUseUnderscoreLongJmp(false);
286 } else {
287 setUseUnderscoreSetJmp(true);
288 setUseUnderscoreLongJmp(true);
289 }
291 // Set up the register classes.
292 addRegisterClass(MVT::i8, &X86::GR8RegClass);
293 addRegisterClass(MVT::i16, &X86::GR16RegClass);
294 addRegisterClass(MVT::i32, &X86::GR32RegClass);
295 if (Subtarget->is64Bit())
296 addRegisterClass(MVT::i64, &X86::GR64RegClass);
298 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
300 // We don't accept any truncstore of integer registers.
301 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
302 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
303 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
304 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
305 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
306 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
308 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
310 // SETOEQ and SETUNE require checking two conditions.
311 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
312 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
313 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
314 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
315 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
316 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
318 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
319 // operation.
320 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
321 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
322 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
324 if (Subtarget->is64Bit()) {
325 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
326 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
327 } else if (!TM.Options.UseSoftFloat) {
328 // We have an algorithm for SSE2->double, and we turn this into a
329 // 64-bit FILD followed by conditional FADD for other targets.
330 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
331 // We have an algorithm for SSE2, and we turn this into a 64-bit
332 // FILD for other targets.
333 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
334 }
336 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
337 // this operation.
338 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
339 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
341 if (!TM.Options.UseSoftFloat) {
342 // SSE has no i16 to fp conversion, only i32
343 if (X86ScalarSSEf32) {
344 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
345 // f32 and f64 cases are Legal, f80 case is not
346 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
347 } else {
348 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
349 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
350 }
351 } else {
352 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
353 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
354 }
356 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
357 // are Legal, f80 is custom lowered.
358 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
359 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
361 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
362 // this operation.
363 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
364 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
366 if (X86ScalarSSEf32) {
367 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
368 // f32 and f64 cases are Legal, f80 case is not
369 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
370 } else {
371 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
372 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
373 }
375 // Handle FP_TO_UINT by promoting the destination to a larger signed
376 // conversion.
377 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
378 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
379 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
381 if (Subtarget->is64Bit()) {
382 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
383 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
384 } else if (!TM.Options.UseSoftFloat) {
385 // Since AVX is a superset of SSE3, only check for SSE here.
386 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
387 // Expand FP_TO_UINT into a select.
388 // FIXME: We would like to use a Custom expander here eventually to do
389 // the optimal thing for SSE vs. the default expansion in the legalizer.
390 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
391 else
392 // With SSE3 we can use fisttpll to convert to a signed i64; without
393 // SSE, we're stuck with a fistpll.
394 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
395 }
397 if (isTargetFTOL()) {
398 // Use the _ftol2 runtime function, which has a pseudo-instruction
399 // to handle its weird calling convention.
400 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
401 }
403 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
404 if (!X86ScalarSSEf64) {
405 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
406 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
407 if (Subtarget->is64Bit()) {
408 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
409 // Without SSE, i64->f64 goes through memory.
410 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
411 }
412 }
414 // Scalar integer divide and remainder are lowered to use operations that
415 // produce two results, to match the available instructions. This exposes
416 // the two-result form to trivial CSE, which is able to combine x/y and x%y
417 // into a single instruction.
418 //
419 // Scalar integer multiply-high is also lowered to use two-result
420 // operations, to match the available instructions. However, plain multiply
421 // (low) operations are left as Legal, as there are single-result
422 // instructions for this in x86. Using the two-result multiply instructions
423 // when both high and low results are needed must be arranged by dagcombine.
424 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
425 MVT VT = IntVTs[i];
426 setOperationAction(ISD::MULHS, VT, Expand);
427 setOperationAction(ISD::MULHU, VT, Expand);
428 setOperationAction(ISD::SDIV, VT, Expand);
429 setOperationAction(ISD::UDIV, VT, Expand);
430 setOperationAction(ISD::SREM, VT, Expand);
431 setOperationAction(ISD::UREM, VT, Expand);
433 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
434 setOperationAction(ISD::ADDC, VT, Custom);
435 setOperationAction(ISD::ADDE, VT, Custom);
436 setOperationAction(ISD::SUBC, VT, Custom);
437 setOperationAction(ISD::SUBE, VT, Custom);
438 }
440 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
441 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
442 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
443 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
444 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
445 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
446 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
447 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
448 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
449 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
450 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
451 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
452 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
453 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
454 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
455 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
456 if (Subtarget->is64Bit())
457 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
458 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
459 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
460 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
461 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
462 setOperationAction(ISD::FREM , MVT::f32 , Expand);
463 setOperationAction(ISD::FREM , MVT::f64 , Expand);
464 setOperationAction(ISD::FREM , MVT::f80 , Expand);
465 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
467 // Promote the i8 variants and force them on up to i32 which has a shorter
468 // encoding.
469 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
470 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
471 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
472 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
473 if (Subtarget->hasBMI()) {
474 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
475 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
476 if (Subtarget->is64Bit())
477 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
478 } else {
479 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
480 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
481 if (Subtarget->is64Bit())
482 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
483 }
485 if (Subtarget->hasLZCNT()) {
486 // When promoting the i8 variants, force them to i32 for a shorter
487 // encoding.
488 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
489 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
490 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
491 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
492 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
493 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
494 if (Subtarget->is64Bit())
495 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
496 } else {
497 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
498 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
499 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
500 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
501 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
502 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
503 if (Subtarget->is64Bit()) {
504 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
505 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
506 }
507 }
509 // Special handling for half-precision floating point conversions.
510 // If we don't have F16C support, then lower half float conversions
511 // into library calls.
512 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
513 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
514 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
515 }
517 // There's never any support for operations beyond MVT::f32.
518 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
519 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
520 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
521 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
523 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
524 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
525 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
526 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
528 if (Subtarget->hasPOPCNT()) {
529 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
530 } else {
531 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
532 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
533 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
534 if (Subtarget->is64Bit())
535 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
536 }
538 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
540 if (!Subtarget->hasMOVBE())
541 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
543 // These should be promoted to a larger select which is supported.
544 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
545 // X86 wants to expand cmov itself.
546 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
547 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
548 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
549 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
550 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
551 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
552 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
553 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
554 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
555 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
556 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
557 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
558 if (Subtarget->is64Bit()) {
559 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
560 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
561 }
562 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
563 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
564 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
565 // support continuation, user-level threading, and etc.. As a result, no
566 // other SjLj exception interfaces are implemented and please don't build
567 // your own exception handling based on them.
568 // LLVM/Clang supports zero-cost DWARF exception handling.
569 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
570 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
572 // Darwin ABI issue.
573 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
574 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
575 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
576 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
577 if (Subtarget->is64Bit())
578 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
579 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
580 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
581 if (Subtarget->is64Bit()) {
582 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
583 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
584 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
585 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
586 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
587 }
588 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
589 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
590 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
591 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
592 if (Subtarget->is64Bit()) {
593 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
594 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
595 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
596 }
598 if (Subtarget->hasSSE1())
599 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
601 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
603 // Expand certain atomics
604 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
605 MVT VT = IntVTs[i];
606 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
607 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
608 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
609 }
611 if (Subtarget->hasCmpxchg16b()) {
612 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
613 }
615 // FIXME - use subtarget debug flags
616 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
617 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
618 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
619 }
621 if (Subtarget->is64Bit()) {
622 setExceptionPointerRegister(X86::RAX);
623 setExceptionSelectorRegister(X86::RDX);
624 } else {
625 setExceptionPointerRegister(X86::EAX);
626 setExceptionSelectorRegister(X86::EDX);
627 }
628 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
629 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
631 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
632 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
634 setOperationAction(ISD::TRAP, MVT::Other, Legal);
635 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
637 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
638 setOperationAction(ISD::VASTART , MVT::Other, Custom);
639 setOperationAction(ISD::VAEND , MVT::Other, Expand);
640 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
641 // TargetInfo::X86_64ABIBuiltinVaList
642 setOperationAction(ISD::VAARG , MVT::Other, Custom);
643 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
644 } else {
645 // TargetInfo::CharPtrBuiltinVaList
646 setOperationAction(ISD::VAARG , MVT::Other, Expand);
647 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
648 }
650 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
651 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
653 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
655 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
656 // f32 and f64 use SSE.
657 // Set up the FP register classes.
658 addRegisterClass(MVT::f32, &X86::FR32RegClass);
659 addRegisterClass(MVT::f64, &X86::FR64RegClass);
661 // Use ANDPD to simulate FABS.
662 setOperationAction(ISD::FABS , MVT::f64, Custom);
663 setOperationAction(ISD::FABS , MVT::f32, Custom);
665 // Use XORP to simulate FNEG.
666 setOperationAction(ISD::FNEG , MVT::f64, Custom);
667 setOperationAction(ISD::FNEG , MVT::f32, Custom);
669 // Use ANDPD and ORPD to simulate FCOPYSIGN.
670 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
671 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
673 // Lower this to FGETSIGNx86 plus an AND.
674 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
675 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
677 // We don't support sin/cos/fmod
678 setOperationAction(ISD::FSIN , MVT::f64, Expand);
679 setOperationAction(ISD::FCOS , MVT::f64, Expand);
680 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
681 setOperationAction(ISD::FSIN , MVT::f32, Expand);
682 setOperationAction(ISD::FCOS , MVT::f32, Expand);
683 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
685 // Expand FP immediates into loads from the stack, except for the special
686 // cases we handle.
687 addLegalFPImmediate(APFloat(+0.0)); // xorpd
688 addLegalFPImmediate(APFloat(+0.0f)); // xorps
689 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
690 // Use SSE for f32, x87 for f64.
691 // Set up the FP register classes.
692 addRegisterClass(MVT::f32, &X86::FR32RegClass);
693 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
695 // Use ANDPS to simulate FABS.
696 setOperationAction(ISD::FABS , MVT::f32, Custom);
698 // Use XORP to simulate FNEG.
699 setOperationAction(ISD::FNEG , MVT::f32, Custom);
701 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
703 // Use ANDPS and ORPS to simulate FCOPYSIGN.
704 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
705 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
707 // We don't support sin/cos/fmod
708 setOperationAction(ISD::FSIN , MVT::f32, Expand);
709 setOperationAction(ISD::FCOS , MVT::f32, Expand);
710 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
712 // Special cases we handle for FP constants.
713 addLegalFPImmediate(APFloat(+0.0f)); // xorps
714 addLegalFPImmediate(APFloat(+0.0)); // FLD0
715 addLegalFPImmediate(APFloat(+1.0)); // FLD1
716 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
717 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
719 if (!TM.Options.UnsafeFPMath) {
720 setOperationAction(ISD::FSIN , MVT::f64, Expand);
721 setOperationAction(ISD::FCOS , MVT::f64, Expand);
722 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
723 }
724 } else if (!TM.Options.UseSoftFloat) {
725 // f32 and f64 in x87.
726 // Set up the FP register classes.
727 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
728 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
730 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
731 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
732 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
733 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
735 if (!TM.Options.UnsafeFPMath) {
736 setOperationAction(ISD::FSIN , MVT::f64, Expand);
737 setOperationAction(ISD::FSIN , MVT::f32, Expand);
738 setOperationAction(ISD::FCOS , MVT::f64, Expand);
739 setOperationAction(ISD::FCOS , MVT::f32, Expand);
740 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
741 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
742 }
743 addLegalFPImmediate(APFloat(+0.0)); // FLD0
744 addLegalFPImmediate(APFloat(+1.0)); // FLD1
745 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
746 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
747 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
748 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
749 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
750 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
751 }
753 // We don't support FMA.
754 setOperationAction(ISD::FMA, MVT::f64, Expand);
755 setOperationAction(ISD::FMA, MVT::f32, Expand);
757 // Long double always uses X87.
758 if (!TM.Options.UseSoftFloat) {
759 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
760 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
761 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
762 {
763 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
764 addLegalFPImmediate(TmpFlt); // FLD0
765 TmpFlt.changeSign();
766 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
768 bool ignored;
769 APFloat TmpFlt2(+1.0);
770 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
771 &ignored);
772 addLegalFPImmediate(TmpFlt2); // FLD1
773 TmpFlt2.changeSign();
774 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
775 }
777 if (!TM.Options.UnsafeFPMath) {
778 setOperationAction(ISD::FSIN , MVT::f80, Expand);
779 setOperationAction(ISD::FCOS , MVT::f80, Expand);
780 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
781 }
783 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
784 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
785 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
786 setOperationAction(ISD::FRINT, MVT::f80, Expand);
787 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
788 setOperationAction(ISD::FMA, MVT::f80, Expand);
789 }
791 // Always use a library call for pow.
792 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
793 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
794 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
796 setOperationAction(ISD::FLOG, MVT::f80, Expand);
797 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
798 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
799 setOperationAction(ISD::FEXP, MVT::f80, Expand);
800 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
801 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
802 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
804 // First set operation action for all vector types to either promote
805 // (for widening) or expand (for scalarization). Then we will selectively
806 // turn on ones that can be effectively codegen'd.
807 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
808 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
809 MVT VT = (MVT::SimpleValueType)i;
810 setOperationAction(ISD::ADD , VT, Expand);
811 setOperationAction(ISD::SUB , VT, Expand);
812 setOperationAction(ISD::FADD, VT, Expand);
813 setOperationAction(ISD::FNEG, VT, Expand);
814 setOperationAction(ISD::FSUB, VT, Expand);
815 setOperationAction(ISD::MUL , VT, Expand);
816 setOperationAction(ISD::FMUL, VT, Expand);
817 setOperationAction(ISD::SDIV, VT, Expand);
818 setOperationAction(ISD::UDIV, VT, Expand);
819 setOperationAction(ISD::FDIV, VT, Expand);
820 setOperationAction(ISD::SREM, VT, Expand);
821 setOperationAction(ISD::UREM, VT, Expand);
822 setOperationAction(ISD::LOAD, VT, Expand);
823 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
824 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
825 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
826 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
827 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
828 setOperationAction(ISD::FABS, VT, Expand);
829 setOperationAction(ISD::FSIN, VT, Expand);
830 setOperationAction(ISD::FSINCOS, VT, Expand);
831 setOperationAction(ISD::FCOS, VT, Expand);
832 setOperationAction(ISD::FSINCOS, VT, Expand);
833 setOperationAction(ISD::FREM, VT, Expand);
834 setOperationAction(ISD::FMA, VT, Expand);
835 setOperationAction(ISD::FPOWI, VT, Expand);
836 setOperationAction(ISD::FSQRT, VT, Expand);
837 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
838 setOperationAction(ISD::FFLOOR, VT, Expand);
839 setOperationAction(ISD::FCEIL, VT, Expand);
840 setOperationAction(ISD::FTRUNC, VT, Expand);
841 setOperationAction(ISD::FRINT, VT, Expand);
842 setOperationAction(ISD::FNEARBYINT, VT, Expand);
843 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
844 setOperationAction(ISD::MULHS, VT, Expand);
845 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
846 setOperationAction(ISD::MULHU, VT, Expand);
847 setOperationAction(ISD::SDIVREM, VT, Expand);
848 setOperationAction(ISD::UDIVREM, VT, Expand);
849 setOperationAction(ISD::FPOW, VT, Expand);
850 setOperationAction(ISD::CTPOP, VT, Expand);
851 setOperationAction(ISD::CTTZ, VT, Expand);
852 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
853 setOperationAction(ISD::CTLZ, VT, Expand);
854 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
855 setOperationAction(ISD::SHL, VT, Expand);
856 setOperationAction(ISD::SRA, VT, Expand);
857 setOperationAction(ISD::SRL, VT, Expand);
858 setOperationAction(ISD::ROTL, VT, Expand);
859 setOperationAction(ISD::ROTR, VT, Expand);
860 setOperationAction(ISD::BSWAP, VT, Expand);
861 setOperationAction(ISD::SETCC, VT, Expand);
862 setOperationAction(ISD::FLOG, VT, Expand);
863 setOperationAction(ISD::FLOG2, VT, Expand);
864 setOperationAction(ISD::FLOG10, VT, Expand);
865 setOperationAction(ISD::FEXP, VT, Expand);
866 setOperationAction(ISD::FEXP2, VT, Expand);
867 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
868 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
869 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
870 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
871 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
872 setOperationAction(ISD::TRUNCATE, VT, Expand);
873 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
874 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
875 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
876 setOperationAction(ISD::VSELECT, VT, Expand);
877 setOperationAction(ISD::SELECT_CC, VT, Expand);
878 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
879 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
880 setTruncStoreAction(VT,
881 (MVT::SimpleValueType)InnerVT, Expand);
882 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
883 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
885 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
886 // we have to deal with them whether we ask for Expansion or not. Setting
887 // Expand causes its own optimisation problems though, so leave them legal.
888 if (VT.getVectorElementType() == MVT::i1)
889 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
890 }
892 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
893 // with -msoft-float, disable use of MMX as well.
894 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
895 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
896 // No operations on x86mmx supported, everything uses intrinsics.
897 }
899 // MMX-sized vectors (other than x86mmx) are expected to be expanded
900 // into smaller operations.
901 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
902 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
903 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
904 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
905 setOperationAction(ISD::AND, MVT::v8i8, Expand);
906 setOperationAction(ISD::AND, MVT::v4i16, Expand);
907 setOperationAction(ISD::AND, MVT::v2i32, Expand);
908 setOperationAction(ISD::AND, MVT::v1i64, Expand);
909 setOperationAction(ISD::OR, MVT::v8i8, Expand);
910 setOperationAction(ISD::OR, MVT::v4i16, Expand);
911 setOperationAction(ISD::OR, MVT::v2i32, Expand);
912 setOperationAction(ISD::OR, MVT::v1i64, Expand);
913 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
914 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
915 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
916 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
917 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
918 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
919 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
920 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
921 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
922 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
923 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
924 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
925 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
926 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
927 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
928 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
929 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
931 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
932 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
934 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
935 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
936 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
937 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
938 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
939 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
940 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
941 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
942 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
943 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
944 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
945 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
946 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
947 }
949 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
950 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
952 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
953 // registers cannot be used even for integer operations.
954 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
955 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
956 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
957 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
959 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
960 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
961 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
962 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
963 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
964 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
965 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
966 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
967 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
968 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
969 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
970 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
971 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
972 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
973 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
974 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
975 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
976 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
977 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
978 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
979 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
980 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
982 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
983 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
984 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
985 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
987 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
988 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
989 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
990 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
991 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
993 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
994 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
995 MVT VT = (MVT::SimpleValueType)i;
996 // Do not attempt to custom lower non-power-of-2 vectors
997 if (!isPowerOf2_32(VT.getVectorNumElements()))
998 continue;
999 // Do not attempt to custom lower non-128-bit vectors
1000 if (!VT.is128BitVector())
1001 continue;
1002 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1003 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1004 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1005 }
1007 // We support custom legalizing of sext and anyext loads for specific
1008 // memory vector types which we can load as a scalar (or sequence of
1009 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1010 // loads these must work with a single scalar load.
1011 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1012 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1013 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1014 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1015 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1016 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1017 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1018 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1019 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1021 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1022 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1023 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1024 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1025 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1026 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1028 if (Subtarget->is64Bit()) {
1029 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1030 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1031 }
1033 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1034 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1035 MVT VT = (MVT::SimpleValueType)i;
1037 // Do not attempt to promote non-128-bit vectors
1038 if (!VT.is128BitVector())
1039 continue;
1041 setOperationAction(ISD::AND, VT, Promote);
1042 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1043 setOperationAction(ISD::OR, VT, Promote);
1044 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1045 setOperationAction(ISD::XOR, VT, Promote);
1046 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1047 setOperationAction(ISD::LOAD, VT, Promote);
1048 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1049 setOperationAction(ISD::SELECT, VT, Promote);
1050 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1051 }
1053 // Custom lower v2i64 and v2f64 selects.
1054 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1055 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1056 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1057 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1059 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1060 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1062 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1063 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1064 // As there is no 64-bit GPR available, we need build a special custom
1065 // sequence to convert from v2i32 to v2f32.
1066 if (!Subtarget->is64Bit())
1067 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1069 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1070 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1072 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1074 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1075 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1076 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1077 }
1079 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1080 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1081 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1082 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1083 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1084 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1085 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1086 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1087 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1088 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1089 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1091 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1092 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1093 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1094 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1095 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1096 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1097 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1098 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1099 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1100 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1102 // FIXME: Do we need to handle scalar-to-vector here?
1103 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1105 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1106 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1107 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1108 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1109 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1110 // There is no BLENDI for byte vectors. We don't need to custom lower
1111 // some vselects for now.
1112 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1114 // SSE41 brings specific instructions for doing vector sign extend even in
1115 // cases where we don't have SRA.
1116 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1117 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1118 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1120 // i8 and i16 vectors are custom because the source register and source
1121 // source memory operand types are not the same width. f32 vectors are
1122 // custom since the immediate controlling the insert encodes additional
1123 // information.
1124 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1125 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1126 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1127 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1129 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1130 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1131 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1132 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1134 // FIXME: these should be Legal, but that's only for the case where
1135 // the index is constant. For now custom expand to deal with that.
1136 if (Subtarget->is64Bit()) {
1137 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1138 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1139 }
1140 }
1142 if (Subtarget->hasSSE2()) {
1143 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1144 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1146 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1147 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1149 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1150 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1152 // In the customized shift lowering, the legal cases in AVX2 will be
1153 // recognized.
1154 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1155 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1157 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1158 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1160 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1161 }
1163 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1164 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1165 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1166 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1167 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1168 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1169 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1171 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1172 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1173 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1175 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1176 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1177 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1178 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1179 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1180 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1181 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1182 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1183 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1184 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1185 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1186 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1188 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1189 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1190 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1191 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1192 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1193 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1194 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1195 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1196 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1197 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1198 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1199 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1201 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1202 // even though v8i16 is a legal type.
1203 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1204 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1205 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1207 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1208 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1209 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1211 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1212 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1214 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1216 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1217 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1219 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1220 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1222 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1223 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1225 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1226 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1227 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1228 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1230 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1231 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1232 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1234 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1235 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1236 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1237 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1239 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1240 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1241 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1242 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1243 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1244 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1245 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1246 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1247 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1248 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1249 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1250 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1252 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1253 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1254 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1255 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1256 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1257 setOperationAction(ISD::FMA, MVT::f32, Legal);
1258 setOperationAction(ISD::FMA, MVT::f64, Legal);
1259 }
1261 if (Subtarget->hasInt256()) {
1262 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1263 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1264 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1265 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1267 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1268 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1269 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1270 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1272 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1273 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1274 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1275 // Don't lower v32i8 because there is no 128-bit byte mul
1277 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1278 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1279 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1280 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1282 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1283 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1285 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1286 // when we have a 256bit-wide blend with immediate.
1287 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1288 } else {
1289 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1290 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1291 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1292 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1294 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1295 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1296 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1297 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1299 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1300 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1301 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1302 // Don't lower v32i8 because there is no 128-bit byte mul
1303 }
1305 // In the customized shift lowering, the legal cases in AVX2 will be
1306 // recognized.
1307 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1308 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1310 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1311 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1313 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1315 // Custom lower several nodes for 256-bit types.
1316 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1317 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1318 MVT VT = (MVT::SimpleValueType)i;
1320 // Extract subvector is special because the value type
1321 // (result) is 128-bit but the source is 256-bit wide.
1322 if (VT.is128BitVector()) {
1323 if (VT.getScalarSizeInBits() >= 32) {
1324 setOperationAction(ISD::MLOAD, VT, Custom);
1325 setOperationAction(ISD::MSTORE, VT, Custom);
1326 }
1327 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1328 }
1329 // Do not attempt to custom lower other non-256-bit vectors
1330 if (!VT.is256BitVector())
1331 continue;
1333 if (VT.getScalarSizeInBits() >= 32) {
1334 setOperationAction(ISD::MLOAD, VT, Legal);
1335 setOperationAction(ISD::MSTORE, VT, Legal);
1336 }
1337 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1338 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1339 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1340 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1341 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1342 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1343 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1344 }
1346 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1347 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1348 MVT VT = (MVT::SimpleValueType)i;
1350 // Do not attempt to promote non-256-bit vectors
1351 if (!VT.is256BitVector())
1352 continue;
1354 setOperationAction(ISD::AND, VT, Promote);
1355 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1356 setOperationAction(ISD::OR, VT, Promote);
1357 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1358 setOperationAction(ISD::XOR, VT, Promote);
1359 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1360 setOperationAction(ISD::LOAD, VT, Promote);
1361 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1362 setOperationAction(ISD::SELECT, VT, Promote);
1363 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1364 }
1365 }
1367 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1368 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1369 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1370 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1371 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1373 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1374 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1375 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1377 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1378 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1379 setOperationAction(ISD::XOR, MVT::i1, Legal);
1380 setOperationAction(ISD::OR, MVT::i1, Legal);
1381 setOperationAction(ISD::AND, MVT::i1, Legal);
1382 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1383 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1384 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1385 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1386 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1387 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1389 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1390 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1391 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1392 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1393 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1394 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1396 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1397 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1398 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1399 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1400 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1401 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1402 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1403 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1405 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1406 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1407 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1408 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1409 if (Subtarget->is64Bit()) {
1410 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1411 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1412 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1413 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1414 }
1415 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1416 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1417 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1418 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1419 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1420 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1421 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1422 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1423 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1424 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1425 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1426 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1427 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1428 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1430 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1431 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1432 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1433 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1434 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1435 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1436 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1437 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1438 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1439 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1440 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1441 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1442 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1444 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1445 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1446 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1447 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1448 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1449 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1451 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1452 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1454 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1456 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1457 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1458 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1459 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1460 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1461 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1462 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1463 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1464 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1466 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1467 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1469 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1470 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1472 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1474 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1475 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1477 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1478 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1480 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1481 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1483 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1484 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1485 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1486 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1487 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1488 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1490 if (Subtarget->hasCDI()) {
1491 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1492 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1493 }
1495 // Custom lower several nodes.
1496 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1497 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1498 MVT VT = (MVT::SimpleValueType)i;
1500 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1501 // Extract subvector is special because the value type
1502 // (result) is 256/128-bit but the source is 512-bit wide.
1503 if (VT.is128BitVector() || VT.is256BitVector()) {
1504 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1505 if ( EltSize >= 32) {
1506 setOperationAction(ISD::MLOAD, VT, Legal);
1507 setOperationAction(ISD::MSTORE, VT, Legal);
1508 }
1509 }
1510 if (VT.getVectorElementType() == MVT::i1)
1511 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1513 // Do not attempt to custom lower other non-512-bit vectors
1514 if (!VT.is512BitVector())
1515 continue;
1517 if ( EltSize >= 32) {
1518 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1519 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1520 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1521 setOperationAction(ISD::VSELECT, VT, Legal);
1522 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1523 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1524 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1525 setOperationAction(ISD::MLOAD, VT, Legal);
1526 setOperationAction(ISD::MSTORE, VT, Legal);
1527 }
1528 }
1529 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1530 MVT VT = (MVT::SimpleValueType)i;
1532 // Do not attempt to promote non-256-bit vectors.
1533 if (!VT.is512BitVector())
1534 continue;
1536 setOperationAction(ISD::SELECT, VT, Promote);
1537 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1538 }
1539 }// has AVX-512
1541 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1542 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1543 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1545 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1546 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1548 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1549 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1550 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1551 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1553 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1554 const MVT VT = (MVT::SimpleValueType)i;
1556 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1558 // Do not attempt to promote non-256-bit vectors.
1559 if (!VT.is512BitVector())
1560 continue;
1562 if (EltSize < 32) {
1563 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1564 setOperationAction(ISD::VSELECT, VT, Legal);
1565 }
1566 }
1567 }
1569 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1570 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1571 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1573 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1574 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1575 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Legal);
1576 }
1578 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1579 // of this type with custom code.
1580 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1581 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1582 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1583 Custom);
1584 }
1586 // We want to custom lower some of our intrinsics.
1587 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1588 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1589 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1590 if (!Subtarget->is64Bit())
1591 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1593 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1594 // handle type legalization for these operations here.
1595 //
1596 // FIXME: We really should do custom legalization for addition and
1597 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1598 // than generic legalization for 64-bit multiplication-with-overflow, though.
1599 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1600 // Add/Sub/Mul with overflow operations are custom lowered.
1601 MVT VT = IntVTs[i];
1602 setOperationAction(ISD::SADDO, VT, Custom);
1603 setOperationAction(ISD::UADDO, VT, Custom);
1604 setOperationAction(ISD::SSUBO, VT, Custom);
1605 setOperationAction(ISD::USUBO, VT, Custom);
1606 setOperationAction(ISD::SMULO, VT, Custom);
1607 setOperationAction(ISD::UMULO, VT, Custom);
1608 }
1611 if (!Subtarget->is64Bit()) {
1612 // These libcalls are not available in 32-bit.
1613 setLibcallName(RTLIB::SHL_I128, nullptr);
1614 setLibcallName(RTLIB::SRL_I128, nullptr);
1615 setLibcallName(RTLIB::SRA_I128, nullptr);
1616 }
1618 // Combine sin / cos into one node or libcall if possible.
1619 if (Subtarget->hasSinCos()) {
1620 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1621 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1622 if (Subtarget->isTargetDarwin()) {
1623 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1624 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1625 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1626 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1627 }
1628 }
1630 if (Subtarget->isTargetWin64()) {
1631 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1632 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1633 setOperationAction(ISD::SREM, MVT::i128, Custom);
1634 setOperationAction(ISD::UREM, MVT::i128, Custom);
1635 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1636 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1637 }
1639 // We have target-specific dag combine patterns for the following nodes:
1640 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1641 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1642 setTargetDAGCombine(ISD::VSELECT);
1643 setTargetDAGCombine(ISD::SELECT);
1644 setTargetDAGCombine(ISD::SHL);
1645 setTargetDAGCombine(ISD::SRA);
1646 setTargetDAGCombine(ISD::SRL);
1647 setTargetDAGCombine(ISD::OR);
1648 setTargetDAGCombine(ISD::AND);
1649 setTargetDAGCombine(ISD::ADD);
1650 setTargetDAGCombine(ISD::FADD);
1651 setTargetDAGCombine(ISD::FSUB);
1652 setTargetDAGCombine(ISD::FMA);
1653 setTargetDAGCombine(ISD::SUB);
1654 setTargetDAGCombine(ISD::LOAD);
1655 setTargetDAGCombine(ISD::STORE);
1656 setTargetDAGCombine(ISD::ZERO_EXTEND);
1657 setTargetDAGCombine(ISD::ANY_EXTEND);
1658 setTargetDAGCombine(ISD::SIGN_EXTEND);
1659 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1660 setTargetDAGCombine(ISD::TRUNCATE);
1661 setTargetDAGCombine(ISD::SINT_TO_FP);
1662 setTargetDAGCombine(ISD::SETCC);
1663 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1664 setTargetDAGCombine(ISD::BUILD_VECTOR);
1665 if (Subtarget->is64Bit())
1666 setTargetDAGCombine(ISD::MUL);
1667 setTargetDAGCombine(ISD::XOR);
1669 computeRegisterProperties();
1671 // On Darwin, -Os means optimize for size without hurting performance,
1672 // do not reduce the limit.
1673 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1674 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1675 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1676 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1677 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1678 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1679 setPrefLoopAlignment(4); // 2^4 bytes.
1681 // Predictable cmov don't hurt on atom because it's in-order.
1682 PredictableSelectIsExpensive = !Subtarget->isAtom();
1684 setPrefFunctionAlignment(4); // 2^4 bytes.
1686 verifyIntrinsicTables();
1687 }
1689 // This has so far only been implemented for 64-bit MachO.
1690 bool X86TargetLowering::useLoadStackGuardNode() const {
1691 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1692 }
1694 TargetLoweringBase::LegalizeTypeAction
1695 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1696 if (ExperimentalVectorWideningLegalization &&
1697 VT.getVectorNumElements() != 1 &&
1698 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1699 return TypeWidenVector;
1701 return TargetLoweringBase::getPreferredVectorAction(VT);
1702 }
1704 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1705 if (!VT.isVector())
1706 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1708 const unsigned NumElts = VT.getVectorNumElements();
1709 const EVT EltVT = VT.getVectorElementType();
1710 if (VT.is512BitVector()) {
1711 if (Subtarget->hasAVX512())
1712 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1713 EltVT == MVT::f32 || EltVT == MVT::f64)
1714 switch(NumElts) {
1715 case 8: return MVT::v8i1;
1716 case 16: return MVT::v16i1;
1717 }
1718 if (Subtarget->hasBWI())
1719 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1720 switch(NumElts) {
1721 case 32: return MVT::v32i1;
1722 case 64: return MVT::v64i1;
1723 }
1724 }
1726 if (VT.is256BitVector() || VT.is128BitVector()) {
1727 if (Subtarget->hasVLX())
1728 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1729 EltVT == MVT::f32 || EltVT == MVT::f64)
1730 switch(NumElts) {
1731 case 2: return MVT::v2i1;
1732 case 4: return MVT::v4i1;
1733 case 8: return MVT::v8i1;
1734 }
1735 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1736 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1737 switch(NumElts) {
1738 case 8: return MVT::v8i1;
1739 case 16: return MVT::v16i1;
1740 case 32: return MVT::v32i1;
1741 }
1742 }
1744 return VT.changeVectorElementTypeToInteger();
1745 }
1747 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1748 /// the desired ByVal argument alignment.
1749 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1750 if (MaxAlign == 16)
1751 return;
1752 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1753 if (VTy->getBitWidth() == 128)
1754 MaxAlign = 16;
1755 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1756 unsigned EltAlign = 0;
1757 getMaxByValAlign(ATy->getElementType(), EltAlign);
1758 if (EltAlign > MaxAlign)
1759 MaxAlign = EltAlign;
1760 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1761 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1762 unsigned EltAlign = 0;
1763 getMaxByValAlign(STy->getElementType(i), EltAlign);
1764 if (EltAlign > MaxAlign)
1765 MaxAlign = EltAlign;
1766 if (MaxAlign == 16)
1767 break;
1768 }
1769 }
1770 }
1772 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1773 /// function arguments in the caller parameter area. For X86, aggregates
1774 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1775 /// are at 4-byte boundaries.
1776 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1777 if (Subtarget->is64Bit()) {
1778 // Max of 8 and alignment of type.
1779 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1780 if (TyAlign > 8)
1781 return TyAlign;
1782 return 8;
1783 }
1785 unsigned Align = 4;
1786 if (Subtarget->hasSSE1())
1787 getMaxByValAlign(Ty, Align);
1788 return Align;
1789 }
1791 /// getOptimalMemOpType - Returns the target specific optimal type for load
1792 /// and store operations as a result of memset, memcpy, and memmove
1793 /// lowering. If DstAlign is zero that means it's safe to destination
1794 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1795 /// means there isn't a need to check it against alignment requirement,
1796 /// probably because the source does not need to be loaded. If 'IsMemset' is
1797 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1798 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1799 /// source is constant so it does not need to be loaded.
1800 /// It returns EVT::Other if the type should be determined using generic
1801 /// target-independent logic.
1802 EVT
1803 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1804 unsigned DstAlign, unsigned SrcAlign,
1805 bool IsMemset, bool ZeroMemset,
1806 bool MemcpyStrSrc,
1807 MachineFunction &MF) const {
1808 const Function *F = MF.getFunction();
1809 if ((!IsMemset || ZeroMemset) &&
1810 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1811 Attribute::NoImplicitFloat)) {
1812 if (Size >= 16 &&
1813 (Subtarget->isUnalignedMemAccessFast() ||
1814 ((DstAlign == 0 || DstAlign >= 16) &&
1815 (SrcAlign == 0 || SrcAlign >= 16)))) {
1816 if (Size >= 32) {
1817 if (Subtarget->hasInt256())
1818 return MVT::v8i32;
1819 if (Subtarget->hasFp256())
1820 return MVT::v8f32;
1821 }
1822 if (Subtarget->hasSSE2())
1823 return MVT::v4i32;
1824 if (Subtarget->hasSSE1())
1825 return MVT::v4f32;
1826 } else if (!MemcpyStrSrc && Size >= 8 &&
1827 !Subtarget->is64Bit() &&
1828 Subtarget->hasSSE2()) {
1829 // Do not use f64 to lower memcpy if source is string constant. It's
1830 // better to use i32 to avoid the loads.
1831 return MVT::f64;
1832 }
1833 }
1834 if (Subtarget->is64Bit() && Size >= 8)
1835 return MVT::i64;
1836 return MVT::i32;
1837 }
1839 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1840 if (VT == MVT::f32)
1841 return X86ScalarSSEf32;
1842 else if (VT == MVT::f64)
1843 return X86ScalarSSEf64;
1844 return true;
1845 }
1847 bool
1848 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1849 unsigned,
1850 unsigned,
1851 bool *Fast) const {
1852 if (Fast)
1853 *Fast = Subtarget->isUnalignedMemAccessFast();
1854 return true;
1855 }
1857 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1858 /// current function. The returned value is a member of the
1859 /// MachineJumpTableInfo::JTEntryKind enum.
1860 unsigned X86TargetLowering::getJumpTableEncoding() const {
1861 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1862 // symbol.
1863 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1864 Subtarget->isPICStyleGOT())
1865 return MachineJumpTableInfo::EK_Custom32;
1867 // Otherwise, use the normal jump table encoding heuristics.
1868 return TargetLowering::getJumpTableEncoding();
1869 }
1871 const MCExpr *
1872 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1873 const MachineBasicBlock *MBB,
1874 unsigned uid,MCContext &Ctx) const{
1875 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1876 Subtarget->isPICStyleGOT());
1877 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1878 // entries.
1879 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1880 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1881 }
1883 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1884 /// jumptable.
1885 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1886 SelectionDAG &DAG) const {
1887 if (!Subtarget->is64Bit())
1888 // This doesn't have SDLoc associated with it, but is not really the
1889 // same as a Register.
1890 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1891 return Table;
1892 }
1894 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1895 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1896 /// MCExpr.
1897 const MCExpr *X86TargetLowering::
1898 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1899 MCContext &Ctx) const {
1900 // X86-64 uses RIP relative addressing based on the jump table label.
1901 if (Subtarget->isPICStyleRIPRel())
1902 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1904 // Otherwise, the reference is relative to the PIC base.
1905 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1906 }
1908 // FIXME: Why this routine is here? Move to RegInfo!
1909 std::pair<const TargetRegisterClass*, uint8_t>
1910 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1911 const TargetRegisterClass *RRC = nullptr;
1912 uint8_t Cost = 1;
1913 switch (VT.SimpleTy) {
1914 default:
1915 return TargetLowering::findRepresentativeClass(VT);
1916 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1917 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1918 break;
1919 case MVT::x86mmx:
1920 RRC = &X86::VR64RegClass;
1921 break;
1922 case MVT::f32: case MVT::f64:
1923 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1924 case MVT::v4f32: case MVT::v2f64:
1925 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1926 case MVT::v4f64:
1927 RRC = &X86::VR128RegClass;
1928 break;
1929 }
1930 return std::make_pair(RRC, Cost);
1931 }
1933 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1934 unsigned &Offset) const {
1935 if (!Subtarget->isTargetLinux())
1936 return false;
1938 if (Subtarget->is64Bit()) {
1939 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1940 Offset = 0x28;
1941 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1942 AddressSpace = 256;
1943 else
1944 AddressSpace = 257;
1945 } else {
1946 // %gs:0x14 on i386
1947 Offset = 0x14;
1948 AddressSpace = 256;
1949 }
1950 return true;
1951 }
1953 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1954 unsigned DestAS) const {
1955 assert(SrcAS != DestAS && "Expected different address spaces!");
1957 return SrcAS < 256 && DestAS < 256;
1958 }
1960 //===----------------------------------------------------------------------===//
1961 // Return Value Calling Convention Implementation
1962 //===----------------------------------------------------------------------===//
1964 #include "X86GenCallingConv.inc"
1966 bool
1967 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1968 MachineFunction &MF, bool isVarArg,
1969 const SmallVectorImpl<ISD::OutputArg> &Outs,
1970 LLVMContext &Context) const {
1971 SmallVector<CCValAssign, 16> RVLocs;
1972 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1973 return CCInfo.CheckReturn(Outs, RetCC_X86);
1974 }
1976 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1977 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1978 return ScratchRegs;
1979 }
1981 SDValue
1982 X86TargetLowering::LowerReturn(SDValue Chain,
1983 CallingConv::ID CallConv, bool isVarArg,
1984 const SmallVectorImpl<ISD::OutputArg> &Outs,
1985 const SmallVectorImpl<SDValue> &OutVals,
1986 SDLoc dl, SelectionDAG &DAG) const {
1987 MachineFunction &MF = DAG.getMachineFunction();
1988 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1990 SmallVector<CCValAssign, 16> RVLocs;
1991 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1992 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1994 SDValue Flag;
1995 SmallVector<SDValue, 6> RetOps;
1996 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1997 // Operand #1 = Bytes To Pop
1998 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1999 MVT::i16));
2001 // Copy the result values into the output registers.
2002 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2003 CCValAssign &VA = RVLocs[i];
2004 assert(VA.isRegLoc() && "Can only return in registers!");
2005 SDValue ValToCopy = OutVals[i];
2006 EVT ValVT = ValToCopy.getValueType();
2008 // Promote values to the appropriate types.
2009 if (VA.getLocInfo() == CCValAssign::SExt)
2010 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2011 else if (VA.getLocInfo() == CCValAssign::ZExt)
2012 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2013 else if (VA.getLocInfo() == CCValAssign::AExt)
2014 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2015 else if (VA.getLocInfo() == CCValAssign::BCvt)
2016 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2018 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2019 "Unexpected FP-extend for return value.");
2021 // If this is x86-64, and we disabled SSE, we can't return FP values,
2022 // or SSE or MMX vectors.
2023 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2024 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2025 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2026 report_fatal_error("SSE register return with SSE disabled");
2027 }
2028 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2029 // llvm-gcc has never done it right and no one has noticed, so this
2030 // should be OK for now.
2031 if (ValVT == MVT::f64 &&
2032 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2033 report_fatal_error("SSE2 register return with SSE2 disabled");
2035 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2036 // the RET instruction and handled by the FP Stackifier.
2037 if (VA.getLocReg() == X86::FP0 ||
2038 VA.getLocReg() == X86::FP1) {
2039 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2040 // change the value to the FP stack register class.
2041 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2042 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2043 RetOps.push_back(ValToCopy);
2044 // Don't emit a copytoreg.
2045 continue;
2046 }
2048 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2049 // which is returned in RAX / RDX.
2050 if (Subtarget->is64Bit()) {
2051 if (ValVT == MVT::x86mmx) {
2052 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2053 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2054 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2055 ValToCopy);
2056 // If we don't have SSE2 available, convert to v4f32 so the generated
2057 // register is legal.
2058 if (!Subtarget->hasSSE2())
2059 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2060 }
2061 }
2062 }
2064 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2065 Flag = Chain.getValue(1);
2066 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2067 }
2069 // The x86-64 ABIs require that for returning structs by value we copy
2070 // the sret argument into %rax/%eax (depending on ABI) for the return.
2071 // Win32 requires us to put the sret argument to %eax as well.
2072 // We saved the argument into a virtual register in the entry block,
2073 // so now we copy the value out and into %rax/%eax.
2074 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2075 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2076 MachineFunction &MF = DAG.getMachineFunction();
2077 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2078 unsigned Reg = FuncInfo->getSRetReturnReg();
2079 assert(Reg &&
2080 "SRetReturnReg should have been set in LowerFormalArguments().");
2081 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2083 unsigned RetValReg
2084 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2085 X86::RAX : X86::EAX;
2086 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2087 Flag = Chain.getValue(1);
2089 // RAX/EAX now acts like a return value.
2090 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2091 }
2093 RetOps[0] = Chain; // Update chain.
2095 // Add the flag if we have it.
2096 if (Flag.getNode())
2097 RetOps.push_back(Flag);
2099 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2100 }
2102 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2103 if (N->getNumValues() != 1)
2104 return false;
2105 if (!N->hasNUsesOfValue(1, 0))
2106 return false;
2108 SDValue TCChain = Chain;
2109 SDNode *Copy = *N->use_begin();
2110 if (Copy->getOpcode() == ISD::CopyToReg) {
2111 // If the copy has a glue operand, we conservatively assume it isn't safe to
2112 // perform a tail call.
2113 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2114 return false;
2115 TCChain = Copy->getOperand(0);
2116 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2117 return false;
2119 bool HasRet = false;
2120 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2121 UI != UE; ++UI) {
2122 if (UI->getOpcode() != X86ISD::RET_FLAG)
2123 return false;
2124 // If we are returning more than one value, we can definitely
2125 // not make a tail call see PR19530
2126 if (UI->getNumOperands() > 4)
2127 return false;
2128 if (UI->getNumOperands() == 4 &&
2129 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2130 return false;
2131 HasRet = true;
2132 }
2134 if (!HasRet)
2135 return false;
2137 Chain = TCChain;
2138 return true;
2139 }
2141 EVT
2142 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2143 ISD::NodeType ExtendKind) const {
2144 MVT ReturnMVT;
2145 // TODO: Is this also valid on 32-bit?
2146 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2147 ReturnMVT = MVT::i8;
2148 else
2149 ReturnMVT = MVT::i32;
2151 EVT MinVT = getRegisterType(Context, ReturnMVT);
2152 return VT.bitsLT(MinVT) ? MinVT : VT;
2153 }
2155 /// LowerCallResult - Lower the result values of a call into the
2156 /// appropriate copies out of appropriate physical registers.
2157 ///
2158 SDValue
2159 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2160 CallingConv::ID CallConv, bool isVarArg,
2161 const SmallVectorImpl<ISD::InputArg> &Ins,
2162 SDLoc dl, SelectionDAG &DAG,
2163 SmallVectorImpl<SDValue> &InVals) const {
2165 // Assign locations to each value returned by this call.
2166 SmallVector<CCValAssign, 16> RVLocs;
2167 bool Is64Bit = Subtarget->is64Bit();
2168 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2169 *DAG.getContext());
2170 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2172 // Copy all of the result registers out of their specified physreg.
2173 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2174 CCValAssign &VA = RVLocs[i];
2175 EVT CopyVT = VA.getValVT();
2177 // If this is x86-64, and we disabled SSE, we can't return FP values
2178 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2179 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2180 report_fatal_error("SSE register return with SSE disabled");
2181 }
2183 // If we prefer to use the value in xmm registers, copy it out as f80 and
2184 // use a truncate to move it from fp stack reg to xmm reg.
2185 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2186 isScalarFPTypeInSSEReg(VA.getValVT()))
2187 CopyVT = MVT::f80;
2189 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2190 CopyVT, InFlag).getValue(1);
2191 SDValue Val = Chain.getValue(0);
2193 if (CopyVT != VA.getValVT())
2194 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2195 // This truncation won't change the value.
2196 DAG.getIntPtrConstant(1));
2198 InFlag = Chain.getValue(2);
2199 InVals.push_back(Val);
2200 }
2202 return Chain;
2203 }
2205 //===----------------------------------------------------------------------===//
2206 // C & StdCall & Fast Calling Convention implementation
2207 //===----------------------------------------------------------------------===//
2208 // StdCall calling convention seems to be standard for many Windows' API
2209 // routines and around. It differs from C calling convention just a little:
2210 // callee should clean up the stack, not caller. Symbols should be also
2211 // decorated in some fancy way :) It doesn't support any vector arguments.
2212 // For info on fast calling convention see Fast Calling Convention (tail call)
2213 // implementation LowerX86_32FastCCCallTo.
2215 /// CallIsStructReturn - Determines whether a call uses struct return
2216 /// semantics.
2217 enum StructReturnType {
2218 NotStructReturn,
2219 RegStructReturn,
2220 StackStructReturn
2221 };
2222 static StructReturnType
2223 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2224 if (Outs.empty())
2225 return NotStructReturn;
2227 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2228 if (!Flags.isSRet())
2229 return NotStructReturn;
2230 if (Flags.isInReg())
2231 return RegStructReturn;
2232 return StackStructReturn;
2233 }
2235 /// ArgsAreStructReturn - Determines whether a function uses struct
2236 /// return semantics.
2237 static StructReturnType
2238 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2239 if (Ins.empty())
2240 return NotStructReturn;
2242 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2243 if (!Flags.isSRet())
2244 return NotStructReturn;
2245 if (Flags.isInReg())
2246 return RegStructReturn;
2247 return StackStructReturn;
2248 }
2250 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2251 /// by "Src" to address "Dst" with size and alignment information specified by
2252 /// the specific parameter attribute. The copy will be passed as a byval
2253 /// function parameter.
2254 static SDValue
2255 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2256 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2257 SDLoc dl) {
2258 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2260 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2261 /*isVolatile*/false, /*AlwaysInline=*/true,
2262 MachinePointerInfo(), MachinePointerInfo());
2263 }
2265 /// IsTailCallConvention - Return true if the calling convention is one that
2266 /// supports tail call optimization.
2267 static bool IsTailCallConvention(CallingConv::ID CC) {
2268 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2269 CC == CallingConv::HiPE);
2270 }
2272 /// \brief Return true if the calling convention is a C calling convention.
2273 static bool IsCCallConvention(CallingConv::ID CC) {
2274 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2275 CC == CallingConv::X86_64_SysV);
2276 }
2278 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2279 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2280 return false;
2282 CallSite CS(CI);
2283 CallingConv::ID CalleeCC = CS.getCallingConv();
2284 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2285 return false;
2287 return true;
2288 }
2290 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2291 /// a tailcall target by changing its ABI.
2292 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2293 bool GuaranteedTailCallOpt) {
2294 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2295 }
2297 SDValue
2298 X86TargetLowering::LowerMemArgument(SDValue Chain,
2299 CallingConv::ID CallConv,
2300 const SmallVectorImpl<ISD::InputArg> &Ins,
2301 SDLoc dl, SelectionDAG &DAG,
2302 const CCValAssign &VA,
2303 MachineFrameInfo *MFI,
2304 unsigned i) const {
2305 // Create the nodes corresponding to a load from this parameter slot.
2306 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2307 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2308 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2309 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2310 EVT ValVT;
2312 // If value is passed by pointer we have address passed instead of the value
2313 // itself.
2314 if (VA.getLocInfo() == CCValAssign::Indirect)
2315 ValVT = VA.getLocVT();
2316 else
2317 ValVT = VA.getValVT();
2319 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2320 // changed with more analysis.
2321 // In case of tail call optimization mark all arguments mutable. Since they
2322 // could be overwritten by lowering of arguments in case of a tail call.
2323 if (Flags.isByVal()) {
2324 unsigned Bytes = Flags.getByValSize();
2325 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2326 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2327 return DAG.getFrameIndex(FI, getPointerTy());
2328 } else {
2329 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2330 VA.getLocMemOffset(), isImmutable);
2331 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2332 return DAG.getLoad(ValVT, dl, Chain, FIN,
2333 MachinePointerInfo::getFixedStack(FI),
2334 false, false, false, 0);
2335 }
2336 }
2338 // FIXME: Get this from tablegen.
2339 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2340 const X86Subtarget *Subtarget) {
2341 assert(Subtarget->is64Bit());
2343 if (Subtarget->isCallingConvWin64(CallConv)) {
2344 static const MCPhysReg GPR64ArgRegsWin64[] = {
2345 X86::RCX, X86::RDX, X86::R8, X86::R9
2346 };
2347 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2348 }
2350 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2351 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2352 };
2353 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2354 }
2356 // FIXME: Get this from tablegen.
2357 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2358 CallingConv::ID CallConv,
2359 const X86Subtarget *Subtarget) {
2360 assert(Subtarget->is64Bit());
2361 if (Subtarget->isCallingConvWin64(CallConv)) {
2362 // The XMM registers which might contain var arg parameters are shadowed
2363 // in their paired GPR. So we only need to save the GPR to their home
2364 // slots.
2365 // TODO: __vectorcall will change this.
2366 return None;
2367 }
2369 const Function *Fn = MF.getFunction();
2370 bool NoImplicitFloatOps = Fn->getAttributes().
2371 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2372 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2373 "SSE register cannot be used when SSE is disabled!");
2374 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2375 !Subtarget->hasSSE1())
2376 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2377 // registers.
2378 return None;
2380 static const MCPhysReg XMMArgRegs64Bit[] = {
2381 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2382 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2383 };
2384 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2385 }
2387 SDValue
2388 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2389 CallingConv::ID CallConv,
2390 bool isVarArg,
2391 const SmallVectorImpl<ISD::InputArg> &Ins,
2392 SDLoc dl,
2393 SelectionDAG &DAG,
2394 SmallVectorImpl<SDValue> &InVals)
2395 const {
2396 MachineFunction &MF = DAG.getMachineFunction();
2397 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2399 const Function* Fn = MF.getFunction();
2400 if (Fn->hasExternalLinkage() &&
2401 Subtarget->isTargetCygMing() &&
2402 Fn->getName() == "main")
2403 FuncInfo->setForceFramePointer(true);
2405 MachineFrameInfo *MFI = MF.getFrameInfo();
2406 bool Is64Bit = Subtarget->is64Bit();
2407 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2409 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2410 "Var args not supported with calling convention fastcc, ghc or hipe");
2412 // Assign locations to all of the incoming arguments.
2413 SmallVector<CCValAssign, 16> ArgLocs;
2414 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2416 // Allocate shadow area for Win64
2417 if (IsWin64)
2418 CCInfo.AllocateStack(32, 8);
2420 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2422 unsigned LastVal = ~0U;
2423 SDValue ArgValue;
2424 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2425 CCValAssign &VA = ArgLocs[i];
2426 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2427 // places.
2428 assert(VA.getValNo() != LastVal &&
2429 "Don't support value assigned to multiple locs yet");
2430 (void)LastVal;
2431 LastVal = VA.getValNo();
2433 if (VA.isRegLoc()) {
2434 EVT RegVT = VA.getLocVT();
2435 const TargetRegisterClass *RC;
2436 if (RegVT == MVT::i32)
2437 RC = &X86::GR32RegClass;
2438 else if (Is64Bit && RegVT == MVT::i64)
2439 RC = &X86::GR64RegClass;
2440 else if (RegVT == MVT::f32)
2441 RC = &X86::FR32RegClass;
2442 else if (RegVT == MVT::f64)
2443 RC = &X86::FR64RegClass;
2444 else if (RegVT.is512BitVector())
2445 RC = &X86::VR512RegClass;
2446 else if (RegVT.is256BitVector())
2447 RC = &X86::VR256RegClass;
2448 else if (RegVT.is128BitVector())
2449 RC = &X86::VR128RegClass;
2450 else if (RegVT == MVT::x86mmx)
2451 RC = &X86::VR64RegClass;
2452 else if (RegVT == MVT::i1)
2453 RC = &X86::VK1RegClass;
2454 else if (RegVT == MVT::v8i1)
2455 RC = &X86::VK8RegClass;
2456 else if (RegVT == MVT::v16i1)
2457 RC = &X86::VK16RegClass;
2458 else if (RegVT == MVT::v32i1)
2459 RC = &X86::VK32RegClass;
2460 else if (RegVT == MVT::v64i1)
2461 RC = &X86::VK64RegClass;
2462 else
2463 llvm_unreachable("Unknown argument type!");
2465 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2466 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2468 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2469 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2470 // right size.
2471 if (VA.getLocInfo() == CCValAssign::SExt)
2472 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2473 DAG.getValueType(VA.getValVT()));
2474 else if (VA.getLocInfo() == CCValAssign::ZExt)
2475 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2476 DAG.getValueType(VA.getValVT()));
2477 else if (VA.getLocInfo() == CCValAssign::BCvt)
2478 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2480 if (VA.isExtInLoc()) {
2481 // Handle MMX values passed in XMM regs.
2482 if (RegVT.isVector())
2483 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2484 else
2485 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2486 }
2487 } else {
2488 assert(VA.isMemLoc());
2489 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2490 }
2492 // If value is passed via pointer - do a load.
2493 if (VA.getLocInfo() == CCValAssign::Indirect)
2494 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2495 MachinePointerInfo(), false, false, false, 0);
2497 InVals.push_back(ArgValue);
2498 }
2500 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2501 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2502 // The x86-64 ABIs require that for returning structs by value we copy
2503 // the sret argument into %rax/%eax (depending on ABI) for the return.
2504 // Win32 requires us to put the sret argument to %eax as well.
2505 // Save the argument into a virtual register so that we can access it
2506 // from the return points.
2507 if (Ins[i].Flags.isSRet()) {
2508 unsigned Reg = FuncInfo->getSRetReturnReg();
2509 if (!Reg) {
2510 MVT PtrTy = getPointerTy();
2511 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2512 FuncInfo->setSRetReturnReg(Reg);
2513 }
2514 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2515 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2516 break;
2517 }
2518 }
2519 }
2521 unsigned StackSize = CCInfo.getNextStackOffset();
2522 // Align stack specially for tail calls.
2523 if (FuncIsMadeTailCallSafe(CallConv,
2524 MF.getTarget().Options.GuaranteedTailCallOpt))
2525 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2527 // If the function takes variable number of arguments, make a frame index for
2528 // the start of the first vararg value... for expansion of llvm.va_start. We
2529 // can skip this if there are no va_start calls.
2530 if (MFI->hasVAStart() &&
2531 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2532 CallConv != CallingConv::X86_ThisCall))) {
2533 FuncInfo->setVarArgsFrameIndex(
2534 MFI->CreateFixedObject(1, StackSize, true));
2535 }
2537 // 64-bit calling conventions support varargs and register parameters, so we
2538 // have to do extra work to spill them in the prologue or forward them to
2539 // musttail calls.
2540 if (Is64Bit && isVarArg &&
2541 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2542 // Find the first unallocated argument registers.
2543 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2544 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2545 unsigned NumIntRegs =
2546 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2547 unsigned NumXMMRegs =
2548 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2549 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2550 "SSE register cannot be used when SSE is disabled!");
2552 // Gather all the live in physical registers.
2553 SmallVector<SDValue, 6> LiveGPRs;
2554 SmallVector<SDValue, 8> LiveXMMRegs;
2555 SDValue ALVal;
2556 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2557 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2558 LiveGPRs.push_back(
2559 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2560 }
2561 if (!ArgXMMs.empty()) {
2562 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2563 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2564 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2565 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2566 LiveXMMRegs.push_back(
2567 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2568 }
2569 }
2571 // Store them to the va_list returned by va_start.
2572 if (MFI->hasVAStart()) {
2573 if (IsWin64) {
2574 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2575 // Get to the caller-allocated home save location. Add 8 to account
2576 // for the return address.
2577 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2578 FuncInfo->setRegSaveFrameIndex(
2579 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2580 // Fixup to set vararg frame on shadow area (4 x i64).
2581 if (NumIntRegs < 4)
2582 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2583 } else {
2584 // For X86-64, if there are vararg parameters that are passed via
2585 // registers, then we must store them to their spots on the stack so
2586 // they may be loaded by deferencing the result of va_next.
2587 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2588 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2589 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2590 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2591 }
2593 // Store the integer parameter registers.
2594 SmallVector<SDValue, 8> MemOps;
2595 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2596 getPointerTy());
2597 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2598 for (SDValue Val : LiveGPRs) {
2599 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2600 DAG.getIntPtrConstant(Offset));
2601 SDValue Store =
2602 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2603 MachinePointerInfo::getFixedStack(
2604 FuncInfo->getRegSaveFrameIndex(), Offset),
2605 false, false, 0);
2606 MemOps.push_back(Store);
2607 Offset += 8;
2608 }
2610 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2611 // Now store the XMM (fp + vector) parameter registers.
2612 SmallVector<SDValue, 12> SaveXMMOps;
2613 SaveXMMOps.push_back(Chain);
2614 SaveXMMOps.push_back(ALVal);
2615 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2616 FuncInfo->getRegSaveFrameIndex()));
2617 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2618 FuncInfo->getVarArgsFPOffset()));
2619 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2620 LiveXMMRegs.end());
2621 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2622 MVT::Other, SaveXMMOps));
2623 }
2625 if (!MemOps.empty())
2626 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2627 } else {
2628 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2629 // to the liveout set on a musttail call.
2630 assert(MFI->hasMustTailInVarArgFunc());
2631 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2632 typedef X86MachineFunctionInfo::Forward Forward;
2634 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2635 unsigned VReg =
2636 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2637 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2638 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2639 }
2641 if (!ArgXMMs.empty()) {
2642 unsigned ALVReg =
2643 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2644 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2645 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2647 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2648 unsigned VReg =
2649 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2650 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2651 Forwards.push_back(
2652 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2653 }
2654 }
2655 }
2656 }
2658 // Some CCs need callee pop.
2659 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2660 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2661 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2662 } else {
2663 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2664 // If this is an sret function, the return should pop the hidden pointer.
2665 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2666 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2667 argsAreStructReturn(Ins) == StackStructReturn)
2668 FuncInfo->setBytesToPopOnReturn(4);
2669 }
2671 if (!Is64Bit) {
2672 // RegSaveFrameIndex is X86-64 only.
2673 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2674 if (CallConv == CallingConv::X86_FastCall ||
2675 CallConv == CallingConv::X86_ThisCall)
2676 // fastcc functions can't have varargs.
2677 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2678 }
2680 FuncInfo->setArgumentStackSize(StackSize);
2682 return Chain;
2683 }
2685 SDValue
2686 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2687 SDValue StackPtr, SDValue Arg,
2688 SDLoc dl, SelectionDAG &DAG,
2689 const CCValAssign &VA,
2690 ISD::ArgFlagsTy Flags) const {
2691 unsigned LocMemOffset = VA.getLocMemOffset();
2692 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2693 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2694 if (Flags.isByVal())
2695 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2697 return DAG.getStore(Chain, dl, Arg, PtrOff,
2698 MachinePointerInfo::getStack(LocMemOffset),
2699 false, false, 0);
2700 }
2702 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2703 /// optimization is performed and it is required.
2704 SDValue
2705 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2706 SDValue &OutRetAddr, SDValue Chain,
2707 bool IsTailCall, bool Is64Bit,
2708 int FPDiff, SDLoc dl) const {
2709 // Adjust the Return address stack slot.
2710 EVT VT = getPointerTy();
2711 OutRetAddr = getReturnAddressFrameIndex(DAG);
2713 // Load the "old" Return address.
2714 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2715 false, false, false, 0);
2716 return SDValue(OutRetAddr.getNode(), 1);
2717 }
2719 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2720 /// optimization is performed and it is required (FPDiff!=0).
2721 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2722 SDValue Chain, SDValue RetAddrFrIdx,
2723 EVT PtrVT, unsigned SlotSize,
2724 int FPDiff, SDLoc dl) {
2725 // Store the return address to the appropriate stack slot.
2726 if (!FPDiff) return Chain;
2727 // Calculate the new stack slot for the return address.
2728 int NewReturnAddrFI =
2729 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2730 false);
2731 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2732 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2733 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2734 false, false, 0);
2735 return Chain;
2736 }
2738 SDValue
2739 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2740 SmallVectorImpl<SDValue> &InVals) const {
2741 SelectionDAG &DAG = CLI.DAG;
2742 SDLoc &dl = CLI.DL;
2743 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2744 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2745 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2746 SDValue Chain = CLI.Chain;
2747 SDValue Callee = CLI.Callee;
2748 CallingConv::ID CallConv = CLI.CallConv;
2749 bool &isTailCall = CLI.IsTailCall;
2750 bool isVarArg = CLI.IsVarArg;
2752 MachineFunction &MF = DAG.getMachineFunction();
2753 bool Is64Bit = Subtarget->is64Bit();
2754 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2755 StructReturnType SR = callIsStructReturn(Outs);
2756 bool IsSibcall = false;
2757 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2759 if (MF.getTarget().Options.DisableTailCalls)
2760 isTailCall = false;
2762 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2763 if (IsMustTail) {
2764 // Force this to be a tail call. The verifier rules are enough to ensure
2765 // that we can lower this successfully without moving the return address
2766 // around.
2767 isTailCall = true;
2768 } else if (isTailCall) {
2769 // Check if it's really possible to do a tail call.
2770 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2771 isVarArg, SR != NotStructReturn,
2772 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2773 Outs, OutVals, Ins, DAG);
2775 // Sibcalls are automatically detected tailcalls which do not require
2776 // ABI changes.
2777 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2778 IsSibcall = true;
2780 if (isTailCall)
2781 ++NumTailCalls;
2782 }
2784 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2785 "Var args not supported with calling convention fastcc, ghc or hipe");
2787 // Analyze operands of the call, assigning locations to each operand.
2788 SmallVector<CCValAssign, 16> ArgLocs;
2789 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2791 // Allocate shadow area for Win64
2792 if (IsWin64)
2793 CCInfo.AllocateStack(32, 8);
2795 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2797 // Get a count of how many bytes are to be pushed on the stack.
2798 unsigned NumBytes = CCInfo.getNextStackOffset();
2799 if (IsSibcall)
2800 // This is a sibcall. The memory operands are available in caller's
2801 // own caller's stack.
2802 NumBytes = 0;
2803 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2804 IsTailCallConvention(CallConv))
2805 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2807 int FPDiff = 0;
2808 if (isTailCall && !IsSibcall && !IsMustTail) {
2809 // Lower arguments at fp - stackoffset + fpdiff.
2810 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2812 FPDiff = NumBytesCallerPushed - NumBytes;
2814 // Set the delta of movement of the returnaddr stackslot.
2815 // But only set if delta is greater than previous delta.
2816 if (FPDiff < X86Info->getTCReturnAddrDelta())
2817 X86Info->setTCReturnAddrDelta(FPDiff);
2818 }
2820 unsigned NumBytesToPush = NumBytes;
2821 unsigned NumBytesToPop = NumBytes;
2823 // If we have an inalloca argument, all stack space has already been allocated
2824 // for us and be right at the top of the stack. We don't support multiple
2825 // arguments passed in memory when using inalloca.
2826 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2827 NumBytesToPush = 0;
2828 if (!ArgLocs.back().isMemLoc())
2829 report_fatal_error("cannot use inalloca attribute on a register "
2830 "parameter");
2831 if (ArgLocs.back().getLocMemOffset() != 0)
2832 report_fatal_error("any parameter with the inalloca attribute must be "
2833 "the only memory argument");
2834 }
2836 if (!IsSibcall)
2837 Chain = DAG.getCALLSEQ_START(
2838 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2840 SDValue RetAddrFrIdx;
2841 // Load return address for tail calls.
2842 if (isTailCall && FPDiff)
2843 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2844 Is64Bit, FPDiff, dl);
2846 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2847 SmallVector<SDValue, 8> MemOpChains;
2848 SDValue StackPtr;
2850 // Walk the register/memloc assignments, inserting copies/loads. In the case
2851 // of tail call optimization arguments are handle later.
2852 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2853 DAG.getSubtarget().getRegisterInfo());
2854 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2855 // Skip inalloca arguments, they have already been written.
2856 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2857 if (Flags.isInAlloca())
2858 continue;
2860 CCValAssign &VA = ArgLocs[i];
2861 EVT RegVT = VA.getLocVT();
2862 SDValue Arg = OutVals[i];
2863 bool isByVal = Flags.isByVal();
2865 // Promote the value if needed.
2866 switch (VA.getLocInfo()) {
2867 default: llvm_unreachable("Unknown loc info!");
2868 case CCValAssign::Full: break;
2869 case CCValAssign::SExt:
2870 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2871 break;
2872 case CCValAssign::ZExt:
2873 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2874 break;
2875 case CCValAssign::AExt:
2876 if (RegVT.is128BitVector()) {
2877 // Special case: passing MMX values in XMM registers.
2878 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2879 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2880 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2881 } else
2882 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2883 break;
2884 case CCValAssign::BCvt:
2885 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2886 break;
2887 case CCValAssign::Indirect: {
2888 // Store the argument.
2889 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2890 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2891 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2892 MachinePointerInfo::getFixedStack(FI),
2893 false, false, 0);
2894 Arg = SpillSlot;
2895 break;
2896 }
2897 }
2899 if (VA.isRegLoc()) {
2900 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2901 if (isVarArg && IsWin64) {
2902 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2903 // shadow reg if callee is a varargs function.
2904 unsigned ShadowReg = 0;
2905 switch (VA.getLocReg()) {
2906 case X86::XMM0: ShadowReg = X86::RCX; break;
2907 case X86::XMM1: ShadowReg = X86::RDX; break;
2908 case X86::XMM2: ShadowReg = X86::R8; break;
2909 case X86::XMM3: ShadowReg = X86::R9; break;
2910 }
2911 if (ShadowReg)
2912 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2913 }
2914 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2915 assert(VA.isMemLoc());
2916 if (!StackPtr.getNode())
2917 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2918 getPointerTy());
2919 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2920 dl, DAG, VA, Flags));
2921 }
2922 }
2924 if (!MemOpChains.empty())
2925 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2927 if (Subtarget->isPICStyleGOT()) {
2928 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2929 // GOT pointer.
2930 if (!isTailCall) {
2931 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2932 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2933 } else {
2934 // If we are tail calling and generating PIC/GOT style code load the
2935 // address of the callee into ECX. The value in ecx is used as target of
2936 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2937 // for tail calls on PIC/GOT architectures. Normally we would just put the
2938 // address of GOT into ebx and then call target@PLT. But for tail calls
2939 // ebx would be restored (since ebx is callee saved) before jumping to the
2940 // target@PLT.
2942 // Note: The actual moving to ECX is done further down.
2943 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2944 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2945 !G->getGlobal()->hasProtectedVisibility())
2946 Callee = LowerGlobalAddress(Callee, DAG);
2947 else if (isa<ExternalSymbolSDNode>(Callee))
2948 Callee = LowerExternalSymbol(Callee, DAG);
2949 }
2950 }
2952 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2953 // From AMD64 ABI document:
2954 // For calls that may call functions that use varargs or stdargs
2955 // (prototype-less calls or calls to functions containing ellipsis (...) in
2956 // the declaration) %al is used as hidden argument to specify the number
2957 // of SSE registers used. The contents of %al do not need to match exactly
2958 // the number of registers, but must be an ubound on the number of SSE
2959 // registers used and is in the range 0 - 8 inclusive.
2961 // Count the number of XMM registers allocated.
2962 static const MCPhysReg XMMArgRegs[] = {
2963 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2964 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2965 };
2966 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2967 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2968 && "SSE registers cannot be used when SSE is disabled");
2970 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2971 DAG.getConstant(NumXMMRegs, MVT::i8)));
2972 }
2974 if (Is64Bit && isVarArg && IsMustTail) {
2975 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2976 for (const auto &F : Forwards) {
2977 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2978 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2979 }
2980 }
2982 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2983 // don't need this because the eligibility check rejects calls that require
2984 // shuffling arguments passed in memory.
2985 if (!IsSibcall && isTailCall) {
2986 // Force all the incoming stack arguments to be loaded from the stack
2987 // before any new outgoing arguments are stored to the stack, because the
2988 // outgoing stack slots may alias the incoming argument stack slots, and
2989 // the alias isn't otherwise explicit. This is slightly more conservative
2990 // than necessary, because it means that each store effectively depends
2991 // on every argument instead of just those arguments it would clobber.
2992 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2994 SmallVector<SDValue, 8> MemOpChains2;
2995 SDValue FIN;
2996 int FI = 0;
2997 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2998 CCValAssign &VA = ArgLocs[i];
2999 if (VA.isRegLoc())
3000 continue;
3001 assert(VA.isMemLoc());
3002 SDValue Arg = OutVals[i];
3003 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3004 // Skip inalloca arguments. They don't require any work.
3005 if (Flags.isInAlloca())
3006 continue;
3007 // Create frame index.
3008 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3009 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3010 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3011 FIN = DAG.getFrameIndex(FI, getPointerTy());
3013 if (Flags.isByVal()) {
3014 // Copy relative to framepointer.
3015 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3016 if (!StackPtr.getNode())
3017 StackPtr = DAG.getCopyFromReg(Chain, dl,
3018 RegInfo->getStackRegister(),
3019 getPointerTy());
3020 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3022 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3023 ArgChain,
3024 Flags, DAG, dl));
3025 } else {
3026 // Store relative to framepointer.
3027 MemOpChains2.push_back(
3028 DAG.getStore(ArgChain, dl, Arg, FIN,
3029 MachinePointerInfo::getFixedStack(FI),
3030 false, false, 0));
3031 }
3032 }
3034 if (!MemOpChains2.empty())
3035 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3037 // Store the return address to the appropriate stack slot.
3038 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3039 getPointerTy(), RegInfo->getSlotSize(),
3040 FPDiff, dl);
3041 }
3043 // Build a sequence of copy-to-reg nodes chained together with token chain
3044 // and flag operands which copy the outgoing args into registers.
3045 SDValue InFlag;
3046 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3047 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3048 RegsToPass[i].second, InFlag);
3049 InFlag = Chain.getValue(1);
3050 }
3052 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3053 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3054 // In the 64-bit large code model, we have to make all calls
3055 // through a register, since the call instruction's 32-bit
3056 // pc-relative offset may not be large enough to hold the whole
3057 // address.
3058 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3059 // If the callee is a GlobalAddress node (quite common, every direct call
3060 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3061 // it.
3063 // We should use extra load for direct calls to dllimported functions in
3064 // non-JIT mode.
3065 const GlobalValue *GV = G->getGlobal();
3066 if (!GV->hasDLLImportStorageClass()) {
3067 unsigned char OpFlags = 0;
3068 bool ExtraLoad = false;
3069 unsigned WrapperKind = ISD::DELETED_NODE;
3071 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3072 // external symbols most go through the PLT in PIC mode. If the symbol
3073 // has hidden or protected visibility, or if it is static or local, then
3074 // we don't need to use the PLT - we can directly call it.
3075 if (Subtarget->isTargetELF() &&
3076 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3077 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3078 OpFlags = X86II::MO_PLT;
3079 } else if (Subtarget->isPICStyleStubAny() &&
3080 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3081 (!Subtarget->getTargetTriple().isMacOSX() ||
3082 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3083 // PC-relative references to external symbols should go through $stub,
3084 // unless we're building with the leopard linker or later, which
3085 // automatically synthesizes these stubs.
3086 OpFlags = X86II::MO_DARWIN_STUB;
3087 } else if (Subtarget->isPICStyleRIPRel() &&
3088 isa<Function>(GV) &&
3089 cast<Function>(GV)->getAttributes().
3090 hasAttribute(AttributeSet::FunctionIndex,
3091 Attribute::NonLazyBind)) {
3092 // If the function is marked as non-lazy, generate an indirect call
3093 // which loads from the GOT directly. This avoids runtime overhead
3094 // at the cost of eager binding (and one extra byte of encoding).
3095 OpFlags = X86II::MO_GOTPCREL;
3096 WrapperKind = X86ISD::WrapperRIP;
3097 ExtraLoad = true;
3098 }
3100 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3101 G->getOffset(), OpFlags);
3103 // Add a wrapper if needed.
3104 if (WrapperKind != ISD::DELETED_NODE)
3105 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3106 // Add extra indirection if needed.
3107 if (ExtraLoad)
3108 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3109 MachinePointerInfo::getGOT(),
3110 false, false, false, 0);
3111 }
3112 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3113 unsigned char OpFlags = 0;
3115 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3116 // external symbols should go through the PLT.
3117 if (Subtarget->isTargetELF() &&
3118 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3119 OpFlags = X86II::MO_PLT;
3120 } else if (Subtarget->isPICStyleStubAny() &&
3121 (!Subtarget->getTargetTriple().isMacOSX() ||
3122 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3123 // PC-relative references to external symbols should go through $stub,
3124 // unless we're building with the leopard linker or later, which
3125 // automatically synthesizes these stubs.
3126 OpFlags = X86II::MO_DARWIN_STUB;
3127 }
3129 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3130 OpFlags);
3131 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3132 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3133 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3134 }
3136 // Returns a chain & a flag for retval copy to use.
3137 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3138 SmallVector<SDValue, 8> Ops;
3140 if (!IsSibcall && isTailCall) {
3141 Chain = DAG.getCALLSEQ_END(Chain,
3142 DAG.getIntPtrConstant(NumBytesToPop, true),
3143 DAG.getIntPtrConstant(0, true), InFlag, dl);
3144 InFlag = Chain.getValue(1);
3145 }
3147 Ops.push_back(Chain);
3148 Ops.push_back(Callee);
3150 if (isTailCall)
3151 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3153 // Add argument registers to the end of the list so that they are known live
3154 // into the call.
3155 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3156 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3157 RegsToPass[i].second.getValueType()));
3159 // Add a register mask operand representing the call-preserved registers.
3160 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3161 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3162 assert(Mask && "Missing call preserved mask for calling convention");
3163 Ops.push_back(DAG.getRegisterMask(Mask));
3165 if (InFlag.getNode())
3166 Ops.push_back(InFlag);
3168 if (isTailCall) {
3169 // We used to do:
3170 //// If this is the first return lowered for this function, add the regs
3171 //// to the liveout set for the function.
3172 // This isn't right, although it's probably harmless on x86; liveouts
3173 // should be computed from returns not tail calls. Consider a void
3174 // function making a tail call to a function returning int.
3175 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3176 }
3178 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3179 InFlag = Chain.getValue(1);
3181 // Create the CALLSEQ_END node.
3182 unsigned NumBytesForCalleeToPop;
3183 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3184 DAG.getTarget().Options.GuaranteedTailCallOpt))
3185 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3186 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3187 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3188 SR == StackStructReturn)
3189 // If this is a call to a struct-return function, the callee
3190 // pops the hidden struct pointer, so we have to push it back.
3191 // This is common for Darwin/X86, Linux & Mingw32 targets.
3192 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3193 NumBytesForCalleeToPop = 4;
3194 else
3195 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3197 // Returns a flag for retval copy to use.
3198 if (!IsSibcall) {
3199 Chain = DAG.getCALLSEQ_END(Chain,
3200 DAG.getIntPtrConstant(NumBytesToPop, true),
3201 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3202 true),
3203 InFlag, dl);
3204 InFlag = Chain.getValue(1);
3205 }
3207 // Handle result values, copying them out of physregs into vregs that we
3208 // return.
3209 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3210 Ins, dl, DAG, InVals);
3211 }
3213 //===----------------------------------------------------------------------===//
3214 // Fast Calling Convention (tail call) implementation
3215 //===----------------------------------------------------------------------===//
3217 // Like std call, callee cleans arguments, convention except that ECX is
3218 // reserved for storing the tail called function address. Only 2 registers are
3219 // free for argument passing (inreg). Tail call optimization is performed
3220 // provided:
3221 // * tailcallopt is enabled
3222 // * caller/callee are fastcc
3223 // On X86_64 architecture with GOT-style position independent code only local
3224 // (within module) calls are supported at the moment.
3225 // To keep the stack aligned according to platform abi the function
3226 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3227 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3228 // If a tail called function callee has more arguments than the caller the
3229 // caller needs to make sure that there is room to move the RETADDR to. This is
3230 // achieved by reserving an area the size of the argument delta right after the
3231 // original RETADDR, but before the saved framepointer or the spilled registers
3232 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3233 // stack layout:
3234 // arg1
3235 // arg2
3236 // RETADDR
3237 // [ new RETADDR
3238 // move area ]
3239 // (possible EBP)
3240 // ESI
3241 // EDI
3242 // local1 ..
3244 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3245 /// for a 16 byte align requirement.
3246 unsigned
3247 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3248 SelectionDAG& DAG) const {
3249 MachineFunction &MF = DAG.getMachineFunction();
3250 const TargetMachine &TM = MF.getTarget();
3251 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3252 TM.getSubtargetImpl()->getRegisterInfo());
3253 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3254 unsigned StackAlignment = TFI.getStackAlignment();
3255 uint64_t AlignMask = StackAlignment - 1;
3256 int64_t Offset = StackSize;
3257 unsigned SlotSize = RegInfo->getSlotSize();
3258 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3259 // Number smaller than 12 so just add the difference.
3260 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3261 } else {
3262 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3263 Offset = ((~AlignMask) & Offset) + StackAlignment +
3264 (StackAlignment-SlotSize);
3265 }
3266 return Offset;
3267 }
3269 /// MatchingStackOffset - Return true if the given stack call argument is
3270 /// already available in the same position (relatively) of the caller's
3271 /// incoming argument stack.
3272 static
3273 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3274 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3275 const X86InstrInfo *TII) {
3276 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3277 int FI = INT_MAX;
3278 if (Arg.getOpcode() == ISD::CopyFromReg) {
3279 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3280 if (!TargetRegisterInfo::isVirtualRegister(VR))
3281 return false;
3282 MachineInstr *Def = MRI->getVRegDef(VR);
3283 if (!Def)
3284 return false;
3285 if (!Flags.isByVal()) {
3286 if (!TII->isLoadFromStackSlot(Def, FI))
3287 return false;
3288 } else {
3289 unsigned Opcode = Def->getOpcode();
3290 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3291 Def->getOperand(1).isFI()) {
3292 FI = Def->getOperand(1).getIndex();
3293 Bytes = Flags.getByValSize();
3294 } else
3295 return false;
3296 }
3297 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3298 if (Flags.isByVal())
3299 // ByVal argument is passed in as a pointer but it's now being
3300 // dereferenced. e.g.
3301 // define @foo(%struct.X* %A) {
3302 // tail call @bar(%struct.X* byval %A)
3303 // }
3304 return false;
3305 SDValue Ptr = Ld->getBasePtr();
3306 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3307 if (!FINode)
3308 return false;
3309 FI = FINode->getIndex();
3310 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3311 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3312 FI = FINode->getIndex();
3313 Bytes = Flags.getByValSize();
3314 } else
3315 return false;
3317 assert(FI != INT_MAX);
3318 if (!MFI->isFixedObjectIndex(FI))
3319 return false;
3320 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3321 }
3323 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3324 /// for tail call optimization. Targets which want to do tail call
3325 /// optimization should implement this function.
3326 bool
3327 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3328 CallingConv::ID CalleeCC,
3329 bool isVarArg,
3330 bool isCalleeStructRet,
3331 bool isCallerStructRet,
3332 Type *RetTy,
3333 const SmallVectorImpl<ISD::OutputArg> &Outs,
3334 const SmallVectorImpl<SDValue> &OutVals,
3335 const SmallVectorImpl<ISD::InputArg> &Ins,
3336 SelectionDAG &DAG) const {
3337 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3338 return false;
3340 // If -tailcallopt is specified, make fastcc functions tail-callable.
3341 const MachineFunction &MF = DAG.getMachineFunction();
3342 const Function *CallerF = MF.getFunction();
3344 // If the function return type is x86_fp80 and the callee return type is not,
3345 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3346 // perform a tailcall optimization here.
3347 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3348 return false;
3350 CallingConv::ID CallerCC = CallerF->getCallingConv();
3351 bool CCMatch = CallerCC == CalleeCC;
3352 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3353 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3355 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3356 if (IsTailCallConvention(CalleeCC) && CCMatch)
3357 return true;
3358 return false;
3359 }
3361 // Look for obvious safe cases to perform tail call optimization that do not
3362 // require ABI changes. This is what gcc calls sibcall.
3364 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3365 // emit a special epilogue.
3366 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3367 DAG.getSubtarget().getRegisterInfo());
3368 if (RegInfo->needsStackRealignment(MF))
3369 return false;
3371 // Also avoid sibcall optimization if either caller or callee uses struct
3372 // return semantics.
3373 if (isCalleeStructRet || isCallerStructRet)
3374 return false;
3376 // An stdcall/thiscall caller is expected to clean up its arguments; the
3377 // callee isn't going to do that.
3378 // FIXME: this is more restrictive than needed. We could produce a tailcall
3379 // when the stack adjustment matches. For example, with a thiscall that takes
3380 // only one argument.
3381 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3382 CallerCC == CallingConv::X86_ThisCall))
3383 return false;
3385 // Do not sibcall optimize vararg calls unless all arguments are passed via
3386 // registers.
3387 if (isVarArg && !Outs.empty()) {
3389 // Optimizing for varargs on Win64 is unlikely to be safe without
3390 // additional testing.
3391 if (IsCalleeWin64 || IsCallerWin64)
3392 return false;
3394 SmallVector<CCValAssign, 16> ArgLocs;
3395 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3396 *DAG.getContext());
3398 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3399 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3400 if (!ArgLocs[i].isRegLoc())
3401 return false;
3402 }
3404 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3405 // stack. Therefore, if it's not used by the call it is not safe to optimize
3406 // this into a sibcall.
3407 bool Unused = false;
3408 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3409 if (!Ins[i].Used) {
3410 Unused = true;
3411 break;
3412 }
3413 }
3414 if (Unused) {
3415 SmallVector<CCValAssign, 16> RVLocs;
3416 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3417 *DAG.getContext());
3418 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3419 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3420 CCValAssign &VA = RVLocs[i];
3421 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3422 return false;
3423 }
3424 }
3426 // If the calling conventions do not match, then we'd better make sure the
3427 // results are returned in the same way as what the caller expects.
3428 if (!CCMatch) {
3429 SmallVector<CCValAssign, 16> RVLocs1;
3430 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3431 *DAG.getContext());
3432 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3434 SmallVector<CCValAssign, 16> RVLocs2;
3435 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3436 *DAG.getContext());
3437 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3439 if (RVLocs1.size() != RVLocs2.size())
3440 return false;
3441 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3442 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3443 return false;
3444 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3445 return false;
3446 if (RVLocs1[i].isRegLoc()) {
3447 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3448 return false;
3449 } else {
3450 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3451 return false;
3452 }
3453 }
3454 }
3456 // If the callee takes no arguments then go on to check the results of the
3457 // call.
3458 if (!Outs.empty()) {
3459 // Check if stack adjustment is needed. For now, do not do this if any
3460 // argument is passed on the stack.
3461 SmallVector<CCValAssign, 16> ArgLocs;
3462 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3463 *DAG.getContext());
3465 // Allocate shadow area for Win64
3466 if (IsCalleeWin64)
3467 CCInfo.AllocateStack(32, 8);
3469 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3470 if (CCInfo.getNextStackOffset()) {
3471 MachineFunction &MF = DAG.getMachineFunction();
3472 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3473 return false;
3475 // Check if the arguments are already laid out in the right way as
3476 // the caller's fixed stack objects.
3477 MachineFrameInfo *MFI = MF.getFrameInfo();
3478 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3479 const X86InstrInfo *TII =
3480 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3481 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3482 CCValAssign &VA = ArgLocs[i];
3483 SDValue Arg = OutVals[i];
3484 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3485 if (VA.getLocInfo() == CCValAssign::Indirect)
3486 return false;
3487 if (!VA.isRegLoc()) {
3488 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3489 MFI, MRI, TII))
3490 return false;
3491 }
3492 }
3493 }
3495 // If the tailcall address may be in a register, then make sure it's
3496 // possible to register allocate for it. In 32-bit, the call address can
3497 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3498 // callee-saved registers are restored. These happen to be the same
3499 // registers used to pass 'inreg' arguments so watch out for those.
3500 if (!Subtarget->is64Bit() &&
3501 ((!isa<GlobalAddressSDNode>(Callee) &&
3502 !isa<ExternalSymbolSDNode>(Callee)) ||
3503 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3504 unsigned NumInRegs = 0;
3505 // In PIC we need an extra register to formulate the address computation
3506 // for the callee.
3507 unsigned MaxInRegs =
3508 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3510 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3511 CCValAssign &VA = ArgLocs[i];
3512 if (!VA.isRegLoc())
3513 continue;
3514 unsigned Reg = VA.getLocReg();
3515 switch (Reg) {
3516 default: break;
3517 case X86::EAX: case X86::EDX: case X86::ECX:
3518 if (++NumInRegs == MaxInRegs)
3519 return false;
3520 break;
3521 }
3522 }
3523 }
3524 }
3526 return true;
3527 }
3529 FastISel *
3530 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3531 const TargetLibraryInfo *libInfo) const {
3532 return X86::createFastISel(funcInfo, libInfo);
3533 }
3535 //===----------------------------------------------------------------------===//
3536 // Other Lowering Hooks
3537 //===----------------------------------------------------------------------===//
3539 static bool MayFoldLoad(SDValue Op) {
3540 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3541 }
3543 static bool MayFoldIntoStore(SDValue Op) {
3544 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3545 }
3547 static bool isTargetShuffle(unsigned Opcode) {
3548 switch(Opcode) {
3549 default: return false;
3550 case X86ISD::BLENDI:
3551 case X86ISD::PSHUFB:
3552 case X86ISD::PSHUFD:
3553 case X86ISD::PSHUFHW:
3554 case X86ISD::PSHUFLW:
3555 case X86ISD::SHUFP:
3556 case X86ISD::PALIGNR:
3557 case X86ISD::MOVLHPS:
3558 case X86ISD::MOVLHPD:
3559 case X86ISD::MOVHLPS:
3560 case X86ISD::MOVLPS:
3561 case X86ISD::MOVLPD:
3562 case X86ISD::MOVSHDUP:
3563 case X86ISD::MOVSLDUP:
3564 case X86ISD::MOVDDUP:
3565 case X86ISD::MOVSS:
3566 case X86ISD::MOVSD:
3567 case X86ISD::UNPCKL:
3568 case X86ISD::UNPCKH:
3569 case X86ISD::VPERMILPI:
3570 case X86ISD::VPERM2X128:
3571 case X86ISD::VPERMI:
3572 return true;
3573 }
3574 }
3576 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3577 SDValue V1, SelectionDAG &DAG) {
3578 switch(Opc) {
3579 default: llvm_unreachable("Unknown x86 shuffle node");
3580 case X86ISD::MOVSHDUP:
3581 case X86ISD::MOVSLDUP:
3582 case X86ISD::MOVDDUP:
3583 return DAG.getNode(Opc, dl, VT, V1);
3584 }
3585 }
3587 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3588 SDValue V1, unsigned TargetMask,
3589 SelectionDAG &DAG) {
3590 switch(Opc) {
3591 default: llvm_unreachable("Unknown x86 shuffle node");
3592 case X86ISD::PSHUFD:
3593 case X86ISD::PSHUFHW:
3594 case X86ISD::PSHUFLW:
3595 case X86ISD::VPERMILPI:
3596 case X86ISD::VPERMI:
3597 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3598 }
3599 }
3601 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3602 SDValue V1, SDValue V2, unsigned TargetMask,
3603 SelectionDAG &DAG) {
3604 switch(Opc) {
3605 default: llvm_unreachable("Unknown x86 shuffle node");
3606 case X86ISD::PALIGNR:
3607 case X86ISD::VALIGN:
3608 case X86ISD::SHUFP:
3609 case X86ISD::VPERM2X128:
3610 return DAG.getNode(Opc, dl, VT, V1, V2,
3611 DAG.getConstant(TargetMask, MVT::i8));
3612 }
3613 }
3615 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3616 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3617 switch(Opc) {
3618 default: llvm_unreachable("Unknown x86 shuffle node");
3619 case X86ISD::MOVLHPS:
3620 case X86ISD::MOVLHPD:
3621 case X86ISD::MOVHLPS:
3622 case X86ISD::MOVLPS:
3623 case X86ISD::MOVLPD:
3624 case X86ISD::MOVSS:
3625 case X86ISD::MOVSD:
3626 case X86ISD::UNPCKL:
3627 case X86ISD::UNPCKH:
3628 return DAG.getNode(Opc, dl, VT, V1, V2);
3629 }
3630 }
3632 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3633 MachineFunction &MF = DAG.getMachineFunction();
3634 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3635 DAG.getSubtarget().getRegisterInfo());
3636 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3637 int ReturnAddrIndex = FuncInfo->getRAIndex();
3639 if (ReturnAddrIndex == 0) {
3640 // Set up a frame object for the return address.
3641 unsigned SlotSize = RegInfo->getSlotSize();
3642 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3643 -(int64_t)SlotSize,
3644 false);
3645 FuncInfo->setRAIndex(ReturnAddrIndex);
3646 }
3648 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3649 }
3651 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3652 bool hasSymbolicDisplacement) {
3653 // Offset should fit into 32 bit immediate field.
3654 if (!isInt<32>(Offset))
3655 return false;
3657 // If we don't have a symbolic displacement - we don't have any extra
3658 // restrictions.
3659 if (!hasSymbolicDisplacement)
3660 return true;
3662 // FIXME: Some tweaks might be needed for medium code model.
3663 if (M != CodeModel::Small && M != CodeModel::Kernel)
3664 return false;
3666 // For small code model we assume that latest object is 16MB before end of 31
3667 // bits boundary. We may also accept pretty large negative constants knowing
3668 // that all objects are in the positive half of address space.
3669 if (M == CodeModel::Small && Offset < 16*1024*1024)
3670 return true;
3672 // For kernel code model we know that all object resist in the negative half
3673 // of 32bits address space. We may not accept negative offsets, since they may
3674 // be just off and we may accept pretty large positive ones.
3675 if (M == CodeModel::Kernel && Offset >= 0)
3676 return true;
3678 return false;
3679 }
3681 /// isCalleePop - Determines whether the callee is required to pop its
3682 /// own arguments. Callee pop is necessary to support tail calls.
3683 bool X86::isCalleePop(CallingConv::ID CallingConv,
3684 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3685 switch (CallingConv) {
3686 default:
3687 return false;
3688 case CallingConv::X86_StdCall:
3689 case CallingConv::X86_FastCall:
3690 case CallingConv::X86_ThisCall:
3691 return !is64Bit;
3692 case CallingConv::Fast:
3693 case CallingConv::GHC:
3694 case CallingConv::HiPE:
3695 if (IsVarArg)
3696 return false;
3697 return TailCallOpt;
3698 }
3699 }
3701 /// \brief Return true if the condition is an unsigned comparison operation.
3702 static bool isX86CCUnsigned(unsigned X86CC) {
3703 switch (X86CC) {
3704 default: llvm_unreachable("Invalid integer condition!");
3705 case X86::COND_E: return true;
3706 case X86::COND_G: return false;
3707 case X86::COND_GE: return false;
3708 case X86::COND_L: return false;
3709 case X86::COND_LE: return false;
3710 case X86::COND_NE: return true;
3711 case X86::COND_B: return true;
3712 case X86::COND_A: return true;
3713 case X86::COND_BE: return true;
3714 case X86::COND_AE: return true;
3715 }
3716 llvm_unreachable("covered switch fell through?!");
3717 }
3719 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3720 /// specific condition code, returning the condition code and the LHS/RHS of the
3721 /// comparison to make.
3722 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3723 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3724 if (!isFP) {
3725 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3726 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3727 // X > -1 -> X == 0, jump !sign.
3728 RHS = DAG.getConstant(0, RHS.getValueType());
3729 return X86::COND_NS;
3730 }
3731 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3732 // X < 0 -> X == 0, jump on sign.
3733 return X86::COND_S;
3734 }
3735 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3736 // X < 1 -> X <= 0
3737 RHS = DAG.getConstant(0, RHS.getValueType());
3738 return X86::COND_LE;
3739 }
3740 }
3742 switch (SetCCOpcode) {
3743 default: llvm_unreachable("Invalid integer condition!");
3744 case ISD::SETEQ: return X86::COND_E;
3745 case ISD::SETGT: return X86::COND_G;
3746 case ISD::SETGE: return X86::COND_GE;
3747 case ISD::SETLT: return X86::COND_L;
3748 case ISD::SETLE: return X86::COND_LE;
3749 case ISD::SETNE: return X86::COND_NE;
3750 case ISD::SETULT: return X86::COND_B;
3751 case ISD::SETUGT: return X86::COND_A;
3752 case ISD::SETULE: return X86::COND_BE;
3753 case ISD::SETUGE: return X86::COND_AE;
3754 }
3755 }
3757 // First determine if it is required or is profitable to flip the operands.
3759 // If LHS is a foldable load, but RHS is not, flip the condition.
3760 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3761 !ISD::isNON_EXTLoad(RHS.getNode())) {
3762 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3763 std::swap(LHS, RHS);
3764 }
3766 switch (SetCCOpcode) {
3767 default: break;
3768 case ISD::SETOLT:
3769 case ISD::SETOLE:
3770 case ISD::SETUGT:
3771 case ISD::SETUGE:
3772 std::swap(LHS, RHS);
3773 break;
3774 }
3776 // On a floating point condition, the flags are set as follows:
3777 // ZF PF CF op
3778 // 0 | 0 | 0 | X > Y
3779 // 0 | 0 | 1 | X < Y
3780 // 1 | 0 | 0 | X == Y
3781 // 1 | 1 | 1 | unordered
3782 switch (SetCCOpcode) {
3783 default: llvm_unreachable("Condcode should be pre-legalized away");
3784 case ISD::SETUEQ:
3785 case ISD::SETEQ: return X86::COND_E;
3786 case ISD::SETOLT: // flipped
3787 case ISD::SETOGT:
3788 case ISD::SETGT: return X86::COND_A;
3789 case ISD::SETOLE: // flipped
3790 case ISD::SETOGE:
3791 case ISD::SETGE: return X86::COND_AE;
3792 case ISD::SETUGT: // flipped
3793 case ISD::SETULT:
3794 case ISD::SETLT: return X86::COND_B;
3795 case ISD::SETUGE: // flipped
3796 case ISD::SETULE:
3797 case ISD::SETLE: return X86::COND_BE;
3798 case ISD::SETONE:
3799 case ISD::SETNE: return X86::COND_NE;
3800 case ISD::SETUO: return X86::COND_P;
3801 case ISD::SETO: return X86::COND_NP;
3802 case ISD::SETOEQ:
3803 case ISD::SETUNE: return X86::COND_INVALID;
3804 }
3805 }
3807 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3808 /// code. Current x86 isa includes the following FP cmov instructions:
3809 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3810 static bool hasFPCMov(unsigned X86CC) {
3811 switch (X86CC) {
3812 default:
3813 return false;
3814 case X86::COND_B:
3815 case X86::COND_BE:
3816 case X86::COND_E:
3817 case X86::COND_P:
3818 case X86::COND_A:
3819 case X86::COND_AE:
3820 case X86::COND_NE:
3821 case X86::COND_NP:
3822 return true;
3823 }
3824 }
3826 /// isFPImmLegal - Returns true if the target can instruction select the
3827 /// specified FP immediate natively. If false, the legalizer will
3828 /// materialize the FP immediate as a load from a constant pool.
3829 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3830 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3831 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3832 return true;
3833 }
3834 return false;
3835 }
3837 /// \brief Returns true if it is beneficial to convert a load of a constant
3838 /// to just the constant itself.
3839 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3840 Type *Ty) const {
3841 assert(Ty->isIntegerTy());
3843 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3844 if (BitSize == 0 || BitSize > 64)
3845 return false;
3846 return true;
3847 }
3849 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3850 /// the specified range (L, H].
3851 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3852 return (Val < 0) || (Val >= Low && Val < Hi);
3853 }
3855 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3856 /// specified value.
3857 static bool isUndefOrEqual(int Val, int CmpVal) {
3858 return (Val < 0 || Val == CmpVal);
3859 }
3861 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3862 /// from position Pos and ending in Pos+Size, falls within the specified
3863 /// sequential range (L, L+Pos]. or is undef.
3864 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3865 unsigned Pos, unsigned Size, int Low) {
3866 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3867 if (!isUndefOrEqual(Mask[i], Low))
3868 return false;
3869 return true;
3870 }
3872 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3873 /// is suitable for input to PSHUFD. That is, it doesn't reference the other
3874 /// operand - by default will match for first operand.
3875 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT,
3876 bool TestSecondOperand = false) {
3877 if (VT != MVT::v4f32 && VT != MVT::v4i32 &&
3878 VT != MVT::v2f64 && VT != MVT::v2i64)
3879 return false;
3881 unsigned NumElems = VT.getVectorNumElements();
3882 unsigned Lo = TestSecondOperand ? NumElems : 0;
3883 unsigned Hi = Lo + NumElems;
3885 for (unsigned i = 0; i < NumElems; ++i)
3886 if (!isUndefOrInRange(Mask[i], (int)Lo, (int)Hi))
3887 return false;
3889 return true;
3890 }
3892 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3893 /// is suitable for input to PSHUFHW.
3894 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3895 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3896 return false;
3898 // Lower quadword copied in order or undef.
3899 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3900 return false;
3902 // Upper quadword shuffled.
3903 for (unsigned i = 4; i != 8; ++i)
3904 if (!isUndefOrInRange(Mask[i], 4, 8))
3905 return false;
3907 if (VT == MVT::v16i16) {
3908 // Lower quadword copied in order or undef.
3909 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3910 return false;
3912 // Upper quadword shuffled.
3913 for (unsigned i = 12; i != 16; ++i)
3914 if (!isUndefOrInRange(Mask[i], 12, 16))
3915 return false;
3916 }
3918 return true;
3919 }
3921 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3922 /// is suitable for input to PSHUFLW.
3923 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3924 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3925 return false;
3927 // Upper quadword copied in order.
3928 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3929 return false;
3931 // Lower quadword shuffled.
3932 for (unsigned i = 0; i != 4; ++i)
3933 if (!isUndefOrInRange(Mask[i], 0, 4))
3934 return false;
3936 if (VT == MVT::v16i16) {
3937 // Upper quadword copied in order.
3938 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3939 return false;
3941 // Lower quadword shuffled.
3942 for (unsigned i = 8; i != 12; ++i)
3943 if (!isUndefOrInRange(Mask[i], 8, 12))
3944 return false;
3945 }
3947 return true;
3948 }
3950 /// \brief Return true if the mask specifies a shuffle of elements that is
3951 /// suitable for input to intralane (palignr) or interlane (valign) vector
3952 /// right-shift.
3953 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3954 unsigned NumElts = VT.getVectorNumElements();
3955 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3956 unsigned NumLaneElts = NumElts/NumLanes;
3958 // Do not handle 64-bit element shuffles with palignr.
3959 if (NumLaneElts == 2)
3960 return false;
3962 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3963 unsigned i;
3964 for (i = 0; i != NumLaneElts; ++i) {
3965 if (Mask[i+l] >= 0)
3966 break;
3967 }
3969 // Lane is all undef, go to next lane
3970 if (i == NumLaneElts)
3971 continue;
3973 int Start = Mask[i+l];
3975 // Make sure its in this lane in one of the sources
3976 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3977 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3978 return false;
3980 // If not lane 0, then we must match lane 0
3981 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3982 return false;
3984 // Correct second source to be contiguous with first source
3985 if (Start >= (int)NumElts)
3986 Start -= NumElts - NumLaneElts;
3988 // Make sure we're shifting in the right direction.
3989 if (Start <= (int)(i+l))
3990 return false;
3992 Start -= i;
3994 // Check the rest of the elements to see if they are consecutive.
3995 for (++i; i != NumLaneElts; ++i) {
3996 int Idx = Mask[i+l];
3998 // Make sure its in this lane
3999 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
4000 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
4001 return false;
4003 // If not lane 0, then we must match lane 0
4004 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
4005 return false;
4007 if (Idx >= (int)NumElts)
4008 Idx -= NumElts - NumLaneElts;
4010 if (!isUndefOrEqual(Idx, Start+i))
4011 return false;
4013 }
4014 }
4016 return true;
4017 }
4019 /// \brief Return true if the node specifies a shuffle of elements that is
4020 /// suitable for input to PALIGNR.
4021 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4022 const X86Subtarget *Subtarget) {
4023 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4024 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4025 VT.is512BitVector())
4026 // FIXME: Add AVX512BW.
4027 return false;
4029 return isAlignrMask(Mask, VT, false);
4030 }
4032 /// \brief Return true if the node specifies a shuffle of elements that is
4033 /// suitable for input to VALIGN.
4034 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4035 const X86Subtarget *Subtarget) {
4036 // FIXME: Add AVX512VL.
4037 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4038 return false;
4039 return isAlignrMask(Mask, VT, true);
4040 }
4042 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4043 /// the two vector operands have swapped position.
4044 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4045 unsigned NumElems) {
4046 for (unsigned i = 0; i != NumElems; ++i) {
4047 int idx = Mask[i];
4048 if (idx < 0)
4049 continue;
4050 else if (idx < (int)NumElems)
4051 Mask[i] = idx + NumElems;
4052 else
4053 Mask[i] = idx - NumElems;
4054 }
4055 }
4057 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4058 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4059 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4060 /// reverse of what x86 shuffles want.
4061 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4063 unsigned NumElems = VT.getVectorNumElements();
4064 unsigned NumLanes = VT.getSizeInBits()/128;
4065 unsigned NumLaneElems = NumElems/NumLanes;
4067 if (NumLaneElems != 2 && NumLaneElems != 4)
4068 return false;
4070 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4071 bool symetricMaskRequired =
4072 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4074 // VSHUFPSY divides the resulting vector into 4 chunks.
4075 // The sources are also splitted into 4 chunks, and each destination
4076 // chunk must come from a different source chunk.
4077 //
4078 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4079 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4080 //
4081 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4082 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4083 //
4084 // VSHUFPDY divides the resulting vector into 4 chunks.
4085 // The sources are also splitted into 4 chunks, and each destination
4086 // chunk must come from a different source chunk.
4087 //
4088 // SRC1 => X3 X2 X1 X0
4089 // SRC2 => Y3 Y2 Y1 Y0
4090 //
4091 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4092 //
4093 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4094 unsigned HalfLaneElems = NumLaneElems/2;
4095 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4096 for (unsigned i = 0; i != NumLaneElems; ++i) {
4097 int Idx = Mask[i+l];
4098 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4099 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4100 return false;
4101 // For VSHUFPSY, the mask of the second half must be the same as the
4102 // first but with the appropriate offsets. This works in the same way as
4103 // VPERMILPS works with masks.
4104 if (!symetricMaskRequired || Idx < 0)
4105 continue;
4106 if (MaskVal[i] < 0) {
4107 MaskVal[i] = Idx - l;
4108 continue;
4109 }
4110 if ((signed)(Idx - l) != MaskVal[i])
4111 return false;
4112 }
4113 }
4115 return true;
4116 }
4118 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4119 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4120 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4121 if (!VT.is128BitVector())
4122 return false;
4124 unsigned NumElems = VT.getVectorNumElements();
4126 if (NumElems != 4)
4127 return false;
4129 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4130 return isUndefOrEqual(Mask[0], 6) &&
4131 isUndefOrEqual(Mask[1], 7) &&
4132 isUndefOrEqual(Mask[2], 2) &&
4133 isUndefOrEqual(Mask[3], 3);
4134 }
4136 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4137 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4138 /// <2, 3, 2, 3>
4139 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4140 if (!VT.is128BitVector())
4141 return false;
4143 unsigned NumElems = VT.getVectorNumElements();
4145 if (NumElems != 4)
4146 return false;
4148 return isUndefOrEqual(Mask[0], 2) &&
4149 isUndefOrEqual(Mask[1], 3) &&
4150 isUndefOrEqual(Mask[2], 2) &&
4151 isUndefOrEqual(Mask[3], 3);
4152 }
4154 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4155 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4156 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4157 if (!VT.is128BitVector())
4158 return false;
4160 unsigned NumElems = VT.getVectorNumElements();
4162 if (NumElems != 2 && NumElems != 4)
4163 return false;
4165 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4166 if (!isUndefOrEqual(Mask[i], i + NumElems))
4167 return false;
4169 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4170 if (!isUndefOrEqual(Mask[i], i))
4171 return false;
4173 return true;
4174 }
4176 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4177 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4178 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4179 if (!VT.is128BitVector())
4180 return false;
4182 unsigned NumElems = VT.getVectorNumElements();
4184 if (NumElems != 2 && NumElems != 4)
4185 return false;
4187 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4188 if (!isUndefOrEqual(Mask[i], i))
4189 return false;
4191 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4192 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4193 return false;
4195 return true;
4196 }
4198 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4199 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4200 /// i. e: If all but one element come from the same vector.
4201 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4202 // TODO: Deal with AVX's VINSERTPS
4203 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4204 return false;
4206 unsigned CorrectPosV1 = 0;
4207 unsigned CorrectPosV2 = 0;
4208 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4209 if (Mask[i] == -1) {
4210 ++CorrectPosV1;
4211 ++CorrectPosV2;
4212 continue;
4213 }
4215 if (Mask[i] == i)
4216 ++CorrectPosV1;
4217 else if (Mask[i] == i + 4)
4218 ++CorrectPosV2;
4219 }
4221 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4222 // We have 3 elements (undefs count as elements from any vector) from one
4223 // vector, and one from another.
4224 return true;
4226 return false;
4227 }
4229 //
4230 // Some special combinations that can be optimized.
4231 //
4232 static
4233 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4234 SelectionDAG &DAG) {
4235 MVT VT = SVOp->getSimpleValueType(0);
4236 SDLoc dl(SVOp);
4238 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4239 return SDValue();
4241 ArrayRef<int> Mask = SVOp->getMask();
4243 // These are the special masks that may be optimized.
4244 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4245 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4246 bool MatchEvenMask = true;
4247 bool MatchOddMask = true;
4248 for (int i=0; i<8; ++i) {
4249 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4250 MatchEvenMask = false;
4251 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4252 MatchOddMask = false;
4253 }
4255 if (!MatchEvenMask && !MatchOddMask)
4256 return SDValue();
4258 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4260 SDValue Op0 = SVOp->getOperand(0);
4261 SDValue Op1 = SVOp->getOperand(1);
4263 if (MatchEvenMask) {
4264 // Shift the second operand right to 32 bits.
4265 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4266 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4267 } else {
4268 // Shift the first operand left to 32 bits.
4269 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4270 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4271 }
4272 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4273 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4274 }
4276 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4277 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4278 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4279 bool HasInt256, bool V2IsSplat = false) {
4281 assert(VT.getSizeInBits() >= 128 &&
4282 "Unsupported vector type for unpckl");
4284 unsigned NumElts = VT.getVectorNumElements();
4285 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4286 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4287 return false;
4289 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4290 "Unsupported vector type for unpckh");
4292 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4293 unsigned NumLanes = VT.getSizeInBits()/128;
4294 unsigned NumLaneElts = NumElts/NumLanes;
4296 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4297 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4298 int BitI = Mask[l+i];
4299 int BitI1 = Mask[l+i+1];
4300 if (!isUndefOrEqual(BitI, j))
4301 return false;
4302 if (V2IsSplat) {
4303 if (!isUndefOrEqual(BitI1, NumElts))
4304 return false;
4305 } else {
4306 if (!isUndefOrEqual(BitI1, j + NumElts))
4307 return false;
4308 }
4309 }
4310 }
4312 return true;
4313 }
4315 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4316 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4317 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4318 bool HasInt256, bool V2IsSplat = false) {
4319 assert(VT.getSizeInBits() >= 128 &&
4320 "Unsupported vector type for unpckh");
4322 unsigned NumElts = VT.getVectorNumElements();
4323 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4324 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4325 return false;
4327 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4328 "Unsupported vector type for unpckh");
4330 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4331 unsigned NumLanes = VT.getSizeInBits()/128;
4332 unsigned NumLaneElts = NumElts/NumLanes;
4334 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4335 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4336 int BitI = Mask[l+i];
4337 int BitI1 = Mask[l+i+1];
4338 if (!isUndefOrEqual(BitI, j))
4339 return false;
4340 if (V2IsSplat) {
4341 if (isUndefOrEqual(BitI1, NumElts))
4342 return false;
4343 } else {
4344 if (!isUndefOrEqual(BitI1, j+NumElts))
4345 return false;
4346 }
4347 }
4348 }
4349 return true;
4350 }
4352 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4353 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4354 /// <0, 0, 1, 1>
4355 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4356 unsigned NumElts = VT.getVectorNumElements();
4357 bool Is256BitVec = VT.is256BitVector();
4359 if (VT.is512BitVector())
4360 return false;
4361 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4362 "Unsupported vector type for unpckh");
4364 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4365 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4366 return false;
4368 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4369 // FIXME: Need a better way to get rid of this, there's no latency difference
4370 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4371 // the former later. We should also remove the "_undef" special mask.
4372 if (NumElts == 4 && Is256BitVec)
4373 return false;
4375 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4376 // independently on 128-bit lanes.
4377 unsigned NumLanes = VT.getSizeInBits()/128;
4378 unsigned NumLaneElts = NumElts/NumLanes;
4380 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4381 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4382 int BitI = Mask[l+i];
4383 int BitI1 = Mask[l+i+1];
4385 if (!isUndefOrEqual(BitI, j))
4386 return false;
4387 if (!isUndefOrEqual(BitI1, j))
4388 return false;
4389 }
4390 }
4392 return true;
4393 }
4395 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4396 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4397 /// <2, 2, 3, 3>
4398 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4399 unsigned NumElts = VT.getVectorNumElements();
4401 if (VT.is512BitVector())
4402 return false;
4404 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4405 "Unsupported vector type for unpckh");
4407 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4408 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4409 return false;
4411 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4412 // independently on 128-bit lanes.
4413 unsigned NumLanes = VT.getSizeInBits()/128;
4414 unsigned NumLaneElts = NumElts/NumLanes;
4416 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4417 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4418 int BitI = Mask[l+i];
4419 int BitI1 = Mask[l+i+1];
4420 if (!isUndefOrEqual(BitI, j))
4421 return false;
4422 if (!isUndefOrEqual(BitI1, j))
4423 return false;
4424 }
4425 }
4426 return true;
4427 }
4429 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4430 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4431 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4432 if (!VT.is512BitVector())
4433 return false;
4435 unsigned NumElts = VT.getVectorNumElements();
4436 unsigned HalfSize = NumElts/2;
4437 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4438 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4439 *Imm = 1;
4440 return true;
4441 }
4442 }
4443 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4444 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4445 *Imm = 0;
4446 return true;
4447 }
4448 }
4449 return false;
4450 }
4452 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4453 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4454 /// MOVSD, and MOVD, i.e. setting the lowest element.
4455 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4456 if (VT.getVectorElementType().getSizeInBits() < 32)
4457 return false;
4458 if (!VT.is128BitVector())
4459 return false;
4461 unsigned NumElts = VT.getVectorNumElements();
4463 if (!isUndefOrEqual(Mask[0], NumElts))
4464 return false;
4466 for (unsigned i = 1; i != NumElts; ++i)
4467 if (!isUndefOrEqual(Mask[i], i))
4468 return false;
4470 return true;
4471 }
4473 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4474 /// as permutations between 128-bit chunks or halves. As an example: this
4475 /// shuffle bellow:
4476 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4477 /// The first half comes from the second half of V1 and the second half from the
4478 /// the second half of V2.
4479 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4480 if (!HasFp256 || !VT.is256BitVector())
4481 return false;
4483 // The shuffle result is divided into half A and half B. In total the two
4484 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4485 // B must come from C, D, E or F.
4486 unsigned HalfSize = VT.getVectorNumElements()/2;
4487 bool MatchA = false, MatchB = false;
4489 // Check if A comes from one of C, D, E, F.
4490 for (unsigned Half = 0; Half != 4; ++Half) {
4491 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4492 MatchA = true;
4493 break;
4494 }
4495 }
4497 // Check if B comes from one of C, D, E, F.
4498 for (unsigned Half = 0; Half != 4; ++Half) {
4499 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4500 MatchB = true;
4501 break;
4502 }
4503 }
4505 return MatchA && MatchB;
4506 }
4508 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4509 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4510 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4511 MVT VT = SVOp->getSimpleValueType(0);
4513 unsigned HalfSize = VT.getVectorNumElements()/2;
4515 unsigned FstHalf = 0, SndHalf = 0;
4516 for (unsigned i = 0; i < HalfSize; ++i) {
4517 if (SVOp->getMaskElt(i) > 0) {
4518 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4519 break;
4520 }
4521 }
4522 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4523 if (SVOp->getMaskElt(i) > 0) {
4524 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4525 break;
4526 }
4527 }
4529 return (FstHalf | (SndHalf << 4));
4530 }
4532 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4533 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4534 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4535 if (EltSize < 32)
4536 return false;
4538 unsigned NumElts = VT.getVectorNumElements();
4539 Imm8 = 0;
4540 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4541 for (unsigned i = 0; i != NumElts; ++i) {
4542 if (Mask[i] < 0)
4543 continue;
4544 Imm8 |= Mask[i] << (i*2);
4545 }
4546 return true;
4547 }
4549 unsigned LaneSize = 4;
4550 SmallVector<int, 4> MaskVal(LaneSize, -1);
4552 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4553 for (unsigned i = 0; i != LaneSize; ++i) {
4554 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4555 return false;
4556 if (Mask[i+l] < 0)
4557 continue;
4558 if (MaskVal[i] < 0) {
4559 MaskVal[i] = Mask[i+l] - l;
4560 Imm8 |= MaskVal[i] << (i*2);
4561 continue;
4562 }
4563 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4564 return false;
4565 }
4566 }
4567 return true;
4568 }
4570 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4571 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4572 /// Note that VPERMIL mask matching is different depending whether theunderlying
4573 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4574 /// to the same elements of the low, but to the higher half of the source.
4575 /// In VPERMILPD the two lanes could be shuffled independently of each other
4576 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4577 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4578 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4579 if (VT.getSizeInBits() < 256 || EltSize < 32)
4580 return false;
4581 bool symetricMaskRequired = (EltSize == 32);
4582 unsigned NumElts = VT.getVectorNumElements();
4584 unsigned NumLanes = VT.getSizeInBits()/128;
4585 unsigned LaneSize = NumElts/NumLanes;
4586 // 2 or 4 elements in one lane
4588 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4589 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4590 for (unsigned i = 0; i != LaneSize; ++i) {
4591 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4592 return false;
4593 if (symetricMaskRequired) {
4594 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4595 ExpectedMaskVal[i] = Mask[i+l] - l;
4596 continue;
4597 }
4598 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4599 return false;
4600 }
4601 }
4602 }
4603 return true;
4604 }
4606 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4607 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4608 /// element of vector 2 and the other elements to come from vector 1 in order.
4609 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4610 bool V2IsSplat = false, bool V2IsUndef = false) {
4611 if (!VT.is128BitVector())
4612 return false;
4614 unsigned NumOps = VT.getVectorNumElements();
4615 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4616 return false;
4618 if (!isUndefOrEqual(Mask[0], 0))
4619 return false;
4621 for (unsigned i = 1; i != NumOps; ++i)
4622 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4623 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4624 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4625 return false;
4627 return true;
4628 }
4630 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4631 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4632 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4633 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4634 const X86Subtarget *Subtarget) {
4635 if (!Subtarget->hasSSE3())
4636 return false;
4638 unsigned NumElems = VT.getVectorNumElements();
4640 if ((VT.is128BitVector() && NumElems != 4) ||
4641 (VT.is256BitVector() && NumElems != 8) ||
4642 (VT.is512BitVector() && NumElems != 16))
4643 return false;
4645 // "i+1" is the value the indexed mask element must have
4646 for (unsigned i = 0; i != NumElems; i += 2)
4647 if (!isUndefOrEqual(Mask[i], i+1) ||
4648 !isUndefOrEqual(Mask[i+1], i+1))
4649 return false;
4651 return true;
4652 }
4654 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4655 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4656 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4657 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4658 const X86Subtarget *Subtarget) {
4659 if (!Subtarget->hasSSE3())
4660 return false;
4662 unsigned NumElems = VT.getVectorNumElements();
4664 if ((VT.is128BitVector() && NumElems != 4) ||
4665 (VT.is256BitVector() && NumElems != 8) ||
4666 (VT.is512BitVector() && NumElems != 16))
4667 return false;
4669 // "i" is the value the indexed mask element must have
4670 for (unsigned i = 0; i != NumElems; i += 2)
4671 if (!isUndefOrEqual(Mask[i], i) ||
4672 !isUndefOrEqual(Mask[i+1], i))
4673 return false;
4675 return true;
4676 }
4678 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4679 /// specifies a shuffle of elements that is suitable for input to 256-bit
4680 /// version of MOVDDUP.
4681 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4682 if (!HasFp256 || !VT.is256BitVector())
4683 return false;
4685 unsigned NumElts = VT.getVectorNumElements();
4686 if (NumElts != 4)
4687 return false;
4689 for (unsigned i = 0; i != NumElts/2; ++i)
4690 if (!isUndefOrEqual(Mask[i], 0))
4691 return false;
4692 for (unsigned i = NumElts/2; i != NumElts; ++i)
4693 if (!isUndefOrEqual(Mask[i], NumElts/2))
4694 return false;
4695 return true;
4696 }
4698 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4699 /// specifies a shuffle of elements that is suitable for input to 128-bit
4700 /// version of MOVDDUP.
4701 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4702 if (!VT.is128BitVector())
4703 return false;
4705 unsigned e = VT.getVectorNumElements() / 2;
4706 for (unsigned i = 0; i != e; ++i)
4707 if (!isUndefOrEqual(Mask[i], i))
4708 return false;
4709 for (unsigned i = 0; i != e; ++i)
4710 if (!isUndefOrEqual(Mask[e+i], i))
4711 return false;
4712 return true;
4713 }
4715 /// isVEXTRACTIndex - Return true if the specified
4716 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4717 /// suitable for instruction that extract 128 or 256 bit vectors
4718 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4719 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4720 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4721 return false;
4723 // The index should be aligned on a vecWidth-bit boundary.
4724 uint64_t Index =
4725 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4727 MVT VT = N->getSimpleValueType(0);
4728 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4729 bool Result = (Index * ElSize) % vecWidth == 0;
4731 return Result;
4732 }
4734 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4735 /// operand specifies a subvector insert that is suitable for input to
4736 /// insertion of 128 or 256-bit subvectors
4737 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4738 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4739 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4740 return false;
4741 // The index should be aligned on a vecWidth-bit boundary.
4742 uint64_t Index =
4743 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4745 MVT VT = N->getSimpleValueType(0);
4746 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4747 bool Result = (Index * ElSize) % vecWidth == 0;
4749 return Result;
4750 }
4752 bool X86::isVINSERT128Index(SDNode *N) {
4753 return isVINSERTIndex(N, 128);
4754 }
4756 bool X86::isVINSERT256Index(SDNode *N) {
4757 return isVINSERTIndex(N, 256);
4758 }
4760 bool X86::isVEXTRACT128Index(SDNode *N) {
4761 return isVEXTRACTIndex(N, 128);
4762 }
4764 bool X86::isVEXTRACT256Index(SDNode *N) {
4765 return isVEXTRACTIndex(N, 256);
4766 }
4768 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4769 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4770 /// Handles 128-bit and 256-bit.
4771 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4772 MVT VT = N->getSimpleValueType(0);
4774 assert((VT.getSizeInBits() >= 128) &&
4775 "Unsupported vector type for PSHUF/SHUFP");
4777 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4778 // independently on 128-bit lanes.
4779 unsigned NumElts = VT.getVectorNumElements();
4780 unsigned NumLanes = VT.getSizeInBits()/128;
4781 unsigned NumLaneElts = NumElts/NumLanes;
4783 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4784 "Only supports 2, 4 or 8 elements per lane");
4786 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4787 unsigned Mask = 0;
4788 for (unsigned i = 0; i != NumElts; ++i) {
4789 int Elt = N->getMaskElt(i);
4790 if (Elt < 0) continue;
4791 Elt &= NumLaneElts - 1;
4792 unsigned ShAmt = (i << Shift) % 8;
4793 Mask |= Elt << ShAmt;
4794 }
4796 return Mask;
4797 }
4799 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4800 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4801 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4802 MVT VT = N->getSimpleValueType(0);
4804 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4805 "Unsupported vector type for PSHUFHW");
4807 unsigned NumElts = VT.getVectorNumElements();
4809 unsigned Mask = 0;
4810 for (unsigned l = 0; l != NumElts; l += 8) {
4811 // 8 nodes per lane, but we only care about the last 4.
4812 for (unsigned i = 0; i < 4; ++i) {
4813 int Elt = N->getMaskElt(l+i+4);
4814 if (Elt < 0) continue;
4815 Elt &= 0x3; // only 2-bits.
4816 Mask |= Elt << (i * 2);
4817 }
4818 }
4820 return Mask;
4821 }
4823 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4824 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4825 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4826 MVT VT = N->getSimpleValueType(0);
4828 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4829 "Unsupported vector type for PSHUFHW");
4831 unsigned NumElts = VT.getVectorNumElements();
4833 unsigned Mask = 0;
4834 for (unsigned l = 0; l != NumElts; l += 8) {
4835 // 8 nodes per lane, but we only care about the first 4.
4836 for (unsigned i = 0; i < 4; ++i) {
4837 int Elt = N->getMaskElt(l+i);
4838 if (Elt < 0) continue;
4839 Elt &= 0x3; // only 2-bits
4840 Mask |= Elt << (i * 2);
4841 }
4842 }
4844 return Mask;
4845 }
4847 /// \brief Return the appropriate immediate to shuffle the specified
4848 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4849 /// VALIGN (if Interlane is true) instructions.
4850 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4851 bool InterLane) {
4852 MVT VT = SVOp->getSimpleValueType(0);
4853 unsigned EltSize = InterLane ? 1 :
4854 VT.getVectorElementType().getSizeInBits() >> 3;
4856 unsigned NumElts = VT.getVectorNumElements();
4857 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4858 unsigned NumLaneElts = NumElts/NumLanes;
4860 int Val = 0;
4861 unsigned i;
4862 for (i = 0; i != NumElts; ++i) {
4863 Val = SVOp->getMaskElt(i);
4864 if (Val >= 0)
4865 break;
4866 }
4867 if (Val >= (int)NumElts)
4868 Val -= NumElts - NumLaneElts;
4870 assert(Val - i > 0 && "PALIGNR imm should be positive");
4871 return (Val - i) * EltSize;
4872 }
4874 /// \brief Return the appropriate immediate to shuffle the specified
4875 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4876 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4877 return getShuffleAlignrImmediate(SVOp, false);
4878 }
4880 /// \brief Return the appropriate immediate to shuffle the specified
4881 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4882 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4883 return getShuffleAlignrImmediate(SVOp, true);
4884 }
4887 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4888 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4889 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4890 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4892 uint64_t Index =
4893 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4895 MVT VecVT = N->getOperand(0).getSimpleValueType();
4896 MVT ElVT = VecVT.getVectorElementType();
4898 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4899 return Index / NumElemsPerChunk;
4900 }
4902 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4903 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4904 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4905 llvm_unreachable("Illegal insert subvector for VINSERT");
4907 uint64_t Index =
4908 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4910 MVT VecVT = N->getSimpleValueType(0);
4911 MVT ElVT = VecVT.getVectorElementType();
4913 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4914 return Index / NumElemsPerChunk;
4915 }
4917 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4918 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4919 /// and VINSERTI128 instructions.
4920 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4921 return getExtractVEXTRACTImmediate(N, 128);
4922 }
4924 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4925 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4926 /// and VINSERTI64x4 instructions.
4927 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4928 return getExtractVEXTRACTImmediate(N, 256);
4929 }
4931 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4932 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4933 /// and VINSERTI128 instructions.
4934 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4935 return getInsertVINSERTImmediate(N, 128);
4936 }
4938 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4939 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4940 /// and VINSERTI64x4 instructions.
4941 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4942 return getInsertVINSERTImmediate(N, 256);
4943 }
4945 /// isZero - Returns true if Elt is a constant integer zero
4946 static bool isZero(SDValue V) {
4947 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4948 return C && C->isNullValue();
4949 }
4951 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4952 /// constant +0.0.
4953 bool X86::isZeroNode(SDValue Elt) {
4954 if (isZero(Elt))
4955 return true;
4956 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4957 return CFP->getValueAPF().isPosZero();
4958 return false;
4959 }
4961 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4962 /// match movhlps. The lower half elements should come from upper half of
4963 /// V1 (and in order), and the upper half elements should come from the upper
4964 /// half of V2 (and in order).
4965 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4966 if (!VT.is128BitVector())
4967 return false;
4968 if (VT.getVectorNumElements() != 4)
4969 return false;
4970 for (unsigned i = 0, e = 2; i != e; ++i)
4971 if (!isUndefOrEqual(Mask[i], i+2))
4972 return false;
4973 for (unsigned i = 2; i != 4; ++i)
4974 if (!isUndefOrEqual(Mask[i], i+4))
4975 return false;
4976 return true;
4977 }
4979 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4980 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4981 /// required.
4982 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4983 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4984 return false;
4985 N = N->getOperand(0).getNode();
4986 if (!ISD::isNON_EXTLoad(N))
4987 return false;
4988 if (LD)
4989 *LD = cast<LoadSDNode>(N);
4990 return true;
4991 }
4993 // Test whether the given value is a vector value which will be legalized
4994 // into a load.
4995 static bool WillBeConstantPoolLoad(SDNode *N) {
4996 if (N->getOpcode() != ISD::BUILD_VECTOR)
4997 return false;
4999 // Check for any non-constant elements.
5000 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
5001 switch (N->getOperand(i).getNode()->getOpcode()) {
5002 case ISD::UNDEF:
5003 case ISD::ConstantFP:
5004 case ISD::Constant:
5005 break;
5006 default:
5007 return false;
5008 }
5010 // Vectors of all-zeros and all-ones are materialized with special
5011 // instructions rather than being loaded.
5012 return !ISD::isBuildVectorAllZeros(N) &&
5013 !ISD::isBuildVectorAllOnes(N);
5014 }
5016 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5017 /// match movlp{s|d}. The lower half elements should come from lower half of
5018 /// V1 (and in order), and the upper half elements should come from the upper
5019 /// half of V2 (and in order). And since V1 will become the source of the
5020 /// MOVLP, it must be either a vector load or a scalar load to vector.
5021 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5022 ArrayRef<int> Mask, MVT VT) {
5023 if (!VT.is128BitVector())
5024 return false;
5026 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5027 return false;
5028 // Is V2 is a vector load, don't do this transformation. We will try to use
5029 // load folding shufps op.
5030 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5031 return false;
5033 unsigned NumElems = VT.getVectorNumElements();
5035 if (NumElems != 2 && NumElems != 4)
5036 return false;
5037 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5038 if (!isUndefOrEqual(Mask[i], i))
5039 return false;
5040 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5041 if (!isUndefOrEqual(Mask[i], i+NumElems))
5042 return false;
5043 return true;
5044 }
5046 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5047 /// to an zero vector.
5048 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5049 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5050 SDValue V1 = N->getOperand(0);
5051 SDValue V2 = N->getOperand(1);
5052 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5053 for (unsigned i = 0; i != NumElems; ++i) {
5054 int Idx = N->getMaskElt(i);
5055 if (Idx >= (int)NumElems) {
5056 unsigned Opc = V2.getOpcode();
5057 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5058 continue;
5059 if (Opc != ISD::BUILD_VECTOR ||
5060 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5061 return false;
5062 } else if (Idx >= 0) {
5063 unsigned Opc = V1.getOpcode();
5064 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5065 continue;
5066 if (Opc != ISD::BUILD_VECTOR ||
5067 !X86::isZeroNode(V1.getOperand(Idx)))
5068 return false;
5069 }
5070 }
5071 return true;
5072 }
5074 /// getZeroVector - Returns a vector of specified type with all zero elements.
5075 ///
5076 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5077 SelectionDAG &DAG, SDLoc dl) {
5078 assert(VT.isVector() && "Expected a vector type");
5080 // Always build SSE zero vectors as <4 x i32> bitcasted
5081 // to their dest type. This ensures they get CSE'd.
5082 SDValue Vec;
5083 if (VT.is128BitVector()) { // SSE
5084 if (Subtarget->hasSSE2()) { // SSE2
5085 SDValue Cst = DAG.getConstant(0, MVT::i32);
5086 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5087 } else { // SSE1
5088 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5089 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5090 }
5091 } else if (VT.is256BitVector()) { // AVX
5092 if (Subtarget->hasInt256()) { // AVX2
5093 SDValue Cst = DAG.getConstant(0, MVT::i32);
5094 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5095 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5096 } else {
5097 // 256-bit logic and arithmetic instructions in AVX are all
5098 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5099 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5100 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5101 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5102 }
5103 } else if (VT.is512BitVector()) { // AVX-512
5104 SDValue Cst = DAG.getConstant(0, MVT::i32);
5105 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5106 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5107 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5108 } else if (VT.getScalarType() == MVT::i1) {
5109 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5110 SDValue Cst = DAG.getConstant(0, MVT::i1);
5111 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5112 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5113 } else
5114 llvm_unreachable("Unexpected vector type");
5116 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5117 }
5119 /// getOnesVector - Returns a vector of specified type with all bits set.
5120 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5121 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5122 /// Then bitcast to their original type, ensuring they get CSE'd.
5123 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5124 SDLoc dl) {
5125 assert(VT.isVector() && "Expected a vector type");
5127 SDValue Cst = DAG.getConstant(~0U, MVT::i32);
5128 SDValue Vec;
5129 if (VT.is256BitVector()) {
5130 if (HasInt256) { // AVX2
5131 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5132 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5133 } else { // AVX
5134 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5135 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5136 }
5137 } else if (VT.is128BitVector()) {
5138 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5139 } else
5140 llvm_unreachable("Unexpected vector type");
5142 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5143 }
5145 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5146 /// that point to V2 points to its first element.
5147 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5148 for (unsigned i = 0; i != NumElems; ++i) {
5149 if (Mask[i] > (int)NumElems) {
5150 Mask[i] = NumElems;
5151 }
5152 }
5153 }
5155 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5156 /// operation of specified width.
5157 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5158 SDValue V2) {
5159 unsigned NumElems = VT.getVectorNumElements();
5160 SmallVector<int, 8> Mask;
5161 Mask.push_back(NumElems);
5162 for (unsigned i = 1; i != NumElems; ++i)
5163 Mask.push_back(i);
5164 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5165 }
5167 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5168 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5169 SDValue V2) {
5170 unsigned NumElems = VT.getVectorNumElements();
5171 SmallVector<int, 8> Mask;
5172 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5173 Mask.push_back(i);
5174 Mask.push_back(i + NumElems);
5175 }
5176 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5177 }
5179 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5180 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5181 SDValue V2) {
5182 unsigned NumElems = VT.getVectorNumElements();
5183 SmallVector<int, 8> Mask;
5184 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5185 Mask.push_back(i + Half);
5186 Mask.push_back(i + NumElems + Half);
5187 }
5188 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5189 }
5191 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5192 // a generic shuffle instruction because the target has no such instructions.
5193 // Generate shuffles which repeat i16 and i8 several times until they can be
5194 // represented by v4f32 and then be manipulated by target suported shuffles.
5195 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5196 MVT VT = V.getSimpleValueType();
5197 int NumElems = VT.getVectorNumElements();
5198 SDLoc dl(V);
5200 while (NumElems > 4) {
5201 if (EltNo < NumElems/2) {
5202 V = getUnpackl(DAG, dl, VT, V, V);
5203 } else {
5204 V = getUnpackh(DAG, dl, VT, V, V);
5205 EltNo -= NumElems/2;
5206 }
5207 NumElems >>= 1;
5208 }
5209 return V;
5210 }
5212 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5213 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5214 MVT VT = V.getSimpleValueType();
5215 SDLoc dl(V);
5217 if (VT.is128BitVector()) {
5218 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5219 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5220 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5221 &SplatMask[0]);
5222 } else if (VT.is256BitVector()) {
5223 // To use VPERMILPS to splat scalars, the second half of indicies must
5224 // refer to the higher part, which is a duplication of the lower one,
5225 // because VPERMILPS can only handle in-lane permutations.
5226 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5227 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5229 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5230 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5231 &SplatMask[0]);
5232 } else
5233 llvm_unreachable("Vector size not supported");
5235 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5236 }
5238 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5239 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5240 MVT SrcVT = SV->getSimpleValueType(0);
5241 SDValue V1 = SV->getOperand(0);
5242 SDLoc dl(SV);
5244 int EltNo = SV->getSplatIndex();
5245 int NumElems = SrcVT.getVectorNumElements();
5246 bool Is256BitVec = SrcVT.is256BitVector();
5248 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5249 "Unknown how to promote splat for type");
5251 // Extract the 128-bit part containing the splat element and update
5252 // the splat element index when it refers to the higher register.
5253 if (Is256BitVec) {
5254 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5255 if (EltNo >= NumElems/2)
5256 EltNo -= NumElems/2;
5257 }
5259 // All i16 and i8 vector types can't be used directly by a generic shuffle
5260 // instruction because the target has no such instruction. Generate shuffles
5261 // which repeat i16 and i8 several times until they fit in i32, and then can
5262 // be manipulated by target suported shuffles.
5263 MVT EltVT = SrcVT.getVectorElementType();
5264 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5265 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5267 // Recreate the 256-bit vector and place the same 128-bit vector
5268 // into the low and high part. This is necessary because we want
5269 // to use VPERM* to shuffle the vectors
5270 if (Is256BitVec) {
5271 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5272 }
5274 return getLegalSplat(DAG, V1, EltNo);
5275 }
5277 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5278 /// vector of zero or undef vector. This produces a shuffle where the low
5279 /// element of V2 is swizzled into the zero/undef vector, landing at element
5280 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5281 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5282 bool IsZero,
5283 const X86Subtarget *Subtarget,
5284 SelectionDAG &DAG) {
5285 MVT VT = V2.getSimpleValueType();
5286 SDValue V1 = IsZero
5287 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5288 unsigned NumElems = VT.getVectorNumElements();
5289 SmallVector<int, 16> MaskVec;
5290 for (unsigned i = 0; i != NumElems; ++i)
5291 // If this is the insertion idx, put the low elt of V2 here.
5292 MaskVec.push_back(i == Idx ? NumElems : i);
5293 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5294 }
5296 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5297 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5298 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5299 /// shuffles which use a single input multiple times, and in those cases it will
5300 /// adjust the mask to only have indices within that single input.
5301 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5302 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5303 unsigned NumElems = VT.getVectorNumElements();
5304 SDValue ImmN;
5306 IsUnary = false;
5307 bool IsFakeUnary = false;
5308 switch(N->getOpcode()) {
5309 case X86ISD::BLENDI:
5310 ImmN = N->getOperand(N->getNumOperands()-1);
5311 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5312 break;
5313 case X86ISD::SHUFP:
5314 ImmN = N->getOperand(N->getNumOperands()-1);
5315 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5316 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5317 break;
5318 case X86ISD::UNPCKH:
5319 DecodeUNPCKHMask(VT, Mask);
5320 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5321 break;
5322 case X86ISD::UNPCKL:
5323 DecodeUNPCKLMask(VT, Mask);
5324 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5325 break;
5326 case X86ISD::MOVHLPS:
5327 DecodeMOVHLPSMask(NumElems, Mask);
5328 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5329 break;
5330 case X86ISD::MOVLHPS:
5331 DecodeMOVLHPSMask(NumElems, Mask);
5332 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5333 break;
5334 case X86ISD::PALIGNR:
5335 ImmN = N->getOperand(N->getNumOperands()-1);
5336 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5337 break;
5338 case X86ISD::PSHUFD:
5339 case X86ISD::VPERMILPI:
5340 ImmN = N->getOperand(N->getNumOperands()-1);
5341 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5342 IsUnary = true;
5343 break;
5344 case X86ISD::PSHUFHW:
5345 ImmN = N->getOperand(N->getNumOperands()-1);
5346 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5347 IsUnary = true;
5348 break;
5349 case X86ISD::PSHUFLW:
5350 ImmN = N->getOperand(N->getNumOperands()-1);
5351 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5352 IsUnary = true;
5353 break;
5354 case X86ISD::PSHUFB: {
5355 IsUnary = true;
5356 SDValue MaskNode = N->getOperand(1);
5357 while (MaskNode->getOpcode() == ISD::BITCAST)
5358 MaskNode = MaskNode->getOperand(0);
5360 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5361 // If we have a build-vector, then things are easy.
5362 EVT VT = MaskNode.getValueType();
5363 assert(VT.isVector() &&
5364 "Can't produce a non-vector with a build_vector!");
5365 if (!VT.isInteger())
5366 return false;
5368 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5370 SmallVector<uint64_t, 32> RawMask;
5371 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5372 SDValue Op = MaskNode->getOperand(i);
5373 if (Op->getOpcode() == ISD::UNDEF) {
5374 RawMask.push_back((uint64_t)SM_SentinelUndef);
5375 continue;
5376 }
5377 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5378 if (!CN)
5379 return false;
5380 APInt MaskElement = CN->getAPIntValue();
5382 // We now have to decode the element which could be any integer size and
5383 // extract each byte of it.
5384 for (int j = 0; j < NumBytesPerElement; ++j) {
5385 // Note that this is x86 and so always little endian: the low byte is
5386 // the first byte of the mask.
5387 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5388 MaskElement = MaskElement.lshr(8);
5389 }
5390 }
5391 DecodePSHUFBMask(RawMask, Mask);
5392 break;
5393 }
5395 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5396 if (!MaskLoad)
5397 return false;
5399 SDValue Ptr = MaskLoad->getBasePtr();
5400 if (Ptr->getOpcode() == X86ISD::Wrapper)
5401 Ptr = Ptr->getOperand(0);
5403 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5404 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5405 return false;
5407 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5408 // FIXME: Support AVX-512 here.
5409 Type *Ty = C->getType();
5410 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5411 Ty->getVectorNumElements() != 32))
5412 return false;
5414 DecodePSHUFBMask(C, Mask);
5415 break;
5416 }
5418 return false;
5419 }
5420 case X86ISD::VPERMI:
5421 ImmN = N->getOperand(N->getNumOperands()-1);
5422 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5423 IsUnary = true;
5424 break;
5425 case X86ISD::MOVSS:
5426 case X86ISD::MOVSD: {
5427 // The index 0 always comes from the first element of the second source,
5428 // this is why MOVSS and MOVSD are used in the first place. The other
5429 // elements come from the other positions of the first source vector
5430 Mask.push_back(NumElems);
5431 for (unsigned i = 1; i != NumElems; ++i) {
5432 Mask.push_back(i);
5433 }
5434 break;
5435 }
5436 case X86ISD::VPERM2X128:
5437 ImmN = N->getOperand(N->getNumOperands()-1);
5438 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5439 if (Mask.empty()) return false;
5440 break;
5441 case X86ISD::MOVSLDUP:
5442 DecodeMOVSLDUPMask(VT, Mask);
5443 break;
5444 case X86ISD::MOVSHDUP:
5445 DecodeMOVSHDUPMask(VT, Mask);
5446 break;
5447 case X86ISD::MOVDDUP:
5448 case X86ISD::MOVLHPD:
5449 case X86ISD::MOVLPD:
5450 case X86ISD::MOVLPS:
5451 // Not yet implemented
5452 return false;
5453 default: llvm_unreachable("unknown target shuffle node");
5454 }
5456 // If we have a fake unary shuffle, the shuffle mask is spread across two
5457 // inputs that are actually the same node. Re-map the mask to always point
5458 // into the first input.
5459 if (IsFakeUnary)
5460 for (int &M : Mask)
5461 if (M >= (int)Mask.size())
5462 M -= Mask.size();
5464 return true;
5465 }
5467 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5468 /// element of the result of the vector shuffle.
5469 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5470 unsigned Depth) {
5471 if (Depth == 6)
5472 return SDValue(); // Limit search depth.
5474 SDValue V = SDValue(N, 0);
5475 EVT VT = V.getValueType();
5476 unsigned Opcode = V.getOpcode();
5478 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5479 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5480 int Elt = SV->getMaskElt(Index);
5482 if (Elt < 0)
5483 return DAG.getUNDEF(VT.getVectorElementType());
5485 unsigned NumElems = VT.getVectorNumElements();
5486 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5487 : SV->getOperand(1);
5488 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5489 }
5491 // Recurse into target specific vector shuffles to find scalars.
5492 if (isTargetShuffle(Opcode)) {
5493 MVT ShufVT = V.getSimpleValueType();
5494 unsigned NumElems = ShufVT.getVectorNumElements();
5495 SmallVector<int, 16> ShuffleMask;
5496 bool IsUnary;
5498 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5499 return SDValue();
5501 int Elt = ShuffleMask[Index];
5502 if (Elt < 0)
5503 return DAG.getUNDEF(ShufVT.getVectorElementType());
5505 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5506 : N->getOperand(1);
5507 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5508 Depth+1);
5509 }
5511 // Actual nodes that may contain scalar elements
5512 if (Opcode == ISD::BITCAST) {
5513 V = V.getOperand(0);
5514 EVT SrcVT = V.getValueType();
5515 unsigned NumElems = VT.getVectorNumElements();
5517 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5518 return SDValue();
5519 }
5521 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5522 return (Index == 0) ? V.getOperand(0)
5523 : DAG.getUNDEF(VT.getVectorElementType());
5525 if (V.getOpcode() == ISD::BUILD_VECTOR)
5526 return V.getOperand(Index);
5528 return SDValue();
5529 }
5531 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5532 /// shuffle operation which come from a consecutively from a zero. The
5533 /// search can start in two different directions, from left or right.
5534 /// We count undefs as zeros until PreferredNum is reached.
5535 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5536 unsigned NumElems, bool ZerosFromLeft,
5537 SelectionDAG &DAG,
5538 unsigned PreferredNum = -1U) {
5539 unsigned NumZeros = 0;
5540 for (unsigned i = 0; i != NumElems; ++i) {
5541 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5542 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5543 if (!Elt.getNode())
5544 break;
5546 if (X86::isZeroNode(Elt))
5547 ++NumZeros;
5548 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5549 NumZeros = std::min(NumZeros + 1, PreferredNum);
5550 else
5551 break;
5552 }
5554 return NumZeros;
5555 }
5557 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5558 /// correspond consecutively to elements from one of the vector operands,
5559 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5560 static
5561 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5562 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5563 unsigned NumElems, unsigned &OpNum) {
5564 bool SeenV1 = false;
5565 bool SeenV2 = false;
5567 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5568 int Idx = SVOp->getMaskElt(i);
5569 // Ignore undef indicies
5570 if (Idx < 0)
5571 continue;
5573 if (Idx < (int)NumElems)
5574 SeenV1 = true;
5575 else
5576 SeenV2 = true;
5578 // Only accept consecutive elements from the same vector
5579 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5580 return false;
5581 }
5583 OpNum = SeenV1 ? 0 : 1;
5584 return true;
5585 }
5587 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5588 /// logical left shift of a vector.
5589 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5590 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5591 unsigned NumElems =
5592 SVOp->getSimpleValueType(0).getVectorNumElements();
5593 unsigned NumZeros = getNumOfConsecutiveZeros(
5594 SVOp, NumElems, false /* check zeros from right */, DAG,
5595 SVOp->getMaskElt(0));
5596 unsigned OpSrc;
5598 if (!NumZeros)
5599 return false;
5601 // Considering the elements in the mask that are not consecutive zeros,
5602 // check if they consecutively come from only one of the source vectors.
5603 //
5604 // V1 = {X, A, B, C} 0
5605 // \ \ \ /
5606 // vector_shuffle V1, V2 <1, 2, 3, X>
5607 //
5608 if (!isShuffleMaskConsecutive(SVOp,
5609 0, // Mask Start Index
5610 NumElems-NumZeros, // Mask End Index(exclusive)
5611 NumZeros, // Where to start looking in the src vector
5612 NumElems, // Number of elements in vector
5613 OpSrc)) // Which source operand ?
5614 return false;
5616 isLeft = false;
5617 ShAmt = NumZeros;
5618 ShVal = SVOp->getOperand(OpSrc);
5619 return true;
5620 }
5622 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5623 /// logical left shift of a vector.
5624 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5625 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5626 unsigned NumElems =
5627 SVOp->getSimpleValueType(0).getVectorNumElements();
5628 unsigned NumZeros = getNumOfConsecutiveZeros(
5629 SVOp, NumElems, true /* check zeros from left */, DAG,
5630 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5631 unsigned OpSrc;
5633 if (!NumZeros)
5634 return false;
5636 // Considering the elements in the mask that are not consecutive zeros,
5637 // check if they consecutively come from only one of the source vectors.
5638 //
5639 // 0 { A, B, X, X } = V2
5640 // / \ / /
5641 // vector_shuffle V1, V2 <X, X, 4, 5>
5642 //
5643 if (!isShuffleMaskConsecutive(SVOp,
5644 NumZeros, // Mask Start Index
5645 NumElems, // Mask End Index(exclusive)
5646 0, // Where to start looking in the src vector
5647 NumElems, // Number of elements in vector
5648 OpSrc)) // Which source operand ?
5649 return false;
5651 isLeft = true;
5652 ShAmt = NumZeros;
5653 ShVal = SVOp->getOperand(OpSrc);
5654 return true;
5655 }
5657 /// isVectorShift - Returns true if the shuffle can be implemented as a
5658 /// logical left or right shift of a vector.
5659 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5660 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5661 // Although the logic below support any bitwidth size, there are no
5662 // shift instructions which handle more than 128-bit vectors.
5663 if (!SVOp->getSimpleValueType(0).is128BitVector())
5664 return false;
5666 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5667 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5668 return true;
5670 return false;
5671 }
5673 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5674 ///
5675 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5676 unsigned NumNonZero, unsigned NumZero,
5677 SelectionDAG &DAG,
5678 const X86Subtarget* Subtarget,
5679 const TargetLowering &TLI) {
5680 if (NumNonZero > 8)
5681 return SDValue();
5683 SDLoc dl(Op);
5684 SDValue V;
5685 bool First = true;
5686 for (unsigned i = 0; i < 16; ++i) {
5687 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5688 if (ThisIsNonZero && First) {
5689 if (NumZero)
5690 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5691 else
5692 V = DAG.getUNDEF(MVT::v8i16);
5693 First = false;
5694 }
5696 if ((i & 1) != 0) {
5697 SDValue ThisElt, LastElt;
5698 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5699 if (LastIsNonZero) {
5700 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5701 MVT::i16, Op.getOperand(i-1));
5702 }
5703 if (ThisIsNonZero) {
5704 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5705 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5706 ThisElt, DAG.getConstant(8, MVT::i8));
5707 if (LastIsNonZero)
5708 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5709 } else
5710 ThisElt = LastElt;
5712 if (ThisElt.getNode())
5713 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5714 DAG.getIntPtrConstant(i/2));
5715 }
5716 }
5718 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5719 }
5721 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5722 ///
5723 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5724 unsigned NumNonZero, unsigned NumZero,
5725 SelectionDAG &DAG,
5726 const X86Subtarget* Subtarget,
5727 const TargetLowering &TLI) {
5728 if (NumNonZero > 4)
5729 return SDValue();
5731 SDLoc dl(Op);
5732 SDValue V;
5733 bool First = true;
5734 for (unsigned i = 0; i < 8; ++i) {
5735 bool isNonZero = (NonZeros & (1 << i)) != 0;
5736 if (isNonZero) {
5737 if (First) {
5738 if (NumZero)
5739 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5740 else
5741 V = DAG.getUNDEF(MVT::v8i16);
5742 First = false;
5743 }
5744 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5745 MVT::v8i16, V, Op.getOperand(i),
5746 DAG.getIntPtrConstant(i));
5747 }
5748 }
5750 return V;
5751 }
5753 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5754 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5755 const X86Subtarget *Subtarget,
5756 const TargetLowering &TLI) {
5757 // Find all zeroable elements.
5758 bool Zeroable[4];
5759 for (int i=0; i < 4; ++i) {
5760 SDValue Elt = Op->getOperand(i);
5761 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5762 }
5763 assert(std::count_if(&Zeroable[0], &Zeroable[4],
5764 [](bool M) { return !M; }) > 1 &&
5765 "We expect at least two non-zero elements!");
5767 // We only know how to deal with build_vector nodes where elements are either
5768 // zeroable or extract_vector_elt with constant index.
5769 SDValue FirstNonZero;
5770 unsigned FirstNonZeroIdx;
5771 for (unsigned i=0; i < 4; ++i) {
5772 if (Zeroable[i])
5773 continue;
5774 SDValue Elt = Op->getOperand(i);
5775 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5776 !isa<ConstantSDNode>(Elt.getOperand(1)))
5777 return SDValue();
5778 // Make sure that this node is extracting from a 128-bit vector.
5779 MVT VT = Elt.getOperand(0).getSimpleValueType();
5780 if (!VT.is128BitVector())
5781 return SDValue();
5782 if (!FirstNonZero.getNode()) {
5783 FirstNonZero = Elt;
5784 FirstNonZeroIdx = i;
5785 }
5786 }
5788 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5789 SDValue V1 = FirstNonZero.getOperand(0);
5790 MVT VT = V1.getSimpleValueType();
5792 // See if this build_vector can be lowered as a blend with zero.
5793 SDValue Elt;
5794 unsigned EltMaskIdx, EltIdx;
5795 int Mask[4];
5796 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5797 if (Zeroable[EltIdx]) {
5798 // The zero vector will be on the right hand side.
5799 Mask[EltIdx] = EltIdx+4;
5800 continue;
5801 }
5803 Elt = Op->getOperand(EltIdx);
5804 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5805 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5806 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5807 break;
5808 Mask[EltIdx] = EltIdx;
5809 }
5811 if (EltIdx == 4) {
5812 // Let the shuffle legalizer deal with blend operations.
5813 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5814 if (V1.getSimpleValueType() != VT)
5815 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5816 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5817 }
5819 // See if we can lower this build_vector to a INSERTPS.
5820 if (!Subtarget->hasSSE41())
5821 return SDValue();
5823 SDValue V2 = Elt.getOperand(0);
5824 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5825 V1 = SDValue();
5827 bool CanFold = true;
5828 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5829 if (Zeroable[i])
5830 continue;
5832 SDValue Current = Op->getOperand(i);
5833 SDValue SrcVector = Current->getOperand(0);
5834 if (!V1.getNode())
5835 V1 = SrcVector;
5836 CanFold = SrcVector == V1 &&
5837 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5838 }
5840 if (!CanFold)
5841 return SDValue();
5843 assert(V1.getNode() && "Expected at least two non-zero elements!");
5844 if (V1.getSimpleValueType() != MVT::v4f32)
5845 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5846 if (V2.getSimpleValueType() != MVT::v4f32)
5847 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5849 // Ok, we can emit an INSERTPS instruction.
5850 unsigned ZMask = 0;
5851 for (int i = 0; i < 4; ++i)
5852 if (Zeroable[i])
5853 ZMask |= 1 << i;
5855 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5856 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5857 SDValue Result = DAG.getNode(X86ISD::INSERTPS, SDLoc(Op), MVT::v4f32, V1, V2,
5858 DAG.getIntPtrConstant(InsertPSMask));
5859 return DAG.getNode(ISD::BITCAST, SDLoc(Op), VT, Result);
5860 }
5862 /// getVShift - Return a vector logical shift node.
5863 ///
5864 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5865 unsigned NumBits, SelectionDAG &DAG,
5866 const TargetLowering &TLI, SDLoc dl) {
5867 assert(VT.is128BitVector() && "Unknown type for VShift");
5868 EVT ShVT = MVT::v2i64;
5869 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5870 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5871 return DAG.getNode(ISD::BITCAST, dl, VT,
5872 DAG.getNode(Opc, dl, ShVT, SrcOp,
5873 DAG.getConstant(NumBits,
5874 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5875 }
5877 static SDValue
5878 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5880 // Check if the scalar load can be widened into a vector load. And if
5881 // the address is "base + cst" see if the cst can be "absorbed" into
5882 // the shuffle mask.
5883 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5884 SDValue Ptr = LD->getBasePtr();
5885 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5886 return SDValue();
5887 EVT PVT = LD->getValueType(0);
5888 if (PVT != MVT::i32 && PVT != MVT::f32)
5889 return SDValue();
5891 int FI = -1;
5892 int64_t Offset = 0;
5893 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5894 FI = FINode->getIndex();
5895 Offset = 0;
5896 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5897 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5898 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5899 Offset = Ptr.getConstantOperandVal(1);
5900 Ptr = Ptr.getOperand(0);
5901 } else {
5902 return SDValue();
5903 }
5905 // FIXME: 256-bit vector instructions don't require a strict alignment,
5906 // improve this code to support it better.
5907 unsigned RequiredAlign = VT.getSizeInBits()/8;
5908 SDValue Chain = LD->getChain();
5909 // Make sure the stack object alignment is at least 16 or 32.
5910 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5911 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5912 if (MFI->isFixedObjectIndex(FI)) {
5913 // Can't change the alignment. FIXME: It's possible to compute
5914 // the exact stack offset and reference FI + adjust offset instead.
5915 // If someone *really* cares about this. That's the way to implement it.
5916 return SDValue();
5917 } else {
5918 MFI->setObjectAlignment(FI, RequiredAlign);
5919 }
5920 }
5922 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5923 // Ptr + (Offset & ~15).
5924 if (Offset < 0)
5925 return SDValue();
5926 if ((Offset % RequiredAlign) & 3)
5927 return SDValue();
5928 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5929 if (StartOffset)
5930 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5931 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5933 int EltNo = (Offset - StartOffset) >> 2;
5934 unsigned NumElems = VT.getVectorNumElements();
5936 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5937 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5938 LD->getPointerInfo().getWithOffset(StartOffset),
5939 false, false, false, 0);
5941 SmallVector<int, 8> Mask;
5942 for (unsigned i = 0; i != NumElems; ++i)
5943 Mask.push_back(EltNo);
5945 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5946 }
5948 return SDValue();
5949 }
5951 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5952 /// vector of type 'VT', see if the elements can be replaced by a single large
5953 /// load which has the same value as a build_vector whose operands are 'elts'.
5954 ///
5955 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5956 ///
5957 /// FIXME: we'd also like to handle the case where the last elements are zero
5958 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5959 /// There's even a handy isZeroNode for that purpose.
5960 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5961 SDLoc &DL, SelectionDAG &DAG,
5962 bool isAfterLegalize) {
5963 EVT EltVT = VT.getVectorElementType();
5964 unsigned NumElems = Elts.size();
5966 LoadSDNode *LDBase = nullptr;
5967 unsigned LastLoadedElt = -1U;
5969 // For each element in the initializer, see if we've found a load or an undef.
5970 // If we don't find an initial load element, or later load elements are
5971 // non-consecutive, bail out.
5972 for (unsigned i = 0; i < NumElems; ++i) {
5973 SDValue Elt = Elts[i];
5975 if (!Elt.getNode() ||
5976 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5977 return SDValue();
5978 if (!LDBase) {
5979 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5980 return SDValue();
5981 LDBase = cast<LoadSDNode>(Elt.getNode());
5982 LastLoadedElt = i;
5983 continue;
5984 }
5985 if (Elt.getOpcode() == ISD::UNDEF)
5986 continue;
5988 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5989 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5990 return SDValue();
5991 LastLoadedElt = i;
5992 }
5994 // If we have found an entire vector of loads and undefs, then return a large
5995 // load of the entire vector width starting at the base pointer. If we found
5996 // consecutive loads for the low half, generate a vzext_load node.
5997 if (LastLoadedElt == NumElems - 1) {
5999 if (isAfterLegalize &&
6000 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
6001 return SDValue();
6003 SDValue NewLd = SDValue();
6005 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
6006 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
6007 LDBase->getPointerInfo(),
6008 LDBase->isVolatile(), LDBase->isNonTemporal(),
6009 LDBase->isInvariant(), 0);
6010 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
6011 LDBase->getPointerInfo(),
6012 LDBase->isVolatile(), LDBase->isNonTemporal(),
6013 LDBase->isInvariant(), LDBase->getAlignment());
6015 if (LDBase->hasAnyUseOfValue(1)) {
6016 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6017 SDValue(LDBase, 1),
6018 SDValue(NewLd.getNode(), 1));
6019 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6020 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6021 SDValue(NewLd.getNode(), 1));
6022 }
6024 return NewLd;
6025 }
6026 if (NumElems == 4 && LastLoadedElt == 1 &&
6027 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
6028 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
6029 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
6030 SDValue ResNode =
6031 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
6032 LDBase->getPointerInfo(),
6033 LDBase->getAlignment(),
6034 false/*isVolatile*/, true/*ReadMem*/,
6035 false/*WriteMem*/);
6037 // Make sure the newly-created LOAD is in the same position as LDBase in
6038 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
6039 // update uses of LDBase's output chain to use the TokenFactor.
6040 if (LDBase->hasAnyUseOfValue(1)) {
6041 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6042 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
6043 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6044 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6045 SDValue(ResNode.getNode(), 1));
6046 }
6048 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
6049 }
6050 return SDValue();
6051 }
6053 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6054 /// to generate a splat value for the following cases:
6055 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6056 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6057 /// a scalar load, or a constant.
6058 /// The VBROADCAST node is returned when a pattern is found,
6059 /// or SDValue() otherwise.
6060 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6061 SelectionDAG &DAG) {
6062 // VBROADCAST requires AVX.
6063 // TODO: Splats could be generated for non-AVX CPUs using SSE
6064 // instructions, but there's less potential gain for only 128-bit vectors.
6065 if (!Subtarget->hasAVX())
6066 return SDValue();
6068 MVT VT = Op.getSimpleValueType();
6069 SDLoc dl(Op);
6071 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6072 "Unsupported vector type for broadcast.");
6074 SDValue Ld;
6075 bool ConstSplatVal;
6077 switch (Op.getOpcode()) {
6078 default:
6079 // Unknown pattern found.
6080 return SDValue();
6082 case ISD::BUILD_VECTOR: {
6083 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6084 BitVector UndefElements;
6085 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6087 // We need a splat of a single value to use broadcast, and it doesn't
6088 // make any sense if the value is only in one element of the vector.
6089 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6090 return SDValue();
6092 Ld = Splat;
6093 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6094 Ld.getOpcode() == ISD::ConstantFP);
6096 // Make sure that all of the users of a non-constant load are from the
6097 // BUILD_VECTOR node.
6098 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6099 return SDValue();
6100 break;
6101 }
6103 case ISD::VECTOR_SHUFFLE: {
6104 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6106 // Shuffles must have a splat mask where the first element is
6107 // broadcasted.
6108 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6109 return SDValue();
6111 SDValue Sc = Op.getOperand(0);
6112 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6113 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6115 if (!Subtarget->hasInt256())
6116 return SDValue();
6118 // Use the register form of the broadcast instruction available on AVX2.
6119 if (VT.getSizeInBits() >= 256)
6120 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6121 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6122 }
6124 Ld = Sc.getOperand(0);
6125 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6126 Ld.getOpcode() == ISD::ConstantFP);
6128 // The scalar_to_vector node and the suspected
6129 // load node must have exactly one user.
6130 // Constants may have multiple users.
6132 // AVX-512 has register version of the broadcast
6133 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6134 Ld.getValueType().getSizeInBits() >= 32;
6135 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6136 !hasRegVer))
6137 return SDValue();
6138 break;
6139 }
6140 }
6142 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6143 bool IsGE256 = (VT.getSizeInBits() >= 256);
6145 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6146 // instruction to save 8 or more bytes of constant pool data.
6147 // TODO: If multiple splats are generated to load the same constant,
6148 // it may be detrimental to overall size. There needs to be a way to detect
6149 // that condition to know if this is truly a size win.
6150 const Function *F = DAG.getMachineFunction().getFunction();
6151 bool OptForSize = F->getAttributes().
6152 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6154 // Handle broadcasting a single constant scalar from the constant pool
6155 // into a vector.
6156 // On Sandybridge (no AVX2), it is still better to load a constant vector
6157 // from the constant pool and not to broadcast it from a scalar.
6158 // But override that restriction when optimizing for size.
6159 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6160 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6161 EVT CVT = Ld.getValueType();
6162 assert(!CVT.isVector() && "Must not broadcast a vector type");
6164 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6165 // For size optimization, also splat v2f64 and v2i64, and for size opt
6166 // with AVX2, also splat i8 and i16.
6167 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6168 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6169 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6170 const Constant *C = nullptr;
6171 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6172 C = CI->getConstantIntValue();
6173 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6174 C = CF->getConstantFPValue();
6176 assert(C && "Invalid constant type");
6178 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6179 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6180 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6181 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6182 MachinePointerInfo::getConstantPool(),
6183 false, false, false, Alignment);
6185 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6186 }
6187 }
6189 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6191 // Handle AVX2 in-register broadcasts.
6192 if (!IsLoad && Subtarget->hasInt256() &&
6193 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6194 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6196 // The scalar source must be a normal load.
6197 if (!IsLoad)
6198 return SDValue();
6200 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6201 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6203 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6204 // double since there is no vbroadcastsd xmm
6205 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6206 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6207 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6208 }
6210 // Unsupported broadcast.
6211 return SDValue();
6212 }
6214 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6215 /// underlying vector and index.
6216 ///
6217 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6218 /// index.
6219 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6220 SDValue ExtIdx) {
6221 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6222 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6223 return Idx;
6225 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6226 // lowered this:
6227 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6228 // to:
6229 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6230 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6231 // undef)
6232 // Constant<0>)
6233 // In this case the vector is the extract_subvector expression and the index
6234 // is 2, as specified by the shuffle.
6235 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6236 SDValue ShuffleVec = SVOp->getOperand(0);
6237 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6238 assert(ShuffleVecVT.getVectorElementType() ==
6239 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6241 int ShuffleIdx = SVOp->getMaskElt(Idx);
6242 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6243 ExtractedFromVec = ShuffleVec;
6244 return ShuffleIdx;
6245 }
6246 return Idx;
6247 }
6249 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6250 MVT VT = Op.getSimpleValueType();
6252 // Skip if insert_vec_elt is not supported.
6253 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6254 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6255 return SDValue();
6257 SDLoc DL(Op);
6258 unsigned NumElems = Op.getNumOperands();
6260 SDValue VecIn1;
6261 SDValue VecIn2;
6262 SmallVector<unsigned, 4> InsertIndices;
6263 SmallVector<int, 8> Mask(NumElems, -1);
6265 for (unsigned i = 0; i != NumElems; ++i) {
6266 unsigned Opc = Op.getOperand(i).getOpcode();
6268 if (Opc == ISD::UNDEF)
6269 continue;
6271 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6272 // Quit if more than 1 elements need inserting.
6273 if (InsertIndices.size() > 1)
6274 return SDValue();
6276 InsertIndices.push_back(i);
6277 continue;
6278 }
6280 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6281 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6282 // Quit if non-constant index.
6283 if (!isa<ConstantSDNode>(ExtIdx))
6284 return SDValue();
6285 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6287 // Quit if extracted from vector of different type.
6288 if (ExtractedFromVec.getValueType() != VT)
6289 return SDValue();
6291 if (!VecIn1.getNode())
6292 VecIn1 = ExtractedFromVec;
6293 else if (VecIn1 != ExtractedFromVec) {
6294 if (!VecIn2.getNode())
6295 VecIn2 = ExtractedFromVec;
6296 else if (VecIn2 != ExtractedFromVec)
6297 // Quit if more than 2 vectors to shuffle
6298 return SDValue();
6299 }
6301 if (ExtractedFromVec == VecIn1)
6302 Mask[i] = Idx;
6303 else if (ExtractedFromVec == VecIn2)
6304 Mask[i] = Idx + NumElems;
6305 }
6307 if (!VecIn1.getNode())
6308 return SDValue();
6310 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6311 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6312 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6313 unsigned Idx = InsertIndices[i];
6314 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6315 DAG.getIntPtrConstant(Idx));
6316 }
6318 return NV;
6319 }
6321 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6322 SDValue
6323 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6325 MVT VT = Op.getSimpleValueType();
6326 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6327 "Unexpected type in LowerBUILD_VECTORvXi1!");
6329 SDLoc dl(Op);
6330 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6331 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6332 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6333 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6334 }
6336 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6337 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6338 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6339 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6340 }
6342 bool AllContants = true;
6343 uint64_t Immediate = 0;
6344 int NonConstIdx = -1;
6345 bool IsSplat = true;
6346 unsigned NumNonConsts = 0;
6347 unsigned NumConsts = 0;
6348 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6349 SDValue In = Op.getOperand(idx);
6350 if (In.getOpcode() == ISD::UNDEF)
6351 continue;
6352 if (!isa<ConstantSDNode>(In)) {
6353 AllContants = false;
6354 NonConstIdx = idx;
6355 NumNonConsts++;
6356 } else {
6357 NumConsts++;
6358 if (cast<ConstantSDNode>(In)->getZExtValue())
6359 Immediate |= (1ULL << idx);
6360 }
6361 if (In != Op.getOperand(0))
6362 IsSplat = false;
6363 }
6365 if (AllContants) {
6366 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6367 DAG.getConstant(Immediate, MVT::i16));
6368 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6369 DAG.getIntPtrConstant(0));
6370 }
6372 if (NumNonConsts == 1 && NonConstIdx != 0) {
6373 SDValue DstVec;
6374 if (NumConsts) {
6375 SDValue VecAsImm = DAG.getConstant(Immediate,
6376 MVT::getIntegerVT(VT.getSizeInBits()));
6377 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6378 }
6379 else
6380 DstVec = DAG.getUNDEF(VT);
6381 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6382 Op.getOperand(NonConstIdx),
6383 DAG.getIntPtrConstant(NonConstIdx));
6384 }
6385 if (!IsSplat && (NonConstIdx != 0))
6386 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6387 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6388 SDValue Select;
6389 if (IsSplat)
6390 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6391 DAG.getConstant(-1, SelectVT),
6392 DAG.getConstant(0, SelectVT));
6393 else
6394 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6395 DAG.getConstant((Immediate | 1), SelectVT),
6396 DAG.getConstant(Immediate, SelectVT));
6397 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6398 }
6400 /// \brief Return true if \p N implements a horizontal binop and return the
6401 /// operands for the horizontal binop into V0 and V1.
6402 ///
6403 /// This is a helper function of PerformBUILD_VECTORCombine.
6404 /// This function checks that the build_vector \p N in input implements a
6405 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6406 /// operation to match.
6407 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6408 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6409 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6410 /// arithmetic sub.
6411 ///
6412 /// This function only analyzes elements of \p N whose indices are
6413 /// in range [BaseIdx, LastIdx).
6414 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6415 SelectionDAG &DAG,
6416 unsigned BaseIdx, unsigned LastIdx,
6417 SDValue &V0, SDValue &V1) {
6418 EVT VT = N->getValueType(0);
6420 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6421 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6422 "Invalid Vector in input!");
6424 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6425 bool CanFold = true;
6426 unsigned ExpectedVExtractIdx = BaseIdx;
6427 unsigned NumElts = LastIdx - BaseIdx;
6428 V0 = DAG.getUNDEF(VT);
6429 V1 = DAG.getUNDEF(VT);
6431 // Check if N implements a horizontal binop.
6432 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6433 SDValue Op = N->getOperand(i + BaseIdx);
6435 // Skip UNDEFs.
6436 if (Op->getOpcode() == ISD::UNDEF) {
6437 // Update the expected vector extract index.
6438 if (i * 2 == NumElts)
6439 ExpectedVExtractIdx = BaseIdx;
6440 ExpectedVExtractIdx += 2;
6441 continue;
6442 }
6444 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6446 if (!CanFold)
6447 break;
6449 SDValue Op0 = Op.getOperand(0);
6450 SDValue Op1 = Op.getOperand(1);
6452 // Try to match the following pattern:
6453 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6454 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6455 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6456 Op0.getOperand(0) == Op1.getOperand(0) &&
6457 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6458 isa<ConstantSDNode>(Op1.getOperand(1)));
6459 if (!CanFold)
6460 break;
6462 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6463 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6465 if (i * 2 < NumElts) {
6466 if (V0.getOpcode() == ISD::UNDEF)
6467 V0 = Op0.getOperand(0);
6468 } else {
6469 if (V1.getOpcode() == ISD::UNDEF)
6470 V1 = Op0.getOperand(0);
6471 if (i * 2 == NumElts)
6472 ExpectedVExtractIdx = BaseIdx;
6473 }
6475 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6476 if (I0 == ExpectedVExtractIdx)
6477 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6478 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6479 // Try to match the following dag sequence:
6480 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6481 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6482 } else
6483 CanFold = false;
6485 ExpectedVExtractIdx += 2;
6486 }
6488 return CanFold;
6489 }
6491 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6492 /// a concat_vector.
6493 ///
6494 /// This is a helper function of PerformBUILD_VECTORCombine.
6495 /// This function expects two 256-bit vectors called V0 and V1.
6496 /// At first, each vector is split into two separate 128-bit vectors.
6497 /// Then, the resulting 128-bit vectors are used to implement two
6498 /// horizontal binary operations.
6499 ///
6500 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6501 ///
6502 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6503 /// the two new horizontal binop.
6504 /// When Mode is set, the first horizontal binop dag node would take as input
6505 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6506 /// horizontal binop dag node would take as input the lower 128-bit of V1
6507 /// and the upper 128-bit of V1.
6508 /// Example:
6509 /// HADD V0_LO, V0_HI
6510 /// HADD V1_LO, V1_HI
6511 ///
6512 /// Otherwise, the first horizontal binop dag node takes as input the lower
6513 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6514 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6515 /// Example:
6516 /// HADD V0_LO, V1_LO
6517 /// HADD V0_HI, V1_HI
6518 ///
6519 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6520 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6521 /// the upper 128-bits of the result.
6522 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6523 SDLoc DL, SelectionDAG &DAG,
6524 unsigned X86Opcode, bool Mode,
6525 bool isUndefLO, bool isUndefHI) {
6526 EVT VT = V0.getValueType();
6527 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6528 "Invalid nodes in input!");
6530 unsigned NumElts = VT.getVectorNumElements();
6531 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6532 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6533 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6534 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6535 EVT NewVT = V0_LO.getValueType();
6537 SDValue LO = DAG.getUNDEF(NewVT);
6538 SDValue HI = DAG.getUNDEF(NewVT);
6540 if (Mode) {
6541 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6542 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6543 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6544 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6545 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6546 } else {
6547 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6548 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6549 V1_LO->getOpcode() != ISD::UNDEF))
6550 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6552 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6553 V1_HI->getOpcode() != ISD::UNDEF))
6554 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6555 }
6557 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6558 }
6560 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6561 /// sequence of 'vadd + vsub + blendi'.
6562 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6563 const X86Subtarget *Subtarget) {
6564 SDLoc DL(BV);
6565 EVT VT = BV->getValueType(0);
6566 unsigned NumElts = VT.getVectorNumElements();
6567 SDValue InVec0 = DAG.getUNDEF(VT);
6568 SDValue InVec1 = DAG.getUNDEF(VT);
6570 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6571 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6573 // Odd-numbered elements in the input build vector are obtained from
6574 // adding two integer/float elements.
6575 // Even-numbered elements in the input build vector are obtained from
6576 // subtracting two integer/float elements.
6577 unsigned ExpectedOpcode = ISD::FSUB;
6578 unsigned NextExpectedOpcode = ISD::FADD;
6579 bool AddFound = false;
6580 bool SubFound = false;
6582 for (unsigned i = 0, e = NumElts; i != e; i++) {
6583 SDValue Op = BV->getOperand(i);
6585 // Skip 'undef' values.
6586 unsigned Opcode = Op.getOpcode();
6587 if (Opcode == ISD::UNDEF) {
6588 std::swap(ExpectedOpcode, NextExpectedOpcode);
6589 continue;
6590 }
6592 // Early exit if we found an unexpected opcode.
6593 if (Opcode != ExpectedOpcode)
6594 return SDValue();
6596 SDValue Op0 = Op.getOperand(0);
6597 SDValue Op1 = Op.getOperand(1);
6599 // Try to match the following pattern:
6600 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6601 // Early exit if we cannot match that sequence.
6602 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6603 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6604 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6605 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6606 Op0.getOperand(1) != Op1.getOperand(1))
6607 return SDValue();
6609 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6610 if (I0 != i)
6611 return SDValue();
6613 // We found a valid add/sub node. Update the information accordingly.
6614 if (i & 1)
6615 AddFound = true;
6616 else
6617 SubFound = true;
6619 // Update InVec0 and InVec1.
6620 if (InVec0.getOpcode() == ISD::UNDEF)
6621 InVec0 = Op0.getOperand(0);
6622 if (InVec1.getOpcode() == ISD::UNDEF)
6623 InVec1 = Op1.getOperand(0);
6625 // Make sure that operands in input to each add/sub node always
6626 // come from a same pair of vectors.
6627 if (InVec0 != Op0.getOperand(0)) {
6628 if (ExpectedOpcode == ISD::FSUB)
6629 return SDValue();
6631 // FADD is commutable. Try to commute the operands
6632 // and then test again.
6633 std::swap(Op0, Op1);
6634 if (InVec0 != Op0.getOperand(0))
6635 return SDValue();
6636 }
6638 if (InVec1 != Op1.getOperand(0))
6639 return SDValue();
6641 // Update the pair of expected opcodes.
6642 std::swap(ExpectedOpcode, NextExpectedOpcode);
6643 }
6645 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6646 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6647 InVec1.getOpcode() != ISD::UNDEF)
6648 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6650 return SDValue();
6651 }
6653 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6654 const X86Subtarget *Subtarget) {
6655 SDLoc DL(N);
6656 EVT VT = N->getValueType(0);
6657 unsigned NumElts = VT.getVectorNumElements();
6658 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6659 SDValue InVec0, InVec1;
6661 // Try to match an ADDSUB.
6662 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6663 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6664 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6665 if (Value.getNode())
6666 return Value;
6667 }
6669 // Try to match horizontal ADD/SUB.
6670 unsigned NumUndefsLO = 0;
6671 unsigned NumUndefsHI = 0;
6672 unsigned Half = NumElts/2;
6674 // Count the number of UNDEF operands in the build_vector in input.
6675 for (unsigned i = 0, e = Half; i != e; ++i)
6676 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6677 NumUndefsLO++;
6679 for (unsigned i = Half, e = NumElts; i != e; ++i)
6680 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6681 NumUndefsHI++;
6683 // Early exit if this is either a build_vector of all UNDEFs or all the
6684 // operands but one are UNDEF.
6685 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6686 return SDValue();
6688 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6689 // Try to match an SSE3 float HADD/HSUB.
6690 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6691 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6693 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6694 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6695 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6696 // Try to match an SSSE3 integer HADD/HSUB.
6697 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6698 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6700 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6701 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6702 }
6704 if (!Subtarget->hasAVX())
6705 return SDValue();
6707 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6708 // Try to match an AVX horizontal add/sub of packed single/double
6709 // precision floating point values from 256-bit vectors.
6710 SDValue InVec2, InVec3;
6711 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6712 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6713 ((InVec0.getOpcode() == ISD::UNDEF ||
6714 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6715 ((InVec1.getOpcode() == ISD::UNDEF ||
6716 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6717 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6719 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6720 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6721 ((InVec0.getOpcode() == ISD::UNDEF ||
6722 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6723 ((InVec1.getOpcode() == ISD::UNDEF ||
6724 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6725 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6726 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6727 // Try to match an AVX2 horizontal add/sub of signed integers.
6728 SDValue InVec2, InVec3;
6729 unsigned X86Opcode;
6730 bool CanFold = true;
6732 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6733 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6734 ((InVec0.getOpcode() == ISD::UNDEF ||
6735 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6736 ((InVec1.getOpcode() == ISD::UNDEF ||
6737 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6738 X86Opcode = X86ISD::HADD;
6739 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6740 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6741 ((InVec0.getOpcode() == ISD::UNDEF ||
6742 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6743 ((InVec1.getOpcode() == ISD::UNDEF ||
6744 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6745 X86Opcode = X86ISD::HSUB;
6746 else
6747 CanFold = false;
6749 if (CanFold) {
6750 // Fold this build_vector into a single horizontal add/sub.
6751 // Do this only if the target has AVX2.
6752 if (Subtarget->hasAVX2())
6753 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6755 // Do not try to expand this build_vector into a pair of horizontal
6756 // add/sub if we can emit a pair of scalar add/sub.
6757 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6758 return SDValue();
6760 // Convert this build_vector into a pair of horizontal binop followed by
6761 // a concat vector.
6762 bool isUndefLO = NumUndefsLO == Half;
6763 bool isUndefHI = NumUndefsHI == Half;
6764 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6765 isUndefLO, isUndefHI);
6766 }
6767 }
6769 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6770 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6771 unsigned X86Opcode;
6772 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6773 X86Opcode = X86ISD::HADD;
6774 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6775 X86Opcode = X86ISD::HSUB;
6776 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6777 X86Opcode = X86ISD::FHADD;
6778 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6779 X86Opcode = X86ISD::FHSUB;
6780 else
6781 return SDValue();
6783 // Don't try to expand this build_vector into a pair of horizontal add/sub
6784 // if we can simply emit a pair of scalar add/sub.
6785 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6786 return SDValue();
6788 // Convert this build_vector into two horizontal add/sub followed by
6789 // a concat vector.
6790 bool isUndefLO = NumUndefsLO == Half;
6791 bool isUndefHI = NumUndefsHI == Half;
6792 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6793 isUndefLO, isUndefHI);
6794 }
6796 return SDValue();
6797 }
6799 SDValue
6800 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6801 SDLoc dl(Op);
6803 MVT VT = Op.getSimpleValueType();
6804 MVT ExtVT = VT.getVectorElementType();
6805 unsigned NumElems = Op.getNumOperands();
6807 // Generate vectors for predicate vectors.
6808 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6809 return LowerBUILD_VECTORvXi1(Op, DAG);
6811 // Vectors containing all zeros can be matched by pxor and xorps later
6812 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6813 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6814 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6815 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6816 return Op;
6818 return getZeroVector(VT, Subtarget, DAG, dl);
6819 }
6821 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6822 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6823 // vpcmpeqd on 256-bit vectors.
6824 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6825 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6826 return Op;
6828 if (!VT.is512BitVector())
6829 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6830 }
6832 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6833 if (Broadcast.getNode())
6834 return Broadcast;
6836 unsigned EVTBits = ExtVT.getSizeInBits();
6838 unsigned NumZero = 0;
6839 unsigned NumNonZero = 0;
6840 unsigned NonZeros = 0;
6841 bool IsAllConstants = true;
6842 SmallSet<SDValue, 8> Values;
6843 for (unsigned i = 0; i < NumElems; ++i) {
6844 SDValue Elt = Op.getOperand(i);
6845 if (Elt.getOpcode() == ISD::UNDEF)
6846 continue;
6847 Values.insert(Elt);
6848 if (Elt.getOpcode() != ISD::Constant &&
6849 Elt.getOpcode() != ISD::ConstantFP)
6850 IsAllConstants = false;
6851 if (X86::isZeroNode(Elt))
6852 NumZero++;
6853 else {
6854 NonZeros |= (1 << i);
6855 NumNonZero++;
6856 }
6857 }
6859 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6860 if (NumNonZero == 0)
6861 return DAG.getUNDEF(VT);
6863 // Special case for single non-zero, non-undef, element.
6864 if (NumNonZero == 1) {
6865 unsigned Idx = countTrailingZeros(NonZeros);
6866 SDValue Item = Op.getOperand(Idx);
6868 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6869 // the value are obviously zero, truncate the value to i32 and do the
6870 // insertion that way. Only do this if the value is non-constant or if the
6871 // value is a constant being inserted into element 0. It is cheaper to do
6872 // a constant pool load than it is to do a movd + shuffle.
6873 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6874 (!IsAllConstants || Idx == 0)) {
6875 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6876 // Handle SSE only.
6877 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6878 EVT VecVT = MVT::v4i32;
6879 unsigned VecElts = 4;
6881 // Truncate the value (which may itself be a constant) to i32, and
6882 // convert it to a vector with movd (S2V+shuffle to zero extend).
6883 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6884 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6886 // If using the new shuffle lowering, just directly insert this.
6887 if (ExperimentalVectorShuffleLowering)
6888 return DAG.getNode(
6889 ISD::BITCAST, dl, VT,
6890 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6892 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6894 // Now we have our 32-bit value zero extended in the low element of
6895 // a vector. If Idx != 0, swizzle it into place.
6896 if (Idx != 0) {
6897 SmallVector<int, 4> Mask;
6898 Mask.push_back(Idx);
6899 for (unsigned i = 1; i != VecElts; ++i)
6900 Mask.push_back(i);
6901 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6902 &Mask[0]);
6903 }
6904 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6905 }
6906 }
6908 // If we have a constant or non-constant insertion into the low element of
6909 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6910 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6911 // depending on what the source datatype is.
6912 if (Idx == 0) {
6913 if (NumZero == 0)
6914 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6916 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6917 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6918 if (VT.is256BitVector() || VT.is512BitVector()) {
6919 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6920 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6921 Item, DAG.getIntPtrConstant(0));
6922 }
6923 assert(VT.is128BitVector() && "Expected an SSE value type!");
6924 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6925 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6926 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6927 }
6929 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6930 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6931 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6932 if (VT.is256BitVector()) {
6933 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6934 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6935 } else {
6936 assert(VT.is128BitVector() && "Expected an SSE value type!");
6937 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6938 }
6939 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6940 }
6941 }
6943 // Is it a vector logical left shift?
6944 if (NumElems == 2 && Idx == 1 &&
6945 X86::isZeroNode(Op.getOperand(0)) &&
6946 !X86::isZeroNode(Op.getOperand(1))) {
6947 unsigned NumBits = VT.getSizeInBits();
6948 return getVShift(true, VT,
6949 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6950 VT, Op.getOperand(1)),
6951 NumBits/2, DAG, *this, dl);
6952 }
6954 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6955 return SDValue();
6957 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6958 // is a non-constant being inserted into an element other than the low one,
6959 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6960 // movd/movss) to move this into the low element, then shuffle it into
6961 // place.
6962 if (EVTBits == 32) {
6963 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6965 // If using the new shuffle lowering, just directly insert this.
6966 if (ExperimentalVectorShuffleLowering)
6967 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6969 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6970 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6971 SmallVector<int, 8> MaskVec;
6972 for (unsigned i = 0; i != NumElems; ++i)
6973 MaskVec.push_back(i == Idx ? 0 : 1);
6974 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6975 }
6976 }
6978 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6979 if (Values.size() == 1) {
6980 if (EVTBits == 32) {
6981 // Instead of a shuffle like this:
6982 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6983 // Check if it's possible to issue this instead.
6984 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6985 unsigned Idx = countTrailingZeros(NonZeros);
6986 SDValue Item = Op.getOperand(Idx);
6987 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6988 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6989 }
6990 return SDValue();
6991 }
6993 // A vector full of immediates; various special cases are already
6994 // handled, so this is best done with a single constant-pool load.
6995 if (IsAllConstants)
6996 return SDValue();
6998 // For AVX-length vectors, build the individual 128-bit pieces and use
6999 // shuffles to put them in place.
7000 if (VT.is256BitVector() || VT.is512BitVector()) {
7001 SmallVector<SDValue, 64> V;
7002 for (unsigned i = 0; i != NumElems; ++i)
7003 V.push_back(Op.getOperand(i));
7005 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
7007 // Build both the lower and upper subvector.
7008 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
7009 makeArrayRef(&V[0], NumElems/2));
7010 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
7011 makeArrayRef(&V[NumElems / 2], NumElems/2));
7013 // Recreate the wider vector with the lower and upper part.
7014 if (VT.is256BitVector())
7015 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7016 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7017 }
7019 // Let legalizer expand 2-wide build_vectors.
7020 if (EVTBits == 64) {
7021 if (NumNonZero == 1) {
7022 // One half is zero or undef.
7023 unsigned Idx = countTrailingZeros(NonZeros);
7024 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
7025 Op.getOperand(Idx));
7026 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
7027 }
7028 return SDValue();
7029 }
7031 // If element VT is < 32 bits, convert it to inserts into a zero vector.
7032 if (EVTBits == 8 && NumElems == 16) {
7033 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
7034 Subtarget, *this);
7035 if (V.getNode()) return V;
7036 }
7038 if (EVTBits == 16 && NumElems == 8) {
7039 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
7040 Subtarget, *this);
7041 if (V.getNode()) return V;
7042 }
7044 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
7045 if (EVTBits == 32 && NumElems == 4) {
7046 SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this);
7047 if (V.getNode())
7048 return V;
7049 }
7051 // If element VT is == 32 bits, turn it into a number of shuffles.
7052 SmallVector<SDValue, 8> V(NumElems);
7053 if (NumElems == 4 && NumZero > 0) {
7054 for (unsigned i = 0; i < 4; ++i) {
7055 bool isZero = !(NonZeros & (1 << i));
7056 if (isZero)
7057 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7058 else
7059 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7060 }
7062 for (unsigned i = 0; i < 2; ++i) {
7063 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7064 default: break;
7065 case 0:
7066 V[i] = V[i*2]; // Must be a zero vector.
7067 break;
7068 case 1:
7069 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7070 break;
7071 case 2:
7072 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7073 break;
7074 case 3:
7075 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7076 break;
7077 }
7078 }
7080 bool Reverse1 = (NonZeros & 0x3) == 2;
7081 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7082 int MaskVec[] = {
7083 Reverse1 ? 1 : 0,
7084 Reverse1 ? 0 : 1,
7085 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7086 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7087 };
7088 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7089 }
7091 if (Values.size() > 1 && VT.is128BitVector()) {
7092 // Check for a build vector of consecutive loads.
7093 for (unsigned i = 0; i < NumElems; ++i)
7094 V[i] = Op.getOperand(i);
7096 // Check for elements which are consecutive loads.
7097 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7098 if (LD.getNode())
7099 return LD;
7101 // Check for a build vector from mostly shuffle plus few inserting.
7102 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7103 if (Sh.getNode())
7104 return Sh;
7106 // For SSE 4.1, use insertps to put the high elements into the low element.
7107 if (getSubtarget()->hasSSE41()) {
7108 SDValue Result;
7109 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7110 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7111 else
7112 Result = DAG.getUNDEF(VT);
7114 for (unsigned i = 1; i < NumElems; ++i) {
7115 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7116 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7117 Op.getOperand(i), DAG.getIntPtrConstant(i));
7118 }
7119 return Result;
7120 }
7122 // Otherwise, expand into a number of unpckl*, start by extending each of
7123 // our (non-undef) elements to the full vector width with the element in the
7124 // bottom slot of the vector (which generates no code for SSE).
7125 for (unsigned i = 0; i < NumElems; ++i) {
7126 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7127 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7128 else
7129 V[i] = DAG.getUNDEF(VT);
7130 }
7132 // Next, we iteratively mix elements, e.g. for v4f32:
7133 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7134 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7135 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7136 unsigned EltStride = NumElems >> 1;
7137 while (EltStride != 0) {
7138 for (unsigned i = 0; i < EltStride; ++i) {
7139 // If V[i+EltStride] is undef and this is the first round of mixing,
7140 // then it is safe to just drop this shuffle: V[i] is already in the
7141 // right place, the one element (since it's the first round) being
7142 // inserted as undef can be dropped. This isn't safe for successive
7143 // rounds because they will permute elements within both vectors.
7144 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7145 EltStride == NumElems/2)
7146 continue;
7148 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7149 }
7150 EltStride >>= 1;
7151 }
7152 return V[0];
7153 }
7154 return SDValue();
7155 }
7157 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7158 // to create 256-bit vectors from two other 128-bit ones.
7159 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7160 SDLoc dl(Op);
7161 MVT ResVT = Op.getSimpleValueType();
7163 assert((ResVT.is256BitVector() ||
7164 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7166 SDValue V1 = Op.getOperand(0);
7167 SDValue V2 = Op.getOperand(1);
7168 unsigned NumElems = ResVT.getVectorNumElements();
7169 if(ResVT.is256BitVector())
7170 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7172 if (Op.getNumOperands() == 4) {
7173 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7174 ResVT.getVectorNumElements()/2);
7175 SDValue V3 = Op.getOperand(2);
7176 SDValue V4 = Op.getOperand(3);
7177 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7178 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7179 }
7180 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7181 }
7183 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7184 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7185 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7186 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7187 Op.getNumOperands() == 4)));
7189 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7190 // from two other 128-bit ones.
7192 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7193 return LowerAVXCONCAT_VECTORS(Op, DAG);
7194 }
7197 //===----------------------------------------------------------------------===//
7198 // Vector shuffle lowering
7199 //
7200 // This is an experimental code path for lowering vector shuffles on x86. It is
7201 // designed to handle arbitrary vector shuffles and blends, gracefully
7202 // degrading performance as necessary. It works hard to recognize idiomatic
7203 // shuffles and lower them to optimal instruction patterns without leaving
7204 // a framework that allows reasonably efficient handling of all vector shuffle
7205 // patterns.
7206 //===----------------------------------------------------------------------===//
7208 /// \brief Tiny helper function to identify a no-op mask.
7209 ///
7210 /// This is a somewhat boring predicate function. It checks whether the mask
7211 /// array input, which is assumed to be a single-input shuffle mask of the kind
7212 /// used by the X86 shuffle instructions (not a fully general
7213 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7214 /// in-place shuffle are 'no-op's.
7215 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7216 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7217 if (Mask[i] != -1 && Mask[i] != i)
7218 return false;
7219 return true;
7220 }
7222 /// \brief Helper function to classify a mask as a single-input mask.
7223 ///
7224 /// This isn't a generic single-input test because in the vector shuffle
7225 /// lowering we canonicalize single inputs to be the first input operand. This
7226 /// means we can more quickly test for a single input by only checking whether
7227 /// an input from the second operand exists. We also assume that the size of
7228 /// mask corresponds to the size of the input vectors which isn't true in the
7229 /// fully general case.
7230 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7231 for (int M : Mask)
7232 if (M >= (int)Mask.size())
7233 return false;
7234 return true;
7235 }
7237 /// \brief Test whether there are elements crossing 128-bit lanes in this
7238 /// shuffle mask.
7239 ///
7240 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7241 /// and we routinely test for these.
7242 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7243 int LaneSize = 128 / VT.getScalarSizeInBits();
7244 int Size = Mask.size();
7245 for (int i = 0; i < Size; ++i)
7246 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7247 return true;
7248 return false;
7249 }
7251 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7252 ///
7253 /// This checks a shuffle mask to see if it is performing the same
7254 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7255 /// that it is also not lane-crossing. It may however involve a blend from the
7256 /// same lane of a second vector.
7257 ///
7258 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7259 /// non-trivial to compute in the face of undef lanes. The representation is
7260 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7261 /// entries from both V1 and V2 inputs to the wider mask.
7262 static bool
7263 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7264 SmallVectorImpl<int> &RepeatedMask) {
7265 int LaneSize = 128 / VT.getScalarSizeInBits();
7266 RepeatedMask.resize(LaneSize, -1);
7267 int Size = Mask.size();
7268 for (int i = 0; i < Size; ++i) {
7269 if (Mask[i] < 0)
7270 continue;
7271 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7272 // This entry crosses lanes, so there is no way to model this shuffle.
7273 return false;
7275 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7276 if (RepeatedMask[i % LaneSize] == -1)
7277 // This is the first non-undef entry in this slot of a 128-bit lane.
7278 RepeatedMask[i % LaneSize] =
7279 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7280 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7281 // Found a mismatch with the repeated mask.
7282 return false;
7283 }
7284 return true;
7285 }
7287 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7288 // 2013 will allow us to use it as a non-type template parameter.
7289 namespace {
7291 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7292 ///
7293 /// See its documentation for details.
7294 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7295 if (Mask.size() != Args.size())
7296 return false;
7297 for (int i = 0, e = Mask.size(); i < e; ++i) {
7298 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7299 if (Mask[i] != -1 && Mask[i] != *Args[i])
7300 return false;
7301 }
7302 return true;
7303 }
7305 } // namespace
7307 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7308 /// arguments.
7309 ///
7310 /// This is a fast way to test a shuffle mask against a fixed pattern:
7311 ///
7312 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7313 ///
7314 /// It returns true if the mask is exactly as wide as the argument list, and
7315 /// each element of the mask is either -1 (signifying undef) or the value given
7316 /// in the argument.
7317 static const VariadicFunction1<
7318 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7320 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7321 ///
7322 /// This helper function produces an 8-bit shuffle immediate corresponding to
7323 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7324 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7325 /// example.
7326 ///
7327 /// NB: We rely heavily on "undef" masks preserving the input lane.
7328 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7329 SelectionDAG &DAG) {
7330 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7331 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7332 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7333 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7334 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7336 unsigned Imm = 0;
7337 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7338 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7339 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7340 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7341 return DAG.getConstant(Imm, MVT::i8);
7342 }
7344 /// \brief Try to emit a blend instruction for a shuffle.
7345 ///
7346 /// This doesn't do any checks for the availability of instructions for blending
7347 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7348 /// be matched in the backend with the type given. What it does check for is
7349 /// that the shuffle mask is in fact a blend.
7350 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7351 SDValue V2, ArrayRef<int> Mask,
7352 const X86Subtarget *Subtarget,
7353 SelectionDAG &DAG) {
7355 unsigned BlendMask = 0;
7356 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7357 if (Mask[i] >= Size) {
7358 if (Mask[i] != i + Size)
7359 return SDValue(); // Shuffled V2 input!
7360 BlendMask |= 1u << i;
7361 continue;
7362 }
7363 if (Mask[i] >= 0 && Mask[i] != i)
7364 return SDValue(); // Shuffled V1 input!
7365 }
7366 switch (VT.SimpleTy) {
7367 case MVT::v2f64:
7368 case MVT::v4f32:
7369 case MVT::v4f64:
7370 case MVT::v8f32:
7371 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7372 DAG.getConstant(BlendMask, MVT::i8));
7374 case MVT::v4i64:
7375 case MVT::v8i32:
7376 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7377 // FALLTHROUGH
7378 case MVT::v2i64:
7379 case MVT::v4i32:
7380 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7381 // that instruction.
7382 if (Subtarget->hasAVX2()) {
7383 // Scale the blend by the number of 32-bit dwords per element.
7384 int Scale = VT.getScalarSizeInBits() / 32;
7385 BlendMask = 0;
7386 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7387 if (Mask[i] >= Size)
7388 for (int j = 0; j < Scale; ++j)
7389 BlendMask |= 1u << (i * Scale + j);
7391 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7392 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7393 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7394 return DAG.getNode(ISD::BITCAST, DL, VT,
7395 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7396 DAG.getConstant(BlendMask, MVT::i8)));
7397 }
7398 // FALLTHROUGH
7399 case MVT::v8i16: {
7400 // For integer shuffles we need to expand the mask and cast the inputs to
7401 // v8i16s prior to blending.
7402 int Scale = 8 / VT.getVectorNumElements();
7403 BlendMask = 0;
7404 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7405 if (Mask[i] >= Size)
7406 for (int j = 0; j < Scale; ++j)
7407 BlendMask |= 1u << (i * Scale + j);
7409 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7410 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7411 return DAG.getNode(ISD::BITCAST, DL, VT,
7412 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7413 DAG.getConstant(BlendMask, MVT::i8)));
7414 }
7416 case MVT::v16i16: {
7417 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7418 SmallVector<int, 8> RepeatedMask;
7419 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7420 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7421 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7422 BlendMask = 0;
7423 for (int i = 0; i < 8; ++i)
7424 if (RepeatedMask[i] >= 16)
7425 BlendMask |= 1u << i;
7426 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7427 DAG.getConstant(BlendMask, MVT::i8));
7428 }
7429 }
7430 // FALLTHROUGH
7431 case MVT::v32i8: {
7432 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7433 // Scale the blend by the number of bytes per element.
7434 int Scale = VT.getScalarSizeInBits() / 8;
7435 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7437 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7438 // mix of LLVM's code generator and the x86 backend. We tell the code
7439 // generator that boolean values in the elements of an x86 vector register
7440 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7441 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7442 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7443 // of the element (the remaining are ignored) and 0 in that high bit would
7444 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7445 // the LLVM model for boolean values in vector elements gets the relevant
7446 // bit set, it is set backwards and over constrained relative to x86's
7447 // actual model.
7448 SDValue VSELECTMask[32];
7449 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7450 for (int j = 0; j < Scale; ++j)
7451 VSELECTMask[Scale * i + j] =
7452 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7453 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8);
7455 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7456 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7457 return DAG.getNode(
7458 ISD::BITCAST, DL, VT,
7459 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8,
7460 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, VSELECTMask),
7461 V1, V2));
7462 }
7464 default:
7465 llvm_unreachable("Not a supported integer vector type!");
7466 }
7467 }
7469 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7470 /// unblended shuffles followed by an unshuffled blend.
7471 ///
7472 /// This matches the extremely common pattern for handling combined
7473 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7474 /// operations.
7475 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7476 SDValue V1,
7477 SDValue V2,
7478 ArrayRef<int> Mask,
7479 SelectionDAG &DAG) {
7480 // Shuffle the input elements into the desired positions in V1 and V2 and
7481 // blend them together.
7482 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7483 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7484 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7485 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7486 if (Mask[i] >= 0 && Mask[i] < Size) {
7487 V1Mask[i] = Mask[i];
7488 BlendMask[i] = i;
7489 } else if (Mask[i] >= Size) {
7490 V2Mask[i] = Mask[i] - Size;
7491 BlendMask[i] = i + Size;
7492 }
7494 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7495 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7496 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7497 }
7499 /// \brief Try to lower a vector shuffle as a byte rotation.
7500 ///
7501 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7502 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7503 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7504 /// try to generically lower a vector shuffle through such an pattern. It
7505 /// does not check for the profitability of lowering either as PALIGNR or
7506 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7507 /// This matches shuffle vectors that look like:
7508 ///
7509 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7510 ///
7511 /// Essentially it concatenates V1 and V2, shifts right by some number of
7512 /// elements, and takes the low elements as the result. Note that while this is
7513 /// specified as a *right shift* because x86 is little-endian, it is a *left
7514 /// rotate* of the vector lanes.
7515 ///
7516 /// Note that this only handles 128-bit vector widths currently.
7517 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7518 SDValue V2,
7519 ArrayRef<int> Mask,
7520 const X86Subtarget *Subtarget,
7521 SelectionDAG &DAG) {
7522 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7524 // We need to detect various ways of spelling a rotation:
7525 // [11, 12, 13, 14, 15, 0, 1, 2]
7526 // [-1, 12, 13, 14, -1, -1, 1, -1]
7527 // [-1, -1, -1, -1, -1, -1, 1, 2]
7528 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7529 // [-1, 4, 5, 6, -1, -1, 9, -1]
7530 // [-1, 4, 5, 6, -1, -1, -1, -1]
7531 int Rotation = 0;
7532 SDValue Lo, Hi;
7533 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7534 if (Mask[i] == -1)
7535 continue;
7536 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7538 // Based on the mod-Size value of this mask element determine where
7539 // a rotated vector would have started.
7540 int StartIdx = i - (Mask[i] % Size);
7541 if (StartIdx == 0)
7542 // The identity rotation isn't interesting, stop.
7543 return SDValue();
7545 // If we found the tail of a vector the rotation must be the missing
7546 // front. If we found the head of a vector, it must be how much of the head.
7547 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7549 if (Rotation == 0)
7550 Rotation = CandidateRotation;
7551 else if (Rotation != CandidateRotation)
7552 // The rotations don't match, so we can't match this mask.
7553 return SDValue();
7555 // Compute which value this mask is pointing at.
7556 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7558 // Compute which of the two target values this index should be assigned to.
7559 // This reflects whether the high elements are remaining or the low elements
7560 // are remaining.
7561 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7563 // Either set up this value if we've not encountered it before, or check
7564 // that it remains consistent.
7565 if (!TargetV)
7566 TargetV = MaskV;
7567 else if (TargetV != MaskV)
7568 // This may be a rotation, but it pulls from the inputs in some
7569 // unsupported interleaving.
7570 return SDValue();
7571 }
7573 // Check that we successfully analyzed the mask, and normalize the results.
7574 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7575 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7576 if (!Lo)
7577 Lo = Hi;
7578 else if (!Hi)
7579 Hi = Lo;
7581 assert(VT.getSizeInBits() == 128 &&
7582 "Rotate-based lowering only supports 128-bit lowering!");
7583 assert(Mask.size() <= 16 &&
7584 "Can shuffle at most 16 bytes in a 128-bit vector!");
7586 // The actual rotate instruction rotates bytes, so we need to scale the
7587 // rotation based on how many bytes are in the vector.
7588 int Scale = 16 / Mask.size();
7590 // SSSE3 targets can use the palignr instruction
7591 if (Subtarget->hasSSSE3()) {
7592 // Cast the inputs to v16i8 to match PALIGNR.
7593 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7594 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7596 return DAG.getNode(ISD::BITCAST, DL, VT,
7597 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7598 DAG.getConstant(Rotation * Scale, MVT::i8)));
7599 }
7601 // Default SSE2 implementation
7602 int LoByteShift = 16 - Rotation * Scale;
7603 int HiByteShift = Rotation * Scale;
7605 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7606 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Lo);
7607 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Hi);
7609 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7610 DAG.getConstant(8 * LoByteShift, MVT::i8));
7611 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7612 DAG.getConstant(8 * HiByteShift, MVT::i8));
7613 return DAG.getNode(ISD::BITCAST, DL, VT,
7614 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7615 }
7617 /// \brief Compute whether each element of a shuffle is zeroable.
7618 ///
7619 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7620 /// Either it is an undef element in the shuffle mask, the element of the input
7621 /// referenced is undef, or the element of the input referenced is known to be
7622 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7623 /// as many lanes with this technique as possible to simplify the remaining
7624 /// shuffle.
7625 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7626 SDValue V1, SDValue V2) {
7627 SmallBitVector Zeroable(Mask.size(), false);
7629 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7630 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7632 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7633 int M = Mask[i];
7634 // Handle the easy cases.
7635 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7636 Zeroable[i] = true;
7637 continue;
7638 }
7640 // If this is an index into a build_vector node, dig out the input value and
7641 // use it.
7642 SDValue V = M < Size ? V1 : V2;
7643 if (V.getOpcode() != ISD::BUILD_VECTOR)
7644 continue;
7646 SDValue Input = V.getOperand(M % Size);
7647 // The UNDEF opcode check really should be dead code here, but not quite
7648 // worth asserting on (it isn't invalid, just unexpected).
7649 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7650 Zeroable[i] = true;
7651 }
7653 return Zeroable;
7654 }
7656 /// \brief Try to lower a vector shuffle as a byte shift (shifts in zeros).
7657 ///
7658 /// Attempts to match a shuffle mask against the PSRLDQ and PSLLDQ SSE2
7659 /// byte-shift instructions. The mask must consist of a shifted sequential
7660 /// shuffle from one of the input vectors and zeroable elements for the
7661 /// remaining 'shifted in' elements.
7662 ///
7663 /// Note that this only handles 128-bit vector widths currently.
7664 static SDValue lowerVectorShuffleAsByteShift(SDLoc DL, MVT VT, SDValue V1,
7665 SDValue V2, ArrayRef<int> Mask,
7666 SelectionDAG &DAG) {
7667 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7669 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7671 int Size = Mask.size();
7672 int Scale = 16 / Size;
7674 auto isSequential = [](int Base, int StartIndex, int EndIndex, int MaskOffset,
7675 ArrayRef<int> Mask) {
7676 for (int i = StartIndex; i < EndIndex; i++) {
7677 if (Mask[i] < 0)
7678 continue;
7679 if (i + Base != Mask[i] - MaskOffset)
7680 return false;
7681 }
7682 return true;
7683 };
7685 for (int Shift = 1; Shift < Size; Shift++) {
7686 int ByteShift = Shift * Scale;
7688 // PSRLDQ : (little-endian) right byte shift
7689 // [ 5, 6, 7, zz, zz, zz, zz, zz]
7690 // [ -1, 5, 6, 7, zz, zz, zz, zz]
7691 // [ 1, 2, -1, -1, -1, -1, zz, zz]
7692 bool ZeroableRight = true;
7693 for (int i = Size - Shift; i < Size; i++) {
7694 ZeroableRight &= Zeroable[i];
7695 }
7697 if (ZeroableRight) {
7698 bool ValidShiftRight1 = isSequential(Shift, 0, Size - Shift, 0, Mask);
7699 bool ValidShiftRight2 = isSequential(Shift, 0, Size - Shift, Size, Mask);
7701 if (ValidShiftRight1 || ValidShiftRight2) {
7702 // Cast the inputs to v2i64 to match PSRLDQ.
7703 SDValue &TargetV = ValidShiftRight1 ? V1 : V2;
7704 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7705 SDValue Shifted = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, V,
7706 DAG.getConstant(ByteShift * 8, MVT::i8));
7707 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7708 }
7709 }
7711 // PSLLDQ : (little-endian) left byte shift
7712 // [ zz, 0, 1, 2, 3, 4, 5, 6]
7713 // [ zz, zz, -1, -1, 2, 3, 4, -1]
7714 // [ zz, zz, zz, zz, zz, zz, -1, 1]
7715 bool ZeroableLeft = true;
7716 for (int i = 0; i < Shift; i++) {
7717 ZeroableLeft &= Zeroable[i];
7718 }
7720 if (ZeroableLeft) {
7721 bool ValidShiftLeft1 = isSequential(-Shift, Shift, Size, 0, Mask);
7722 bool ValidShiftLeft2 = isSequential(-Shift, Shift, Size, Size, Mask);
7724 if (ValidShiftLeft1 || ValidShiftLeft2) {
7725 // Cast the inputs to v2i64 to match PSLLDQ.
7726 SDValue &TargetV = ValidShiftLeft1 ? V1 : V2;
7727 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7728 SDValue Shifted = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, V,
7729 DAG.getConstant(ByteShift * 8, MVT::i8));
7730 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7731 }
7732 }
7733 }
7735 return SDValue();
7736 }
7738 /// \brief Lower a vector shuffle as a zero or any extension.
7739 ///
7740 /// Given a specific number of elements, element bit width, and extension
7741 /// stride, produce either a zero or any extension based on the available
7742 /// features of the subtarget.
7743 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7744 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7745 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7746 assert(Scale > 1 && "Need a scale to extend.");
7747 int EltBits = VT.getSizeInBits() / NumElements;
7748 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7749 "Only 8, 16, and 32 bit elements can be extended.");
7750 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7752 // Found a valid zext mask! Try various lowering strategies based on the
7753 // input type and available ISA extensions.
7754 if (Subtarget->hasSSE41()) {
7755 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7756 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7757 NumElements / Scale);
7758 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7759 return DAG.getNode(ISD::BITCAST, DL, VT,
7760 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7761 }
7763 // For any extends we can cheat for larger element sizes and use shuffle
7764 // instructions that can fold with a load and/or copy.
7765 if (AnyExt && EltBits == 32) {
7766 int PSHUFDMask[4] = {0, -1, 1, -1};
7767 return DAG.getNode(
7768 ISD::BITCAST, DL, VT,
7769 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7770 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7771 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7772 }
7773 if (AnyExt && EltBits == 16 && Scale > 2) {
7774 int PSHUFDMask[4] = {0, -1, 0, -1};
7775 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7776 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7777 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7778 int PSHUFHWMask[4] = {1, -1, -1, -1};
7779 return DAG.getNode(
7780 ISD::BITCAST, DL, VT,
7781 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7782 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7783 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7784 }
7786 // If this would require more than 2 unpack instructions to expand, use
7787 // pshufb when available. We can only use more than 2 unpack instructions
7788 // when zero extending i8 elements which also makes it easier to use pshufb.
7789 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7790 assert(NumElements == 16 && "Unexpected byte vector width!");
7791 SDValue PSHUFBMask[16];
7792 for (int i = 0; i < 16; ++i)
7793 PSHUFBMask[i] =
7794 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7795 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7796 return DAG.getNode(ISD::BITCAST, DL, VT,
7797 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7798 DAG.getNode(ISD::BUILD_VECTOR, DL,
7799 MVT::v16i8, PSHUFBMask)));
7800 }
7802 // Otherwise emit a sequence of unpacks.
7803 do {
7804 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7805 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7806 : getZeroVector(InputVT, Subtarget, DAG, DL);
7807 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7808 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7809 Scale /= 2;
7810 EltBits *= 2;
7811 NumElements /= 2;
7812 } while (Scale > 1);
7813 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7814 }
7816 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7817 ///
7818 /// This routine will try to do everything in its power to cleverly lower
7819 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7820 /// check for the profitability of this lowering, it tries to aggressively
7821 /// match this pattern. It will use all of the micro-architectural details it
7822 /// can to emit an efficient lowering. It handles both blends with all-zero
7823 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7824 /// masking out later).
7825 ///
7826 /// The reason we have dedicated lowering for zext-style shuffles is that they
7827 /// are both incredibly common and often quite performance sensitive.
7828 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7829 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7830 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7831 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7833 int Bits = VT.getSizeInBits();
7834 int NumElements = Mask.size();
7836 // Define a helper function to check a particular ext-scale and lower to it if
7837 // valid.
7838 auto Lower = [&](int Scale) -> SDValue {
7839 SDValue InputV;
7840 bool AnyExt = true;
7841 for (int i = 0; i < NumElements; ++i) {
7842 if (Mask[i] == -1)
7843 continue; // Valid anywhere but doesn't tell us anything.
7844 if (i % Scale != 0) {
7845 // Each of the extend elements needs to be zeroable.
7846 if (!Zeroable[i])
7847 return SDValue();
7849 // We no lorger are in the anyext case.
7850 AnyExt = false;
7851 continue;
7852 }
7854 // Each of the base elements needs to be consecutive indices into the
7855 // same input vector.
7856 SDValue V = Mask[i] < NumElements ? V1 : V2;
7857 if (!InputV)
7858 InputV = V;
7859 else if (InputV != V)
7860 return SDValue(); // Flip-flopping inputs.
7862 if (Mask[i] % NumElements != i / Scale)
7863 return SDValue(); // Non-consecutive strided elemenst.
7864 }
7866 // If we fail to find an input, we have a zero-shuffle which should always
7867 // have already been handled.
7868 // FIXME: Maybe handle this here in case during blending we end up with one?
7869 if (!InputV)
7870 return SDValue();
7872 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7873 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7874 };
7876 // The widest scale possible for extending is to a 64-bit integer.
7877 assert(Bits % 64 == 0 &&
7878 "The number of bits in a vector must be divisible by 64 on x86!");
7879 int NumExtElements = Bits / 64;
7881 // Each iteration, try extending the elements half as much, but into twice as
7882 // many elements.
7883 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7884 assert(NumElements % NumExtElements == 0 &&
7885 "The input vector size must be divisble by the extended size.");
7886 if (SDValue V = Lower(NumElements / NumExtElements))
7887 return V;
7888 }
7890 // No viable ext lowering found.
7891 return SDValue();
7892 }
7894 /// \brief Try to get a scalar value for a specific element of a vector.
7895 ///
7896 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7897 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7898 SelectionDAG &DAG) {
7899 MVT VT = V.getSimpleValueType();
7900 MVT EltVT = VT.getVectorElementType();
7901 while (V.getOpcode() == ISD::BITCAST)
7902 V = V.getOperand(0);
7903 // If the bitcasts shift the element size, we can't extract an equivalent
7904 // element from it.
7905 MVT NewVT = V.getSimpleValueType();
7906 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7907 return SDValue();
7909 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7910 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR))
7911 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, V.getOperand(Idx));
7913 return SDValue();
7914 }
7916 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7917 ///
7918 /// This is particularly important because the set of instructions varies
7919 /// significantly based on whether the operand is a load or not.
7920 static bool isShuffleFoldableLoad(SDValue V) {
7921 while (V.getOpcode() == ISD::BITCAST)
7922 V = V.getOperand(0);
7924 return ISD::isNON_EXTLoad(V.getNode());
7925 }
7927 /// \brief Try to lower insertion of a single element into a zero vector.
7928 ///
7929 /// This is a common pattern that we have especially efficient patterns to lower
7930 /// across all subtarget feature sets.
7931 static SDValue lowerVectorShuffleAsElementInsertion(
7932 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7933 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7934 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7935 MVT ExtVT = VT;
7936 MVT EltVT = VT.getVectorElementType();
7938 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7939 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7940 Mask.begin();
7941 bool IsV1Zeroable = true;
7942 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7943 if (i != V2Index && !Zeroable[i]) {
7944 IsV1Zeroable = false;
7945 break;
7946 }
7948 // Check for a single input from a SCALAR_TO_VECTOR node.
7949 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7950 // all the smarts here sunk into that routine. However, the current
7951 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7952 // vector shuffle lowering is dead.
7953 if (SDValue V2S = getScalarValueForVectorElement(
7954 V2, Mask[V2Index] - Mask.size(), DAG)) {
7955 // We need to zext the scalar if it is smaller than an i32.
7956 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7957 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7958 // Using zext to expand a narrow element won't work for non-zero
7959 // insertions.
7960 if (!IsV1Zeroable)
7961 return SDValue();
7963 // Zero-extend directly to i32.
7964 ExtVT = MVT::v4i32;
7965 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7966 }
7967 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7968 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7969 EltVT == MVT::i16) {
7970 // Either not inserting from the low element of the input or the input
7971 // element size is too small to use VZEXT_MOVL to clear the high bits.
7972 return SDValue();
7973 }
7975 if (!IsV1Zeroable) {
7976 // If V1 can't be treated as a zero vector we have fewer options to lower
7977 // this. We can't support integer vectors or non-zero targets cheaply, and
7978 // the V1 elements can't be permuted in any way.
7979 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7980 if (!VT.isFloatingPoint() || V2Index != 0)
7981 return SDValue();
7982 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7983 V1Mask[V2Index] = -1;
7984 if (!isNoopShuffleMask(V1Mask))
7985 return SDValue();
7986 // This is essentially a special case blend operation, but if we have
7987 // general purpose blend operations, they are always faster. Bail and let
7988 // the rest of the lowering handle these as blends.
7989 if (Subtarget->hasSSE41())
7990 return SDValue();
7992 // Otherwise, use MOVSD or MOVSS.
7993 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7994 "Only two types of floating point element types to handle!");
7995 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7996 ExtVT, V1, V2);
7997 }
7999 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
8000 if (ExtVT != VT)
8001 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
8003 if (V2Index != 0) {
8004 // If we have 4 or fewer lanes we can cheaply shuffle the element into
8005 // the desired position. Otherwise it is more efficient to do a vector
8006 // shift left. We know that we can do a vector shift left because all
8007 // the inputs are zero.
8008 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
8009 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
8010 V2Shuffle[V2Index] = 0;
8011 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
8012 } else {
8013 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
8014 V2 = DAG.getNode(
8015 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
8016 DAG.getConstant(
8017 V2Index * EltVT.getSizeInBits(),
8018 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
8019 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
8020 }
8021 }
8022 return V2;
8023 }
8025 /// \brief Try to lower broadcast of a single element.
8026 ///
8027 /// For convenience, this code also bundles all of the subtarget feature set
8028 /// filtering. While a little annoying to re-dispatch on type here, there isn't
8029 /// a convenient way to factor it out.
8030 static SDValue lowerVectorShuffleAsBroadcast(MVT VT, SDLoc DL, SDValue V,
8031 ArrayRef<int> Mask,
8032 const X86Subtarget *Subtarget,
8033 SelectionDAG &DAG) {
8034 if (!Subtarget->hasAVX())
8035 return SDValue();
8036 if (VT.isInteger() && !Subtarget->hasAVX2())
8037 return SDValue();
8039 // Check that the mask is a broadcast.
8040 int BroadcastIdx = -1;
8041 for (int M : Mask)
8042 if (M >= 0 && BroadcastIdx == -1)
8043 BroadcastIdx = M;
8044 else if (M >= 0 && M != BroadcastIdx)
8045 return SDValue();
8047 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
8048 "a sorted mask where the broadcast "
8049 "comes from V1.");
8051 // Go up the chain of (vector) values to try and find a scalar load that
8052 // we can combine with the broadcast.
8053 for (;;) {
8054 switch (V.getOpcode()) {
8055 case ISD::CONCAT_VECTORS: {
8056 int OperandSize = Mask.size() / V.getNumOperands();
8057 V = V.getOperand(BroadcastIdx / OperandSize);
8058 BroadcastIdx %= OperandSize;
8059 continue;
8060 }
8062 case ISD::INSERT_SUBVECTOR: {
8063 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
8064 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
8065 if (!ConstantIdx)
8066 break;
8068 int BeginIdx = (int)ConstantIdx->getZExtValue();
8069 int EndIdx =
8070 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
8071 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
8072 BroadcastIdx -= BeginIdx;
8073 V = VInner;
8074 } else {
8075 V = VOuter;
8076 }
8077 continue;
8078 }
8079 }
8080 break;
8081 }
8083 // Check if this is a broadcast of a scalar. We special case lowering
8084 // for scalars so that we can more effectively fold with loads.
8085 if (V.getOpcode() == ISD::BUILD_VECTOR ||
8086 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
8087 V = V.getOperand(BroadcastIdx);
8089 // If the scalar isn't a load we can't broadcast from it in AVX1, only with
8090 // AVX2.
8091 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
8092 return SDValue();
8093 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
8094 // We can't broadcast from a vector register w/o AVX2, and we can only
8095 // broadcast from the zero-element of a vector register.
8096 return SDValue();
8097 }
8099 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
8100 }
8102 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8103 ///
8104 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8105 /// support for floating point shuffles but not integer shuffles. These
8106 /// instructions will incur a domain crossing penalty on some chips though so
8107 /// it is better to avoid lowering through this for integer vectors where
8108 /// possible.
8109 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8110 const X86Subtarget *Subtarget,
8111 SelectionDAG &DAG) {
8112 SDLoc DL(Op);
8113 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8114 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8115 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8116 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8117 ArrayRef<int> Mask = SVOp->getMask();
8118 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8120 if (isSingleInputShuffleMask(Mask)) {
8121 // Straight shuffle of a single input vector. Simulate this by using the
8122 // single input as both of the "inputs" to this instruction..
8123 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8125 if (Subtarget->hasAVX()) {
8126 // If we have AVX, we can use VPERMILPS which will allow folding a load
8127 // into the shuffle.
8128 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8129 DAG.getConstant(SHUFPDMask, MVT::i8));
8130 }
8132 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
8133 DAG.getConstant(SHUFPDMask, MVT::i8));
8134 }
8135 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8136 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8138 // Use dedicated unpack instructions for masks that match their pattern.
8139 if (isShuffleEquivalent(Mask, 0, 2))
8140 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
8141 if (isShuffleEquivalent(Mask, 1, 3))
8142 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
8144 // If we have a single input, insert that into V1 if we can do so cheaply.
8145 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8146 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8147 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
8148 return Insertion;
8149 // Try inverting the insertion since for v2 masks it is easy to do and we
8150 // can't reliably sort the mask one way or the other.
8151 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8152 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8153 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8154 MVT::v2f64, DL, V2, V1, InverseMask, Subtarget, DAG))
8155 return Insertion;
8156 }
8158 // Try to use one of the special instruction patterns to handle two common
8159 // blend patterns if a zero-blend above didn't work.
8160 if (isShuffleEquivalent(Mask, 0, 3) || isShuffleEquivalent(Mask, 1, 3))
8161 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8162 // We can either use a special instruction to load over the low double or
8163 // to move just the low double.
8164 return DAG.getNode(
8165 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8166 DL, MVT::v2f64, V2,
8167 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8169 if (Subtarget->hasSSE41())
8170 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8171 Subtarget, DAG))
8172 return Blend;
8174 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8175 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
8176 DAG.getConstant(SHUFPDMask, MVT::i8));
8177 }
8179 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8180 ///
8181 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8182 /// the integer unit to minimize domain crossing penalties. However, for blends
8183 /// it falls back to the floating point shuffle operation with appropriate bit
8184 /// casting.
8185 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8186 const X86Subtarget *Subtarget,
8187 SelectionDAG &DAG) {
8188 SDLoc DL(Op);
8189 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8190 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8191 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8192 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8193 ArrayRef<int> Mask = SVOp->getMask();
8194 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8196 if (isSingleInputShuffleMask(Mask)) {
8197 // Check for being able to broadcast a single element.
8198 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v2i64, DL, V1,
8199 Mask, Subtarget, DAG))
8200 return Broadcast;
8202 // Straight shuffle of a single input vector. For everything from SSE2
8203 // onward this has a single fast instruction with no scary immediates.
8204 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8205 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
8206 int WidenedMask[4] = {
8207 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8208 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8209 return DAG.getNode(
8210 ISD::BITCAST, DL, MVT::v2i64,
8211 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
8212 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
8213 }
8215 // Try to use byte shift instructions.
8216 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8217 DL, MVT::v2i64, V1, V2, Mask, DAG))
8218 return Shift;
8220 // If we have a single input from V2 insert that into V1 if we can do so
8221 // cheaply.
8222 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8223 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8224 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
8225 return Insertion;
8226 // Try inverting the insertion since for v2 masks it is easy to do and we
8227 // can't reliably sort the mask one way or the other.
8228 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8229 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8230 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8231 MVT::v2i64, DL, V2, V1, InverseMask, Subtarget, DAG))
8232 return Insertion;
8233 }
8235 // Use dedicated unpack instructions for masks that match their pattern.
8236 if (isShuffleEquivalent(Mask, 0, 2))
8237 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8238 if (isShuffleEquivalent(Mask, 1, 3))
8239 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8241 if (Subtarget->hasSSE41())
8242 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8243 Subtarget, DAG))
8244 return Blend;
8246 // Try to use byte rotation instructions.
8247 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8248 if (Subtarget->hasSSSE3())
8249 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8250 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8251 return Rotate;
8253 // We implement this with SHUFPD which is pretty lame because it will likely
8254 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8255 // However, all the alternatives are still more cycles and newer chips don't
8256 // have this problem. It would be really nice if x86 had better shuffles here.
8257 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
8258 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
8259 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
8260 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8261 }
8263 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8264 ///
8265 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8266 /// It makes no assumptions about whether this is the *best* lowering, it simply
8267 /// uses it.
8268 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8269 ArrayRef<int> Mask, SDValue V1,
8270 SDValue V2, SelectionDAG &DAG) {
8271 SDValue LowV = V1, HighV = V2;
8272 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8274 int NumV2Elements =
8275 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8277 if (NumV2Elements == 1) {
8278 int V2Index =
8279 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8280 Mask.begin();
8282 // Compute the index adjacent to V2Index and in the same half by toggling
8283 // the low bit.
8284 int V2AdjIndex = V2Index ^ 1;
8286 if (Mask[V2AdjIndex] == -1) {
8287 // Handles all the cases where we have a single V2 element and an undef.
8288 // This will only ever happen in the high lanes because we commute the
8289 // vector otherwise.
8290 if (V2Index < 2)
8291 std::swap(LowV, HighV);
8292 NewMask[V2Index] -= 4;
8293 } else {
8294 // Handle the case where the V2 element ends up adjacent to a V1 element.
8295 // To make this work, blend them together as the first step.
8296 int V1Index = V2AdjIndex;
8297 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8298 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8299 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8301 // Now proceed to reconstruct the final blend as we have the necessary
8302 // high or low half formed.
8303 if (V2Index < 2) {
8304 LowV = V2;
8305 HighV = V1;
8306 } else {
8307 HighV = V2;
8308 }
8309 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8310 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8311 }
8312 } else if (NumV2Elements == 2) {
8313 if (Mask[0] < 4 && Mask[1] < 4) {
8314 // Handle the easy case where we have V1 in the low lanes and V2 in the
8315 // high lanes.
8316 NewMask[2] -= 4;
8317 NewMask[3] -= 4;
8318 } else if (Mask[2] < 4 && Mask[3] < 4) {
8319 // We also handle the reversed case because this utility may get called
8320 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8321 // arrange things in the right direction.
8322 NewMask[0] -= 4;
8323 NewMask[1] -= 4;
8324 HighV = V1;
8325 LowV = V2;
8326 } else {
8327 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8328 // trying to place elements directly, just blend them and set up the final
8329 // shuffle to place them.
8331 // The first two blend mask elements are for V1, the second two are for
8332 // V2.
8333 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8334 Mask[2] < 4 ? Mask[2] : Mask[3],
8335 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8336 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8337 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8338 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8340 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8341 // a blend.
8342 LowV = HighV = V1;
8343 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8344 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8345 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8346 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8347 }
8348 }
8349 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8350 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8351 }
8353 /// \brief Lower 4-lane 32-bit floating point shuffles.
8354 ///
8355 /// Uses instructions exclusively from the floating point unit to minimize
8356 /// domain crossing penalties, as these are sufficient to implement all v4f32
8357 /// shuffles.
8358 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8359 const X86Subtarget *Subtarget,
8360 SelectionDAG &DAG) {
8361 SDLoc DL(Op);
8362 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8363 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8364 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8365 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8366 ArrayRef<int> Mask = SVOp->getMask();
8367 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8369 int NumV2Elements =
8370 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8372 if (NumV2Elements == 0) {
8373 // Check for being able to broadcast a single element.
8374 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f32, DL, V1,
8375 Mask, Subtarget, DAG))
8376 return Broadcast;
8378 if (Subtarget->hasAVX()) {
8379 // If we have AVX, we can use VPERMILPS which will allow folding a load
8380 // into the shuffle.
8381 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8382 getV4X86ShuffleImm8ForMask(Mask, DAG));
8383 }
8385 // Otherwise, use a straight shuffle of a single input vector. We pass the
8386 // input vector to both operands to simulate this with a SHUFPS.
8387 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8388 getV4X86ShuffleImm8ForMask(Mask, DAG));
8389 }
8391 // Use dedicated unpack instructions for masks that match their pattern.
8392 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8393 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8394 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8395 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8397 // There are special ways we can lower some single-element blends. However, we
8398 // have custom ways we can lower more complex single-element blends below that
8399 // we defer to if both this and BLENDPS fail to match, so restrict this to
8400 // when the V2 input is targeting element 0 of the mask -- that is the fast
8401 // case here.
8402 if (NumV2Elements == 1 && Mask[0] >= 4)
8403 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8404 Mask, Subtarget, DAG))
8405 return V;
8407 if (Subtarget->hasSSE41())
8408 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8409 Subtarget, DAG))
8410 return Blend;
8412 // Check for whether we can use INSERTPS to perform the blend. We only use
8413 // INSERTPS when the V1 elements are already in the correct locations
8414 // because otherwise we can just always use two SHUFPS instructions which
8415 // are much smaller to encode than a SHUFPS and an INSERTPS.
8416 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
8417 int V2Index =
8418 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8419 Mask.begin();
8421 // When using INSERTPS we can zero any lane of the destination. Collect
8422 // the zero inputs into a mask and drop them from the lanes of V1 which
8423 // actually need to be present as inputs to the INSERTPS.
8424 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8426 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
8427 bool InsertNeedsShuffle = false;
8428 unsigned ZMask = 0;
8429 for (int i = 0; i < 4; ++i)
8430 if (i != V2Index) {
8431 if (Zeroable[i]) {
8432 ZMask |= 1 << i;
8433 } else if (Mask[i] != i) {
8434 InsertNeedsShuffle = true;
8435 break;
8436 }
8437 }
8439 // We don't want to use INSERTPS or other insertion techniques if it will
8440 // require shuffling anyways.
8441 if (!InsertNeedsShuffle) {
8442 // If all of V1 is zeroable, replace it with undef.
8443 if ((ZMask | 1 << V2Index) == 0xF)
8444 V1 = DAG.getUNDEF(MVT::v4f32);
8446 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
8447 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8449 // Insert the V2 element into the desired position.
8450 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8451 DAG.getConstant(InsertPSMask, MVT::i8));
8452 }
8453 }
8455 // Otherwise fall back to a SHUFPS lowering strategy.
8456 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8457 }
8459 /// \brief Lower 4-lane i32 vector shuffles.
8460 ///
8461 /// We try to handle these with integer-domain shuffles where we can, but for
8462 /// blends we use the floating point domain blend instructions.
8463 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8464 const X86Subtarget *Subtarget,
8465 SelectionDAG &DAG) {
8466 SDLoc DL(Op);
8467 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8468 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8469 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8470 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8471 ArrayRef<int> Mask = SVOp->getMask();
8472 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8474 // Whenever we can lower this as a zext, that instruction is strictly faster
8475 // than any alternative. It also allows us to fold memory operands into the
8476 // shuffle in many cases.
8477 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8478 Mask, Subtarget, DAG))
8479 return ZExt;
8481 int NumV2Elements =
8482 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8484 if (NumV2Elements == 0) {
8485 // Check for being able to broadcast a single element.
8486 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i32, DL, V1,
8487 Mask, Subtarget, DAG))
8488 return Broadcast;
8490 // Straight shuffle of a single input vector. For everything from SSE2
8491 // onward this has a single fast instruction with no scary immediates.
8492 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8493 // but we aren't actually going to use the UNPCK instruction because doing
8494 // so prevents folding a load into this instruction or making a copy.
8495 const int UnpackLoMask[] = {0, 0, 1, 1};
8496 const int UnpackHiMask[] = {2, 2, 3, 3};
8497 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8498 Mask = UnpackLoMask;
8499 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8500 Mask = UnpackHiMask;
8502 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8503 getV4X86ShuffleImm8ForMask(Mask, DAG));
8504 }
8506 // Try to use byte shift instructions.
8507 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8508 DL, MVT::v4i32, V1, V2, Mask, DAG))
8509 return Shift;
8511 // There are special ways we can lower some single-element blends.
8512 if (NumV2Elements == 1)
8513 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8514 Mask, Subtarget, DAG))
8515 return V;
8517 // Use dedicated unpack instructions for masks that match their pattern.
8518 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8519 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8520 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8521 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8523 if (Subtarget->hasSSE41())
8524 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8525 Subtarget, DAG))
8526 return Blend;
8528 // Try to use byte rotation instructions.
8529 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8530 if (Subtarget->hasSSSE3())
8531 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8532 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8533 return Rotate;
8535 // We implement this with SHUFPS because it can blend from two vectors.
8536 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8537 // up the inputs, bypassing domain shift penalties that we would encur if we
8538 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8539 // relevant.
8540 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8541 DAG.getVectorShuffle(
8542 MVT::v4f32, DL,
8543 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8544 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8545 }
8547 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8548 /// shuffle lowering, and the most complex part.
8549 ///
8550 /// The lowering strategy is to try to form pairs of input lanes which are
8551 /// targeted at the same half of the final vector, and then use a dword shuffle
8552 /// to place them onto the right half, and finally unpack the paired lanes into
8553 /// their final position.
8554 ///
8555 /// The exact breakdown of how to form these dword pairs and align them on the
8556 /// correct sides is really tricky. See the comments within the function for
8557 /// more of the details.
8558 static SDValue lowerV8I16SingleInputVectorShuffle(
8559 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8560 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8561 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8562 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8563 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8565 SmallVector<int, 4> LoInputs;
8566 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8567 [](int M) { return M >= 0; });
8568 std::sort(LoInputs.begin(), LoInputs.end());
8569 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8570 SmallVector<int, 4> HiInputs;
8571 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8572 [](int M) { return M >= 0; });
8573 std::sort(HiInputs.begin(), HiInputs.end());
8574 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8575 int NumLToL =
8576 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8577 int NumHToL = LoInputs.size() - NumLToL;
8578 int NumLToH =
8579 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8580 int NumHToH = HiInputs.size() - NumLToH;
8581 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8582 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8583 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8584 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8586 // Check for being able to broadcast a single element.
8587 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i16, DL, V,
8588 Mask, Subtarget, DAG))
8589 return Broadcast;
8591 // Try to use byte shift instructions.
8592 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8593 DL, MVT::v8i16, V, V, Mask, DAG))
8594 return Shift;
8596 // Use dedicated unpack instructions for masks that match their pattern.
8597 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8598 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8599 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8600 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8602 // Try to use byte rotation instructions.
8603 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8604 DL, MVT::v8i16, V, V, Mask, Subtarget, DAG))
8605 return Rotate;
8607 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8608 // such inputs we can swap two of the dwords across the half mark and end up
8609 // with <=2 inputs to each half in each half. Once there, we can fall through
8610 // to the generic code below. For example:
8611 //
8612 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8613 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8614 //
8615 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8616 // and an existing 2-into-2 on the other half. In this case we may have to
8617 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8618 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8619 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8620 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8621 // half than the one we target for fixing) will be fixed when we re-enter this
8622 // path. We will also combine away any sequence of PSHUFD instructions that
8623 // result into a single instruction. Here is an example of the tricky case:
8624 //
8625 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8626 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8627 //
8628 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8629 //
8630 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8631 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8632 //
8633 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8634 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8635 //
8636 // The result is fine to be handled by the generic logic.
8637 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8638 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8639 int AOffset, int BOffset) {
8640 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8641 "Must call this with A having 3 or 1 inputs from the A half.");
8642 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8643 "Must call this with B having 1 or 3 inputs from the B half.");
8644 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8645 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8647 // Compute the index of dword with only one word among the three inputs in
8648 // a half by taking the sum of the half with three inputs and subtracting
8649 // the sum of the actual three inputs. The difference is the remaining
8650 // slot.
8651 int ADWord, BDWord;
8652 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8653 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8654 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8655 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8656 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8657 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8658 int TripleNonInputIdx =
8659 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8660 TripleDWord = TripleNonInputIdx / 2;
8662 // We use xor with one to compute the adjacent DWord to whichever one the
8663 // OneInput is in.
8664 OneInputDWord = (OneInput / 2) ^ 1;
8666 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8667 // and BToA inputs. If there is also such a problem with the BToB and AToB
8668 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8669 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8670 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8671 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8672 // Compute how many inputs will be flipped by swapping these DWords. We
8673 // need
8674 // to balance this to ensure we don't form a 3-1 shuffle in the other
8675 // half.
8676 int NumFlippedAToBInputs =
8677 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8678 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8679 int NumFlippedBToBInputs =
8680 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8681 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8682 if ((NumFlippedAToBInputs == 1 &&
8683 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8684 (NumFlippedBToBInputs == 1 &&
8685 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8686 // We choose whether to fix the A half or B half based on whether that
8687 // half has zero flipped inputs. At zero, we may not be able to fix it
8688 // with that half. We also bias towards fixing the B half because that
8689 // will more commonly be the high half, and we have to bias one way.
8690 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8691 ArrayRef<int> Inputs) {
8692 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8693 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8694 PinnedIdx ^ 1) != Inputs.end();
8695 // Determine whether the free index is in the flipped dword or the
8696 // unflipped dword based on where the pinned index is. We use this bit
8697 // in an xor to conditionally select the adjacent dword.
8698 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8699 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8700 FixFreeIdx) != Inputs.end();
8701 if (IsFixIdxInput == IsFixFreeIdxInput)
8702 FixFreeIdx += 1;
8703 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8704 FixFreeIdx) != Inputs.end();
8705 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8706 "We need to be changing the number of flipped inputs!");
8707 int PSHUFHalfMask[] = {0, 1, 2, 3};
8708 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8709 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8710 MVT::v8i16, V,
8711 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8713 for (int &M : Mask)
8714 if (M != -1 && M == FixIdx)
8715 M = FixFreeIdx;
8716 else if (M != -1 && M == FixFreeIdx)
8717 M = FixIdx;
8718 };
8719 if (NumFlippedBToBInputs != 0) {
8720 int BPinnedIdx =
8721 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8722 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8723 } else {
8724 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8725 int APinnedIdx =
8726 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8727 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8728 }
8729 }
8730 }
8732 int PSHUFDMask[] = {0, 1, 2, 3};
8733 PSHUFDMask[ADWord] = BDWord;
8734 PSHUFDMask[BDWord] = ADWord;
8735 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8736 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8737 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8738 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8740 // Adjust the mask to match the new locations of A and B.
8741 for (int &M : Mask)
8742 if (M != -1 && M/2 == ADWord)
8743 M = 2 * BDWord + M % 2;
8744 else if (M != -1 && M/2 == BDWord)
8745 M = 2 * ADWord + M % 2;
8747 // Recurse back into this routine to re-compute state now that this isn't
8748 // a 3 and 1 problem.
8749 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8750 Mask);
8751 };
8752 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8753 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8754 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8755 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8757 // At this point there are at most two inputs to the low and high halves from
8758 // each half. That means the inputs can always be grouped into dwords and
8759 // those dwords can then be moved to the correct half with a dword shuffle.
8760 // We use at most one low and one high word shuffle to collect these paired
8761 // inputs into dwords, and finally a dword shuffle to place them.
8762 int PSHUFLMask[4] = {-1, -1, -1, -1};
8763 int PSHUFHMask[4] = {-1, -1, -1, -1};
8764 int PSHUFDMask[4] = {-1, -1, -1, -1};
8766 // First fix the masks for all the inputs that are staying in their
8767 // original halves. This will then dictate the targets of the cross-half
8768 // shuffles.
8769 auto fixInPlaceInputs =
8770 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8771 MutableArrayRef<int> SourceHalfMask,
8772 MutableArrayRef<int> HalfMask, int HalfOffset) {
8773 if (InPlaceInputs.empty())
8774 return;
8775 if (InPlaceInputs.size() == 1) {
8776 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8777 InPlaceInputs[0] - HalfOffset;
8778 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8779 return;
8780 }
8781 if (IncomingInputs.empty()) {
8782 // Just fix all of the in place inputs.
8783 for (int Input : InPlaceInputs) {
8784 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8785 PSHUFDMask[Input / 2] = Input / 2;
8786 }
8787 return;
8788 }
8790 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8791 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8792 InPlaceInputs[0] - HalfOffset;
8793 // Put the second input next to the first so that they are packed into
8794 // a dword. We find the adjacent index by toggling the low bit.
8795 int AdjIndex = InPlaceInputs[0] ^ 1;
8796 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8797 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8798 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8799 };
8800 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8801 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8803 // Now gather the cross-half inputs and place them into a free dword of
8804 // their target half.
8805 // FIXME: This operation could almost certainly be simplified dramatically to
8806 // look more like the 3-1 fixing operation.
8807 auto moveInputsToRightHalf = [&PSHUFDMask](
8808 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8809 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8810 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8811 int DestOffset) {
8812 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8813 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8814 };
8815 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8816 int Word) {
8817 int LowWord = Word & ~1;
8818 int HighWord = Word | 1;
8819 return isWordClobbered(SourceHalfMask, LowWord) ||
8820 isWordClobbered(SourceHalfMask, HighWord);
8821 };
8823 if (IncomingInputs.empty())
8824 return;
8826 if (ExistingInputs.empty()) {
8827 // Map any dwords with inputs from them into the right half.
8828 for (int Input : IncomingInputs) {
8829 // If the source half mask maps over the inputs, turn those into
8830 // swaps and use the swapped lane.
8831 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8832 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8833 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8834 Input - SourceOffset;
8835 // We have to swap the uses in our half mask in one sweep.
8836 for (int &M : HalfMask)
8837 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8838 M = Input;
8839 else if (M == Input)
8840 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8841 } else {
8842 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8843 Input - SourceOffset &&
8844 "Previous placement doesn't match!");
8845 }
8846 // Note that this correctly re-maps both when we do a swap and when
8847 // we observe the other side of the swap above. We rely on that to
8848 // avoid swapping the members of the input list directly.
8849 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8850 }
8852 // Map the input's dword into the correct half.
8853 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8854 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8855 else
8856 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8857 Input / 2 &&
8858 "Previous placement doesn't match!");
8859 }
8861 // And just directly shift any other-half mask elements to be same-half
8862 // as we will have mirrored the dword containing the element into the
8863 // same position within that half.
8864 for (int &M : HalfMask)
8865 if (M >= SourceOffset && M < SourceOffset + 4) {
8866 M = M - SourceOffset + DestOffset;
8867 assert(M >= 0 && "This should never wrap below zero!");
8868 }
8869 return;
8870 }
8872 // Ensure we have the input in a viable dword of its current half. This
8873 // is particularly tricky because the original position may be clobbered
8874 // by inputs being moved and *staying* in that half.
8875 if (IncomingInputs.size() == 1) {
8876 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8877 int InputFixed = std::find(std::begin(SourceHalfMask),
8878 std::end(SourceHalfMask), -1) -
8879 std::begin(SourceHalfMask) + SourceOffset;
8880 SourceHalfMask[InputFixed - SourceOffset] =
8881 IncomingInputs[0] - SourceOffset;
8882 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8883 InputFixed);
8884 IncomingInputs[0] = InputFixed;
8885 }
8886 } else if (IncomingInputs.size() == 2) {
8887 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8888 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8889 // We have two non-adjacent or clobbered inputs we need to extract from
8890 // the source half. To do this, we need to map them into some adjacent
8891 // dword slot in the source mask.
8892 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8893 IncomingInputs[1] - SourceOffset};
8895 // If there is a free slot in the source half mask adjacent to one of
8896 // the inputs, place the other input in it. We use (Index XOR 1) to
8897 // compute an adjacent index.
8898 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8899 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8900 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8901 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8902 InputsFixed[1] = InputsFixed[0] ^ 1;
8903 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8904 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8905 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8906 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8907 InputsFixed[0] = InputsFixed[1] ^ 1;
8908 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8909 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8910 // The two inputs are in the same DWord but it is clobbered and the
8911 // adjacent DWord isn't used at all. Move both inputs to the free
8912 // slot.
8913 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8914 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8915 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8916 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8917 } else {
8918 // The only way we hit this point is if there is no clobbering
8919 // (because there are no off-half inputs to this half) and there is no
8920 // free slot adjacent to one of the inputs. In this case, we have to
8921 // swap an input with a non-input.
8922 for (int i = 0; i < 4; ++i)
8923 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8924 "We can't handle any clobbers here!");
8925 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8926 "Cannot have adjacent inputs here!");
8928 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8929 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8931 // We also have to update the final source mask in this case because
8932 // it may need to undo the above swap.
8933 for (int &M : FinalSourceHalfMask)
8934 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8935 M = InputsFixed[1] + SourceOffset;
8936 else if (M == InputsFixed[1] + SourceOffset)
8937 M = (InputsFixed[0] ^ 1) + SourceOffset;
8939 InputsFixed[1] = InputsFixed[0] ^ 1;
8940 }
8942 // Point everything at the fixed inputs.
8943 for (int &M : HalfMask)
8944 if (M == IncomingInputs[0])
8945 M = InputsFixed[0] + SourceOffset;
8946 else if (M == IncomingInputs[1])
8947 M = InputsFixed[1] + SourceOffset;
8949 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8950 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8951 }
8952 } else {
8953 llvm_unreachable("Unhandled input size!");
8954 }
8956 // Now hoist the DWord down to the right half.
8957 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8958 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8959 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8960 for (int &M : HalfMask)
8961 for (int Input : IncomingInputs)
8962 if (M == Input)
8963 M = FreeDWord * 2 + Input % 2;
8964 };
8965 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8966 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8967 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8968 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8970 // Now enact all the shuffles we've computed to move the inputs into their
8971 // target half.
8972 if (!isNoopShuffleMask(PSHUFLMask))
8973 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8974 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8975 if (!isNoopShuffleMask(PSHUFHMask))
8976 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8977 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8978 if (!isNoopShuffleMask(PSHUFDMask))
8979 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8980 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8981 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8982 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8984 // At this point, each half should contain all its inputs, and we can then
8985 // just shuffle them into their final position.
8986 assert(std::count_if(LoMask.begin(), LoMask.end(),
8987 [](int M) { return M >= 4; }) == 0 &&
8988 "Failed to lift all the high half inputs to the low mask!");
8989 assert(std::count_if(HiMask.begin(), HiMask.end(),
8990 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8991 "Failed to lift all the low half inputs to the high mask!");
8993 // Do a half shuffle for the low mask.
8994 if (!isNoopShuffleMask(LoMask))
8995 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8996 getV4X86ShuffleImm8ForMask(LoMask, DAG));
8998 // Do a half shuffle with the high mask after shifting its values down.
8999 for (int &M : HiMask)
9000 if (M >= 0)
9001 M -= 4;
9002 if (!isNoopShuffleMask(HiMask))
9003 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
9004 getV4X86ShuffleImm8ForMask(HiMask, DAG));
9006 return V;
9007 }
9009 /// \brief Detect whether the mask pattern should be lowered through
9010 /// interleaving.
9011 ///
9012 /// This essentially tests whether viewing the mask as an interleaving of two
9013 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
9014 /// lowering it through interleaving is a significantly better strategy.
9015 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
9016 int NumEvenInputs[2] = {0, 0};
9017 int NumOddInputs[2] = {0, 0};
9018 int NumLoInputs[2] = {0, 0};
9019 int NumHiInputs[2] = {0, 0};
9020 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
9021 if (Mask[i] < 0)
9022 continue;
9024 int InputIdx = Mask[i] >= Size;
9026 if (i < Size / 2)
9027 ++NumLoInputs[InputIdx];
9028 else
9029 ++NumHiInputs[InputIdx];
9031 if ((i % 2) == 0)
9032 ++NumEvenInputs[InputIdx];
9033 else
9034 ++NumOddInputs[InputIdx];
9035 }
9037 // The minimum number of cross-input results for both the interleaved and
9038 // split cases. If interleaving results in fewer cross-input results, return
9039 // true.
9040 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
9041 NumEvenInputs[0] + NumOddInputs[1]);
9042 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
9043 NumLoInputs[0] + NumHiInputs[1]);
9044 return InterleavedCrosses < SplitCrosses;
9045 }
9047 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
9048 ///
9049 /// This strategy only works when the inputs from each vector fit into a single
9050 /// half of that vector, and generally there are not so many inputs as to leave
9051 /// the in-place shuffles required highly constrained (and thus expensive). It
9052 /// shifts all the inputs into a single side of both input vectors and then
9053 /// uses an unpack to interleave these inputs in a single vector. At that
9054 /// point, we will fall back on the generic single input shuffle lowering.
9055 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
9056 SDValue V2,
9057 MutableArrayRef<int> Mask,
9058 const X86Subtarget *Subtarget,
9059 SelectionDAG &DAG) {
9060 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9061 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9062 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
9063 for (int i = 0; i < 8; ++i)
9064 if (Mask[i] >= 0 && Mask[i] < 4)
9065 LoV1Inputs.push_back(i);
9066 else if (Mask[i] >= 4 && Mask[i] < 8)
9067 HiV1Inputs.push_back(i);
9068 else if (Mask[i] >= 8 && Mask[i] < 12)
9069 LoV2Inputs.push_back(i);
9070 else if (Mask[i] >= 12)
9071 HiV2Inputs.push_back(i);
9073 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
9074 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
9075 (void)NumV1Inputs;
9076 (void)NumV2Inputs;
9077 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
9078 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
9079 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
9081 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
9082 HiV1Inputs.size() + HiV2Inputs.size();
9084 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
9085 ArrayRef<int> HiInputs, bool MoveToLo,
9086 int MaskOffset) {
9087 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
9088 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
9089 if (BadInputs.empty())
9090 return V;
9092 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9093 int MoveOffset = MoveToLo ? 0 : 4;
9095 if (GoodInputs.empty()) {
9096 for (int BadInput : BadInputs) {
9097 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
9098 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
9099 }
9100 } else {
9101 if (GoodInputs.size() == 2) {
9102 // If the low inputs are spread across two dwords, pack them into
9103 // a single dword.
9104 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
9105 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
9106 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
9107 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
9108 } else {
9109 // Otherwise pin the good inputs.
9110 for (int GoodInput : GoodInputs)
9111 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
9112 }
9114 if (BadInputs.size() == 2) {
9115 // If we have two bad inputs then there may be either one or two good
9116 // inputs fixed in place. Find a fixed input, and then find the *other*
9117 // two adjacent indices by using modular arithmetic.
9118 int GoodMaskIdx =
9119 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
9120 [](int M) { return M >= 0; }) -
9121 std::begin(MoveMask);
9122 int MoveMaskIdx =
9123 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
9124 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
9125 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
9126 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9127 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
9128 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9129 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
9130 } else {
9131 assert(BadInputs.size() == 1 && "All sizes handled");
9132 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
9133 std::end(MoveMask), -1) -
9134 std::begin(MoveMask);
9135 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9136 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9137 }
9138 }
9140 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
9141 MoveMask);
9142 };
9143 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
9144 /*MaskOffset*/ 0);
9145 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
9146 /*MaskOffset*/ 8);
9148 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
9149 // cross-half traffic in the final shuffle.
9151 // Munge the mask to be a single-input mask after the unpack merges the
9152 // results.
9153 for (int &M : Mask)
9154 if (M != -1)
9155 M = 2 * (M % 4) + (M / 8);
9157 return DAG.getVectorShuffle(
9158 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
9159 DL, MVT::v8i16, V1, V2),
9160 DAG.getUNDEF(MVT::v8i16), Mask);
9161 }
9163 /// \brief Generic lowering of 8-lane i16 shuffles.
9164 ///
9165 /// This handles both single-input shuffles and combined shuffle/blends with
9166 /// two inputs. The single input shuffles are immediately delegated to
9167 /// a dedicated lowering routine.
9168 ///
9169 /// The blends are lowered in one of three fundamental ways. If there are few
9170 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9171 /// of the input is significantly cheaper when lowered as an interleaving of
9172 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9173 /// halves of the inputs separately (making them have relatively few inputs)
9174 /// and then concatenate them.
9175 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9176 const X86Subtarget *Subtarget,
9177 SelectionDAG &DAG) {
9178 SDLoc DL(Op);
9179 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9180 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9181 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9182 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9183 ArrayRef<int> OrigMask = SVOp->getMask();
9184 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9185 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9186 MutableArrayRef<int> Mask(MaskStorage);
9188 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9190 // Whenever we can lower this as a zext, that instruction is strictly faster
9191 // than any alternative.
9192 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9193 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9194 return ZExt;
9196 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9197 auto isV2 = [](int M) { return M >= 8; };
9199 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
9200 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9202 if (NumV2Inputs == 0)
9203 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
9205 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
9206 "to be V1-input shuffles.");
9208 // Try to use byte shift instructions.
9209 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9210 DL, MVT::v8i16, V1, V2, Mask, DAG))
9211 return Shift;
9213 // There are special ways we can lower some single-element blends.
9214 if (NumV2Inputs == 1)
9215 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
9216 Mask, Subtarget, DAG))
9217 return V;
9219 // Use dedicated unpack instructions for masks that match their pattern.
9220 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 2, 10, 3, 11))
9221 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
9222 if (isShuffleEquivalent(Mask, 4, 12, 5, 13, 6, 14, 7, 15))
9223 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
9225 if (Subtarget->hasSSE41())
9226 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9227 Subtarget, DAG))
9228 return Blend;
9230 // Try to use byte rotation instructions.
9231 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9232 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9233 return Rotate;
9235 if (NumV1Inputs + NumV2Inputs <= 4)
9236 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
9238 // Check whether an interleaving lowering is likely to be more efficient.
9239 // This isn't perfect but it is a strong heuristic that tends to work well on
9240 // the kinds of shuffles that show up in practice.
9241 //
9242 // FIXME: Handle 1x, 2x, and 4x interleaving.
9243 if (shouldLowerAsInterleaving(Mask)) {
9244 // FIXME: Figure out whether we should pack these into the low or high
9245 // halves.
9247 int EMask[8], OMask[8];
9248 for (int i = 0; i < 4; ++i) {
9249 EMask[i] = Mask[2*i];
9250 OMask[i] = Mask[2*i + 1];
9251 EMask[i + 4] = -1;
9252 OMask[i + 4] = -1;
9253 }
9255 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
9256 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
9258 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
9259 }
9261 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9262 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9264 for (int i = 0; i < 4; ++i) {
9265 LoBlendMask[i] = Mask[i];
9266 HiBlendMask[i] = Mask[i + 4];
9267 }
9269 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9270 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9271 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
9272 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
9274 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9275 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
9276 }
9278 /// \brief Check whether a compaction lowering can be done by dropping even
9279 /// elements and compute how many times even elements must be dropped.
9280 ///
9281 /// This handles shuffles which take every Nth element where N is a power of
9282 /// two. Example shuffle masks:
9283 ///
9284 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9285 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9286 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9287 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9288 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9289 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9290 ///
9291 /// Any of these lanes can of course be undef.
9292 ///
9293 /// This routine only supports N <= 3.
9294 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9295 /// for larger N.
9296 ///
9297 /// \returns N above, or the number of times even elements must be dropped if
9298 /// there is such a number. Otherwise returns zero.
9299 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9300 // Figure out whether we're looping over two inputs or just one.
9301 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9303 // The modulus for the shuffle vector entries is based on whether this is
9304 // a single input or not.
9305 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9306 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9307 "We should only be called with masks with a power-of-2 size!");
9309 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9311 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9312 // and 2^3 simultaneously. This is because we may have ambiguity with
9313 // partially undef inputs.
9314 bool ViableForN[3] = {true, true, true};
9316 for (int i = 0, e = Mask.size(); i < e; ++i) {
9317 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9318 // want.
9319 if (Mask[i] == -1)
9320 continue;
9322 bool IsAnyViable = false;
9323 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9324 if (ViableForN[j]) {
9325 uint64_t N = j + 1;
9327 // The shuffle mask must be equal to (i * 2^N) % M.
9328 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9329 IsAnyViable = true;
9330 else
9331 ViableForN[j] = false;
9332 }
9333 // Early exit if we exhaust the possible powers of two.
9334 if (!IsAnyViable)
9335 break;
9336 }
9338 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9339 if (ViableForN[j])
9340 return j + 1;
9342 // Return 0 as there is no viable power of two.
9343 return 0;
9344 }
9346 /// \brief Generic lowering of v16i8 shuffles.
9347 ///
9348 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9349 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9350 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9351 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9352 /// back together.
9353 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9354 const X86Subtarget *Subtarget,
9355 SelectionDAG &DAG) {
9356 SDLoc DL(Op);
9357 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9358 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9359 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9360 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9361 ArrayRef<int> OrigMask = SVOp->getMask();
9362 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9364 // Try to use byte shift instructions.
9365 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9366 DL, MVT::v16i8, V1, V2, OrigMask, DAG))
9367 return Shift;
9369 // Try to use byte rotation instructions.
9370 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9371 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9372 return Rotate;
9374 // Try to use a zext lowering.
9375 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9376 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9377 return ZExt;
9379 int MaskStorage[16] = {
9380 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9381 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9382 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9383 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9384 MutableArrayRef<int> Mask(MaskStorage);
9385 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9386 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9388 int NumV2Elements =
9389 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9391 // For single-input shuffles, there are some nicer lowering tricks we can use.
9392 if (NumV2Elements == 0) {
9393 // Check for being able to broadcast a single element.
9394 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i8, DL, V1,
9395 Mask, Subtarget, DAG))
9396 return Broadcast;
9398 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9399 // Notably, this handles splat and partial-splat shuffles more efficiently.
9400 // However, it only makes sense if the pre-duplication shuffle simplifies
9401 // things significantly. Currently, this means we need to be able to
9402 // express the pre-duplication shuffle as an i16 shuffle.
9403 //
9404 // FIXME: We should check for other patterns which can be widened into an
9405 // i16 shuffle as well.
9406 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9407 for (int i = 0; i < 16; i += 2)
9408 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9409 return false;
9411 return true;
9412 };
9413 auto tryToWidenViaDuplication = [&]() -> SDValue {
9414 if (!canWidenViaDuplication(Mask))
9415 return SDValue();
9416 SmallVector<int, 4> LoInputs;
9417 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9418 [](int M) { return M >= 0 && M < 8; });
9419 std::sort(LoInputs.begin(), LoInputs.end());
9420 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9421 LoInputs.end());
9422 SmallVector<int, 4> HiInputs;
9423 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9424 [](int M) { return M >= 8; });
9425 std::sort(HiInputs.begin(), HiInputs.end());
9426 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9427 HiInputs.end());
9429 bool TargetLo = LoInputs.size() >= HiInputs.size();
9430 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9431 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9433 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9434 SmallDenseMap<int, int, 8> LaneMap;
9435 for (int I : InPlaceInputs) {
9436 PreDupI16Shuffle[I/2] = I/2;
9437 LaneMap[I] = I;
9438 }
9439 int j = TargetLo ? 0 : 4, je = j + 4;
9440 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9441 // Check if j is already a shuffle of this input. This happens when
9442 // there are two adjacent bytes after we move the low one.
9443 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9444 // If we haven't yet mapped the input, search for a slot into which
9445 // we can map it.
9446 while (j < je && PreDupI16Shuffle[j] != -1)
9447 ++j;
9449 if (j == je)
9450 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9451 return SDValue();
9453 // Map this input with the i16 shuffle.
9454 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9455 }
9457 // Update the lane map based on the mapping we ended up with.
9458 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9459 }
9460 V1 = DAG.getNode(
9461 ISD::BITCAST, DL, MVT::v16i8,
9462 DAG.getVectorShuffle(MVT::v8i16, DL,
9463 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9464 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9466 // Unpack the bytes to form the i16s that will be shuffled into place.
9467 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9468 MVT::v16i8, V1, V1);
9470 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9471 for (int i = 0; i < 16; ++i)
9472 if (Mask[i] != -1) {
9473 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9474 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9475 if (PostDupI16Shuffle[i / 2] == -1)
9476 PostDupI16Shuffle[i / 2] = MappedMask;
9477 else
9478 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9479 "Conflicting entrties in the original shuffle!");
9480 }
9481 return DAG.getNode(
9482 ISD::BITCAST, DL, MVT::v16i8,
9483 DAG.getVectorShuffle(MVT::v8i16, DL,
9484 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9485 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9486 };
9487 if (SDValue V = tryToWidenViaDuplication())
9488 return V;
9489 }
9491 // Check whether an interleaving lowering is likely to be more efficient.
9492 // This isn't perfect but it is a strong heuristic that tends to work well on
9493 // the kinds of shuffles that show up in practice.
9494 //
9495 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9496 if (shouldLowerAsInterleaving(Mask)) {
9497 int NumLoHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9498 return (M >= 0 && M < 8) || (M >= 16 && M < 24);
9499 });
9500 int NumHiHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9501 return (M >= 8 && M < 16) || M >= 24;
9502 });
9503 int EMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9504 -1, -1, -1, -1, -1, -1, -1, -1};
9505 int OMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9506 -1, -1, -1, -1, -1, -1, -1, -1};
9507 bool UnpackLo = NumLoHalf >= NumHiHalf;
9508 MutableArrayRef<int> TargetEMask(UnpackLo ? EMask : EMask + 8, 8);
9509 MutableArrayRef<int> TargetOMask(UnpackLo ? OMask : OMask + 8, 8);
9510 for (int i = 0; i < 8; ++i) {
9511 TargetEMask[i] = Mask[2 * i];
9512 TargetOMask[i] = Mask[2 * i + 1];
9513 }
9515 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9516 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9518 return DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9519 MVT::v16i8, Evens, Odds);
9520 }
9522 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9523 // with PSHUFB. It is important to do this before we attempt to generate any
9524 // blends but after all of the single-input lowerings. If the single input
9525 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9526 // want to preserve that and we can DAG combine any longer sequences into
9527 // a PSHUFB in the end. But once we start blending from multiple inputs,
9528 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9529 // and there are *very* few patterns that would actually be faster than the
9530 // PSHUFB approach because of its ability to zero lanes.
9531 //
9532 // FIXME: The only exceptions to the above are blends which are exact
9533 // interleavings with direct instructions supporting them. We currently don't
9534 // handle those well here.
9535 if (Subtarget->hasSSSE3()) {
9536 SDValue V1Mask[16];
9537 SDValue V2Mask[16];
9538 for (int i = 0; i < 16; ++i)
9539 if (Mask[i] == -1) {
9540 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9541 } else {
9542 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9543 V2Mask[i] =
9544 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9545 }
9546 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9547 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9548 if (isSingleInputShuffleMask(Mask))
9549 return V1; // Single inputs are easy.
9551 // Otherwise, blend the two.
9552 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9553 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9554 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9555 }
9557 // There are special ways we can lower some single-element blends.
9558 if (NumV2Elements == 1)
9559 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9560 Mask, Subtarget, DAG))
9561 return V;
9563 // Check whether a compaction lowering can be done. This handles shuffles
9564 // which take every Nth element for some even N. See the helper function for
9565 // details.
9566 //
9567 // We special case these as they can be particularly efficiently handled with
9568 // the PACKUSB instruction on x86 and they show up in common patterns of
9569 // rearranging bytes to truncate wide elements.
9570 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9571 // NumEvenDrops is the power of two stride of the elements. Another way of
9572 // thinking about it is that we need to drop the even elements this many
9573 // times to get the original input.
9574 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9576 // First we need to zero all the dropped bytes.
9577 assert(NumEvenDrops <= 3 &&
9578 "No support for dropping even elements more than 3 times.");
9579 // We use the mask type to pick which bytes are preserved based on how many
9580 // elements are dropped.
9581 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9582 SDValue ByteClearMask =
9583 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9584 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9585 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9586 if (!IsSingleInput)
9587 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9589 // Now pack things back together.
9590 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9591 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9592 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9593 for (int i = 1; i < NumEvenDrops; ++i) {
9594 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9595 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9596 }
9598 return Result;
9599 }
9601 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9602 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9603 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9604 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9606 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9607 MutableArrayRef<int> V1HalfBlendMask,
9608 MutableArrayRef<int> V2HalfBlendMask) {
9609 for (int i = 0; i < 8; ++i)
9610 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9611 V1HalfBlendMask[i] = HalfMask[i];
9612 HalfMask[i] = i;
9613 } else if (HalfMask[i] >= 16) {
9614 V2HalfBlendMask[i] = HalfMask[i] - 16;
9615 HalfMask[i] = i + 8;
9616 }
9617 };
9618 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9619 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9621 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9623 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9624 MutableArrayRef<int> HiBlendMask) {
9625 SDValue V1, V2;
9626 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9627 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9628 // i16s.
9629 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9630 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9631 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9632 [](int M) { return M >= 0 && M % 2 == 1; })) {
9633 // Use a mask to drop the high bytes.
9634 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9635 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9636 DAG.getConstant(0x00FF, MVT::v8i16));
9638 // This will be a single vector shuffle instead of a blend so nuke V2.
9639 V2 = DAG.getUNDEF(MVT::v8i16);
9641 // Squash the masks to point directly into V1.
9642 for (int &M : LoBlendMask)
9643 if (M >= 0)
9644 M /= 2;
9645 for (int &M : HiBlendMask)
9646 if (M >= 0)
9647 M /= 2;
9648 } else {
9649 // Otherwise just unpack the low half of V into V1 and the high half into
9650 // V2 so that we can blend them as i16s.
9651 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9652 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9653 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9654 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9655 }
9657 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9658 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9659 return std::make_pair(BlendedLo, BlendedHi);
9660 };
9661 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9662 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9663 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9665 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9666 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9668 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9669 }
9671 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9672 ///
9673 /// This routine breaks down the specific type of 128-bit shuffle and
9674 /// dispatches to the lowering routines accordingly.
9675 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9676 MVT VT, const X86Subtarget *Subtarget,
9677 SelectionDAG &DAG) {
9678 switch (VT.SimpleTy) {
9679 case MVT::v2i64:
9680 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9681 case MVT::v2f64:
9682 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9683 case MVT::v4i32:
9684 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9685 case MVT::v4f32:
9686 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9687 case MVT::v8i16:
9688 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9689 case MVT::v16i8:
9690 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9692 default:
9693 llvm_unreachable("Unimplemented!");
9694 }
9695 }
9697 /// \brief Helper function to test whether a shuffle mask could be
9698 /// simplified by widening the elements being shuffled.
9699 ///
9700 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9701 /// leaves it in an unspecified state.
9702 ///
9703 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9704 /// shuffle masks. The latter have the special property of a '-2' representing
9705 /// a zero-ed lane of a vector.
9706 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9707 SmallVectorImpl<int> &WidenedMask) {
9708 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9709 // If both elements are undef, its trivial.
9710 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9711 WidenedMask.push_back(SM_SentinelUndef);
9712 continue;
9713 }
9715 // Check for an undef mask and a mask value properly aligned to fit with
9716 // a pair of values. If we find such a case, use the non-undef mask's value.
9717 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9718 WidenedMask.push_back(Mask[i + 1] / 2);
9719 continue;
9720 }
9721 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9722 WidenedMask.push_back(Mask[i] / 2);
9723 continue;
9724 }
9726 // When zeroing, we need to spread the zeroing across both lanes to widen.
9727 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9728 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9729 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9730 WidenedMask.push_back(SM_SentinelZero);
9731 continue;
9732 }
9733 return false;
9734 }
9736 // Finally check if the two mask values are adjacent and aligned with
9737 // a pair.
9738 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9739 WidenedMask.push_back(Mask[i] / 2);
9740 continue;
9741 }
9743 // Otherwise we can't safely widen the elements used in this shuffle.
9744 return false;
9745 }
9746 assert(WidenedMask.size() == Mask.size() / 2 &&
9747 "Incorrect size of mask after widening the elements!");
9749 return true;
9750 }
9752 /// \brief Generic routine to split ector shuffle into half-sized shuffles.
9753 ///
9754 /// This routine just extracts two subvectors, shuffles them independently, and
9755 /// then concatenates them back together. This should work effectively with all
9756 /// AVX vector shuffle types.
9757 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9758 SDValue V2, ArrayRef<int> Mask,
9759 SelectionDAG &DAG) {
9760 assert(VT.getSizeInBits() >= 256 &&
9761 "Only for 256-bit or wider vector shuffles!");
9762 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9763 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9765 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9766 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9768 int NumElements = VT.getVectorNumElements();
9769 int SplitNumElements = NumElements / 2;
9770 MVT ScalarVT = VT.getScalarType();
9771 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9773 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9774 DAG.getIntPtrConstant(0));
9775 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9776 DAG.getIntPtrConstant(SplitNumElements));
9777 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9778 DAG.getIntPtrConstant(0));
9779 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9780 DAG.getIntPtrConstant(SplitNumElements));
9782 // Now create two 4-way blends of these half-width vectors.
9783 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9784 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9785 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9786 for (int i = 0; i < SplitNumElements; ++i) {
9787 int M = HalfMask[i];
9788 if (M >= NumElements) {
9789 if (M >= NumElements + SplitNumElements)
9790 UseHiV2 = true;
9791 else
9792 UseLoV2 = true;
9793 V2BlendMask.push_back(M - NumElements);
9794 V1BlendMask.push_back(-1);
9795 BlendMask.push_back(SplitNumElements + i);
9796 } else if (M >= 0) {
9797 if (M >= SplitNumElements)
9798 UseHiV1 = true;
9799 else
9800 UseLoV1 = true;
9801 V2BlendMask.push_back(-1);
9802 V1BlendMask.push_back(M);
9803 BlendMask.push_back(i);
9804 } else {
9805 V2BlendMask.push_back(-1);
9806 V1BlendMask.push_back(-1);
9807 BlendMask.push_back(-1);
9808 }
9809 }
9811 // Because the lowering happens after all combining takes place, we need to
9812 // manually combine these blend masks as much as possible so that we create
9813 // a minimal number of high-level vector shuffle nodes.
9815 // First try just blending the halves of V1 or V2.
9816 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9817 return DAG.getUNDEF(SplitVT);
9818 if (!UseLoV2 && !UseHiV2)
9819 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9820 if (!UseLoV1 && !UseHiV1)
9821 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9823 SDValue V1Blend, V2Blend;
9824 if (UseLoV1 && UseHiV1) {
9825 V1Blend =
9826 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9827 } else {
9828 // We only use half of V1 so map the usage down into the final blend mask.
9829 V1Blend = UseLoV1 ? LoV1 : HiV1;
9830 for (int i = 0; i < SplitNumElements; ++i)
9831 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9832 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9833 }
9834 if (UseLoV2 && UseHiV2) {
9835 V2Blend =
9836 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9837 } else {
9838 // We only use half of V2 so map the usage down into the final blend mask.
9839 V2Blend = UseLoV2 ? LoV2 : HiV2;
9840 for (int i = 0; i < SplitNumElements; ++i)
9841 if (BlendMask[i] >= SplitNumElements)
9842 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9843 }
9844 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9845 };
9846 SDValue Lo = HalfBlend(LoMask);
9847 SDValue Hi = HalfBlend(HiMask);
9848 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9849 }
9851 /// \brief Either split a vector in halves or decompose the shuffles and the
9852 /// blend.
9853 ///
9854 /// This is provided as a good fallback for many lowerings of non-single-input
9855 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9856 /// between splitting the shuffle into 128-bit components and stitching those
9857 /// back together vs. extracting the single-input shuffles and blending those
9858 /// results.
9859 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9860 SDValue V2, ArrayRef<int> Mask,
9861 SelectionDAG &DAG) {
9862 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9863 "lower single-input shuffles as it "
9864 "could then recurse on itself.");
9865 int Size = Mask.size();
9867 // If this can be modeled as a broadcast of two elements followed by a blend,
9868 // prefer that lowering. This is especially important because broadcasts can
9869 // often fold with memory operands.
9870 auto DoBothBroadcast = [&] {
9871 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9872 for (int M : Mask)
9873 if (M >= Size) {
9874 if (V2BroadcastIdx == -1)
9875 V2BroadcastIdx = M - Size;
9876 else if (M - Size != V2BroadcastIdx)
9877 return false;
9878 } else if (M >= 0) {
9879 if (V1BroadcastIdx == -1)
9880 V1BroadcastIdx = M;
9881 else if (M != V1BroadcastIdx)
9882 return false;
9883 }
9884 return true;
9885 };
9886 if (DoBothBroadcast())
9887 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9888 DAG);
9890 // If the inputs all stem from a single 128-bit lane of each input, then we
9891 // split them rather than blending because the split will decompose to
9892 // unusually few instructions.
9893 int LaneCount = VT.getSizeInBits() / 128;
9894 int LaneSize = Size / LaneCount;
9895 SmallBitVector LaneInputs[2];
9896 LaneInputs[0].resize(LaneCount, false);
9897 LaneInputs[1].resize(LaneCount, false);
9898 for (int i = 0; i < Size; ++i)
9899 if (Mask[i] >= 0)
9900 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9901 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9902 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9904 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9905 // that the decomposed single-input shuffles don't end up here.
9906 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9907 }
9909 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9910 /// a permutation and blend of those lanes.
9911 ///
9912 /// This essentially blends the out-of-lane inputs to each lane into the lane
9913 /// from a permuted copy of the vector. This lowering strategy results in four
9914 /// instructions in the worst case for a single-input cross lane shuffle which
9915 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9916 /// of. Special cases for each particular shuffle pattern should be handled
9917 /// prior to trying this lowering.
9918 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9919 SDValue V1, SDValue V2,
9920 ArrayRef<int> Mask,
9921 SelectionDAG &DAG) {
9922 // FIXME: This should probably be generalized for 512-bit vectors as well.
9923 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9924 int LaneSize = Mask.size() / 2;
9926 // If there are only inputs from one 128-bit lane, splitting will in fact be
9927 // less expensive. The flags track wether the given lane contains an element
9928 // that crosses to another lane.
9929 bool LaneCrossing[2] = {false, false};
9930 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9931 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9932 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9933 if (!LaneCrossing[0] || !LaneCrossing[1])
9934 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9936 if (isSingleInputShuffleMask(Mask)) {
9937 SmallVector<int, 32> FlippedBlendMask;
9938 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9939 FlippedBlendMask.push_back(
9940 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9941 ? Mask[i]
9942 : Mask[i] % LaneSize +
9943 (i / LaneSize) * LaneSize + Size));
9945 // Flip the vector, and blend the results which should now be in-lane. The
9946 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9947 // 5 for the high source. The value 3 selects the high half of source 2 and
9948 // the value 2 selects the low half of source 2. We only use source 2 to
9949 // allow folding it into a memory operand.
9950 unsigned PERMMask = 3 | 2 << 4;
9951 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9952 V1, DAG.getConstant(PERMMask, MVT::i8));
9953 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9954 }
9956 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9957 // will be handled by the above logic and a blend of the results, much like
9958 // other patterns in AVX.
9959 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9960 }
9962 /// \brief Handle lowering 2-lane 128-bit shuffles.
9963 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9964 SDValue V2, ArrayRef<int> Mask,
9965 const X86Subtarget *Subtarget,
9966 SelectionDAG &DAG) {
9967 // Blends are faster and handle all the non-lane-crossing cases.
9968 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9969 Subtarget, DAG))
9970 return Blend;
9972 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9973 VT.getVectorNumElements() / 2);
9974 // Check for patterns which can be matched with a single insert of a 128-bit
9975 // subvector.
9976 if (isShuffleEquivalent(Mask, 0, 1, 0, 1) ||
9977 isShuffleEquivalent(Mask, 0, 1, 4, 5)) {
9978 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9979 DAG.getIntPtrConstant(0));
9980 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9981 Mask[2] < 4 ? V1 : V2, DAG.getIntPtrConstant(0));
9982 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9983 }
9984 if (isShuffleEquivalent(Mask, 0, 1, 6, 7)) {
9985 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9986 DAG.getIntPtrConstant(0));
9987 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V2,
9988 DAG.getIntPtrConstant(2));
9989 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9990 }
9992 // Otherwise form a 128-bit permutation.
9993 // FIXME: Detect zero-vector inputs and use the VPERM2X128 to zero that half.
9994 unsigned PermMask = Mask[0] / 2 | (Mask[2] / 2) << 4;
9995 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9996 DAG.getConstant(PermMask, MVT::i8));
9997 }
9999 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
10000 /// shuffling each lane.
10001 ///
10002 /// This will only succeed when the result of fixing the 128-bit lanes results
10003 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
10004 /// each 128-bit lanes. This handles many cases where we can quickly blend away
10005 /// the lane crosses early and then use simpler shuffles within each lane.
10006 ///
10007 /// FIXME: It might be worthwhile at some point to support this without
10008 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
10009 /// in x86 only floating point has interesting non-repeating shuffles, and even
10010 /// those are still *marginally* more expensive.
10011 static SDValue lowerVectorShuffleByMerging128BitLanes(
10012 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
10013 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
10014 assert(!isSingleInputShuffleMask(Mask) &&
10015 "This is only useful with multiple inputs.");
10017 int Size = Mask.size();
10018 int LaneSize = 128 / VT.getScalarSizeInBits();
10019 int NumLanes = Size / LaneSize;
10020 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10022 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10023 // check whether the in-128-bit lane shuffles share a repeating pattern.
10024 SmallVector<int, 4> Lanes;
10025 Lanes.resize(NumLanes, -1);
10026 SmallVector<int, 4> InLaneMask;
10027 InLaneMask.resize(LaneSize, -1);
10028 for (int i = 0; i < Size; ++i) {
10029 if (Mask[i] < 0)
10030 continue;
10032 int j = i / LaneSize;
10034 if (Lanes[j] < 0) {
10035 // First entry we've seen for this lane.
10036 Lanes[j] = Mask[i] / LaneSize;
10037 } else if (Lanes[j] != Mask[i] / LaneSize) {
10038 // This doesn't match the lane selected previously!
10039 return SDValue();
10040 }
10042 // Check that within each lane we have a consistent shuffle mask.
10043 int k = i % LaneSize;
10044 if (InLaneMask[k] < 0) {
10045 InLaneMask[k] = Mask[i] % LaneSize;
10046 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10047 // This doesn't fit a repeating in-lane mask.
10048 return SDValue();
10049 }
10050 }
10052 // First shuffle the lanes into place.
10053 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10054 VT.getSizeInBits() / 64);
10055 SmallVector<int, 8> LaneMask;
10056 LaneMask.resize(NumLanes * 2, -1);
10057 for (int i = 0; i < NumLanes; ++i)
10058 if (Lanes[i] >= 0) {
10059 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10060 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10061 }
10063 V1 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V1);
10064 V2 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V2);
10065 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10067 // Cast it back to the type we actually want.
10068 LaneShuffle = DAG.getNode(ISD::BITCAST, DL, VT, LaneShuffle);
10070 // Now do a simple shuffle that isn't lane crossing.
10071 SmallVector<int, 8> NewMask;
10072 NewMask.resize(Size, -1);
10073 for (int i = 0; i < Size; ++i)
10074 if (Mask[i] >= 0)
10075 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10076 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10077 "Must not introduce lane crosses at this point!");
10079 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10080 }
10082 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10083 /// given mask.
10084 ///
10085 /// This returns true if the elements from a particular input are already in the
10086 /// slot required by the given mask and require no permutation.
10087 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10088 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10089 int Size = Mask.size();
10090 for (int i = 0; i < Size; ++i)
10091 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10092 return false;
10094 return true;
10095 }
10097 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10098 ///
10099 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10100 /// isn't available.
10101 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10102 const X86Subtarget *Subtarget,
10103 SelectionDAG &DAG) {
10104 SDLoc DL(Op);
10105 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10106 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10107 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10108 ArrayRef<int> Mask = SVOp->getMask();
10109 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10111 SmallVector<int, 4> WidenedMask;
10112 if (canWidenShuffleElements(Mask, WidenedMask))
10113 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10114 DAG);
10116 if (isSingleInputShuffleMask(Mask)) {
10117 // Check for being able to broadcast a single element.
10118 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f64, DL, V1,
10119 Mask, Subtarget, DAG))
10120 return Broadcast;
10122 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10123 // Non-half-crossing single input shuffles can be lowerid with an
10124 // interleaved permutation.
10125 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10126 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10127 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10128 DAG.getConstant(VPERMILPMask, MVT::i8));
10129 }
10131 // With AVX2 we have direct support for this permutation.
10132 if (Subtarget->hasAVX2())
10133 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10134 getV4X86ShuffleImm8ForMask(Mask, DAG));
10136 // Otherwise, fall back.
10137 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10138 DAG);
10139 }
10141 // X86 has dedicated unpack instructions that can handle specific blend
10142 // operations: UNPCKH and UNPCKL.
10143 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10144 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
10145 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10146 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
10148 // If we have a single input to the zero element, insert that into V1 if we
10149 // can do so cheaply.
10150 int NumV2Elements =
10151 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
10152 if (NumV2Elements == 1 && Mask[0] >= 4)
10153 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10154 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
10155 return Insertion;
10157 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10158 Subtarget, DAG))
10159 return Blend;
10161 // Check if the blend happens to exactly fit that of SHUFPD.
10162 if ((Mask[0] == -1 || Mask[0] < 2) &&
10163 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
10164 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
10165 (Mask[3] == -1 || Mask[3] >= 6)) {
10166 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
10167 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
10168 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
10169 DAG.getConstant(SHUFPDMask, MVT::i8));
10170 }
10171 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
10172 (Mask[1] == -1 || Mask[1] < 2) &&
10173 (Mask[2] == -1 || Mask[2] >= 6) &&
10174 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
10175 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
10176 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
10177 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
10178 DAG.getConstant(SHUFPDMask, MVT::i8));
10179 }
10181 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10182 // shuffle. However, if we have AVX2 and either inputs are already in place,
10183 // we will be able to shuffle even across lanes the other input in a single
10184 // instruction so skip this pattern.
10185 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10186 isShuffleMaskInputInPlace(1, Mask))))
10187 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10188 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10189 return Result;
10191 // If we have AVX2 then we always want to lower with a blend because an v4 we
10192 // can fully permute the elements.
10193 if (Subtarget->hasAVX2())
10194 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10195 Mask, DAG);
10197 // Otherwise fall back on generic lowering.
10198 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10199 }
10201 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10202 ///
10203 /// This routine is only called when we have AVX2 and thus a reasonable
10204 /// instruction set for v4i64 shuffling..
10205 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10206 const X86Subtarget *Subtarget,
10207 SelectionDAG &DAG) {
10208 SDLoc DL(Op);
10209 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10210 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10211 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10212 ArrayRef<int> Mask = SVOp->getMask();
10213 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10214 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10216 SmallVector<int, 4> WidenedMask;
10217 if (canWidenShuffleElements(Mask, WidenedMask))
10218 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10219 DAG);
10221 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10222 Subtarget, DAG))
10223 return Blend;
10225 // Check for being able to broadcast a single element.
10226 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i64, DL, V1,
10227 Mask, Subtarget, DAG))
10228 return Broadcast;
10230 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10231 // use lower latency instructions that will operate on both 128-bit lanes.
10232 SmallVector<int, 2> RepeatedMask;
10233 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10234 if (isSingleInputShuffleMask(Mask)) {
10235 int PSHUFDMask[] = {-1, -1, -1, -1};
10236 for (int i = 0; i < 2; ++i)
10237 if (RepeatedMask[i] >= 0) {
10238 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10239 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10240 }
10241 return DAG.getNode(
10242 ISD::BITCAST, DL, MVT::v4i64,
10243 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10244 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
10245 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
10246 }
10248 // Use dedicated unpack instructions for masks that match their pattern.
10249 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10250 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
10251 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10252 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
10253 }
10255 // AVX2 provides a direct instruction for permuting a single input across
10256 // lanes.
10257 if (isSingleInputShuffleMask(Mask))
10258 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10259 getV4X86ShuffleImm8ForMask(Mask, DAG));
10261 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10262 // shuffle. However, if we have AVX2 and either inputs are already in place,
10263 // we will be able to shuffle even across lanes the other input in a single
10264 // instruction so skip this pattern.
10265 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10266 isShuffleMaskInputInPlace(1, Mask))))
10267 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10268 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10269 return Result;
10271 // Otherwise fall back on generic blend lowering.
10272 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10273 Mask, DAG);
10274 }
10276 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10277 ///
10278 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10279 /// isn't available.
10280 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10281 const X86Subtarget *Subtarget,
10282 SelectionDAG &DAG) {
10283 SDLoc DL(Op);
10284 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10285 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10286 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10287 ArrayRef<int> Mask = SVOp->getMask();
10288 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10290 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10291 Subtarget, DAG))
10292 return Blend;
10294 // Check for being able to broadcast a single element.
10295 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8f32, DL, V1,
10296 Mask, Subtarget, DAG))
10297 return Broadcast;
10299 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10300 // options to efficiently lower the shuffle.
10301 SmallVector<int, 4> RepeatedMask;
10302 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10303 assert(RepeatedMask.size() == 4 &&
10304 "Repeated masks must be half the mask width!");
10305 if (isSingleInputShuffleMask(Mask))
10306 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10307 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10309 // Use dedicated unpack instructions for masks that match their pattern.
10310 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10311 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
10312 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10313 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
10315 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10316 // have already handled any direct blends. We also need to squash the
10317 // repeated mask into a simulated v4f32 mask.
10318 for (int i = 0; i < 4; ++i)
10319 if (RepeatedMask[i] >= 8)
10320 RepeatedMask[i] -= 4;
10321 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10322 }
10324 // If we have a single input shuffle with different shuffle patterns in the
10325 // two 128-bit lanes use the variable mask to VPERMILPS.
10326 if (isSingleInputShuffleMask(Mask)) {
10327 SDValue VPermMask[8];
10328 for (int i = 0; i < 8; ++i)
10329 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10330 : DAG.getConstant(Mask[i], MVT::i32);
10331 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10332 return DAG.getNode(
10333 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10334 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10336 if (Subtarget->hasAVX2())
10337 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
10338 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
10339 DAG.getNode(ISD::BUILD_VECTOR, DL,
10340 MVT::v8i32, VPermMask)),
10341 V1);
10343 // Otherwise, fall back.
10344 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10345 DAG);
10346 }
10348 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10349 // shuffle.
10350 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10351 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10352 return Result;
10354 // If we have AVX2 then we always want to lower with a blend because at v8 we
10355 // can fully permute the elements.
10356 if (Subtarget->hasAVX2())
10357 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10358 Mask, DAG);
10360 // Otherwise fall back on generic lowering.
10361 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10362 }
10364 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10365 ///
10366 /// This routine is only called when we have AVX2 and thus a reasonable
10367 /// instruction set for v8i32 shuffling..
10368 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10369 const X86Subtarget *Subtarget,
10370 SelectionDAG &DAG) {
10371 SDLoc DL(Op);
10372 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10373 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10374 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10375 ArrayRef<int> Mask = SVOp->getMask();
10376 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10377 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10379 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10380 Subtarget, DAG))
10381 return Blend;
10383 // Check for being able to broadcast a single element.
10384 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i32, DL, V1,
10385 Mask, Subtarget, DAG))
10386 return Broadcast;
10388 // If the shuffle mask is repeated in each 128-bit lane we can use more
10389 // efficient instructions that mirror the shuffles across the two 128-bit
10390 // lanes.
10391 SmallVector<int, 4> RepeatedMask;
10392 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10393 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10394 if (isSingleInputShuffleMask(Mask))
10395 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10396 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10398 // Use dedicated unpack instructions for masks that match their pattern.
10399 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10400 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10401 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10402 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10403 }
10405 // If the shuffle patterns aren't repeated but it is a single input, directly
10406 // generate a cross-lane VPERMD instruction.
10407 if (isSingleInputShuffleMask(Mask)) {
10408 SDValue VPermMask[8];
10409 for (int i = 0; i < 8; ++i)
10410 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10411 : DAG.getConstant(Mask[i], MVT::i32);
10412 return DAG.getNode(
10413 X86ISD::VPERMV, DL, MVT::v8i32,
10414 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10415 }
10417 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10418 // shuffle.
10419 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10420 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10421 return Result;
10423 // Otherwise fall back on generic blend lowering.
10424 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10425 Mask, DAG);
10426 }
10428 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10429 ///
10430 /// This routine is only called when we have AVX2 and thus a reasonable
10431 /// instruction set for v16i16 shuffling..
10432 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10433 const X86Subtarget *Subtarget,
10434 SelectionDAG &DAG) {
10435 SDLoc DL(Op);
10436 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10437 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10438 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10439 ArrayRef<int> Mask = SVOp->getMask();
10440 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10441 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10443 // Check for being able to broadcast a single element.
10444 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i16, DL, V1,
10445 Mask, Subtarget, DAG))
10446 return Broadcast;
10448 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10449 Subtarget, DAG))
10450 return Blend;
10452 // Use dedicated unpack instructions for masks that match their pattern.
10453 if (isShuffleEquivalent(Mask,
10454 // First 128-bit lane:
10455 0, 16, 1, 17, 2, 18, 3, 19,
10456 // Second 128-bit lane:
10457 8, 24, 9, 25, 10, 26, 11, 27))
10458 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10459 if (isShuffleEquivalent(Mask,
10460 // First 128-bit lane:
10461 4, 20, 5, 21, 6, 22, 7, 23,
10462 // Second 128-bit lane:
10463 12, 28, 13, 29, 14, 30, 15, 31))
10464 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10466 if (isSingleInputShuffleMask(Mask)) {
10467 // There are no generalized cross-lane shuffle operations available on i16
10468 // element types.
10469 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10470 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10471 Mask, DAG);
10473 SDValue PSHUFBMask[32];
10474 for (int i = 0; i < 16; ++i) {
10475 if (Mask[i] == -1) {
10476 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10477 continue;
10478 }
10480 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10481 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10482 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
10483 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
10484 }
10485 return DAG.getNode(
10486 ISD::BITCAST, DL, MVT::v16i16,
10487 DAG.getNode(
10488 X86ISD::PSHUFB, DL, MVT::v32i8,
10489 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
10490 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
10491 }
10493 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10494 // shuffle.
10495 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10496 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10497 return Result;
10499 // Otherwise fall back on generic lowering.
10500 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10501 }
10503 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10504 ///
10505 /// This routine is only called when we have AVX2 and thus a reasonable
10506 /// instruction set for v32i8 shuffling..
10507 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10508 const X86Subtarget *Subtarget,
10509 SelectionDAG &DAG) {
10510 SDLoc DL(Op);
10511 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10512 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10513 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10514 ArrayRef<int> Mask = SVOp->getMask();
10515 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10516 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10518 // Check for being able to broadcast a single element.
10519 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v32i8, DL, V1,
10520 Mask, Subtarget, DAG))
10521 return Broadcast;
10523 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10524 Subtarget, DAG))
10525 return Blend;
10527 // Use dedicated unpack instructions for masks that match their pattern.
10528 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10529 // 256-bit lanes.
10530 if (isShuffleEquivalent(
10531 Mask,
10532 // First 128-bit lane:
10533 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10534 // Second 128-bit lane:
10535 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
10536 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10537 if (isShuffleEquivalent(
10538 Mask,
10539 // First 128-bit lane:
10540 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10541 // Second 128-bit lane:
10542 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
10543 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10545 if (isSingleInputShuffleMask(Mask)) {
10546 // There are no generalized cross-lane shuffle operations available on i8
10547 // element types.
10548 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10549 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10550 Mask, DAG);
10552 SDValue PSHUFBMask[32];
10553 for (int i = 0; i < 32; ++i)
10554 PSHUFBMask[i] =
10555 Mask[i] < 0
10556 ? DAG.getUNDEF(MVT::i8)
10557 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
10559 return DAG.getNode(
10560 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10561 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10562 }
10564 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10565 // shuffle.
10566 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10567 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10568 return Result;
10570 // Otherwise fall back on generic lowering.
10571 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10572 }
10574 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10575 ///
10576 /// This routine either breaks down the specific type of a 256-bit x86 vector
10577 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10578 /// together based on the available instructions.
10579 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10580 MVT VT, const X86Subtarget *Subtarget,
10581 SelectionDAG &DAG) {
10582 SDLoc DL(Op);
10583 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10584 ArrayRef<int> Mask = SVOp->getMask();
10586 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10587 // check for those subtargets here and avoid much of the subtarget querying in
10588 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10589 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10590 // floating point types there eventually, just immediately cast everything to
10591 // a float and operate entirely in that domain.
10592 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10593 int ElementBits = VT.getScalarSizeInBits();
10594 if (ElementBits < 32)
10595 // No floating point type available, decompose into 128-bit vectors.
10596 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10598 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10599 VT.getVectorNumElements());
10600 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
10601 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
10602 return DAG.getNode(ISD::BITCAST, DL, VT,
10603 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10604 }
10606 switch (VT.SimpleTy) {
10607 case MVT::v4f64:
10608 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10609 case MVT::v4i64:
10610 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10611 case MVT::v8f32:
10612 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10613 case MVT::v8i32:
10614 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10615 case MVT::v16i16:
10616 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10617 case MVT::v32i8:
10618 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10620 default:
10621 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10622 }
10623 }
10625 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10626 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10627 const X86Subtarget *Subtarget,
10628 SelectionDAG &DAG) {
10629 SDLoc DL(Op);
10630 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10631 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10632 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10633 ArrayRef<int> Mask = SVOp->getMask();
10634 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10636 // FIXME: Implement direct support for this type!
10637 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10638 }
10640 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10641 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10642 const X86Subtarget *Subtarget,
10643 SelectionDAG &DAG) {
10644 SDLoc DL(Op);
10645 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10646 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10647 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10648 ArrayRef<int> Mask = SVOp->getMask();
10649 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10651 // FIXME: Implement direct support for this type!
10652 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10653 }
10655 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10656 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10657 const X86Subtarget *Subtarget,
10658 SelectionDAG &DAG) {
10659 SDLoc DL(Op);
10660 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10661 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10662 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10663 ArrayRef<int> Mask = SVOp->getMask();
10664 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10666 // FIXME: Implement direct support for this type!
10667 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10668 }
10670 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10671 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10672 const X86Subtarget *Subtarget,
10673 SelectionDAG &DAG) {
10674 SDLoc DL(Op);
10675 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10676 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10677 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10678 ArrayRef<int> Mask = SVOp->getMask();
10679 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10681 // FIXME: Implement direct support for this type!
10682 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10683 }
10685 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10686 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10687 const X86Subtarget *Subtarget,
10688 SelectionDAG &DAG) {
10689 SDLoc DL(Op);
10690 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10691 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10692 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10693 ArrayRef<int> Mask = SVOp->getMask();
10694 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10695 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10697 // FIXME: Implement direct support for this type!
10698 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10699 }
10701 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10702 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10703 const X86Subtarget *Subtarget,
10704 SelectionDAG &DAG) {
10705 SDLoc DL(Op);
10706 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10707 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10708 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10709 ArrayRef<int> Mask = SVOp->getMask();
10710 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10711 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10713 // FIXME: Implement direct support for this type!
10714 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10715 }
10717 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10718 ///
10719 /// This routine either breaks down the specific type of a 512-bit x86 vector
10720 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10721 /// together based on the available instructions.
10722 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10723 MVT VT, const X86Subtarget *Subtarget,
10724 SelectionDAG &DAG) {
10725 SDLoc DL(Op);
10726 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10727 ArrayRef<int> Mask = SVOp->getMask();
10728 assert(Subtarget->hasAVX512() &&
10729 "Cannot lower 512-bit vectors w/ basic ISA!");
10731 // Check for being able to broadcast a single element.
10732 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(VT.SimpleTy, DL, V1,
10733 Mask, Subtarget, DAG))
10734 return Broadcast;
10736 // Dispatch to each element type for lowering. If we don't have supprot for
10737 // specific element type shuffles at 512 bits, immediately split them and
10738 // lower them. Each lowering routine of a given type is allowed to assume that
10739 // the requisite ISA extensions for that element type are available.
10740 switch (VT.SimpleTy) {
10741 case MVT::v8f64:
10742 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10743 case MVT::v16f32:
10744 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10745 case MVT::v8i64:
10746 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10747 case MVT::v16i32:
10748 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10749 case MVT::v32i16:
10750 if (Subtarget->hasBWI())
10751 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10752 break;
10753 case MVT::v64i8:
10754 if (Subtarget->hasBWI())
10755 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10756 break;
10758 default:
10759 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10760 }
10762 // Otherwise fall back on splitting.
10763 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10764 }
10766 /// \brief Top-level lowering for x86 vector shuffles.
10767 ///
10768 /// This handles decomposition, canonicalization, and lowering of all x86
10769 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10770 /// above in helper routines. The canonicalization attempts to widen shuffles
10771 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10772 /// s.t. only one of the two inputs needs to be tested, etc.
10773 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10774 SelectionDAG &DAG) {
10775 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10776 ArrayRef<int> Mask = SVOp->getMask();
10777 SDValue V1 = Op.getOperand(0);
10778 SDValue V2 = Op.getOperand(1);
10779 MVT VT = Op.getSimpleValueType();
10780 int NumElements = VT.getVectorNumElements();
10781 SDLoc dl(Op);
10783 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10785 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10786 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10787 if (V1IsUndef && V2IsUndef)
10788 return DAG.getUNDEF(VT);
10790 // When we create a shuffle node we put the UNDEF node to second operand,
10791 // but in some cases the first operand may be transformed to UNDEF.
10792 // In this case we should just commute the node.
10793 if (V1IsUndef)
10794 return DAG.getCommutedVectorShuffle(*SVOp);
10796 // Check for non-undef masks pointing at an undef vector and make the masks
10797 // undef as well. This makes it easier to match the shuffle based solely on
10798 // the mask.
10799 if (V2IsUndef)
10800 for (int M : Mask)
10801 if (M >= NumElements) {
10802 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10803 for (int &M : NewMask)
10804 if (M >= NumElements)
10805 M = -1;
10806 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10807 }
10809 // Try to collapse shuffles into using a vector type with fewer elements but
10810 // wider element types. We cap this to not form integers or floating point
10811 // elements wider than 64 bits, but it might be interesting to form i128
10812 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10813 SmallVector<int, 16> WidenedMask;
10814 if (VT.getScalarSizeInBits() < 64 &&
10815 canWidenShuffleElements(Mask, WidenedMask)) {
10816 MVT NewEltVT = VT.isFloatingPoint()
10817 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10818 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10819 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10820 // Make sure that the new vector type is legal. For example, v2f64 isn't
10821 // legal on SSE1.
10822 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10823 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10824 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10825 return DAG.getNode(ISD::BITCAST, dl, VT,
10826 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10827 }
10828 }
10830 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10831 for (int M : SVOp->getMask())
10832 if (M < 0)
10833 ++NumUndefElements;
10834 else if (M < NumElements)
10835 ++NumV1Elements;
10836 else
10837 ++NumV2Elements;
10839 // Commute the shuffle as needed such that more elements come from V1 than
10840 // V2. This allows us to match the shuffle pattern strictly on how many
10841 // elements come from V1 without handling the symmetric cases.
10842 if (NumV2Elements > NumV1Elements)
10843 return DAG.getCommutedVectorShuffle(*SVOp);
10845 // When the number of V1 and V2 elements are the same, try to minimize the
10846 // number of uses of V2 in the low half of the vector. When that is tied,
10847 // ensure that the sum of indices for V1 is equal to or lower than the sum
10848 // indices for V2. When those are equal, try to ensure that the number of odd
10849 // indices for V1 is lower than the number of odd indices for V2.
10850 if (NumV1Elements == NumV2Elements) {
10851 int LowV1Elements = 0, LowV2Elements = 0;
10852 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10853 if (M >= NumElements)
10854 ++LowV2Elements;
10855 else if (M >= 0)
10856 ++LowV1Elements;
10857 if (LowV2Elements > LowV1Elements) {
10858 return DAG.getCommutedVectorShuffle(*SVOp);
10859 } else if (LowV2Elements == LowV1Elements) {
10860 int SumV1Indices = 0, SumV2Indices = 0;
10861 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10862 if (SVOp->getMask()[i] >= NumElements)
10863 SumV2Indices += i;
10864 else if (SVOp->getMask()[i] >= 0)
10865 SumV1Indices += i;
10866 if (SumV2Indices < SumV1Indices) {
10867 return DAG.getCommutedVectorShuffle(*SVOp);
10868 } else if (SumV2Indices == SumV1Indices) {
10869 int NumV1OddIndices = 0, NumV2OddIndices = 0;
10870 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10871 if (SVOp->getMask()[i] >= NumElements)
10872 NumV2OddIndices += i % 2;
10873 else if (SVOp->getMask()[i] >= 0)
10874 NumV1OddIndices += i % 2;
10875 if (NumV2OddIndices < NumV1OddIndices)
10876 return DAG.getCommutedVectorShuffle(*SVOp);
10877 }
10878 }
10879 }
10881 // For each vector width, delegate to a specialized lowering routine.
10882 if (VT.getSizeInBits() == 128)
10883 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10885 if (VT.getSizeInBits() == 256)
10886 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10888 // Force AVX-512 vectors to be scalarized for now.
10889 // FIXME: Implement AVX-512 support!
10890 if (VT.getSizeInBits() == 512)
10891 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10893 llvm_unreachable("Unimplemented!");
10894 }
10897 //===----------------------------------------------------------------------===//
10898 // Legacy vector shuffle lowering
10899 //
10900 // This code is the legacy code handling vector shuffles until the above
10901 // replaces its functionality and performance.
10902 //===----------------------------------------------------------------------===//
10904 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
10905 bool hasInt256, unsigned *MaskOut = nullptr) {
10906 MVT EltVT = VT.getVectorElementType();
10908 // There is no blend with immediate in AVX-512.
10909 if (VT.is512BitVector())
10910 return false;
10912 if (!hasSSE41 || EltVT == MVT::i8)
10913 return false;
10914 if (!hasInt256 && VT == MVT::v16i16)
10915 return false;
10917 unsigned MaskValue = 0;
10918 unsigned NumElems = VT.getVectorNumElements();
10919 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10920 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10921 unsigned NumElemsInLane = NumElems / NumLanes;
10923 // Blend for v16i16 should be symetric for the both lanes.
10924 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10926 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
10927 int EltIdx = MaskVals[i];
10929 if ((EltIdx < 0 || EltIdx == (int)i) &&
10930 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
10931 continue;
10933 if (((unsigned)EltIdx == (i + NumElems)) &&
10934 (SndLaneEltIdx < 0 ||
10935 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
10936 MaskValue |= (1 << i);
10937 else
10938 return false;
10939 }
10941 if (MaskOut)
10942 *MaskOut = MaskValue;
10943 return true;
10944 }
10946 // Try to lower a shuffle node into a simple blend instruction.
10947 // This function assumes isBlendMask returns true for this
10948 // SuffleVectorSDNode
10949 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
10950 unsigned MaskValue,
10951 const X86Subtarget *Subtarget,
10952 SelectionDAG &DAG) {
10953 MVT VT = SVOp->getSimpleValueType(0);
10954 MVT EltVT = VT.getVectorElementType();
10955 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
10956 Subtarget->hasInt256() && "Trying to lower a "
10957 "VECTOR_SHUFFLE to a Blend but "
10958 "with the wrong mask"));
10959 SDValue V1 = SVOp->getOperand(0);
10960 SDValue V2 = SVOp->getOperand(1);
10961 SDLoc dl(SVOp);
10962 unsigned NumElems = VT.getVectorNumElements();
10964 // Convert i32 vectors to floating point if it is not AVX2.
10965 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
10966 MVT BlendVT = VT;
10967 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
10968 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
10969 NumElems);
10970 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
10971 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
10972 }
10974 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
10975 DAG.getConstant(MaskValue, MVT::i32));
10976 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
10977 }
10979 /// In vector type \p VT, return true if the element at index \p InputIdx
10980 /// falls on a different 128-bit lane than \p OutputIdx.
10981 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
10982 unsigned OutputIdx) {
10983 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
10984 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
10985 }
10987 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
10988 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
10989 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
10990 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
10991 /// zero.
10992 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
10993 SelectionDAG &DAG) {
10994 MVT VT = V1.getSimpleValueType();
10995 assert(VT.is128BitVector() || VT.is256BitVector());
10997 MVT EltVT = VT.getVectorElementType();
10998 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
10999 unsigned NumElts = VT.getVectorNumElements();
11001 SmallVector<SDValue, 32> PshufbMask;
11002 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
11003 int InputIdx = MaskVals[OutputIdx];
11004 unsigned InputByteIdx;
11006 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
11007 InputByteIdx = 0x80;
11008 else {
11009 // Cross lane is not allowed.
11010 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
11011 return SDValue();
11012 InputByteIdx = InputIdx * EltSizeInBytes;
11013 // Index is an byte offset within the 128-bit lane.
11014 InputByteIdx &= 0xf;
11015 }
11017 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
11018 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
11019 if (InputByteIdx != 0x80)
11020 ++InputByteIdx;
11021 }
11022 }
11024 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
11025 if (ShufVT != VT)
11026 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
11027 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
11028 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
11029 }
11031 // v8i16 shuffles - Prefer shuffles in the following order:
11032 // 1. [all] pshuflw, pshufhw, optional move
11033 // 2. [ssse3] 1 x pshufb
11034 // 3. [ssse3] 2 x pshufb + 1 x por
11035 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
11036 static SDValue
11037 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
11038 SelectionDAG &DAG) {
11039 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11040 SDValue V1 = SVOp->getOperand(0);
11041 SDValue V2 = SVOp->getOperand(1);
11042 SDLoc dl(SVOp);
11043 SmallVector<int, 8> MaskVals;
11045 // Determine if more than 1 of the words in each of the low and high quadwords
11046 // of the result come from the same quadword of one of the two inputs. Undef
11047 // mask values count as coming from any quadword, for better codegen.
11048 //
11049 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
11050 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
11051 unsigned LoQuad[] = { 0, 0, 0, 0 };
11052 unsigned HiQuad[] = { 0, 0, 0, 0 };
11053 // Indices of quads used.
11054 std::bitset<4> InputQuads;
11055 for (unsigned i = 0; i < 8; ++i) {
11056 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
11057 int EltIdx = SVOp->getMaskElt(i);
11058 MaskVals.push_back(EltIdx);
11059 if (EltIdx < 0) {
11060 ++Quad[0];
11061 ++Quad[1];
11062 ++Quad[2];
11063 ++Quad[3];
11064 continue;
11065 }
11066 ++Quad[EltIdx / 4];
11067 InputQuads.set(EltIdx / 4);
11068 }
11070 int BestLoQuad = -1;
11071 unsigned MaxQuad = 1;
11072 for (unsigned i = 0; i < 4; ++i) {
11073 if (LoQuad[i] > MaxQuad) {
11074 BestLoQuad = i;
11075 MaxQuad = LoQuad[i];
11076 }
11077 }
11079 int BestHiQuad = -1;
11080 MaxQuad = 1;
11081 for (unsigned i = 0; i < 4; ++i) {
11082 if (HiQuad[i] > MaxQuad) {
11083 BestHiQuad = i;
11084 MaxQuad = HiQuad[i];
11085 }
11086 }
11088 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
11089 // of the two input vectors, shuffle them into one input vector so only a
11090 // single pshufb instruction is necessary. If there are more than 2 input
11091 // quads, disable the next transformation since it does not help SSSE3.
11092 bool V1Used = InputQuads[0] || InputQuads[1];
11093 bool V2Used = InputQuads[2] || InputQuads[3];
11094 if (Subtarget->hasSSSE3()) {
11095 if (InputQuads.count() == 2 && V1Used && V2Used) {
11096 BestLoQuad = InputQuads[0] ? 0 : 1;
11097 BestHiQuad = InputQuads[2] ? 2 : 3;
11098 }
11099 if (InputQuads.count() > 2) {
11100 BestLoQuad = -1;
11101 BestHiQuad = -1;
11102 }
11103 }
11105 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
11106 // the shuffle mask. If a quad is scored as -1, that means that it contains
11107 // words from all 4 input quadwords.
11108 SDValue NewV;
11109 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
11110 int MaskV[] = {
11111 BestLoQuad < 0 ? 0 : BestLoQuad,
11112 BestHiQuad < 0 ? 1 : BestHiQuad
11113 };
11114 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
11115 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
11116 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
11117 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
11119 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
11120 // source words for the shuffle, to aid later transformations.
11121 bool AllWordsInNewV = true;
11122 bool InOrder[2] = { true, true };
11123 for (unsigned i = 0; i != 8; ++i) {
11124 int idx = MaskVals[i];
11125 if (idx != (int)i)
11126 InOrder[i/4] = false;
11127 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
11128 continue;
11129 AllWordsInNewV = false;
11130 break;
11131 }
11133 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
11134 if (AllWordsInNewV) {
11135 for (int i = 0; i != 8; ++i) {
11136 int idx = MaskVals[i];
11137 if (idx < 0)
11138 continue;
11139 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
11140 if ((idx != i) && idx < 4)
11141 pshufhw = false;
11142 if ((idx != i) && idx > 3)
11143 pshuflw = false;
11144 }
11145 V1 = NewV;
11146 V2Used = false;
11147 BestLoQuad = 0;
11148 BestHiQuad = 1;
11149 }
11151 // If we've eliminated the use of V2, and the new mask is a pshuflw or
11152 // pshufhw, that's as cheap as it gets. Return the new shuffle.
11153 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
11154 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
11155 unsigned TargetMask = 0;
11156 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
11157 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
11158 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11159 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
11160 getShufflePSHUFLWImmediate(SVOp);
11161 V1 = NewV.getOperand(0);
11162 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
11163 }
11164 }
11166 // Promote splats to a larger type which usually leads to more efficient code.
11167 // FIXME: Is this true if pshufb is available?
11168 if (SVOp->isSplat())
11169 return PromoteSplat(SVOp, DAG);
11171 // If we have SSSE3, and all words of the result are from 1 input vector,
11172 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
11173 // is present, fall back to case 4.
11174 if (Subtarget->hasSSSE3()) {
11175 SmallVector<SDValue,16> pshufbMask;
11177 // If we have elements from both input vectors, set the high bit of the
11178 // shuffle mask element to zero out elements that come from V2 in the V1
11179 // mask, and elements that come from V1 in the V2 mask, so that the two
11180 // results can be OR'd together.
11181 bool TwoInputs = V1Used && V2Used;
11182 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
11183 if (!TwoInputs)
11184 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11186 // Calculate the shuffle mask for the second input, shuffle it, and
11187 // OR it with the first shuffled input.
11188 CommuteVectorShuffleMask(MaskVals, 8);
11189 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
11190 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11191 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11192 }
11194 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
11195 // and update MaskVals with new element order.
11196 std::bitset<8> InOrder;
11197 if (BestLoQuad >= 0) {
11198 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
11199 for (int i = 0; i != 4; ++i) {
11200 int idx = MaskVals[i];
11201 if (idx < 0) {
11202 InOrder.set(i);
11203 } else if ((idx / 4) == BestLoQuad) {
11204 MaskV[i] = idx & 3;
11205 InOrder.set(i);
11206 }
11207 }
11208 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11209 &MaskV[0]);
11211 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11212 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11213 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
11214 NewV.getOperand(0),
11215 getShufflePSHUFLWImmediate(SVOp), DAG);
11216 }
11217 }
11219 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
11220 // and update MaskVals with the new element order.
11221 if (BestHiQuad >= 0) {
11222 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
11223 for (unsigned i = 4; i != 8; ++i) {
11224 int idx = MaskVals[i];
11225 if (idx < 0) {
11226 InOrder.set(i);
11227 } else if ((idx / 4) == BestHiQuad) {
11228 MaskV[i] = (idx & 3) + 4;
11229 InOrder.set(i);
11230 }
11231 }
11232 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11233 &MaskV[0]);
11235 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11236 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11237 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
11238 NewV.getOperand(0),
11239 getShufflePSHUFHWImmediate(SVOp), DAG);
11240 }
11241 }
11243 // In case BestHi & BestLo were both -1, which means each quadword has a word
11244 // from each of the four input quadwords, calculate the InOrder bitvector now
11245 // before falling through to the insert/extract cleanup.
11246 if (BestLoQuad == -1 && BestHiQuad == -1) {
11247 NewV = V1;
11248 for (int i = 0; i != 8; ++i)
11249 if (MaskVals[i] < 0 || MaskVals[i] == i)
11250 InOrder.set(i);
11251 }
11253 // The other elements are put in the right place using pextrw and pinsrw.
11254 for (unsigned i = 0; i != 8; ++i) {
11255 if (InOrder[i])
11256 continue;
11257 int EltIdx = MaskVals[i];
11258 if (EltIdx < 0)
11259 continue;
11260 SDValue ExtOp = (EltIdx < 8) ?
11261 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
11262 DAG.getIntPtrConstant(EltIdx)) :
11263 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
11264 DAG.getIntPtrConstant(EltIdx - 8));
11265 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
11266 DAG.getIntPtrConstant(i));
11267 }
11268 return NewV;
11269 }
11271 /// \brief v16i16 shuffles
11272 ///
11273 /// FIXME: We only support generation of a single pshufb currently. We can
11274 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
11275 /// well (e.g 2 x pshufb + 1 x por).
11276 static SDValue
11277 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
11278 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11279 SDValue V1 = SVOp->getOperand(0);
11280 SDValue V2 = SVOp->getOperand(1);
11281 SDLoc dl(SVOp);
11283 if (V2.getOpcode() != ISD::UNDEF)
11284 return SDValue();
11286 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11287 return getPSHUFB(MaskVals, V1, dl, DAG);
11288 }
11290 // v16i8 shuffles - Prefer shuffles in the following order:
11291 // 1. [ssse3] 1 x pshufb
11292 // 2. [ssse3] 2 x pshufb + 1 x por
11293 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
11294 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
11295 const X86Subtarget* Subtarget,
11296 SelectionDAG &DAG) {
11297 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11298 SDValue V1 = SVOp->getOperand(0);
11299 SDValue V2 = SVOp->getOperand(1);
11300 SDLoc dl(SVOp);
11301 ArrayRef<int> MaskVals = SVOp->getMask();
11303 // Promote splats to a larger type which usually leads to more efficient code.
11304 // FIXME: Is this true if pshufb is available?
11305 if (SVOp->isSplat())
11306 return PromoteSplat(SVOp, DAG);
11308 // If we have SSSE3, case 1 is generated when all result bytes come from
11309 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
11310 // present, fall back to case 3.
11312 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
11313 if (Subtarget->hasSSSE3()) {
11314 SmallVector<SDValue,16> pshufbMask;
11316 // If all result elements are from one input vector, then only translate
11317 // undef mask values to 0x80 (zero out result) in the pshufb mask.
11318 //
11319 // Otherwise, we have elements from both input vectors, and must zero out
11320 // elements that come from V2 in the first mask, and V1 in the second mask
11321 // so that we can OR them together.
11322 for (unsigned i = 0; i != 16; ++i) {
11323 int EltIdx = MaskVals[i];
11324 if (EltIdx < 0 || EltIdx >= 16)
11325 EltIdx = 0x80;
11326 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11327 }
11328 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
11329 DAG.getNode(ISD::BUILD_VECTOR, dl,
11330 MVT::v16i8, pshufbMask));
11332 // As PSHUFB will zero elements with negative indices, it's safe to ignore
11333 // the 2nd operand if it's undefined or zero.
11334 if (V2.getOpcode() == ISD::UNDEF ||
11335 ISD::isBuildVectorAllZeros(V2.getNode()))
11336 return V1;
11338 // Calculate the shuffle mask for the second input, shuffle it, and
11339 // OR it with the first shuffled input.
11340 pshufbMask.clear();
11341 for (unsigned i = 0; i != 16; ++i) {
11342 int EltIdx = MaskVals[i];
11343 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
11344 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11345 }
11346 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
11347 DAG.getNode(ISD::BUILD_VECTOR, dl,
11348 MVT::v16i8, pshufbMask));
11349 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11350 }
11352 // No SSSE3 - Calculate in place words and then fix all out of place words
11353 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
11354 // the 16 different words that comprise the two doublequadword input vectors.
11355 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11356 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
11357 SDValue NewV = V1;
11358 for (int i = 0; i != 8; ++i) {
11359 int Elt0 = MaskVals[i*2];
11360 int Elt1 = MaskVals[i*2+1];
11362 // This word of the result is all undef, skip it.
11363 if (Elt0 < 0 && Elt1 < 0)
11364 continue;
11366 // This word of the result is already in the correct place, skip it.
11367 if ((Elt0 == i*2) && (Elt1 == i*2+1))
11368 continue;
11370 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
11371 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
11372 SDValue InsElt;
11374 // If Elt0 and Elt1 are defined, are consecutive, and can be load
11375 // using a single extract together, load it and store it.
11376 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
11377 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11378 DAG.getIntPtrConstant(Elt1 / 2));
11379 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11380 DAG.getIntPtrConstant(i));
11381 continue;
11382 }
11384 // If Elt1 is defined, extract it from the appropriate source. If the
11385 // source byte is not also odd, shift the extracted word left 8 bits
11386 // otherwise clear the bottom 8 bits if we need to do an or.
11387 if (Elt1 >= 0) {
11388 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11389 DAG.getIntPtrConstant(Elt1 / 2));
11390 if ((Elt1 & 1) == 0)
11391 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
11392 DAG.getConstant(8,
11393 TLI.getShiftAmountTy(InsElt.getValueType())));
11394 else if (Elt0 >= 0)
11395 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
11396 DAG.getConstant(0xFF00, MVT::i16));
11397 }
11398 // If Elt0 is defined, extract it from the appropriate source. If the
11399 // source byte is not also even, shift the extracted word right 8 bits. If
11400 // Elt1 was also defined, OR the extracted values together before
11401 // inserting them in the result.
11402 if (Elt0 >= 0) {
11403 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
11404 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
11405 if ((Elt0 & 1) != 0)
11406 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
11407 DAG.getConstant(8,
11408 TLI.getShiftAmountTy(InsElt0.getValueType())));
11409 else if (Elt1 >= 0)
11410 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
11411 DAG.getConstant(0x00FF, MVT::i16));
11412 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
11413 : InsElt0;
11414 }
11415 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11416 DAG.getIntPtrConstant(i));
11417 }
11418 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
11419 }
11421 // v32i8 shuffles - Translate to VPSHUFB if possible.
11422 static
11423 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
11424 const X86Subtarget *Subtarget,
11425 SelectionDAG &DAG) {
11426 MVT VT = SVOp->getSimpleValueType(0);
11427 SDValue V1 = SVOp->getOperand(0);
11428 SDValue V2 = SVOp->getOperand(1);
11429 SDLoc dl(SVOp);
11430 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11432 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11433 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
11434 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
11436 // VPSHUFB may be generated if
11437 // (1) one of input vector is undefined or zeroinitializer.
11438 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
11439 // And (2) the mask indexes don't cross the 128-bit lane.
11440 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
11441 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
11442 return SDValue();
11444 if (V1IsAllZero && !V2IsAllZero) {
11445 CommuteVectorShuffleMask(MaskVals, 32);
11446 V1 = V2;
11447 }
11448 return getPSHUFB(MaskVals, V1, dl, DAG);
11449 }
11451 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
11452 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
11453 /// done when every pair / quad of shuffle mask elements point to elements in
11454 /// the right sequence. e.g.
11455 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
11456 static
11457 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
11458 SelectionDAG &DAG) {
11459 MVT VT = SVOp->getSimpleValueType(0);
11460 SDLoc dl(SVOp);
11461 unsigned NumElems = VT.getVectorNumElements();
11462 MVT NewVT;
11463 unsigned Scale;
11464 switch (VT.SimpleTy) {
11465 default: llvm_unreachable("Unexpected!");
11466 case MVT::v2i64:
11467 case MVT::v2f64:
11468 return SDValue(SVOp, 0);
11469 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
11470 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
11471 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
11472 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
11473 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
11474 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
11475 }
11477 SmallVector<int, 8> MaskVec;
11478 for (unsigned i = 0; i != NumElems; i += Scale) {
11479 int StartIdx = -1;
11480 for (unsigned j = 0; j != Scale; ++j) {
11481 int EltIdx = SVOp->getMaskElt(i+j);
11482 if (EltIdx < 0)
11483 continue;
11484 if (StartIdx < 0)
11485 StartIdx = (EltIdx / Scale);
11486 if (EltIdx != (int)(StartIdx*Scale + j))
11487 return SDValue();
11488 }
11489 MaskVec.push_back(StartIdx);
11490 }
11492 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
11493 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
11494 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
11495 }
11497 /// getVZextMovL - Return a zero-extending vector move low node.
11498 ///
11499 static SDValue getVZextMovL(MVT VT, MVT OpVT,
11500 SDValue SrcOp, SelectionDAG &DAG,
11501 const X86Subtarget *Subtarget, SDLoc dl) {
11502 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
11503 LoadSDNode *LD = nullptr;
11504 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
11505 LD = dyn_cast<LoadSDNode>(SrcOp);
11506 if (!LD) {
11507 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
11508 // instead.
11509 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
11510 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
11511 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
11512 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
11513 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
11514 // PR2108
11515 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
11516 return DAG.getNode(ISD::BITCAST, dl, VT,
11517 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11518 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11519 OpVT,
11520 SrcOp.getOperand(0)
11521 .getOperand(0))));
11522 }
11523 }
11524 }
11526 return DAG.getNode(ISD::BITCAST, dl, VT,
11527 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11528 DAG.getNode(ISD::BITCAST, dl,
11529 OpVT, SrcOp)));
11530 }
11532 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
11533 /// which could not be matched by any known target speficic shuffle
11534 static SDValue
11535 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11537 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
11538 if (NewOp.getNode())
11539 return NewOp;
11541 MVT VT = SVOp->getSimpleValueType(0);
11543 unsigned NumElems = VT.getVectorNumElements();
11544 unsigned NumLaneElems = NumElems / 2;
11546 SDLoc dl(SVOp);
11547 MVT EltVT = VT.getVectorElementType();
11548 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
11549 SDValue Output[2];
11551 SmallVector<int, 16> Mask;
11552 for (unsigned l = 0; l < 2; ++l) {
11553 // Build a shuffle mask for the output, discovering on the fly which
11554 // input vectors to use as shuffle operands (recorded in InputUsed).
11555 // If building a suitable shuffle vector proves too hard, then bail
11556 // out with UseBuildVector set.
11557 bool UseBuildVector = false;
11558 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
11559 unsigned LaneStart = l * NumLaneElems;
11560 for (unsigned i = 0; i != NumLaneElems; ++i) {
11561 // The mask element. This indexes into the input.
11562 int Idx = SVOp->getMaskElt(i+LaneStart);
11563 if (Idx < 0) {
11564 // the mask element does not index into any input vector.
11565 Mask.push_back(-1);
11566 continue;
11567 }
11569 // The input vector this mask element indexes into.
11570 int Input = Idx / NumLaneElems;
11572 // Turn the index into an offset from the start of the input vector.
11573 Idx -= Input * NumLaneElems;
11575 // Find or create a shuffle vector operand to hold this input.
11576 unsigned OpNo;
11577 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
11578 if (InputUsed[OpNo] == Input)
11579 // This input vector is already an operand.
11580 break;
11581 if (InputUsed[OpNo] < 0) {
11582 // Create a new operand for this input vector.
11583 InputUsed[OpNo] = Input;
11584 break;
11585 }
11586 }
11588 if (OpNo >= array_lengthof(InputUsed)) {
11589 // More than two input vectors used! Give up on trying to create a
11590 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
11591 UseBuildVector = true;
11592 break;
11593 }
11595 // Add the mask index for the new shuffle vector.
11596 Mask.push_back(Idx + OpNo * NumLaneElems);
11597 }
11599 if (UseBuildVector) {
11600 SmallVector<SDValue, 16> SVOps;
11601 for (unsigned i = 0; i != NumLaneElems; ++i) {
11602 // The mask element. This indexes into the input.
11603 int Idx = SVOp->getMaskElt(i+LaneStart);
11604 if (Idx < 0) {
11605 SVOps.push_back(DAG.getUNDEF(EltVT));
11606 continue;
11607 }
11609 // The input vector this mask element indexes into.
11610 int Input = Idx / NumElems;
11612 // Turn the index into an offset from the start of the input vector.
11613 Idx -= Input * NumElems;
11615 // Extract the vector element by hand.
11616 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
11617 SVOp->getOperand(Input),
11618 DAG.getIntPtrConstant(Idx)));
11619 }
11621 // Construct the output using a BUILD_VECTOR.
11622 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
11623 } else if (InputUsed[0] < 0) {
11624 // No input vectors were used! The result is undefined.
11625 Output[l] = DAG.getUNDEF(NVT);
11626 } else {
11627 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
11628 (InputUsed[0] % 2) * NumLaneElems,
11629 DAG, dl);
11630 // If only one input was used, use an undefined vector for the other.
11631 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
11632 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
11633 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
11634 // At least one input vector was used. Create a new shuffle vector.
11635 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
11636 }
11638 Mask.clear();
11639 }
11641 // Concatenate the result back
11642 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
11643 }
11645 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
11646 /// 4 elements, and match them with several different shuffle types.
11647 static SDValue
11648 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11649 SDValue V1 = SVOp->getOperand(0);
11650 SDValue V2 = SVOp->getOperand(1);
11651 SDLoc dl(SVOp);
11652 MVT VT = SVOp->getSimpleValueType(0);
11654 assert(VT.is128BitVector() && "Unsupported vector size");
11656 std::pair<int, int> Locs[4];
11657 int Mask1[] = { -1, -1, -1, -1 };
11658 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
11660 unsigned NumHi = 0;
11661 unsigned NumLo = 0;
11662 for (unsigned i = 0; i != 4; ++i) {
11663 int Idx = PermMask[i];
11664 if (Idx < 0) {
11665 Locs[i] = std::make_pair(-1, -1);
11666 } else {
11667 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
11668 if (Idx < 4) {
11669 Locs[i] = std::make_pair(0, NumLo);
11670 Mask1[NumLo] = Idx;
11671 NumLo++;
11672 } else {
11673 Locs[i] = std::make_pair(1, NumHi);
11674 if (2+NumHi < 4)
11675 Mask1[2+NumHi] = Idx;
11676 NumHi++;
11677 }
11678 }
11679 }
11681 if (NumLo <= 2 && NumHi <= 2) {
11682 // If no more than two elements come from either vector. This can be
11683 // implemented with two shuffles. First shuffle gather the elements.
11684 // The second shuffle, which takes the first shuffle as both of its
11685 // vector operands, put the elements into the right order.
11686 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11688 int Mask2[] = { -1, -1, -1, -1 };
11690 for (unsigned i = 0; i != 4; ++i)
11691 if (Locs[i].first != -1) {
11692 unsigned Idx = (i < 2) ? 0 : 4;
11693 Idx += Locs[i].first * 2 + Locs[i].second;
11694 Mask2[i] = Idx;
11695 }
11697 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
11698 }
11700 if (NumLo == 3 || NumHi == 3) {
11701 // Otherwise, we must have three elements from one vector, call it X, and
11702 // one element from the other, call it Y. First, use a shufps to build an
11703 // intermediate vector with the one element from Y and the element from X
11704 // that will be in the same half in the final destination (the indexes don't
11705 // matter). Then, use a shufps to build the final vector, taking the half
11706 // containing the element from Y from the intermediate, and the other half
11707 // from X.
11708 if (NumHi == 3) {
11709 // Normalize it so the 3 elements come from V1.
11710 CommuteVectorShuffleMask(PermMask, 4);
11711 std::swap(V1, V2);
11712 }
11714 // Find the element from V2.
11715 unsigned HiIndex;
11716 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
11717 int Val = PermMask[HiIndex];
11718 if (Val < 0)
11719 continue;
11720 if (Val >= 4)
11721 break;
11722 }
11724 Mask1[0] = PermMask[HiIndex];
11725 Mask1[1] = -1;
11726 Mask1[2] = PermMask[HiIndex^1];
11727 Mask1[3] = -1;
11728 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11730 if (HiIndex >= 2) {
11731 Mask1[0] = PermMask[0];
11732 Mask1[1] = PermMask[1];
11733 Mask1[2] = HiIndex & 1 ? 6 : 4;
11734 Mask1[3] = HiIndex & 1 ? 4 : 6;
11735 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11736 }
11738 Mask1[0] = HiIndex & 1 ? 2 : 0;
11739 Mask1[1] = HiIndex & 1 ? 0 : 2;
11740 Mask1[2] = PermMask[2];
11741 Mask1[3] = PermMask[3];
11742 if (Mask1[2] >= 0)
11743 Mask1[2] += 4;
11744 if (Mask1[3] >= 0)
11745 Mask1[3] += 4;
11746 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
11747 }
11749 // Break it into (shuffle shuffle_hi, shuffle_lo).
11750 int LoMask[] = { -1, -1, -1, -1 };
11751 int HiMask[] = { -1, -1, -1, -1 };
11753 int *MaskPtr = LoMask;
11754 unsigned MaskIdx = 0;
11755 unsigned LoIdx = 0;
11756 unsigned HiIdx = 2;
11757 for (unsigned i = 0; i != 4; ++i) {
11758 if (i == 2) {
11759 MaskPtr = HiMask;
11760 MaskIdx = 1;
11761 LoIdx = 0;
11762 HiIdx = 2;
11763 }
11764 int Idx = PermMask[i];
11765 if (Idx < 0) {
11766 Locs[i] = std::make_pair(-1, -1);
11767 } else if (Idx < 4) {
11768 Locs[i] = std::make_pair(MaskIdx, LoIdx);
11769 MaskPtr[LoIdx] = Idx;
11770 LoIdx++;
11771 } else {
11772 Locs[i] = std::make_pair(MaskIdx, HiIdx);
11773 MaskPtr[HiIdx] = Idx;
11774 HiIdx++;
11775 }
11776 }
11778 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
11779 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
11780 int MaskOps[] = { -1, -1, -1, -1 };
11781 for (unsigned i = 0; i != 4; ++i)
11782 if (Locs[i].first != -1)
11783 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
11784 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
11785 }
11787 static bool MayFoldVectorLoad(SDValue V) {
11788 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
11789 V = V.getOperand(0);
11791 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
11792 V = V.getOperand(0);
11793 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
11794 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
11795 // BUILD_VECTOR (load), undef
11796 V = V.getOperand(0);
11798 return MayFoldLoad(V);
11799 }
11801 static
11802 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
11803 MVT VT = Op.getSimpleValueType();
11805 // Canonizalize to v2f64.
11806 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
11807 return DAG.getNode(ISD::BITCAST, dl, VT,
11808 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
11809 V1, DAG));
11810 }
11812 static
11813 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
11814 bool HasSSE2) {
11815 SDValue V1 = Op.getOperand(0);
11816 SDValue V2 = Op.getOperand(1);
11817 MVT VT = Op.getSimpleValueType();
11819 assert(VT != MVT::v2i64 && "unsupported shuffle type");
11821 if (HasSSE2 && VT == MVT::v2f64)
11822 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
11824 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
11825 return DAG.getNode(ISD::BITCAST, dl, VT,
11826 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
11827 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
11828 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
11829 }
11831 static
11832 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
11833 SDValue V1 = Op.getOperand(0);
11834 SDValue V2 = Op.getOperand(1);
11835 MVT VT = Op.getSimpleValueType();
11837 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
11838 "unsupported shuffle type");
11840 if (V2.getOpcode() == ISD::UNDEF)
11841 V2 = V1;
11843 // v4i32 or v4f32
11844 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
11845 }
11847 static
11848 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
11849 SDValue V1 = Op.getOperand(0);
11850 SDValue V2 = Op.getOperand(1);
11851 MVT VT = Op.getSimpleValueType();
11852 unsigned NumElems = VT.getVectorNumElements();
11854 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
11855 // operand of these instructions is only memory, so check if there's a
11856 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
11857 // same masks.
11858 bool CanFoldLoad = false;
11860 // Trivial case, when V2 comes from a load.
11861 if (MayFoldVectorLoad(V2))
11862 CanFoldLoad = true;
11864 // When V1 is a load, it can be folded later into a store in isel, example:
11865 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
11866 // turns into:
11867 // (MOVLPSmr addr:$src1, VR128:$src2)
11868 // So, recognize this potential and also use MOVLPS or MOVLPD
11869 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
11870 CanFoldLoad = true;
11872 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11873 if (CanFoldLoad) {
11874 if (HasSSE2 && NumElems == 2)
11875 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
11877 if (NumElems == 4)
11878 // If we don't care about the second element, proceed to use movss.
11879 if (SVOp->getMaskElt(1) != -1)
11880 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
11881 }
11883 // movl and movlp will both match v2i64, but v2i64 is never matched by
11884 // movl earlier because we make it strict to avoid messing with the movlp load
11885 // folding logic (see the code above getMOVLP call). Match it here then,
11886 // this is horrible, but will stay like this until we move all shuffle
11887 // matching to x86 specific nodes. Note that for the 1st condition all
11888 // types are matched with movsd.
11889 if (HasSSE2) {
11890 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
11891 // as to remove this logic from here, as much as possible
11892 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
11893 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11894 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11895 }
11897 assert(VT != MVT::v4i32 && "unsupported shuffle type");
11899 // Invert the operand order and use SHUFPS to match it.
11900 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
11901 getShuffleSHUFImmediate(SVOp), DAG);
11902 }
11904 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
11905 SelectionDAG &DAG) {
11906 SDLoc dl(Load);
11907 MVT VT = Load->getSimpleValueType(0);
11908 MVT EVT = VT.getVectorElementType();
11909 SDValue Addr = Load->getOperand(1);
11910 SDValue NewAddr = DAG.getNode(
11911 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
11912 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
11914 SDValue NewLoad =
11915 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
11916 DAG.getMachineFunction().getMachineMemOperand(
11917 Load->getMemOperand(), 0, EVT.getStoreSize()));
11918 return NewLoad;
11919 }
11921 // It is only safe to call this function if isINSERTPSMask is true for
11922 // this shufflevector mask.
11923 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
11924 SelectionDAG &DAG) {
11925 // Generate an insertps instruction when inserting an f32 from memory onto a
11926 // v4f32 or when copying a member from one v4f32 to another.
11927 // We also use it for transferring i32 from one register to another,
11928 // since it simply copies the same bits.
11929 // If we're transferring an i32 from memory to a specific element in a
11930 // register, we output a generic DAG that will match the PINSRD
11931 // instruction.
11932 MVT VT = SVOp->getSimpleValueType(0);
11933 MVT EVT = VT.getVectorElementType();
11934 SDValue V1 = SVOp->getOperand(0);
11935 SDValue V2 = SVOp->getOperand(1);
11936 auto Mask = SVOp->getMask();
11937 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
11938 "unsupported vector type for insertps/pinsrd");
11940 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
11941 auto FromV2Predicate = [](const int &i) { return i >= 4; };
11942 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
11944 SDValue From;
11945 SDValue To;
11946 unsigned DestIndex;
11947 if (FromV1 == 1) {
11948 From = V1;
11949 To = V2;
11950 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
11951 Mask.begin();
11953 // If we have 1 element from each vector, we have to check if we're
11954 // changing V1's element's place. If so, we're done. Otherwise, we
11955 // should assume we're changing V2's element's place and behave
11956 // accordingly.
11957 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
11958 assert(DestIndex <= INT32_MAX && "truncated destination index");
11959 if (FromV1 == FromV2 &&
11960 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
11961 From = V2;
11962 To = V1;
11963 DestIndex =
11964 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11965 }
11966 } else {
11967 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
11968 "More than one element from V1 and from V2, or no elements from one "
11969 "of the vectors. This case should not have returned true from "
11970 "isINSERTPSMask");
11971 From = V2;
11972 To = V1;
11973 DestIndex =
11974 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11975 }
11977 // Get an index into the source vector in the range [0,4) (the mask is
11978 // in the range [0,8) because it can address V1 and V2)
11979 unsigned SrcIndex = Mask[DestIndex] % 4;
11980 if (MayFoldLoad(From)) {
11981 // Trivial case, when From comes from a load and is only used by the
11982 // shuffle. Make it use insertps from the vector that we need from that
11983 // load.
11984 SDValue NewLoad =
11985 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
11986 if (!NewLoad.getNode())
11987 return SDValue();
11989 if (EVT == MVT::f32) {
11990 // Create this as a scalar to vector to match the instruction pattern.
11991 SDValue LoadScalarToVector =
11992 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
11993 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
11994 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
11995 InsertpsMask);
11996 } else { // EVT == MVT::i32
11997 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
11998 // instruction, to match the PINSRD instruction, which loads an i32 to a
11999 // certain vector element.
12000 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
12001 DAG.getConstant(DestIndex, MVT::i32));
12002 }
12003 }
12005 // Vector-element-to-vector
12006 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
12007 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
12008 }
12010 // Reduce a vector shuffle to zext.
12011 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
12012 SelectionDAG &DAG) {
12013 // PMOVZX is only available from SSE41.
12014 if (!Subtarget->hasSSE41())
12015 return SDValue();
12017 MVT VT = Op.getSimpleValueType();
12019 // Only AVX2 support 256-bit vector integer extending.
12020 if (!Subtarget->hasInt256() && VT.is256BitVector())
12021 return SDValue();
12023 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12024 SDLoc DL(Op);
12025 SDValue V1 = Op.getOperand(0);
12026 SDValue V2 = Op.getOperand(1);
12027 unsigned NumElems = VT.getVectorNumElements();
12029 // Extending is an unary operation and the element type of the source vector
12030 // won't be equal to or larger than i64.
12031 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
12032 VT.getVectorElementType() == MVT::i64)
12033 return SDValue();
12035 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
12036 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
12037 while ((1U << Shift) < NumElems) {
12038 if (SVOp->getMaskElt(1U << Shift) == 1)
12039 break;
12040 Shift += 1;
12041 // The maximal ratio is 8, i.e. from i8 to i64.
12042 if (Shift > 3)
12043 return SDValue();
12044 }
12046 // Check the shuffle mask.
12047 unsigned Mask = (1U << Shift) - 1;
12048 for (unsigned i = 0; i != NumElems; ++i) {
12049 int EltIdx = SVOp->getMaskElt(i);
12050 if ((i & Mask) != 0 && EltIdx != -1)
12051 return SDValue();
12052 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
12053 return SDValue();
12054 }
12056 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
12057 MVT NeVT = MVT::getIntegerVT(NBits);
12058 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
12060 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
12061 return SDValue();
12063 return DAG.getNode(ISD::BITCAST, DL, VT,
12064 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
12065 }
12067 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
12068 SelectionDAG &DAG) {
12069 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12070 MVT VT = Op.getSimpleValueType();
12071 SDLoc dl(Op);
12072 SDValue V1 = Op.getOperand(0);
12073 SDValue V2 = Op.getOperand(1);
12075 if (isZeroShuffle(SVOp))
12076 return getZeroVector(VT, Subtarget, DAG, dl);
12078 // Handle splat operations
12079 if (SVOp->isSplat()) {
12080 // Use vbroadcast whenever the splat comes from a foldable load
12081 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
12082 if (Broadcast.getNode())
12083 return Broadcast;
12084 }
12086 // Check integer expanding shuffles.
12087 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
12088 if (NewOp.getNode())
12089 return NewOp;
12091 // If the shuffle can be profitably rewritten as a narrower shuffle, then
12092 // do it!
12093 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
12094 VT == MVT::v32i8) {
12095 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12096 if (NewOp.getNode())
12097 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
12098 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
12099 // FIXME: Figure out a cleaner way to do this.
12100 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
12101 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12102 if (NewOp.getNode()) {
12103 MVT NewVT = NewOp.getSimpleValueType();
12104 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
12105 NewVT, true, false))
12106 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
12107 dl);
12108 }
12109 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
12110 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12111 if (NewOp.getNode()) {
12112 MVT NewVT = NewOp.getSimpleValueType();
12113 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
12114 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
12115 dl);
12116 }
12117 }
12118 }
12119 return SDValue();
12120 }
12122 SDValue
12123 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
12124 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12125 SDValue V1 = Op.getOperand(0);
12126 SDValue V2 = Op.getOperand(1);
12127 MVT VT = Op.getSimpleValueType();
12128 SDLoc dl(Op);
12129 unsigned NumElems = VT.getVectorNumElements();
12130 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
12131 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
12132 bool V1IsSplat = false;
12133 bool V2IsSplat = false;
12134 bool HasSSE2 = Subtarget->hasSSE2();
12135 bool HasFp256 = Subtarget->hasFp256();
12136 bool HasInt256 = Subtarget->hasInt256();
12137 MachineFunction &MF = DAG.getMachineFunction();
12138 bool OptForSize = MF.getFunction()->getAttributes().
12139 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
12141 // Check if we should use the experimental vector shuffle lowering. If so,
12142 // delegate completely to that code path.
12143 if (ExperimentalVectorShuffleLowering)
12144 return lowerVectorShuffle(Op, Subtarget, DAG);
12146 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
12148 if (V1IsUndef && V2IsUndef)
12149 return DAG.getUNDEF(VT);
12151 // When we create a shuffle node we put the UNDEF node to second operand,
12152 // but in some cases the first operand may be transformed to UNDEF.
12153 // In this case we should just commute the node.
12154 if (V1IsUndef)
12155 return DAG.getCommutedVectorShuffle(*SVOp);
12157 // Vector shuffle lowering takes 3 steps:
12158 //
12159 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
12160 // narrowing and commutation of operands should be handled.
12161 // 2) Matching of shuffles with known shuffle masks to x86 target specific
12162 // shuffle nodes.
12163 // 3) Rewriting of unmatched masks into new generic shuffle operations,
12164 // so the shuffle can be broken into other shuffles and the legalizer can
12165 // try the lowering again.
12166 //
12167 // The general idea is that no vector_shuffle operation should be left to
12168 // be matched during isel, all of them must be converted to a target specific
12169 // node here.
12171 // Normalize the input vectors. Here splats, zeroed vectors, profitable
12172 // narrowing and commutation of operands should be handled. The actual code
12173 // doesn't include all of those, work in progress...
12174 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
12175 if (NewOp.getNode())
12176 return NewOp;
12178 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
12180 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
12181 // unpckh_undef). Only use pshufd if speed is more important than size.
12182 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12183 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12184 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12185 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12187 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
12188 V2IsUndef && MayFoldVectorLoad(V1))
12189 return getMOVDDup(Op, dl, V1, DAG);
12191 if (isMOVHLPS_v_undef_Mask(M, VT))
12192 return getMOVHighToLow(Op, dl, DAG);
12194 // Use to match splats
12195 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
12196 (VT == MVT::v2f64 || VT == MVT::v2i64))
12197 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12199 if (isPSHUFDMask(M, VT)) {
12200 // The actual implementation will match the mask in the if above and then
12201 // during isel it can match several different instructions, not only pshufd
12202 // as its name says, sad but true, emulate the behavior for now...
12203 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
12204 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
12206 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
12208 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
12209 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
12211 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
12212 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
12213 DAG);
12215 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
12216 TargetMask, DAG);
12217 }
12219 if (isPALIGNRMask(M, VT, Subtarget))
12220 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
12221 getShufflePALIGNRImmediate(SVOp),
12222 DAG);
12224 if (isVALIGNMask(M, VT, Subtarget))
12225 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
12226 getShuffleVALIGNImmediate(SVOp),
12227 DAG);
12229 // Check if this can be converted into a logical shift.
12230 bool isLeft = false;
12231 unsigned ShAmt = 0;
12232 SDValue ShVal;
12233 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
12234 if (isShift && ShVal.hasOneUse()) {
12235 // If the shifted value has multiple uses, it may be cheaper to use
12236 // v_set0 + movlhps or movhlps, etc.
12237 MVT EltVT = VT.getVectorElementType();
12238 ShAmt *= EltVT.getSizeInBits();
12239 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12240 }
12242 if (isMOVLMask(M, VT)) {
12243 if (ISD::isBuildVectorAllZeros(V1.getNode()))
12244 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
12245 if (!isMOVLPMask(M, VT)) {
12246 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
12247 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
12249 if (VT == MVT::v4i32 || VT == MVT::v4f32)
12250 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
12251 }
12252 }
12254 // FIXME: fold these into legal mask.
12255 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
12256 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
12258 if (isMOVHLPSMask(M, VT))
12259 return getMOVHighToLow(Op, dl, DAG);
12261 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
12262 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
12264 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
12265 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
12267 if (isMOVLPMask(M, VT))
12268 return getMOVLP(Op, dl, DAG, HasSSE2);
12270 if (ShouldXformToMOVHLPS(M, VT) ||
12271 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
12272 return DAG.getCommutedVectorShuffle(*SVOp);
12274 if (isShift) {
12275 // No better options. Use a vshldq / vsrldq.
12276 MVT EltVT = VT.getVectorElementType();
12277 ShAmt *= EltVT.getSizeInBits();
12278 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12279 }
12281 bool Commuted = false;
12282 // FIXME: This should also accept a bitcast of a splat? Be careful, not
12283 // 1,1,1,1 -> v8i16 though.
12284 BitVector UndefElements;
12285 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
12286 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12287 V1IsSplat = true;
12288 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
12289 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12290 V2IsSplat = true;
12292 // Canonicalize the splat or undef, if present, to be on the RHS.
12293 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
12294 CommuteVectorShuffleMask(M, NumElems);
12295 std::swap(V1, V2);
12296 std::swap(V1IsSplat, V2IsSplat);
12297 Commuted = true;
12298 }
12300 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
12301 // Shuffling low element of v1 into undef, just return v1.
12302 if (V2IsUndef)
12303 return V1;
12304 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
12305 // the instruction selector will not match, so get a canonical MOVL with
12306 // swapped operands to undo the commute.
12307 return getMOVL(DAG, dl, VT, V2, V1);
12308 }
12310 if (isUNPCKLMask(M, VT, HasInt256))
12311 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12313 if (isUNPCKHMask(M, VT, HasInt256))
12314 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12316 if (V2IsSplat) {
12317 // Normalize mask so all entries that point to V2 points to its first
12318 // element then try to match unpck{h|l} again. If match, return a
12319 // new vector_shuffle with the corrected mask.p
12320 SmallVector<int, 8> NewMask(M.begin(), M.end());
12321 NormalizeMask(NewMask, NumElems);
12322 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
12323 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12324 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
12325 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12326 }
12328 if (Commuted) {
12329 // Commute is back and try unpck* again.
12330 // FIXME: this seems wrong.
12331 CommuteVectorShuffleMask(M, NumElems);
12332 std::swap(V1, V2);
12333 std::swap(V1IsSplat, V2IsSplat);
12335 if (isUNPCKLMask(M, VT, HasInt256))
12336 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12338 if (isUNPCKHMask(M, VT, HasInt256))
12339 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12340 }
12342 // Normalize the node to match x86 shuffle ops if needed
12343 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
12344 return DAG.getCommutedVectorShuffle(*SVOp);
12346 // The checks below are all present in isShuffleMaskLegal, but they are
12347 // inlined here right now to enable us to directly emit target specific
12348 // nodes, and remove one by one until they don't return Op anymore.
12350 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
12351 SVOp->getSplatIndex() == 0 && V2IsUndef) {
12352 if (VT == MVT::v2f64 || VT == MVT::v2i64)
12353 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12354 }
12356 if (isPSHUFHWMask(M, VT, HasInt256))
12357 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
12358 getShufflePSHUFHWImmediate(SVOp),
12359 DAG);
12361 if (isPSHUFLWMask(M, VT, HasInt256))
12362 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
12363 getShufflePSHUFLWImmediate(SVOp),
12364 DAG);
12366 unsigned MaskValue;
12367 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
12368 &MaskValue))
12369 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
12371 if (isSHUFPMask(M, VT))
12372 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
12373 getShuffleSHUFImmediate(SVOp), DAG);
12375 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12376 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12377 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12378 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12380 //===--------------------------------------------------------------------===//
12381 // Generate target specific nodes for 128 or 256-bit shuffles only
12382 // supported in the AVX instruction set.
12383 //
12385 // Handle VMOVDDUPY permutations
12386 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
12387 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
12389 // Handle VPERMILPS/D* permutations
12390 if (isVPERMILPMask(M, VT)) {
12391 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
12392 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
12393 getShuffleSHUFImmediate(SVOp), DAG);
12394 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
12395 getShuffleSHUFImmediate(SVOp), DAG);
12396 }
12398 unsigned Idx;
12399 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
12400 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
12401 Idx*(NumElems/2), DAG, dl);
12403 // Handle VPERM2F128/VPERM2I128 permutations
12404 if (isVPERM2X128Mask(M, VT, HasFp256))
12405 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
12406 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
12408 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
12409 return getINSERTPS(SVOp, dl, DAG);
12411 unsigned Imm8;
12412 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
12413 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
12415 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
12416 VT.is512BitVector()) {
12417 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
12418 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
12419 SmallVector<SDValue, 16> permclMask;
12420 for (unsigned i = 0; i != NumElems; ++i) {
12421 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
12422 }
12424 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
12425 if (V2IsUndef)
12426 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
12427 return DAG.getNode(X86ISD::VPERMV, dl, VT,
12428 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
12429 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
12430 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
12431 }
12433 //===--------------------------------------------------------------------===//
12434 // Since no target specific shuffle was selected for this generic one,
12435 // lower it into other known shuffles. FIXME: this isn't true yet, but
12436 // this is the plan.
12437 //
12439 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
12440 if (VT == MVT::v8i16) {
12441 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
12442 if (NewOp.getNode())
12443 return NewOp;
12444 }
12446 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
12447 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
12448 if (NewOp.getNode())
12449 return NewOp;
12450 }
12452 if (VT == MVT::v16i8) {
12453 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
12454 if (NewOp.getNode())
12455 return NewOp;
12456 }
12458 if (VT == MVT::v32i8) {
12459 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
12460 if (NewOp.getNode())
12461 return NewOp;
12462 }
12464 // Handle all 128-bit wide vectors with 4 elements, and match them with
12465 // several different shuffle types.
12466 if (NumElems == 4 && VT.is128BitVector())
12467 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
12469 // Handle general 256-bit shuffles
12470 if (VT.is256BitVector())
12471 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
12473 return SDValue();
12474 }
12476 // This function assumes its argument is a BUILD_VECTOR of constants or
12477 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
12478 // true.
12479 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
12480 unsigned &MaskValue) {
12481 MaskValue = 0;
12482 unsigned NumElems = BuildVector->getNumOperands();
12483 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
12484 unsigned NumLanes = (NumElems - 1) / 8 + 1;
12485 unsigned NumElemsInLane = NumElems / NumLanes;
12487 // Blend for v16i16 should be symetric for the both lanes.
12488 for (unsigned i = 0; i < NumElemsInLane; ++i) {
12489 SDValue EltCond = BuildVector->getOperand(i);
12490 SDValue SndLaneEltCond =
12491 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
12493 int Lane1Cond = -1, Lane2Cond = -1;
12494 if (isa<ConstantSDNode>(EltCond))
12495 Lane1Cond = !isZero(EltCond);
12496 if (isa<ConstantSDNode>(SndLaneEltCond))
12497 Lane2Cond = !isZero(SndLaneEltCond);
12499 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
12500 // Lane1Cond != 0, means we want the first argument.
12501 // Lane1Cond == 0, means we want the second argument.
12502 // The encoding of this argument is 0 for the first argument, 1
12503 // for the second. Therefore, invert the condition.
12504 MaskValue |= !Lane1Cond << i;
12505 else if (Lane1Cond < 0)
12506 MaskValue |= !Lane2Cond << i;
12507 else
12508 return false;
12509 }
12510 return true;
12511 }
12513 /// \brief Try to lower a VSELECT instruction to an immediate-controlled blend
12514 /// instruction.
12515 static SDValue lowerVSELECTtoBLENDI(SDValue Op, const X86Subtarget *Subtarget,
12516 SelectionDAG &DAG) {
12517 SDValue Cond = Op.getOperand(0);
12518 SDValue LHS = Op.getOperand(1);
12519 SDValue RHS = Op.getOperand(2);
12520 SDLoc dl(Op);
12521 MVT VT = Op.getSimpleValueType();
12522 MVT EltVT = VT.getVectorElementType();
12523 unsigned NumElems = VT.getVectorNumElements();
12525 // There is no blend with immediate in AVX-512.
12526 if (VT.is512BitVector())
12527 return SDValue();
12529 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
12530 return SDValue();
12531 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
12532 return SDValue();
12534 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
12535 return SDValue();
12537 // Check the mask for BLEND and build the value.
12538 unsigned MaskValue = 0;
12539 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
12540 return SDValue();
12542 // Convert i32 vectors to floating point if it is not AVX2.
12543 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
12544 MVT BlendVT = VT;
12545 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
12546 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
12547 NumElems);
12548 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
12549 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
12550 }
12552 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
12553 DAG.getConstant(MaskValue, MVT::i32));
12554 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
12555 }
12557 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
12558 // A vselect where all conditions and data are constants can be optimized into
12559 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
12560 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
12561 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
12562 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
12563 return SDValue();
12565 SDValue BlendOp = lowerVSELECTtoBLENDI(Op, Subtarget, DAG);
12566 if (BlendOp.getNode())
12567 return BlendOp;
12569 // Some types for vselect were previously set to Expand, not Legal or
12570 // Custom. Return an empty SDValue so we fall-through to Expand, after
12571 // the Custom lowering phase.
12572 MVT VT = Op.getSimpleValueType();
12573 switch (VT.SimpleTy) {
12574 default:
12575 break;
12576 case MVT::v8i16:
12577 case MVT::v16i16:
12578 if (Subtarget->hasBWI() && Subtarget->hasVLX())
12579 break;
12580 return SDValue();
12581 }
12583 // We couldn't create a "Blend with immediate" node.
12584 // This node should still be legal, but we'll have to emit a blendv*
12585 // instruction.
12586 return Op;
12587 }
12589 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
12590 MVT VT = Op.getSimpleValueType();
12591 SDLoc dl(Op);
12593 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
12594 return SDValue();
12596 if (VT.getSizeInBits() == 8) {
12597 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
12598 Op.getOperand(0), Op.getOperand(1));
12599 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12600 DAG.getValueType(VT));
12601 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12602 }
12604 if (VT.getSizeInBits() == 16) {
12605 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12606 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
12607 if (Idx == 0)
12608 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12609 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12610 DAG.getNode(ISD::BITCAST, dl,
12611 MVT::v4i32,
12612 Op.getOperand(0)),
12613 Op.getOperand(1)));
12614 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
12615 Op.getOperand(0), Op.getOperand(1));
12616 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12617 DAG.getValueType(VT));
12618 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12619 }
12621 if (VT == MVT::f32) {
12622 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
12623 // the result back to FR32 register. It's only worth matching if the
12624 // result has a single use which is a store or a bitcast to i32. And in
12625 // the case of a store, it's not worth it if the index is a constant 0,
12626 // because a MOVSSmr can be used instead, which is smaller and faster.
12627 if (!Op.hasOneUse())
12628 return SDValue();
12629 SDNode *User = *Op.getNode()->use_begin();
12630 if ((User->getOpcode() != ISD::STORE ||
12631 (isa<ConstantSDNode>(Op.getOperand(1)) &&
12632 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
12633 (User->getOpcode() != ISD::BITCAST ||
12634 User->getValueType(0) != MVT::i32))
12635 return SDValue();
12636 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12637 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
12638 Op.getOperand(0)),
12639 Op.getOperand(1));
12640 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
12641 }
12643 if (VT == MVT::i32 || VT == MVT::i64) {
12644 // ExtractPS/pextrq works with constant index.
12645 if (isa<ConstantSDNode>(Op.getOperand(1)))
12646 return Op;
12647 }
12648 return SDValue();
12649 }
12651 /// Extract one bit from mask vector, like v16i1 or v8i1.
12652 /// AVX-512 feature.
12653 SDValue
12654 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
12655 SDValue Vec = Op.getOperand(0);
12656 SDLoc dl(Vec);
12657 MVT VecVT = Vec.getSimpleValueType();
12658 SDValue Idx = Op.getOperand(1);
12659 MVT EltVT = Op.getSimpleValueType();
12661 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
12663 // variable index can't be handled in mask registers,
12664 // extend vector to VR512
12665 if (!isa<ConstantSDNode>(Idx)) {
12666 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12667 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
12668 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
12669 ExtVT.getVectorElementType(), Ext, Idx);
12670 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
12671 }
12673 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12674 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12675 unsigned MaxSift = rc->getSize()*8 - 1;
12676 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
12677 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12678 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
12679 DAG.getConstant(MaxSift, MVT::i8));
12680 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
12681 DAG.getIntPtrConstant(0));
12682 }
12684 SDValue
12685 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
12686 SelectionDAG &DAG) const {
12687 SDLoc dl(Op);
12688 SDValue Vec = Op.getOperand(0);
12689 MVT VecVT = Vec.getSimpleValueType();
12690 SDValue Idx = Op.getOperand(1);
12692 if (Op.getSimpleValueType() == MVT::i1)
12693 return ExtractBitFromMaskVector(Op, DAG);
12695 if (!isa<ConstantSDNode>(Idx)) {
12696 if (VecVT.is512BitVector() ||
12697 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
12698 VecVT.getVectorElementType().getSizeInBits() == 32)) {
12700 MVT MaskEltVT =
12701 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
12702 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
12703 MaskEltVT.getSizeInBits());
12705 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
12706 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
12707 getZeroVector(MaskVT, Subtarget, DAG, dl),
12708 Idx, DAG.getConstant(0, getPointerTy()));
12709 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
12710 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
12711 Perm, DAG.getConstant(0, getPointerTy()));
12712 }
12713 return SDValue();
12714 }
12716 // If this is a 256-bit vector result, first extract the 128-bit vector and
12717 // then extract the element from the 128-bit vector.
12718 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
12720 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12721 // Get the 128-bit vector.
12722 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
12723 MVT EltVT = VecVT.getVectorElementType();
12725 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
12727 //if (IdxVal >= NumElems/2)
12728 // IdxVal -= NumElems/2;
12729 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
12730 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
12731 DAG.getConstant(IdxVal, MVT::i32));
12732 }
12734 assert(VecVT.is128BitVector() && "Unexpected vector length");
12736 if (Subtarget->hasSSE41()) {
12737 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
12738 if (Res.getNode())
12739 return Res;
12740 }
12742 MVT VT = Op.getSimpleValueType();
12743 // TODO: handle v16i8.
12744 if (VT.getSizeInBits() == 16) {
12745 SDValue Vec = Op.getOperand(0);
12746 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12747 if (Idx == 0)
12748 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12749 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12750 DAG.getNode(ISD::BITCAST, dl,
12751 MVT::v4i32, Vec),
12752 Op.getOperand(1)));
12753 // Transform it so it match pextrw which produces a 32-bit result.
12754 MVT EltVT = MVT::i32;
12755 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
12756 Op.getOperand(0), Op.getOperand(1));
12757 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
12758 DAG.getValueType(VT));
12759 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12760 }
12762 if (VT.getSizeInBits() == 32) {
12763 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12764 if (Idx == 0)
12765 return Op;
12767 // SHUFPS the element to the lowest double word, then movss.
12768 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
12769 MVT VVT = Op.getOperand(0).getSimpleValueType();
12770 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12771 DAG.getUNDEF(VVT), Mask);
12772 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12773 DAG.getIntPtrConstant(0));
12774 }
12776 if (VT.getSizeInBits() == 64) {
12777 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
12778 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
12779 // to match extract_elt for f64.
12780 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12781 if (Idx == 0)
12782 return Op;
12784 // UNPCKHPD the element to the lowest double word, then movsd.
12785 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
12786 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
12787 int Mask[2] = { 1, -1 };
12788 MVT VVT = Op.getOperand(0).getSimpleValueType();
12789 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12790 DAG.getUNDEF(VVT), Mask);
12791 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12792 DAG.getIntPtrConstant(0));
12793 }
12795 return SDValue();
12796 }
12798 /// Insert one bit to mask vector, like v16i1 or v8i1.
12799 /// AVX-512 feature.
12800 SDValue
12801 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
12802 SDLoc dl(Op);
12803 SDValue Vec = Op.getOperand(0);
12804 SDValue Elt = Op.getOperand(1);
12805 SDValue Idx = Op.getOperand(2);
12806 MVT VecVT = Vec.getSimpleValueType();
12808 if (!isa<ConstantSDNode>(Idx)) {
12809 // Non constant index. Extend source and destination,
12810 // insert element and then truncate the result.
12811 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12812 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
12813 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
12814 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
12815 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
12816 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
12817 }
12819 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12820 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
12821 if (Vec.getOpcode() == ISD::UNDEF)
12822 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12823 DAG.getConstant(IdxVal, MVT::i8));
12824 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12825 unsigned MaxSift = rc->getSize()*8 - 1;
12826 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12827 DAG.getConstant(MaxSift, MVT::i8));
12828 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
12829 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12830 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
12831 }
12833 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
12834 SelectionDAG &DAG) const {
12835 MVT VT = Op.getSimpleValueType();
12836 MVT EltVT = VT.getVectorElementType();
12838 if (EltVT == MVT::i1)
12839 return InsertBitToMaskVector(Op, DAG);
12841 SDLoc dl(Op);
12842 SDValue N0 = Op.getOperand(0);
12843 SDValue N1 = Op.getOperand(1);
12844 SDValue N2 = Op.getOperand(2);
12845 if (!isa<ConstantSDNode>(N2))
12846 return SDValue();
12847 auto *N2C = cast<ConstantSDNode>(N2);
12848 unsigned IdxVal = N2C->getZExtValue();
12850 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
12851 // into that, and then insert the subvector back into the result.
12852 if (VT.is256BitVector() || VT.is512BitVector()) {
12853 // Get the desired 128-bit vector half.
12854 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
12856 // Insert the element into the desired half.
12857 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
12858 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
12860 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
12861 DAG.getConstant(IdxIn128, MVT::i32));
12863 // Insert the changed part back to the 256-bit vector
12864 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
12865 }
12866 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
12868 if (Subtarget->hasSSE41()) {
12869 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
12870 unsigned Opc;
12871 if (VT == MVT::v8i16) {
12872 Opc = X86ISD::PINSRW;
12873 } else {
12874 assert(VT == MVT::v16i8);
12875 Opc = X86ISD::PINSRB;
12876 }
12878 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
12879 // argument.
12880 if (N1.getValueType() != MVT::i32)
12881 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12882 if (N2.getValueType() != MVT::i32)
12883 N2 = DAG.getIntPtrConstant(IdxVal);
12884 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
12885 }
12887 if (EltVT == MVT::f32) {
12888 // Bits [7:6] of the constant are the source select. This will always be
12889 // zero here. The DAG Combiner may combine an extract_elt index into
12890 // these
12891 // bits. For example (insert (extract, 3), 2) could be matched by
12892 // putting
12893 // the '3' into bits [7:6] of X86ISD::INSERTPS.
12894 // Bits [5:4] of the constant are the destination select. This is the
12895 // value of the incoming immediate.
12896 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
12897 // combine either bitwise AND or insert of float 0.0 to set these bits.
12898 N2 = DAG.getIntPtrConstant(IdxVal << 4);
12899 // Create this as a scalar to vector..
12900 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
12901 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
12902 }
12904 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
12905 // PINSR* works with constant index.
12906 return Op;
12907 }
12908 }
12910 if (EltVT == MVT::i8)
12911 return SDValue();
12913 if (EltVT.getSizeInBits() == 16) {
12914 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
12915 // as its second argument.
12916 if (N1.getValueType() != MVT::i32)
12917 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12918 if (N2.getValueType() != MVT::i32)
12919 N2 = DAG.getIntPtrConstant(IdxVal);
12920 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
12921 }
12922 return SDValue();
12923 }
12925 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
12926 SDLoc dl(Op);
12927 MVT OpVT = Op.getSimpleValueType();
12929 // If this is a 256-bit vector result, first insert into a 128-bit
12930 // vector and then insert into the 256-bit vector.
12931 if (!OpVT.is128BitVector()) {
12932 // Insert into a 128-bit vector.
12933 unsigned SizeFactor = OpVT.getSizeInBits()/128;
12934 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
12935 OpVT.getVectorNumElements() / SizeFactor);
12937 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
12939 // Insert the 128-bit vector.
12940 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
12941 }
12943 if (OpVT == MVT::v1i64 &&
12944 Op.getOperand(0).getValueType() == MVT::i64)
12945 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
12947 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
12948 assert(OpVT.is128BitVector() && "Expected an SSE type!");
12949 return DAG.getNode(ISD::BITCAST, dl, OpVT,
12950 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
12951 }
12953 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
12954 // a simple subregister reference or explicit instructions to grab
12955 // upper bits of a vector.
12956 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12957 SelectionDAG &DAG) {
12958 SDLoc dl(Op);
12959 SDValue In = Op.getOperand(0);
12960 SDValue Idx = Op.getOperand(1);
12961 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12962 MVT ResVT = Op.getSimpleValueType();
12963 MVT InVT = In.getSimpleValueType();
12965 if (Subtarget->hasFp256()) {
12966 if (ResVT.is128BitVector() &&
12967 (InVT.is256BitVector() || InVT.is512BitVector()) &&
12968 isa<ConstantSDNode>(Idx)) {
12969 return Extract128BitVector(In, IdxVal, DAG, dl);
12970 }
12971 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
12972 isa<ConstantSDNode>(Idx)) {
12973 return Extract256BitVector(In, IdxVal, DAG, dl);
12974 }
12975 }
12976 return SDValue();
12977 }
12979 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
12980 // simple superregister reference or explicit instructions to insert
12981 // the upper bits of a vector.
12982 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12983 SelectionDAG &DAG) {
12984 if (Subtarget->hasFp256()) {
12985 SDLoc dl(Op.getNode());
12986 SDValue Vec = Op.getNode()->getOperand(0);
12987 SDValue SubVec = Op.getNode()->getOperand(1);
12988 SDValue Idx = Op.getNode()->getOperand(2);
12990 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
12991 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
12992 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
12993 isa<ConstantSDNode>(Idx)) {
12994 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12995 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
12996 }
12998 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
12999 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
13000 isa<ConstantSDNode>(Idx)) {
13001 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
13002 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
13003 }
13004 }
13005 return SDValue();
13006 }
13008 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
13009 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
13010 // one of the above mentioned nodes. It has to be wrapped because otherwise
13011 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
13012 // be used to form addressing mode. These wrapped nodes will be selected
13013 // into MOV32ri.
13014 SDValue
13015 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
13016 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
13018 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13019 // global base reg.
13020 unsigned char OpFlag = 0;
13021 unsigned WrapperKind = X86ISD::Wrapper;
13022 CodeModel::Model M = DAG.getTarget().getCodeModel();
13024 if (Subtarget->isPICStyleRIPRel() &&
13025 (M == CodeModel::Small || M == CodeModel::Kernel))
13026 WrapperKind = X86ISD::WrapperRIP;
13027 else if (Subtarget->isPICStyleGOT())
13028 OpFlag = X86II::MO_GOTOFF;
13029 else if (Subtarget->isPICStyleStubPIC())
13030 OpFlag = X86II::MO_PIC_BASE_OFFSET;
13032 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
13033 CP->getAlignment(),
13034 CP->getOffset(), OpFlag);
13035 SDLoc DL(CP);
13036 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13037 // With PIC, the address is actually $g + Offset.
13038 if (OpFlag) {
13039 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13040 DAG.getNode(X86ISD::GlobalBaseReg,
13041 SDLoc(), getPointerTy()),
13042 Result);
13043 }
13045 return Result;
13046 }
13048 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
13049 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
13051 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13052 // global base reg.
13053 unsigned char OpFlag = 0;
13054 unsigned WrapperKind = X86ISD::Wrapper;
13055 CodeModel::Model M = DAG.getTarget().getCodeModel();
13057 if (Subtarget->isPICStyleRIPRel() &&
13058 (M == CodeModel::Small || M == CodeModel::Kernel))
13059 WrapperKind = X86ISD::WrapperRIP;
13060 else if (Subtarget->isPICStyleGOT())
13061 OpFlag = X86II::MO_GOTOFF;
13062 else if (Subtarget->isPICStyleStubPIC())
13063 OpFlag = X86II::MO_PIC_BASE_OFFSET;
13065 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
13066 OpFlag);
13067 SDLoc DL(JT);
13068 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13070 // With PIC, the address is actually $g + Offset.
13071 if (OpFlag)
13072 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13073 DAG.getNode(X86ISD::GlobalBaseReg,
13074 SDLoc(), getPointerTy()),
13075 Result);
13077 return Result;
13078 }
13080 SDValue
13081 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
13082 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
13084 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13085 // global base reg.
13086 unsigned char OpFlag = 0;
13087 unsigned WrapperKind = X86ISD::Wrapper;
13088 CodeModel::Model M = DAG.getTarget().getCodeModel();
13090 if (Subtarget->isPICStyleRIPRel() &&
13091 (M == CodeModel::Small || M == CodeModel::Kernel)) {
13092 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
13093 OpFlag = X86II::MO_GOTPCREL;
13094 WrapperKind = X86ISD::WrapperRIP;
13095 } else if (Subtarget->isPICStyleGOT()) {
13096 OpFlag = X86II::MO_GOT;
13097 } else if (Subtarget->isPICStyleStubPIC()) {
13098 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
13099 } else if (Subtarget->isPICStyleStubNoDynamic()) {
13100 OpFlag = X86II::MO_DARWIN_NONLAZY;
13101 }
13103 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
13105 SDLoc DL(Op);
13106 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13108 // With PIC, the address is actually $g + Offset.
13109 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
13110 !Subtarget->is64Bit()) {
13111 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13112 DAG.getNode(X86ISD::GlobalBaseReg,
13113 SDLoc(), getPointerTy()),
13114 Result);
13115 }
13117 // For symbols that require a load from a stub to get the address, emit the
13118 // load.
13119 if (isGlobalStubReference(OpFlag))
13120 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
13121 MachinePointerInfo::getGOT(), false, false, false, 0);
13123 return Result;
13124 }
13126 SDValue
13127 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
13128 // Create the TargetBlockAddressAddress node.
13129 unsigned char OpFlags =
13130 Subtarget->ClassifyBlockAddressReference();
13131 CodeModel::Model M = DAG.getTarget().getCodeModel();
13132 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
13133 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
13134 SDLoc dl(Op);
13135 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
13136 OpFlags);
13138 if (Subtarget->isPICStyleRIPRel() &&
13139 (M == CodeModel::Small || M == CodeModel::Kernel))
13140 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13141 else
13142 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13144 // With PIC, the address is actually $g + Offset.
13145 if (isGlobalRelativeToPICBase(OpFlags)) {
13146 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13147 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13148 Result);
13149 }
13151 return Result;
13152 }
13154 SDValue
13155 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
13156 int64_t Offset, SelectionDAG &DAG) const {
13157 // Create the TargetGlobalAddress node, folding in the constant
13158 // offset if it is legal.
13159 unsigned char OpFlags =
13160 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
13161 CodeModel::Model M = DAG.getTarget().getCodeModel();
13162 SDValue Result;
13163 if (OpFlags == X86II::MO_NO_FLAG &&
13164 X86::isOffsetSuitableForCodeModel(Offset, M)) {
13165 // A direct static reference to a global.
13166 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
13167 Offset = 0;
13168 } else {
13169 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
13170 }
13172 if (Subtarget->isPICStyleRIPRel() &&
13173 (M == CodeModel::Small || M == CodeModel::Kernel))
13174 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13175 else
13176 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13178 // With PIC, the address is actually $g + Offset.
13179 if (isGlobalRelativeToPICBase(OpFlags)) {
13180 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13181 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13182 Result);
13183 }
13185 // For globals that require a load from a stub to get the address, emit the
13186 // load.
13187 if (isGlobalStubReference(OpFlags))
13188 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
13189 MachinePointerInfo::getGOT(), false, false, false, 0);
13191 // If there was a non-zero offset that we didn't fold, create an explicit
13192 // addition for it.
13193 if (Offset != 0)
13194 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
13195 DAG.getConstant(Offset, getPointerTy()));
13197 return Result;
13198 }
13200 SDValue
13201 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
13202 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
13203 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
13204 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
13205 }
13207 static SDValue
13208 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
13209 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
13210 unsigned char OperandFlags, bool LocalDynamic = false) {
13211 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13212 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13213 SDLoc dl(GA);
13214 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13215 GA->getValueType(0),
13216 GA->getOffset(),
13217 OperandFlags);
13219 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
13220 : X86ISD::TLSADDR;
13222 if (InFlag) {
13223 SDValue Ops[] = { Chain, TGA, *InFlag };
13224 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13225 } else {
13226 SDValue Ops[] = { Chain, TGA };
13227 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13228 }
13230 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
13231 MFI->setAdjustsStack(true);
13232 MFI->setHasCalls(true);
13234 SDValue Flag = Chain.getValue(1);
13235 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
13236 }
13238 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
13239 static SDValue
13240 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13241 const EVT PtrVT) {
13242 SDValue InFlag;
13243 SDLoc dl(GA); // ? function entry point might be better
13244 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13245 DAG.getNode(X86ISD::GlobalBaseReg,
13246 SDLoc(), PtrVT), InFlag);
13247 InFlag = Chain.getValue(1);
13249 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
13250 }
13252 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
13253 static SDValue
13254 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13255 const EVT PtrVT) {
13256 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
13257 X86::RAX, X86II::MO_TLSGD);
13258 }
13260 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
13261 SelectionDAG &DAG,
13262 const EVT PtrVT,
13263 bool is64Bit) {
13264 SDLoc dl(GA);
13266 // Get the start address of the TLS block for this module.
13267 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
13268 .getInfo<X86MachineFunctionInfo>();
13269 MFI->incNumLocalDynamicTLSAccesses();
13271 SDValue Base;
13272 if (is64Bit) {
13273 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
13274 X86II::MO_TLSLD, /*LocalDynamic=*/true);
13275 } else {
13276 SDValue InFlag;
13277 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13278 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
13279 InFlag = Chain.getValue(1);
13280 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
13281 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
13282 }
13284 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
13285 // of Base.
13287 // Build x@dtpoff.
13288 unsigned char OperandFlags = X86II::MO_DTPOFF;
13289 unsigned WrapperKind = X86ISD::Wrapper;
13290 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13291 GA->getValueType(0),
13292 GA->getOffset(), OperandFlags);
13293 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13295 // Add x@dtpoff with the base.
13296 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
13297 }
13299 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
13300 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13301 const EVT PtrVT, TLSModel::Model model,
13302 bool is64Bit, bool isPIC) {
13303 SDLoc dl(GA);
13305 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
13306 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
13307 is64Bit ? 257 : 256));
13309 SDValue ThreadPointer =
13310 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
13311 MachinePointerInfo(Ptr), false, false, false, 0);
13313 unsigned char OperandFlags = 0;
13314 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
13315 // initialexec.
13316 unsigned WrapperKind = X86ISD::Wrapper;
13317 if (model == TLSModel::LocalExec) {
13318 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
13319 } else if (model == TLSModel::InitialExec) {
13320 if (is64Bit) {
13321 OperandFlags = X86II::MO_GOTTPOFF;
13322 WrapperKind = X86ISD::WrapperRIP;
13323 } else {
13324 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
13325 }
13326 } else {
13327 llvm_unreachable("Unexpected model");
13328 }
13330 // emit "addl x@ntpoff,%eax" (local exec)
13331 // or "addl x@indntpoff,%eax" (initial exec)
13332 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
13333 SDValue TGA =
13334 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
13335 GA->getOffset(), OperandFlags);
13336 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13338 if (model == TLSModel::InitialExec) {
13339 if (isPIC && !is64Bit) {
13340 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
13341 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
13342 Offset);
13343 }
13345 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
13346 MachinePointerInfo::getGOT(), false, false, false, 0);
13347 }
13349 // The address of the thread local variable is the add of the thread
13350 // pointer with the offset of the variable.
13351 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
13352 }
13354 SDValue
13355 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
13357 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
13358 const GlobalValue *GV = GA->getGlobal();
13360 if (Subtarget->isTargetELF()) {
13361 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
13363 switch (model) {
13364 case TLSModel::GeneralDynamic:
13365 if (Subtarget->is64Bit())
13366 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
13367 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
13368 case TLSModel::LocalDynamic:
13369 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
13370 Subtarget->is64Bit());
13371 case TLSModel::InitialExec:
13372 case TLSModel::LocalExec:
13373 return LowerToTLSExecModel(
13374 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
13375 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
13376 }
13377 llvm_unreachable("Unknown TLS model.");
13378 }
13380 if (Subtarget->isTargetDarwin()) {
13381 // Darwin only has one model of TLS. Lower to that.
13382 unsigned char OpFlag = 0;
13383 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
13384 X86ISD::WrapperRIP : X86ISD::Wrapper;
13386 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13387 // global base reg.
13388 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
13389 !Subtarget->is64Bit();
13390 if (PIC32)
13391 OpFlag = X86II::MO_TLVP_PIC_BASE;
13392 else
13393 OpFlag = X86II::MO_TLVP;
13394 SDLoc DL(Op);
13395 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
13396 GA->getValueType(0),
13397 GA->getOffset(), OpFlag);
13398 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13400 // With PIC32, the address is actually $g + Offset.
13401 if (PIC32)
13402 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13403 DAG.getNode(X86ISD::GlobalBaseReg,
13404 SDLoc(), getPointerTy()),
13405 Offset);
13407 // Lowering the machine isd will make sure everything is in the right
13408 // location.
13409 SDValue Chain = DAG.getEntryNode();
13410 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13411 SDValue Args[] = { Chain, Offset };
13412 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
13414 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
13415 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13416 MFI->setAdjustsStack(true);
13418 // And our return value (tls address) is in the standard call return value
13419 // location.
13420 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
13421 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
13422 Chain.getValue(1));
13423 }
13425 if (Subtarget->isTargetKnownWindowsMSVC() ||
13426 Subtarget->isTargetWindowsGNU()) {
13427 // Just use the implicit TLS architecture
13428 // Need to generate someting similar to:
13429 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
13430 // ; from TEB
13431 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
13432 // mov rcx, qword [rdx+rcx*8]
13433 // mov eax, .tls$:tlsvar
13434 // [rax+rcx] contains the address
13435 // Windows 64bit: gs:0x58
13436 // Windows 32bit: fs:__tls_array
13438 SDLoc dl(GA);
13439 SDValue Chain = DAG.getEntryNode();
13441 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
13442 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
13443 // use its literal value of 0x2C.
13444 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
13445 ? Type::getInt8PtrTy(*DAG.getContext(),
13446 256)
13447 : Type::getInt32PtrTy(*DAG.getContext(),
13448 257));
13450 SDValue TlsArray =
13451 Subtarget->is64Bit()
13452 ? DAG.getIntPtrConstant(0x58)
13453 : (Subtarget->isTargetWindowsGNU()
13454 ? DAG.getIntPtrConstant(0x2C)
13455 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
13457 SDValue ThreadPointer =
13458 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
13459 MachinePointerInfo(Ptr), false, false, false, 0);
13461 // Load the _tls_index variable
13462 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
13463 if (Subtarget->is64Bit())
13464 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
13465 IDX, MachinePointerInfo(), MVT::i32,
13466 false, false, false, 0);
13467 else
13468 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
13469 false, false, false, 0);
13471 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
13472 getPointerTy());
13473 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
13475 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
13476 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
13477 false, false, false, 0);
13479 // Get the offset of start of .tls section
13480 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13481 GA->getValueType(0),
13482 GA->getOffset(), X86II::MO_SECREL);
13483 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
13485 // The address of the thread local variable is the add of the thread
13486 // pointer with the offset of the variable.
13487 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
13488 }
13490 llvm_unreachable("TLS not implemented for this target.");
13491 }
13493 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
13494 /// and take a 2 x i32 value to shift plus a shift amount.
13495 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
13496 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
13497 MVT VT = Op.getSimpleValueType();
13498 unsigned VTBits = VT.getSizeInBits();
13499 SDLoc dl(Op);
13500 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
13501 SDValue ShOpLo = Op.getOperand(0);
13502 SDValue ShOpHi = Op.getOperand(1);
13503 SDValue ShAmt = Op.getOperand(2);
13504 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
13505 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
13506 // during isel.
13507 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13508 DAG.getConstant(VTBits - 1, MVT::i8));
13509 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
13510 DAG.getConstant(VTBits - 1, MVT::i8))
13511 : DAG.getConstant(0, VT);
13513 SDValue Tmp2, Tmp3;
13514 if (Op.getOpcode() == ISD::SHL_PARTS) {
13515 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
13516 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
13517 } else {
13518 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
13519 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
13520 }
13522 // If the shift amount is larger or equal than the width of a part we can't
13523 // rely on the results of shld/shrd. Insert a test and select the appropriate
13524 // values for large shift amounts.
13525 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13526 DAG.getConstant(VTBits, MVT::i8));
13527 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13528 AndNode, DAG.getConstant(0, MVT::i8));
13530 SDValue Hi, Lo;
13531 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13532 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
13533 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
13535 if (Op.getOpcode() == ISD::SHL_PARTS) {
13536 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13537 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13538 } else {
13539 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13540 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13541 }
13543 SDValue Ops[2] = { Lo, Hi };
13544 return DAG.getMergeValues(Ops, dl);
13545 }
13547 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
13548 SelectionDAG &DAG) const {
13549 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13550 SDLoc dl(Op);
13552 if (SrcVT.isVector()) {
13553 if (SrcVT.getVectorElementType() == MVT::i1) {
13554 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
13555 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13556 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT,
13557 Op.getOperand(0)));
13558 }
13559 return SDValue();
13560 }
13562 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
13563 "Unknown SINT_TO_FP to lower!");
13565 // These are really Legal; return the operand so the caller accepts it as
13566 // Legal.
13567 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
13568 return Op;
13569 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
13570 Subtarget->is64Bit()) {
13571 return Op;
13572 }
13574 unsigned Size = SrcVT.getSizeInBits()/8;
13575 MachineFunction &MF = DAG.getMachineFunction();
13576 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
13577 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13578 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13579 StackSlot,
13580 MachinePointerInfo::getFixedStack(SSFI),
13581 false, false, 0);
13582 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
13583 }
13585 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
13586 SDValue StackSlot,
13587 SelectionDAG &DAG) const {
13588 // Build the FILD
13589 SDLoc DL(Op);
13590 SDVTList Tys;
13591 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
13592 if (useSSE)
13593 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
13594 else
13595 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
13597 unsigned ByteSize = SrcVT.getSizeInBits()/8;
13599 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
13600 MachineMemOperand *MMO;
13601 if (FI) {
13602 int SSFI = FI->getIndex();
13603 MMO =
13604 DAG.getMachineFunction()
13605 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13606 MachineMemOperand::MOLoad, ByteSize, ByteSize);
13607 } else {
13608 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
13609 StackSlot = StackSlot.getOperand(1);
13610 }
13611 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
13612 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
13613 X86ISD::FILD, DL,
13614 Tys, Ops, SrcVT, MMO);
13616 if (useSSE) {
13617 Chain = Result.getValue(1);
13618 SDValue InFlag = Result.getValue(2);
13620 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
13621 // shouldn't be necessary except that RFP cannot be live across
13622 // multiple blocks. When stackifier is fixed, they can be uncoupled.
13623 MachineFunction &MF = DAG.getMachineFunction();
13624 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
13625 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
13626 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13627 Tys = DAG.getVTList(MVT::Other);
13628 SDValue Ops[] = {
13629 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
13630 };
13631 MachineMemOperand *MMO =
13632 DAG.getMachineFunction()
13633 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13634 MachineMemOperand::MOStore, SSFISize, SSFISize);
13636 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
13637 Ops, Op.getValueType(), MMO);
13638 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
13639 MachinePointerInfo::getFixedStack(SSFI),
13640 false, false, false, 0);
13641 }
13643 return Result;
13644 }
13646 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
13647 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
13648 SelectionDAG &DAG) const {
13649 // This algorithm is not obvious. Here it is what we're trying to output:
13650 /*
13651 movq %rax, %xmm0
13652 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
13653 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
13654 #ifdef __SSE3__
13655 haddpd %xmm0, %xmm0
13656 #else
13657 pshufd $0x4e, %xmm0, %xmm1
13658 addpd %xmm1, %xmm0
13659 #endif
13660 */
13662 SDLoc dl(Op);
13663 LLVMContext *Context = DAG.getContext();
13665 // Build some magic constants.
13666 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
13667 Constant *C0 = ConstantDataVector::get(*Context, CV0);
13668 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
13670 SmallVector<Constant*,2> CV1;
13671 CV1.push_back(
13672 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13673 APInt(64, 0x4330000000000000ULL))));
13674 CV1.push_back(
13675 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13676 APInt(64, 0x4530000000000000ULL))));
13677 Constant *C1 = ConstantVector::get(CV1);
13678 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
13680 // Load the 64-bit value into an XMM register.
13681 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
13682 Op.getOperand(0));
13683 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
13684 MachinePointerInfo::getConstantPool(),
13685 false, false, false, 16);
13686 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
13687 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
13688 CLod0);
13690 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
13691 MachinePointerInfo::getConstantPool(),
13692 false, false, false, 16);
13693 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
13694 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
13695 SDValue Result;
13697 if (Subtarget->hasSSE3()) {
13698 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
13699 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
13700 } else {
13701 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
13702 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
13703 S2F, 0x4E, DAG);
13704 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
13705 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
13706 Sub);
13707 }
13709 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
13710 DAG.getIntPtrConstant(0));
13711 }
13713 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
13714 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
13715 SelectionDAG &DAG) const {
13716 SDLoc dl(Op);
13717 // FP constant to bias correct the final result.
13718 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13719 MVT::f64);
13721 // Load the 32-bit value into an XMM register.
13722 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
13723 Op.getOperand(0));
13725 // Zero out the upper parts of the register.
13726 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
13728 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13729 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
13730 DAG.getIntPtrConstant(0));
13732 // Or the load with the bias.
13733 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
13734 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13735 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13736 MVT::v2f64, Load)),
13737 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13738 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13739 MVT::v2f64, Bias)));
13740 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13741 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
13742 DAG.getIntPtrConstant(0));
13744 // Subtract the bias.
13745 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
13747 // Handle final rounding.
13748 EVT DestVT = Op.getValueType();
13750 if (DestVT.bitsLT(MVT::f64))
13751 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
13752 DAG.getIntPtrConstant(0));
13753 if (DestVT.bitsGT(MVT::f64))
13754 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
13756 // Handle final rounding.
13757 return Sub;
13758 }
13760 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
13761 const X86Subtarget &Subtarget) {
13762 // The algorithm is the following:
13763 // #ifdef __SSE4_1__
13764 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13765 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13766 // (uint4) 0x53000000, 0xaa);
13767 // #else
13768 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13769 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13770 // #endif
13771 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13772 // return (float4) lo + fhi;
13774 SDLoc DL(Op);
13775 SDValue V = Op->getOperand(0);
13776 EVT VecIntVT = V.getValueType();
13777 bool Is128 = VecIntVT == MVT::v4i32;
13778 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
13779 // If we convert to something else than the supported type, e.g., to v4f64,
13780 // abort early.
13781 if (VecFloatVT != Op->getValueType(0))
13782 return SDValue();
13784 unsigned NumElts = VecIntVT.getVectorNumElements();
13785 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
13786 "Unsupported custom type");
13787 assert(NumElts <= 8 && "The size of the constant array must be fixed");
13789 // In the #idef/#else code, we have in common:
13790 // - The vector of constants:
13791 // -- 0x4b000000
13792 // -- 0x53000000
13793 // - A shift:
13794 // -- v >> 16
13796 // Create the splat vector for 0x4b000000.
13797 SDValue CstLow = DAG.getConstant(0x4b000000, MVT::i32);
13798 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
13799 CstLow, CstLow, CstLow, CstLow};
13800 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13801 makeArrayRef(&CstLowArray[0], NumElts));
13802 // Create the splat vector for 0x53000000.
13803 SDValue CstHigh = DAG.getConstant(0x53000000, MVT::i32);
13804 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
13805 CstHigh, CstHigh, CstHigh, CstHigh};
13806 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13807 makeArrayRef(&CstHighArray[0], NumElts));
13809 // Create the right shift.
13810 SDValue CstShift = DAG.getConstant(16, MVT::i32);
13811 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
13812 CstShift, CstShift, CstShift, CstShift};
13813 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13814 makeArrayRef(&CstShiftArray[0], NumElts));
13815 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
13817 SDValue Low, High;
13818 if (Subtarget.hasSSE41()) {
13819 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
13820 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13821 SDValue VecCstLowBitcast =
13822 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstLow);
13823 SDValue VecBitcast = DAG.getNode(ISD::BITCAST, DL, VecI16VT, V);
13824 // Low will be bitcasted right away, so do not bother bitcasting back to its
13825 // original type.
13826 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
13827 VecCstLowBitcast, DAG.getConstant(0xaa, MVT::i32));
13828 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13829 // (uint4) 0x53000000, 0xaa);
13830 SDValue VecCstHighBitcast =
13831 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstHigh);
13832 SDValue VecShiftBitcast =
13833 DAG.getNode(ISD::BITCAST, DL, VecI16VT, HighShift);
13834 // High will be bitcasted right away, so do not bother bitcasting back to
13835 // its original type.
13836 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
13837 VecCstHighBitcast, DAG.getConstant(0xaa, MVT::i32));
13838 } else {
13839 SDValue CstMask = DAG.getConstant(0xffff, MVT::i32);
13840 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
13841 CstMask, CstMask, CstMask);
13842 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13843 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
13844 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
13846 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13847 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
13848 }
13850 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
13851 SDValue CstFAdd = DAG.getConstantFP(
13852 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), MVT::f32);
13853 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
13854 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
13855 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
13856 makeArrayRef(&CstFAddArray[0], NumElts));
13858 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13859 SDValue HighBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, High);
13860 SDValue FHigh =
13861 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
13862 // return (float4) lo + fhi;
13863 SDValue LowBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, Low);
13864 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
13865 }
13867 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
13868 SelectionDAG &DAG) const {
13869 SDValue N0 = Op.getOperand(0);
13870 MVT SVT = N0.getSimpleValueType();
13871 SDLoc dl(Op);
13873 switch (SVT.SimpleTy) {
13874 default:
13875 llvm_unreachable("Custom UINT_TO_FP is not supported!");
13876 case MVT::v4i8:
13877 case MVT::v4i16:
13878 case MVT::v8i8:
13879 case MVT::v8i16: {
13880 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
13881 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13882 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
13883 }
13884 case MVT::v4i32:
13885 case MVT::v8i32:
13886 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
13887 }
13888 llvm_unreachable(nullptr);
13889 }
13891 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
13892 SelectionDAG &DAG) const {
13893 SDValue N0 = Op.getOperand(0);
13894 SDLoc dl(Op);
13896 if (Op.getValueType().isVector())
13897 return lowerUINT_TO_FP_vec(Op, DAG);
13899 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
13900 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
13901 // the optimization here.
13902 if (DAG.SignBitIsZero(N0))
13903 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
13905 MVT SrcVT = N0.getSimpleValueType();
13906 MVT DstVT = Op.getSimpleValueType();
13907 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
13908 return LowerUINT_TO_FP_i64(Op, DAG);
13909 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
13910 return LowerUINT_TO_FP_i32(Op, DAG);
13911 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
13912 return SDValue();
13914 // Make a 64-bit buffer, and use it to build an FILD.
13915 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
13916 if (SrcVT == MVT::i32) {
13917 SDValue WordOff = DAG.getConstant(4, getPointerTy());
13918 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
13919 getPointerTy(), StackSlot, WordOff);
13920 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13921 StackSlot, MachinePointerInfo(),
13922 false, false, 0);
13923 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
13924 OffsetSlot, MachinePointerInfo(),
13925 false, false, 0);
13926 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
13927 return Fild;
13928 }
13930 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
13931 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13932 StackSlot, MachinePointerInfo(),
13933 false, false, 0);
13934 // For i64 source, we need to add the appropriate power of 2 if the input
13935 // was negative. This is the same as the optimization in
13936 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
13937 // we must be careful to do the computation in x87 extended precision, not
13938 // in SSE. (The generic code can't know it's OK to do this, or how to.)
13939 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
13940 MachineMemOperand *MMO =
13941 DAG.getMachineFunction()
13942 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13943 MachineMemOperand::MOLoad, 8, 8);
13945 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
13946 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
13947 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
13948 MVT::i64, MMO);
13950 APInt FF(32, 0x5F800000ULL);
13952 // Check whether the sign bit is set.
13953 SDValue SignSet = DAG.getSetCC(dl,
13954 getSetCCResultType(*DAG.getContext(), MVT::i64),
13955 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
13956 ISD::SETLT);
13958 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
13959 SDValue FudgePtr = DAG.getConstantPool(
13960 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
13961 getPointerTy());
13963 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
13964 SDValue Zero = DAG.getIntPtrConstant(0);
13965 SDValue Four = DAG.getIntPtrConstant(4);
13966 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
13967 Zero, Four);
13968 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
13970 // Load the value out, extending it from f32 to f80.
13971 // FIXME: Avoid the extend by constructing the right constant pool?
13972 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
13973 FudgePtr, MachinePointerInfo::getConstantPool(),
13974 MVT::f32, false, false, false, 4);
13975 // Extend everything to 80 bits to force it to be done on x87.
13976 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
13977 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
13978 }
13980 std::pair<SDValue,SDValue>
13981 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
13982 bool IsSigned, bool IsReplace) const {
13983 SDLoc DL(Op);
13985 EVT DstTy = Op.getValueType();
13987 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
13988 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
13989 DstTy = MVT::i64;
13990 }
13992 assert(DstTy.getSimpleVT() <= MVT::i64 &&
13993 DstTy.getSimpleVT() >= MVT::i16 &&
13994 "Unknown FP_TO_INT to lower!");
13996 // These are really Legal.
13997 if (DstTy == MVT::i32 &&
13998 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13999 return std::make_pair(SDValue(), SDValue());
14000 if (Subtarget->is64Bit() &&
14001 DstTy == MVT::i64 &&
14002 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
14003 return std::make_pair(SDValue(), SDValue());
14005 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
14006 // stack slot, or into the FTOL runtime function.
14007 MachineFunction &MF = DAG.getMachineFunction();
14008 unsigned MemSize = DstTy.getSizeInBits()/8;
14009 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
14010 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14012 unsigned Opc;
14013 if (!IsSigned && isIntegerTypeFTOL(DstTy))
14014 Opc = X86ISD::WIN_FTOL;
14015 else
14016 switch (DstTy.getSimpleVT().SimpleTy) {
14017 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
14018 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
14019 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
14020 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
14021 }
14023 SDValue Chain = DAG.getEntryNode();
14024 SDValue Value = Op.getOperand(0);
14025 EVT TheVT = Op.getOperand(0).getValueType();
14026 // FIXME This causes a redundant load/store if the SSE-class value is already
14027 // in memory, such as if it is on the callstack.
14028 if (isScalarFPTypeInSSEReg(TheVT)) {
14029 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
14030 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
14031 MachinePointerInfo::getFixedStack(SSFI),
14032 false, false, 0);
14033 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
14034 SDValue Ops[] = {
14035 Chain, StackSlot, DAG.getValueType(TheVT)
14036 };
14038 MachineMemOperand *MMO =
14039 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14040 MachineMemOperand::MOLoad, MemSize, MemSize);
14041 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
14042 Chain = Value.getValue(1);
14043 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
14044 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14045 }
14047 MachineMemOperand *MMO =
14048 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14049 MachineMemOperand::MOStore, MemSize, MemSize);
14051 if (Opc != X86ISD::WIN_FTOL) {
14052 // Build the FP_TO_INT*_IN_MEM
14053 SDValue Ops[] = { Chain, Value, StackSlot };
14054 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
14055 Ops, DstTy, MMO);
14056 return std::make_pair(FIST, StackSlot);
14057 } else {
14058 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
14059 DAG.getVTList(MVT::Other, MVT::Glue),
14060 Chain, Value);
14061 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
14062 MVT::i32, ftol.getValue(1));
14063 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
14064 MVT::i32, eax.getValue(2));
14065 SDValue Ops[] = { eax, edx };
14066 SDValue pair = IsReplace
14067 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
14068 : DAG.getMergeValues(Ops, DL);
14069 return std::make_pair(pair, SDValue());
14070 }
14071 }
14073 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
14074 const X86Subtarget *Subtarget) {
14075 MVT VT = Op->getSimpleValueType(0);
14076 SDValue In = Op->getOperand(0);
14077 MVT InVT = In.getSimpleValueType();
14078 SDLoc dl(Op);
14080 // Optimize vectors in AVX mode:
14081 //
14082 // v8i16 -> v8i32
14083 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
14084 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
14085 // Concat upper and lower parts.
14086 //
14087 // v4i32 -> v4i64
14088 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
14089 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
14090 // Concat upper and lower parts.
14091 //
14093 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
14094 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
14095 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
14096 return SDValue();
14098 if (Subtarget->hasInt256())
14099 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
14101 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
14102 SDValue Undef = DAG.getUNDEF(InVT);
14103 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
14104 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
14105 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
14107 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
14108 VT.getVectorNumElements()/2);
14110 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
14111 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
14113 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14114 }
14116 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
14117 SelectionDAG &DAG) {
14118 MVT VT = Op->getSimpleValueType(0);
14119 SDValue In = Op->getOperand(0);
14120 MVT InVT = In.getSimpleValueType();
14121 SDLoc DL(Op);
14122 unsigned int NumElts = VT.getVectorNumElements();
14123 if (NumElts != 8 && NumElts != 16)
14124 return SDValue();
14126 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
14127 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
14129 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
14130 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14131 // Now we have only mask extension
14132 assert(InVT.getVectorElementType() == MVT::i1);
14133 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
14134 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14135 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
14136 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14137 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14138 MachinePointerInfo::getConstantPool(),
14139 false, false, false, Alignment);
14141 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
14142 if (VT.is512BitVector())
14143 return Brcst;
14144 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
14145 }
14147 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14148 SelectionDAG &DAG) {
14149 if (Subtarget->hasFp256()) {
14150 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14151 if (Res.getNode())
14152 return Res;
14153 }
14155 return SDValue();
14156 }
14158 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14159 SelectionDAG &DAG) {
14160 SDLoc DL(Op);
14161 MVT VT = Op.getSimpleValueType();
14162 SDValue In = Op.getOperand(0);
14163 MVT SVT = In.getSimpleValueType();
14165 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
14166 return LowerZERO_EXTEND_AVX512(Op, DAG);
14168 if (Subtarget->hasFp256()) {
14169 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14170 if (Res.getNode())
14171 return Res;
14172 }
14174 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
14175 VT.getVectorNumElements() != SVT.getVectorNumElements());
14176 return SDValue();
14177 }
14179 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
14180 SDLoc DL(Op);
14181 MVT VT = Op.getSimpleValueType();
14182 SDValue In = Op.getOperand(0);
14183 MVT InVT = In.getSimpleValueType();
14185 if (VT == MVT::i1) {
14186 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
14187 "Invalid scalar TRUNCATE operation");
14188 if (InVT.getSizeInBits() >= 32)
14189 return SDValue();
14190 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
14191 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
14192 }
14193 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
14194 "Invalid TRUNCATE operation");
14196 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
14197 if (VT.getVectorElementType().getSizeInBits() >=8)
14198 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
14200 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14201 unsigned NumElts = InVT.getVectorNumElements();
14202 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
14203 if (InVT.getSizeInBits() < 512) {
14204 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
14205 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
14206 InVT = ExtVT;
14207 }
14209 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
14210 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14211 SDValue CP = DAG.getConstantPool(C, getPointerTy());
14212 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14213 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14214 MachinePointerInfo::getConstantPool(),
14215 false, false, false, Alignment);
14216 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
14217 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
14218 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
14219 }
14221 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
14222 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
14223 if (Subtarget->hasInt256()) {
14224 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
14225 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
14226 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
14227 ShufMask);
14228 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
14229 DAG.getIntPtrConstant(0));
14230 }
14232 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14233 DAG.getIntPtrConstant(0));
14234 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14235 DAG.getIntPtrConstant(2));
14236 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14237 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14238 static const int ShufMask[] = {0, 2, 4, 6};
14239 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
14240 }
14242 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
14243 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
14244 if (Subtarget->hasInt256()) {
14245 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
14247 SmallVector<SDValue,32> pshufbMask;
14248 for (unsigned i = 0; i < 2; ++i) {
14249 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
14250 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
14251 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
14252 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
14253 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
14254 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
14255 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
14256 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
14257 for (unsigned j = 0; j < 8; ++j)
14258 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
14259 }
14260 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
14261 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
14262 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
14264 static const int ShufMask[] = {0, 2, -1, -1};
14265 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
14266 &ShufMask[0]);
14267 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14268 DAG.getIntPtrConstant(0));
14269 return DAG.getNode(ISD::BITCAST, DL, VT, In);
14270 }
14272 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14273 DAG.getIntPtrConstant(0));
14275 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14276 DAG.getIntPtrConstant(4));
14278 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
14279 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
14281 // The PSHUFB mask:
14282 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
14283 -1, -1, -1, -1, -1, -1, -1, -1};
14285 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
14286 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
14287 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
14289 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14290 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14292 // The MOVLHPS Mask:
14293 static const int ShufMask2[] = {0, 1, 4, 5};
14294 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
14295 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
14296 }
14298 // Handle truncation of V256 to V128 using shuffles.
14299 if (!VT.is128BitVector() || !InVT.is256BitVector())
14300 return SDValue();
14302 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
14304 unsigned NumElems = VT.getVectorNumElements();
14305 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
14307 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
14308 // Prepare truncation shuffle mask
14309 for (unsigned i = 0; i != NumElems; ++i)
14310 MaskVec[i] = i * 2;
14311 SDValue V = DAG.getVectorShuffle(NVT, DL,
14312 DAG.getNode(ISD::BITCAST, DL, NVT, In),
14313 DAG.getUNDEF(NVT), &MaskVec[0]);
14314 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
14315 DAG.getIntPtrConstant(0));
14316 }
14318 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
14319 SelectionDAG &DAG) const {
14320 assert(!Op.getSimpleValueType().isVector());
14322 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14323 /*IsSigned=*/ true, /*IsReplace=*/ false);
14324 SDValue FIST = Vals.first, StackSlot = Vals.second;
14325 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
14326 if (!FIST.getNode()) return Op;
14328 if (StackSlot.getNode())
14329 // Load the result.
14330 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14331 FIST, StackSlot, MachinePointerInfo(),
14332 false, false, false, 0);
14334 // The node is the result.
14335 return FIST;
14336 }
14338 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
14339 SelectionDAG &DAG) const {
14340 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14341 /*IsSigned=*/ false, /*IsReplace=*/ false);
14342 SDValue FIST = Vals.first, StackSlot = Vals.second;
14343 assert(FIST.getNode() && "Unexpected failure");
14345 if (StackSlot.getNode())
14346 // Load the result.
14347 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14348 FIST, StackSlot, MachinePointerInfo(),
14349 false, false, false, 0);
14351 // The node is the result.
14352 return FIST;
14353 }
14355 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
14356 SDLoc DL(Op);
14357 MVT VT = Op.getSimpleValueType();
14358 SDValue In = Op.getOperand(0);
14359 MVT SVT = In.getSimpleValueType();
14361 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
14363 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
14364 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
14365 In, DAG.getUNDEF(SVT)));
14366 }
14368 /// The only differences between FABS and FNEG are the mask and the logic op.
14369 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
14370 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
14371 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
14372 "Wrong opcode for lowering FABS or FNEG.");
14374 bool IsFABS = (Op.getOpcode() == ISD::FABS);
14376 // If this is a FABS and it has an FNEG user, bail out to fold the combination
14377 // into an FNABS. We'll lower the FABS after that if it is still in use.
14378 if (IsFABS)
14379 for (SDNode *User : Op->uses())
14380 if (User->getOpcode() == ISD::FNEG)
14381 return Op;
14383 SDValue Op0 = Op.getOperand(0);
14384 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
14386 SDLoc dl(Op);
14387 MVT VT = Op.getSimpleValueType();
14388 // Assume scalar op for initialization; update for vector if needed.
14389 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
14390 // generate a 16-byte vector constant and logic op even for the scalar case.
14391 // Using a 16-byte mask allows folding the load of the mask with
14392 // the logic op, so it can save (~4 bytes) on code size.
14393 MVT EltVT = VT;
14394 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
14395 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
14396 // decide if we should generate a 16-byte constant mask when we only need 4 or
14397 // 8 bytes for the scalar case.
14398 if (VT.isVector()) {
14399 EltVT = VT.getVectorElementType();
14400 NumElts = VT.getVectorNumElements();
14401 }
14403 unsigned EltBits = EltVT.getSizeInBits();
14404 LLVMContext *Context = DAG.getContext();
14405 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
14406 APInt MaskElt =
14407 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
14408 Constant *C = ConstantInt::get(*Context, MaskElt);
14409 C = ConstantVector::getSplat(NumElts, C);
14410 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14411 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
14412 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
14413 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14414 MachinePointerInfo::getConstantPool(),
14415 false, false, false, Alignment);
14417 if (VT.isVector()) {
14418 // For a vector, cast operands to a vector type, perform the logic op,
14419 // and cast the result back to the original value type.
14420 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
14421 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
14422 SDValue Operand = IsFNABS ?
14423 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
14424 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
14425 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
14426 return DAG.getNode(ISD::BITCAST, dl, VT,
14427 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
14428 }
14430 // If not vector, then scalar.
14431 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
14432 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
14433 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
14434 }
14436 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
14437 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14438 LLVMContext *Context = DAG.getContext();
14439 SDValue Op0 = Op.getOperand(0);
14440 SDValue Op1 = Op.getOperand(1);
14441 SDLoc dl(Op);
14442 MVT VT = Op.getSimpleValueType();
14443 MVT SrcVT = Op1.getSimpleValueType();
14445 // If second operand is smaller, extend it first.
14446 if (SrcVT.bitsLT(VT)) {
14447 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
14448 SrcVT = VT;
14449 }
14450 // And if it is bigger, shrink it first.
14451 if (SrcVT.bitsGT(VT)) {
14452 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
14453 SrcVT = VT;
14454 }
14456 // At this point the operands and the result should have the same
14457 // type, and that won't be f80 since that is not custom lowered.
14459 // First get the sign bit of second operand.
14460 SmallVector<Constant*,4> CV;
14461 if (SrcVT == MVT::f64) {
14462 const fltSemantics &Sem = APFloat::IEEEdouble;
14463 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
14464 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
14465 } else {
14466 const fltSemantics &Sem = APFloat::IEEEsingle;
14467 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
14468 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14469 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14470 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14471 }
14472 Constant *C = ConstantVector::get(CV);
14473 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14474 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
14475 MachinePointerInfo::getConstantPool(),
14476 false, false, false, 16);
14477 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
14479 // Clear first operand sign bit.
14480 CV.clear();
14481 if (VT == MVT::f64) {
14482 const fltSemantics &Sem = APFloat::IEEEdouble;
14483 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
14484 APInt(64, ~(1ULL << 63)))));
14485 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
14486 } else {
14487 const fltSemantics &Sem = APFloat::IEEEsingle;
14488 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
14489 APInt(32, ~(1U << 31)))));
14490 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14491 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14492 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14493 }
14494 C = ConstantVector::get(CV);
14495 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14496 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14497 MachinePointerInfo::getConstantPool(),
14498 false, false, false, 16);
14499 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
14501 // Or the value with the sign bit.
14502 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
14503 }
14505 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
14506 SDValue N0 = Op.getOperand(0);
14507 SDLoc dl(Op);
14508 MVT VT = Op.getSimpleValueType();
14510 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
14511 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
14512 DAG.getConstant(1, VT));
14513 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
14514 }
14516 // Check whether an OR'd tree is PTEST-able.
14517 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
14518 SelectionDAG &DAG) {
14519 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
14521 if (!Subtarget->hasSSE41())
14522 return SDValue();
14524 if (!Op->hasOneUse())
14525 return SDValue();
14527 SDNode *N = Op.getNode();
14528 SDLoc DL(N);
14530 SmallVector<SDValue, 8> Opnds;
14531 DenseMap<SDValue, unsigned> VecInMap;
14532 SmallVector<SDValue, 8> VecIns;
14533 EVT VT = MVT::Other;
14535 // Recognize a special case where a vector is casted into wide integer to
14536 // test all 0s.
14537 Opnds.push_back(N->getOperand(0));
14538 Opnds.push_back(N->getOperand(1));
14540 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
14541 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
14542 // BFS traverse all OR'd operands.
14543 if (I->getOpcode() == ISD::OR) {
14544 Opnds.push_back(I->getOperand(0));
14545 Opnds.push_back(I->getOperand(1));
14546 // Re-evaluate the number of nodes to be traversed.
14547 e += 2; // 2 more nodes (LHS and RHS) are pushed.
14548 continue;
14549 }
14551 // Quit if a non-EXTRACT_VECTOR_ELT
14552 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
14553 return SDValue();
14555 // Quit if without a constant index.
14556 SDValue Idx = I->getOperand(1);
14557 if (!isa<ConstantSDNode>(Idx))
14558 return SDValue();
14560 SDValue ExtractedFromVec = I->getOperand(0);
14561 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
14562 if (M == VecInMap.end()) {
14563 VT = ExtractedFromVec.getValueType();
14564 // Quit if not 128/256-bit vector.
14565 if (!VT.is128BitVector() && !VT.is256BitVector())
14566 return SDValue();
14567 // Quit if not the same type.
14568 if (VecInMap.begin() != VecInMap.end() &&
14569 VT != VecInMap.begin()->first.getValueType())
14570 return SDValue();
14571 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
14572 VecIns.push_back(ExtractedFromVec);
14573 }
14574 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
14575 }
14577 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14578 "Not extracted from 128-/256-bit vector.");
14580 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
14582 for (DenseMap<SDValue, unsigned>::const_iterator
14583 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
14584 // Quit if not all elements are used.
14585 if (I->second != FullMask)
14586 return SDValue();
14587 }
14589 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
14591 // Cast all vectors into TestVT for PTEST.
14592 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
14593 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
14595 // If more than one full vectors are evaluated, OR them first before PTEST.
14596 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
14597 // Each iteration will OR 2 nodes and append the result until there is only
14598 // 1 node left, i.e. the final OR'd value of all vectors.
14599 SDValue LHS = VecIns[Slot];
14600 SDValue RHS = VecIns[Slot + 1];
14601 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
14602 }
14604 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
14605 VecIns.back(), VecIns.back());
14606 }
14608 /// \brief return true if \c Op has a use that doesn't just read flags.
14609 static bool hasNonFlagsUse(SDValue Op) {
14610 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
14611 ++UI) {
14612 SDNode *User = *UI;
14613 unsigned UOpNo = UI.getOperandNo();
14614 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
14615 // Look pass truncate.
14616 UOpNo = User->use_begin().getOperandNo();
14617 User = *User->use_begin();
14618 }
14620 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
14621 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
14622 return true;
14623 }
14624 return false;
14625 }
14627 /// Emit nodes that will be selected as "test Op0,Op0", or something
14628 /// equivalent.
14629 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
14630 SelectionDAG &DAG) const {
14631 if (Op.getValueType() == MVT::i1)
14632 // KORTEST instruction should be selected
14633 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14634 DAG.getConstant(0, Op.getValueType()));
14636 // CF and OF aren't always set the way we want. Determine which
14637 // of these we need.
14638 bool NeedCF = false;
14639 bool NeedOF = false;
14640 switch (X86CC) {
14641 default: break;
14642 case X86::COND_A: case X86::COND_AE:
14643 case X86::COND_B: case X86::COND_BE:
14644 NeedCF = true;
14645 break;
14646 case X86::COND_G: case X86::COND_GE:
14647 case X86::COND_L: case X86::COND_LE:
14648 case X86::COND_O: case X86::COND_NO: {
14649 // Check if we really need to set the
14650 // Overflow flag. If NoSignedWrap is present
14651 // that is not actually needed.
14652 switch (Op->getOpcode()) {
14653 case ISD::ADD:
14654 case ISD::SUB:
14655 case ISD::MUL:
14656 case ISD::SHL: {
14657 const BinaryWithFlagsSDNode *BinNode =
14658 cast<BinaryWithFlagsSDNode>(Op.getNode());
14659 if (BinNode->hasNoSignedWrap())
14660 break;
14661 }
14662 default:
14663 NeedOF = true;
14664 break;
14665 }
14666 break;
14667 }
14668 }
14669 // See if we can use the EFLAGS value from the operand instead of
14670 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
14671 // we prove that the arithmetic won't overflow, we can't use OF or CF.
14672 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
14673 // Emit a CMP with 0, which is the TEST pattern.
14674 //if (Op.getValueType() == MVT::i1)
14675 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
14676 // DAG.getConstant(0, MVT::i1));
14677 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14678 DAG.getConstant(0, Op.getValueType()));
14679 }
14680 unsigned Opcode = 0;
14681 unsigned NumOperands = 0;
14683 // Truncate operations may prevent the merge of the SETCC instruction
14684 // and the arithmetic instruction before it. Attempt to truncate the operands
14685 // of the arithmetic instruction and use a reduced bit-width instruction.
14686 bool NeedTruncation = false;
14687 SDValue ArithOp = Op;
14688 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
14689 SDValue Arith = Op->getOperand(0);
14690 // Both the trunc and the arithmetic op need to have one user each.
14691 if (Arith->hasOneUse())
14692 switch (Arith.getOpcode()) {
14693 default: break;
14694 case ISD::ADD:
14695 case ISD::SUB:
14696 case ISD::AND:
14697 case ISD::OR:
14698 case ISD::XOR: {
14699 NeedTruncation = true;
14700 ArithOp = Arith;
14701 }
14702 }
14703 }
14705 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
14706 // which may be the result of a CAST. We use the variable 'Op', which is the
14707 // non-casted variable when we check for possible users.
14708 switch (ArithOp.getOpcode()) {
14709 case ISD::ADD:
14710 // Due to an isel shortcoming, be conservative if this add is likely to be
14711 // selected as part of a load-modify-store instruction. When the root node
14712 // in a match is a store, isel doesn't know how to remap non-chain non-flag
14713 // uses of other nodes in the match, such as the ADD in this case. This
14714 // leads to the ADD being left around and reselected, with the result being
14715 // two adds in the output. Alas, even if none our users are stores, that
14716 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
14717 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
14718 // climbing the DAG back to the root, and it doesn't seem to be worth the
14719 // effort.
14720 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14721 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14722 if (UI->getOpcode() != ISD::CopyToReg &&
14723 UI->getOpcode() != ISD::SETCC &&
14724 UI->getOpcode() != ISD::STORE)
14725 goto default_case;
14727 if (ConstantSDNode *C =
14728 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
14729 // An add of one will be selected as an INC.
14730 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
14731 Opcode = X86ISD::INC;
14732 NumOperands = 1;
14733 break;
14734 }
14736 // An add of negative one (subtract of one) will be selected as a DEC.
14737 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
14738 Opcode = X86ISD::DEC;
14739 NumOperands = 1;
14740 break;
14741 }
14742 }
14744 // Otherwise use a regular EFLAGS-setting add.
14745 Opcode = X86ISD::ADD;
14746 NumOperands = 2;
14747 break;
14748 case ISD::SHL:
14749 case ISD::SRL:
14750 // If we have a constant logical shift that's only used in a comparison
14751 // against zero turn it into an equivalent AND. This allows turning it into
14752 // a TEST instruction later.
14753 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
14754 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
14755 EVT VT = Op.getValueType();
14756 unsigned BitWidth = VT.getSizeInBits();
14757 unsigned ShAmt = Op->getConstantOperandVal(1);
14758 if (ShAmt >= BitWidth) // Avoid undefined shifts.
14759 break;
14760 APInt Mask = ArithOp.getOpcode() == ISD::SRL
14761 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
14762 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
14763 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
14764 break;
14765 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
14766 DAG.getConstant(Mask, VT));
14767 DAG.ReplaceAllUsesWith(Op, New);
14768 Op = New;
14769 }
14770 break;
14772 case ISD::AND:
14773 // If the primary and result isn't used, don't bother using X86ISD::AND,
14774 // because a TEST instruction will be better.
14775 if (!hasNonFlagsUse(Op))
14776 break;
14777 // FALL THROUGH
14778 case ISD::SUB:
14779 case ISD::OR:
14780 case ISD::XOR:
14781 // Due to the ISEL shortcoming noted above, be conservative if this op is
14782 // likely to be selected as part of a load-modify-store instruction.
14783 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14784 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14785 if (UI->getOpcode() == ISD::STORE)
14786 goto default_case;
14788 // Otherwise use a regular EFLAGS-setting instruction.
14789 switch (ArithOp.getOpcode()) {
14790 default: llvm_unreachable("unexpected operator!");
14791 case ISD::SUB: Opcode = X86ISD::SUB; break;
14792 case ISD::XOR: Opcode = X86ISD::XOR; break;
14793 case ISD::AND: Opcode = X86ISD::AND; break;
14794 case ISD::OR: {
14795 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
14796 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
14797 if (EFLAGS.getNode())
14798 return EFLAGS;
14799 }
14800 Opcode = X86ISD::OR;
14801 break;
14802 }
14803 }
14805 NumOperands = 2;
14806 break;
14807 case X86ISD::ADD:
14808 case X86ISD::SUB:
14809 case X86ISD::INC:
14810 case X86ISD::DEC:
14811 case X86ISD::OR:
14812 case X86ISD::XOR:
14813 case X86ISD::AND:
14814 return SDValue(Op.getNode(), 1);
14815 default:
14816 default_case:
14817 break;
14818 }
14820 // If we found that truncation is beneficial, perform the truncation and
14821 // update 'Op'.
14822 if (NeedTruncation) {
14823 EVT VT = Op.getValueType();
14824 SDValue WideVal = Op->getOperand(0);
14825 EVT WideVT = WideVal.getValueType();
14826 unsigned ConvertedOp = 0;
14827 // Use a target machine opcode to prevent further DAGCombine
14828 // optimizations that may separate the arithmetic operations
14829 // from the setcc node.
14830 switch (WideVal.getOpcode()) {
14831 default: break;
14832 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
14833 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
14834 case ISD::AND: ConvertedOp = X86ISD::AND; break;
14835 case ISD::OR: ConvertedOp = X86ISD::OR; break;
14836 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
14837 }
14839 if (ConvertedOp) {
14840 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14841 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
14842 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
14843 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
14844 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
14845 }
14846 }
14847 }
14849 if (Opcode == 0)
14850 // Emit a CMP with 0, which is the TEST pattern.
14851 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14852 DAG.getConstant(0, Op.getValueType()));
14854 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14855 SmallVector<SDValue, 4> Ops;
14856 for (unsigned i = 0; i != NumOperands; ++i)
14857 Ops.push_back(Op.getOperand(i));
14859 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
14860 DAG.ReplaceAllUsesWith(Op, New);
14861 return SDValue(New.getNode(), 1);
14862 }
14864 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
14865 /// equivalent.
14866 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
14867 SDLoc dl, SelectionDAG &DAG) const {
14868 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
14869 if (C->getAPIntValue() == 0)
14870 return EmitTest(Op0, X86CC, dl, DAG);
14872 if (Op0.getValueType() == MVT::i1)
14873 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
14874 }
14876 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
14877 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
14878 // Do the comparison at i32 if it's smaller, besides the Atom case.
14879 // This avoids subregister aliasing issues. Keep the smaller reference
14880 // if we're optimizing for size, however, as that'll allow better folding
14881 // of memory operations.
14882 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
14883 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
14884 AttributeSet::FunctionIndex, Attribute::MinSize) &&
14885 !Subtarget->isAtom()) {
14886 unsigned ExtendOp =
14887 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
14888 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
14889 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
14890 }
14891 // Use SUB instead of CMP to enable CSE between SUB and CMP.
14892 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
14893 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
14894 Op0, Op1);
14895 return SDValue(Sub.getNode(), 1);
14896 }
14897 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
14898 }
14900 /// Convert a comparison if required by the subtarget.
14901 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
14902 SelectionDAG &DAG) const {
14903 // If the subtarget does not support the FUCOMI instruction, floating-point
14904 // comparisons have to be converted.
14905 if (Subtarget->hasCMov() ||
14906 Cmp.getOpcode() != X86ISD::CMP ||
14907 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
14908 !Cmp.getOperand(1).getValueType().isFloatingPoint())
14909 return Cmp;
14911 // The instruction selector will select an FUCOM instruction instead of
14912 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
14913 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
14914 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
14915 SDLoc dl(Cmp);
14916 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
14917 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
14918 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
14919 DAG.getConstant(8, MVT::i8));
14920 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
14921 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
14922 }
14924 /// The minimum architected relative accuracy is 2^-12. We need one
14925 /// Newton-Raphson step to have a good float result (24 bits of precision).
14926 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
14927 DAGCombinerInfo &DCI,
14928 unsigned &RefinementSteps,
14929 bool &UseOneConstNR) const {
14930 // FIXME: We should use instruction latency models to calculate the cost of
14931 // each potential sequence, but this is very hard to do reliably because
14932 // at least Intel's Core* chips have variable timing based on the number of
14933 // significant digits in the divisor and/or sqrt operand.
14934 if (!Subtarget->useSqrtEst())
14935 return SDValue();
14937 EVT VT = Op.getValueType();
14939 // SSE1 has rsqrtss and rsqrtps.
14940 // TODO: Add support for AVX512 (v16f32).
14941 // It is likely not profitable to do this for f64 because a double-precision
14942 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
14943 // instructions: convert to single, rsqrtss, convert back to double, refine
14944 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
14945 // along with FMA, this could be a throughput win.
14946 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14947 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
14948 RefinementSteps = 1;
14949 UseOneConstNR = false;
14950 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
14951 }
14952 return SDValue();
14953 }
14955 /// The minimum architected relative accuracy is 2^-12. We need one
14956 /// Newton-Raphson step to have a good float result (24 bits of precision).
14957 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
14958 DAGCombinerInfo &DCI,
14959 unsigned &RefinementSteps) const {
14960 // FIXME: We should use instruction latency models to calculate the cost of
14961 // each potential sequence, but this is very hard to do reliably because
14962 // at least Intel's Core* chips have variable timing based on the number of
14963 // significant digits in the divisor.
14964 if (!Subtarget->useReciprocalEst())
14965 return SDValue();
14967 EVT VT = Op.getValueType();
14969 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
14970 // TODO: Add support for AVX512 (v16f32).
14971 // It is likely not profitable to do this for f64 because a double-precision
14972 // reciprocal estimate with refinement on x86 prior to FMA requires
14973 // 15 instructions: convert to single, rcpss, convert back to double, refine
14974 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
14975 // along with FMA, this could be a throughput win.
14976 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14977 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
14978 RefinementSteps = ReciprocalEstimateRefinementSteps;
14979 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
14980 }
14981 return SDValue();
14982 }
14984 static bool isAllOnes(SDValue V) {
14985 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
14986 return C && C->isAllOnesValue();
14987 }
14989 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
14990 /// if it's possible.
14991 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
14992 SDLoc dl, SelectionDAG &DAG) const {
14993 SDValue Op0 = And.getOperand(0);
14994 SDValue Op1 = And.getOperand(1);
14995 if (Op0.getOpcode() == ISD::TRUNCATE)
14996 Op0 = Op0.getOperand(0);
14997 if (Op1.getOpcode() == ISD::TRUNCATE)
14998 Op1 = Op1.getOperand(0);
15000 SDValue LHS, RHS;
15001 if (Op1.getOpcode() == ISD::SHL)
15002 std::swap(Op0, Op1);
15003 if (Op0.getOpcode() == ISD::SHL) {
15004 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
15005 if (And00C->getZExtValue() == 1) {
15006 // If we looked past a truncate, check that it's only truncating away
15007 // known zeros.
15008 unsigned BitWidth = Op0.getValueSizeInBits();
15009 unsigned AndBitWidth = And.getValueSizeInBits();
15010 if (BitWidth > AndBitWidth) {
15011 APInt Zeros, Ones;
15012 DAG.computeKnownBits(Op0, Zeros, Ones);
15013 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
15014 return SDValue();
15015 }
15016 LHS = Op1;
15017 RHS = Op0.getOperand(1);
15018 }
15019 } else if (Op1.getOpcode() == ISD::Constant) {
15020 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
15021 uint64_t AndRHSVal = AndRHS->getZExtValue();
15022 SDValue AndLHS = Op0;
15024 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
15025 LHS = AndLHS.getOperand(0);
15026 RHS = AndLHS.getOperand(1);
15027 }
15029 // Use BT if the immediate can't be encoded in a TEST instruction.
15030 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
15031 LHS = AndLHS;
15032 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
15033 }
15034 }
15036 if (LHS.getNode()) {
15037 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
15038 // instruction. Since the shift amount is in-range-or-undefined, we know
15039 // that doing a bittest on the i32 value is ok. We extend to i32 because
15040 // the encoding for the i16 version is larger than the i32 version.
15041 // Also promote i16 to i32 for performance / code size reason.
15042 if (LHS.getValueType() == MVT::i8 ||
15043 LHS.getValueType() == MVT::i16)
15044 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
15046 // If the operand types disagree, extend the shift amount to match. Since
15047 // BT ignores high bits (like shifts) we can use anyextend.
15048 if (LHS.getValueType() != RHS.getValueType())
15049 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
15051 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
15052 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
15053 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15054 DAG.getConstant(Cond, MVT::i8), BT);
15055 }
15057 return SDValue();
15058 }
15060 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
15061 /// mask CMPs.
15062 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
15063 SDValue &Op1) {
15064 unsigned SSECC;
15065 bool Swap = false;
15067 // SSE Condition code mapping:
15068 // 0 - EQ
15069 // 1 - LT
15070 // 2 - LE
15071 // 3 - UNORD
15072 // 4 - NEQ
15073 // 5 - NLT
15074 // 6 - NLE
15075 // 7 - ORD
15076 switch (SetCCOpcode) {
15077 default: llvm_unreachable("Unexpected SETCC condition");
15078 case ISD::SETOEQ:
15079 case ISD::SETEQ: SSECC = 0; break;
15080 case ISD::SETOGT:
15081 case ISD::SETGT: Swap = true; // Fallthrough
15082 case ISD::SETLT:
15083 case ISD::SETOLT: SSECC = 1; break;
15084 case ISD::SETOGE:
15085 case ISD::SETGE: Swap = true; // Fallthrough
15086 case ISD::SETLE:
15087 case ISD::SETOLE: SSECC = 2; break;
15088 case ISD::SETUO: SSECC = 3; break;
15089 case ISD::SETUNE:
15090 case ISD::SETNE: SSECC = 4; break;
15091 case ISD::SETULE: Swap = true; // Fallthrough
15092 case ISD::SETUGE: SSECC = 5; break;
15093 case ISD::SETULT: Swap = true; // Fallthrough
15094 case ISD::SETUGT: SSECC = 6; break;
15095 case ISD::SETO: SSECC = 7; break;
15096 case ISD::SETUEQ:
15097 case ISD::SETONE: SSECC = 8; break;
15098 }
15099 if (Swap)
15100 std::swap(Op0, Op1);
15102 return SSECC;
15103 }
15105 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
15106 // ones, and then concatenate the result back.
15107 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
15108 MVT VT = Op.getSimpleValueType();
15110 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
15111 "Unsupported value type for operation");
15113 unsigned NumElems = VT.getVectorNumElements();
15114 SDLoc dl(Op);
15115 SDValue CC = Op.getOperand(2);
15117 // Extract the LHS vectors
15118 SDValue LHS = Op.getOperand(0);
15119 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
15120 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
15122 // Extract the RHS vectors
15123 SDValue RHS = Op.getOperand(1);
15124 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
15125 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
15127 // Issue the operation on the smaller types and concatenate the result back
15128 MVT EltVT = VT.getVectorElementType();
15129 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15130 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
15131 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
15132 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
15133 }
15135 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
15136 const X86Subtarget *Subtarget) {
15137 SDValue Op0 = Op.getOperand(0);
15138 SDValue Op1 = Op.getOperand(1);
15139 SDValue CC = Op.getOperand(2);
15140 MVT VT = Op.getSimpleValueType();
15141 SDLoc dl(Op);
15143 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
15144 Op.getValueType().getScalarType() == MVT::i1 &&
15145 "Cannot set masked compare for this operation");
15147 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15148 unsigned Opc = 0;
15149 bool Unsigned = false;
15150 bool Swap = false;
15151 unsigned SSECC;
15152 switch (SetCCOpcode) {
15153 default: llvm_unreachable("Unexpected SETCC condition");
15154 case ISD::SETNE: SSECC = 4; break;
15155 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
15156 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
15157 case ISD::SETLT: Swap = true; //fall-through
15158 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
15159 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
15160 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
15161 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
15162 case ISD::SETULE: Unsigned = true; //fall-through
15163 case ISD::SETLE: SSECC = 2; break;
15164 }
15166 if (Swap)
15167 std::swap(Op0, Op1);
15168 if (Opc)
15169 return DAG.getNode(Opc, dl, VT, Op0, Op1);
15170 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
15171 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15172 DAG.getConstant(SSECC, MVT::i8));
15173 }
15175 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
15176 /// operand \p Op1. If non-trivial (for example because it's not constant)
15177 /// return an empty value.
15178 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
15179 {
15180 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
15181 if (!BV)
15182 return SDValue();
15184 MVT VT = Op1.getSimpleValueType();
15185 MVT EVT = VT.getVectorElementType();
15186 unsigned n = VT.getVectorNumElements();
15187 SmallVector<SDValue, 8> ULTOp1;
15189 for (unsigned i = 0; i < n; ++i) {
15190 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
15191 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
15192 return SDValue();
15194 // Avoid underflow.
15195 APInt Val = Elt->getAPIntValue();
15196 if (Val == 0)
15197 return SDValue();
15199 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
15200 }
15202 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
15203 }
15205 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
15206 SelectionDAG &DAG) {
15207 SDValue Op0 = Op.getOperand(0);
15208 SDValue Op1 = Op.getOperand(1);
15209 SDValue CC = Op.getOperand(2);
15210 MVT VT = Op.getSimpleValueType();
15211 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15212 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
15213 SDLoc dl(Op);
15215 if (isFP) {
15216 #ifndef NDEBUG
15217 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
15218 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
15219 #endif
15221 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
15222 unsigned Opc = X86ISD::CMPP;
15223 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
15224 assert(VT.getVectorNumElements() <= 16);
15225 Opc = X86ISD::CMPM;
15226 }
15227 // In the two special cases we can't handle, emit two comparisons.
15228 if (SSECC == 8) {
15229 unsigned CC0, CC1;
15230 unsigned CombineOpc;
15231 if (SetCCOpcode == ISD::SETUEQ) {
15232 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
15233 } else {
15234 assert(SetCCOpcode == ISD::SETONE);
15235 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
15236 }
15238 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15239 DAG.getConstant(CC0, MVT::i8));
15240 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15241 DAG.getConstant(CC1, MVT::i8));
15242 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
15243 }
15244 // Handle all other FP comparisons here.
15245 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15246 DAG.getConstant(SSECC, MVT::i8));
15247 }
15249 // Break 256-bit integer vector compare into smaller ones.
15250 if (VT.is256BitVector() && !Subtarget->hasInt256())
15251 return Lower256IntVSETCC(Op, DAG);
15253 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
15254 EVT OpVT = Op1.getValueType();
15255 if (Subtarget->hasAVX512()) {
15256 if (Op1.getValueType().is512BitVector() ||
15257 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
15258 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
15259 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
15261 // In AVX-512 architecture setcc returns mask with i1 elements,
15262 // But there is no compare instruction for i8 and i16 elements in KNL.
15263 // We are not talking about 512-bit operands in this case, these
15264 // types are illegal.
15265 if (MaskResult &&
15266 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
15267 OpVT.getVectorElementType().getSizeInBits() >= 8))
15268 return DAG.getNode(ISD::TRUNCATE, dl, VT,
15269 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
15270 }
15272 // We are handling one of the integer comparisons here. Since SSE only has
15273 // GT and EQ comparisons for integer, swapping operands and multiple
15274 // operations may be required for some comparisons.
15275 unsigned Opc;
15276 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
15277 bool Subus = false;
15279 switch (SetCCOpcode) {
15280 default: llvm_unreachable("Unexpected SETCC condition");
15281 case ISD::SETNE: Invert = true;
15282 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
15283 case ISD::SETLT: Swap = true;
15284 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
15285 case ISD::SETGE: Swap = true;
15286 case ISD::SETLE: Opc = X86ISD::PCMPGT;
15287 Invert = true; break;
15288 case ISD::SETULT: Swap = true;
15289 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
15290 FlipSigns = true; break;
15291 case ISD::SETUGE: Swap = true;
15292 case ISD::SETULE: Opc = X86ISD::PCMPGT;
15293 FlipSigns = true; Invert = true; break;
15294 }
15296 // Special case: Use min/max operations for SETULE/SETUGE
15297 MVT VET = VT.getVectorElementType();
15298 bool hasMinMax =
15299 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
15300 || (Subtarget->hasSSE2() && (VET == MVT::i8));
15302 if (hasMinMax) {
15303 switch (SetCCOpcode) {
15304 default: break;
15305 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
15306 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
15307 }
15309 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
15310 }
15312 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
15313 if (!MinMax && hasSubus) {
15314 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
15315 // Op0 u<= Op1:
15316 // t = psubus Op0, Op1
15317 // pcmpeq t, <0..0>
15318 switch (SetCCOpcode) {
15319 default: break;
15320 case ISD::SETULT: {
15321 // If the comparison is against a constant we can turn this into a
15322 // setule. With psubus, setule does not require a swap. This is
15323 // beneficial because the constant in the register is no longer
15324 // destructed as the destination so it can be hoisted out of a loop.
15325 // Only do this pre-AVX since vpcmp* is no longer destructive.
15326 if (Subtarget->hasAVX())
15327 break;
15328 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
15329 if (ULEOp1.getNode()) {
15330 Op1 = ULEOp1;
15331 Subus = true; Invert = false; Swap = false;
15332 }
15333 break;
15334 }
15335 // Psubus is better than flip-sign because it requires no inversion.
15336 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
15337 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
15338 }
15340 if (Subus) {
15341 Opc = X86ISD::SUBUS;
15342 FlipSigns = false;
15343 }
15344 }
15346 if (Swap)
15347 std::swap(Op0, Op1);
15349 // Check that the operation in question is available (most are plain SSE2,
15350 // but PCMPGTQ and PCMPEQQ have different requirements).
15351 if (VT == MVT::v2i64) {
15352 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
15353 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
15355 // First cast everything to the right type.
15356 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15357 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15359 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15360 // bits of the inputs before performing those operations. The lower
15361 // compare is always unsigned.
15362 SDValue SB;
15363 if (FlipSigns) {
15364 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
15365 } else {
15366 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
15367 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
15368 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
15369 Sign, Zero, Sign, Zero);
15370 }
15371 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
15372 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
15374 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
15375 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
15376 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
15378 // Create masks for only the low parts/high parts of the 64 bit integers.
15379 static const int MaskHi[] = { 1, 1, 3, 3 };
15380 static const int MaskLo[] = { 0, 0, 2, 2 };
15381 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
15382 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
15383 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
15385 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
15386 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
15388 if (Invert)
15389 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15391 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15392 }
15394 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
15395 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
15396 // pcmpeqd + pshufd + pand.
15397 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
15399 // First cast everything to the right type.
15400 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15401 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15403 // Do the compare.
15404 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
15406 // Make sure the lower and upper halves are both all-ones.
15407 static const int Mask[] = { 1, 0, 3, 2 };
15408 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
15409 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
15411 if (Invert)
15412 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15414 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15415 }
15416 }
15418 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15419 // bits of the inputs before performing those operations.
15420 if (FlipSigns) {
15421 EVT EltVT = VT.getVectorElementType();
15422 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
15423 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
15424 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
15425 }
15427 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
15429 // If the logical-not of the result is required, perform that now.
15430 if (Invert)
15431 Result = DAG.getNOT(dl, Result, VT);
15433 if (MinMax)
15434 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
15436 if (Subus)
15437 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
15438 getZeroVector(VT, Subtarget, DAG, dl));
15440 return Result;
15441 }
15443 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
15445 MVT VT = Op.getSimpleValueType();
15447 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
15449 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
15450 && "SetCC type must be 8-bit or 1-bit integer");
15451 SDValue Op0 = Op.getOperand(0);
15452 SDValue Op1 = Op.getOperand(1);
15453 SDLoc dl(Op);
15454 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
15456 // Optimize to BT if possible.
15457 // Lower (X & (1 << N)) == 0 to BT(X, N).
15458 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
15459 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
15460 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
15461 Op1.getOpcode() == ISD::Constant &&
15462 cast<ConstantSDNode>(Op1)->isNullValue() &&
15463 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15464 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
15465 if (NewSetCC.getNode())
15466 return NewSetCC;
15467 }
15469 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
15470 // these.
15471 if (Op1.getOpcode() == ISD::Constant &&
15472 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
15473 cast<ConstantSDNode>(Op1)->isNullValue()) &&
15474 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15476 // If the input is a setcc, then reuse the input setcc or use a new one with
15477 // the inverted condition.
15478 if (Op0.getOpcode() == X86ISD::SETCC) {
15479 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
15480 bool Invert = (CC == ISD::SETNE) ^
15481 cast<ConstantSDNode>(Op1)->isNullValue();
15482 if (!Invert)
15483 return Op0;
15485 CCode = X86::GetOppositeBranchCondition(CCode);
15486 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15487 DAG.getConstant(CCode, MVT::i8),
15488 Op0.getOperand(1));
15489 if (VT == MVT::i1)
15490 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15491 return SetCC;
15492 }
15493 }
15494 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
15495 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
15496 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15498 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
15499 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
15500 }
15502 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
15503 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
15504 if (X86CC == X86::COND_INVALID)
15505 return SDValue();
15507 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
15508 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
15509 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15510 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
15511 if (VT == MVT::i1)
15512 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15513 return SetCC;
15514 }
15516 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
15517 static bool isX86LogicalCmp(SDValue Op) {
15518 unsigned Opc = Op.getNode()->getOpcode();
15519 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
15520 Opc == X86ISD::SAHF)
15521 return true;
15522 if (Op.getResNo() == 1 &&
15523 (Opc == X86ISD::ADD ||
15524 Opc == X86ISD::SUB ||
15525 Opc == X86ISD::ADC ||
15526 Opc == X86ISD::SBB ||
15527 Opc == X86ISD::SMUL ||
15528 Opc == X86ISD::UMUL ||
15529 Opc == X86ISD::INC ||
15530 Opc == X86ISD::DEC ||
15531 Opc == X86ISD::OR ||
15532 Opc == X86ISD::XOR ||
15533 Opc == X86ISD::AND))
15534 return true;
15536 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
15537 return true;
15539 return false;
15540 }
15542 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
15543 if (V.getOpcode() != ISD::TRUNCATE)
15544 return false;
15546 SDValue VOp0 = V.getOperand(0);
15547 unsigned InBits = VOp0.getValueSizeInBits();
15548 unsigned Bits = V.getValueSizeInBits();
15549 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
15550 }
15552 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
15553 bool addTest = true;
15554 SDValue Cond = Op.getOperand(0);
15555 SDValue Op1 = Op.getOperand(1);
15556 SDValue Op2 = Op.getOperand(2);
15557 SDLoc DL(Op);
15558 EVT VT = Op1.getValueType();
15559 SDValue CC;
15561 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
15562 // are available. Otherwise fp cmovs get lowered into a less efficient branch
15563 // sequence later on.
15564 if (Cond.getOpcode() == ISD::SETCC &&
15565 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
15566 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
15567 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
15568 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
15569 int SSECC = translateX86FSETCC(
15570 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
15572 if (SSECC != 8) {
15573 if (Subtarget->hasAVX512()) {
15574 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
15575 DAG.getConstant(SSECC, MVT::i8));
15576 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
15577 }
15578 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
15579 DAG.getConstant(SSECC, MVT::i8));
15580 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
15581 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
15582 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
15583 }
15584 }
15586 if (Cond.getOpcode() == ISD::SETCC) {
15587 SDValue NewCond = LowerSETCC(Cond, DAG);
15588 if (NewCond.getNode())
15589 Cond = NewCond;
15590 }
15592 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
15593 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
15594 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
15595 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
15596 if (Cond.getOpcode() == X86ISD::SETCC &&
15597 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
15598 isZero(Cond.getOperand(1).getOperand(1))) {
15599 SDValue Cmp = Cond.getOperand(1);
15601 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
15603 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
15604 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
15605 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
15607 SDValue CmpOp0 = Cmp.getOperand(0);
15608 // Apply further optimizations for special cases
15609 // (select (x != 0), -1, 0) -> neg & sbb
15610 // (select (x == 0), 0, -1) -> neg & sbb
15611 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
15612 if (YC->isNullValue() &&
15613 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
15614 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
15615 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
15616 DAG.getConstant(0, CmpOp0.getValueType()),
15617 CmpOp0);
15618 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15619 DAG.getConstant(X86::COND_B, MVT::i8),
15620 SDValue(Neg.getNode(), 1));
15621 return Res;
15622 }
15624 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
15625 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
15626 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15628 SDValue Res = // Res = 0 or -1.
15629 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15630 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
15632 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
15633 Res = DAG.getNOT(DL, Res, Res.getValueType());
15635 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
15636 if (!N2C || !N2C->isNullValue())
15637 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
15638 return Res;
15639 }
15640 }
15642 // Look past (and (setcc_carry (cmp ...)), 1).
15643 if (Cond.getOpcode() == ISD::AND &&
15644 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15645 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15646 if (C && C->getAPIntValue() == 1)
15647 Cond = Cond.getOperand(0);
15648 }
15650 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15651 // setting operand in place of the X86ISD::SETCC.
15652 unsigned CondOpcode = Cond.getOpcode();
15653 if (CondOpcode == X86ISD::SETCC ||
15654 CondOpcode == X86ISD::SETCC_CARRY) {
15655 CC = Cond.getOperand(0);
15657 SDValue Cmp = Cond.getOperand(1);
15658 unsigned Opc = Cmp.getOpcode();
15659 MVT VT = Op.getSimpleValueType();
15661 bool IllegalFPCMov = false;
15662 if (VT.isFloatingPoint() && !VT.isVector() &&
15663 !isScalarFPTypeInSSEReg(VT)) // FPStack?
15664 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
15666 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
15667 Opc == X86ISD::BT) { // FIXME
15668 Cond = Cmp;
15669 addTest = false;
15670 }
15671 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15672 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15673 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15674 Cond.getOperand(0).getValueType() != MVT::i8)) {
15675 SDValue LHS = Cond.getOperand(0);
15676 SDValue RHS = Cond.getOperand(1);
15677 unsigned X86Opcode;
15678 unsigned X86Cond;
15679 SDVTList VTs;
15680 switch (CondOpcode) {
15681 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15682 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15683 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15684 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15685 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15686 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15687 default: llvm_unreachable("unexpected overflowing operator");
15688 }
15689 if (CondOpcode == ISD::UMULO)
15690 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15691 MVT::i32);
15692 else
15693 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15695 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
15697 if (CondOpcode == ISD::UMULO)
15698 Cond = X86Op.getValue(2);
15699 else
15700 Cond = X86Op.getValue(1);
15702 CC = DAG.getConstant(X86Cond, MVT::i8);
15703 addTest = false;
15704 }
15706 if (addTest) {
15707 // Look pass the truncate if the high bits are known zero.
15708 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15709 Cond = Cond.getOperand(0);
15711 // We know the result of AND is compared against zero. Try to match
15712 // it to BT.
15713 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15714 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
15715 if (NewSetCC.getNode()) {
15716 CC = NewSetCC.getOperand(0);
15717 Cond = NewSetCC.getOperand(1);
15718 addTest = false;
15719 }
15720 }
15721 }
15723 if (addTest) {
15724 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15725 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
15726 }
15728 // a < b ? -1 : 0 -> RES = ~setcc_carry
15729 // a < b ? 0 : -1 -> RES = setcc_carry
15730 // a >= b ? -1 : 0 -> RES = setcc_carry
15731 // a >= b ? 0 : -1 -> RES = ~setcc_carry
15732 if (Cond.getOpcode() == X86ISD::SUB) {
15733 Cond = ConvertCmpIfNecessary(Cond, DAG);
15734 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
15736 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
15737 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
15738 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15739 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
15740 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
15741 return DAG.getNOT(DL, Res, Res.getValueType());
15742 return Res;
15743 }
15744 }
15746 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
15747 // widen the cmov and push the truncate through. This avoids introducing a new
15748 // branch during isel and doesn't add any extensions.
15749 if (Op.getValueType() == MVT::i8 &&
15750 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
15751 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
15752 if (T1.getValueType() == T2.getValueType() &&
15753 // Blacklist CopyFromReg to avoid partial register stalls.
15754 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
15755 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
15756 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
15757 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
15758 }
15759 }
15761 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
15762 // condition is true.
15763 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
15764 SDValue Ops[] = { Op2, Op1, CC, Cond };
15765 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
15766 }
15768 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, const X86Subtarget *Subtarget,
15769 SelectionDAG &DAG) {
15770 MVT VT = Op->getSimpleValueType(0);
15771 SDValue In = Op->getOperand(0);
15772 MVT InVT = In.getSimpleValueType();
15773 MVT VTElt = VT.getVectorElementType();
15774 MVT InVTElt = InVT.getVectorElementType();
15775 SDLoc dl(Op);
15777 // SKX processor
15778 if ((InVTElt == MVT::i1) &&
15779 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
15780 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
15782 ((Subtarget->hasBWI() && VT.is512BitVector() &&
15783 VTElt.getSizeInBits() <= 16)) ||
15785 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
15786 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
15788 ((Subtarget->hasDQI() && VT.is512BitVector() &&
15789 VTElt.getSizeInBits() >= 32))))
15790 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15792 unsigned int NumElts = VT.getVectorNumElements();
15794 if (NumElts != 8 && NumElts != 16)
15795 return SDValue();
15797 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
15798 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
15799 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
15800 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15801 }
15803 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15804 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15806 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
15807 Constant *C = ConstantInt::get(*DAG.getContext(),
15808 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
15810 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
15811 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
15812 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
15813 MachinePointerInfo::getConstantPool(),
15814 false, false, false, Alignment);
15815 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
15816 if (VT.is512BitVector())
15817 return Brcst;
15818 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
15819 }
15821 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15822 SelectionDAG &DAG) {
15823 MVT VT = Op->getSimpleValueType(0);
15824 SDValue In = Op->getOperand(0);
15825 MVT InVT = In.getSimpleValueType();
15826 SDLoc dl(Op);
15828 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15829 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15831 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15832 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15833 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15834 return SDValue();
15836 if (Subtarget->hasInt256())
15837 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15839 // Optimize vectors in AVX mode
15840 // Sign extend v8i16 to v8i32 and
15841 // v4i32 to v4i64
15842 //
15843 // Divide input vector into two parts
15844 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15845 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15846 // concat the vectors to original VT
15848 unsigned NumElems = InVT.getVectorNumElements();
15849 SDValue Undef = DAG.getUNDEF(InVT);
15851 SmallVector<int,8> ShufMask1(NumElems, -1);
15852 for (unsigned i = 0; i != NumElems/2; ++i)
15853 ShufMask1[i] = i;
15855 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15857 SmallVector<int,8> ShufMask2(NumElems, -1);
15858 for (unsigned i = 0; i != NumElems/2; ++i)
15859 ShufMask2[i] = i + NumElems/2;
15861 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15863 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
15864 VT.getVectorNumElements()/2);
15866 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15867 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15869 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15870 }
15872 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15873 // may emit an illegal shuffle but the expansion is still better than scalar
15874 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15875 // we'll emit a shuffle and a arithmetic shift.
15876 // TODO: It is possible to support ZExt by zeroing the undef values during
15877 // the shuffle phase or after the shuffle.
15878 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15879 SelectionDAG &DAG) {
15880 MVT RegVT = Op.getSimpleValueType();
15881 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15882 assert(RegVT.isInteger() &&
15883 "We only custom lower integer vector sext loads.");
15885 // Nothing useful we can do without SSE2 shuffles.
15886 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15888 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15889 SDLoc dl(Ld);
15890 EVT MemVT = Ld->getMemoryVT();
15891 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15892 unsigned RegSz = RegVT.getSizeInBits();
15894 ISD::LoadExtType Ext = Ld->getExtensionType();
15896 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15897 && "Only anyext and sext are currently implemented.");
15898 assert(MemVT != RegVT && "Cannot extend to the same type");
15899 assert(MemVT.isVector() && "Must load a vector from memory");
15901 unsigned NumElems = RegVT.getVectorNumElements();
15902 unsigned MemSz = MemVT.getSizeInBits();
15903 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15905 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15906 // The only way in which we have a legal 256-bit vector result but not the
15907 // integer 256-bit operations needed to directly lower a sextload is if we
15908 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15909 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15910 // correctly legalized. We do this late to allow the canonical form of
15911 // sextload to persist throughout the rest of the DAG combiner -- it wants
15912 // to fold together any extensions it can, and so will fuse a sign_extend
15913 // of an sextload into a sextload targeting a wider value.
15914 SDValue Load;
15915 if (MemSz == 128) {
15916 // Just switch this to a normal load.
15917 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15918 "it must be a legal 128-bit vector "
15919 "type!");
15920 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15921 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15922 Ld->isInvariant(), Ld->getAlignment());
15923 } else {
15924 assert(MemSz < 128 &&
15925 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15926 // Do an sext load to a 128-bit vector type. We want to use the same
15927 // number of elements, but elements half as wide. This will end up being
15928 // recursively lowered by this routine, but will succeed as we definitely
15929 // have all the necessary features if we're using AVX1.
15930 EVT HalfEltVT =
15931 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15932 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15933 Load =
15934 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15935 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15936 Ld->isNonTemporal(), Ld->isInvariant(),
15937 Ld->getAlignment());
15938 }
15940 // Replace chain users with the new chain.
15941 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15942 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15944 // Finally, do a normal sign-extend to the desired register.
15945 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15946 }
15948 // All sizes must be a power of two.
15949 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15950 "Non-power-of-two elements are not custom lowered!");
15952 // Attempt to load the original value using scalar loads.
15953 // Find the largest scalar type that divides the total loaded size.
15954 MVT SclrLoadTy = MVT::i8;
15955 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
15956 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
15957 MVT Tp = (MVT::SimpleValueType)tp;
15958 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15959 SclrLoadTy = Tp;
15960 }
15961 }
15963 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15964 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15965 (64 <= MemSz))
15966 SclrLoadTy = MVT::f64;
15968 // Calculate the number of scalar loads that we need to perform
15969 // in order to load our vector from memory.
15970 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15972 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15973 "Can only lower sext loads with a single scalar load!");
15975 unsigned loadRegZize = RegSz;
15976 if (Ext == ISD::SEXTLOAD && RegSz == 256)
15977 loadRegZize /= 2;
15979 // Represent our vector as a sequence of elements which are the
15980 // largest scalar that we can load.
15981 EVT LoadUnitVecVT = EVT::getVectorVT(
15982 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15984 // Represent the data using the same element type that is stored in
15985 // memory. In practice, we ''widen'' MemVT.
15986 EVT WideVecVT =
15987 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15988 loadRegZize / MemVT.getScalarType().getSizeInBits());
15990 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15991 "Invalid vector type");
15993 // We can't shuffle using an illegal type.
15994 assert(TLI.isTypeLegal(WideVecVT) &&
15995 "We only lower types that form legal widened vector types");
15997 SmallVector<SDValue, 8> Chains;
15998 SDValue Ptr = Ld->getBasePtr();
15999 SDValue Increment =
16000 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
16001 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
16003 for (unsigned i = 0; i < NumLoads; ++i) {
16004 // Perform a single load.
16005 SDValue ScalarLoad =
16006 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
16007 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
16008 Ld->getAlignment());
16009 Chains.push_back(ScalarLoad.getValue(1));
16010 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
16011 // another round of DAGCombining.
16012 if (i == 0)
16013 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
16014 else
16015 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
16016 ScalarLoad, DAG.getIntPtrConstant(i));
16018 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
16019 }
16021 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
16023 // Bitcast the loaded value to a vector of the original element type, in
16024 // the size of the target vector type.
16025 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
16026 unsigned SizeRatio = RegSz / MemSz;
16028 if (Ext == ISD::SEXTLOAD) {
16029 // If we have SSE4.1, we can directly emit a VSEXT node.
16030 if (Subtarget->hasSSE41()) {
16031 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
16032 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16033 return Sext;
16034 }
16036 // Otherwise we'll shuffle the small elements in the high bits of the
16037 // larger type and perform an arithmetic shift. If the shift is not legal
16038 // it's better to scalarize.
16039 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
16040 "We can't implement a sext load without an arithmetic right shift!");
16042 // Redistribute the loaded elements into the different locations.
16043 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
16044 for (unsigned i = 0; i != NumElems; ++i)
16045 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
16047 SDValue Shuff = DAG.getVectorShuffle(
16048 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
16050 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16052 // Build the arithmetic shift.
16053 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
16054 MemVT.getVectorElementType().getSizeInBits();
16055 Shuff =
16056 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
16058 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16059 return Shuff;
16060 }
16062 // Redistribute the loaded elements into the different locations.
16063 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
16064 for (unsigned i = 0; i != NumElems; ++i)
16065 ShuffleVec[i * SizeRatio] = i;
16067 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
16068 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
16070 // Bitcast to the requested type.
16071 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16072 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16073 return Shuff;
16074 }
16076 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
16077 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
16078 // from the AND / OR.
16079 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
16080 Opc = Op.getOpcode();
16081 if (Opc != ISD::OR && Opc != ISD::AND)
16082 return false;
16083 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
16084 Op.getOperand(0).hasOneUse() &&
16085 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
16086 Op.getOperand(1).hasOneUse());
16087 }
16089 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
16090 // 1 and that the SETCC node has a single use.
16091 static bool isXor1OfSetCC(SDValue Op) {
16092 if (Op.getOpcode() != ISD::XOR)
16093 return false;
16094 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
16095 if (N1C && N1C->getAPIntValue() == 1) {
16096 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
16097 Op.getOperand(0).hasOneUse();
16098 }
16099 return false;
16100 }
16102 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
16103 bool addTest = true;
16104 SDValue Chain = Op.getOperand(0);
16105 SDValue Cond = Op.getOperand(1);
16106 SDValue Dest = Op.getOperand(2);
16107 SDLoc dl(Op);
16108 SDValue CC;
16109 bool Inverted = false;
16111 if (Cond.getOpcode() == ISD::SETCC) {
16112 // Check for setcc([su]{add,sub,mul}o == 0).
16113 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
16114 isa<ConstantSDNode>(Cond.getOperand(1)) &&
16115 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
16116 Cond.getOperand(0).getResNo() == 1 &&
16117 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
16118 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
16119 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
16120 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
16121 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
16122 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
16123 Inverted = true;
16124 Cond = Cond.getOperand(0);
16125 } else {
16126 SDValue NewCond = LowerSETCC(Cond, DAG);
16127 if (NewCond.getNode())
16128 Cond = NewCond;
16129 }
16130 }
16131 #if 0
16132 // FIXME: LowerXALUO doesn't handle these!!
16133 else if (Cond.getOpcode() == X86ISD::ADD ||
16134 Cond.getOpcode() == X86ISD::SUB ||
16135 Cond.getOpcode() == X86ISD::SMUL ||
16136 Cond.getOpcode() == X86ISD::UMUL)
16137 Cond = LowerXALUO(Cond, DAG);
16138 #endif
16140 // Look pass (and (setcc_carry (cmp ...)), 1).
16141 if (Cond.getOpcode() == ISD::AND &&
16142 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
16143 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
16144 if (C && C->getAPIntValue() == 1)
16145 Cond = Cond.getOperand(0);
16146 }
16148 // If condition flag is set by a X86ISD::CMP, then use it as the condition
16149 // setting operand in place of the X86ISD::SETCC.
16150 unsigned CondOpcode = Cond.getOpcode();
16151 if (CondOpcode == X86ISD::SETCC ||
16152 CondOpcode == X86ISD::SETCC_CARRY) {
16153 CC = Cond.getOperand(0);
16155 SDValue Cmp = Cond.getOperand(1);
16156 unsigned Opc = Cmp.getOpcode();
16157 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
16158 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
16159 Cond = Cmp;
16160 addTest = false;
16161 } else {
16162 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
16163 default: break;
16164 case X86::COND_O:
16165 case X86::COND_B:
16166 // These can only come from an arithmetic instruction with overflow,
16167 // e.g. SADDO, UADDO.
16168 Cond = Cond.getNode()->getOperand(1);
16169 addTest = false;
16170 break;
16171 }
16172 }
16173 }
16174 CondOpcode = Cond.getOpcode();
16175 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
16176 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
16177 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
16178 Cond.getOperand(0).getValueType() != MVT::i8)) {
16179 SDValue LHS = Cond.getOperand(0);
16180 SDValue RHS = Cond.getOperand(1);
16181 unsigned X86Opcode;
16182 unsigned X86Cond;
16183 SDVTList VTs;
16184 // Keep this in sync with LowerXALUO, otherwise we might create redundant
16185 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
16186 // X86ISD::INC).
16187 switch (CondOpcode) {
16188 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
16189 case ISD::SADDO:
16190 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16191 if (C->isOne()) {
16192 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
16193 break;
16194 }
16195 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
16196 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
16197 case ISD::SSUBO:
16198 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16199 if (C->isOne()) {
16200 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
16201 break;
16202 }
16203 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
16204 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
16205 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
16206 default: llvm_unreachable("unexpected overflowing operator");
16207 }
16208 if (Inverted)
16209 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
16210 if (CondOpcode == ISD::UMULO)
16211 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
16212 MVT::i32);
16213 else
16214 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
16216 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
16218 if (CondOpcode == ISD::UMULO)
16219 Cond = X86Op.getValue(2);
16220 else
16221 Cond = X86Op.getValue(1);
16223 CC = DAG.getConstant(X86Cond, MVT::i8);
16224 addTest = false;
16225 } else {
16226 unsigned CondOpc;
16227 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
16228 SDValue Cmp = Cond.getOperand(0).getOperand(1);
16229 if (CondOpc == ISD::OR) {
16230 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
16231 // two branches instead of an explicit OR instruction with a
16232 // separate test.
16233 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16234 isX86LogicalCmp(Cmp)) {
16235 CC = Cond.getOperand(0).getOperand(0);
16236 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16237 Chain, Dest, CC, Cmp);
16238 CC = Cond.getOperand(1).getOperand(0);
16239 Cond = Cmp;
16240 addTest = false;
16241 }
16242 } else { // ISD::AND
16243 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
16244 // two branches instead of an explicit AND instruction with a
16245 // separate test. However, we only do this if this block doesn't
16246 // have a fall-through edge, because this requires an explicit
16247 // jmp when the condition is false.
16248 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16249 isX86LogicalCmp(Cmp) &&
16250 Op.getNode()->hasOneUse()) {
16251 X86::CondCode CCode =
16252 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16253 CCode = X86::GetOppositeBranchCondition(CCode);
16254 CC = DAG.getConstant(CCode, MVT::i8);
16255 SDNode *User = *Op.getNode()->use_begin();
16256 // Look for an unconditional branch following this conditional branch.
16257 // We need this because we need to reverse the successors in order
16258 // to implement FCMP_OEQ.
16259 if (User->getOpcode() == ISD::BR) {
16260 SDValue FalseBB = User->getOperand(1);
16261 SDNode *NewBR =
16262 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16263 assert(NewBR == User);
16264 (void)NewBR;
16265 Dest = FalseBB;
16267 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16268 Chain, Dest, CC, Cmp);
16269 X86::CondCode CCode =
16270 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
16271 CCode = X86::GetOppositeBranchCondition(CCode);
16272 CC = DAG.getConstant(CCode, MVT::i8);
16273 Cond = Cmp;
16274 addTest = false;
16275 }
16276 }
16277 }
16278 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
16279 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
16280 // It should be transformed during dag combiner except when the condition
16281 // is set by a arithmetics with overflow node.
16282 X86::CondCode CCode =
16283 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16284 CCode = X86::GetOppositeBranchCondition(CCode);
16285 CC = DAG.getConstant(CCode, MVT::i8);
16286 Cond = Cond.getOperand(0).getOperand(1);
16287 addTest = false;
16288 } else if (Cond.getOpcode() == ISD::SETCC &&
16289 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
16290 // For FCMP_OEQ, we can emit
16291 // two branches instead of an explicit AND instruction with a
16292 // separate test. However, we only do this if this block doesn't
16293 // have a fall-through edge, because this requires an explicit
16294 // jmp when the condition is false.
16295 if (Op.getNode()->hasOneUse()) {
16296 SDNode *User = *Op.getNode()->use_begin();
16297 // Look for an unconditional branch following this conditional branch.
16298 // We need this because we need to reverse the successors in order
16299 // to implement FCMP_OEQ.
16300 if (User->getOpcode() == ISD::BR) {
16301 SDValue FalseBB = User->getOperand(1);
16302 SDNode *NewBR =
16303 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16304 assert(NewBR == User);
16305 (void)NewBR;
16306 Dest = FalseBB;
16308 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16309 Cond.getOperand(0), Cond.getOperand(1));
16310 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16311 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16312 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16313 Chain, Dest, CC, Cmp);
16314 CC = DAG.getConstant(X86::COND_P, MVT::i8);
16315 Cond = Cmp;
16316 addTest = false;
16317 }
16318 }
16319 } else if (Cond.getOpcode() == ISD::SETCC &&
16320 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
16321 // For FCMP_UNE, we can emit
16322 // two branches instead of an explicit AND instruction with a
16323 // separate test. However, we only do this if this block doesn't
16324 // have a fall-through edge, because this requires an explicit
16325 // jmp when the condition is false.
16326 if (Op.getNode()->hasOneUse()) {
16327 SDNode *User = *Op.getNode()->use_begin();
16328 // Look for an unconditional branch following this conditional branch.
16329 // We need this because we need to reverse the successors in order
16330 // to implement FCMP_UNE.
16331 if (User->getOpcode() == ISD::BR) {
16332 SDValue FalseBB = User->getOperand(1);
16333 SDNode *NewBR =
16334 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16335 assert(NewBR == User);
16336 (void)NewBR;
16338 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16339 Cond.getOperand(0), Cond.getOperand(1));
16340 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16341 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16342 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16343 Chain, Dest, CC, Cmp);
16344 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
16345 Cond = Cmp;
16346 addTest = false;
16347 Dest = FalseBB;
16348 }
16349 }
16350 }
16351 }
16353 if (addTest) {
16354 // Look pass the truncate if the high bits are known zero.
16355 if (isTruncWithZeroHighBitsInput(Cond, DAG))
16356 Cond = Cond.getOperand(0);
16358 // We know the result of AND is compared against zero. Try to match
16359 // it to BT.
16360 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
16361 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
16362 if (NewSetCC.getNode()) {
16363 CC = NewSetCC.getOperand(0);
16364 Cond = NewSetCC.getOperand(1);
16365 addTest = false;
16366 }
16367 }
16368 }
16370 if (addTest) {
16371 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
16372 CC = DAG.getConstant(X86Cond, MVT::i8);
16373 Cond = EmitTest(Cond, X86Cond, dl, DAG);
16374 }
16375 Cond = ConvertCmpIfNecessary(Cond, DAG);
16376 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16377 Chain, Dest, CC, Cond);
16378 }
16380 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
16381 // Calls to _alloca are needed to probe the stack when allocating more than 4k
16382 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
16383 // that the guard pages used by the OS virtual memory manager are allocated in
16384 // correct sequence.
16385 SDValue
16386 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
16387 SelectionDAG &DAG) const {
16388 MachineFunction &MF = DAG.getMachineFunction();
16389 bool SplitStack = MF.shouldSplitStack();
16390 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
16391 SplitStack;
16392 SDLoc dl(Op);
16394 if (!Lower) {
16395 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16396 SDNode* Node = Op.getNode();
16398 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
16399 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
16400 " not tell us which reg is the stack pointer!");
16401 EVT VT = Node->getValueType(0);
16402 SDValue Tmp1 = SDValue(Node, 0);
16403 SDValue Tmp2 = SDValue(Node, 1);
16404 SDValue Tmp3 = Node->getOperand(2);
16405 SDValue Chain = Tmp1.getOperand(0);
16407 // Chain the dynamic stack allocation so that it doesn't modify the stack
16408 // pointer when other instructions are using the stack.
16409 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
16410 SDLoc(Node));
16412 SDValue Size = Tmp2.getOperand(1);
16413 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
16414 Chain = SP.getValue(1);
16415 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
16416 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
16417 unsigned StackAlign = TFI.getStackAlignment();
16418 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
16419 if (Align > StackAlign)
16420 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
16421 DAG.getConstant(-(uint64_t)Align, VT));
16422 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
16424 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
16425 DAG.getIntPtrConstant(0, true), SDValue(),
16426 SDLoc(Node));
16428 SDValue Ops[2] = { Tmp1, Tmp2 };
16429 return DAG.getMergeValues(Ops, dl);
16430 }
16432 // Get the inputs.
16433 SDValue Chain = Op.getOperand(0);
16434 SDValue Size = Op.getOperand(1);
16435 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
16436 EVT VT = Op.getNode()->getValueType(0);
16438 bool Is64Bit = Subtarget->is64Bit();
16439 EVT SPTy = getPointerTy();
16441 if (SplitStack) {
16442 MachineRegisterInfo &MRI = MF.getRegInfo();
16444 if (Is64Bit) {
16445 // The 64 bit implementation of segmented stacks needs to clobber both r10
16446 // r11. This makes it impossible to use it along with nested parameters.
16447 const Function *F = MF.getFunction();
16449 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
16450 I != E; ++I)
16451 if (I->hasNestAttr())
16452 report_fatal_error("Cannot use segmented stacks with functions that "
16453 "have nested arguments.");
16454 }
16456 const TargetRegisterClass *AddrRegClass =
16457 getRegClassFor(getPointerTy());
16458 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
16459 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
16460 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
16461 DAG.getRegister(Vreg, SPTy));
16462 SDValue Ops1[2] = { Value, Chain };
16463 return DAG.getMergeValues(Ops1, dl);
16464 } else {
16465 SDValue Flag;
16466 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
16468 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
16469 Flag = Chain.getValue(1);
16470 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
16472 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
16474 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16475 DAG.getSubtarget().getRegisterInfo());
16476 unsigned SPReg = RegInfo->getStackRegister();
16477 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
16478 Chain = SP.getValue(1);
16480 if (Align) {
16481 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
16482 DAG.getConstant(-(uint64_t)Align, VT));
16483 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
16484 }
16486 SDValue Ops1[2] = { SP, Chain };
16487 return DAG.getMergeValues(Ops1, dl);
16488 }
16489 }
16491 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
16492 MachineFunction &MF = DAG.getMachineFunction();
16493 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
16495 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16496 SDLoc DL(Op);
16498 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
16499 // vastart just stores the address of the VarArgsFrameIndex slot into the
16500 // memory location argument.
16501 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16502 getPointerTy());
16503 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
16504 MachinePointerInfo(SV), false, false, 0);
16505 }
16507 // __va_list_tag:
16508 // gp_offset (0 - 6 * 8)
16509 // fp_offset (48 - 48 + 8 * 16)
16510 // overflow_arg_area (point to parameters coming in memory).
16511 // reg_save_area
16512 SmallVector<SDValue, 8> MemOps;
16513 SDValue FIN = Op.getOperand(1);
16514 // Store gp_offset
16515 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
16516 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
16517 MVT::i32),
16518 FIN, MachinePointerInfo(SV), false, false, 0);
16519 MemOps.push_back(Store);
16521 // Store fp_offset
16522 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16523 FIN, DAG.getIntPtrConstant(4));
16524 Store = DAG.getStore(Op.getOperand(0), DL,
16525 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
16526 MVT::i32),
16527 FIN, MachinePointerInfo(SV, 4), false, false, 0);
16528 MemOps.push_back(Store);
16530 // Store ptr to overflow_arg_area
16531 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16532 FIN, DAG.getIntPtrConstant(4));
16533 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16534 getPointerTy());
16535 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
16536 MachinePointerInfo(SV, 8),
16537 false, false, 0);
16538 MemOps.push_back(Store);
16540 // Store ptr to reg_save_area.
16541 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16542 FIN, DAG.getIntPtrConstant(8));
16543 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
16544 getPointerTy());
16545 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
16546 MachinePointerInfo(SV, 16), false, false, 0);
16547 MemOps.push_back(Store);
16548 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
16549 }
16551 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
16552 assert(Subtarget->is64Bit() &&
16553 "LowerVAARG only handles 64-bit va_arg!");
16554 assert((Subtarget->isTargetLinux() ||
16555 Subtarget->isTargetDarwin()) &&
16556 "Unhandled target in LowerVAARG");
16557 assert(Op.getNode()->getNumOperands() == 4);
16558 SDValue Chain = Op.getOperand(0);
16559 SDValue SrcPtr = Op.getOperand(1);
16560 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16561 unsigned Align = Op.getConstantOperandVal(3);
16562 SDLoc dl(Op);
16564 EVT ArgVT = Op.getNode()->getValueType(0);
16565 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16566 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
16567 uint8_t ArgMode;
16569 // Decide which area this value should be read from.
16570 // TODO: Implement the AMD64 ABI in its entirety. This simple
16571 // selection mechanism works only for the basic types.
16572 if (ArgVT == MVT::f80) {
16573 llvm_unreachable("va_arg for f80 not yet implemented");
16574 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
16575 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
16576 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
16577 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
16578 } else {
16579 llvm_unreachable("Unhandled argument type in LowerVAARG");
16580 }
16582 if (ArgMode == 2) {
16583 // Sanity Check: Make sure using fp_offset makes sense.
16584 assert(!DAG.getTarget().Options.UseSoftFloat &&
16585 !(DAG.getMachineFunction()
16586 .getFunction()->getAttributes()
16587 .hasAttribute(AttributeSet::FunctionIndex,
16588 Attribute::NoImplicitFloat)) &&
16589 Subtarget->hasSSE1());
16590 }
16592 // Insert VAARG_64 node into the DAG
16593 // VAARG_64 returns two values: Variable Argument Address, Chain
16594 SmallVector<SDValue, 11> InstOps;
16595 InstOps.push_back(Chain);
16596 InstOps.push_back(SrcPtr);
16597 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
16598 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
16599 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
16600 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
16601 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
16602 VTs, InstOps, MVT::i64,
16603 MachinePointerInfo(SV),
16604 /*Align=*/0,
16605 /*Volatile=*/false,
16606 /*ReadMem=*/true,
16607 /*WriteMem=*/true);
16608 Chain = VAARG.getValue(1);
16610 // Load the next argument and return it
16611 return DAG.getLoad(ArgVT, dl,
16612 Chain,
16613 VAARG,
16614 MachinePointerInfo(),
16615 false, false, false, 0);
16616 }
16618 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
16619 SelectionDAG &DAG) {
16620 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
16621 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
16622 SDValue Chain = Op.getOperand(0);
16623 SDValue DstPtr = Op.getOperand(1);
16624 SDValue SrcPtr = Op.getOperand(2);
16625 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
16626 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16627 SDLoc DL(Op);
16629 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
16630 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
16631 false,
16632 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
16633 }
16635 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
16636 // amount is a constant. Takes immediate version of shift as input.
16637 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
16638 SDValue SrcOp, uint64_t ShiftAmt,
16639 SelectionDAG &DAG) {
16640 MVT ElementType = VT.getVectorElementType();
16642 // Fold this packed shift into its first operand if ShiftAmt is 0.
16643 if (ShiftAmt == 0)
16644 return SrcOp;
16646 // Check for ShiftAmt >= element width
16647 if (ShiftAmt >= ElementType.getSizeInBits()) {
16648 if (Opc == X86ISD::VSRAI)
16649 ShiftAmt = ElementType.getSizeInBits() - 1;
16650 else
16651 return DAG.getConstant(0, VT);
16652 }
16654 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
16655 && "Unknown target vector shift-by-constant node");
16657 // Fold this packed vector shift into a build vector if SrcOp is a
16658 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
16659 if (VT == SrcOp.getSimpleValueType() &&
16660 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
16661 SmallVector<SDValue, 8> Elts;
16662 unsigned NumElts = SrcOp->getNumOperands();
16663 ConstantSDNode *ND;
16665 switch(Opc) {
16666 default: llvm_unreachable(nullptr);
16667 case X86ISD::VSHLI:
16668 for (unsigned i=0; i!=NumElts; ++i) {
16669 SDValue CurrentOp = SrcOp->getOperand(i);
16670 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16671 Elts.push_back(CurrentOp);
16672 continue;
16673 }
16674 ND = cast<ConstantSDNode>(CurrentOp);
16675 const APInt &C = ND->getAPIntValue();
16676 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
16677 }
16678 break;
16679 case X86ISD::VSRLI:
16680 for (unsigned i=0; i!=NumElts; ++i) {
16681 SDValue CurrentOp = SrcOp->getOperand(i);
16682 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16683 Elts.push_back(CurrentOp);
16684 continue;
16685 }
16686 ND = cast<ConstantSDNode>(CurrentOp);
16687 const APInt &C = ND->getAPIntValue();
16688 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
16689 }
16690 break;
16691 case X86ISD::VSRAI:
16692 for (unsigned i=0; i!=NumElts; ++i) {
16693 SDValue CurrentOp = SrcOp->getOperand(i);
16694 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16695 Elts.push_back(CurrentOp);
16696 continue;
16697 }
16698 ND = cast<ConstantSDNode>(CurrentOp);
16699 const APInt &C = ND->getAPIntValue();
16700 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
16701 }
16702 break;
16703 }
16705 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16706 }
16708 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
16709 }
16711 // getTargetVShiftNode - Handle vector element shifts where the shift amount
16712 // may or may not be a constant. Takes immediate version of shift as input.
16713 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
16714 SDValue SrcOp, SDValue ShAmt,
16715 SelectionDAG &DAG) {
16716 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
16718 // Catch shift-by-constant.
16719 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
16720 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
16721 CShAmt->getZExtValue(), DAG);
16723 // Change opcode to non-immediate version
16724 switch (Opc) {
16725 default: llvm_unreachable("Unknown target vector shift node");
16726 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
16727 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
16728 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
16729 }
16731 // Need to build a vector containing shift amount
16732 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
16733 SDValue ShOps[4];
16734 ShOps[0] = ShAmt;
16735 ShOps[1] = DAG.getConstant(0, MVT::i32);
16736 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
16737 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
16739 // The return type has to be a 128-bit type with the same element
16740 // type as the input type.
16741 MVT EltVT = VT.getVectorElementType();
16742 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
16744 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
16745 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
16746 }
16748 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16749 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16750 /// necessary casting for \p Mask when lowering masking intrinsics.
16751 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16752 SDValue PreservedSrc,
16753 const X86Subtarget *Subtarget,
16754 SelectionDAG &DAG) {
16755 EVT VT = Op.getValueType();
16756 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16757 MVT::i1, VT.getVectorNumElements());
16758 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16759 Mask.getValueType().getSizeInBits());
16760 SDLoc dl(Op);
16762 assert(MaskVT.isSimple() && "invalid mask type");
16764 if (isAllOnes(Mask))
16765 return Op;
16767 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16768 // are extracted by EXTRACT_SUBVECTOR.
16769 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16770 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
16771 DAG.getIntPtrConstant(0));
16773 switch (Op.getOpcode()) {
16774 default: break;
16775 case X86ISD::PCMPEQM:
16776 case X86ISD::PCMPGTM:
16777 case X86ISD::CMPM:
16778 case X86ISD::CMPMU:
16779 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16780 }
16781 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16782 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16783 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
16784 }
16786 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
16787 SDValue PreservedSrc,
16788 const X86Subtarget *Subtarget,
16789 SelectionDAG &DAG) {
16790 if (isAllOnes(Mask))
16791 return Op;
16793 EVT VT = Op.getValueType();
16794 SDLoc dl(Op);
16795 // The mask should be of type MVT::i1
16796 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
16798 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16799 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16800 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
16801 }
16803 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
16804 switch (IntNo) {
16805 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16806 case Intrinsic::x86_fma_vfmadd_ps:
16807 case Intrinsic::x86_fma_vfmadd_pd:
16808 case Intrinsic::x86_fma_vfmadd_ps_256:
16809 case Intrinsic::x86_fma_vfmadd_pd_256:
16810 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16811 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16812 return X86ISD::FMADD;
16813 case Intrinsic::x86_fma_vfmsub_ps:
16814 case Intrinsic::x86_fma_vfmsub_pd:
16815 case Intrinsic::x86_fma_vfmsub_ps_256:
16816 case Intrinsic::x86_fma_vfmsub_pd_256:
16817 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16818 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16819 return X86ISD::FMSUB;
16820 case Intrinsic::x86_fma_vfnmadd_ps:
16821 case Intrinsic::x86_fma_vfnmadd_pd:
16822 case Intrinsic::x86_fma_vfnmadd_ps_256:
16823 case Intrinsic::x86_fma_vfnmadd_pd_256:
16824 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16825 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16826 return X86ISD::FNMADD;
16827 case Intrinsic::x86_fma_vfnmsub_ps:
16828 case Intrinsic::x86_fma_vfnmsub_pd:
16829 case Intrinsic::x86_fma_vfnmsub_ps_256:
16830 case Intrinsic::x86_fma_vfnmsub_pd_256:
16831 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16832 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16833 return X86ISD::FNMSUB;
16834 case Intrinsic::x86_fma_vfmaddsub_ps:
16835 case Intrinsic::x86_fma_vfmaddsub_pd:
16836 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16837 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16838 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16839 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16840 return X86ISD::FMADDSUB;
16841 case Intrinsic::x86_fma_vfmsubadd_ps:
16842 case Intrinsic::x86_fma_vfmsubadd_pd:
16843 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16844 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16845 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16846 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
16847 return X86ISD::FMSUBADD;
16848 }
16849 }
16851 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16852 SelectionDAG &DAG) {
16853 SDLoc dl(Op);
16854 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16855 EVT VT = Op.getValueType();
16856 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16857 if (IntrData) {
16858 switch(IntrData->Type) {
16859 case INTR_TYPE_1OP:
16860 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16861 case INTR_TYPE_2OP:
16862 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16863 Op.getOperand(2));
16864 case INTR_TYPE_3OP:
16865 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16866 Op.getOperand(2), Op.getOperand(3));
16867 case INTR_TYPE_1OP_MASK_RM: {
16868 SDValue Src = Op.getOperand(1);
16869 SDValue Src0 = Op.getOperand(2);
16870 SDValue Mask = Op.getOperand(3);
16871 SDValue RoundingMode = Op.getOperand(4);
16872 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16873 RoundingMode),
16874 Mask, Src0, Subtarget, DAG);
16875 }
16876 case INTR_TYPE_SCALAR_MASK_RM: {
16877 SDValue Src1 = Op.getOperand(1);
16878 SDValue Src2 = Op.getOperand(2);
16879 SDValue Src0 = Op.getOperand(3);
16880 SDValue Mask = Op.getOperand(4);
16881 SDValue RoundingMode = Op.getOperand(5);
16882 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
16883 RoundingMode),
16884 Mask, Src0, Subtarget, DAG);
16885 }
16886 case INTR_TYPE_2OP_MASK: {
16887 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Op.getOperand(1),
16888 Op.getOperand(2)),
16889 Op.getOperand(4), Op.getOperand(3), Subtarget, DAG);
16890 }
16891 case CMP_MASK:
16892 case CMP_MASK_CC: {
16893 // Comparison intrinsics with masks.
16894 // Example of transformation:
16895 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16896 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16897 // (i8 (bitcast
16898 // (v8i1 (insert_subvector undef,
16899 // (v2i1 (and (PCMPEQM %a, %b),
16900 // (extract_subvector
16901 // (v8i1 (bitcast %mask)), 0))), 0))))
16902 EVT VT = Op.getOperand(1).getValueType();
16903 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16904 VT.getVectorNumElements());
16905 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16906 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16907 Mask.getValueType().getSizeInBits());
16908 SDValue Cmp;
16909 if (IntrData->Type == CMP_MASK_CC) {
16910 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16911 Op.getOperand(2), Op.getOperand(3));
16912 } else {
16913 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16914 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16915 Op.getOperand(2));
16916 }
16917 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16918 DAG.getTargetConstant(0, MaskVT),
16919 Subtarget, DAG);
16920 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16921 DAG.getUNDEF(BitcastVT), CmpMask,
16922 DAG.getIntPtrConstant(0));
16923 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
16924 }
16925 case COMI: { // Comparison intrinsics
16926 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16927 SDValue LHS = Op.getOperand(1);
16928 SDValue RHS = Op.getOperand(2);
16929 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
16930 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16931 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16932 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16933 DAG.getConstant(X86CC, MVT::i8), Cond);
16934 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16935 }
16936 case VSHIFT:
16937 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16938 Op.getOperand(1), Op.getOperand(2), DAG);
16939 case VSHIFT_MASK:
16940 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16941 Op.getOperand(1), Op.getOperand(2), DAG),
16942 Op.getOperand(4), Op.getOperand(3), Subtarget, DAG);
16943 default:
16944 break;
16945 }
16946 }
16948 switch (IntNo) {
16949 default: return SDValue(); // Don't custom lower most intrinsics.
16951 // Arithmetic intrinsics.
16952 case Intrinsic::x86_sse2_pmulu_dq:
16953 case Intrinsic::x86_avx2_pmulu_dq:
16954 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
16955 Op.getOperand(1), Op.getOperand(2));
16957 case Intrinsic::x86_sse41_pmuldq:
16958 case Intrinsic::x86_avx2_pmul_dq:
16959 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
16960 Op.getOperand(1), Op.getOperand(2));
16962 case Intrinsic::x86_sse2_pmulhu_w:
16963 case Intrinsic::x86_avx2_pmulhu_w:
16964 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
16965 Op.getOperand(1), Op.getOperand(2));
16967 case Intrinsic::x86_sse2_pmulh_w:
16968 case Intrinsic::x86_avx2_pmulh_w:
16969 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
16970 Op.getOperand(1), Op.getOperand(2));
16972 // SSE/SSE2/AVX floating point max/min intrinsics.
16973 case Intrinsic::x86_sse_max_ps:
16974 case Intrinsic::x86_sse2_max_pd:
16975 case Intrinsic::x86_avx_max_ps_256:
16976 case Intrinsic::x86_avx_max_pd_256:
16977 case Intrinsic::x86_sse_min_ps:
16978 case Intrinsic::x86_sse2_min_pd:
16979 case Intrinsic::x86_avx_min_ps_256:
16980 case Intrinsic::x86_avx_min_pd_256: {
16981 unsigned Opcode;
16982 switch (IntNo) {
16983 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16984 case Intrinsic::x86_sse_max_ps:
16985 case Intrinsic::x86_sse2_max_pd:
16986 case Intrinsic::x86_avx_max_ps_256:
16987 case Intrinsic::x86_avx_max_pd_256:
16988 Opcode = X86ISD::FMAX;
16989 break;
16990 case Intrinsic::x86_sse_min_ps:
16991 case Intrinsic::x86_sse2_min_pd:
16992 case Intrinsic::x86_avx_min_ps_256:
16993 case Intrinsic::x86_avx_min_pd_256:
16994 Opcode = X86ISD::FMIN;
16995 break;
16996 }
16997 return DAG.getNode(Opcode, dl, Op.getValueType(),
16998 Op.getOperand(1), Op.getOperand(2));
16999 }
17001 // AVX2 variable shift intrinsics
17002 case Intrinsic::x86_avx2_psllv_d:
17003 case Intrinsic::x86_avx2_psllv_q:
17004 case Intrinsic::x86_avx2_psllv_d_256:
17005 case Intrinsic::x86_avx2_psllv_q_256:
17006 case Intrinsic::x86_avx2_psrlv_d:
17007 case Intrinsic::x86_avx2_psrlv_q:
17008 case Intrinsic::x86_avx2_psrlv_d_256:
17009 case Intrinsic::x86_avx2_psrlv_q_256:
17010 case Intrinsic::x86_avx2_psrav_d:
17011 case Intrinsic::x86_avx2_psrav_d_256: {
17012 unsigned Opcode;
17013 switch (IntNo) {
17014 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
17015 case Intrinsic::x86_avx2_psllv_d:
17016 case Intrinsic::x86_avx2_psllv_q:
17017 case Intrinsic::x86_avx2_psllv_d_256:
17018 case Intrinsic::x86_avx2_psllv_q_256:
17019 Opcode = ISD::SHL;
17020 break;
17021 case Intrinsic::x86_avx2_psrlv_d:
17022 case Intrinsic::x86_avx2_psrlv_q:
17023 case Intrinsic::x86_avx2_psrlv_d_256:
17024 case Intrinsic::x86_avx2_psrlv_q_256:
17025 Opcode = ISD::SRL;
17026 break;
17027 case Intrinsic::x86_avx2_psrav_d:
17028 case Intrinsic::x86_avx2_psrav_d_256:
17029 Opcode = ISD::SRA;
17030 break;
17031 }
17032 return DAG.getNode(Opcode, dl, Op.getValueType(),
17033 Op.getOperand(1), Op.getOperand(2));
17034 }
17036 case Intrinsic::x86_sse2_packssdw_128:
17037 case Intrinsic::x86_sse2_packsswb_128:
17038 case Intrinsic::x86_avx2_packssdw:
17039 case Intrinsic::x86_avx2_packsswb:
17040 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
17041 Op.getOperand(1), Op.getOperand(2));
17043 case Intrinsic::x86_sse2_packuswb_128:
17044 case Intrinsic::x86_sse41_packusdw:
17045 case Intrinsic::x86_avx2_packuswb:
17046 case Intrinsic::x86_avx2_packusdw:
17047 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
17048 Op.getOperand(1), Op.getOperand(2));
17050 case Intrinsic::x86_ssse3_pshuf_b_128:
17051 case Intrinsic::x86_avx2_pshuf_b:
17052 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
17053 Op.getOperand(1), Op.getOperand(2));
17055 case Intrinsic::x86_sse2_pshuf_d:
17056 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
17057 Op.getOperand(1), Op.getOperand(2));
17059 case Intrinsic::x86_sse2_pshufl_w:
17060 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
17061 Op.getOperand(1), Op.getOperand(2));
17063 case Intrinsic::x86_sse2_pshufh_w:
17064 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
17065 Op.getOperand(1), Op.getOperand(2));
17067 case Intrinsic::x86_ssse3_psign_b_128:
17068 case Intrinsic::x86_ssse3_psign_w_128:
17069 case Intrinsic::x86_ssse3_psign_d_128:
17070 case Intrinsic::x86_avx2_psign_b:
17071 case Intrinsic::x86_avx2_psign_w:
17072 case Intrinsic::x86_avx2_psign_d:
17073 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
17074 Op.getOperand(1), Op.getOperand(2));
17076 case Intrinsic::x86_avx2_permd:
17077 case Intrinsic::x86_avx2_permps:
17078 // Operands intentionally swapped. Mask is last operand to intrinsic,
17079 // but second operand for node/instruction.
17080 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
17081 Op.getOperand(2), Op.getOperand(1));
17083 case Intrinsic::x86_avx512_mask_valign_q_512:
17084 case Intrinsic::x86_avx512_mask_valign_d_512:
17085 // Vector source operands are swapped.
17086 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
17087 Op.getValueType(), Op.getOperand(2),
17088 Op.getOperand(1),
17089 Op.getOperand(3)),
17090 Op.getOperand(5), Op.getOperand(4),
17091 Subtarget, DAG);
17093 // ptest and testp intrinsics. The intrinsic these come from are designed to
17094 // return an integer value, not just an instruction so lower it to the ptest
17095 // or testp pattern and a setcc for the result.
17096 case Intrinsic::x86_sse41_ptestz:
17097 case Intrinsic::x86_sse41_ptestc:
17098 case Intrinsic::x86_sse41_ptestnzc:
17099 case Intrinsic::x86_avx_ptestz_256:
17100 case Intrinsic::x86_avx_ptestc_256:
17101 case Intrinsic::x86_avx_ptestnzc_256:
17102 case Intrinsic::x86_avx_vtestz_ps:
17103 case Intrinsic::x86_avx_vtestc_ps:
17104 case Intrinsic::x86_avx_vtestnzc_ps:
17105 case Intrinsic::x86_avx_vtestz_pd:
17106 case Intrinsic::x86_avx_vtestc_pd:
17107 case Intrinsic::x86_avx_vtestnzc_pd:
17108 case Intrinsic::x86_avx_vtestz_ps_256:
17109 case Intrinsic::x86_avx_vtestc_ps_256:
17110 case Intrinsic::x86_avx_vtestnzc_ps_256:
17111 case Intrinsic::x86_avx_vtestz_pd_256:
17112 case Intrinsic::x86_avx_vtestc_pd_256:
17113 case Intrinsic::x86_avx_vtestnzc_pd_256: {
17114 bool IsTestPacked = false;
17115 unsigned X86CC;
17116 switch (IntNo) {
17117 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
17118 case Intrinsic::x86_avx_vtestz_ps:
17119 case Intrinsic::x86_avx_vtestz_pd:
17120 case Intrinsic::x86_avx_vtestz_ps_256:
17121 case Intrinsic::x86_avx_vtestz_pd_256:
17122 IsTestPacked = true; // Fallthrough
17123 case Intrinsic::x86_sse41_ptestz:
17124 case Intrinsic::x86_avx_ptestz_256:
17125 // ZF = 1
17126 X86CC = X86::COND_E;
17127 break;
17128 case Intrinsic::x86_avx_vtestc_ps:
17129 case Intrinsic::x86_avx_vtestc_pd:
17130 case Intrinsic::x86_avx_vtestc_ps_256:
17131 case Intrinsic::x86_avx_vtestc_pd_256:
17132 IsTestPacked = true; // Fallthrough
17133 case Intrinsic::x86_sse41_ptestc:
17134 case Intrinsic::x86_avx_ptestc_256:
17135 // CF = 1
17136 X86CC = X86::COND_B;
17137 break;
17138 case Intrinsic::x86_avx_vtestnzc_ps:
17139 case Intrinsic::x86_avx_vtestnzc_pd:
17140 case Intrinsic::x86_avx_vtestnzc_ps_256:
17141 case Intrinsic::x86_avx_vtestnzc_pd_256:
17142 IsTestPacked = true; // Fallthrough
17143 case Intrinsic::x86_sse41_ptestnzc:
17144 case Intrinsic::x86_avx_ptestnzc_256:
17145 // ZF and CF = 0
17146 X86CC = X86::COND_A;
17147 break;
17148 }
17150 SDValue LHS = Op.getOperand(1);
17151 SDValue RHS = Op.getOperand(2);
17152 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
17153 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
17154 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
17155 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
17156 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17157 }
17158 case Intrinsic::x86_avx512_kortestz_w:
17159 case Intrinsic::x86_avx512_kortestc_w: {
17160 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
17161 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
17162 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
17163 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
17164 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
17165 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
17166 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17167 }
17169 case Intrinsic::x86_sse42_pcmpistria128:
17170 case Intrinsic::x86_sse42_pcmpestria128:
17171 case Intrinsic::x86_sse42_pcmpistric128:
17172 case Intrinsic::x86_sse42_pcmpestric128:
17173 case Intrinsic::x86_sse42_pcmpistrio128:
17174 case Intrinsic::x86_sse42_pcmpestrio128:
17175 case Intrinsic::x86_sse42_pcmpistris128:
17176 case Intrinsic::x86_sse42_pcmpestris128:
17177 case Intrinsic::x86_sse42_pcmpistriz128:
17178 case Intrinsic::x86_sse42_pcmpestriz128: {
17179 unsigned Opcode;
17180 unsigned X86CC;
17181 switch (IntNo) {
17182 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
17183 case Intrinsic::x86_sse42_pcmpistria128:
17184 Opcode = X86ISD::PCMPISTRI;
17185 X86CC = X86::COND_A;
17186 break;
17187 case Intrinsic::x86_sse42_pcmpestria128:
17188 Opcode = X86ISD::PCMPESTRI;
17189 X86CC = X86::COND_A;
17190 break;
17191 case Intrinsic::x86_sse42_pcmpistric128:
17192 Opcode = X86ISD::PCMPISTRI;
17193 X86CC = X86::COND_B;
17194 break;
17195 case Intrinsic::x86_sse42_pcmpestric128:
17196 Opcode = X86ISD::PCMPESTRI;
17197 X86CC = X86::COND_B;
17198 break;
17199 case Intrinsic::x86_sse42_pcmpistrio128:
17200 Opcode = X86ISD::PCMPISTRI;
17201 X86CC = X86::COND_O;
17202 break;
17203 case Intrinsic::x86_sse42_pcmpestrio128:
17204 Opcode = X86ISD::PCMPESTRI;
17205 X86CC = X86::COND_O;
17206 break;
17207 case Intrinsic::x86_sse42_pcmpistris128:
17208 Opcode = X86ISD::PCMPISTRI;
17209 X86CC = X86::COND_S;
17210 break;
17211 case Intrinsic::x86_sse42_pcmpestris128:
17212 Opcode = X86ISD::PCMPESTRI;
17213 X86CC = X86::COND_S;
17214 break;
17215 case Intrinsic::x86_sse42_pcmpistriz128:
17216 Opcode = X86ISD::PCMPISTRI;
17217 X86CC = X86::COND_E;
17218 break;
17219 case Intrinsic::x86_sse42_pcmpestriz128:
17220 Opcode = X86ISD::PCMPESTRI;
17221 X86CC = X86::COND_E;
17222 break;
17223 }
17224 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17225 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17226 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
17227 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17228 DAG.getConstant(X86CC, MVT::i8),
17229 SDValue(PCMP.getNode(), 1));
17230 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17231 }
17233 case Intrinsic::x86_sse42_pcmpistri128:
17234 case Intrinsic::x86_sse42_pcmpestri128: {
17235 unsigned Opcode;
17236 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
17237 Opcode = X86ISD::PCMPISTRI;
17238 else
17239 Opcode = X86ISD::PCMPESTRI;
17241 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17242 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17243 return DAG.getNode(Opcode, dl, VTs, NewOps);
17244 }
17246 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
17247 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
17248 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
17249 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
17250 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
17251 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
17252 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
17253 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
17254 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
17255 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
17256 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
17257 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
17258 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
17259 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
17260 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
17261 dl, Op.getValueType(),
17262 Op.getOperand(1),
17263 Op.getOperand(2),
17264 Op.getOperand(3)),
17265 Op.getOperand(4), Op.getOperand(1),
17266 Subtarget, DAG);
17267 else
17268 return SDValue();
17269 }
17271 case Intrinsic::x86_fma_vfmadd_ps:
17272 case Intrinsic::x86_fma_vfmadd_pd:
17273 case Intrinsic::x86_fma_vfmsub_ps:
17274 case Intrinsic::x86_fma_vfmsub_pd:
17275 case Intrinsic::x86_fma_vfnmadd_ps:
17276 case Intrinsic::x86_fma_vfnmadd_pd:
17277 case Intrinsic::x86_fma_vfnmsub_ps:
17278 case Intrinsic::x86_fma_vfnmsub_pd:
17279 case Intrinsic::x86_fma_vfmaddsub_ps:
17280 case Intrinsic::x86_fma_vfmaddsub_pd:
17281 case Intrinsic::x86_fma_vfmsubadd_ps:
17282 case Intrinsic::x86_fma_vfmsubadd_pd:
17283 case Intrinsic::x86_fma_vfmadd_ps_256:
17284 case Intrinsic::x86_fma_vfmadd_pd_256:
17285 case Intrinsic::x86_fma_vfmsub_ps_256:
17286 case Intrinsic::x86_fma_vfmsub_pd_256:
17287 case Intrinsic::x86_fma_vfnmadd_ps_256:
17288 case Intrinsic::x86_fma_vfnmadd_pd_256:
17289 case Intrinsic::x86_fma_vfnmsub_ps_256:
17290 case Intrinsic::x86_fma_vfnmsub_pd_256:
17291 case Intrinsic::x86_fma_vfmaddsub_ps_256:
17292 case Intrinsic::x86_fma_vfmaddsub_pd_256:
17293 case Intrinsic::x86_fma_vfmsubadd_ps_256:
17294 case Intrinsic::x86_fma_vfmsubadd_pd_256:
17295 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
17296 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
17297 }
17298 }
17300 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17301 SDValue Src, SDValue Mask, SDValue Base,
17302 SDValue Index, SDValue ScaleOp, SDValue Chain,
17303 const X86Subtarget * Subtarget) {
17304 SDLoc dl(Op);
17305 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17306 assert(C && "Invalid scale type");
17307 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17308 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17309 Index.getSimpleValueType().getVectorNumElements());
17310 SDValue MaskInReg;
17311 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17312 if (MaskC)
17313 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17314 else
17315 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17316 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
17317 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17318 SDValue Segment = DAG.getRegister(0, MVT::i32);
17319 if (Src.getOpcode() == ISD::UNDEF)
17320 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
17321 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17322 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17323 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
17324 return DAG.getMergeValues(RetOps, dl);
17325 }
17327 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17328 SDValue Src, SDValue Mask, SDValue Base,
17329 SDValue Index, SDValue ScaleOp, SDValue Chain) {
17330 SDLoc dl(Op);
17331 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17332 assert(C && "Invalid scale type");
17333 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17334 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17335 SDValue Segment = DAG.getRegister(0, MVT::i32);
17336 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17337 Index.getSimpleValueType().getVectorNumElements());
17338 SDValue MaskInReg;
17339 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17340 if (MaskC)
17341 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17342 else
17343 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17344 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
17345 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
17346 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17347 return SDValue(Res, 1);
17348 }
17350 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17351 SDValue Mask, SDValue Base, SDValue Index,
17352 SDValue ScaleOp, SDValue Chain) {
17353 SDLoc dl(Op);
17354 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17355 assert(C && "Invalid scale type");
17356 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17357 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17358 SDValue Segment = DAG.getRegister(0, MVT::i32);
17359 EVT MaskVT =
17360 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
17361 SDValue MaskInReg;
17362 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17363 if (MaskC)
17364 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17365 else
17366 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17367 //SDVTList VTs = DAG.getVTList(MVT::Other);
17368 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17369 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
17370 return SDValue(Res, 0);
17371 }
17373 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
17374 // read performance monitor counters (x86_rdpmc).
17375 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
17376 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17377 SmallVectorImpl<SDValue> &Results) {
17378 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17379 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17380 SDValue LO, HI;
17382 // The ECX register is used to select the index of the performance counter
17383 // to read.
17384 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
17385 N->getOperand(2));
17386 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
17388 // Reads the content of a 64-bit performance counter and returns it in the
17389 // registers EDX:EAX.
17390 if (Subtarget->is64Bit()) {
17391 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17392 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17393 LO.getValue(2));
17394 } else {
17395 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17396 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17397 LO.getValue(2));
17398 }
17399 Chain = HI.getValue(1);
17401 if (Subtarget->is64Bit()) {
17402 // The EAX register is loaded with the low-order 32 bits. The EDX register
17403 // is loaded with the supported high-order bits of the counter.
17404 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17405 DAG.getConstant(32, MVT::i8));
17406 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17407 Results.push_back(Chain);
17408 return;
17409 }
17411 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17412 SDValue Ops[] = { LO, HI };
17413 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17414 Results.push_back(Pair);
17415 Results.push_back(Chain);
17416 }
17418 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
17419 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
17420 // also used to custom lower READCYCLECOUNTER nodes.
17421 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
17422 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17423 SmallVectorImpl<SDValue> &Results) {
17424 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17425 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
17426 SDValue LO, HI;
17428 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
17429 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
17430 // and the EAX register is loaded with the low-order 32 bits.
17431 if (Subtarget->is64Bit()) {
17432 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17433 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17434 LO.getValue(2));
17435 } else {
17436 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17437 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17438 LO.getValue(2));
17439 }
17440 SDValue Chain = HI.getValue(1);
17442 if (Opcode == X86ISD::RDTSCP_DAG) {
17443 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17445 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
17446 // the ECX register. Add 'ecx' explicitly to the chain.
17447 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
17448 HI.getValue(2));
17449 // Explicitly store the content of ECX at the location passed in input
17450 // to the 'rdtscp' intrinsic.
17451 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
17452 MachinePointerInfo(), false, false, 0);
17453 }
17455 if (Subtarget->is64Bit()) {
17456 // The EDX register is loaded with the high-order 32 bits of the MSR, and
17457 // the EAX register is loaded with the low-order 32 bits.
17458 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17459 DAG.getConstant(32, MVT::i8));
17460 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17461 Results.push_back(Chain);
17462 return;
17463 }
17465 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17466 SDValue Ops[] = { LO, HI };
17467 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17468 Results.push_back(Pair);
17469 Results.push_back(Chain);
17470 }
17472 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
17473 SelectionDAG &DAG) {
17474 SmallVector<SDValue, 2> Results;
17475 SDLoc DL(Op);
17476 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
17477 Results);
17478 return DAG.getMergeValues(Results, DL);
17479 }
17482 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17483 SelectionDAG &DAG) {
17484 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
17486 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
17487 if (!IntrData)
17488 return SDValue();
17490 SDLoc dl(Op);
17491 switch(IntrData->Type) {
17492 default:
17493 llvm_unreachable("Unknown Intrinsic Type");
17494 break;
17495 case RDSEED:
17496 case RDRAND: {
17497 // Emit the node with the right value type.
17498 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
17499 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17501 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17502 // Otherwise return the value from Rand, which is always 0, casted to i32.
17503 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17504 DAG.getConstant(1, Op->getValueType(1)),
17505 DAG.getConstant(X86::COND_B, MVT::i32),
17506 SDValue(Result.getNode(), 1) };
17507 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17508 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17509 Ops);
17511 // Return { result, isValid, chain }.
17512 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17513 SDValue(Result.getNode(), 2));
17514 }
17515 case GATHER: {
17516 //gather(v1, mask, index, base, scale);
17517 SDValue Chain = Op.getOperand(0);
17518 SDValue Src = Op.getOperand(2);
17519 SDValue Base = Op.getOperand(3);
17520 SDValue Index = Op.getOperand(4);
17521 SDValue Mask = Op.getOperand(5);
17522 SDValue Scale = Op.getOperand(6);
17523 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
17524 Subtarget);
17525 }
17526 case SCATTER: {
17527 //scatter(base, mask, index, v1, scale);
17528 SDValue Chain = Op.getOperand(0);
17529 SDValue Base = Op.getOperand(2);
17530 SDValue Mask = Op.getOperand(3);
17531 SDValue Index = Op.getOperand(4);
17532 SDValue Src = Op.getOperand(5);
17533 SDValue Scale = Op.getOperand(6);
17534 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
17535 }
17536 case PREFETCH: {
17537 SDValue Hint = Op.getOperand(6);
17538 unsigned HintVal;
17539 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
17540 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
17541 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
17542 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17543 SDValue Chain = Op.getOperand(0);
17544 SDValue Mask = Op.getOperand(2);
17545 SDValue Index = Op.getOperand(3);
17546 SDValue Base = Op.getOperand(4);
17547 SDValue Scale = Op.getOperand(5);
17548 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17549 }
17550 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17551 case RDTSC: {
17552 SmallVector<SDValue, 2> Results;
17553 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
17554 return DAG.getMergeValues(Results, dl);
17555 }
17556 // Read Performance Monitoring Counters.
17557 case RDPMC: {
17558 SmallVector<SDValue, 2> Results;
17559 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17560 return DAG.getMergeValues(Results, dl);
17561 }
17562 // XTEST intrinsics.
17563 case XTEST: {
17564 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17565 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17566 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17567 DAG.getConstant(X86::COND_NE, MVT::i8),
17568 InTrans);
17569 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17570 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17571 Ret, SDValue(InTrans.getNode(), 1));
17572 }
17573 // ADC/ADCX/SBB
17574 case ADX: {
17575 SmallVector<SDValue, 2> Results;
17576 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17577 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17578 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17579 DAG.getConstant(-1, MVT::i8));
17580 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17581 Op.getOperand(4), GenCF.getValue(1));
17582 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17583 Op.getOperand(5), MachinePointerInfo(),
17584 false, false, 0);
17585 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17586 DAG.getConstant(X86::COND_B, MVT::i8),
17587 Res.getValue(1));
17588 Results.push_back(SetCC);
17589 Results.push_back(Store);
17590 return DAG.getMergeValues(Results, dl);
17591 }
17592 }
17593 }
17595 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17596 SelectionDAG &DAG) const {
17597 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17598 MFI->setReturnAddressIsTaken(true);
17600 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17601 return SDValue();
17603 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17604 SDLoc dl(Op);
17605 EVT PtrVT = getPointerTy();
17607 if (Depth > 0) {
17608 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17609 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17610 DAG.getSubtarget().getRegisterInfo());
17611 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
17612 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17613 DAG.getNode(ISD::ADD, dl, PtrVT,
17614 FrameAddr, Offset),
17615 MachinePointerInfo(), false, false, false, 0);
17616 }
17618 // Just load the return address.
17619 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17620 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17621 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17622 }
17624 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17625 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17626 MFI->setFrameAddressIsTaken(true);
17628 EVT VT = Op.getValueType();
17629 SDLoc dl(Op); // FIXME probably not meaningful
17630 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17631 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17632 DAG.getSubtarget().getRegisterInfo());
17633 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17634 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17635 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17636 "Invalid Frame Register!");
17637 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17638 while (Depth--)
17639 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17640 MachinePointerInfo(),
17641 false, false, false, 0);
17642 return FrameAddr;
17643 }
17645 // FIXME? Maybe this could be a TableGen attribute on some registers and
17646 // this table could be generated automatically from RegInfo.
17647 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
17648 EVT VT) const {
17649 unsigned Reg = StringSwitch<unsigned>(RegName)
17650 .Case("esp", X86::ESP)
17651 .Case("rsp", X86::RSP)
17652 .Default(0);
17653 if (Reg)
17654 return Reg;
17655 report_fatal_error("Invalid register name global variable");
17656 }
17658 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17659 SelectionDAG &DAG) const {
17660 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17661 DAG.getSubtarget().getRegisterInfo());
17662 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
17663 }
17665 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17666 SDValue Chain = Op.getOperand(0);
17667 SDValue Offset = Op.getOperand(1);
17668 SDValue Handler = Op.getOperand(2);
17669 SDLoc dl (Op);
17671 EVT PtrVT = getPointerTy();
17672 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17673 DAG.getSubtarget().getRegisterInfo());
17674 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17675 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17676 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17677 "Invalid Frame Register!");
17678 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17679 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17681 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17682 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
17683 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17684 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17685 false, false, 0);
17686 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17688 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17689 DAG.getRegister(StoreAddrReg, PtrVT));
17690 }
17692 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17693 SelectionDAG &DAG) const {
17694 SDLoc DL(Op);
17695 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17696 DAG.getVTList(MVT::i32, MVT::Other),
17697 Op.getOperand(0), Op.getOperand(1));
17698 }
17700 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17701 SelectionDAG &DAG) const {
17702 SDLoc DL(Op);
17703 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17704 Op.getOperand(0), Op.getOperand(1));
17705 }
17707 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17708 return Op.getOperand(0);
17709 }
17711 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17712 SelectionDAG &DAG) const {
17713 SDValue Root = Op.getOperand(0);
17714 SDValue Trmp = Op.getOperand(1); // trampoline
17715 SDValue FPtr = Op.getOperand(2); // nested function
17716 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17717 SDLoc dl (Op);
17719 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17720 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
17722 if (Subtarget->is64Bit()) {
17723 SDValue OutChains[6];
17725 // Large code-model.
17726 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17727 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17729 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17730 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17732 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17734 // Load the pointer to the nested function into R11.
17735 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17736 SDValue Addr = Trmp;
17737 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17738 Addr, MachinePointerInfo(TrmpAddr),
17739 false, false, 0);
17741 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17742 DAG.getConstant(2, MVT::i64));
17743 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17744 MachinePointerInfo(TrmpAddr, 2),
17745 false, false, 2);
17747 // Load the 'nest' parameter value into R10.
17748 // R10 is specified in X86CallingConv.td
17749 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17750 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17751 DAG.getConstant(10, MVT::i64));
17752 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17753 Addr, MachinePointerInfo(TrmpAddr, 10),
17754 false, false, 0);
17756 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17757 DAG.getConstant(12, MVT::i64));
17758 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17759 MachinePointerInfo(TrmpAddr, 12),
17760 false, false, 2);
17762 // Jump to the nested function.
17763 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17764 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17765 DAG.getConstant(20, MVT::i64));
17766 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17767 Addr, MachinePointerInfo(TrmpAddr, 20),
17768 false, false, 0);
17770 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17771 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17772 DAG.getConstant(22, MVT::i64));
17773 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
17774 MachinePointerInfo(TrmpAddr, 22),
17775 false, false, 0);
17777 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17778 } else {
17779 const Function *Func =
17780 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17781 CallingConv::ID CC = Func->getCallingConv();
17782 unsigned NestReg;
17784 switch (CC) {
17785 default:
17786 llvm_unreachable("Unsupported calling convention");
17787 case CallingConv::C:
17788 case CallingConv::X86_StdCall: {
17789 // Pass 'nest' parameter in ECX.
17790 // Must be kept in sync with X86CallingConv.td
17791 NestReg = X86::ECX;
17793 // Check that ECX wasn't needed by an 'inreg' parameter.
17794 FunctionType *FTy = Func->getFunctionType();
17795 const AttributeSet &Attrs = Func->getAttributes();
17797 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17798 unsigned InRegCount = 0;
17799 unsigned Idx = 1;
17801 for (FunctionType::param_iterator I = FTy->param_begin(),
17802 E = FTy->param_end(); I != E; ++I, ++Idx)
17803 if (Attrs.hasAttribute(Idx, Attribute::InReg))
17804 // FIXME: should only count parameters that are lowered to integers.
17805 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
17807 if (InRegCount > 2) {
17808 report_fatal_error("Nest register in use - reduce number of inreg"
17809 " parameters!");
17810 }
17811 }
17812 break;
17813 }
17814 case CallingConv::X86_FastCall:
17815 case CallingConv::X86_ThisCall:
17816 case CallingConv::Fast:
17817 // Pass 'nest' parameter in EAX.
17818 // Must be kept in sync with X86CallingConv.td
17819 NestReg = X86::EAX;
17820 break;
17821 }
17823 SDValue OutChains[4];
17824 SDValue Addr, Disp;
17826 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17827 DAG.getConstant(10, MVT::i32));
17828 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17830 // This is storing the opcode for MOV32ri.
17831 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17832 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17833 OutChains[0] = DAG.getStore(Root, dl,
17834 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
17835 Trmp, MachinePointerInfo(TrmpAddr),
17836 false, false, 0);
17838 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17839 DAG.getConstant(1, MVT::i32));
17840 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17841 MachinePointerInfo(TrmpAddr, 1),
17842 false, false, 1);
17844 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17845 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17846 DAG.getConstant(5, MVT::i32));
17847 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
17848 MachinePointerInfo(TrmpAddr, 5),
17849 false, false, 1);
17851 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17852 DAG.getConstant(6, MVT::i32));
17853 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17854 MachinePointerInfo(TrmpAddr, 6),
17855 false, false, 1);
17857 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17858 }
17859 }
17861 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17862 SelectionDAG &DAG) const {
17863 /*
17864 The rounding mode is in bits 11:10 of FPSR, and has the following
17865 settings:
17866 00 Round to nearest
17867 01 Round to -inf
17868 10 Round to +inf
17869 11 Round to 0
17871 FLT_ROUNDS, on the other hand, expects the following:
17872 -1 Undefined
17873 0 Round to 0
17874 1 Round to nearest
17875 2 Round to +inf
17876 3 Round to -inf
17878 To perform the conversion, we do:
17879 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17880 */
17882 MachineFunction &MF = DAG.getMachineFunction();
17883 const TargetMachine &TM = MF.getTarget();
17884 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
17885 unsigned StackAlignment = TFI.getStackAlignment();
17886 MVT VT = Op.getSimpleValueType();
17887 SDLoc DL(Op);
17889 // Save FP Control Word to stack slot
17890 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17891 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
17893 MachineMemOperand *MMO =
17894 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
17895 MachineMemOperand::MOStore, 2, 2);
17897 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17898 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17899 DAG.getVTList(MVT::Other),
17900 Ops, MVT::i16, MMO);
17902 // Load FP Control Word from stack slot
17903 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17904 MachinePointerInfo(), false, false, false, 0);
17906 // Transform as necessary
17907 SDValue CWD1 =
17908 DAG.getNode(ISD::SRL, DL, MVT::i16,
17909 DAG.getNode(ISD::AND, DL, MVT::i16,
17910 CWD, DAG.getConstant(0x800, MVT::i16)),
17911 DAG.getConstant(11, MVT::i8));
17912 SDValue CWD2 =
17913 DAG.getNode(ISD::SRL, DL, MVT::i16,
17914 DAG.getNode(ISD::AND, DL, MVT::i16,
17915 CWD, DAG.getConstant(0x400, MVT::i16)),
17916 DAG.getConstant(9, MVT::i8));
17918 SDValue RetVal =
17919 DAG.getNode(ISD::AND, DL, MVT::i16,
17920 DAG.getNode(ISD::ADD, DL, MVT::i16,
17921 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17922 DAG.getConstant(1, MVT::i16)),
17923 DAG.getConstant(3, MVT::i16));
17925 return DAG.getNode((VT.getSizeInBits() < 16 ?
17926 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17927 }
17929 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17930 MVT VT = Op.getSimpleValueType();
17931 EVT OpVT = VT;
17932 unsigned NumBits = VT.getSizeInBits();
17933 SDLoc dl(Op);
17935 Op = Op.getOperand(0);
17936 if (VT == MVT::i8) {
17937 // Zero extend to i32 since there is not an i8 bsr.
17938 OpVT = MVT::i32;
17939 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17940 }
17942 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17943 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17944 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17946 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17947 SDValue Ops[] = {
17948 Op,
17949 DAG.getConstant(NumBits+NumBits-1, OpVT),
17950 DAG.getConstant(X86::COND_E, MVT::i8),
17951 Op.getValue(1)
17952 };
17953 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17955 // Finally xor with NumBits-1.
17956 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17958 if (VT == MVT::i8)
17959 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17960 return Op;
17961 }
17963 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
17964 MVT VT = Op.getSimpleValueType();
17965 EVT OpVT = VT;
17966 unsigned NumBits = VT.getSizeInBits();
17967 SDLoc dl(Op);
17969 Op = Op.getOperand(0);
17970 if (VT == MVT::i8) {
17971 // Zero extend to i32 since there is not an i8 bsr.
17972 OpVT = MVT::i32;
17973 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17974 }
17976 // Issue a bsr (scan bits in reverse).
17977 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17978 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17980 // And xor with NumBits-1.
17981 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17983 if (VT == MVT::i8)
17984 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17985 return Op;
17986 }
17988 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17989 MVT VT = Op.getSimpleValueType();
17990 unsigned NumBits = VT.getSizeInBits();
17991 SDLoc dl(Op);
17992 Op = Op.getOperand(0);
17994 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17995 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17996 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
17998 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17999 SDValue Ops[] = {
18000 Op,
18001 DAG.getConstant(NumBits, VT),
18002 DAG.getConstant(X86::COND_E, MVT::i8),
18003 Op.getValue(1)
18004 };
18005 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
18006 }
18008 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
18009 // ones, and then concatenate the result back.
18010 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
18011 MVT VT = Op.getSimpleValueType();
18013 assert(VT.is256BitVector() && VT.isInteger() &&
18014 "Unsupported value type for operation");
18016 unsigned NumElems = VT.getVectorNumElements();
18017 SDLoc dl(Op);
18019 // Extract the LHS vectors
18020 SDValue LHS = Op.getOperand(0);
18021 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18022 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18024 // Extract the RHS vectors
18025 SDValue RHS = Op.getOperand(1);
18026 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
18027 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
18029 MVT EltVT = VT.getVectorElementType();
18030 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18032 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
18033 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
18034 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
18035 }
18037 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
18038 assert(Op.getSimpleValueType().is256BitVector() &&
18039 Op.getSimpleValueType().isInteger() &&
18040 "Only handle AVX 256-bit vector integer operation");
18041 return Lower256IntArith(Op, DAG);
18042 }
18044 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
18045 assert(Op.getSimpleValueType().is256BitVector() &&
18046 Op.getSimpleValueType().isInteger() &&
18047 "Only handle AVX 256-bit vector integer operation");
18048 return Lower256IntArith(Op, DAG);
18049 }
18051 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
18052 SelectionDAG &DAG) {
18053 SDLoc dl(Op);
18054 MVT VT = Op.getSimpleValueType();
18056 // Decompose 256-bit ops into smaller 128-bit ops.
18057 if (VT.is256BitVector() && !Subtarget->hasInt256())
18058 return Lower256IntArith(Op, DAG);
18060 SDValue A = Op.getOperand(0);
18061 SDValue B = Op.getOperand(1);
18063 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
18064 if (VT == MVT::v4i32) {
18065 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
18066 "Should not custom lower when pmuldq is available!");
18068 // Extract the odd parts.
18069 static const int UnpackMask[] = { 1, -1, 3, -1 };
18070 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
18071 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
18073 // Multiply the even parts.
18074 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
18075 // Now multiply odd parts.
18076 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
18078 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
18079 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
18081 // Merge the two vectors back together with a shuffle. This expands into 2
18082 // shuffles.
18083 static const int ShufMask[] = { 0, 4, 2, 6 };
18084 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
18085 }
18087 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
18088 "Only know how to lower V2I64/V4I64/V8I64 multiply");
18090 // Ahi = psrlqi(a, 32);
18091 // Bhi = psrlqi(b, 32);
18092 //
18093 // AloBlo = pmuludq(a, b);
18094 // AloBhi = pmuludq(a, Bhi);
18095 // AhiBlo = pmuludq(Ahi, b);
18097 // AloBhi = psllqi(AloBhi, 32);
18098 // AhiBlo = psllqi(AhiBlo, 32);
18099 // return AloBlo + AloBhi + AhiBlo;
18101 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
18102 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
18104 // Bit cast to 32-bit vectors for MULUDQ
18105 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
18106 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
18107 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
18108 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
18109 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
18110 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
18112 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
18113 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
18114 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
18116 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
18117 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
18119 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
18120 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
18121 }
18123 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
18124 assert(Subtarget->isTargetWin64() && "Unexpected target");
18125 EVT VT = Op.getValueType();
18126 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
18127 "Unexpected return type for lowering");
18129 RTLIB::Libcall LC;
18130 bool isSigned;
18131 switch (Op->getOpcode()) {
18132 default: llvm_unreachable("Unexpected request for libcall!");
18133 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
18134 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
18135 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
18136 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
18137 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
18138 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
18139 }
18141 SDLoc dl(Op);
18142 SDValue InChain = DAG.getEntryNode();
18144 TargetLowering::ArgListTy Args;
18145 TargetLowering::ArgListEntry Entry;
18146 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
18147 EVT ArgVT = Op->getOperand(i).getValueType();
18148 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
18149 "Unexpected argument type for lowering");
18150 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
18151 Entry.Node = StackPtr;
18152 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
18153 false, false, 16);
18154 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18155 Entry.Ty = PointerType::get(ArgTy,0);
18156 Entry.isSExt = false;
18157 Entry.isZExt = false;
18158 Args.push_back(Entry);
18159 }
18161 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
18162 getPointerTy());
18164 TargetLowering::CallLoweringInfo CLI(DAG);
18165 CLI.setDebugLoc(dl).setChain(InChain)
18166 .setCallee(getLibcallCallingConv(LC),
18167 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
18168 Callee, std::move(Args), 0)
18169 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
18171 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
18172 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
18173 }
18175 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
18176 SelectionDAG &DAG) {
18177 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
18178 EVT VT = Op0.getValueType();
18179 SDLoc dl(Op);
18181 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
18182 (VT == MVT::v8i32 && Subtarget->hasInt256()));
18184 // PMULxD operations multiply each even value (starting at 0) of LHS with
18185 // the related value of RHS and produce a widen result.
18186 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18187 // => <2 x i64> <ae|cg>
18188 //
18189 // In other word, to have all the results, we need to perform two PMULxD:
18190 // 1. one with the even values.
18191 // 2. one with the odd values.
18192 // To achieve #2, with need to place the odd values at an even position.
18193 //
18194 // Place the odd value at an even position (basically, shift all values 1
18195 // step to the left):
18196 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
18197 // <a|b|c|d> => <b|undef|d|undef>
18198 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
18199 // <e|f|g|h> => <f|undef|h|undef>
18200 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
18202 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
18203 // ints.
18204 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
18205 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
18206 unsigned Opcode =
18207 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
18208 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18209 // => <2 x i64> <ae|cg>
18210 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
18211 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
18212 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
18213 // => <2 x i64> <bf|dh>
18214 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
18215 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
18217 // Shuffle it back into the right order.
18218 SDValue Highs, Lows;
18219 if (VT == MVT::v8i32) {
18220 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
18221 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18222 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
18223 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18224 } else {
18225 const int HighMask[] = {1, 5, 3, 7};
18226 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18227 const int LowMask[] = {0, 4, 2, 6};
18228 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18229 }
18231 // If we have a signed multiply but no PMULDQ fix up the high parts of a
18232 // unsigned multiply.
18233 if (IsSigned && !Subtarget->hasSSE41()) {
18234 SDValue ShAmt =
18235 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
18236 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
18237 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
18238 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
18239 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
18241 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
18242 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
18243 }
18245 // The first result of MUL_LOHI is actually the low value, followed by the
18246 // high value.
18247 SDValue Ops[] = {Lows, Highs};
18248 return DAG.getMergeValues(Ops, dl);
18249 }
18251 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18252 const X86Subtarget *Subtarget) {
18253 MVT VT = Op.getSimpleValueType();
18254 SDLoc dl(Op);
18255 SDValue R = Op.getOperand(0);
18256 SDValue Amt = Op.getOperand(1);
18258 // Optimize shl/srl/sra with constant shift amount.
18259 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18260 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18261 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18263 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
18264 (Subtarget->hasInt256() &&
18265 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18266 (Subtarget->hasAVX512() &&
18267 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18268 if (Op.getOpcode() == ISD::SHL)
18269 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18270 DAG);
18271 if (Op.getOpcode() == ISD::SRL)
18272 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18273 DAG);
18274 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
18275 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18276 DAG);
18277 }
18279 if (VT == MVT::v16i8) {
18280 if (Op.getOpcode() == ISD::SHL) {
18281 // Make a large shift.
18282 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18283 MVT::v8i16, R, ShiftAmt,
18284 DAG);
18285 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18286 // Zero out the rightmost bits.
18287 SmallVector<SDValue, 16> V(16,
18288 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18289 MVT::i8));
18290 return DAG.getNode(ISD::AND, dl, VT, SHL,
18291 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18292 }
18293 if (Op.getOpcode() == ISD::SRL) {
18294 // Make a large shift.
18295 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18296 MVT::v8i16, R, ShiftAmt,
18297 DAG);
18298 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18299 // Zero out the leftmost bits.
18300 SmallVector<SDValue, 16> V(16,
18301 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18302 MVT::i8));
18303 return DAG.getNode(ISD::AND, dl, VT, SRL,
18304 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18305 }
18306 if (Op.getOpcode() == ISD::SRA) {
18307 if (ShiftAmt == 7) {
18308 // R s>> 7 === R s< 0
18309 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18310 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18311 }
18313 // R s>> a === ((R u>> a) ^ m) - m
18314 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18315 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
18316 MVT::i8));
18317 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18318 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18319 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18320 return Res;
18321 }
18322 llvm_unreachable("Unknown shift opcode.");
18323 }
18325 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
18326 if (Op.getOpcode() == ISD::SHL) {
18327 // Make a large shift.
18328 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18329 MVT::v16i16, R, ShiftAmt,
18330 DAG);
18331 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18332 // Zero out the rightmost bits.
18333 SmallVector<SDValue, 32> V(32,
18334 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18335 MVT::i8));
18336 return DAG.getNode(ISD::AND, dl, VT, SHL,
18337 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18338 }
18339 if (Op.getOpcode() == ISD::SRL) {
18340 // Make a large shift.
18341 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18342 MVT::v16i16, R, ShiftAmt,
18343 DAG);
18344 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18345 // Zero out the leftmost bits.
18346 SmallVector<SDValue, 32> V(32,
18347 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18348 MVT::i8));
18349 return DAG.getNode(ISD::AND, dl, VT, SRL,
18350 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18351 }
18352 if (Op.getOpcode() == ISD::SRA) {
18353 if (ShiftAmt == 7) {
18354 // R s>> 7 === R s< 0
18355 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18356 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18357 }
18359 // R s>> a === ((R u>> a) ^ m) - m
18360 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18361 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
18362 MVT::i8));
18363 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18364 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18365 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18366 return Res;
18367 }
18368 llvm_unreachable("Unknown shift opcode.");
18369 }
18370 }
18371 }
18373 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18374 if (!Subtarget->is64Bit() &&
18375 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18376 Amt.getOpcode() == ISD::BITCAST &&
18377 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18378 Amt = Amt.getOperand(0);
18379 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18380 VT.getVectorNumElements();
18381 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18382 uint64_t ShiftAmt = 0;
18383 for (unsigned i = 0; i != Ratio; ++i) {
18384 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
18385 if (!C)
18386 return SDValue();
18387 // 6 == Log2(64)
18388 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18389 }
18390 // Check remaining shift amounts.
18391 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18392 uint64_t ShAmt = 0;
18393 for (unsigned j = 0; j != Ratio; ++j) {
18394 ConstantSDNode *C =
18395 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18396 if (!C)
18397 return SDValue();
18398 // 6 == Log2(64)
18399 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18400 }
18401 if (ShAmt != ShiftAmt)
18402 return SDValue();
18403 }
18404 switch (Op.getOpcode()) {
18405 default:
18406 llvm_unreachable("Unknown shift opcode!");
18407 case ISD::SHL:
18408 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18409 DAG);
18410 case ISD::SRL:
18411 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18412 DAG);
18413 case ISD::SRA:
18414 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18415 DAG);
18416 }
18417 }
18419 return SDValue();
18420 }
18422 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18423 const X86Subtarget* Subtarget) {
18424 MVT VT = Op.getSimpleValueType();
18425 SDLoc dl(Op);
18426 SDValue R = Op.getOperand(0);
18427 SDValue Amt = Op.getOperand(1);
18429 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
18430 VT == MVT::v4i32 || VT == MVT::v8i16 ||
18431 (Subtarget->hasInt256() &&
18432 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
18433 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18434 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18435 SDValue BaseShAmt;
18436 EVT EltVT = VT.getVectorElementType();
18438 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
18439 // Check if this build_vector node is doing a splat.
18440 // If so, then set BaseShAmt equal to the splat value.
18441 BaseShAmt = BV->getSplatValue();
18442 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
18443 BaseShAmt = SDValue();
18444 } else {
18445 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18446 Amt = Amt.getOperand(0);
18447 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
18448 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
18449 SDValue InVec = Amt.getOperand(0);
18450 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18451 unsigned NumElts = InVec.getValueType().getVectorNumElements();
18452 unsigned i = 0;
18453 for (; i != NumElts; ++i) {
18454 SDValue Arg = InVec.getOperand(i);
18455 if (Arg.getOpcode() == ISD::UNDEF) continue;
18456 BaseShAmt = Arg;
18457 break;
18458 }
18459 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18460 if (ConstantSDNode *C =
18461 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18462 unsigned SplatIdx =
18463 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
18464 if (C->getZExtValue() == SplatIdx)
18465 BaseShAmt = InVec.getOperand(1);
18466 }
18467 }
18468 if (!BaseShAmt.getNode())
18469 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
18470 DAG.getIntPtrConstant(0));
18471 }
18472 }
18474 if (BaseShAmt.getNode()) {
18475 if (EltVT.bitsGT(MVT::i32))
18476 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
18477 else if (EltVT.bitsLT(MVT::i32))
18478 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18480 switch (Op.getOpcode()) {
18481 default:
18482 llvm_unreachable("Unknown shift opcode!");
18483 case ISD::SHL:
18484 switch (VT.SimpleTy) {
18485 default: return SDValue();
18486 case MVT::v2i64:
18487 case MVT::v4i32:
18488 case MVT::v8i16:
18489 case MVT::v4i64:
18490 case MVT::v8i32:
18491 case MVT::v16i16:
18492 case MVT::v16i32:
18493 case MVT::v8i64:
18494 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
18495 }
18496 case ISD::SRA:
18497 switch (VT.SimpleTy) {
18498 default: return SDValue();
18499 case MVT::v4i32:
18500 case MVT::v8i16:
18501 case MVT::v8i32:
18502 case MVT::v16i16:
18503 case MVT::v16i32:
18504 case MVT::v8i64:
18505 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
18506 }
18507 case ISD::SRL:
18508 switch (VT.SimpleTy) {
18509 default: return SDValue();
18510 case MVT::v2i64:
18511 case MVT::v4i32:
18512 case MVT::v8i16:
18513 case MVT::v4i64:
18514 case MVT::v8i32:
18515 case MVT::v16i16:
18516 case MVT::v16i32:
18517 case MVT::v8i64:
18518 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
18519 }
18520 }
18521 }
18522 }
18524 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18525 if (!Subtarget->is64Bit() &&
18526 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
18527 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
18528 Amt.getOpcode() == ISD::BITCAST &&
18529 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18530 Amt = Amt.getOperand(0);
18531 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18532 VT.getVectorNumElements();
18533 std::vector<SDValue> Vals(Ratio);
18534 for (unsigned i = 0; i != Ratio; ++i)
18535 Vals[i] = Amt.getOperand(i);
18536 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18537 for (unsigned j = 0; j != Ratio; ++j)
18538 if (Vals[j] != Amt.getOperand(i + j))
18539 return SDValue();
18540 }
18541 switch (Op.getOpcode()) {
18542 default:
18543 llvm_unreachable("Unknown shift opcode!");
18544 case ISD::SHL:
18545 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
18546 case ISD::SRL:
18547 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
18548 case ISD::SRA:
18549 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
18550 }
18551 }
18553 return SDValue();
18554 }
18556 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18557 SelectionDAG &DAG) {
18558 MVT VT = Op.getSimpleValueType();
18559 SDLoc dl(Op);
18560 SDValue R = Op.getOperand(0);
18561 SDValue Amt = Op.getOperand(1);
18562 SDValue V;
18564 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18565 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18567 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
18568 if (V.getNode())
18569 return V;
18571 V = LowerScalarVariableShift(Op, DAG, Subtarget);
18572 if (V.getNode())
18573 return V;
18575 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
18576 return Op;
18577 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
18578 if (Subtarget->hasInt256()) {
18579 if (Op.getOpcode() == ISD::SRL &&
18580 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18581 VT == MVT::v4i64 || VT == MVT::v8i32))
18582 return Op;
18583 if (Op.getOpcode() == ISD::SHL &&
18584 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18585 VT == MVT::v4i64 || VT == MVT::v8i32))
18586 return Op;
18587 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
18588 return Op;
18589 }
18591 // If possible, lower this packed shift into a vector multiply instead of
18592 // expanding it into a sequence of scalar shifts.
18593 // Do this only if the vector shift count is a constant build_vector.
18594 if (Op.getOpcode() == ISD::SHL &&
18595 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18596 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18597 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18598 SmallVector<SDValue, 8> Elts;
18599 EVT SVT = VT.getScalarType();
18600 unsigned SVTBits = SVT.getSizeInBits();
18601 const APInt &One = APInt(SVTBits, 1);
18602 unsigned NumElems = VT.getVectorNumElements();
18604 for (unsigned i=0; i !=NumElems; ++i) {
18605 SDValue Op = Amt->getOperand(i);
18606 if (Op->getOpcode() == ISD::UNDEF) {
18607 Elts.push_back(Op);
18608 continue;
18609 }
18611 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18612 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
18613 uint64_t ShAmt = C.getZExtValue();
18614 if (ShAmt >= SVTBits) {
18615 Elts.push_back(DAG.getUNDEF(SVT));
18616 continue;
18617 }
18618 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
18619 }
18620 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18621 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18622 }
18624 // Lower SHL with variable shift amount.
18625 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18626 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
18628 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
18629 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
18630 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18631 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18632 }
18634 // If possible, lower this shift as a sequence of two shifts by
18635 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18636 // Example:
18637 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18638 //
18639 // Could be rewritten as:
18640 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18641 //
18642 // The advantage is that the two shifts from the example would be
18643 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18644 // the vector shift into four scalar shifts plus four pairs of vector
18645 // insert/extract.
18646 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18647 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18648 unsigned TargetOpcode = X86ISD::MOVSS;
18649 bool CanBeSimplified;
18650 // The splat value for the first packed shift (the 'X' from the example).
18651 SDValue Amt1 = Amt->getOperand(0);
18652 // The splat value for the second packed shift (the 'Y' from the example).
18653 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18654 Amt->getOperand(2);
18656 // See if it is possible to replace this node with a sequence of
18657 // two shifts followed by a MOVSS/MOVSD
18658 if (VT == MVT::v4i32) {
18659 // Check if it is legal to use a MOVSS.
18660 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18661 Amt2 == Amt->getOperand(3);
18662 if (!CanBeSimplified) {
18663 // Otherwise, check if we can still simplify this node using a MOVSD.
18664 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18665 Amt->getOperand(2) == Amt->getOperand(3);
18666 TargetOpcode = X86ISD::MOVSD;
18667 Amt2 = Amt->getOperand(2);
18668 }
18669 } else {
18670 // Do similar checks for the case where the machine value type
18671 // is MVT::v8i16.
18672 CanBeSimplified = Amt1 == Amt->getOperand(1);
18673 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18674 CanBeSimplified = Amt2 == Amt->getOperand(i);
18676 if (!CanBeSimplified) {
18677 TargetOpcode = X86ISD::MOVSD;
18678 CanBeSimplified = true;
18679 Amt2 = Amt->getOperand(4);
18680 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18681 CanBeSimplified = Amt1 == Amt->getOperand(i);
18682 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18683 CanBeSimplified = Amt2 == Amt->getOperand(j);
18684 }
18685 }
18687 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18688 isa<ConstantSDNode>(Amt2)) {
18689 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18690 EVT CastVT = MVT::v4i32;
18691 SDValue Splat1 =
18692 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
18693 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18694 SDValue Splat2 =
18695 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
18696 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18697 if (TargetOpcode == X86ISD::MOVSD)
18698 CastVT = MVT::v2i64;
18699 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
18700 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
18701 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18702 BitCast1, DAG);
18703 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
18704 }
18705 }
18707 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
18708 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
18710 // a = a << 5;
18711 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
18712 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
18714 // Turn 'a' into a mask suitable for VSELECT
18715 SDValue VSelM = DAG.getConstant(0x80, VT);
18716 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18717 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18719 SDValue CM1 = DAG.getConstant(0x0f, VT);
18720 SDValue CM2 = DAG.getConstant(0x3f, VT);
18722 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
18723 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
18724 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
18725 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18726 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18728 // a += a
18729 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18730 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18731 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18733 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
18734 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
18735 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
18736 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18737 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18739 // a += a
18740 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18741 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18742 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18744 // return VSELECT(r, r+r, a);
18745 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
18746 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
18747 return R;
18748 }
18750 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18751 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18752 // solution better.
18753 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18754 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
18755 unsigned ExtOpc =
18756 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18757 R = DAG.getNode(ExtOpc, dl, NewVT, R);
18758 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
18759 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18760 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
18761 }
18763 // Decompose 256-bit shifts into smaller 128-bit shifts.
18764 if (VT.is256BitVector()) {
18765 unsigned NumElems = VT.getVectorNumElements();
18766 MVT EltVT = VT.getVectorElementType();
18767 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18769 // Extract the two vectors
18770 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18771 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18773 // Recreate the shift amount vectors
18774 SDValue Amt1, Amt2;
18775 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18776 // Constant shift amount
18777 SmallVector<SDValue, 4> Amt1Csts;
18778 SmallVector<SDValue, 4> Amt2Csts;
18779 for (unsigned i = 0; i != NumElems/2; ++i)
18780 Amt1Csts.push_back(Amt->getOperand(i));
18781 for (unsigned i = NumElems/2; i != NumElems; ++i)
18782 Amt2Csts.push_back(Amt->getOperand(i));
18784 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18785 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18786 } else {
18787 // Variable shift amount
18788 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18789 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18790 }
18792 // Issue new vector shifts for the smaller types
18793 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18794 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18796 // Concatenate the result back
18797 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18798 }
18800 return SDValue();
18801 }
18803 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18804 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18805 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18806 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18807 // has only one use.
18808 SDNode *N = Op.getNode();
18809 SDValue LHS = N->getOperand(0);
18810 SDValue RHS = N->getOperand(1);
18811 unsigned BaseOp = 0;
18812 unsigned Cond = 0;
18813 SDLoc DL(Op);
18814 switch (Op.getOpcode()) {
18815 default: llvm_unreachable("Unknown ovf instruction!");
18816 case ISD::SADDO:
18817 // A subtract of one will be selected as a INC. Note that INC doesn't
18818 // set CF, so we can't do this for UADDO.
18819 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18820 if (C->isOne()) {
18821 BaseOp = X86ISD::INC;
18822 Cond = X86::COND_O;
18823 break;
18824 }
18825 BaseOp = X86ISD::ADD;
18826 Cond = X86::COND_O;
18827 break;
18828 case ISD::UADDO:
18829 BaseOp = X86ISD::ADD;
18830 Cond = X86::COND_B;
18831 break;
18832 case ISD::SSUBO:
18833 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18834 // set CF, so we can't do this for USUBO.
18835 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18836 if (C->isOne()) {
18837 BaseOp = X86ISD::DEC;
18838 Cond = X86::COND_O;
18839 break;
18840 }
18841 BaseOp = X86ISD::SUB;
18842 Cond = X86::COND_O;
18843 break;
18844 case ISD::USUBO:
18845 BaseOp = X86ISD::SUB;
18846 Cond = X86::COND_B;
18847 break;
18848 case ISD::SMULO:
18849 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18850 Cond = X86::COND_O;
18851 break;
18852 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18853 if (N->getValueType(0) == MVT::i8) {
18854 BaseOp = X86ISD::UMUL8;
18855 Cond = X86::COND_O;
18856 break;
18857 }
18858 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18859 MVT::i32);
18860 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18862 SDValue SetCC =
18863 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18864 DAG.getConstant(X86::COND_O, MVT::i32),
18865 SDValue(Sum.getNode(), 2));
18867 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18868 }
18869 }
18871 // Also sets EFLAGS.
18872 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18873 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18875 SDValue SetCC =
18876 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18877 DAG.getConstant(Cond, MVT::i32),
18878 SDValue(Sum.getNode(), 1));
18880 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18881 }
18883 // Sign extension of the low part of vector elements. This may be used either
18884 // when sign extend instructions are not available or if the vector element
18885 // sizes already match the sign-extended size. If the vector elements are in
18886 // their pre-extended size and sign extend instructions are available, that will
18887 // be handled by LowerSIGN_EXTEND.
18888 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
18889 SelectionDAG &DAG) const {
18890 SDLoc dl(Op);
18891 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
18892 MVT VT = Op.getSimpleValueType();
18894 if (!Subtarget->hasSSE2() || !VT.isVector())
18895 return SDValue();
18897 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
18898 ExtraVT.getScalarType().getSizeInBits();
18900 switch (VT.SimpleTy) {
18901 default: return SDValue();
18902 case MVT::v8i32:
18903 case MVT::v16i16:
18904 if (!Subtarget->hasFp256())
18905 return SDValue();
18906 if (!Subtarget->hasInt256()) {
18907 // needs to be split
18908 unsigned NumElems = VT.getVectorNumElements();
18910 // Extract the LHS vectors
18911 SDValue LHS = Op.getOperand(0);
18912 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18913 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18915 MVT EltVT = VT.getVectorElementType();
18916 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18918 EVT ExtraEltVT = ExtraVT.getVectorElementType();
18919 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
18920 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
18921 ExtraNumElems/2);
18922 SDValue Extra = DAG.getValueType(ExtraVT);
18924 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
18925 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
18927 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
18928 }
18929 // fall through
18930 case MVT::v4i32:
18931 case MVT::v8i16: {
18932 SDValue Op0 = Op.getOperand(0);
18934 // This is a sign extension of some low part of vector elements without
18935 // changing the size of the vector elements themselves:
18936 // Shift-Left + Shift-Right-Algebraic.
18937 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
18938 BitsDiff, DAG);
18939 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
18940 DAG);
18941 }
18942 }
18943 }
18945 /// Returns true if the operand type is exactly twice the native width, and
18946 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18947 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18948 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18949 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
18950 const X86Subtarget &Subtarget =
18951 getTargetMachine().getSubtarget<X86Subtarget>();
18952 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18954 if (OpWidth == 64)
18955 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18956 else if (OpWidth == 128)
18957 return Subtarget.hasCmpxchg16b();
18958 else
18959 return false;
18960 }
18962 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18963 return needsCmpXchgNb(SI->getValueOperand()->getType());
18964 }
18966 // Note: this turns large loads into lock cmpxchg8b/16b.
18967 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18968 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18969 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18970 return needsCmpXchgNb(PTy->getElementType());
18971 }
18973 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18974 const X86Subtarget &Subtarget =
18975 getTargetMachine().getSubtarget<X86Subtarget>();
18976 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18977 const Type *MemType = AI->getType();
18979 // If the operand is too big, we must see if cmpxchg8/16b is available
18980 // and default to library calls otherwise.
18981 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18982 return needsCmpXchgNb(MemType);
18984 AtomicRMWInst::BinOp Op = AI->getOperation();
18985 switch (Op) {
18986 default:
18987 llvm_unreachable("Unknown atomic operation");
18988 case AtomicRMWInst::Xchg:
18989 case AtomicRMWInst::Add:
18990 case AtomicRMWInst::Sub:
18991 // It's better to use xadd, xsub or xchg for these in all cases.
18992 return false;
18993 case AtomicRMWInst::Or:
18994 case AtomicRMWInst::And:
18995 case AtomicRMWInst::Xor:
18996 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18997 // prefix to a normal instruction for these operations.
18998 return !AI->use_empty();
18999 case AtomicRMWInst::Nand:
19000 case AtomicRMWInst::Max:
19001 case AtomicRMWInst::Min:
19002 case AtomicRMWInst::UMax:
19003 case AtomicRMWInst::UMin:
19004 // These always require a non-trivial set of data operations on x86. We must
19005 // use a cmpxchg loop.
19006 return true;
19007 }
19008 }
19010 static bool hasMFENCE(const X86Subtarget& Subtarget) {
19011 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
19012 // no-sse2). There isn't any reason to disable it if the target processor
19013 // supports it.
19014 return Subtarget.hasSSE2() || Subtarget.is64Bit();
19015 }
19017 LoadInst *
19018 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
19019 const X86Subtarget &Subtarget =
19020 getTargetMachine().getSubtarget<X86Subtarget>();
19021 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
19022 const Type *MemType = AI->getType();
19023 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
19024 // there is no benefit in turning such RMWs into loads, and it is actually
19025 // harmful as it introduces a mfence.
19026 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
19027 return nullptr;
19029 auto Builder = IRBuilder<>(AI);
19030 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
19031 auto SynchScope = AI->getSynchScope();
19032 // We must restrict the ordering to avoid generating loads with Release or
19033 // ReleaseAcquire orderings.
19034 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
19035 auto Ptr = AI->getPointerOperand();
19037 // Before the load we need a fence. Here is an example lifted from
19038 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
19039 // is required:
19040 // Thread 0:
19041 // x.store(1, relaxed);
19042 // r1 = y.fetch_add(0, release);
19043 // Thread 1:
19044 // y.fetch_add(42, acquire);
19045 // r2 = x.load(relaxed);
19046 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
19047 // lowered to just a load without a fence. A mfence flushes the store buffer,
19048 // making the optimization clearly correct.
19049 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
19050 // otherwise, we might be able to be more agressive on relaxed idempotent
19051 // rmw. In practice, they do not look useful, so we don't try to be
19052 // especially clever.
19053 if (SynchScope == SingleThread) {
19054 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
19055 // the IR level, so we must wrap it in an intrinsic.
19056 return nullptr;
19057 } else if (hasMFENCE(Subtarget)) {
19058 Function *MFence = llvm::Intrinsic::getDeclaration(M,
19059 Intrinsic::x86_sse2_mfence);
19060 Builder.CreateCall(MFence);
19061 } else {
19062 // FIXME: it might make sense to use a locked operation here but on a
19063 // different cache-line to prevent cache-line bouncing. In practice it
19064 // is probably a small win, and x86 processors without mfence are rare
19065 // enough that we do not bother.
19066 return nullptr;
19067 }
19069 // Finally we can emit the atomic load.
19070 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
19071 AI->getType()->getPrimitiveSizeInBits());
19072 Loaded->setAtomic(Order, SynchScope);
19073 AI->replaceAllUsesWith(Loaded);
19074 AI->eraseFromParent();
19075 return Loaded;
19076 }
19078 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
19079 SelectionDAG &DAG) {
19080 SDLoc dl(Op);
19081 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
19082 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
19083 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
19084 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
19086 // The only fence that needs an instruction is a sequentially-consistent
19087 // cross-thread fence.
19088 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
19089 if (hasMFENCE(*Subtarget))
19090 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
19092 SDValue Chain = Op.getOperand(0);
19093 SDValue Zero = DAG.getConstant(0, MVT::i32);
19094 SDValue Ops[] = {
19095 DAG.getRegister(X86::ESP, MVT::i32), // Base
19096 DAG.getTargetConstant(1, MVT::i8), // Scale
19097 DAG.getRegister(0, MVT::i32), // Index
19098 DAG.getTargetConstant(0, MVT::i32), // Disp
19099 DAG.getRegister(0, MVT::i32), // Segment.
19100 Zero,
19101 Chain
19102 };
19103 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
19104 return SDValue(Res, 0);
19105 }
19107 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
19108 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
19109 }
19111 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
19112 SelectionDAG &DAG) {
19113 MVT T = Op.getSimpleValueType();
19114 SDLoc DL(Op);
19115 unsigned Reg = 0;
19116 unsigned size = 0;
19117 switch(T.SimpleTy) {
19118 default: llvm_unreachable("Invalid value type!");
19119 case MVT::i8: Reg = X86::AL; size = 1; break;
19120 case MVT::i16: Reg = X86::AX; size = 2; break;
19121 case MVT::i32: Reg = X86::EAX; size = 4; break;
19122 case MVT::i64:
19123 assert(Subtarget->is64Bit() && "Node not type legal!");
19124 Reg = X86::RAX; size = 8;
19125 break;
19126 }
19127 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
19128 Op.getOperand(2), SDValue());
19129 SDValue Ops[] = { cpIn.getValue(0),
19130 Op.getOperand(1),
19131 Op.getOperand(3),
19132 DAG.getTargetConstant(size, MVT::i8),
19133 cpIn.getValue(1) };
19134 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19135 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
19136 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
19137 Ops, T, MMO);
19139 SDValue cpOut =
19140 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
19141 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
19142 MVT::i32, cpOut.getValue(2));
19143 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
19144 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19146 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
19147 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
19148 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
19149 return SDValue();
19150 }
19152 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
19153 SelectionDAG &DAG) {
19154 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
19155 MVT DstVT = Op.getSimpleValueType();
19157 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
19158 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19159 if (DstVT != MVT::f64)
19160 // This conversion needs to be expanded.
19161 return SDValue();
19163 SDValue InVec = Op->getOperand(0);
19164 SDLoc dl(Op);
19165 unsigned NumElts = SrcVT.getVectorNumElements();
19166 EVT SVT = SrcVT.getVectorElementType();
19168 // Widen the vector in input in the case of MVT::v2i32.
19169 // Example: from MVT::v2i32 to MVT::v4i32.
19170 SmallVector<SDValue, 16> Elts;
19171 for (unsigned i = 0, e = NumElts; i != e; ++i)
19172 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
19173 DAG.getIntPtrConstant(i)));
19175 // Explicitly mark the extra elements as Undef.
19176 SDValue Undef = DAG.getUNDEF(SVT);
19177 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
19178 Elts.push_back(Undef);
19180 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19181 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
19182 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
19183 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
19184 DAG.getIntPtrConstant(0));
19185 }
19187 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
19188 Subtarget->hasMMX() && "Unexpected custom BITCAST");
19189 assert((DstVT == MVT::i64 ||
19190 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
19191 "Unexpected custom BITCAST");
19192 // i64 <=> MMX conversions are Legal.
19193 if (SrcVT==MVT::i64 && DstVT.isVector())
19194 return Op;
19195 if (DstVT==MVT::i64 && SrcVT.isVector())
19196 return Op;
19197 // MMX <=> MMX conversions are Legal.
19198 if (SrcVT.isVector() && DstVT.isVector())
19199 return Op;
19200 // All other conversions need to be expanded.
19201 return SDValue();
19202 }
19204 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19205 SDNode *Node = Op.getNode();
19206 SDLoc dl(Node);
19207 EVT T = Node->getValueType(0);
19208 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19209 DAG.getConstant(0, T), Node->getOperand(2));
19210 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19211 cast<AtomicSDNode>(Node)->getMemoryVT(),
19212 Node->getOperand(0),
19213 Node->getOperand(1), negOp,
19214 cast<AtomicSDNode>(Node)->getMemOperand(),
19215 cast<AtomicSDNode>(Node)->getOrdering(),
19216 cast<AtomicSDNode>(Node)->getSynchScope());
19217 }
19219 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19220 SDNode *Node = Op.getNode();
19221 SDLoc dl(Node);
19222 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19224 // Convert seq_cst store -> xchg
19225 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19226 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19227 // (The only way to get a 16-byte store is cmpxchg16b)
19228 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19229 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19230 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19231 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19232 cast<AtomicSDNode>(Node)->getMemoryVT(),
19233 Node->getOperand(0),
19234 Node->getOperand(1), Node->getOperand(2),
19235 cast<AtomicSDNode>(Node)->getMemOperand(),
19236 cast<AtomicSDNode>(Node)->getOrdering(),
19237 cast<AtomicSDNode>(Node)->getSynchScope());
19238 return Swap.getValue(1);
19239 }
19240 // Other atomic stores have a simple pattern.
19241 return Op;
19242 }
19244 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19245 EVT VT = Op.getNode()->getSimpleValueType(0);
19247 // Let legalize expand this if it isn't a legal type yet.
19248 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19249 return SDValue();
19251 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19253 unsigned Opc;
19254 bool ExtraOp = false;
19255 switch (Op.getOpcode()) {
19256 default: llvm_unreachable("Invalid code");
19257 case ISD::ADDC: Opc = X86ISD::ADD; break;
19258 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19259 case ISD::SUBC: Opc = X86ISD::SUB; break;
19260 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19261 }
19263 if (!ExtraOp)
19264 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19265 Op.getOperand(1));
19266 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19267 Op.getOperand(1), Op.getOperand(2));
19268 }
19270 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19271 SelectionDAG &DAG) {
19272 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19274 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19275 // which returns the values as { float, float } (in XMM0) or
19276 // { double, double } (which is returned in XMM0, XMM1).
19277 SDLoc dl(Op);
19278 SDValue Arg = Op.getOperand(0);
19279 EVT ArgVT = Arg.getValueType();
19280 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19282 TargetLowering::ArgListTy Args;
19283 TargetLowering::ArgListEntry Entry;
19285 Entry.Node = Arg;
19286 Entry.Ty = ArgTy;
19287 Entry.isSExt = false;
19288 Entry.isZExt = false;
19289 Args.push_back(Entry);
19291 bool isF64 = ArgVT == MVT::f64;
19292 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19293 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19294 // the results are returned via SRet in memory.
19295 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19296 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19297 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
19299 Type *RetTy = isF64
19300 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19301 : (Type*)VectorType::get(ArgTy, 4);
19303 TargetLowering::CallLoweringInfo CLI(DAG);
19304 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19305 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19307 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19309 if (isF64)
19310 // Returned in xmm0 and xmm1.
19311 return CallResult.first;
19313 // Returned in bits 0:31 and 32:64 xmm0.
19314 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19315 CallResult.first, DAG.getIntPtrConstant(0));
19316 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19317 CallResult.first, DAG.getIntPtrConstant(1));
19318 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19319 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19320 }
19322 /// LowerOperation - Provide custom lowering hooks for some operations.
19323 ///
19324 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19325 switch (Op.getOpcode()) {
19326 default: llvm_unreachable("Should not custom lower this!");
19327 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
19328 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19329 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19330 return LowerCMP_SWAP(Op, Subtarget, DAG);
19331 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19332 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19333 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19334 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
19335 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
19336 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19337 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19338 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19339 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19340 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19341 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19342 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19343 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19344 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19345 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19346 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19347 case ISD::SHL_PARTS:
19348 case ISD::SRA_PARTS:
19349 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19350 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19351 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19352 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19353 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19354 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19355 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19356 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19357 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19358 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19359 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19360 case ISD::FABS:
19361 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19362 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19363 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19364 case ISD::SETCC: return LowerSETCC(Op, DAG);
19365 case ISD::SELECT: return LowerSELECT(Op, DAG);
19366 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19367 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19368 case ISD::VASTART: return LowerVASTART(Op, DAG);
19369 case ISD::VAARG: return LowerVAARG(Op, DAG);
19370 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19371 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19372 case ISD::INTRINSIC_VOID:
19373 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19374 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19375 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19376 case ISD::FRAME_TO_ARGS_OFFSET:
19377 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19378 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19379 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19380 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19381 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19382 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19383 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19384 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19385 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
19386 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
19387 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
19388 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19389 case ISD::UMUL_LOHI:
19390 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19391 case ISD::SRA:
19392 case ISD::SRL:
19393 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19394 case ISD::SADDO:
19395 case ISD::UADDO:
19396 case ISD::SSUBO:
19397 case ISD::USUBO:
19398 case ISD::SMULO:
19399 case ISD::UMULO: return LowerXALUO(Op, DAG);
19400 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19401 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19402 case ISD::ADDC:
19403 case ISD::ADDE:
19404 case ISD::SUBC:
19405 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19406 case ISD::ADD: return LowerADD(Op, DAG);
19407 case ISD::SUB: return LowerSUB(Op, DAG);
19408 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19409 }
19410 }
19412 /// ReplaceNodeResults - Replace a node with an illegal result type
19413 /// with a new node built out of custom code.
19414 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19415 SmallVectorImpl<SDValue>&Results,
19416 SelectionDAG &DAG) const {
19417 SDLoc dl(N);
19418 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19419 switch (N->getOpcode()) {
19420 default:
19421 llvm_unreachable("Do not know how to custom type legalize this operation!");
19422 case ISD::SIGN_EXTEND_INREG:
19423 case ISD::ADDC:
19424 case ISD::ADDE:
19425 case ISD::SUBC:
19426 case ISD::SUBE:
19427 // We don't want to expand or promote these.
19428 return;
19429 case ISD::SDIV:
19430 case ISD::UDIV:
19431 case ISD::SREM:
19432 case ISD::UREM:
19433 case ISD::SDIVREM:
19434 case ISD::UDIVREM: {
19435 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19436 Results.push_back(V);
19437 return;
19438 }
19439 case ISD::FP_TO_SINT:
19440 case ISD::FP_TO_UINT: {
19441 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19443 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
19444 return;
19446 std::pair<SDValue,SDValue> Vals =
19447 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19448 SDValue FIST = Vals.first, StackSlot = Vals.second;
19449 if (FIST.getNode()) {
19450 EVT VT = N->getValueType(0);
19451 // Return a load from the stack slot.
19452 if (StackSlot.getNode())
19453 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19454 MachinePointerInfo(),
19455 false, false, false, 0));
19456 else
19457 Results.push_back(FIST);
19458 }
19459 return;
19460 }
19461 case ISD::UINT_TO_FP: {
19462 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19463 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19464 N->getValueType(0) != MVT::v2f32)
19465 return;
19466 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19467 N->getOperand(0));
19468 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
19469 MVT::f64);
19470 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19471 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19472 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
19473 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
19474 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19475 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19476 return;
19477 }
19478 case ISD::FP_ROUND: {
19479 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19480 return;
19481 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19482 Results.push_back(V);
19483 return;
19484 }
19485 case ISD::INTRINSIC_W_CHAIN: {
19486 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19487 switch (IntNo) {
19488 default : llvm_unreachable("Do not know how to custom type "
19489 "legalize this intrinsic operation!");
19490 case Intrinsic::x86_rdtsc:
19491 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19492 Results);
19493 case Intrinsic::x86_rdtscp:
19494 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19495 Results);
19496 case Intrinsic::x86_rdpmc:
19497 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19498 }
19499 }
19500 case ISD::READCYCLECOUNTER: {
19501 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19502 Results);
19503 }
19504 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19505 EVT T = N->getValueType(0);
19506 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19507 bool Regs64bit = T == MVT::i128;
19508 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19509 SDValue cpInL, cpInH;
19510 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19511 DAG.getConstant(0, HalfT));
19512 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19513 DAG.getConstant(1, HalfT));
19514 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19515 Regs64bit ? X86::RAX : X86::EAX,
19516 cpInL, SDValue());
19517 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19518 Regs64bit ? X86::RDX : X86::EDX,
19519 cpInH, cpInL.getValue(1));
19520 SDValue swapInL, swapInH;
19521 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19522 DAG.getConstant(0, HalfT));
19523 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19524 DAG.getConstant(1, HalfT));
19525 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19526 Regs64bit ? X86::RBX : X86::EBX,
19527 swapInL, cpInH.getValue(1));
19528 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19529 Regs64bit ? X86::RCX : X86::ECX,
19530 swapInH, swapInL.getValue(1));
19531 SDValue Ops[] = { swapInH.getValue(0),
19532 N->getOperand(1),
19533 swapInH.getValue(1) };
19534 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19535 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19536 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19537 X86ISD::LCMPXCHG8_DAG;
19538 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19539 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19540 Regs64bit ? X86::RAX : X86::EAX,
19541 HalfT, Result.getValue(1));
19542 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19543 Regs64bit ? X86::RDX : X86::EDX,
19544 HalfT, cpOutL.getValue(2));
19545 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19547 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19548 MVT::i32, cpOutH.getValue(2));
19549 SDValue Success =
19550 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19551 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19552 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19554 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19555 Results.push_back(Success);
19556 Results.push_back(EFLAGS.getValue(1));
19557 return;
19558 }
19559 case ISD::ATOMIC_SWAP:
19560 case ISD::ATOMIC_LOAD_ADD:
19561 case ISD::ATOMIC_LOAD_SUB:
19562 case ISD::ATOMIC_LOAD_AND:
19563 case ISD::ATOMIC_LOAD_OR:
19564 case ISD::ATOMIC_LOAD_XOR:
19565 case ISD::ATOMIC_LOAD_NAND:
19566 case ISD::ATOMIC_LOAD_MIN:
19567 case ISD::ATOMIC_LOAD_MAX:
19568 case ISD::ATOMIC_LOAD_UMIN:
19569 case ISD::ATOMIC_LOAD_UMAX:
19570 case ISD::ATOMIC_LOAD: {
19571 // Delegate to generic TypeLegalization. Situations we can really handle
19572 // should have already been dealt with by AtomicExpandPass.cpp.
19573 break;
19574 }
19575 case ISD::BITCAST: {
19576 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19577 EVT DstVT = N->getValueType(0);
19578 EVT SrcVT = N->getOperand(0)->getValueType(0);
19580 if (SrcVT != MVT::f64 ||
19581 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19582 return;
19584 unsigned NumElts = DstVT.getVectorNumElements();
19585 EVT SVT = DstVT.getVectorElementType();
19586 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19587 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19588 MVT::v2f64, N->getOperand(0));
19589 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
19591 if (ExperimentalVectorWideningLegalization) {
19592 // If we are legalizing vectors by widening, we already have the desired
19593 // legal vector type, just return it.
19594 Results.push_back(ToVecInt);
19595 return;
19596 }
19598 SmallVector<SDValue, 8> Elts;
19599 for (unsigned i = 0, e = NumElts; i != e; ++i)
19600 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19601 ToVecInt, DAG.getIntPtrConstant(i)));
19603 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19604 }
19605 }
19606 }
19608 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19609 switch (Opcode) {
19610 default: return nullptr;
19611 case X86ISD::BSF: return "X86ISD::BSF";
19612 case X86ISD::BSR: return "X86ISD::BSR";
19613 case X86ISD::SHLD: return "X86ISD::SHLD";
19614 case X86ISD::SHRD: return "X86ISD::SHRD";
19615 case X86ISD::FAND: return "X86ISD::FAND";
19616 case X86ISD::FANDN: return "X86ISD::FANDN";
19617 case X86ISD::FOR: return "X86ISD::FOR";
19618 case X86ISD::FXOR: return "X86ISD::FXOR";
19619 case X86ISD::FSRL: return "X86ISD::FSRL";
19620 case X86ISD::FILD: return "X86ISD::FILD";
19621 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19622 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19623 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19624 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19625 case X86ISD::FLD: return "X86ISD::FLD";
19626 case X86ISD::FST: return "X86ISD::FST";
19627 case X86ISD::CALL: return "X86ISD::CALL";
19628 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19629 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19630 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19631 case X86ISD::BT: return "X86ISD::BT";
19632 case X86ISD::CMP: return "X86ISD::CMP";
19633 case X86ISD::COMI: return "X86ISD::COMI";
19634 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19635 case X86ISD::CMPM: return "X86ISD::CMPM";
19636 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19637 case X86ISD::SETCC: return "X86ISD::SETCC";
19638 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19639 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19640 case X86ISD::CMOV: return "X86ISD::CMOV";
19641 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19642 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19643 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19644 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19645 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19646 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19647 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19648 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19649 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19650 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19651 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19652 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19653 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19654 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19655 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19656 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19657 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19658 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19659 case X86ISD::HADD: return "X86ISD::HADD";
19660 case X86ISD::HSUB: return "X86ISD::HSUB";
19661 case X86ISD::FHADD: return "X86ISD::FHADD";
19662 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19663 case X86ISD::UMAX: return "X86ISD::UMAX";
19664 case X86ISD::UMIN: return "X86ISD::UMIN";
19665 case X86ISD::SMAX: return "X86ISD::SMAX";
19666 case X86ISD::SMIN: return "X86ISD::SMIN";
19667 case X86ISD::FMAX: return "X86ISD::FMAX";
19668 case X86ISD::FMIN: return "X86ISD::FMIN";
19669 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19670 case X86ISD::FMINC: return "X86ISD::FMINC";
19671 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19672 case X86ISD::FRCP: return "X86ISD::FRCP";
19673 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19674 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19675 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19676 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19677 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19678 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19679 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19680 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19681 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19682 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19683 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19684 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19685 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19686 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19687 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19688 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19689 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19690 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
19691 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19692 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19693 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19694 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19695 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19696 case X86ISD::VSHL: return "X86ISD::VSHL";
19697 case X86ISD::VSRL: return "X86ISD::VSRL";
19698 case X86ISD::VSRA: return "X86ISD::VSRA";
19699 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19700 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19701 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19702 case X86ISD::CMPP: return "X86ISD::CMPP";
19703 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19704 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19705 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19706 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19707 case X86ISD::ADD: return "X86ISD::ADD";
19708 case X86ISD::SUB: return "X86ISD::SUB";
19709 case X86ISD::ADC: return "X86ISD::ADC";
19710 case X86ISD::SBB: return "X86ISD::SBB";
19711 case X86ISD::SMUL: return "X86ISD::SMUL";
19712 case X86ISD::UMUL: return "X86ISD::UMUL";
19713 case X86ISD::SMUL8: return "X86ISD::SMUL8";
19714 case X86ISD::UMUL8: return "X86ISD::UMUL8";
19715 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
19716 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
19717 case X86ISD::INC: return "X86ISD::INC";
19718 case X86ISD::DEC: return "X86ISD::DEC";
19719 case X86ISD::OR: return "X86ISD::OR";
19720 case X86ISD::XOR: return "X86ISD::XOR";
19721 case X86ISD::AND: return "X86ISD::AND";
19722 case X86ISD::BEXTR: return "X86ISD::BEXTR";
19723 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
19724 case X86ISD::PTEST: return "X86ISD::PTEST";
19725 case X86ISD::TESTP: return "X86ISD::TESTP";
19726 case X86ISD::TESTM: return "X86ISD::TESTM";
19727 case X86ISD::TESTNM: return "X86ISD::TESTNM";
19728 case X86ISD::KORTEST: return "X86ISD::KORTEST";
19729 case X86ISD::PACKSS: return "X86ISD::PACKSS";
19730 case X86ISD::PACKUS: return "X86ISD::PACKUS";
19731 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
19732 case X86ISD::VALIGN: return "X86ISD::VALIGN";
19733 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
19734 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
19735 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
19736 case X86ISD::SHUFP: return "X86ISD::SHUFP";
19737 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
19738 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
19739 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
19740 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
19741 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
19742 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
19743 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
19744 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
19745 case X86ISD::MOVSD: return "X86ISD::MOVSD";
19746 case X86ISD::MOVSS: return "X86ISD::MOVSS";
19747 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
19748 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
19749 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
19750 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
19751 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
19752 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
19753 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
19754 case X86ISD::VPERMV: return "X86ISD::VPERMV";
19755 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
19756 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
19757 case X86ISD::VPERMI: return "X86ISD::VPERMI";
19758 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
19759 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
19760 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
19761 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
19762 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
19763 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
19764 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
19765 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
19766 case X86ISD::SAHF: return "X86ISD::SAHF";
19767 case X86ISD::RDRAND: return "X86ISD::RDRAND";
19768 case X86ISD::RDSEED: return "X86ISD::RDSEED";
19769 case X86ISD::FMADD: return "X86ISD::FMADD";
19770 case X86ISD::FMSUB: return "X86ISD::FMSUB";
19771 case X86ISD::FNMADD: return "X86ISD::FNMADD";
19772 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
19773 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
19774 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
19775 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
19776 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
19777 case X86ISD::XTEST: return "X86ISD::XTEST";
19778 }
19779 }
19781 // isLegalAddressingMode - Return true if the addressing mode represented
19782 // by AM is legal for this target, for a load/store of the specified type.
19783 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
19784 Type *Ty) const {
19785 // X86 supports extremely general addressing modes.
19786 CodeModel::Model M = getTargetMachine().getCodeModel();
19787 Reloc::Model R = getTargetMachine().getRelocationModel();
19789 // X86 allows a sign-extended 32-bit immediate field as a displacement.
19790 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
19791 return false;
19793 if (AM.BaseGV) {
19794 unsigned GVFlags =
19795 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
19797 // If a reference to this global requires an extra load, we can't fold it.
19798 if (isGlobalStubReference(GVFlags))
19799 return false;
19801 // If BaseGV requires a register for the PIC base, we cannot also have a
19802 // BaseReg specified.
19803 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
19804 return false;
19806 // If lower 4G is not available, then we must use rip-relative addressing.
19807 if ((M != CodeModel::Small || R != Reloc::Static) &&
19808 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
19809 return false;
19810 }
19812 switch (AM.Scale) {
19813 case 0:
19814 case 1:
19815 case 2:
19816 case 4:
19817 case 8:
19818 // These scales always work.
19819 break;
19820 case 3:
19821 case 5:
19822 case 9:
19823 // These scales are formed with basereg+scalereg. Only accept if there is
19824 // no basereg yet.
19825 if (AM.HasBaseReg)
19826 return false;
19827 break;
19828 default: // Other stuff never works.
19829 return false;
19830 }
19832 return true;
19833 }
19835 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
19836 unsigned Bits = Ty->getScalarSizeInBits();
19838 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
19839 // particularly cheaper than those without.
19840 if (Bits == 8)
19841 return false;
19843 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
19844 // variable shifts just as cheap as scalar ones.
19845 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
19846 return false;
19848 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
19849 // fully general vector.
19850 return true;
19851 }
19853 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
19854 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19855 return false;
19856 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
19857 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
19858 return NumBits1 > NumBits2;
19859 }
19861 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
19862 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19863 return false;
19865 if (!isTypeLegal(EVT::getEVT(Ty1)))
19866 return false;
19868 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
19870 // Assuming the caller doesn't have a zeroext or signext return parameter,
19871 // truncation all the way down to i1 is valid.
19872 return true;
19873 }
19875 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
19876 return isInt<32>(Imm);
19877 }
19879 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
19880 // Can also use sub to handle negated immediates.
19881 return isInt<32>(Imm);
19882 }
19884 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
19885 if (!VT1.isInteger() || !VT2.isInteger())
19886 return false;
19887 unsigned NumBits1 = VT1.getSizeInBits();
19888 unsigned NumBits2 = VT2.getSizeInBits();
19889 return NumBits1 > NumBits2;
19890 }
19892 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
19893 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19894 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
19895 }
19897 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
19898 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19899 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
19900 }
19902 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
19903 EVT VT1 = Val.getValueType();
19904 if (isZExtFree(VT1, VT2))
19905 return true;
19907 if (Val.getOpcode() != ISD::LOAD)
19908 return false;
19910 if (!VT1.isSimple() || !VT1.isInteger() ||
19911 !VT2.isSimple() || !VT2.isInteger())
19912 return false;
19914 switch (VT1.getSimpleVT().SimpleTy) {
19915 default: break;
19916 case MVT::i8:
19917 case MVT::i16:
19918 case MVT::i32:
19919 // X86 has 8, 16, and 32-bit zero-extending loads.
19920 return true;
19921 }
19923 return false;
19924 }
19926 bool
19927 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
19928 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
19929 return false;
19931 VT = VT.getScalarType();
19933 if (!VT.isSimple())
19934 return false;
19936 switch (VT.getSimpleVT().SimpleTy) {
19937 case MVT::f32:
19938 case MVT::f64:
19939 return true;
19940 default:
19941 break;
19942 }
19944 return false;
19945 }
19947 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
19948 // i16 instructions are longer (0x66 prefix) and potentially slower.
19949 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
19950 }
19952 /// isShuffleMaskLegal - Targets can use this to indicate that they only
19953 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
19954 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
19955 /// are assumed to be legal.
19956 bool
19957 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
19958 EVT VT) const {
19959 if (!VT.isSimple())
19960 return false;
19962 MVT SVT = VT.getSimpleVT();
19964 // Very little shuffling can be done for 64-bit vectors right now.
19965 if (VT.getSizeInBits() == 64)
19966 return false;
19968 // If this is a single-input shuffle with no 128 bit lane crossings we can
19969 // lower it into pshufb.
19970 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
19971 (SVT.is256BitVector() && Subtarget->hasInt256())) {
19972 bool isLegal = true;
19973 for (unsigned I = 0, E = M.size(); I != E; ++I) {
19974 if (M[I] >= (int)SVT.getVectorNumElements() ||
19975 ShuffleCrosses128bitLane(SVT, I, M[I])) {
19976 isLegal = false;
19977 break;
19978 }
19979 }
19980 if (isLegal)
19981 return true;
19982 }
19984 // FIXME: blends, shifts.
19985 return (SVT.getVectorNumElements() == 2 ||
19986 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
19987 isMOVLMask(M, SVT) ||
19988 isCommutedMOVLMask(M, SVT) ||
19989 isMOVHLPSMask(M, SVT) ||
19990 isSHUFPMask(M, SVT) ||
19991 isSHUFPMask(M, SVT, /* Commuted */ true) ||
19992 isPSHUFDMask(M, SVT) ||
19993 isPSHUFDMask(M, SVT, /* SecondOperand */ true) ||
19994 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
19995 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
19996 isPALIGNRMask(M, SVT, Subtarget) ||
19997 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
19998 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
19999 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
20000 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
20001 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()) ||
20002 (Subtarget->hasSSE41() && isINSERTPSMask(M, SVT)));
20003 }
20005 bool
20006 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
20007 EVT VT) const {
20008 if (!VT.isSimple())
20009 return false;
20011 MVT SVT = VT.getSimpleVT();
20012 unsigned NumElts = SVT.getVectorNumElements();
20013 // FIXME: This collection of masks seems suspect.
20014 if (NumElts == 2)
20015 return true;
20016 if (NumElts == 4 && SVT.is128BitVector()) {
20017 return (isMOVLMask(Mask, SVT) ||
20018 isCommutedMOVLMask(Mask, SVT, true) ||
20019 isSHUFPMask(Mask, SVT) ||
20020 isSHUFPMask(Mask, SVT, /* Commuted */ true) ||
20021 isBlendMask(Mask, SVT, Subtarget->hasSSE41(),
20022 Subtarget->hasInt256()));
20023 }
20024 return false;
20025 }
20027 //===----------------------------------------------------------------------===//
20028 // X86 Scheduler Hooks
20029 //===----------------------------------------------------------------------===//
20031 /// Utility function to emit xbegin specifying the start of an RTM region.
20032 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
20033 const TargetInstrInfo *TII) {
20034 DebugLoc DL = MI->getDebugLoc();
20036 const BasicBlock *BB = MBB->getBasicBlock();
20037 MachineFunction::iterator I = MBB;
20038 ++I;
20040 // For the v = xbegin(), we generate
20041 //
20042 // thisMBB:
20043 // xbegin sinkMBB
20044 //
20045 // mainMBB:
20046 // eax = -1
20047 //
20048 // sinkMBB:
20049 // v = eax
20051 MachineBasicBlock *thisMBB = MBB;
20052 MachineFunction *MF = MBB->getParent();
20053 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20054 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20055 MF->insert(I, mainMBB);
20056 MF->insert(I, sinkMBB);
20058 // Transfer the remainder of BB and its successor edges to sinkMBB.
20059 sinkMBB->splice(sinkMBB->begin(), MBB,
20060 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20061 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20063 // thisMBB:
20064 // xbegin sinkMBB
20065 // # fallthrough to mainMBB
20066 // # abortion to sinkMBB
20067 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20068 thisMBB->addSuccessor(mainMBB);
20069 thisMBB->addSuccessor(sinkMBB);
20071 // mainMBB:
20072 // EAX = -1
20073 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20074 mainMBB->addSuccessor(sinkMBB);
20076 // sinkMBB:
20077 // EAX is live into the sinkMBB
20078 sinkMBB->addLiveIn(X86::EAX);
20079 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20080 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20081 .addReg(X86::EAX);
20083 MI->eraseFromParent();
20084 return sinkMBB;
20085 }
20087 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20088 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20089 // in the .td file.
20090 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20091 const TargetInstrInfo *TII) {
20092 unsigned Opc;
20093 switch (MI->getOpcode()) {
20094 default: llvm_unreachable("illegal opcode!");
20095 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20096 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20097 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20098 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20099 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20100 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20101 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20102 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20103 }
20105 DebugLoc dl = MI->getDebugLoc();
20106 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20108 unsigned NumArgs = MI->getNumOperands();
20109 for (unsigned i = 1; i < NumArgs; ++i) {
20110 MachineOperand &Op = MI->getOperand(i);
20111 if (!(Op.isReg() && Op.isImplicit()))
20112 MIB.addOperand(Op);
20113 }
20114 if (MI->hasOneMemOperand())
20115 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20117 BuildMI(*BB, MI, dl,
20118 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20119 .addReg(X86::XMM0);
20121 MI->eraseFromParent();
20122 return BB;
20123 }
20125 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20126 // defs in an instruction pattern
20127 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20128 const TargetInstrInfo *TII) {
20129 unsigned Opc;
20130 switch (MI->getOpcode()) {
20131 default: llvm_unreachable("illegal opcode!");
20132 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20133 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20134 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20135 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20136 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20137 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20138 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20139 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20140 }
20142 DebugLoc dl = MI->getDebugLoc();
20143 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20145 unsigned NumArgs = MI->getNumOperands(); // remove the results
20146 for (unsigned i = 1; i < NumArgs; ++i) {
20147 MachineOperand &Op = MI->getOperand(i);
20148 if (!(Op.isReg() && Op.isImplicit()))
20149 MIB.addOperand(Op);
20150 }
20151 if (MI->hasOneMemOperand())
20152 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20154 BuildMI(*BB, MI, dl,
20155 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20156 .addReg(X86::ECX);
20158 MI->eraseFromParent();
20159 return BB;
20160 }
20162 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20163 const TargetInstrInfo *TII,
20164 const X86Subtarget* Subtarget) {
20165 DebugLoc dl = MI->getDebugLoc();
20167 // Address into RAX/EAX, other two args into ECX, EDX.
20168 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20169 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20170 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20171 for (int i = 0; i < X86::AddrNumOperands; ++i)
20172 MIB.addOperand(MI->getOperand(i));
20174 unsigned ValOps = X86::AddrNumOperands;
20175 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20176 .addReg(MI->getOperand(ValOps).getReg());
20177 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20178 .addReg(MI->getOperand(ValOps+1).getReg());
20180 // The instruction doesn't actually take any operands though.
20181 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20183 MI->eraseFromParent(); // The pseudo is gone now.
20184 return BB;
20185 }
20187 MachineBasicBlock *
20188 X86TargetLowering::EmitVAARG64WithCustomInserter(
20189 MachineInstr *MI,
20190 MachineBasicBlock *MBB) const {
20191 // Emit va_arg instruction on X86-64.
20193 // Operands to this pseudo-instruction:
20194 // 0 ) Output : destination address (reg)
20195 // 1-5) Input : va_list address (addr, i64mem)
20196 // 6 ) ArgSize : Size (in bytes) of vararg type
20197 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20198 // 8 ) Align : Alignment of type
20199 // 9 ) EFLAGS (implicit-def)
20201 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20202 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
20204 unsigned DestReg = MI->getOperand(0).getReg();
20205 MachineOperand &Base = MI->getOperand(1);
20206 MachineOperand &Scale = MI->getOperand(2);
20207 MachineOperand &Index = MI->getOperand(3);
20208 MachineOperand &Disp = MI->getOperand(4);
20209 MachineOperand &Segment = MI->getOperand(5);
20210 unsigned ArgSize = MI->getOperand(6).getImm();
20211 unsigned ArgMode = MI->getOperand(7).getImm();
20212 unsigned Align = MI->getOperand(8).getImm();
20214 // Memory Reference
20215 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20216 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20217 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20219 // Machine Information
20220 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20221 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20222 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20223 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20224 DebugLoc DL = MI->getDebugLoc();
20226 // struct va_list {
20227 // i32 gp_offset
20228 // i32 fp_offset
20229 // i64 overflow_area (address)
20230 // i64 reg_save_area (address)
20231 // }
20232 // sizeof(va_list) = 24
20233 // alignment(va_list) = 8
20235 unsigned TotalNumIntRegs = 6;
20236 unsigned TotalNumXMMRegs = 8;
20237 bool UseGPOffset = (ArgMode == 1);
20238 bool UseFPOffset = (ArgMode == 2);
20239 unsigned MaxOffset = TotalNumIntRegs * 8 +
20240 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20242 /* Align ArgSize to a multiple of 8 */
20243 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20244 bool NeedsAlign = (Align > 8);
20246 MachineBasicBlock *thisMBB = MBB;
20247 MachineBasicBlock *overflowMBB;
20248 MachineBasicBlock *offsetMBB;
20249 MachineBasicBlock *endMBB;
20251 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20252 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20253 unsigned OffsetReg = 0;
20255 if (!UseGPOffset && !UseFPOffset) {
20256 // If we only pull from the overflow region, we don't create a branch.
20257 // We don't need to alter control flow.
20258 OffsetDestReg = 0; // unused
20259 OverflowDestReg = DestReg;
20261 offsetMBB = nullptr;
20262 overflowMBB = thisMBB;
20263 endMBB = thisMBB;
20264 } else {
20265 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20266 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20267 // If not, pull from overflow_area. (branch to overflowMBB)
20268 //
20269 // thisMBB
20270 // | .
20271 // | .
20272 // offsetMBB overflowMBB
20273 // | .
20274 // | .
20275 // endMBB
20277 // Registers for the PHI in endMBB
20278 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20279 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20281 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20282 MachineFunction *MF = MBB->getParent();
20283 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20284 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20285 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20287 MachineFunction::iterator MBBIter = MBB;
20288 ++MBBIter;
20290 // Insert the new basic blocks
20291 MF->insert(MBBIter, offsetMBB);
20292 MF->insert(MBBIter, overflowMBB);
20293 MF->insert(MBBIter, endMBB);
20295 // Transfer the remainder of MBB and its successor edges to endMBB.
20296 endMBB->splice(endMBB->begin(), thisMBB,
20297 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20298 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20300 // Make offsetMBB and overflowMBB successors of thisMBB
20301 thisMBB->addSuccessor(offsetMBB);
20302 thisMBB->addSuccessor(overflowMBB);
20304 // endMBB is a successor of both offsetMBB and overflowMBB
20305 offsetMBB->addSuccessor(endMBB);
20306 overflowMBB->addSuccessor(endMBB);
20308 // Load the offset value into a register
20309 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20310 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20311 .addOperand(Base)
20312 .addOperand(Scale)
20313 .addOperand(Index)
20314 .addDisp(Disp, UseFPOffset ? 4 : 0)
20315 .addOperand(Segment)
20316 .setMemRefs(MMOBegin, MMOEnd);
20318 // Check if there is enough room left to pull this argument.
20319 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20320 .addReg(OffsetReg)
20321 .addImm(MaxOffset + 8 - ArgSizeA8);
20323 // Branch to "overflowMBB" if offset >= max
20324 // Fall through to "offsetMBB" otherwise
20325 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20326 .addMBB(overflowMBB);
20327 }
20329 // In offsetMBB, emit code to use the reg_save_area.
20330 if (offsetMBB) {
20331 assert(OffsetReg != 0);
20333 // Read the reg_save_area address.
20334 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20335 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20336 .addOperand(Base)
20337 .addOperand(Scale)
20338 .addOperand(Index)
20339 .addDisp(Disp, 16)
20340 .addOperand(Segment)
20341 .setMemRefs(MMOBegin, MMOEnd);
20343 // Zero-extend the offset
20344 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20345 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20346 .addImm(0)
20347 .addReg(OffsetReg)
20348 .addImm(X86::sub_32bit);
20350 // Add the offset to the reg_save_area to get the final address.
20351 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20352 .addReg(OffsetReg64)
20353 .addReg(RegSaveReg);
20355 // Compute the offset for the next argument
20356 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20357 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20358 .addReg(OffsetReg)
20359 .addImm(UseFPOffset ? 16 : 8);
20361 // Store it back into the va_list.
20362 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20363 .addOperand(Base)
20364 .addOperand(Scale)
20365 .addOperand(Index)
20366 .addDisp(Disp, UseFPOffset ? 4 : 0)
20367 .addOperand(Segment)
20368 .addReg(NextOffsetReg)
20369 .setMemRefs(MMOBegin, MMOEnd);
20371 // Jump to endMBB
20372 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
20373 .addMBB(endMBB);
20374 }
20376 //
20377 // Emit code to use overflow area
20378 //
20380 // Load the overflow_area address into a register.
20381 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20382 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20383 .addOperand(Base)
20384 .addOperand(Scale)
20385 .addOperand(Index)
20386 .addDisp(Disp, 8)
20387 .addOperand(Segment)
20388 .setMemRefs(MMOBegin, MMOEnd);
20390 // If we need to align it, do so. Otherwise, just copy the address
20391 // to OverflowDestReg.
20392 if (NeedsAlign) {
20393 // Align the overflow address
20394 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20395 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20397 // aligned_addr = (addr + (align-1)) & ~(align-1)
20398 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20399 .addReg(OverflowAddrReg)
20400 .addImm(Align-1);
20402 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20403 .addReg(TmpReg)
20404 .addImm(~(uint64_t)(Align-1));
20405 } else {
20406 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20407 .addReg(OverflowAddrReg);
20408 }
20410 // Compute the next overflow address after this argument.
20411 // (the overflow address should be kept 8-byte aligned)
20412 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20413 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20414 .addReg(OverflowDestReg)
20415 .addImm(ArgSizeA8);
20417 // Store the new overflow address.
20418 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20419 .addOperand(Base)
20420 .addOperand(Scale)
20421 .addOperand(Index)
20422 .addDisp(Disp, 8)
20423 .addOperand(Segment)
20424 .addReg(NextAddrReg)
20425 .setMemRefs(MMOBegin, MMOEnd);
20427 // If we branched, emit the PHI to the front of endMBB.
20428 if (offsetMBB) {
20429 BuildMI(*endMBB, endMBB->begin(), DL,
20430 TII->get(X86::PHI), DestReg)
20431 .addReg(OffsetDestReg).addMBB(offsetMBB)
20432 .addReg(OverflowDestReg).addMBB(overflowMBB);
20433 }
20435 // Erase the pseudo instruction
20436 MI->eraseFromParent();
20438 return endMBB;
20439 }
20441 MachineBasicBlock *
20442 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20443 MachineInstr *MI,
20444 MachineBasicBlock *MBB) const {
20445 // Emit code to save XMM registers to the stack. The ABI says that the
20446 // number of registers to save is given in %al, so it's theoretically
20447 // possible to do an indirect jump trick to avoid saving all of them,
20448 // however this code takes a simpler approach and just executes all
20449 // of the stores if %al is non-zero. It's less code, and it's probably
20450 // easier on the hardware branch predictor, and stores aren't all that
20451 // expensive anyway.
20453 // Create the new basic blocks. One block contains all the XMM stores,
20454 // and one block is the final destination regardless of whether any
20455 // stores were performed.
20456 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20457 MachineFunction *F = MBB->getParent();
20458 MachineFunction::iterator MBBIter = MBB;
20459 ++MBBIter;
20460 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20461 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20462 F->insert(MBBIter, XMMSaveMBB);
20463 F->insert(MBBIter, EndMBB);
20465 // Transfer the remainder of MBB and its successor edges to EndMBB.
20466 EndMBB->splice(EndMBB->begin(), MBB,
20467 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20468 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20470 // The original block will now fall through to the XMM save block.
20471 MBB->addSuccessor(XMMSaveMBB);
20472 // The XMMSaveMBB will fall through to the end block.
20473 XMMSaveMBB->addSuccessor(EndMBB);
20475 // Now add the instructions.
20476 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20477 DebugLoc DL = MI->getDebugLoc();
20479 unsigned CountReg = MI->getOperand(0).getReg();
20480 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20481 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20483 if (!Subtarget->isTargetWin64()) {
20484 // If %al is 0, branch around the XMM save block.
20485 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20486 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
20487 MBB->addSuccessor(EndMBB);
20488 }
20490 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20491 // that was just emitted, but clearly shouldn't be "saved".
20492 assert((MI->getNumOperands() <= 3 ||
20493 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20494 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20495 && "Expected last argument to be EFLAGS");
20496 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20497 // In the XMM save block, save all the XMM argument registers.
20498 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20499 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20500 MachineMemOperand *MMO =
20501 F->getMachineMemOperand(
20502 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
20503 MachineMemOperand::MOStore,
20504 /*Size=*/16, /*Align=*/16);
20505 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20506 .addFrameIndex(RegSaveFrameIndex)
20507 .addImm(/*Scale=*/1)
20508 .addReg(/*IndexReg=*/0)
20509 .addImm(/*Disp=*/Offset)
20510 .addReg(/*Segment=*/0)
20511 .addReg(MI->getOperand(i).getReg())
20512 .addMemOperand(MMO);
20513 }
20515 MI->eraseFromParent(); // The pseudo instruction is gone now.
20517 return EndMBB;
20518 }
20520 // The EFLAGS operand of SelectItr might be missing a kill marker
20521 // because there were multiple uses of EFLAGS, and ISel didn't know
20522 // which to mark. Figure out whether SelectItr should have had a
20523 // kill marker, and set it if it should. Returns the correct kill
20524 // marker value.
20525 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20526 MachineBasicBlock* BB,
20527 const TargetRegisterInfo* TRI) {
20528 // Scan forward through BB for a use/def of EFLAGS.
20529 MachineBasicBlock::iterator miI(std::next(SelectItr));
20530 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20531 const MachineInstr& mi = *miI;
20532 if (mi.readsRegister(X86::EFLAGS))
20533 return false;
20534 if (mi.definesRegister(X86::EFLAGS))
20535 break; // Should have kill-flag - update below.
20536 }
20538 // If we hit the end of the block, check whether EFLAGS is live into a
20539 // successor.
20540 if (miI == BB->end()) {
20541 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20542 sEnd = BB->succ_end();
20543 sItr != sEnd; ++sItr) {
20544 MachineBasicBlock* succ = *sItr;
20545 if (succ->isLiveIn(X86::EFLAGS))
20546 return false;
20547 }
20548 }
20550 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20551 // out. SelectMI should have a kill flag on EFLAGS.
20552 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20553 return true;
20554 }
20556 MachineBasicBlock *
20557 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20558 MachineBasicBlock *BB) const {
20559 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20560 DebugLoc DL = MI->getDebugLoc();
20562 // To "insert" a SELECT_CC instruction, we actually have to insert the
20563 // diamond control-flow pattern. The incoming instruction knows the
20564 // destination vreg to set, the condition code register to branch on, the
20565 // true/false values to select between, and a branch opcode to use.
20566 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20567 MachineFunction::iterator It = BB;
20568 ++It;
20570 // thisMBB:
20571 // ...
20572 // TrueVal = ...
20573 // cmpTY ccX, r1, r2
20574 // bCC copy1MBB
20575 // fallthrough --> copy0MBB
20576 MachineBasicBlock *thisMBB = BB;
20577 MachineFunction *F = BB->getParent();
20578 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
20579 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
20580 F->insert(It, copy0MBB);
20581 F->insert(It, sinkMBB);
20583 // If the EFLAGS register isn't dead in the terminator, then claim that it's
20584 // live into the sink and copy blocks.
20585 const TargetRegisterInfo *TRI =
20586 BB->getParent()->getSubtarget().getRegisterInfo();
20587 if (!MI->killsRegister(X86::EFLAGS) &&
20588 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
20589 copy0MBB->addLiveIn(X86::EFLAGS);
20590 sinkMBB->addLiveIn(X86::EFLAGS);
20591 }
20593 // Transfer the remainder of BB and its successor edges to sinkMBB.
20594 sinkMBB->splice(sinkMBB->begin(), BB,
20595 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20596 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
20598 // Add the true and fallthrough blocks as its successors.
20599 BB->addSuccessor(copy0MBB);
20600 BB->addSuccessor(sinkMBB);
20602 // Create the conditional branch instruction.
20603 unsigned Opc =
20604 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
20605 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
20607 // copy0MBB:
20608 // %FalseValue = ...
20609 // # fallthrough to sinkMBB
20610 copy0MBB->addSuccessor(sinkMBB);
20612 // sinkMBB:
20613 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
20614 // ...
20615 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20616 TII->get(X86::PHI), MI->getOperand(0).getReg())
20617 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
20618 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
20620 MI->eraseFromParent(); // The pseudo instruction is gone now.
20621 return sinkMBB;
20622 }
20624 MachineBasicBlock *
20625 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
20626 MachineBasicBlock *BB) const {
20627 MachineFunction *MF = BB->getParent();
20628 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20629 DebugLoc DL = MI->getDebugLoc();
20630 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20632 assert(MF->shouldSplitStack());
20634 const bool Is64Bit = Subtarget->is64Bit();
20635 const bool IsLP64 = Subtarget->isTarget64BitLP64();
20637 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
20638 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
20640 // BB:
20641 // ... [Till the alloca]
20642 // If stacklet is not large enough, jump to mallocMBB
20643 //
20644 // bumpMBB:
20645 // Allocate by subtracting from RSP
20646 // Jump to continueMBB
20647 //
20648 // mallocMBB:
20649 // Allocate by call to runtime
20650 //
20651 // continueMBB:
20652 // ...
20653 // [rest of original BB]
20654 //
20656 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20657 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20658 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20660 MachineRegisterInfo &MRI = MF->getRegInfo();
20661 const TargetRegisterClass *AddrRegClass =
20662 getRegClassFor(getPointerTy());
20664 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20665 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20666 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
20667 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
20668 sizeVReg = MI->getOperand(1).getReg(),
20669 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
20671 MachineFunction::iterator MBBIter = BB;
20672 ++MBBIter;
20674 MF->insert(MBBIter, bumpMBB);
20675 MF->insert(MBBIter, mallocMBB);
20676 MF->insert(MBBIter, continueMBB);
20678 continueMBB->splice(continueMBB->begin(), BB,
20679 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20680 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
20682 // Add code to the main basic block to check if the stack limit has been hit,
20683 // and if so, jump to mallocMBB otherwise to bumpMBB.
20684 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
20685 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
20686 .addReg(tmpSPVReg).addReg(sizeVReg);
20687 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
20688 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
20689 .addReg(SPLimitVReg);
20690 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
20692 // bumpMBB simply decreases the stack pointer, since we know the current
20693 // stacklet has enough space.
20694 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
20695 .addReg(SPLimitVReg);
20696 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
20697 .addReg(SPLimitVReg);
20698 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20700 // Calls into a routine in libgcc to allocate more space from the heap.
20701 const uint32_t *RegMask = MF->getTarget()
20702 .getSubtargetImpl()
20703 ->getRegisterInfo()
20704 ->getCallPreservedMask(CallingConv::C);
20705 if (IsLP64) {
20706 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
20707 .addReg(sizeVReg);
20708 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20709 .addExternalSymbol("__morestack_allocate_stack_space")
20710 .addRegMask(RegMask)
20711 .addReg(X86::RDI, RegState::Implicit)
20712 .addReg(X86::RAX, RegState::ImplicitDefine);
20713 } else if (Is64Bit) {
20714 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
20715 .addReg(sizeVReg);
20716 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20717 .addExternalSymbol("__morestack_allocate_stack_space")
20718 .addRegMask(RegMask)
20719 .addReg(X86::EDI, RegState::Implicit)
20720 .addReg(X86::EAX, RegState::ImplicitDefine);
20721 } else {
20722 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
20723 .addImm(12);
20724 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
20725 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
20726 .addExternalSymbol("__morestack_allocate_stack_space")
20727 .addRegMask(RegMask)
20728 .addReg(X86::EAX, RegState::ImplicitDefine);
20729 }
20731 if (!Is64Bit)
20732 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
20733 .addImm(16);
20735 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
20736 .addReg(IsLP64 ? X86::RAX : X86::EAX);
20737 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20739 // Set up the CFG correctly.
20740 BB->addSuccessor(bumpMBB);
20741 BB->addSuccessor(mallocMBB);
20742 mallocMBB->addSuccessor(continueMBB);
20743 bumpMBB->addSuccessor(continueMBB);
20745 // Take care of the PHI nodes.
20746 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
20747 MI->getOperand(0).getReg())
20748 .addReg(mallocPtrVReg).addMBB(mallocMBB)
20749 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
20751 // Delete the original pseudo instruction.
20752 MI->eraseFromParent();
20754 // And we're done.
20755 return continueMBB;
20756 }
20758 MachineBasicBlock *
20759 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
20760 MachineBasicBlock *BB) const {
20761 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20762 DebugLoc DL = MI->getDebugLoc();
20764 assert(!Subtarget->isTargetMachO());
20766 // The lowering is pretty easy: we're just emitting the call to _alloca. The
20767 // non-trivial part is impdef of ESP.
20769 if (Subtarget->isTargetWin64()) {
20770 if (Subtarget->isTargetCygMing()) {
20771 // ___chkstk(Mingw64):
20772 // Clobbers R10, R11, RAX and EFLAGS.
20773 // Updates RSP.
20774 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20775 .addExternalSymbol("___chkstk")
20776 .addReg(X86::RAX, RegState::Implicit)
20777 .addReg(X86::RSP, RegState::Implicit)
20778 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
20779 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
20780 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20781 } else {
20782 // __chkstk(MSVCRT): does not update stack pointer.
20783 // Clobbers R10, R11 and EFLAGS.
20784 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20785 .addExternalSymbol("__chkstk")
20786 .addReg(X86::RAX, RegState::Implicit)
20787 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20788 // RAX has the offset to be subtracted from RSP.
20789 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
20790 .addReg(X86::RSP)
20791 .addReg(X86::RAX);
20792 }
20793 } else {
20794 const char *StackProbeSymbol = (Subtarget->isTargetKnownWindowsMSVC() ||
20795 Subtarget->isTargetWindowsItanium())
20796 ? "_chkstk"
20797 : "_alloca";
20799 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
20800 .addExternalSymbol(StackProbeSymbol)
20801 .addReg(X86::EAX, RegState::Implicit)
20802 .addReg(X86::ESP, RegState::Implicit)
20803 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
20804 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
20805 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20806 }
20808 MI->eraseFromParent(); // The pseudo instruction is gone now.
20809 return BB;
20810 }
20812 MachineBasicBlock *
20813 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
20814 MachineBasicBlock *BB) const {
20815 // This is pretty easy. We're taking the value that we received from
20816 // our load from the relocation, sticking it in either RDI (x86-64)
20817 // or EAX and doing an indirect call. The return value will then
20818 // be in the normal return register.
20819 MachineFunction *F = BB->getParent();
20820 const X86InstrInfo *TII =
20821 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
20822 DebugLoc DL = MI->getDebugLoc();
20824 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
20825 assert(MI->getOperand(3).isGlobal() && "This should be a global");
20827 // Get a register mask for the lowered call.
20828 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
20829 // proper register mask.
20830 const uint32_t *RegMask = F->getTarget()
20831 .getSubtargetImpl()
20832 ->getRegisterInfo()
20833 ->getCallPreservedMask(CallingConv::C);
20834 if (Subtarget->is64Bit()) {
20835 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20836 TII->get(X86::MOV64rm), X86::RDI)
20837 .addReg(X86::RIP)
20838 .addImm(0).addReg(0)
20839 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20840 MI->getOperand(3).getTargetFlags())
20841 .addReg(0);
20842 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
20843 addDirectMem(MIB, X86::RDI);
20844 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
20845 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
20846 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20847 TII->get(X86::MOV32rm), X86::EAX)
20848 .addReg(0)
20849 .addImm(0).addReg(0)
20850 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20851 MI->getOperand(3).getTargetFlags())
20852 .addReg(0);
20853 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20854 addDirectMem(MIB, X86::EAX);
20855 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20856 } else {
20857 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20858 TII->get(X86::MOV32rm), X86::EAX)
20859 .addReg(TII->getGlobalBaseReg(F))
20860 .addImm(0).addReg(0)
20861 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20862 MI->getOperand(3).getTargetFlags())
20863 .addReg(0);
20864 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20865 addDirectMem(MIB, X86::EAX);
20866 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20867 }
20869 MI->eraseFromParent(); // The pseudo instruction is gone now.
20870 return BB;
20871 }
20873 MachineBasicBlock *
20874 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
20875 MachineBasicBlock *MBB) const {
20876 DebugLoc DL = MI->getDebugLoc();
20877 MachineFunction *MF = MBB->getParent();
20878 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20879 MachineRegisterInfo &MRI = MF->getRegInfo();
20881 const BasicBlock *BB = MBB->getBasicBlock();
20882 MachineFunction::iterator I = MBB;
20883 ++I;
20885 // Memory Reference
20886 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20887 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20889 unsigned DstReg;
20890 unsigned MemOpndSlot = 0;
20892 unsigned CurOp = 0;
20894 DstReg = MI->getOperand(CurOp++).getReg();
20895 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
20896 assert(RC->hasType(MVT::i32) && "Invalid destination!");
20897 unsigned mainDstReg = MRI.createVirtualRegister(RC);
20898 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
20900 MemOpndSlot = CurOp;
20902 MVT PVT = getPointerTy();
20903 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20904 "Invalid Pointer Size!");
20906 // For v = setjmp(buf), we generate
20907 //
20908 // thisMBB:
20909 // buf[LabelOffset] = restoreMBB
20910 // SjLjSetup restoreMBB
20911 //
20912 // mainMBB:
20913 // v_main = 0
20914 //
20915 // sinkMBB:
20916 // v = phi(main, restore)
20917 //
20918 // restoreMBB:
20919 // if base pointer being used, load it from frame
20920 // v_restore = 1
20922 MachineBasicBlock *thisMBB = MBB;
20923 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20924 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20925 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
20926 MF->insert(I, mainMBB);
20927 MF->insert(I, sinkMBB);
20928 MF->push_back(restoreMBB);
20930 MachineInstrBuilder MIB;
20932 // Transfer the remainder of BB and its successor edges to sinkMBB.
20933 sinkMBB->splice(sinkMBB->begin(), MBB,
20934 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20935 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20937 // thisMBB:
20938 unsigned PtrStoreOpc = 0;
20939 unsigned LabelReg = 0;
20940 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20941 Reloc::Model RM = MF->getTarget().getRelocationModel();
20942 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
20943 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
20945 // Prepare IP either in reg or imm.
20946 if (!UseImmLabel) {
20947 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
20948 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
20949 LabelReg = MRI.createVirtualRegister(PtrRC);
20950 if (Subtarget->is64Bit()) {
20951 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
20952 .addReg(X86::RIP)
20953 .addImm(0)
20954 .addReg(0)
20955 .addMBB(restoreMBB)
20956 .addReg(0);
20957 } else {
20958 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
20959 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
20960 .addReg(XII->getGlobalBaseReg(MF))
20961 .addImm(0)
20962 .addReg(0)
20963 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
20964 .addReg(0);
20965 }
20966 } else
20967 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
20968 // Store IP
20969 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
20970 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20971 if (i == X86::AddrDisp)
20972 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
20973 else
20974 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
20975 }
20976 if (!UseImmLabel)
20977 MIB.addReg(LabelReg);
20978 else
20979 MIB.addMBB(restoreMBB);
20980 MIB.setMemRefs(MMOBegin, MMOEnd);
20981 // Setup
20982 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
20983 .addMBB(restoreMBB);
20985 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20986 MF->getSubtarget().getRegisterInfo());
20987 MIB.addRegMask(RegInfo->getNoPreservedMask());
20988 thisMBB->addSuccessor(mainMBB);
20989 thisMBB->addSuccessor(restoreMBB);
20991 // mainMBB:
20992 // EAX = 0
20993 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
20994 mainMBB->addSuccessor(sinkMBB);
20996 // sinkMBB:
20997 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20998 TII->get(X86::PHI), DstReg)
20999 .addReg(mainDstReg).addMBB(mainMBB)
21000 .addReg(restoreDstReg).addMBB(restoreMBB);
21002 // restoreMBB:
21003 if (RegInfo->hasBasePointer(*MF)) {
21004 const X86Subtarget &STI = MF->getTarget().getSubtarget<X86Subtarget>();
21005 const bool Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64();
21006 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
21007 X86FI->setRestoreBasePointer(MF);
21008 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
21009 unsigned BasePtr = RegInfo->getBaseRegister();
21010 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
21011 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
21012 FramePtr, true, X86FI->getRestoreBasePointerOffset())
21013 .setMIFlag(MachineInstr::FrameSetup);
21014 }
21015 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
21016 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
21017 restoreMBB->addSuccessor(sinkMBB);
21019 MI->eraseFromParent();
21020 return sinkMBB;
21021 }
21023 MachineBasicBlock *
21024 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
21025 MachineBasicBlock *MBB) const {
21026 DebugLoc DL = MI->getDebugLoc();
21027 MachineFunction *MF = MBB->getParent();
21028 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
21029 MachineRegisterInfo &MRI = MF->getRegInfo();
21031 // Memory Reference
21032 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21033 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21035 MVT PVT = getPointerTy();
21036 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21037 "Invalid Pointer Size!");
21039 const TargetRegisterClass *RC =
21040 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
21041 unsigned Tmp = MRI.createVirtualRegister(RC);
21042 // Since FP is only updated here but NOT referenced, it's treated as GPR.
21043 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
21044 MF->getSubtarget().getRegisterInfo());
21045 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
21046 unsigned SP = RegInfo->getStackRegister();
21048 MachineInstrBuilder MIB;
21050 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21051 const int64_t SPOffset = 2 * PVT.getStoreSize();
21053 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
21054 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
21056 // Reload FP
21057 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
21058 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
21059 MIB.addOperand(MI->getOperand(i));
21060 MIB.setMemRefs(MMOBegin, MMOEnd);
21061 // Reload IP
21062 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
21063 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21064 if (i == X86::AddrDisp)
21065 MIB.addDisp(MI->getOperand(i), LabelOffset);
21066 else
21067 MIB.addOperand(MI->getOperand(i));
21068 }
21069 MIB.setMemRefs(MMOBegin, MMOEnd);
21070 // Reload SP
21071 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
21072 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21073 if (i == X86::AddrDisp)
21074 MIB.addDisp(MI->getOperand(i), SPOffset);
21075 else
21076 MIB.addOperand(MI->getOperand(i));
21077 }
21078 MIB.setMemRefs(MMOBegin, MMOEnd);
21079 // Jump
21080 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
21082 MI->eraseFromParent();
21083 return MBB;
21084 }
21086 // Replace 213-type (isel default) FMA3 instructions with 231-type for
21087 // accumulator loops. Writing back to the accumulator allows the coalescer
21088 // to remove extra copies in the loop.
21089 MachineBasicBlock *
21090 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
21091 MachineBasicBlock *MBB) const {
21092 MachineOperand &AddendOp = MI->getOperand(3);
21094 // Bail out early if the addend isn't a register - we can't switch these.
21095 if (!AddendOp.isReg())
21096 return MBB;
21098 MachineFunction &MF = *MBB->getParent();
21099 MachineRegisterInfo &MRI = MF.getRegInfo();
21101 // Check whether the addend is defined by a PHI:
21102 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
21103 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
21104 if (!AddendDef.isPHI())
21105 return MBB;
21107 // Look for the following pattern:
21108 // loop:
21109 // %addend = phi [%entry, 0], [%loop, %result]
21110 // ...
21111 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
21113 // Replace with:
21114 // loop:
21115 // %addend = phi [%entry, 0], [%loop, %result]
21116 // ...
21117 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
21119 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
21120 assert(AddendDef.getOperand(i).isReg());
21121 MachineOperand PHISrcOp = AddendDef.getOperand(i);
21122 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
21123 if (&PHISrcInst == MI) {
21124 // Found a matching instruction.
21125 unsigned NewFMAOpc = 0;
21126 switch (MI->getOpcode()) {
21127 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
21128 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
21129 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
21130 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
21131 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
21132 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
21133 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
21134 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
21135 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
21136 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
21137 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
21138 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
21139 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
21140 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
21141 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
21142 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
21143 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
21144 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
21145 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
21146 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
21148 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
21149 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
21150 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
21151 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
21152 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
21153 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
21154 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
21155 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
21156 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
21157 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
21158 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
21159 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
21160 default: llvm_unreachable("Unrecognized FMA variant.");
21161 }
21163 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
21164 MachineInstrBuilder MIB =
21165 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
21166 .addOperand(MI->getOperand(0))
21167 .addOperand(MI->getOperand(3))
21168 .addOperand(MI->getOperand(2))
21169 .addOperand(MI->getOperand(1));
21170 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
21171 MI->eraseFromParent();
21172 }
21173 }
21175 return MBB;
21176 }
21178 MachineBasicBlock *
21179 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
21180 MachineBasicBlock *BB) const {
21181 switch (MI->getOpcode()) {
21182 default: llvm_unreachable("Unexpected instr type to insert");
21183 case X86::TAILJMPd64:
21184 case X86::TAILJMPr64:
21185 case X86::TAILJMPm64:
21186 llvm_unreachable("TAILJMP64 would not be touched here.");
21187 case X86::TCRETURNdi64:
21188 case X86::TCRETURNri64:
21189 case X86::TCRETURNmi64:
21190 return BB;
21191 case X86::WIN_ALLOCA:
21192 return EmitLoweredWinAlloca(MI, BB);
21193 case X86::SEG_ALLOCA_32:
21194 case X86::SEG_ALLOCA_64:
21195 return EmitLoweredSegAlloca(MI, BB);
21196 case X86::TLSCall_32:
21197 case X86::TLSCall_64:
21198 return EmitLoweredTLSCall(MI, BB);
21199 case X86::CMOV_GR8:
21200 case X86::CMOV_FR32:
21201 case X86::CMOV_FR64:
21202 case X86::CMOV_V4F32:
21203 case X86::CMOV_V2F64:
21204 case X86::CMOV_V2I64:
21205 case X86::CMOV_V8F32:
21206 case X86::CMOV_V4F64:
21207 case X86::CMOV_V4I64:
21208 case X86::CMOV_V16F32:
21209 case X86::CMOV_V8F64:
21210 case X86::CMOV_V8I64:
21211 case X86::CMOV_GR16:
21212 case X86::CMOV_GR32:
21213 case X86::CMOV_RFP32:
21214 case X86::CMOV_RFP64:
21215 case X86::CMOV_RFP80:
21216 return EmitLoweredSelect(MI, BB);
21218 case X86::FP32_TO_INT16_IN_MEM:
21219 case X86::FP32_TO_INT32_IN_MEM:
21220 case X86::FP32_TO_INT64_IN_MEM:
21221 case X86::FP64_TO_INT16_IN_MEM:
21222 case X86::FP64_TO_INT32_IN_MEM:
21223 case X86::FP64_TO_INT64_IN_MEM:
21224 case X86::FP80_TO_INT16_IN_MEM:
21225 case X86::FP80_TO_INT32_IN_MEM:
21226 case X86::FP80_TO_INT64_IN_MEM: {
21227 MachineFunction *F = BB->getParent();
21228 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
21229 DebugLoc DL = MI->getDebugLoc();
21231 // Change the floating point control register to use "round towards zero"
21232 // mode when truncating to an integer value.
21233 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
21234 addFrameReference(BuildMI(*BB, MI, DL,
21235 TII->get(X86::FNSTCW16m)), CWFrameIdx);
21237 // Load the old value of the high byte of the control word...
21238 unsigned OldCW =
21239 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
21240 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
21241 CWFrameIdx);
21243 // Set the high part to be round to zero...
21244 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
21245 .addImm(0xC7F);
21247 // Reload the modified control word now...
21248 addFrameReference(BuildMI(*BB, MI, DL,
21249 TII->get(X86::FLDCW16m)), CWFrameIdx);
21251 // Restore the memory image of control word to original value
21252 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
21253 .addReg(OldCW);
21255 // Get the X86 opcode to use.
21256 unsigned Opc;
21257 switch (MI->getOpcode()) {
21258 default: llvm_unreachable("illegal opcode!");
21259 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
21260 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
21261 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
21262 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
21263 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
21264 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
21265 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
21266 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
21267 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
21268 }
21270 X86AddressMode AM;
21271 MachineOperand &Op = MI->getOperand(0);
21272 if (Op.isReg()) {
21273 AM.BaseType = X86AddressMode::RegBase;
21274 AM.Base.Reg = Op.getReg();
21275 } else {
21276 AM.BaseType = X86AddressMode::FrameIndexBase;
21277 AM.Base.FrameIndex = Op.getIndex();
21278 }
21279 Op = MI->getOperand(1);
21280 if (Op.isImm())
21281 AM.Scale = Op.getImm();
21282 Op = MI->getOperand(2);
21283 if (Op.isImm())
21284 AM.IndexReg = Op.getImm();
21285 Op = MI->getOperand(3);
21286 if (Op.isGlobal()) {
21287 AM.GV = Op.getGlobal();
21288 } else {
21289 AM.Disp = Op.getImm();
21290 }
21291 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
21292 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
21294 // Reload the original control word now.
21295 addFrameReference(BuildMI(*BB, MI, DL,
21296 TII->get(X86::FLDCW16m)), CWFrameIdx);
21298 MI->eraseFromParent(); // The pseudo instruction is gone now.
21299 return BB;
21300 }
21301 // String/text processing lowering.
21302 case X86::PCMPISTRM128REG:
21303 case X86::VPCMPISTRM128REG:
21304 case X86::PCMPISTRM128MEM:
21305 case X86::VPCMPISTRM128MEM:
21306 case X86::PCMPESTRM128REG:
21307 case X86::VPCMPESTRM128REG:
21308 case X86::PCMPESTRM128MEM:
21309 case X86::VPCMPESTRM128MEM:
21310 assert(Subtarget->hasSSE42() &&
21311 "Target must have SSE4.2 or AVX features enabled");
21312 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21314 // String/text processing lowering.
21315 case X86::PCMPISTRIREG:
21316 case X86::VPCMPISTRIREG:
21317 case X86::PCMPISTRIMEM:
21318 case X86::VPCMPISTRIMEM:
21319 case X86::PCMPESTRIREG:
21320 case X86::VPCMPESTRIREG:
21321 case X86::PCMPESTRIMEM:
21322 case X86::VPCMPESTRIMEM:
21323 assert(Subtarget->hasSSE42() &&
21324 "Target must have SSE4.2 or AVX features enabled");
21325 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21327 // Thread synchronization.
21328 case X86::MONITOR:
21329 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
21330 Subtarget);
21332 // xbegin
21333 case X86::XBEGIN:
21334 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21336 case X86::VASTART_SAVE_XMM_REGS:
21337 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
21339 case X86::VAARG_64:
21340 return EmitVAARG64WithCustomInserter(MI, BB);
21342 case X86::EH_SjLj_SetJmp32:
21343 case X86::EH_SjLj_SetJmp64:
21344 return emitEHSjLjSetJmp(MI, BB);
21346 case X86::EH_SjLj_LongJmp32:
21347 case X86::EH_SjLj_LongJmp64:
21348 return emitEHSjLjLongJmp(MI, BB);
21350 case TargetOpcode::STATEPOINT:
21351 // As an implementation detail, STATEPOINT shares the STACKMAP format at
21352 // this point in the process. We diverge later.
21353 return emitPatchPoint(MI, BB);
21355 case TargetOpcode::STACKMAP:
21356 case TargetOpcode::PATCHPOINT:
21357 return emitPatchPoint(MI, BB);
21359 case X86::VFMADDPDr213r:
21360 case X86::VFMADDPSr213r:
21361 case X86::VFMADDSDr213r:
21362 case X86::VFMADDSSr213r:
21363 case X86::VFMSUBPDr213r:
21364 case X86::VFMSUBPSr213r:
21365 case X86::VFMSUBSDr213r:
21366 case X86::VFMSUBSSr213r:
21367 case X86::VFNMADDPDr213r:
21368 case X86::VFNMADDPSr213r:
21369 case X86::VFNMADDSDr213r:
21370 case X86::VFNMADDSSr213r:
21371 case X86::VFNMSUBPDr213r:
21372 case X86::VFNMSUBPSr213r:
21373 case X86::VFNMSUBSDr213r:
21374 case X86::VFNMSUBSSr213r:
21375 case X86::VFMADDSUBPDr213r:
21376 case X86::VFMADDSUBPSr213r:
21377 case X86::VFMSUBADDPDr213r:
21378 case X86::VFMSUBADDPSr213r:
21379 case X86::VFMADDPDr213rY:
21380 case X86::VFMADDPSr213rY:
21381 case X86::VFMSUBPDr213rY:
21382 case X86::VFMSUBPSr213rY:
21383 case X86::VFNMADDPDr213rY:
21384 case X86::VFNMADDPSr213rY:
21385 case X86::VFNMSUBPDr213rY:
21386 case X86::VFNMSUBPSr213rY:
21387 case X86::VFMADDSUBPDr213rY:
21388 case X86::VFMADDSUBPSr213rY:
21389 case X86::VFMSUBADDPDr213rY:
21390 case X86::VFMSUBADDPSr213rY:
21391 return emitFMA3Instr(MI, BB);
21392 }
21393 }
21395 //===----------------------------------------------------------------------===//
21396 // X86 Optimization Hooks
21397 //===----------------------------------------------------------------------===//
21399 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
21400 APInt &KnownZero,
21401 APInt &KnownOne,
21402 const SelectionDAG &DAG,
21403 unsigned Depth) const {
21404 unsigned BitWidth = KnownZero.getBitWidth();
21405 unsigned Opc = Op.getOpcode();
21406 assert((Opc >= ISD::BUILTIN_OP_END ||
21407 Opc == ISD::INTRINSIC_WO_CHAIN ||
21408 Opc == ISD::INTRINSIC_W_CHAIN ||
21409 Opc == ISD::INTRINSIC_VOID) &&
21410 "Should use MaskedValueIsZero if you don't know whether Op"
21411 " is a target node!");
21413 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
21414 switch (Opc) {
21415 default: break;
21416 case X86ISD::ADD:
21417 case X86ISD::SUB:
21418 case X86ISD::ADC:
21419 case X86ISD::SBB:
21420 case X86ISD::SMUL:
21421 case X86ISD::UMUL:
21422 case X86ISD::INC:
21423 case X86ISD::DEC:
21424 case X86ISD::OR:
21425 case X86ISD::XOR:
21426 case X86ISD::AND:
21427 // These nodes' second result is a boolean.
21428 if (Op.getResNo() == 0)
21429 break;
21430 // Fallthrough
21431 case X86ISD::SETCC:
21432 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
21433 break;
21434 case ISD::INTRINSIC_WO_CHAIN: {
21435 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
21436 unsigned NumLoBits = 0;
21437 switch (IntId) {
21438 default: break;
21439 case Intrinsic::x86_sse_movmsk_ps:
21440 case Intrinsic::x86_avx_movmsk_ps_256:
21441 case Intrinsic::x86_sse2_movmsk_pd:
21442 case Intrinsic::x86_avx_movmsk_pd_256:
21443 case Intrinsic::x86_mmx_pmovmskb:
21444 case Intrinsic::x86_sse2_pmovmskb_128:
21445 case Intrinsic::x86_avx2_pmovmskb: {
21446 // High bits of movmskp{s|d}, pmovmskb are known zero.
21447 switch (IntId) {
21448 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
21449 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
21450 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
21451 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
21452 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
21453 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
21454 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
21455 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
21456 }
21457 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
21458 break;
21459 }
21460 }
21461 break;
21462 }
21463 }
21464 }
21466 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
21467 SDValue Op,
21468 const SelectionDAG &,
21469 unsigned Depth) const {
21470 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
21471 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
21472 return Op.getValueType().getScalarType().getSizeInBits();
21474 // Fallback case.
21475 return 1;
21476 }
21478 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
21479 /// node is a GlobalAddress + offset.
21480 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
21481 const GlobalValue* &GA,
21482 int64_t &Offset) const {
21483 if (N->getOpcode() == X86ISD::Wrapper) {
21484 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
21485 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
21486 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
21487 return true;
21488 }
21489 }
21490 return TargetLowering::isGAPlusOffset(N, GA, Offset);
21491 }
21493 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
21494 /// same as extracting the high 128-bit part of 256-bit vector and then
21495 /// inserting the result into the low part of a new 256-bit vector
21496 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
21497 EVT VT = SVOp->getValueType(0);
21498 unsigned NumElems = VT.getVectorNumElements();
21500 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21501 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
21502 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21503 SVOp->getMaskElt(j) >= 0)
21504 return false;
21506 return true;
21507 }
21509 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
21510 /// same as extracting the low 128-bit part of 256-bit vector and then
21511 /// inserting the result into the high part of a new 256-bit vector
21512 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
21513 EVT VT = SVOp->getValueType(0);
21514 unsigned NumElems = VT.getVectorNumElements();
21516 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21517 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
21518 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21519 SVOp->getMaskElt(j) >= 0)
21520 return false;
21522 return true;
21523 }
21525 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
21526 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
21527 TargetLowering::DAGCombinerInfo &DCI,
21528 const X86Subtarget* Subtarget) {
21529 SDLoc dl(N);
21530 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21531 SDValue V1 = SVOp->getOperand(0);
21532 SDValue V2 = SVOp->getOperand(1);
21533 EVT VT = SVOp->getValueType(0);
21534 unsigned NumElems = VT.getVectorNumElements();
21536 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
21537 V2.getOpcode() == ISD::CONCAT_VECTORS) {
21538 //
21539 // 0,0,0,...
21540 // |
21541 // V UNDEF BUILD_VECTOR UNDEF
21542 // \ / \ /
21543 // CONCAT_VECTOR CONCAT_VECTOR
21544 // \ /
21545 // \ /
21546 // RESULT: V + zero extended
21547 //
21548 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
21549 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
21550 V1.getOperand(1).getOpcode() != ISD::UNDEF)
21551 return SDValue();
21553 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
21554 return SDValue();
21556 // To match the shuffle mask, the first half of the mask should
21557 // be exactly the first vector, and all the rest a splat with the
21558 // first element of the second one.
21559 for (unsigned i = 0; i != NumElems/2; ++i)
21560 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
21561 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
21562 return SDValue();
21564 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
21565 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
21566 if (Ld->hasNUsesOfValue(1, 0)) {
21567 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
21568 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
21569 SDValue ResNode =
21570 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
21571 Ld->getMemoryVT(),
21572 Ld->getPointerInfo(),
21573 Ld->getAlignment(),
21574 false/*isVolatile*/, true/*ReadMem*/,
21575 false/*WriteMem*/);
21577 // Make sure the newly-created LOAD is in the same position as Ld in
21578 // terms of dependency. We create a TokenFactor for Ld and ResNode,
21579 // and update uses of Ld's output chain to use the TokenFactor.
21580 if (Ld->hasAnyUseOfValue(1)) {
21581 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21582 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
21583 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
21584 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
21585 SDValue(ResNode.getNode(), 1));
21586 }
21588 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
21589 }
21590 }
21592 // Emit a zeroed vector and insert the desired subvector on its
21593 // first half.
21594 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
21595 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
21596 return DCI.CombineTo(N, InsV);
21597 }
21599 //===--------------------------------------------------------------------===//
21600 // Combine some shuffles into subvector extracts and inserts:
21601 //
21603 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21604 if (isShuffleHigh128VectorInsertLow(SVOp)) {
21605 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
21606 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
21607 return DCI.CombineTo(N, InsV);
21608 }
21610 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21611 if (isShuffleLow128VectorInsertHigh(SVOp)) {
21612 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
21613 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
21614 return DCI.CombineTo(N, InsV);
21615 }
21617 return SDValue();
21618 }
21620 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
21621 /// possible.
21622 ///
21623 /// This is the leaf of the recursive combinine below. When we have found some
21624 /// chain of single-use x86 shuffle instructions and accumulated the combined
21625 /// shuffle mask represented by them, this will try to pattern match that mask
21626 /// into either a single instruction if there is a special purpose instruction
21627 /// for this operation, or into a PSHUFB instruction which is a fully general
21628 /// instruction but should only be used to replace chains over a certain depth.
21629 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
21630 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
21631 TargetLowering::DAGCombinerInfo &DCI,
21632 const X86Subtarget *Subtarget) {
21633 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
21635 // Find the operand that enters the chain. Note that multiple uses are OK
21636 // here, we're not going to remove the operand we find.
21637 SDValue Input = Op.getOperand(0);
21638 while (Input.getOpcode() == ISD::BITCAST)
21639 Input = Input.getOperand(0);
21641 MVT VT = Input.getSimpleValueType();
21642 MVT RootVT = Root.getSimpleValueType();
21643 SDLoc DL(Root);
21645 // Just remove no-op shuffle masks.
21646 if (Mask.size() == 1) {
21647 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
21648 /*AddTo*/ true);
21649 return true;
21650 }
21652 // Use the float domain if the operand type is a floating point type.
21653 bool FloatDomain = VT.isFloatingPoint();
21655 // For floating point shuffles, we don't have free copies in the shuffle
21656 // instructions or the ability to load as part of the instruction, so
21657 // canonicalize their shuffles to UNPCK or MOV variants.
21658 //
21659 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
21660 // vectors because it can have a load folded into it that UNPCK cannot. This
21661 // doesn't preclude something switching to the shorter encoding post-RA.
21662 if (FloatDomain) {
21663 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
21664 bool Lo = Mask.equals(0, 0);
21665 unsigned Shuffle;
21666 MVT ShuffleVT;
21667 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
21668 // is no slower than UNPCKLPD but has the option to fold the input operand
21669 // into even an unaligned memory load.
21670 if (Lo && Subtarget->hasSSE3()) {
21671 Shuffle = X86ISD::MOVDDUP;
21672 ShuffleVT = MVT::v2f64;
21673 } else {
21674 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
21675 // than the UNPCK variants.
21676 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
21677 ShuffleVT = MVT::v4f32;
21678 }
21679 if (Depth == 1 && Root->getOpcode() == Shuffle)
21680 return false; // Nothing to do!
21681 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21682 DCI.AddToWorklist(Op.getNode());
21683 if (Shuffle == X86ISD::MOVDDUP)
21684 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21685 else
21686 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21687 DCI.AddToWorklist(Op.getNode());
21688 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21689 /*AddTo*/ true);
21690 return true;
21691 }
21692 if (Subtarget->hasSSE3() &&
21693 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
21694 bool Lo = Mask.equals(0, 0, 2, 2);
21695 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
21696 MVT ShuffleVT = MVT::v4f32;
21697 if (Depth == 1 && Root->getOpcode() == Shuffle)
21698 return false; // Nothing to do!
21699 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21700 DCI.AddToWorklist(Op.getNode());
21701 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21702 DCI.AddToWorklist(Op.getNode());
21703 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21704 /*AddTo*/ true);
21705 return true;
21706 }
21707 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
21708 bool Lo = Mask.equals(0, 0, 1, 1);
21709 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21710 MVT ShuffleVT = MVT::v4f32;
21711 if (Depth == 1 && Root->getOpcode() == Shuffle)
21712 return false; // Nothing to do!
21713 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21714 DCI.AddToWorklist(Op.getNode());
21715 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21716 DCI.AddToWorklist(Op.getNode());
21717 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21718 /*AddTo*/ true);
21719 return true;
21720 }
21721 }
21723 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
21724 // variants as none of these have single-instruction variants that are
21725 // superior to the UNPCK formulation.
21726 if (!FloatDomain &&
21727 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
21728 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
21729 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
21730 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
21731 15))) {
21732 bool Lo = Mask[0] == 0;
21733 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21734 if (Depth == 1 && Root->getOpcode() == Shuffle)
21735 return false; // Nothing to do!
21736 MVT ShuffleVT;
21737 switch (Mask.size()) {
21738 case 8:
21739 ShuffleVT = MVT::v8i16;
21740 break;
21741 case 16:
21742 ShuffleVT = MVT::v16i8;
21743 break;
21744 default:
21745 llvm_unreachable("Impossible mask size!");
21746 };
21747 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21748 DCI.AddToWorklist(Op.getNode());
21749 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21750 DCI.AddToWorklist(Op.getNode());
21751 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21752 /*AddTo*/ true);
21753 return true;
21754 }
21756 // Don't try to re-form single instruction chains under any circumstances now
21757 // that we've done encoding canonicalization for them.
21758 if (Depth < 2)
21759 return false;
21761 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
21762 // can replace them with a single PSHUFB instruction profitably. Intel's
21763 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
21764 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
21765 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
21766 SmallVector<SDValue, 16> PSHUFBMask;
21767 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
21768 int Ratio = 16 / Mask.size();
21769 for (unsigned i = 0; i < 16; ++i) {
21770 if (Mask[i / Ratio] == SM_SentinelUndef) {
21771 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
21772 continue;
21773 }
21774 int M = Mask[i / Ratio] != SM_SentinelZero
21775 ? Ratio * Mask[i / Ratio] + i % Ratio
21776 : 255;
21777 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
21778 }
21779 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
21780 DCI.AddToWorklist(Op.getNode());
21781 SDValue PSHUFBMaskOp =
21782 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
21783 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
21784 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
21785 DCI.AddToWorklist(Op.getNode());
21786 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21787 /*AddTo*/ true);
21788 return true;
21789 }
21791 // Failed to find any combines.
21792 return false;
21793 }
21795 /// \brief Fully generic combining of x86 shuffle instructions.
21796 ///
21797 /// This should be the last combine run over the x86 shuffle instructions. Once
21798 /// they have been fully optimized, this will recursively consider all chains
21799 /// of single-use shuffle instructions, build a generic model of the cumulative
21800 /// shuffle operation, and check for simpler instructions which implement this
21801 /// operation. We use this primarily for two purposes:
21802 ///
21803 /// 1) Collapse generic shuffles to specialized single instructions when
21804 /// equivalent. In most cases, this is just an encoding size win, but
21805 /// sometimes we will collapse multiple generic shuffles into a single
21806 /// special-purpose shuffle.
21807 /// 2) Look for sequences of shuffle instructions with 3 or more total
21808 /// instructions, and replace them with the slightly more expensive SSSE3
21809 /// PSHUFB instruction if available. We do this as the last combining step
21810 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
21811 /// a suitable short sequence of other instructions. The PHUFB will either
21812 /// use a register or have to read from memory and so is slightly (but only
21813 /// slightly) more expensive than the other shuffle instructions.
21814 ///
21815 /// Because this is inherently a quadratic operation (for each shuffle in
21816 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
21817 /// This should never be an issue in practice as the shuffle lowering doesn't
21818 /// produce sequences of more than 8 instructions.
21819 ///
21820 /// FIXME: We will currently miss some cases where the redundant shuffling
21821 /// would simplify under the threshold for PSHUFB formation because of
21822 /// combine-ordering. To fix this, we should do the redundant instruction
21823 /// combining in this recursive walk.
21824 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
21825 ArrayRef<int> RootMask,
21826 int Depth, bool HasPSHUFB,
21827 SelectionDAG &DAG,
21828 TargetLowering::DAGCombinerInfo &DCI,
21829 const X86Subtarget *Subtarget) {
21830 // Bound the depth of our recursive combine because this is ultimately
21831 // quadratic in nature.
21832 if (Depth > 8)
21833 return false;
21835 // Directly rip through bitcasts to find the underlying operand.
21836 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
21837 Op = Op.getOperand(0);
21839 MVT VT = Op.getSimpleValueType();
21840 if (!VT.isVector())
21841 return false; // Bail if we hit a non-vector.
21842 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
21843 // version should be added.
21844 if (VT.getSizeInBits() != 128)
21845 return false;
21847 assert(Root.getSimpleValueType().isVector() &&
21848 "Shuffles operate on vector types!");
21849 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
21850 "Can only combine shuffles of the same vector register size.");
21852 if (!isTargetShuffle(Op.getOpcode()))
21853 return false;
21854 SmallVector<int, 16> OpMask;
21855 bool IsUnary;
21856 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
21857 // We only can combine unary shuffles which we can decode the mask for.
21858 if (!HaveMask || !IsUnary)
21859 return false;
21861 assert(VT.getVectorNumElements() == OpMask.size() &&
21862 "Different mask size from vector size!");
21863 assert(((RootMask.size() > OpMask.size() &&
21864 RootMask.size() % OpMask.size() == 0) ||
21865 (OpMask.size() > RootMask.size() &&
21866 OpMask.size() % RootMask.size() == 0) ||
21867 OpMask.size() == RootMask.size()) &&
21868 "The smaller number of elements must divide the larger.");
21869 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
21870 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
21871 assert(((RootRatio == 1 && OpRatio == 1) ||
21872 (RootRatio == 1) != (OpRatio == 1)) &&
21873 "Must not have a ratio for both incoming and op masks!");
21875 SmallVector<int, 16> Mask;
21876 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
21878 // Merge this shuffle operation's mask into our accumulated mask. Note that
21879 // this shuffle's mask will be the first applied to the input, followed by the
21880 // root mask to get us all the way to the root value arrangement. The reason
21881 // for this order is that we are recursing up the operation chain.
21882 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
21883 int RootIdx = i / RootRatio;
21884 if (RootMask[RootIdx] < 0) {
21885 // This is a zero or undef lane, we're done.
21886 Mask.push_back(RootMask[RootIdx]);
21887 continue;
21888 }
21890 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
21891 int OpIdx = RootMaskedIdx / OpRatio;
21892 if (OpMask[OpIdx] < 0) {
21893 // The incoming lanes are zero or undef, it doesn't matter which ones we
21894 // are using.
21895 Mask.push_back(OpMask[OpIdx]);
21896 continue;
21897 }
21899 // Ok, we have non-zero lanes, map them through.
21900 Mask.push_back(OpMask[OpIdx] * OpRatio +
21901 RootMaskedIdx % OpRatio);
21902 }
21904 // See if we can recurse into the operand to combine more things.
21905 switch (Op.getOpcode()) {
21906 case X86ISD::PSHUFB:
21907 HasPSHUFB = true;
21908 case X86ISD::PSHUFD:
21909 case X86ISD::PSHUFHW:
21910 case X86ISD::PSHUFLW:
21911 if (Op.getOperand(0).hasOneUse() &&
21912 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21913 HasPSHUFB, DAG, DCI, Subtarget))
21914 return true;
21915 break;
21917 case X86ISD::UNPCKL:
21918 case X86ISD::UNPCKH:
21919 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
21920 // We can't check for single use, we have to check that this shuffle is the only user.
21921 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
21922 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21923 HasPSHUFB, DAG, DCI, Subtarget))
21924 return true;
21925 break;
21926 }
21928 // Minor canonicalization of the accumulated shuffle mask to make it easier
21929 // to match below. All this does is detect masks with squential pairs of
21930 // elements, and shrink them to the half-width mask. It does this in a loop
21931 // so it will reduce the size of the mask to the minimal width mask which
21932 // performs an equivalent shuffle.
21933 SmallVector<int, 16> WidenedMask;
21934 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
21935 Mask = std::move(WidenedMask);
21936 WidenedMask.clear();
21937 }
21939 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
21940 Subtarget);
21941 }
21943 /// \brief Get the PSHUF-style mask from PSHUF node.
21944 ///
21945 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
21946 /// PSHUF-style masks that can be reused with such instructions.
21947 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
21948 SmallVector<int, 4> Mask;
21949 bool IsUnary;
21950 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
21951 (void)HaveMask;
21952 assert(HaveMask);
21954 switch (N.getOpcode()) {
21955 case X86ISD::PSHUFD:
21956 return Mask;
21957 case X86ISD::PSHUFLW:
21958 Mask.resize(4);
21959 return Mask;
21960 case X86ISD::PSHUFHW:
21961 Mask.erase(Mask.begin(), Mask.begin() + 4);
21962 for (int &M : Mask)
21963 M -= 4;
21964 return Mask;
21965 default:
21966 llvm_unreachable("No valid shuffle instruction found!");
21967 }
21968 }
21970 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
21971 ///
21972 /// We walk up the chain and look for a combinable shuffle, skipping over
21973 /// shuffles that we could hoist this shuffle's transformation past without
21974 /// altering anything.
21975 static SDValue
21976 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
21977 SelectionDAG &DAG,
21978 TargetLowering::DAGCombinerInfo &DCI) {
21979 assert(N.getOpcode() == X86ISD::PSHUFD &&
21980 "Called with something other than an x86 128-bit half shuffle!");
21981 SDLoc DL(N);
21983 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
21984 // of the shuffles in the chain so that we can form a fresh chain to replace
21985 // this one.
21986 SmallVector<SDValue, 8> Chain;
21987 SDValue V = N.getOperand(0);
21988 for (; V.hasOneUse(); V = V.getOperand(0)) {
21989 switch (V.getOpcode()) {
21990 default:
21991 return SDValue(); // Nothing combined!
21993 case ISD::BITCAST:
21994 // Skip bitcasts as we always know the type for the target specific
21995 // instructions.
21996 continue;
21998 case X86ISD::PSHUFD:
21999 // Found another dword shuffle.
22000 break;
22002 case X86ISD::PSHUFLW:
22003 // Check that the low words (being shuffled) are the identity in the
22004 // dword shuffle, and the high words are self-contained.
22005 if (Mask[0] != 0 || Mask[1] != 1 ||
22006 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
22007 return SDValue();
22009 Chain.push_back(V);
22010 continue;
22012 case X86ISD::PSHUFHW:
22013 // Check that the high words (being shuffled) are the identity in the
22014 // dword shuffle, and the low words are self-contained.
22015 if (Mask[2] != 2 || Mask[3] != 3 ||
22016 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
22017 return SDValue();
22019 Chain.push_back(V);
22020 continue;
22022 case X86ISD::UNPCKL:
22023 case X86ISD::UNPCKH:
22024 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
22025 // shuffle into a preceding word shuffle.
22026 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
22027 return SDValue();
22029 // Search for a half-shuffle which we can combine with.
22030 unsigned CombineOp =
22031 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
22032 if (V.getOperand(0) != V.getOperand(1) ||
22033 !V->isOnlyUserOf(V.getOperand(0).getNode()))
22034 return SDValue();
22035 Chain.push_back(V);
22036 V = V.getOperand(0);
22037 do {
22038 switch (V.getOpcode()) {
22039 default:
22040 return SDValue(); // Nothing to combine.
22042 case X86ISD::PSHUFLW:
22043 case X86ISD::PSHUFHW:
22044 if (V.getOpcode() == CombineOp)
22045 break;
22047 Chain.push_back(V);
22049 // Fallthrough!
22050 case ISD::BITCAST:
22051 V = V.getOperand(0);
22052 continue;
22053 }
22054 break;
22055 } while (V.hasOneUse());
22056 break;
22057 }
22058 // Break out of the loop if we break out of the switch.
22059 break;
22060 }
22062 if (!V.hasOneUse())
22063 // We fell out of the loop without finding a viable combining instruction.
22064 return SDValue();
22066 // Merge this node's mask and our incoming mask.
22067 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22068 for (int &M : Mask)
22069 M = VMask[M];
22070 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
22071 getV4X86ShuffleImm8ForMask(Mask, DAG));
22073 // Rebuild the chain around this new shuffle.
22074 while (!Chain.empty()) {
22075 SDValue W = Chain.pop_back_val();
22077 if (V.getValueType() != W.getOperand(0).getValueType())
22078 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
22080 switch (W.getOpcode()) {
22081 default:
22082 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
22084 case X86ISD::UNPCKL:
22085 case X86ISD::UNPCKH:
22086 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
22087 break;
22089 case X86ISD::PSHUFD:
22090 case X86ISD::PSHUFLW:
22091 case X86ISD::PSHUFHW:
22092 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
22093 break;
22094 }
22095 }
22096 if (V.getValueType() != N.getValueType())
22097 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
22099 // Return the new chain to replace N.
22100 return V;
22101 }
22103 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
22104 ///
22105 /// We walk up the chain, skipping shuffles of the other half and looking
22106 /// through shuffles which switch halves trying to find a shuffle of the same
22107 /// pair of dwords.
22108 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
22109 SelectionDAG &DAG,
22110 TargetLowering::DAGCombinerInfo &DCI) {
22111 assert(
22112 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
22113 "Called with something other than an x86 128-bit half shuffle!");
22114 SDLoc DL(N);
22115 unsigned CombineOpcode = N.getOpcode();
22117 // Walk up a single-use chain looking for a combinable shuffle.
22118 SDValue V = N.getOperand(0);
22119 for (; V.hasOneUse(); V = V.getOperand(0)) {
22120 switch (V.getOpcode()) {
22121 default:
22122 return false; // Nothing combined!
22124 case ISD::BITCAST:
22125 // Skip bitcasts as we always know the type for the target specific
22126 // instructions.
22127 continue;
22129 case X86ISD::PSHUFLW:
22130 case X86ISD::PSHUFHW:
22131 if (V.getOpcode() == CombineOpcode)
22132 break;
22134 // Other-half shuffles are no-ops.
22135 continue;
22136 }
22137 // Break out of the loop if we break out of the switch.
22138 break;
22139 }
22141 if (!V.hasOneUse())
22142 // We fell out of the loop without finding a viable combining instruction.
22143 return false;
22145 // Combine away the bottom node as its shuffle will be accumulated into
22146 // a preceding shuffle.
22147 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22149 // Record the old value.
22150 SDValue Old = V;
22152 // Merge this node's mask and our incoming mask (adjusted to account for all
22153 // the pshufd instructions encountered).
22154 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22155 for (int &M : Mask)
22156 M = VMask[M];
22157 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
22158 getV4X86ShuffleImm8ForMask(Mask, DAG));
22160 // Check that the shuffles didn't cancel each other out. If not, we need to
22161 // combine to the new one.
22162 if (Old != V)
22163 // Replace the combinable shuffle with the combined one, updating all users
22164 // so that we re-evaluate the chain here.
22165 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
22167 return true;
22168 }
22170 /// \brief Try to combine x86 target specific shuffles.
22171 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
22172 TargetLowering::DAGCombinerInfo &DCI,
22173 const X86Subtarget *Subtarget) {
22174 SDLoc DL(N);
22175 MVT VT = N.getSimpleValueType();
22176 SmallVector<int, 4> Mask;
22178 switch (N.getOpcode()) {
22179 case X86ISD::PSHUFD:
22180 case X86ISD::PSHUFLW:
22181 case X86ISD::PSHUFHW:
22182 Mask = getPSHUFShuffleMask(N);
22183 assert(Mask.size() == 4);
22184 break;
22185 default:
22186 return SDValue();
22187 }
22189 // Nuke no-op shuffles that show up after combining.
22190 if (isNoopShuffleMask(Mask))
22191 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22193 // Look for simplifications involving one or two shuffle instructions.
22194 SDValue V = N.getOperand(0);
22195 switch (N.getOpcode()) {
22196 default:
22197 break;
22198 case X86ISD::PSHUFLW:
22199 case X86ISD::PSHUFHW:
22200 assert(VT == MVT::v8i16);
22201 (void)VT;
22203 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
22204 return SDValue(); // We combined away this shuffle, so we're done.
22206 // See if this reduces to a PSHUFD which is no more expensive and can
22207 // combine with more operations. Note that it has to at least flip the
22208 // dwords as otherwise it would have been removed as a no-op.
22209 if (Mask[0] == 2 && Mask[1] == 3 && Mask[2] == 0 && Mask[3] == 1) {
22210 int DMask[] = {0, 1, 2, 3};
22211 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
22212 DMask[DOffset + 0] = DOffset + 1;
22213 DMask[DOffset + 1] = DOffset + 0;
22214 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
22215 DCI.AddToWorklist(V.getNode());
22216 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
22217 getV4X86ShuffleImm8ForMask(DMask, DAG));
22218 DCI.AddToWorklist(V.getNode());
22219 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
22220 }
22222 // Look for shuffle patterns which can be implemented as a single unpack.
22223 // FIXME: This doesn't handle the location of the PSHUFD generically, and
22224 // only works when we have a PSHUFD followed by two half-shuffles.
22225 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
22226 (V.getOpcode() == X86ISD::PSHUFLW ||
22227 V.getOpcode() == X86ISD::PSHUFHW) &&
22228 V.getOpcode() != N.getOpcode() &&
22229 V.hasOneUse()) {
22230 SDValue D = V.getOperand(0);
22231 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
22232 D = D.getOperand(0);
22233 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
22234 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22235 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
22236 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22237 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22238 int WordMask[8];
22239 for (int i = 0; i < 4; ++i) {
22240 WordMask[i + NOffset] = Mask[i] + NOffset;
22241 WordMask[i + VOffset] = VMask[i] + VOffset;
22242 }
22243 // Map the word mask through the DWord mask.
22244 int MappedMask[8];
22245 for (int i = 0; i < 8; ++i)
22246 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
22247 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
22248 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
22249 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
22250 std::begin(UnpackLoMask)) ||
22251 std::equal(std::begin(MappedMask), std::end(MappedMask),
22252 std::begin(UnpackHiMask))) {
22253 // We can replace all three shuffles with an unpack.
22254 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
22255 DCI.AddToWorklist(V.getNode());
22256 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
22257 : X86ISD::UNPCKH,
22258 DL, MVT::v8i16, V, V);
22259 }
22260 }
22261 }
22263 break;
22265 case X86ISD::PSHUFD:
22266 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
22267 return NewN;
22269 break;
22270 }
22272 return SDValue();
22273 }
22275 /// \brief Try to combine a shuffle into a target-specific add-sub node.
22276 ///
22277 /// We combine this directly on the abstract vector shuffle nodes so it is
22278 /// easier to generically match. We also insert dummy vector shuffle nodes for
22279 /// the operands which explicitly discard the lanes which are unused by this
22280 /// operation to try to flow through the rest of the combiner the fact that
22281 /// they're unused.
22282 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
22283 SDLoc DL(N);
22284 EVT VT = N->getValueType(0);
22286 // We only handle target-independent shuffles.
22287 // FIXME: It would be easy and harmless to use the target shuffle mask
22288 // extraction tool to support more.
22289 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
22290 return SDValue();
22292 auto *SVN = cast<ShuffleVectorSDNode>(N);
22293 ArrayRef<int> Mask = SVN->getMask();
22294 SDValue V1 = N->getOperand(0);
22295 SDValue V2 = N->getOperand(1);
22297 // We require the first shuffle operand to be the SUB node, and the second to
22298 // be the ADD node.
22299 // FIXME: We should support the commuted patterns.
22300 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
22301 return SDValue();
22303 // If there are other uses of these operations we can't fold them.
22304 if (!V1->hasOneUse() || !V2->hasOneUse())
22305 return SDValue();
22307 // Ensure that both operations have the same operands. Note that we can
22308 // commute the FADD operands.
22309 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
22310 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
22311 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
22312 return SDValue();
22314 // We're looking for blends between FADD and FSUB nodes. We insist on these
22315 // nodes being lined up in a specific expected pattern.
22316 if (!(isShuffleEquivalent(Mask, 0, 3) ||
22317 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
22318 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
22319 return SDValue();
22321 // Only specific types are legal at this point, assert so we notice if and
22322 // when these change.
22323 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
22324 VT == MVT::v4f64) &&
22325 "Unknown vector type encountered!");
22327 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
22328 }
22330 /// PerformShuffleCombine - Performs several different shuffle combines.
22331 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
22332 TargetLowering::DAGCombinerInfo &DCI,
22333 const X86Subtarget *Subtarget) {
22334 SDLoc dl(N);
22335 SDValue N0 = N->getOperand(0);
22336 SDValue N1 = N->getOperand(1);
22337 EVT VT = N->getValueType(0);
22339 // Don't create instructions with illegal types after legalize types has run.
22340 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22341 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
22342 return SDValue();
22344 // If we have legalized the vector types, look for blends of FADD and FSUB
22345 // nodes that we can fuse into an ADDSUB node.
22346 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
22347 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
22348 return AddSub;
22350 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
22351 if (Subtarget->hasFp256() && VT.is256BitVector() &&
22352 N->getOpcode() == ISD::VECTOR_SHUFFLE)
22353 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
22355 // During Type Legalization, when promoting illegal vector types,
22356 // the backend might introduce new shuffle dag nodes and bitcasts.
22357 //
22358 // This code performs the following transformation:
22359 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
22360 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
22361 //
22362 // We do this only if both the bitcast and the BINOP dag nodes have
22363 // one use. Also, perform this transformation only if the new binary
22364 // operation is legal. This is to avoid introducing dag nodes that
22365 // potentially need to be further expanded (or custom lowered) into a
22366 // less optimal sequence of dag nodes.
22367 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
22368 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
22369 N0.getOpcode() == ISD::BITCAST) {
22370 SDValue BC0 = N0.getOperand(0);
22371 EVT SVT = BC0.getValueType();
22372 unsigned Opcode = BC0.getOpcode();
22373 unsigned NumElts = VT.getVectorNumElements();
22375 if (BC0.hasOneUse() && SVT.isVector() &&
22376 SVT.getVectorNumElements() * 2 == NumElts &&
22377 TLI.isOperationLegal(Opcode, VT)) {
22378 bool CanFold = false;
22379 switch (Opcode) {
22380 default : break;
22381 case ISD::ADD :
22382 case ISD::FADD :
22383 case ISD::SUB :
22384 case ISD::FSUB :
22385 case ISD::MUL :
22386 case ISD::FMUL :
22387 CanFold = true;
22388 }
22390 unsigned SVTNumElts = SVT.getVectorNumElements();
22391 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22392 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
22393 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
22394 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
22395 CanFold = SVOp->getMaskElt(i) < 0;
22397 if (CanFold) {
22398 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
22399 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
22400 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
22401 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
22402 }
22403 }
22404 }
22406 // Only handle 128 wide vector from here on.
22407 if (!VT.is128BitVector())
22408 return SDValue();
22410 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
22411 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
22412 // consecutive, non-overlapping, and in the right order.
22413 SmallVector<SDValue, 16> Elts;
22414 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
22415 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
22417 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
22418 if (LD.getNode())
22419 return LD;
22421 if (isTargetShuffle(N->getOpcode())) {
22422 SDValue Shuffle =
22423 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
22424 if (Shuffle.getNode())
22425 return Shuffle;
22427 // Try recursively combining arbitrary sequences of x86 shuffle
22428 // instructions into higher-order shuffles. We do this after combining
22429 // specific PSHUF instruction sequences into their minimal form so that we
22430 // can evaluate how many specialized shuffle instructions are involved in
22431 // a particular chain.
22432 SmallVector<int, 1> NonceMask; // Just a placeholder.
22433 NonceMask.push_back(0);
22434 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
22435 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
22436 DCI, Subtarget))
22437 return SDValue(); // This routine will use CombineTo to replace N.
22438 }
22440 return SDValue();
22441 }
22443 /// PerformTruncateCombine - Converts truncate operation to
22444 /// a sequence of vector shuffle operations.
22445 /// It is possible when we truncate 256-bit vector to 128-bit vector
22446 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
22447 TargetLowering::DAGCombinerInfo &DCI,
22448 const X86Subtarget *Subtarget) {
22449 return SDValue();
22450 }
22452 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
22453 /// specific shuffle of a load can be folded into a single element load.
22454 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
22455 /// shuffles have been custom lowered so we need to handle those here.
22456 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
22457 TargetLowering::DAGCombinerInfo &DCI) {
22458 if (DCI.isBeforeLegalizeOps())
22459 return SDValue();
22461 SDValue InVec = N->getOperand(0);
22462 SDValue EltNo = N->getOperand(1);
22464 if (!isa<ConstantSDNode>(EltNo))
22465 return SDValue();
22467 EVT OriginalVT = InVec.getValueType();
22469 if (InVec.getOpcode() == ISD::BITCAST) {
22470 // Don't duplicate a load with other uses.
22471 if (!InVec.hasOneUse())
22472 return SDValue();
22473 EVT BCVT = InVec.getOperand(0).getValueType();
22474 if (BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
22475 return SDValue();
22476 InVec = InVec.getOperand(0);
22477 }
22479 EVT CurrentVT = InVec.getValueType();
22481 if (!isTargetShuffle(InVec.getOpcode()))
22482 return SDValue();
22484 // Don't duplicate a load with other uses.
22485 if (!InVec.hasOneUse())
22486 return SDValue();
22488 SmallVector<int, 16> ShuffleMask;
22489 bool UnaryShuffle;
22490 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
22491 ShuffleMask, UnaryShuffle))
22492 return SDValue();
22494 // Select the input vector, guarding against out of range extract vector.
22495 unsigned NumElems = CurrentVT.getVectorNumElements();
22496 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
22497 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
22498 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
22499 : InVec.getOperand(1);
22501 // If inputs to shuffle are the same for both ops, then allow 2 uses
22502 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
22504 if (LdNode.getOpcode() == ISD::BITCAST) {
22505 // Don't duplicate a load with other uses.
22506 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
22507 return SDValue();
22509 AllowedUses = 1; // only allow 1 load use if we have a bitcast
22510 LdNode = LdNode.getOperand(0);
22511 }
22513 if (!ISD::isNormalLoad(LdNode.getNode()))
22514 return SDValue();
22516 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
22518 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
22519 return SDValue();
22521 EVT EltVT = N->getValueType(0);
22522 // If there's a bitcast before the shuffle, check if the load type and
22523 // alignment is valid.
22524 unsigned Align = LN0->getAlignment();
22525 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22526 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
22527 EltVT.getTypeForEVT(*DAG.getContext()));
22529 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
22530 return SDValue();
22532 // All checks match so transform back to vector_shuffle so that DAG combiner
22533 // can finish the job
22534 SDLoc dl(N);
22536 // Create shuffle node taking into account the case that its a unary shuffle
22537 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
22538 : InVec.getOperand(1);
22539 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
22540 InVec.getOperand(0), Shuffle,
22541 &ShuffleMask[0]);
22542 Shuffle = DAG.getNode(ISD::BITCAST, dl, OriginalVT, Shuffle);
22543 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
22544 EltNo);
22545 }
22547 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
22548 /// generation and convert it from being a bunch of shuffles and extracts
22549 /// into a somewhat faster sequence. For i686, the best sequence is apparently
22550 /// storing the value and loading scalars back, while for x64 we should
22551 /// use 64-bit extracts and shifts.
22552 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
22553 TargetLowering::DAGCombinerInfo &DCI) {
22554 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
22555 if (NewOp.getNode())
22556 return NewOp;
22558 SDValue InputVector = N->getOperand(0);
22560 // Detect whether we are trying to convert from mmx to i32 and the bitcast
22561 // from mmx to v2i32 has a single usage.
22562 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
22563 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
22564 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
22565 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22566 N->getValueType(0),
22567 InputVector.getNode()->getOperand(0));
22569 // Only operate on vectors of 4 elements, where the alternative shuffling
22570 // gets to be more expensive.
22571 if (InputVector.getValueType() != MVT::v4i32)
22572 return SDValue();
22574 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
22575 // single use which is a sign-extend or zero-extend, and all elements are
22576 // used.
22577 SmallVector<SDNode *, 4> Uses;
22578 unsigned ExtractedElements = 0;
22579 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
22580 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
22581 if (UI.getUse().getResNo() != InputVector.getResNo())
22582 return SDValue();
22584 SDNode *Extract = *UI;
22585 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
22586 return SDValue();
22588 if (Extract->getValueType(0) != MVT::i32)
22589 return SDValue();
22590 if (!Extract->hasOneUse())
22591 return SDValue();
22592 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
22593 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
22594 return SDValue();
22595 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
22596 return SDValue();
22598 // Record which element was extracted.
22599 ExtractedElements |=
22600 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
22602 Uses.push_back(Extract);
22603 }
22605 // If not all the elements were used, this may not be worthwhile.
22606 if (ExtractedElements != 15)
22607 return SDValue();
22609 // Ok, we've now decided to do the transformation.
22610 // If 64-bit shifts are legal, use the extract-shift sequence,
22611 // otherwise bounce the vector off the cache.
22612 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22613 SDValue Vals[4];
22614 SDLoc dl(InputVector);
22616 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
22617 SDValue Cst = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, InputVector);
22618 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy();
22619 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22620 DAG.getConstant(0, VecIdxTy));
22621 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22622 DAG.getConstant(1, VecIdxTy));
22624 SDValue ShAmt = DAG.getConstant(32,
22625 DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64));
22626 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
22627 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22628 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
22629 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
22630 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22631 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
22632 } else {
22633 // Store the value to a temporary stack slot.
22634 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
22635 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
22636 MachinePointerInfo(), false, false, 0);
22638 EVT ElementType = InputVector.getValueType().getVectorElementType();
22639 unsigned EltSize = ElementType.getSizeInBits() / 8;
22641 // Replace each use (extract) with a load of the appropriate element.
22642 for (unsigned i = 0; i < 4; ++i) {
22643 uint64_t Offset = EltSize * i;
22644 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
22646 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
22647 StackPtr, OffsetVal);
22649 // Load the scalar.
22650 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
22651 ScalarAddr, MachinePointerInfo(),
22652 false, false, false, 0);
22654 }
22655 }
22657 // Replace the extracts
22658 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
22659 UE = Uses.end(); UI != UE; ++UI) {
22660 SDNode *Extract = *UI;
22662 SDValue Idx = Extract->getOperand(1);
22663 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
22664 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
22665 }
22667 // The replacement was made in place; don't return anything.
22668 return SDValue();
22669 }
22671 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
22672 static std::pair<unsigned, bool>
22673 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
22674 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
22675 if (!VT.isVector())
22676 return std::make_pair(0, false);
22678 bool NeedSplit = false;
22679 switch (VT.getSimpleVT().SimpleTy) {
22680 default: return std::make_pair(0, false);
22681 case MVT::v32i8:
22682 case MVT::v16i16:
22683 case MVT::v8i32:
22684 if (!Subtarget->hasAVX2())
22685 NeedSplit = true;
22686 if (!Subtarget->hasAVX())
22687 return std::make_pair(0, false);
22688 break;
22689 case MVT::v16i8:
22690 case MVT::v8i16:
22691 case MVT::v4i32:
22692 if (!Subtarget->hasSSE2())
22693 return std::make_pair(0, false);
22694 }
22696 // SSE2 has only a small subset of the operations.
22697 bool hasUnsigned = Subtarget->hasSSE41() ||
22698 (Subtarget->hasSSE2() && VT == MVT::v16i8);
22699 bool hasSigned = Subtarget->hasSSE41() ||
22700 (Subtarget->hasSSE2() && VT == MVT::v8i16);
22702 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22704 unsigned Opc = 0;
22705 // Check for x CC y ? x : y.
22706 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22707 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22708 switch (CC) {
22709 default: break;
22710 case ISD::SETULT:
22711 case ISD::SETULE:
22712 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22713 case ISD::SETUGT:
22714 case ISD::SETUGE:
22715 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22716 case ISD::SETLT:
22717 case ISD::SETLE:
22718 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22719 case ISD::SETGT:
22720 case ISD::SETGE:
22721 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22722 }
22723 // Check for x CC y ? y : x -- a min/max with reversed arms.
22724 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22725 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22726 switch (CC) {
22727 default: break;
22728 case ISD::SETULT:
22729 case ISD::SETULE:
22730 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22731 case ISD::SETUGT:
22732 case ISD::SETUGE:
22733 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22734 case ISD::SETLT:
22735 case ISD::SETLE:
22736 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22737 case ISD::SETGT:
22738 case ISD::SETGE:
22739 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22740 }
22741 }
22743 return std::make_pair(Opc, NeedSplit);
22744 }
22746 static SDValue
22747 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
22748 const X86Subtarget *Subtarget) {
22749 SDLoc dl(N);
22750 SDValue Cond = N->getOperand(0);
22751 SDValue LHS = N->getOperand(1);
22752 SDValue RHS = N->getOperand(2);
22754 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
22755 SDValue CondSrc = Cond->getOperand(0);
22756 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
22757 Cond = CondSrc->getOperand(0);
22758 }
22760 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
22761 return SDValue();
22763 // A vselect where all conditions and data are constants can be optimized into
22764 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
22765 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
22766 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
22767 return SDValue();
22769 unsigned MaskValue = 0;
22770 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
22771 return SDValue();
22773 MVT VT = N->getSimpleValueType(0);
22774 unsigned NumElems = VT.getVectorNumElements();
22775 SmallVector<int, 8> ShuffleMask(NumElems, -1);
22776 for (unsigned i = 0; i < NumElems; ++i) {
22777 // Be sure we emit undef where we can.
22778 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
22779 ShuffleMask[i] = -1;
22780 else
22781 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
22782 }
22784 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22785 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
22786 return SDValue();
22787 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
22788 }
22790 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
22791 /// nodes.
22792 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
22793 TargetLowering::DAGCombinerInfo &DCI,
22794 const X86Subtarget *Subtarget) {
22795 SDLoc DL(N);
22796 SDValue Cond = N->getOperand(0);
22797 // Get the LHS/RHS of the select.
22798 SDValue LHS = N->getOperand(1);
22799 SDValue RHS = N->getOperand(2);
22800 EVT VT = LHS.getValueType();
22801 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22803 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
22804 // instructions match the semantics of the common C idiom x<y?x:y but not
22805 // x<=y?x:y, because of how they handle negative zero (which can be
22806 // ignored in unsafe-math mode).
22807 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
22808 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
22809 (Subtarget->hasSSE2() ||
22810 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
22811 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22813 unsigned Opcode = 0;
22814 // Check for x CC y ? x : y.
22815 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22816 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22817 switch (CC) {
22818 default: break;
22819 case ISD::SETULT:
22820 // Converting this to a min would handle NaNs incorrectly, and swapping
22821 // the operands would cause it to handle comparisons between positive
22822 // and negative zero incorrectly.
22823 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22824 if (!DAG.getTarget().Options.UnsafeFPMath &&
22825 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22826 break;
22827 std::swap(LHS, RHS);
22828 }
22829 Opcode = X86ISD::FMIN;
22830 break;
22831 case ISD::SETOLE:
22832 // Converting this to a min would handle comparisons between positive
22833 // and negative zero incorrectly.
22834 if (!DAG.getTarget().Options.UnsafeFPMath &&
22835 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22836 break;
22837 Opcode = X86ISD::FMIN;
22838 break;
22839 case ISD::SETULE:
22840 // Converting this to a min would handle both negative zeros and NaNs
22841 // incorrectly, but we can swap the operands to fix both.
22842 std::swap(LHS, RHS);
22843 case ISD::SETOLT:
22844 case ISD::SETLT:
22845 case ISD::SETLE:
22846 Opcode = X86ISD::FMIN;
22847 break;
22849 case ISD::SETOGE:
22850 // Converting this to a max would handle comparisons between positive
22851 // and negative zero incorrectly.
22852 if (!DAG.getTarget().Options.UnsafeFPMath &&
22853 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22854 break;
22855 Opcode = X86ISD::FMAX;
22856 break;
22857 case ISD::SETUGT:
22858 // Converting this to a max would handle NaNs incorrectly, and swapping
22859 // the operands would cause it to handle comparisons between positive
22860 // and negative zero incorrectly.
22861 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22862 if (!DAG.getTarget().Options.UnsafeFPMath &&
22863 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22864 break;
22865 std::swap(LHS, RHS);
22866 }
22867 Opcode = X86ISD::FMAX;
22868 break;
22869 case ISD::SETUGE:
22870 // Converting this to a max would handle both negative zeros and NaNs
22871 // incorrectly, but we can swap the operands to fix both.
22872 std::swap(LHS, RHS);
22873 case ISD::SETOGT:
22874 case ISD::SETGT:
22875 case ISD::SETGE:
22876 Opcode = X86ISD::FMAX;
22877 break;
22878 }
22879 // Check for x CC y ? y : x -- a min/max with reversed arms.
22880 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22881 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22882 switch (CC) {
22883 default: break;
22884 case ISD::SETOGE:
22885 // Converting this to a min would handle comparisons between positive
22886 // and negative zero incorrectly, and swapping the operands would
22887 // cause it to handle NaNs incorrectly.
22888 if (!DAG.getTarget().Options.UnsafeFPMath &&
22889 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
22890 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22891 break;
22892 std::swap(LHS, RHS);
22893 }
22894 Opcode = X86ISD::FMIN;
22895 break;
22896 case ISD::SETUGT:
22897 // Converting this to a min would handle NaNs incorrectly.
22898 if (!DAG.getTarget().Options.UnsafeFPMath &&
22899 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
22900 break;
22901 Opcode = X86ISD::FMIN;
22902 break;
22903 case ISD::SETUGE:
22904 // Converting this to a min would handle both negative zeros and NaNs
22905 // incorrectly, but we can swap the operands to fix both.
22906 std::swap(LHS, RHS);
22907 case ISD::SETOGT:
22908 case ISD::SETGT:
22909 case ISD::SETGE:
22910 Opcode = X86ISD::FMIN;
22911 break;
22913 case ISD::SETULT:
22914 // Converting this to a max would handle NaNs incorrectly.
22915 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22916 break;
22917 Opcode = X86ISD::FMAX;
22918 break;
22919 case ISD::SETOLE:
22920 // Converting this to a max would handle comparisons between positive
22921 // and negative zero incorrectly, and swapping the operands would
22922 // cause it to handle NaNs incorrectly.
22923 if (!DAG.getTarget().Options.UnsafeFPMath &&
22924 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
22925 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22926 break;
22927 std::swap(LHS, RHS);
22928 }
22929 Opcode = X86ISD::FMAX;
22930 break;
22931 case ISD::SETULE:
22932 // Converting this to a max would handle both negative zeros and NaNs
22933 // incorrectly, but we can swap the operands to fix both.
22934 std::swap(LHS, RHS);
22935 case ISD::SETOLT:
22936 case ISD::SETLT:
22937 case ISD::SETLE:
22938 Opcode = X86ISD::FMAX;
22939 break;
22940 }
22941 }
22943 if (Opcode)
22944 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
22945 }
22947 EVT CondVT = Cond.getValueType();
22948 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
22949 CondVT.getVectorElementType() == MVT::i1) {
22950 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
22951 // lowering on KNL. In this case we convert it to
22952 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
22953 // The same situation for all 128 and 256-bit vectors of i8 and i16.
22954 // Since SKX these selects have a proper lowering.
22955 EVT OpVT = LHS.getValueType();
22956 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
22957 (OpVT.getVectorElementType() == MVT::i8 ||
22958 OpVT.getVectorElementType() == MVT::i16) &&
22959 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
22960 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
22961 DCI.AddToWorklist(Cond.getNode());
22962 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
22963 }
22964 }
22965 // If this is a select between two integer constants, try to do some
22966 // optimizations.
22967 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
22968 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
22969 // Don't do this for crazy integer types.
22970 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
22971 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
22972 // so that TrueC (the true value) is larger than FalseC.
22973 bool NeedsCondInvert = false;
22975 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
22976 // Efficiently invertible.
22977 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
22978 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
22979 isa<ConstantSDNode>(Cond.getOperand(1))))) {
22980 NeedsCondInvert = true;
22981 std::swap(TrueC, FalseC);
22982 }
22984 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
22985 if (FalseC->getAPIntValue() == 0 &&
22986 TrueC->getAPIntValue().isPowerOf2()) {
22987 if (NeedsCondInvert) // Invert the condition if needed.
22988 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22989 DAG.getConstant(1, Cond.getValueType()));
22991 // Zero extend the condition if needed.
22992 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
22994 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22995 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
22996 DAG.getConstant(ShAmt, MVT::i8));
22997 }
22999 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
23000 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23001 if (NeedsCondInvert) // Invert the condition if needed.
23002 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23003 DAG.getConstant(1, Cond.getValueType()));
23005 // Zero extend the condition if needed.
23006 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23007 FalseC->getValueType(0), Cond);
23008 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23009 SDValue(FalseC, 0));
23010 }
23012 // Optimize cases that will turn into an LEA instruction. This requires
23013 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23014 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23015 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23016 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23018 bool isFastMultiplier = false;
23019 if (Diff < 10) {
23020 switch ((unsigned char)Diff) {
23021 default: break;
23022 case 1: // result = add base, cond
23023 case 2: // result = lea base( , cond*2)
23024 case 3: // result = lea base(cond, cond*2)
23025 case 4: // result = lea base( , cond*4)
23026 case 5: // result = lea base(cond, cond*4)
23027 case 8: // result = lea base( , cond*8)
23028 case 9: // result = lea base(cond, cond*8)
23029 isFastMultiplier = true;
23030 break;
23031 }
23032 }
23034 if (isFastMultiplier) {
23035 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23036 if (NeedsCondInvert) // Invert the condition if needed.
23037 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23038 DAG.getConstant(1, Cond.getValueType()));
23040 // Zero extend the condition if needed.
23041 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23042 Cond);
23043 // Scale the condition by the difference.
23044 if (Diff != 1)
23045 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23046 DAG.getConstant(Diff, Cond.getValueType()));
23048 // Add the base if non-zero.
23049 if (FalseC->getAPIntValue() != 0)
23050 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23051 SDValue(FalseC, 0));
23052 return Cond;
23053 }
23054 }
23055 }
23056 }
23058 // Canonicalize max and min:
23059 // (x > y) ? x : y -> (x >= y) ? x : y
23060 // (x < y) ? x : y -> (x <= y) ? x : y
23061 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
23062 // the need for an extra compare
23063 // against zero. e.g.
23064 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
23065 // subl %esi, %edi
23066 // testl %edi, %edi
23067 // movl $0, %eax
23068 // cmovgl %edi, %eax
23069 // =>
23070 // xorl %eax, %eax
23071 // subl %esi, $edi
23072 // cmovsl %eax, %edi
23073 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
23074 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23075 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23076 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23077 switch (CC) {
23078 default: break;
23079 case ISD::SETLT:
23080 case ISD::SETGT: {
23081 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
23082 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
23083 Cond.getOperand(0), Cond.getOperand(1), NewCC);
23084 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
23085 }
23086 }
23087 }
23089 // Early exit check
23090 if (!TLI.isTypeLegal(VT))
23091 return SDValue();
23093 // Match VSELECTs into subs with unsigned saturation.
23094 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
23095 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
23096 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
23097 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
23098 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23100 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
23101 // left side invert the predicate to simplify logic below.
23102 SDValue Other;
23103 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
23104 Other = RHS;
23105 CC = ISD::getSetCCInverse(CC, true);
23106 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
23107 Other = LHS;
23108 }
23110 if (Other.getNode() && Other->getNumOperands() == 2 &&
23111 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
23112 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
23113 SDValue CondRHS = Cond->getOperand(1);
23115 // Look for a general sub with unsigned saturation first.
23116 // x >= y ? x-y : 0 --> subus x, y
23117 // x > y ? x-y : 0 --> subus x, y
23118 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
23119 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
23120 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
23122 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
23123 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
23124 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
23125 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
23126 // If the RHS is a constant we have to reverse the const
23127 // canonicalization.
23128 // x > C-1 ? x+-C : 0 --> subus x, C
23129 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
23130 CondRHSConst->getAPIntValue() ==
23131 (-OpRHSConst->getAPIntValue() - 1))
23132 return DAG.getNode(
23133 X86ISD::SUBUS, DL, VT, OpLHS,
23134 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
23136 // Another special case: If C was a sign bit, the sub has been
23137 // canonicalized into a xor.
23138 // FIXME: Would it be better to use computeKnownBits to determine
23139 // whether it's safe to decanonicalize the xor?
23140 // x s< 0 ? x^C : 0 --> subus x, C
23141 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
23142 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
23143 OpRHSConst->getAPIntValue().isSignBit())
23144 // Note that we have to rebuild the RHS constant here to ensure we
23145 // don't rely on particular values of undef lanes.
23146 return DAG.getNode(
23147 X86ISD::SUBUS, DL, VT, OpLHS,
23148 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
23149 }
23150 }
23151 }
23153 // Try to match a min/max vector operation.
23154 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
23155 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
23156 unsigned Opc = ret.first;
23157 bool NeedSplit = ret.second;
23159 if (Opc && NeedSplit) {
23160 unsigned NumElems = VT.getVectorNumElements();
23161 // Extract the LHS vectors
23162 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
23163 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
23165 // Extract the RHS vectors
23166 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
23167 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
23169 // Create min/max for each subvector
23170 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
23171 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
23173 // Merge the result
23174 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
23175 } else if (Opc)
23176 return DAG.getNode(Opc, DL, VT, LHS, RHS);
23177 }
23179 // Simplify vector selection if condition value type matches vselect
23180 // operand type
23181 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
23182 assert(Cond.getValueType().isVector() &&
23183 "vector select expects a vector selector!");
23185 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
23186 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
23188 // Try invert the condition if true value is not all 1s and false value
23189 // is not all 0s.
23190 if (!TValIsAllOnes && !FValIsAllZeros &&
23191 // Check if the selector will be produced by CMPP*/PCMP*
23192 Cond.getOpcode() == ISD::SETCC &&
23193 // Check if SETCC has already been promoted
23194 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
23195 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
23196 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
23198 if (TValIsAllZeros || FValIsAllOnes) {
23199 SDValue CC = Cond.getOperand(2);
23200 ISD::CondCode NewCC =
23201 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
23202 Cond.getOperand(0).getValueType().isInteger());
23203 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
23204 std::swap(LHS, RHS);
23205 TValIsAllOnes = FValIsAllOnes;
23206 FValIsAllZeros = TValIsAllZeros;
23207 }
23208 }
23210 if (TValIsAllOnes || FValIsAllZeros) {
23211 SDValue Ret;
23213 if (TValIsAllOnes && FValIsAllZeros)
23214 Ret = Cond;
23215 else if (TValIsAllOnes)
23216 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
23217 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
23218 else if (FValIsAllZeros)
23219 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
23220 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
23222 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
23223 }
23224 }
23226 // If we know that this node is legal then we know that it is going to be
23227 // matched by one of the SSE/AVX BLEND instructions. These instructions only
23228 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
23229 // to simplify previous instructions.
23230 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
23231 !DCI.isBeforeLegalize() &&
23232 // We explicitly check against v8i16 and v16i16 because, although
23233 // they're marked as Custom, they might only be legal when Cond is a
23234 // build_vector of constants. This will be taken care in a later
23235 // condition.
23236 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
23237 VT != MVT::v8i16) &&
23238 // Don't optimize vector of constants. Those are handled by
23239 // the generic code and all the bits must be properly set for
23240 // the generic optimizer.
23241 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
23242 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
23244 // Don't optimize vector selects that map to mask-registers.
23245 if (BitWidth == 1)
23246 return SDValue();
23248 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
23249 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
23251 APInt KnownZero, KnownOne;
23252 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
23253 DCI.isBeforeLegalizeOps());
23254 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
23255 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
23256 TLO)) {
23257 // If we changed the computation somewhere in the DAG, this change
23258 // will affect all users of Cond.
23259 // Make sure it is fine and update all the nodes so that we do not
23260 // use the generic VSELECT anymore. Otherwise, we may perform
23261 // wrong optimizations as we messed up with the actual expectation
23262 // for the vector boolean values.
23263 if (Cond != TLO.Old) {
23264 // Check all uses of that condition operand to check whether it will be
23265 // consumed by non-BLEND instructions, which may depend on all bits are
23266 // set properly.
23267 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23268 I != E; ++I)
23269 if (I->getOpcode() != ISD::VSELECT)
23270 // TODO: Add other opcodes eventually lowered into BLEND.
23271 return SDValue();
23273 // Update all the users of the condition, before committing the change,
23274 // so that the VSELECT optimizations that expect the correct vector
23275 // boolean value will not be triggered.
23276 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23277 I != E; ++I)
23278 DAG.ReplaceAllUsesOfValueWith(
23279 SDValue(*I, 0),
23280 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
23281 Cond, I->getOperand(1), I->getOperand(2)));
23282 DCI.CommitTargetLoweringOpt(TLO);
23283 return SDValue();
23284 }
23285 // At this point, only Cond is changed. Change the condition
23286 // just for N to keep the opportunity to optimize all other
23287 // users their own way.
23288 DAG.ReplaceAllUsesOfValueWith(
23289 SDValue(N, 0),
23290 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
23291 TLO.New, N->getOperand(1), N->getOperand(2)));
23292 return SDValue();
23293 }
23294 }
23296 // We should generate an X86ISD::BLENDI from a vselect if its argument
23297 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
23298 // constants. This specific pattern gets generated when we split a
23299 // selector for a 512 bit vector in a machine without AVX512 (but with
23300 // 256-bit vectors), during legalization:
23301 //
23302 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
23303 //
23304 // Iff we find this pattern and the build_vectors are built from
23305 // constants, we translate the vselect into a shuffle_vector that we
23306 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
23307 if ((N->getOpcode() == ISD::VSELECT ||
23308 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
23309 !DCI.isBeforeLegalize()) {
23310 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
23311 if (Shuffle.getNode())
23312 return Shuffle;
23313 }
23315 return SDValue();
23316 }
23318 // Check whether a boolean test is testing a boolean value generated by
23319 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23320 // code.
23321 //
23322 // Simplify the following patterns:
23323 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23324 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23325 // to (Op EFLAGS Cond)
23326 //
23327 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23328 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23329 // to (Op EFLAGS !Cond)
23330 //
23331 // where Op could be BRCOND or CMOV.
23332 //
23333 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23334 // Quit if not CMP and SUB with its value result used.
23335 if (Cmp.getOpcode() != X86ISD::CMP &&
23336 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23337 return SDValue();
23339 // Quit if not used as a boolean value.
23340 if (CC != X86::COND_E && CC != X86::COND_NE)
23341 return SDValue();
23343 // Check CMP operands. One of them should be 0 or 1 and the other should be
23344 // an SetCC or extended from it.
23345 SDValue Op1 = Cmp.getOperand(0);
23346 SDValue Op2 = Cmp.getOperand(1);
23348 SDValue SetCC;
23349 const ConstantSDNode* C = nullptr;
23350 bool needOppositeCond = (CC == X86::COND_E);
23351 bool checkAgainstTrue = false; // Is it a comparison against 1?
23353 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23354 SetCC = Op2;
23355 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23356 SetCC = Op1;
23357 else // Quit if all operands are not constants.
23358 return SDValue();
23360 if (C->getZExtValue() == 1) {
23361 needOppositeCond = !needOppositeCond;
23362 checkAgainstTrue = true;
23363 } else if (C->getZExtValue() != 0)
23364 // Quit if the constant is neither 0 or 1.
23365 return SDValue();
23367 bool truncatedToBoolWithAnd = false;
23368 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23369 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23370 SetCC.getOpcode() == ISD::TRUNCATE ||
23371 SetCC.getOpcode() == ISD::AND) {
23372 if (SetCC.getOpcode() == ISD::AND) {
23373 int OpIdx = -1;
23374 ConstantSDNode *CS;
23375 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23376 CS->getZExtValue() == 1)
23377 OpIdx = 1;
23378 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23379 CS->getZExtValue() == 1)
23380 OpIdx = 0;
23381 if (OpIdx == -1)
23382 break;
23383 SetCC = SetCC.getOperand(OpIdx);
23384 truncatedToBoolWithAnd = true;
23385 } else
23386 SetCC = SetCC.getOperand(0);
23387 }
23389 switch (SetCC.getOpcode()) {
23390 case X86ISD::SETCC_CARRY:
23391 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23392 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23393 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23394 // truncated to i1 using 'and'.
23395 if (checkAgainstTrue && !truncatedToBoolWithAnd)
23396 break;
23397 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
23398 "Invalid use of SETCC_CARRY!");
23399 // FALL THROUGH
23400 case X86ISD::SETCC:
23401 // Set the condition code or opposite one if necessary.
23402 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
23403 if (needOppositeCond)
23404 CC = X86::GetOppositeBranchCondition(CC);
23405 return SetCC.getOperand(1);
23406 case X86ISD::CMOV: {
23407 // Check whether false/true value has canonical one, i.e. 0 or 1.
23408 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
23409 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
23410 // Quit if true value is not a constant.
23411 if (!TVal)
23412 return SDValue();
23413 // Quit if false value is not a constant.
23414 if (!FVal) {
23415 SDValue Op = SetCC.getOperand(0);
23416 // Skip 'zext' or 'trunc' node.
23417 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
23418 Op.getOpcode() == ISD::TRUNCATE)
23419 Op = Op.getOperand(0);
23420 // A special case for rdrand/rdseed, where 0 is set if false cond is
23421 // found.
23422 if ((Op.getOpcode() != X86ISD::RDRAND &&
23423 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
23424 return SDValue();
23425 }
23426 // Quit if false value is not the constant 0 or 1.
23427 bool FValIsFalse = true;
23428 if (FVal && FVal->getZExtValue() != 0) {
23429 if (FVal->getZExtValue() != 1)
23430 return SDValue();
23431 // If FVal is 1, opposite cond is needed.
23432 needOppositeCond = !needOppositeCond;
23433 FValIsFalse = false;
23434 }
23435 // Quit if TVal is not the constant opposite of FVal.
23436 if (FValIsFalse && TVal->getZExtValue() != 1)
23437 return SDValue();
23438 if (!FValIsFalse && TVal->getZExtValue() != 0)
23439 return SDValue();
23440 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
23441 if (needOppositeCond)
23442 CC = X86::GetOppositeBranchCondition(CC);
23443 return SetCC.getOperand(3);
23444 }
23445 }
23447 return SDValue();
23448 }
23450 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
23451 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
23452 TargetLowering::DAGCombinerInfo &DCI,
23453 const X86Subtarget *Subtarget) {
23454 SDLoc DL(N);
23456 // If the flag operand isn't dead, don't touch this CMOV.
23457 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
23458 return SDValue();
23460 SDValue FalseOp = N->getOperand(0);
23461 SDValue TrueOp = N->getOperand(1);
23462 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
23463 SDValue Cond = N->getOperand(3);
23465 if (CC == X86::COND_E || CC == X86::COND_NE) {
23466 switch (Cond.getOpcode()) {
23467 default: break;
23468 case X86ISD::BSR:
23469 case X86ISD::BSF:
23470 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
23471 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
23472 return (CC == X86::COND_E) ? FalseOp : TrueOp;
23473 }
23474 }
23476 SDValue Flags;
23478 Flags = checkBoolTestSetCCCombine(Cond, CC);
23479 if (Flags.getNode() &&
23480 // Extra check as FCMOV only supports a subset of X86 cond.
23481 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
23482 SDValue Ops[] = { FalseOp, TrueOp,
23483 DAG.getConstant(CC, MVT::i8), Flags };
23484 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23485 }
23487 // If this is a select between two integer constants, try to do some
23488 // optimizations. Note that the operands are ordered the opposite of SELECT
23489 // operands.
23490 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
23491 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
23492 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
23493 // larger than FalseC (the false value).
23494 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
23495 CC = X86::GetOppositeBranchCondition(CC);
23496 std::swap(TrueC, FalseC);
23497 std::swap(TrueOp, FalseOp);
23498 }
23500 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
23501 // This is efficient for any integer data type (including i8/i16) and
23502 // shift amount.
23503 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
23504 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23505 DAG.getConstant(CC, MVT::i8), Cond);
23507 // Zero extend the condition if needed.
23508 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
23510 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23511 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
23512 DAG.getConstant(ShAmt, MVT::i8));
23513 if (N->getNumValues() == 2) // Dead flag value?
23514 return DCI.CombineTo(N, Cond, SDValue());
23515 return Cond;
23516 }
23518 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
23519 // for any integer data type, including i8/i16.
23520 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23521 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23522 DAG.getConstant(CC, MVT::i8), Cond);
23524 // Zero extend the condition if needed.
23525 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23526 FalseC->getValueType(0), Cond);
23527 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23528 SDValue(FalseC, 0));
23530 if (N->getNumValues() == 2) // Dead flag value?
23531 return DCI.CombineTo(N, Cond, SDValue());
23532 return Cond;
23533 }
23535 // Optimize cases that will turn into an LEA instruction. This requires
23536 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23537 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23538 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23539 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23541 bool isFastMultiplier = false;
23542 if (Diff < 10) {
23543 switch ((unsigned char)Diff) {
23544 default: break;
23545 case 1: // result = add base, cond
23546 case 2: // result = lea base( , cond*2)
23547 case 3: // result = lea base(cond, cond*2)
23548 case 4: // result = lea base( , cond*4)
23549 case 5: // result = lea base(cond, cond*4)
23550 case 8: // result = lea base( , cond*8)
23551 case 9: // result = lea base(cond, cond*8)
23552 isFastMultiplier = true;
23553 break;
23554 }
23555 }
23557 if (isFastMultiplier) {
23558 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23559 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23560 DAG.getConstant(CC, MVT::i8), Cond);
23561 // Zero extend the condition if needed.
23562 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23563 Cond);
23564 // Scale the condition by the difference.
23565 if (Diff != 1)
23566 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23567 DAG.getConstant(Diff, Cond.getValueType()));
23569 // Add the base if non-zero.
23570 if (FalseC->getAPIntValue() != 0)
23571 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23572 SDValue(FalseC, 0));
23573 if (N->getNumValues() == 2) // Dead flag value?
23574 return DCI.CombineTo(N, Cond, SDValue());
23575 return Cond;
23576 }
23577 }
23578 }
23579 }
23581 // Handle these cases:
23582 // (select (x != c), e, c) -> select (x != c), e, x),
23583 // (select (x == c), c, e) -> select (x == c), x, e)
23584 // where the c is an integer constant, and the "select" is the combination
23585 // of CMOV and CMP.
23586 //
23587 // The rationale for this change is that the conditional-move from a constant
23588 // needs two instructions, however, conditional-move from a register needs
23589 // only one instruction.
23590 //
23591 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
23592 // some instruction-combining opportunities. This opt needs to be
23593 // postponed as late as possible.
23594 //
23595 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
23596 // the DCI.xxxx conditions are provided to postpone the optimization as
23597 // late as possible.
23599 ConstantSDNode *CmpAgainst = nullptr;
23600 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
23601 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
23602 !isa<ConstantSDNode>(Cond.getOperand(0))) {
23604 if (CC == X86::COND_NE &&
23605 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
23606 CC = X86::GetOppositeBranchCondition(CC);
23607 std::swap(TrueOp, FalseOp);
23608 }
23610 if (CC == X86::COND_E &&
23611 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
23612 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
23613 DAG.getConstant(CC, MVT::i8), Cond };
23614 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
23615 }
23616 }
23617 }
23619 return SDValue();
23620 }
23622 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
23623 const X86Subtarget *Subtarget) {
23624 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
23625 switch (IntNo) {
23626 default: return SDValue();
23627 // SSE/AVX/AVX2 blend intrinsics.
23628 case Intrinsic::x86_avx2_pblendvb:
23629 case Intrinsic::x86_avx2_pblendw:
23630 case Intrinsic::x86_avx2_pblendd_128:
23631 case Intrinsic::x86_avx2_pblendd_256:
23632 // Don't try to simplify this intrinsic if we don't have AVX2.
23633 if (!Subtarget->hasAVX2())
23634 return SDValue();
23635 // FALL-THROUGH
23636 case Intrinsic::x86_avx_blend_pd_256:
23637 case Intrinsic::x86_avx_blend_ps_256:
23638 case Intrinsic::x86_avx_blendv_pd_256:
23639 case Intrinsic::x86_avx_blendv_ps_256:
23640 // Don't try to simplify this intrinsic if we don't have AVX.
23641 if (!Subtarget->hasAVX())
23642 return SDValue();
23643 // FALL-THROUGH
23644 case Intrinsic::x86_sse41_pblendw:
23645 case Intrinsic::x86_sse41_blendpd:
23646 case Intrinsic::x86_sse41_blendps:
23647 case Intrinsic::x86_sse41_blendvps:
23648 case Intrinsic::x86_sse41_blendvpd:
23649 case Intrinsic::x86_sse41_pblendvb: {
23650 SDValue Op0 = N->getOperand(1);
23651 SDValue Op1 = N->getOperand(2);
23652 SDValue Mask = N->getOperand(3);
23654 // Don't try to simplify this intrinsic if we don't have SSE4.1.
23655 if (!Subtarget->hasSSE41())
23656 return SDValue();
23658 // fold (blend A, A, Mask) -> A
23659 if (Op0 == Op1)
23660 return Op0;
23661 // fold (blend A, B, allZeros) -> A
23662 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
23663 return Op0;
23664 // fold (blend A, B, allOnes) -> B
23665 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
23666 return Op1;
23668 // Simplify the case where the mask is a constant i32 value.
23669 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
23670 if (C->isNullValue())
23671 return Op0;
23672 if (C->isAllOnesValue())
23673 return Op1;
23674 }
23676 return SDValue();
23677 }
23679 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
23680 case Intrinsic::x86_sse2_psrai_w:
23681 case Intrinsic::x86_sse2_psrai_d:
23682 case Intrinsic::x86_avx2_psrai_w:
23683 case Intrinsic::x86_avx2_psrai_d:
23684 case Intrinsic::x86_sse2_psra_w:
23685 case Intrinsic::x86_sse2_psra_d:
23686 case Intrinsic::x86_avx2_psra_w:
23687 case Intrinsic::x86_avx2_psra_d: {
23688 SDValue Op0 = N->getOperand(1);
23689 SDValue Op1 = N->getOperand(2);
23690 EVT VT = Op0.getValueType();
23691 assert(VT.isVector() && "Expected a vector type!");
23693 if (isa<BuildVectorSDNode>(Op1))
23694 Op1 = Op1.getOperand(0);
23696 if (!isa<ConstantSDNode>(Op1))
23697 return SDValue();
23699 EVT SVT = VT.getVectorElementType();
23700 unsigned SVTBits = SVT.getSizeInBits();
23702 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
23703 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
23704 uint64_t ShAmt = C.getZExtValue();
23706 // Don't try to convert this shift into a ISD::SRA if the shift
23707 // count is bigger than or equal to the element size.
23708 if (ShAmt >= SVTBits)
23709 return SDValue();
23711 // Trivial case: if the shift count is zero, then fold this
23712 // into the first operand.
23713 if (ShAmt == 0)
23714 return Op0;
23716 // Replace this packed shift intrinsic with a target independent
23717 // shift dag node.
23718 SDValue Splat = DAG.getConstant(C, VT);
23719 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
23720 }
23721 }
23722 }
23724 /// PerformMulCombine - Optimize a single multiply with constant into two
23725 /// in order to implement it with two cheaper instructions, e.g.
23726 /// LEA + SHL, LEA + LEA.
23727 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
23728 TargetLowering::DAGCombinerInfo &DCI) {
23729 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
23730 return SDValue();
23732 EVT VT = N->getValueType(0);
23733 if (VT != MVT::i64)
23734 return SDValue();
23736 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
23737 if (!C)
23738 return SDValue();
23739 uint64_t MulAmt = C->getZExtValue();
23740 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
23741 return SDValue();
23743 uint64_t MulAmt1 = 0;
23744 uint64_t MulAmt2 = 0;
23745 if ((MulAmt % 9) == 0) {
23746 MulAmt1 = 9;
23747 MulAmt2 = MulAmt / 9;
23748 } else if ((MulAmt % 5) == 0) {
23749 MulAmt1 = 5;
23750 MulAmt2 = MulAmt / 5;
23751 } else if ((MulAmt % 3) == 0) {
23752 MulAmt1 = 3;
23753 MulAmt2 = MulAmt / 3;
23754 }
23755 if (MulAmt2 &&
23756 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
23757 SDLoc DL(N);
23759 if (isPowerOf2_64(MulAmt2) &&
23760 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
23761 // If second multiplifer is pow2, issue it first. We want the multiply by
23762 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
23763 // is an add.
23764 std::swap(MulAmt1, MulAmt2);
23766 SDValue NewMul;
23767 if (isPowerOf2_64(MulAmt1))
23768 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
23769 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
23770 else
23771 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
23772 DAG.getConstant(MulAmt1, VT));
23774 if (isPowerOf2_64(MulAmt2))
23775 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
23776 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
23777 else
23778 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
23779 DAG.getConstant(MulAmt2, VT));
23781 // Do not add new nodes to DAG combiner worklist.
23782 DCI.CombineTo(N, NewMul, false);
23783 }
23784 return SDValue();
23785 }
23787 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
23788 SDValue N0 = N->getOperand(0);
23789 SDValue N1 = N->getOperand(1);
23790 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
23791 EVT VT = N0.getValueType();
23793 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
23794 // since the result of setcc_c is all zero's or all ones.
23795 if (VT.isInteger() && !VT.isVector() &&
23796 N1C && N0.getOpcode() == ISD::AND &&
23797 N0.getOperand(1).getOpcode() == ISD::Constant) {
23798 SDValue N00 = N0.getOperand(0);
23799 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
23800 ((N00.getOpcode() == ISD::ANY_EXTEND ||
23801 N00.getOpcode() == ISD::ZERO_EXTEND) &&
23802 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
23803 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
23804 APInt ShAmt = N1C->getAPIntValue();
23805 Mask = Mask.shl(ShAmt);
23806 if (Mask != 0)
23807 return DAG.getNode(ISD::AND, SDLoc(N), VT,
23808 N00, DAG.getConstant(Mask, VT));
23809 }
23810 }
23812 // Hardware support for vector shifts is sparse which makes us scalarize the
23813 // vector operations in many cases. Also, on sandybridge ADD is faster than
23814 // shl.
23815 // (shl V, 1) -> add V,V
23816 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
23817 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
23818 assert(N0.getValueType().isVector() && "Invalid vector shift type");
23819 // We shift all of the values by one. In many cases we do not have
23820 // hardware support for this operation. This is better expressed as an ADD
23821 // of two values.
23822 if (N1SplatC->getZExtValue() == 1)
23823 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
23824 }
23826 return SDValue();
23827 }
23829 /// \brief Returns a vector of 0s if the node in input is a vector logical
23830 /// shift by a constant amount which is known to be bigger than or equal
23831 /// to the vector element size in bits.
23832 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
23833 const X86Subtarget *Subtarget) {
23834 EVT VT = N->getValueType(0);
23836 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
23837 (!Subtarget->hasInt256() ||
23838 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
23839 return SDValue();
23841 SDValue Amt = N->getOperand(1);
23842 SDLoc DL(N);
23843 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
23844 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
23845 APInt ShiftAmt = AmtSplat->getAPIntValue();
23846 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
23848 // SSE2/AVX2 logical shifts always return a vector of 0s
23849 // if the shift amount is bigger than or equal to
23850 // the element size. The constant shift amount will be
23851 // encoded as a 8-bit immediate.
23852 if (ShiftAmt.trunc(8).uge(MaxAmount))
23853 return getZeroVector(VT, Subtarget, DAG, DL);
23854 }
23856 return SDValue();
23857 }
23859 /// PerformShiftCombine - Combine shifts.
23860 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
23861 TargetLowering::DAGCombinerInfo &DCI,
23862 const X86Subtarget *Subtarget) {
23863 if (N->getOpcode() == ISD::SHL) {
23864 SDValue V = PerformSHLCombine(N, DAG);
23865 if (V.getNode()) return V;
23866 }
23868 if (N->getOpcode() != ISD::SRA) {
23869 // Try to fold this logical shift into a zero vector.
23870 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
23871 if (V.getNode()) return V;
23872 }
23874 return SDValue();
23875 }
23877 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
23878 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
23879 // and friends. Likewise for OR -> CMPNEQSS.
23880 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
23881 TargetLowering::DAGCombinerInfo &DCI,
23882 const X86Subtarget *Subtarget) {
23883 unsigned opcode;
23885 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
23886 // we're requiring SSE2 for both.
23887 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
23888 SDValue N0 = N->getOperand(0);
23889 SDValue N1 = N->getOperand(1);
23890 SDValue CMP0 = N0->getOperand(1);
23891 SDValue CMP1 = N1->getOperand(1);
23892 SDLoc DL(N);
23894 // The SETCCs should both refer to the same CMP.
23895 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
23896 return SDValue();
23898 SDValue CMP00 = CMP0->getOperand(0);
23899 SDValue CMP01 = CMP0->getOperand(1);
23900 EVT VT = CMP00.getValueType();
23902 if (VT == MVT::f32 || VT == MVT::f64) {
23903 bool ExpectingFlags = false;
23904 // Check for any users that want flags:
23905 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
23906 !ExpectingFlags && UI != UE; ++UI)
23907 switch (UI->getOpcode()) {
23908 default:
23909 case ISD::BR_CC:
23910 case ISD::BRCOND:
23911 case ISD::SELECT:
23912 ExpectingFlags = true;
23913 break;
23914 case ISD::CopyToReg:
23915 case ISD::SIGN_EXTEND:
23916 case ISD::ZERO_EXTEND:
23917 case ISD::ANY_EXTEND:
23918 break;
23919 }
23921 if (!ExpectingFlags) {
23922 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
23923 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
23925 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
23926 X86::CondCode tmp = cc0;
23927 cc0 = cc1;
23928 cc1 = tmp;
23929 }
23931 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
23932 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
23933 // FIXME: need symbolic constants for these magic numbers.
23934 // See X86ATTInstPrinter.cpp:printSSECC().
23935 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
23936 if (Subtarget->hasAVX512()) {
23937 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
23938 CMP01, DAG.getConstant(x86cc, MVT::i8));
23939 if (N->getValueType(0) != MVT::i1)
23940 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
23941 FSetCC);
23942 return FSetCC;
23943 }
23944 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
23945 CMP00.getValueType(), CMP00, CMP01,
23946 DAG.getConstant(x86cc, MVT::i8));
23948 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
23949 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
23951 if (is64BitFP && !Subtarget->is64Bit()) {
23952 // On a 32-bit target, we cannot bitcast the 64-bit float to a
23953 // 64-bit integer, since that's not a legal type. Since
23954 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
23955 // bits, but can do this little dance to extract the lowest 32 bits
23956 // and work with those going forward.
23957 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
23958 OnesOrZeroesF);
23959 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
23960 Vector64);
23961 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
23962 Vector32, DAG.getIntPtrConstant(0));
23963 IntVT = MVT::i32;
23964 }
23966 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
23967 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
23968 DAG.getConstant(1, IntVT));
23969 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
23970 return OneBitOfTruth;
23971 }
23972 }
23973 }
23974 }
23975 return SDValue();
23976 }
23978 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
23979 /// so it can be folded inside ANDNP.
23980 static bool CanFoldXORWithAllOnes(const SDNode *N) {
23981 EVT VT = N->getValueType(0);
23983 // Match direct AllOnes for 128 and 256-bit vectors
23984 if (ISD::isBuildVectorAllOnes(N))
23985 return true;
23987 // Look through a bit convert.
23988 if (N->getOpcode() == ISD::BITCAST)
23989 N = N->getOperand(0).getNode();
23991 // Sometimes the operand may come from a insert_subvector building a 256-bit
23992 // allones vector
23993 if (VT.is256BitVector() &&
23994 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
23995 SDValue V1 = N->getOperand(0);
23996 SDValue V2 = N->getOperand(1);
23998 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
23999 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
24000 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
24001 ISD::isBuildVectorAllOnes(V2.getNode()))
24002 return true;
24003 }
24005 return false;
24006 }
24008 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
24009 // register. In most cases we actually compare or select YMM-sized registers
24010 // and mixing the two types creates horrible code. This method optimizes
24011 // some of the transition sequences.
24012 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
24013 TargetLowering::DAGCombinerInfo &DCI,
24014 const X86Subtarget *Subtarget) {
24015 EVT VT = N->getValueType(0);
24016 if (!VT.is256BitVector())
24017 return SDValue();
24019 assert((N->getOpcode() == ISD::ANY_EXTEND ||
24020 N->getOpcode() == ISD::ZERO_EXTEND ||
24021 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
24023 SDValue Narrow = N->getOperand(0);
24024 EVT NarrowVT = Narrow->getValueType(0);
24025 if (!NarrowVT.is128BitVector())
24026 return SDValue();
24028 if (Narrow->getOpcode() != ISD::XOR &&
24029 Narrow->getOpcode() != ISD::AND &&
24030 Narrow->getOpcode() != ISD::OR)
24031 return SDValue();
24033 SDValue N0 = Narrow->getOperand(0);
24034 SDValue N1 = Narrow->getOperand(1);
24035 SDLoc DL(Narrow);
24037 // The Left side has to be a trunc.
24038 if (N0.getOpcode() != ISD::TRUNCATE)
24039 return SDValue();
24041 // The type of the truncated inputs.
24042 EVT WideVT = N0->getOperand(0)->getValueType(0);
24043 if (WideVT != VT)
24044 return SDValue();
24046 // The right side has to be a 'trunc' or a constant vector.
24047 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
24048 ConstantSDNode *RHSConstSplat = nullptr;
24049 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
24050 RHSConstSplat = RHSBV->getConstantSplatNode();
24051 if (!RHSTrunc && !RHSConstSplat)
24052 return SDValue();
24054 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24056 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
24057 return SDValue();
24059 // Set N0 and N1 to hold the inputs to the new wide operation.
24060 N0 = N0->getOperand(0);
24061 if (RHSConstSplat) {
24062 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
24063 SDValue(RHSConstSplat, 0));
24064 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
24065 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
24066 } else if (RHSTrunc) {
24067 N1 = N1->getOperand(0);
24068 }
24070 // Generate the wide operation.
24071 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
24072 unsigned Opcode = N->getOpcode();
24073 switch (Opcode) {
24074 case ISD::ANY_EXTEND:
24075 return Op;
24076 case ISD::ZERO_EXTEND: {
24077 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
24078 APInt Mask = APInt::getAllOnesValue(InBits);
24079 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
24080 return DAG.getNode(ISD::AND, DL, VT,
24081 Op, DAG.getConstant(Mask, VT));
24082 }
24083 case ISD::SIGN_EXTEND:
24084 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
24085 Op, DAG.getValueType(NarrowVT));
24086 default:
24087 llvm_unreachable("Unexpected opcode");
24088 }
24089 }
24091 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
24092 TargetLowering::DAGCombinerInfo &DCI,
24093 const X86Subtarget *Subtarget) {
24094 EVT VT = N->getValueType(0);
24095 if (DCI.isBeforeLegalizeOps())
24096 return SDValue();
24098 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24099 if (R.getNode())
24100 return R;
24102 // Create BEXTR instructions
24103 // BEXTR is ((X >> imm) & (2**size-1))
24104 if (VT == MVT::i32 || VT == MVT::i64) {
24105 SDValue N0 = N->getOperand(0);
24106 SDValue N1 = N->getOperand(1);
24107 SDLoc DL(N);
24109 // Check for BEXTR.
24110 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
24111 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
24112 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
24113 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24114 if (MaskNode && ShiftNode) {
24115 uint64_t Mask = MaskNode->getZExtValue();
24116 uint64_t Shift = ShiftNode->getZExtValue();
24117 if (isMask_64(Mask)) {
24118 uint64_t MaskSize = CountPopulation_64(Mask);
24119 if (Shift + MaskSize <= VT.getSizeInBits())
24120 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
24121 DAG.getConstant(Shift | (MaskSize << 8), VT));
24122 }
24123 }
24124 } // BEXTR
24126 return SDValue();
24127 }
24129 // Want to form ANDNP nodes:
24130 // 1) In the hopes of then easily combining them with OR and AND nodes
24131 // to form PBLEND/PSIGN.
24132 // 2) To match ANDN packed intrinsics
24133 if (VT != MVT::v2i64 && VT != MVT::v4i64)
24134 return SDValue();
24136 SDValue N0 = N->getOperand(0);
24137 SDValue N1 = N->getOperand(1);
24138 SDLoc DL(N);
24140 // Check LHS for vnot
24141 if (N0.getOpcode() == ISD::XOR &&
24142 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
24143 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
24144 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
24146 // Check RHS for vnot
24147 if (N1.getOpcode() == ISD::XOR &&
24148 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
24149 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
24150 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
24152 return SDValue();
24153 }
24155 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
24156 TargetLowering::DAGCombinerInfo &DCI,
24157 const X86Subtarget *Subtarget) {
24158 if (DCI.isBeforeLegalizeOps())
24159 return SDValue();
24161 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24162 if (R.getNode())
24163 return R;
24165 SDValue N0 = N->getOperand(0);
24166 SDValue N1 = N->getOperand(1);
24167 EVT VT = N->getValueType(0);
24169 // look for psign/blend
24170 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
24171 if (!Subtarget->hasSSSE3() ||
24172 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
24173 return SDValue();
24175 // Canonicalize pandn to RHS
24176 if (N0.getOpcode() == X86ISD::ANDNP)
24177 std::swap(N0, N1);
24178 // or (and (m, y), (pandn m, x))
24179 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
24180 SDValue Mask = N1.getOperand(0);
24181 SDValue X = N1.getOperand(1);
24182 SDValue Y;
24183 if (N0.getOperand(0) == Mask)
24184 Y = N0.getOperand(1);
24185 if (N0.getOperand(1) == Mask)
24186 Y = N0.getOperand(0);
24188 // Check to see if the mask appeared in both the AND and ANDNP and
24189 if (!Y.getNode())
24190 return SDValue();
24192 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
24193 // Look through mask bitcast.
24194 if (Mask.getOpcode() == ISD::BITCAST)
24195 Mask = Mask.getOperand(0);
24196 if (X.getOpcode() == ISD::BITCAST)
24197 X = X.getOperand(0);
24198 if (Y.getOpcode() == ISD::BITCAST)
24199 Y = Y.getOperand(0);
24201 EVT MaskVT = Mask.getValueType();
24203 // Validate that the Mask operand is a vector sra node.
24204 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
24205 // there is no psrai.b
24206 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
24207 unsigned SraAmt = ~0;
24208 if (Mask.getOpcode() == ISD::SRA) {
24209 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
24210 if (auto *AmtConst = AmtBV->getConstantSplatNode())
24211 SraAmt = AmtConst->getZExtValue();
24212 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
24213 SDValue SraC = Mask.getOperand(1);
24214 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
24215 }
24216 if ((SraAmt + 1) != EltBits)
24217 return SDValue();
24219 SDLoc DL(N);
24221 // Now we know we at least have a plendvb with the mask val. See if
24222 // we can form a psignb/w/d.
24223 // psign = x.type == y.type == mask.type && y = sub(0, x);
24224 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
24225 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
24226 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
24227 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
24228 "Unsupported VT for PSIGN");
24229 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
24230 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24231 }
24232 // PBLENDVB only available on SSE 4.1
24233 if (!Subtarget->hasSSE41())
24234 return SDValue();
24236 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
24238 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
24239 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
24240 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
24241 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
24242 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24243 }
24244 }
24246 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
24247 return SDValue();
24249 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
24250 MachineFunction &MF = DAG.getMachineFunction();
24251 bool OptForSize = MF.getFunction()->getAttributes().
24252 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
24254 // SHLD/SHRD instructions have lower register pressure, but on some
24255 // platforms they have higher latency than the equivalent
24256 // series of shifts/or that would otherwise be generated.
24257 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
24258 // have higher latencies and we are not optimizing for size.
24259 if (!OptForSize && Subtarget->isSHLDSlow())
24260 return SDValue();
24262 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
24263 std::swap(N0, N1);
24264 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
24265 return SDValue();
24266 if (!N0.hasOneUse() || !N1.hasOneUse())
24267 return SDValue();
24269 SDValue ShAmt0 = N0.getOperand(1);
24270 if (ShAmt0.getValueType() != MVT::i8)
24271 return SDValue();
24272 SDValue ShAmt1 = N1.getOperand(1);
24273 if (ShAmt1.getValueType() != MVT::i8)
24274 return SDValue();
24275 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
24276 ShAmt0 = ShAmt0.getOperand(0);
24277 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
24278 ShAmt1 = ShAmt1.getOperand(0);
24280 SDLoc DL(N);
24281 unsigned Opc = X86ISD::SHLD;
24282 SDValue Op0 = N0.getOperand(0);
24283 SDValue Op1 = N1.getOperand(0);
24284 if (ShAmt0.getOpcode() == ISD::SUB) {
24285 Opc = X86ISD::SHRD;
24286 std::swap(Op0, Op1);
24287 std::swap(ShAmt0, ShAmt1);
24288 }
24290 unsigned Bits = VT.getSizeInBits();
24291 if (ShAmt1.getOpcode() == ISD::SUB) {
24292 SDValue Sum = ShAmt1.getOperand(0);
24293 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
24294 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
24295 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
24296 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
24297 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
24298 return DAG.getNode(Opc, DL, VT,
24299 Op0, Op1,
24300 DAG.getNode(ISD::TRUNCATE, DL,
24301 MVT::i8, ShAmt0));
24302 }
24303 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
24304 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
24305 if (ShAmt0C &&
24306 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
24307 return DAG.getNode(Opc, DL, VT,
24308 N0.getOperand(0), N1.getOperand(0),
24309 DAG.getNode(ISD::TRUNCATE, DL,
24310 MVT::i8, ShAmt0));
24311 }
24313 return SDValue();
24314 }
24316 // Generate NEG and CMOV for integer abs.
24317 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
24318 EVT VT = N->getValueType(0);
24320 // Since X86 does not have CMOV for 8-bit integer, we don't convert
24321 // 8-bit integer abs to NEG and CMOV.
24322 if (VT.isInteger() && VT.getSizeInBits() == 8)
24323 return SDValue();
24325 SDValue N0 = N->getOperand(0);
24326 SDValue N1 = N->getOperand(1);
24327 SDLoc DL(N);
24329 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
24330 // and change it to SUB and CMOV.
24331 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
24332 N0.getOpcode() == ISD::ADD &&
24333 N0.getOperand(1) == N1 &&
24334 N1.getOpcode() == ISD::SRA &&
24335 N1.getOperand(0) == N0.getOperand(0))
24336 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
24337 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
24338 // Generate SUB & CMOV.
24339 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
24340 DAG.getConstant(0, VT), N0.getOperand(0));
24342 SDValue Ops[] = { N0.getOperand(0), Neg,
24343 DAG.getConstant(X86::COND_GE, MVT::i8),
24344 SDValue(Neg.getNode(), 1) };
24345 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
24346 }
24347 return SDValue();
24348 }
24350 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
24351 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
24352 TargetLowering::DAGCombinerInfo &DCI,
24353 const X86Subtarget *Subtarget) {
24354 if (DCI.isBeforeLegalizeOps())
24355 return SDValue();
24357 if (Subtarget->hasCMov()) {
24358 SDValue RV = performIntegerAbsCombine(N, DAG);
24359 if (RV.getNode())
24360 return RV;
24361 }
24363 return SDValue();
24364 }
24366 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
24367 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
24368 TargetLowering::DAGCombinerInfo &DCI,
24369 const X86Subtarget *Subtarget) {
24370 LoadSDNode *Ld = cast<LoadSDNode>(N);
24371 EVT RegVT = Ld->getValueType(0);
24372 EVT MemVT = Ld->getMemoryVT();
24373 SDLoc dl(Ld);
24374 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24376 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
24377 // into two 16-byte operations.
24378 ISD::LoadExtType Ext = Ld->getExtensionType();
24379 unsigned Alignment = Ld->getAlignment();
24380 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
24381 if (RegVT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
24382 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
24383 unsigned NumElems = RegVT.getVectorNumElements();
24384 if (NumElems < 2)
24385 return SDValue();
24387 SDValue Ptr = Ld->getBasePtr();
24388 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
24390 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
24391 NumElems/2);
24392 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24393 Ld->getPointerInfo(), Ld->isVolatile(),
24394 Ld->isNonTemporal(), Ld->isInvariant(),
24395 Alignment);
24396 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24397 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24398 Ld->getPointerInfo(), Ld->isVolatile(),
24399 Ld->isNonTemporal(), Ld->isInvariant(),
24400 std::min(16U, Alignment));
24401 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
24402 Load1.getValue(1),
24403 Load2.getValue(1));
24405 SDValue NewVec = DAG.getUNDEF(RegVT);
24406 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
24407 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
24408 return DCI.CombineTo(N, NewVec, TF, true);
24409 }
24411 return SDValue();
24412 }
24414 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
24415 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
24416 const X86Subtarget *Subtarget) {
24417 StoreSDNode *St = cast<StoreSDNode>(N);
24418 EVT VT = St->getValue().getValueType();
24419 EVT StVT = St->getMemoryVT();
24420 SDLoc dl(St);
24421 SDValue StoredVal = St->getOperand(1);
24422 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24424 // If we are saving a concatenation of two XMM registers and 32-byte stores
24425 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
24426 unsigned Alignment = St->getAlignment();
24427 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
24428 if (VT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
24429 StVT == VT && !IsAligned) {
24430 unsigned NumElems = VT.getVectorNumElements();
24431 if (NumElems < 2)
24432 return SDValue();
24434 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
24435 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
24437 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
24438 SDValue Ptr0 = St->getBasePtr();
24439 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
24441 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
24442 St->getPointerInfo(), St->isVolatile(),
24443 St->isNonTemporal(), Alignment);
24444 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
24445 St->getPointerInfo(), St->isVolatile(),
24446 St->isNonTemporal(),
24447 std::min(16U, Alignment));
24448 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
24449 }
24451 // Optimize trunc store (of multiple scalars) to shuffle and store.
24452 // First, pack all of the elements in one place. Next, store to memory
24453 // in fewer chunks.
24454 if (St->isTruncatingStore() && VT.isVector()) {
24455 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24456 unsigned NumElems = VT.getVectorNumElements();
24457 assert(StVT != VT && "Cannot truncate to the same type");
24458 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24459 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24461 // From, To sizes and ElemCount must be pow of two
24462 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
24463 // We are going to use the original vector elt for storing.
24464 // Accumulated smaller vector elements must be a multiple of the store size.
24465 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
24467 unsigned SizeRatio = FromSz / ToSz;
24469 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24471 // Create a type on which we perform the shuffle
24472 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24473 StVT.getScalarType(), NumElems*SizeRatio);
24475 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24477 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
24478 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
24479 for (unsigned i = 0; i != NumElems; ++i)
24480 ShuffleVec[i] = i * SizeRatio;
24482 // Can't shuffle using an illegal type.
24483 if (!TLI.isTypeLegal(WideVecVT))
24484 return SDValue();
24486 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
24487 DAG.getUNDEF(WideVecVT),
24488 &ShuffleVec[0]);
24489 // At this point all of the data is stored at the bottom of the
24490 // register. We now need to save it to mem.
24492 // Find the largest store unit
24493 MVT StoreType = MVT::i8;
24494 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
24495 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
24496 MVT Tp = (MVT::SimpleValueType)tp;
24497 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
24498 StoreType = Tp;
24499 }
24501 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
24502 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
24503 (64 <= NumElems * ToSz))
24504 StoreType = MVT::f64;
24506 // Bitcast the original vector into a vector of store-size units
24507 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
24508 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
24509 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
24510 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
24511 SmallVector<SDValue, 8> Chains;
24512 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
24513 TLI.getPointerTy());
24514 SDValue Ptr = St->getBasePtr();
24516 // Perform one or more big stores into memory.
24517 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
24518 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
24519 StoreType, ShuffWide,
24520 DAG.getIntPtrConstant(i));
24521 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
24522 St->getPointerInfo(), St->isVolatile(),
24523 St->isNonTemporal(), St->getAlignment());
24524 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24525 Chains.push_back(Ch);
24526 }
24528 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
24529 }
24531 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
24532 // the FP state in cases where an emms may be missing.
24533 // A preferable solution to the general problem is to figure out the right
24534 // places to insert EMMS. This qualifies as a quick hack.
24536 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
24537 if (VT.getSizeInBits() != 64)
24538 return SDValue();
24540 const Function *F = DAG.getMachineFunction().getFunction();
24541 bool NoImplicitFloatOps = F->getAttributes().
24542 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
24543 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
24544 && Subtarget->hasSSE2();
24545 if ((VT.isVector() ||
24546 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
24547 isa<LoadSDNode>(St->getValue()) &&
24548 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
24549 St->getChain().hasOneUse() && !St->isVolatile()) {
24550 SDNode* LdVal = St->getValue().getNode();
24551 LoadSDNode *Ld = nullptr;
24552 int TokenFactorIndex = -1;
24553 SmallVector<SDValue, 8> Ops;
24554 SDNode* ChainVal = St->getChain().getNode();
24555 // Must be a store of a load. We currently handle two cases: the load
24556 // is a direct child, and it's under an intervening TokenFactor. It is
24557 // possible to dig deeper under nested TokenFactors.
24558 if (ChainVal == LdVal)
24559 Ld = cast<LoadSDNode>(St->getChain());
24560 else if (St->getValue().hasOneUse() &&
24561 ChainVal->getOpcode() == ISD::TokenFactor) {
24562 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
24563 if (ChainVal->getOperand(i).getNode() == LdVal) {
24564 TokenFactorIndex = i;
24565 Ld = cast<LoadSDNode>(St->getValue());
24566 } else
24567 Ops.push_back(ChainVal->getOperand(i));
24568 }
24569 }
24571 if (!Ld || !ISD::isNormalLoad(Ld))
24572 return SDValue();
24574 // If this is not the MMX case, i.e. we are just turning i64 load/store
24575 // into f64 load/store, avoid the transformation if there are multiple
24576 // uses of the loaded value.
24577 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
24578 return SDValue();
24580 SDLoc LdDL(Ld);
24581 SDLoc StDL(N);
24582 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
24583 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
24584 // pair instead.
24585 if (Subtarget->is64Bit() || F64IsLegal) {
24586 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
24587 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
24588 Ld->getPointerInfo(), Ld->isVolatile(),
24589 Ld->isNonTemporal(), Ld->isInvariant(),
24590 Ld->getAlignment());
24591 SDValue NewChain = NewLd.getValue(1);
24592 if (TokenFactorIndex != -1) {
24593 Ops.push_back(NewChain);
24594 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24595 }
24596 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
24597 St->getPointerInfo(),
24598 St->isVolatile(), St->isNonTemporal(),
24599 St->getAlignment());
24600 }
24602 // Otherwise, lower to two pairs of 32-bit loads / stores.
24603 SDValue LoAddr = Ld->getBasePtr();
24604 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
24605 DAG.getConstant(4, MVT::i32));
24607 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
24608 Ld->getPointerInfo(),
24609 Ld->isVolatile(), Ld->isNonTemporal(),
24610 Ld->isInvariant(), Ld->getAlignment());
24611 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
24612 Ld->getPointerInfo().getWithOffset(4),
24613 Ld->isVolatile(), Ld->isNonTemporal(),
24614 Ld->isInvariant(),
24615 MinAlign(Ld->getAlignment(), 4));
24617 SDValue NewChain = LoLd.getValue(1);
24618 if (TokenFactorIndex != -1) {
24619 Ops.push_back(LoLd);
24620 Ops.push_back(HiLd);
24621 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24622 }
24624 LoAddr = St->getBasePtr();
24625 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
24626 DAG.getConstant(4, MVT::i32));
24628 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
24629 St->getPointerInfo(),
24630 St->isVolatile(), St->isNonTemporal(),
24631 St->getAlignment());
24632 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
24633 St->getPointerInfo().getWithOffset(4),
24634 St->isVolatile(),
24635 St->isNonTemporal(),
24636 MinAlign(St->getAlignment(), 4));
24637 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
24638 }
24639 return SDValue();
24640 }
24642 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
24643 /// and return the operands for the horizontal operation in LHS and RHS. A
24644 /// horizontal operation performs the binary operation on successive elements
24645 /// of its first operand, then on successive elements of its second operand,
24646 /// returning the resulting values in a vector. For example, if
24647 /// A = < float a0, float a1, float a2, float a3 >
24648 /// and
24649 /// B = < float b0, float b1, float b2, float b3 >
24650 /// then the result of doing a horizontal operation on A and B is
24651 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
24652 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
24653 /// A horizontal-op B, for some already available A and B, and if so then LHS is
24654 /// set to A, RHS to B, and the routine returns 'true'.
24655 /// Note that the binary operation should have the property that if one of the
24656 /// operands is UNDEF then the result is UNDEF.
24657 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
24658 // Look for the following pattern: if
24659 // A = < float a0, float a1, float a2, float a3 >
24660 // B = < float b0, float b1, float b2, float b3 >
24661 // and
24662 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
24663 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
24664 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
24665 // which is A horizontal-op B.
24667 // At least one of the operands should be a vector shuffle.
24668 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
24669 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
24670 return false;
24672 MVT VT = LHS.getSimpleValueType();
24674 assert((VT.is128BitVector() || VT.is256BitVector()) &&
24675 "Unsupported vector type for horizontal add/sub");
24677 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
24678 // operate independently on 128-bit lanes.
24679 unsigned NumElts = VT.getVectorNumElements();
24680 unsigned NumLanes = VT.getSizeInBits()/128;
24681 unsigned NumLaneElts = NumElts / NumLanes;
24682 assert((NumLaneElts % 2 == 0) &&
24683 "Vector type should have an even number of elements in each lane");
24684 unsigned HalfLaneElts = NumLaneElts/2;
24686 // View LHS in the form
24687 // LHS = VECTOR_SHUFFLE A, B, LMask
24688 // If LHS is not a shuffle then pretend it is the shuffle
24689 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
24690 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
24691 // type VT.
24692 SDValue A, B;
24693 SmallVector<int, 16> LMask(NumElts);
24694 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24695 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
24696 A = LHS.getOperand(0);
24697 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
24698 B = LHS.getOperand(1);
24699 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
24700 std::copy(Mask.begin(), Mask.end(), LMask.begin());
24701 } else {
24702 if (LHS.getOpcode() != ISD::UNDEF)
24703 A = LHS;
24704 for (unsigned i = 0; i != NumElts; ++i)
24705 LMask[i] = i;
24706 }
24708 // Likewise, view RHS in the form
24709 // RHS = VECTOR_SHUFFLE C, D, RMask
24710 SDValue C, D;
24711 SmallVector<int, 16> RMask(NumElts);
24712 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24713 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
24714 C = RHS.getOperand(0);
24715 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
24716 D = RHS.getOperand(1);
24717 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
24718 std::copy(Mask.begin(), Mask.end(), RMask.begin());
24719 } else {
24720 if (RHS.getOpcode() != ISD::UNDEF)
24721 C = RHS;
24722 for (unsigned i = 0; i != NumElts; ++i)
24723 RMask[i] = i;
24724 }
24726 // Check that the shuffles are both shuffling the same vectors.
24727 if (!(A == C && B == D) && !(A == D && B == C))
24728 return false;
24730 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
24731 if (!A.getNode() && !B.getNode())
24732 return false;
24734 // If A and B occur in reverse order in RHS, then "swap" them (which means
24735 // rewriting the mask).
24736 if (A != C)
24737 CommuteVectorShuffleMask(RMask, NumElts);
24739 // At this point LHS and RHS are equivalent to
24740 // LHS = VECTOR_SHUFFLE A, B, LMask
24741 // RHS = VECTOR_SHUFFLE A, B, RMask
24742 // Check that the masks correspond to performing a horizontal operation.
24743 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
24744 for (unsigned i = 0; i != NumLaneElts; ++i) {
24745 int LIdx = LMask[i+l], RIdx = RMask[i+l];
24747 // Ignore any UNDEF components.
24748 if (LIdx < 0 || RIdx < 0 ||
24749 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
24750 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
24751 continue;
24753 // Check that successive elements are being operated on. If not, this is
24754 // not a horizontal operation.
24755 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
24756 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
24757 if (!(LIdx == Index && RIdx == Index + 1) &&
24758 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
24759 return false;
24760 }
24761 }
24763 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
24764 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
24765 return true;
24766 }
24768 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
24769 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
24770 const X86Subtarget *Subtarget) {
24771 EVT VT = N->getValueType(0);
24772 SDValue LHS = N->getOperand(0);
24773 SDValue RHS = N->getOperand(1);
24775 // Try to synthesize horizontal adds from adds of shuffles.
24776 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24777 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24778 isHorizontalBinOp(LHS, RHS, true))
24779 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
24780 return SDValue();
24781 }
24783 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
24784 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
24785 const X86Subtarget *Subtarget) {
24786 EVT VT = N->getValueType(0);
24787 SDValue LHS = N->getOperand(0);
24788 SDValue RHS = N->getOperand(1);
24790 // Try to synthesize horizontal subs from subs of shuffles.
24791 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24792 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24793 isHorizontalBinOp(LHS, RHS, false))
24794 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
24795 return SDValue();
24796 }
24798 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
24799 /// X86ISD::FXOR nodes.
24800 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
24801 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
24802 // F[X]OR(0.0, x) -> x
24803 // F[X]OR(x, 0.0) -> x
24804 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24805 if (C->getValueAPF().isPosZero())
24806 return N->getOperand(1);
24807 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24808 if (C->getValueAPF().isPosZero())
24809 return N->getOperand(0);
24810 return SDValue();
24811 }
24813 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
24814 /// X86ISD::FMAX nodes.
24815 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
24816 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
24818 // Only perform optimizations if UnsafeMath is used.
24819 if (!DAG.getTarget().Options.UnsafeFPMath)
24820 return SDValue();
24822 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
24823 // into FMINC and FMAXC, which are Commutative operations.
24824 unsigned NewOp = 0;
24825 switch (N->getOpcode()) {
24826 default: llvm_unreachable("unknown opcode");
24827 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
24828 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
24829 }
24831 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
24832 N->getOperand(0), N->getOperand(1));
24833 }
24835 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
24836 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
24837 // FAND(0.0, x) -> 0.0
24838 // FAND(x, 0.0) -> 0.0
24839 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24840 if (C->getValueAPF().isPosZero())
24841 return N->getOperand(0);
24842 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24843 if (C->getValueAPF().isPosZero())
24844 return N->getOperand(1);
24845 return SDValue();
24846 }
24848 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
24849 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
24850 // FANDN(x, 0.0) -> 0.0
24851 // FANDN(0.0, x) -> x
24852 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24853 if (C->getValueAPF().isPosZero())
24854 return N->getOperand(1);
24855 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24856 if (C->getValueAPF().isPosZero())
24857 return N->getOperand(1);
24858 return SDValue();
24859 }
24861 static SDValue PerformBTCombine(SDNode *N,
24862 SelectionDAG &DAG,
24863 TargetLowering::DAGCombinerInfo &DCI) {
24864 // BT ignores high bits in the bit index operand.
24865 SDValue Op1 = N->getOperand(1);
24866 if (Op1.hasOneUse()) {
24867 unsigned BitWidth = Op1.getValueSizeInBits();
24868 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
24869 APInt KnownZero, KnownOne;
24870 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
24871 !DCI.isBeforeLegalizeOps());
24872 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24873 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
24874 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
24875 DCI.CommitTargetLoweringOpt(TLO);
24876 }
24877 return SDValue();
24878 }
24880 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
24881 SDValue Op = N->getOperand(0);
24882 if (Op.getOpcode() == ISD::BITCAST)
24883 Op = Op.getOperand(0);
24884 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
24885 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
24886 VT.getVectorElementType().getSizeInBits() ==
24887 OpVT.getVectorElementType().getSizeInBits()) {
24888 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
24889 }
24890 return SDValue();
24891 }
24893 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
24894 const X86Subtarget *Subtarget) {
24895 EVT VT = N->getValueType(0);
24896 if (!VT.isVector())
24897 return SDValue();
24899 SDValue N0 = N->getOperand(0);
24900 SDValue N1 = N->getOperand(1);
24901 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
24902 SDLoc dl(N);
24904 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
24905 // both SSE and AVX2 since there is no sign-extended shift right
24906 // operation on a vector with 64-bit elements.
24907 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
24908 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
24909 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
24910 N0.getOpcode() == ISD::SIGN_EXTEND)) {
24911 SDValue N00 = N0.getOperand(0);
24913 // EXTLOAD has a better solution on AVX2,
24914 // it may be replaced with X86ISD::VSEXT node.
24915 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
24916 if (!ISD::isNormalLoad(N00.getNode()))
24917 return SDValue();
24919 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
24920 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
24921 N00, N1);
24922 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
24923 }
24924 }
24925 return SDValue();
24926 }
24928 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
24929 TargetLowering::DAGCombinerInfo &DCI,
24930 const X86Subtarget *Subtarget) {
24931 SDValue N0 = N->getOperand(0);
24932 EVT VT = N->getValueType(0);
24934 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
24935 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
24936 // This exposes the sext to the sdivrem lowering, so that it directly extends
24937 // from AH (which we otherwise need to do contortions to access).
24938 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
24939 N0.getValueType() == MVT::i8 && VT == MVT::i32) {
24940 SDLoc dl(N);
24941 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24942 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, dl, NodeTys,
24943 N0.getOperand(0), N0.getOperand(1));
24944 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24945 return R.getValue(1);
24946 }
24948 if (!DCI.isBeforeLegalizeOps())
24949 return SDValue();
24951 if (!Subtarget->hasFp256())
24952 return SDValue();
24954 if (VT.isVector() && VT.getSizeInBits() == 256) {
24955 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24956 if (R.getNode())
24957 return R;
24958 }
24960 return SDValue();
24961 }
24963 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
24964 const X86Subtarget* Subtarget) {
24965 SDLoc dl(N);
24966 EVT VT = N->getValueType(0);
24968 // Let legalize expand this if it isn't a legal type yet.
24969 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
24970 return SDValue();
24972 EVT ScalarVT = VT.getScalarType();
24973 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
24974 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
24975 return SDValue();
24977 SDValue A = N->getOperand(0);
24978 SDValue B = N->getOperand(1);
24979 SDValue C = N->getOperand(2);
24981 bool NegA = (A.getOpcode() == ISD::FNEG);
24982 bool NegB = (B.getOpcode() == ISD::FNEG);
24983 bool NegC = (C.getOpcode() == ISD::FNEG);
24985 // Negative multiplication when NegA xor NegB
24986 bool NegMul = (NegA != NegB);
24987 if (NegA)
24988 A = A.getOperand(0);
24989 if (NegB)
24990 B = B.getOperand(0);
24991 if (NegC)
24992 C = C.getOperand(0);
24994 unsigned Opcode;
24995 if (!NegMul)
24996 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
24997 else
24998 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
25000 return DAG.getNode(Opcode, dl, VT, A, B, C);
25001 }
25003 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
25004 TargetLowering::DAGCombinerInfo &DCI,
25005 const X86Subtarget *Subtarget) {
25006 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
25007 // (and (i32 x86isd::setcc_carry), 1)
25008 // This eliminates the zext. This transformation is necessary because
25009 // ISD::SETCC is always legalized to i8.
25010 SDLoc dl(N);
25011 SDValue N0 = N->getOperand(0);
25012 EVT VT = N->getValueType(0);
25014 if (N0.getOpcode() == ISD::AND &&
25015 N0.hasOneUse() &&
25016 N0.getOperand(0).hasOneUse()) {
25017 SDValue N00 = N0.getOperand(0);
25018 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25019 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
25020 if (!C || C->getZExtValue() != 1)
25021 return SDValue();
25022 return DAG.getNode(ISD::AND, dl, VT,
25023 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25024 N00.getOperand(0), N00.getOperand(1)),
25025 DAG.getConstant(1, VT));
25026 }
25027 }
25029 if (N0.getOpcode() == ISD::TRUNCATE &&
25030 N0.hasOneUse() &&
25031 N0.getOperand(0).hasOneUse()) {
25032 SDValue N00 = N0.getOperand(0);
25033 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25034 return DAG.getNode(ISD::AND, dl, VT,
25035 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25036 N00.getOperand(0), N00.getOperand(1)),
25037 DAG.getConstant(1, VT));
25038 }
25039 }
25040 if (VT.is256BitVector()) {
25041 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
25042 if (R.getNode())
25043 return R;
25044 }
25046 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
25047 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
25048 // This exposes the zext to the udivrem lowering, so that it directly extends
25049 // from AH (which we otherwise need to do contortions to access).
25050 if (N0.getOpcode() == ISD::UDIVREM &&
25051 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
25052 (VT == MVT::i32 || VT == MVT::i64)) {
25053 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25054 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
25055 N0.getOperand(0), N0.getOperand(1));
25056 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25057 return R.getValue(1);
25058 }
25060 return SDValue();
25061 }
25063 // Optimize x == -y --> x+y == 0
25064 // x != -y --> x+y != 0
25065 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
25066 const X86Subtarget* Subtarget) {
25067 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
25068 SDValue LHS = N->getOperand(0);
25069 SDValue RHS = N->getOperand(1);
25070 EVT VT = N->getValueType(0);
25071 SDLoc DL(N);
25073 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
25074 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
25075 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
25076 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
25077 LHS.getValueType(), RHS, LHS.getOperand(1));
25078 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
25079 addV, DAG.getConstant(0, addV.getValueType()), CC);
25080 }
25081 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
25082 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
25083 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
25084 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
25085 RHS.getValueType(), LHS, RHS.getOperand(1));
25086 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
25087 addV, DAG.getConstant(0, addV.getValueType()), CC);
25088 }
25090 if (VT.getScalarType() == MVT::i1) {
25091 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
25092 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25093 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
25094 if (!IsSEXT0 && !IsVZero0)
25095 return SDValue();
25096 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
25097 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25098 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
25100 if (!IsSEXT1 && !IsVZero1)
25101 return SDValue();
25103 if (IsSEXT0 && IsVZero1) {
25104 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
25105 if (CC == ISD::SETEQ)
25106 return DAG.getNOT(DL, LHS.getOperand(0), VT);
25107 return LHS.getOperand(0);
25108 }
25109 if (IsSEXT1 && IsVZero0) {
25110 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
25111 if (CC == ISD::SETEQ)
25112 return DAG.getNOT(DL, RHS.getOperand(0), VT);
25113 return RHS.getOperand(0);
25114 }
25115 }
25117 return SDValue();
25118 }
25120 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
25121 const X86Subtarget *Subtarget) {
25122 SDLoc dl(N);
25123 MVT VT = N->getOperand(1)->getSimpleValueType(0);
25124 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
25125 "X86insertps is only defined for v4x32");
25127 SDValue Ld = N->getOperand(1);
25128 if (MayFoldLoad(Ld)) {
25129 // Extract the countS bits from the immediate so we can get the proper
25130 // address when narrowing the vector load to a specific element.
25131 // When the second source op is a memory address, interps doesn't use
25132 // countS and just gets an f32 from that address.
25133 unsigned DestIndex =
25134 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
25135 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
25136 } else
25137 return SDValue();
25139 // Create this as a scalar to vector to match the instruction pattern.
25140 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
25141 // countS bits are ignored when loading from memory on insertps, which
25142 // means we don't need to explicitly set them to 0.
25143 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
25144 LoadScalarToVector, N->getOperand(2));
25145 }
25147 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
25148 // as "sbb reg,reg", since it can be extended without zext and produces
25149 // an all-ones bit which is more useful than 0/1 in some cases.
25150 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
25151 MVT VT) {
25152 if (VT == MVT::i8)
25153 return DAG.getNode(ISD::AND, DL, VT,
25154 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25155 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
25156 DAG.getConstant(1, VT));
25157 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
25158 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
25159 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25160 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
25161 }
25163 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
25164 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
25165 TargetLowering::DAGCombinerInfo &DCI,
25166 const X86Subtarget *Subtarget) {
25167 SDLoc DL(N);
25168 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
25169 SDValue EFLAGS = N->getOperand(1);
25171 if (CC == X86::COND_A) {
25172 // Try to convert COND_A into COND_B in an attempt to facilitate
25173 // materializing "setb reg".
25174 //
25175 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
25176 // cannot take an immediate as its first operand.
25177 //
25178 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
25179 EFLAGS.getValueType().isInteger() &&
25180 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
25181 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
25182 EFLAGS.getNode()->getVTList(),
25183 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
25184 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
25185 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
25186 }
25187 }
25189 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
25190 // a zext and produces an all-ones bit which is more useful than 0/1 in some
25191 // cases.
25192 if (CC == X86::COND_B)
25193 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
25195 SDValue Flags;
25197 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25198 if (Flags.getNode()) {
25199 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25200 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
25201 }
25203 return SDValue();
25204 }
25206 // Optimize branch condition evaluation.
25207 //
25208 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
25209 TargetLowering::DAGCombinerInfo &DCI,
25210 const X86Subtarget *Subtarget) {
25211 SDLoc DL(N);
25212 SDValue Chain = N->getOperand(0);
25213 SDValue Dest = N->getOperand(1);
25214 SDValue EFLAGS = N->getOperand(3);
25215 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
25217 SDValue Flags;
25219 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25220 if (Flags.getNode()) {
25221 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25222 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
25223 Flags);
25224 }
25226 return SDValue();
25227 }
25229 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
25230 SelectionDAG &DAG) {
25231 // Take advantage of vector comparisons producing 0 or -1 in each lane to
25232 // optimize away operation when it's from a constant.
25233 //
25234 // The general transformation is:
25235 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
25236 // AND(VECTOR_CMP(x,y), constant2)
25237 // constant2 = UNARYOP(constant)
25239 // Early exit if this isn't a vector operation, the operand of the
25240 // unary operation isn't a bitwise AND, or if the sizes of the operations
25241 // aren't the same.
25242 EVT VT = N->getValueType(0);
25243 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
25244 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
25245 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
25246 return SDValue();
25248 // Now check that the other operand of the AND is a constant. We could
25249 // make the transformation for non-constant splats as well, but it's unclear
25250 // that would be a benefit as it would not eliminate any operations, just
25251 // perform one more step in scalar code before moving to the vector unit.
25252 if (BuildVectorSDNode *BV =
25253 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
25254 // Bail out if the vector isn't a constant.
25255 if (!BV->isConstant())
25256 return SDValue();
25258 // Everything checks out. Build up the new and improved node.
25259 SDLoc DL(N);
25260 EVT IntVT = BV->getValueType(0);
25261 // Create a new constant of the appropriate type for the transformed
25262 // DAG.
25263 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
25264 // The AND node needs bitcasts to/from an integer vector type around it.
25265 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
25266 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
25267 N->getOperand(0)->getOperand(0), MaskConst);
25268 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
25269 return Res;
25270 }
25272 return SDValue();
25273 }
25275 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
25276 const X86TargetLowering *XTLI) {
25277 // First try to optimize away the conversion entirely when it's
25278 // conditionally from a constant. Vectors only.
25279 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
25280 if (Res != SDValue())
25281 return Res;
25283 // Now move on to more general possibilities.
25284 SDValue Op0 = N->getOperand(0);
25285 EVT InVT = Op0->getValueType(0);
25287 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
25288 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
25289 SDLoc dl(N);
25290 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
25291 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
25292 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
25293 }
25295 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
25296 // a 32-bit target where SSE doesn't support i64->FP operations.
25297 if (Op0.getOpcode() == ISD::LOAD) {
25298 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
25299 EVT VT = Ld->getValueType(0);
25300 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
25301 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
25302 !XTLI->getSubtarget()->is64Bit() &&
25303 VT == MVT::i64) {
25304 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
25305 Ld->getChain(), Op0, DAG);
25306 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
25307 return FILDChain;
25308 }
25309 }
25310 return SDValue();
25311 }
25313 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
25314 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
25315 X86TargetLowering::DAGCombinerInfo &DCI) {
25316 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
25317 // the result is either zero or one (depending on the input carry bit).
25318 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
25319 if (X86::isZeroNode(N->getOperand(0)) &&
25320 X86::isZeroNode(N->getOperand(1)) &&
25321 // We don't have a good way to replace an EFLAGS use, so only do this when
25322 // dead right now.
25323 SDValue(N, 1).use_empty()) {
25324 SDLoc DL(N);
25325 EVT VT = N->getValueType(0);
25326 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
25327 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
25328 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
25329 DAG.getConstant(X86::COND_B,MVT::i8),
25330 N->getOperand(2)),
25331 DAG.getConstant(1, VT));
25332 return DCI.CombineTo(N, Res1, CarryOut);
25333 }
25335 return SDValue();
25336 }
25338 // fold (add Y, (sete X, 0)) -> adc 0, Y
25339 // (add Y, (setne X, 0)) -> sbb -1, Y
25340 // (sub (sete X, 0), Y) -> sbb 0, Y
25341 // (sub (setne X, 0), Y) -> adc -1, Y
25342 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
25343 SDLoc DL(N);
25345 // Look through ZExts.
25346 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
25347 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
25348 return SDValue();
25350 SDValue SetCC = Ext.getOperand(0);
25351 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
25352 return SDValue();
25354 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
25355 if (CC != X86::COND_E && CC != X86::COND_NE)
25356 return SDValue();
25358 SDValue Cmp = SetCC.getOperand(1);
25359 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
25360 !X86::isZeroNode(Cmp.getOperand(1)) ||
25361 !Cmp.getOperand(0).getValueType().isInteger())
25362 return SDValue();
25364 SDValue CmpOp0 = Cmp.getOperand(0);
25365 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
25366 DAG.getConstant(1, CmpOp0.getValueType()));
25368 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
25369 if (CC == X86::COND_NE)
25370 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
25371 DL, OtherVal.getValueType(), OtherVal,
25372 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
25373 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
25374 DL, OtherVal.getValueType(), OtherVal,
25375 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
25376 }
25378 /// PerformADDCombine - Do target-specific dag combines on integer adds.
25379 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
25380 const X86Subtarget *Subtarget) {
25381 EVT VT = N->getValueType(0);
25382 SDValue Op0 = N->getOperand(0);
25383 SDValue Op1 = N->getOperand(1);
25385 // Try to synthesize horizontal adds from adds of shuffles.
25386 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25387 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25388 isHorizontalBinOp(Op0, Op1, true))
25389 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
25391 return OptimizeConditionalInDecrement(N, DAG);
25392 }
25394 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
25395 const X86Subtarget *Subtarget) {
25396 SDValue Op0 = N->getOperand(0);
25397 SDValue Op1 = N->getOperand(1);
25399 // X86 can't encode an immediate LHS of a sub. See if we can push the
25400 // negation into a preceding instruction.
25401 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
25402 // If the RHS of the sub is a XOR with one use and a constant, invert the
25403 // immediate. Then add one to the LHS of the sub so we can turn
25404 // X-Y -> X+~Y+1, saving one register.
25405 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
25406 isa<ConstantSDNode>(Op1.getOperand(1))) {
25407 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
25408 EVT VT = Op0.getValueType();
25409 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
25410 Op1.getOperand(0),
25411 DAG.getConstant(~XorC, VT));
25412 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
25413 DAG.getConstant(C->getAPIntValue()+1, VT));
25414 }
25415 }
25417 // Try to synthesize horizontal adds from adds of shuffles.
25418 EVT VT = N->getValueType(0);
25419 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25420 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25421 isHorizontalBinOp(Op0, Op1, true))
25422 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
25424 return OptimizeConditionalInDecrement(N, DAG);
25425 }
25427 /// performVZEXTCombine - Performs build vector combines
25428 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
25429 TargetLowering::DAGCombinerInfo &DCI,
25430 const X86Subtarget *Subtarget) {
25431 SDLoc DL(N);
25432 MVT VT = N->getSimpleValueType(0);
25433 SDValue Op = N->getOperand(0);
25434 MVT OpVT = Op.getSimpleValueType();
25435 MVT OpEltVT = OpVT.getVectorElementType();
25436 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
25438 // (vzext (bitcast (vzext (x)) -> (vzext x)
25439 SDValue V = Op;
25440 while (V.getOpcode() == ISD::BITCAST)
25441 V = V.getOperand(0);
25443 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
25444 MVT InnerVT = V.getSimpleValueType();
25445 MVT InnerEltVT = InnerVT.getVectorElementType();
25447 // If the element sizes match exactly, we can just do one larger vzext. This
25448 // is always an exact type match as vzext operates on integer types.
25449 if (OpEltVT == InnerEltVT) {
25450 assert(OpVT == InnerVT && "Types must match for vzext!");
25451 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
25452 }
25454 // The only other way we can combine them is if only a single element of the
25455 // inner vzext is used in the input to the outer vzext.
25456 if (InnerEltVT.getSizeInBits() < InputBits)
25457 return SDValue();
25459 // In this case, the inner vzext is completely dead because we're going to
25460 // only look at bits inside of the low element. Just do the outer vzext on
25461 // a bitcast of the input to the inner.
25462 return DAG.getNode(X86ISD::VZEXT, DL, VT,
25463 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
25464 }
25466 // Check if we can bypass extracting and re-inserting an element of an input
25467 // vector. Essentialy:
25468 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
25469 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
25470 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
25471 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
25472 SDValue ExtractedV = V.getOperand(0);
25473 SDValue OrigV = ExtractedV.getOperand(0);
25474 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
25475 if (ExtractIdx->getZExtValue() == 0) {
25476 MVT OrigVT = OrigV.getSimpleValueType();
25477 // Extract a subvector if necessary...
25478 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
25479 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
25480 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
25481 OrigVT.getVectorNumElements() / Ratio);
25482 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
25483 DAG.getIntPtrConstant(0));
25484 }
25485 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
25486 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
25487 }
25488 }
25490 return SDValue();
25491 }
25493 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
25494 DAGCombinerInfo &DCI) const {
25495 SelectionDAG &DAG = DCI.DAG;
25496 switch (N->getOpcode()) {
25497 default: break;
25498 case ISD::EXTRACT_VECTOR_ELT:
25499 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
25500 case ISD::VSELECT:
25501 case ISD::SELECT:
25502 case X86ISD::SHRUNKBLEND:
25503 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
25504 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
25505 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
25506 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
25507 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
25508 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
25509 case ISD::SHL:
25510 case ISD::SRA:
25511 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
25512 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
25513 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
25514 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
25515 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
25516 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
25517 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
25518 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
25519 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
25520 case X86ISD::FXOR:
25521 case X86ISD::FOR: return PerformFORCombine(N, DAG);
25522 case X86ISD::FMIN:
25523 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
25524 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
25525 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
25526 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
25527 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
25528 case ISD::ANY_EXTEND:
25529 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
25530 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
25531 case ISD::SIGN_EXTEND_INREG:
25532 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
25533 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
25534 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
25535 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
25536 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
25537 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
25538 case X86ISD::SHUFP: // Handle all target specific shuffles
25539 case X86ISD::PALIGNR:
25540 case X86ISD::UNPCKH:
25541 case X86ISD::UNPCKL:
25542 case X86ISD::MOVHLPS:
25543 case X86ISD::MOVLHPS:
25544 case X86ISD::PSHUFB:
25545 case X86ISD::PSHUFD:
25546 case X86ISD::PSHUFHW:
25547 case X86ISD::PSHUFLW:
25548 case X86ISD::MOVSS:
25549 case X86ISD::MOVSD:
25550 case X86ISD::VPERMILPI:
25551 case X86ISD::VPERM2X128:
25552 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
25553 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
25554 case ISD::INTRINSIC_WO_CHAIN:
25555 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
25556 case X86ISD::INSERTPS:
25557 return PerformINSERTPSCombine(N, DAG, Subtarget);
25558 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
25559 }
25561 return SDValue();
25562 }
25564 /// isTypeDesirableForOp - Return true if the target has native support for
25565 /// the specified value type and it is 'desirable' to use the type for the
25566 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
25567 /// instruction encodings are longer and some i16 instructions are slow.
25568 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
25569 if (!isTypeLegal(VT))
25570 return false;
25571 if (VT != MVT::i16)
25572 return true;
25574 switch (Opc) {
25575 default:
25576 return true;
25577 case ISD::LOAD:
25578 case ISD::SIGN_EXTEND:
25579 case ISD::ZERO_EXTEND:
25580 case ISD::ANY_EXTEND:
25581 case ISD::SHL:
25582 case ISD::SRL:
25583 case ISD::SUB:
25584 case ISD::ADD:
25585 case ISD::MUL:
25586 case ISD::AND:
25587 case ISD::OR:
25588 case ISD::XOR:
25589 return false;
25590 }
25591 }
25593 /// IsDesirableToPromoteOp - This method query the target whether it is
25594 /// beneficial for dag combiner to promote the specified node. If true, it
25595 /// should return the desired promotion type by reference.
25596 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
25597 EVT VT = Op.getValueType();
25598 if (VT != MVT::i16)
25599 return false;
25601 bool Promote = false;
25602 bool Commute = false;
25603 switch (Op.getOpcode()) {
25604 default: break;
25605 case ISD::LOAD: {
25606 LoadSDNode *LD = cast<LoadSDNode>(Op);
25607 // If the non-extending load has a single use and it's not live out, then it
25608 // might be folded.
25609 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
25610 Op.hasOneUse()*/) {
25611 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
25612 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
25613 // The only case where we'd want to promote LOAD (rather then it being
25614 // promoted as an operand is when it's only use is liveout.
25615 if (UI->getOpcode() != ISD::CopyToReg)
25616 return false;
25617 }
25618 }
25619 Promote = true;
25620 break;
25621 }
25622 case ISD::SIGN_EXTEND:
25623 case ISD::ZERO_EXTEND:
25624 case ISD::ANY_EXTEND:
25625 Promote = true;
25626 break;
25627 case ISD::SHL:
25628 case ISD::SRL: {
25629 SDValue N0 = Op.getOperand(0);
25630 // Look out for (store (shl (load), x)).
25631 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
25632 return false;
25633 Promote = true;
25634 break;
25635 }
25636 case ISD::ADD:
25637 case ISD::MUL:
25638 case ISD::AND:
25639 case ISD::OR:
25640 case ISD::XOR:
25641 Commute = true;
25642 // fallthrough
25643 case ISD::SUB: {
25644 SDValue N0 = Op.getOperand(0);
25645 SDValue N1 = Op.getOperand(1);
25646 if (!Commute && MayFoldLoad(N1))
25647 return false;
25648 // Avoid disabling potential load folding opportunities.
25649 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
25650 return false;
25651 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
25652 return false;
25653 Promote = true;
25654 }
25655 }
25657 PVT = MVT::i32;
25658 return Promote;
25659 }
25661 //===----------------------------------------------------------------------===//
25662 // X86 Inline Assembly Support
25663 //===----------------------------------------------------------------------===//
25665 namespace {
25666 // Helper to match a string separated by whitespace.
25667 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
25668 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
25670 for (unsigned i = 0, e = args.size(); i != e; ++i) {
25671 StringRef piece(*args[i]);
25672 if (!s.startswith(piece)) // Check if the piece matches.
25673 return false;
25675 s = s.substr(piece.size());
25676 StringRef::size_type pos = s.find_first_not_of(" \t");
25677 if (pos == 0) // We matched a prefix.
25678 return false;
25680 s = s.substr(pos);
25681 }
25683 return s.empty();
25684 }
25685 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
25686 }
25688 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
25690 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
25691 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
25692 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
25693 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
25695 if (AsmPieces.size() == 3)
25696 return true;
25697 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
25698 return true;
25699 }
25700 }
25701 return false;
25702 }
25704 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
25705 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
25707 std::string AsmStr = IA->getAsmString();
25709 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
25710 if (!Ty || Ty->getBitWidth() % 16 != 0)
25711 return false;
25713 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
25714 SmallVector<StringRef, 4> AsmPieces;
25715 SplitString(AsmStr, AsmPieces, ";\n");
25717 switch (AsmPieces.size()) {
25718 default: return false;
25719 case 1:
25720 // FIXME: this should verify that we are targeting a 486 or better. If not,
25721 // we will turn this bswap into something that will be lowered to logical
25722 // ops instead of emitting the bswap asm. For now, we don't support 486 or
25723 // lower so don't worry about this.
25724 // bswap $0
25725 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
25726 matchAsm(AsmPieces[0], "bswapl", "$0") ||
25727 matchAsm(AsmPieces[0], "bswapq", "$0") ||
25728 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
25729 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
25730 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
25731 // No need to check constraints, nothing other than the equivalent of
25732 // "=r,0" would be valid here.
25733 return IntrinsicLowering::LowerToByteSwap(CI);
25734 }
25736 // rorw $$8, ${0:w} --> llvm.bswap.i16
25737 if (CI->getType()->isIntegerTy(16) &&
25738 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25739 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
25740 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
25741 AsmPieces.clear();
25742 const std::string &ConstraintsStr = IA->getConstraintString();
25743 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25744 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25745 if (clobbersFlagRegisters(AsmPieces))
25746 return IntrinsicLowering::LowerToByteSwap(CI);
25747 }
25748 break;
25749 case 3:
25750 if (CI->getType()->isIntegerTy(32) &&
25751 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25752 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
25753 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
25754 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
25755 AsmPieces.clear();
25756 const std::string &ConstraintsStr = IA->getConstraintString();
25757 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25758 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25759 if (clobbersFlagRegisters(AsmPieces))
25760 return IntrinsicLowering::LowerToByteSwap(CI);
25761 }
25763 if (CI->getType()->isIntegerTy(64)) {
25764 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
25765 if (Constraints.size() >= 2 &&
25766 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
25767 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
25768 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
25769 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
25770 matchAsm(AsmPieces[1], "bswap", "%edx") &&
25771 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
25772 return IntrinsicLowering::LowerToByteSwap(CI);
25773 }
25774 }
25775 break;
25776 }
25777 return false;
25778 }
25780 /// getConstraintType - Given a constraint letter, return the type of
25781 /// constraint it is for this target.
25782 X86TargetLowering::ConstraintType
25783 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
25784 if (Constraint.size() == 1) {
25785 switch (Constraint[0]) {
25786 case 'R':
25787 case 'q':
25788 case 'Q':
25789 case 'f':
25790 case 't':
25791 case 'u':
25792 case 'y':
25793 case 'x':
25794 case 'Y':
25795 case 'l':
25796 return C_RegisterClass;
25797 case 'a':
25798 case 'b':
25799 case 'c':
25800 case 'd':
25801 case 'S':
25802 case 'D':
25803 case 'A':
25804 return C_Register;
25805 case 'I':
25806 case 'J':
25807 case 'K':
25808 case 'L':
25809 case 'M':
25810 case 'N':
25811 case 'G':
25812 case 'C':
25813 case 'e':
25814 case 'Z':
25815 return C_Other;
25816 default:
25817 break;
25818 }
25819 }
25820 return TargetLowering::getConstraintType(Constraint);
25821 }
25823 /// Examine constraint type and operand type and determine a weight value.
25824 /// This object must already have been set up with the operand type
25825 /// and the current alternative constraint selected.
25826 TargetLowering::ConstraintWeight
25827 X86TargetLowering::getSingleConstraintMatchWeight(
25828 AsmOperandInfo &info, const char *constraint) const {
25829 ConstraintWeight weight = CW_Invalid;
25830 Value *CallOperandVal = info.CallOperandVal;
25831 // If we don't have a value, we can't do a match,
25832 // but allow it at the lowest weight.
25833 if (!CallOperandVal)
25834 return CW_Default;
25835 Type *type = CallOperandVal->getType();
25836 // Look at the constraint type.
25837 switch (*constraint) {
25838 default:
25839 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
25840 case 'R':
25841 case 'q':
25842 case 'Q':
25843 case 'a':
25844 case 'b':
25845 case 'c':
25846 case 'd':
25847 case 'S':
25848 case 'D':
25849 case 'A':
25850 if (CallOperandVal->getType()->isIntegerTy())
25851 weight = CW_SpecificReg;
25852 break;
25853 case 'f':
25854 case 't':
25855 case 'u':
25856 if (type->isFloatingPointTy())
25857 weight = CW_SpecificReg;
25858 break;
25859 case 'y':
25860 if (type->isX86_MMXTy() && Subtarget->hasMMX())
25861 weight = CW_SpecificReg;
25862 break;
25863 case 'x':
25864 case 'Y':
25865 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
25866 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
25867 weight = CW_Register;
25868 break;
25869 case 'I':
25870 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
25871 if (C->getZExtValue() <= 31)
25872 weight = CW_Constant;
25873 }
25874 break;
25875 case 'J':
25876 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25877 if (C->getZExtValue() <= 63)
25878 weight = CW_Constant;
25879 }
25880 break;
25881 case 'K':
25882 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25883 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
25884 weight = CW_Constant;
25885 }
25886 break;
25887 case 'L':
25888 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25889 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
25890 weight = CW_Constant;
25891 }
25892 break;
25893 case 'M':
25894 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25895 if (C->getZExtValue() <= 3)
25896 weight = CW_Constant;
25897 }
25898 break;
25899 case 'N':
25900 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25901 if (C->getZExtValue() <= 0xff)
25902 weight = CW_Constant;
25903 }
25904 break;
25905 case 'G':
25906 case 'C':
25907 if (dyn_cast<ConstantFP>(CallOperandVal)) {
25908 weight = CW_Constant;
25909 }
25910 break;
25911 case 'e':
25912 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25913 if ((C->getSExtValue() >= -0x80000000LL) &&
25914 (C->getSExtValue() <= 0x7fffffffLL))
25915 weight = CW_Constant;
25916 }
25917 break;
25918 case 'Z':
25919 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25920 if (C->getZExtValue() <= 0xffffffff)
25921 weight = CW_Constant;
25922 }
25923 break;
25924 }
25925 return weight;
25926 }
25928 /// LowerXConstraint - try to replace an X constraint, which matches anything,
25929 /// with another that has more specific requirements based on the type of the
25930 /// corresponding operand.
25931 const char *X86TargetLowering::
25932 LowerXConstraint(EVT ConstraintVT) const {
25933 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
25934 // 'f' like normal targets.
25935 if (ConstraintVT.isFloatingPoint()) {
25936 if (Subtarget->hasSSE2())
25937 return "Y";
25938 if (Subtarget->hasSSE1())
25939 return "x";
25940 }
25942 return TargetLowering::LowerXConstraint(ConstraintVT);
25943 }
25945 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
25946 /// vector. If it is invalid, don't add anything to Ops.
25947 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
25948 std::string &Constraint,
25949 std::vector<SDValue>&Ops,
25950 SelectionDAG &DAG) const {
25951 SDValue Result;
25953 // Only support length 1 constraints for now.
25954 if (Constraint.length() > 1) return;
25956 char ConstraintLetter = Constraint[0];
25957 switch (ConstraintLetter) {
25958 default: break;
25959 case 'I':
25960 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25961 if (C->getZExtValue() <= 31) {
25962 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25963 break;
25964 }
25965 }
25966 return;
25967 case 'J':
25968 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25969 if (C->getZExtValue() <= 63) {
25970 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25971 break;
25972 }
25973 }
25974 return;
25975 case 'K':
25976 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25977 if (isInt<8>(C->getSExtValue())) {
25978 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25979 break;
25980 }
25981 }
25982 return;
25983 case 'N':
25984 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25985 if (C->getZExtValue() <= 255) {
25986 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25987 break;
25988 }
25989 }
25990 return;
25991 case 'e': {
25992 // 32-bit signed value
25993 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25994 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25995 C->getSExtValue())) {
25996 // Widen to 64 bits here to get it sign extended.
25997 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
25998 break;
25999 }
26000 // FIXME gcc accepts some relocatable values here too, but only in certain
26001 // memory models; it's complicated.
26002 }
26003 return;
26004 }
26005 case 'Z': {
26006 // 32-bit unsigned value
26007 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26008 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26009 C->getZExtValue())) {
26010 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26011 break;
26012 }
26013 }
26014 // FIXME gcc accepts some relocatable values here too, but only in certain
26015 // memory models; it's complicated.
26016 return;
26017 }
26018 case 'i': {
26019 // Literal immediates are always ok.
26020 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
26021 // Widen to 64 bits here to get it sign extended.
26022 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
26023 break;
26024 }
26026 // In any sort of PIC mode addresses need to be computed at runtime by
26027 // adding in a register or some sort of table lookup. These can't
26028 // be used as immediates.
26029 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
26030 return;
26032 // If we are in non-pic codegen mode, we allow the address of a global (with
26033 // an optional displacement) to be used with 'i'.
26034 GlobalAddressSDNode *GA = nullptr;
26035 int64_t Offset = 0;
26037 // Match either (GA), (GA+C), (GA+C1+C2), etc.
26038 while (1) {
26039 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
26040 Offset += GA->getOffset();
26041 break;
26042 } else if (Op.getOpcode() == ISD::ADD) {
26043 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26044 Offset += C->getZExtValue();
26045 Op = Op.getOperand(0);
26046 continue;
26047 }
26048 } else if (Op.getOpcode() == ISD::SUB) {
26049 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26050 Offset += -C->getZExtValue();
26051 Op = Op.getOperand(0);
26052 continue;
26053 }
26054 }
26056 // Otherwise, this isn't something we can handle, reject it.
26057 return;
26058 }
26060 const GlobalValue *GV = GA->getGlobal();
26061 // If we require an extra load to get this address, as in PIC mode, we
26062 // can't accept it.
26063 if (isGlobalStubReference(
26064 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
26065 return;
26067 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
26068 GA->getValueType(0), Offset);
26069 break;
26070 }
26071 }
26073 if (Result.getNode()) {
26074 Ops.push_back(Result);
26075 return;
26076 }
26077 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
26078 }
26080 std::pair<unsigned, const TargetRegisterClass*>
26081 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
26082 MVT VT) const {
26083 // First, see if this is a constraint that directly corresponds to an LLVM
26084 // register class.
26085 if (Constraint.size() == 1) {
26086 // GCC Constraint Letters
26087 switch (Constraint[0]) {
26088 default: break;
26089 // TODO: Slight differences here in allocation order and leaving
26090 // RIP in the class. Do they matter any more here than they do
26091 // in the normal allocation?
26092 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
26093 if (Subtarget->is64Bit()) {
26094 if (VT == MVT::i32 || VT == MVT::f32)
26095 return std::make_pair(0U, &X86::GR32RegClass);
26096 if (VT == MVT::i16)
26097 return std::make_pair(0U, &X86::GR16RegClass);
26098 if (VT == MVT::i8 || VT == MVT::i1)
26099 return std::make_pair(0U, &X86::GR8RegClass);
26100 if (VT == MVT::i64 || VT == MVT::f64)
26101 return std::make_pair(0U, &X86::GR64RegClass);
26102 break;
26103 }
26104 // 32-bit fallthrough
26105 case 'Q': // Q_REGS
26106 if (VT == MVT::i32 || VT == MVT::f32)
26107 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
26108 if (VT == MVT::i16)
26109 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
26110 if (VT == MVT::i8 || VT == MVT::i1)
26111 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
26112 if (VT == MVT::i64)
26113 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
26114 break;
26115 case 'r': // GENERAL_REGS
26116 case 'l': // INDEX_REGS
26117 if (VT == MVT::i8 || VT == MVT::i1)
26118 return std::make_pair(0U, &X86::GR8RegClass);
26119 if (VT == MVT::i16)
26120 return std::make_pair(0U, &X86::GR16RegClass);
26121 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
26122 return std::make_pair(0U, &X86::GR32RegClass);
26123 return std::make_pair(0U, &X86::GR64RegClass);
26124 case 'R': // LEGACY_REGS
26125 if (VT == MVT::i8 || VT == MVT::i1)
26126 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
26127 if (VT == MVT::i16)
26128 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
26129 if (VT == MVT::i32 || !Subtarget->is64Bit())
26130 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
26131 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
26132 case 'f': // FP Stack registers.
26133 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
26134 // value to the correct fpstack register class.
26135 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
26136 return std::make_pair(0U, &X86::RFP32RegClass);
26137 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
26138 return std::make_pair(0U, &X86::RFP64RegClass);
26139 return std::make_pair(0U, &X86::RFP80RegClass);
26140 case 'y': // MMX_REGS if MMX allowed.
26141 if (!Subtarget->hasMMX()) break;
26142 return std::make_pair(0U, &X86::VR64RegClass);
26143 case 'Y': // SSE_REGS if SSE2 allowed
26144 if (!Subtarget->hasSSE2()) break;
26145 // FALL THROUGH.
26146 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
26147 if (!Subtarget->hasSSE1()) break;
26149 switch (VT.SimpleTy) {
26150 default: break;
26151 // Scalar SSE types.
26152 case MVT::f32:
26153 case MVT::i32:
26154 return std::make_pair(0U, &X86::FR32RegClass);
26155 case MVT::f64:
26156 case MVT::i64:
26157 return std::make_pair(0U, &X86::FR64RegClass);
26158 // Vector types.
26159 case MVT::v16i8:
26160 case MVT::v8i16:
26161 case MVT::v4i32:
26162 case MVT::v2i64:
26163 case MVT::v4f32:
26164 case MVT::v2f64:
26165 return std::make_pair(0U, &X86::VR128RegClass);
26166 // AVX types.
26167 case MVT::v32i8:
26168 case MVT::v16i16:
26169 case MVT::v8i32:
26170 case MVT::v4i64:
26171 case MVT::v8f32:
26172 case MVT::v4f64:
26173 return std::make_pair(0U, &X86::VR256RegClass);
26174 case MVT::v8f64:
26175 case MVT::v16f32:
26176 case MVT::v16i32:
26177 case MVT::v8i64:
26178 return std::make_pair(0U, &X86::VR512RegClass);
26179 }
26180 break;
26181 }
26182 }
26184 // Use the default implementation in TargetLowering to convert the register
26185 // constraint into a member of a register class.
26186 std::pair<unsigned, const TargetRegisterClass*> Res;
26187 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
26189 // Not found as a standard register?
26190 if (!Res.second) {
26191 // Map st(0) -> st(7) -> ST0
26192 if (Constraint.size() == 7 && Constraint[0] == '{' &&
26193 tolower(Constraint[1]) == 's' &&
26194 tolower(Constraint[2]) == 't' &&
26195 Constraint[3] == '(' &&
26196 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
26197 Constraint[5] == ')' &&
26198 Constraint[6] == '}') {
26200 Res.first = X86::FP0+Constraint[4]-'0';
26201 Res.second = &X86::RFP80RegClass;
26202 return Res;
26203 }
26205 // GCC allows "st(0)" to be called just plain "st".
26206 if (StringRef("{st}").equals_lower(Constraint)) {
26207 Res.first = X86::FP0;
26208 Res.second = &X86::RFP80RegClass;
26209 return Res;
26210 }
26212 // flags -> EFLAGS
26213 if (StringRef("{flags}").equals_lower(Constraint)) {
26214 Res.first = X86::EFLAGS;
26215 Res.second = &X86::CCRRegClass;
26216 return Res;
26217 }
26219 // 'A' means EAX + EDX.
26220 if (Constraint == "A") {
26221 Res.first = X86::EAX;
26222 Res.second = &X86::GR32_ADRegClass;
26223 return Res;
26224 }
26225 return Res;
26226 }
26228 // Otherwise, check to see if this is a register class of the wrong value
26229 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
26230 // turn into {ax},{dx}.
26231 if (Res.second->hasType(VT))
26232 return Res; // Correct type already, nothing to do.
26234 // All of the single-register GCC register classes map their values onto
26235 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
26236 // really want an 8-bit or 32-bit register, map to the appropriate register
26237 // class and return the appropriate register.
26238 if (Res.second == &X86::GR16RegClass) {
26239 if (VT == MVT::i8 || VT == MVT::i1) {
26240 unsigned DestReg = 0;
26241 switch (Res.first) {
26242 default: break;
26243 case X86::AX: DestReg = X86::AL; break;
26244 case X86::DX: DestReg = X86::DL; break;
26245 case X86::CX: DestReg = X86::CL; break;
26246 case X86::BX: DestReg = X86::BL; break;
26247 }
26248 if (DestReg) {
26249 Res.first = DestReg;
26250 Res.second = &X86::GR8RegClass;
26251 }
26252 } else if (VT == MVT::i32 || VT == MVT::f32) {
26253 unsigned DestReg = 0;
26254 switch (Res.first) {
26255 default: break;
26256 case X86::AX: DestReg = X86::EAX; break;
26257 case X86::DX: DestReg = X86::EDX; break;
26258 case X86::CX: DestReg = X86::ECX; break;
26259 case X86::BX: DestReg = X86::EBX; break;
26260 case X86::SI: DestReg = X86::ESI; break;
26261 case X86::DI: DestReg = X86::EDI; break;
26262 case X86::BP: DestReg = X86::EBP; break;
26263 case X86::SP: DestReg = X86::ESP; break;
26264 }
26265 if (DestReg) {
26266 Res.first = DestReg;
26267 Res.second = &X86::GR32RegClass;
26268 }
26269 } else if (VT == MVT::i64 || VT == MVT::f64) {
26270 unsigned DestReg = 0;
26271 switch (Res.first) {
26272 default: break;
26273 case X86::AX: DestReg = X86::RAX; break;
26274 case X86::DX: DestReg = X86::RDX; break;
26275 case X86::CX: DestReg = X86::RCX; break;
26276 case X86::BX: DestReg = X86::RBX; break;
26277 case X86::SI: DestReg = X86::RSI; break;
26278 case X86::DI: DestReg = X86::RDI; break;
26279 case X86::BP: DestReg = X86::RBP; break;
26280 case X86::SP: DestReg = X86::RSP; break;
26281 }
26282 if (DestReg) {
26283 Res.first = DestReg;
26284 Res.second = &X86::GR64RegClass;
26285 }
26286 }
26287 } else if (Res.second == &X86::FR32RegClass ||
26288 Res.second == &X86::FR64RegClass ||
26289 Res.second == &X86::VR128RegClass ||
26290 Res.second == &X86::VR256RegClass ||
26291 Res.second == &X86::FR32XRegClass ||
26292 Res.second == &X86::FR64XRegClass ||
26293 Res.second == &X86::VR128XRegClass ||
26294 Res.second == &X86::VR256XRegClass ||
26295 Res.second == &X86::VR512RegClass) {
26296 // Handle references to XMM physical registers that got mapped into the
26297 // wrong class. This can happen with constraints like {xmm0} where the
26298 // target independent register mapper will just pick the first match it can
26299 // find, ignoring the required type.
26301 if (VT == MVT::f32 || VT == MVT::i32)
26302 Res.second = &X86::FR32RegClass;
26303 else if (VT == MVT::f64 || VT == MVT::i64)
26304 Res.second = &X86::FR64RegClass;
26305 else if (X86::VR128RegClass.hasType(VT))
26306 Res.second = &X86::VR128RegClass;
26307 else if (X86::VR256RegClass.hasType(VT))
26308 Res.second = &X86::VR256RegClass;
26309 else if (X86::VR512RegClass.hasType(VT))
26310 Res.second = &X86::VR512RegClass;
26311 }
26313 return Res;
26314 }
26316 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
26317 Type *Ty) const {
26318 // Scaling factors are not free at all.
26319 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
26320 // will take 2 allocations in the out of order engine instead of 1
26321 // for plain addressing mode, i.e. inst (reg1).
26322 // E.g.,
26323 // vaddps (%rsi,%drx), %ymm0, %ymm1
26324 // Requires two allocations (one for the load, one for the computation)
26325 // whereas:
26326 // vaddps (%rsi), %ymm0, %ymm1
26327 // Requires just 1 allocation, i.e., freeing allocations for other operations
26328 // and having less micro operations to execute.
26329 //
26330 // For some X86 architectures, this is even worse because for instance for
26331 // stores, the complex addressing mode forces the instruction to use the
26332 // "load" ports instead of the dedicated "store" port.
26333 // E.g., on Haswell:
26334 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
26335 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
26336 if (isLegalAddressingMode(AM, Ty))
26337 // Scale represents reg2 * scale, thus account for 1
26338 // as soon as we use a second register.
26339 return AM.Scale != 0;
26340 return -1;
26341 }
26343 bool X86TargetLowering::isTargetFTOL() const {
26344 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();
26345 }