1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
54 #include <bitset>
55 #include <numeric>
56 #include <cctype>
57 using namespace llvm;
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
67 cl::Hidden);
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(false),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
72 cl::Hidden);
74 // Forward declarations.
75 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
76 SDValue V2);
78 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
79 SelectionDAG &DAG, SDLoc dl,
80 unsigned vectorWidth) {
81 assert((vectorWidth == 128 || vectorWidth == 256) &&
82 "Unsupported vector width");
83 EVT VT = Vec.getValueType();
84 EVT ElVT = VT.getVectorElementType();
85 unsigned Factor = VT.getSizeInBits()/vectorWidth;
86 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
87 VT.getVectorNumElements()/Factor);
89 // Extract from UNDEF is UNDEF.
90 if (Vec.getOpcode() == ISD::UNDEF)
91 return DAG.getUNDEF(ResultVT);
93 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
94 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
96 // This is the index of the first element of the vectorWidth-bit chunk
97 // we want.
98 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
99 * ElemsPerChunk);
101 // If the input is a buildvector just emit a smaller one.
102 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
103 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
104 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
105 ElemsPerChunk));
107 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
108 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
109 VecIdx);
111 return Result;
113 }
114 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
115 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
116 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
117 /// instructions or a simple subregister reference. Idx is an index in the
118 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
119 /// lowering EXTRACT_VECTOR_ELT operations easier.
120 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
121 SelectionDAG &DAG, SDLoc dl) {
122 assert((Vec.getValueType().is256BitVector() ||
123 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
124 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
125 }
127 /// Generate a DAG to grab 256-bits from a 512-bit vector.
128 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
129 SelectionDAG &DAG, SDLoc dl) {
130 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
131 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
132 }
134 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
135 unsigned IdxVal, SelectionDAG &DAG,
136 SDLoc dl, unsigned vectorWidth) {
137 assert((vectorWidth == 128 || vectorWidth == 256) &&
138 "Unsupported vector width");
139 // Inserting UNDEF is Result
140 if (Vec.getOpcode() == ISD::UNDEF)
141 return Result;
142 EVT VT = Vec.getValueType();
143 EVT ElVT = VT.getVectorElementType();
144 EVT ResultVT = Result.getValueType();
146 // Insert the relevant vectorWidth bits.
147 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
149 // This is the index of the first element of the vectorWidth-bit chunk
150 // we want.
151 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
152 * ElemsPerChunk);
154 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
155 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
156 VecIdx);
157 }
158 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
159 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
160 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
161 /// simple superregister reference. Idx is an index in the 128 bits
162 /// we want. It need not be aligned to a 128-bit bounday. That makes
163 /// lowering INSERT_VECTOR_ELT operations easier.
164 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
165 unsigned IdxVal, SelectionDAG &DAG,
166 SDLoc dl) {
167 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
168 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
169 }
171 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
172 unsigned IdxVal, SelectionDAG &DAG,
173 SDLoc dl) {
174 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
175 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
176 }
178 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
179 /// instructions. This is used because creating CONCAT_VECTOR nodes of
180 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
181 /// large BUILD_VECTORS.
182 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
183 unsigned NumElems, SelectionDAG &DAG,
184 SDLoc dl) {
185 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
186 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
187 }
189 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
190 unsigned NumElems, SelectionDAG &DAG,
191 SDLoc dl) {
192 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
193 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
194 }
196 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
197 if (TT.isOSBinFormatMachO()) {
198 if (TT.getArch() == Triple::x86_64)
199 return new X86_64MachoTargetObjectFile();
200 return new TargetLoweringObjectFileMachO();
201 }
203 if (TT.isOSLinux())
204 return new X86LinuxTargetObjectFile();
205 if (TT.isOSBinFormatELF())
206 return new TargetLoweringObjectFileELF();
207 if (TT.isKnownWindowsMSVCEnvironment())
208 return new X86WindowsTargetObjectFile();
209 if (TT.isOSBinFormatCOFF())
210 return new TargetLoweringObjectFileCOFF();
211 llvm_unreachable("unknown subtarget type");
212 }
214 // FIXME: This should stop caching the target machine as soon as
215 // we can remove resetOperationActions et al.
216 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM)
217 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
218 Subtarget = &TM.getSubtarget<X86Subtarget>();
219 X86ScalarSSEf64 = Subtarget->hasSSE2();
220 X86ScalarSSEf32 = Subtarget->hasSSE1();
221 TD = getDataLayout();
223 resetOperationActions();
224 }
226 void X86TargetLowering::resetOperationActions() {
227 const TargetMachine &TM = getTargetMachine();
228 static bool FirstTimeThrough = true;
230 // If none of the target options have changed, then we don't need to reset the
231 // operation actions.
232 if (!FirstTimeThrough && TO == TM.Options) return;
234 if (!FirstTimeThrough) {
235 // Reinitialize the actions.
236 initActions();
237 FirstTimeThrough = false;
238 }
240 TO = TM.Options;
242 // Set up the TargetLowering object.
243 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
245 // X86 is weird, it always uses i8 for shift amounts and setcc results.
246 setBooleanContents(ZeroOrOneBooleanContent);
247 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
248 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
250 // For 64-bit since we have so many registers use the ILP scheduler, for
251 // 32-bit code use the register pressure specific scheduling.
252 // For Atom, always use ILP scheduling.
253 if (Subtarget->isAtom())
254 setSchedulingPreference(Sched::ILP);
255 else if (Subtarget->is64Bit())
256 setSchedulingPreference(Sched::ILP);
257 else
258 setSchedulingPreference(Sched::RegPressure);
259 const X86RegisterInfo *RegInfo =
260 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
261 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
263 // Bypass expensive divides on Atom when compiling with O2
264 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
265 addBypassSlowDiv(32, 8);
266 if (Subtarget->is64Bit())
267 addBypassSlowDiv(64, 16);
268 }
270 if (Subtarget->isTargetKnownWindowsMSVC()) {
271 // Setup Windows compiler runtime calls.
272 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
273 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
274 setLibcallName(RTLIB::SREM_I64, "_allrem");
275 setLibcallName(RTLIB::UREM_I64, "_aullrem");
276 setLibcallName(RTLIB::MUL_I64, "_allmul");
277 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
278 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
279 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
280 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
281 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
283 // The _ftol2 runtime function has an unusual calling conv, which
284 // is modeled by a special pseudo-instruction.
285 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
286 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
287 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
288 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
289 }
291 if (Subtarget->isTargetDarwin()) {
292 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
293 setUseUnderscoreSetJmp(false);
294 setUseUnderscoreLongJmp(false);
295 } else if (Subtarget->isTargetWindowsGNU()) {
296 // MS runtime is weird: it exports _setjmp, but longjmp!
297 setUseUnderscoreSetJmp(true);
298 setUseUnderscoreLongJmp(false);
299 } else {
300 setUseUnderscoreSetJmp(true);
301 setUseUnderscoreLongJmp(true);
302 }
304 // Set up the register classes.
305 addRegisterClass(MVT::i8, &X86::GR8RegClass);
306 addRegisterClass(MVT::i16, &X86::GR16RegClass);
307 addRegisterClass(MVT::i32, &X86::GR32RegClass);
308 if (Subtarget->is64Bit())
309 addRegisterClass(MVT::i64, &X86::GR64RegClass);
311 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
313 // We don't accept any truncstore of integer registers.
314 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
315 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
316 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
317 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
318 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
319 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
321 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
323 // SETOEQ and SETUNE require checking two conditions.
324 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
325 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
326 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
327 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
328 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
329 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
331 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
332 // operation.
333 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
334 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
335 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
337 if (Subtarget->is64Bit()) {
338 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
339 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
340 } else if (!TM.Options.UseSoftFloat) {
341 // We have an algorithm for SSE2->double, and we turn this into a
342 // 64-bit FILD followed by conditional FADD for other targets.
343 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
344 // We have an algorithm for SSE2, and we turn this into a 64-bit
345 // FILD for other targets.
346 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
347 }
349 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
350 // this operation.
351 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
352 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
354 if (!TM.Options.UseSoftFloat) {
355 // SSE has no i16 to fp conversion, only i32
356 if (X86ScalarSSEf32) {
357 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
358 // f32 and f64 cases are Legal, f80 case is not
359 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
360 } else {
361 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
362 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
363 }
364 } else {
365 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
366 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
367 }
369 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
370 // are Legal, f80 is custom lowered.
371 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
372 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
374 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
375 // this operation.
376 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
377 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
379 if (X86ScalarSSEf32) {
380 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
381 // f32 and f64 cases are Legal, f80 case is not
382 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
383 } else {
384 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
385 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
386 }
388 // Handle FP_TO_UINT by promoting the destination to a larger signed
389 // conversion.
390 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
391 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
392 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
394 if (Subtarget->is64Bit()) {
395 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
396 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
397 } else if (!TM.Options.UseSoftFloat) {
398 // Since AVX is a superset of SSE3, only check for SSE here.
399 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
400 // Expand FP_TO_UINT into a select.
401 // FIXME: We would like to use a Custom expander here eventually to do
402 // the optimal thing for SSE vs. the default expansion in the legalizer.
403 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
404 else
405 // With SSE3 we can use fisttpll to convert to a signed i64; without
406 // SSE, we're stuck with a fistpll.
407 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
408 }
410 if (isTargetFTOL()) {
411 // Use the _ftol2 runtime function, which has a pseudo-instruction
412 // to handle its weird calling convention.
413 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
414 }
416 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
417 if (!X86ScalarSSEf64) {
418 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
419 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
420 if (Subtarget->is64Bit()) {
421 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
422 // Without SSE, i64->f64 goes through memory.
423 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
424 }
425 }
427 // Scalar integer divide and remainder are lowered to use operations that
428 // produce two results, to match the available instructions. This exposes
429 // the two-result form to trivial CSE, which is able to combine x/y and x%y
430 // into a single instruction.
431 //
432 // Scalar integer multiply-high is also lowered to use two-result
433 // operations, to match the available instructions. However, plain multiply
434 // (low) operations are left as Legal, as there are single-result
435 // instructions for this in x86. Using the two-result multiply instructions
436 // when both high and low results are needed must be arranged by dagcombine.
437 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
438 MVT VT = IntVTs[i];
439 setOperationAction(ISD::MULHS, VT, Expand);
440 setOperationAction(ISD::MULHU, VT, Expand);
441 setOperationAction(ISD::SDIV, VT, Expand);
442 setOperationAction(ISD::UDIV, VT, Expand);
443 setOperationAction(ISD::SREM, VT, Expand);
444 setOperationAction(ISD::UREM, VT, Expand);
446 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
447 setOperationAction(ISD::ADDC, VT, Custom);
448 setOperationAction(ISD::ADDE, VT, Custom);
449 setOperationAction(ISD::SUBC, VT, Custom);
450 setOperationAction(ISD::SUBE, VT, Custom);
451 }
453 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
454 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
455 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
456 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
457 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
458 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
459 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
460 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
461 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
462 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
463 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
464 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
465 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
466 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
467 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
468 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
469 if (Subtarget->is64Bit())
470 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
471 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
472 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
473 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
474 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
475 setOperationAction(ISD::FREM , MVT::f32 , Expand);
476 setOperationAction(ISD::FREM , MVT::f64 , Expand);
477 setOperationAction(ISD::FREM , MVT::f80 , Expand);
478 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
480 // Promote the i8 variants and force them on up to i32 which has a shorter
481 // encoding.
482 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
483 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
484 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
485 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
486 if (Subtarget->hasBMI()) {
487 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
488 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
489 if (Subtarget->is64Bit())
490 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
491 } else {
492 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
493 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
494 if (Subtarget->is64Bit())
495 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
496 }
498 if (Subtarget->hasLZCNT()) {
499 // When promoting the i8 variants, force them to i32 for a shorter
500 // encoding.
501 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
502 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
503 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
504 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
505 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
506 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
507 if (Subtarget->is64Bit())
508 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
509 } else {
510 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
511 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
512 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
513 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
515 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
516 if (Subtarget->is64Bit()) {
517 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
518 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
519 }
520 }
522 // Special handling for half-precision floating point conversions.
523 // If we don't have F16C support, then lower half float conversions
524 // into library calls.
525 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
526 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
527 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
528 }
530 // There's never any support for operations beyond MVT::f32.
531 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
532 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
533 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
534 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
536 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
537 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
538 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
539 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
541 if (Subtarget->hasPOPCNT()) {
542 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
543 } else {
544 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
545 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
546 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
547 if (Subtarget->is64Bit())
548 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
549 }
551 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
553 if (!Subtarget->hasMOVBE())
554 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
556 // These should be promoted to a larger select which is supported.
557 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
558 // X86 wants to expand cmov itself.
559 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
560 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
561 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
562 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
563 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
564 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
565 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
566 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
567 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
568 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
569 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
570 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
571 if (Subtarget->is64Bit()) {
572 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
573 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
574 }
575 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
576 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
577 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
578 // support continuation, user-level threading, and etc.. As a result, no
579 // other SjLj exception interfaces are implemented and please don't build
580 // your own exception handling based on them.
581 // LLVM/Clang supports zero-cost DWARF exception handling.
582 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
583 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
585 // Darwin ABI issue.
586 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
587 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
588 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
589 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
590 if (Subtarget->is64Bit())
591 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
592 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
593 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
594 if (Subtarget->is64Bit()) {
595 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
596 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
597 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
598 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
599 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
600 }
601 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
602 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
603 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
604 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
605 if (Subtarget->is64Bit()) {
606 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
607 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
608 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
609 }
611 if (Subtarget->hasSSE1())
612 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
614 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
616 // Expand certain atomics
617 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
618 MVT VT = IntVTs[i];
619 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
620 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
621 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
622 }
624 if (Subtarget->hasCmpxchg16b()) {
625 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
626 }
628 // FIXME - use subtarget debug flags
629 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
630 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
631 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
632 }
634 if (Subtarget->is64Bit()) {
635 setExceptionPointerRegister(X86::RAX);
636 setExceptionSelectorRegister(X86::RDX);
637 } else {
638 setExceptionPointerRegister(X86::EAX);
639 setExceptionSelectorRegister(X86::EDX);
640 }
641 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
642 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
644 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
645 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
647 setOperationAction(ISD::TRAP, MVT::Other, Legal);
648 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
650 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
651 setOperationAction(ISD::VASTART , MVT::Other, Custom);
652 setOperationAction(ISD::VAEND , MVT::Other, Expand);
653 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
654 // TargetInfo::X86_64ABIBuiltinVaList
655 setOperationAction(ISD::VAARG , MVT::Other, Custom);
656 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
657 } else {
658 // TargetInfo::CharPtrBuiltinVaList
659 setOperationAction(ISD::VAARG , MVT::Other, Expand);
660 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
661 }
663 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
664 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
666 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
668 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
669 // f32 and f64 use SSE.
670 // Set up the FP register classes.
671 addRegisterClass(MVT::f32, &X86::FR32RegClass);
672 addRegisterClass(MVT::f64, &X86::FR64RegClass);
674 // Use ANDPD to simulate FABS.
675 setOperationAction(ISD::FABS , MVT::f64, Custom);
676 setOperationAction(ISD::FABS , MVT::f32, Custom);
678 // Use XORP to simulate FNEG.
679 setOperationAction(ISD::FNEG , MVT::f64, Custom);
680 setOperationAction(ISD::FNEG , MVT::f32, Custom);
682 // Use ANDPD and ORPD to simulate FCOPYSIGN.
683 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
684 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
686 // Lower this to FGETSIGNx86 plus an AND.
687 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
688 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
690 // We don't support sin/cos/fmod
691 setOperationAction(ISD::FSIN , MVT::f64, Expand);
692 setOperationAction(ISD::FCOS , MVT::f64, Expand);
693 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
694 setOperationAction(ISD::FSIN , MVT::f32, Expand);
695 setOperationAction(ISD::FCOS , MVT::f32, Expand);
696 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
698 // Expand FP immediates into loads from the stack, except for the special
699 // cases we handle.
700 addLegalFPImmediate(APFloat(+0.0)); // xorpd
701 addLegalFPImmediate(APFloat(+0.0f)); // xorps
702 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
703 // Use SSE for f32, x87 for f64.
704 // Set up the FP register classes.
705 addRegisterClass(MVT::f32, &X86::FR32RegClass);
706 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
708 // Use ANDPS to simulate FABS.
709 setOperationAction(ISD::FABS , MVT::f32, Custom);
711 // Use XORP to simulate FNEG.
712 setOperationAction(ISD::FNEG , MVT::f32, Custom);
714 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
716 // Use ANDPS and ORPS to simulate FCOPYSIGN.
717 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
718 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
720 // We don't support sin/cos/fmod
721 setOperationAction(ISD::FSIN , MVT::f32, Expand);
722 setOperationAction(ISD::FCOS , MVT::f32, Expand);
723 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
725 // Special cases we handle for FP constants.
726 addLegalFPImmediate(APFloat(+0.0f)); // xorps
727 addLegalFPImmediate(APFloat(+0.0)); // FLD0
728 addLegalFPImmediate(APFloat(+1.0)); // FLD1
729 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
730 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
732 if (!TM.Options.UnsafeFPMath) {
733 setOperationAction(ISD::FSIN , MVT::f64, Expand);
734 setOperationAction(ISD::FCOS , MVT::f64, Expand);
735 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
736 }
737 } else if (!TM.Options.UseSoftFloat) {
738 // f32 and f64 in x87.
739 // Set up the FP register classes.
740 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
741 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
743 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
744 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
745 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
746 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
748 if (!TM.Options.UnsafeFPMath) {
749 setOperationAction(ISD::FSIN , MVT::f64, Expand);
750 setOperationAction(ISD::FSIN , MVT::f32, Expand);
751 setOperationAction(ISD::FCOS , MVT::f64, Expand);
752 setOperationAction(ISD::FCOS , MVT::f32, Expand);
753 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
754 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
755 }
756 addLegalFPImmediate(APFloat(+0.0)); // FLD0
757 addLegalFPImmediate(APFloat(+1.0)); // FLD1
758 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
759 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
760 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
761 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
762 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
763 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
764 }
766 // We don't support FMA.
767 setOperationAction(ISD::FMA, MVT::f64, Expand);
768 setOperationAction(ISD::FMA, MVT::f32, Expand);
770 // Long double always uses X87.
771 if (!TM.Options.UseSoftFloat) {
772 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
773 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
774 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
775 {
776 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
777 addLegalFPImmediate(TmpFlt); // FLD0
778 TmpFlt.changeSign();
779 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
781 bool ignored;
782 APFloat TmpFlt2(+1.0);
783 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
784 &ignored);
785 addLegalFPImmediate(TmpFlt2); // FLD1
786 TmpFlt2.changeSign();
787 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
788 }
790 if (!TM.Options.UnsafeFPMath) {
791 setOperationAction(ISD::FSIN , MVT::f80, Expand);
792 setOperationAction(ISD::FCOS , MVT::f80, Expand);
793 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
794 }
796 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
797 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
798 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
799 setOperationAction(ISD::FRINT, MVT::f80, Expand);
800 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
801 setOperationAction(ISD::FMA, MVT::f80, Expand);
802 }
804 // Always use a library call for pow.
805 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
806 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
807 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
809 setOperationAction(ISD::FLOG, MVT::f80, Expand);
810 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
811 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
812 setOperationAction(ISD::FEXP, MVT::f80, Expand);
813 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
815 // First set operation action for all vector types to either promote
816 // (for widening) or expand (for scalarization). Then we will selectively
817 // turn on ones that can be effectively codegen'd.
818 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
819 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
820 MVT VT = (MVT::SimpleValueType)i;
821 setOperationAction(ISD::ADD , VT, Expand);
822 setOperationAction(ISD::SUB , VT, Expand);
823 setOperationAction(ISD::FADD, VT, Expand);
824 setOperationAction(ISD::FNEG, VT, Expand);
825 setOperationAction(ISD::FSUB, VT, Expand);
826 setOperationAction(ISD::MUL , VT, Expand);
827 setOperationAction(ISD::FMUL, VT, Expand);
828 setOperationAction(ISD::SDIV, VT, Expand);
829 setOperationAction(ISD::UDIV, VT, Expand);
830 setOperationAction(ISD::FDIV, VT, Expand);
831 setOperationAction(ISD::SREM, VT, Expand);
832 setOperationAction(ISD::UREM, VT, Expand);
833 setOperationAction(ISD::LOAD, VT, Expand);
834 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
835 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
836 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
837 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
838 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
839 setOperationAction(ISD::FABS, VT, Expand);
840 setOperationAction(ISD::FSIN, VT, Expand);
841 setOperationAction(ISD::FSINCOS, VT, Expand);
842 setOperationAction(ISD::FCOS, VT, Expand);
843 setOperationAction(ISD::FSINCOS, VT, Expand);
844 setOperationAction(ISD::FREM, VT, Expand);
845 setOperationAction(ISD::FMA, VT, Expand);
846 setOperationAction(ISD::FPOWI, VT, Expand);
847 setOperationAction(ISD::FSQRT, VT, Expand);
848 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
849 setOperationAction(ISD::FFLOOR, VT, Expand);
850 setOperationAction(ISD::FCEIL, VT, Expand);
851 setOperationAction(ISD::FTRUNC, VT, Expand);
852 setOperationAction(ISD::FRINT, VT, Expand);
853 setOperationAction(ISD::FNEARBYINT, VT, Expand);
854 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
855 setOperationAction(ISD::MULHS, VT, Expand);
856 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
857 setOperationAction(ISD::MULHU, VT, Expand);
858 setOperationAction(ISD::SDIVREM, VT, Expand);
859 setOperationAction(ISD::UDIVREM, VT, Expand);
860 setOperationAction(ISD::FPOW, VT, Expand);
861 setOperationAction(ISD::CTPOP, VT, Expand);
862 setOperationAction(ISD::CTTZ, VT, Expand);
863 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
864 setOperationAction(ISD::CTLZ, VT, Expand);
865 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
866 setOperationAction(ISD::SHL, VT, Expand);
867 setOperationAction(ISD::SRA, VT, Expand);
868 setOperationAction(ISD::SRL, VT, Expand);
869 setOperationAction(ISD::ROTL, VT, Expand);
870 setOperationAction(ISD::ROTR, VT, Expand);
871 setOperationAction(ISD::BSWAP, VT, Expand);
872 setOperationAction(ISD::SETCC, VT, Expand);
873 setOperationAction(ISD::FLOG, VT, Expand);
874 setOperationAction(ISD::FLOG2, VT, Expand);
875 setOperationAction(ISD::FLOG10, VT, Expand);
876 setOperationAction(ISD::FEXP, VT, Expand);
877 setOperationAction(ISD::FEXP2, VT, Expand);
878 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
879 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
880 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
881 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
882 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
883 setOperationAction(ISD::TRUNCATE, VT, Expand);
884 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
885 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
886 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
887 setOperationAction(ISD::VSELECT, VT, Expand);
888 setOperationAction(ISD::SELECT_CC, VT, Expand);
889 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
890 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
891 setTruncStoreAction(VT,
892 (MVT::SimpleValueType)InnerVT, Expand);
893 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
894 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
896 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
897 // we have to deal with them whether we ask for Expansion or not. Setting
898 // Expand causes its own optimisation problems though, so leave them legal.
899 if (VT.getVectorElementType() == MVT::i1)
900 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
901 }
903 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
904 // with -msoft-float, disable use of MMX as well.
905 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
906 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
907 // No operations on x86mmx supported, everything uses intrinsics.
908 }
910 // MMX-sized vectors (other than x86mmx) are expected to be expanded
911 // into smaller operations.
912 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
913 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
914 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
915 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
916 setOperationAction(ISD::AND, MVT::v8i8, Expand);
917 setOperationAction(ISD::AND, MVT::v4i16, Expand);
918 setOperationAction(ISD::AND, MVT::v2i32, Expand);
919 setOperationAction(ISD::AND, MVT::v1i64, Expand);
920 setOperationAction(ISD::OR, MVT::v8i8, Expand);
921 setOperationAction(ISD::OR, MVT::v4i16, Expand);
922 setOperationAction(ISD::OR, MVT::v2i32, Expand);
923 setOperationAction(ISD::OR, MVT::v1i64, Expand);
924 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
925 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
926 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
927 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
928 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
929 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
930 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
931 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
932 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
933 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
934 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
935 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
936 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
937 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
938 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
939 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
940 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
942 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
943 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
945 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
946 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
947 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
948 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
949 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
950 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
951 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
952 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
953 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
954 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
955 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
956 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
957 }
959 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
960 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
962 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
963 // registers cannot be used even for integer operations.
964 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
965 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
966 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
967 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
969 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
970 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
971 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
972 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
973 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
974 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
975 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
976 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
977 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
978 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
979 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
980 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
981 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
982 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
983 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
984 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
985 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
986 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
987 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
988 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
989 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
990 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
992 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
993 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
994 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
995 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
997 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
998 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
999 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1000 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1001 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1003 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
1004 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1005 MVT VT = (MVT::SimpleValueType)i;
1006 // Do not attempt to custom lower non-power-of-2 vectors
1007 if (!isPowerOf2_32(VT.getVectorNumElements()))
1008 continue;
1009 // Do not attempt to custom lower non-128-bit vectors
1010 if (!VT.is128BitVector())
1011 continue;
1012 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1013 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1014 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1015 }
1017 // We support custom legalizing of sext and anyext loads for specific
1018 // memory vector types which we can load as a scalar (or sequence of
1019 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1020 // loads these must work with a single scalar load.
1021 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1022 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1023 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1024 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1025 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1026 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1027 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1028 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1029 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1031 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1032 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1033 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1034 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1035 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1036 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1038 if (Subtarget->is64Bit()) {
1039 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1040 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1041 }
1043 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1044 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1045 MVT VT = (MVT::SimpleValueType)i;
1047 // Do not attempt to promote non-128-bit vectors
1048 if (!VT.is128BitVector())
1049 continue;
1051 setOperationAction(ISD::AND, VT, Promote);
1052 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1053 setOperationAction(ISD::OR, VT, Promote);
1054 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1055 setOperationAction(ISD::XOR, VT, Promote);
1056 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1057 setOperationAction(ISD::LOAD, VT, Promote);
1058 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1059 setOperationAction(ISD::SELECT, VT, Promote);
1060 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1061 }
1063 // Custom lower v2i64 and v2f64 selects.
1064 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1065 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1066 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1067 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1069 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1070 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1072 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1073 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1074 // As there is no 64-bit GPR available, we need build a special custom
1075 // sequence to convert from v2i32 to v2f32.
1076 if (!Subtarget->is64Bit())
1077 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1079 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1080 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1082 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1084 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1085 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1086 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1087 }
1089 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1090 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1091 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1092 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1093 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1094 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1095 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1096 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1097 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1098 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1099 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1101 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1102 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1103 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1104 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1105 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1106 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1107 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1108 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1109 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1110 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1112 // FIXME: Do we need to handle scalar-to-vector here?
1113 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1115 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1116 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1117 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1118 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1119 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1120 // There is no BLENDI for byte vectors. We don't need to custom lower
1121 // some vselects for now.
1122 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1124 // SSE41 brings specific instructions for doing vector sign extend even in
1125 // cases where we don't have SRA.
1126 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1127 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1128 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1130 // i8 and i16 vectors are custom because the source register and source
1131 // source memory operand types are not the same width. f32 vectors are
1132 // custom since the immediate controlling the insert encodes additional
1133 // information.
1134 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1135 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1136 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1137 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1139 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1140 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1142 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1144 // FIXME: these should be Legal, but that's only for the case where
1145 // the index is constant. For now custom expand to deal with that.
1146 if (Subtarget->is64Bit()) {
1147 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1148 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1149 }
1150 }
1152 if (Subtarget->hasSSE2()) {
1153 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1154 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1156 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1157 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1159 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1160 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1162 // In the customized shift lowering, the legal cases in AVX2 will be
1163 // recognized.
1164 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1165 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1167 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1168 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1170 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1171 }
1173 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1174 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1175 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1176 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1177 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1178 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1179 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1181 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1182 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1183 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1185 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1186 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1187 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1188 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1189 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1190 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1191 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1192 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1193 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1194 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1195 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1196 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1198 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1199 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1200 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1201 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1202 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1203 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1204 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1205 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1206 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1207 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1208 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1209 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1211 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1212 // even though v8i16 is a legal type.
1213 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1214 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1215 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1217 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1218 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1219 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1221 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1222 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1224 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1226 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1227 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1229 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1230 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1232 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1233 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1235 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1236 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1237 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1238 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1240 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1241 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1242 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1244 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1245 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1246 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1247 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1249 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1250 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1252 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1253 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1254 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1255 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1256 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1257 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1258 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1259 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1260 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1262 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1263 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1264 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1265 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1266 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1267 setOperationAction(ISD::FMA, MVT::f32, Legal);
1268 setOperationAction(ISD::FMA, MVT::f64, Legal);
1269 }
1271 if (Subtarget->hasInt256()) {
1272 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1273 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1274 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1275 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1277 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1278 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1279 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1280 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1282 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1283 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1284 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1285 // Don't lower v32i8 because there is no 128-bit byte mul
1287 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1288 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1289 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1290 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1292 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1293 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1294 } else {
1295 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1296 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1297 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1298 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1300 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1301 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1302 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1303 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1305 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1306 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1307 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1308 // Don't lower v32i8 because there is no 128-bit byte mul
1309 }
1311 // In the customized shift lowering, the legal cases in AVX2 will be
1312 // recognized.
1313 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1314 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1316 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1317 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1319 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1321 // Custom lower several nodes for 256-bit types.
1322 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1323 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1324 MVT VT = (MVT::SimpleValueType)i;
1326 // Extract subvector is special because the value type
1327 // (result) is 128-bit but the source is 256-bit wide.
1328 if (VT.is128BitVector())
1329 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1331 // Do not attempt to custom lower other non-256-bit vectors
1332 if (!VT.is256BitVector())
1333 continue;
1335 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1336 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1337 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1338 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1339 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1340 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1341 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1342 }
1344 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1345 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1346 MVT VT = (MVT::SimpleValueType)i;
1348 // Do not attempt to promote non-256-bit vectors
1349 if (!VT.is256BitVector())
1350 continue;
1352 setOperationAction(ISD::AND, VT, Promote);
1353 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1354 setOperationAction(ISD::OR, VT, Promote);
1355 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1356 setOperationAction(ISD::XOR, VT, Promote);
1357 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1358 setOperationAction(ISD::LOAD, VT, Promote);
1359 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1360 setOperationAction(ISD::SELECT, VT, Promote);
1361 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1362 }
1363 }
1365 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1366 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1367 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1368 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1369 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1371 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1372 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1373 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1375 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1376 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1377 setOperationAction(ISD::XOR, MVT::i1, Legal);
1378 setOperationAction(ISD::OR, MVT::i1, Legal);
1379 setOperationAction(ISD::AND, MVT::i1, Legal);
1380 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1381 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1382 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1383 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1384 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1385 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1387 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1388 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1389 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1390 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1391 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1392 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1394 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1395 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1396 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1397 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1398 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1399 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1400 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1401 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1403 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1404 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1405 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1406 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1407 if (Subtarget->is64Bit()) {
1408 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1409 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1410 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1411 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1412 }
1413 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1414 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1416 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1417 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1420 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1421 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1422 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1424 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1425 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1426 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1427 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1430 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1431 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1434 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1438 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1439 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1443 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1445 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1446 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1448 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1450 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1451 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1452 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1453 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1454 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1455 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1456 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1457 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1458 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1460 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1461 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1463 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1464 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1466 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1468 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1469 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1471 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1472 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1474 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1475 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1477 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1478 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1479 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1480 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1481 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1482 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1484 if (Subtarget->hasCDI()) {
1485 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1486 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1487 }
1489 // Custom lower several nodes.
1490 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1491 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1492 MVT VT = (MVT::SimpleValueType)i;
1494 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1495 // Extract subvector is special because the value type
1496 // (result) is 256/128-bit but the source is 512-bit wide.
1497 if (VT.is128BitVector() || VT.is256BitVector())
1498 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1500 if (VT.getVectorElementType() == MVT::i1)
1501 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1503 // Do not attempt to custom lower other non-512-bit vectors
1504 if (!VT.is512BitVector())
1505 continue;
1507 if ( EltSize >= 32) {
1508 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1509 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1510 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1511 setOperationAction(ISD::VSELECT, VT, Legal);
1512 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1513 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1514 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1515 }
1516 }
1517 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1518 MVT VT = (MVT::SimpleValueType)i;
1520 // Do not attempt to promote non-256-bit vectors
1521 if (!VT.is512BitVector())
1522 continue;
1524 setOperationAction(ISD::SELECT, VT, Promote);
1525 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1526 }
1527 }// has AVX-512
1529 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1530 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1531 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1533 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1534 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1536 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1537 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1538 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1539 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1541 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1542 const MVT VT = (MVT::SimpleValueType)i;
1544 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1546 // Do not attempt to promote non-256-bit vectors
1547 if (!VT.is512BitVector())
1548 continue;
1550 if ( EltSize < 32) {
1551 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1552 setOperationAction(ISD::VSELECT, VT, Legal);
1553 }
1554 }
1555 }
1557 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1558 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1559 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1561 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1562 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1563 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Legal);
1564 }
1566 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1567 // of this type with custom code.
1568 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1569 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1570 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1571 Custom);
1572 }
1574 // We want to custom lower some of our intrinsics.
1575 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1576 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1577 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1578 if (!Subtarget->is64Bit())
1579 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1581 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1582 // handle type legalization for these operations here.
1583 //
1584 // FIXME: We really should do custom legalization for addition and
1585 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1586 // than generic legalization for 64-bit multiplication-with-overflow, though.
1587 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1588 // Add/Sub/Mul with overflow operations are custom lowered.
1589 MVT VT = IntVTs[i];
1590 setOperationAction(ISD::SADDO, VT, Custom);
1591 setOperationAction(ISD::UADDO, VT, Custom);
1592 setOperationAction(ISD::SSUBO, VT, Custom);
1593 setOperationAction(ISD::USUBO, VT, Custom);
1594 setOperationAction(ISD::SMULO, VT, Custom);
1595 setOperationAction(ISD::UMULO, VT, Custom);
1596 }
1598 // There are no 8-bit 3-address imul/mul instructions
1599 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1600 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1602 if (!Subtarget->is64Bit()) {
1603 // These libcalls are not available in 32-bit.
1604 setLibcallName(RTLIB::SHL_I128, nullptr);
1605 setLibcallName(RTLIB::SRL_I128, nullptr);
1606 setLibcallName(RTLIB::SRA_I128, nullptr);
1607 }
1609 // Combine sin / cos into one node or libcall if possible.
1610 if (Subtarget->hasSinCos()) {
1611 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1612 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1613 if (Subtarget->isTargetDarwin()) {
1614 // For MacOSX, we don't want to the normal expansion of a libcall to
1615 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1616 // traffic.
1617 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1618 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1619 }
1620 }
1622 if (Subtarget->isTargetWin64()) {
1623 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1624 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1625 setOperationAction(ISD::SREM, MVT::i128, Custom);
1626 setOperationAction(ISD::UREM, MVT::i128, Custom);
1627 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1628 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1629 }
1631 // We have target-specific dag combine patterns for the following nodes:
1632 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1633 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1634 setTargetDAGCombine(ISD::VSELECT);
1635 setTargetDAGCombine(ISD::SELECT);
1636 setTargetDAGCombine(ISD::SHL);
1637 setTargetDAGCombine(ISD::SRA);
1638 setTargetDAGCombine(ISD::SRL);
1639 setTargetDAGCombine(ISD::OR);
1640 setTargetDAGCombine(ISD::AND);
1641 setTargetDAGCombine(ISD::ADD);
1642 setTargetDAGCombine(ISD::FADD);
1643 setTargetDAGCombine(ISD::FSUB);
1644 setTargetDAGCombine(ISD::FMA);
1645 setTargetDAGCombine(ISD::SUB);
1646 setTargetDAGCombine(ISD::LOAD);
1647 setTargetDAGCombine(ISD::STORE);
1648 setTargetDAGCombine(ISD::ZERO_EXTEND);
1649 setTargetDAGCombine(ISD::ANY_EXTEND);
1650 setTargetDAGCombine(ISD::SIGN_EXTEND);
1651 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1652 setTargetDAGCombine(ISD::TRUNCATE);
1653 setTargetDAGCombine(ISD::SINT_TO_FP);
1654 setTargetDAGCombine(ISD::SETCC);
1655 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1656 setTargetDAGCombine(ISD::BUILD_VECTOR);
1657 if (Subtarget->is64Bit())
1658 setTargetDAGCombine(ISD::MUL);
1659 setTargetDAGCombine(ISD::XOR);
1661 computeRegisterProperties();
1663 // On Darwin, -Os means optimize for size without hurting performance,
1664 // do not reduce the limit.
1665 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1666 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1667 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1668 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1669 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1670 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1671 setPrefLoopAlignment(4); // 2^4 bytes.
1673 // Predictable cmov don't hurt on atom because it's in-order.
1674 PredictableSelectIsExpensive = !Subtarget->isAtom();
1676 setPrefFunctionAlignment(4); // 2^4 bytes.
1678 verifyIntrinsicTables();
1679 }
1681 // This has so far only been implemented for 64-bit MachO.
1682 bool X86TargetLowering::useLoadStackGuardNode() const {
1683 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1684 Subtarget->is64Bit();
1685 }
1687 TargetLoweringBase::LegalizeTypeAction
1688 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1689 if (ExperimentalVectorWideningLegalization &&
1690 VT.getVectorNumElements() != 1 &&
1691 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1692 return TypeWidenVector;
1694 return TargetLoweringBase::getPreferredVectorAction(VT);
1695 }
1697 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1698 if (!VT.isVector())
1699 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1701 const unsigned NumElts = VT.getVectorNumElements();
1702 const EVT EltVT = VT.getVectorElementType();
1703 if (VT.is512BitVector()) {
1704 if (Subtarget->hasAVX512())
1705 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1706 EltVT == MVT::f32 || EltVT == MVT::f64)
1707 switch(NumElts) {
1708 case 8: return MVT::v8i1;
1709 case 16: return MVT::v16i1;
1710 }
1711 if (Subtarget->hasBWI())
1712 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1713 switch(NumElts) {
1714 case 32: return MVT::v32i1;
1715 case 64: return MVT::v64i1;
1716 }
1717 }
1719 if (VT.is256BitVector() || VT.is128BitVector()) {
1720 if (Subtarget->hasVLX())
1721 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1722 EltVT == MVT::f32 || EltVT == MVT::f64)
1723 switch(NumElts) {
1724 case 2: return MVT::v2i1;
1725 case 4: return MVT::v4i1;
1726 case 8: return MVT::v8i1;
1727 }
1728 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1729 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1730 switch(NumElts) {
1731 case 8: return MVT::v8i1;
1732 case 16: return MVT::v16i1;
1733 case 32: return MVT::v32i1;
1734 }
1735 }
1737 return VT.changeVectorElementTypeToInteger();
1738 }
1740 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1741 /// the desired ByVal argument alignment.
1742 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1743 if (MaxAlign == 16)
1744 return;
1745 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1746 if (VTy->getBitWidth() == 128)
1747 MaxAlign = 16;
1748 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1749 unsigned EltAlign = 0;
1750 getMaxByValAlign(ATy->getElementType(), EltAlign);
1751 if (EltAlign > MaxAlign)
1752 MaxAlign = EltAlign;
1753 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1754 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1755 unsigned EltAlign = 0;
1756 getMaxByValAlign(STy->getElementType(i), EltAlign);
1757 if (EltAlign > MaxAlign)
1758 MaxAlign = EltAlign;
1759 if (MaxAlign == 16)
1760 break;
1761 }
1762 }
1763 }
1765 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1766 /// function arguments in the caller parameter area. For X86, aggregates
1767 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1768 /// are at 4-byte boundaries.
1769 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1770 if (Subtarget->is64Bit()) {
1771 // Max of 8 and alignment of type.
1772 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1773 if (TyAlign > 8)
1774 return TyAlign;
1775 return 8;
1776 }
1778 unsigned Align = 4;
1779 if (Subtarget->hasSSE1())
1780 getMaxByValAlign(Ty, Align);
1781 return Align;
1782 }
1784 /// getOptimalMemOpType - Returns the target specific optimal type for load
1785 /// and store operations as a result of memset, memcpy, and memmove
1786 /// lowering. If DstAlign is zero that means it's safe to destination
1787 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1788 /// means there isn't a need to check it against alignment requirement,
1789 /// probably because the source does not need to be loaded. If 'IsMemset' is
1790 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1791 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1792 /// source is constant so it does not need to be loaded.
1793 /// It returns EVT::Other if the type should be determined using generic
1794 /// target-independent logic.
1795 EVT
1796 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1797 unsigned DstAlign, unsigned SrcAlign,
1798 bool IsMemset, bool ZeroMemset,
1799 bool MemcpyStrSrc,
1800 MachineFunction &MF) const {
1801 const Function *F = MF.getFunction();
1802 if ((!IsMemset || ZeroMemset) &&
1803 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1804 Attribute::NoImplicitFloat)) {
1805 if (Size >= 16 &&
1806 (Subtarget->isUnalignedMemAccessFast() ||
1807 ((DstAlign == 0 || DstAlign >= 16) &&
1808 (SrcAlign == 0 || SrcAlign >= 16)))) {
1809 if (Size >= 32) {
1810 if (Subtarget->hasInt256())
1811 return MVT::v8i32;
1812 if (Subtarget->hasFp256())
1813 return MVT::v8f32;
1814 }
1815 if (Subtarget->hasSSE2())
1816 return MVT::v4i32;
1817 if (Subtarget->hasSSE1())
1818 return MVT::v4f32;
1819 } else if (!MemcpyStrSrc && Size >= 8 &&
1820 !Subtarget->is64Bit() &&
1821 Subtarget->hasSSE2()) {
1822 // Do not use f64 to lower memcpy if source is string constant. It's
1823 // better to use i32 to avoid the loads.
1824 return MVT::f64;
1825 }
1826 }
1827 if (Subtarget->is64Bit() && Size >= 8)
1828 return MVT::i64;
1829 return MVT::i32;
1830 }
1832 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1833 if (VT == MVT::f32)
1834 return X86ScalarSSEf32;
1835 else if (VT == MVT::f64)
1836 return X86ScalarSSEf64;
1837 return true;
1838 }
1840 bool
1841 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1842 unsigned,
1843 unsigned,
1844 bool *Fast) const {
1845 if (Fast)
1846 *Fast = Subtarget->isUnalignedMemAccessFast();
1847 return true;
1848 }
1850 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1851 /// current function. The returned value is a member of the
1852 /// MachineJumpTableInfo::JTEntryKind enum.
1853 unsigned X86TargetLowering::getJumpTableEncoding() const {
1854 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1855 // symbol.
1856 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1857 Subtarget->isPICStyleGOT())
1858 return MachineJumpTableInfo::EK_Custom32;
1860 // Otherwise, use the normal jump table encoding heuristics.
1861 return TargetLowering::getJumpTableEncoding();
1862 }
1864 const MCExpr *
1865 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1866 const MachineBasicBlock *MBB,
1867 unsigned uid,MCContext &Ctx) const{
1868 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1869 Subtarget->isPICStyleGOT());
1870 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1871 // entries.
1872 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1873 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1874 }
1876 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1877 /// jumptable.
1878 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1879 SelectionDAG &DAG) const {
1880 if (!Subtarget->is64Bit())
1881 // This doesn't have SDLoc associated with it, but is not really the
1882 // same as a Register.
1883 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1884 return Table;
1885 }
1887 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1888 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1889 /// MCExpr.
1890 const MCExpr *X86TargetLowering::
1891 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1892 MCContext &Ctx) const {
1893 // X86-64 uses RIP relative addressing based on the jump table label.
1894 if (Subtarget->isPICStyleRIPRel())
1895 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1897 // Otherwise, the reference is relative to the PIC base.
1898 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1899 }
1901 // FIXME: Why this routine is here? Move to RegInfo!
1902 std::pair<const TargetRegisterClass*, uint8_t>
1903 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1904 const TargetRegisterClass *RRC = nullptr;
1905 uint8_t Cost = 1;
1906 switch (VT.SimpleTy) {
1907 default:
1908 return TargetLowering::findRepresentativeClass(VT);
1909 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1910 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1911 break;
1912 case MVT::x86mmx:
1913 RRC = &X86::VR64RegClass;
1914 break;
1915 case MVT::f32: case MVT::f64:
1916 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1917 case MVT::v4f32: case MVT::v2f64:
1918 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1919 case MVT::v4f64:
1920 RRC = &X86::VR128RegClass;
1921 break;
1922 }
1923 return std::make_pair(RRC, Cost);
1924 }
1926 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1927 unsigned &Offset) const {
1928 if (!Subtarget->isTargetLinux())
1929 return false;
1931 if (Subtarget->is64Bit()) {
1932 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1933 Offset = 0x28;
1934 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1935 AddressSpace = 256;
1936 else
1937 AddressSpace = 257;
1938 } else {
1939 // %gs:0x14 on i386
1940 Offset = 0x14;
1941 AddressSpace = 256;
1942 }
1943 return true;
1944 }
1946 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1947 unsigned DestAS) const {
1948 assert(SrcAS != DestAS && "Expected different address spaces!");
1950 return SrcAS < 256 && DestAS < 256;
1951 }
1953 //===----------------------------------------------------------------------===//
1954 // Return Value Calling Convention Implementation
1955 //===----------------------------------------------------------------------===//
1957 #include "X86GenCallingConv.inc"
1959 bool
1960 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1961 MachineFunction &MF, bool isVarArg,
1962 const SmallVectorImpl<ISD::OutputArg> &Outs,
1963 LLVMContext &Context) const {
1964 SmallVector<CCValAssign, 16> RVLocs;
1965 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1966 return CCInfo.CheckReturn(Outs, RetCC_X86);
1967 }
1969 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1970 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1971 return ScratchRegs;
1972 }
1974 SDValue
1975 X86TargetLowering::LowerReturn(SDValue Chain,
1976 CallingConv::ID CallConv, bool isVarArg,
1977 const SmallVectorImpl<ISD::OutputArg> &Outs,
1978 const SmallVectorImpl<SDValue> &OutVals,
1979 SDLoc dl, SelectionDAG &DAG) const {
1980 MachineFunction &MF = DAG.getMachineFunction();
1981 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1983 SmallVector<CCValAssign, 16> RVLocs;
1984 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1985 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1987 SDValue Flag;
1988 SmallVector<SDValue, 6> RetOps;
1989 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1990 // Operand #1 = Bytes To Pop
1991 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1992 MVT::i16));
1994 // Copy the result values into the output registers.
1995 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1996 CCValAssign &VA = RVLocs[i];
1997 assert(VA.isRegLoc() && "Can only return in registers!");
1998 SDValue ValToCopy = OutVals[i];
1999 EVT ValVT = ValToCopy.getValueType();
2001 // Promote values to the appropriate types
2002 if (VA.getLocInfo() == CCValAssign::SExt)
2003 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2004 else if (VA.getLocInfo() == CCValAssign::ZExt)
2005 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2006 else if (VA.getLocInfo() == CCValAssign::AExt)
2007 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2008 else if (VA.getLocInfo() == CCValAssign::BCvt)
2009 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2011 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2012 "Unexpected FP-extend for return value.");
2014 // If this is x86-64, and we disabled SSE, we can't return FP values,
2015 // or SSE or MMX vectors.
2016 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2017 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2018 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2019 report_fatal_error("SSE register return with SSE disabled");
2020 }
2021 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2022 // llvm-gcc has never done it right and no one has noticed, so this
2023 // should be OK for now.
2024 if (ValVT == MVT::f64 &&
2025 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2026 report_fatal_error("SSE2 register return with SSE2 disabled");
2028 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2029 // the RET instruction and handled by the FP Stackifier.
2030 if (VA.getLocReg() == X86::FP0 ||
2031 VA.getLocReg() == X86::FP1) {
2032 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2033 // change the value to the FP stack register class.
2034 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2035 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2036 RetOps.push_back(ValToCopy);
2037 // Don't emit a copytoreg.
2038 continue;
2039 }
2041 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2042 // which is returned in RAX / RDX.
2043 if (Subtarget->is64Bit()) {
2044 if (ValVT == MVT::x86mmx) {
2045 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2046 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2047 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2048 ValToCopy);
2049 // If we don't have SSE2 available, convert to v4f32 so the generated
2050 // register is legal.
2051 if (!Subtarget->hasSSE2())
2052 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2053 }
2054 }
2055 }
2057 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2058 Flag = Chain.getValue(1);
2059 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2060 }
2062 // The x86-64 ABIs require that for returning structs by value we copy
2063 // the sret argument into %rax/%eax (depending on ABI) for the return.
2064 // Win32 requires us to put the sret argument to %eax as well.
2065 // We saved the argument into a virtual register in the entry block,
2066 // so now we copy the value out and into %rax/%eax.
2067 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2068 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2069 MachineFunction &MF = DAG.getMachineFunction();
2070 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2071 unsigned Reg = FuncInfo->getSRetReturnReg();
2072 assert(Reg &&
2073 "SRetReturnReg should have been set in LowerFormalArguments().");
2074 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2076 unsigned RetValReg
2077 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2078 X86::RAX : X86::EAX;
2079 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2080 Flag = Chain.getValue(1);
2082 // RAX/EAX now acts like a return value.
2083 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2084 }
2086 RetOps[0] = Chain; // Update chain.
2088 // Add the flag if we have it.
2089 if (Flag.getNode())
2090 RetOps.push_back(Flag);
2092 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2093 }
2095 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2096 if (N->getNumValues() != 1)
2097 return false;
2098 if (!N->hasNUsesOfValue(1, 0))
2099 return false;
2101 SDValue TCChain = Chain;
2102 SDNode *Copy = *N->use_begin();
2103 if (Copy->getOpcode() == ISD::CopyToReg) {
2104 // If the copy has a glue operand, we conservatively assume it isn't safe to
2105 // perform a tail call.
2106 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2107 return false;
2108 TCChain = Copy->getOperand(0);
2109 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2110 return false;
2112 bool HasRet = false;
2113 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2114 UI != UE; ++UI) {
2115 if (UI->getOpcode() != X86ISD::RET_FLAG)
2116 return false;
2117 // If we are returning more than one value, we can definitely
2118 // not make a tail call see PR19530
2119 if (UI->getNumOperands() > 4)
2120 return false;
2121 if (UI->getNumOperands() == 4 &&
2122 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2123 return false;
2124 HasRet = true;
2125 }
2127 if (!HasRet)
2128 return false;
2130 Chain = TCChain;
2131 return true;
2132 }
2134 EVT
2135 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2136 ISD::NodeType ExtendKind) const {
2137 MVT ReturnMVT;
2138 // TODO: Is this also valid on 32-bit?
2139 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2140 ReturnMVT = MVT::i8;
2141 else
2142 ReturnMVT = MVT::i32;
2144 EVT MinVT = getRegisterType(Context, ReturnMVT);
2145 return VT.bitsLT(MinVT) ? MinVT : VT;
2146 }
2148 /// LowerCallResult - Lower the result values of a call into the
2149 /// appropriate copies out of appropriate physical registers.
2150 ///
2151 SDValue
2152 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2153 CallingConv::ID CallConv, bool isVarArg,
2154 const SmallVectorImpl<ISD::InputArg> &Ins,
2155 SDLoc dl, SelectionDAG &DAG,
2156 SmallVectorImpl<SDValue> &InVals) const {
2158 // Assign locations to each value returned by this call.
2159 SmallVector<CCValAssign, 16> RVLocs;
2160 bool Is64Bit = Subtarget->is64Bit();
2161 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2162 *DAG.getContext());
2163 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2165 // Copy all of the result registers out of their specified physreg.
2166 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2167 CCValAssign &VA = RVLocs[i];
2168 EVT CopyVT = VA.getValVT();
2170 // If this is x86-64, and we disabled SSE, we can't return FP values
2171 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2172 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2173 report_fatal_error("SSE register return with SSE disabled");
2174 }
2176 // If we prefer to use the value in xmm registers, copy it out as f80 and
2177 // use a truncate to move it from fp stack reg to xmm reg.
2178 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2179 isScalarFPTypeInSSEReg(VA.getValVT()))
2180 CopyVT = MVT::f80;
2182 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2183 CopyVT, InFlag).getValue(1);
2184 SDValue Val = Chain.getValue(0);
2186 if (CopyVT != VA.getValVT())
2187 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2188 // This truncation won't change the value.
2189 DAG.getIntPtrConstant(1));
2191 InFlag = Chain.getValue(2);
2192 InVals.push_back(Val);
2193 }
2195 return Chain;
2196 }
2198 //===----------------------------------------------------------------------===//
2199 // C & StdCall & Fast Calling Convention implementation
2200 //===----------------------------------------------------------------------===//
2201 // StdCall calling convention seems to be standard for many Windows' API
2202 // routines and around. It differs from C calling convention just a little:
2203 // callee should clean up the stack, not caller. Symbols should be also
2204 // decorated in some fancy way :) It doesn't support any vector arguments.
2205 // For info on fast calling convention see Fast Calling Convention (tail call)
2206 // implementation LowerX86_32FastCCCallTo.
2208 /// CallIsStructReturn - Determines whether a call uses struct return
2209 /// semantics.
2210 enum StructReturnType {
2211 NotStructReturn,
2212 RegStructReturn,
2213 StackStructReturn
2214 };
2215 static StructReturnType
2216 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2217 if (Outs.empty())
2218 return NotStructReturn;
2220 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2221 if (!Flags.isSRet())
2222 return NotStructReturn;
2223 if (Flags.isInReg())
2224 return RegStructReturn;
2225 return StackStructReturn;
2226 }
2228 /// ArgsAreStructReturn - Determines whether a function uses struct
2229 /// return semantics.
2230 static StructReturnType
2231 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2232 if (Ins.empty())
2233 return NotStructReturn;
2235 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2236 if (!Flags.isSRet())
2237 return NotStructReturn;
2238 if (Flags.isInReg())
2239 return RegStructReturn;
2240 return StackStructReturn;
2241 }
2243 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2244 /// by "Src" to address "Dst" with size and alignment information specified by
2245 /// the specific parameter attribute. The copy will be passed as a byval
2246 /// function parameter.
2247 static SDValue
2248 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2249 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2250 SDLoc dl) {
2251 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2253 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2254 /*isVolatile*/false, /*AlwaysInline=*/true,
2255 MachinePointerInfo(), MachinePointerInfo());
2256 }
2258 /// IsTailCallConvention - Return true if the calling convention is one that
2259 /// supports tail call optimization.
2260 static bool IsTailCallConvention(CallingConv::ID CC) {
2261 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2262 CC == CallingConv::HiPE);
2263 }
2265 /// \brief Return true if the calling convention is a C calling convention.
2266 static bool IsCCallConvention(CallingConv::ID CC) {
2267 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2268 CC == CallingConv::X86_64_SysV);
2269 }
2271 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2272 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2273 return false;
2275 CallSite CS(CI);
2276 CallingConv::ID CalleeCC = CS.getCallingConv();
2277 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2278 return false;
2280 return true;
2281 }
2283 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2284 /// a tailcall target by changing its ABI.
2285 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2286 bool GuaranteedTailCallOpt) {
2287 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2288 }
2290 SDValue
2291 X86TargetLowering::LowerMemArgument(SDValue Chain,
2292 CallingConv::ID CallConv,
2293 const SmallVectorImpl<ISD::InputArg> &Ins,
2294 SDLoc dl, SelectionDAG &DAG,
2295 const CCValAssign &VA,
2296 MachineFrameInfo *MFI,
2297 unsigned i) const {
2298 // Create the nodes corresponding to a load from this parameter slot.
2299 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2300 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2301 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2302 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2303 EVT ValVT;
2305 // If value is passed by pointer we have address passed instead of the value
2306 // itself.
2307 if (VA.getLocInfo() == CCValAssign::Indirect)
2308 ValVT = VA.getLocVT();
2309 else
2310 ValVT = VA.getValVT();
2312 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2313 // changed with more analysis.
2314 // In case of tail call optimization mark all arguments mutable. Since they
2315 // could be overwritten by lowering of arguments in case of a tail call.
2316 if (Flags.isByVal()) {
2317 unsigned Bytes = Flags.getByValSize();
2318 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2319 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2320 return DAG.getFrameIndex(FI, getPointerTy());
2321 } else {
2322 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2323 VA.getLocMemOffset(), isImmutable);
2324 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2325 return DAG.getLoad(ValVT, dl, Chain, FIN,
2326 MachinePointerInfo::getFixedStack(FI),
2327 false, false, false, 0);
2328 }
2329 }
2331 // FIXME: Get this from tablegen.
2332 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2333 const X86Subtarget *Subtarget) {
2334 assert(Subtarget->is64Bit());
2336 if (Subtarget->isCallingConvWin64(CallConv)) {
2337 static const MCPhysReg GPR64ArgRegsWin64[] = {
2338 X86::RCX, X86::RDX, X86::R8, X86::R9
2339 };
2340 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2341 }
2343 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2344 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2345 };
2346 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2347 }
2349 // FIXME: Get this from tablegen.
2350 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2351 CallingConv::ID CallConv,
2352 const X86Subtarget *Subtarget) {
2353 assert(Subtarget->is64Bit());
2354 if (Subtarget->isCallingConvWin64(CallConv)) {
2355 // The XMM registers which might contain var arg parameters are shadowed
2356 // in their paired GPR. So we only need to save the GPR to their home
2357 // slots.
2358 // TODO: __vectorcall will change this.
2359 return None;
2360 }
2362 const Function *Fn = MF.getFunction();
2363 bool NoImplicitFloatOps = Fn->getAttributes().
2364 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2365 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2366 "SSE register cannot be used when SSE is disabled!");
2367 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2368 !Subtarget->hasSSE1())
2369 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2370 // registers.
2371 return None;
2373 static const MCPhysReg XMMArgRegs64Bit[] = {
2374 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2375 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2376 };
2377 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2378 }
2380 SDValue
2381 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2382 CallingConv::ID CallConv,
2383 bool isVarArg,
2384 const SmallVectorImpl<ISD::InputArg> &Ins,
2385 SDLoc dl,
2386 SelectionDAG &DAG,
2387 SmallVectorImpl<SDValue> &InVals)
2388 const {
2389 MachineFunction &MF = DAG.getMachineFunction();
2390 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2392 const Function* Fn = MF.getFunction();
2393 if (Fn->hasExternalLinkage() &&
2394 Subtarget->isTargetCygMing() &&
2395 Fn->getName() == "main")
2396 FuncInfo->setForceFramePointer(true);
2398 MachineFrameInfo *MFI = MF.getFrameInfo();
2399 bool Is64Bit = Subtarget->is64Bit();
2400 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2402 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2403 "Var args not supported with calling convention fastcc, ghc or hipe");
2405 // Assign locations to all of the incoming arguments.
2406 SmallVector<CCValAssign, 16> ArgLocs;
2407 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2409 // Allocate shadow area for Win64
2410 if (IsWin64)
2411 CCInfo.AllocateStack(32, 8);
2413 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2415 unsigned LastVal = ~0U;
2416 SDValue ArgValue;
2417 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2418 CCValAssign &VA = ArgLocs[i];
2419 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2420 // places.
2421 assert(VA.getValNo() != LastVal &&
2422 "Don't support value assigned to multiple locs yet");
2423 (void)LastVal;
2424 LastVal = VA.getValNo();
2426 if (VA.isRegLoc()) {
2427 EVT RegVT = VA.getLocVT();
2428 const TargetRegisterClass *RC;
2429 if (RegVT == MVT::i32)
2430 RC = &X86::GR32RegClass;
2431 else if (Is64Bit && RegVT == MVT::i64)
2432 RC = &X86::GR64RegClass;
2433 else if (RegVT == MVT::f32)
2434 RC = &X86::FR32RegClass;
2435 else if (RegVT == MVT::f64)
2436 RC = &X86::FR64RegClass;
2437 else if (RegVT.is512BitVector())
2438 RC = &X86::VR512RegClass;
2439 else if (RegVT.is256BitVector())
2440 RC = &X86::VR256RegClass;
2441 else if (RegVT.is128BitVector())
2442 RC = &X86::VR128RegClass;
2443 else if (RegVT == MVT::x86mmx)
2444 RC = &X86::VR64RegClass;
2445 else if (RegVT == MVT::i1)
2446 RC = &X86::VK1RegClass;
2447 else if (RegVT == MVT::v8i1)
2448 RC = &X86::VK8RegClass;
2449 else if (RegVT == MVT::v16i1)
2450 RC = &X86::VK16RegClass;
2451 else if (RegVT == MVT::v32i1)
2452 RC = &X86::VK32RegClass;
2453 else if (RegVT == MVT::v64i1)
2454 RC = &X86::VK64RegClass;
2455 else
2456 llvm_unreachable("Unknown argument type!");
2458 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2459 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2461 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2462 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2463 // right size.
2464 if (VA.getLocInfo() == CCValAssign::SExt)
2465 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2466 DAG.getValueType(VA.getValVT()));
2467 else if (VA.getLocInfo() == CCValAssign::ZExt)
2468 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2469 DAG.getValueType(VA.getValVT()));
2470 else if (VA.getLocInfo() == CCValAssign::BCvt)
2471 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2473 if (VA.isExtInLoc()) {
2474 // Handle MMX values passed in XMM regs.
2475 if (RegVT.isVector())
2476 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2477 else
2478 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2479 }
2480 } else {
2481 assert(VA.isMemLoc());
2482 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2483 }
2485 // If value is passed via pointer - do a load.
2486 if (VA.getLocInfo() == CCValAssign::Indirect)
2487 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2488 MachinePointerInfo(), false, false, false, 0);
2490 InVals.push_back(ArgValue);
2491 }
2493 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2494 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2495 // The x86-64 ABIs require that for returning structs by value we copy
2496 // the sret argument into %rax/%eax (depending on ABI) for the return.
2497 // Win32 requires us to put the sret argument to %eax as well.
2498 // Save the argument into a virtual register so that we can access it
2499 // from the return points.
2500 if (Ins[i].Flags.isSRet()) {
2501 unsigned Reg = FuncInfo->getSRetReturnReg();
2502 if (!Reg) {
2503 MVT PtrTy = getPointerTy();
2504 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2505 FuncInfo->setSRetReturnReg(Reg);
2506 }
2507 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2508 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2509 break;
2510 }
2511 }
2512 }
2514 unsigned StackSize = CCInfo.getNextStackOffset();
2515 // Align stack specially for tail calls.
2516 if (FuncIsMadeTailCallSafe(CallConv,
2517 MF.getTarget().Options.GuaranteedTailCallOpt))
2518 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2520 // If the function takes variable number of arguments, make a frame index for
2521 // the start of the first vararg value... for expansion of llvm.va_start. We
2522 // can skip this if there are no va_start calls.
2523 if (MFI->hasVAStart() &&
2524 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2525 CallConv != CallingConv::X86_ThisCall))) {
2526 FuncInfo->setVarArgsFrameIndex(
2527 MFI->CreateFixedObject(1, StackSize, true));
2528 }
2530 // 64-bit calling conventions support varargs and register parameters, so we
2531 // have to do extra work to spill them in the prologue or forward them to
2532 // musttail calls.
2533 if (Is64Bit && isVarArg &&
2534 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2535 // Find the first unallocated argument registers.
2536 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2537 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2538 unsigned NumIntRegs =
2539 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2540 unsigned NumXMMRegs =
2541 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2542 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2543 "SSE register cannot be used when SSE is disabled!");
2545 // Gather all the live in physical registers.
2546 SmallVector<SDValue, 6> LiveGPRs;
2547 SmallVector<SDValue, 8> LiveXMMRegs;
2548 SDValue ALVal;
2549 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2550 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2551 LiveGPRs.push_back(
2552 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2553 }
2554 if (!ArgXMMs.empty()) {
2555 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2556 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2557 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2558 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2559 LiveXMMRegs.push_back(
2560 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2561 }
2562 }
2564 // Store them to the va_list returned by va_start.
2565 if (MFI->hasVAStart()) {
2566 if (IsWin64) {
2567 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2568 // Get to the caller-allocated home save location. Add 8 to account
2569 // for the return address.
2570 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2571 FuncInfo->setRegSaveFrameIndex(
2572 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2573 // Fixup to set vararg frame on shadow area (4 x i64).
2574 if (NumIntRegs < 4)
2575 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2576 } else {
2577 // For X86-64, if there are vararg parameters that are passed via
2578 // registers, then we must store them to their spots on the stack so
2579 // they may be loaded by deferencing the result of va_next.
2580 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2581 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2582 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2583 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2584 }
2586 // Store the integer parameter registers.
2587 SmallVector<SDValue, 8> MemOps;
2588 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2589 getPointerTy());
2590 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2591 for (SDValue Val : LiveGPRs) {
2592 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2593 DAG.getIntPtrConstant(Offset));
2594 SDValue Store =
2595 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2596 MachinePointerInfo::getFixedStack(
2597 FuncInfo->getRegSaveFrameIndex(), Offset),
2598 false, false, 0);
2599 MemOps.push_back(Store);
2600 Offset += 8;
2601 }
2603 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2604 // Now store the XMM (fp + vector) parameter registers.
2605 SmallVector<SDValue, 12> SaveXMMOps;
2606 SaveXMMOps.push_back(Chain);
2607 SaveXMMOps.push_back(ALVal);
2608 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2609 FuncInfo->getRegSaveFrameIndex()));
2610 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2611 FuncInfo->getVarArgsFPOffset()));
2612 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2613 LiveXMMRegs.end());
2614 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2615 MVT::Other, SaveXMMOps));
2616 }
2618 if (!MemOps.empty())
2619 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2620 } else {
2621 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2622 // to the liveout set on a musttail call.
2623 assert(MFI->hasMustTailInVarArgFunc());
2624 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2625 typedef X86MachineFunctionInfo::Forward Forward;
2627 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2628 unsigned VReg =
2629 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2630 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2631 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2632 }
2634 if (!ArgXMMs.empty()) {
2635 unsigned ALVReg =
2636 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2637 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2638 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2640 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2641 unsigned VReg =
2642 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2643 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2644 Forwards.push_back(
2645 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2646 }
2647 }
2648 }
2649 }
2651 // Some CCs need callee pop.
2652 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2653 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2654 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2655 } else {
2656 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2657 // If this is an sret function, the return should pop the hidden pointer.
2658 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2659 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2660 argsAreStructReturn(Ins) == StackStructReturn)
2661 FuncInfo->setBytesToPopOnReturn(4);
2662 }
2664 if (!Is64Bit) {
2665 // RegSaveFrameIndex is X86-64 only.
2666 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2667 if (CallConv == CallingConv::X86_FastCall ||
2668 CallConv == CallingConv::X86_ThisCall)
2669 // fastcc functions can't have varargs.
2670 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2671 }
2673 FuncInfo->setArgumentStackSize(StackSize);
2675 return Chain;
2676 }
2678 SDValue
2679 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2680 SDValue StackPtr, SDValue Arg,
2681 SDLoc dl, SelectionDAG &DAG,
2682 const CCValAssign &VA,
2683 ISD::ArgFlagsTy Flags) const {
2684 unsigned LocMemOffset = VA.getLocMemOffset();
2685 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2686 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2687 if (Flags.isByVal())
2688 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2690 return DAG.getStore(Chain, dl, Arg, PtrOff,
2691 MachinePointerInfo::getStack(LocMemOffset),
2692 false, false, 0);
2693 }
2695 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2696 /// optimization is performed and it is required.
2697 SDValue
2698 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2699 SDValue &OutRetAddr, SDValue Chain,
2700 bool IsTailCall, bool Is64Bit,
2701 int FPDiff, SDLoc dl) const {
2702 // Adjust the Return address stack slot.
2703 EVT VT = getPointerTy();
2704 OutRetAddr = getReturnAddressFrameIndex(DAG);
2706 // Load the "old" Return address.
2707 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2708 false, false, false, 0);
2709 return SDValue(OutRetAddr.getNode(), 1);
2710 }
2712 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2713 /// optimization is performed and it is required (FPDiff!=0).
2714 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2715 SDValue Chain, SDValue RetAddrFrIdx,
2716 EVT PtrVT, unsigned SlotSize,
2717 int FPDiff, SDLoc dl) {
2718 // Store the return address to the appropriate stack slot.
2719 if (!FPDiff) return Chain;
2720 // Calculate the new stack slot for the return address.
2721 int NewReturnAddrFI =
2722 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2723 false);
2724 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2725 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2726 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2727 false, false, 0);
2728 return Chain;
2729 }
2731 SDValue
2732 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2733 SmallVectorImpl<SDValue> &InVals) const {
2734 SelectionDAG &DAG = CLI.DAG;
2735 SDLoc &dl = CLI.DL;
2736 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2737 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2738 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2739 SDValue Chain = CLI.Chain;
2740 SDValue Callee = CLI.Callee;
2741 CallingConv::ID CallConv = CLI.CallConv;
2742 bool &isTailCall = CLI.IsTailCall;
2743 bool isVarArg = CLI.IsVarArg;
2745 MachineFunction &MF = DAG.getMachineFunction();
2746 bool Is64Bit = Subtarget->is64Bit();
2747 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2748 StructReturnType SR = callIsStructReturn(Outs);
2749 bool IsSibcall = false;
2750 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2752 if (MF.getTarget().Options.DisableTailCalls)
2753 isTailCall = false;
2755 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2756 if (IsMustTail) {
2757 // Force this to be a tail call. The verifier rules are enough to ensure
2758 // that we can lower this successfully without moving the return address
2759 // around.
2760 isTailCall = true;
2761 } else if (isTailCall) {
2762 // Check if it's really possible to do a tail call.
2763 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2764 isVarArg, SR != NotStructReturn,
2765 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2766 Outs, OutVals, Ins, DAG);
2768 // Sibcalls are automatically detected tailcalls which do not require
2769 // ABI changes.
2770 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2771 IsSibcall = true;
2773 if (isTailCall)
2774 ++NumTailCalls;
2775 }
2777 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2778 "Var args not supported with calling convention fastcc, ghc or hipe");
2780 // Analyze operands of the call, assigning locations to each operand.
2781 SmallVector<CCValAssign, 16> ArgLocs;
2782 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2784 // Allocate shadow area for Win64
2785 if (IsWin64)
2786 CCInfo.AllocateStack(32, 8);
2788 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2790 // Get a count of how many bytes are to be pushed on the stack.
2791 unsigned NumBytes = CCInfo.getNextStackOffset();
2792 if (IsSibcall)
2793 // This is a sibcall. The memory operands are available in caller's
2794 // own caller's stack.
2795 NumBytes = 0;
2796 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2797 IsTailCallConvention(CallConv))
2798 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2800 int FPDiff = 0;
2801 if (isTailCall && !IsSibcall && !IsMustTail) {
2802 // Lower arguments at fp - stackoffset + fpdiff.
2803 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2805 FPDiff = NumBytesCallerPushed - NumBytes;
2807 // Set the delta of movement of the returnaddr stackslot.
2808 // But only set if delta is greater than previous delta.
2809 if (FPDiff < X86Info->getTCReturnAddrDelta())
2810 X86Info->setTCReturnAddrDelta(FPDiff);
2811 }
2813 unsigned NumBytesToPush = NumBytes;
2814 unsigned NumBytesToPop = NumBytes;
2816 // If we have an inalloca argument, all stack space has already been allocated
2817 // for us and be right at the top of the stack. We don't support multiple
2818 // arguments passed in memory when using inalloca.
2819 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2820 NumBytesToPush = 0;
2821 if (!ArgLocs.back().isMemLoc())
2822 report_fatal_error("cannot use inalloca attribute on a register "
2823 "parameter");
2824 if (ArgLocs.back().getLocMemOffset() != 0)
2825 report_fatal_error("any parameter with the inalloca attribute must be "
2826 "the only memory argument");
2827 }
2829 if (!IsSibcall)
2830 Chain = DAG.getCALLSEQ_START(
2831 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2833 SDValue RetAddrFrIdx;
2834 // Load return address for tail calls.
2835 if (isTailCall && FPDiff)
2836 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2837 Is64Bit, FPDiff, dl);
2839 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2840 SmallVector<SDValue, 8> MemOpChains;
2841 SDValue StackPtr;
2843 // Walk the register/memloc assignments, inserting copies/loads. In the case
2844 // of tail call optimization arguments are handle later.
2845 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2846 DAG.getSubtarget().getRegisterInfo());
2847 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2848 // Skip inalloca arguments, they have already been written.
2849 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2850 if (Flags.isInAlloca())
2851 continue;
2853 CCValAssign &VA = ArgLocs[i];
2854 EVT RegVT = VA.getLocVT();
2855 SDValue Arg = OutVals[i];
2856 bool isByVal = Flags.isByVal();
2858 // Promote the value if needed.
2859 switch (VA.getLocInfo()) {
2860 default: llvm_unreachable("Unknown loc info!");
2861 case CCValAssign::Full: break;
2862 case CCValAssign::SExt:
2863 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2864 break;
2865 case CCValAssign::ZExt:
2866 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2867 break;
2868 case CCValAssign::AExt:
2869 if (RegVT.is128BitVector()) {
2870 // Special case: passing MMX values in XMM registers.
2871 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2872 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2873 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2874 } else
2875 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2876 break;
2877 case CCValAssign::BCvt:
2878 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2879 break;
2880 case CCValAssign::Indirect: {
2881 // Store the argument.
2882 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2883 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2884 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2885 MachinePointerInfo::getFixedStack(FI),
2886 false, false, 0);
2887 Arg = SpillSlot;
2888 break;
2889 }
2890 }
2892 if (VA.isRegLoc()) {
2893 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2894 if (isVarArg && IsWin64) {
2895 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2896 // shadow reg if callee is a varargs function.
2897 unsigned ShadowReg = 0;
2898 switch (VA.getLocReg()) {
2899 case X86::XMM0: ShadowReg = X86::RCX; break;
2900 case X86::XMM1: ShadowReg = X86::RDX; break;
2901 case X86::XMM2: ShadowReg = X86::R8; break;
2902 case X86::XMM3: ShadowReg = X86::R9; break;
2903 }
2904 if (ShadowReg)
2905 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2906 }
2907 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2908 assert(VA.isMemLoc());
2909 if (!StackPtr.getNode())
2910 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2911 getPointerTy());
2912 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2913 dl, DAG, VA, Flags));
2914 }
2915 }
2917 if (!MemOpChains.empty())
2918 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2920 if (Subtarget->isPICStyleGOT()) {
2921 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2922 // GOT pointer.
2923 if (!isTailCall) {
2924 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2925 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2926 } else {
2927 // If we are tail calling and generating PIC/GOT style code load the
2928 // address of the callee into ECX. The value in ecx is used as target of
2929 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2930 // for tail calls on PIC/GOT architectures. Normally we would just put the
2931 // address of GOT into ebx and then call target@PLT. But for tail calls
2932 // ebx would be restored (since ebx is callee saved) before jumping to the
2933 // target@PLT.
2935 // Note: The actual moving to ECX is done further down.
2936 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2937 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2938 !G->getGlobal()->hasProtectedVisibility())
2939 Callee = LowerGlobalAddress(Callee, DAG);
2940 else if (isa<ExternalSymbolSDNode>(Callee))
2941 Callee = LowerExternalSymbol(Callee, DAG);
2942 }
2943 }
2945 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2946 // From AMD64 ABI document:
2947 // For calls that may call functions that use varargs or stdargs
2948 // (prototype-less calls or calls to functions containing ellipsis (...) in
2949 // the declaration) %al is used as hidden argument to specify the number
2950 // of SSE registers used. The contents of %al do not need to match exactly
2951 // the number of registers, but must be an ubound on the number of SSE
2952 // registers used and is in the range 0 - 8 inclusive.
2954 // Count the number of XMM registers allocated.
2955 static const MCPhysReg XMMArgRegs[] = {
2956 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2957 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2958 };
2959 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2960 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2961 && "SSE registers cannot be used when SSE is disabled");
2963 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2964 DAG.getConstant(NumXMMRegs, MVT::i8)));
2965 }
2967 if (Is64Bit && isVarArg && IsMustTail) {
2968 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2969 for (const auto &F : Forwards) {
2970 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2971 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2972 }
2973 }
2975 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2976 // don't need this because the eligibility check rejects calls that require
2977 // shuffling arguments passed in memory.
2978 if (!IsSibcall && isTailCall) {
2979 // Force all the incoming stack arguments to be loaded from the stack
2980 // before any new outgoing arguments are stored to the stack, because the
2981 // outgoing stack slots may alias the incoming argument stack slots, and
2982 // the alias isn't otherwise explicit. This is slightly more conservative
2983 // than necessary, because it means that each store effectively depends
2984 // on every argument instead of just those arguments it would clobber.
2985 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2987 SmallVector<SDValue, 8> MemOpChains2;
2988 SDValue FIN;
2989 int FI = 0;
2990 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2991 CCValAssign &VA = ArgLocs[i];
2992 if (VA.isRegLoc())
2993 continue;
2994 assert(VA.isMemLoc());
2995 SDValue Arg = OutVals[i];
2996 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2997 // Skip inalloca arguments. They don't require any work.
2998 if (Flags.isInAlloca())
2999 continue;
3000 // Create frame index.
3001 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3002 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3003 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3004 FIN = DAG.getFrameIndex(FI, getPointerTy());
3006 if (Flags.isByVal()) {
3007 // Copy relative to framepointer.
3008 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3009 if (!StackPtr.getNode())
3010 StackPtr = DAG.getCopyFromReg(Chain, dl,
3011 RegInfo->getStackRegister(),
3012 getPointerTy());
3013 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3015 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3016 ArgChain,
3017 Flags, DAG, dl));
3018 } else {
3019 // Store relative to framepointer.
3020 MemOpChains2.push_back(
3021 DAG.getStore(ArgChain, dl, Arg, FIN,
3022 MachinePointerInfo::getFixedStack(FI),
3023 false, false, 0));
3024 }
3025 }
3027 if (!MemOpChains2.empty())
3028 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3030 // Store the return address to the appropriate stack slot.
3031 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3032 getPointerTy(), RegInfo->getSlotSize(),
3033 FPDiff, dl);
3034 }
3036 // Build a sequence of copy-to-reg nodes chained together with token chain
3037 // and flag operands which copy the outgoing args into registers.
3038 SDValue InFlag;
3039 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3040 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3041 RegsToPass[i].second, InFlag);
3042 InFlag = Chain.getValue(1);
3043 }
3045 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3046 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3047 // In the 64-bit large code model, we have to make all calls
3048 // through a register, since the call instruction's 32-bit
3049 // pc-relative offset may not be large enough to hold the whole
3050 // address.
3051 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3052 // If the callee is a GlobalAddress node (quite common, every direct call
3053 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3054 // it.
3056 // We should use extra load for direct calls to dllimported functions in
3057 // non-JIT mode.
3058 const GlobalValue *GV = G->getGlobal();
3059 if (!GV->hasDLLImportStorageClass()) {
3060 unsigned char OpFlags = 0;
3061 bool ExtraLoad = false;
3062 unsigned WrapperKind = ISD::DELETED_NODE;
3064 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3065 // external symbols most go through the PLT in PIC mode. If the symbol
3066 // has hidden or protected visibility, or if it is static or local, then
3067 // we don't need to use the PLT - we can directly call it.
3068 if (Subtarget->isTargetELF() &&
3069 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3070 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3071 OpFlags = X86II::MO_PLT;
3072 } else if (Subtarget->isPICStyleStubAny() &&
3073 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3074 (!Subtarget->getTargetTriple().isMacOSX() ||
3075 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3076 // PC-relative references to external symbols should go through $stub,
3077 // unless we're building with the leopard linker or later, which
3078 // automatically synthesizes these stubs.
3079 OpFlags = X86II::MO_DARWIN_STUB;
3080 } else if (Subtarget->isPICStyleRIPRel() &&
3081 isa<Function>(GV) &&
3082 cast<Function>(GV)->getAttributes().
3083 hasAttribute(AttributeSet::FunctionIndex,
3084 Attribute::NonLazyBind)) {
3085 // If the function is marked as non-lazy, generate an indirect call
3086 // which loads from the GOT directly. This avoids runtime overhead
3087 // at the cost of eager binding (and one extra byte of encoding).
3088 OpFlags = X86II::MO_GOTPCREL;
3089 WrapperKind = X86ISD::WrapperRIP;
3090 ExtraLoad = true;
3091 }
3093 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3094 G->getOffset(), OpFlags);
3096 // Add a wrapper if needed.
3097 if (WrapperKind != ISD::DELETED_NODE)
3098 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3099 // Add extra indirection if needed.
3100 if (ExtraLoad)
3101 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3102 MachinePointerInfo::getGOT(),
3103 false, false, false, 0);
3104 }
3105 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3106 unsigned char OpFlags = 0;
3108 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3109 // external symbols should go through the PLT.
3110 if (Subtarget->isTargetELF() &&
3111 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3112 OpFlags = X86II::MO_PLT;
3113 } else if (Subtarget->isPICStyleStubAny() &&
3114 (!Subtarget->getTargetTriple().isMacOSX() ||
3115 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3116 // PC-relative references to external symbols should go through $stub,
3117 // unless we're building with the leopard linker or later, which
3118 // automatically synthesizes these stubs.
3119 OpFlags = X86II::MO_DARWIN_STUB;
3120 }
3122 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3123 OpFlags);
3124 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3125 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3126 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3127 }
3129 // Returns a chain & a flag for retval copy to use.
3130 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3131 SmallVector<SDValue, 8> Ops;
3133 if (!IsSibcall && isTailCall) {
3134 Chain = DAG.getCALLSEQ_END(Chain,
3135 DAG.getIntPtrConstant(NumBytesToPop, true),
3136 DAG.getIntPtrConstant(0, true), InFlag, dl);
3137 InFlag = Chain.getValue(1);
3138 }
3140 Ops.push_back(Chain);
3141 Ops.push_back(Callee);
3143 if (isTailCall)
3144 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3146 // Add argument registers to the end of the list so that they are known live
3147 // into the call.
3148 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3149 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3150 RegsToPass[i].second.getValueType()));
3152 // Add a register mask operand representing the call-preserved registers.
3153 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3154 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3155 assert(Mask && "Missing call preserved mask for calling convention");
3156 Ops.push_back(DAG.getRegisterMask(Mask));
3158 if (InFlag.getNode())
3159 Ops.push_back(InFlag);
3161 if (isTailCall) {
3162 // We used to do:
3163 //// If this is the first return lowered for this function, add the regs
3164 //// to the liveout set for the function.
3165 // This isn't right, although it's probably harmless on x86; liveouts
3166 // should be computed from returns not tail calls. Consider a void
3167 // function making a tail call to a function returning int.
3168 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3169 }
3171 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3172 InFlag = Chain.getValue(1);
3174 // Create the CALLSEQ_END node.
3175 unsigned NumBytesForCalleeToPop;
3176 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3177 DAG.getTarget().Options.GuaranteedTailCallOpt))
3178 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3179 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3180 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3181 SR == StackStructReturn)
3182 // If this is a call to a struct-return function, the callee
3183 // pops the hidden struct pointer, so we have to push it back.
3184 // This is common for Darwin/X86, Linux & Mingw32 targets.
3185 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3186 NumBytesForCalleeToPop = 4;
3187 else
3188 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3190 // Returns a flag for retval copy to use.
3191 if (!IsSibcall) {
3192 Chain = DAG.getCALLSEQ_END(Chain,
3193 DAG.getIntPtrConstant(NumBytesToPop, true),
3194 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3195 true),
3196 InFlag, dl);
3197 InFlag = Chain.getValue(1);
3198 }
3200 // Handle result values, copying them out of physregs into vregs that we
3201 // return.
3202 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3203 Ins, dl, DAG, InVals);
3204 }
3206 //===----------------------------------------------------------------------===//
3207 // Fast Calling Convention (tail call) implementation
3208 //===----------------------------------------------------------------------===//
3210 // Like std call, callee cleans arguments, convention except that ECX is
3211 // reserved for storing the tail called function address. Only 2 registers are
3212 // free for argument passing (inreg). Tail call optimization is performed
3213 // provided:
3214 // * tailcallopt is enabled
3215 // * caller/callee are fastcc
3216 // On X86_64 architecture with GOT-style position independent code only local
3217 // (within module) calls are supported at the moment.
3218 // To keep the stack aligned according to platform abi the function
3219 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3220 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3221 // If a tail called function callee has more arguments than the caller the
3222 // caller needs to make sure that there is room to move the RETADDR to. This is
3223 // achieved by reserving an area the size of the argument delta right after the
3224 // original RETADDR, but before the saved framepointer or the spilled registers
3225 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3226 // stack layout:
3227 // arg1
3228 // arg2
3229 // RETADDR
3230 // [ new RETADDR
3231 // move area ]
3232 // (possible EBP)
3233 // ESI
3234 // EDI
3235 // local1 ..
3237 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3238 /// for a 16 byte align requirement.
3239 unsigned
3240 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3241 SelectionDAG& DAG) const {
3242 MachineFunction &MF = DAG.getMachineFunction();
3243 const TargetMachine &TM = MF.getTarget();
3244 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3245 TM.getSubtargetImpl()->getRegisterInfo());
3246 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3247 unsigned StackAlignment = TFI.getStackAlignment();
3248 uint64_t AlignMask = StackAlignment - 1;
3249 int64_t Offset = StackSize;
3250 unsigned SlotSize = RegInfo->getSlotSize();
3251 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3252 // Number smaller than 12 so just add the difference.
3253 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3254 } else {
3255 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3256 Offset = ((~AlignMask) & Offset) + StackAlignment +
3257 (StackAlignment-SlotSize);
3258 }
3259 return Offset;
3260 }
3262 /// MatchingStackOffset - Return true if the given stack call argument is
3263 /// already available in the same position (relatively) of the caller's
3264 /// incoming argument stack.
3265 static
3266 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3267 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3268 const X86InstrInfo *TII) {
3269 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3270 int FI = INT_MAX;
3271 if (Arg.getOpcode() == ISD::CopyFromReg) {
3272 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3273 if (!TargetRegisterInfo::isVirtualRegister(VR))
3274 return false;
3275 MachineInstr *Def = MRI->getVRegDef(VR);
3276 if (!Def)
3277 return false;
3278 if (!Flags.isByVal()) {
3279 if (!TII->isLoadFromStackSlot(Def, FI))
3280 return false;
3281 } else {
3282 unsigned Opcode = Def->getOpcode();
3283 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3284 Def->getOperand(1).isFI()) {
3285 FI = Def->getOperand(1).getIndex();
3286 Bytes = Flags.getByValSize();
3287 } else
3288 return false;
3289 }
3290 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3291 if (Flags.isByVal())
3292 // ByVal argument is passed in as a pointer but it's now being
3293 // dereferenced. e.g.
3294 // define @foo(%struct.X* %A) {
3295 // tail call @bar(%struct.X* byval %A)
3296 // }
3297 return false;
3298 SDValue Ptr = Ld->getBasePtr();
3299 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3300 if (!FINode)
3301 return false;
3302 FI = FINode->getIndex();
3303 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3304 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3305 FI = FINode->getIndex();
3306 Bytes = Flags.getByValSize();
3307 } else
3308 return false;
3310 assert(FI != INT_MAX);
3311 if (!MFI->isFixedObjectIndex(FI))
3312 return false;
3313 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3314 }
3316 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3317 /// for tail call optimization. Targets which want to do tail call
3318 /// optimization should implement this function.
3319 bool
3320 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3321 CallingConv::ID CalleeCC,
3322 bool isVarArg,
3323 bool isCalleeStructRet,
3324 bool isCallerStructRet,
3325 Type *RetTy,
3326 const SmallVectorImpl<ISD::OutputArg> &Outs,
3327 const SmallVectorImpl<SDValue> &OutVals,
3328 const SmallVectorImpl<ISD::InputArg> &Ins,
3329 SelectionDAG &DAG) const {
3330 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3331 return false;
3333 // If -tailcallopt is specified, make fastcc functions tail-callable.
3334 const MachineFunction &MF = DAG.getMachineFunction();
3335 const Function *CallerF = MF.getFunction();
3337 // If the function return type is x86_fp80 and the callee return type is not,
3338 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3339 // perform a tailcall optimization here.
3340 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3341 return false;
3343 CallingConv::ID CallerCC = CallerF->getCallingConv();
3344 bool CCMatch = CallerCC == CalleeCC;
3345 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3346 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3348 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3349 if (IsTailCallConvention(CalleeCC) && CCMatch)
3350 return true;
3351 return false;
3352 }
3354 // Look for obvious safe cases to perform tail call optimization that do not
3355 // require ABI changes. This is what gcc calls sibcall.
3357 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3358 // emit a special epilogue.
3359 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3360 DAG.getSubtarget().getRegisterInfo());
3361 if (RegInfo->needsStackRealignment(MF))
3362 return false;
3364 // Also avoid sibcall optimization if either caller or callee uses struct
3365 // return semantics.
3366 if (isCalleeStructRet || isCallerStructRet)
3367 return false;
3369 // An stdcall/thiscall caller is expected to clean up its arguments; the
3370 // callee isn't going to do that.
3371 // FIXME: this is more restrictive than needed. We could produce a tailcall
3372 // when the stack adjustment matches. For example, with a thiscall that takes
3373 // only one argument.
3374 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3375 CallerCC == CallingConv::X86_ThisCall))
3376 return false;
3378 // Do not sibcall optimize vararg calls unless all arguments are passed via
3379 // registers.
3380 if (isVarArg && !Outs.empty()) {
3382 // Optimizing for varargs on Win64 is unlikely to be safe without
3383 // additional testing.
3384 if (IsCalleeWin64 || IsCallerWin64)
3385 return false;
3387 SmallVector<CCValAssign, 16> ArgLocs;
3388 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3389 *DAG.getContext());
3391 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3392 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3393 if (!ArgLocs[i].isRegLoc())
3394 return false;
3395 }
3397 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3398 // stack. Therefore, if it's not used by the call it is not safe to optimize
3399 // this into a sibcall.
3400 bool Unused = false;
3401 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3402 if (!Ins[i].Used) {
3403 Unused = true;
3404 break;
3405 }
3406 }
3407 if (Unused) {
3408 SmallVector<CCValAssign, 16> RVLocs;
3409 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3410 *DAG.getContext());
3411 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3412 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3413 CCValAssign &VA = RVLocs[i];
3414 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3415 return false;
3416 }
3417 }
3419 // If the calling conventions do not match, then we'd better make sure the
3420 // results are returned in the same way as what the caller expects.
3421 if (!CCMatch) {
3422 SmallVector<CCValAssign, 16> RVLocs1;
3423 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3424 *DAG.getContext());
3425 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3427 SmallVector<CCValAssign, 16> RVLocs2;
3428 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3429 *DAG.getContext());
3430 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3432 if (RVLocs1.size() != RVLocs2.size())
3433 return false;
3434 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3435 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3436 return false;
3437 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3438 return false;
3439 if (RVLocs1[i].isRegLoc()) {
3440 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3441 return false;
3442 } else {
3443 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3444 return false;
3445 }
3446 }
3447 }
3449 // If the callee takes no arguments then go on to check the results of the
3450 // call.
3451 if (!Outs.empty()) {
3452 // Check if stack adjustment is needed. For now, do not do this if any
3453 // argument is passed on the stack.
3454 SmallVector<CCValAssign, 16> ArgLocs;
3455 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3456 *DAG.getContext());
3458 // Allocate shadow area for Win64
3459 if (IsCalleeWin64)
3460 CCInfo.AllocateStack(32, 8);
3462 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3463 if (CCInfo.getNextStackOffset()) {
3464 MachineFunction &MF = DAG.getMachineFunction();
3465 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3466 return false;
3468 // Check if the arguments are already laid out in the right way as
3469 // the caller's fixed stack objects.
3470 MachineFrameInfo *MFI = MF.getFrameInfo();
3471 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3472 const X86InstrInfo *TII =
3473 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3474 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3475 CCValAssign &VA = ArgLocs[i];
3476 SDValue Arg = OutVals[i];
3477 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3478 if (VA.getLocInfo() == CCValAssign::Indirect)
3479 return false;
3480 if (!VA.isRegLoc()) {
3481 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3482 MFI, MRI, TII))
3483 return false;
3484 }
3485 }
3486 }
3488 // If the tailcall address may be in a register, then make sure it's
3489 // possible to register allocate for it. In 32-bit, the call address can
3490 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3491 // callee-saved registers are restored. These happen to be the same
3492 // registers used to pass 'inreg' arguments so watch out for those.
3493 if (!Subtarget->is64Bit() &&
3494 ((!isa<GlobalAddressSDNode>(Callee) &&
3495 !isa<ExternalSymbolSDNode>(Callee)) ||
3496 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3497 unsigned NumInRegs = 0;
3498 // In PIC we need an extra register to formulate the address computation
3499 // for the callee.
3500 unsigned MaxInRegs =
3501 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3503 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3504 CCValAssign &VA = ArgLocs[i];
3505 if (!VA.isRegLoc())
3506 continue;
3507 unsigned Reg = VA.getLocReg();
3508 switch (Reg) {
3509 default: break;
3510 case X86::EAX: case X86::EDX: case X86::ECX:
3511 if (++NumInRegs == MaxInRegs)
3512 return false;
3513 break;
3514 }
3515 }
3516 }
3517 }
3519 return true;
3520 }
3522 FastISel *
3523 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3524 const TargetLibraryInfo *libInfo) const {
3525 return X86::createFastISel(funcInfo, libInfo);
3526 }
3528 //===----------------------------------------------------------------------===//
3529 // Other Lowering Hooks
3530 //===----------------------------------------------------------------------===//
3532 static bool MayFoldLoad(SDValue Op) {
3533 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3534 }
3536 static bool MayFoldIntoStore(SDValue Op) {
3537 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3538 }
3540 static bool isTargetShuffle(unsigned Opcode) {
3541 switch(Opcode) {
3542 default: return false;
3543 case X86ISD::BLENDI:
3544 case X86ISD::PSHUFB:
3545 case X86ISD::PSHUFD:
3546 case X86ISD::PSHUFHW:
3547 case X86ISD::PSHUFLW:
3548 case X86ISD::SHUFP:
3549 case X86ISD::PALIGNR:
3550 case X86ISD::MOVLHPS:
3551 case X86ISD::MOVLHPD:
3552 case X86ISD::MOVHLPS:
3553 case X86ISD::MOVLPS:
3554 case X86ISD::MOVLPD:
3555 case X86ISD::MOVSHDUP:
3556 case X86ISD::MOVSLDUP:
3557 case X86ISD::MOVDDUP:
3558 case X86ISD::MOVSS:
3559 case X86ISD::MOVSD:
3560 case X86ISD::UNPCKL:
3561 case X86ISD::UNPCKH:
3562 case X86ISD::VPERMILPI:
3563 case X86ISD::VPERM2X128:
3564 case X86ISD::VPERMI:
3565 return true;
3566 }
3567 }
3569 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3570 SDValue V1, SelectionDAG &DAG) {
3571 switch(Opc) {
3572 default: llvm_unreachable("Unknown x86 shuffle node");
3573 case X86ISD::MOVSHDUP:
3574 case X86ISD::MOVSLDUP:
3575 case X86ISD::MOVDDUP:
3576 return DAG.getNode(Opc, dl, VT, V1);
3577 }
3578 }
3580 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3581 SDValue V1, unsigned TargetMask,
3582 SelectionDAG &DAG) {
3583 switch(Opc) {
3584 default: llvm_unreachable("Unknown x86 shuffle node");
3585 case X86ISD::PSHUFD:
3586 case X86ISD::PSHUFHW:
3587 case X86ISD::PSHUFLW:
3588 case X86ISD::VPERMILPI:
3589 case X86ISD::VPERMI:
3590 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3591 }
3592 }
3594 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3595 SDValue V1, SDValue V2, unsigned TargetMask,
3596 SelectionDAG &DAG) {
3597 switch(Opc) {
3598 default: llvm_unreachable("Unknown x86 shuffle node");
3599 case X86ISD::PALIGNR:
3600 case X86ISD::VALIGN:
3601 case X86ISD::SHUFP:
3602 case X86ISD::VPERM2X128:
3603 return DAG.getNode(Opc, dl, VT, V1, V2,
3604 DAG.getConstant(TargetMask, MVT::i8));
3605 }
3606 }
3608 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3609 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3610 switch(Opc) {
3611 default: llvm_unreachable("Unknown x86 shuffle node");
3612 case X86ISD::MOVLHPS:
3613 case X86ISD::MOVLHPD:
3614 case X86ISD::MOVHLPS:
3615 case X86ISD::MOVLPS:
3616 case X86ISD::MOVLPD:
3617 case X86ISD::MOVSS:
3618 case X86ISD::MOVSD:
3619 case X86ISD::UNPCKL:
3620 case X86ISD::UNPCKH:
3621 return DAG.getNode(Opc, dl, VT, V1, V2);
3622 }
3623 }
3625 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3626 MachineFunction &MF = DAG.getMachineFunction();
3627 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3628 DAG.getSubtarget().getRegisterInfo());
3629 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3630 int ReturnAddrIndex = FuncInfo->getRAIndex();
3632 if (ReturnAddrIndex == 0) {
3633 // Set up a frame object for the return address.
3634 unsigned SlotSize = RegInfo->getSlotSize();
3635 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3636 -(int64_t)SlotSize,
3637 false);
3638 FuncInfo->setRAIndex(ReturnAddrIndex);
3639 }
3641 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3642 }
3644 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3645 bool hasSymbolicDisplacement) {
3646 // Offset should fit into 32 bit immediate field.
3647 if (!isInt<32>(Offset))
3648 return false;
3650 // If we don't have a symbolic displacement - we don't have any extra
3651 // restrictions.
3652 if (!hasSymbolicDisplacement)
3653 return true;
3655 // FIXME: Some tweaks might be needed for medium code model.
3656 if (M != CodeModel::Small && M != CodeModel::Kernel)
3657 return false;
3659 // For small code model we assume that latest object is 16MB before end of 31
3660 // bits boundary. We may also accept pretty large negative constants knowing
3661 // that all objects are in the positive half of address space.
3662 if (M == CodeModel::Small && Offset < 16*1024*1024)
3663 return true;
3665 // For kernel code model we know that all object resist in the negative half
3666 // of 32bits address space. We may not accept negative offsets, since they may
3667 // be just off and we may accept pretty large positive ones.
3668 if (M == CodeModel::Kernel && Offset > 0)
3669 return true;
3671 return false;
3672 }
3674 /// isCalleePop - Determines whether the callee is required to pop its
3675 /// own arguments. Callee pop is necessary to support tail calls.
3676 bool X86::isCalleePop(CallingConv::ID CallingConv,
3677 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3678 switch (CallingConv) {
3679 default:
3680 return false;
3681 case CallingConv::X86_StdCall:
3682 case CallingConv::X86_FastCall:
3683 case CallingConv::X86_ThisCall:
3684 return !is64Bit;
3685 case CallingConv::Fast:
3686 case CallingConv::GHC:
3687 case CallingConv::HiPE:
3688 if (IsVarArg)
3689 return false;
3690 return TailCallOpt;
3691 }
3692 }
3694 /// \brief Return true if the condition is an unsigned comparison operation.
3695 static bool isX86CCUnsigned(unsigned X86CC) {
3696 switch (X86CC) {
3697 default: llvm_unreachable("Invalid integer condition!");
3698 case X86::COND_E: return true;
3699 case X86::COND_G: return false;
3700 case X86::COND_GE: return false;
3701 case X86::COND_L: return false;
3702 case X86::COND_LE: return false;
3703 case X86::COND_NE: return true;
3704 case X86::COND_B: return true;
3705 case X86::COND_A: return true;
3706 case X86::COND_BE: return true;
3707 case X86::COND_AE: return true;
3708 }
3709 llvm_unreachable("covered switch fell through?!");
3710 }
3712 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3713 /// specific condition code, returning the condition code and the LHS/RHS of the
3714 /// comparison to make.
3715 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3716 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3717 if (!isFP) {
3718 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3719 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3720 // X > -1 -> X == 0, jump !sign.
3721 RHS = DAG.getConstant(0, RHS.getValueType());
3722 return X86::COND_NS;
3723 }
3724 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3725 // X < 0 -> X == 0, jump on sign.
3726 return X86::COND_S;
3727 }
3728 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3729 // X < 1 -> X <= 0
3730 RHS = DAG.getConstant(0, RHS.getValueType());
3731 return X86::COND_LE;
3732 }
3733 }
3735 switch (SetCCOpcode) {
3736 default: llvm_unreachable("Invalid integer condition!");
3737 case ISD::SETEQ: return X86::COND_E;
3738 case ISD::SETGT: return X86::COND_G;
3739 case ISD::SETGE: return X86::COND_GE;
3740 case ISD::SETLT: return X86::COND_L;
3741 case ISD::SETLE: return X86::COND_LE;
3742 case ISD::SETNE: return X86::COND_NE;
3743 case ISD::SETULT: return X86::COND_B;
3744 case ISD::SETUGT: return X86::COND_A;
3745 case ISD::SETULE: return X86::COND_BE;
3746 case ISD::SETUGE: return X86::COND_AE;
3747 }
3748 }
3750 // First determine if it is required or is profitable to flip the operands.
3752 // If LHS is a foldable load, but RHS is not, flip the condition.
3753 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3754 !ISD::isNON_EXTLoad(RHS.getNode())) {
3755 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3756 std::swap(LHS, RHS);
3757 }
3759 switch (SetCCOpcode) {
3760 default: break;
3761 case ISD::SETOLT:
3762 case ISD::SETOLE:
3763 case ISD::SETUGT:
3764 case ISD::SETUGE:
3765 std::swap(LHS, RHS);
3766 break;
3767 }
3769 // On a floating point condition, the flags are set as follows:
3770 // ZF PF CF op
3771 // 0 | 0 | 0 | X > Y
3772 // 0 | 0 | 1 | X < Y
3773 // 1 | 0 | 0 | X == Y
3774 // 1 | 1 | 1 | unordered
3775 switch (SetCCOpcode) {
3776 default: llvm_unreachable("Condcode should be pre-legalized away");
3777 case ISD::SETUEQ:
3778 case ISD::SETEQ: return X86::COND_E;
3779 case ISD::SETOLT: // flipped
3780 case ISD::SETOGT:
3781 case ISD::SETGT: return X86::COND_A;
3782 case ISD::SETOLE: // flipped
3783 case ISD::SETOGE:
3784 case ISD::SETGE: return X86::COND_AE;
3785 case ISD::SETUGT: // flipped
3786 case ISD::SETULT:
3787 case ISD::SETLT: return X86::COND_B;
3788 case ISD::SETUGE: // flipped
3789 case ISD::SETULE:
3790 case ISD::SETLE: return X86::COND_BE;
3791 case ISD::SETONE:
3792 case ISD::SETNE: return X86::COND_NE;
3793 case ISD::SETUO: return X86::COND_P;
3794 case ISD::SETO: return X86::COND_NP;
3795 case ISD::SETOEQ:
3796 case ISD::SETUNE: return X86::COND_INVALID;
3797 }
3798 }
3800 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3801 /// code. Current x86 isa includes the following FP cmov instructions:
3802 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3803 static bool hasFPCMov(unsigned X86CC) {
3804 switch (X86CC) {
3805 default:
3806 return false;
3807 case X86::COND_B:
3808 case X86::COND_BE:
3809 case X86::COND_E:
3810 case X86::COND_P:
3811 case X86::COND_A:
3812 case X86::COND_AE:
3813 case X86::COND_NE:
3814 case X86::COND_NP:
3815 return true;
3816 }
3817 }
3819 /// isFPImmLegal - Returns true if the target can instruction select the
3820 /// specified FP immediate natively. If false, the legalizer will
3821 /// materialize the FP immediate as a load from a constant pool.
3822 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3823 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3824 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3825 return true;
3826 }
3827 return false;
3828 }
3830 /// \brief Returns true if it is beneficial to convert a load of a constant
3831 /// to just the constant itself.
3832 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3833 Type *Ty) const {
3834 assert(Ty->isIntegerTy());
3836 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3837 if (BitSize == 0 || BitSize > 64)
3838 return false;
3839 return true;
3840 }
3842 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3843 /// the specified range (L, H].
3844 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3845 return (Val < 0) || (Val >= Low && Val < Hi);
3846 }
3848 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3849 /// specified value.
3850 static bool isUndefOrEqual(int Val, int CmpVal) {
3851 return (Val < 0 || Val == CmpVal);
3852 }
3854 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3855 /// from position Pos and ending in Pos+Size, falls within the specified
3856 /// sequential range (L, L+Pos]. or is undef.
3857 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3858 unsigned Pos, unsigned Size, int Low) {
3859 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3860 if (!isUndefOrEqual(Mask[i], Low))
3861 return false;
3862 return true;
3863 }
3865 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3866 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3867 /// the second operand.
3868 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3869 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3870 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3871 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3872 return (Mask[0] < 2 && Mask[1] < 2);
3873 return false;
3874 }
3876 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3877 /// is suitable for input to PSHUFHW.
3878 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3879 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3880 return false;
3882 // Lower quadword copied in order or undef.
3883 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3884 return false;
3886 // Upper quadword shuffled.
3887 for (unsigned i = 4; i != 8; ++i)
3888 if (!isUndefOrInRange(Mask[i], 4, 8))
3889 return false;
3891 if (VT == MVT::v16i16) {
3892 // Lower quadword copied in order or undef.
3893 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3894 return false;
3896 // Upper quadword shuffled.
3897 for (unsigned i = 12; i != 16; ++i)
3898 if (!isUndefOrInRange(Mask[i], 12, 16))
3899 return false;
3900 }
3902 return true;
3903 }
3905 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3906 /// is suitable for input to PSHUFLW.
3907 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3908 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3909 return false;
3911 // Upper quadword copied in order.
3912 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3913 return false;
3915 // Lower quadword shuffled.
3916 for (unsigned i = 0; i != 4; ++i)
3917 if (!isUndefOrInRange(Mask[i], 0, 4))
3918 return false;
3920 if (VT == MVT::v16i16) {
3921 // Upper quadword copied in order.
3922 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3923 return false;
3925 // Lower quadword shuffled.
3926 for (unsigned i = 8; i != 12; ++i)
3927 if (!isUndefOrInRange(Mask[i], 8, 12))
3928 return false;
3929 }
3931 return true;
3932 }
3934 /// \brief Return true if the mask specifies a shuffle of elements that is
3935 /// suitable for input to intralane (palignr) or interlane (valign) vector
3936 /// right-shift.
3937 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3938 unsigned NumElts = VT.getVectorNumElements();
3939 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3940 unsigned NumLaneElts = NumElts/NumLanes;
3942 // Do not handle 64-bit element shuffles with palignr.
3943 if (NumLaneElts == 2)
3944 return false;
3946 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3947 unsigned i;
3948 for (i = 0; i != NumLaneElts; ++i) {
3949 if (Mask[i+l] >= 0)
3950 break;
3951 }
3953 // Lane is all undef, go to next lane
3954 if (i == NumLaneElts)
3955 continue;
3957 int Start = Mask[i+l];
3959 // Make sure its in this lane in one of the sources
3960 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3961 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3962 return false;
3964 // If not lane 0, then we must match lane 0
3965 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3966 return false;
3968 // Correct second source to be contiguous with first source
3969 if (Start >= (int)NumElts)
3970 Start -= NumElts - NumLaneElts;
3972 // Make sure we're shifting in the right direction.
3973 if (Start <= (int)(i+l))
3974 return false;
3976 Start -= i;
3978 // Check the rest of the elements to see if they are consecutive.
3979 for (++i; i != NumLaneElts; ++i) {
3980 int Idx = Mask[i+l];
3982 // Make sure its in this lane
3983 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3984 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3985 return false;
3987 // If not lane 0, then we must match lane 0
3988 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3989 return false;
3991 if (Idx >= (int)NumElts)
3992 Idx -= NumElts - NumLaneElts;
3994 if (!isUndefOrEqual(Idx, Start+i))
3995 return false;
3997 }
3998 }
4000 return true;
4001 }
4003 /// \brief Return true if the node specifies a shuffle of elements that is
4004 /// suitable for input to PALIGNR.
4005 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4006 const X86Subtarget *Subtarget) {
4007 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4008 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4009 VT.is512BitVector())
4010 // FIXME: Add AVX512BW.
4011 return false;
4013 return isAlignrMask(Mask, VT, false);
4014 }
4016 /// \brief Return true if the node specifies a shuffle of elements that is
4017 /// suitable for input to VALIGN.
4018 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4019 const X86Subtarget *Subtarget) {
4020 // FIXME: Add AVX512VL.
4021 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4022 return false;
4023 return isAlignrMask(Mask, VT, true);
4024 }
4026 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4027 /// the two vector operands have swapped position.
4028 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4029 unsigned NumElems) {
4030 for (unsigned i = 0; i != NumElems; ++i) {
4031 int idx = Mask[i];
4032 if (idx < 0)
4033 continue;
4034 else if (idx < (int)NumElems)
4035 Mask[i] = idx + NumElems;
4036 else
4037 Mask[i] = idx - NumElems;
4038 }
4039 }
4041 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4042 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4043 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4044 /// reverse of what x86 shuffles want.
4045 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4047 unsigned NumElems = VT.getVectorNumElements();
4048 unsigned NumLanes = VT.getSizeInBits()/128;
4049 unsigned NumLaneElems = NumElems/NumLanes;
4051 if (NumLaneElems != 2 && NumLaneElems != 4)
4052 return false;
4054 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4055 bool symetricMaskRequired =
4056 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4058 // VSHUFPSY divides the resulting vector into 4 chunks.
4059 // The sources are also splitted into 4 chunks, and each destination
4060 // chunk must come from a different source chunk.
4061 //
4062 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4063 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4064 //
4065 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4066 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4067 //
4068 // VSHUFPDY divides the resulting vector into 4 chunks.
4069 // The sources are also splitted into 4 chunks, and each destination
4070 // chunk must come from a different source chunk.
4071 //
4072 // SRC1 => X3 X2 X1 X0
4073 // SRC2 => Y3 Y2 Y1 Y0
4074 //
4075 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4076 //
4077 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4078 unsigned HalfLaneElems = NumLaneElems/2;
4079 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4080 for (unsigned i = 0; i != NumLaneElems; ++i) {
4081 int Idx = Mask[i+l];
4082 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4083 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4084 return false;
4085 // For VSHUFPSY, the mask of the second half must be the same as the
4086 // first but with the appropriate offsets. This works in the same way as
4087 // VPERMILPS works with masks.
4088 if (!symetricMaskRequired || Idx < 0)
4089 continue;
4090 if (MaskVal[i] < 0) {
4091 MaskVal[i] = Idx - l;
4092 continue;
4093 }
4094 if ((signed)(Idx - l) != MaskVal[i])
4095 return false;
4096 }
4097 }
4099 return true;
4100 }
4102 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4103 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4104 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4105 if (!VT.is128BitVector())
4106 return false;
4108 unsigned NumElems = VT.getVectorNumElements();
4110 if (NumElems != 4)
4111 return false;
4113 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4114 return isUndefOrEqual(Mask[0], 6) &&
4115 isUndefOrEqual(Mask[1], 7) &&
4116 isUndefOrEqual(Mask[2], 2) &&
4117 isUndefOrEqual(Mask[3], 3);
4118 }
4120 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4121 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4122 /// <2, 3, 2, 3>
4123 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4124 if (!VT.is128BitVector())
4125 return false;
4127 unsigned NumElems = VT.getVectorNumElements();
4129 if (NumElems != 4)
4130 return false;
4132 return isUndefOrEqual(Mask[0], 2) &&
4133 isUndefOrEqual(Mask[1], 3) &&
4134 isUndefOrEqual(Mask[2], 2) &&
4135 isUndefOrEqual(Mask[3], 3);
4136 }
4138 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4139 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4140 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4141 if (!VT.is128BitVector())
4142 return false;
4144 unsigned NumElems = VT.getVectorNumElements();
4146 if (NumElems != 2 && NumElems != 4)
4147 return false;
4149 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4150 if (!isUndefOrEqual(Mask[i], i + NumElems))
4151 return false;
4153 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4154 if (!isUndefOrEqual(Mask[i], i))
4155 return false;
4157 return true;
4158 }
4160 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4161 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4162 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4163 if (!VT.is128BitVector())
4164 return false;
4166 unsigned NumElems = VT.getVectorNumElements();
4168 if (NumElems != 2 && NumElems != 4)
4169 return false;
4171 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4172 if (!isUndefOrEqual(Mask[i], i))
4173 return false;
4175 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4176 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4177 return false;
4179 return true;
4180 }
4182 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4183 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4184 /// i. e: If all but one element come from the same vector.
4185 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4186 // TODO: Deal with AVX's VINSERTPS
4187 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4188 return false;
4190 unsigned CorrectPosV1 = 0;
4191 unsigned CorrectPosV2 = 0;
4192 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4193 if (Mask[i] == -1) {
4194 ++CorrectPosV1;
4195 ++CorrectPosV2;
4196 continue;
4197 }
4199 if (Mask[i] == i)
4200 ++CorrectPosV1;
4201 else if (Mask[i] == i + 4)
4202 ++CorrectPosV2;
4203 }
4205 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4206 // We have 3 elements (undefs count as elements from any vector) from one
4207 // vector, and one from another.
4208 return true;
4210 return false;
4211 }
4213 //
4214 // Some special combinations that can be optimized.
4215 //
4216 static
4217 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4218 SelectionDAG &DAG) {
4219 MVT VT = SVOp->getSimpleValueType(0);
4220 SDLoc dl(SVOp);
4222 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4223 return SDValue();
4225 ArrayRef<int> Mask = SVOp->getMask();
4227 // These are the special masks that may be optimized.
4228 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4229 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4230 bool MatchEvenMask = true;
4231 bool MatchOddMask = true;
4232 for (int i=0; i<8; ++i) {
4233 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4234 MatchEvenMask = false;
4235 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4236 MatchOddMask = false;
4237 }
4239 if (!MatchEvenMask && !MatchOddMask)
4240 return SDValue();
4242 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4244 SDValue Op0 = SVOp->getOperand(0);
4245 SDValue Op1 = SVOp->getOperand(1);
4247 if (MatchEvenMask) {
4248 // Shift the second operand right to 32 bits.
4249 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4250 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4251 } else {
4252 // Shift the first operand left to 32 bits.
4253 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4254 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4255 }
4256 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4257 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4258 }
4260 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4261 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4262 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4263 bool HasInt256, bool V2IsSplat = false) {
4265 assert(VT.getSizeInBits() >= 128 &&
4266 "Unsupported vector type for unpckl");
4268 unsigned NumElts = VT.getVectorNumElements();
4269 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4270 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4271 return false;
4273 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4274 "Unsupported vector type for unpckh");
4276 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4277 unsigned NumLanes = VT.getSizeInBits()/128;
4278 unsigned NumLaneElts = NumElts/NumLanes;
4280 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4281 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4282 int BitI = Mask[l+i];
4283 int BitI1 = Mask[l+i+1];
4284 if (!isUndefOrEqual(BitI, j))
4285 return false;
4286 if (V2IsSplat) {
4287 if (!isUndefOrEqual(BitI1, NumElts))
4288 return false;
4289 } else {
4290 if (!isUndefOrEqual(BitI1, j + NumElts))
4291 return false;
4292 }
4293 }
4294 }
4296 return true;
4297 }
4299 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4300 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4301 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4302 bool HasInt256, bool V2IsSplat = false) {
4303 assert(VT.getSizeInBits() >= 128 &&
4304 "Unsupported vector type for unpckh");
4306 unsigned NumElts = VT.getVectorNumElements();
4307 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4308 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4309 return false;
4311 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4312 "Unsupported vector type for unpckh");
4314 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4315 unsigned NumLanes = VT.getSizeInBits()/128;
4316 unsigned NumLaneElts = NumElts/NumLanes;
4318 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4319 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4320 int BitI = Mask[l+i];
4321 int BitI1 = Mask[l+i+1];
4322 if (!isUndefOrEqual(BitI, j))
4323 return false;
4324 if (V2IsSplat) {
4325 if (isUndefOrEqual(BitI1, NumElts))
4326 return false;
4327 } else {
4328 if (!isUndefOrEqual(BitI1, j+NumElts))
4329 return false;
4330 }
4331 }
4332 }
4333 return true;
4334 }
4336 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4337 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4338 /// <0, 0, 1, 1>
4339 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4340 unsigned NumElts = VT.getVectorNumElements();
4341 bool Is256BitVec = VT.is256BitVector();
4343 if (VT.is512BitVector())
4344 return false;
4345 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4346 "Unsupported vector type for unpckh");
4348 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4349 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4350 return false;
4352 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4353 // FIXME: Need a better way to get rid of this, there's no latency difference
4354 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4355 // the former later. We should also remove the "_undef" special mask.
4356 if (NumElts == 4 && Is256BitVec)
4357 return false;
4359 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4360 // independently on 128-bit lanes.
4361 unsigned NumLanes = VT.getSizeInBits()/128;
4362 unsigned NumLaneElts = NumElts/NumLanes;
4364 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4365 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4366 int BitI = Mask[l+i];
4367 int BitI1 = Mask[l+i+1];
4369 if (!isUndefOrEqual(BitI, j))
4370 return false;
4371 if (!isUndefOrEqual(BitI1, j))
4372 return false;
4373 }
4374 }
4376 return true;
4377 }
4379 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4380 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4381 /// <2, 2, 3, 3>
4382 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4383 unsigned NumElts = VT.getVectorNumElements();
4385 if (VT.is512BitVector())
4386 return false;
4388 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4389 "Unsupported vector type for unpckh");
4391 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4392 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4393 return false;
4395 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4396 // independently on 128-bit lanes.
4397 unsigned NumLanes = VT.getSizeInBits()/128;
4398 unsigned NumLaneElts = NumElts/NumLanes;
4400 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4401 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4402 int BitI = Mask[l+i];
4403 int BitI1 = Mask[l+i+1];
4404 if (!isUndefOrEqual(BitI, j))
4405 return false;
4406 if (!isUndefOrEqual(BitI1, j))
4407 return false;
4408 }
4409 }
4410 return true;
4411 }
4413 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4414 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4415 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4416 if (!VT.is512BitVector())
4417 return false;
4419 unsigned NumElts = VT.getVectorNumElements();
4420 unsigned HalfSize = NumElts/2;
4421 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4422 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4423 *Imm = 1;
4424 return true;
4425 }
4426 }
4427 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4428 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4429 *Imm = 0;
4430 return true;
4431 }
4432 }
4433 return false;
4434 }
4436 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4437 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4438 /// MOVSD, and MOVD, i.e. setting the lowest element.
4439 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4440 if (VT.getVectorElementType().getSizeInBits() < 32)
4441 return false;
4442 if (!VT.is128BitVector())
4443 return false;
4445 unsigned NumElts = VT.getVectorNumElements();
4447 if (!isUndefOrEqual(Mask[0], NumElts))
4448 return false;
4450 for (unsigned i = 1; i != NumElts; ++i)
4451 if (!isUndefOrEqual(Mask[i], i))
4452 return false;
4454 return true;
4455 }
4457 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4458 /// as permutations between 128-bit chunks or halves. As an example: this
4459 /// shuffle bellow:
4460 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4461 /// The first half comes from the second half of V1 and the second half from the
4462 /// the second half of V2.
4463 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4464 if (!HasFp256 || !VT.is256BitVector())
4465 return false;
4467 // The shuffle result is divided into half A and half B. In total the two
4468 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4469 // B must come from C, D, E or F.
4470 unsigned HalfSize = VT.getVectorNumElements()/2;
4471 bool MatchA = false, MatchB = false;
4473 // Check if A comes from one of C, D, E, F.
4474 for (unsigned Half = 0; Half != 4; ++Half) {
4475 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4476 MatchA = true;
4477 break;
4478 }
4479 }
4481 // Check if B comes from one of C, D, E, F.
4482 for (unsigned Half = 0; Half != 4; ++Half) {
4483 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4484 MatchB = true;
4485 break;
4486 }
4487 }
4489 return MatchA && MatchB;
4490 }
4492 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4493 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4494 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4495 MVT VT = SVOp->getSimpleValueType(0);
4497 unsigned HalfSize = VT.getVectorNumElements()/2;
4499 unsigned FstHalf = 0, SndHalf = 0;
4500 for (unsigned i = 0; i < HalfSize; ++i) {
4501 if (SVOp->getMaskElt(i) > 0) {
4502 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4503 break;
4504 }
4505 }
4506 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4507 if (SVOp->getMaskElt(i) > 0) {
4508 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4509 break;
4510 }
4511 }
4513 return (FstHalf | (SndHalf << 4));
4514 }
4516 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4517 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4518 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4519 if (EltSize < 32)
4520 return false;
4522 unsigned NumElts = VT.getVectorNumElements();
4523 Imm8 = 0;
4524 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4525 for (unsigned i = 0; i != NumElts; ++i) {
4526 if (Mask[i] < 0)
4527 continue;
4528 Imm8 |= Mask[i] << (i*2);
4529 }
4530 return true;
4531 }
4533 unsigned LaneSize = 4;
4534 SmallVector<int, 4> MaskVal(LaneSize, -1);
4536 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4537 for (unsigned i = 0; i != LaneSize; ++i) {
4538 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4539 return false;
4540 if (Mask[i+l] < 0)
4541 continue;
4542 if (MaskVal[i] < 0) {
4543 MaskVal[i] = Mask[i+l] - l;
4544 Imm8 |= MaskVal[i] << (i*2);
4545 continue;
4546 }
4547 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4548 return false;
4549 }
4550 }
4551 return true;
4552 }
4554 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4555 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4556 /// Note that VPERMIL mask matching is different depending whether theunderlying
4557 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4558 /// to the same elements of the low, but to the higher half of the source.
4559 /// In VPERMILPD the two lanes could be shuffled independently of each other
4560 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4561 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4562 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4563 if (VT.getSizeInBits() < 256 || EltSize < 32)
4564 return false;
4565 bool symetricMaskRequired = (EltSize == 32);
4566 unsigned NumElts = VT.getVectorNumElements();
4568 unsigned NumLanes = VT.getSizeInBits()/128;
4569 unsigned LaneSize = NumElts/NumLanes;
4570 // 2 or 4 elements in one lane
4572 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4573 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4574 for (unsigned i = 0; i != LaneSize; ++i) {
4575 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4576 return false;
4577 if (symetricMaskRequired) {
4578 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4579 ExpectedMaskVal[i] = Mask[i+l] - l;
4580 continue;
4581 }
4582 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4583 return false;
4584 }
4585 }
4586 }
4587 return true;
4588 }
4590 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4591 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4592 /// element of vector 2 and the other elements to come from vector 1 in order.
4593 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4594 bool V2IsSplat = false, bool V2IsUndef = false) {
4595 if (!VT.is128BitVector())
4596 return false;
4598 unsigned NumOps = VT.getVectorNumElements();
4599 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4600 return false;
4602 if (!isUndefOrEqual(Mask[0], 0))
4603 return false;
4605 for (unsigned i = 1; i != NumOps; ++i)
4606 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4607 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4608 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4609 return false;
4611 return true;
4612 }
4614 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4615 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4616 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4617 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4618 const X86Subtarget *Subtarget) {
4619 if (!Subtarget->hasSSE3())
4620 return false;
4622 unsigned NumElems = VT.getVectorNumElements();
4624 if ((VT.is128BitVector() && NumElems != 4) ||
4625 (VT.is256BitVector() && NumElems != 8) ||
4626 (VT.is512BitVector() && NumElems != 16))
4627 return false;
4629 // "i+1" is the value the indexed mask element must have
4630 for (unsigned i = 0; i != NumElems; i += 2)
4631 if (!isUndefOrEqual(Mask[i], i+1) ||
4632 !isUndefOrEqual(Mask[i+1], i+1))
4633 return false;
4635 return true;
4636 }
4638 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4639 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4640 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4641 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4642 const X86Subtarget *Subtarget) {
4643 if (!Subtarget->hasSSE3())
4644 return false;
4646 unsigned NumElems = VT.getVectorNumElements();
4648 if ((VT.is128BitVector() && NumElems != 4) ||
4649 (VT.is256BitVector() && NumElems != 8) ||
4650 (VT.is512BitVector() && NumElems != 16))
4651 return false;
4653 // "i" is the value the indexed mask element must have
4654 for (unsigned i = 0; i != NumElems; i += 2)
4655 if (!isUndefOrEqual(Mask[i], i) ||
4656 !isUndefOrEqual(Mask[i+1], i))
4657 return false;
4659 return true;
4660 }
4662 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4663 /// specifies a shuffle of elements that is suitable for input to 256-bit
4664 /// version of MOVDDUP.
4665 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4666 if (!HasFp256 || !VT.is256BitVector())
4667 return false;
4669 unsigned NumElts = VT.getVectorNumElements();
4670 if (NumElts != 4)
4671 return false;
4673 for (unsigned i = 0; i != NumElts/2; ++i)
4674 if (!isUndefOrEqual(Mask[i], 0))
4675 return false;
4676 for (unsigned i = NumElts/2; i != NumElts; ++i)
4677 if (!isUndefOrEqual(Mask[i], NumElts/2))
4678 return false;
4679 return true;
4680 }
4682 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4683 /// specifies a shuffle of elements that is suitable for input to 128-bit
4684 /// version of MOVDDUP.
4685 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4686 if (!VT.is128BitVector())
4687 return false;
4689 unsigned e = VT.getVectorNumElements() / 2;
4690 for (unsigned i = 0; i != e; ++i)
4691 if (!isUndefOrEqual(Mask[i], i))
4692 return false;
4693 for (unsigned i = 0; i != e; ++i)
4694 if (!isUndefOrEqual(Mask[e+i], i))
4695 return false;
4696 return true;
4697 }
4699 /// isVEXTRACTIndex - Return true if the specified
4700 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4701 /// suitable for instruction that extract 128 or 256 bit vectors
4702 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4703 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4704 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4705 return false;
4707 // The index should be aligned on a vecWidth-bit boundary.
4708 uint64_t Index =
4709 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4711 MVT VT = N->getSimpleValueType(0);
4712 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4713 bool Result = (Index * ElSize) % vecWidth == 0;
4715 return Result;
4716 }
4718 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4719 /// operand specifies a subvector insert that is suitable for input to
4720 /// insertion of 128 or 256-bit subvectors
4721 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4722 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4723 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4724 return false;
4725 // The index should be aligned on a vecWidth-bit boundary.
4726 uint64_t Index =
4727 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4729 MVT VT = N->getSimpleValueType(0);
4730 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4731 bool Result = (Index * ElSize) % vecWidth == 0;
4733 return Result;
4734 }
4736 bool X86::isVINSERT128Index(SDNode *N) {
4737 return isVINSERTIndex(N, 128);
4738 }
4740 bool X86::isVINSERT256Index(SDNode *N) {
4741 return isVINSERTIndex(N, 256);
4742 }
4744 bool X86::isVEXTRACT128Index(SDNode *N) {
4745 return isVEXTRACTIndex(N, 128);
4746 }
4748 bool X86::isVEXTRACT256Index(SDNode *N) {
4749 return isVEXTRACTIndex(N, 256);
4750 }
4752 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4753 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4754 /// Handles 128-bit and 256-bit.
4755 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4756 MVT VT = N->getSimpleValueType(0);
4758 assert((VT.getSizeInBits() >= 128) &&
4759 "Unsupported vector type for PSHUF/SHUFP");
4761 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4762 // independently on 128-bit lanes.
4763 unsigned NumElts = VT.getVectorNumElements();
4764 unsigned NumLanes = VT.getSizeInBits()/128;
4765 unsigned NumLaneElts = NumElts/NumLanes;
4767 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4768 "Only supports 2, 4 or 8 elements per lane");
4770 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4771 unsigned Mask = 0;
4772 for (unsigned i = 0; i != NumElts; ++i) {
4773 int Elt = N->getMaskElt(i);
4774 if (Elt < 0) continue;
4775 Elt &= NumLaneElts - 1;
4776 unsigned ShAmt = (i << Shift) % 8;
4777 Mask |= Elt << ShAmt;
4778 }
4780 return Mask;
4781 }
4783 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4784 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4785 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4786 MVT VT = N->getSimpleValueType(0);
4788 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4789 "Unsupported vector type for PSHUFHW");
4791 unsigned NumElts = VT.getVectorNumElements();
4793 unsigned Mask = 0;
4794 for (unsigned l = 0; l != NumElts; l += 8) {
4795 // 8 nodes per lane, but we only care about the last 4.
4796 for (unsigned i = 0; i < 4; ++i) {
4797 int Elt = N->getMaskElt(l+i+4);
4798 if (Elt < 0) continue;
4799 Elt &= 0x3; // only 2-bits.
4800 Mask |= Elt << (i * 2);
4801 }
4802 }
4804 return Mask;
4805 }
4807 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4808 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4809 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4810 MVT VT = N->getSimpleValueType(0);
4812 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4813 "Unsupported vector type for PSHUFHW");
4815 unsigned NumElts = VT.getVectorNumElements();
4817 unsigned Mask = 0;
4818 for (unsigned l = 0; l != NumElts; l += 8) {
4819 // 8 nodes per lane, but we only care about the first 4.
4820 for (unsigned i = 0; i < 4; ++i) {
4821 int Elt = N->getMaskElt(l+i);
4822 if (Elt < 0) continue;
4823 Elt &= 0x3; // only 2-bits
4824 Mask |= Elt << (i * 2);
4825 }
4826 }
4828 return Mask;
4829 }
4831 /// \brief Return the appropriate immediate to shuffle the specified
4832 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4833 /// VALIGN (if Interlane is true) instructions.
4834 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4835 bool InterLane) {
4836 MVT VT = SVOp->getSimpleValueType(0);
4837 unsigned EltSize = InterLane ? 1 :
4838 VT.getVectorElementType().getSizeInBits() >> 3;
4840 unsigned NumElts = VT.getVectorNumElements();
4841 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4842 unsigned NumLaneElts = NumElts/NumLanes;
4844 int Val = 0;
4845 unsigned i;
4846 for (i = 0; i != NumElts; ++i) {
4847 Val = SVOp->getMaskElt(i);
4848 if (Val >= 0)
4849 break;
4850 }
4851 if (Val >= (int)NumElts)
4852 Val -= NumElts - NumLaneElts;
4854 assert(Val - i > 0 && "PALIGNR imm should be positive");
4855 return (Val - i) * EltSize;
4856 }
4858 /// \brief Return the appropriate immediate to shuffle the specified
4859 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4860 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4861 return getShuffleAlignrImmediate(SVOp, false);
4862 }
4864 /// \brief Return the appropriate immediate to shuffle the specified
4865 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4866 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4867 return getShuffleAlignrImmediate(SVOp, true);
4868 }
4871 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4872 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4873 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4874 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4876 uint64_t Index =
4877 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4879 MVT VecVT = N->getOperand(0).getSimpleValueType();
4880 MVT ElVT = VecVT.getVectorElementType();
4882 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4883 return Index / NumElemsPerChunk;
4884 }
4886 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4887 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4888 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4889 llvm_unreachable("Illegal insert subvector for VINSERT");
4891 uint64_t Index =
4892 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4894 MVT VecVT = N->getSimpleValueType(0);
4895 MVT ElVT = VecVT.getVectorElementType();
4897 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4898 return Index / NumElemsPerChunk;
4899 }
4901 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4902 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4903 /// and VINSERTI128 instructions.
4904 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4905 return getExtractVEXTRACTImmediate(N, 128);
4906 }
4908 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4909 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4910 /// and VINSERTI64x4 instructions.
4911 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4912 return getExtractVEXTRACTImmediate(N, 256);
4913 }
4915 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4916 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4917 /// and VINSERTI128 instructions.
4918 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4919 return getInsertVINSERTImmediate(N, 128);
4920 }
4922 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4923 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4924 /// and VINSERTI64x4 instructions.
4925 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4926 return getInsertVINSERTImmediate(N, 256);
4927 }
4929 /// isZero - Returns true if Elt is a constant integer zero
4930 static bool isZero(SDValue V) {
4931 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4932 return C && C->isNullValue();
4933 }
4935 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4936 /// constant +0.0.
4937 bool X86::isZeroNode(SDValue Elt) {
4938 if (isZero(Elt))
4939 return true;
4940 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4941 return CFP->getValueAPF().isPosZero();
4942 return false;
4943 }
4945 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4946 /// match movhlps. The lower half elements should come from upper half of
4947 /// V1 (and in order), and the upper half elements should come from the upper
4948 /// half of V2 (and in order).
4949 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4950 if (!VT.is128BitVector())
4951 return false;
4952 if (VT.getVectorNumElements() != 4)
4953 return false;
4954 for (unsigned i = 0, e = 2; i != e; ++i)
4955 if (!isUndefOrEqual(Mask[i], i+2))
4956 return false;
4957 for (unsigned i = 2; i != 4; ++i)
4958 if (!isUndefOrEqual(Mask[i], i+4))
4959 return false;
4960 return true;
4961 }
4963 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4964 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4965 /// required.
4966 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4967 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4968 return false;
4969 N = N->getOperand(0).getNode();
4970 if (!ISD::isNON_EXTLoad(N))
4971 return false;
4972 if (LD)
4973 *LD = cast<LoadSDNode>(N);
4974 return true;
4975 }
4977 // Test whether the given value is a vector value which will be legalized
4978 // into a load.
4979 static bool WillBeConstantPoolLoad(SDNode *N) {
4980 if (N->getOpcode() != ISD::BUILD_VECTOR)
4981 return false;
4983 // Check for any non-constant elements.
4984 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4985 switch (N->getOperand(i).getNode()->getOpcode()) {
4986 case ISD::UNDEF:
4987 case ISD::ConstantFP:
4988 case ISD::Constant:
4989 break;
4990 default:
4991 return false;
4992 }
4994 // Vectors of all-zeros and all-ones are materialized with special
4995 // instructions rather than being loaded.
4996 return !ISD::isBuildVectorAllZeros(N) &&
4997 !ISD::isBuildVectorAllOnes(N);
4998 }
5000 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5001 /// match movlp{s|d}. The lower half elements should come from lower half of
5002 /// V1 (and in order), and the upper half elements should come from the upper
5003 /// half of V2 (and in order). And since V1 will become the source of the
5004 /// MOVLP, it must be either a vector load or a scalar load to vector.
5005 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5006 ArrayRef<int> Mask, MVT VT) {
5007 if (!VT.is128BitVector())
5008 return false;
5010 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5011 return false;
5012 // Is V2 is a vector load, don't do this transformation. We will try to use
5013 // load folding shufps op.
5014 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5015 return false;
5017 unsigned NumElems = VT.getVectorNumElements();
5019 if (NumElems != 2 && NumElems != 4)
5020 return false;
5021 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5022 if (!isUndefOrEqual(Mask[i], i))
5023 return false;
5024 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5025 if (!isUndefOrEqual(Mask[i], i+NumElems))
5026 return false;
5027 return true;
5028 }
5030 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5031 /// to an zero vector.
5032 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5033 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5034 SDValue V1 = N->getOperand(0);
5035 SDValue V2 = N->getOperand(1);
5036 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5037 for (unsigned i = 0; i != NumElems; ++i) {
5038 int Idx = N->getMaskElt(i);
5039 if (Idx >= (int)NumElems) {
5040 unsigned Opc = V2.getOpcode();
5041 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5042 continue;
5043 if (Opc != ISD::BUILD_VECTOR ||
5044 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5045 return false;
5046 } else if (Idx >= 0) {
5047 unsigned Opc = V1.getOpcode();
5048 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5049 continue;
5050 if (Opc != ISD::BUILD_VECTOR ||
5051 !X86::isZeroNode(V1.getOperand(Idx)))
5052 return false;
5053 }
5054 }
5055 return true;
5056 }
5058 /// getZeroVector - Returns a vector of specified type with all zero elements.
5059 ///
5060 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5061 SelectionDAG &DAG, SDLoc dl) {
5062 assert(VT.isVector() && "Expected a vector type");
5064 // Always build SSE zero vectors as <4 x i32> bitcasted
5065 // to their dest type. This ensures they get CSE'd.
5066 SDValue Vec;
5067 if (VT.is128BitVector()) { // SSE
5068 if (Subtarget->hasSSE2()) { // SSE2
5069 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5070 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5071 } else { // SSE1
5072 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5073 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5074 }
5075 } else if (VT.is256BitVector()) { // AVX
5076 if (Subtarget->hasInt256()) { // AVX2
5077 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5078 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5079 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5080 } else {
5081 // 256-bit logic and arithmetic instructions in AVX are all
5082 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5083 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5084 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5085 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5086 }
5087 } else if (VT.is512BitVector()) { // AVX-512
5088 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5089 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5090 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5091 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5092 } else if (VT.getScalarType() == MVT::i1) {
5093 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5094 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5095 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5096 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5097 } else
5098 llvm_unreachable("Unexpected vector type");
5100 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5101 }
5103 /// getOnesVector - Returns a vector of specified type with all bits set.
5104 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5105 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5106 /// Then bitcast to their original type, ensuring they get CSE'd.
5107 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5108 SDLoc dl) {
5109 assert(VT.isVector() && "Expected a vector type");
5111 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
5112 SDValue Vec;
5113 if (VT.is256BitVector()) {
5114 if (HasInt256) { // AVX2
5115 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5116 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5117 } else { // AVX
5118 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5119 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5120 }
5121 } else if (VT.is128BitVector()) {
5122 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5123 } else
5124 llvm_unreachable("Unexpected vector type");
5126 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5127 }
5129 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5130 /// that point to V2 points to its first element.
5131 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5132 for (unsigned i = 0; i != NumElems; ++i) {
5133 if (Mask[i] > (int)NumElems) {
5134 Mask[i] = NumElems;
5135 }
5136 }
5137 }
5139 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5140 /// operation of specified width.
5141 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5142 SDValue V2) {
5143 unsigned NumElems = VT.getVectorNumElements();
5144 SmallVector<int, 8> Mask;
5145 Mask.push_back(NumElems);
5146 for (unsigned i = 1; i != NumElems; ++i)
5147 Mask.push_back(i);
5148 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5149 }
5151 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5152 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5153 SDValue V2) {
5154 unsigned NumElems = VT.getVectorNumElements();
5155 SmallVector<int, 8> Mask;
5156 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5157 Mask.push_back(i);
5158 Mask.push_back(i + NumElems);
5159 }
5160 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5161 }
5163 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5164 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5165 SDValue V2) {
5166 unsigned NumElems = VT.getVectorNumElements();
5167 SmallVector<int, 8> Mask;
5168 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5169 Mask.push_back(i + Half);
5170 Mask.push_back(i + NumElems + Half);
5171 }
5172 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5173 }
5175 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5176 // a generic shuffle instruction because the target has no such instructions.
5177 // Generate shuffles which repeat i16 and i8 several times until they can be
5178 // represented by v4f32 and then be manipulated by target suported shuffles.
5179 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5180 MVT VT = V.getSimpleValueType();
5181 int NumElems = VT.getVectorNumElements();
5182 SDLoc dl(V);
5184 while (NumElems > 4) {
5185 if (EltNo < NumElems/2) {
5186 V = getUnpackl(DAG, dl, VT, V, V);
5187 } else {
5188 V = getUnpackh(DAG, dl, VT, V, V);
5189 EltNo -= NumElems/2;
5190 }
5191 NumElems >>= 1;
5192 }
5193 return V;
5194 }
5196 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5197 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5198 MVT VT = V.getSimpleValueType();
5199 SDLoc dl(V);
5201 if (VT.is128BitVector()) {
5202 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5203 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5204 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5205 &SplatMask[0]);
5206 } else if (VT.is256BitVector()) {
5207 // To use VPERMILPS to splat scalars, the second half of indicies must
5208 // refer to the higher part, which is a duplication of the lower one,
5209 // because VPERMILPS can only handle in-lane permutations.
5210 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5211 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5213 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5214 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5215 &SplatMask[0]);
5216 } else
5217 llvm_unreachable("Vector size not supported");
5219 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5220 }
5222 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5223 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5224 MVT SrcVT = SV->getSimpleValueType(0);
5225 SDValue V1 = SV->getOperand(0);
5226 SDLoc dl(SV);
5228 int EltNo = SV->getSplatIndex();
5229 int NumElems = SrcVT.getVectorNumElements();
5230 bool Is256BitVec = SrcVT.is256BitVector();
5232 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5233 "Unknown how to promote splat for type");
5235 // Extract the 128-bit part containing the splat element and update
5236 // the splat element index when it refers to the higher register.
5237 if (Is256BitVec) {
5238 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5239 if (EltNo >= NumElems/2)
5240 EltNo -= NumElems/2;
5241 }
5243 // All i16 and i8 vector types can't be used directly by a generic shuffle
5244 // instruction because the target has no such instruction. Generate shuffles
5245 // which repeat i16 and i8 several times until they fit in i32, and then can
5246 // be manipulated by target suported shuffles.
5247 MVT EltVT = SrcVT.getVectorElementType();
5248 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5249 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5251 // Recreate the 256-bit vector and place the same 128-bit vector
5252 // into the low and high part. This is necessary because we want
5253 // to use VPERM* to shuffle the vectors
5254 if (Is256BitVec) {
5255 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5256 }
5258 return getLegalSplat(DAG, V1, EltNo);
5259 }
5261 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5262 /// vector of zero or undef vector. This produces a shuffle where the low
5263 /// element of V2 is swizzled into the zero/undef vector, landing at element
5264 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5265 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5266 bool IsZero,
5267 const X86Subtarget *Subtarget,
5268 SelectionDAG &DAG) {
5269 MVT VT = V2.getSimpleValueType();
5270 SDValue V1 = IsZero
5271 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5272 unsigned NumElems = VT.getVectorNumElements();
5273 SmallVector<int, 16> MaskVec;
5274 for (unsigned i = 0; i != NumElems; ++i)
5275 // If this is the insertion idx, put the low elt of V2 here.
5276 MaskVec.push_back(i == Idx ? NumElems : i);
5277 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5278 }
5280 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5281 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5282 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5283 /// shuffles which use a single input multiple times, and in those cases it will
5284 /// adjust the mask to only have indices within that single input.
5285 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5286 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5287 unsigned NumElems = VT.getVectorNumElements();
5288 SDValue ImmN;
5290 IsUnary = false;
5291 bool IsFakeUnary = false;
5292 switch(N->getOpcode()) {
5293 case X86ISD::BLENDI:
5294 ImmN = N->getOperand(N->getNumOperands()-1);
5295 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5296 break;
5297 case X86ISD::SHUFP:
5298 ImmN = N->getOperand(N->getNumOperands()-1);
5299 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5300 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5301 break;
5302 case X86ISD::UNPCKH:
5303 DecodeUNPCKHMask(VT, Mask);
5304 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5305 break;
5306 case X86ISD::UNPCKL:
5307 DecodeUNPCKLMask(VT, Mask);
5308 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5309 break;
5310 case X86ISD::MOVHLPS:
5311 DecodeMOVHLPSMask(NumElems, Mask);
5312 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5313 break;
5314 case X86ISD::MOVLHPS:
5315 DecodeMOVLHPSMask(NumElems, Mask);
5316 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5317 break;
5318 case X86ISD::PALIGNR:
5319 ImmN = N->getOperand(N->getNumOperands()-1);
5320 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5321 break;
5322 case X86ISD::PSHUFD:
5323 case X86ISD::VPERMILPI:
5324 ImmN = N->getOperand(N->getNumOperands()-1);
5325 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5326 IsUnary = true;
5327 break;
5328 case X86ISD::PSHUFHW:
5329 ImmN = N->getOperand(N->getNumOperands()-1);
5330 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5331 IsUnary = true;
5332 break;
5333 case X86ISD::PSHUFLW:
5334 ImmN = N->getOperand(N->getNumOperands()-1);
5335 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5336 IsUnary = true;
5337 break;
5338 case X86ISD::PSHUFB: {
5339 IsUnary = true;
5340 SDValue MaskNode = N->getOperand(1);
5341 while (MaskNode->getOpcode() == ISD::BITCAST)
5342 MaskNode = MaskNode->getOperand(0);
5344 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5345 // If we have a build-vector, then things are easy.
5346 EVT VT = MaskNode.getValueType();
5347 assert(VT.isVector() &&
5348 "Can't produce a non-vector with a build_vector!");
5349 if (!VT.isInteger())
5350 return false;
5352 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5354 SmallVector<uint64_t, 32> RawMask;
5355 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5356 SDValue Op = MaskNode->getOperand(i);
5357 if (Op->getOpcode() == ISD::UNDEF) {
5358 RawMask.push_back((uint64_t)SM_SentinelUndef);
5359 continue;
5360 }
5361 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5362 if (!CN)
5363 return false;
5364 APInt MaskElement = CN->getAPIntValue();
5366 // We now have to decode the element which could be any integer size and
5367 // extract each byte of it.
5368 for (int j = 0; j < NumBytesPerElement; ++j) {
5369 // Note that this is x86 and so always little endian: the low byte is
5370 // the first byte of the mask.
5371 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5372 MaskElement = MaskElement.lshr(8);
5373 }
5374 }
5375 DecodePSHUFBMask(RawMask, Mask);
5376 break;
5377 }
5379 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5380 if (!MaskLoad)
5381 return false;
5383 SDValue Ptr = MaskLoad->getBasePtr();
5384 if (Ptr->getOpcode() == X86ISD::Wrapper)
5385 Ptr = Ptr->getOperand(0);
5387 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5388 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5389 return false;
5391 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5392 // FIXME: Support AVX-512 here.
5393 Type *Ty = C->getType();
5394 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5395 Ty->getVectorNumElements() != 32))
5396 return false;
5398 DecodePSHUFBMask(C, Mask);
5399 break;
5400 }
5402 return false;
5403 }
5404 case X86ISD::VPERMI:
5405 ImmN = N->getOperand(N->getNumOperands()-1);
5406 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5407 IsUnary = true;
5408 break;
5409 case X86ISD::MOVSS:
5410 case X86ISD::MOVSD: {
5411 // The index 0 always comes from the first element of the second source,
5412 // this is why MOVSS and MOVSD are used in the first place. The other
5413 // elements come from the other positions of the first source vector
5414 Mask.push_back(NumElems);
5415 for (unsigned i = 1; i != NumElems; ++i) {
5416 Mask.push_back(i);
5417 }
5418 break;
5419 }
5420 case X86ISD::VPERM2X128:
5421 ImmN = N->getOperand(N->getNumOperands()-1);
5422 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5423 if (Mask.empty()) return false;
5424 break;
5425 case X86ISD::MOVSLDUP:
5426 DecodeMOVSLDUPMask(VT, Mask);
5427 break;
5428 case X86ISD::MOVSHDUP:
5429 DecodeMOVSHDUPMask(VT, Mask);
5430 break;
5431 case X86ISD::MOVDDUP:
5432 case X86ISD::MOVLHPD:
5433 case X86ISD::MOVLPD:
5434 case X86ISD::MOVLPS:
5435 // Not yet implemented
5436 return false;
5437 default: llvm_unreachable("unknown target shuffle node");
5438 }
5440 // If we have a fake unary shuffle, the shuffle mask is spread across two
5441 // inputs that are actually the same node. Re-map the mask to always point
5442 // into the first input.
5443 if (IsFakeUnary)
5444 for (int &M : Mask)
5445 if (M >= (int)Mask.size())
5446 M -= Mask.size();
5448 return true;
5449 }
5451 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5452 /// element of the result of the vector shuffle.
5453 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5454 unsigned Depth) {
5455 if (Depth == 6)
5456 return SDValue(); // Limit search depth.
5458 SDValue V = SDValue(N, 0);
5459 EVT VT = V.getValueType();
5460 unsigned Opcode = V.getOpcode();
5462 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5463 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5464 int Elt = SV->getMaskElt(Index);
5466 if (Elt < 0)
5467 return DAG.getUNDEF(VT.getVectorElementType());
5469 unsigned NumElems = VT.getVectorNumElements();
5470 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5471 : SV->getOperand(1);
5472 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5473 }
5475 // Recurse into target specific vector shuffles to find scalars.
5476 if (isTargetShuffle(Opcode)) {
5477 MVT ShufVT = V.getSimpleValueType();
5478 unsigned NumElems = ShufVT.getVectorNumElements();
5479 SmallVector<int, 16> ShuffleMask;
5480 bool IsUnary;
5482 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5483 return SDValue();
5485 int Elt = ShuffleMask[Index];
5486 if (Elt < 0)
5487 return DAG.getUNDEF(ShufVT.getVectorElementType());
5489 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5490 : N->getOperand(1);
5491 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5492 Depth+1);
5493 }
5495 // Actual nodes that may contain scalar elements
5496 if (Opcode == ISD::BITCAST) {
5497 V = V.getOperand(0);
5498 EVT SrcVT = V.getValueType();
5499 unsigned NumElems = VT.getVectorNumElements();
5501 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5502 return SDValue();
5503 }
5505 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5506 return (Index == 0) ? V.getOperand(0)
5507 : DAG.getUNDEF(VT.getVectorElementType());
5509 if (V.getOpcode() == ISD::BUILD_VECTOR)
5510 return V.getOperand(Index);
5512 return SDValue();
5513 }
5515 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5516 /// shuffle operation which come from a consecutively from a zero. The
5517 /// search can start in two different directions, from left or right.
5518 /// We count undefs as zeros until PreferredNum is reached.
5519 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5520 unsigned NumElems, bool ZerosFromLeft,
5521 SelectionDAG &DAG,
5522 unsigned PreferredNum = -1U) {
5523 unsigned NumZeros = 0;
5524 for (unsigned i = 0; i != NumElems; ++i) {
5525 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5526 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5527 if (!Elt.getNode())
5528 break;
5530 if (X86::isZeroNode(Elt))
5531 ++NumZeros;
5532 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5533 NumZeros = std::min(NumZeros + 1, PreferredNum);
5534 else
5535 break;
5536 }
5538 return NumZeros;
5539 }
5541 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5542 /// correspond consecutively to elements from one of the vector operands,
5543 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5544 static
5545 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5546 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5547 unsigned NumElems, unsigned &OpNum) {
5548 bool SeenV1 = false;
5549 bool SeenV2 = false;
5551 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5552 int Idx = SVOp->getMaskElt(i);
5553 // Ignore undef indicies
5554 if (Idx < 0)
5555 continue;
5557 if (Idx < (int)NumElems)
5558 SeenV1 = true;
5559 else
5560 SeenV2 = true;
5562 // Only accept consecutive elements from the same vector
5563 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5564 return false;
5565 }
5567 OpNum = SeenV1 ? 0 : 1;
5568 return true;
5569 }
5571 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5572 /// logical left shift of a vector.
5573 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5574 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5575 unsigned NumElems =
5576 SVOp->getSimpleValueType(0).getVectorNumElements();
5577 unsigned NumZeros = getNumOfConsecutiveZeros(
5578 SVOp, NumElems, false /* check zeros from right */, DAG,
5579 SVOp->getMaskElt(0));
5580 unsigned OpSrc;
5582 if (!NumZeros)
5583 return false;
5585 // Considering the elements in the mask that are not consecutive zeros,
5586 // check if they consecutively come from only one of the source vectors.
5587 //
5588 // V1 = {X, A, B, C} 0
5589 // \ \ \ /
5590 // vector_shuffle V1, V2 <1, 2, 3, X>
5591 //
5592 if (!isShuffleMaskConsecutive(SVOp,
5593 0, // Mask Start Index
5594 NumElems-NumZeros, // Mask End Index(exclusive)
5595 NumZeros, // Where to start looking in the src vector
5596 NumElems, // Number of elements in vector
5597 OpSrc)) // Which source operand ?
5598 return false;
5600 isLeft = false;
5601 ShAmt = NumZeros;
5602 ShVal = SVOp->getOperand(OpSrc);
5603 return true;
5604 }
5606 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5607 /// logical left shift of a vector.
5608 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5609 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5610 unsigned NumElems =
5611 SVOp->getSimpleValueType(0).getVectorNumElements();
5612 unsigned NumZeros = getNumOfConsecutiveZeros(
5613 SVOp, NumElems, true /* check zeros from left */, DAG,
5614 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5615 unsigned OpSrc;
5617 if (!NumZeros)
5618 return false;
5620 // Considering the elements in the mask that are not consecutive zeros,
5621 // check if they consecutively come from only one of the source vectors.
5622 //
5623 // 0 { A, B, X, X } = V2
5624 // / \ / /
5625 // vector_shuffle V1, V2 <X, X, 4, 5>
5626 //
5627 if (!isShuffleMaskConsecutive(SVOp,
5628 NumZeros, // Mask Start Index
5629 NumElems, // Mask End Index(exclusive)
5630 0, // Where to start looking in the src vector
5631 NumElems, // Number of elements in vector
5632 OpSrc)) // Which source operand ?
5633 return false;
5635 isLeft = true;
5636 ShAmt = NumZeros;
5637 ShVal = SVOp->getOperand(OpSrc);
5638 return true;
5639 }
5641 /// isVectorShift - Returns true if the shuffle can be implemented as a
5642 /// logical left or right shift of a vector.
5643 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5644 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5645 // Although the logic below support any bitwidth size, there are no
5646 // shift instructions which handle more than 128-bit vectors.
5647 if (!SVOp->getSimpleValueType(0).is128BitVector())
5648 return false;
5650 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5651 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5652 return true;
5654 return false;
5655 }
5657 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5658 ///
5659 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5660 unsigned NumNonZero, unsigned NumZero,
5661 SelectionDAG &DAG,
5662 const X86Subtarget* Subtarget,
5663 const TargetLowering &TLI) {
5664 if (NumNonZero > 8)
5665 return SDValue();
5667 SDLoc dl(Op);
5668 SDValue V;
5669 bool First = true;
5670 for (unsigned i = 0; i < 16; ++i) {
5671 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5672 if (ThisIsNonZero && First) {
5673 if (NumZero)
5674 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5675 else
5676 V = DAG.getUNDEF(MVT::v8i16);
5677 First = false;
5678 }
5680 if ((i & 1) != 0) {
5681 SDValue ThisElt, LastElt;
5682 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5683 if (LastIsNonZero) {
5684 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5685 MVT::i16, Op.getOperand(i-1));
5686 }
5687 if (ThisIsNonZero) {
5688 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5689 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5690 ThisElt, DAG.getConstant(8, MVT::i8));
5691 if (LastIsNonZero)
5692 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5693 } else
5694 ThisElt = LastElt;
5696 if (ThisElt.getNode())
5697 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5698 DAG.getIntPtrConstant(i/2));
5699 }
5700 }
5702 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5703 }
5705 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5706 ///
5707 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5708 unsigned NumNonZero, unsigned NumZero,
5709 SelectionDAG &DAG,
5710 const X86Subtarget* Subtarget,
5711 const TargetLowering &TLI) {
5712 if (NumNonZero > 4)
5713 return SDValue();
5715 SDLoc dl(Op);
5716 SDValue V;
5717 bool First = true;
5718 for (unsigned i = 0; i < 8; ++i) {
5719 bool isNonZero = (NonZeros & (1 << i)) != 0;
5720 if (isNonZero) {
5721 if (First) {
5722 if (NumZero)
5723 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5724 else
5725 V = DAG.getUNDEF(MVT::v8i16);
5726 First = false;
5727 }
5728 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5729 MVT::v8i16, V, Op.getOperand(i),
5730 DAG.getIntPtrConstant(i));
5731 }
5732 }
5734 return V;
5735 }
5737 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5738 static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
5739 unsigned NonZeros, unsigned NumNonZero,
5740 unsigned NumZero, SelectionDAG &DAG,
5741 const X86Subtarget *Subtarget,
5742 const TargetLowering &TLI) {
5743 // We know there's at least one non-zero element
5744 unsigned FirstNonZeroIdx = 0;
5745 SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5746 while (FirstNonZero.getOpcode() == ISD::UNDEF ||
5747 X86::isZeroNode(FirstNonZero)) {
5748 ++FirstNonZeroIdx;
5749 FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5750 }
5752 if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5753 !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
5754 return SDValue();
5756 SDValue V = FirstNonZero.getOperand(0);
5757 MVT VVT = V.getSimpleValueType();
5758 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
5759 return SDValue();
5761 unsigned FirstNonZeroDst =
5762 cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
5763 unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
5764 unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
5765 unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
5767 for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
5768 SDValue Elem = Op.getOperand(Idx);
5769 if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
5770 continue;
5772 // TODO: What else can be here? Deal with it.
5773 if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5774 return SDValue();
5776 // TODO: Some optimizations are still possible here
5777 // ex: Getting one element from a vector, and the rest from another.
5778 if (Elem.getOperand(0) != V)
5779 return SDValue();
5781 unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
5782 if (Dst == Idx)
5783 ++CorrectIdx;
5784 else if (IncorrectIdx == -1U) {
5785 IncorrectIdx = Idx;
5786 IncorrectDst = Dst;
5787 } else
5788 // There was already one element with an incorrect index.
5789 // We can't optimize this case to an insertps.
5790 return SDValue();
5791 }
5793 if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
5794 SDLoc dl(Op);
5795 EVT VT = Op.getSimpleValueType();
5796 unsigned ElementMoveMask = 0;
5797 if (IncorrectIdx == -1U)
5798 ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
5799 else
5800 ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
5802 SDValue InsertpsMask =
5803 DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
5804 return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
5805 }
5807 return SDValue();
5808 }
5810 /// getVShift - Return a vector logical shift node.
5811 ///
5812 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5813 unsigned NumBits, SelectionDAG &DAG,
5814 const TargetLowering &TLI, SDLoc dl) {
5815 assert(VT.is128BitVector() && "Unknown type for VShift");
5816 EVT ShVT = MVT::v2i64;
5817 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5818 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5819 return DAG.getNode(ISD::BITCAST, dl, VT,
5820 DAG.getNode(Opc, dl, ShVT, SrcOp,
5821 DAG.getConstant(NumBits,
5822 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5823 }
5825 static SDValue
5826 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5828 // Check if the scalar load can be widened into a vector load. And if
5829 // the address is "base + cst" see if the cst can be "absorbed" into
5830 // the shuffle mask.
5831 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5832 SDValue Ptr = LD->getBasePtr();
5833 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5834 return SDValue();
5835 EVT PVT = LD->getValueType(0);
5836 if (PVT != MVT::i32 && PVT != MVT::f32)
5837 return SDValue();
5839 int FI = -1;
5840 int64_t Offset = 0;
5841 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5842 FI = FINode->getIndex();
5843 Offset = 0;
5844 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5845 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5846 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5847 Offset = Ptr.getConstantOperandVal(1);
5848 Ptr = Ptr.getOperand(0);
5849 } else {
5850 return SDValue();
5851 }
5853 // FIXME: 256-bit vector instructions don't require a strict alignment,
5854 // improve this code to support it better.
5855 unsigned RequiredAlign = VT.getSizeInBits()/8;
5856 SDValue Chain = LD->getChain();
5857 // Make sure the stack object alignment is at least 16 or 32.
5858 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5859 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5860 if (MFI->isFixedObjectIndex(FI)) {
5861 // Can't change the alignment. FIXME: It's possible to compute
5862 // the exact stack offset and reference FI + adjust offset instead.
5863 // If someone *really* cares about this. That's the way to implement it.
5864 return SDValue();
5865 } else {
5866 MFI->setObjectAlignment(FI, RequiredAlign);
5867 }
5868 }
5870 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5871 // Ptr + (Offset & ~15).
5872 if (Offset < 0)
5873 return SDValue();
5874 if ((Offset % RequiredAlign) & 3)
5875 return SDValue();
5876 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5877 if (StartOffset)
5878 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5879 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5881 int EltNo = (Offset - StartOffset) >> 2;
5882 unsigned NumElems = VT.getVectorNumElements();
5884 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5885 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5886 LD->getPointerInfo().getWithOffset(StartOffset),
5887 false, false, false, 0);
5889 SmallVector<int, 8> Mask;
5890 for (unsigned i = 0; i != NumElems; ++i)
5891 Mask.push_back(EltNo);
5893 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5894 }
5896 return SDValue();
5897 }
5899 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5900 /// vector of type 'VT', see if the elements can be replaced by a single large
5901 /// load which has the same value as a build_vector whose operands are 'elts'.
5902 ///
5903 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5904 ///
5905 /// FIXME: we'd also like to handle the case where the last elements are zero
5906 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5907 /// There's even a handy isZeroNode for that purpose.
5908 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5909 SDLoc &DL, SelectionDAG &DAG,
5910 bool isAfterLegalize) {
5911 EVT EltVT = VT.getVectorElementType();
5912 unsigned NumElems = Elts.size();
5914 LoadSDNode *LDBase = nullptr;
5915 unsigned LastLoadedElt = -1U;
5917 // For each element in the initializer, see if we've found a load or an undef.
5918 // If we don't find an initial load element, or later load elements are
5919 // non-consecutive, bail out.
5920 for (unsigned i = 0; i < NumElems; ++i) {
5921 SDValue Elt = Elts[i];
5923 if (!Elt.getNode() ||
5924 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5925 return SDValue();
5926 if (!LDBase) {
5927 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5928 return SDValue();
5929 LDBase = cast<LoadSDNode>(Elt.getNode());
5930 LastLoadedElt = i;
5931 continue;
5932 }
5933 if (Elt.getOpcode() == ISD::UNDEF)
5934 continue;
5936 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5937 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5938 return SDValue();
5939 LastLoadedElt = i;
5940 }
5942 // If we have found an entire vector of loads and undefs, then return a large
5943 // load of the entire vector width starting at the base pointer. If we found
5944 // consecutive loads for the low half, generate a vzext_load node.
5945 if (LastLoadedElt == NumElems - 1) {
5947 if (isAfterLegalize &&
5948 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5949 return SDValue();
5951 SDValue NewLd = SDValue();
5953 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5954 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5955 LDBase->getPointerInfo(),
5956 LDBase->isVolatile(), LDBase->isNonTemporal(),
5957 LDBase->isInvariant(), 0);
5958 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5959 LDBase->getPointerInfo(),
5960 LDBase->isVolatile(), LDBase->isNonTemporal(),
5961 LDBase->isInvariant(), LDBase->getAlignment());
5963 if (LDBase->hasAnyUseOfValue(1)) {
5964 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5965 SDValue(LDBase, 1),
5966 SDValue(NewLd.getNode(), 1));
5967 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5968 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5969 SDValue(NewLd.getNode(), 1));
5970 }
5972 return NewLd;
5973 }
5974 if (NumElems == 4 && LastLoadedElt == 1 &&
5975 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5976 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5977 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5978 SDValue ResNode =
5979 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5980 LDBase->getPointerInfo(),
5981 LDBase->getAlignment(),
5982 false/*isVolatile*/, true/*ReadMem*/,
5983 false/*WriteMem*/);
5985 // Make sure the newly-created LOAD is in the same position as LDBase in
5986 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5987 // update uses of LDBase's output chain to use the TokenFactor.
5988 if (LDBase->hasAnyUseOfValue(1)) {
5989 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5990 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5991 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5992 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5993 SDValue(ResNode.getNode(), 1));
5994 }
5996 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5997 }
5998 return SDValue();
5999 }
6001 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6002 /// to generate a splat value for the following cases:
6003 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6004 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6005 /// a scalar load, or a constant.
6006 /// The VBROADCAST node is returned when a pattern is found,
6007 /// or SDValue() otherwise.
6008 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6009 SelectionDAG &DAG) {
6010 // VBROADCAST requires AVX.
6011 // TODO: Splats could be generated for non-AVX CPUs using SSE
6012 // instructions, but there's less potential gain for only 128-bit vectors.
6013 if (!Subtarget->hasAVX())
6014 return SDValue();
6016 MVT VT = Op.getSimpleValueType();
6017 SDLoc dl(Op);
6019 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6020 "Unsupported vector type for broadcast.");
6022 SDValue Ld;
6023 bool ConstSplatVal;
6025 switch (Op.getOpcode()) {
6026 default:
6027 // Unknown pattern found.
6028 return SDValue();
6030 case ISD::BUILD_VECTOR: {
6031 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6032 BitVector UndefElements;
6033 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6035 // We need a splat of a single value to use broadcast, and it doesn't
6036 // make any sense if the value is only in one element of the vector.
6037 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6038 return SDValue();
6040 Ld = Splat;
6041 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6042 Ld.getOpcode() == ISD::ConstantFP);
6044 // Make sure that all of the users of a non-constant load are from the
6045 // BUILD_VECTOR node.
6046 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6047 return SDValue();
6048 break;
6049 }
6051 case ISD::VECTOR_SHUFFLE: {
6052 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6054 // Shuffles must have a splat mask where the first element is
6055 // broadcasted.
6056 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6057 return SDValue();
6059 SDValue Sc = Op.getOperand(0);
6060 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6061 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6063 if (!Subtarget->hasInt256())
6064 return SDValue();
6066 // Use the register form of the broadcast instruction available on AVX2.
6067 if (VT.getSizeInBits() >= 256)
6068 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6069 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6070 }
6072 Ld = Sc.getOperand(0);
6073 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6074 Ld.getOpcode() == ISD::ConstantFP);
6076 // The scalar_to_vector node and the suspected
6077 // load node must have exactly one user.
6078 // Constants may have multiple users.
6080 // AVX-512 has register version of the broadcast
6081 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6082 Ld.getValueType().getSizeInBits() >= 32;
6083 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6084 !hasRegVer))
6085 return SDValue();
6086 break;
6087 }
6088 }
6090 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6091 bool IsGE256 = (VT.getSizeInBits() >= 256);
6093 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6094 // instruction to save 8 or more bytes of constant pool data.
6095 // TODO: If multiple splats are generated to load the same constant,
6096 // it may be detrimental to overall size. There needs to be a way to detect
6097 // that condition to know if this is truly a size win.
6098 const Function *F = DAG.getMachineFunction().getFunction();
6099 bool OptForSize = F->getAttributes().
6100 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6102 // Handle broadcasting a single constant scalar from the constant pool
6103 // into a vector.
6104 // On Sandybridge (no AVX2), it is still better to load a constant vector
6105 // from the constant pool and not to broadcast it from a scalar.
6106 // But override that restriction when optimizing for size.
6107 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6108 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6109 EVT CVT = Ld.getValueType();
6110 assert(!CVT.isVector() && "Must not broadcast a vector type");
6112 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6113 // For size optimization, also splat v2f64 and v2i64, and for size opt
6114 // with AVX2, also splat i8 and i16.
6115 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6116 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6117 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6118 const Constant *C = nullptr;
6119 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6120 C = CI->getConstantIntValue();
6121 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6122 C = CF->getConstantFPValue();
6124 assert(C && "Invalid constant type");
6126 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6127 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6128 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6129 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6130 MachinePointerInfo::getConstantPool(),
6131 false, false, false, Alignment);
6133 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6134 }
6135 }
6137 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6139 // Handle AVX2 in-register broadcasts.
6140 if (!IsLoad && Subtarget->hasInt256() &&
6141 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6142 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6144 // The scalar source must be a normal load.
6145 if (!IsLoad)
6146 return SDValue();
6148 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6149 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6151 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6152 // double since there is no vbroadcastsd xmm
6153 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6154 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6155 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6156 }
6158 // Unsupported broadcast.
6159 return SDValue();
6160 }
6162 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6163 /// underlying vector and index.
6164 ///
6165 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6166 /// index.
6167 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6168 SDValue ExtIdx) {
6169 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6170 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6171 return Idx;
6173 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6174 // lowered this:
6175 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6176 // to:
6177 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6178 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6179 // undef)
6180 // Constant<0>)
6181 // In this case the vector is the extract_subvector expression and the index
6182 // is 2, as specified by the shuffle.
6183 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6184 SDValue ShuffleVec = SVOp->getOperand(0);
6185 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6186 assert(ShuffleVecVT.getVectorElementType() ==
6187 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6189 int ShuffleIdx = SVOp->getMaskElt(Idx);
6190 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6191 ExtractedFromVec = ShuffleVec;
6192 return ShuffleIdx;
6193 }
6194 return Idx;
6195 }
6197 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6198 MVT VT = Op.getSimpleValueType();
6200 // Skip if insert_vec_elt is not supported.
6201 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6202 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6203 return SDValue();
6205 SDLoc DL(Op);
6206 unsigned NumElems = Op.getNumOperands();
6208 SDValue VecIn1;
6209 SDValue VecIn2;
6210 SmallVector<unsigned, 4> InsertIndices;
6211 SmallVector<int, 8> Mask(NumElems, -1);
6213 for (unsigned i = 0; i != NumElems; ++i) {
6214 unsigned Opc = Op.getOperand(i).getOpcode();
6216 if (Opc == ISD::UNDEF)
6217 continue;
6219 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6220 // Quit if more than 1 elements need inserting.
6221 if (InsertIndices.size() > 1)
6222 return SDValue();
6224 InsertIndices.push_back(i);
6225 continue;
6226 }
6228 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6229 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6230 // Quit if non-constant index.
6231 if (!isa<ConstantSDNode>(ExtIdx))
6232 return SDValue();
6233 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6235 // Quit if extracted from vector of different type.
6236 if (ExtractedFromVec.getValueType() != VT)
6237 return SDValue();
6239 if (!VecIn1.getNode())
6240 VecIn1 = ExtractedFromVec;
6241 else if (VecIn1 != ExtractedFromVec) {
6242 if (!VecIn2.getNode())
6243 VecIn2 = ExtractedFromVec;
6244 else if (VecIn2 != ExtractedFromVec)
6245 // Quit if more than 2 vectors to shuffle
6246 return SDValue();
6247 }
6249 if (ExtractedFromVec == VecIn1)
6250 Mask[i] = Idx;
6251 else if (ExtractedFromVec == VecIn2)
6252 Mask[i] = Idx + NumElems;
6253 }
6255 if (!VecIn1.getNode())
6256 return SDValue();
6258 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6259 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6260 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6261 unsigned Idx = InsertIndices[i];
6262 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6263 DAG.getIntPtrConstant(Idx));
6264 }
6266 return NV;
6267 }
6269 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6270 SDValue
6271 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6273 MVT VT = Op.getSimpleValueType();
6274 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6275 "Unexpected type in LowerBUILD_VECTORvXi1!");
6277 SDLoc dl(Op);
6278 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6279 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6280 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6281 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6282 }
6284 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6285 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6286 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6287 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6288 }
6290 bool AllContants = true;
6291 uint64_t Immediate = 0;
6292 int NonConstIdx = -1;
6293 bool IsSplat = true;
6294 unsigned NumNonConsts = 0;
6295 unsigned NumConsts = 0;
6296 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6297 SDValue In = Op.getOperand(idx);
6298 if (In.getOpcode() == ISD::UNDEF)
6299 continue;
6300 if (!isa<ConstantSDNode>(In)) {
6301 AllContants = false;
6302 NonConstIdx = idx;
6303 NumNonConsts++;
6304 }
6305 else {
6306 NumConsts++;
6307 if (cast<ConstantSDNode>(In)->getZExtValue())
6308 Immediate |= (1ULL << idx);
6309 }
6310 if (In != Op.getOperand(0))
6311 IsSplat = false;
6312 }
6314 if (AllContants) {
6315 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6316 DAG.getConstant(Immediate, MVT::i16));
6317 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6318 DAG.getIntPtrConstant(0));
6319 }
6321 if (NumNonConsts == 1 && NonConstIdx != 0) {
6322 SDValue DstVec;
6323 if (NumConsts) {
6324 SDValue VecAsImm = DAG.getConstant(Immediate,
6325 MVT::getIntegerVT(VT.getSizeInBits()));
6326 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6327 }
6328 else
6329 DstVec = DAG.getUNDEF(VT);
6330 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6331 Op.getOperand(NonConstIdx),
6332 DAG.getIntPtrConstant(NonConstIdx));
6333 }
6334 if (!IsSplat && (NonConstIdx != 0))
6335 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6336 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6337 SDValue Select;
6338 if (IsSplat)
6339 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6340 DAG.getConstant(-1, SelectVT),
6341 DAG.getConstant(0, SelectVT));
6342 else
6343 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6344 DAG.getConstant((Immediate | 1), SelectVT),
6345 DAG.getConstant(Immediate, SelectVT));
6346 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6347 }
6349 /// \brief Return true if \p N implements a horizontal binop and return the
6350 /// operands for the horizontal binop into V0 and V1.
6351 ///
6352 /// This is a helper function of PerformBUILD_VECTORCombine.
6353 /// This function checks that the build_vector \p N in input implements a
6354 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6355 /// operation to match.
6356 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6357 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6358 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6359 /// arithmetic sub.
6360 ///
6361 /// This function only analyzes elements of \p N whose indices are
6362 /// in range [BaseIdx, LastIdx).
6363 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6364 SelectionDAG &DAG,
6365 unsigned BaseIdx, unsigned LastIdx,
6366 SDValue &V0, SDValue &V1) {
6367 EVT VT = N->getValueType(0);
6369 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6370 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6371 "Invalid Vector in input!");
6373 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6374 bool CanFold = true;
6375 unsigned ExpectedVExtractIdx = BaseIdx;
6376 unsigned NumElts = LastIdx - BaseIdx;
6377 V0 = DAG.getUNDEF(VT);
6378 V1 = DAG.getUNDEF(VT);
6380 // Check if N implements a horizontal binop.
6381 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6382 SDValue Op = N->getOperand(i + BaseIdx);
6384 // Skip UNDEFs.
6385 if (Op->getOpcode() == ISD::UNDEF) {
6386 // Update the expected vector extract index.
6387 if (i * 2 == NumElts)
6388 ExpectedVExtractIdx = BaseIdx;
6389 ExpectedVExtractIdx += 2;
6390 continue;
6391 }
6393 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6395 if (!CanFold)
6396 break;
6398 SDValue Op0 = Op.getOperand(0);
6399 SDValue Op1 = Op.getOperand(1);
6401 // Try to match the following pattern:
6402 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6403 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6404 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6405 Op0.getOperand(0) == Op1.getOperand(0) &&
6406 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6407 isa<ConstantSDNode>(Op1.getOperand(1)));
6408 if (!CanFold)
6409 break;
6411 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6412 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6414 if (i * 2 < NumElts) {
6415 if (V0.getOpcode() == ISD::UNDEF)
6416 V0 = Op0.getOperand(0);
6417 } else {
6418 if (V1.getOpcode() == ISD::UNDEF)
6419 V1 = Op0.getOperand(0);
6420 if (i * 2 == NumElts)
6421 ExpectedVExtractIdx = BaseIdx;
6422 }
6424 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6425 if (I0 == ExpectedVExtractIdx)
6426 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6427 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6428 // Try to match the following dag sequence:
6429 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6430 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6431 } else
6432 CanFold = false;
6434 ExpectedVExtractIdx += 2;
6435 }
6437 return CanFold;
6438 }
6440 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6441 /// a concat_vector.
6442 ///
6443 /// This is a helper function of PerformBUILD_VECTORCombine.
6444 /// This function expects two 256-bit vectors called V0 and V1.
6445 /// At first, each vector is split into two separate 128-bit vectors.
6446 /// Then, the resulting 128-bit vectors are used to implement two
6447 /// horizontal binary operations.
6448 ///
6449 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6450 ///
6451 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6452 /// the two new horizontal binop.
6453 /// When Mode is set, the first horizontal binop dag node would take as input
6454 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6455 /// horizontal binop dag node would take as input the lower 128-bit of V1
6456 /// and the upper 128-bit of V1.
6457 /// Example:
6458 /// HADD V0_LO, V0_HI
6459 /// HADD V1_LO, V1_HI
6460 ///
6461 /// Otherwise, the first horizontal binop dag node takes as input the lower
6462 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6463 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6464 /// Example:
6465 /// HADD V0_LO, V1_LO
6466 /// HADD V0_HI, V1_HI
6467 ///
6468 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6469 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6470 /// the upper 128-bits of the result.
6471 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6472 SDLoc DL, SelectionDAG &DAG,
6473 unsigned X86Opcode, bool Mode,
6474 bool isUndefLO, bool isUndefHI) {
6475 EVT VT = V0.getValueType();
6476 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6477 "Invalid nodes in input!");
6479 unsigned NumElts = VT.getVectorNumElements();
6480 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6481 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6482 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6483 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6484 EVT NewVT = V0_LO.getValueType();
6486 SDValue LO = DAG.getUNDEF(NewVT);
6487 SDValue HI = DAG.getUNDEF(NewVT);
6489 if (Mode) {
6490 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6491 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6492 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6493 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6494 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6495 } else {
6496 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6497 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6498 V1_LO->getOpcode() != ISD::UNDEF))
6499 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6501 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6502 V1_HI->getOpcode() != ISD::UNDEF))
6503 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6504 }
6506 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6507 }
6509 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6510 /// sequence of 'vadd + vsub + blendi'.
6511 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6512 const X86Subtarget *Subtarget) {
6513 SDLoc DL(BV);
6514 EVT VT = BV->getValueType(0);
6515 unsigned NumElts = VT.getVectorNumElements();
6516 SDValue InVec0 = DAG.getUNDEF(VT);
6517 SDValue InVec1 = DAG.getUNDEF(VT);
6519 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6520 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6522 // Odd-numbered elements in the input build vector are obtained from
6523 // adding two integer/float elements.
6524 // Even-numbered elements in the input build vector are obtained from
6525 // subtracting two integer/float elements.
6526 unsigned ExpectedOpcode = ISD::FSUB;
6527 unsigned NextExpectedOpcode = ISD::FADD;
6528 bool AddFound = false;
6529 bool SubFound = false;
6531 for (unsigned i = 0, e = NumElts; i != e; i++) {
6532 SDValue Op = BV->getOperand(i);
6534 // Skip 'undef' values.
6535 unsigned Opcode = Op.getOpcode();
6536 if (Opcode == ISD::UNDEF) {
6537 std::swap(ExpectedOpcode, NextExpectedOpcode);
6538 continue;
6539 }
6541 // Early exit if we found an unexpected opcode.
6542 if (Opcode != ExpectedOpcode)
6543 return SDValue();
6545 SDValue Op0 = Op.getOperand(0);
6546 SDValue Op1 = Op.getOperand(1);
6548 // Try to match the following pattern:
6549 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6550 // Early exit if we cannot match that sequence.
6551 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6552 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6553 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6554 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6555 Op0.getOperand(1) != Op1.getOperand(1))
6556 return SDValue();
6558 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6559 if (I0 != i)
6560 return SDValue();
6562 // We found a valid add/sub node. Update the information accordingly.
6563 if (i & 1)
6564 AddFound = true;
6565 else
6566 SubFound = true;
6568 // Update InVec0 and InVec1.
6569 if (InVec0.getOpcode() == ISD::UNDEF)
6570 InVec0 = Op0.getOperand(0);
6571 if (InVec1.getOpcode() == ISD::UNDEF)
6572 InVec1 = Op1.getOperand(0);
6574 // Make sure that operands in input to each add/sub node always
6575 // come from a same pair of vectors.
6576 if (InVec0 != Op0.getOperand(0)) {
6577 if (ExpectedOpcode == ISD::FSUB)
6578 return SDValue();
6580 // FADD is commutable. Try to commute the operands
6581 // and then test again.
6582 std::swap(Op0, Op1);
6583 if (InVec0 != Op0.getOperand(0))
6584 return SDValue();
6585 }
6587 if (InVec1 != Op1.getOperand(0))
6588 return SDValue();
6590 // Update the pair of expected opcodes.
6591 std::swap(ExpectedOpcode, NextExpectedOpcode);
6592 }
6594 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6595 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6596 InVec1.getOpcode() != ISD::UNDEF)
6597 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6599 return SDValue();
6600 }
6602 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6603 const X86Subtarget *Subtarget) {
6604 SDLoc DL(N);
6605 EVT VT = N->getValueType(0);
6606 unsigned NumElts = VT.getVectorNumElements();
6607 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6608 SDValue InVec0, InVec1;
6610 // Try to match an ADDSUB.
6611 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6612 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6613 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6614 if (Value.getNode())
6615 return Value;
6616 }
6618 // Try to match horizontal ADD/SUB.
6619 unsigned NumUndefsLO = 0;
6620 unsigned NumUndefsHI = 0;
6621 unsigned Half = NumElts/2;
6623 // Count the number of UNDEF operands in the build_vector in input.
6624 for (unsigned i = 0, e = Half; i != e; ++i)
6625 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6626 NumUndefsLO++;
6628 for (unsigned i = Half, e = NumElts; i != e; ++i)
6629 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6630 NumUndefsHI++;
6632 // Early exit if this is either a build_vector of all UNDEFs or all the
6633 // operands but one are UNDEF.
6634 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6635 return SDValue();
6637 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6638 // Try to match an SSE3 float HADD/HSUB.
6639 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6640 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6642 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6643 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6644 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6645 // Try to match an SSSE3 integer HADD/HSUB.
6646 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6647 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6649 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6650 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6651 }
6653 if (!Subtarget->hasAVX())
6654 return SDValue();
6656 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6657 // Try to match an AVX horizontal add/sub of packed single/double
6658 // precision floating point values from 256-bit vectors.
6659 SDValue InVec2, InVec3;
6660 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6661 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6662 ((InVec0.getOpcode() == ISD::UNDEF ||
6663 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6664 ((InVec1.getOpcode() == ISD::UNDEF ||
6665 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6666 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6668 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6669 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6670 ((InVec0.getOpcode() == ISD::UNDEF ||
6671 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6672 ((InVec1.getOpcode() == ISD::UNDEF ||
6673 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6674 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6675 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6676 // Try to match an AVX2 horizontal add/sub of signed integers.
6677 SDValue InVec2, InVec3;
6678 unsigned X86Opcode;
6679 bool CanFold = true;
6681 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6682 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6683 ((InVec0.getOpcode() == ISD::UNDEF ||
6684 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6685 ((InVec1.getOpcode() == ISD::UNDEF ||
6686 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6687 X86Opcode = X86ISD::HADD;
6688 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6689 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6690 ((InVec0.getOpcode() == ISD::UNDEF ||
6691 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6692 ((InVec1.getOpcode() == ISD::UNDEF ||
6693 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6694 X86Opcode = X86ISD::HSUB;
6695 else
6696 CanFold = false;
6698 if (CanFold) {
6699 // Fold this build_vector into a single horizontal add/sub.
6700 // Do this only if the target has AVX2.
6701 if (Subtarget->hasAVX2())
6702 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6704 // Do not try to expand this build_vector into a pair of horizontal
6705 // add/sub if we can emit a pair of scalar add/sub.
6706 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6707 return SDValue();
6709 // Convert this build_vector into a pair of horizontal binop followed by
6710 // a concat vector.
6711 bool isUndefLO = NumUndefsLO == Half;
6712 bool isUndefHI = NumUndefsHI == Half;
6713 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6714 isUndefLO, isUndefHI);
6715 }
6716 }
6718 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6719 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6720 unsigned X86Opcode;
6721 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6722 X86Opcode = X86ISD::HADD;
6723 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6724 X86Opcode = X86ISD::HSUB;
6725 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6726 X86Opcode = X86ISD::FHADD;
6727 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6728 X86Opcode = X86ISD::FHSUB;
6729 else
6730 return SDValue();
6732 // Don't try to expand this build_vector into a pair of horizontal add/sub
6733 // if we can simply emit a pair of scalar add/sub.
6734 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6735 return SDValue();
6737 // Convert this build_vector into two horizontal add/sub followed by
6738 // a concat vector.
6739 bool isUndefLO = NumUndefsLO == Half;
6740 bool isUndefHI = NumUndefsHI == Half;
6741 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6742 isUndefLO, isUndefHI);
6743 }
6745 return SDValue();
6746 }
6748 SDValue
6749 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6750 SDLoc dl(Op);
6752 MVT VT = Op.getSimpleValueType();
6753 MVT ExtVT = VT.getVectorElementType();
6754 unsigned NumElems = Op.getNumOperands();
6756 // Generate vectors for predicate vectors.
6757 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6758 return LowerBUILD_VECTORvXi1(Op, DAG);
6760 // Vectors containing all zeros can be matched by pxor and xorps later
6761 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6762 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6763 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6764 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6765 return Op;
6767 return getZeroVector(VT, Subtarget, DAG, dl);
6768 }
6770 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6771 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6772 // vpcmpeqd on 256-bit vectors.
6773 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6774 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6775 return Op;
6777 if (!VT.is512BitVector())
6778 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6779 }
6781 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6782 if (Broadcast.getNode())
6783 return Broadcast;
6785 unsigned EVTBits = ExtVT.getSizeInBits();
6787 unsigned NumZero = 0;
6788 unsigned NumNonZero = 0;
6789 unsigned NonZeros = 0;
6790 bool IsAllConstants = true;
6791 SmallSet<SDValue, 8> Values;
6792 for (unsigned i = 0; i < NumElems; ++i) {
6793 SDValue Elt = Op.getOperand(i);
6794 if (Elt.getOpcode() == ISD::UNDEF)
6795 continue;
6796 Values.insert(Elt);
6797 if (Elt.getOpcode() != ISD::Constant &&
6798 Elt.getOpcode() != ISD::ConstantFP)
6799 IsAllConstants = false;
6800 if (X86::isZeroNode(Elt))
6801 NumZero++;
6802 else {
6803 NonZeros |= (1 << i);
6804 NumNonZero++;
6805 }
6806 }
6808 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6809 if (NumNonZero == 0)
6810 return DAG.getUNDEF(VT);
6812 // Special case for single non-zero, non-undef, element.
6813 if (NumNonZero == 1) {
6814 unsigned Idx = countTrailingZeros(NonZeros);
6815 SDValue Item = Op.getOperand(Idx);
6817 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6818 // the value are obviously zero, truncate the value to i32 and do the
6819 // insertion that way. Only do this if the value is non-constant or if the
6820 // value is a constant being inserted into element 0. It is cheaper to do
6821 // a constant pool load than it is to do a movd + shuffle.
6822 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6823 (!IsAllConstants || Idx == 0)) {
6824 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6825 // Handle SSE only.
6826 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6827 EVT VecVT = MVT::v4i32;
6828 unsigned VecElts = 4;
6830 // Truncate the value (which may itself be a constant) to i32, and
6831 // convert it to a vector with movd (S2V+shuffle to zero extend).
6832 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6833 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6835 // If using the new shuffle lowering, just directly insert this.
6836 if (ExperimentalVectorShuffleLowering)
6837 return DAG.getNode(
6838 ISD::BITCAST, dl, VT,
6839 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6841 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6843 // Now we have our 32-bit value zero extended in the low element of
6844 // a vector. If Idx != 0, swizzle it into place.
6845 if (Idx != 0) {
6846 SmallVector<int, 4> Mask;
6847 Mask.push_back(Idx);
6848 for (unsigned i = 1; i != VecElts; ++i)
6849 Mask.push_back(i);
6850 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6851 &Mask[0]);
6852 }
6853 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6854 }
6855 }
6857 // If we have a constant or non-constant insertion into the low element of
6858 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6859 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6860 // depending on what the source datatype is.
6861 if (Idx == 0) {
6862 if (NumZero == 0)
6863 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6865 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6866 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6867 if (VT.is256BitVector() || VT.is512BitVector()) {
6868 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6869 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6870 Item, DAG.getIntPtrConstant(0));
6871 }
6872 assert(VT.is128BitVector() && "Expected an SSE value type!");
6873 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6874 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6875 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6876 }
6878 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6879 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6880 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6881 if (VT.is256BitVector()) {
6882 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6883 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6884 } else {
6885 assert(VT.is128BitVector() && "Expected an SSE value type!");
6886 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6887 }
6888 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6889 }
6890 }
6892 // Is it a vector logical left shift?
6893 if (NumElems == 2 && Idx == 1 &&
6894 X86::isZeroNode(Op.getOperand(0)) &&
6895 !X86::isZeroNode(Op.getOperand(1))) {
6896 unsigned NumBits = VT.getSizeInBits();
6897 return getVShift(true, VT,
6898 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6899 VT, Op.getOperand(1)),
6900 NumBits/2, DAG, *this, dl);
6901 }
6903 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6904 return SDValue();
6906 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6907 // is a non-constant being inserted into an element other than the low one,
6908 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6909 // movd/movss) to move this into the low element, then shuffle it into
6910 // place.
6911 if (EVTBits == 32) {
6912 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6914 // If using the new shuffle lowering, just directly insert this.
6915 if (ExperimentalVectorShuffleLowering)
6916 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6918 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6919 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6920 SmallVector<int, 8> MaskVec;
6921 for (unsigned i = 0; i != NumElems; ++i)
6922 MaskVec.push_back(i == Idx ? 0 : 1);
6923 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6924 }
6925 }
6927 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6928 if (Values.size() == 1) {
6929 if (EVTBits == 32) {
6930 // Instead of a shuffle like this:
6931 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6932 // Check if it's possible to issue this instead.
6933 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6934 unsigned Idx = countTrailingZeros(NonZeros);
6935 SDValue Item = Op.getOperand(Idx);
6936 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6937 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6938 }
6939 return SDValue();
6940 }
6942 // A vector full of immediates; various special cases are already
6943 // handled, so this is best done with a single constant-pool load.
6944 if (IsAllConstants)
6945 return SDValue();
6947 // For AVX-length vectors, build the individual 128-bit pieces and use
6948 // shuffles to put them in place.
6949 if (VT.is256BitVector() || VT.is512BitVector()) {
6950 SmallVector<SDValue, 64> V;
6951 for (unsigned i = 0; i != NumElems; ++i)
6952 V.push_back(Op.getOperand(i));
6954 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6956 // Build both the lower and upper subvector.
6957 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6958 makeArrayRef(&V[0], NumElems/2));
6959 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6960 makeArrayRef(&V[NumElems / 2], NumElems/2));
6962 // Recreate the wider vector with the lower and upper part.
6963 if (VT.is256BitVector())
6964 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6965 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6966 }
6968 // Let legalizer expand 2-wide build_vectors.
6969 if (EVTBits == 64) {
6970 if (NumNonZero == 1) {
6971 // One half is zero or undef.
6972 unsigned Idx = countTrailingZeros(NonZeros);
6973 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6974 Op.getOperand(Idx));
6975 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6976 }
6977 return SDValue();
6978 }
6980 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6981 if (EVTBits == 8 && NumElems == 16) {
6982 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6983 Subtarget, *this);
6984 if (V.getNode()) return V;
6985 }
6987 if (EVTBits == 16 && NumElems == 8) {
6988 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6989 Subtarget, *this);
6990 if (V.getNode()) return V;
6991 }
6993 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6994 if (EVTBits == 32 && NumElems == 4) {
6995 SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
6996 NumZero, DAG, Subtarget, *this);
6997 if (V.getNode())
6998 return V;
6999 }
7001 // If element VT is == 32 bits, turn it into a number of shuffles.
7002 SmallVector<SDValue, 8> V(NumElems);
7003 if (NumElems == 4 && NumZero > 0) {
7004 for (unsigned i = 0; i < 4; ++i) {
7005 bool isZero = !(NonZeros & (1 << i));
7006 if (isZero)
7007 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7008 else
7009 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7010 }
7012 for (unsigned i = 0; i < 2; ++i) {
7013 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7014 default: break;
7015 case 0:
7016 V[i] = V[i*2]; // Must be a zero vector.
7017 break;
7018 case 1:
7019 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7020 break;
7021 case 2:
7022 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7023 break;
7024 case 3:
7025 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7026 break;
7027 }
7028 }
7030 bool Reverse1 = (NonZeros & 0x3) == 2;
7031 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7032 int MaskVec[] = {
7033 Reverse1 ? 1 : 0,
7034 Reverse1 ? 0 : 1,
7035 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7036 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7037 };
7038 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7039 }
7041 if (Values.size() > 1 && VT.is128BitVector()) {
7042 // Check for a build vector of consecutive loads.
7043 for (unsigned i = 0; i < NumElems; ++i)
7044 V[i] = Op.getOperand(i);
7046 // Check for elements which are consecutive loads.
7047 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7048 if (LD.getNode())
7049 return LD;
7051 // Check for a build vector from mostly shuffle plus few inserting.
7052 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7053 if (Sh.getNode())
7054 return Sh;
7056 // For SSE 4.1, use insertps to put the high elements into the low element.
7057 if (getSubtarget()->hasSSE41()) {
7058 SDValue Result;
7059 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7060 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7061 else
7062 Result = DAG.getUNDEF(VT);
7064 for (unsigned i = 1; i < NumElems; ++i) {
7065 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7066 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7067 Op.getOperand(i), DAG.getIntPtrConstant(i));
7068 }
7069 return Result;
7070 }
7072 // Otherwise, expand into a number of unpckl*, start by extending each of
7073 // our (non-undef) elements to the full vector width with the element in the
7074 // bottom slot of the vector (which generates no code for SSE).
7075 for (unsigned i = 0; i < NumElems; ++i) {
7076 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7077 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7078 else
7079 V[i] = DAG.getUNDEF(VT);
7080 }
7082 // Next, we iteratively mix elements, e.g. for v4f32:
7083 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7084 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7085 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7086 unsigned EltStride = NumElems >> 1;
7087 while (EltStride != 0) {
7088 for (unsigned i = 0; i < EltStride; ++i) {
7089 // If V[i+EltStride] is undef and this is the first round of mixing,
7090 // then it is safe to just drop this shuffle: V[i] is already in the
7091 // right place, the one element (since it's the first round) being
7092 // inserted as undef can be dropped. This isn't safe for successive
7093 // rounds because they will permute elements within both vectors.
7094 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7095 EltStride == NumElems/2)
7096 continue;
7098 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7099 }
7100 EltStride >>= 1;
7101 }
7102 return V[0];
7103 }
7104 return SDValue();
7105 }
7107 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7108 // to create 256-bit vectors from two other 128-bit ones.
7109 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7110 SDLoc dl(Op);
7111 MVT ResVT = Op.getSimpleValueType();
7113 assert((ResVT.is256BitVector() ||
7114 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7116 SDValue V1 = Op.getOperand(0);
7117 SDValue V2 = Op.getOperand(1);
7118 unsigned NumElems = ResVT.getVectorNumElements();
7119 if(ResVT.is256BitVector())
7120 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7122 if (Op.getNumOperands() == 4) {
7123 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7124 ResVT.getVectorNumElements()/2);
7125 SDValue V3 = Op.getOperand(2);
7126 SDValue V4 = Op.getOperand(3);
7127 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7128 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7129 }
7130 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7131 }
7133 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7134 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7135 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7136 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7137 Op.getNumOperands() == 4)));
7139 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7140 // from two other 128-bit ones.
7142 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7143 return LowerAVXCONCAT_VECTORS(Op, DAG);
7144 }
7147 //===----------------------------------------------------------------------===//
7148 // Vector shuffle lowering
7149 //
7150 // This is an experimental code path for lowering vector shuffles on x86. It is
7151 // designed to handle arbitrary vector shuffles and blends, gracefully
7152 // degrading performance as necessary. It works hard to recognize idiomatic
7153 // shuffles and lower them to optimal instruction patterns without leaving
7154 // a framework that allows reasonably efficient handling of all vector shuffle
7155 // patterns.
7156 //===----------------------------------------------------------------------===//
7158 /// \brief Tiny helper function to identify a no-op mask.
7159 ///
7160 /// This is a somewhat boring predicate function. It checks whether the mask
7161 /// array input, which is assumed to be a single-input shuffle mask of the kind
7162 /// used by the X86 shuffle instructions (not a fully general
7163 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7164 /// in-place shuffle are 'no-op's.
7165 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7166 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7167 if (Mask[i] != -1 && Mask[i] != i)
7168 return false;
7169 return true;
7170 }
7172 /// \brief Helper function to classify a mask as a single-input mask.
7173 ///
7174 /// This isn't a generic single-input test because in the vector shuffle
7175 /// lowering we canonicalize single inputs to be the first input operand. This
7176 /// means we can more quickly test for a single input by only checking whether
7177 /// an input from the second operand exists. We also assume that the size of
7178 /// mask corresponds to the size of the input vectors which isn't true in the
7179 /// fully general case.
7180 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7181 for (int M : Mask)
7182 if (M >= (int)Mask.size())
7183 return false;
7184 return true;
7185 }
7187 /// \brief Test whether there are elements crossing 128-bit lanes in this
7188 /// shuffle mask.
7189 ///
7190 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7191 /// and we routinely test for these.
7192 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7193 int LaneSize = 128 / VT.getScalarSizeInBits();
7194 int Size = Mask.size();
7195 for (int i = 0; i < Size; ++i)
7196 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7197 return true;
7198 return false;
7199 }
7201 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7202 ///
7203 /// This checks a shuffle mask to see if it is performing the same
7204 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7205 /// that it is also not lane-crossing. It may however involve a blend from the
7206 /// same lane of a second vector.
7207 ///
7208 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7209 /// non-trivial to compute in the face of undef lanes. The representation is
7210 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7211 /// entries from both V1 and V2 inputs to the wider mask.
7212 static bool
7213 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7214 SmallVectorImpl<int> &RepeatedMask) {
7215 int LaneSize = 128 / VT.getScalarSizeInBits();
7216 RepeatedMask.resize(LaneSize, -1);
7217 int Size = Mask.size();
7218 for (int i = 0; i < Size; ++i) {
7219 if (Mask[i] < 0)
7220 continue;
7221 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7222 // This entry crosses lanes, so there is no way to model this shuffle.
7223 return false;
7225 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7226 if (RepeatedMask[i % LaneSize] == -1)
7227 // This is the first non-undef entry in this slot of a 128-bit lane.
7228 RepeatedMask[i % LaneSize] =
7229 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7230 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7231 // Found a mismatch with the repeated mask.
7232 return false;
7233 }
7234 return true;
7235 }
7237 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7238 // 2013 will allow us to use it as a non-type template parameter.
7239 namespace {
7241 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7242 ///
7243 /// See its documentation for details.
7244 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7245 if (Mask.size() != Args.size())
7246 return false;
7247 for (int i = 0, e = Mask.size(); i < e; ++i) {
7248 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7249 if (Mask[i] != -1 && Mask[i] != *Args[i])
7250 return false;
7251 }
7252 return true;
7253 }
7255 } // namespace
7257 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7258 /// arguments.
7259 ///
7260 /// This is a fast way to test a shuffle mask against a fixed pattern:
7261 ///
7262 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7263 ///
7264 /// It returns true if the mask is exactly as wide as the argument list, and
7265 /// each element of the mask is either -1 (signifying undef) or the value given
7266 /// in the argument.
7267 static const VariadicFunction1<
7268 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7270 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7271 ///
7272 /// This helper function produces an 8-bit shuffle immediate corresponding to
7273 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7274 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7275 /// example.
7276 ///
7277 /// NB: We rely heavily on "undef" masks preserving the input lane.
7278 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7279 SelectionDAG &DAG) {
7280 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7281 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7282 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7283 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7284 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7286 unsigned Imm = 0;
7287 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7288 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7289 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7290 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7291 return DAG.getConstant(Imm, MVT::i8);
7292 }
7294 /// \brief Try to emit a blend instruction for a shuffle.
7295 ///
7296 /// This doesn't do any checks for the availability of instructions for blending
7297 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7298 /// be matched in the backend with the type given. What it does check for is
7299 /// that the shuffle mask is in fact a blend.
7300 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7301 SDValue V2, ArrayRef<int> Mask,
7302 const X86Subtarget *Subtarget,
7303 SelectionDAG &DAG) {
7305 unsigned BlendMask = 0;
7306 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7307 if (Mask[i] >= Size) {
7308 if (Mask[i] != i + Size)
7309 return SDValue(); // Shuffled V2 input!
7310 BlendMask |= 1u << i;
7311 continue;
7312 }
7313 if (Mask[i] >= 0 && Mask[i] != i)
7314 return SDValue(); // Shuffled V1 input!
7315 }
7316 switch (VT.SimpleTy) {
7317 case MVT::v2f64:
7318 case MVT::v4f32:
7319 case MVT::v4f64:
7320 case MVT::v8f32:
7321 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7322 DAG.getConstant(BlendMask, MVT::i8));
7324 case MVT::v4i64:
7325 case MVT::v8i32:
7326 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7327 // FALLTHROUGH
7328 case MVT::v2i64:
7329 case MVT::v4i32:
7330 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7331 // that instruction.
7332 if (Subtarget->hasAVX2()) {
7333 // Scale the blend by the number of 32-bit dwords per element.
7334 int Scale = VT.getScalarSizeInBits() / 32;
7335 BlendMask = 0;
7336 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7337 if (Mask[i] >= Size)
7338 for (int j = 0; j < Scale; ++j)
7339 BlendMask |= 1u << (i * Scale + j);
7341 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7342 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7343 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7344 return DAG.getNode(ISD::BITCAST, DL, VT,
7345 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7346 DAG.getConstant(BlendMask, MVT::i8)));
7347 }
7348 // FALLTHROUGH
7349 case MVT::v8i16: {
7350 // For integer shuffles we need to expand the mask and cast the inputs to
7351 // v8i16s prior to blending.
7352 int Scale = 8 / VT.getVectorNumElements();
7353 BlendMask = 0;
7354 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7355 if (Mask[i] >= Size)
7356 for (int j = 0; j < Scale; ++j)
7357 BlendMask |= 1u << (i * Scale + j);
7359 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7360 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7361 return DAG.getNode(ISD::BITCAST, DL, VT,
7362 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7363 DAG.getConstant(BlendMask, MVT::i8)));
7364 }
7366 case MVT::v16i16: {
7367 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7368 SmallVector<int, 8> RepeatedMask;
7369 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7370 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7371 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7372 BlendMask = 0;
7373 for (int i = 0; i < 8; ++i)
7374 if (RepeatedMask[i] >= 16)
7375 BlendMask |= 1u << i;
7376 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7377 DAG.getConstant(BlendMask, MVT::i8));
7378 }
7379 }
7380 // FALLTHROUGH
7381 case MVT::v32i8: {
7382 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7383 // Scale the blend by the number of bytes per element.
7384 int Scale = VT.getScalarSizeInBits() / 8;
7385 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7387 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7388 // mix of LLVM's code generator and the x86 backend. We tell the code
7389 // generator that boolean values in the elements of an x86 vector register
7390 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7391 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7392 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7393 // of the element (the remaining are ignored) and 0 in that high bit would
7394 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7395 // the LLVM model for boolean values in vector elements gets the relevant
7396 // bit set, it is set backwards and over constrained relative to x86's
7397 // actual model.
7398 SDValue VSELECTMask[32];
7399 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7400 for (int j = 0; j < Scale; ++j)
7401 VSELECTMask[Scale * i + j] =
7402 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7403 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8);
7405 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7406 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7407 return DAG.getNode(
7408 ISD::BITCAST, DL, VT,
7409 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8,
7410 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, VSELECTMask),
7411 V1, V2));
7412 }
7414 default:
7415 llvm_unreachable("Not a supported integer vector type!");
7416 }
7417 }
7419 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7420 /// unblended shuffles followed by an unshuffled blend.
7421 ///
7422 /// This matches the extremely common pattern for handling combined
7423 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7424 /// operations.
7425 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7426 SDValue V1,
7427 SDValue V2,
7428 ArrayRef<int> Mask,
7429 SelectionDAG &DAG) {
7430 // Shuffle the input elements into the desired positions in V1 and V2 and
7431 // blend them together.
7432 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7433 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7434 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7435 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7436 if (Mask[i] >= 0 && Mask[i] < Size) {
7437 V1Mask[i] = Mask[i];
7438 BlendMask[i] = i;
7439 } else if (Mask[i] >= Size) {
7440 V2Mask[i] = Mask[i] - Size;
7441 BlendMask[i] = i + Size;
7442 }
7444 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7445 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7446 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7447 }
7449 /// \brief Try to lower a vector shuffle as a byte rotation.
7450 ///
7451 /// We have a generic PALIGNR instruction in x86 that will do an arbitrary
7452 /// byte-rotation of a the concatentation of two vectors. This routine will
7453 /// try to generically lower a vector shuffle through such an instruction. It
7454 /// does not check for the availability of PALIGNR-based lowerings, only the
7455 /// applicability of this strategy to the given mask. This matches shuffle
7456 /// vectors that look like:
7457 ///
7458 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7459 ///
7460 /// Essentially it concatenates V1 and V2, shifts right by some number of
7461 /// elements, and takes the low elements as the result. Note that while this is
7462 /// specified as a *right shift* because x86 is little-endian, it is a *left
7463 /// rotate* of the vector lanes.
7464 ///
7465 /// Note that this only handles 128-bit vector widths currently.
7466 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7467 SDValue V2,
7468 ArrayRef<int> Mask,
7469 SelectionDAG &DAG) {
7470 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7472 // We need to detect various ways of spelling a rotation:
7473 // [11, 12, 13, 14, 15, 0, 1, 2]
7474 // [-1, 12, 13, 14, -1, -1, 1, -1]
7475 // [-1, -1, -1, -1, -1, -1, 1, 2]
7476 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7477 // [-1, 4, 5, 6, -1, -1, 9, -1]
7478 // [-1, 4, 5, 6, -1, -1, -1, -1]
7479 int Rotation = 0;
7480 SDValue Lo, Hi;
7481 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7482 if (Mask[i] == -1)
7483 continue;
7484 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7486 // Based on the mod-Size value of this mask element determine where
7487 // a rotated vector would have started.
7488 int StartIdx = i - (Mask[i] % Size);
7489 if (StartIdx == 0)
7490 // The identity rotation isn't interesting, stop.
7491 return SDValue();
7493 // If we found the tail of a vector the rotation must be the missing
7494 // front. If we found the head of a vector, it must be how much of the head.
7495 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7497 if (Rotation == 0)
7498 Rotation = CandidateRotation;
7499 else if (Rotation != CandidateRotation)
7500 // The rotations don't match, so we can't match this mask.
7501 return SDValue();
7503 // Compute which value this mask is pointing at.
7504 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7506 // Compute which of the two target values this index should be assigned to.
7507 // This reflects whether the high elements are remaining or the low elements
7508 // are remaining.
7509 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7511 // Either set up this value if we've not encountered it before, or check
7512 // that it remains consistent.
7513 if (!TargetV)
7514 TargetV = MaskV;
7515 else if (TargetV != MaskV)
7516 // This may be a rotation, but it pulls from the inputs in some
7517 // unsupported interleaving.
7518 return SDValue();
7519 }
7521 // Check that we successfully analyzed the mask, and normalize the results.
7522 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7523 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7524 if (!Lo)
7525 Lo = Hi;
7526 else if (!Hi)
7527 Hi = Lo;
7529 // Cast the inputs to v16i8 to match PALIGNR.
7530 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7531 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7533 assert(VT.getSizeInBits() == 128 &&
7534 "Rotate-based lowering only supports 128-bit lowering!");
7535 assert(Mask.size() <= 16 &&
7536 "Can shuffle at most 16 bytes in a 128-bit vector!");
7537 // The actual rotate instruction rotates bytes, so we need to scale the
7538 // rotation based on how many bytes are in the vector.
7539 int Scale = 16 / Mask.size();
7541 return DAG.getNode(ISD::BITCAST, DL, VT,
7542 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7543 DAG.getConstant(Rotation * Scale, MVT::i8)));
7544 }
7546 /// \brief Compute whether each element of a shuffle is zeroable.
7547 ///
7548 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7549 /// Either it is an undef element in the shuffle mask, the element of the input
7550 /// referenced is undef, or the element of the input referenced is known to be
7551 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7552 /// as many lanes with this technique as possible to simplify the remaining
7553 /// shuffle.
7554 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7555 SDValue V1, SDValue V2) {
7556 SmallBitVector Zeroable(Mask.size(), false);
7558 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7559 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7561 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7562 int M = Mask[i];
7563 // Handle the easy cases.
7564 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7565 Zeroable[i] = true;
7566 continue;
7567 }
7569 // If this is an index into a build_vector node, dig out the input value and
7570 // use it.
7571 SDValue V = M < Size ? V1 : V2;
7572 if (V.getOpcode() != ISD::BUILD_VECTOR)
7573 continue;
7575 SDValue Input = V.getOperand(M % Size);
7576 // The UNDEF opcode check really should be dead code here, but not quite
7577 // worth asserting on (it isn't invalid, just unexpected).
7578 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7579 Zeroable[i] = true;
7580 }
7582 return Zeroable;
7583 }
7585 /// \brief Lower a vector shuffle as a zero or any extension.
7586 ///
7587 /// Given a specific number of elements, element bit width, and extension
7588 /// stride, produce either a zero or any extension based on the available
7589 /// features of the subtarget.
7590 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7591 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7592 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7593 assert(Scale > 1 && "Need a scale to extend.");
7594 int EltBits = VT.getSizeInBits() / NumElements;
7595 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7596 "Only 8, 16, and 32 bit elements can be extended.");
7597 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7599 // Found a valid zext mask! Try various lowering strategies based on the
7600 // input type and available ISA extensions.
7601 if (Subtarget->hasSSE41()) {
7602 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7603 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7604 NumElements / Scale);
7605 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7606 return DAG.getNode(ISD::BITCAST, DL, VT,
7607 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7608 }
7610 // For any extends we can cheat for larger element sizes and use shuffle
7611 // instructions that can fold with a load and/or copy.
7612 if (AnyExt && EltBits == 32) {
7613 int PSHUFDMask[4] = {0, -1, 1, -1};
7614 return DAG.getNode(
7615 ISD::BITCAST, DL, VT,
7616 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7617 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7618 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7619 }
7620 if (AnyExt && EltBits == 16 && Scale > 2) {
7621 int PSHUFDMask[4] = {0, -1, 0, -1};
7622 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7623 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7624 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7625 int PSHUFHWMask[4] = {1, -1, -1, -1};
7626 return DAG.getNode(
7627 ISD::BITCAST, DL, VT,
7628 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7629 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7630 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7631 }
7633 // If this would require more than 2 unpack instructions to expand, use
7634 // pshufb when available. We can only use more than 2 unpack instructions
7635 // when zero extending i8 elements which also makes it easier to use pshufb.
7636 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7637 assert(NumElements == 16 && "Unexpected byte vector width!");
7638 SDValue PSHUFBMask[16];
7639 for (int i = 0; i < 16; ++i)
7640 PSHUFBMask[i] =
7641 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7642 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7643 return DAG.getNode(ISD::BITCAST, DL, VT,
7644 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7645 DAG.getNode(ISD::BUILD_VECTOR, DL,
7646 MVT::v16i8, PSHUFBMask)));
7647 }
7649 // Otherwise emit a sequence of unpacks.
7650 do {
7651 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7652 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7653 : getZeroVector(InputVT, Subtarget, DAG, DL);
7654 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7655 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7656 Scale /= 2;
7657 EltBits *= 2;
7658 NumElements /= 2;
7659 } while (Scale > 1);
7660 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7661 }
7663 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7664 ///
7665 /// This routine will try to do everything in its power to cleverly lower
7666 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7667 /// check for the profitability of this lowering, it tries to aggressively
7668 /// match this pattern. It will use all of the micro-architectural details it
7669 /// can to emit an efficient lowering. It handles both blends with all-zero
7670 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7671 /// masking out later).
7672 ///
7673 /// The reason we have dedicated lowering for zext-style shuffles is that they
7674 /// are both incredibly common and often quite performance sensitive.
7675 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7676 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7677 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7678 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7680 int Bits = VT.getSizeInBits();
7681 int NumElements = Mask.size();
7683 // Define a helper function to check a particular ext-scale and lower to it if
7684 // valid.
7685 auto Lower = [&](int Scale) -> SDValue {
7686 SDValue InputV;
7687 bool AnyExt = true;
7688 for (int i = 0; i < NumElements; ++i) {
7689 if (Mask[i] == -1)
7690 continue; // Valid anywhere but doesn't tell us anything.
7691 if (i % Scale != 0) {
7692 // Each of the extend elements needs to be zeroable.
7693 if (!Zeroable[i])
7694 return SDValue();
7696 // We no lorger are in the anyext case.
7697 AnyExt = false;
7698 continue;
7699 }
7701 // Each of the base elements needs to be consecutive indices into the
7702 // same input vector.
7703 SDValue V = Mask[i] < NumElements ? V1 : V2;
7704 if (!InputV)
7705 InputV = V;
7706 else if (InputV != V)
7707 return SDValue(); // Flip-flopping inputs.
7709 if (Mask[i] % NumElements != i / Scale)
7710 return SDValue(); // Non-consecutive strided elemenst.
7711 }
7713 // If we fail to find an input, we have a zero-shuffle which should always
7714 // have already been handled.
7715 // FIXME: Maybe handle this here in case during blending we end up with one?
7716 if (!InputV)
7717 return SDValue();
7719 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7720 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7721 };
7723 // The widest scale possible for extending is to a 64-bit integer.
7724 assert(Bits % 64 == 0 &&
7725 "The number of bits in a vector must be divisible by 64 on x86!");
7726 int NumExtElements = Bits / 64;
7728 // Each iteration, try extending the elements half as much, but into twice as
7729 // many elements.
7730 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7731 assert(NumElements % NumExtElements == 0 &&
7732 "The input vector size must be divisble by the extended size.");
7733 if (SDValue V = Lower(NumElements / NumExtElements))
7734 return V;
7735 }
7737 // No viable ext lowering found.
7738 return SDValue();
7739 }
7741 /// \brief Try to get a scalar value for a specific element of a vector.
7742 ///
7743 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7744 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7745 SelectionDAG &DAG) {
7746 MVT VT = V.getSimpleValueType();
7747 MVT EltVT = VT.getVectorElementType();
7748 while (V.getOpcode() == ISD::BITCAST)
7749 V = V.getOperand(0);
7750 // If the bitcasts shift the element size, we can't extract an equivalent
7751 // element from it.
7752 MVT NewVT = V.getSimpleValueType();
7753 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7754 return SDValue();
7756 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7757 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR))
7758 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, V.getOperand(Idx));
7760 return SDValue();
7761 }
7763 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7764 ///
7765 /// This is particularly important because the set of instructions varies
7766 /// significantly based on whether the operand is a load or not.
7767 static bool isShuffleFoldableLoad(SDValue V) {
7768 while (V.getOpcode() == ISD::BITCAST)
7769 V = V.getOperand(0);
7771 return ISD::isNON_EXTLoad(V.getNode());
7772 }
7774 /// \brief Try to lower insertion of a single element into a zero vector.
7775 ///
7776 /// This is a common pattern that we have especially efficient patterns to lower
7777 /// across all subtarget feature sets.
7778 static SDValue lowerVectorShuffleAsElementInsertion(
7779 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7780 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7781 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7783 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7784 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7785 Mask.begin();
7786 if (Mask.size() == 2) {
7787 if (!Zeroable[V2Index ^ 1]) {
7788 // For 2-wide masks we may be able to just invert the inputs. We use an xor
7789 // with 2 to flip from {2,3} to {0,1} and vice versa.
7790 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7791 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
7792 if (Zeroable[V2Index])
7793 return lowerVectorShuffleAsElementInsertion(VT, DL, V2, V1, InverseMask,
7794 Subtarget, DAG);
7795 else
7796 return SDValue();
7797 }
7798 } else {
7799 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7800 if (i != V2Index && !Zeroable[i])
7801 return SDValue(); // Not inserting into a zero vector.
7802 }
7804 MVT ExtVT = VT;
7805 MVT EltVT = VT.getVectorElementType();
7807 // Check for a single input from a SCALAR_TO_VECTOR node.
7808 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7809 // all the smarts here sunk into that routine. However, the current
7810 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7811 // vector shuffle lowering is dead.
7812 if (SDValue V2S = getScalarValueForVectorElement(
7813 V2, Mask[V2Index] - Mask.size(), DAG)) {
7814 // We need to zext the scalar if it is smaller than an i32.
7815 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7816 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7817 // Zero-extend directly to i32.
7818 ExtVT = MVT::v4i32;
7819 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7820 }
7821 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7822 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7823 EltVT == MVT::i16) {
7824 // Either not inserting from the low element of the input or the input
7825 // element size is too small to use VZEXT_MOVL to clear the high bits.
7826 return SDValue();
7827 }
7829 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7830 if (ExtVT != VT)
7831 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7833 if (V2Index != 0) {
7834 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7835 // the desired position. Otherwise it is more efficient to do a vector
7836 // shift left. We know that we can do a vector shift left because all
7837 // the inputs are zero.
7838 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7839 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7840 V2Shuffle[V2Index] = 0;
7841 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7842 } else {
7843 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
7844 V2 = DAG.getNode(
7845 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7846 DAG.getConstant(
7847 V2Index * EltVT.getSizeInBits(),
7848 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7849 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7850 }
7851 }
7852 return V2;
7853 }
7855 /// \brief Try to lower broadcast of a single element.
7856 ///
7857 /// For convenience, this code also bundles all of the subtarget feature set
7858 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7859 /// a convenient way to factor it out.
7860 static SDValue lowerVectorShuffleAsBroadcast(MVT VT, SDLoc DL, SDValue V,
7861 ArrayRef<int> Mask,
7862 const X86Subtarget *Subtarget,
7863 SelectionDAG &DAG) {
7864 if (!Subtarget->hasAVX())
7865 return SDValue();
7866 if (VT.isInteger() && !Subtarget->hasAVX2())
7867 return SDValue();
7869 // Check that the mask is a broadcast.
7870 int BroadcastIdx = -1;
7871 for (int M : Mask)
7872 if (M >= 0 && BroadcastIdx == -1)
7873 BroadcastIdx = M;
7874 else if (M >= 0 && M != BroadcastIdx)
7875 return SDValue();
7877 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7878 "a sorted mask where the broadcast "
7879 "comes from V1.");
7881 // Check if this is a broadcast of a scalar. We special case lowering for
7882 // scalars so that we can more effectively fold with loads.
7883 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7884 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7885 V = V.getOperand(BroadcastIdx);
7887 // If the scalar isn't a load we can't broadcast from it in AVX1, only with
7888 // AVX2.
7889 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7890 return SDValue();
7891 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7892 // We can't broadcast from a vector register w/o AVX2, and we can only
7893 // broadcast from the zero-element of a vector register.
7894 return SDValue();
7895 }
7897 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7898 }
7900 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7901 ///
7902 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7903 /// support for floating point shuffles but not integer shuffles. These
7904 /// instructions will incur a domain crossing penalty on some chips though so
7905 /// it is better to avoid lowering through this for integer vectors where
7906 /// possible.
7907 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7908 const X86Subtarget *Subtarget,
7909 SelectionDAG &DAG) {
7910 SDLoc DL(Op);
7911 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7912 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7913 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7914 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7915 ArrayRef<int> Mask = SVOp->getMask();
7916 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7918 if (isSingleInputShuffleMask(Mask)) {
7919 // Straight shuffle of a single input vector. Simulate this by using the
7920 // single input as both of the "inputs" to this instruction..
7921 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7923 if (Subtarget->hasAVX()) {
7924 // If we have AVX, we can use VPERMILPS which will allow folding a load
7925 // into the shuffle.
7926 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7927 DAG.getConstant(SHUFPDMask, MVT::i8));
7928 }
7930 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
7931 DAG.getConstant(SHUFPDMask, MVT::i8));
7932 }
7933 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7934 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7936 // Use dedicated unpack instructions for masks that match their pattern.
7937 if (isShuffleEquivalent(Mask, 0, 2))
7938 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7939 if (isShuffleEquivalent(Mask, 1, 3))
7940 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7942 // If we have a single input, insert that into V1 if we can do so cheaply.
7943 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1)
7944 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7945 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
7946 return Insertion;
7948 // Try to use one of the special instruction patterns to handle two common
7949 // blend patterns if a zero-blend above didn't work.
7950 if (isShuffleEquivalent(Mask, 0, 3) || isShuffleEquivalent(Mask, 1, 3))
7951 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
7952 // We can either use a special instruction to load over the low double or
7953 // to move just the low double.
7954 return DAG.getNode(
7955 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
7956 DL, MVT::v2f64, V2,
7957 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
7959 if (Subtarget->hasSSE41())
7960 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
7961 Subtarget, DAG))
7962 return Blend;
7964 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7965 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
7966 DAG.getConstant(SHUFPDMask, MVT::i8));
7967 }
7969 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7970 ///
7971 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7972 /// the integer unit to minimize domain crossing penalties. However, for blends
7973 /// it falls back to the floating point shuffle operation with appropriate bit
7974 /// casting.
7975 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7976 const X86Subtarget *Subtarget,
7977 SelectionDAG &DAG) {
7978 SDLoc DL(Op);
7979 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7980 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7981 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7982 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7983 ArrayRef<int> Mask = SVOp->getMask();
7984 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7986 if (isSingleInputShuffleMask(Mask)) {
7987 // Check for being able to broadcast a single element.
7988 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v2i64, DL, V1,
7989 Mask, Subtarget, DAG))
7990 return Broadcast;
7992 // Straight shuffle of a single input vector. For everything from SSE2
7993 // onward this has a single fast instruction with no scary immediates.
7994 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7995 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7996 int WidenedMask[4] = {
7997 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7998 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7999 return DAG.getNode(
8000 ISD::BITCAST, DL, MVT::v2i64,
8001 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
8002 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
8003 }
8005 // If we have a single input from V2 insert that into V1 if we can do so
8006 // cheaply.
8007 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1)
8008 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8009 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
8010 return Insertion;
8012 // Use dedicated unpack instructions for masks that match their pattern.
8013 if (isShuffleEquivalent(Mask, 0, 2))
8014 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8015 if (isShuffleEquivalent(Mask, 1, 3))
8016 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8018 if (Subtarget->hasSSE41())
8019 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8020 Subtarget, DAG))
8021 return Blend;
8023 // Try to use rotation instructions if available.
8024 if (Subtarget->hasSSSE3())
8025 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8026 DL, MVT::v2i64, V1, V2, Mask, DAG))
8027 return Rotate;
8029 // We implement this with SHUFPD which is pretty lame because it will likely
8030 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8031 // However, all the alternatives are still more cycles and newer chips don't
8032 // have this problem. It would be really nice if x86 had better shuffles here.
8033 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
8034 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
8035 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
8036 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8037 }
8039 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8040 ///
8041 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8042 /// It makes no assumptions about whether this is the *best* lowering, it simply
8043 /// uses it.
8044 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8045 ArrayRef<int> Mask, SDValue V1,
8046 SDValue V2, SelectionDAG &DAG) {
8047 SDValue LowV = V1, HighV = V2;
8048 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8050 int NumV2Elements =
8051 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8053 if (NumV2Elements == 1) {
8054 int V2Index =
8055 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8056 Mask.begin();
8058 // Compute the index adjacent to V2Index and in the same half by toggling
8059 // the low bit.
8060 int V2AdjIndex = V2Index ^ 1;
8062 if (Mask[V2AdjIndex] == -1) {
8063 // Handles all the cases where we have a single V2 element and an undef.
8064 // This will only ever happen in the high lanes because we commute the
8065 // vector otherwise.
8066 if (V2Index < 2)
8067 std::swap(LowV, HighV);
8068 NewMask[V2Index] -= 4;
8069 } else {
8070 // Handle the case where the V2 element ends up adjacent to a V1 element.
8071 // To make this work, blend them together as the first step.
8072 int V1Index = V2AdjIndex;
8073 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8074 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8075 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8077 // Now proceed to reconstruct the final blend as we have the necessary
8078 // high or low half formed.
8079 if (V2Index < 2) {
8080 LowV = V2;
8081 HighV = V1;
8082 } else {
8083 HighV = V2;
8084 }
8085 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8086 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8087 }
8088 } else if (NumV2Elements == 2) {
8089 if (Mask[0] < 4 && Mask[1] < 4) {
8090 // Handle the easy case where we have V1 in the low lanes and V2 in the
8091 // high lanes.
8092 NewMask[2] -= 4;
8093 NewMask[3] -= 4;
8094 } else if (Mask[2] < 4 && Mask[3] < 4) {
8095 // We also handle the reversed case because this utility may get called
8096 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8097 // arrange things in the right direction.
8098 NewMask[0] -= 4;
8099 NewMask[1] -= 4;
8100 HighV = V1;
8101 LowV = V2;
8102 } else {
8103 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8104 // trying to place elements directly, just blend them and set up the final
8105 // shuffle to place them.
8107 // The first two blend mask elements are for V1, the second two are for
8108 // V2.
8109 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8110 Mask[2] < 4 ? Mask[2] : Mask[3],
8111 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8112 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8113 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8114 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8116 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8117 // a blend.
8118 LowV = HighV = V1;
8119 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8120 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8121 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8122 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8123 }
8124 }
8125 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8126 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8127 }
8129 /// \brief Lower 4-lane 32-bit floating point shuffles.
8130 ///
8131 /// Uses instructions exclusively from the floating point unit to minimize
8132 /// domain crossing penalties, as these are sufficient to implement all v4f32
8133 /// shuffles.
8134 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8135 const X86Subtarget *Subtarget,
8136 SelectionDAG &DAG) {
8137 SDLoc DL(Op);
8138 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8139 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8140 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8141 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8142 ArrayRef<int> Mask = SVOp->getMask();
8143 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8145 int NumV2Elements =
8146 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8148 if (NumV2Elements == 0) {
8149 // Check for being able to broadcast a single element.
8150 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f32, DL, V1,
8151 Mask, Subtarget, DAG))
8152 return Broadcast;
8154 if (Subtarget->hasAVX()) {
8155 // If we have AVX, we can use VPERMILPS which will allow folding a load
8156 // into the shuffle.
8157 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8158 getV4X86ShuffleImm8ForMask(Mask, DAG));
8159 }
8161 // Otherwise, use a straight shuffle of a single input vector. We pass the
8162 // input vector to both operands to simulate this with a SHUFPS.
8163 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8164 getV4X86ShuffleImm8ForMask(Mask, DAG));
8165 }
8167 // Use dedicated unpack instructions for masks that match their pattern.
8168 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8169 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8170 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8171 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8173 // There are special ways we can lower some single-element blends. However, we
8174 // have custom ways we can lower more complex single-element blends below that
8175 // we defer to if both this and BLENDPS fail to match, so restrict this to
8176 // when the V2 input is targeting element 0 of the mask -- that is the fast
8177 // case here.
8178 if (NumV2Elements == 1 && Mask[0] >= 4)
8179 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8180 Mask, Subtarget, DAG))
8181 return V;
8183 if (Subtarget->hasSSE41())
8184 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8185 Subtarget, DAG))
8186 return Blend;
8188 // Check for whether we can use INSERTPS to perform the blend. We only use
8189 // INSERTPS when the V1 elements are already in the correct locations
8190 // because otherwise we can just always use two SHUFPS instructions which
8191 // are much smaller to encode than a SHUFPS and an INSERTPS.
8192 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
8193 int V2Index =
8194 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8195 Mask.begin();
8197 // When using INSERTPS we can zero any lane of the destination. Collect
8198 // the zero inputs into a mask and drop them from the lanes of V1 which
8199 // actually need to be present as inputs to the INSERTPS.
8200 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8202 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
8203 bool InsertNeedsShuffle = false;
8204 unsigned ZMask = 0;
8205 for (int i = 0; i < 4; ++i)
8206 if (i != V2Index) {
8207 if (Zeroable[i]) {
8208 ZMask |= 1 << i;
8209 } else if (Mask[i] != i) {
8210 InsertNeedsShuffle = true;
8211 break;
8212 }
8213 }
8215 // We don't want to use INSERTPS or other insertion techniques if it will
8216 // require shuffling anyways.
8217 if (!InsertNeedsShuffle) {
8218 // If all of V1 is zeroable, replace it with undef.
8219 if ((ZMask | 1 << V2Index) == 0xF)
8220 V1 = DAG.getUNDEF(MVT::v4f32);
8222 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
8223 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8225 // Insert the V2 element into the desired position.
8226 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8227 DAG.getConstant(InsertPSMask, MVT::i8));
8228 }
8229 }
8231 // Otherwise fall back to a SHUFPS lowering strategy.
8232 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8233 }
8235 /// \brief Lower 4-lane i32 vector shuffles.
8236 ///
8237 /// We try to handle these with integer-domain shuffles where we can, but for
8238 /// blends we use the floating point domain blend instructions.
8239 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8240 const X86Subtarget *Subtarget,
8241 SelectionDAG &DAG) {
8242 SDLoc DL(Op);
8243 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8244 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8245 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8246 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8247 ArrayRef<int> Mask = SVOp->getMask();
8248 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8250 // Whenever we can lower this as a zext, that instruction is strictly faster
8251 // than any alternative. It also allows us to fold memory operands into the
8252 // shuffle in many cases.
8253 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8254 Mask, Subtarget, DAG))
8255 return ZExt;
8257 int NumV2Elements =
8258 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8260 if (NumV2Elements == 0) {
8261 // Check for being able to broadcast a single element.
8262 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i32, DL, V1,
8263 Mask, Subtarget, DAG))
8264 return Broadcast;
8266 // Straight shuffle of a single input vector. For everything from SSE2
8267 // onward this has a single fast instruction with no scary immediates.
8268 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8269 // but we aren't actually going to use the UNPCK instruction because doing
8270 // so prevents folding a load into this instruction or making a copy.
8271 const int UnpackLoMask[] = {0, 0, 1, 1};
8272 const int UnpackHiMask[] = {2, 2, 3, 3};
8273 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8274 Mask = UnpackLoMask;
8275 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8276 Mask = UnpackHiMask;
8278 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8279 getV4X86ShuffleImm8ForMask(Mask, DAG));
8280 }
8282 // There are special ways we can lower some single-element blends.
8283 if (NumV2Elements == 1)
8284 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8285 Mask, Subtarget, DAG))
8286 return V;
8288 // Use dedicated unpack instructions for masks that match their pattern.
8289 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8290 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8291 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8292 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8294 if (Subtarget->hasSSE41())
8295 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8296 Subtarget, DAG))
8297 return Blend;
8299 // Try to use rotation instructions if available.
8300 if (Subtarget->hasSSSE3())
8301 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8302 DL, MVT::v4i32, V1, V2, Mask, DAG))
8303 return Rotate;
8305 // We implement this with SHUFPS because it can blend from two vectors.
8306 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8307 // up the inputs, bypassing domain shift penalties that we would encur if we
8308 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8309 // relevant.
8310 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8311 DAG.getVectorShuffle(
8312 MVT::v4f32, DL,
8313 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8314 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8315 }
8317 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8318 /// shuffle lowering, and the most complex part.
8319 ///
8320 /// The lowering strategy is to try to form pairs of input lanes which are
8321 /// targeted at the same half of the final vector, and then use a dword shuffle
8322 /// to place them onto the right half, and finally unpack the paired lanes into
8323 /// their final position.
8324 ///
8325 /// The exact breakdown of how to form these dword pairs and align them on the
8326 /// correct sides is really tricky. See the comments within the function for
8327 /// more of the details.
8328 static SDValue lowerV8I16SingleInputVectorShuffle(
8329 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8330 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8331 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8332 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8333 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8335 SmallVector<int, 4> LoInputs;
8336 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8337 [](int M) { return M >= 0; });
8338 std::sort(LoInputs.begin(), LoInputs.end());
8339 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8340 SmallVector<int, 4> HiInputs;
8341 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8342 [](int M) { return M >= 0; });
8343 std::sort(HiInputs.begin(), HiInputs.end());
8344 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8345 int NumLToL =
8346 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8347 int NumHToL = LoInputs.size() - NumLToL;
8348 int NumLToH =
8349 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8350 int NumHToH = HiInputs.size() - NumLToH;
8351 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8352 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8353 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8354 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8356 // Check for being able to broadcast a single element.
8357 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i16, DL, V,
8358 Mask, Subtarget, DAG))
8359 return Broadcast;
8361 // Use dedicated unpack instructions for masks that match their pattern.
8362 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8363 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8364 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8365 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8367 // Try to use rotation instructions if available.
8368 if (Subtarget->hasSSSE3())
8369 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8370 DL, MVT::v8i16, V, V, Mask, DAG))
8371 return Rotate;
8373 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8374 // such inputs we can swap two of the dwords across the half mark and end up
8375 // with <=2 inputs to each half in each half. Once there, we can fall through
8376 // to the generic code below. For example:
8377 //
8378 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8379 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8380 //
8381 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8382 // and an existing 2-into-2 on the other half. In this case we may have to
8383 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8384 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8385 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8386 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8387 // half than the one we target for fixing) will be fixed when we re-enter this
8388 // path. We will also combine away any sequence of PSHUFD instructions that
8389 // result into a single instruction. Here is an example of the tricky case:
8390 //
8391 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8392 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8393 //
8394 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8395 //
8396 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8397 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8398 //
8399 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8400 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8401 //
8402 // The result is fine to be handled by the generic logic.
8403 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8404 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8405 int AOffset, int BOffset) {
8406 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8407 "Must call this with A having 3 or 1 inputs from the A half.");
8408 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8409 "Must call this with B having 1 or 3 inputs from the B half.");
8410 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8411 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8413 // Compute the index of dword with only one word among the three inputs in
8414 // a half by taking the sum of the half with three inputs and subtracting
8415 // the sum of the actual three inputs. The difference is the remaining
8416 // slot.
8417 int ADWord, BDWord;
8418 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8419 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8420 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8421 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8422 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8423 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8424 int TripleNonInputIdx =
8425 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8426 TripleDWord = TripleNonInputIdx / 2;
8428 // We use xor with one to compute the adjacent DWord to whichever one the
8429 // OneInput is in.
8430 OneInputDWord = (OneInput / 2) ^ 1;
8432 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8433 // and BToA inputs. If there is also such a problem with the BToB and AToB
8434 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8435 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8436 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8437 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8438 // Compute how many inputs will be flipped by swapping these DWords. We
8439 // need
8440 // to balance this to ensure we don't form a 3-1 shuffle in the other
8441 // half.
8442 int NumFlippedAToBInputs =
8443 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8444 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8445 int NumFlippedBToBInputs =
8446 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8447 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8448 if ((NumFlippedAToBInputs == 1 &&
8449 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8450 (NumFlippedBToBInputs == 1 &&
8451 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8452 // We choose whether to fix the A half or B half based on whether that
8453 // half has zero flipped inputs. At zero, we may not be able to fix it
8454 // with that half. We also bias towards fixing the B half because that
8455 // will more commonly be the high half, and we have to bias one way.
8456 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8457 ArrayRef<int> Inputs) {
8458 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8459 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8460 PinnedIdx ^ 1) != Inputs.end();
8461 // Determine whether the free index is in the flipped dword or the
8462 // unflipped dword based on where the pinned index is. We use this bit
8463 // in an xor to conditionally select the adjacent dword.
8464 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8465 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8466 FixFreeIdx) != Inputs.end();
8467 if (IsFixIdxInput == IsFixFreeIdxInput)
8468 FixFreeIdx += 1;
8469 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8470 FixFreeIdx) != Inputs.end();
8471 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8472 "We need to be changing the number of flipped inputs!");
8473 int PSHUFHalfMask[] = {0, 1, 2, 3};
8474 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8475 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8476 MVT::v8i16, V,
8477 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8479 for (int &M : Mask)
8480 if (M != -1 && M == FixIdx)
8481 M = FixFreeIdx;
8482 else if (M != -1 && M == FixFreeIdx)
8483 M = FixIdx;
8484 };
8485 if (NumFlippedBToBInputs != 0) {
8486 int BPinnedIdx =
8487 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8488 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8489 } else {
8490 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8491 int APinnedIdx =
8492 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8493 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8494 }
8495 }
8496 }
8498 int PSHUFDMask[] = {0, 1, 2, 3};
8499 PSHUFDMask[ADWord] = BDWord;
8500 PSHUFDMask[BDWord] = ADWord;
8501 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8502 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8503 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8504 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8506 // Adjust the mask to match the new locations of A and B.
8507 for (int &M : Mask)
8508 if (M != -1 && M/2 == ADWord)
8509 M = 2 * BDWord + M % 2;
8510 else if (M != -1 && M/2 == BDWord)
8511 M = 2 * ADWord + M % 2;
8513 // Recurse back into this routine to re-compute state now that this isn't
8514 // a 3 and 1 problem.
8515 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8516 Mask);
8517 };
8518 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8519 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8520 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8521 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8523 // At this point there are at most two inputs to the low and high halves from
8524 // each half. That means the inputs can always be grouped into dwords and
8525 // those dwords can then be moved to the correct half with a dword shuffle.
8526 // We use at most one low and one high word shuffle to collect these paired
8527 // inputs into dwords, and finally a dword shuffle to place them.
8528 int PSHUFLMask[4] = {-1, -1, -1, -1};
8529 int PSHUFHMask[4] = {-1, -1, -1, -1};
8530 int PSHUFDMask[4] = {-1, -1, -1, -1};
8532 // First fix the masks for all the inputs that are staying in their
8533 // original halves. This will then dictate the targets of the cross-half
8534 // shuffles.
8535 auto fixInPlaceInputs =
8536 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8537 MutableArrayRef<int> SourceHalfMask,
8538 MutableArrayRef<int> HalfMask, int HalfOffset) {
8539 if (InPlaceInputs.empty())
8540 return;
8541 if (InPlaceInputs.size() == 1) {
8542 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8543 InPlaceInputs[0] - HalfOffset;
8544 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8545 return;
8546 }
8547 if (IncomingInputs.empty()) {
8548 // Just fix all of the in place inputs.
8549 for (int Input : InPlaceInputs) {
8550 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8551 PSHUFDMask[Input / 2] = Input / 2;
8552 }
8553 return;
8554 }
8556 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8557 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8558 InPlaceInputs[0] - HalfOffset;
8559 // Put the second input next to the first so that they are packed into
8560 // a dword. We find the adjacent index by toggling the low bit.
8561 int AdjIndex = InPlaceInputs[0] ^ 1;
8562 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8563 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8564 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8565 };
8566 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8567 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8569 // Now gather the cross-half inputs and place them into a free dword of
8570 // their target half.
8571 // FIXME: This operation could almost certainly be simplified dramatically to
8572 // look more like the 3-1 fixing operation.
8573 auto moveInputsToRightHalf = [&PSHUFDMask](
8574 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8575 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8576 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8577 int DestOffset) {
8578 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8579 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8580 };
8581 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8582 int Word) {
8583 int LowWord = Word & ~1;
8584 int HighWord = Word | 1;
8585 return isWordClobbered(SourceHalfMask, LowWord) ||
8586 isWordClobbered(SourceHalfMask, HighWord);
8587 };
8589 if (IncomingInputs.empty())
8590 return;
8592 if (ExistingInputs.empty()) {
8593 // Map any dwords with inputs from them into the right half.
8594 for (int Input : IncomingInputs) {
8595 // If the source half mask maps over the inputs, turn those into
8596 // swaps and use the swapped lane.
8597 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8598 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8599 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8600 Input - SourceOffset;
8601 // We have to swap the uses in our half mask in one sweep.
8602 for (int &M : HalfMask)
8603 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8604 M = Input;
8605 else if (M == Input)
8606 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8607 } else {
8608 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8609 Input - SourceOffset &&
8610 "Previous placement doesn't match!");
8611 }
8612 // Note that this correctly re-maps both when we do a swap and when
8613 // we observe the other side of the swap above. We rely on that to
8614 // avoid swapping the members of the input list directly.
8615 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8616 }
8618 // Map the input's dword into the correct half.
8619 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8620 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8621 else
8622 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8623 Input / 2 &&
8624 "Previous placement doesn't match!");
8625 }
8627 // And just directly shift any other-half mask elements to be same-half
8628 // as we will have mirrored the dword containing the element into the
8629 // same position within that half.
8630 for (int &M : HalfMask)
8631 if (M >= SourceOffset && M < SourceOffset + 4) {
8632 M = M - SourceOffset + DestOffset;
8633 assert(M >= 0 && "This should never wrap below zero!");
8634 }
8635 return;
8636 }
8638 // Ensure we have the input in a viable dword of its current half. This
8639 // is particularly tricky because the original position may be clobbered
8640 // by inputs being moved and *staying* in that half.
8641 if (IncomingInputs.size() == 1) {
8642 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8643 int InputFixed = std::find(std::begin(SourceHalfMask),
8644 std::end(SourceHalfMask), -1) -
8645 std::begin(SourceHalfMask) + SourceOffset;
8646 SourceHalfMask[InputFixed - SourceOffset] =
8647 IncomingInputs[0] - SourceOffset;
8648 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8649 InputFixed);
8650 IncomingInputs[0] = InputFixed;
8651 }
8652 } else if (IncomingInputs.size() == 2) {
8653 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8654 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8655 // We have two non-adjacent or clobbered inputs we need to extract from
8656 // the source half. To do this, we need to map them into some adjacent
8657 // dword slot in the source mask.
8658 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8659 IncomingInputs[1] - SourceOffset};
8661 // If there is a free slot in the source half mask adjacent to one of
8662 // the inputs, place the other input in it. We use (Index XOR 1) to
8663 // compute an adjacent index.
8664 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8665 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8666 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8667 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8668 InputsFixed[1] = InputsFixed[0] ^ 1;
8669 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8670 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8671 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8672 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8673 InputsFixed[0] = InputsFixed[1] ^ 1;
8674 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8675 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8676 // The two inputs are in the same DWord but it is clobbered and the
8677 // adjacent DWord isn't used at all. Move both inputs to the free
8678 // slot.
8679 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8680 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8681 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8682 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8683 } else {
8684 // The only way we hit this point is if there is no clobbering
8685 // (because there are no off-half inputs to this half) and there is no
8686 // free slot adjacent to one of the inputs. In this case, we have to
8687 // swap an input with a non-input.
8688 for (int i = 0; i < 4; ++i)
8689 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8690 "We can't handle any clobbers here!");
8691 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8692 "Cannot have adjacent inputs here!");
8694 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8695 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8697 // We also have to update the final source mask in this case because
8698 // it may need to undo the above swap.
8699 for (int &M : FinalSourceHalfMask)
8700 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8701 M = InputsFixed[1] + SourceOffset;
8702 else if (M == InputsFixed[1] + SourceOffset)
8703 M = (InputsFixed[0] ^ 1) + SourceOffset;
8705 InputsFixed[1] = InputsFixed[0] ^ 1;
8706 }
8708 // Point everything at the fixed inputs.
8709 for (int &M : HalfMask)
8710 if (M == IncomingInputs[0])
8711 M = InputsFixed[0] + SourceOffset;
8712 else if (M == IncomingInputs[1])
8713 M = InputsFixed[1] + SourceOffset;
8715 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8716 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8717 }
8718 } else {
8719 llvm_unreachable("Unhandled input size!");
8720 }
8722 // Now hoist the DWord down to the right half.
8723 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8724 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8725 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8726 for (int &M : HalfMask)
8727 for (int Input : IncomingInputs)
8728 if (M == Input)
8729 M = FreeDWord * 2 + Input % 2;
8730 };
8731 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8732 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8733 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8734 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8736 // Now enact all the shuffles we've computed to move the inputs into their
8737 // target half.
8738 if (!isNoopShuffleMask(PSHUFLMask))
8739 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8740 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8741 if (!isNoopShuffleMask(PSHUFHMask))
8742 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8743 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8744 if (!isNoopShuffleMask(PSHUFDMask))
8745 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8746 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8747 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8748 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8750 // At this point, each half should contain all its inputs, and we can then
8751 // just shuffle them into their final position.
8752 assert(std::count_if(LoMask.begin(), LoMask.end(),
8753 [](int M) { return M >= 4; }) == 0 &&
8754 "Failed to lift all the high half inputs to the low mask!");
8755 assert(std::count_if(HiMask.begin(), HiMask.end(),
8756 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8757 "Failed to lift all the low half inputs to the high mask!");
8759 // Do a half shuffle for the low mask.
8760 if (!isNoopShuffleMask(LoMask))
8761 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8762 getV4X86ShuffleImm8ForMask(LoMask, DAG));
8764 // Do a half shuffle with the high mask after shifting its values down.
8765 for (int &M : HiMask)
8766 if (M >= 0)
8767 M -= 4;
8768 if (!isNoopShuffleMask(HiMask))
8769 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8770 getV4X86ShuffleImm8ForMask(HiMask, DAG));
8772 return V;
8773 }
8775 /// \brief Detect whether the mask pattern should be lowered through
8776 /// interleaving.
8777 ///
8778 /// This essentially tests whether viewing the mask as an interleaving of two
8779 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
8780 /// lowering it through interleaving is a significantly better strategy.
8781 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
8782 int NumEvenInputs[2] = {0, 0};
8783 int NumOddInputs[2] = {0, 0};
8784 int NumLoInputs[2] = {0, 0};
8785 int NumHiInputs[2] = {0, 0};
8786 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
8787 if (Mask[i] < 0)
8788 continue;
8790 int InputIdx = Mask[i] >= Size;
8792 if (i < Size / 2)
8793 ++NumLoInputs[InputIdx];
8794 else
8795 ++NumHiInputs[InputIdx];
8797 if ((i % 2) == 0)
8798 ++NumEvenInputs[InputIdx];
8799 else
8800 ++NumOddInputs[InputIdx];
8801 }
8803 // The minimum number of cross-input results for both the interleaved and
8804 // split cases. If interleaving results in fewer cross-input results, return
8805 // true.
8806 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
8807 NumEvenInputs[0] + NumOddInputs[1]);
8808 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
8809 NumLoInputs[0] + NumHiInputs[1]);
8810 return InterleavedCrosses < SplitCrosses;
8811 }
8813 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
8814 ///
8815 /// This strategy only works when the inputs from each vector fit into a single
8816 /// half of that vector, and generally there are not so many inputs as to leave
8817 /// the in-place shuffles required highly constrained (and thus expensive). It
8818 /// shifts all the inputs into a single side of both input vectors and then
8819 /// uses an unpack to interleave these inputs in a single vector. At that
8820 /// point, we will fall back on the generic single input shuffle lowering.
8821 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
8822 SDValue V2,
8823 MutableArrayRef<int> Mask,
8824 const X86Subtarget *Subtarget,
8825 SelectionDAG &DAG) {
8826 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8827 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8828 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
8829 for (int i = 0; i < 8; ++i)
8830 if (Mask[i] >= 0 && Mask[i] < 4)
8831 LoV1Inputs.push_back(i);
8832 else if (Mask[i] >= 4 && Mask[i] < 8)
8833 HiV1Inputs.push_back(i);
8834 else if (Mask[i] >= 8 && Mask[i] < 12)
8835 LoV2Inputs.push_back(i);
8836 else if (Mask[i] >= 12)
8837 HiV2Inputs.push_back(i);
8839 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
8840 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
8841 (void)NumV1Inputs;
8842 (void)NumV2Inputs;
8843 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
8844 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
8845 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
8847 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
8848 HiV1Inputs.size() + HiV2Inputs.size();
8850 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
8851 ArrayRef<int> HiInputs, bool MoveToLo,
8852 int MaskOffset) {
8853 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
8854 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
8855 if (BadInputs.empty())
8856 return V;
8858 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8859 int MoveOffset = MoveToLo ? 0 : 4;
8861 if (GoodInputs.empty()) {
8862 for (int BadInput : BadInputs) {
8863 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
8864 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
8865 }
8866 } else {
8867 if (GoodInputs.size() == 2) {
8868 // If the low inputs are spread across two dwords, pack them into
8869 // a single dword.
8870 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
8871 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
8872 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
8873 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
8874 } else {
8875 // Otherwise pin the good inputs.
8876 for (int GoodInput : GoodInputs)
8877 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
8878 }
8880 if (BadInputs.size() == 2) {
8881 // If we have two bad inputs then there may be either one or two good
8882 // inputs fixed in place. Find a fixed input, and then find the *other*
8883 // two adjacent indices by using modular arithmetic.
8884 int GoodMaskIdx =
8885 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
8886 [](int M) { return M >= 0; }) -
8887 std::begin(MoveMask);
8888 int MoveMaskIdx =
8889 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
8890 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
8891 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
8892 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8893 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
8894 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8895 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
8896 } else {
8897 assert(BadInputs.size() == 1 && "All sizes handled");
8898 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
8899 std::end(MoveMask), -1) -
8900 std::begin(MoveMask);
8901 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8902 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8903 }
8904 }
8906 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8907 MoveMask);
8908 };
8909 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
8910 /*MaskOffset*/ 0);
8911 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
8912 /*MaskOffset*/ 8);
8914 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
8915 // cross-half traffic in the final shuffle.
8917 // Munge the mask to be a single-input mask after the unpack merges the
8918 // results.
8919 for (int &M : Mask)
8920 if (M != -1)
8921 M = 2 * (M % 4) + (M / 8);
8923 return DAG.getVectorShuffle(
8924 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
8925 DL, MVT::v8i16, V1, V2),
8926 DAG.getUNDEF(MVT::v8i16), Mask);
8927 }
8929 /// \brief Generic lowering of 8-lane i16 shuffles.
8930 ///
8931 /// This handles both single-input shuffles and combined shuffle/blends with
8932 /// two inputs. The single input shuffles are immediately delegated to
8933 /// a dedicated lowering routine.
8934 ///
8935 /// The blends are lowered in one of three fundamental ways. If there are few
8936 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8937 /// of the input is significantly cheaper when lowered as an interleaving of
8938 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8939 /// halves of the inputs separately (making them have relatively few inputs)
8940 /// and then concatenate them.
8941 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8942 const X86Subtarget *Subtarget,
8943 SelectionDAG &DAG) {
8944 SDLoc DL(Op);
8945 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8946 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8947 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8948 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8949 ArrayRef<int> OrigMask = SVOp->getMask();
8950 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8951 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8952 MutableArrayRef<int> Mask(MaskStorage);
8954 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8956 // Whenever we can lower this as a zext, that instruction is strictly faster
8957 // than any alternative.
8958 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8959 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
8960 return ZExt;
8962 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8963 auto isV2 = [](int M) { return M >= 8; };
8965 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
8966 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
8968 if (NumV2Inputs == 0)
8969 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
8971 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
8972 "to be V1-input shuffles.");
8974 // There are special ways we can lower some single-element blends.
8975 if (NumV2Inputs == 1)
8976 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
8977 Mask, Subtarget, DAG))
8978 return V;
8980 if (Subtarget->hasSSE41())
8981 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
8982 Subtarget, DAG))
8983 return Blend;
8985 // Try to use rotation instructions if available.
8986 if (Subtarget->hasSSSE3())
8987 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V2, Mask, DAG))
8988 return Rotate;
8990 if (NumV1Inputs + NumV2Inputs <= 4)
8991 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
8993 // Check whether an interleaving lowering is likely to be more efficient.
8994 // This isn't perfect but it is a strong heuristic that tends to work well on
8995 // the kinds of shuffles that show up in practice.
8996 //
8997 // FIXME: Handle 1x, 2x, and 4x interleaving.
8998 if (shouldLowerAsInterleaving(Mask)) {
8999 // FIXME: Figure out whether we should pack these into the low or high
9000 // halves.
9002 int EMask[8], OMask[8];
9003 for (int i = 0; i < 4; ++i) {
9004 EMask[i] = Mask[2*i];
9005 OMask[i] = Mask[2*i + 1];
9006 EMask[i + 4] = -1;
9007 OMask[i + 4] = -1;
9008 }
9010 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
9011 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
9013 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
9014 }
9016 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9017 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9019 for (int i = 0; i < 4; ++i) {
9020 LoBlendMask[i] = Mask[i];
9021 HiBlendMask[i] = Mask[i + 4];
9022 }
9024 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9025 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9026 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
9027 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
9029 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9030 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
9031 }
9033 /// \brief Check whether a compaction lowering can be done by dropping even
9034 /// elements and compute how many times even elements must be dropped.
9035 ///
9036 /// This handles shuffles which take every Nth element where N is a power of
9037 /// two. Example shuffle masks:
9038 ///
9039 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9040 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9041 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9042 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9043 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9044 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9045 ///
9046 /// Any of these lanes can of course be undef.
9047 ///
9048 /// This routine only supports N <= 3.
9049 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9050 /// for larger N.
9051 ///
9052 /// \returns N above, or the number of times even elements must be dropped if
9053 /// there is such a number. Otherwise returns zero.
9054 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9055 // Figure out whether we're looping over two inputs or just one.
9056 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9058 // The modulus for the shuffle vector entries is based on whether this is
9059 // a single input or not.
9060 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9061 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9062 "We should only be called with masks with a power-of-2 size!");
9064 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9066 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9067 // and 2^3 simultaneously. This is because we may have ambiguity with
9068 // partially undef inputs.
9069 bool ViableForN[3] = {true, true, true};
9071 for (int i = 0, e = Mask.size(); i < e; ++i) {
9072 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9073 // want.
9074 if (Mask[i] == -1)
9075 continue;
9077 bool IsAnyViable = false;
9078 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9079 if (ViableForN[j]) {
9080 uint64_t N = j + 1;
9082 // The shuffle mask must be equal to (i * 2^N) % M.
9083 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9084 IsAnyViable = true;
9085 else
9086 ViableForN[j] = false;
9087 }
9088 // Early exit if we exhaust the possible powers of two.
9089 if (!IsAnyViable)
9090 break;
9091 }
9093 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9094 if (ViableForN[j])
9095 return j + 1;
9097 // Return 0 as there is no viable power of two.
9098 return 0;
9099 }
9101 /// \brief Generic lowering of v16i8 shuffles.
9102 ///
9103 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9104 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9105 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9106 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9107 /// back together.
9108 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9109 const X86Subtarget *Subtarget,
9110 SelectionDAG &DAG) {
9111 SDLoc DL(Op);
9112 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9113 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9114 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9115 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9116 ArrayRef<int> OrigMask = SVOp->getMask();
9117 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9119 // Try to use rotation instructions if available.
9120 if (Subtarget->hasSSSE3())
9121 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v16i8, V1, V2,
9122 OrigMask, DAG))
9123 return Rotate;
9125 // Try to use a zext lowering.
9126 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9127 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9128 return ZExt;
9130 int MaskStorage[16] = {
9131 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9132 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9133 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9134 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9135 MutableArrayRef<int> Mask(MaskStorage);
9136 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9137 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9139 int NumV2Elements =
9140 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9142 // For single-input shuffles, there are some nicer lowering tricks we can use.
9143 if (NumV2Elements == 0) {
9144 // Check for being able to broadcast a single element.
9145 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i8, DL, V1,
9146 Mask, Subtarget, DAG))
9147 return Broadcast;
9149 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9150 // Notably, this handles splat and partial-splat shuffles more efficiently.
9151 // However, it only makes sense if the pre-duplication shuffle simplifies
9152 // things significantly. Currently, this means we need to be able to
9153 // express the pre-duplication shuffle as an i16 shuffle.
9154 //
9155 // FIXME: We should check for other patterns which can be widened into an
9156 // i16 shuffle as well.
9157 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9158 for (int i = 0; i < 16; i += 2)
9159 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9160 return false;
9162 return true;
9163 };
9164 auto tryToWidenViaDuplication = [&]() -> SDValue {
9165 if (!canWidenViaDuplication(Mask))
9166 return SDValue();
9167 SmallVector<int, 4> LoInputs;
9168 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9169 [](int M) { return M >= 0 && M < 8; });
9170 std::sort(LoInputs.begin(), LoInputs.end());
9171 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9172 LoInputs.end());
9173 SmallVector<int, 4> HiInputs;
9174 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9175 [](int M) { return M >= 8; });
9176 std::sort(HiInputs.begin(), HiInputs.end());
9177 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9178 HiInputs.end());
9180 bool TargetLo = LoInputs.size() >= HiInputs.size();
9181 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9182 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9184 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9185 SmallDenseMap<int, int, 8> LaneMap;
9186 for (int I : InPlaceInputs) {
9187 PreDupI16Shuffle[I/2] = I/2;
9188 LaneMap[I] = I;
9189 }
9190 int j = TargetLo ? 0 : 4, je = j + 4;
9191 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9192 // Check if j is already a shuffle of this input. This happens when
9193 // there are two adjacent bytes after we move the low one.
9194 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9195 // If we haven't yet mapped the input, search for a slot into which
9196 // we can map it.
9197 while (j < je && PreDupI16Shuffle[j] != -1)
9198 ++j;
9200 if (j == je)
9201 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9202 return SDValue();
9204 // Map this input with the i16 shuffle.
9205 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9206 }
9208 // Update the lane map based on the mapping we ended up with.
9209 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9210 }
9211 V1 = DAG.getNode(
9212 ISD::BITCAST, DL, MVT::v16i8,
9213 DAG.getVectorShuffle(MVT::v8i16, DL,
9214 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9215 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9217 // Unpack the bytes to form the i16s that will be shuffled into place.
9218 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9219 MVT::v16i8, V1, V1);
9221 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9222 for (int i = 0; i < 16; ++i)
9223 if (Mask[i] != -1) {
9224 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9225 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9226 if (PostDupI16Shuffle[i / 2] == -1)
9227 PostDupI16Shuffle[i / 2] = MappedMask;
9228 else
9229 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9230 "Conflicting entrties in the original shuffle!");
9231 }
9232 return DAG.getNode(
9233 ISD::BITCAST, DL, MVT::v16i8,
9234 DAG.getVectorShuffle(MVT::v8i16, DL,
9235 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9236 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9237 };
9238 if (SDValue V = tryToWidenViaDuplication())
9239 return V;
9240 }
9242 // Check whether an interleaving lowering is likely to be more efficient.
9243 // This isn't perfect but it is a strong heuristic that tends to work well on
9244 // the kinds of shuffles that show up in practice.
9245 //
9246 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9247 if (shouldLowerAsInterleaving(Mask)) {
9248 // FIXME: Figure out whether we should pack these into the low or high
9249 // halves.
9251 int EMask[16], OMask[16];
9252 for (int i = 0; i < 8; ++i) {
9253 EMask[i] = Mask[2*i];
9254 OMask[i] = Mask[2*i + 1];
9255 EMask[i + 8] = -1;
9256 OMask[i + 8] = -1;
9257 }
9259 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9260 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9262 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, Evens, Odds);
9263 }
9265 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9266 // with PSHUFB. It is important to do this before we attempt to generate any
9267 // blends but after all of the single-input lowerings. If the single input
9268 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9269 // want to preserve that and we can DAG combine any longer sequences into
9270 // a PSHUFB in the end. But once we start blending from multiple inputs,
9271 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9272 // and there are *very* few patterns that would actually be faster than the
9273 // PSHUFB approach because of its ability to zero lanes.
9274 //
9275 // FIXME: The only exceptions to the above are blends which are exact
9276 // interleavings with direct instructions supporting them. We currently don't
9277 // handle those well here.
9278 if (Subtarget->hasSSSE3()) {
9279 SDValue V1Mask[16];
9280 SDValue V2Mask[16];
9281 for (int i = 0; i < 16; ++i)
9282 if (Mask[i] == -1) {
9283 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9284 } else {
9285 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9286 V2Mask[i] =
9287 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9288 }
9289 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9290 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9291 if (isSingleInputShuffleMask(Mask))
9292 return V1; // Single inputs are easy.
9294 // Otherwise, blend the two.
9295 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9296 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9297 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9298 }
9300 // There are special ways we can lower some single-element blends.
9301 if (NumV2Elements == 1)
9302 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9303 Mask, Subtarget, DAG))
9304 return V;
9306 // Check whether a compaction lowering can be done. This handles shuffles
9307 // which take every Nth element for some even N. See the helper function for
9308 // details.
9309 //
9310 // We special case these as they can be particularly efficiently handled with
9311 // the PACKUSB instruction on x86 and they show up in common patterns of
9312 // rearranging bytes to truncate wide elements.
9313 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9314 // NumEvenDrops is the power of two stride of the elements. Another way of
9315 // thinking about it is that we need to drop the even elements this many
9316 // times to get the original input.
9317 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9319 // First we need to zero all the dropped bytes.
9320 assert(NumEvenDrops <= 3 &&
9321 "No support for dropping even elements more than 3 times.");
9322 // We use the mask type to pick which bytes are preserved based on how many
9323 // elements are dropped.
9324 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9325 SDValue ByteClearMask =
9326 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9327 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9328 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9329 if (!IsSingleInput)
9330 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9332 // Now pack things back together.
9333 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9334 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9335 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9336 for (int i = 1; i < NumEvenDrops; ++i) {
9337 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9338 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9339 }
9341 return Result;
9342 }
9344 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9345 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9346 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9347 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9349 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9350 MutableArrayRef<int> V1HalfBlendMask,
9351 MutableArrayRef<int> V2HalfBlendMask) {
9352 for (int i = 0; i < 8; ++i)
9353 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9354 V1HalfBlendMask[i] = HalfMask[i];
9355 HalfMask[i] = i;
9356 } else if (HalfMask[i] >= 16) {
9357 V2HalfBlendMask[i] = HalfMask[i] - 16;
9358 HalfMask[i] = i + 8;
9359 }
9360 };
9361 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9362 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9364 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9366 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9367 MutableArrayRef<int> HiBlendMask) {
9368 SDValue V1, V2;
9369 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9370 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9371 // i16s.
9372 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9373 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9374 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9375 [](int M) { return M >= 0 && M % 2 == 1; })) {
9376 // Use a mask to drop the high bytes.
9377 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9378 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9379 DAG.getConstant(0x00FF, MVT::v8i16));
9381 // This will be a single vector shuffle instead of a blend so nuke V2.
9382 V2 = DAG.getUNDEF(MVT::v8i16);
9384 // Squash the masks to point directly into V1.
9385 for (int &M : LoBlendMask)
9386 if (M >= 0)
9387 M /= 2;
9388 for (int &M : HiBlendMask)
9389 if (M >= 0)
9390 M /= 2;
9391 } else {
9392 // Otherwise just unpack the low half of V into V1 and the high half into
9393 // V2 so that we can blend them as i16s.
9394 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9395 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9396 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9397 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9398 }
9400 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9401 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9402 return std::make_pair(BlendedLo, BlendedHi);
9403 };
9404 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9405 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9406 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9408 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9409 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9411 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9412 }
9414 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9415 ///
9416 /// This routine breaks down the specific type of 128-bit shuffle and
9417 /// dispatches to the lowering routines accordingly.
9418 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9419 MVT VT, const X86Subtarget *Subtarget,
9420 SelectionDAG &DAG) {
9421 switch (VT.SimpleTy) {
9422 case MVT::v2i64:
9423 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9424 case MVT::v2f64:
9425 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9426 case MVT::v4i32:
9427 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9428 case MVT::v4f32:
9429 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9430 case MVT::v8i16:
9431 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9432 case MVT::v16i8:
9433 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9435 default:
9436 llvm_unreachable("Unimplemented!");
9437 }
9438 }
9440 /// \brief Generic routine to split ector shuffle into half-sized shuffles.
9441 ///
9442 /// This routine just extracts two subvectors, shuffles them independently, and
9443 /// then concatenates them back together. This should work effectively with all
9444 /// AVX vector shuffle types.
9445 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9446 SDValue V2, ArrayRef<int> Mask,
9447 SelectionDAG &DAG) {
9448 assert(VT.getSizeInBits() >= 256 &&
9449 "Only for 256-bit or wider vector shuffles!");
9450 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9451 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9453 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9454 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9456 int NumElements = VT.getVectorNumElements();
9457 int SplitNumElements = NumElements / 2;
9458 MVT ScalarVT = VT.getScalarType();
9459 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9461 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9462 DAG.getIntPtrConstant(0));
9463 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9464 DAG.getIntPtrConstant(SplitNumElements));
9465 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9466 DAG.getIntPtrConstant(0));
9467 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9468 DAG.getIntPtrConstant(SplitNumElements));
9470 // Now create two 4-way blends of these half-width vectors.
9471 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9472 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9473 for (int i = 0; i < SplitNumElements; ++i) {
9474 int M = HalfMask[i];
9475 if (M >= NumElements) {
9476 V2BlendMask.push_back(M - NumElements);
9477 V1BlendMask.push_back(-1);
9478 BlendMask.push_back(SplitNumElements + i);
9479 } else if (M >= 0) {
9480 V2BlendMask.push_back(-1);
9481 V1BlendMask.push_back(M);
9482 BlendMask.push_back(i);
9483 } else {
9484 V2BlendMask.push_back(-1);
9485 V1BlendMask.push_back(-1);
9486 BlendMask.push_back(-1);
9487 }
9488 }
9489 SDValue V1Blend =
9490 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9491 SDValue V2Blend =
9492 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9493 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9494 };
9495 SDValue Lo = HalfBlend(LoMask);
9496 SDValue Hi = HalfBlend(HiMask);
9497 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9498 }
9500 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9501 /// a permutation and blend of those lanes.
9502 ///
9503 /// This essentially blends the out-of-lane inputs to each lane into the lane
9504 /// from a permuted copy of the vector. This lowering strategy results in four
9505 /// instructions in the worst case for a single-input cross lane shuffle which
9506 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9507 /// of. Special cases for each particular shuffle pattern should be handled
9508 /// prior to trying this lowering.
9509 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9510 SDValue V1, SDValue V2,
9511 ArrayRef<int> Mask,
9512 SelectionDAG &DAG) {
9513 // FIXME: This should probably be generalized for 512-bit vectors as well.
9514 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9515 int LaneSize = Mask.size() / 2;
9517 // If there are only inputs from one 128-bit lane, splitting will in fact be
9518 // less expensive. The flags track wether the given lane contains an element
9519 // that crosses to another lane.
9520 bool LaneCrossing[2] = {false, false};
9521 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9522 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9523 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9524 if (!LaneCrossing[0] || !LaneCrossing[1])
9525 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9527 if (isSingleInputShuffleMask(Mask)) {
9528 SmallVector<int, 32> FlippedBlendMask;
9529 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9530 FlippedBlendMask.push_back(
9531 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9532 ? Mask[i]
9533 : Mask[i] % LaneSize +
9534 (i / LaneSize) * LaneSize + Size));
9536 // Flip the vector, and blend the results which should now be in-lane. The
9537 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9538 // 5 for the high source. The value 3 selects the high half of source 2 and
9539 // the value 2 selects the low half of source 2. We only use source 2 to
9540 // allow folding it into a memory operand.
9541 unsigned PERMMask = 3 | 2 << 4;
9542 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9543 V1, DAG.getConstant(PERMMask, MVT::i8));
9544 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9545 }
9547 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9548 // will be handled by the above logic and a blend of the results, much like
9549 // other patterns in AVX.
9550 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9551 }
9553 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9554 ///
9555 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9556 /// isn't available.
9557 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9558 const X86Subtarget *Subtarget,
9559 SelectionDAG &DAG) {
9560 SDLoc DL(Op);
9561 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9562 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9563 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9564 ArrayRef<int> Mask = SVOp->getMask();
9565 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9567 if (isSingleInputShuffleMask(Mask)) {
9568 // Check for being able to broadcast a single element.
9569 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f64, DL, V1,
9570 Mask, Subtarget, DAG))
9571 return Broadcast;
9573 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
9574 // Non-half-crossing single input shuffles can be lowerid with an
9575 // interleaved permutation.
9576 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9577 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9578 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9579 DAG.getConstant(VPERMILPMask, MVT::i8));
9580 }
9582 // With AVX2 we have direct support for this permutation.
9583 if (Subtarget->hasAVX2())
9584 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
9585 getV4X86ShuffleImm8ForMask(Mask, DAG));
9587 // Otherwise, fall back.
9588 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
9589 DAG);
9590 }
9592 // X86 has dedicated unpack instructions that can handle specific blend
9593 // operations: UNPCKH and UNPCKL.
9594 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9595 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9596 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9597 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9599 // If we have a single input to the zero element, insert that into V1 if we
9600 // can do so cheaply.
9601 int NumV2Elements =
9602 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
9603 if (NumV2Elements == 1 && Mask[0] >= 4)
9604 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
9605 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
9606 return Insertion;
9608 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
9609 Subtarget, DAG))
9610 return Blend;
9612 // Check if the blend happens to exactly fit that of SHUFPD.
9613 if ((Mask[0] == -1 || Mask[0] < 2) &&
9614 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
9615 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
9616 (Mask[3] == -1 || Mask[3] >= 6)) {
9617 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
9618 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
9619 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
9620 DAG.getConstant(SHUFPDMask, MVT::i8));
9621 }
9622 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
9623 (Mask[1] == -1 || Mask[1] < 2) &&
9624 (Mask[2] == -1 || Mask[2] >= 6) &&
9625 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
9626 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
9627 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
9628 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
9629 DAG.getConstant(SHUFPDMask, MVT::i8));
9630 }
9632 // Otherwise fall back on generic blend lowering.
9633 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
9634 Mask, DAG);
9635 }
9637 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9638 ///
9639 /// This routine is only called when we have AVX2 and thus a reasonable
9640 /// instruction set for v4i64 shuffling..
9641 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9642 const X86Subtarget *Subtarget,
9643 SelectionDAG &DAG) {
9644 SDLoc DL(Op);
9645 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9646 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9647 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9648 ArrayRef<int> Mask = SVOp->getMask();
9649 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9650 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9652 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
9653 Subtarget, DAG))
9654 return Blend;
9656 // Check for being able to broadcast a single element.
9657 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i64, DL, V1,
9658 Mask, Subtarget, DAG))
9659 return Broadcast;
9661 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
9662 // use lower latency instructions that will operate on both 128-bit lanes.
9663 SmallVector<int, 2> RepeatedMask;
9664 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
9665 if (isSingleInputShuffleMask(Mask)) {
9666 int PSHUFDMask[] = {-1, -1, -1, -1};
9667 for (int i = 0; i < 2; ++i)
9668 if (RepeatedMask[i] >= 0) {
9669 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
9670 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
9671 }
9672 return DAG.getNode(
9673 ISD::BITCAST, DL, MVT::v4i64,
9674 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
9675 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
9676 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
9677 }
9679 // Use dedicated unpack instructions for masks that match their pattern.
9680 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9681 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
9682 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9683 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
9684 }
9686 // AVX2 provides a direct instruction for permuting a single input across
9687 // lanes.
9688 if (isSingleInputShuffleMask(Mask))
9689 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
9690 getV4X86ShuffleImm8ForMask(Mask, DAG));
9692 // Otherwise fall back on generic blend lowering.
9693 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
9694 Mask, DAG);
9695 }
9697 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9698 ///
9699 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9700 /// isn't available.
9701 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9702 const X86Subtarget *Subtarget,
9703 SelectionDAG &DAG) {
9704 SDLoc DL(Op);
9705 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9706 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9707 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9708 ArrayRef<int> Mask = SVOp->getMask();
9709 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9711 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
9712 Subtarget, DAG))
9713 return Blend;
9715 // Check for being able to broadcast a single element.
9716 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8f32, DL, V1,
9717 Mask, Subtarget, DAG))
9718 return Broadcast;
9720 // If the shuffle mask is repeated in each 128-bit lane, we have many more
9721 // options to efficiently lower the shuffle.
9722 SmallVector<int, 4> RepeatedMask;
9723 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
9724 assert(RepeatedMask.size() == 4 &&
9725 "Repeated masks must be half the mask width!");
9726 if (isSingleInputShuffleMask(Mask))
9727 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
9728 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
9730 // Use dedicated unpack instructions for masks that match their pattern.
9731 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
9732 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
9733 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
9734 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
9736 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
9737 // have already handled any direct blends. We also need to squash the
9738 // repeated mask into a simulated v4f32 mask.
9739 for (int i = 0; i < 4; ++i)
9740 if (RepeatedMask[i] >= 8)
9741 RepeatedMask[i] -= 4;
9742 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
9743 }
9745 // If we have a single input shuffle with different shuffle patterns in the
9746 // two 128-bit lanes use the variable mask to VPERMILPS.
9747 if (isSingleInputShuffleMask(Mask)) {
9748 SDValue VPermMask[8];
9749 for (int i = 0; i < 8; ++i)
9750 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9751 : DAG.getConstant(Mask[i], MVT::i32);
9752 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
9753 return DAG.getNode(
9754 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
9755 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
9757 if (Subtarget->hasAVX2())
9758 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
9759 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
9760 DAG.getNode(ISD::BUILD_VECTOR, DL,
9761 MVT::v8i32, VPermMask)),
9762 V1);
9764 // Otherwise, fall back.
9765 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
9766 DAG);
9767 }
9769 // Otherwise fall back on generic blend lowering.
9770 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
9771 Mask, DAG);
9772 }
9774 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
9775 ///
9776 /// This routine is only called when we have AVX2 and thus a reasonable
9777 /// instruction set for v8i32 shuffling..
9778 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9779 const X86Subtarget *Subtarget,
9780 SelectionDAG &DAG) {
9781 SDLoc DL(Op);
9782 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9783 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9784 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9785 ArrayRef<int> Mask = SVOp->getMask();
9786 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9787 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
9789 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
9790 Subtarget, DAG))
9791 return Blend;
9793 // Check for being able to broadcast a single element.
9794 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i32, DL, V1,
9795 Mask, Subtarget, DAG))
9796 return Broadcast;
9798 // If the shuffle mask is repeated in each 128-bit lane we can use more
9799 // efficient instructions that mirror the shuffles across the two 128-bit
9800 // lanes.
9801 SmallVector<int, 4> RepeatedMask;
9802 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
9803 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
9804 if (isSingleInputShuffleMask(Mask))
9805 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
9806 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
9808 // Use dedicated unpack instructions for masks that match their pattern.
9809 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
9810 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
9811 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
9812 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
9813 }
9815 // If the shuffle patterns aren't repeated but it is a single input, directly
9816 // generate a cross-lane VPERMD instruction.
9817 if (isSingleInputShuffleMask(Mask)) {
9818 SDValue VPermMask[8];
9819 for (int i = 0; i < 8; ++i)
9820 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9821 : DAG.getConstant(Mask[i], MVT::i32);
9822 return DAG.getNode(
9823 X86ISD::VPERMV, DL, MVT::v8i32,
9824 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
9825 }
9827 // Otherwise fall back on generic blend lowering.
9828 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
9829 Mask, DAG);
9830 }
9832 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
9833 ///
9834 /// This routine is only called when we have AVX2 and thus a reasonable
9835 /// instruction set for v16i16 shuffling..
9836 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9837 const X86Subtarget *Subtarget,
9838 SelectionDAG &DAG) {
9839 SDLoc DL(Op);
9840 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9841 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9842 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9843 ArrayRef<int> Mask = SVOp->getMask();
9844 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9845 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
9847 // Check for being able to broadcast a single element.
9848 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i16, DL, V1,
9849 Mask, Subtarget, DAG))
9850 return Broadcast;
9852 // There are no generalized cross-lane shuffle operations available on i16
9853 // element types.
9854 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
9855 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
9856 Mask, DAG);
9858 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
9859 Subtarget, DAG))
9860 return Blend;
9862 // Use dedicated unpack instructions for masks that match their pattern.
9863 if (isShuffleEquivalent(Mask,
9864 // First 128-bit lane:
9865 0, 16, 1, 17, 2, 18, 3, 19,
9866 // Second 128-bit lane:
9867 8, 24, 9, 25, 10, 26, 11, 27))
9868 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
9869 if (isShuffleEquivalent(Mask,
9870 // First 128-bit lane:
9871 4, 20, 5, 21, 6, 22, 7, 23,
9872 // Second 128-bit lane:
9873 12, 28, 13, 29, 14, 30, 15, 31))
9874 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
9876 if (isSingleInputShuffleMask(Mask)) {
9877 SDValue PSHUFBMask[32];
9878 for (int i = 0; i < 16; ++i) {
9879 if (Mask[i] == -1) {
9880 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
9881 continue;
9882 }
9884 int M = i < 8 ? Mask[i] : Mask[i] - 8;
9885 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
9886 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
9887 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
9888 }
9889 return DAG.getNode(
9890 ISD::BITCAST, DL, MVT::v16i16,
9891 DAG.getNode(
9892 X86ISD::PSHUFB, DL, MVT::v32i8,
9893 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
9894 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
9895 }
9897 // Otherwise fall back on generic blend lowering.
9898 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i16, V1, V2,
9899 Mask, DAG);
9900 }
9902 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
9903 ///
9904 /// This routine is only called when we have AVX2 and thus a reasonable
9905 /// instruction set for v32i8 shuffling..
9906 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9907 const X86Subtarget *Subtarget,
9908 SelectionDAG &DAG) {
9909 SDLoc DL(Op);
9910 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9911 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9912 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9913 ArrayRef<int> Mask = SVOp->getMask();
9914 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
9915 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
9917 // Check for being able to broadcast a single element.
9918 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v32i8, DL, V1,
9919 Mask, Subtarget, DAG))
9920 return Broadcast;
9922 // There are no generalized cross-lane shuffle operations available on i8
9923 // element types.
9924 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
9925 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
9926 Mask, DAG);
9928 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
9929 Subtarget, DAG))
9930 return Blend;
9932 // Use dedicated unpack instructions for masks that match their pattern.
9933 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
9934 // 256-bit lanes.
9935 if (isShuffleEquivalent(
9936 Mask,
9937 // First 128-bit lane:
9938 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
9939 // Second 128-bit lane:
9940 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
9941 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
9942 if (isShuffleEquivalent(
9943 Mask,
9944 // First 128-bit lane:
9945 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
9946 // Second 128-bit lane:
9947 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
9948 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
9950 if (isSingleInputShuffleMask(Mask)) {
9951 SDValue PSHUFBMask[32];
9952 for (int i = 0; i < 32; ++i)
9953 PSHUFBMask[i] =
9954 Mask[i] < 0
9955 ? DAG.getUNDEF(MVT::i8)
9956 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
9958 return DAG.getNode(
9959 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
9960 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
9961 }
9963 // Otherwise fall back on generic blend lowering.
9964 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v32i8, V1, V2,
9965 Mask, DAG);
9966 }
9968 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
9969 ///
9970 /// This routine either breaks down the specific type of a 256-bit x86 vector
9971 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
9972 /// together based on the available instructions.
9973 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9974 MVT VT, const X86Subtarget *Subtarget,
9975 SelectionDAG &DAG) {
9976 SDLoc DL(Op);
9977 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9978 ArrayRef<int> Mask = SVOp->getMask();
9980 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
9981 // check for those subtargets here and avoid much of the subtarget querying in
9982 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
9983 // ability to manipulate a 256-bit vector with integer types. Since we'll use
9984 // floating point types there eventually, just immediately cast everything to
9985 // a float and operate entirely in that domain.
9986 if (VT.isInteger() && !Subtarget->hasAVX2()) {
9987 int ElementBits = VT.getScalarSizeInBits();
9988 if (ElementBits < 32)
9989 // No floating point type available, decompose into 128-bit vectors.
9990 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9992 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
9993 VT.getVectorNumElements());
9994 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
9995 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
9996 return DAG.getNode(ISD::BITCAST, DL, VT,
9997 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
9998 }
10000 switch (VT.SimpleTy) {
10001 case MVT::v4f64:
10002 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10003 case MVT::v4i64:
10004 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10005 case MVT::v8f32:
10006 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10007 case MVT::v8i32:
10008 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10009 case MVT::v16i16:
10010 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10011 case MVT::v32i8:
10012 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10014 default:
10015 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10016 }
10017 }
10019 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10020 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10021 const X86Subtarget *Subtarget,
10022 SelectionDAG &DAG) {
10023 SDLoc DL(Op);
10024 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10025 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10026 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10027 ArrayRef<int> Mask = SVOp->getMask();
10028 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10030 // FIXME: Implement direct support for this type!
10031 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10032 }
10034 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10035 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10036 const X86Subtarget *Subtarget,
10037 SelectionDAG &DAG) {
10038 SDLoc DL(Op);
10039 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10040 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10041 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10042 ArrayRef<int> Mask = SVOp->getMask();
10043 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10045 // FIXME: Implement direct support for this type!
10046 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10047 }
10049 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10050 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10051 const X86Subtarget *Subtarget,
10052 SelectionDAG &DAG) {
10053 SDLoc DL(Op);
10054 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10055 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10056 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10057 ArrayRef<int> Mask = SVOp->getMask();
10058 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10059 assert(Subtarget->hasDQI() && "We can only lower v8i64 with AVX-512-DQI");
10061 // FIXME: Implement direct support for this type!
10062 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10063 }
10065 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10066 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10067 const X86Subtarget *Subtarget,
10068 SelectionDAG &DAG) {
10069 SDLoc DL(Op);
10070 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10071 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10072 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10073 ArrayRef<int> Mask = SVOp->getMask();
10074 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10075 assert(Subtarget->hasDQI() && "We can only lower v16i32 with AVX-512-DQI!");
10077 // FIXME: Implement direct support for this type!
10078 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10079 }
10081 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10082 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10083 const X86Subtarget *Subtarget,
10084 SelectionDAG &DAG) {
10085 SDLoc DL(Op);
10086 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10087 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10088 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10089 ArrayRef<int> Mask = SVOp->getMask();
10090 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10091 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10093 // FIXME: Implement direct support for this type!
10094 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10095 }
10097 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10098 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10099 const X86Subtarget *Subtarget,
10100 SelectionDAG &DAG) {
10101 SDLoc DL(Op);
10102 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10103 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10104 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10105 ArrayRef<int> Mask = SVOp->getMask();
10106 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10107 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10109 // FIXME: Implement direct support for this type!
10110 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10111 }
10113 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10114 ///
10115 /// This routine either breaks down the specific type of a 512-bit x86 vector
10116 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10117 /// together based on the available instructions.
10118 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10119 MVT VT, const X86Subtarget *Subtarget,
10120 SelectionDAG &DAG) {
10121 SDLoc DL(Op);
10122 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10123 ArrayRef<int> Mask = SVOp->getMask();
10124 assert(Subtarget->hasAVX512() &&
10125 "Cannot lower 512-bit vectors w/ basic ISA!");
10127 // Dispatch to each element type for lowering. If we don't have supprot for
10128 // specific element type shuffles at 512 bits, immediately split them and
10129 // lower them. Each lowering routine of a given type is allowed to assume that
10130 // the requisite ISA extensions for that element type are available.
10131 switch (VT.SimpleTy) {
10132 case MVT::v8f64:
10133 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10134 case MVT::v16f32:
10135 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10136 case MVT::v8i64:
10137 if (Subtarget->hasDQI())
10138 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10139 break;
10140 case MVT::v16i32:
10141 if (Subtarget->hasDQI())
10142 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10143 break;
10144 case MVT::v32i16:
10145 if (Subtarget->hasBWI())
10146 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10147 break;
10148 case MVT::v64i8:
10149 if (Subtarget->hasBWI())
10150 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10151 break;
10153 default:
10154 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10155 }
10157 // Otherwise fall back on splitting.
10158 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10159 }
10161 /// \brief Helper function to test whether a shuffle mask could be
10162 /// simplified by widening the elements being shuffled.
10163 ///
10164 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
10165 /// leaves it in an unspecified state.
10166 ///
10167 /// NOTE: This must handle normal vector shuffle masks and *target* vector
10168 /// shuffle masks. The latter have the special property of a '-2' representing
10169 /// a zero-ed lane of a vector.
10170 static bool canWidenShuffleElements(ArrayRef<int> Mask,
10171 SmallVectorImpl<int> &WidenedMask) {
10172 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
10173 // If both elements are undef, its trivial.
10174 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
10175 WidenedMask.push_back(SM_SentinelUndef);
10176 continue;
10177 }
10179 // Check for an undef mask and a mask value properly aligned to fit with
10180 // a pair of values. If we find such a case, use the non-undef mask's value.
10181 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
10182 WidenedMask.push_back(Mask[i + 1] / 2);
10183 continue;
10184 }
10185 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
10186 WidenedMask.push_back(Mask[i] / 2);
10187 continue;
10188 }
10190 // When zeroing, we need to spread the zeroing across both lanes to widen.
10191 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
10192 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
10193 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
10194 WidenedMask.push_back(SM_SentinelZero);
10195 continue;
10196 }
10197 return false;
10198 }
10200 // Finally check if the two mask values are adjacent and aligned with
10201 // a pair.
10202 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
10203 WidenedMask.push_back(Mask[i] / 2);
10204 continue;
10205 }
10207 // Otherwise we can't safely widen the elements used in this shuffle.
10208 return false;
10209 }
10210 assert(WidenedMask.size() == Mask.size() / 2 &&
10211 "Incorrect size of mask after widening the elements!");
10213 return true;
10214 }
10216 /// \brief Top-level lowering for x86 vector shuffles.
10217 ///
10218 /// This handles decomposition, canonicalization, and lowering of all x86
10219 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10220 /// above in helper routines. The canonicalization attempts to widen shuffles
10221 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10222 /// s.t. only one of the two inputs needs to be tested, etc.
10223 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10224 SelectionDAG &DAG) {
10225 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10226 ArrayRef<int> Mask = SVOp->getMask();
10227 SDValue V1 = Op.getOperand(0);
10228 SDValue V2 = Op.getOperand(1);
10229 MVT VT = Op.getSimpleValueType();
10230 int NumElements = VT.getVectorNumElements();
10231 SDLoc dl(Op);
10233 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10235 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10236 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10237 if (V1IsUndef && V2IsUndef)
10238 return DAG.getUNDEF(VT);
10240 // When we create a shuffle node we put the UNDEF node to second operand,
10241 // but in some cases the first operand may be transformed to UNDEF.
10242 // In this case we should just commute the node.
10243 if (V1IsUndef)
10244 return DAG.getCommutedVectorShuffle(*SVOp);
10246 // Check for non-undef masks pointing at an undef vector and make the masks
10247 // undef as well. This makes it easier to match the shuffle based solely on
10248 // the mask.
10249 if (V2IsUndef)
10250 for (int M : Mask)
10251 if (M >= NumElements) {
10252 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10253 for (int &M : NewMask)
10254 if (M >= NumElements)
10255 M = -1;
10256 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10257 }
10259 // Try to collapse shuffles into using a vector type with fewer elements but
10260 // wider element types. We cap this to not form integers or floating point
10261 // elements wider than 64 bits, but it might be interesting to form i128
10262 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10263 SmallVector<int, 16> WidenedMask;
10264 if (VT.getScalarSizeInBits() < 64 &&
10265 canWidenShuffleElements(Mask, WidenedMask)) {
10266 MVT NewEltVT = VT.isFloatingPoint()
10267 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10268 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10269 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10270 // Make sure that the new vector type is legal. For example, v2f64 isn't
10271 // legal on SSE1.
10272 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10273 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10274 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10275 return DAG.getNode(ISD::BITCAST, dl, VT,
10276 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10277 }
10278 }
10280 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10281 for (int M : SVOp->getMask())
10282 if (M < 0)
10283 ++NumUndefElements;
10284 else if (M < NumElements)
10285 ++NumV1Elements;
10286 else
10287 ++NumV2Elements;
10289 // Commute the shuffle as needed such that more elements come from V1 than
10290 // V2. This allows us to match the shuffle pattern strictly on how many
10291 // elements come from V1 without handling the symmetric cases.
10292 if (NumV2Elements > NumV1Elements)
10293 return DAG.getCommutedVectorShuffle(*SVOp);
10295 // When the number of V1 and V2 elements are the same, try to minimize the
10296 // number of uses of V2 in the low half of the vector. When that is tied,
10297 // ensure that the sum of indices for V1 is equal to or lower than the sum
10298 // indices for V2.
10299 if (NumV1Elements == NumV2Elements) {
10300 int LowV1Elements = 0, LowV2Elements = 0;
10301 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10302 if (M >= NumElements)
10303 ++LowV2Elements;
10304 else if (M >= 0)
10305 ++LowV1Elements;
10306 if (LowV2Elements > LowV1Elements) {
10307 return DAG.getCommutedVectorShuffle(*SVOp);
10308 } else if (LowV2Elements == LowV1Elements) {
10309 int SumV1Indices = 0, SumV2Indices = 0;
10310 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10311 if (SVOp->getMask()[i] >= NumElements)
10312 SumV2Indices += i;
10313 else if (SVOp->getMask()[i] >= 0)
10314 SumV1Indices += i;
10315 if (SumV2Indices < SumV1Indices)
10316 return DAG.getCommutedVectorShuffle(*SVOp);
10317 }
10318 }
10320 // For each vector width, delegate to a specialized lowering routine.
10321 if (VT.getSizeInBits() == 128)
10322 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10324 if (VT.getSizeInBits() == 256)
10325 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10327 // Force AVX-512 vectors to be scalarized for now.
10328 // FIXME: Implement AVX-512 support!
10329 if (VT.getSizeInBits() == 512)
10330 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10332 llvm_unreachable("Unimplemented!");
10333 }
10336 //===----------------------------------------------------------------------===//
10337 // Legacy vector shuffle lowering
10338 //
10339 // This code is the legacy code handling vector shuffles until the above
10340 // replaces its functionality and performance.
10341 //===----------------------------------------------------------------------===//
10343 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
10344 bool hasInt256, unsigned *MaskOut = nullptr) {
10345 MVT EltVT = VT.getVectorElementType();
10347 // There is no blend with immediate in AVX-512.
10348 if (VT.is512BitVector())
10349 return false;
10351 if (!hasSSE41 || EltVT == MVT::i8)
10352 return false;
10353 if (!hasInt256 && VT == MVT::v16i16)
10354 return false;
10356 unsigned MaskValue = 0;
10357 unsigned NumElems = VT.getVectorNumElements();
10358 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10359 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10360 unsigned NumElemsInLane = NumElems / NumLanes;
10362 // Blend for v16i16 should be symetric for the both lanes.
10363 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10365 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
10366 int EltIdx = MaskVals[i];
10368 if ((EltIdx < 0 || EltIdx == (int)i) &&
10369 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
10370 continue;
10372 if (((unsigned)EltIdx == (i + NumElems)) &&
10373 (SndLaneEltIdx < 0 ||
10374 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
10375 MaskValue |= (1 << i);
10376 else
10377 return false;
10378 }
10380 if (MaskOut)
10381 *MaskOut = MaskValue;
10382 return true;
10383 }
10385 // Try to lower a shuffle node into a simple blend instruction.
10386 // This function assumes isBlendMask returns true for this
10387 // SuffleVectorSDNode
10388 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
10389 unsigned MaskValue,
10390 const X86Subtarget *Subtarget,
10391 SelectionDAG &DAG) {
10392 MVT VT = SVOp->getSimpleValueType(0);
10393 MVT EltVT = VT.getVectorElementType();
10394 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
10395 Subtarget->hasInt256() && "Trying to lower a "
10396 "VECTOR_SHUFFLE to a Blend but "
10397 "with the wrong mask"));
10398 SDValue V1 = SVOp->getOperand(0);
10399 SDValue V2 = SVOp->getOperand(1);
10400 SDLoc dl(SVOp);
10401 unsigned NumElems = VT.getVectorNumElements();
10403 // Convert i32 vectors to floating point if it is not AVX2.
10404 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
10405 MVT BlendVT = VT;
10406 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
10407 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
10408 NumElems);
10409 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
10410 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
10411 }
10413 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
10414 DAG.getConstant(MaskValue, MVT::i32));
10415 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
10416 }
10418 /// In vector type \p VT, return true if the element at index \p InputIdx
10419 /// falls on a different 128-bit lane than \p OutputIdx.
10420 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
10421 unsigned OutputIdx) {
10422 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
10423 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
10424 }
10426 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
10427 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
10428 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
10429 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
10430 /// zero.
10431 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
10432 SelectionDAG &DAG) {
10433 MVT VT = V1.getSimpleValueType();
10434 assert(VT.is128BitVector() || VT.is256BitVector());
10436 MVT EltVT = VT.getVectorElementType();
10437 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
10438 unsigned NumElts = VT.getVectorNumElements();
10440 SmallVector<SDValue, 32> PshufbMask;
10441 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
10442 int InputIdx = MaskVals[OutputIdx];
10443 unsigned InputByteIdx;
10445 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
10446 InputByteIdx = 0x80;
10447 else {
10448 // Cross lane is not allowed.
10449 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
10450 return SDValue();
10451 InputByteIdx = InputIdx * EltSizeInBytes;
10452 // Index is an byte offset within the 128-bit lane.
10453 InputByteIdx &= 0xf;
10454 }
10456 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
10457 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
10458 if (InputByteIdx != 0x80)
10459 ++InputByteIdx;
10460 }
10461 }
10463 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
10464 if (ShufVT != VT)
10465 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
10466 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
10467 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
10468 }
10470 // v8i16 shuffles - Prefer shuffles in the following order:
10471 // 1. [all] pshuflw, pshufhw, optional move
10472 // 2. [ssse3] 1 x pshufb
10473 // 3. [ssse3] 2 x pshufb + 1 x por
10474 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
10475 static SDValue
10476 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
10477 SelectionDAG &DAG) {
10478 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10479 SDValue V1 = SVOp->getOperand(0);
10480 SDValue V2 = SVOp->getOperand(1);
10481 SDLoc dl(SVOp);
10482 SmallVector<int, 8> MaskVals;
10484 // Determine if more than 1 of the words in each of the low and high quadwords
10485 // of the result come from the same quadword of one of the two inputs. Undef
10486 // mask values count as coming from any quadword, for better codegen.
10487 //
10488 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
10489 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
10490 unsigned LoQuad[] = { 0, 0, 0, 0 };
10491 unsigned HiQuad[] = { 0, 0, 0, 0 };
10492 // Indices of quads used.
10493 std::bitset<4> InputQuads;
10494 for (unsigned i = 0; i < 8; ++i) {
10495 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
10496 int EltIdx = SVOp->getMaskElt(i);
10497 MaskVals.push_back(EltIdx);
10498 if (EltIdx < 0) {
10499 ++Quad[0];
10500 ++Quad[1];
10501 ++Quad[2];
10502 ++Quad[3];
10503 continue;
10504 }
10505 ++Quad[EltIdx / 4];
10506 InputQuads.set(EltIdx / 4);
10507 }
10509 int BestLoQuad = -1;
10510 unsigned MaxQuad = 1;
10511 for (unsigned i = 0; i < 4; ++i) {
10512 if (LoQuad[i] > MaxQuad) {
10513 BestLoQuad = i;
10514 MaxQuad = LoQuad[i];
10515 }
10516 }
10518 int BestHiQuad = -1;
10519 MaxQuad = 1;
10520 for (unsigned i = 0; i < 4; ++i) {
10521 if (HiQuad[i] > MaxQuad) {
10522 BestHiQuad = i;
10523 MaxQuad = HiQuad[i];
10524 }
10525 }
10527 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
10528 // of the two input vectors, shuffle them into one input vector so only a
10529 // single pshufb instruction is necessary. If there are more than 2 input
10530 // quads, disable the next transformation since it does not help SSSE3.
10531 bool V1Used = InputQuads[0] || InputQuads[1];
10532 bool V2Used = InputQuads[2] || InputQuads[3];
10533 if (Subtarget->hasSSSE3()) {
10534 if (InputQuads.count() == 2 && V1Used && V2Used) {
10535 BestLoQuad = InputQuads[0] ? 0 : 1;
10536 BestHiQuad = InputQuads[2] ? 2 : 3;
10537 }
10538 if (InputQuads.count() > 2) {
10539 BestLoQuad = -1;
10540 BestHiQuad = -1;
10541 }
10542 }
10544 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
10545 // the shuffle mask. If a quad is scored as -1, that means that it contains
10546 // words from all 4 input quadwords.
10547 SDValue NewV;
10548 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
10549 int MaskV[] = {
10550 BestLoQuad < 0 ? 0 : BestLoQuad,
10551 BestHiQuad < 0 ? 1 : BestHiQuad
10552 };
10553 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
10554 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
10555 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
10556 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
10558 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
10559 // source words for the shuffle, to aid later transformations.
10560 bool AllWordsInNewV = true;
10561 bool InOrder[2] = { true, true };
10562 for (unsigned i = 0; i != 8; ++i) {
10563 int idx = MaskVals[i];
10564 if (idx != (int)i)
10565 InOrder[i/4] = false;
10566 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
10567 continue;
10568 AllWordsInNewV = false;
10569 break;
10570 }
10572 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
10573 if (AllWordsInNewV) {
10574 for (int i = 0; i != 8; ++i) {
10575 int idx = MaskVals[i];
10576 if (idx < 0)
10577 continue;
10578 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
10579 if ((idx != i) && idx < 4)
10580 pshufhw = false;
10581 if ((idx != i) && idx > 3)
10582 pshuflw = false;
10583 }
10584 V1 = NewV;
10585 V2Used = false;
10586 BestLoQuad = 0;
10587 BestHiQuad = 1;
10588 }
10590 // If we've eliminated the use of V2, and the new mask is a pshuflw or
10591 // pshufhw, that's as cheap as it gets. Return the new shuffle.
10592 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
10593 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
10594 unsigned TargetMask = 0;
10595 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
10596 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
10597 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10598 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
10599 getShufflePSHUFLWImmediate(SVOp);
10600 V1 = NewV.getOperand(0);
10601 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
10602 }
10603 }
10605 // Promote splats to a larger type which usually leads to more efficient code.
10606 // FIXME: Is this true if pshufb is available?
10607 if (SVOp->isSplat())
10608 return PromoteSplat(SVOp, DAG);
10610 // If we have SSSE3, and all words of the result are from 1 input vector,
10611 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
10612 // is present, fall back to case 4.
10613 if (Subtarget->hasSSSE3()) {
10614 SmallVector<SDValue,16> pshufbMask;
10616 // If we have elements from both input vectors, set the high bit of the
10617 // shuffle mask element to zero out elements that come from V2 in the V1
10618 // mask, and elements that come from V1 in the V2 mask, so that the two
10619 // results can be OR'd together.
10620 bool TwoInputs = V1Used && V2Used;
10621 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
10622 if (!TwoInputs)
10623 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10625 // Calculate the shuffle mask for the second input, shuffle it, and
10626 // OR it with the first shuffled input.
10627 CommuteVectorShuffleMask(MaskVals, 8);
10628 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
10629 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
10630 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10631 }
10633 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
10634 // and update MaskVals with new element order.
10635 std::bitset<8> InOrder;
10636 if (BestLoQuad >= 0) {
10637 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
10638 for (int i = 0; i != 4; ++i) {
10639 int idx = MaskVals[i];
10640 if (idx < 0) {
10641 InOrder.set(i);
10642 } else if ((idx / 4) == BestLoQuad) {
10643 MaskV[i] = idx & 3;
10644 InOrder.set(i);
10645 }
10646 }
10647 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10648 &MaskV[0]);
10650 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10651 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10652 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
10653 NewV.getOperand(0),
10654 getShufflePSHUFLWImmediate(SVOp), DAG);
10655 }
10656 }
10658 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
10659 // and update MaskVals with the new element order.
10660 if (BestHiQuad >= 0) {
10661 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
10662 for (unsigned i = 4; i != 8; ++i) {
10663 int idx = MaskVals[i];
10664 if (idx < 0) {
10665 InOrder.set(i);
10666 } else if ((idx / 4) == BestHiQuad) {
10667 MaskV[i] = (idx & 3) + 4;
10668 InOrder.set(i);
10669 }
10670 }
10671 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10672 &MaskV[0]);
10674 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10675 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10676 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
10677 NewV.getOperand(0),
10678 getShufflePSHUFHWImmediate(SVOp), DAG);
10679 }
10680 }
10682 // In case BestHi & BestLo were both -1, which means each quadword has a word
10683 // from each of the four input quadwords, calculate the InOrder bitvector now
10684 // before falling through to the insert/extract cleanup.
10685 if (BestLoQuad == -1 && BestHiQuad == -1) {
10686 NewV = V1;
10687 for (int i = 0; i != 8; ++i)
10688 if (MaskVals[i] < 0 || MaskVals[i] == i)
10689 InOrder.set(i);
10690 }
10692 // The other elements are put in the right place using pextrw and pinsrw.
10693 for (unsigned i = 0; i != 8; ++i) {
10694 if (InOrder[i])
10695 continue;
10696 int EltIdx = MaskVals[i];
10697 if (EltIdx < 0)
10698 continue;
10699 SDValue ExtOp = (EltIdx < 8) ?
10700 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
10701 DAG.getIntPtrConstant(EltIdx)) :
10702 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
10703 DAG.getIntPtrConstant(EltIdx - 8));
10704 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
10705 DAG.getIntPtrConstant(i));
10706 }
10707 return NewV;
10708 }
10710 /// \brief v16i16 shuffles
10711 ///
10712 /// FIXME: We only support generation of a single pshufb currently. We can
10713 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
10714 /// well (e.g 2 x pshufb + 1 x por).
10715 static SDValue
10716 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
10717 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10718 SDValue V1 = SVOp->getOperand(0);
10719 SDValue V2 = SVOp->getOperand(1);
10720 SDLoc dl(SVOp);
10722 if (V2.getOpcode() != ISD::UNDEF)
10723 return SDValue();
10725 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10726 return getPSHUFB(MaskVals, V1, dl, DAG);
10727 }
10729 // v16i8 shuffles - Prefer shuffles in the following order:
10730 // 1. [ssse3] 1 x pshufb
10731 // 2. [ssse3] 2 x pshufb + 1 x por
10732 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
10733 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
10734 const X86Subtarget* Subtarget,
10735 SelectionDAG &DAG) {
10736 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10737 SDValue V1 = SVOp->getOperand(0);
10738 SDValue V2 = SVOp->getOperand(1);
10739 SDLoc dl(SVOp);
10740 ArrayRef<int> MaskVals = SVOp->getMask();
10742 // Promote splats to a larger type which usually leads to more efficient code.
10743 // FIXME: Is this true if pshufb is available?
10744 if (SVOp->isSplat())
10745 return PromoteSplat(SVOp, DAG);
10747 // If we have SSSE3, case 1 is generated when all result bytes come from
10748 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
10749 // present, fall back to case 3.
10751 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
10752 if (Subtarget->hasSSSE3()) {
10753 SmallVector<SDValue,16> pshufbMask;
10755 // If all result elements are from one input vector, then only translate
10756 // undef mask values to 0x80 (zero out result) in the pshufb mask.
10757 //
10758 // Otherwise, we have elements from both input vectors, and must zero out
10759 // elements that come from V2 in the first mask, and V1 in the second mask
10760 // so that we can OR them together.
10761 for (unsigned i = 0; i != 16; ++i) {
10762 int EltIdx = MaskVals[i];
10763 if (EltIdx < 0 || EltIdx >= 16)
10764 EltIdx = 0x80;
10765 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10766 }
10767 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
10768 DAG.getNode(ISD::BUILD_VECTOR, dl,
10769 MVT::v16i8, pshufbMask));
10771 // As PSHUFB will zero elements with negative indices, it's safe to ignore
10772 // the 2nd operand if it's undefined or zero.
10773 if (V2.getOpcode() == ISD::UNDEF ||
10774 ISD::isBuildVectorAllZeros(V2.getNode()))
10775 return V1;
10777 // Calculate the shuffle mask for the second input, shuffle it, and
10778 // OR it with the first shuffled input.
10779 pshufbMask.clear();
10780 for (unsigned i = 0; i != 16; ++i) {
10781 int EltIdx = MaskVals[i];
10782 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
10783 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10784 }
10785 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
10786 DAG.getNode(ISD::BUILD_VECTOR, dl,
10787 MVT::v16i8, pshufbMask));
10788 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
10789 }
10791 // No SSSE3 - Calculate in place words and then fix all out of place words
10792 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
10793 // the 16 different words that comprise the two doublequadword input vectors.
10794 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10795 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
10796 SDValue NewV = V1;
10797 for (int i = 0; i != 8; ++i) {
10798 int Elt0 = MaskVals[i*2];
10799 int Elt1 = MaskVals[i*2+1];
10801 // This word of the result is all undef, skip it.
10802 if (Elt0 < 0 && Elt1 < 0)
10803 continue;
10805 // This word of the result is already in the correct place, skip it.
10806 if ((Elt0 == i*2) && (Elt1 == i*2+1))
10807 continue;
10809 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
10810 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
10811 SDValue InsElt;
10813 // If Elt0 and Elt1 are defined, are consecutive, and can be load
10814 // using a single extract together, load it and store it.
10815 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
10816 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
10817 DAG.getIntPtrConstant(Elt1 / 2));
10818 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10819 DAG.getIntPtrConstant(i));
10820 continue;
10821 }
10823 // If Elt1 is defined, extract it from the appropriate source. If the
10824 // source byte is not also odd, shift the extracted word left 8 bits
10825 // otherwise clear the bottom 8 bits if we need to do an or.
10826 if (Elt1 >= 0) {
10827 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
10828 DAG.getIntPtrConstant(Elt1 / 2));
10829 if ((Elt1 & 1) == 0)
10830 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
10831 DAG.getConstant(8,
10832 TLI.getShiftAmountTy(InsElt.getValueType())));
10833 else if (Elt0 >= 0)
10834 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
10835 DAG.getConstant(0xFF00, MVT::i16));
10836 }
10837 // If Elt0 is defined, extract it from the appropriate source. If the
10838 // source byte is not also even, shift the extracted word right 8 bits. If
10839 // Elt1 was also defined, OR the extracted values together before
10840 // inserting them in the result.
10841 if (Elt0 >= 0) {
10842 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
10843 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
10844 if ((Elt0 & 1) != 0)
10845 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
10846 DAG.getConstant(8,
10847 TLI.getShiftAmountTy(InsElt0.getValueType())));
10848 else if (Elt1 >= 0)
10849 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
10850 DAG.getConstant(0x00FF, MVT::i16));
10851 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
10852 : InsElt0;
10853 }
10854 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10855 DAG.getIntPtrConstant(i));
10856 }
10857 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
10858 }
10860 // v32i8 shuffles - Translate to VPSHUFB if possible.
10861 static
10862 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
10863 const X86Subtarget *Subtarget,
10864 SelectionDAG &DAG) {
10865 MVT VT = SVOp->getSimpleValueType(0);
10866 SDValue V1 = SVOp->getOperand(0);
10867 SDValue V2 = SVOp->getOperand(1);
10868 SDLoc dl(SVOp);
10869 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10871 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10872 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
10873 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
10875 // VPSHUFB may be generated if
10876 // (1) one of input vector is undefined or zeroinitializer.
10877 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
10878 // And (2) the mask indexes don't cross the 128-bit lane.
10879 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
10880 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
10881 return SDValue();
10883 if (V1IsAllZero && !V2IsAllZero) {
10884 CommuteVectorShuffleMask(MaskVals, 32);
10885 V1 = V2;
10886 }
10887 return getPSHUFB(MaskVals, V1, dl, DAG);
10888 }
10890 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
10891 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
10892 /// done when every pair / quad of shuffle mask elements point to elements in
10893 /// the right sequence. e.g.
10894 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
10895 static
10896 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
10897 SelectionDAG &DAG) {
10898 MVT VT = SVOp->getSimpleValueType(0);
10899 SDLoc dl(SVOp);
10900 unsigned NumElems = VT.getVectorNumElements();
10901 MVT NewVT;
10902 unsigned Scale;
10903 switch (VT.SimpleTy) {
10904 default: llvm_unreachable("Unexpected!");
10905 case MVT::v2i64:
10906 case MVT::v2f64:
10907 return SDValue(SVOp, 0);
10908 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
10909 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
10910 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
10911 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
10912 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
10913 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
10914 }
10916 SmallVector<int, 8> MaskVec;
10917 for (unsigned i = 0; i != NumElems; i += Scale) {
10918 int StartIdx = -1;
10919 for (unsigned j = 0; j != Scale; ++j) {
10920 int EltIdx = SVOp->getMaskElt(i+j);
10921 if (EltIdx < 0)
10922 continue;
10923 if (StartIdx < 0)
10924 StartIdx = (EltIdx / Scale);
10925 if (EltIdx != (int)(StartIdx*Scale + j))
10926 return SDValue();
10927 }
10928 MaskVec.push_back(StartIdx);
10929 }
10931 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
10932 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
10933 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
10934 }
10936 /// getVZextMovL - Return a zero-extending vector move low node.
10937 ///
10938 static SDValue getVZextMovL(MVT VT, MVT OpVT,
10939 SDValue SrcOp, SelectionDAG &DAG,
10940 const X86Subtarget *Subtarget, SDLoc dl) {
10941 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
10942 LoadSDNode *LD = nullptr;
10943 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
10944 LD = dyn_cast<LoadSDNode>(SrcOp);
10945 if (!LD) {
10946 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
10947 // instead.
10948 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
10949 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
10950 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
10951 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
10952 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
10953 // PR2108
10954 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
10955 return DAG.getNode(ISD::BITCAST, dl, VT,
10956 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
10957 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
10958 OpVT,
10959 SrcOp.getOperand(0)
10960 .getOperand(0))));
10961 }
10962 }
10963 }
10965 return DAG.getNode(ISD::BITCAST, dl, VT,
10966 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
10967 DAG.getNode(ISD::BITCAST, dl,
10968 OpVT, SrcOp)));
10969 }
10971 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
10972 /// which could not be matched by any known target speficic shuffle
10973 static SDValue
10974 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
10976 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
10977 if (NewOp.getNode())
10978 return NewOp;
10980 MVT VT = SVOp->getSimpleValueType(0);
10982 unsigned NumElems = VT.getVectorNumElements();
10983 unsigned NumLaneElems = NumElems / 2;
10985 SDLoc dl(SVOp);
10986 MVT EltVT = VT.getVectorElementType();
10987 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
10988 SDValue Output[2];
10990 SmallVector<int, 16> Mask;
10991 for (unsigned l = 0; l < 2; ++l) {
10992 // Build a shuffle mask for the output, discovering on the fly which
10993 // input vectors to use as shuffle operands (recorded in InputUsed).
10994 // If building a suitable shuffle vector proves too hard, then bail
10995 // out with UseBuildVector set.
10996 bool UseBuildVector = false;
10997 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
10998 unsigned LaneStart = l * NumLaneElems;
10999 for (unsigned i = 0; i != NumLaneElems; ++i) {
11000 // The mask element. This indexes into the input.
11001 int Idx = SVOp->getMaskElt(i+LaneStart);
11002 if (Idx < 0) {
11003 // the mask element does not index into any input vector.
11004 Mask.push_back(-1);
11005 continue;
11006 }
11008 // The input vector this mask element indexes into.
11009 int Input = Idx / NumLaneElems;
11011 // Turn the index into an offset from the start of the input vector.
11012 Idx -= Input * NumLaneElems;
11014 // Find or create a shuffle vector operand to hold this input.
11015 unsigned OpNo;
11016 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
11017 if (InputUsed[OpNo] == Input)
11018 // This input vector is already an operand.
11019 break;
11020 if (InputUsed[OpNo] < 0) {
11021 // Create a new operand for this input vector.
11022 InputUsed[OpNo] = Input;
11023 break;
11024 }
11025 }
11027 if (OpNo >= array_lengthof(InputUsed)) {
11028 // More than two input vectors used! Give up on trying to create a
11029 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
11030 UseBuildVector = true;
11031 break;
11032 }
11034 // Add the mask index for the new shuffle vector.
11035 Mask.push_back(Idx + OpNo * NumLaneElems);
11036 }
11038 if (UseBuildVector) {
11039 SmallVector<SDValue, 16> SVOps;
11040 for (unsigned i = 0; i != NumLaneElems; ++i) {
11041 // The mask element. This indexes into the input.
11042 int Idx = SVOp->getMaskElt(i+LaneStart);
11043 if (Idx < 0) {
11044 SVOps.push_back(DAG.getUNDEF(EltVT));
11045 continue;
11046 }
11048 // The input vector this mask element indexes into.
11049 int Input = Idx / NumElems;
11051 // Turn the index into an offset from the start of the input vector.
11052 Idx -= Input * NumElems;
11054 // Extract the vector element by hand.
11055 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
11056 SVOp->getOperand(Input),
11057 DAG.getIntPtrConstant(Idx)));
11058 }
11060 // Construct the output using a BUILD_VECTOR.
11061 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
11062 } else if (InputUsed[0] < 0) {
11063 // No input vectors were used! The result is undefined.
11064 Output[l] = DAG.getUNDEF(NVT);
11065 } else {
11066 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
11067 (InputUsed[0] % 2) * NumLaneElems,
11068 DAG, dl);
11069 // If only one input was used, use an undefined vector for the other.
11070 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
11071 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
11072 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
11073 // At least one input vector was used. Create a new shuffle vector.
11074 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
11075 }
11077 Mask.clear();
11078 }
11080 // Concatenate the result back
11081 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
11082 }
11084 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
11085 /// 4 elements, and match them with several different shuffle types.
11086 static SDValue
11087 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11088 SDValue V1 = SVOp->getOperand(0);
11089 SDValue V2 = SVOp->getOperand(1);
11090 SDLoc dl(SVOp);
11091 MVT VT = SVOp->getSimpleValueType(0);
11093 assert(VT.is128BitVector() && "Unsupported vector size");
11095 std::pair<int, int> Locs[4];
11096 int Mask1[] = { -1, -1, -1, -1 };
11097 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
11099 unsigned NumHi = 0;
11100 unsigned NumLo = 0;
11101 for (unsigned i = 0; i != 4; ++i) {
11102 int Idx = PermMask[i];
11103 if (Idx < 0) {
11104 Locs[i] = std::make_pair(-1, -1);
11105 } else {
11106 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
11107 if (Idx < 4) {
11108 Locs[i] = std::make_pair(0, NumLo);
11109 Mask1[NumLo] = Idx;
11110 NumLo++;
11111 } else {
11112 Locs[i] = std::make_pair(1, NumHi);
11113 if (2+NumHi < 4)
11114 Mask1[2+NumHi] = Idx;
11115 NumHi++;
11116 }
11117 }
11118 }
11120 if (NumLo <= 2 && NumHi <= 2) {
11121 // If no more than two elements come from either vector. This can be
11122 // implemented with two shuffles. First shuffle gather the elements.
11123 // The second shuffle, which takes the first shuffle as both of its
11124 // vector operands, put the elements into the right order.
11125 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11127 int Mask2[] = { -1, -1, -1, -1 };
11129 for (unsigned i = 0; i != 4; ++i)
11130 if (Locs[i].first != -1) {
11131 unsigned Idx = (i < 2) ? 0 : 4;
11132 Idx += Locs[i].first * 2 + Locs[i].second;
11133 Mask2[i] = Idx;
11134 }
11136 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
11137 }
11139 if (NumLo == 3 || NumHi == 3) {
11140 // Otherwise, we must have three elements from one vector, call it X, and
11141 // one element from the other, call it Y. First, use a shufps to build an
11142 // intermediate vector with the one element from Y and the element from X
11143 // that will be in the same half in the final destination (the indexes don't
11144 // matter). Then, use a shufps to build the final vector, taking the half
11145 // containing the element from Y from the intermediate, and the other half
11146 // from X.
11147 if (NumHi == 3) {
11148 // Normalize it so the 3 elements come from V1.
11149 CommuteVectorShuffleMask(PermMask, 4);
11150 std::swap(V1, V2);
11151 }
11153 // Find the element from V2.
11154 unsigned HiIndex;
11155 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
11156 int Val = PermMask[HiIndex];
11157 if (Val < 0)
11158 continue;
11159 if (Val >= 4)
11160 break;
11161 }
11163 Mask1[0] = PermMask[HiIndex];
11164 Mask1[1] = -1;
11165 Mask1[2] = PermMask[HiIndex^1];
11166 Mask1[3] = -1;
11167 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11169 if (HiIndex >= 2) {
11170 Mask1[0] = PermMask[0];
11171 Mask1[1] = PermMask[1];
11172 Mask1[2] = HiIndex & 1 ? 6 : 4;
11173 Mask1[3] = HiIndex & 1 ? 4 : 6;
11174 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11175 }
11177 Mask1[0] = HiIndex & 1 ? 2 : 0;
11178 Mask1[1] = HiIndex & 1 ? 0 : 2;
11179 Mask1[2] = PermMask[2];
11180 Mask1[3] = PermMask[3];
11181 if (Mask1[2] >= 0)
11182 Mask1[2] += 4;
11183 if (Mask1[3] >= 0)
11184 Mask1[3] += 4;
11185 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
11186 }
11188 // Break it into (shuffle shuffle_hi, shuffle_lo).
11189 int LoMask[] = { -1, -1, -1, -1 };
11190 int HiMask[] = { -1, -1, -1, -1 };
11192 int *MaskPtr = LoMask;
11193 unsigned MaskIdx = 0;
11194 unsigned LoIdx = 0;
11195 unsigned HiIdx = 2;
11196 for (unsigned i = 0; i != 4; ++i) {
11197 if (i == 2) {
11198 MaskPtr = HiMask;
11199 MaskIdx = 1;
11200 LoIdx = 0;
11201 HiIdx = 2;
11202 }
11203 int Idx = PermMask[i];
11204 if (Idx < 0) {
11205 Locs[i] = std::make_pair(-1, -1);
11206 } else if (Idx < 4) {
11207 Locs[i] = std::make_pair(MaskIdx, LoIdx);
11208 MaskPtr[LoIdx] = Idx;
11209 LoIdx++;
11210 } else {
11211 Locs[i] = std::make_pair(MaskIdx, HiIdx);
11212 MaskPtr[HiIdx] = Idx;
11213 HiIdx++;
11214 }
11215 }
11217 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
11218 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
11219 int MaskOps[] = { -1, -1, -1, -1 };
11220 for (unsigned i = 0; i != 4; ++i)
11221 if (Locs[i].first != -1)
11222 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
11223 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
11224 }
11226 static bool MayFoldVectorLoad(SDValue V) {
11227 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
11228 V = V.getOperand(0);
11230 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
11231 V = V.getOperand(0);
11232 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
11233 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
11234 // BUILD_VECTOR (load), undef
11235 V = V.getOperand(0);
11237 return MayFoldLoad(V);
11238 }
11240 static
11241 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
11242 MVT VT = Op.getSimpleValueType();
11244 // Canonizalize to v2f64.
11245 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
11246 return DAG.getNode(ISD::BITCAST, dl, VT,
11247 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
11248 V1, DAG));
11249 }
11251 static
11252 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
11253 bool HasSSE2) {
11254 SDValue V1 = Op.getOperand(0);
11255 SDValue V2 = Op.getOperand(1);
11256 MVT VT = Op.getSimpleValueType();
11258 assert(VT != MVT::v2i64 && "unsupported shuffle type");
11260 if (HasSSE2 && VT == MVT::v2f64)
11261 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
11263 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
11264 return DAG.getNode(ISD::BITCAST, dl, VT,
11265 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
11266 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
11267 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
11268 }
11270 static
11271 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
11272 SDValue V1 = Op.getOperand(0);
11273 SDValue V2 = Op.getOperand(1);
11274 MVT VT = Op.getSimpleValueType();
11276 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
11277 "unsupported shuffle type");
11279 if (V2.getOpcode() == ISD::UNDEF)
11280 V2 = V1;
11282 // v4i32 or v4f32
11283 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
11284 }
11286 static
11287 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
11288 SDValue V1 = Op.getOperand(0);
11289 SDValue V2 = Op.getOperand(1);
11290 MVT VT = Op.getSimpleValueType();
11291 unsigned NumElems = VT.getVectorNumElements();
11293 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
11294 // operand of these instructions is only memory, so check if there's a
11295 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
11296 // same masks.
11297 bool CanFoldLoad = false;
11299 // Trivial case, when V2 comes from a load.
11300 if (MayFoldVectorLoad(V2))
11301 CanFoldLoad = true;
11303 // When V1 is a load, it can be folded later into a store in isel, example:
11304 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
11305 // turns into:
11306 // (MOVLPSmr addr:$src1, VR128:$src2)
11307 // So, recognize this potential and also use MOVLPS or MOVLPD
11308 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
11309 CanFoldLoad = true;
11311 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11312 if (CanFoldLoad) {
11313 if (HasSSE2 && NumElems == 2)
11314 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
11316 if (NumElems == 4)
11317 // If we don't care about the second element, proceed to use movss.
11318 if (SVOp->getMaskElt(1) != -1)
11319 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
11320 }
11322 // movl and movlp will both match v2i64, but v2i64 is never matched by
11323 // movl earlier because we make it strict to avoid messing with the movlp load
11324 // folding logic (see the code above getMOVLP call). Match it here then,
11325 // this is horrible, but will stay like this until we move all shuffle
11326 // matching to x86 specific nodes. Note that for the 1st condition all
11327 // types are matched with movsd.
11328 if (HasSSE2) {
11329 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
11330 // as to remove this logic from here, as much as possible
11331 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
11332 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11333 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11334 }
11336 assert(VT != MVT::v4i32 && "unsupported shuffle type");
11338 // Invert the operand order and use SHUFPS to match it.
11339 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
11340 getShuffleSHUFImmediate(SVOp), DAG);
11341 }
11343 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
11344 SelectionDAG &DAG) {
11345 SDLoc dl(Load);
11346 MVT VT = Load->getSimpleValueType(0);
11347 MVT EVT = VT.getVectorElementType();
11348 SDValue Addr = Load->getOperand(1);
11349 SDValue NewAddr = DAG.getNode(
11350 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
11351 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
11353 SDValue NewLoad =
11354 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
11355 DAG.getMachineFunction().getMachineMemOperand(
11356 Load->getMemOperand(), 0, EVT.getStoreSize()));
11357 return NewLoad;
11358 }
11360 // It is only safe to call this function if isINSERTPSMask is true for
11361 // this shufflevector mask.
11362 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
11363 SelectionDAG &DAG) {
11364 // Generate an insertps instruction when inserting an f32 from memory onto a
11365 // v4f32 or when copying a member from one v4f32 to another.
11366 // We also use it for transferring i32 from one register to another,
11367 // since it simply copies the same bits.
11368 // If we're transferring an i32 from memory to a specific element in a
11369 // register, we output a generic DAG that will match the PINSRD
11370 // instruction.
11371 MVT VT = SVOp->getSimpleValueType(0);
11372 MVT EVT = VT.getVectorElementType();
11373 SDValue V1 = SVOp->getOperand(0);
11374 SDValue V2 = SVOp->getOperand(1);
11375 auto Mask = SVOp->getMask();
11376 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
11377 "unsupported vector type for insertps/pinsrd");
11379 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
11380 auto FromV2Predicate = [](const int &i) { return i >= 4; };
11381 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
11383 SDValue From;
11384 SDValue To;
11385 unsigned DestIndex;
11386 if (FromV1 == 1) {
11387 From = V1;
11388 To = V2;
11389 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
11390 Mask.begin();
11392 // If we have 1 element from each vector, we have to check if we're
11393 // changing V1's element's place. If so, we're done. Otherwise, we
11394 // should assume we're changing V2's element's place and behave
11395 // accordingly.
11396 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
11397 assert(DestIndex <= INT32_MAX && "truncated destination index");
11398 if (FromV1 == FromV2 &&
11399 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
11400 From = V2;
11401 To = V1;
11402 DestIndex =
11403 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11404 }
11405 } else {
11406 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
11407 "More than one element from V1 and from V2, or no elements from one "
11408 "of the vectors. This case should not have returned true from "
11409 "isINSERTPSMask");
11410 From = V2;
11411 To = V1;
11412 DestIndex =
11413 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11414 }
11416 // Get an index into the source vector in the range [0,4) (the mask is
11417 // in the range [0,8) because it can address V1 and V2)
11418 unsigned SrcIndex = Mask[DestIndex] % 4;
11419 if (MayFoldLoad(From)) {
11420 // Trivial case, when From comes from a load and is only used by the
11421 // shuffle. Make it use insertps from the vector that we need from that
11422 // load.
11423 SDValue NewLoad =
11424 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
11425 if (!NewLoad.getNode())
11426 return SDValue();
11428 if (EVT == MVT::f32) {
11429 // Create this as a scalar to vector to match the instruction pattern.
11430 SDValue LoadScalarToVector =
11431 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
11432 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
11433 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
11434 InsertpsMask);
11435 } else { // EVT == MVT::i32
11436 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
11437 // instruction, to match the PINSRD instruction, which loads an i32 to a
11438 // certain vector element.
11439 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
11440 DAG.getConstant(DestIndex, MVT::i32));
11441 }
11442 }
11444 // Vector-element-to-vector
11445 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
11446 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
11447 }
11449 // Reduce a vector shuffle to zext.
11450 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
11451 SelectionDAG &DAG) {
11452 // PMOVZX is only available from SSE41.
11453 if (!Subtarget->hasSSE41())
11454 return SDValue();
11456 MVT VT = Op.getSimpleValueType();
11458 // Only AVX2 support 256-bit vector integer extending.
11459 if (!Subtarget->hasInt256() && VT.is256BitVector())
11460 return SDValue();
11462 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11463 SDLoc DL(Op);
11464 SDValue V1 = Op.getOperand(0);
11465 SDValue V2 = Op.getOperand(1);
11466 unsigned NumElems = VT.getVectorNumElements();
11468 // Extending is an unary operation and the element type of the source vector
11469 // won't be equal to or larger than i64.
11470 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
11471 VT.getVectorElementType() == MVT::i64)
11472 return SDValue();
11474 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
11475 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
11476 while ((1U << Shift) < NumElems) {
11477 if (SVOp->getMaskElt(1U << Shift) == 1)
11478 break;
11479 Shift += 1;
11480 // The maximal ratio is 8, i.e. from i8 to i64.
11481 if (Shift > 3)
11482 return SDValue();
11483 }
11485 // Check the shuffle mask.
11486 unsigned Mask = (1U << Shift) - 1;
11487 for (unsigned i = 0; i != NumElems; ++i) {
11488 int EltIdx = SVOp->getMaskElt(i);
11489 if ((i & Mask) != 0 && EltIdx != -1)
11490 return SDValue();
11491 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
11492 return SDValue();
11493 }
11495 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
11496 MVT NeVT = MVT::getIntegerVT(NBits);
11497 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
11499 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
11500 return SDValue();
11502 // Simplify the operand as it's prepared to be fed into shuffle.
11503 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
11504 if (V1.getOpcode() == ISD::BITCAST &&
11505 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
11506 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
11507 V1.getOperand(0).getOperand(0)
11508 .getSimpleValueType().getSizeInBits() == SignificantBits) {
11509 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
11510 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
11511 ConstantSDNode *CIdx =
11512 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
11513 // If it's foldable, i.e. normal load with single use, we will let code
11514 // selection to fold it. Otherwise, we will short the conversion sequence.
11515 if (CIdx && CIdx->getZExtValue() == 0 &&
11516 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
11517 MVT FullVT = V.getSimpleValueType();
11518 MVT V1VT = V1.getSimpleValueType();
11519 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
11520 // The "ext_vec_elt" node is wider than the result node.
11521 // In this case we should extract subvector from V.
11522 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
11523 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
11524 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
11525 FullVT.getVectorNumElements()/Ratio);
11526 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
11527 DAG.getIntPtrConstant(0));
11528 }
11529 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
11530 }
11531 }
11533 return DAG.getNode(ISD::BITCAST, DL, VT,
11534 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
11535 }
11537 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
11538 SelectionDAG &DAG) {
11539 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11540 MVT VT = Op.getSimpleValueType();
11541 SDLoc dl(Op);
11542 SDValue V1 = Op.getOperand(0);
11543 SDValue V2 = Op.getOperand(1);
11545 if (isZeroShuffle(SVOp))
11546 return getZeroVector(VT, Subtarget, DAG, dl);
11548 // Handle splat operations
11549 if (SVOp->isSplat()) {
11550 // Use vbroadcast whenever the splat comes from a foldable load
11551 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
11552 if (Broadcast.getNode())
11553 return Broadcast;
11554 }
11556 // Check integer expanding shuffles.
11557 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
11558 if (NewOp.getNode())
11559 return NewOp;
11561 // If the shuffle can be profitably rewritten as a narrower shuffle, then
11562 // do it!
11563 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
11564 VT == MVT::v32i8) {
11565 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11566 if (NewOp.getNode())
11567 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
11568 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
11569 // FIXME: Figure out a cleaner way to do this.
11570 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
11571 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11572 if (NewOp.getNode()) {
11573 MVT NewVT = NewOp.getSimpleValueType();
11574 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
11575 NewVT, true, false))
11576 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
11577 dl);
11578 }
11579 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
11580 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11581 if (NewOp.getNode()) {
11582 MVT NewVT = NewOp.getSimpleValueType();
11583 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
11584 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
11585 dl);
11586 }
11587 }
11588 }
11589 return SDValue();
11590 }
11592 SDValue
11593 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
11594 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11595 SDValue V1 = Op.getOperand(0);
11596 SDValue V2 = Op.getOperand(1);
11597 MVT VT = Op.getSimpleValueType();
11598 SDLoc dl(Op);
11599 unsigned NumElems = VT.getVectorNumElements();
11600 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
11601 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11602 bool V1IsSplat = false;
11603 bool V2IsSplat = false;
11604 bool HasSSE2 = Subtarget->hasSSE2();
11605 bool HasFp256 = Subtarget->hasFp256();
11606 bool HasInt256 = Subtarget->hasInt256();
11607 MachineFunction &MF = DAG.getMachineFunction();
11608 bool OptForSize = MF.getFunction()->getAttributes().
11609 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
11611 // Check if we should use the experimental vector shuffle lowering. If so,
11612 // delegate completely to that code path.
11613 if (ExperimentalVectorShuffleLowering)
11614 return lowerVectorShuffle(Op, Subtarget, DAG);
11616 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
11618 if (V1IsUndef && V2IsUndef)
11619 return DAG.getUNDEF(VT);
11621 // When we create a shuffle node we put the UNDEF node to second operand,
11622 // but in some cases the first operand may be transformed to UNDEF.
11623 // In this case we should just commute the node.
11624 if (V1IsUndef)
11625 return DAG.getCommutedVectorShuffle(*SVOp);
11627 // Vector shuffle lowering takes 3 steps:
11628 //
11629 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
11630 // narrowing and commutation of operands should be handled.
11631 // 2) Matching of shuffles with known shuffle masks to x86 target specific
11632 // shuffle nodes.
11633 // 3) Rewriting of unmatched masks into new generic shuffle operations,
11634 // so the shuffle can be broken into other shuffles and the legalizer can
11635 // try the lowering again.
11636 //
11637 // The general idea is that no vector_shuffle operation should be left to
11638 // be matched during isel, all of them must be converted to a target specific
11639 // node here.
11641 // Normalize the input vectors. Here splats, zeroed vectors, profitable
11642 // narrowing and commutation of operands should be handled. The actual code
11643 // doesn't include all of those, work in progress...
11644 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
11645 if (NewOp.getNode())
11646 return NewOp;
11648 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
11650 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
11651 // unpckh_undef). Only use pshufd if speed is more important than size.
11652 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11653 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11654 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11655 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11657 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
11658 V2IsUndef && MayFoldVectorLoad(V1))
11659 return getMOVDDup(Op, dl, V1, DAG);
11661 if (isMOVHLPS_v_undef_Mask(M, VT))
11662 return getMOVHighToLow(Op, dl, DAG);
11664 // Use to match splats
11665 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
11666 (VT == MVT::v2f64 || VT == MVT::v2i64))
11667 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11669 if (isPSHUFDMask(M, VT)) {
11670 // The actual implementation will match the mask in the if above and then
11671 // during isel it can match several different instructions, not only pshufd
11672 // as its name says, sad but true, emulate the behavior for now...
11673 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
11674 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
11676 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
11678 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
11679 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
11681 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
11682 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
11683 DAG);
11685 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
11686 TargetMask, DAG);
11687 }
11689 if (isPALIGNRMask(M, VT, Subtarget))
11690 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
11691 getShufflePALIGNRImmediate(SVOp),
11692 DAG);
11694 if (isVALIGNMask(M, VT, Subtarget))
11695 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
11696 getShuffleVALIGNImmediate(SVOp),
11697 DAG);
11699 // Check if this can be converted into a logical shift.
11700 bool isLeft = false;
11701 unsigned ShAmt = 0;
11702 SDValue ShVal;
11703 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
11704 if (isShift && ShVal.hasOneUse()) {
11705 // If the shifted value has multiple uses, it may be cheaper to use
11706 // v_set0 + movlhps or movhlps, etc.
11707 MVT EltVT = VT.getVectorElementType();
11708 ShAmt *= EltVT.getSizeInBits();
11709 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11710 }
11712 if (isMOVLMask(M, VT)) {
11713 if (ISD::isBuildVectorAllZeros(V1.getNode()))
11714 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
11715 if (!isMOVLPMask(M, VT)) {
11716 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
11717 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11719 if (VT == MVT::v4i32 || VT == MVT::v4f32)
11720 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11721 }
11722 }
11724 // FIXME: fold these into legal mask.
11725 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
11726 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
11728 if (isMOVHLPSMask(M, VT))
11729 return getMOVHighToLow(Op, dl, DAG);
11731 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
11732 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
11734 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
11735 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
11737 if (isMOVLPMask(M, VT))
11738 return getMOVLP(Op, dl, DAG, HasSSE2);
11740 if (ShouldXformToMOVHLPS(M, VT) ||
11741 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
11742 return DAG.getCommutedVectorShuffle(*SVOp);
11744 if (isShift) {
11745 // No better options. Use a vshldq / vsrldq.
11746 MVT EltVT = VT.getVectorElementType();
11747 ShAmt *= EltVT.getSizeInBits();
11748 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11749 }
11751 bool Commuted = false;
11752 // FIXME: This should also accept a bitcast of a splat? Be careful, not
11753 // 1,1,1,1 -> v8i16 though.
11754 BitVector UndefElements;
11755 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
11756 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11757 V1IsSplat = true;
11758 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
11759 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11760 V2IsSplat = true;
11762 // Canonicalize the splat or undef, if present, to be on the RHS.
11763 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
11764 CommuteVectorShuffleMask(M, NumElems);
11765 std::swap(V1, V2);
11766 std::swap(V1IsSplat, V2IsSplat);
11767 Commuted = true;
11768 }
11770 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
11771 // Shuffling low element of v1 into undef, just return v1.
11772 if (V2IsUndef)
11773 return V1;
11774 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
11775 // the instruction selector will not match, so get a canonical MOVL with
11776 // swapped operands to undo the commute.
11777 return getMOVL(DAG, dl, VT, V2, V1);
11778 }
11780 if (isUNPCKLMask(M, VT, HasInt256))
11781 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11783 if (isUNPCKHMask(M, VT, HasInt256))
11784 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11786 if (V2IsSplat) {
11787 // Normalize mask so all entries that point to V2 points to its first
11788 // element then try to match unpck{h|l} again. If match, return a
11789 // new vector_shuffle with the corrected mask.p
11790 SmallVector<int, 8> NewMask(M.begin(), M.end());
11791 NormalizeMask(NewMask, NumElems);
11792 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
11793 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11794 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
11795 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11796 }
11798 if (Commuted) {
11799 // Commute is back and try unpck* again.
11800 // FIXME: this seems wrong.
11801 CommuteVectorShuffleMask(M, NumElems);
11802 std::swap(V1, V2);
11803 std::swap(V1IsSplat, V2IsSplat);
11805 if (isUNPCKLMask(M, VT, HasInt256))
11806 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11808 if (isUNPCKHMask(M, VT, HasInt256))
11809 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11810 }
11812 // Normalize the node to match x86 shuffle ops if needed
11813 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
11814 return DAG.getCommutedVectorShuffle(*SVOp);
11816 // The checks below are all present in isShuffleMaskLegal, but they are
11817 // inlined here right now to enable us to directly emit target specific
11818 // nodes, and remove one by one until they don't return Op anymore.
11820 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
11821 SVOp->getSplatIndex() == 0 && V2IsUndef) {
11822 if (VT == MVT::v2f64 || VT == MVT::v2i64)
11823 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11824 }
11826 if (isPSHUFHWMask(M, VT, HasInt256))
11827 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
11828 getShufflePSHUFHWImmediate(SVOp),
11829 DAG);
11831 if (isPSHUFLWMask(M, VT, HasInt256))
11832 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
11833 getShufflePSHUFLWImmediate(SVOp),
11834 DAG);
11836 unsigned MaskValue;
11837 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
11838 &MaskValue))
11839 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
11841 if (isSHUFPMask(M, VT))
11842 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
11843 getShuffleSHUFImmediate(SVOp), DAG);
11845 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11846 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11847 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11848 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11850 //===--------------------------------------------------------------------===//
11851 // Generate target specific nodes for 128 or 256-bit shuffles only
11852 // supported in the AVX instruction set.
11853 //
11855 // Handle VMOVDDUPY permutations
11856 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
11857 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
11859 // Handle VPERMILPS/D* permutations
11860 if (isVPERMILPMask(M, VT)) {
11861 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
11862 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
11863 getShuffleSHUFImmediate(SVOp), DAG);
11864 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
11865 getShuffleSHUFImmediate(SVOp), DAG);
11866 }
11868 unsigned Idx;
11869 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
11870 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
11871 Idx*(NumElems/2), DAG, dl);
11873 // Handle VPERM2F128/VPERM2I128 permutations
11874 if (isVPERM2X128Mask(M, VT, HasFp256))
11875 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
11876 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
11878 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
11879 return getINSERTPS(SVOp, dl, DAG);
11881 unsigned Imm8;
11882 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
11883 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
11885 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
11886 VT.is512BitVector()) {
11887 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
11888 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
11889 SmallVector<SDValue, 16> permclMask;
11890 for (unsigned i = 0; i != NumElems; ++i) {
11891 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
11892 }
11894 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
11895 if (V2IsUndef)
11896 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
11897 return DAG.getNode(X86ISD::VPERMV, dl, VT,
11898 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
11899 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
11900 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
11901 }
11903 //===--------------------------------------------------------------------===//
11904 // Since no target specific shuffle was selected for this generic one,
11905 // lower it into other known shuffles. FIXME: this isn't true yet, but
11906 // this is the plan.
11907 //
11909 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
11910 if (VT == MVT::v8i16) {
11911 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
11912 if (NewOp.getNode())
11913 return NewOp;
11914 }
11916 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
11917 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
11918 if (NewOp.getNode())
11919 return NewOp;
11920 }
11922 if (VT == MVT::v16i8) {
11923 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
11924 if (NewOp.getNode())
11925 return NewOp;
11926 }
11928 if (VT == MVT::v32i8) {
11929 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
11930 if (NewOp.getNode())
11931 return NewOp;
11932 }
11934 // Handle all 128-bit wide vectors with 4 elements, and match them with
11935 // several different shuffle types.
11936 if (NumElems == 4 && VT.is128BitVector())
11937 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
11939 // Handle general 256-bit shuffles
11940 if (VT.is256BitVector())
11941 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
11943 return SDValue();
11944 }
11946 // This function assumes its argument is a BUILD_VECTOR of constants or
11947 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11948 // true.
11949 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11950 unsigned &MaskValue) {
11951 MaskValue = 0;
11952 unsigned NumElems = BuildVector->getNumOperands();
11953 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11954 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11955 unsigned NumElemsInLane = NumElems / NumLanes;
11957 // Blend for v16i16 should be symetric for the both lanes.
11958 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11959 SDValue EltCond = BuildVector->getOperand(i);
11960 SDValue SndLaneEltCond =
11961 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11963 int Lane1Cond = -1, Lane2Cond = -1;
11964 if (isa<ConstantSDNode>(EltCond))
11965 Lane1Cond = !isZero(EltCond);
11966 if (isa<ConstantSDNode>(SndLaneEltCond))
11967 Lane2Cond = !isZero(SndLaneEltCond);
11969 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11970 // Lane1Cond != 0, means we want the first argument.
11971 // Lane1Cond == 0, means we want the second argument.
11972 // The encoding of this argument is 0 for the first argument, 1
11973 // for the second. Therefore, invert the condition.
11974 MaskValue |= !Lane1Cond << i;
11975 else if (Lane1Cond < 0)
11976 MaskValue |= !Lane2Cond << i;
11977 else
11978 return false;
11979 }
11980 return true;
11981 }
11983 /// \brief Try to lower a VSELECT instruction to an immediate-controlled blend
11984 /// instruction.
11985 static SDValue lowerVSELECTtoBLENDI(SDValue Op, const X86Subtarget *Subtarget,
11986 SelectionDAG &DAG) {
11987 SDValue Cond = Op.getOperand(0);
11988 SDValue LHS = Op.getOperand(1);
11989 SDValue RHS = Op.getOperand(2);
11990 SDLoc dl(Op);
11991 MVT VT = Op.getSimpleValueType();
11992 MVT EltVT = VT.getVectorElementType();
11993 unsigned NumElems = VT.getVectorNumElements();
11995 // There is no blend with immediate in AVX-512.
11996 if (VT.is512BitVector())
11997 return SDValue();
11999 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
12000 return SDValue();
12001 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
12002 return SDValue();
12004 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
12005 return SDValue();
12007 // Check the mask for BLEND and build the value.
12008 unsigned MaskValue = 0;
12009 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
12010 return SDValue();
12012 // Convert i32 vectors to floating point if it is not AVX2.
12013 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
12014 MVT BlendVT = VT;
12015 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
12016 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
12017 NumElems);
12018 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
12019 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
12020 }
12022 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
12023 DAG.getConstant(MaskValue, MVT::i32));
12024 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
12025 }
12027 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
12028 // A vselect where all conditions and data are constants can be optimized into
12029 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
12030 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
12031 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
12032 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
12033 return SDValue();
12035 SDValue BlendOp = lowerVSELECTtoBLENDI(Op, Subtarget, DAG);
12036 if (BlendOp.getNode())
12037 return BlendOp;
12039 // Some types for vselect were previously set to Expand, not Legal or
12040 // Custom. Return an empty SDValue so we fall-through to Expand, after
12041 // the Custom lowering phase.
12042 MVT VT = Op.getSimpleValueType();
12043 switch (VT.SimpleTy) {
12044 default:
12045 break;
12046 case MVT::v8i16:
12047 case MVT::v16i16:
12048 if (Subtarget->hasBWI() && Subtarget->hasVLX())
12049 break;
12050 return SDValue();
12051 }
12053 // We couldn't create a "Blend with immediate" node.
12054 // This node should still be legal, but we'll have to emit a blendv*
12055 // instruction.
12056 return Op;
12057 }
12059 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
12060 MVT VT = Op.getSimpleValueType();
12061 SDLoc dl(Op);
12063 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
12064 return SDValue();
12066 if (VT.getSizeInBits() == 8) {
12067 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
12068 Op.getOperand(0), Op.getOperand(1));
12069 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12070 DAG.getValueType(VT));
12071 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12072 }
12074 if (VT.getSizeInBits() == 16) {
12075 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12076 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
12077 if (Idx == 0)
12078 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12079 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12080 DAG.getNode(ISD::BITCAST, dl,
12081 MVT::v4i32,
12082 Op.getOperand(0)),
12083 Op.getOperand(1)));
12084 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
12085 Op.getOperand(0), Op.getOperand(1));
12086 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12087 DAG.getValueType(VT));
12088 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12089 }
12091 if (VT == MVT::f32) {
12092 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
12093 // the result back to FR32 register. It's only worth matching if the
12094 // result has a single use which is a store or a bitcast to i32. And in
12095 // the case of a store, it's not worth it if the index is a constant 0,
12096 // because a MOVSSmr can be used instead, which is smaller and faster.
12097 if (!Op.hasOneUse())
12098 return SDValue();
12099 SDNode *User = *Op.getNode()->use_begin();
12100 if ((User->getOpcode() != ISD::STORE ||
12101 (isa<ConstantSDNode>(Op.getOperand(1)) &&
12102 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
12103 (User->getOpcode() != ISD::BITCAST ||
12104 User->getValueType(0) != MVT::i32))
12105 return SDValue();
12106 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12107 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
12108 Op.getOperand(0)),
12109 Op.getOperand(1));
12110 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
12111 }
12113 if (VT == MVT::i32 || VT == MVT::i64) {
12114 // ExtractPS/pextrq works with constant index.
12115 if (isa<ConstantSDNode>(Op.getOperand(1)))
12116 return Op;
12117 }
12118 return SDValue();
12119 }
12121 /// Extract one bit from mask vector, like v16i1 or v8i1.
12122 /// AVX-512 feature.
12123 SDValue
12124 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
12125 SDValue Vec = Op.getOperand(0);
12126 SDLoc dl(Vec);
12127 MVT VecVT = Vec.getSimpleValueType();
12128 SDValue Idx = Op.getOperand(1);
12129 MVT EltVT = Op.getSimpleValueType();
12131 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
12133 // variable index can't be handled in mask registers,
12134 // extend vector to VR512
12135 if (!isa<ConstantSDNode>(Idx)) {
12136 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12137 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
12138 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
12139 ExtVT.getVectorElementType(), Ext, Idx);
12140 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
12141 }
12143 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12144 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12145 unsigned MaxSift = rc->getSize()*8 - 1;
12146 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
12147 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12148 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
12149 DAG.getConstant(MaxSift, MVT::i8));
12150 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
12151 DAG.getIntPtrConstant(0));
12152 }
12154 SDValue
12155 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
12156 SelectionDAG &DAG) const {
12157 SDLoc dl(Op);
12158 SDValue Vec = Op.getOperand(0);
12159 MVT VecVT = Vec.getSimpleValueType();
12160 SDValue Idx = Op.getOperand(1);
12162 if (Op.getSimpleValueType() == MVT::i1)
12163 return ExtractBitFromMaskVector(Op, DAG);
12165 if (!isa<ConstantSDNode>(Idx)) {
12166 if (VecVT.is512BitVector() ||
12167 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
12168 VecVT.getVectorElementType().getSizeInBits() == 32)) {
12170 MVT MaskEltVT =
12171 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
12172 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
12173 MaskEltVT.getSizeInBits());
12175 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
12176 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
12177 getZeroVector(MaskVT, Subtarget, DAG, dl),
12178 Idx, DAG.getConstant(0, getPointerTy()));
12179 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
12180 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
12181 Perm, DAG.getConstant(0, getPointerTy()));
12182 }
12183 return SDValue();
12184 }
12186 // If this is a 256-bit vector result, first extract the 128-bit vector and
12187 // then extract the element from the 128-bit vector.
12188 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
12190 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12191 // Get the 128-bit vector.
12192 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
12193 MVT EltVT = VecVT.getVectorElementType();
12195 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
12197 //if (IdxVal >= NumElems/2)
12198 // IdxVal -= NumElems/2;
12199 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
12200 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
12201 DAG.getConstant(IdxVal, MVT::i32));
12202 }
12204 assert(VecVT.is128BitVector() && "Unexpected vector length");
12206 if (Subtarget->hasSSE41()) {
12207 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
12208 if (Res.getNode())
12209 return Res;
12210 }
12212 MVT VT = Op.getSimpleValueType();
12213 // TODO: handle v16i8.
12214 if (VT.getSizeInBits() == 16) {
12215 SDValue Vec = Op.getOperand(0);
12216 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12217 if (Idx == 0)
12218 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12219 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12220 DAG.getNode(ISD::BITCAST, dl,
12221 MVT::v4i32, Vec),
12222 Op.getOperand(1)));
12223 // Transform it so it match pextrw which produces a 32-bit result.
12224 MVT EltVT = MVT::i32;
12225 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
12226 Op.getOperand(0), Op.getOperand(1));
12227 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
12228 DAG.getValueType(VT));
12229 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12230 }
12232 if (VT.getSizeInBits() == 32) {
12233 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12234 if (Idx == 0)
12235 return Op;
12237 // SHUFPS the element to the lowest double word, then movss.
12238 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
12239 MVT VVT = Op.getOperand(0).getSimpleValueType();
12240 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12241 DAG.getUNDEF(VVT), Mask);
12242 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12243 DAG.getIntPtrConstant(0));
12244 }
12246 if (VT.getSizeInBits() == 64) {
12247 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
12248 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
12249 // to match extract_elt for f64.
12250 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12251 if (Idx == 0)
12252 return Op;
12254 // UNPCKHPD the element to the lowest double word, then movsd.
12255 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
12256 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
12257 int Mask[2] = { 1, -1 };
12258 MVT VVT = Op.getOperand(0).getSimpleValueType();
12259 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12260 DAG.getUNDEF(VVT), Mask);
12261 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12262 DAG.getIntPtrConstant(0));
12263 }
12265 return SDValue();
12266 }
12268 /// Insert one bit to mask vector, like v16i1 or v8i1.
12269 /// AVX-512 feature.
12270 SDValue
12271 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
12272 SDLoc dl(Op);
12273 SDValue Vec = Op.getOperand(0);
12274 SDValue Elt = Op.getOperand(1);
12275 SDValue Idx = Op.getOperand(2);
12276 MVT VecVT = Vec.getSimpleValueType();
12278 if (!isa<ConstantSDNode>(Idx)) {
12279 // Non constant index. Extend source and destination,
12280 // insert element and then truncate the result.
12281 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12282 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
12283 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
12284 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
12285 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
12286 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
12287 }
12289 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12290 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
12291 if (Vec.getOpcode() == ISD::UNDEF)
12292 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12293 DAG.getConstant(IdxVal, MVT::i8));
12294 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12295 unsigned MaxSift = rc->getSize()*8 - 1;
12296 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12297 DAG.getConstant(MaxSift, MVT::i8));
12298 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
12299 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12300 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
12301 }
12303 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
12304 SelectionDAG &DAG) const {
12305 MVT VT = Op.getSimpleValueType();
12306 MVT EltVT = VT.getVectorElementType();
12308 if (EltVT == MVT::i1)
12309 return InsertBitToMaskVector(Op, DAG);
12311 SDLoc dl(Op);
12312 SDValue N0 = Op.getOperand(0);
12313 SDValue N1 = Op.getOperand(1);
12314 SDValue N2 = Op.getOperand(2);
12315 if (!isa<ConstantSDNode>(N2))
12316 return SDValue();
12317 auto *N2C = cast<ConstantSDNode>(N2);
12318 unsigned IdxVal = N2C->getZExtValue();
12320 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
12321 // into that, and then insert the subvector back into the result.
12322 if (VT.is256BitVector() || VT.is512BitVector()) {
12323 // Get the desired 128-bit vector half.
12324 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
12326 // Insert the element into the desired half.
12327 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
12328 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
12330 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
12331 DAG.getConstant(IdxIn128, MVT::i32));
12333 // Insert the changed part back to the 256-bit vector
12334 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
12335 }
12336 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
12338 if (Subtarget->hasSSE41()) {
12339 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
12340 unsigned Opc;
12341 if (VT == MVT::v8i16) {
12342 Opc = X86ISD::PINSRW;
12343 } else {
12344 assert(VT == MVT::v16i8);
12345 Opc = X86ISD::PINSRB;
12346 }
12348 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
12349 // argument.
12350 if (N1.getValueType() != MVT::i32)
12351 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12352 if (N2.getValueType() != MVT::i32)
12353 N2 = DAG.getIntPtrConstant(IdxVal);
12354 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
12355 }
12357 if (EltVT == MVT::f32) {
12358 // Bits [7:6] of the constant are the source select. This will always be
12359 // zero here. The DAG Combiner may combine an extract_elt index into
12360 // these
12361 // bits. For example (insert (extract, 3), 2) could be matched by
12362 // putting
12363 // the '3' into bits [7:6] of X86ISD::INSERTPS.
12364 // Bits [5:4] of the constant are the destination select. This is the
12365 // value of the incoming immediate.
12366 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
12367 // combine either bitwise AND or insert of float 0.0 to set these bits.
12368 N2 = DAG.getIntPtrConstant(IdxVal << 4);
12369 // Create this as a scalar to vector..
12370 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
12371 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
12372 }
12374 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
12375 // PINSR* works with constant index.
12376 return Op;
12377 }
12378 }
12380 if (EltVT == MVT::i8)
12381 return SDValue();
12383 if (EltVT.getSizeInBits() == 16) {
12384 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
12385 // as its second argument.
12386 if (N1.getValueType() != MVT::i32)
12387 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12388 if (N2.getValueType() != MVT::i32)
12389 N2 = DAG.getIntPtrConstant(IdxVal);
12390 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
12391 }
12392 return SDValue();
12393 }
12395 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
12396 SDLoc dl(Op);
12397 MVT OpVT = Op.getSimpleValueType();
12399 // If this is a 256-bit vector result, first insert into a 128-bit
12400 // vector and then insert into the 256-bit vector.
12401 if (!OpVT.is128BitVector()) {
12402 // Insert into a 128-bit vector.
12403 unsigned SizeFactor = OpVT.getSizeInBits()/128;
12404 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
12405 OpVT.getVectorNumElements() / SizeFactor);
12407 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
12409 // Insert the 128-bit vector.
12410 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
12411 }
12413 if (OpVT == MVT::v1i64 &&
12414 Op.getOperand(0).getValueType() == MVT::i64)
12415 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
12417 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
12418 assert(OpVT.is128BitVector() && "Expected an SSE type!");
12419 return DAG.getNode(ISD::BITCAST, dl, OpVT,
12420 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
12421 }
12423 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
12424 // a simple subregister reference or explicit instructions to grab
12425 // upper bits of a vector.
12426 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12427 SelectionDAG &DAG) {
12428 SDLoc dl(Op);
12429 SDValue In = Op.getOperand(0);
12430 SDValue Idx = Op.getOperand(1);
12431 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12432 MVT ResVT = Op.getSimpleValueType();
12433 MVT InVT = In.getSimpleValueType();
12435 if (Subtarget->hasFp256()) {
12436 if (ResVT.is128BitVector() &&
12437 (InVT.is256BitVector() || InVT.is512BitVector()) &&
12438 isa<ConstantSDNode>(Idx)) {
12439 return Extract128BitVector(In, IdxVal, DAG, dl);
12440 }
12441 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
12442 isa<ConstantSDNode>(Idx)) {
12443 return Extract256BitVector(In, IdxVal, DAG, dl);
12444 }
12445 }
12446 return SDValue();
12447 }
12449 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
12450 // simple superregister reference or explicit instructions to insert
12451 // the upper bits of a vector.
12452 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12453 SelectionDAG &DAG) {
12454 if (Subtarget->hasFp256()) {
12455 SDLoc dl(Op.getNode());
12456 SDValue Vec = Op.getNode()->getOperand(0);
12457 SDValue SubVec = Op.getNode()->getOperand(1);
12458 SDValue Idx = Op.getNode()->getOperand(2);
12460 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
12461 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
12462 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
12463 isa<ConstantSDNode>(Idx)) {
12464 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12465 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
12466 }
12468 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
12469 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
12470 isa<ConstantSDNode>(Idx)) {
12471 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12472 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
12473 }
12474 }
12475 return SDValue();
12476 }
12478 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
12479 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
12480 // one of the above mentioned nodes. It has to be wrapped because otherwise
12481 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
12482 // be used to form addressing mode. These wrapped nodes will be selected
12483 // into MOV32ri.
12484 SDValue
12485 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
12486 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
12488 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12489 // global base reg.
12490 unsigned char OpFlag = 0;
12491 unsigned WrapperKind = X86ISD::Wrapper;
12492 CodeModel::Model M = DAG.getTarget().getCodeModel();
12494 if (Subtarget->isPICStyleRIPRel() &&
12495 (M == CodeModel::Small || M == CodeModel::Kernel))
12496 WrapperKind = X86ISD::WrapperRIP;
12497 else if (Subtarget->isPICStyleGOT())
12498 OpFlag = X86II::MO_GOTOFF;
12499 else if (Subtarget->isPICStyleStubPIC())
12500 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12502 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
12503 CP->getAlignment(),
12504 CP->getOffset(), OpFlag);
12505 SDLoc DL(CP);
12506 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12507 // With PIC, the address is actually $g + Offset.
12508 if (OpFlag) {
12509 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12510 DAG.getNode(X86ISD::GlobalBaseReg,
12511 SDLoc(), getPointerTy()),
12512 Result);
12513 }
12515 return Result;
12516 }
12518 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
12519 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
12521 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12522 // global base reg.
12523 unsigned char OpFlag = 0;
12524 unsigned WrapperKind = X86ISD::Wrapper;
12525 CodeModel::Model M = DAG.getTarget().getCodeModel();
12527 if (Subtarget->isPICStyleRIPRel() &&
12528 (M == CodeModel::Small || M == CodeModel::Kernel))
12529 WrapperKind = X86ISD::WrapperRIP;
12530 else if (Subtarget->isPICStyleGOT())
12531 OpFlag = X86II::MO_GOTOFF;
12532 else if (Subtarget->isPICStyleStubPIC())
12533 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12535 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
12536 OpFlag);
12537 SDLoc DL(JT);
12538 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12540 // With PIC, the address is actually $g + Offset.
12541 if (OpFlag)
12542 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12543 DAG.getNode(X86ISD::GlobalBaseReg,
12544 SDLoc(), getPointerTy()),
12545 Result);
12547 return Result;
12548 }
12550 SDValue
12551 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
12552 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
12554 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12555 // global base reg.
12556 unsigned char OpFlag = 0;
12557 unsigned WrapperKind = X86ISD::Wrapper;
12558 CodeModel::Model M = DAG.getTarget().getCodeModel();
12560 if (Subtarget->isPICStyleRIPRel() &&
12561 (M == CodeModel::Small || M == CodeModel::Kernel)) {
12562 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
12563 OpFlag = X86II::MO_GOTPCREL;
12564 WrapperKind = X86ISD::WrapperRIP;
12565 } else if (Subtarget->isPICStyleGOT()) {
12566 OpFlag = X86II::MO_GOT;
12567 } else if (Subtarget->isPICStyleStubPIC()) {
12568 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
12569 } else if (Subtarget->isPICStyleStubNoDynamic()) {
12570 OpFlag = X86II::MO_DARWIN_NONLAZY;
12571 }
12573 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
12575 SDLoc DL(Op);
12576 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12578 // With PIC, the address is actually $g + Offset.
12579 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
12580 !Subtarget->is64Bit()) {
12581 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12582 DAG.getNode(X86ISD::GlobalBaseReg,
12583 SDLoc(), getPointerTy()),
12584 Result);
12585 }
12587 // For symbols that require a load from a stub to get the address, emit the
12588 // load.
12589 if (isGlobalStubReference(OpFlag))
12590 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
12591 MachinePointerInfo::getGOT(), false, false, false, 0);
12593 return Result;
12594 }
12596 SDValue
12597 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
12598 // Create the TargetBlockAddressAddress node.
12599 unsigned char OpFlags =
12600 Subtarget->ClassifyBlockAddressReference();
12601 CodeModel::Model M = DAG.getTarget().getCodeModel();
12602 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
12603 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
12604 SDLoc dl(Op);
12605 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
12606 OpFlags);
12608 if (Subtarget->isPICStyleRIPRel() &&
12609 (M == CodeModel::Small || M == CodeModel::Kernel))
12610 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12611 else
12612 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12614 // With PIC, the address is actually $g + Offset.
12615 if (isGlobalRelativeToPICBase(OpFlags)) {
12616 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12617 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12618 Result);
12619 }
12621 return Result;
12622 }
12624 SDValue
12625 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
12626 int64_t Offset, SelectionDAG &DAG) const {
12627 // Create the TargetGlobalAddress node, folding in the constant
12628 // offset if it is legal.
12629 unsigned char OpFlags =
12630 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
12631 CodeModel::Model M = DAG.getTarget().getCodeModel();
12632 SDValue Result;
12633 if (OpFlags == X86II::MO_NO_FLAG &&
12634 X86::isOffsetSuitableForCodeModel(Offset, M)) {
12635 // A direct static reference to a global.
12636 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
12637 Offset = 0;
12638 } else {
12639 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
12640 }
12642 if (Subtarget->isPICStyleRIPRel() &&
12643 (M == CodeModel::Small || M == CodeModel::Kernel))
12644 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12645 else
12646 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12648 // With PIC, the address is actually $g + Offset.
12649 if (isGlobalRelativeToPICBase(OpFlags)) {
12650 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12651 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12652 Result);
12653 }
12655 // For globals that require a load from a stub to get the address, emit the
12656 // load.
12657 if (isGlobalStubReference(OpFlags))
12658 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
12659 MachinePointerInfo::getGOT(), false, false, false, 0);
12661 // If there was a non-zero offset that we didn't fold, create an explicit
12662 // addition for it.
12663 if (Offset != 0)
12664 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
12665 DAG.getConstant(Offset, getPointerTy()));
12667 return Result;
12668 }
12670 SDValue
12671 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
12672 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
12673 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
12674 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
12675 }
12677 static SDValue
12678 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
12679 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
12680 unsigned char OperandFlags, bool LocalDynamic = false) {
12681 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12682 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12683 SDLoc dl(GA);
12684 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12685 GA->getValueType(0),
12686 GA->getOffset(),
12687 OperandFlags);
12689 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
12690 : X86ISD::TLSADDR;
12692 if (InFlag) {
12693 SDValue Ops[] = { Chain, TGA, *InFlag };
12694 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12695 } else {
12696 SDValue Ops[] = { Chain, TGA };
12697 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12698 }
12700 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
12701 MFI->setAdjustsStack(true);
12703 SDValue Flag = Chain.getValue(1);
12704 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
12705 }
12707 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
12708 static SDValue
12709 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12710 const EVT PtrVT) {
12711 SDValue InFlag;
12712 SDLoc dl(GA); // ? function entry point might be better
12713 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12714 DAG.getNode(X86ISD::GlobalBaseReg,
12715 SDLoc(), PtrVT), InFlag);
12716 InFlag = Chain.getValue(1);
12718 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
12719 }
12721 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
12722 static SDValue
12723 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12724 const EVT PtrVT) {
12725 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
12726 X86::RAX, X86II::MO_TLSGD);
12727 }
12729 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12730 SelectionDAG &DAG,
12731 const EVT PtrVT,
12732 bool is64Bit) {
12733 SDLoc dl(GA);
12735 // Get the start address of the TLS block for this module.
12736 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
12737 .getInfo<X86MachineFunctionInfo>();
12738 MFI->incNumLocalDynamicTLSAccesses();
12740 SDValue Base;
12741 if (is64Bit) {
12742 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
12743 X86II::MO_TLSLD, /*LocalDynamic=*/true);
12744 } else {
12745 SDValue InFlag;
12746 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12747 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12748 InFlag = Chain.getValue(1);
12749 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12750 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12751 }
12753 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12754 // of Base.
12756 // Build x@dtpoff.
12757 unsigned char OperandFlags = X86II::MO_DTPOFF;
12758 unsigned WrapperKind = X86ISD::Wrapper;
12759 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12760 GA->getValueType(0),
12761 GA->getOffset(), OperandFlags);
12762 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12764 // Add x@dtpoff with the base.
12765 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12766 }
12768 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12769 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12770 const EVT PtrVT, TLSModel::Model model,
12771 bool is64Bit, bool isPIC) {
12772 SDLoc dl(GA);
12774 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12775 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12776 is64Bit ? 257 : 256));
12778 SDValue ThreadPointer =
12779 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
12780 MachinePointerInfo(Ptr), false, false, false, 0);
12782 unsigned char OperandFlags = 0;
12783 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12784 // initialexec.
12785 unsigned WrapperKind = X86ISD::Wrapper;
12786 if (model == TLSModel::LocalExec) {
12787 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12788 } else if (model == TLSModel::InitialExec) {
12789 if (is64Bit) {
12790 OperandFlags = X86II::MO_GOTTPOFF;
12791 WrapperKind = X86ISD::WrapperRIP;
12792 } else {
12793 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12794 }
12795 } else {
12796 llvm_unreachable("Unexpected model");
12797 }
12799 // emit "addl x@ntpoff,%eax" (local exec)
12800 // or "addl x@indntpoff,%eax" (initial exec)
12801 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12802 SDValue TGA =
12803 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12804 GA->getOffset(), OperandFlags);
12805 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12807 if (model == TLSModel::InitialExec) {
12808 if (isPIC && !is64Bit) {
12809 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12810 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12811 Offset);
12812 }
12814 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12815 MachinePointerInfo::getGOT(), false, false, false, 0);
12816 }
12818 // The address of the thread local variable is the add of the thread
12819 // pointer with the offset of the variable.
12820 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12821 }
12823 SDValue
12824 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12826 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12827 const GlobalValue *GV = GA->getGlobal();
12829 if (Subtarget->isTargetELF()) {
12830 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12832 switch (model) {
12833 case TLSModel::GeneralDynamic:
12834 if (Subtarget->is64Bit())
12835 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
12836 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
12837 case TLSModel::LocalDynamic:
12838 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
12839 Subtarget->is64Bit());
12840 case TLSModel::InitialExec:
12841 case TLSModel::LocalExec:
12842 return LowerToTLSExecModel(
12843 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
12844 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
12845 }
12846 llvm_unreachable("Unknown TLS model.");
12847 }
12849 if (Subtarget->isTargetDarwin()) {
12850 // Darwin only has one model of TLS. Lower to that.
12851 unsigned char OpFlag = 0;
12852 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12853 X86ISD::WrapperRIP : X86ISD::Wrapper;
12855 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12856 // global base reg.
12857 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12858 !Subtarget->is64Bit();
12859 if (PIC32)
12860 OpFlag = X86II::MO_TLVP_PIC_BASE;
12861 else
12862 OpFlag = X86II::MO_TLVP;
12863 SDLoc DL(Op);
12864 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12865 GA->getValueType(0),
12866 GA->getOffset(), OpFlag);
12867 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12869 // With PIC32, the address is actually $g + Offset.
12870 if (PIC32)
12871 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12872 DAG.getNode(X86ISD::GlobalBaseReg,
12873 SDLoc(), getPointerTy()),
12874 Offset);
12876 // Lowering the machine isd will make sure everything is in the right
12877 // location.
12878 SDValue Chain = DAG.getEntryNode();
12879 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12880 SDValue Args[] = { Chain, Offset };
12881 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12883 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12884 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12885 MFI->setAdjustsStack(true);
12887 // And our return value (tls address) is in the standard call return value
12888 // location.
12889 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12890 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
12891 Chain.getValue(1));
12892 }
12894 if (Subtarget->isTargetKnownWindowsMSVC() ||
12895 Subtarget->isTargetWindowsGNU()) {
12896 // Just use the implicit TLS architecture
12897 // Need to generate someting similar to:
12898 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12899 // ; from TEB
12900 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12901 // mov rcx, qword [rdx+rcx*8]
12902 // mov eax, .tls$:tlsvar
12903 // [rax+rcx] contains the address
12904 // Windows 64bit: gs:0x58
12905 // Windows 32bit: fs:__tls_array
12907 SDLoc dl(GA);
12908 SDValue Chain = DAG.getEntryNode();
12910 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12911 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12912 // use its literal value of 0x2C.
12913 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12914 ? Type::getInt8PtrTy(*DAG.getContext(),
12915 256)
12916 : Type::getInt32PtrTy(*DAG.getContext(),
12917 257));
12919 SDValue TlsArray =
12920 Subtarget->is64Bit()
12921 ? DAG.getIntPtrConstant(0x58)
12922 : (Subtarget->isTargetWindowsGNU()
12923 ? DAG.getIntPtrConstant(0x2C)
12924 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
12926 SDValue ThreadPointer =
12927 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
12928 MachinePointerInfo(Ptr), false, false, false, 0);
12930 // Load the _tls_index variable
12931 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
12932 if (Subtarget->is64Bit())
12933 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
12934 IDX, MachinePointerInfo(), MVT::i32,
12935 false, false, false, 0);
12936 else
12937 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
12938 false, false, false, 0);
12940 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
12941 getPointerTy());
12942 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
12944 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
12945 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
12946 false, false, false, 0);
12948 // Get the offset of start of .tls section
12949 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12950 GA->getValueType(0),
12951 GA->getOffset(), X86II::MO_SECREL);
12952 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
12954 // The address of the thread local variable is the add of the thread
12955 // pointer with the offset of the variable.
12956 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
12957 }
12959 llvm_unreachable("TLS not implemented for this target.");
12960 }
12962 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12963 /// and take a 2 x i32 value to shift plus a shift amount.
12964 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12965 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12966 MVT VT = Op.getSimpleValueType();
12967 unsigned VTBits = VT.getSizeInBits();
12968 SDLoc dl(Op);
12969 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12970 SDValue ShOpLo = Op.getOperand(0);
12971 SDValue ShOpHi = Op.getOperand(1);
12972 SDValue ShAmt = Op.getOperand(2);
12973 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12974 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12975 // during isel.
12976 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12977 DAG.getConstant(VTBits - 1, MVT::i8));
12978 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12979 DAG.getConstant(VTBits - 1, MVT::i8))
12980 : DAG.getConstant(0, VT);
12982 SDValue Tmp2, Tmp3;
12983 if (Op.getOpcode() == ISD::SHL_PARTS) {
12984 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12985 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12986 } else {
12987 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12988 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12989 }
12991 // If the shift amount is larger or equal than the width of a part we can't
12992 // rely on the results of shld/shrd. Insert a test and select the appropriate
12993 // values for large shift amounts.
12994 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12995 DAG.getConstant(VTBits, MVT::i8));
12996 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12997 AndNode, DAG.getConstant(0, MVT::i8));
12999 SDValue Hi, Lo;
13000 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13001 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
13002 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
13004 if (Op.getOpcode() == ISD::SHL_PARTS) {
13005 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13006 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13007 } else {
13008 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13009 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13010 }
13012 SDValue Ops[2] = { Lo, Hi };
13013 return DAG.getMergeValues(Ops, dl);
13014 }
13016 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
13017 SelectionDAG &DAG) const {
13018 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13020 if (SrcVT.isVector())
13021 return SDValue();
13023 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
13024 "Unknown SINT_TO_FP to lower!");
13026 // These are really Legal; return the operand so the caller accepts it as
13027 // Legal.
13028 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
13029 return Op;
13030 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
13031 Subtarget->is64Bit()) {
13032 return Op;
13033 }
13035 SDLoc dl(Op);
13036 unsigned Size = SrcVT.getSizeInBits()/8;
13037 MachineFunction &MF = DAG.getMachineFunction();
13038 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
13039 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13040 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13041 StackSlot,
13042 MachinePointerInfo::getFixedStack(SSFI),
13043 false, false, 0);
13044 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
13045 }
13047 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
13048 SDValue StackSlot,
13049 SelectionDAG &DAG) const {
13050 // Build the FILD
13051 SDLoc DL(Op);
13052 SDVTList Tys;
13053 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
13054 if (useSSE)
13055 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
13056 else
13057 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
13059 unsigned ByteSize = SrcVT.getSizeInBits()/8;
13061 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
13062 MachineMemOperand *MMO;
13063 if (FI) {
13064 int SSFI = FI->getIndex();
13065 MMO =
13066 DAG.getMachineFunction()
13067 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13068 MachineMemOperand::MOLoad, ByteSize, ByteSize);
13069 } else {
13070 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
13071 StackSlot = StackSlot.getOperand(1);
13072 }
13073 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
13074 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
13075 X86ISD::FILD, DL,
13076 Tys, Ops, SrcVT, MMO);
13078 if (useSSE) {
13079 Chain = Result.getValue(1);
13080 SDValue InFlag = Result.getValue(2);
13082 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
13083 // shouldn't be necessary except that RFP cannot be live across
13084 // multiple blocks. When stackifier is fixed, they can be uncoupled.
13085 MachineFunction &MF = DAG.getMachineFunction();
13086 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
13087 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
13088 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13089 Tys = DAG.getVTList(MVT::Other);
13090 SDValue Ops[] = {
13091 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
13092 };
13093 MachineMemOperand *MMO =
13094 DAG.getMachineFunction()
13095 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13096 MachineMemOperand::MOStore, SSFISize, SSFISize);
13098 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
13099 Ops, Op.getValueType(), MMO);
13100 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
13101 MachinePointerInfo::getFixedStack(SSFI),
13102 false, false, false, 0);
13103 }
13105 return Result;
13106 }
13108 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
13109 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
13110 SelectionDAG &DAG) const {
13111 // This algorithm is not obvious. Here it is what we're trying to output:
13112 /*
13113 movq %rax, %xmm0
13114 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
13115 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
13116 #ifdef __SSE3__
13117 haddpd %xmm0, %xmm0
13118 #else
13119 pshufd $0x4e, %xmm0, %xmm1
13120 addpd %xmm1, %xmm0
13121 #endif
13122 */
13124 SDLoc dl(Op);
13125 LLVMContext *Context = DAG.getContext();
13127 // Build some magic constants.
13128 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
13129 Constant *C0 = ConstantDataVector::get(*Context, CV0);
13130 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
13132 SmallVector<Constant*,2> CV1;
13133 CV1.push_back(
13134 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13135 APInt(64, 0x4330000000000000ULL))));
13136 CV1.push_back(
13137 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13138 APInt(64, 0x4530000000000000ULL))));
13139 Constant *C1 = ConstantVector::get(CV1);
13140 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
13142 // Load the 64-bit value into an XMM register.
13143 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
13144 Op.getOperand(0));
13145 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
13146 MachinePointerInfo::getConstantPool(),
13147 false, false, false, 16);
13148 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
13149 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
13150 CLod0);
13152 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
13153 MachinePointerInfo::getConstantPool(),
13154 false, false, false, 16);
13155 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
13156 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
13157 SDValue Result;
13159 if (Subtarget->hasSSE3()) {
13160 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
13161 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
13162 } else {
13163 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
13164 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
13165 S2F, 0x4E, DAG);
13166 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
13167 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
13168 Sub);
13169 }
13171 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
13172 DAG.getIntPtrConstant(0));
13173 }
13175 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
13176 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
13177 SelectionDAG &DAG) const {
13178 SDLoc dl(Op);
13179 // FP constant to bias correct the final result.
13180 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13181 MVT::f64);
13183 // Load the 32-bit value into an XMM register.
13184 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
13185 Op.getOperand(0));
13187 // Zero out the upper parts of the register.
13188 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
13190 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13191 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
13192 DAG.getIntPtrConstant(0));
13194 // Or the load with the bias.
13195 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
13196 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13197 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13198 MVT::v2f64, Load)),
13199 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13200 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13201 MVT::v2f64, Bias)));
13202 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13203 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
13204 DAG.getIntPtrConstant(0));
13206 // Subtract the bias.
13207 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
13209 // Handle final rounding.
13210 EVT DestVT = Op.getValueType();
13212 if (DestVT.bitsLT(MVT::f64))
13213 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
13214 DAG.getIntPtrConstant(0));
13215 if (DestVT.bitsGT(MVT::f64))
13216 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
13218 // Handle final rounding.
13219 return Sub;
13220 }
13222 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
13223 SelectionDAG &DAG) const {
13224 SDValue N0 = Op.getOperand(0);
13225 MVT SVT = N0.getSimpleValueType();
13226 SDLoc dl(Op);
13228 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
13229 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
13230 "Custom UINT_TO_FP is not supported!");
13232 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
13233 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13234 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
13235 }
13237 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
13238 SelectionDAG &DAG) const {
13239 SDValue N0 = Op.getOperand(0);
13240 SDLoc dl(Op);
13242 if (Op.getValueType().isVector())
13243 return lowerUINT_TO_FP_vec(Op, DAG);
13245 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
13246 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
13247 // the optimization here.
13248 if (DAG.SignBitIsZero(N0))
13249 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
13251 MVT SrcVT = N0.getSimpleValueType();
13252 MVT DstVT = Op.getSimpleValueType();
13253 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
13254 return LowerUINT_TO_FP_i64(Op, DAG);
13255 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
13256 return LowerUINT_TO_FP_i32(Op, DAG);
13257 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
13258 return SDValue();
13260 // Make a 64-bit buffer, and use it to build an FILD.
13261 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
13262 if (SrcVT == MVT::i32) {
13263 SDValue WordOff = DAG.getConstant(4, getPointerTy());
13264 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
13265 getPointerTy(), StackSlot, WordOff);
13266 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13267 StackSlot, MachinePointerInfo(),
13268 false, false, 0);
13269 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
13270 OffsetSlot, MachinePointerInfo(),
13271 false, false, 0);
13272 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
13273 return Fild;
13274 }
13276 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
13277 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13278 StackSlot, MachinePointerInfo(),
13279 false, false, 0);
13280 // For i64 source, we need to add the appropriate power of 2 if the input
13281 // was negative. This is the same as the optimization in
13282 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
13283 // we must be careful to do the computation in x87 extended precision, not
13284 // in SSE. (The generic code can't know it's OK to do this, or how to.)
13285 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
13286 MachineMemOperand *MMO =
13287 DAG.getMachineFunction()
13288 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13289 MachineMemOperand::MOLoad, 8, 8);
13291 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
13292 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
13293 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
13294 MVT::i64, MMO);
13296 APInt FF(32, 0x5F800000ULL);
13298 // Check whether the sign bit is set.
13299 SDValue SignSet = DAG.getSetCC(dl,
13300 getSetCCResultType(*DAG.getContext(), MVT::i64),
13301 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
13302 ISD::SETLT);
13304 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
13305 SDValue FudgePtr = DAG.getConstantPool(
13306 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
13307 getPointerTy());
13309 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
13310 SDValue Zero = DAG.getIntPtrConstant(0);
13311 SDValue Four = DAG.getIntPtrConstant(4);
13312 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
13313 Zero, Four);
13314 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
13316 // Load the value out, extending it from f32 to f80.
13317 // FIXME: Avoid the extend by constructing the right constant pool?
13318 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
13319 FudgePtr, MachinePointerInfo::getConstantPool(),
13320 MVT::f32, false, false, false, 4);
13321 // Extend everything to 80 bits to force it to be done on x87.
13322 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
13323 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
13324 }
13326 std::pair<SDValue,SDValue>
13327 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
13328 bool IsSigned, bool IsReplace) const {
13329 SDLoc DL(Op);
13331 EVT DstTy = Op.getValueType();
13333 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
13334 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
13335 DstTy = MVT::i64;
13336 }
13338 assert(DstTy.getSimpleVT() <= MVT::i64 &&
13339 DstTy.getSimpleVT() >= MVT::i16 &&
13340 "Unknown FP_TO_INT to lower!");
13342 // These are really Legal.
13343 if (DstTy == MVT::i32 &&
13344 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13345 return std::make_pair(SDValue(), SDValue());
13346 if (Subtarget->is64Bit() &&
13347 DstTy == MVT::i64 &&
13348 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13349 return std::make_pair(SDValue(), SDValue());
13351 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
13352 // stack slot, or into the FTOL runtime function.
13353 MachineFunction &MF = DAG.getMachineFunction();
13354 unsigned MemSize = DstTy.getSizeInBits()/8;
13355 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13356 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13358 unsigned Opc;
13359 if (!IsSigned && isIntegerTypeFTOL(DstTy))
13360 Opc = X86ISD::WIN_FTOL;
13361 else
13362 switch (DstTy.getSimpleVT().SimpleTy) {
13363 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
13364 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
13365 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
13366 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
13367 }
13369 SDValue Chain = DAG.getEntryNode();
13370 SDValue Value = Op.getOperand(0);
13371 EVT TheVT = Op.getOperand(0).getValueType();
13372 // FIXME This causes a redundant load/store if the SSE-class value is already
13373 // in memory, such as if it is on the callstack.
13374 if (isScalarFPTypeInSSEReg(TheVT)) {
13375 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
13376 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
13377 MachinePointerInfo::getFixedStack(SSFI),
13378 false, false, 0);
13379 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
13380 SDValue Ops[] = {
13381 Chain, StackSlot, DAG.getValueType(TheVT)
13382 };
13384 MachineMemOperand *MMO =
13385 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13386 MachineMemOperand::MOLoad, MemSize, MemSize);
13387 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
13388 Chain = Value.getValue(1);
13389 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13390 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13391 }
13393 MachineMemOperand *MMO =
13394 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13395 MachineMemOperand::MOStore, MemSize, MemSize);
13397 if (Opc != X86ISD::WIN_FTOL) {
13398 // Build the FP_TO_INT*_IN_MEM
13399 SDValue Ops[] = { Chain, Value, StackSlot };
13400 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13401 Ops, DstTy, MMO);
13402 return std::make_pair(FIST, StackSlot);
13403 } else {
13404 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
13405 DAG.getVTList(MVT::Other, MVT::Glue),
13406 Chain, Value);
13407 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
13408 MVT::i32, ftol.getValue(1));
13409 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
13410 MVT::i32, eax.getValue(2));
13411 SDValue Ops[] = { eax, edx };
13412 SDValue pair = IsReplace
13413 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
13414 : DAG.getMergeValues(Ops, DL);
13415 return std::make_pair(pair, SDValue());
13416 }
13417 }
13419 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
13420 const X86Subtarget *Subtarget) {
13421 MVT VT = Op->getSimpleValueType(0);
13422 SDValue In = Op->getOperand(0);
13423 MVT InVT = In.getSimpleValueType();
13424 SDLoc dl(Op);
13426 // Optimize vectors in AVX mode:
13427 //
13428 // v8i16 -> v8i32
13429 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
13430 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
13431 // Concat upper and lower parts.
13432 //
13433 // v4i32 -> v4i64
13434 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
13435 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
13436 // Concat upper and lower parts.
13437 //
13439 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
13440 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
13441 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
13442 return SDValue();
13444 if (Subtarget->hasInt256())
13445 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
13447 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
13448 SDValue Undef = DAG.getUNDEF(InVT);
13449 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
13450 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13451 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13453 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
13454 VT.getVectorNumElements()/2);
13456 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
13457 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
13459 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13460 }
13462 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
13463 SelectionDAG &DAG) {
13464 MVT VT = Op->getSimpleValueType(0);
13465 SDValue In = Op->getOperand(0);
13466 MVT InVT = In.getSimpleValueType();
13467 SDLoc DL(Op);
13468 unsigned int NumElts = VT.getVectorNumElements();
13469 if (NumElts != 8 && NumElts != 16)
13470 return SDValue();
13472 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13473 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
13475 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
13476 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13477 // Now we have only mask extension
13478 assert(InVT.getVectorElementType() == MVT::i1);
13479 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
13480 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
13481 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
13482 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13483 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
13484 MachinePointerInfo::getConstantPool(),
13485 false, false, false, Alignment);
13487 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
13488 if (VT.is512BitVector())
13489 return Brcst;
13490 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
13491 }
13493 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13494 SelectionDAG &DAG) {
13495 if (Subtarget->hasFp256()) {
13496 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
13497 if (Res.getNode())
13498 return Res;
13499 }
13501 return SDValue();
13502 }
13504 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13505 SelectionDAG &DAG) {
13506 SDLoc DL(Op);
13507 MVT VT = Op.getSimpleValueType();
13508 SDValue In = Op.getOperand(0);
13509 MVT SVT = In.getSimpleValueType();
13511 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
13512 return LowerZERO_EXTEND_AVX512(Op, DAG);
13514 if (Subtarget->hasFp256()) {
13515 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
13516 if (Res.getNode())
13517 return Res;
13518 }
13520 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
13521 VT.getVectorNumElements() != SVT.getVectorNumElements());
13522 return SDValue();
13523 }
13525 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
13526 SDLoc DL(Op);
13527 MVT VT = Op.getSimpleValueType();
13528 SDValue In = Op.getOperand(0);
13529 MVT InVT = In.getSimpleValueType();
13531 if (VT == MVT::i1) {
13532 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
13533 "Invalid scalar TRUNCATE operation");
13534 if (InVT.getSizeInBits() >= 32)
13535 return SDValue();
13536 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
13537 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
13538 }
13539 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
13540 "Invalid TRUNCATE operation");
13542 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
13543 if (VT.getVectorElementType().getSizeInBits() >=8)
13544 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13546 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13547 unsigned NumElts = InVT.getVectorNumElements();
13548 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
13549 if (InVT.getSizeInBits() < 512) {
13550 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
13551 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13552 InVT = ExtVT;
13553 }
13555 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
13556 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
13557 SDValue CP = DAG.getConstantPool(C, getPointerTy());
13558 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13559 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
13560 MachinePointerInfo::getConstantPool(),
13561 false, false, false, Alignment);
13562 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
13563 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
13564 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
13565 }
13567 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13568 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13569 if (Subtarget->hasInt256()) {
13570 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13571 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
13572 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13573 ShufMask);
13574 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13575 DAG.getIntPtrConstant(0));
13576 }
13578 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13579 DAG.getIntPtrConstant(0));
13580 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13581 DAG.getIntPtrConstant(2));
13582 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
13583 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
13584 static const int ShufMask[] = {0, 2, 4, 6};
13585 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13586 }
13588 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13589 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13590 if (Subtarget->hasInt256()) {
13591 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
13593 SmallVector<SDValue,32> pshufbMask;
13594 for (unsigned i = 0; i < 2; ++i) {
13595 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
13596 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
13597 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
13598 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
13599 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
13600 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
13601 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
13602 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
13603 for (unsigned j = 0; j < 8; ++j)
13604 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
13605 }
13606 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13607 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13608 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
13610 static const int ShufMask[] = {0, 2, -1, -1};
13611 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13612 &ShufMask[0]);
13613 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13614 DAG.getIntPtrConstant(0));
13615 return DAG.getNode(ISD::BITCAST, DL, VT, In);
13616 }
13618 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13619 DAG.getIntPtrConstant(0));
13621 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13622 DAG.getIntPtrConstant(4));
13624 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
13625 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
13627 // The PSHUFB mask:
13628 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13629 -1, -1, -1, -1, -1, -1, -1, -1};
13631 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13632 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13633 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13635 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
13636 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
13638 // The MOVLHPS Mask:
13639 static const int ShufMask2[] = {0, 1, 4, 5};
13640 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13641 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
13642 }
13644 // Handle truncation of V256 to V128 using shuffles.
13645 if (!VT.is128BitVector() || !InVT.is256BitVector())
13646 return SDValue();
13648 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13650 unsigned NumElems = VT.getVectorNumElements();
13651 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13653 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13654 // Prepare truncation shuffle mask
13655 for (unsigned i = 0; i != NumElems; ++i)
13656 MaskVec[i] = i * 2;
13657 SDValue V = DAG.getVectorShuffle(NVT, DL,
13658 DAG.getNode(ISD::BITCAST, DL, NVT, In),
13659 DAG.getUNDEF(NVT), &MaskVec[0]);
13660 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13661 DAG.getIntPtrConstant(0));
13662 }
13664 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13665 SelectionDAG &DAG) const {
13666 assert(!Op.getSimpleValueType().isVector());
13668 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13669 /*IsSigned=*/ true, /*IsReplace=*/ false);
13670 SDValue FIST = Vals.first, StackSlot = Vals.second;
13671 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13672 if (!FIST.getNode()) return Op;
13674 if (StackSlot.getNode())
13675 // Load the result.
13676 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13677 FIST, StackSlot, MachinePointerInfo(),
13678 false, false, false, 0);
13680 // The node is the result.
13681 return FIST;
13682 }
13684 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13685 SelectionDAG &DAG) const {
13686 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13687 /*IsSigned=*/ false, /*IsReplace=*/ false);
13688 SDValue FIST = Vals.first, StackSlot = Vals.second;
13689 assert(FIST.getNode() && "Unexpected failure");
13691 if (StackSlot.getNode())
13692 // Load the result.
13693 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13694 FIST, StackSlot, MachinePointerInfo(),
13695 false, false, false, 0);
13697 // The node is the result.
13698 return FIST;
13699 }
13701 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13702 SDLoc DL(Op);
13703 MVT VT = Op.getSimpleValueType();
13704 SDValue In = Op.getOperand(0);
13705 MVT SVT = In.getSimpleValueType();
13707 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13709 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13710 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13711 In, DAG.getUNDEF(SVT)));
13712 }
13714 /// The only differences between FABS and FNEG are the mask and the logic op.
13715 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
13716 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13717 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13718 "Wrong opcode for lowering FABS or FNEG.");
13720 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13722 // If this is a FABS and it has an FNEG user, bail out to fold the combination
13723 // into an FNABS. We'll lower the FABS after that if it is still in use.
13724 if (IsFABS)
13725 for (SDNode *User : Op->uses())
13726 if (User->getOpcode() == ISD::FNEG)
13727 return Op;
13729 SDValue Op0 = Op.getOperand(0);
13730 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
13732 SDLoc dl(Op);
13733 MVT VT = Op.getSimpleValueType();
13734 // Assume scalar op for initialization; update for vector if needed.
13735 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
13736 // generate a 16-byte vector constant and logic op even for the scalar case.
13737 // Using a 16-byte mask allows folding the load of the mask with
13738 // the logic op, so it can save (~4 bytes) on code size.
13739 MVT EltVT = VT;
13740 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
13741 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13742 // decide if we should generate a 16-byte constant mask when we only need 4 or
13743 // 8 bytes for the scalar case.
13744 if (VT.isVector()) {
13745 EltVT = VT.getVectorElementType();
13746 NumElts = VT.getVectorNumElements();
13747 }
13749 unsigned EltBits = EltVT.getSizeInBits();
13750 LLVMContext *Context = DAG.getContext();
13751 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13752 APInt MaskElt =
13753 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13754 Constant *C = ConstantInt::get(*Context, MaskElt);
13755 C = ConstantVector::getSplat(NumElts, C);
13756 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13757 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
13758 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13759 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
13760 MachinePointerInfo::getConstantPool(),
13761 false, false, false, Alignment);
13763 if (VT.isVector()) {
13764 // For a vector, cast operands to a vector type, perform the logic op,
13765 // and cast the result back to the original value type.
13766 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
13767 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
13768 SDValue Operand = IsFNABS ?
13769 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
13770 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
13771 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
13772 return DAG.getNode(ISD::BITCAST, dl, VT,
13773 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
13774 }
13776 // If not vector, then scalar.
13777 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
13778 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
13779 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
13780 }
13782 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13783 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13784 LLVMContext *Context = DAG.getContext();
13785 SDValue Op0 = Op.getOperand(0);
13786 SDValue Op1 = Op.getOperand(1);
13787 SDLoc dl(Op);
13788 MVT VT = Op.getSimpleValueType();
13789 MVT SrcVT = Op1.getSimpleValueType();
13791 // If second operand is smaller, extend it first.
13792 if (SrcVT.bitsLT(VT)) {
13793 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13794 SrcVT = VT;
13795 }
13796 // And if it is bigger, shrink it first.
13797 if (SrcVT.bitsGT(VT)) {
13798 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
13799 SrcVT = VT;
13800 }
13802 // At this point the operands and the result should have the same
13803 // type, and that won't be f80 since that is not custom lowered.
13805 // First get the sign bit of second operand.
13806 SmallVector<Constant*,4> CV;
13807 if (SrcVT == MVT::f64) {
13808 const fltSemantics &Sem = APFloat::IEEEdouble;
13809 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
13810 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
13811 } else {
13812 const fltSemantics &Sem = APFloat::IEEEsingle;
13813 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
13814 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13815 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13816 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13817 }
13818 Constant *C = ConstantVector::get(CV);
13819 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
13820 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
13821 MachinePointerInfo::getConstantPool(),
13822 false, false, false, 16);
13823 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
13825 // Shift sign bit right or left if the two operands have different types.
13826 if (SrcVT.bitsGT(VT)) {
13827 // Op0 is MVT::f32, Op1 is MVT::f64.
13828 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
13829 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
13830 DAG.getConstant(32, MVT::i32));
13831 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
13832 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
13833 DAG.getIntPtrConstant(0));
13834 }
13836 // Clear first operand sign bit.
13837 CV.clear();
13838 if (VT == MVT::f64) {
13839 const fltSemantics &Sem = APFloat::IEEEdouble;
13840 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
13841 APInt(64, ~(1ULL << 63)))));
13842 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
13843 } else {
13844 const fltSemantics &Sem = APFloat::IEEEsingle;
13845 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
13846 APInt(32, ~(1U << 31)))));
13847 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13848 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13849 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13850 }
13851 C = ConstantVector::get(CV);
13852 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
13853 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
13854 MachinePointerInfo::getConstantPool(),
13855 false, false, false, 16);
13856 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
13858 // Or the value with the sign bit.
13859 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
13860 }
13862 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13863 SDValue N0 = Op.getOperand(0);
13864 SDLoc dl(Op);
13865 MVT VT = Op.getSimpleValueType();
13867 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13868 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13869 DAG.getConstant(1, VT));
13870 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
13871 }
13873 // Check whether an OR'd tree is PTEST-able.
13874 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13875 SelectionDAG &DAG) {
13876 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13878 if (!Subtarget->hasSSE41())
13879 return SDValue();
13881 if (!Op->hasOneUse())
13882 return SDValue();
13884 SDNode *N = Op.getNode();
13885 SDLoc DL(N);
13887 SmallVector<SDValue, 8> Opnds;
13888 DenseMap<SDValue, unsigned> VecInMap;
13889 SmallVector<SDValue, 8> VecIns;
13890 EVT VT = MVT::Other;
13892 // Recognize a special case where a vector is casted into wide integer to
13893 // test all 0s.
13894 Opnds.push_back(N->getOperand(0));
13895 Opnds.push_back(N->getOperand(1));
13897 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13898 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13899 // BFS traverse all OR'd operands.
13900 if (I->getOpcode() == ISD::OR) {
13901 Opnds.push_back(I->getOperand(0));
13902 Opnds.push_back(I->getOperand(1));
13903 // Re-evaluate the number of nodes to be traversed.
13904 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13905 continue;
13906 }
13908 // Quit if a non-EXTRACT_VECTOR_ELT
13909 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13910 return SDValue();
13912 // Quit if without a constant index.
13913 SDValue Idx = I->getOperand(1);
13914 if (!isa<ConstantSDNode>(Idx))
13915 return SDValue();
13917 SDValue ExtractedFromVec = I->getOperand(0);
13918 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13919 if (M == VecInMap.end()) {
13920 VT = ExtractedFromVec.getValueType();
13921 // Quit if not 128/256-bit vector.
13922 if (!VT.is128BitVector() && !VT.is256BitVector())
13923 return SDValue();
13924 // Quit if not the same type.
13925 if (VecInMap.begin() != VecInMap.end() &&
13926 VT != VecInMap.begin()->first.getValueType())
13927 return SDValue();
13928 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13929 VecIns.push_back(ExtractedFromVec);
13930 }
13931 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13932 }
13934 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13935 "Not extracted from 128-/256-bit vector.");
13937 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13939 for (DenseMap<SDValue, unsigned>::const_iterator
13940 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13941 // Quit if not all elements are used.
13942 if (I->second != FullMask)
13943 return SDValue();
13944 }
13946 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13948 // Cast all vectors into TestVT for PTEST.
13949 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13950 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
13952 // If more than one full vectors are evaluated, OR them first before PTEST.
13953 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13954 // Each iteration will OR 2 nodes and append the result until there is only
13955 // 1 node left, i.e. the final OR'd value of all vectors.
13956 SDValue LHS = VecIns[Slot];
13957 SDValue RHS = VecIns[Slot + 1];
13958 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13959 }
13961 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13962 VecIns.back(), VecIns.back());
13963 }
13965 /// \brief return true if \c Op has a use that doesn't just read flags.
13966 static bool hasNonFlagsUse(SDValue Op) {
13967 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13968 ++UI) {
13969 SDNode *User = *UI;
13970 unsigned UOpNo = UI.getOperandNo();
13971 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13972 // Look pass truncate.
13973 UOpNo = User->use_begin().getOperandNo();
13974 User = *User->use_begin();
13975 }
13977 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13978 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13979 return true;
13980 }
13981 return false;
13982 }
13984 /// Emit nodes that will be selected as "test Op0,Op0", or something
13985 /// equivalent.
13986 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13987 SelectionDAG &DAG) const {
13988 if (Op.getValueType() == MVT::i1)
13989 // KORTEST instruction should be selected
13990 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13991 DAG.getConstant(0, Op.getValueType()));
13993 // CF and OF aren't always set the way we want. Determine which
13994 // of these we need.
13995 bool NeedCF = false;
13996 bool NeedOF = false;
13997 switch (X86CC) {
13998 default: break;
13999 case X86::COND_A: case X86::COND_AE:
14000 case X86::COND_B: case X86::COND_BE:
14001 NeedCF = true;
14002 break;
14003 case X86::COND_G: case X86::COND_GE:
14004 case X86::COND_L: case X86::COND_LE:
14005 case X86::COND_O: case X86::COND_NO: {
14006 // Check if we really need to set the
14007 // Overflow flag. If NoSignedWrap is present
14008 // that is not actually needed.
14009 switch (Op->getOpcode()) {
14010 case ISD::ADD:
14011 case ISD::SUB:
14012 case ISD::MUL:
14013 case ISD::SHL: {
14014 const BinaryWithFlagsSDNode *BinNode =
14015 cast<BinaryWithFlagsSDNode>(Op.getNode());
14016 if (BinNode->hasNoSignedWrap())
14017 break;
14018 }
14019 default:
14020 NeedOF = true;
14021 break;
14022 }
14023 break;
14024 }
14025 }
14026 // See if we can use the EFLAGS value from the operand instead of
14027 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
14028 // we prove that the arithmetic won't overflow, we can't use OF or CF.
14029 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
14030 // Emit a CMP with 0, which is the TEST pattern.
14031 //if (Op.getValueType() == MVT::i1)
14032 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
14033 // DAG.getConstant(0, MVT::i1));
14034 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14035 DAG.getConstant(0, Op.getValueType()));
14036 }
14037 unsigned Opcode = 0;
14038 unsigned NumOperands = 0;
14040 // Truncate operations may prevent the merge of the SETCC instruction
14041 // and the arithmetic instruction before it. Attempt to truncate the operands
14042 // of the arithmetic instruction and use a reduced bit-width instruction.
14043 bool NeedTruncation = false;
14044 SDValue ArithOp = Op;
14045 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
14046 SDValue Arith = Op->getOperand(0);
14047 // Both the trunc and the arithmetic op need to have one user each.
14048 if (Arith->hasOneUse())
14049 switch (Arith.getOpcode()) {
14050 default: break;
14051 case ISD::ADD:
14052 case ISD::SUB:
14053 case ISD::AND:
14054 case ISD::OR:
14055 case ISD::XOR: {
14056 NeedTruncation = true;
14057 ArithOp = Arith;
14058 }
14059 }
14060 }
14062 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
14063 // which may be the result of a CAST. We use the variable 'Op', which is the
14064 // non-casted variable when we check for possible users.
14065 switch (ArithOp.getOpcode()) {
14066 case ISD::ADD:
14067 // Due to an isel shortcoming, be conservative if this add is likely to be
14068 // selected as part of a load-modify-store instruction. When the root node
14069 // in a match is a store, isel doesn't know how to remap non-chain non-flag
14070 // uses of other nodes in the match, such as the ADD in this case. This
14071 // leads to the ADD being left around and reselected, with the result being
14072 // two adds in the output. Alas, even if none our users are stores, that
14073 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
14074 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
14075 // climbing the DAG back to the root, and it doesn't seem to be worth the
14076 // effort.
14077 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14078 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14079 if (UI->getOpcode() != ISD::CopyToReg &&
14080 UI->getOpcode() != ISD::SETCC &&
14081 UI->getOpcode() != ISD::STORE)
14082 goto default_case;
14084 if (ConstantSDNode *C =
14085 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
14086 // An add of one will be selected as an INC.
14087 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
14088 Opcode = X86ISD::INC;
14089 NumOperands = 1;
14090 break;
14091 }
14093 // An add of negative one (subtract of one) will be selected as a DEC.
14094 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
14095 Opcode = X86ISD::DEC;
14096 NumOperands = 1;
14097 break;
14098 }
14099 }
14101 // Otherwise use a regular EFLAGS-setting add.
14102 Opcode = X86ISD::ADD;
14103 NumOperands = 2;
14104 break;
14105 case ISD::SHL:
14106 case ISD::SRL:
14107 // If we have a constant logical shift that's only used in a comparison
14108 // against zero turn it into an equivalent AND. This allows turning it into
14109 // a TEST instruction later.
14110 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
14111 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
14112 EVT VT = Op.getValueType();
14113 unsigned BitWidth = VT.getSizeInBits();
14114 unsigned ShAmt = Op->getConstantOperandVal(1);
14115 if (ShAmt >= BitWidth) // Avoid undefined shifts.
14116 break;
14117 APInt Mask = ArithOp.getOpcode() == ISD::SRL
14118 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
14119 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
14120 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
14121 break;
14122 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
14123 DAG.getConstant(Mask, VT));
14124 DAG.ReplaceAllUsesWith(Op, New);
14125 Op = New;
14126 }
14127 break;
14129 case ISD::AND:
14130 // If the primary and result isn't used, don't bother using X86ISD::AND,
14131 // because a TEST instruction will be better.
14132 if (!hasNonFlagsUse(Op))
14133 break;
14134 // FALL THROUGH
14135 case ISD::SUB:
14136 case ISD::OR:
14137 case ISD::XOR:
14138 // Due to the ISEL shortcoming noted above, be conservative if this op is
14139 // likely to be selected as part of a load-modify-store instruction.
14140 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14141 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14142 if (UI->getOpcode() == ISD::STORE)
14143 goto default_case;
14145 // Otherwise use a regular EFLAGS-setting instruction.
14146 switch (ArithOp.getOpcode()) {
14147 default: llvm_unreachable("unexpected operator!");
14148 case ISD::SUB: Opcode = X86ISD::SUB; break;
14149 case ISD::XOR: Opcode = X86ISD::XOR; break;
14150 case ISD::AND: Opcode = X86ISD::AND; break;
14151 case ISD::OR: {
14152 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
14153 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
14154 if (EFLAGS.getNode())
14155 return EFLAGS;
14156 }
14157 Opcode = X86ISD::OR;
14158 break;
14159 }
14160 }
14162 NumOperands = 2;
14163 break;
14164 case X86ISD::ADD:
14165 case X86ISD::SUB:
14166 case X86ISD::INC:
14167 case X86ISD::DEC:
14168 case X86ISD::OR:
14169 case X86ISD::XOR:
14170 case X86ISD::AND:
14171 return SDValue(Op.getNode(), 1);
14172 default:
14173 default_case:
14174 break;
14175 }
14177 // If we found that truncation is beneficial, perform the truncation and
14178 // update 'Op'.
14179 if (NeedTruncation) {
14180 EVT VT = Op.getValueType();
14181 SDValue WideVal = Op->getOperand(0);
14182 EVT WideVT = WideVal.getValueType();
14183 unsigned ConvertedOp = 0;
14184 // Use a target machine opcode to prevent further DAGCombine
14185 // optimizations that may separate the arithmetic operations
14186 // from the setcc node.
14187 switch (WideVal.getOpcode()) {
14188 default: break;
14189 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
14190 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
14191 case ISD::AND: ConvertedOp = X86ISD::AND; break;
14192 case ISD::OR: ConvertedOp = X86ISD::OR; break;
14193 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
14194 }
14196 if (ConvertedOp) {
14197 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14198 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
14199 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
14200 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
14201 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
14202 }
14203 }
14204 }
14206 if (Opcode == 0)
14207 // Emit a CMP with 0, which is the TEST pattern.
14208 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14209 DAG.getConstant(0, Op.getValueType()));
14211 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14212 SmallVector<SDValue, 4> Ops;
14213 for (unsigned i = 0; i != NumOperands; ++i)
14214 Ops.push_back(Op.getOperand(i));
14216 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
14217 DAG.ReplaceAllUsesWith(Op, New);
14218 return SDValue(New.getNode(), 1);
14219 }
14221 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
14222 /// equivalent.
14223 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
14224 SDLoc dl, SelectionDAG &DAG) const {
14225 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
14226 if (C->getAPIntValue() == 0)
14227 return EmitTest(Op0, X86CC, dl, DAG);
14229 if (Op0.getValueType() == MVT::i1)
14230 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
14231 }
14233 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
14234 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
14235 // Do the comparison at i32 if it's smaller, besides the Atom case.
14236 // This avoids subregister aliasing issues. Keep the smaller reference
14237 // if we're optimizing for size, however, as that'll allow better folding
14238 // of memory operations.
14239 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
14240 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
14241 AttributeSet::FunctionIndex, Attribute::MinSize) &&
14242 !Subtarget->isAtom()) {
14243 unsigned ExtendOp =
14244 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
14245 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
14246 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
14247 }
14248 // Use SUB instead of CMP to enable CSE between SUB and CMP.
14249 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
14250 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
14251 Op0, Op1);
14252 return SDValue(Sub.getNode(), 1);
14253 }
14254 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
14255 }
14257 /// Convert a comparison if required by the subtarget.
14258 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
14259 SelectionDAG &DAG) const {
14260 // If the subtarget does not support the FUCOMI instruction, floating-point
14261 // comparisons have to be converted.
14262 if (Subtarget->hasCMov() ||
14263 Cmp.getOpcode() != X86ISD::CMP ||
14264 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
14265 !Cmp.getOperand(1).getValueType().isFloatingPoint())
14266 return Cmp;
14268 // The instruction selector will select an FUCOM instruction instead of
14269 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
14270 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
14271 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
14272 SDLoc dl(Cmp);
14273 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
14274 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
14275 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
14276 DAG.getConstant(8, MVT::i8));
14277 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
14278 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
14279 }
14281 static bool isAllOnes(SDValue V) {
14282 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
14283 return C && C->isAllOnesValue();
14284 }
14286 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
14287 /// if it's possible.
14288 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
14289 SDLoc dl, SelectionDAG &DAG) const {
14290 SDValue Op0 = And.getOperand(0);
14291 SDValue Op1 = And.getOperand(1);
14292 if (Op0.getOpcode() == ISD::TRUNCATE)
14293 Op0 = Op0.getOperand(0);
14294 if (Op1.getOpcode() == ISD::TRUNCATE)
14295 Op1 = Op1.getOperand(0);
14297 SDValue LHS, RHS;
14298 if (Op1.getOpcode() == ISD::SHL)
14299 std::swap(Op0, Op1);
14300 if (Op0.getOpcode() == ISD::SHL) {
14301 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
14302 if (And00C->getZExtValue() == 1) {
14303 // If we looked past a truncate, check that it's only truncating away
14304 // known zeros.
14305 unsigned BitWidth = Op0.getValueSizeInBits();
14306 unsigned AndBitWidth = And.getValueSizeInBits();
14307 if (BitWidth > AndBitWidth) {
14308 APInt Zeros, Ones;
14309 DAG.computeKnownBits(Op0, Zeros, Ones);
14310 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
14311 return SDValue();
14312 }
14313 LHS = Op1;
14314 RHS = Op0.getOperand(1);
14315 }
14316 } else if (Op1.getOpcode() == ISD::Constant) {
14317 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
14318 uint64_t AndRHSVal = AndRHS->getZExtValue();
14319 SDValue AndLHS = Op0;
14321 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
14322 LHS = AndLHS.getOperand(0);
14323 RHS = AndLHS.getOperand(1);
14324 }
14326 // Use BT if the immediate can't be encoded in a TEST instruction.
14327 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
14328 LHS = AndLHS;
14329 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
14330 }
14331 }
14333 if (LHS.getNode()) {
14334 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
14335 // instruction. Since the shift amount is in-range-or-undefined, we know
14336 // that doing a bittest on the i32 value is ok. We extend to i32 because
14337 // the encoding for the i16 version is larger than the i32 version.
14338 // Also promote i16 to i32 for performance / code size reason.
14339 if (LHS.getValueType() == MVT::i8 ||
14340 LHS.getValueType() == MVT::i16)
14341 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
14343 // If the operand types disagree, extend the shift amount to match. Since
14344 // BT ignores high bits (like shifts) we can use anyextend.
14345 if (LHS.getValueType() != RHS.getValueType())
14346 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
14348 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
14349 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
14350 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14351 DAG.getConstant(Cond, MVT::i8), BT);
14352 }
14354 return SDValue();
14355 }
14357 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
14358 /// mask CMPs.
14359 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
14360 SDValue &Op1) {
14361 unsigned SSECC;
14362 bool Swap = false;
14364 // SSE Condition code mapping:
14365 // 0 - EQ
14366 // 1 - LT
14367 // 2 - LE
14368 // 3 - UNORD
14369 // 4 - NEQ
14370 // 5 - NLT
14371 // 6 - NLE
14372 // 7 - ORD
14373 switch (SetCCOpcode) {
14374 default: llvm_unreachable("Unexpected SETCC condition");
14375 case ISD::SETOEQ:
14376 case ISD::SETEQ: SSECC = 0; break;
14377 case ISD::SETOGT:
14378 case ISD::SETGT: Swap = true; // Fallthrough
14379 case ISD::SETLT:
14380 case ISD::SETOLT: SSECC = 1; break;
14381 case ISD::SETOGE:
14382 case ISD::SETGE: Swap = true; // Fallthrough
14383 case ISD::SETLE:
14384 case ISD::SETOLE: SSECC = 2; break;
14385 case ISD::SETUO: SSECC = 3; break;
14386 case ISD::SETUNE:
14387 case ISD::SETNE: SSECC = 4; break;
14388 case ISD::SETULE: Swap = true; // Fallthrough
14389 case ISD::SETUGE: SSECC = 5; break;
14390 case ISD::SETULT: Swap = true; // Fallthrough
14391 case ISD::SETUGT: SSECC = 6; break;
14392 case ISD::SETO: SSECC = 7; break;
14393 case ISD::SETUEQ:
14394 case ISD::SETONE: SSECC = 8; break;
14395 }
14396 if (Swap)
14397 std::swap(Op0, Op1);
14399 return SSECC;
14400 }
14402 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
14403 // ones, and then concatenate the result back.
14404 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
14405 MVT VT = Op.getSimpleValueType();
14407 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
14408 "Unsupported value type for operation");
14410 unsigned NumElems = VT.getVectorNumElements();
14411 SDLoc dl(Op);
14412 SDValue CC = Op.getOperand(2);
14414 // Extract the LHS vectors
14415 SDValue LHS = Op.getOperand(0);
14416 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14417 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14419 // Extract the RHS vectors
14420 SDValue RHS = Op.getOperand(1);
14421 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14422 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14424 // Issue the operation on the smaller types and concatenate the result back
14425 MVT EltVT = VT.getVectorElementType();
14426 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14427 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14428 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
14429 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
14430 }
14432 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14433 const X86Subtarget *Subtarget) {
14434 SDValue Op0 = Op.getOperand(0);
14435 SDValue Op1 = Op.getOperand(1);
14436 SDValue CC = Op.getOperand(2);
14437 MVT VT = Op.getSimpleValueType();
14438 SDLoc dl(Op);
14440 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
14441 Op.getValueType().getScalarType() == MVT::i1 &&
14442 "Cannot set masked compare for this operation");
14444 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14445 unsigned Opc = 0;
14446 bool Unsigned = false;
14447 bool Swap = false;
14448 unsigned SSECC;
14449 switch (SetCCOpcode) {
14450 default: llvm_unreachable("Unexpected SETCC condition");
14451 case ISD::SETNE: SSECC = 4; break;
14452 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14453 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14454 case ISD::SETLT: Swap = true; //fall-through
14455 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14456 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14457 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14458 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14459 case ISD::SETULE: Unsigned = true; //fall-through
14460 case ISD::SETLE: SSECC = 2; break;
14461 }
14463 if (Swap)
14464 std::swap(Op0, Op1);
14465 if (Opc)
14466 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14467 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14468 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14469 DAG.getConstant(SSECC, MVT::i8));
14470 }
14472 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14473 /// operand \p Op1. If non-trivial (for example because it's not constant)
14474 /// return an empty value.
14475 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14476 {
14477 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14478 if (!BV)
14479 return SDValue();
14481 MVT VT = Op1.getSimpleValueType();
14482 MVT EVT = VT.getVectorElementType();
14483 unsigned n = VT.getVectorNumElements();
14484 SmallVector<SDValue, 8> ULTOp1;
14486 for (unsigned i = 0; i < n; ++i) {
14487 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14488 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
14489 return SDValue();
14491 // Avoid underflow.
14492 APInt Val = Elt->getAPIntValue();
14493 if (Val == 0)
14494 return SDValue();
14496 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
14497 }
14499 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14500 }
14502 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14503 SelectionDAG &DAG) {
14504 SDValue Op0 = Op.getOperand(0);
14505 SDValue Op1 = Op.getOperand(1);
14506 SDValue CC = Op.getOperand(2);
14507 MVT VT = Op.getSimpleValueType();
14508 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14509 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14510 SDLoc dl(Op);
14512 if (isFP) {
14513 #ifndef NDEBUG
14514 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14515 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14516 #endif
14518 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14519 unsigned Opc = X86ISD::CMPP;
14520 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14521 assert(VT.getVectorNumElements() <= 16);
14522 Opc = X86ISD::CMPM;
14523 }
14524 // In the two special cases we can't handle, emit two comparisons.
14525 if (SSECC == 8) {
14526 unsigned CC0, CC1;
14527 unsigned CombineOpc;
14528 if (SetCCOpcode == ISD::SETUEQ) {
14529 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14530 } else {
14531 assert(SetCCOpcode == ISD::SETONE);
14532 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14533 }
14535 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14536 DAG.getConstant(CC0, MVT::i8));
14537 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14538 DAG.getConstant(CC1, MVT::i8));
14539 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14540 }
14541 // Handle all other FP comparisons here.
14542 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14543 DAG.getConstant(SSECC, MVT::i8));
14544 }
14546 // Break 256-bit integer vector compare into smaller ones.
14547 if (VT.is256BitVector() && !Subtarget->hasInt256())
14548 return Lower256IntVSETCC(Op, DAG);
14550 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14551 EVT OpVT = Op1.getValueType();
14552 if (Subtarget->hasAVX512()) {
14553 if (Op1.getValueType().is512BitVector() ||
14554 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14555 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14556 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14558 // In AVX-512 architecture setcc returns mask with i1 elements,
14559 // But there is no compare instruction for i8 and i16 elements in KNL.
14560 // We are not talking about 512-bit operands in this case, these
14561 // types are illegal.
14562 if (MaskResult &&
14563 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14564 OpVT.getVectorElementType().getSizeInBits() >= 8))
14565 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14566 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14567 }
14569 // We are handling one of the integer comparisons here. Since SSE only has
14570 // GT and EQ comparisons for integer, swapping operands and multiple
14571 // operations may be required for some comparisons.
14572 unsigned Opc;
14573 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14574 bool Subus = false;
14576 switch (SetCCOpcode) {
14577 default: llvm_unreachable("Unexpected SETCC condition");
14578 case ISD::SETNE: Invert = true;
14579 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14580 case ISD::SETLT: Swap = true;
14581 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14582 case ISD::SETGE: Swap = true;
14583 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14584 Invert = true; break;
14585 case ISD::SETULT: Swap = true;
14586 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14587 FlipSigns = true; break;
14588 case ISD::SETUGE: Swap = true;
14589 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14590 FlipSigns = true; Invert = true; break;
14591 }
14593 // Special case: Use min/max operations for SETULE/SETUGE
14594 MVT VET = VT.getVectorElementType();
14595 bool hasMinMax =
14596 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14597 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14599 if (hasMinMax) {
14600 switch (SetCCOpcode) {
14601 default: break;
14602 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
14603 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
14604 }
14606 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14607 }
14609 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14610 if (!MinMax && hasSubus) {
14611 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14612 // Op0 u<= Op1:
14613 // t = psubus Op0, Op1
14614 // pcmpeq t, <0..0>
14615 switch (SetCCOpcode) {
14616 default: break;
14617 case ISD::SETULT: {
14618 // If the comparison is against a constant we can turn this into a
14619 // setule. With psubus, setule does not require a swap. This is
14620 // beneficial because the constant in the register is no longer
14621 // destructed as the destination so it can be hoisted out of a loop.
14622 // Only do this pre-AVX since vpcmp* is no longer destructive.
14623 if (Subtarget->hasAVX())
14624 break;
14625 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14626 if (ULEOp1.getNode()) {
14627 Op1 = ULEOp1;
14628 Subus = true; Invert = false; Swap = false;
14629 }
14630 break;
14631 }
14632 // Psubus is better than flip-sign because it requires no inversion.
14633 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14634 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14635 }
14637 if (Subus) {
14638 Opc = X86ISD::SUBUS;
14639 FlipSigns = false;
14640 }
14641 }
14643 if (Swap)
14644 std::swap(Op0, Op1);
14646 // Check that the operation in question is available (most are plain SSE2,
14647 // but PCMPGTQ and PCMPEQQ have different requirements).
14648 if (VT == MVT::v2i64) {
14649 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14650 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14652 // First cast everything to the right type.
14653 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
14654 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
14656 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14657 // bits of the inputs before performing those operations. The lower
14658 // compare is always unsigned.
14659 SDValue SB;
14660 if (FlipSigns) {
14661 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
14662 } else {
14663 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
14664 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
14665 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14666 Sign, Zero, Sign, Zero);
14667 }
14668 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14669 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14671 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14672 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14673 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14675 // Create masks for only the low parts/high parts of the 64 bit integers.
14676 static const int MaskHi[] = { 1, 1, 3, 3 };
14677 static const int MaskLo[] = { 0, 0, 2, 2 };
14678 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14679 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14680 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14682 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14683 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14685 if (Invert)
14686 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14688 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
14689 }
14691 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14692 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14693 // pcmpeqd + pshufd + pand.
14694 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14696 // First cast everything to the right type.
14697 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
14698 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
14700 // Do the compare.
14701 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14703 // Make sure the lower and upper halves are both all-ones.
14704 static const int Mask[] = { 1, 0, 3, 2 };
14705 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14706 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14708 if (Invert)
14709 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14711 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
14712 }
14713 }
14715 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14716 // bits of the inputs before performing those operations.
14717 if (FlipSigns) {
14718 EVT EltVT = VT.getVectorElementType();
14719 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
14720 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14721 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14722 }
14724 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14726 // If the logical-not of the result is required, perform that now.
14727 if (Invert)
14728 Result = DAG.getNOT(dl, Result, VT);
14730 if (MinMax)
14731 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14733 if (Subus)
14734 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14735 getZeroVector(VT, Subtarget, DAG, dl));
14737 return Result;
14738 }
14740 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14742 MVT VT = Op.getSimpleValueType();
14744 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14746 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14747 && "SetCC type must be 8-bit or 1-bit integer");
14748 SDValue Op0 = Op.getOperand(0);
14749 SDValue Op1 = Op.getOperand(1);
14750 SDLoc dl(Op);
14751 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14753 // Optimize to BT if possible.
14754 // Lower (X & (1 << N)) == 0 to BT(X, N).
14755 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14756 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14757 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14758 Op1.getOpcode() == ISD::Constant &&
14759 cast<ConstantSDNode>(Op1)->isNullValue() &&
14760 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14761 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
14762 if (NewSetCC.getNode())
14763 return NewSetCC;
14764 }
14766 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14767 // these.
14768 if (Op1.getOpcode() == ISD::Constant &&
14769 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
14770 cast<ConstantSDNode>(Op1)->isNullValue()) &&
14771 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14773 // If the input is a setcc, then reuse the input setcc or use a new one with
14774 // the inverted condition.
14775 if (Op0.getOpcode() == X86ISD::SETCC) {
14776 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14777 bool Invert = (CC == ISD::SETNE) ^
14778 cast<ConstantSDNode>(Op1)->isNullValue();
14779 if (!Invert)
14780 return Op0;
14782 CCode = X86::GetOppositeBranchCondition(CCode);
14783 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14784 DAG.getConstant(CCode, MVT::i8),
14785 Op0.getOperand(1));
14786 if (VT == MVT::i1)
14787 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14788 return SetCC;
14789 }
14790 }
14791 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
14792 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
14793 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14795 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14796 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
14797 }
14799 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14800 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
14801 if (X86CC == X86::COND_INVALID)
14802 return SDValue();
14804 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14805 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14806 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14807 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
14808 if (VT == MVT::i1)
14809 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14810 return SetCC;
14811 }
14813 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14814 static bool isX86LogicalCmp(SDValue Op) {
14815 unsigned Opc = Op.getNode()->getOpcode();
14816 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14817 Opc == X86ISD::SAHF)
14818 return true;
14819 if (Op.getResNo() == 1 &&
14820 (Opc == X86ISD::ADD ||
14821 Opc == X86ISD::SUB ||
14822 Opc == X86ISD::ADC ||
14823 Opc == X86ISD::SBB ||
14824 Opc == X86ISD::SMUL ||
14825 Opc == X86ISD::UMUL ||
14826 Opc == X86ISD::INC ||
14827 Opc == X86ISD::DEC ||
14828 Opc == X86ISD::OR ||
14829 Opc == X86ISD::XOR ||
14830 Opc == X86ISD::AND))
14831 return true;
14833 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14834 return true;
14836 return false;
14837 }
14839 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14840 if (V.getOpcode() != ISD::TRUNCATE)
14841 return false;
14843 SDValue VOp0 = V.getOperand(0);
14844 unsigned InBits = VOp0.getValueSizeInBits();
14845 unsigned Bits = V.getValueSizeInBits();
14846 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14847 }
14849 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14850 bool addTest = true;
14851 SDValue Cond = Op.getOperand(0);
14852 SDValue Op1 = Op.getOperand(1);
14853 SDValue Op2 = Op.getOperand(2);
14854 SDLoc DL(Op);
14855 EVT VT = Op1.getValueType();
14856 SDValue CC;
14858 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14859 // are available. Otherwise fp cmovs get lowered into a less efficient branch
14860 // sequence later on.
14861 if (Cond.getOpcode() == ISD::SETCC &&
14862 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14863 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14864 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
14865 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14866 int SSECC = translateX86FSETCC(
14867 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14869 if (SSECC != 8) {
14870 if (Subtarget->hasAVX512()) {
14871 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14872 DAG.getConstant(SSECC, MVT::i8));
14873 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14874 }
14875 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14876 DAG.getConstant(SSECC, MVT::i8));
14877 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14878 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14879 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14880 }
14881 }
14883 if (Cond.getOpcode() == ISD::SETCC) {
14884 SDValue NewCond = LowerSETCC(Cond, DAG);
14885 if (NewCond.getNode())
14886 Cond = NewCond;
14887 }
14889 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14890 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14891 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14892 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14893 if (Cond.getOpcode() == X86ISD::SETCC &&
14894 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14895 isZero(Cond.getOperand(1).getOperand(1))) {
14896 SDValue Cmp = Cond.getOperand(1);
14898 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14900 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
14901 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14902 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
14904 SDValue CmpOp0 = Cmp.getOperand(0);
14905 // Apply further optimizations for special cases
14906 // (select (x != 0), -1, 0) -> neg & sbb
14907 // (select (x == 0), 0, -1) -> neg & sbb
14908 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
14909 if (YC->isNullValue() &&
14910 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
14911 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14912 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14913 DAG.getConstant(0, CmpOp0.getValueType()),
14914 CmpOp0);
14915 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14916 DAG.getConstant(X86::COND_B, MVT::i8),
14917 SDValue(Neg.getNode(), 1));
14918 return Res;
14919 }
14921 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14922 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
14923 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14925 SDValue Res = // Res = 0 or -1.
14926 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14927 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
14929 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
14930 Res = DAG.getNOT(DL, Res, Res.getValueType());
14932 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
14933 if (!N2C || !N2C->isNullValue())
14934 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14935 return Res;
14936 }
14937 }
14939 // Look past (and (setcc_carry (cmp ...)), 1).
14940 if (Cond.getOpcode() == ISD::AND &&
14941 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14942 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14943 if (C && C->getAPIntValue() == 1)
14944 Cond = Cond.getOperand(0);
14945 }
14947 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14948 // setting operand in place of the X86ISD::SETCC.
14949 unsigned CondOpcode = Cond.getOpcode();
14950 if (CondOpcode == X86ISD::SETCC ||
14951 CondOpcode == X86ISD::SETCC_CARRY) {
14952 CC = Cond.getOperand(0);
14954 SDValue Cmp = Cond.getOperand(1);
14955 unsigned Opc = Cmp.getOpcode();
14956 MVT VT = Op.getSimpleValueType();
14958 bool IllegalFPCMov = false;
14959 if (VT.isFloatingPoint() && !VT.isVector() &&
14960 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14961 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14963 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14964 Opc == X86ISD::BT) { // FIXME
14965 Cond = Cmp;
14966 addTest = false;
14967 }
14968 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14969 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14970 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14971 Cond.getOperand(0).getValueType() != MVT::i8)) {
14972 SDValue LHS = Cond.getOperand(0);
14973 SDValue RHS = Cond.getOperand(1);
14974 unsigned X86Opcode;
14975 unsigned X86Cond;
14976 SDVTList VTs;
14977 switch (CondOpcode) {
14978 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14979 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14980 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14981 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14982 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14983 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14984 default: llvm_unreachable("unexpected overflowing operator");
14985 }
14986 if (CondOpcode == ISD::UMULO)
14987 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14988 MVT::i32);
14989 else
14990 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14992 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14994 if (CondOpcode == ISD::UMULO)
14995 Cond = X86Op.getValue(2);
14996 else
14997 Cond = X86Op.getValue(1);
14999 CC = DAG.getConstant(X86Cond, MVT::i8);
15000 addTest = false;
15001 }
15003 if (addTest) {
15004 // Look pass the truncate if the high bits are known zero.
15005 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15006 Cond = Cond.getOperand(0);
15008 // We know the result of AND is compared against zero. Try to match
15009 // it to BT.
15010 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15011 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
15012 if (NewSetCC.getNode()) {
15013 CC = NewSetCC.getOperand(0);
15014 Cond = NewSetCC.getOperand(1);
15015 addTest = false;
15016 }
15017 }
15018 }
15020 if (addTest) {
15021 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15022 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
15023 }
15025 // a < b ? -1 : 0 -> RES = ~setcc_carry
15026 // a < b ? 0 : -1 -> RES = setcc_carry
15027 // a >= b ? -1 : 0 -> RES = setcc_carry
15028 // a >= b ? 0 : -1 -> RES = ~setcc_carry
15029 if (Cond.getOpcode() == X86ISD::SUB) {
15030 Cond = ConvertCmpIfNecessary(Cond, DAG);
15031 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
15033 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
15034 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
15035 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15036 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
15037 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
15038 return DAG.getNOT(DL, Res, Res.getValueType());
15039 return Res;
15040 }
15041 }
15043 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
15044 // widen the cmov and push the truncate through. This avoids introducing a new
15045 // branch during isel and doesn't add any extensions.
15046 if (Op.getValueType() == MVT::i8 &&
15047 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
15048 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
15049 if (T1.getValueType() == T2.getValueType() &&
15050 // Blacklist CopyFromReg to avoid partial register stalls.
15051 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
15052 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
15053 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
15054 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
15055 }
15056 }
15058 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
15059 // condition is true.
15060 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
15061 SDValue Ops[] = { Op2, Op1, CC, Cond };
15062 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
15063 }
15065 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
15066 MVT VT = Op->getSimpleValueType(0);
15067 SDValue In = Op->getOperand(0);
15068 MVT InVT = In.getSimpleValueType();
15069 SDLoc dl(Op);
15071 unsigned int NumElts = VT.getVectorNumElements();
15072 if (NumElts != 8 && NumElts != 16)
15073 return SDValue();
15075 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
15076 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15078 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15079 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15081 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
15082 Constant *C = ConstantInt::get(*DAG.getContext(),
15083 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
15085 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
15086 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
15087 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
15088 MachinePointerInfo::getConstantPool(),
15089 false, false, false, Alignment);
15090 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
15091 if (VT.is512BitVector())
15092 return Brcst;
15093 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
15094 }
15096 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15097 SelectionDAG &DAG) {
15098 MVT VT = Op->getSimpleValueType(0);
15099 SDValue In = Op->getOperand(0);
15100 MVT InVT = In.getSimpleValueType();
15101 SDLoc dl(Op);
15103 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15104 return LowerSIGN_EXTEND_AVX512(Op, DAG);
15106 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15107 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15108 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15109 return SDValue();
15111 if (Subtarget->hasInt256())
15112 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15114 // Optimize vectors in AVX mode
15115 // Sign extend v8i16 to v8i32 and
15116 // v4i32 to v4i64
15117 //
15118 // Divide input vector into two parts
15119 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15120 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15121 // concat the vectors to original VT
15123 unsigned NumElems = InVT.getVectorNumElements();
15124 SDValue Undef = DAG.getUNDEF(InVT);
15126 SmallVector<int,8> ShufMask1(NumElems, -1);
15127 for (unsigned i = 0; i != NumElems/2; ++i)
15128 ShufMask1[i] = i;
15130 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15132 SmallVector<int,8> ShufMask2(NumElems, -1);
15133 for (unsigned i = 0; i != NumElems/2; ++i)
15134 ShufMask2[i] = i + NumElems/2;
15136 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15138 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
15139 VT.getVectorNumElements()/2);
15141 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15142 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15144 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15145 }
15147 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15148 // may emit an illegal shuffle but the expansion is still better than scalar
15149 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15150 // we'll emit a shuffle and a arithmetic shift.
15151 // TODO: It is possible to support ZExt by zeroing the undef values during
15152 // the shuffle phase or after the shuffle.
15153 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15154 SelectionDAG &DAG) {
15155 MVT RegVT = Op.getSimpleValueType();
15156 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15157 assert(RegVT.isInteger() &&
15158 "We only custom lower integer vector sext loads.");
15160 // Nothing useful we can do without SSE2 shuffles.
15161 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15163 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15164 SDLoc dl(Ld);
15165 EVT MemVT = Ld->getMemoryVT();
15166 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15167 unsigned RegSz = RegVT.getSizeInBits();
15169 ISD::LoadExtType Ext = Ld->getExtensionType();
15171 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15172 && "Only anyext and sext are currently implemented.");
15173 assert(MemVT != RegVT && "Cannot extend to the same type");
15174 assert(MemVT.isVector() && "Must load a vector from memory");
15176 unsigned NumElems = RegVT.getVectorNumElements();
15177 unsigned MemSz = MemVT.getSizeInBits();
15178 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15180 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15181 // The only way in which we have a legal 256-bit vector result but not the
15182 // integer 256-bit operations needed to directly lower a sextload is if we
15183 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15184 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15185 // correctly legalized. We do this late to allow the canonical form of
15186 // sextload to persist throughout the rest of the DAG combiner -- it wants
15187 // to fold together any extensions it can, and so will fuse a sign_extend
15188 // of an sextload into a sextload targeting a wider value.
15189 SDValue Load;
15190 if (MemSz == 128) {
15191 // Just switch this to a normal load.
15192 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15193 "it must be a legal 128-bit vector "
15194 "type!");
15195 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15196 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15197 Ld->isInvariant(), Ld->getAlignment());
15198 } else {
15199 assert(MemSz < 128 &&
15200 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15201 // Do an sext load to a 128-bit vector type. We want to use the same
15202 // number of elements, but elements half as wide. This will end up being
15203 // recursively lowered by this routine, but will succeed as we definitely
15204 // have all the necessary features if we're using AVX1.
15205 EVT HalfEltVT =
15206 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15207 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15208 Load =
15209 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15210 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15211 Ld->isNonTemporal(), Ld->isInvariant(),
15212 Ld->getAlignment());
15213 }
15215 // Replace chain users with the new chain.
15216 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15217 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15219 // Finally, do a normal sign-extend to the desired register.
15220 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15221 }
15223 // All sizes must be a power of two.
15224 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15225 "Non-power-of-two elements are not custom lowered!");
15227 // Attempt to load the original value using scalar loads.
15228 // Find the largest scalar type that divides the total loaded size.
15229 MVT SclrLoadTy = MVT::i8;
15230 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
15231 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
15232 MVT Tp = (MVT::SimpleValueType)tp;
15233 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15234 SclrLoadTy = Tp;
15235 }
15236 }
15238 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15239 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15240 (64 <= MemSz))
15241 SclrLoadTy = MVT::f64;
15243 // Calculate the number of scalar loads that we need to perform
15244 // in order to load our vector from memory.
15245 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15247 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15248 "Can only lower sext loads with a single scalar load!");
15250 unsigned loadRegZize = RegSz;
15251 if (Ext == ISD::SEXTLOAD && RegSz == 256)
15252 loadRegZize /= 2;
15254 // Represent our vector as a sequence of elements which are the
15255 // largest scalar that we can load.
15256 EVT LoadUnitVecVT = EVT::getVectorVT(
15257 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15259 // Represent the data using the same element type that is stored in
15260 // memory. In practice, we ''widen'' MemVT.
15261 EVT WideVecVT =
15262 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15263 loadRegZize / MemVT.getScalarType().getSizeInBits());
15265 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15266 "Invalid vector type");
15268 // We can't shuffle using an illegal type.
15269 assert(TLI.isTypeLegal(WideVecVT) &&
15270 "We only lower types that form legal widened vector types");
15272 SmallVector<SDValue, 8> Chains;
15273 SDValue Ptr = Ld->getBasePtr();
15274 SDValue Increment =
15275 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
15276 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15278 for (unsigned i = 0; i < NumLoads; ++i) {
15279 // Perform a single load.
15280 SDValue ScalarLoad =
15281 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15282 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15283 Ld->getAlignment());
15284 Chains.push_back(ScalarLoad.getValue(1));
15285 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15286 // another round of DAGCombining.
15287 if (i == 0)
15288 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15289 else
15290 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15291 ScalarLoad, DAG.getIntPtrConstant(i));
15293 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15294 }
15296 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
15298 // Bitcast the loaded value to a vector of the original element type, in
15299 // the size of the target vector type.
15300 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
15301 unsigned SizeRatio = RegSz / MemSz;
15303 if (Ext == ISD::SEXTLOAD) {
15304 // If we have SSE4.1, we can directly emit a VSEXT node.
15305 if (Subtarget->hasSSE41()) {
15306 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
15307 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15308 return Sext;
15309 }
15311 // Otherwise we'll shuffle the small elements in the high bits of the
15312 // larger type and perform an arithmetic shift. If the shift is not legal
15313 // it's better to scalarize.
15314 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
15315 "We can't implement a sext load without an arithmetic right shift!");
15317 // Redistribute the loaded elements into the different locations.
15318 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15319 for (unsigned i = 0; i != NumElems; ++i)
15320 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
15322 SDValue Shuff = DAG.getVectorShuffle(
15323 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15325 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
15327 // Build the arithmetic shift.
15328 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
15329 MemVT.getVectorElementType().getSizeInBits();
15330 Shuff =
15331 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
15333 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15334 return Shuff;
15335 }
15337 // Redistribute the loaded elements into the different locations.
15338 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15339 for (unsigned i = 0; i != NumElems; ++i)
15340 ShuffleVec[i * SizeRatio] = i;
15342 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15343 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15345 // Bitcast to the requested type.
15346 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
15347 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15348 return Shuff;
15349 }
15351 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15352 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15353 // from the AND / OR.
15354 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15355 Opc = Op.getOpcode();
15356 if (Opc != ISD::OR && Opc != ISD::AND)
15357 return false;
15358 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15359 Op.getOperand(0).hasOneUse() &&
15360 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15361 Op.getOperand(1).hasOneUse());
15362 }
15364 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15365 // 1 and that the SETCC node has a single use.
15366 static bool isXor1OfSetCC(SDValue Op) {
15367 if (Op.getOpcode() != ISD::XOR)
15368 return false;
15369 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
15370 if (N1C && N1C->getAPIntValue() == 1) {
15371 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15372 Op.getOperand(0).hasOneUse();
15373 }
15374 return false;
15375 }
15377 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15378 bool addTest = true;
15379 SDValue Chain = Op.getOperand(0);
15380 SDValue Cond = Op.getOperand(1);
15381 SDValue Dest = Op.getOperand(2);
15382 SDLoc dl(Op);
15383 SDValue CC;
15384 bool Inverted = false;
15386 if (Cond.getOpcode() == ISD::SETCC) {
15387 // Check for setcc([su]{add,sub,mul}o == 0).
15388 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15389 isa<ConstantSDNode>(Cond.getOperand(1)) &&
15390 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
15391 Cond.getOperand(0).getResNo() == 1 &&
15392 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15393 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15394 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15395 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15396 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15397 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15398 Inverted = true;
15399 Cond = Cond.getOperand(0);
15400 } else {
15401 SDValue NewCond = LowerSETCC(Cond, DAG);
15402 if (NewCond.getNode())
15403 Cond = NewCond;
15404 }
15405 }
15406 #if 0
15407 // FIXME: LowerXALUO doesn't handle these!!
15408 else if (Cond.getOpcode() == X86ISD::ADD ||
15409 Cond.getOpcode() == X86ISD::SUB ||
15410 Cond.getOpcode() == X86ISD::SMUL ||
15411 Cond.getOpcode() == X86ISD::UMUL)
15412 Cond = LowerXALUO(Cond, DAG);
15413 #endif
15415 // Look pass (and (setcc_carry (cmp ...)), 1).
15416 if (Cond.getOpcode() == ISD::AND &&
15417 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15418 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15419 if (C && C->getAPIntValue() == 1)
15420 Cond = Cond.getOperand(0);
15421 }
15423 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15424 // setting operand in place of the X86ISD::SETCC.
15425 unsigned CondOpcode = Cond.getOpcode();
15426 if (CondOpcode == X86ISD::SETCC ||
15427 CondOpcode == X86ISD::SETCC_CARRY) {
15428 CC = Cond.getOperand(0);
15430 SDValue Cmp = Cond.getOperand(1);
15431 unsigned Opc = Cmp.getOpcode();
15432 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15433 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15434 Cond = Cmp;
15435 addTest = false;
15436 } else {
15437 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15438 default: break;
15439 case X86::COND_O:
15440 case X86::COND_B:
15441 // These can only come from an arithmetic instruction with overflow,
15442 // e.g. SADDO, UADDO.
15443 Cond = Cond.getNode()->getOperand(1);
15444 addTest = false;
15445 break;
15446 }
15447 }
15448 }
15449 CondOpcode = Cond.getOpcode();
15450 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15451 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15452 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15453 Cond.getOperand(0).getValueType() != MVT::i8)) {
15454 SDValue LHS = Cond.getOperand(0);
15455 SDValue RHS = Cond.getOperand(1);
15456 unsigned X86Opcode;
15457 unsigned X86Cond;
15458 SDVTList VTs;
15459 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15460 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15461 // X86ISD::INC).
15462 switch (CondOpcode) {
15463 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15464 case ISD::SADDO:
15465 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15466 if (C->isOne()) {
15467 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15468 break;
15469 }
15470 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15471 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15472 case ISD::SSUBO:
15473 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15474 if (C->isOne()) {
15475 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15476 break;
15477 }
15478 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15479 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15480 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15481 default: llvm_unreachable("unexpected overflowing operator");
15482 }
15483 if (Inverted)
15484 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15485 if (CondOpcode == ISD::UMULO)
15486 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15487 MVT::i32);
15488 else
15489 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15491 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15493 if (CondOpcode == ISD::UMULO)
15494 Cond = X86Op.getValue(2);
15495 else
15496 Cond = X86Op.getValue(1);
15498 CC = DAG.getConstant(X86Cond, MVT::i8);
15499 addTest = false;
15500 } else {
15501 unsigned CondOpc;
15502 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15503 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15504 if (CondOpc == ISD::OR) {
15505 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15506 // two branches instead of an explicit OR instruction with a
15507 // separate test.
15508 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15509 isX86LogicalCmp(Cmp)) {
15510 CC = Cond.getOperand(0).getOperand(0);
15511 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15512 Chain, Dest, CC, Cmp);
15513 CC = Cond.getOperand(1).getOperand(0);
15514 Cond = Cmp;
15515 addTest = false;
15516 }
15517 } else { // ISD::AND
15518 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15519 // two branches instead of an explicit AND instruction with a
15520 // separate test. However, we only do this if this block doesn't
15521 // have a fall-through edge, because this requires an explicit
15522 // jmp when the condition is false.
15523 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15524 isX86LogicalCmp(Cmp) &&
15525 Op.getNode()->hasOneUse()) {
15526 X86::CondCode CCode =
15527 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15528 CCode = X86::GetOppositeBranchCondition(CCode);
15529 CC = DAG.getConstant(CCode, MVT::i8);
15530 SDNode *User = *Op.getNode()->use_begin();
15531 // Look for an unconditional branch following this conditional branch.
15532 // We need this because we need to reverse the successors in order
15533 // to implement FCMP_OEQ.
15534 if (User->getOpcode() == ISD::BR) {
15535 SDValue FalseBB = User->getOperand(1);
15536 SDNode *NewBR =
15537 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15538 assert(NewBR == User);
15539 (void)NewBR;
15540 Dest = FalseBB;
15542 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15543 Chain, Dest, CC, Cmp);
15544 X86::CondCode CCode =
15545 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15546 CCode = X86::GetOppositeBranchCondition(CCode);
15547 CC = DAG.getConstant(CCode, MVT::i8);
15548 Cond = Cmp;
15549 addTest = false;
15550 }
15551 }
15552 }
15553 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15554 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15555 // It should be transformed during dag combiner except when the condition
15556 // is set by a arithmetics with overflow node.
15557 X86::CondCode CCode =
15558 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15559 CCode = X86::GetOppositeBranchCondition(CCode);
15560 CC = DAG.getConstant(CCode, MVT::i8);
15561 Cond = Cond.getOperand(0).getOperand(1);
15562 addTest = false;
15563 } else if (Cond.getOpcode() == ISD::SETCC &&
15564 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15565 // For FCMP_OEQ, we can emit
15566 // two branches instead of an explicit AND instruction with a
15567 // separate test. However, we only do this if this block doesn't
15568 // have a fall-through edge, because this requires an explicit
15569 // jmp when the condition is false.
15570 if (Op.getNode()->hasOneUse()) {
15571 SDNode *User = *Op.getNode()->use_begin();
15572 // Look for an unconditional branch following this conditional branch.
15573 // We need this because we need to reverse the successors in order
15574 // to implement FCMP_OEQ.
15575 if (User->getOpcode() == ISD::BR) {
15576 SDValue FalseBB = User->getOperand(1);
15577 SDNode *NewBR =
15578 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15579 assert(NewBR == User);
15580 (void)NewBR;
15581 Dest = FalseBB;
15583 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15584 Cond.getOperand(0), Cond.getOperand(1));
15585 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15586 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15587 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15588 Chain, Dest, CC, Cmp);
15589 CC = DAG.getConstant(X86::COND_P, MVT::i8);
15590 Cond = Cmp;
15591 addTest = false;
15592 }
15593 }
15594 } else if (Cond.getOpcode() == ISD::SETCC &&
15595 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15596 // For FCMP_UNE, we can emit
15597 // two branches instead of an explicit AND instruction with a
15598 // separate test. However, we only do this if this block doesn't
15599 // have a fall-through edge, because this requires an explicit
15600 // jmp when the condition is false.
15601 if (Op.getNode()->hasOneUse()) {
15602 SDNode *User = *Op.getNode()->use_begin();
15603 // Look for an unconditional branch following this conditional branch.
15604 // We need this because we need to reverse the successors in order
15605 // to implement FCMP_UNE.
15606 if (User->getOpcode() == ISD::BR) {
15607 SDValue FalseBB = User->getOperand(1);
15608 SDNode *NewBR =
15609 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15610 assert(NewBR == User);
15611 (void)NewBR;
15613 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15614 Cond.getOperand(0), Cond.getOperand(1));
15615 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15616 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15617 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15618 Chain, Dest, CC, Cmp);
15619 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
15620 Cond = Cmp;
15621 addTest = false;
15622 Dest = FalseBB;
15623 }
15624 }
15625 }
15626 }
15628 if (addTest) {
15629 // Look pass the truncate if the high bits are known zero.
15630 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15631 Cond = Cond.getOperand(0);
15633 // We know the result of AND is compared against zero. Try to match
15634 // it to BT.
15635 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15636 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
15637 if (NewSetCC.getNode()) {
15638 CC = NewSetCC.getOperand(0);
15639 Cond = NewSetCC.getOperand(1);
15640 addTest = false;
15641 }
15642 }
15643 }
15645 if (addTest) {
15646 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15647 CC = DAG.getConstant(X86Cond, MVT::i8);
15648 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15649 }
15650 Cond = ConvertCmpIfNecessary(Cond, DAG);
15651 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15652 Chain, Dest, CC, Cond);
15653 }
15655 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15656 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15657 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15658 // that the guard pages used by the OS virtual memory manager are allocated in
15659 // correct sequence.
15660 SDValue
15661 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15662 SelectionDAG &DAG) const {
15663 MachineFunction &MF = DAG.getMachineFunction();
15664 bool SplitStack = MF.shouldSplitStack();
15665 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
15666 SplitStack;
15667 SDLoc dl(Op);
15669 if (!Lower) {
15670 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15671 SDNode* Node = Op.getNode();
15673 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15674 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15675 " not tell us which reg is the stack pointer!");
15676 EVT VT = Node->getValueType(0);
15677 SDValue Tmp1 = SDValue(Node, 0);
15678 SDValue Tmp2 = SDValue(Node, 1);
15679 SDValue Tmp3 = Node->getOperand(2);
15680 SDValue Chain = Tmp1.getOperand(0);
15682 // Chain the dynamic stack allocation so that it doesn't modify the stack
15683 // pointer when other instructions are using the stack.
15684 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
15685 SDLoc(Node));
15687 SDValue Size = Tmp2.getOperand(1);
15688 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15689 Chain = SP.getValue(1);
15690 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15691 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
15692 unsigned StackAlign = TFI.getStackAlignment();
15693 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15694 if (Align > StackAlign)
15695 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
15696 DAG.getConstant(-(uint64_t)Align, VT));
15697 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
15699 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
15700 DAG.getIntPtrConstant(0, true), SDValue(),
15701 SDLoc(Node));
15703 SDValue Ops[2] = { Tmp1, Tmp2 };
15704 return DAG.getMergeValues(Ops, dl);
15705 }
15707 // Get the inputs.
15708 SDValue Chain = Op.getOperand(0);
15709 SDValue Size = Op.getOperand(1);
15710 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15711 EVT VT = Op.getNode()->getValueType(0);
15713 bool Is64Bit = Subtarget->is64Bit();
15714 EVT SPTy = getPointerTy();
15716 if (SplitStack) {
15717 MachineRegisterInfo &MRI = MF.getRegInfo();
15719 if (Is64Bit) {
15720 // The 64 bit implementation of segmented stacks needs to clobber both r10
15721 // r11. This makes it impossible to use it along with nested parameters.
15722 const Function *F = MF.getFunction();
15724 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15725 I != E; ++I)
15726 if (I->hasNestAttr())
15727 report_fatal_error("Cannot use segmented stacks with functions that "
15728 "have nested arguments.");
15729 }
15731 const TargetRegisterClass *AddrRegClass =
15732 getRegClassFor(getPointerTy());
15733 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15734 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15735 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15736 DAG.getRegister(Vreg, SPTy));
15737 SDValue Ops1[2] = { Value, Chain };
15738 return DAG.getMergeValues(Ops1, dl);
15739 } else {
15740 SDValue Flag;
15741 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15743 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15744 Flag = Chain.getValue(1);
15745 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15747 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15749 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15750 DAG.getSubtarget().getRegisterInfo());
15751 unsigned SPReg = RegInfo->getStackRegister();
15752 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15753 Chain = SP.getValue(1);
15755 if (Align) {
15756 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15757 DAG.getConstant(-(uint64_t)Align, VT));
15758 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15759 }
15761 SDValue Ops1[2] = { SP, Chain };
15762 return DAG.getMergeValues(Ops1, dl);
15763 }
15764 }
15766 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15767 MachineFunction &MF = DAG.getMachineFunction();
15768 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15770 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15771 SDLoc DL(Op);
15773 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
15774 // vastart just stores the address of the VarArgsFrameIndex slot into the
15775 // memory location argument.
15776 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
15777 getPointerTy());
15778 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15779 MachinePointerInfo(SV), false, false, 0);
15780 }
15782 // __va_list_tag:
15783 // gp_offset (0 - 6 * 8)
15784 // fp_offset (48 - 48 + 8 * 16)
15785 // overflow_arg_area (point to parameters coming in memory).
15786 // reg_save_area
15787 SmallVector<SDValue, 8> MemOps;
15788 SDValue FIN = Op.getOperand(1);
15789 // Store gp_offset
15790 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15791 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15792 MVT::i32),
15793 FIN, MachinePointerInfo(SV), false, false, 0);
15794 MemOps.push_back(Store);
15796 // Store fp_offset
15797 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15798 FIN, DAG.getIntPtrConstant(4));
15799 Store = DAG.getStore(Op.getOperand(0), DL,
15800 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
15801 MVT::i32),
15802 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15803 MemOps.push_back(Store);
15805 // Store ptr to overflow_arg_area
15806 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15807 FIN, DAG.getIntPtrConstant(4));
15808 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
15809 getPointerTy());
15810 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15811 MachinePointerInfo(SV, 8),
15812 false, false, 0);
15813 MemOps.push_back(Store);
15815 // Store ptr to reg_save_area.
15816 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15817 FIN, DAG.getIntPtrConstant(8));
15818 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
15819 getPointerTy());
15820 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
15821 MachinePointerInfo(SV, 16), false, false, 0);
15822 MemOps.push_back(Store);
15823 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15824 }
15826 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15827 assert(Subtarget->is64Bit() &&
15828 "LowerVAARG only handles 64-bit va_arg!");
15829 assert((Subtarget->isTargetLinux() ||
15830 Subtarget->isTargetDarwin()) &&
15831 "Unhandled target in LowerVAARG");
15832 assert(Op.getNode()->getNumOperands() == 4);
15833 SDValue Chain = Op.getOperand(0);
15834 SDValue SrcPtr = Op.getOperand(1);
15835 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15836 unsigned Align = Op.getConstantOperandVal(3);
15837 SDLoc dl(Op);
15839 EVT ArgVT = Op.getNode()->getValueType(0);
15840 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15841 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
15842 uint8_t ArgMode;
15844 // Decide which area this value should be read from.
15845 // TODO: Implement the AMD64 ABI in its entirety. This simple
15846 // selection mechanism works only for the basic types.
15847 if (ArgVT == MVT::f80) {
15848 llvm_unreachable("va_arg for f80 not yet implemented");
15849 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15850 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15851 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15852 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15853 } else {
15854 llvm_unreachable("Unhandled argument type in LowerVAARG");
15855 }
15857 if (ArgMode == 2) {
15858 // Sanity Check: Make sure using fp_offset makes sense.
15859 assert(!DAG.getTarget().Options.UseSoftFloat &&
15860 !(DAG.getMachineFunction()
15861 .getFunction()->getAttributes()
15862 .hasAttribute(AttributeSet::FunctionIndex,
15863 Attribute::NoImplicitFloat)) &&
15864 Subtarget->hasSSE1());
15865 }
15867 // Insert VAARG_64 node into the DAG
15868 // VAARG_64 returns two values: Variable Argument Address, Chain
15869 SmallVector<SDValue, 11> InstOps;
15870 InstOps.push_back(Chain);
15871 InstOps.push_back(SrcPtr);
15872 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
15873 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
15874 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
15875 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
15876 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15877 VTs, InstOps, MVT::i64,
15878 MachinePointerInfo(SV),
15879 /*Align=*/0,
15880 /*Volatile=*/false,
15881 /*ReadMem=*/true,
15882 /*WriteMem=*/true);
15883 Chain = VAARG.getValue(1);
15885 // Load the next argument and return it
15886 return DAG.getLoad(ArgVT, dl,
15887 Chain,
15888 VAARG,
15889 MachinePointerInfo(),
15890 false, false, false, 0);
15891 }
15893 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15894 SelectionDAG &DAG) {
15895 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
15896 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15897 SDValue Chain = Op.getOperand(0);
15898 SDValue DstPtr = Op.getOperand(1);
15899 SDValue SrcPtr = Op.getOperand(2);
15900 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15901 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15902 SDLoc DL(Op);
15904 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15905 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
15906 false,
15907 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15908 }
15910 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15911 // amount is a constant. Takes immediate version of shift as input.
15912 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15913 SDValue SrcOp, uint64_t ShiftAmt,
15914 SelectionDAG &DAG) {
15915 MVT ElementType = VT.getVectorElementType();
15917 // Fold this packed shift into its first operand if ShiftAmt is 0.
15918 if (ShiftAmt == 0)
15919 return SrcOp;
15921 // Check for ShiftAmt >= element width
15922 if (ShiftAmt >= ElementType.getSizeInBits()) {
15923 if (Opc == X86ISD::VSRAI)
15924 ShiftAmt = ElementType.getSizeInBits() - 1;
15925 else
15926 return DAG.getConstant(0, VT);
15927 }
15929 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15930 && "Unknown target vector shift-by-constant node");
15932 // Fold this packed vector shift into a build vector if SrcOp is a
15933 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15934 if (VT == SrcOp.getSimpleValueType() &&
15935 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15936 SmallVector<SDValue, 8> Elts;
15937 unsigned NumElts = SrcOp->getNumOperands();
15938 ConstantSDNode *ND;
15940 switch(Opc) {
15941 default: llvm_unreachable(nullptr);
15942 case X86ISD::VSHLI:
15943 for (unsigned i=0; i!=NumElts; ++i) {
15944 SDValue CurrentOp = SrcOp->getOperand(i);
15945 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15946 Elts.push_back(CurrentOp);
15947 continue;
15948 }
15949 ND = cast<ConstantSDNode>(CurrentOp);
15950 const APInt &C = ND->getAPIntValue();
15951 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
15952 }
15953 break;
15954 case X86ISD::VSRLI:
15955 for (unsigned i=0; i!=NumElts; ++i) {
15956 SDValue CurrentOp = SrcOp->getOperand(i);
15957 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15958 Elts.push_back(CurrentOp);
15959 continue;
15960 }
15961 ND = cast<ConstantSDNode>(CurrentOp);
15962 const APInt &C = ND->getAPIntValue();
15963 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
15964 }
15965 break;
15966 case X86ISD::VSRAI:
15967 for (unsigned i=0; i!=NumElts; ++i) {
15968 SDValue CurrentOp = SrcOp->getOperand(i);
15969 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15970 Elts.push_back(CurrentOp);
15971 continue;
15972 }
15973 ND = cast<ConstantSDNode>(CurrentOp);
15974 const APInt &C = ND->getAPIntValue();
15975 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
15976 }
15977 break;
15978 }
15980 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15981 }
15983 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
15984 }
15986 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15987 // may or may not be a constant. Takes immediate version of shift as input.
15988 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15989 SDValue SrcOp, SDValue ShAmt,
15990 SelectionDAG &DAG) {
15991 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
15993 // Catch shift-by-constant.
15994 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15995 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15996 CShAmt->getZExtValue(), DAG);
15998 // Change opcode to non-immediate version
15999 switch (Opc) {
16000 default: llvm_unreachable("Unknown target vector shift node");
16001 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
16002 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
16003 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
16004 }
16006 // Need to build a vector containing shift amount
16007 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
16008 SDValue ShOps[4];
16009 ShOps[0] = ShAmt;
16010 ShOps[1] = DAG.getConstant(0, MVT::i32);
16011 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
16012 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
16014 // The return type has to be a 128-bit type with the same element
16015 // type as the input type.
16016 MVT EltVT = VT.getVectorElementType();
16017 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
16019 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
16020 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
16021 }
16023 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16024 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16025 /// necessary casting for \p Mask when lowering masking intrinsics.
16026 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16027 SDValue PreservedSrc, SelectionDAG &DAG) {
16028 EVT VT = Op.getValueType();
16029 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16030 MVT::i1, VT.getVectorNumElements());
16031 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16032 Mask.getValueType().getSizeInBits());
16033 SDLoc dl(Op);
16035 assert(MaskVT.isSimple() && "invalid mask type");
16037 if (isAllOnes(Mask))
16038 return Op;
16040 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16041 // are extracted by EXTRACT_SUBVECTOR.
16042 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16043 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
16044 DAG.getIntPtrConstant(0));
16046 switch (Op.getOpcode()) {
16047 default: break;
16048 case X86ISD::PCMPEQM:
16049 case X86ISD::PCMPGTM:
16050 case X86ISD::CMPM:
16051 case X86ISD::CMPMU:
16052 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16053 }
16055 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
16056 }
16058 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
16059 switch (IntNo) {
16060 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16061 case Intrinsic::x86_fma_vfmadd_ps:
16062 case Intrinsic::x86_fma_vfmadd_pd:
16063 case Intrinsic::x86_fma_vfmadd_ps_256:
16064 case Intrinsic::x86_fma_vfmadd_pd_256:
16065 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16066 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16067 return X86ISD::FMADD;
16068 case Intrinsic::x86_fma_vfmsub_ps:
16069 case Intrinsic::x86_fma_vfmsub_pd:
16070 case Intrinsic::x86_fma_vfmsub_ps_256:
16071 case Intrinsic::x86_fma_vfmsub_pd_256:
16072 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16073 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16074 return X86ISD::FMSUB;
16075 case Intrinsic::x86_fma_vfnmadd_ps:
16076 case Intrinsic::x86_fma_vfnmadd_pd:
16077 case Intrinsic::x86_fma_vfnmadd_ps_256:
16078 case Intrinsic::x86_fma_vfnmadd_pd_256:
16079 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16080 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16081 return X86ISD::FNMADD;
16082 case Intrinsic::x86_fma_vfnmsub_ps:
16083 case Intrinsic::x86_fma_vfnmsub_pd:
16084 case Intrinsic::x86_fma_vfnmsub_ps_256:
16085 case Intrinsic::x86_fma_vfnmsub_pd_256:
16086 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16087 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16088 return X86ISD::FNMSUB;
16089 case Intrinsic::x86_fma_vfmaddsub_ps:
16090 case Intrinsic::x86_fma_vfmaddsub_pd:
16091 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16092 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16093 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16094 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16095 return X86ISD::FMADDSUB;
16096 case Intrinsic::x86_fma_vfmsubadd_ps:
16097 case Intrinsic::x86_fma_vfmsubadd_pd:
16098 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16099 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16100 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16101 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
16102 return X86ISD::FMSUBADD;
16103 }
16104 }
16106 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
16107 SDLoc dl(Op);
16108 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16110 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16111 if (IntrData) {
16112 switch(IntrData->Type) {
16113 case INTR_TYPE_1OP:
16114 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16115 case INTR_TYPE_2OP:
16116 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16117 Op.getOperand(2));
16118 case INTR_TYPE_3OP:
16119 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16120 Op.getOperand(2), Op.getOperand(3));
16121 case CMP_MASK: {
16122 // Comparison intrinsics with masks.
16123 // Example of transformation:
16124 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16125 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16126 // (i8 (bitcast
16127 // (v8i1 (insert_subvector undef,
16128 // (v2i1 (and (PCMPEQM %a, %b),
16129 // (extract_subvector
16130 // (v8i1 (bitcast %mask)), 0))), 0))))
16131 EVT VT = Op.getOperand(1).getValueType();
16132 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16133 VT.getVectorNumElements());
16134 SDValue Mask = Op.getOperand(3);
16135 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16136 Mask.getValueType().getSizeInBits());
16137 SDValue Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT,
16138 Op.getOperand(1), Op.getOperand(2));
16139 SDValue CmpMask = getVectorMaskingNode(Cmp, Op.getOperand(3),
16140 DAG.getTargetConstant(0, MaskVT), DAG);
16141 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16142 DAG.getUNDEF(BitcastVT), CmpMask,
16143 DAG.getIntPtrConstant(0));
16144 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
16145 }
16146 case COMI: { // Comparison intrinsics
16147 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16148 SDValue LHS = Op.getOperand(1);
16149 SDValue RHS = Op.getOperand(2);
16150 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
16151 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16152 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16153 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16154 DAG.getConstant(X86CC, MVT::i8), Cond);
16155 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16156 }
16157 case VSHIFT:
16158 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16159 Op.getOperand(1), Op.getOperand(2), DAG);
16160 default:
16161 break;
16162 }
16163 }
16165 switch (IntNo) {
16166 default: return SDValue(); // Don't custom lower most intrinsics.
16168 // Arithmetic intrinsics.
16169 case Intrinsic::x86_sse2_pmulu_dq:
16170 case Intrinsic::x86_avx2_pmulu_dq:
16171 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
16172 Op.getOperand(1), Op.getOperand(2));
16174 case Intrinsic::x86_sse41_pmuldq:
16175 case Intrinsic::x86_avx2_pmul_dq:
16176 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
16177 Op.getOperand(1), Op.getOperand(2));
16179 case Intrinsic::x86_sse2_pmulhu_w:
16180 case Intrinsic::x86_avx2_pmulhu_w:
16181 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
16182 Op.getOperand(1), Op.getOperand(2));
16184 case Intrinsic::x86_sse2_pmulh_w:
16185 case Intrinsic::x86_avx2_pmulh_w:
16186 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
16187 Op.getOperand(1), Op.getOperand(2));
16189 // SSE/SSE2/AVX floating point max/min intrinsics.
16190 case Intrinsic::x86_sse_max_ps:
16191 case Intrinsic::x86_sse2_max_pd:
16192 case Intrinsic::x86_avx_max_ps_256:
16193 case Intrinsic::x86_avx_max_pd_256:
16194 case Intrinsic::x86_sse_min_ps:
16195 case Intrinsic::x86_sse2_min_pd:
16196 case Intrinsic::x86_avx_min_ps_256:
16197 case Intrinsic::x86_avx_min_pd_256: {
16198 unsigned Opcode;
16199 switch (IntNo) {
16200 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16201 case Intrinsic::x86_sse_max_ps:
16202 case Intrinsic::x86_sse2_max_pd:
16203 case Intrinsic::x86_avx_max_ps_256:
16204 case Intrinsic::x86_avx_max_pd_256:
16205 Opcode = X86ISD::FMAX;
16206 break;
16207 case Intrinsic::x86_sse_min_ps:
16208 case Intrinsic::x86_sse2_min_pd:
16209 case Intrinsic::x86_avx_min_ps_256:
16210 case Intrinsic::x86_avx_min_pd_256:
16211 Opcode = X86ISD::FMIN;
16212 break;
16213 }
16214 return DAG.getNode(Opcode, dl, Op.getValueType(),
16215 Op.getOperand(1), Op.getOperand(2));
16216 }
16218 // AVX2 variable shift intrinsics
16219 case Intrinsic::x86_avx2_psllv_d:
16220 case Intrinsic::x86_avx2_psllv_q:
16221 case Intrinsic::x86_avx2_psllv_d_256:
16222 case Intrinsic::x86_avx2_psllv_q_256:
16223 case Intrinsic::x86_avx2_psrlv_d:
16224 case Intrinsic::x86_avx2_psrlv_q:
16225 case Intrinsic::x86_avx2_psrlv_d_256:
16226 case Intrinsic::x86_avx2_psrlv_q_256:
16227 case Intrinsic::x86_avx2_psrav_d:
16228 case Intrinsic::x86_avx2_psrav_d_256: {
16229 unsigned Opcode;
16230 switch (IntNo) {
16231 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16232 case Intrinsic::x86_avx2_psllv_d:
16233 case Intrinsic::x86_avx2_psllv_q:
16234 case Intrinsic::x86_avx2_psllv_d_256:
16235 case Intrinsic::x86_avx2_psllv_q_256:
16236 Opcode = ISD::SHL;
16237 break;
16238 case Intrinsic::x86_avx2_psrlv_d:
16239 case Intrinsic::x86_avx2_psrlv_q:
16240 case Intrinsic::x86_avx2_psrlv_d_256:
16241 case Intrinsic::x86_avx2_psrlv_q_256:
16242 Opcode = ISD::SRL;
16243 break;
16244 case Intrinsic::x86_avx2_psrav_d:
16245 case Intrinsic::x86_avx2_psrav_d_256:
16246 Opcode = ISD::SRA;
16247 break;
16248 }
16249 return DAG.getNode(Opcode, dl, Op.getValueType(),
16250 Op.getOperand(1), Op.getOperand(2));
16251 }
16253 case Intrinsic::x86_sse2_packssdw_128:
16254 case Intrinsic::x86_sse2_packsswb_128:
16255 case Intrinsic::x86_avx2_packssdw:
16256 case Intrinsic::x86_avx2_packsswb:
16257 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
16258 Op.getOperand(1), Op.getOperand(2));
16260 case Intrinsic::x86_sse2_packuswb_128:
16261 case Intrinsic::x86_sse41_packusdw:
16262 case Intrinsic::x86_avx2_packuswb:
16263 case Intrinsic::x86_avx2_packusdw:
16264 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
16265 Op.getOperand(1), Op.getOperand(2));
16267 case Intrinsic::x86_ssse3_pshuf_b_128:
16268 case Intrinsic::x86_avx2_pshuf_b:
16269 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
16270 Op.getOperand(1), Op.getOperand(2));
16272 case Intrinsic::x86_sse2_pshuf_d:
16273 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
16274 Op.getOperand(1), Op.getOperand(2));
16276 case Intrinsic::x86_sse2_pshufl_w:
16277 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
16278 Op.getOperand(1), Op.getOperand(2));
16280 case Intrinsic::x86_sse2_pshufh_w:
16281 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
16282 Op.getOperand(1), Op.getOperand(2));
16284 case Intrinsic::x86_ssse3_psign_b_128:
16285 case Intrinsic::x86_ssse3_psign_w_128:
16286 case Intrinsic::x86_ssse3_psign_d_128:
16287 case Intrinsic::x86_avx2_psign_b:
16288 case Intrinsic::x86_avx2_psign_w:
16289 case Intrinsic::x86_avx2_psign_d:
16290 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
16291 Op.getOperand(1), Op.getOperand(2));
16293 case Intrinsic::x86_avx2_permd:
16294 case Intrinsic::x86_avx2_permps:
16295 // Operands intentionally swapped. Mask is last operand to intrinsic,
16296 // but second operand for node/instruction.
16297 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16298 Op.getOperand(2), Op.getOperand(1));
16300 case Intrinsic::x86_avx512_mask_valign_q_512:
16301 case Intrinsic::x86_avx512_mask_valign_d_512:
16302 // Vector source operands are swapped.
16303 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
16304 Op.getValueType(), Op.getOperand(2),
16305 Op.getOperand(1),
16306 Op.getOperand(3)),
16307 Op.getOperand(5), Op.getOperand(4), DAG);
16309 // ptest and testp intrinsics. The intrinsic these come from are designed to
16310 // return an integer value, not just an instruction so lower it to the ptest
16311 // or testp pattern and a setcc for the result.
16312 case Intrinsic::x86_sse41_ptestz:
16313 case Intrinsic::x86_sse41_ptestc:
16314 case Intrinsic::x86_sse41_ptestnzc:
16315 case Intrinsic::x86_avx_ptestz_256:
16316 case Intrinsic::x86_avx_ptestc_256:
16317 case Intrinsic::x86_avx_ptestnzc_256:
16318 case Intrinsic::x86_avx_vtestz_ps:
16319 case Intrinsic::x86_avx_vtestc_ps:
16320 case Intrinsic::x86_avx_vtestnzc_ps:
16321 case Intrinsic::x86_avx_vtestz_pd:
16322 case Intrinsic::x86_avx_vtestc_pd:
16323 case Intrinsic::x86_avx_vtestnzc_pd:
16324 case Intrinsic::x86_avx_vtestz_ps_256:
16325 case Intrinsic::x86_avx_vtestc_ps_256:
16326 case Intrinsic::x86_avx_vtestnzc_ps_256:
16327 case Intrinsic::x86_avx_vtestz_pd_256:
16328 case Intrinsic::x86_avx_vtestc_pd_256:
16329 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16330 bool IsTestPacked = false;
16331 unsigned X86CC;
16332 switch (IntNo) {
16333 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16334 case Intrinsic::x86_avx_vtestz_ps:
16335 case Intrinsic::x86_avx_vtestz_pd:
16336 case Intrinsic::x86_avx_vtestz_ps_256:
16337 case Intrinsic::x86_avx_vtestz_pd_256:
16338 IsTestPacked = true; // Fallthrough
16339 case Intrinsic::x86_sse41_ptestz:
16340 case Intrinsic::x86_avx_ptestz_256:
16341 // ZF = 1
16342 X86CC = X86::COND_E;
16343 break;
16344 case Intrinsic::x86_avx_vtestc_ps:
16345 case Intrinsic::x86_avx_vtestc_pd:
16346 case Intrinsic::x86_avx_vtestc_ps_256:
16347 case Intrinsic::x86_avx_vtestc_pd_256:
16348 IsTestPacked = true; // Fallthrough
16349 case Intrinsic::x86_sse41_ptestc:
16350 case Intrinsic::x86_avx_ptestc_256:
16351 // CF = 1
16352 X86CC = X86::COND_B;
16353 break;
16354 case Intrinsic::x86_avx_vtestnzc_ps:
16355 case Intrinsic::x86_avx_vtestnzc_pd:
16356 case Intrinsic::x86_avx_vtestnzc_ps_256:
16357 case Intrinsic::x86_avx_vtestnzc_pd_256:
16358 IsTestPacked = true; // Fallthrough
16359 case Intrinsic::x86_sse41_ptestnzc:
16360 case Intrinsic::x86_avx_ptestnzc_256:
16361 // ZF and CF = 0
16362 X86CC = X86::COND_A;
16363 break;
16364 }
16366 SDValue LHS = Op.getOperand(1);
16367 SDValue RHS = Op.getOperand(2);
16368 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16369 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16370 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
16371 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16372 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16373 }
16374 case Intrinsic::x86_avx512_kortestz_w:
16375 case Intrinsic::x86_avx512_kortestc_w: {
16376 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16377 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
16378 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
16379 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
16380 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16381 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16382 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16383 }
16385 case Intrinsic::x86_sse42_pcmpistria128:
16386 case Intrinsic::x86_sse42_pcmpestria128:
16387 case Intrinsic::x86_sse42_pcmpistric128:
16388 case Intrinsic::x86_sse42_pcmpestric128:
16389 case Intrinsic::x86_sse42_pcmpistrio128:
16390 case Intrinsic::x86_sse42_pcmpestrio128:
16391 case Intrinsic::x86_sse42_pcmpistris128:
16392 case Intrinsic::x86_sse42_pcmpestris128:
16393 case Intrinsic::x86_sse42_pcmpistriz128:
16394 case Intrinsic::x86_sse42_pcmpestriz128: {
16395 unsigned Opcode;
16396 unsigned X86CC;
16397 switch (IntNo) {
16398 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16399 case Intrinsic::x86_sse42_pcmpistria128:
16400 Opcode = X86ISD::PCMPISTRI;
16401 X86CC = X86::COND_A;
16402 break;
16403 case Intrinsic::x86_sse42_pcmpestria128:
16404 Opcode = X86ISD::PCMPESTRI;
16405 X86CC = X86::COND_A;
16406 break;
16407 case Intrinsic::x86_sse42_pcmpistric128:
16408 Opcode = X86ISD::PCMPISTRI;
16409 X86CC = X86::COND_B;
16410 break;
16411 case Intrinsic::x86_sse42_pcmpestric128:
16412 Opcode = X86ISD::PCMPESTRI;
16413 X86CC = X86::COND_B;
16414 break;
16415 case Intrinsic::x86_sse42_pcmpistrio128:
16416 Opcode = X86ISD::PCMPISTRI;
16417 X86CC = X86::COND_O;
16418 break;
16419 case Intrinsic::x86_sse42_pcmpestrio128:
16420 Opcode = X86ISD::PCMPESTRI;
16421 X86CC = X86::COND_O;
16422 break;
16423 case Intrinsic::x86_sse42_pcmpistris128:
16424 Opcode = X86ISD::PCMPISTRI;
16425 X86CC = X86::COND_S;
16426 break;
16427 case Intrinsic::x86_sse42_pcmpestris128:
16428 Opcode = X86ISD::PCMPESTRI;
16429 X86CC = X86::COND_S;
16430 break;
16431 case Intrinsic::x86_sse42_pcmpistriz128:
16432 Opcode = X86ISD::PCMPISTRI;
16433 X86CC = X86::COND_E;
16434 break;
16435 case Intrinsic::x86_sse42_pcmpestriz128:
16436 Opcode = X86ISD::PCMPESTRI;
16437 X86CC = X86::COND_E;
16438 break;
16439 }
16440 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16441 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16442 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
16443 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16444 DAG.getConstant(X86CC, MVT::i8),
16445 SDValue(PCMP.getNode(), 1));
16446 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16447 }
16449 case Intrinsic::x86_sse42_pcmpistri128:
16450 case Intrinsic::x86_sse42_pcmpestri128: {
16451 unsigned Opcode;
16452 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
16453 Opcode = X86ISD::PCMPISTRI;
16454 else
16455 Opcode = X86ISD::PCMPESTRI;
16457 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16458 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16459 return DAG.getNode(Opcode, dl, VTs, NewOps);
16460 }
16462 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16463 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16464 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16465 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16466 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16467 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16468 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16469 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16470 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16471 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16472 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16473 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
16474 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
16475 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
16476 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
16477 dl, Op.getValueType(),
16478 Op.getOperand(1),
16479 Op.getOperand(2),
16480 Op.getOperand(3)),
16481 Op.getOperand(4), Op.getOperand(1), DAG);
16482 else
16483 return SDValue();
16484 }
16486 case Intrinsic::x86_fma_vfmadd_ps:
16487 case Intrinsic::x86_fma_vfmadd_pd:
16488 case Intrinsic::x86_fma_vfmsub_ps:
16489 case Intrinsic::x86_fma_vfmsub_pd:
16490 case Intrinsic::x86_fma_vfnmadd_ps:
16491 case Intrinsic::x86_fma_vfnmadd_pd:
16492 case Intrinsic::x86_fma_vfnmsub_ps:
16493 case Intrinsic::x86_fma_vfnmsub_pd:
16494 case Intrinsic::x86_fma_vfmaddsub_ps:
16495 case Intrinsic::x86_fma_vfmaddsub_pd:
16496 case Intrinsic::x86_fma_vfmsubadd_ps:
16497 case Intrinsic::x86_fma_vfmsubadd_pd:
16498 case Intrinsic::x86_fma_vfmadd_ps_256:
16499 case Intrinsic::x86_fma_vfmadd_pd_256:
16500 case Intrinsic::x86_fma_vfmsub_ps_256:
16501 case Intrinsic::x86_fma_vfmsub_pd_256:
16502 case Intrinsic::x86_fma_vfnmadd_ps_256:
16503 case Intrinsic::x86_fma_vfnmadd_pd_256:
16504 case Intrinsic::x86_fma_vfnmsub_ps_256:
16505 case Intrinsic::x86_fma_vfnmsub_pd_256:
16506 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16507 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16508 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16509 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16510 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
16511 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
16512 }
16513 }
16515 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16516 SDValue Src, SDValue Mask, SDValue Base,
16517 SDValue Index, SDValue ScaleOp, SDValue Chain,
16518 const X86Subtarget * Subtarget) {
16519 SDLoc dl(Op);
16520 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16521 assert(C && "Invalid scale type");
16522 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16523 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16524 Index.getSimpleValueType().getVectorNumElements());
16525 SDValue MaskInReg;
16526 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16527 if (MaskC)
16528 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16529 else
16530 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16531 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16532 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16533 SDValue Segment = DAG.getRegister(0, MVT::i32);
16534 if (Src.getOpcode() == ISD::UNDEF)
16535 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
16536 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16537 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16538 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16539 return DAG.getMergeValues(RetOps, dl);
16540 }
16542 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16543 SDValue Src, SDValue Mask, SDValue Base,
16544 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16545 SDLoc dl(Op);
16546 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16547 assert(C && "Invalid scale type");
16548 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16549 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16550 SDValue Segment = DAG.getRegister(0, MVT::i32);
16551 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16552 Index.getSimpleValueType().getVectorNumElements());
16553 SDValue MaskInReg;
16554 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16555 if (MaskC)
16556 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16557 else
16558 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16559 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16560 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16561 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16562 return SDValue(Res, 1);
16563 }
16565 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16566 SDValue Mask, SDValue Base, SDValue Index,
16567 SDValue ScaleOp, SDValue Chain) {
16568 SDLoc dl(Op);
16569 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16570 assert(C && "Invalid scale type");
16571 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16572 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16573 SDValue Segment = DAG.getRegister(0, MVT::i32);
16574 EVT MaskVT =
16575 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
16576 SDValue MaskInReg;
16577 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16578 if (MaskC)
16579 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16580 else
16581 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16582 //SDVTList VTs = DAG.getVTList(MVT::Other);
16583 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16584 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
16585 return SDValue(Res, 0);
16586 }
16588 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
16589 // read performance monitor counters (x86_rdpmc).
16590 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
16591 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16592 SmallVectorImpl<SDValue> &Results) {
16593 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16594 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16595 SDValue LO, HI;
16597 // The ECX register is used to select the index of the performance counter
16598 // to read.
16599 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
16600 N->getOperand(2));
16601 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
16603 // Reads the content of a 64-bit performance counter and returns it in the
16604 // registers EDX:EAX.
16605 if (Subtarget->is64Bit()) {
16606 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16607 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16608 LO.getValue(2));
16609 } else {
16610 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16611 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16612 LO.getValue(2));
16613 }
16614 Chain = HI.getValue(1);
16616 if (Subtarget->is64Bit()) {
16617 // The EAX register is loaded with the low-order 32 bits. The EDX register
16618 // is loaded with the supported high-order bits of the counter.
16619 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16620 DAG.getConstant(32, MVT::i8));
16621 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16622 Results.push_back(Chain);
16623 return;
16624 }
16626 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16627 SDValue Ops[] = { LO, HI };
16628 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16629 Results.push_back(Pair);
16630 Results.push_back(Chain);
16631 }
16633 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
16634 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
16635 // also used to custom lower READCYCLECOUNTER nodes.
16636 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
16637 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16638 SmallVectorImpl<SDValue> &Results) {
16639 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16640 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
16641 SDValue LO, HI;
16643 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
16644 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
16645 // and the EAX register is loaded with the low-order 32 bits.
16646 if (Subtarget->is64Bit()) {
16647 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16648 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16649 LO.getValue(2));
16650 } else {
16651 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16652 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16653 LO.getValue(2));
16654 }
16655 SDValue Chain = HI.getValue(1);
16657 if (Opcode == X86ISD::RDTSCP_DAG) {
16658 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16660 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
16661 // the ECX register. Add 'ecx' explicitly to the chain.
16662 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
16663 HI.getValue(2));
16664 // Explicitly store the content of ECX at the location passed in input
16665 // to the 'rdtscp' intrinsic.
16666 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
16667 MachinePointerInfo(), false, false, 0);
16668 }
16670 if (Subtarget->is64Bit()) {
16671 // The EDX register is loaded with the high-order 32 bits of the MSR, and
16672 // the EAX register is loaded with the low-order 32 bits.
16673 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16674 DAG.getConstant(32, MVT::i8));
16675 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16676 Results.push_back(Chain);
16677 return;
16678 }
16680 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16681 SDValue Ops[] = { LO, HI };
16682 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16683 Results.push_back(Pair);
16684 Results.push_back(Chain);
16685 }
16687 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
16688 SelectionDAG &DAG) {
16689 SmallVector<SDValue, 2> Results;
16690 SDLoc DL(Op);
16691 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
16692 Results);
16693 return DAG.getMergeValues(Results, DL);
16694 }
16697 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16698 SelectionDAG &DAG) {
16699 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
16701 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
16702 if (!IntrData)
16703 return SDValue();
16705 SDLoc dl(Op);
16706 switch(IntrData->Type) {
16707 default:
16708 llvm_unreachable("Unknown Intrinsic Type");
16709 break;
16710 case RDSEED:
16711 case RDRAND: {
16712 // Emit the node with the right value type.
16713 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
16714 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16716 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
16717 // Otherwise return the value from Rand, which is always 0, casted to i32.
16718 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
16719 DAG.getConstant(1, Op->getValueType(1)),
16720 DAG.getConstant(X86::COND_B, MVT::i32),
16721 SDValue(Result.getNode(), 1) };
16722 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
16723 DAG.getVTList(Op->getValueType(1), MVT::Glue),
16724 Ops);
16726 // Return { result, isValid, chain }.
16727 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
16728 SDValue(Result.getNode(), 2));
16729 }
16730 case GATHER: {
16731 //gather(v1, mask, index, base, scale);
16732 SDValue Chain = Op.getOperand(0);
16733 SDValue Src = Op.getOperand(2);
16734 SDValue Base = Op.getOperand(3);
16735 SDValue Index = Op.getOperand(4);
16736 SDValue Mask = Op.getOperand(5);
16737 SDValue Scale = Op.getOperand(6);
16738 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
16739 Subtarget);
16740 }
16741 case SCATTER: {
16742 //scatter(base, mask, index, v1, scale);
16743 SDValue Chain = Op.getOperand(0);
16744 SDValue Base = Op.getOperand(2);
16745 SDValue Mask = Op.getOperand(3);
16746 SDValue Index = Op.getOperand(4);
16747 SDValue Src = Op.getOperand(5);
16748 SDValue Scale = Op.getOperand(6);
16749 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
16750 }
16751 case PREFETCH: {
16752 SDValue Hint = Op.getOperand(6);
16753 unsigned HintVal;
16754 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
16755 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
16756 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
16757 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
16758 SDValue Chain = Op.getOperand(0);
16759 SDValue Mask = Op.getOperand(2);
16760 SDValue Index = Op.getOperand(3);
16761 SDValue Base = Op.getOperand(4);
16762 SDValue Scale = Op.getOperand(5);
16763 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
16764 }
16765 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
16766 case RDTSC: {
16767 SmallVector<SDValue, 2> Results;
16768 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
16769 return DAG.getMergeValues(Results, dl);
16770 }
16771 // Read Performance Monitoring Counters.
16772 case RDPMC: {
16773 SmallVector<SDValue, 2> Results;
16774 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
16775 return DAG.getMergeValues(Results, dl);
16776 }
16777 // XTEST intrinsics.
16778 case XTEST: {
16779 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16780 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16781 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16782 DAG.getConstant(X86::COND_NE, MVT::i8),
16783 InTrans);
16784 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
16785 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
16786 Ret, SDValue(InTrans.getNode(), 1));
16787 }
16788 // ADC/ADCX/SBB
16789 case ADX: {
16790 SmallVector<SDValue, 2> Results;
16791 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16792 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
16793 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
16794 DAG.getConstant(-1, MVT::i8));
16795 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
16796 Op.getOperand(4), GenCF.getValue(1));
16797 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
16798 Op.getOperand(5), MachinePointerInfo(),
16799 false, false, 0);
16800 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16801 DAG.getConstant(X86::COND_B, MVT::i8),
16802 Res.getValue(1));
16803 Results.push_back(SetCC);
16804 Results.push_back(Store);
16805 return DAG.getMergeValues(Results, dl);
16806 }
16807 }
16808 }
16810 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
16811 SelectionDAG &DAG) const {
16812 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16813 MFI->setReturnAddressIsTaken(true);
16815 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
16816 return SDValue();
16818 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16819 SDLoc dl(Op);
16820 EVT PtrVT = getPointerTy();
16822 if (Depth > 0) {
16823 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
16824 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16825 DAG.getSubtarget().getRegisterInfo());
16826 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
16827 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16828 DAG.getNode(ISD::ADD, dl, PtrVT,
16829 FrameAddr, Offset),
16830 MachinePointerInfo(), false, false, false, 0);
16831 }
16833 // Just load the return address.
16834 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
16835 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16836 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
16837 }
16839 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
16840 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16841 MFI->setFrameAddressIsTaken(true);
16843 EVT VT = Op.getValueType();
16844 SDLoc dl(Op); // FIXME probably not meaningful
16845 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16846 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16847 DAG.getSubtarget().getRegisterInfo());
16848 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16849 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
16850 (FrameReg == X86::EBP && VT == MVT::i32)) &&
16851 "Invalid Frame Register!");
16852 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
16853 while (Depth--)
16854 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
16855 MachinePointerInfo(),
16856 false, false, false, 0);
16857 return FrameAddr;
16858 }
16860 // FIXME? Maybe this could be a TableGen attribute on some registers and
16861 // this table could be generated automatically from RegInfo.
16862 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
16863 EVT VT) const {
16864 unsigned Reg = StringSwitch<unsigned>(RegName)
16865 .Case("esp", X86::ESP)
16866 .Case("rsp", X86::RSP)
16867 .Default(0);
16868 if (Reg)
16869 return Reg;
16870 report_fatal_error("Invalid register name global variable");
16871 }
16873 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
16874 SelectionDAG &DAG) const {
16875 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16876 DAG.getSubtarget().getRegisterInfo());
16877 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
16878 }
16880 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
16881 SDValue Chain = Op.getOperand(0);
16882 SDValue Offset = Op.getOperand(1);
16883 SDValue Handler = Op.getOperand(2);
16884 SDLoc dl (Op);
16886 EVT PtrVT = getPointerTy();
16887 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16888 DAG.getSubtarget().getRegisterInfo());
16889 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16890 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
16891 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
16892 "Invalid Frame Register!");
16893 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
16894 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
16896 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
16897 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
16898 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
16899 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
16900 false, false, 0);
16901 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
16903 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
16904 DAG.getRegister(StoreAddrReg, PtrVT));
16905 }
16907 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
16908 SelectionDAG &DAG) const {
16909 SDLoc DL(Op);
16910 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
16911 DAG.getVTList(MVT::i32, MVT::Other),
16912 Op.getOperand(0), Op.getOperand(1));
16913 }
16915 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
16916 SelectionDAG &DAG) const {
16917 SDLoc DL(Op);
16918 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
16919 Op.getOperand(0), Op.getOperand(1));
16920 }
16922 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
16923 return Op.getOperand(0);
16924 }
16926 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
16927 SelectionDAG &DAG) const {
16928 SDValue Root = Op.getOperand(0);
16929 SDValue Trmp = Op.getOperand(1); // trampoline
16930 SDValue FPtr = Op.getOperand(2); // nested function
16931 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
16932 SDLoc dl (Op);
16934 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16935 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
16937 if (Subtarget->is64Bit()) {
16938 SDValue OutChains[6];
16940 // Large code-model.
16941 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
16942 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
16944 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
16945 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
16947 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
16949 // Load the pointer to the nested function into R11.
16950 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
16951 SDValue Addr = Trmp;
16952 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16953 Addr, MachinePointerInfo(TrmpAddr),
16954 false, false, 0);
16956 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16957 DAG.getConstant(2, MVT::i64));
16958 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
16959 MachinePointerInfo(TrmpAddr, 2),
16960 false, false, 2);
16962 // Load the 'nest' parameter value into R10.
16963 // R10 is specified in X86CallingConv.td
16964 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
16965 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16966 DAG.getConstant(10, MVT::i64));
16967 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16968 Addr, MachinePointerInfo(TrmpAddr, 10),
16969 false, false, 0);
16971 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16972 DAG.getConstant(12, MVT::i64));
16973 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
16974 MachinePointerInfo(TrmpAddr, 12),
16975 false, false, 2);
16977 // Jump to the nested function.
16978 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
16979 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16980 DAG.getConstant(20, MVT::i64));
16981 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16982 Addr, MachinePointerInfo(TrmpAddr, 20),
16983 false, false, 0);
16985 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
16986 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16987 DAG.getConstant(22, MVT::i64));
16988 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
16989 MachinePointerInfo(TrmpAddr, 22),
16990 false, false, 0);
16992 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16993 } else {
16994 const Function *Func =
16995 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
16996 CallingConv::ID CC = Func->getCallingConv();
16997 unsigned NestReg;
16999 switch (CC) {
17000 default:
17001 llvm_unreachable("Unsupported calling convention");
17002 case CallingConv::C:
17003 case CallingConv::X86_StdCall: {
17004 // Pass 'nest' parameter in ECX.
17005 // Must be kept in sync with X86CallingConv.td
17006 NestReg = X86::ECX;
17008 // Check that ECX wasn't needed by an 'inreg' parameter.
17009 FunctionType *FTy = Func->getFunctionType();
17010 const AttributeSet &Attrs = Func->getAttributes();
17012 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17013 unsigned InRegCount = 0;
17014 unsigned Idx = 1;
17016 for (FunctionType::param_iterator I = FTy->param_begin(),
17017 E = FTy->param_end(); I != E; ++I, ++Idx)
17018 if (Attrs.hasAttribute(Idx, Attribute::InReg))
17019 // FIXME: should only count parameters that are lowered to integers.
17020 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
17022 if (InRegCount > 2) {
17023 report_fatal_error("Nest register in use - reduce number of inreg"
17024 " parameters!");
17025 }
17026 }
17027 break;
17028 }
17029 case CallingConv::X86_FastCall:
17030 case CallingConv::X86_ThisCall:
17031 case CallingConv::Fast:
17032 // Pass 'nest' parameter in EAX.
17033 // Must be kept in sync with X86CallingConv.td
17034 NestReg = X86::EAX;
17035 break;
17036 }
17038 SDValue OutChains[4];
17039 SDValue Addr, Disp;
17041 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17042 DAG.getConstant(10, MVT::i32));
17043 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17045 // This is storing the opcode for MOV32ri.
17046 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17047 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17048 OutChains[0] = DAG.getStore(Root, dl,
17049 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
17050 Trmp, MachinePointerInfo(TrmpAddr),
17051 false, false, 0);
17053 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17054 DAG.getConstant(1, MVT::i32));
17055 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17056 MachinePointerInfo(TrmpAddr, 1),
17057 false, false, 1);
17059 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17060 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17061 DAG.getConstant(5, MVT::i32));
17062 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
17063 MachinePointerInfo(TrmpAddr, 5),
17064 false, false, 1);
17066 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17067 DAG.getConstant(6, MVT::i32));
17068 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17069 MachinePointerInfo(TrmpAddr, 6),
17070 false, false, 1);
17072 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17073 }
17074 }
17076 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17077 SelectionDAG &DAG) const {
17078 /*
17079 The rounding mode is in bits 11:10 of FPSR, and has the following
17080 settings:
17081 00 Round to nearest
17082 01 Round to -inf
17083 10 Round to +inf
17084 11 Round to 0
17086 FLT_ROUNDS, on the other hand, expects the following:
17087 -1 Undefined
17088 0 Round to 0
17089 1 Round to nearest
17090 2 Round to +inf
17091 3 Round to -inf
17093 To perform the conversion, we do:
17094 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17095 */
17097 MachineFunction &MF = DAG.getMachineFunction();
17098 const TargetMachine &TM = MF.getTarget();
17099 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
17100 unsigned StackAlignment = TFI.getStackAlignment();
17101 MVT VT = Op.getSimpleValueType();
17102 SDLoc DL(Op);
17104 // Save FP Control Word to stack slot
17105 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17106 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
17108 MachineMemOperand *MMO =
17109 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
17110 MachineMemOperand::MOStore, 2, 2);
17112 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17113 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17114 DAG.getVTList(MVT::Other),
17115 Ops, MVT::i16, MMO);
17117 // Load FP Control Word from stack slot
17118 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17119 MachinePointerInfo(), false, false, false, 0);
17121 // Transform as necessary
17122 SDValue CWD1 =
17123 DAG.getNode(ISD::SRL, DL, MVT::i16,
17124 DAG.getNode(ISD::AND, DL, MVT::i16,
17125 CWD, DAG.getConstant(0x800, MVT::i16)),
17126 DAG.getConstant(11, MVT::i8));
17127 SDValue CWD2 =
17128 DAG.getNode(ISD::SRL, DL, MVT::i16,
17129 DAG.getNode(ISD::AND, DL, MVT::i16,
17130 CWD, DAG.getConstant(0x400, MVT::i16)),
17131 DAG.getConstant(9, MVT::i8));
17133 SDValue RetVal =
17134 DAG.getNode(ISD::AND, DL, MVT::i16,
17135 DAG.getNode(ISD::ADD, DL, MVT::i16,
17136 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17137 DAG.getConstant(1, MVT::i16)),
17138 DAG.getConstant(3, MVT::i16));
17140 return DAG.getNode((VT.getSizeInBits() < 16 ?
17141 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17142 }
17144 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17145 MVT VT = Op.getSimpleValueType();
17146 EVT OpVT = VT;
17147 unsigned NumBits = VT.getSizeInBits();
17148 SDLoc dl(Op);
17150 Op = Op.getOperand(0);
17151 if (VT == MVT::i8) {
17152 // Zero extend to i32 since there is not an i8 bsr.
17153 OpVT = MVT::i32;
17154 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17155 }
17157 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17158 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17159 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17161 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17162 SDValue Ops[] = {
17163 Op,
17164 DAG.getConstant(NumBits+NumBits-1, OpVT),
17165 DAG.getConstant(X86::COND_E, MVT::i8),
17166 Op.getValue(1)
17167 };
17168 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17170 // Finally xor with NumBits-1.
17171 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17173 if (VT == MVT::i8)
17174 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17175 return Op;
17176 }
17178 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
17179 MVT VT = Op.getSimpleValueType();
17180 EVT OpVT = VT;
17181 unsigned NumBits = VT.getSizeInBits();
17182 SDLoc dl(Op);
17184 Op = Op.getOperand(0);
17185 if (VT == MVT::i8) {
17186 // Zero extend to i32 since there is not an i8 bsr.
17187 OpVT = MVT::i32;
17188 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17189 }
17191 // Issue a bsr (scan bits in reverse).
17192 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17193 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17195 // And xor with NumBits-1.
17196 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17198 if (VT == MVT::i8)
17199 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17200 return Op;
17201 }
17203 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17204 MVT VT = Op.getSimpleValueType();
17205 unsigned NumBits = VT.getSizeInBits();
17206 SDLoc dl(Op);
17207 Op = Op.getOperand(0);
17209 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17210 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17211 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
17213 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17214 SDValue Ops[] = {
17215 Op,
17216 DAG.getConstant(NumBits, VT),
17217 DAG.getConstant(X86::COND_E, MVT::i8),
17218 Op.getValue(1)
17219 };
17220 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17221 }
17223 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17224 // ones, and then concatenate the result back.
17225 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17226 MVT VT = Op.getSimpleValueType();
17228 assert(VT.is256BitVector() && VT.isInteger() &&
17229 "Unsupported value type for operation");
17231 unsigned NumElems = VT.getVectorNumElements();
17232 SDLoc dl(Op);
17234 // Extract the LHS vectors
17235 SDValue LHS = Op.getOperand(0);
17236 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17237 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17239 // Extract the RHS vectors
17240 SDValue RHS = Op.getOperand(1);
17241 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17242 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17244 MVT EltVT = VT.getVectorElementType();
17245 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17247 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17248 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17249 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17250 }
17252 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17253 assert(Op.getSimpleValueType().is256BitVector() &&
17254 Op.getSimpleValueType().isInteger() &&
17255 "Only handle AVX 256-bit vector integer operation");
17256 return Lower256IntArith(Op, DAG);
17257 }
17259 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17260 assert(Op.getSimpleValueType().is256BitVector() &&
17261 Op.getSimpleValueType().isInteger() &&
17262 "Only handle AVX 256-bit vector integer operation");
17263 return Lower256IntArith(Op, DAG);
17264 }
17266 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17267 SelectionDAG &DAG) {
17268 SDLoc dl(Op);
17269 MVT VT = Op.getSimpleValueType();
17271 // Decompose 256-bit ops into smaller 128-bit ops.
17272 if (VT.is256BitVector() && !Subtarget->hasInt256())
17273 return Lower256IntArith(Op, DAG);
17275 SDValue A = Op.getOperand(0);
17276 SDValue B = Op.getOperand(1);
17278 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
17279 if (VT == MVT::v4i32) {
17280 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
17281 "Should not custom lower when pmuldq is available!");
17283 // Extract the odd parts.
17284 static const int UnpackMask[] = { 1, -1, 3, -1 };
17285 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
17286 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
17288 // Multiply the even parts.
17289 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
17290 // Now multiply odd parts.
17291 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
17293 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
17294 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
17296 // Merge the two vectors back together with a shuffle. This expands into 2
17297 // shuffles.
17298 static const int ShufMask[] = { 0, 4, 2, 6 };
17299 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
17300 }
17302 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
17303 "Only know how to lower V2I64/V4I64/V8I64 multiply");
17305 // Ahi = psrlqi(a, 32);
17306 // Bhi = psrlqi(b, 32);
17307 //
17308 // AloBlo = pmuludq(a, b);
17309 // AloBhi = pmuludq(a, Bhi);
17310 // AhiBlo = pmuludq(Ahi, b);
17312 // AloBhi = psllqi(AloBhi, 32);
17313 // AhiBlo = psllqi(AhiBlo, 32);
17314 // return AloBlo + AloBhi + AhiBlo;
17316 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
17317 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
17319 // Bit cast to 32-bit vectors for MULUDQ
17320 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
17321 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
17322 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
17323 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
17324 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
17325 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
17327 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
17328 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
17329 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
17331 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
17332 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
17334 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
17335 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
17336 }
17338 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
17339 assert(Subtarget->isTargetWin64() && "Unexpected target");
17340 EVT VT = Op.getValueType();
17341 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
17342 "Unexpected return type for lowering");
17344 RTLIB::Libcall LC;
17345 bool isSigned;
17346 switch (Op->getOpcode()) {
17347 default: llvm_unreachable("Unexpected request for libcall!");
17348 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
17349 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
17350 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
17351 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
17352 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
17353 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
17354 }
17356 SDLoc dl(Op);
17357 SDValue InChain = DAG.getEntryNode();
17359 TargetLowering::ArgListTy Args;
17360 TargetLowering::ArgListEntry Entry;
17361 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
17362 EVT ArgVT = Op->getOperand(i).getValueType();
17363 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
17364 "Unexpected argument type for lowering");
17365 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
17366 Entry.Node = StackPtr;
17367 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
17368 false, false, 16);
17369 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17370 Entry.Ty = PointerType::get(ArgTy,0);
17371 Entry.isSExt = false;
17372 Entry.isZExt = false;
17373 Args.push_back(Entry);
17374 }
17376 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
17377 getPointerTy());
17379 TargetLowering::CallLoweringInfo CLI(DAG);
17380 CLI.setDebugLoc(dl).setChain(InChain)
17381 .setCallee(getLibcallCallingConv(LC),
17382 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
17383 Callee, std::move(Args), 0)
17384 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
17386 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
17387 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
17388 }
17390 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
17391 SelectionDAG &DAG) {
17392 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
17393 EVT VT = Op0.getValueType();
17394 SDLoc dl(Op);
17396 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
17397 (VT == MVT::v8i32 && Subtarget->hasInt256()));
17399 // PMULxD operations multiply each even value (starting at 0) of LHS with
17400 // the related value of RHS and produce a widen result.
17401 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17402 // => <2 x i64> <ae|cg>
17403 //
17404 // In other word, to have all the results, we need to perform two PMULxD:
17405 // 1. one with the even values.
17406 // 2. one with the odd values.
17407 // To achieve #2, with need to place the odd values at an even position.
17408 //
17409 // Place the odd value at an even position (basically, shift all values 1
17410 // step to the left):
17411 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
17412 // <a|b|c|d> => <b|undef|d|undef>
17413 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
17414 // <e|f|g|h> => <f|undef|h|undef>
17415 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
17417 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
17418 // ints.
17419 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
17420 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
17421 unsigned Opcode =
17422 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
17423 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17424 // => <2 x i64> <ae|cg>
17425 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
17426 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
17427 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
17428 // => <2 x i64> <bf|dh>
17429 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
17430 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
17432 // Shuffle it back into the right order.
17433 SDValue Highs, Lows;
17434 if (VT == MVT::v8i32) {
17435 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
17436 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17437 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
17438 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17439 } else {
17440 const int HighMask[] = {1, 5, 3, 7};
17441 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17442 const int LowMask[] = {0, 4, 2, 6};
17443 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17444 }
17446 // If we have a signed multiply but no PMULDQ fix up the high parts of a
17447 // unsigned multiply.
17448 if (IsSigned && !Subtarget->hasSSE41()) {
17449 SDValue ShAmt =
17450 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
17451 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
17452 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
17453 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
17454 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
17456 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
17457 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
17458 }
17460 // The first result of MUL_LOHI is actually the low value, followed by the
17461 // high value.
17462 SDValue Ops[] = {Lows, Highs};
17463 return DAG.getMergeValues(Ops, dl);
17464 }
17466 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
17467 const X86Subtarget *Subtarget) {
17468 MVT VT = Op.getSimpleValueType();
17469 SDLoc dl(Op);
17470 SDValue R = Op.getOperand(0);
17471 SDValue Amt = Op.getOperand(1);
17473 // Optimize shl/srl/sra with constant shift amount.
17474 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
17475 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
17476 uint64_t ShiftAmt = ShiftConst->getZExtValue();
17478 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
17479 (Subtarget->hasInt256() &&
17480 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
17481 (Subtarget->hasAVX512() &&
17482 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
17483 if (Op.getOpcode() == ISD::SHL)
17484 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
17485 DAG);
17486 if (Op.getOpcode() == ISD::SRL)
17487 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
17488 DAG);
17489 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
17490 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
17491 DAG);
17492 }
17494 if (VT == MVT::v16i8) {
17495 if (Op.getOpcode() == ISD::SHL) {
17496 // Make a large shift.
17497 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
17498 MVT::v8i16, R, ShiftAmt,
17499 DAG);
17500 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
17501 // Zero out the rightmost bits.
17502 SmallVector<SDValue, 16> V(16,
17503 DAG.getConstant(uint8_t(-1U << ShiftAmt),
17504 MVT::i8));
17505 return DAG.getNode(ISD::AND, dl, VT, SHL,
17506 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17507 }
17508 if (Op.getOpcode() == ISD::SRL) {
17509 // Make a large shift.
17510 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
17511 MVT::v8i16, R, ShiftAmt,
17512 DAG);
17513 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
17514 // Zero out the leftmost bits.
17515 SmallVector<SDValue, 16> V(16,
17516 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
17517 MVT::i8));
17518 return DAG.getNode(ISD::AND, dl, VT, SRL,
17519 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17520 }
17521 if (Op.getOpcode() == ISD::SRA) {
17522 if (ShiftAmt == 7) {
17523 // R s>> 7 === R s< 0
17524 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17525 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17526 }
17528 // R s>> a === ((R u>> a) ^ m) - m
17529 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17530 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
17531 MVT::i8));
17532 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17533 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17534 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17535 return Res;
17536 }
17537 llvm_unreachable("Unknown shift opcode.");
17538 }
17540 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
17541 if (Op.getOpcode() == ISD::SHL) {
17542 // Make a large shift.
17543 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
17544 MVT::v16i16, R, ShiftAmt,
17545 DAG);
17546 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
17547 // Zero out the rightmost bits.
17548 SmallVector<SDValue, 32> V(32,
17549 DAG.getConstant(uint8_t(-1U << ShiftAmt),
17550 MVT::i8));
17551 return DAG.getNode(ISD::AND, dl, VT, SHL,
17552 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17553 }
17554 if (Op.getOpcode() == ISD::SRL) {
17555 // Make a large shift.
17556 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
17557 MVT::v16i16, R, ShiftAmt,
17558 DAG);
17559 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
17560 // Zero out the leftmost bits.
17561 SmallVector<SDValue, 32> V(32,
17562 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
17563 MVT::i8));
17564 return DAG.getNode(ISD::AND, dl, VT, SRL,
17565 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17566 }
17567 if (Op.getOpcode() == ISD::SRA) {
17568 if (ShiftAmt == 7) {
17569 // R s>> 7 === R s< 0
17570 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17571 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17572 }
17574 // R s>> a === ((R u>> a) ^ m) - m
17575 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17576 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
17577 MVT::i8));
17578 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17579 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17580 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17581 return Res;
17582 }
17583 llvm_unreachable("Unknown shift opcode.");
17584 }
17585 }
17586 }
17588 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17589 if (!Subtarget->is64Bit() &&
17590 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
17591 Amt.getOpcode() == ISD::BITCAST &&
17592 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17593 Amt = Amt.getOperand(0);
17594 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17595 VT.getVectorNumElements();
17596 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
17597 uint64_t ShiftAmt = 0;
17598 for (unsigned i = 0; i != Ratio; ++i) {
17599 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
17600 if (!C)
17601 return SDValue();
17602 // 6 == Log2(64)
17603 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
17604 }
17605 // Check remaining shift amounts.
17606 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17607 uint64_t ShAmt = 0;
17608 for (unsigned j = 0; j != Ratio; ++j) {
17609 ConstantSDNode *C =
17610 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
17611 if (!C)
17612 return SDValue();
17613 // 6 == Log2(64)
17614 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
17615 }
17616 if (ShAmt != ShiftAmt)
17617 return SDValue();
17618 }
17619 switch (Op.getOpcode()) {
17620 default:
17621 llvm_unreachable("Unknown shift opcode!");
17622 case ISD::SHL:
17623 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
17624 DAG);
17625 case ISD::SRL:
17626 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
17627 DAG);
17628 case ISD::SRA:
17629 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
17630 DAG);
17631 }
17632 }
17634 return SDValue();
17635 }
17637 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
17638 const X86Subtarget* Subtarget) {
17639 MVT VT = Op.getSimpleValueType();
17640 SDLoc dl(Op);
17641 SDValue R = Op.getOperand(0);
17642 SDValue Amt = Op.getOperand(1);
17644 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
17645 VT == MVT::v4i32 || VT == MVT::v8i16 ||
17646 (Subtarget->hasInt256() &&
17647 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
17648 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
17649 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
17650 SDValue BaseShAmt;
17651 EVT EltVT = VT.getVectorElementType();
17653 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
17654 unsigned NumElts = VT.getVectorNumElements();
17655 unsigned i, j;
17656 for (i = 0; i != NumElts; ++i) {
17657 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
17658 continue;
17659 break;
17660 }
17661 for (j = i; j != NumElts; ++j) {
17662 SDValue Arg = Amt.getOperand(j);
17663 if (Arg.getOpcode() == ISD::UNDEF) continue;
17664 if (Arg != Amt.getOperand(i))
17665 break;
17666 }
17667 if (i != NumElts && j == NumElts)
17668 BaseShAmt = Amt.getOperand(i);
17669 } else {
17670 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
17671 Amt = Amt.getOperand(0);
17672 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
17673 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
17674 SDValue InVec = Amt.getOperand(0);
17675 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
17676 unsigned NumElts = InVec.getValueType().getVectorNumElements();
17677 unsigned i = 0;
17678 for (; i != NumElts; ++i) {
17679 SDValue Arg = InVec.getOperand(i);
17680 if (Arg.getOpcode() == ISD::UNDEF) continue;
17681 BaseShAmt = Arg;
17682 break;
17683 }
17684 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
17685 if (ConstantSDNode *C =
17686 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
17687 unsigned SplatIdx =
17688 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
17689 if (C->getZExtValue() == SplatIdx)
17690 BaseShAmt = InVec.getOperand(1);
17691 }
17692 }
17693 if (!BaseShAmt.getNode())
17694 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
17695 DAG.getIntPtrConstant(0));
17696 }
17697 }
17699 if (BaseShAmt.getNode()) {
17700 if (EltVT.bitsGT(MVT::i32))
17701 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
17702 else if (EltVT.bitsLT(MVT::i32))
17703 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
17705 switch (Op.getOpcode()) {
17706 default:
17707 llvm_unreachable("Unknown shift opcode!");
17708 case ISD::SHL:
17709 switch (VT.SimpleTy) {
17710 default: return SDValue();
17711 case MVT::v2i64:
17712 case MVT::v4i32:
17713 case MVT::v8i16:
17714 case MVT::v4i64:
17715 case MVT::v8i32:
17716 case MVT::v16i16:
17717 case MVT::v16i32:
17718 case MVT::v8i64:
17719 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
17720 }
17721 case ISD::SRA:
17722 switch (VT.SimpleTy) {
17723 default: return SDValue();
17724 case MVT::v4i32:
17725 case MVT::v8i16:
17726 case MVT::v8i32:
17727 case MVT::v16i16:
17728 case MVT::v16i32:
17729 case MVT::v8i64:
17730 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
17731 }
17732 case ISD::SRL:
17733 switch (VT.SimpleTy) {
17734 default: return SDValue();
17735 case MVT::v2i64:
17736 case MVT::v4i32:
17737 case MVT::v8i16:
17738 case MVT::v4i64:
17739 case MVT::v8i32:
17740 case MVT::v16i16:
17741 case MVT::v16i32:
17742 case MVT::v8i64:
17743 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
17744 }
17745 }
17746 }
17747 }
17749 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17750 if (!Subtarget->is64Bit() &&
17751 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
17752 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
17753 Amt.getOpcode() == ISD::BITCAST &&
17754 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17755 Amt = Amt.getOperand(0);
17756 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17757 VT.getVectorNumElements();
17758 std::vector<SDValue> Vals(Ratio);
17759 for (unsigned i = 0; i != Ratio; ++i)
17760 Vals[i] = Amt.getOperand(i);
17761 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17762 for (unsigned j = 0; j != Ratio; ++j)
17763 if (Vals[j] != Amt.getOperand(i + j))
17764 return SDValue();
17765 }
17766 switch (Op.getOpcode()) {
17767 default:
17768 llvm_unreachable("Unknown shift opcode!");
17769 case ISD::SHL:
17770 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
17771 case ISD::SRL:
17772 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
17773 case ISD::SRA:
17774 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
17775 }
17776 }
17778 return SDValue();
17779 }
17781 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
17782 SelectionDAG &DAG) {
17783 MVT VT = Op.getSimpleValueType();
17784 SDLoc dl(Op);
17785 SDValue R = Op.getOperand(0);
17786 SDValue Amt = Op.getOperand(1);
17787 SDValue V;
17789 assert(VT.isVector() && "Custom lowering only for vector shifts!");
17790 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
17792 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
17793 if (V.getNode())
17794 return V;
17796 V = LowerScalarVariableShift(Op, DAG, Subtarget);
17797 if (V.getNode())
17798 return V;
17800 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
17801 return Op;
17802 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
17803 if (Subtarget->hasInt256()) {
17804 if (Op.getOpcode() == ISD::SRL &&
17805 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
17806 VT == MVT::v4i64 || VT == MVT::v8i32))
17807 return Op;
17808 if (Op.getOpcode() == ISD::SHL &&
17809 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
17810 VT == MVT::v4i64 || VT == MVT::v8i32))
17811 return Op;
17812 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
17813 return Op;
17814 }
17816 // If possible, lower this packed shift into a vector multiply instead of
17817 // expanding it into a sequence of scalar shifts.
17818 // Do this only if the vector shift count is a constant build_vector.
17819 if (Op.getOpcode() == ISD::SHL &&
17820 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
17821 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
17822 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17823 SmallVector<SDValue, 8> Elts;
17824 EVT SVT = VT.getScalarType();
17825 unsigned SVTBits = SVT.getSizeInBits();
17826 const APInt &One = APInt(SVTBits, 1);
17827 unsigned NumElems = VT.getVectorNumElements();
17829 for (unsigned i=0; i !=NumElems; ++i) {
17830 SDValue Op = Amt->getOperand(i);
17831 if (Op->getOpcode() == ISD::UNDEF) {
17832 Elts.push_back(Op);
17833 continue;
17834 }
17836 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
17837 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
17838 uint64_t ShAmt = C.getZExtValue();
17839 if (ShAmt >= SVTBits) {
17840 Elts.push_back(DAG.getUNDEF(SVT));
17841 continue;
17842 }
17843 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
17844 }
17845 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
17846 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
17847 }
17849 // Lower SHL with variable shift amount.
17850 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
17851 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
17853 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
17854 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
17855 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
17856 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
17857 }
17859 // If possible, lower this shift as a sequence of two shifts by
17860 // constant plus a MOVSS/MOVSD instead of scalarizing it.
17861 // Example:
17862 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
17863 //
17864 // Could be rewritten as:
17865 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
17866 //
17867 // The advantage is that the two shifts from the example would be
17868 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
17869 // the vector shift into four scalar shifts plus four pairs of vector
17870 // insert/extract.
17871 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
17872 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17873 unsigned TargetOpcode = X86ISD::MOVSS;
17874 bool CanBeSimplified;
17875 // The splat value for the first packed shift (the 'X' from the example).
17876 SDValue Amt1 = Amt->getOperand(0);
17877 // The splat value for the second packed shift (the 'Y' from the example).
17878 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
17879 Amt->getOperand(2);
17881 // See if it is possible to replace this node with a sequence of
17882 // two shifts followed by a MOVSS/MOVSD
17883 if (VT == MVT::v4i32) {
17884 // Check if it is legal to use a MOVSS.
17885 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
17886 Amt2 == Amt->getOperand(3);
17887 if (!CanBeSimplified) {
17888 // Otherwise, check if we can still simplify this node using a MOVSD.
17889 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
17890 Amt->getOperand(2) == Amt->getOperand(3);
17891 TargetOpcode = X86ISD::MOVSD;
17892 Amt2 = Amt->getOperand(2);
17893 }
17894 } else {
17895 // Do similar checks for the case where the machine value type
17896 // is MVT::v8i16.
17897 CanBeSimplified = Amt1 == Amt->getOperand(1);
17898 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
17899 CanBeSimplified = Amt2 == Amt->getOperand(i);
17901 if (!CanBeSimplified) {
17902 TargetOpcode = X86ISD::MOVSD;
17903 CanBeSimplified = true;
17904 Amt2 = Amt->getOperand(4);
17905 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
17906 CanBeSimplified = Amt1 == Amt->getOperand(i);
17907 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
17908 CanBeSimplified = Amt2 == Amt->getOperand(j);
17909 }
17910 }
17912 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
17913 isa<ConstantSDNode>(Amt2)) {
17914 // Replace this node with two shifts followed by a MOVSS/MOVSD.
17915 EVT CastVT = MVT::v4i32;
17916 SDValue Splat1 =
17917 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
17918 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
17919 SDValue Splat2 =
17920 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
17921 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
17922 if (TargetOpcode == X86ISD::MOVSD)
17923 CastVT = MVT::v2i64;
17924 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
17925 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
17926 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
17927 BitCast1, DAG);
17928 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
17929 }
17930 }
17932 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
17933 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
17935 // a = a << 5;
17936 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
17937 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
17939 // Turn 'a' into a mask suitable for VSELECT
17940 SDValue VSelM = DAG.getConstant(0x80, VT);
17941 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17942 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17944 SDValue CM1 = DAG.getConstant(0x0f, VT);
17945 SDValue CM2 = DAG.getConstant(0x3f, VT);
17947 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
17948 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
17949 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
17950 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
17951 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
17953 // a += a
17954 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
17955 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17956 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17958 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
17959 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
17960 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
17961 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
17962 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
17964 // a += a
17965 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
17966 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17967 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17969 // return VSELECT(r, r+r, a);
17970 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
17971 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
17972 return R;
17973 }
17975 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
17976 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
17977 // solution better.
17978 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
17979 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
17980 unsigned ExtOpc =
17981 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
17982 R = DAG.getNode(ExtOpc, dl, NewVT, R);
17983 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
17984 return DAG.getNode(ISD::TRUNCATE, dl, VT,
17985 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
17986 }
17988 // Decompose 256-bit shifts into smaller 128-bit shifts.
17989 if (VT.is256BitVector()) {
17990 unsigned NumElems = VT.getVectorNumElements();
17991 MVT EltVT = VT.getVectorElementType();
17992 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17994 // Extract the two vectors
17995 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
17996 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
17998 // Recreate the shift amount vectors
17999 SDValue Amt1, Amt2;
18000 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18001 // Constant shift amount
18002 SmallVector<SDValue, 4> Amt1Csts;
18003 SmallVector<SDValue, 4> Amt2Csts;
18004 for (unsigned i = 0; i != NumElems/2; ++i)
18005 Amt1Csts.push_back(Amt->getOperand(i));
18006 for (unsigned i = NumElems/2; i != NumElems; ++i)
18007 Amt2Csts.push_back(Amt->getOperand(i));
18009 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18010 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18011 } else {
18012 // Variable shift amount
18013 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18014 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18015 }
18017 // Issue new vector shifts for the smaller types
18018 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18019 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18021 // Concatenate the result back
18022 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18023 }
18025 return SDValue();
18026 }
18028 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18029 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18030 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18031 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18032 // has only one use.
18033 SDNode *N = Op.getNode();
18034 SDValue LHS = N->getOperand(0);
18035 SDValue RHS = N->getOperand(1);
18036 unsigned BaseOp = 0;
18037 unsigned Cond = 0;
18038 SDLoc DL(Op);
18039 switch (Op.getOpcode()) {
18040 default: llvm_unreachable("Unknown ovf instruction!");
18041 case ISD::SADDO:
18042 // A subtract of one will be selected as a INC. Note that INC doesn't
18043 // set CF, so we can't do this for UADDO.
18044 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18045 if (C->isOne()) {
18046 BaseOp = X86ISD::INC;
18047 Cond = X86::COND_O;
18048 break;
18049 }
18050 BaseOp = X86ISD::ADD;
18051 Cond = X86::COND_O;
18052 break;
18053 case ISD::UADDO:
18054 BaseOp = X86ISD::ADD;
18055 Cond = X86::COND_B;
18056 break;
18057 case ISD::SSUBO:
18058 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18059 // set CF, so we can't do this for USUBO.
18060 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18061 if (C->isOne()) {
18062 BaseOp = X86ISD::DEC;
18063 Cond = X86::COND_O;
18064 break;
18065 }
18066 BaseOp = X86ISD::SUB;
18067 Cond = X86::COND_O;
18068 break;
18069 case ISD::USUBO:
18070 BaseOp = X86ISD::SUB;
18071 Cond = X86::COND_B;
18072 break;
18073 case ISD::SMULO:
18074 BaseOp = X86ISD::SMUL;
18075 Cond = X86::COND_O;
18076 break;
18077 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18078 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18079 MVT::i32);
18080 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18082 SDValue SetCC =
18083 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18084 DAG.getConstant(X86::COND_O, MVT::i32),
18085 SDValue(Sum.getNode(), 2));
18087 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18088 }
18089 }
18091 // Also sets EFLAGS.
18092 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18093 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18095 SDValue SetCC =
18096 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18097 DAG.getConstant(Cond, MVT::i32),
18098 SDValue(Sum.getNode(), 1));
18100 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18101 }
18103 // Sign extension of the low part of vector elements. This may be used either
18104 // when sign extend instructions are not available or if the vector element
18105 // sizes already match the sign-extended size. If the vector elements are in
18106 // their pre-extended size and sign extend instructions are available, that will
18107 // be handled by LowerSIGN_EXTEND.
18108 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
18109 SelectionDAG &DAG) const {
18110 SDLoc dl(Op);
18111 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
18112 MVT VT = Op.getSimpleValueType();
18114 if (!Subtarget->hasSSE2() || !VT.isVector())
18115 return SDValue();
18117 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
18118 ExtraVT.getScalarType().getSizeInBits();
18120 switch (VT.SimpleTy) {
18121 default: return SDValue();
18122 case MVT::v8i32:
18123 case MVT::v16i16:
18124 if (!Subtarget->hasFp256())
18125 return SDValue();
18126 if (!Subtarget->hasInt256()) {
18127 // needs to be split
18128 unsigned NumElems = VT.getVectorNumElements();
18130 // Extract the LHS vectors
18131 SDValue LHS = Op.getOperand(0);
18132 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18133 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18135 MVT EltVT = VT.getVectorElementType();
18136 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18138 EVT ExtraEltVT = ExtraVT.getVectorElementType();
18139 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
18140 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
18141 ExtraNumElems/2);
18142 SDValue Extra = DAG.getValueType(ExtraVT);
18144 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
18145 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
18147 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
18148 }
18149 // fall through
18150 case MVT::v4i32:
18151 case MVT::v8i16: {
18152 SDValue Op0 = Op.getOperand(0);
18154 // This is a sign extension of some low part of vector elements without
18155 // changing the size of the vector elements themselves:
18156 // Shift-Left + Shift-Right-Algebraic.
18157 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
18158 BitsDiff, DAG);
18159 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
18160 DAG);
18161 }
18162 }
18163 }
18165 /// Returns true if the operand type is exactly twice the native width, and
18166 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18167 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18168 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18169 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
18170 const X86Subtarget &Subtarget =
18171 getTargetMachine().getSubtarget<X86Subtarget>();
18172 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18174 if (OpWidth == 64)
18175 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18176 else if (OpWidth == 128)
18177 return Subtarget.hasCmpxchg16b();
18178 else
18179 return false;
18180 }
18182 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18183 return needsCmpXchgNb(SI->getValueOperand()->getType());
18184 }
18186 // Note: this turns large loads into lock cmpxchg8b/16b.
18187 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18188 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18189 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18190 return needsCmpXchgNb(PTy->getElementType());
18191 }
18193 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18194 const X86Subtarget &Subtarget =
18195 getTargetMachine().getSubtarget<X86Subtarget>();
18196 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18197 const Type *MemType = AI->getType();
18199 // If the operand is too big, we must see if cmpxchg8/16b is available
18200 // and default to library calls otherwise.
18201 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18202 return needsCmpXchgNb(MemType);
18204 AtomicRMWInst::BinOp Op = AI->getOperation();
18205 switch (Op) {
18206 default:
18207 llvm_unreachable("Unknown atomic operation");
18208 case AtomicRMWInst::Xchg:
18209 case AtomicRMWInst::Add:
18210 case AtomicRMWInst::Sub:
18211 // It's better to use xadd, xsub or xchg for these in all cases.
18212 return false;
18213 case AtomicRMWInst::Or:
18214 case AtomicRMWInst::And:
18215 case AtomicRMWInst::Xor:
18216 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18217 // prefix to a normal instruction for these operations.
18218 return !AI->use_empty();
18219 case AtomicRMWInst::Nand:
18220 case AtomicRMWInst::Max:
18221 case AtomicRMWInst::Min:
18222 case AtomicRMWInst::UMax:
18223 case AtomicRMWInst::UMin:
18224 // These always require a non-trivial set of data operations on x86. We must
18225 // use a cmpxchg loop.
18226 return true;
18227 }
18228 }
18230 static bool hasMFENCE(const X86Subtarget& Subtarget) {
18231 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
18232 // no-sse2). There isn't any reason to disable it if the target processor
18233 // supports it.
18234 return Subtarget.hasSSE2() || Subtarget.is64Bit();
18235 }
18237 LoadInst *
18238 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
18239 const X86Subtarget &Subtarget =
18240 getTargetMachine().getSubtarget<X86Subtarget>();
18241 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18242 const Type *MemType = AI->getType();
18243 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
18244 // there is no benefit in turning such RMWs into loads, and it is actually
18245 // harmful as it introduces a mfence.
18246 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18247 return nullptr;
18249 auto Builder = IRBuilder<>(AI);
18250 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
18251 auto SynchScope = AI->getSynchScope();
18252 // We must restrict the ordering to avoid generating loads with Release or
18253 // ReleaseAcquire orderings.
18254 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
18255 auto Ptr = AI->getPointerOperand();
18257 // Before the load we need a fence. Here is an example lifted from
18258 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
18259 // is required:
18260 // Thread 0:
18261 // x.store(1, relaxed);
18262 // r1 = y.fetch_add(0, release);
18263 // Thread 1:
18264 // y.fetch_add(42, acquire);
18265 // r2 = x.load(relaxed);
18266 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
18267 // lowered to just a load without a fence. A mfence flushes the store buffer,
18268 // making the optimization clearly correct.
18269 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
18270 // otherwise, we might be able to be more agressive on relaxed idempotent
18271 // rmw. In practice, they do not look useful, so we don't try to be
18272 // especially clever.
18273 if (SynchScope == SingleThread) {
18274 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
18275 // the IR level, so we must wrap it in an intrinsic.
18276 return nullptr;
18277 } else if (hasMFENCE(Subtarget)) {
18278 Function *MFence = llvm::Intrinsic::getDeclaration(M,
18279 Intrinsic::x86_sse2_mfence);
18280 Builder.CreateCall(MFence);
18281 } else {
18282 // FIXME: it might make sense to use a locked operation here but on a
18283 // different cache-line to prevent cache-line bouncing. In practice it
18284 // is probably a small win, and x86 processors without mfence are rare
18285 // enough that we do not bother.
18286 return nullptr;
18287 }
18289 // Finally we can emit the atomic load.
18290 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
18291 AI->getType()->getPrimitiveSizeInBits());
18292 Loaded->setAtomic(Order, SynchScope);
18293 AI->replaceAllUsesWith(Loaded);
18294 AI->eraseFromParent();
18295 return Loaded;
18296 }
18298 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
18299 SelectionDAG &DAG) {
18300 SDLoc dl(Op);
18301 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
18302 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
18303 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
18304 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
18306 // The only fence that needs an instruction is a sequentially-consistent
18307 // cross-thread fence.
18308 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
18309 if (hasMFENCE(*Subtarget))
18310 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
18312 SDValue Chain = Op.getOperand(0);
18313 SDValue Zero = DAG.getConstant(0, MVT::i32);
18314 SDValue Ops[] = {
18315 DAG.getRegister(X86::ESP, MVT::i32), // Base
18316 DAG.getTargetConstant(1, MVT::i8), // Scale
18317 DAG.getRegister(0, MVT::i32), // Index
18318 DAG.getTargetConstant(0, MVT::i32), // Disp
18319 DAG.getRegister(0, MVT::i32), // Segment.
18320 Zero,
18321 Chain
18322 };
18323 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
18324 return SDValue(Res, 0);
18325 }
18327 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
18328 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
18329 }
18331 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
18332 SelectionDAG &DAG) {
18333 MVT T = Op.getSimpleValueType();
18334 SDLoc DL(Op);
18335 unsigned Reg = 0;
18336 unsigned size = 0;
18337 switch(T.SimpleTy) {
18338 default: llvm_unreachable("Invalid value type!");
18339 case MVT::i8: Reg = X86::AL; size = 1; break;
18340 case MVT::i16: Reg = X86::AX; size = 2; break;
18341 case MVT::i32: Reg = X86::EAX; size = 4; break;
18342 case MVT::i64:
18343 assert(Subtarget->is64Bit() && "Node not type legal!");
18344 Reg = X86::RAX; size = 8;
18345 break;
18346 }
18347 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
18348 Op.getOperand(2), SDValue());
18349 SDValue Ops[] = { cpIn.getValue(0),
18350 Op.getOperand(1),
18351 Op.getOperand(3),
18352 DAG.getTargetConstant(size, MVT::i8),
18353 cpIn.getValue(1) };
18354 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18355 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
18356 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
18357 Ops, T, MMO);
18359 SDValue cpOut =
18360 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
18361 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
18362 MVT::i32, cpOut.getValue(2));
18363 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
18364 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
18366 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
18367 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
18368 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
18369 return SDValue();
18370 }
18372 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
18373 SelectionDAG &DAG) {
18374 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
18375 MVT DstVT = Op.getSimpleValueType();
18377 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
18378 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18379 if (DstVT != MVT::f64)
18380 // This conversion needs to be expanded.
18381 return SDValue();
18383 SDValue InVec = Op->getOperand(0);
18384 SDLoc dl(Op);
18385 unsigned NumElts = SrcVT.getVectorNumElements();
18386 EVT SVT = SrcVT.getVectorElementType();
18388 // Widen the vector in input in the case of MVT::v2i32.
18389 // Example: from MVT::v2i32 to MVT::v4i32.
18390 SmallVector<SDValue, 16> Elts;
18391 for (unsigned i = 0, e = NumElts; i != e; ++i)
18392 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
18393 DAG.getIntPtrConstant(i)));
18395 // Explicitly mark the extra elements as Undef.
18396 SDValue Undef = DAG.getUNDEF(SVT);
18397 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
18398 Elts.push_back(Undef);
18400 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18401 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
18402 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
18403 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
18404 DAG.getIntPtrConstant(0));
18405 }
18407 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
18408 Subtarget->hasMMX() && "Unexpected custom BITCAST");
18409 assert((DstVT == MVT::i64 ||
18410 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
18411 "Unexpected custom BITCAST");
18412 // i64 <=> MMX conversions are Legal.
18413 if (SrcVT==MVT::i64 && DstVT.isVector())
18414 return Op;
18415 if (DstVT==MVT::i64 && SrcVT.isVector())
18416 return Op;
18417 // MMX <=> MMX conversions are Legal.
18418 if (SrcVT.isVector() && DstVT.isVector())
18419 return Op;
18420 // All other conversions need to be expanded.
18421 return SDValue();
18422 }
18424 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
18425 SDNode *Node = Op.getNode();
18426 SDLoc dl(Node);
18427 EVT T = Node->getValueType(0);
18428 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
18429 DAG.getConstant(0, T), Node->getOperand(2));
18430 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
18431 cast<AtomicSDNode>(Node)->getMemoryVT(),
18432 Node->getOperand(0),
18433 Node->getOperand(1), negOp,
18434 cast<AtomicSDNode>(Node)->getMemOperand(),
18435 cast<AtomicSDNode>(Node)->getOrdering(),
18436 cast<AtomicSDNode>(Node)->getSynchScope());
18437 }
18439 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
18440 SDNode *Node = Op.getNode();
18441 SDLoc dl(Node);
18442 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
18444 // Convert seq_cst store -> xchg
18445 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
18446 // FIXME: On 32-bit, store -> fist or movq would be more efficient
18447 // (The only way to get a 16-byte store is cmpxchg16b)
18448 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
18449 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
18450 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
18451 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
18452 cast<AtomicSDNode>(Node)->getMemoryVT(),
18453 Node->getOperand(0),
18454 Node->getOperand(1), Node->getOperand(2),
18455 cast<AtomicSDNode>(Node)->getMemOperand(),
18456 cast<AtomicSDNode>(Node)->getOrdering(),
18457 cast<AtomicSDNode>(Node)->getSynchScope());
18458 return Swap.getValue(1);
18459 }
18460 // Other atomic stores have a simple pattern.
18461 return Op;
18462 }
18464 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
18465 EVT VT = Op.getNode()->getSimpleValueType(0);
18467 // Let legalize expand this if it isn't a legal type yet.
18468 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
18469 return SDValue();
18471 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
18473 unsigned Opc;
18474 bool ExtraOp = false;
18475 switch (Op.getOpcode()) {
18476 default: llvm_unreachable("Invalid code");
18477 case ISD::ADDC: Opc = X86ISD::ADD; break;
18478 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
18479 case ISD::SUBC: Opc = X86ISD::SUB; break;
18480 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
18481 }
18483 if (!ExtraOp)
18484 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18485 Op.getOperand(1));
18486 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18487 Op.getOperand(1), Op.getOperand(2));
18488 }
18490 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
18491 SelectionDAG &DAG) {
18492 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
18494 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
18495 // which returns the values as { float, float } (in XMM0) or
18496 // { double, double } (which is returned in XMM0, XMM1).
18497 SDLoc dl(Op);
18498 SDValue Arg = Op.getOperand(0);
18499 EVT ArgVT = Arg.getValueType();
18500 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18502 TargetLowering::ArgListTy Args;
18503 TargetLowering::ArgListEntry Entry;
18505 Entry.Node = Arg;
18506 Entry.Ty = ArgTy;
18507 Entry.isSExt = false;
18508 Entry.isZExt = false;
18509 Args.push_back(Entry);
18511 bool isF64 = ArgVT == MVT::f64;
18512 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
18513 // the small struct {f32, f32} is returned in (eax, edx). For f64,
18514 // the results are returned via SRet in memory.
18515 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
18516 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18517 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
18519 Type *RetTy = isF64
18520 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
18521 : (Type*)VectorType::get(ArgTy, 4);
18523 TargetLowering::CallLoweringInfo CLI(DAG);
18524 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
18525 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
18527 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
18529 if (isF64)
18530 // Returned in xmm0 and xmm1.
18531 return CallResult.first;
18533 // Returned in bits 0:31 and 32:64 xmm0.
18534 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18535 CallResult.first, DAG.getIntPtrConstant(0));
18536 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18537 CallResult.first, DAG.getIntPtrConstant(1));
18538 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
18539 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
18540 }
18542 /// LowerOperation - Provide custom lowering hooks for some operations.
18543 ///
18544 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
18545 switch (Op.getOpcode()) {
18546 default: llvm_unreachable("Should not custom lower this!");
18547 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
18548 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
18549 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
18550 return LowerCMP_SWAP(Op, Subtarget, DAG);
18551 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
18552 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
18553 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
18554 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
18555 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
18556 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
18557 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
18558 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
18559 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
18560 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
18561 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
18562 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
18563 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
18564 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
18565 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
18566 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
18567 case ISD::SHL_PARTS:
18568 case ISD::SRA_PARTS:
18569 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
18570 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
18571 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
18572 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
18573 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
18574 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
18575 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
18576 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
18577 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
18578 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
18579 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
18580 case ISD::FABS:
18581 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
18582 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
18583 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
18584 case ISD::SETCC: return LowerSETCC(Op, DAG);
18585 case ISD::SELECT: return LowerSELECT(Op, DAG);
18586 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
18587 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
18588 case ISD::VASTART: return LowerVASTART(Op, DAG);
18589 case ISD::VAARG: return LowerVAARG(Op, DAG);
18590 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
18591 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
18592 case ISD::INTRINSIC_VOID:
18593 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
18594 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
18595 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
18596 case ISD::FRAME_TO_ARGS_OFFSET:
18597 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
18598 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
18599 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
18600 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
18601 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
18602 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
18603 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
18604 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
18605 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
18606 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
18607 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
18608 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
18609 case ISD::UMUL_LOHI:
18610 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
18611 case ISD::SRA:
18612 case ISD::SRL:
18613 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
18614 case ISD::SADDO:
18615 case ISD::UADDO:
18616 case ISD::SSUBO:
18617 case ISD::USUBO:
18618 case ISD::SMULO:
18619 case ISD::UMULO: return LowerXALUO(Op, DAG);
18620 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
18621 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
18622 case ISD::ADDC:
18623 case ISD::ADDE:
18624 case ISD::SUBC:
18625 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
18626 case ISD::ADD: return LowerADD(Op, DAG);
18627 case ISD::SUB: return LowerSUB(Op, DAG);
18628 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
18629 }
18630 }
18632 /// ReplaceNodeResults - Replace a node with an illegal result type
18633 /// with a new node built out of custom code.
18634 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
18635 SmallVectorImpl<SDValue>&Results,
18636 SelectionDAG &DAG) const {
18637 SDLoc dl(N);
18638 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18639 switch (N->getOpcode()) {
18640 default:
18641 llvm_unreachable("Do not know how to custom type legalize this operation!");
18642 case ISD::SIGN_EXTEND_INREG:
18643 case ISD::ADDC:
18644 case ISD::ADDE:
18645 case ISD::SUBC:
18646 case ISD::SUBE:
18647 // We don't want to expand or promote these.
18648 return;
18649 case ISD::SDIV:
18650 case ISD::UDIV:
18651 case ISD::SREM:
18652 case ISD::UREM:
18653 case ISD::SDIVREM:
18654 case ISD::UDIVREM: {
18655 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
18656 Results.push_back(V);
18657 return;
18658 }
18659 case ISD::FP_TO_SINT:
18660 case ISD::FP_TO_UINT: {
18661 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
18663 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
18664 return;
18666 std::pair<SDValue,SDValue> Vals =
18667 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
18668 SDValue FIST = Vals.first, StackSlot = Vals.second;
18669 if (FIST.getNode()) {
18670 EVT VT = N->getValueType(0);
18671 // Return a load from the stack slot.
18672 if (StackSlot.getNode())
18673 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
18674 MachinePointerInfo(),
18675 false, false, false, 0));
18676 else
18677 Results.push_back(FIST);
18678 }
18679 return;
18680 }
18681 case ISD::UINT_TO_FP: {
18682 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18683 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
18684 N->getValueType(0) != MVT::v2f32)
18685 return;
18686 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
18687 N->getOperand(0));
18688 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
18689 MVT::f64);
18690 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
18691 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
18692 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
18693 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
18694 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
18695 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
18696 return;
18697 }
18698 case ISD::FP_ROUND: {
18699 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
18700 return;
18701 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
18702 Results.push_back(V);
18703 return;
18704 }
18705 case ISD::INTRINSIC_W_CHAIN: {
18706 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
18707 switch (IntNo) {
18708 default : llvm_unreachable("Do not know how to custom type "
18709 "legalize this intrinsic operation!");
18710 case Intrinsic::x86_rdtsc:
18711 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18712 Results);
18713 case Intrinsic::x86_rdtscp:
18714 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
18715 Results);
18716 case Intrinsic::x86_rdpmc:
18717 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
18718 }
18719 }
18720 case ISD::READCYCLECOUNTER: {
18721 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18722 Results);
18723 }
18724 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
18725 EVT T = N->getValueType(0);
18726 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
18727 bool Regs64bit = T == MVT::i128;
18728 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
18729 SDValue cpInL, cpInH;
18730 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18731 DAG.getConstant(0, HalfT));
18732 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18733 DAG.getConstant(1, HalfT));
18734 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
18735 Regs64bit ? X86::RAX : X86::EAX,
18736 cpInL, SDValue());
18737 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
18738 Regs64bit ? X86::RDX : X86::EDX,
18739 cpInH, cpInL.getValue(1));
18740 SDValue swapInL, swapInH;
18741 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18742 DAG.getConstant(0, HalfT));
18743 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18744 DAG.getConstant(1, HalfT));
18745 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
18746 Regs64bit ? X86::RBX : X86::EBX,
18747 swapInL, cpInH.getValue(1));
18748 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
18749 Regs64bit ? X86::RCX : X86::ECX,
18750 swapInH, swapInL.getValue(1));
18751 SDValue Ops[] = { swapInH.getValue(0),
18752 N->getOperand(1),
18753 swapInH.getValue(1) };
18754 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18755 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
18756 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
18757 X86ISD::LCMPXCHG8_DAG;
18758 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
18759 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
18760 Regs64bit ? X86::RAX : X86::EAX,
18761 HalfT, Result.getValue(1));
18762 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
18763 Regs64bit ? X86::RDX : X86::EDX,
18764 HalfT, cpOutL.getValue(2));
18765 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
18767 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
18768 MVT::i32, cpOutH.getValue(2));
18769 SDValue Success =
18770 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
18771 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
18772 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
18774 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
18775 Results.push_back(Success);
18776 Results.push_back(EFLAGS.getValue(1));
18777 return;
18778 }
18779 case ISD::ATOMIC_SWAP:
18780 case ISD::ATOMIC_LOAD_ADD:
18781 case ISD::ATOMIC_LOAD_SUB:
18782 case ISD::ATOMIC_LOAD_AND:
18783 case ISD::ATOMIC_LOAD_OR:
18784 case ISD::ATOMIC_LOAD_XOR:
18785 case ISD::ATOMIC_LOAD_NAND:
18786 case ISD::ATOMIC_LOAD_MIN:
18787 case ISD::ATOMIC_LOAD_MAX:
18788 case ISD::ATOMIC_LOAD_UMIN:
18789 case ISD::ATOMIC_LOAD_UMAX:
18790 case ISD::ATOMIC_LOAD: {
18791 // Delegate to generic TypeLegalization. Situations we can really handle
18792 // should have already been dealt with by AtomicExpandPass.cpp.
18793 break;
18794 }
18795 case ISD::BITCAST: {
18796 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18797 EVT DstVT = N->getValueType(0);
18798 EVT SrcVT = N->getOperand(0)->getValueType(0);
18800 if (SrcVT != MVT::f64 ||
18801 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
18802 return;
18804 unsigned NumElts = DstVT.getVectorNumElements();
18805 EVT SVT = DstVT.getVectorElementType();
18806 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18807 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
18808 MVT::v2f64, N->getOperand(0));
18809 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
18811 if (ExperimentalVectorWideningLegalization) {
18812 // If we are legalizing vectors by widening, we already have the desired
18813 // legal vector type, just return it.
18814 Results.push_back(ToVecInt);
18815 return;
18816 }
18818 SmallVector<SDValue, 8> Elts;
18819 for (unsigned i = 0, e = NumElts; i != e; ++i)
18820 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
18821 ToVecInt, DAG.getIntPtrConstant(i)));
18823 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
18824 }
18825 }
18826 }
18828 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
18829 switch (Opcode) {
18830 default: return nullptr;
18831 case X86ISD::BSF: return "X86ISD::BSF";
18832 case X86ISD::BSR: return "X86ISD::BSR";
18833 case X86ISD::SHLD: return "X86ISD::SHLD";
18834 case X86ISD::SHRD: return "X86ISD::SHRD";
18835 case X86ISD::FAND: return "X86ISD::FAND";
18836 case X86ISD::FANDN: return "X86ISD::FANDN";
18837 case X86ISD::FOR: return "X86ISD::FOR";
18838 case X86ISD::FXOR: return "X86ISD::FXOR";
18839 case X86ISD::FSRL: return "X86ISD::FSRL";
18840 case X86ISD::FILD: return "X86ISD::FILD";
18841 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
18842 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
18843 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
18844 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
18845 case X86ISD::FLD: return "X86ISD::FLD";
18846 case X86ISD::FST: return "X86ISD::FST";
18847 case X86ISD::CALL: return "X86ISD::CALL";
18848 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
18849 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
18850 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
18851 case X86ISD::BT: return "X86ISD::BT";
18852 case X86ISD::CMP: return "X86ISD::CMP";
18853 case X86ISD::COMI: return "X86ISD::COMI";
18854 case X86ISD::UCOMI: return "X86ISD::UCOMI";
18855 case X86ISD::CMPM: return "X86ISD::CMPM";
18856 case X86ISD::CMPMU: return "X86ISD::CMPMU";
18857 case X86ISD::SETCC: return "X86ISD::SETCC";
18858 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
18859 case X86ISD::FSETCC: return "X86ISD::FSETCC";
18860 case X86ISD::CMOV: return "X86ISD::CMOV";
18861 case X86ISD::BRCOND: return "X86ISD::BRCOND";
18862 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
18863 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
18864 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
18865 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
18866 case X86ISD::Wrapper: return "X86ISD::Wrapper";
18867 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
18868 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
18869 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
18870 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
18871 case X86ISD::PINSRB: return "X86ISD::PINSRB";
18872 case X86ISD::PINSRW: return "X86ISD::PINSRW";
18873 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
18874 case X86ISD::ANDNP: return "X86ISD::ANDNP";
18875 case X86ISD::PSIGN: return "X86ISD::PSIGN";
18876 case X86ISD::BLENDI: return "X86ISD::BLENDI";
18877 case X86ISD::SUBUS: return "X86ISD::SUBUS";
18878 case X86ISD::HADD: return "X86ISD::HADD";
18879 case X86ISD::HSUB: return "X86ISD::HSUB";
18880 case X86ISD::FHADD: return "X86ISD::FHADD";
18881 case X86ISD::FHSUB: return "X86ISD::FHSUB";
18882 case X86ISD::UMAX: return "X86ISD::UMAX";
18883 case X86ISD::UMIN: return "X86ISD::UMIN";
18884 case X86ISD::SMAX: return "X86ISD::SMAX";
18885 case X86ISD::SMIN: return "X86ISD::SMIN";
18886 case X86ISD::FMAX: return "X86ISD::FMAX";
18887 case X86ISD::FMIN: return "X86ISD::FMIN";
18888 case X86ISD::FMAXC: return "X86ISD::FMAXC";
18889 case X86ISD::FMINC: return "X86ISD::FMINC";
18890 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
18891 case X86ISD::FRCP: return "X86ISD::FRCP";
18892 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
18893 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
18894 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
18895 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
18896 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
18897 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
18898 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
18899 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
18900 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
18901 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
18902 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
18903 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
18904 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
18905 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
18906 case X86ISD::VZEXT: return "X86ISD::VZEXT";
18907 case X86ISD::VSEXT: return "X86ISD::VSEXT";
18908 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
18909 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
18910 case X86ISD::VINSERT: return "X86ISD::VINSERT";
18911 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
18912 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
18913 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
18914 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
18915 case X86ISD::VSHL: return "X86ISD::VSHL";
18916 case X86ISD::VSRL: return "X86ISD::VSRL";
18917 case X86ISD::VSRA: return "X86ISD::VSRA";
18918 case X86ISD::VSHLI: return "X86ISD::VSHLI";
18919 case X86ISD::VSRLI: return "X86ISD::VSRLI";
18920 case X86ISD::VSRAI: return "X86ISD::VSRAI";
18921 case X86ISD::CMPP: return "X86ISD::CMPP";
18922 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
18923 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
18924 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
18925 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
18926 case X86ISD::ADD: return "X86ISD::ADD";
18927 case X86ISD::SUB: return "X86ISD::SUB";
18928 case X86ISD::ADC: return "X86ISD::ADC";
18929 case X86ISD::SBB: return "X86ISD::SBB";
18930 case X86ISD::SMUL: return "X86ISD::SMUL";
18931 case X86ISD::UMUL: return "X86ISD::UMUL";
18932 case X86ISD::INC: return "X86ISD::INC";
18933 case X86ISD::DEC: return "X86ISD::DEC";
18934 case X86ISD::OR: return "X86ISD::OR";
18935 case X86ISD::XOR: return "X86ISD::XOR";
18936 case X86ISD::AND: return "X86ISD::AND";
18937 case X86ISD::BEXTR: return "X86ISD::BEXTR";
18938 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
18939 case X86ISD::PTEST: return "X86ISD::PTEST";
18940 case X86ISD::TESTP: return "X86ISD::TESTP";
18941 case X86ISD::TESTM: return "X86ISD::TESTM";
18942 case X86ISD::TESTNM: return "X86ISD::TESTNM";
18943 case X86ISD::KORTEST: return "X86ISD::KORTEST";
18944 case X86ISD::PACKSS: return "X86ISD::PACKSS";
18945 case X86ISD::PACKUS: return "X86ISD::PACKUS";
18946 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
18947 case X86ISD::VALIGN: return "X86ISD::VALIGN";
18948 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
18949 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
18950 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
18951 case X86ISD::SHUFP: return "X86ISD::SHUFP";
18952 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
18953 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
18954 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
18955 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
18956 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
18957 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
18958 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
18959 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
18960 case X86ISD::MOVSD: return "X86ISD::MOVSD";
18961 case X86ISD::MOVSS: return "X86ISD::MOVSS";
18962 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
18963 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
18964 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
18965 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
18966 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
18967 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
18968 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
18969 case X86ISD::VPERMV: return "X86ISD::VPERMV";
18970 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
18971 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
18972 case X86ISD::VPERMI: return "X86ISD::VPERMI";
18973 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
18974 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
18975 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
18976 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
18977 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
18978 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
18979 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
18980 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
18981 case X86ISD::SAHF: return "X86ISD::SAHF";
18982 case X86ISD::RDRAND: return "X86ISD::RDRAND";
18983 case X86ISD::RDSEED: return "X86ISD::RDSEED";
18984 case X86ISD::FMADD: return "X86ISD::FMADD";
18985 case X86ISD::FMSUB: return "X86ISD::FMSUB";
18986 case X86ISD::FNMADD: return "X86ISD::FNMADD";
18987 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
18988 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
18989 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
18990 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
18991 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
18992 case X86ISD::XTEST: return "X86ISD::XTEST";
18993 }
18994 }
18996 // isLegalAddressingMode - Return true if the addressing mode represented
18997 // by AM is legal for this target, for a load/store of the specified type.
18998 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
18999 Type *Ty) const {
19000 // X86 supports extremely general addressing modes.
19001 CodeModel::Model M = getTargetMachine().getCodeModel();
19002 Reloc::Model R = getTargetMachine().getRelocationModel();
19004 // X86 allows a sign-extended 32-bit immediate field as a displacement.
19005 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
19006 return false;
19008 if (AM.BaseGV) {
19009 unsigned GVFlags =
19010 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
19012 // If a reference to this global requires an extra load, we can't fold it.
19013 if (isGlobalStubReference(GVFlags))
19014 return false;
19016 // If BaseGV requires a register for the PIC base, we cannot also have a
19017 // BaseReg specified.
19018 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
19019 return false;
19021 // If lower 4G is not available, then we must use rip-relative addressing.
19022 if ((M != CodeModel::Small || R != Reloc::Static) &&
19023 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
19024 return false;
19025 }
19027 switch (AM.Scale) {
19028 case 0:
19029 case 1:
19030 case 2:
19031 case 4:
19032 case 8:
19033 // These scales always work.
19034 break;
19035 case 3:
19036 case 5:
19037 case 9:
19038 // These scales are formed with basereg+scalereg. Only accept if there is
19039 // no basereg yet.
19040 if (AM.HasBaseReg)
19041 return false;
19042 break;
19043 default: // Other stuff never works.
19044 return false;
19045 }
19047 return true;
19048 }
19050 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
19051 unsigned Bits = Ty->getScalarSizeInBits();
19053 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
19054 // particularly cheaper than those without.
19055 if (Bits == 8)
19056 return false;
19058 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
19059 // variable shifts just as cheap as scalar ones.
19060 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
19061 return false;
19063 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
19064 // fully general vector.
19065 return true;
19066 }
19068 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
19069 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19070 return false;
19071 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
19072 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
19073 return NumBits1 > NumBits2;
19074 }
19076 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
19077 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19078 return false;
19080 if (!isTypeLegal(EVT::getEVT(Ty1)))
19081 return false;
19083 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
19085 // Assuming the caller doesn't have a zeroext or signext return parameter,
19086 // truncation all the way down to i1 is valid.
19087 return true;
19088 }
19090 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
19091 return isInt<32>(Imm);
19092 }
19094 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
19095 // Can also use sub to handle negated immediates.
19096 return isInt<32>(Imm);
19097 }
19099 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
19100 if (!VT1.isInteger() || !VT2.isInteger())
19101 return false;
19102 unsigned NumBits1 = VT1.getSizeInBits();
19103 unsigned NumBits2 = VT2.getSizeInBits();
19104 return NumBits1 > NumBits2;
19105 }
19107 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
19108 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19109 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
19110 }
19112 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
19113 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19114 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
19115 }
19117 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
19118 EVT VT1 = Val.getValueType();
19119 if (isZExtFree(VT1, VT2))
19120 return true;
19122 if (Val.getOpcode() != ISD::LOAD)
19123 return false;
19125 if (!VT1.isSimple() || !VT1.isInteger() ||
19126 !VT2.isSimple() || !VT2.isInteger())
19127 return false;
19129 switch (VT1.getSimpleVT().SimpleTy) {
19130 default: break;
19131 case MVT::i8:
19132 case MVT::i16:
19133 case MVT::i32:
19134 // X86 has 8, 16, and 32-bit zero-extending loads.
19135 return true;
19136 }
19138 return false;
19139 }
19141 bool
19142 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
19143 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
19144 return false;
19146 VT = VT.getScalarType();
19148 if (!VT.isSimple())
19149 return false;
19151 switch (VT.getSimpleVT().SimpleTy) {
19152 case MVT::f32:
19153 case MVT::f64:
19154 return true;
19155 default:
19156 break;
19157 }
19159 return false;
19160 }
19162 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
19163 // i16 instructions are longer (0x66 prefix) and potentially slower.
19164 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
19165 }
19167 /// isShuffleMaskLegal - Targets can use this to indicate that they only
19168 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
19169 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
19170 /// are assumed to be legal.
19171 bool
19172 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
19173 EVT VT) const {
19174 if (!VT.isSimple())
19175 return false;
19177 MVT SVT = VT.getSimpleVT();
19179 // Very little shuffling can be done for 64-bit vectors right now.
19180 if (VT.getSizeInBits() == 64)
19181 return false;
19183 // If this is a single-input shuffle with no 128 bit lane crossings we can
19184 // lower it into pshufb.
19185 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
19186 (SVT.is256BitVector() && Subtarget->hasInt256())) {
19187 bool isLegal = true;
19188 for (unsigned I = 0, E = M.size(); I != E; ++I) {
19189 if (M[I] >= (int)SVT.getVectorNumElements() ||
19190 ShuffleCrosses128bitLane(SVT, I, M[I])) {
19191 isLegal = false;
19192 break;
19193 }
19194 }
19195 if (isLegal)
19196 return true;
19197 }
19199 // FIXME: blends, shifts.
19200 return (SVT.getVectorNumElements() == 2 ||
19201 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
19202 isMOVLMask(M, SVT) ||
19203 isMOVHLPSMask(M, SVT) ||
19204 isSHUFPMask(M, SVT) ||
19205 isPSHUFDMask(M, SVT) ||
19206 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
19207 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
19208 isPALIGNRMask(M, SVT, Subtarget) ||
19209 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
19210 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
19211 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19212 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19213 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()));
19214 }
19216 bool
19217 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
19218 EVT VT) const {
19219 if (!VT.isSimple())
19220 return false;
19222 MVT SVT = VT.getSimpleVT();
19223 unsigned NumElts = SVT.getVectorNumElements();
19224 // FIXME: This collection of masks seems suspect.
19225 if (NumElts == 2)
19226 return true;
19227 if (NumElts == 4 && SVT.is128BitVector()) {
19228 return (isMOVLMask(Mask, SVT) ||
19229 isCommutedMOVLMask(Mask, SVT, true) ||
19230 isSHUFPMask(Mask, SVT) ||
19231 isSHUFPMask(Mask, SVT, /* Commuted */ true));
19232 }
19233 return false;
19234 }
19236 //===----------------------------------------------------------------------===//
19237 // X86 Scheduler Hooks
19238 //===----------------------------------------------------------------------===//
19240 /// Utility function to emit xbegin specifying the start of an RTM region.
19241 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
19242 const TargetInstrInfo *TII) {
19243 DebugLoc DL = MI->getDebugLoc();
19245 const BasicBlock *BB = MBB->getBasicBlock();
19246 MachineFunction::iterator I = MBB;
19247 ++I;
19249 // For the v = xbegin(), we generate
19250 //
19251 // thisMBB:
19252 // xbegin sinkMBB
19253 //
19254 // mainMBB:
19255 // eax = -1
19256 //
19257 // sinkMBB:
19258 // v = eax
19260 MachineBasicBlock *thisMBB = MBB;
19261 MachineFunction *MF = MBB->getParent();
19262 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19263 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19264 MF->insert(I, mainMBB);
19265 MF->insert(I, sinkMBB);
19267 // Transfer the remainder of BB and its successor edges to sinkMBB.
19268 sinkMBB->splice(sinkMBB->begin(), MBB,
19269 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19270 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19272 // thisMBB:
19273 // xbegin sinkMBB
19274 // # fallthrough to mainMBB
19275 // # abortion to sinkMBB
19276 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
19277 thisMBB->addSuccessor(mainMBB);
19278 thisMBB->addSuccessor(sinkMBB);
19280 // mainMBB:
19281 // EAX = -1
19282 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
19283 mainMBB->addSuccessor(sinkMBB);
19285 // sinkMBB:
19286 // EAX is live into the sinkMBB
19287 sinkMBB->addLiveIn(X86::EAX);
19288 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19289 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19290 .addReg(X86::EAX);
19292 MI->eraseFromParent();
19293 return sinkMBB;
19294 }
19296 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
19297 // or XMM0_V32I8 in AVX all of this code can be replaced with that
19298 // in the .td file.
19299 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
19300 const TargetInstrInfo *TII) {
19301 unsigned Opc;
19302 switch (MI->getOpcode()) {
19303 default: llvm_unreachable("illegal opcode!");
19304 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
19305 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
19306 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
19307 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
19308 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
19309 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
19310 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
19311 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
19312 }
19314 DebugLoc dl = MI->getDebugLoc();
19315 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19317 unsigned NumArgs = MI->getNumOperands();
19318 for (unsigned i = 1; i < NumArgs; ++i) {
19319 MachineOperand &Op = MI->getOperand(i);
19320 if (!(Op.isReg() && Op.isImplicit()))
19321 MIB.addOperand(Op);
19322 }
19323 if (MI->hasOneMemOperand())
19324 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19326 BuildMI(*BB, MI, dl,
19327 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19328 .addReg(X86::XMM0);
19330 MI->eraseFromParent();
19331 return BB;
19332 }
19334 // FIXME: Custom handling because TableGen doesn't support multiple implicit
19335 // defs in an instruction pattern
19336 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
19337 const TargetInstrInfo *TII) {
19338 unsigned Opc;
19339 switch (MI->getOpcode()) {
19340 default: llvm_unreachable("illegal opcode!");
19341 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
19342 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
19343 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
19344 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
19345 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
19346 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
19347 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
19348 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
19349 }
19351 DebugLoc dl = MI->getDebugLoc();
19352 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19354 unsigned NumArgs = MI->getNumOperands(); // remove the results
19355 for (unsigned i = 1; i < NumArgs; ++i) {
19356 MachineOperand &Op = MI->getOperand(i);
19357 if (!(Op.isReg() && Op.isImplicit()))
19358 MIB.addOperand(Op);
19359 }
19360 if (MI->hasOneMemOperand())
19361 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19363 BuildMI(*BB, MI, dl,
19364 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19365 .addReg(X86::ECX);
19367 MI->eraseFromParent();
19368 return BB;
19369 }
19371 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
19372 const TargetInstrInfo *TII,
19373 const X86Subtarget* Subtarget) {
19374 DebugLoc dl = MI->getDebugLoc();
19376 // Address into RAX/EAX, other two args into ECX, EDX.
19377 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
19378 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
19379 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
19380 for (int i = 0; i < X86::AddrNumOperands; ++i)
19381 MIB.addOperand(MI->getOperand(i));
19383 unsigned ValOps = X86::AddrNumOperands;
19384 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
19385 .addReg(MI->getOperand(ValOps).getReg());
19386 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
19387 .addReg(MI->getOperand(ValOps+1).getReg());
19389 // The instruction doesn't actually take any operands though.
19390 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
19392 MI->eraseFromParent(); // The pseudo is gone now.
19393 return BB;
19394 }
19396 MachineBasicBlock *
19397 X86TargetLowering::EmitVAARG64WithCustomInserter(
19398 MachineInstr *MI,
19399 MachineBasicBlock *MBB) const {
19400 // Emit va_arg instruction on X86-64.
19402 // Operands to this pseudo-instruction:
19403 // 0 ) Output : destination address (reg)
19404 // 1-5) Input : va_list address (addr, i64mem)
19405 // 6 ) ArgSize : Size (in bytes) of vararg type
19406 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
19407 // 8 ) Align : Alignment of type
19408 // 9 ) EFLAGS (implicit-def)
19410 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
19411 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
19413 unsigned DestReg = MI->getOperand(0).getReg();
19414 MachineOperand &Base = MI->getOperand(1);
19415 MachineOperand &Scale = MI->getOperand(2);
19416 MachineOperand &Index = MI->getOperand(3);
19417 MachineOperand &Disp = MI->getOperand(4);
19418 MachineOperand &Segment = MI->getOperand(5);
19419 unsigned ArgSize = MI->getOperand(6).getImm();
19420 unsigned ArgMode = MI->getOperand(7).getImm();
19421 unsigned Align = MI->getOperand(8).getImm();
19423 // Memory Reference
19424 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
19425 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19426 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19428 // Machine Information
19429 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
19430 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
19431 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
19432 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
19433 DebugLoc DL = MI->getDebugLoc();
19435 // struct va_list {
19436 // i32 gp_offset
19437 // i32 fp_offset
19438 // i64 overflow_area (address)
19439 // i64 reg_save_area (address)
19440 // }
19441 // sizeof(va_list) = 24
19442 // alignment(va_list) = 8
19444 unsigned TotalNumIntRegs = 6;
19445 unsigned TotalNumXMMRegs = 8;
19446 bool UseGPOffset = (ArgMode == 1);
19447 bool UseFPOffset = (ArgMode == 2);
19448 unsigned MaxOffset = TotalNumIntRegs * 8 +
19449 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
19451 /* Align ArgSize to a multiple of 8 */
19452 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
19453 bool NeedsAlign = (Align > 8);
19455 MachineBasicBlock *thisMBB = MBB;
19456 MachineBasicBlock *overflowMBB;
19457 MachineBasicBlock *offsetMBB;
19458 MachineBasicBlock *endMBB;
19460 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
19461 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
19462 unsigned OffsetReg = 0;
19464 if (!UseGPOffset && !UseFPOffset) {
19465 // If we only pull from the overflow region, we don't create a branch.
19466 // We don't need to alter control flow.
19467 OffsetDestReg = 0; // unused
19468 OverflowDestReg = DestReg;
19470 offsetMBB = nullptr;
19471 overflowMBB = thisMBB;
19472 endMBB = thisMBB;
19473 } else {
19474 // First emit code to check if gp_offset (or fp_offset) is below the bound.
19475 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
19476 // If not, pull from overflow_area. (branch to overflowMBB)
19477 //
19478 // thisMBB
19479 // | .
19480 // | .
19481 // offsetMBB overflowMBB
19482 // | .
19483 // | .
19484 // endMBB
19486 // Registers for the PHI in endMBB
19487 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
19488 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
19490 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19491 MachineFunction *MF = MBB->getParent();
19492 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19493 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19494 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19496 MachineFunction::iterator MBBIter = MBB;
19497 ++MBBIter;
19499 // Insert the new basic blocks
19500 MF->insert(MBBIter, offsetMBB);
19501 MF->insert(MBBIter, overflowMBB);
19502 MF->insert(MBBIter, endMBB);
19504 // Transfer the remainder of MBB and its successor edges to endMBB.
19505 endMBB->splice(endMBB->begin(), thisMBB,
19506 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
19507 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
19509 // Make offsetMBB and overflowMBB successors of thisMBB
19510 thisMBB->addSuccessor(offsetMBB);
19511 thisMBB->addSuccessor(overflowMBB);
19513 // endMBB is a successor of both offsetMBB and overflowMBB
19514 offsetMBB->addSuccessor(endMBB);
19515 overflowMBB->addSuccessor(endMBB);
19517 // Load the offset value into a register
19518 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19519 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
19520 .addOperand(Base)
19521 .addOperand(Scale)
19522 .addOperand(Index)
19523 .addDisp(Disp, UseFPOffset ? 4 : 0)
19524 .addOperand(Segment)
19525 .setMemRefs(MMOBegin, MMOEnd);
19527 // Check if there is enough room left to pull this argument.
19528 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
19529 .addReg(OffsetReg)
19530 .addImm(MaxOffset + 8 - ArgSizeA8);
19532 // Branch to "overflowMBB" if offset >= max
19533 // Fall through to "offsetMBB" otherwise
19534 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
19535 .addMBB(overflowMBB);
19536 }
19538 // In offsetMBB, emit code to use the reg_save_area.
19539 if (offsetMBB) {
19540 assert(OffsetReg != 0);
19542 // Read the reg_save_area address.
19543 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
19544 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
19545 .addOperand(Base)
19546 .addOperand(Scale)
19547 .addOperand(Index)
19548 .addDisp(Disp, 16)
19549 .addOperand(Segment)
19550 .setMemRefs(MMOBegin, MMOEnd);
19552 // Zero-extend the offset
19553 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
19554 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
19555 .addImm(0)
19556 .addReg(OffsetReg)
19557 .addImm(X86::sub_32bit);
19559 // Add the offset to the reg_save_area to get the final address.
19560 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
19561 .addReg(OffsetReg64)
19562 .addReg(RegSaveReg);
19564 // Compute the offset for the next argument
19565 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19566 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
19567 .addReg(OffsetReg)
19568 .addImm(UseFPOffset ? 16 : 8);
19570 // Store it back into the va_list.
19571 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
19572 .addOperand(Base)
19573 .addOperand(Scale)
19574 .addOperand(Index)
19575 .addDisp(Disp, UseFPOffset ? 4 : 0)
19576 .addOperand(Segment)
19577 .addReg(NextOffsetReg)
19578 .setMemRefs(MMOBegin, MMOEnd);
19580 // Jump to endMBB
19581 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
19582 .addMBB(endMBB);
19583 }
19585 //
19586 // Emit code to use overflow area
19587 //
19589 // Load the overflow_area address into a register.
19590 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
19591 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
19592 .addOperand(Base)
19593 .addOperand(Scale)
19594 .addOperand(Index)
19595 .addDisp(Disp, 8)
19596 .addOperand(Segment)
19597 .setMemRefs(MMOBegin, MMOEnd);
19599 // If we need to align it, do so. Otherwise, just copy the address
19600 // to OverflowDestReg.
19601 if (NeedsAlign) {
19602 // Align the overflow address
19603 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
19604 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
19606 // aligned_addr = (addr + (align-1)) & ~(align-1)
19607 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
19608 .addReg(OverflowAddrReg)
19609 .addImm(Align-1);
19611 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
19612 .addReg(TmpReg)
19613 .addImm(~(uint64_t)(Align-1));
19614 } else {
19615 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
19616 .addReg(OverflowAddrReg);
19617 }
19619 // Compute the next overflow address after this argument.
19620 // (the overflow address should be kept 8-byte aligned)
19621 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
19622 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
19623 .addReg(OverflowDestReg)
19624 .addImm(ArgSizeA8);
19626 // Store the new overflow address.
19627 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
19628 .addOperand(Base)
19629 .addOperand(Scale)
19630 .addOperand(Index)
19631 .addDisp(Disp, 8)
19632 .addOperand(Segment)
19633 .addReg(NextAddrReg)
19634 .setMemRefs(MMOBegin, MMOEnd);
19636 // If we branched, emit the PHI to the front of endMBB.
19637 if (offsetMBB) {
19638 BuildMI(*endMBB, endMBB->begin(), DL,
19639 TII->get(X86::PHI), DestReg)
19640 .addReg(OffsetDestReg).addMBB(offsetMBB)
19641 .addReg(OverflowDestReg).addMBB(overflowMBB);
19642 }
19644 // Erase the pseudo instruction
19645 MI->eraseFromParent();
19647 return endMBB;
19648 }
19650 MachineBasicBlock *
19651 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
19652 MachineInstr *MI,
19653 MachineBasicBlock *MBB) const {
19654 // Emit code to save XMM registers to the stack. The ABI says that the
19655 // number of registers to save is given in %al, so it's theoretically
19656 // possible to do an indirect jump trick to avoid saving all of them,
19657 // however this code takes a simpler approach and just executes all
19658 // of the stores if %al is non-zero. It's less code, and it's probably
19659 // easier on the hardware branch predictor, and stores aren't all that
19660 // expensive anyway.
19662 // Create the new basic blocks. One block contains all the XMM stores,
19663 // and one block is the final destination regardless of whether any
19664 // stores were performed.
19665 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19666 MachineFunction *F = MBB->getParent();
19667 MachineFunction::iterator MBBIter = MBB;
19668 ++MBBIter;
19669 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
19670 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
19671 F->insert(MBBIter, XMMSaveMBB);
19672 F->insert(MBBIter, EndMBB);
19674 // Transfer the remainder of MBB and its successor edges to EndMBB.
19675 EndMBB->splice(EndMBB->begin(), MBB,
19676 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19677 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
19679 // The original block will now fall through to the XMM save block.
19680 MBB->addSuccessor(XMMSaveMBB);
19681 // The XMMSaveMBB will fall through to the end block.
19682 XMMSaveMBB->addSuccessor(EndMBB);
19684 // Now add the instructions.
19685 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
19686 DebugLoc DL = MI->getDebugLoc();
19688 unsigned CountReg = MI->getOperand(0).getReg();
19689 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
19690 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
19692 if (!Subtarget->isTargetWin64()) {
19693 // If %al is 0, branch around the XMM save block.
19694 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
19695 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
19696 MBB->addSuccessor(EndMBB);
19697 }
19699 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
19700 // that was just emitted, but clearly shouldn't be "saved".
19701 assert((MI->getNumOperands() <= 3 ||
19702 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
19703 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
19704 && "Expected last argument to be EFLAGS");
19705 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
19706 // In the XMM save block, save all the XMM argument registers.
19707 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
19708 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
19709 MachineMemOperand *MMO =
19710 F->getMachineMemOperand(
19711 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
19712 MachineMemOperand::MOStore,
19713 /*Size=*/16, /*Align=*/16);
19714 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
19715 .addFrameIndex(RegSaveFrameIndex)
19716 .addImm(/*Scale=*/1)
19717 .addReg(/*IndexReg=*/0)
19718 .addImm(/*Disp=*/Offset)
19719 .addReg(/*Segment=*/0)
19720 .addReg(MI->getOperand(i).getReg())
19721 .addMemOperand(MMO);
19722 }
19724 MI->eraseFromParent(); // The pseudo instruction is gone now.
19726 return EndMBB;
19727 }
19729 // The EFLAGS operand of SelectItr might be missing a kill marker
19730 // because there were multiple uses of EFLAGS, and ISel didn't know
19731 // which to mark. Figure out whether SelectItr should have had a
19732 // kill marker, and set it if it should. Returns the correct kill
19733 // marker value.
19734 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
19735 MachineBasicBlock* BB,
19736 const TargetRegisterInfo* TRI) {
19737 // Scan forward through BB for a use/def of EFLAGS.
19738 MachineBasicBlock::iterator miI(std::next(SelectItr));
19739 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
19740 const MachineInstr& mi = *miI;
19741 if (mi.readsRegister(X86::EFLAGS))
19742 return false;
19743 if (mi.definesRegister(X86::EFLAGS))
19744 break; // Should have kill-flag - update below.
19745 }
19747 // If we hit the end of the block, check whether EFLAGS is live into a
19748 // successor.
19749 if (miI == BB->end()) {
19750 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
19751 sEnd = BB->succ_end();
19752 sItr != sEnd; ++sItr) {
19753 MachineBasicBlock* succ = *sItr;
19754 if (succ->isLiveIn(X86::EFLAGS))
19755 return false;
19756 }
19757 }
19759 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
19760 // out. SelectMI should have a kill flag on EFLAGS.
19761 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
19762 return true;
19763 }
19765 MachineBasicBlock *
19766 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
19767 MachineBasicBlock *BB) const {
19768 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
19769 DebugLoc DL = MI->getDebugLoc();
19771 // To "insert" a SELECT_CC instruction, we actually have to insert the
19772 // diamond control-flow pattern. The incoming instruction knows the
19773 // destination vreg to set, the condition code register to branch on, the
19774 // true/false values to select between, and a branch opcode to use.
19775 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19776 MachineFunction::iterator It = BB;
19777 ++It;
19779 // thisMBB:
19780 // ...
19781 // TrueVal = ...
19782 // cmpTY ccX, r1, r2
19783 // bCC copy1MBB
19784 // fallthrough --> copy0MBB
19785 MachineBasicBlock *thisMBB = BB;
19786 MachineFunction *F = BB->getParent();
19787 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
19788 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
19789 F->insert(It, copy0MBB);
19790 F->insert(It, sinkMBB);
19792 // If the EFLAGS register isn't dead in the terminator, then claim that it's
19793 // live into the sink and copy blocks.
19794 const TargetRegisterInfo *TRI =
19795 BB->getParent()->getSubtarget().getRegisterInfo();
19796 if (!MI->killsRegister(X86::EFLAGS) &&
19797 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
19798 copy0MBB->addLiveIn(X86::EFLAGS);
19799 sinkMBB->addLiveIn(X86::EFLAGS);
19800 }
19802 // Transfer the remainder of BB and its successor edges to sinkMBB.
19803 sinkMBB->splice(sinkMBB->begin(), BB,
19804 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19805 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
19807 // Add the true and fallthrough blocks as its successors.
19808 BB->addSuccessor(copy0MBB);
19809 BB->addSuccessor(sinkMBB);
19811 // Create the conditional branch instruction.
19812 unsigned Opc =
19813 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
19814 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
19816 // copy0MBB:
19817 // %FalseValue = ...
19818 // # fallthrough to sinkMBB
19819 copy0MBB->addSuccessor(sinkMBB);
19821 // sinkMBB:
19822 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
19823 // ...
19824 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19825 TII->get(X86::PHI), MI->getOperand(0).getReg())
19826 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
19827 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
19829 MI->eraseFromParent(); // The pseudo instruction is gone now.
19830 return sinkMBB;
19831 }
19833 MachineBasicBlock *
19834 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
19835 MachineBasicBlock *BB) const {
19836 MachineFunction *MF = BB->getParent();
19837 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19838 DebugLoc DL = MI->getDebugLoc();
19839 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19841 assert(MF->shouldSplitStack());
19843 const bool Is64Bit = Subtarget->is64Bit();
19844 const bool IsLP64 = Subtarget->isTarget64BitLP64();
19846 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
19847 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
19849 // BB:
19850 // ... [Till the alloca]
19851 // If stacklet is not large enough, jump to mallocMBB
19852 //
19853 // bumpMBB:
19854 // Allocate by subtracting from RSP
19855 // Jump to continueMBB
19856 //
19857 // mallocMBB:
19858 // Allocate by call to runtime
19859 //
19860 // continueMBB:
19861 // ...
19862 // [rest of original BB]
19863 //
19865 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19866 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19867 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19869 MachineRegisterInfo &MRI = MF->getRegInfo();
19870 const TargetRegisterClass *AddrRegClass =
19871 getRegClassFor(getPointerTy());
19873 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19874 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19875 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
19876 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
19877 sizeVReg = MI->getOperand(1).getReg(),
19878 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
19880 MachineFunction::iterator MBBIter = BB;
19881 ++MBBIter;
19883 MF->insert(MBBIter, bumpMBB);
19884 MF->insert(MBBIter, mallocMBB);
19885 MF->insert(MBBIter, continueMBB);
19887 continueMBB->splice(continueMBB->begin(), BB,
19888 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19889 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
19891 // Add code to the main basic block to check if the stack limit has been hit,
19892 // and if so, jump to mallocMBB otherwise to bumpMBB.
19893 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
19894 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
19895 .addReg(tmpSPVReg).addReg(sizeVReg);
19896 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
19897 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
19898 .addReg(SPLimitVReg);
19899 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
19901 // bumpMBB simply decreases the stack pointer, since we know the current
19902 // stacklet has enough space.
19903 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
19904 .addReg(SPLimitVReg);
19905 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
19906 .addReg(SPLimitVReg);
19907 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
19909 // Calls into a routine in libgcc to allocate more space from the heap.
19910 const uint32_t *RegMask = MF->getTarget()
19911 .getSubtargetImpl()
19912 ->getRegisterInfo()
19913 ->getCallPreservedMask(CallingConv::C);
19914 if (IsLP64) {
19915 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
19916 .addReg(sizeVReg);
19917 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19918 .addExternalSymbol("__morestack_allocate_stack_space")
19919 .addRegMask(RegMask)
19920 .addReg(X86::RDI, RegState::Implicit)
19921 .addReg(X86::RAX, RegState::ImplicitDefine);
19922 } else if (Is64Bit) {
19923 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
19924 .addReg(sizeVReg);
19925 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19926 .addExternalSymbol("__morestack_allocate_stack_space")
19927 .addRegMask(RegMask)
19928 .addReg(X86::EDI, RegState::Implicit)
19929 .addReg(X86::EAX, RegState::ImplicitDefine);
19930 } else {
19931 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
19932 .addImm(12);
19933 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
19934 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
19935 .addExternalSymbol("__morestack_allocate_stack_space")
19936 .addRegMask(RegMask)
19937 .addReg(X86::EAX, RegState::ImplicitDefine);
19938 }
19940 if (!Is64Bit)
19941 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
19942 .addImm(16);
19944 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
19945 .addReg(IsLP64 ? X86::RAX : X86::EAX);
19946 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
19948 // Set up the CFG correctly.
19949 BB->addSuccessor(bumpMBB);
19950 BB->addSuccessor(mallocMBB);
19951 mallocMBB->addSuccessor(continueMBB);
19952 bumpMBB->addSuccessor(continueMBB);
19954 // Take care of the PHI nodes.
19955 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
19956 MI->getOperand(0).getReg())
19957 .addReg(mallocPtrVReg).addMBB(mallocMBB)
19958 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
19960 // Delete the original pseudo instruction.
19961 MI->eraseFromParent();
19963 // And we're done.
19964 return continueMBB;
19965 }
19967 MachineBasicBlock *
19968 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
19969 MachineBasicBlock *BB) const {
19970 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
19971 DebugLoc DL = MI->getDebugLoc();
19973 assert(!Subtarget->isTargetMacho());
19975 // The lowering is pretty easy: we're just emitting the call to _alloca. The
19976 // non-trivial part is impdef of ESP.
19978 if (Subtarget->isTargetWin64()) {
19979 if (Subtarget->isTargetCygMing()) {
19980 // ___chkstk(Mingw64):
19981 // Clobbers R10, R11, RAX and EFLAGS.
19982 // Updates RSP.
19983 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
19984 .addExternalSymbol("___chkstk")
19985 .addReg(X86::RAX, RegState::Implicit)
19986 .addReg(X86::RSP, RegState::Implicit)
19987 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
19988 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
19989 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19990 } else {
19991 // __chkstk(MSVCRT): does not update stack pointer.
19992 // Clobbers R10, R11 and EFLAGS.
19993 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
19994 .addExternalSymbol("__chkstk")
19995 .addReg(X86::RAX, RegState::Implicit)
19996 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19997 // RAX has the offset to be subtracted from RSP.
19998 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
19999 .addReg(X86::RSP)
20000 .addReg(X86::RAX);
20001 }
20002 } else {
20003 const char *StackProbeSymbol =
20004 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
20006 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
20007 .addExternalSymbol(StackProbeSymbol)
20008 .addReg(X86::EAX, RegState::Implicit)
20009 .addReg(X86::ESP, RegState::Implicit)
20010 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
20011 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
20012 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20013 }
20015 MI->eraseFromParent(); // The pseudo instruction is gone now.
20016 return BB;
20017 }
20019 MachineBasicBlock *
20020 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
20021 MachineBasicBlock *BB) const {
20022 // This is pretty easy. We're taking the value that we received from
20023 // our load from the relocation, sticking it in either RDI (x86-64)
20024 // or EAX and doing an indirect call. The return value will then
20025 // be in the normal return register.
20026 MachineFunction *F = BB->getParent();
20027 const X86InstrInfo *TII =
20028 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
20029 DebugLoc DL = MI->getDebugLoc();
20031 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
20032 assert(MI->getOperand(3).isGlobal() && "This should be a global");
20034 // Get a register mask for the lowered call.
20035 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
20036 // proper register mask.
20037 const uint32_t *RegMask = F->getTarget()
20038 .getSubtargetImpl()
20039 ->getRegisterInfo()
20040 ->getCallPreservedMask(CallingConv::C);
20041 if (Subtarget->is64Bit()) {
20042 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20043 TII->get(X86::MOV64rm), X86::RDI)
20044 .addReg(X86::RIP)
20045 .addImm(0).addReg(0)
20046 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20047 MI->getOperand(3).getTargetFlags())
20048 .addReg(0);
20049 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
20050 addDirectMem(MIB, X86::RDI);
20051 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
20052 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
20053 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20054 TII->get(X86::MOV32rm), X86::EAX)
20055 .addReg(0)
20056 .addImm(0).addReg(0)
20057 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20058 MI->getOperand(3).getTargetFlags())
20059 .addReg(0);
20060 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20061 addDirectMem(MIB, X86::EAX);
20062 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20063 } else {
20064 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20065 TII->get(X86::MOV32rm), X86::EAX)
20066 .addReg(TII->getGlobalBaseReg(F))
20067 .addImm(0).addReg(0)
20068 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20069 MI->getOperand(3).getTargetFlags())
20070 .addReg(0);
20071 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20072 addDirectMem(MIB, X86::EAX);
20073 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20074 }
20076 MI->eraseFromParent(); // The pseudo instruction is gone now.
20077 return BB;
20078 }
20080 MachineBasicBlock *
20081 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
20082 MachineBasicBlock *MBB) const {
20083 DebugLoc DL = MI->getDebugLoc();
20084 MachineFunction *MF = MBB->getParent();
20085 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20086 MachineRegisterInfo &MRI = MF->getRegInfo();
20088 const BasicBlock *BB = MBB->getBasicBlock();
20089 MachineFunction::iterator I = MBB;
20090 ++I;
20092 // Memory Reference
20093 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20094 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20096 unsigned DstReg;
20097 unsigned MemOpndSlot = 0;
20099 unsigned CurOp = 0;
20101 DstReg = MI->getOperand(CurOp++).getReg();
20102 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
20103 assert(RC->hasType(MVT::i32) && "Invalid destination!");
20104 unsigned mainDstReg = MRI.createVirtualRegister(RC);
20105 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
20107 MemOpndSlot = CurOp;
20109 MVT PVT = getPointerTy();
20110 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20111 "Invalid Pointer Size!");
20113 // For v = setjmp(buf), we generate
20114 //
20115 // thisMBB:
20116 // buf[LabelOffset] = restoreMBB
20117 // SjLjSetup restoreMBB
20118 //
20119 // mainMBB:
20120 // v_main = 0
20121 //
20122 // sinkMBB:
20123 // v = phi(main, restore)
20124 //
20125 // restoreMBB:
20126 // v_restore = 1
20128 MachineBasicBlock *thisMBB = MBB;
20129 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20130 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20131 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
20132 MF->insert(I, mainMBB);
20133 MF->insert(I, sinkMBB);
20134 MF->push_back(restoreMBB);
20136 MachineInstrBuilder MIB;
20138 // Transfer the remainder of BB and its successor edges to sinkMBB.
20139 sinkMBB->splice(sinkMBB->begin(), MBB,
20140 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20141 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20143 // thisMBB:
20144 unsigned PtrStoreOpc = 0;
20145 unsigned LabelReg = 0;
20146 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20147 Reloc::Model RM = MF->getTarget().getRelocationModel();
20148 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
20149 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
20151 // Prepare IP either in reg or imm.
20152 if (!UseImmLabel) {
20153 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
20154 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
20155 LabelReg = MRI.createVirtualRegister(PtrRC);
20156 if (Subtarget->is64Bit()) {
20157 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
20158 .addReg(X86::RIP)
20159 .addImm(0)
20160 .addReg(0)
20161 .addMBB(restoreMBB)
20162 .addReg(0);
20163 } else {
20164 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
20165 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
20166 .addReg(XII->getGlobalBaseReg(MF))
20167 .addImm(0)
20168 .addReg(0)
20169 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
20170 .addReg(0);
20171 }
20172 } else
20173 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
20174 // Store IP
20175 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
20176 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20177 if (i == X86::AddrDisp)
20178 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
20179 else
20180 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
20181 }
20182 if (!UseImmLabel)
20183 MIB.addReg(LabelReg);
20184 else
20185 MIB.addMBB(restoreMBB);
20186 MIB.setMemRefs(MMOBegin, MMOEnd);
20187 // Setup
20188 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
20189 .addMBB(restoreMBB);
20191 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20192 MF->getSubtarget().getRegisterInfo());
20193 MIB.addRegMask(RegInfo->getNoPreservedMask());
20194 thisMBB->addSuccessor(mainMBB);
20195 thisMBB->addSuccessor(restoreMBB);
20197 // mainMBB:
20198 // EAX = 0
20199 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
20200 mainMBB->addSuccessor(sinkMBB);
20202 // sinkMBB:
20203 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20204 TII->get(X86::PHI), DstReg)
20205 .addReg(mainDstReg).addMBB(mainMBB)
20206 .addReg(restoreDstReg).addMBB(restoreMBB);
20208 // restoreMBB:
20209 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
20210 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
20211 restoreMBB->addSuccessor(sinkMBB);
20213 MI->eraseFromParent();
20214 return sinkMBB;
20215 }
20217 MachineBasicBlock *
20218 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
20219 MachineBasicBlock *MBB) const {
20220 DebugLoc DL = MI->getDebugLoc();
20221 MachineFunction *MF = MBB->getParent();
20222 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20223 MachineRegisterInfo &MRI = MF->getRegInfo();
20225 // Memory Reference
20226 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20227 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20229 MVT PVT = getPointerTy();
20230 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20231 "Invalid Pointer Size!");
20233 const TargetRegisterClass *RC =
20234 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
20235 unsigned Tmp = MRI.createVirtualRegister(RC);
20236 // Since FP is only updated here but NOT referenced, it's treated as GPR.
20237 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20238 MF->getSubtarget().getRegisterInfo());
20239 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
20240 unsigned SP = RegInfo->getStackRegister();
20242 MachineInstrBuilder MIB;
20244 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20245 const int64_t SPOffset = 2 * PVT.getStoreSize();
20247 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
20248 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
20250 // Reload FP
20251 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
20252 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
20253 MIB.addOperand(MI->getOperand(i));
20254 MIB.setMemRefs(MMOBegin, MMOEnd);
20255 // Reload IP
20256 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
20257 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20258 if (i == X86::AddrDisp)
20259 MIB.addDisp(MI->getOperand(i), LabelOffset);
20260 else
20261 MIB.addOperand(MI->getOperand(i));
20262 }
20263 MIB.setMemRefs(MMOBegin, MMOEnd);
20264 // Reload SP
20265 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
20266 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20267 if (i == X86::AddrDisp)
20268 MIB.addDisp(MI->getOperand(i), SPOffset);
20269 else
20270 MIB.addOperand(MI->getOperand(i));
20271 }
20272 MIB.setMemRefs(MMOBegin, MMOEnd);
20273 // Jump
20274 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
20276 MI->eraseFromParent();
20277 return MBB;
20278 }
20280 // Replace 213-type (isel default) FMA3 instructions with 231-type for
20281 // accumulator loops. Writing back to the accumulator allows the coalescer
20282 // to remove extra copies in the loop.
20283 MachineBasicBlock *
20284 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
20285 MachineBasicBlock *MBB) const {
20286 MachineOperand &AddendOp = MI->getOperand(3);
20288 // Bail out early if the addend isn't a register - we can't switch these.
20289 if (!AddendOp.isReg())
20290 return MBB;
20292 MachineFunction &MF = *MBB->getParent();
20293 MachineRegisterInfo &MRI = MF.getRegInfo();
20295 // Check whether the addend is defined by a PHI:
20296 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
20297 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
20298 if (!AddendDef.isPHI())
20299 return MBB;
20301 // Look for the following pattern:
20302 // loop:
20303 // %addend = phi [%entry, 0], [%loop, %result]
20304 // ...
20305 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
20307 // Replace with:
20308 // loop:
20309 // %addend = phi [%entry, 0], [%loop, %result]
20310 // ...
20311 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
20313 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
20314 assert(AddendDef.getOperand(i).isReg());
20315 MachineOperand PHISrcOp = AddendDef.getOperand(i);
20316 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
20317 if (&PHISrcInst == MI) {
20318 // Found a matching instruction.
20319 unsigned NewFMAOpc = 0;
20320 switch (MI->getOpcode()) {
20321 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
20322 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
20323 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
20324 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
20325 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
20326 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
20327 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
20328 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
20329 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
20330 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
20331 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
20332 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
20333 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
20334 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
20335 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
20336 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
20337 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
20338 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
20339 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
20340 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
20341 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
20342 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
20343 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
20344 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
20345 default: llvm_unreachable("Unrecognized FMA variant.");
20346 }
20348 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
20349 MachineInstrBuilder MIB =
20350 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
20351 .addOperand(MI->getOperand(0))
20352 .addOperand(MI->getOperand(3))
20353 .addOperand(MI->getOperand(2))
20354 .addOperand(MI->getOperand(1));
20355 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
20356 MI->eraseFromParent();
20357 }
20358 }
20360 return MBB;
20361 }
20363 MachineBasicBlock *
20364 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
20365 MachineBasicBlock *BB) const {
20366 switch (MI->getOpcode()) {
20367 default: llvm_unreachable("Unexpected instr type to insert");
20368 case X86::TAILJMPd64:
20369 case X86::TAILJMPr64:
20370 case X86::TAILJMPm64:
20371 llvm_unreachable("TAILJMP64 would not be touched here.");
20372 case X86::TCRETURNdi64:
20373 case X86::TCRETURNri64:
20374 case X86::TCRETURNmi64:
20375 return BB;
20376 case X86::WIN_ALLOCA:
20377 return EmitLoweredWinAlloca(MI, BB);
20378 case X86::SEG_ALLOCA_32:
20379 case X86::SEG_ALLOCA_64:
20380 return EmitLoweredSegAlloca(MI, BB);
20381 case X86::TLSCall_32:
20382 case X86::TLSCall_64:
20383 return EmitLoweredTLSCall(MI, BB);
20384 case X86::CMOV_GR8:
20385 case X86::CMOV_FR32:
20386 case X86::CMOV_FR64:
20387 case X86::CMOV_V4F32:
20388 case X86::CMOV_V2F64:
20389 case X86::CMOV_V2I64:
20390 case X86::CMOV_V8F32:
20391 case X86::CMOV_V4F64:
20392 case X86::CMOV_V4I64:
20393 case X86::CMOV_V16F32:
20394 case X86::CMOV_V8F64:
20395 case X86::CMOV_V8I64:
20396 case X86::CMOV_GR16:
20397 case X86::CMOV_GR32:
20398 case X86::CMOV_RFP32:
20399 case X86::CMOV_RFP64:
20400 case X86::CMOV_RFP80:
20401 return EmitLoweredSelect(MI, BB);
20403 case X86::FP32_TO_INT16_IN_MEM:
20404 case X86::FP32_TO_INT32_IN_MEM:
20405 case X86::FP32_TO_INT64_IN_MEM:
20406 case X86::FP64_TO_INT16_IN_MEM:
20407 case X86::FP64_TO_INT32_IN_MEM:
20408 case X86::FP64_TO_INT64_IN_MEM:
20409 case X86::FP80_TO_INT16_IN_MEM:
20410 case X86::FP80_TO_INT32_IN_MEM:
20411 case X86::FP80_TO_INT64_IN_MEM: {
20412 MachineFunction *F = BB->getParent();
20413 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
20414 DebugLoc DL = MI->getDebugLoc();
20416 // Change the floating point control register to use "round towards zero"
20417 // mode when truncating to an integer value.
20418 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
20419 addFrameReference(BuildMI(*BB, MI, DL,
20420 TII->get(X86::FNSTCW16m)), CWFrameIdx);
20422 // Load the old value of the high byte of the control word...
20423 unsigned OldCW =
20424 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
20425 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
20426 CWFrameIdx);
20428 // Set the high part to be round to zero...
20429 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
20430 .addImm(0xC7F);
20432 // Reload the modified control word now...
20433 addFrameReference(BuildMI(*BB, MI, DL,
20434 TII->get(X86::FLDCW16m)), CWFrameIdx);
20436 // Restore the memory image of control word to original value
20437 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
20438 .addReg(OldCW);
20440 // Get the X86 opcode to use.
20441 unsigned Opc;
20442 switch (MI->getOpcode()) {
20443 default: llvm_unreachable("illegal opcode!");
20444 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
20445 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
20446 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
20447 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
20448 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
20449 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
20450 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
20451 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
20452 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
20453 }
20455 X86AddressMode AM;
20456 MachineOperand &Op = MI->getOperand(0);
20457 if (Op.isReg()) {
20458 AM.BaseType = X86AddressMode::RegBase;
20459 AM.Base.Reg = Op.getReg();
20460 } else {
20461 AM.BaseType = X86AddressMode::FrameIndexBase;
20462 AM.Base.FrameIndex = Op.getIndex();
20463 }
20464 Op = MI->getOperand(1);
20465 if (Op.isImm())
20466 AM.Scale = Op.getImm();
20467 Op = MI->getOperand(2);
20468 if (Op.isImm())
20469 AM.IndexReg = Op.getImm();
20470 Op = MI->getOperand(3);
20471 if (Op.isGlobal()) {
20472 AM.GV = Op.getGlobal();
20473 } else {
20474 AM.Disp = Op.getImm();
20475 }
20476 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
20477 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
20479 // Reload the original control word now.
20480 addFrameReference(BuildMI(*BB, MI, DL,
20481 TII->get(X86::FLDCW16m)), CWFrameIdx);
20483 MI->eraseFromParent(); // The pseudo instruction is gone now.
20484 return BB;
20485 }
20486 // String/text processing lowering.
20487 case X86::PCMPISTRM128REG:
20488 case X86::VPCMPISTRM128REG:
20489 case X86::PCMPISTRM128MEM:
20490 case X86::VPCMPISTRM128MEM:
20491 case X86::PCMPESTRM128REG:
20492 case X86::VPCMPESTRM128REG:
20493 case X86::PCMPESTRM128MEM:
20494 case X86::VPCMPESTRM128MEM:
20495 assert(Subtarget->hasSSE42() &&
20496 "Target must have SSE4.2 or AVX features enabled");
20497 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20499 // String/text processing lowering.
20500 case X86::PCMPISTRIREG:
20501 case X86::VPCMPISTRIREG:
20502 case X86::PCMPISTRIMEM:
20503 case X86::VPCMPISTRIMEM:
20504 case X86::PCMPESTRIREG:
20505 case X86::VPCMPESTRIREG:
20506 case X86::PCMPESTRIMEM:
20507 case X86::VPCMPESTRIMEM:
20508 assert(Subtarget->hasSSE42() &&
20509 "Target must have SSE4.2 or AVX features enabled");
20510 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20512 // Thread synchronization.
20513 case X86::MONITOR:
20514 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
20515 Subtarget);
20517 // xbegin
20518 case X86::XBEGIN:
20519 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20521 case X86::VASTART_SAVE_XMM_REGS:
20522 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
20524 case X86::VAARG_64:
20525 return EmitVAARG64WithCustomInserter(MI, BB);
20527 case X86::EH_SjLj_SetJmp32:
20528 case X86::EH_SjLj_SetJmp64:
20529 return emitEHSjLjSetJmp(MI, BB);
20531 case X86::EH_SjLj_LongJmp32:
20532 case X86::EH_SjLj_LongJmp64:
20533 return emitEHSjLjLongJmp(MI, BB);
20535 case TargetOpcode::STACKMAP:
20536 case TargetOpcode::PATCHPOINT:
20537 return emitPatchPoint(MI, BB);
20539 case X86::VFMADDPDr213r:
20540 case X86::VFMADDPSr213r:
20541 case X86::VFMADDSDr213r:
20542 case X86::VFMADDSSr213r:
20543 case X86::VFMSUBPDr213r:
20544 case X86::VFMSUBPSr213r:
20545 case X86::VFMSUBSDr213r:
20546 case X86::VFMSUBSSr213r:
20547 case X86::VFNMADDPDr213r:
20548 case X86::VFNMADDPSr213r:
20549 case X86::VFNMADDSDr213r:
20550 case X86::VFNMADDSSr213r:
20551 case X86::VFNMSUBPDr213r:
20552 case X86::VFNMSUBPSr213r:
20553 case X86::VFNMSUBSDr213r:
20554 case X86::VFNMSUBSSr213r:
20555 case X86::VFMADDPDr213rY:
20556 case X86::VFMADDPSr213rY:
20557 case X86::VFMSUBPDr213rY:
20558 case X86::VFMSUBPSr213rY:
20559 case X86::VFNMADDPDr213rY:
20560 case X86::VFNMADDPSr213rY:
20561 case X86::VFNMSUBPDr213rY:
20562 case X86::VFNMSUBPSr213rY:
20563 return emitFMA3Instr(MI, BB);
20564 }
20565 }
20567 //===----------------------------------------------------------------------===//
20568 // X86 Optimization Hooks
20569 //===----------------------------------------------------------------------===//
20571 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
20572 APInt &KnownZero,
20573 APInt &KnownOne,
20574 const SelectionDAG &DAG,
20575 unsigned Depth) const {
20576 unsigned BitWidth = KnownZero.getBitWidth();
20577 unsigned Opc = Op.getOpcode();
20578 assert((Opc >= ISD::BUILTIN_OP_END ||
20579 Opc == ISD::INTRINSIC_WO_CHAIN ||
20580 Opc == ISD::INTRINSIC_W_CHAIN ||
20581 Opc == ISD::INTRINSIC_VOID) &&
20582 "Should use MaskedValueIsZero if you don't know whether Op"
20583 " is a target node!");
20585 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
20586 switch (Opc) {
20587 default: break;
20588 case X86ISD::ADD:
20589 case X86ISD::SUB:
20590 case X86ISD::ADC:
20591 case X86ISD::SBB:
20592 case X86ISD::SMUL:
20593 case X86ISD::UMUL:
20594 case X86ISD::INC:
20595 case X86ISD::DEC:
20596 case X86ISD::OR:
20597 case X86ISD::XOR:
20598 case X86ISD::AND:
20599 // These nodes' second result is a boolean.
20600 if (Op.getResNo() == 0)
20601 break;
20602 // Fallthrough
20603 case X86ISD::SETCC:
20604 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
20605 break;
20606 case ISD::INTRINSIC_WO_CHAIN: {
20607 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
20608 unsigned NumLoBits = 0;
20609 switch (IntId) {
20610 default: break;
20611 case Intrinsic::x86_sse_movmsk_ps:
20612 case Intrinsic::x86_avx_movmsk_ps_256:
20613 case Intrinsic::x86_sse2_movmsk_pd:
20614 case Intrinsic::x86_avx_movmsk_pd_256:
20615 case Intrinsic::x86_mmx_pmovmskb:
20616 case Intrinsic::x86_sse2_pmovmskb_128:
20617 case Intrinsic::x86_avx2_pmovmskb: {
20618 // High bits of movmskp{s|d}, pmovmskb are known zero.
20619 switch (IntId) {
20620 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
20621 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
20622 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
20623 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
20624 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
20625 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
20626 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
20627 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
20628 }
20629 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
20630 break;
20631 }
20632 }
20633 break;
20634 }
20635 }
20636 }
20638 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
20639 SDValue Op,
20640 const SelectionDAG &,
20641 unsigned Depth) const {
20642 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
20643 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
20644 return Op.getValueType().getScalarType().getSizeInBits();
20646 // Fallback case.
20647 return 1;
20648 }
20650 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
20651 /// node is a GlobalAddress + offset.
20652 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
20653 const GlobalValue* &GA,
20654 int64_t &Offset) const {
20655 if (N->getOpcode() == X86ISD::Wrapper) {
20656 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
20657 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
20658 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
20659 return true;
20660 }
20661 }
20662 return TargetLowering::isGAPlusOffset(N, GA, Offset);
20663 }
20665 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
20666 /// same as extracting the high 128-bit part of 256-bit vector and then
20667 /// inserting the result into the low part of a new 256-bit vector
20668 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
20669 EVT VT = SVOp->getValueType(0);
20670 unsigned NumElems = VT.getVectorNumElements();
20672 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20673 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
20674 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20675 SVOp->getMaskElt(j) >= 0)
20676 return false;
20678 return true;
20679 }
20681 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
20682 /// same as extracting the low 128-bit part of 256-bit vector and then
20683 /// inserting the result into the high part of a new 256-bit vector
20684 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
20685 EVT VT = SVOp->getValueType(0);
20686 unsigned NumElems = VT.getVectorNumElements();
20688 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20689 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
20690 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20691 SVOp->getMaskElt(j) >= 0)
20692 return false;
20694 return true;
20695 }
20697 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
20698 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
20699 TargetLowering::DAGCombinerInfo &DCI,
20700 const X86Subtarget* Subtarget) {
20701 SDLoc dl(N);
20702 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20703 SDValue V1 = SVOp->getOperand(0);
20704 SDValue V2 = SVOp->getOperand(1);
20705 EVT VT = SVOp->getValueType(0);
20706 unsigned NumElems = VT.getVectorNumElements();
20708 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
20709 V2.getOpcode() == ISD::CONCAT_VECTORS) {
20710 //
20711 // 0,0,0,...
20712 // |
20713 // V UNDEF BUILD_VECTOR UNDEF
20714 // \ / \ /
20715 // CONCAT_VECTOR CONCAT_VECTOR
20716 // \ /
20717 // \ /
20718 // RESULT: V + zero extended
20719 //
20720 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
20721 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
20722 V1.getOperand(1).getOpcode() != ISD::UNDEF)
20723 return SDValue();
20725 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
20726 return SDValue();
20728 // To match the shuffle mask, the first half of the mask should
20729 // be exactly the first vector, and all the rest a splat with the
20730 // first element of the second one.
20731 for (unsigned i = 0; i != NumElems/2; ++i)
20732 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
20733 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
20734 return SDValue();
20736 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
20737 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
20738 if (Ld->hasNUsesOfValue(1, 0)) {
20739 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
20740 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
20741 SDValue ResNode =
20742 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
20743 Ld->getMemoryVT(),
20744 Ld->getPointerInfo(),
20745 Ld->getAlignment(),
20746 false/*isVolatile*/, true/*ReadMem*/,
20747 false/*WriteMem*/);
20749 // Make sure the newly-created LOAD is in the same position as Ld in
20750 // terms of dependency. We create a TokenFactor for Ld and ResNode,
20751 // and update uses of Ld's output chain to use the TokenFactor.
20752 if (Ld->hasAnyUseOfValue(1)) {
20753 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
20754 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
20755 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
20756 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
20757 SDValue(ResNode.getNode(), 1));
20758 }
20760 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
20761 }
20762 }
20764 // Emit a zeroed vector and insert the desired subvector on its
20765 // first half.
20766 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
20767 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
20768 return DCI.CombineTo(N, InsV);
20769 }
20771 //===--------------------------------------------------------------------===//
20772 // Combine some shuffles into subvector extracts and inserts:
20773 //
20775 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20776 if (isShuffleHigh128VectorInsertLow(SVOp)) {
20777 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
20778 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
20779 return DCI.CombineTo(N, InsV);
20780 }
20782 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20783 if (isShuffleLow128VectorInsertHigh(SVOp)) {
20784 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
20785 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
20786 return DCI.CombineTo(N, InsV);
20787 }
20789 return SDValue();
20790 }
20792 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
20793 /// possible.
20794 ///
20795 /// This is the leaf of the recursive combinine below. When we have found some
20796 /// chain of single-use x86 shuffle instructions and accumulated the combined
20797 /// shuffle mask represented by them, this will try to pattern match that mask
20798 /// into either a single instruction if there is a special purpose instruction
20799 /// for this operation, or into a PSHUFB instruction which is a fully general
20800 /// instruction but should only be used to replace chains over a certain depth.
20801 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
20802 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
20803 TargetLowering::DAGCombinerInfo &DCI,
20804 const X86Subtarget *Subtarget) {
20805 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
20807 // Find the operand that enters the chain. Note that multiple uses are OK
20808 // here, we're not going to remove the operand we find.
20809 SDValue Input = Op.getOperand(0);
20810 while (Input.getOpcode() == ISD::BITCAST)
20811 Input = Input.getOperand(0);
20813 MVT VT = Input.getSimpleValueType();
20814 MVT RootVT = Root.getSimpleValueType();
20815 SDLoc DL(Root);
20817 // Just remove no-op shuffle masks.
20818 if (Mask.size() == 1) {
20819 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
20820 /*AddTo*/ true);
20821 return true;
20822 }
20824 // Use the float domain if the operand type is a floating point type.
20825 bool FloatDomain = VT.isFloatingPoint();
20827 // For floating point shuffles, we don't have free copies in the shuffle
20828 // instructions or the ability to load as part of the instruction, so
20829 // canonicalize their shuffles to UNPCK or MOV variants.
20830 //
20831 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
20832 // vectors because it can have a load folded into it that UNPCK cannot. This
20833 // doesn't preclude something switching to the shorter encoding post-RA.
20834 if (FloatDomain) {
20835 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
20836 bool Lo = Mask.equals(0, 0);
20837 unsigned Shuffle;
20838 MVT ShuffleVT;
20839 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
20840 // is no slower than UNPCKLPD but has the option to fold the input operand
20841 // into even an unaligned memory load.
20842 if (Lo && Subtarget->hasSSE3()) {
20843 Shuffle = X86ISD::MOVDDUP;
20844 ShuffleVT = MVT::v2f64;
20845 } else {
20846 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
20847 // than the UNPCK variants.
20848 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
20849 ShuffleVT = MVT::v4f32;
20850 }
20851 if (Depth == 1 && Root->getOpcode() == Shuffle)
20852 return false; // Nothing to do!
20853 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20854 DCI.AddToWorklist(Op.getNode());
20855 if (Shuffle == X86ISD::MOVDDUP)
20856 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20857 else
20858 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20859 DCI.AddToWorklist(Op.getNode());
20860 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20861 /*AddTo*/ true);
20862 return true;
20863 }
20864 if (Subtarget->hasSSE3() &&
20865 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
20866 bool Lo = Mask.equals(0, 0, 2, 2);
20867 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
20868 MVT ShuffleVT = MVT::v4f32;
20869 if (Depth == 1 && Root->getOpcode() == Shuffle)
20870 return false; // Nothing to do!
20871 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20872 DCI.AddToWorklist(Op.getNode());
20873 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20874 DCI.AddToWorklist(Op.getNode());
20875 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20876 /*AddTo*/ true);
20877 return true;
20878 }
20879 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
20880 bool Lo = Mask.equals(0, 0, 1, 1);
20881 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20882 MVT ShuffleVT = MVT::v4f32;
20883 if (Depth == 1 && Root->getOpcode() == Shuffle)
20884 return false; // Nothing to do!
20885 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20886 DCI.AddToWorklist(Op.getNode());
20887 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20888 DCI.AddToWorklist(Op.getNode());
20889 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20890 /*AddTo*/ true);
20891 return true;
20892 }
20893 }
20895 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
20896 // variants as none of these have single-instruction variants that are
20897 // superior to the UNPCK formulation.
20898 if (!FloatDomain &&
20899 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
20900 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
20901 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
20902 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
20903 15))) {
20904 bool Lo = Mask[0] == 0;
20905 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20906 if (Depth == 1 && Root->getOpcode() == Shuffle)
20907 return false; // Nothing to do!
20908 MVT ShuffleVT;
20909 switch (Mask.size()) {
20910 case 8:
20911 ShuffleVT = MVT::v8i16;
20912 break;
20913 case 16:
20914 ShuffleVT = MVT::v16i8;
20915 break;
20916 default:
20917 llvm_unreachable("Impossible mask size!");
20918 };
20919 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20920 DCI.AddToWorklist(Op.getNode());
20921 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20922 DCI.AddToWorklist(Op.getNode());
20923 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20924 /*AddTo*/ true);
20925 return true;
20926 }
20928 // Don't try to re-form single instruction chains under any circumstances now
20929 // that we've done encoding canonicalization for them.
20930 if (Depth < 2)
20931 return false;
20933 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
20934 // can replace them with a single PSHUFB instruction profitably. Intel's
20935 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
20936 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
20937 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
20938 SmallVector<SDValue, 16> PSHUFBMask;
20939 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
20940 int Ratio = 16 / Mask.size();
20941 for (unsigned i = 0; i < 16; ++i) {
20942 if (Mask[i / Ratio] == SM_SentinelUndef) {
20943 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
20944 continue;
20945 }
20946 int M = Mask[i / Ratio] != SM_SentinelZero
20947 ? Ratio * Mask[i / Ratio] + i % Ratio
20948 : 255;
20949 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
20950 }
20951 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
20952 DCI.AddToWorklist(Op.getNode());
20953 SDValue PSHUFBMaskOp =
20954 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
20955 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
20956 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
20957 DCI.AddToWorklist(Op.getNode());
20958 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20959 /*AddTo*/ true);
20960 return true;
20961 }
20963 // Failed to find any combines.
20964 return false;
20965 }
20967 /// \brief Fully generic combining of x86 shuffle instructions.
20968 ///
20969 /// This should be the last combine run over the x86 shuffle instructions. Once
20970 /// they have been fully optimized, this will recursively consider all chains
20971 /// of single-use shuffle instructions, build a generic model of the cumulative
20972 /// shuffle operation, and check for simpler instructions which implement this
20973 /// operation. We use this primarily for two purposes:
20974 ///
20975 /// 1) Collapse generic shuffles to specialized single instructions when
20976 /// equivalent. In most cases, this is just an encoding size win, but
20977 /// sometimes we will collapse multiple generic shuffles into a single
20978 /// special-purpose shuffle.
20979 /// 2) Look for sequences of shuffle instructions with 3 or more total
20980 /// instructions, and replace them with the slightly more expensive SSSE3
20981 /// PSHUFB instruction if available. We do this as the last combining step
20982 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
20983 /// a suitable short sequence of other instructions. The PHUFB will either
20984 /// use a register or have to read from memory and so is slightly (but only
20985 /// slightly) more expensive than the other shuffle instructions.
20986 ///
20987 /// Because this is inherently a quadratic operation (for each shuffle in
20988 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
20989 /// This should never be an issue in practice as the shuffle lowering doesn't
20990 /// produce sequences of more than 8 instructions.
20991 ///
20992 /// FIXME: We will currently miss some cases where the redundant shuffling
20993 /// would simplify under the threshold for PSHUFB formation because of
20994 /// combine-ordering. To fix this, we should do the redundant instruction
20995 /// combining in this recursive walk.
20996 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
20997 ArrayRef<int> RootMask,
20998 int Depth, bool HasPSHUFB,
20999 SelectionDAG &DAG,
21000 TargetLowering::DAGCombinerInfo &DCI,
21001 const X86Subtarget *Subtarget) {
21002 // Bound the depth of our recursive combine because this is ultimately
21003 // quadratic in nature.
21004 if (Depth > 8)
21005 return false;
21007 // Directly rip through bitcasts to find the underlying operand.
21008 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
21009 Op = Op.getOperand(0);
21011 MVT VT = Op.getSimpleValueType();
21012 if (!VT.isVector())
21013 return false; // Bail if we hit a non-vector.
21014 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
21015 // version should be added.
21016 if (VT.getSizeInBits() != 128)
21017 return false;
21019 assert(Root.getSimpleValueType().isVector() &&
21020 "Shuffles operate on vector types!");
21021 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
21022 "Can only combine shuffles of the same vector register size.");
21024 if (!isTargetShuffle(Op.getOpcode()))
21025 return false;
21026 SmallVector<int, 16> OpMask;
21027 bool IsUnary;
21028 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
21029 // We only can combine unary shuffles which we can decode the mask for.
21030 if (!HaveMask || !IsUnary)
21031 return false;
21033 assert(VT.getVectorNumElements() == OpMask.size() &&
21034 "Different mask size from vector size!");
21035 assert(((RootMask.size() > OpMask.size() &&
21036 RootMask.size() % OpMask.size() == 0) ||
21037 (OpMask.size() > RootMask.size() &&
21038 OpMask.size() % RootMask.size() == 0) ||
21039 OpMask.size() == RootMask.size()) &&
21040 "The smaller number of elements must divide the larger.");
21041 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
21042 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
21043 assert(((RootRatio == 1 && OpRatio == 1) ||
21044 (RootRatio == 1) != (OpRatio == 1)) &&
21045 "Must not have a ratio for both incoming and op masks!");
21047 SmallVector<int, 16> Mask;
21048 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
21050 // Merge this shuffle operation's mask into our accumulated mask. Note that
21051 // this shuffle's mask will be the first applied to the input, followed by the
21052 // root mask to get us all the way to the root value arrangement. The reason
21053 // for this order is that we are recursing up the operation chain.
21054 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
21055 int RootIdx = i / RootRatio;
21056 if (RootMask[RootIdx] < 0) {
21057 // This is a zero or undef lane, we're done.
21058 Mask.push_back(RootMask[RootIdx]);
21059 continue;
21060 }
21062 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
21063 int OpIdx = RootMaskedIdx / OpRatio;
21064 if (OpMask[OpIdx] < 0) {
21065 // The incoming lanes are zero or undef, it doesn't matter which ones we
21066 // are using.
21067 Mask.push_back(OpMask[OpIdx]);
21068 continue;
21069 }
21071 // Ok, we have non-zero lanes, map them through.
21072 Mask.push_back(OpMask[OpIdx] * OpRatio +
21073 RootMaskedIdx % OpRatio);
21074 }
21076 // See if we can recurse into the operand to combine more things.
21077 switch (Op.getOpcode()) {
21078 case X86ISD::PSHUFB:
21079 HasPSHUFB = true;
21080 case X86ISD::PSHUFD:
21081 case X86ISD::PSHUFHW:
21082 case X86ISD::PSHUFLW:
21083 if (Op.getOperand(0).hasOneUse() &&
21084 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21085 HasPSHUFB, DAG, DCI, Subtarget))
21086 return true;
21087 break;
21089 case X86ISD::UNPCKL:
21090 case X86ISD::UNPCKH:
21091 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
21092 // We can't check for single use, we have to check that this shuffle is the only user.
21093 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
21094 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21095 HasPSHUFB, DAG, DCI, Subtarget))
21096 return true;
21097 break;
21098 }
21100 // Minor canonicalization of the accumulated shuffle mask to make it easier
21101 // to match below. All this does is detect masks with squential pairs of
21102 // elements, and shrink them to the half-width mask. It does this in a loop
21103 // so it will reduce the size of the mask to the minimal width mask which
21104 // performs an equivalent shuffle.
21105 SmallVector<int, 16> WidenedMask;
21106 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
21107 Mask = std::move(WidenedMask);
21108 WidenedMask.clear();
21109 }
21111 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
21112 Subtarget);
21113 }
21115 /// \brief Get the PSHUF-style mask from PSHUF node.
21116 ///
21117 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
21118 /// PSHUF-style masks that can be reused with such instructions.
21119 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
21120 SmallVector<int, 4> Mask;
21121 bool IsUnary;
21122 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
21123 (void)HaveMask;
21124 assert(HaveMask);
21126 switch (N.getOpcode()) {
21127 case X86ISD::PSHUFD:
21128 return Mask;
21129 case X86ISD::PSHUFLW:
21130 Mask.resize(4);
21131 return Mask;
21132 case X86ISD::PSHUFHW:
21133 Mask.erase(Mask.begin(), Mask.begin() + 4);
21134 for (int &M : Mask)
21135 M -= 4;
21136 return Mask;
21137 default:
21138 llvm_unreachable("No valid shuffle instruction found!");
21139 }
21140 }
21142 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
21143 ///
21144 /// We walk up the chain and look for a combinable shuffle, skipping over
21145 /// shuffles that we could hoist this shuffle's transformation past without
21146 /// altering anything.
21147 static SDValue
21148 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
21149 SelectionDAG &DAG,
21150 TargetLowering::DAGCombinerInfo &DCI) {
21151 assert(N.getOpcode() == X86ISD::PSHUFD &&
21152 "Called with something other than an x86 128-bit half shuffle!");
21153 SDLoc DL(N);
21155 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
21156 // of the shuffles in the chain so that we can form a fresh chain to replace
21157 // this one.
21158 SmallVector<SDValue, 8> Chain;
21159 SDValue V = N.getOperand(0);
21160 for (; V.hasOneUse(); V = V.getOperand(0)) {
21161 switch (V.getOpcode()) {
21162 default:
21163 return SDValue(); // Nothing combined!
21165 case ISD::BITCAST:
21166 // Skip bitcasts as we always know the type for the target specific
21167 // instructions.
21168 continue;
21170 case X86ISD::PSHUFD:
21171 // Found another dword shuffle.
21172 break;
21174 case X86ISD::PSHUFLW:
21175 // Check that the low words (being shuffled) are the identity in the
21176 // dword shuffle, and the high words are self-contained.
21177 if (Mask[0] != 0 || Mask[1] != 1 ||
21178 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
21179 return SDValue();
21181 Chain.push_back(V);
21182 continue;
21184 case X86ISD::PSHUFHW:
21185 // Check that the high words (being shuffled) are the identity in the
21186 // dword shuffle, and the low words are self-contained.
21187 if (Mask[2] != 2 || Mask[3] != 3 ||
21188 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
21189 return SDValue();
21191 Chain.push_back(V);
21192 continue;
21194 case X86ISD::UNPCKL:
21195 case X86ISD::UNPCKH:
21196 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
21197 // shuffle into a preceding word shuffle.
21198 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
21199 return SDValue();
21201 // Search for a half-shuffle which we can combine with.
21202 unsigned CombineOp =
21203 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
21204 if (V.getOperand(0) != V.getOperand(1) ||
21205 !V->isOnlyUserOf(V.getOperand(0).getNode()))
21206 return SDValue();
21207 Chain.push_back(V);
21208 V = V.getOperand(0);
21209 do {
21210 switch (V.getOpcode()) {
21211 default:
21212 return SDValue(); // Nothing to combine.
21214 case X86ISD::PSHUFLW:
21215 case X86ISD::PSHUFHW:
21216 if (V.getOpcode() == CombineOp)
21217 break;
21219 Chain.push_back(V);
21221 // Fallthrough!
21222 case ISD::BITCAST:
21223 V = V.getOperand(0);
21224 continue;
21225 }
21226 break;
21227 } while (V.hasOneUse());
21228 break;
21229 }
21230 // Break out of the loop if we break out of the switch.
21231 break;
21232 }
21234 if (!V.hasOneUse())
21235 // We fell out of the loop without finding a viable combining instruction.
21236 return SDValue();
21238 // Merge this node's mask and our incoming mask.
21239 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21240 for (int &M : Mask)
21241 M = VMask[M];
21242 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
21243 getV4X86ShuffleImm8ForMask(Mask, DAG));
21245 // Rebuild the chain around this new shuffle.
21246 while (!Chain.empty()) {
21247 SDValue W = Chain.pop_back_val();
21249 if (V.getValueType() != W.getOperand(0).getValueType())
21250 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
21252 switch (W.getOpcode()) {
21253 default:
21254 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
21256 case X86ISD::UNPCKL:
21257 case X86ISD::UNPCKH:
21258 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
21259 break;
21261 case X86ISD::PSHUFD:
21262 case X86ISD::PSHUFLW:
21263 case X86ISD::PSHUFHW:
21264 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
21265 break;
21266 }
21267 }
21268 if (V.getValueType() != N.getValueType())
21269 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
21271 // Return the new chain to replace N.
21272 return V;
21273 }
21275 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
21276 ///
21277 /// We walk up the chain, skipping shuffles of the other half and looking
21278 /// through shuffles which switch halves trying to find a shuffle of the same
21279 /// pair of dwords.
21280 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
21281 SelectionDAG &DAG,
21282 TargetLowering::DAGCombinerInfo &DCI) {
21283 assert(
21284 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
21285 "Called with something other than an x86 128-bit half shuffle!");
21286 SDLoc DL(N);
21287 unsigned CombineOpcode = N.getOpcode();
21289 // Walk up a single-use chain looking for a combinable shuffle.
21290 SDValue V = N.getOperand(0);
21291 for (; V.hasOneUse(); V = V.getOperand(0)) {
21292 switch (V.getOpcode()) {
21293 default:
21294 return false; // Nothing combined!
21296 case ISD::BITCAST:
21297 // Skip bitcasts as we always know the type for the target specific
21298 // instructions.
21299 continue;
21301 case X86ISD::PSHUFLW:
21302 case X86ISD::PSHUFHW:
21303 if (V.getOpcode() == CombineOpcode)
21304 break;
21306 // Other-half shuffles are no-ops.
21307 continue;
21308 }
21309 // Break out of the loop if we break out of the switch.
21310 break;
21311 }
21313 if (!V.hasOneUse())
21314 // We fell out of the loop without finding a viable combining instruction.
21315 return false;
21317 // Combine away the bottom node as its shuffle will be accumulated into
21318 // a preceding shuffle.
21319 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21321 // Record the old value.
21322 SDValue Old = V;
21324 // Merge this node's mask and our incoming mask (adjusted to account for all
21325 // the pshufd instructions encountered).
21326 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21327 for (int &M : Mask)
21328 M = VMask[M];
21329 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
21330 getV4X86ShuffleImm8ForMask(Mask, DAG));
21332 // Check that the shuffles didn't cancel each other out. If not, we need to
21333 // combine to the new one.
21334 if (Old != V)
21335 // Replace the combinable shuffle with the combined one, updating all users
21336 // so that we re-evaluate the chain here.
21337 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
21339 return true;
21340 }
21342 /// \brief Try to combine x86 target specific shuffles.
21343 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
21344 TargetLowering::DAGCombinerInfo &DCI,
21345 const X86Subtarget *Subtarget) {
21346 SDLoc DL(N);
21347 MVT VT = N.getSimpleValueType();
21348 SmallVector<int, 4> Mask;
21350 switch (N.getOpcode()) {
21351 case X86ISD::PSHUFD:
21352 case X86ISD::PSHUFLW:
21353 case X86ISD::PSHUFHW:
21354 Mask = getPSHUFShuffleMask(N);
21355 assert(Mask.size() == 4);
21356 break;
21357 default:
21358 return SDValue();
21359 }
21361 // Nuke no-op shuffles that show up after combining.
21362 if (isNoopShuffleMask(Mask))
21363 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21365 // Look for simplifications involving one or two shuffle instructions.
21366 SDValue V = N.getOperand(0);
21367 switch (N.getOpcode()) {
21368 default:
21369 break;
21370 case X86ISD::PSHUFLW:
21371 case X86ISD::PSHUFHW:
21372 assert(VT == MVT::v8i16);
21373 (void)VT;
21375 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
21376 return SDValue(); // We combined away this shuffle, so we're done.
21378 // See if this reduces to a PSHUFD which is no more expensive and can
21379 // combine with more operations. Note that it has to at least flip the
21380 // dwords as otherwise it would have been removed as a no-op.
21381 if (Mask[0] == 2 && Mask[1] == 3 && Mask[2] == 0 && Mask[3] == 1) {
21382 int DMask[] = {0, 1, 2, 3};
21383 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
21384 DMask[DOffset + 0] = DOffset + 1;
21385 DMask[DOffset + 1] = DOffset + 0;
21386 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
21387 DCI.AddToWorklist(V.getNode());
21388 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
21389 getV4X86ShuffleImm8ForMask(DMask, DAG));
21390 DCI.AddToWorklist(V.getNode());
21391 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
21392 }
21394 // Look for shuffle patterns which can be implemented as a single unpack.
21395 // FIXME: This doesn't handle the location of the PSHUFD generically, and
21396 // only works when we have a PSHUFD followed by two half-shuffles.
21397 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
21398 (V.getOpcode() == X86ISD::PSHUFLW ||
21399 V.getOpcode() == X86ISD::PSHUFHW) &&
21400 V.getOpcode() != N.getOpcode() &&
21401 V.hasOneUse()) {
21402 SDValue D = V.getOperand(0);
21403 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
21404 D = D.getOperand(0);
21405 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
21406 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21407 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
21408 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21409 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21410 int WordMask[8];
21411 for (int i = 0; i < 4; ++i) {
21412 WordMask[i + NOffset] = Mask[i] + NOffset;
21413 WordMask[i + VOffset] = VMask[i] + VOffset;
21414 }
21415 // Map the word mask through the DWord mask.
21416 int MappedMask[8];
21417 for (int i = 0; i < 8; ++i)
21418 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
21419 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
21420 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
21421 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
21422 std::begin(UnpackLoMask)) ||
21423 std::equal(std::begin(MappedMask), std::end(MappedMask),
21424 std::begin(UnpackHiMask))) {
21425 // We can replace all three shuffles with an unpack.
21426 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
21427 DCI.AddToWorklist(V.getNode());
21428 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
21429 : X86ISD::UNPCKH,
21430 DL, MVT::v8i16, V, V);
21431 }
21432 }
21433 }
21435 break;
21437 case X86ISD::PSHUFD:
21438 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
21439 return NewN;
21441 break;
21442 }
21444 return SDValue();
21445 }
21447 /// \brief Try to combine a shuffle into a target-specific add-sub node.
21448 ///
21449 /// We combine this directly on the abstract vector shuffle nodes so it is
21450 /// easier to generically match. We also insert dummy vector shuffle nodes for
21451 /// the operands which explicitly discard the lanes which are unused by this
21452 /// operation to try to flow through the rest of the combiner the fact that
21453 /// they're unused.
21454 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
21455 SDLoc DL(N);
21456 EVT VT = N->getValueType(0);
21458 // We only handle target-independent shuffles.
21459 // FIXME: It would be easy and harmless to use the target shuffle mask
21460 // extraction tool to support more.
21461 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
21462 return SDValue();
21464 auto *SVN = cast<ShuffleVectorSDNode>(N);
21465 ArrayRef<int> Mask = SVN->getMask();
21466 SDValue V1 = N->getOperand(0);
21467 SDValue V2 = N->getOperand(1);
21469 // We require the first shuffle operand to be the SUB node, and the second to
21470 // be the ADD node.
21471 // FIXME: We should support the commuted patterns.
21472 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
21473 return SDValue();
21475 // If there are other uses of these operations we can't fold them.
21476 if (!V1->hasOneUse() || !V2->hasOneUse())
21477 return SDValue();
21479 // Ensure that both operations have the same operands. Note that we can
21480 // commute the FADD operands.
21481 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
21482 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
21483 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
21484 return SDValue();
21486 // We're looking for blends between FADD and FSUB nodes. We insist on these
21487 // nodes being lined up in a specific expected pattern.
21488 if (!(isShuffleEquivalent(Mask, 0, 3) ||
21489 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
21490 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
21491 return SDValue();
21493 // Only specific types are legal at this point, assert so we notice if and
21494 // when these change.
21495 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
21496 VT == MVT::v4f64) &&
21497 "Unknown vector type encountered!");
21499 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
21500 }
21502 /// PerformShuffleCombine - Performs several different shuffle combines.
21503 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
21504 TargetLowering::DAGCombinerInfo &DCI,
21505 const X86Subtarget *Subtarget) {
21506 SDLoc dl(N);
21507 SDValue N0 = N->getOperand(0);
21508 SDValue N1 = N->getOperand(1);
21509 EVT VT = N->getValueType(0);
21511 // Don't create instructions with illegal types after legalize types has run.
21512 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21513 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
21514 return SDValue();
21516 // If we have legalized the vector types, look for blends of FADD and FSUB
21517 // nodes that we can fuse into an ADDSUB node.
21518 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
21519 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
21520 return AddSub;
21522 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
21523 if (Subtarget->hasFp256() && VT.is256BitVector() &&
21524 N->getOpcode() == ISD::VECTOR_SHUFFLE)
21525 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
21527 // During Type Legalization, when promoting illegal vector types,
21528 // the backend might introduce new shuffle dag nodes and bitcasts.
21529 //
21530 // This code performs the following transformation:
21531 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
21532 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
21533 //
21534 // We do this only if both the bitcast and the BINOP dag nodes have
21535 // one use. Also, perform this transformation only if the new binary
21536 // operation is legal. This is to avoid introducing dag nodes that
21537 // potentially need to be further expanded (or custom lowered) into a
21538 // less optimal sequence of dag nodes.
21539 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
21540 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
21541 N0.getOpcode() == ISD::BITCAST) {
21542 SDValue BC0 = N0.getOperand(0);
21543 EVT SVT = BC0.getValueType();
21544 unsigned Opcode = BC0.getOpcode();
21545 unsigned NumElts = VT.getVectorNumElements();
21547 if (BC0.hasOneUse() && SVT.isVector() &&
21548 SVT.getVectorNumElements() * 2 == NumElts &&
21549 TLI.isOperationLegal(Opcode, VT)) {
21550 bool CanFold = false;
21551 switch (Opcode) {
21552 default : break;
21553 case ISD::ADD :
21554 case ISD::FADD :
21555 case ISD::SUB :
21556 case ISD::FSUB :
21557 case ISD::MUL :
21558 case ISD::FMUL :
21559 CanFold = true;
21560 }
21562 unsigned SVTNumElts = SVT.getVectorNumElements();
21563 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21564 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
21565 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
21566 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
21567 CanFold = SVOp->getMaskElt(i) < 0;
21569 if (CanFold) {
21570 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
21571 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
21572 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
21573 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
21574 }
21575 }
21576 }
21578 // Only handle 128 wide vector from here on.
21579 if (!VT.is128BitVector())
21580 return SDValue();
21582 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
21583 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
21584 // consecutive, non-overlapping, and in the right order.
21585 SmallVector<SDValue, 16> Elts;
21586 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
21587 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
21589 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
21590 if (LD.getNode())
21591 return LD;
21593 if (isTargetShuffle(N->getOpcode())) {
21594 SDValue Shuffle =
21595 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
21596 if (Shuffle.getNode())
21597 return Shuffle;
21599 // Try recursively combining arbitrary sequences of x86 shuffle
21600 // instructions into higher-order shuffles. We do this after combining
21601 // specific PSHUF instruction sequences into their minimal form so that we
21602 // can evaluate how many specialized shuffle instructions are involved in
21603 // a particular chain.
21604 SmallVector<int, 1> NonceMask; // Just a placeholder.
21605 NonceMask.push_back(0);
21606 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
21607 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
21608 DCI, Subtarget))
21609 return SDValue(); // This routine will use CombineTo to replace N.
21610 }
21612 return SDValue();
21613 }
21615 /// PerformTruncateCombine - Converts truncate operation to
21616 /// a sequence of vector shuffle operations.
21617 /// It is possible when we truncate 256-bit vector to 128-bit vector
21618 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
21619 TargetLowering::DAGCombinerInfo &DCI,
21620 const X86Subtarget *Subtarget) {
21621 return SDValue();
21622 }
21624 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
21625 /// specific shuffle of a load can be folded into a single element load.
21626 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
21627 /// shuffles have been customed lowered so we need to handle those here.
21628 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
21629 TargetLowering::DAGCombinerInfo &DCI) {
21630 if (DCI.isBeforeLegalizeOps())
21631 return SDValue();
21633 SDValue InVec = N->getOperand(0);
21634 SDValue EltNo = N->getOperand(1);
21636 if (!isa<ConstantSDNode>(EltNo))
21637 return SDValue();
21639 EVT VT = InVec.getValueType();
21641 if (InVec.getOpcode() == ISD::BITCAST) {
21642 // Don't duplicate a load with other uses.
21643 if (!InVec.hasOneUse())
21644 return SDValue();
21645 EVT BCVT = InVec.getOperand(0).getValueType();
21646 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
21647 return SDValue();
21648 InVec = InVec.getOperand(0);
21649 }
21651 if (!isTargetShuffle(InVec.getOpcode()))
21652 return SDValue();
21654 // Don't duplicate a load with other uses.
21655 if (!InVec.hasOneUse())
21656 return SDValue();
21658 SmallVector<int, 16> ShuffleMask;
21659 bool UnaryShuffle;
21660 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
21661 UnaryShuffle))
21662 return SDValue();
21664 // Select the input vector, guarding against out of range extract vector.
21665 unsigned NumElems = VT.getVectorNumElements();
21666 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
21667 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
21668 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
21669 : InVec.getOperand(1);
21671 // If inputs to shuffle are the same for both ops, then allow 2 uses
21672 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
21674 if (LdNode.getOpcode() == ISD::BITCAST) {
21675 // Don't duplicate a load with other uses.
21676 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
21677 return SDValue();
21679 AllowedUses = 1; // only allow 1 load use if we have a bitcast
21680 LdNode = LdNode.getOperand(0);
21681 }
21683 if (!ISD::isNormalLoad(LdNode.getNode()))
21684 return SDValue();
21686 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
21688 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
21689 return SDValue();
21691 EVT EltVT = N->getValueType(0);
21692 // If there's a bitcast before the shuffle, check if the load type and
21693 // alignment is valid.
21694 unsigned Align = LN0->getAlignment();
21695 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21696 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
21697 EltVT.getTypeForEVT(*DAG.getContext()));
21699 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
21700 return SDValue();
21702 // All checks match so transform back to vector_shuffle so that DAG combiner
21703 // can finish the job
21704 SDLoc dl(N);
21706 // Create shuffle node taking into account the case that its a unary shuffle
21707 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
21708 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
21709 InVec.getOperand(0), Shuffle,
21710 &ShuffleMask[0]);
21711 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
21712 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
21713 EltNo);
21714 }
21716 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
21717 /// generation and convert it from being a bunch of shuffles and extracts
21718 /// to a simple store and scalar loads to extract the elements.
21719 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
21720 TargetLowering::DAGCombinerInfo &DCI) {
21721 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
21722 if (NewOp.getNode())
21723 return NewOp;
21725 SDValue InputVector = N->getOperand(0);
21727 // Detect whether we are trying to convert from mmx to i32 and the bitcast
21728 // from mmx to v2i32 has a single usage.
21729 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
21730 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
21731 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
21732 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
21733 N->getValueType(0),
21734 InputVector.getNode()->getOperand(0));
21736 // Only operate on vectors of 4 elements, where the alternative shuffling
21737 // gets to be more expensive.
21738 if (InputVector.getValueType() != MVT::v4i32)
21739 return SDValue();
21741 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
21742 // single use which is a sign-extend or zero-extend, and all elements are
21743 // used.
21744 SmallVector<SDNode *, 4> Uses;
21745 unsigned ExtractedElements = 0;
21746 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
21747 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
21748 if (UI.getUse().getResNo() != InputVector.getResNo())
21749 return SDValue();
21751 SDNode *Extract = *UI;
21752 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
21753 return SDValue();
21755 if (Extract->getValueType(0) != MVT::i32)
21756 return SDValue();
21757 if (!Extract->hasOneUse())
21758 return SDValue();
21759 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
21760 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
21761 return SDValue();
21762 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
21763 return SDValue();
21765 // Record which element was extracted.
21766 ExtractedElements |=
21767 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
21769 Uses.push_back(Extract);
21770 }
21772 // If not all the elements were used, this may not be worthwhile.
21773 if (ExtractedElements != 15)
21774 return SDValue();
21776 // Ok, we've now decided to do the transformation.
21777 SDLoc dl(InputVector);
21779 // Store the value to a temporary stack slot.
21780 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
21781 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
21782 MachinePointerInfo(), false, false, 0);
21784 // Replace each use (extract) with a load of the appropriate element.
21785 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
21786 UE = Uses.end(); UI != UE; ++UI) {
21787 SDNode *Extract = *UI;
21789 // cOMpute the element's address.
21790 SDValue Idx = Extract->getOperand(1);
21791 unsigned EltSize =
21792 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
21793 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
21794 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21795 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
21797 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
21798 StackPtr, OffsetVal);
21800 // Load the scalar.
21801 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
21802 ScalarAddr, MachinePointerInfo(),
21803 false, false, false, 0);
21805 // Replace the exact with the load.
21806 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
21807 }
21809 // The replacement was made in place; don't return anything.
21810 return SDValue();
21811 }
21813 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
21814 static std::pair<unsigned, bool>
21815 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
21816 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
21817 if (!VT.isVector())
21818 return std::make_pair(0, false);
21820 bool NeedSplit = false;
21821 switch (VT.getSimpleVT().SimpleTy) {
21822 default: return std::make_pair(0, false);
21823 case MVT::v32i8:
21824 case MVT::v16i16:
21825 case MVT::v8i32:
21826 if (!Subtarget->hasAVX2())
21827 NeedSplit = true;
21828 if (!Subtarget->hasAVX())
21829 return std::make_pair(0, false);
21830 break;
21831 case MVT::v16i8:
21832 case MVT::v8i16:
21833 case MVT::v4i32:
21834 if (!Subtarget->hasSSE2())
21835 return std::make_pair(0, false);
21836 }
21838 // SSE2 has only a small subset of the operations.
21839 bool hasUnsigned = Subtarget->hasSSE41() ||
21840 (Subtarget->hasSSE2() && VT == MVT::v16i8);
21841 bool hasSigned = Subtarget->hasSSE41() ||
21842 (Subtarget->hasSSE2() && VT == MVT::v8i16);
21844 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21846 unsigned Opc = 0;
21847 // Check for x CC y ? x : y.
21848 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21849 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21850 switch (CC) {
21851 default: break;
21852 case ISD::SETULT:
21853 case ISD::SETULE:
21854 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
21855 case ISD::SETUGT:
21856 case ISD::SETUGE:
21857 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
21858 case ISD::SETLT:
21859 case ISD::SETLE:
21860 Opc = hasSigned ? X86ISD::SMIN : 0; break;
21861 case ISD::SETGT:
21862 case ISD::SETGE:
21863 Opc = hasSigned ? X86ISD::SMAX : 0; break;
21864 }
21865 // Check for x CC y ? y : x -- a min/max with reversed arms.
21866 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21867 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21868 switch (CC) {
21869 default: break;
21870 case ISD::SETULT:
21871 case ISD::SETULE:
21872 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
21873 case ISD::SETUGT:
21874 case ISD::SETUGE:
21875 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
21876 case ISD::SETLT:
21877 case ISD::SETLE:
21878 Opc = hasSigned ? X86ISD::SMAX : 0; break;
21879 case ISD::SETGT:
21880 case ISD::SETGE:
21881 Opc = hasSigned ? X86ISD::SMIN : 0; break;
21882 }
21883 }
21885 return std::make_pair(Opc, NeedSplit);
21886 }
21888 static SDValue
21889 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
21890 const X86Subtarget *Subtarget) {
21891 SDLoc dl(N);
21892 SDValue Cond = N->getOperand(0);
21893 SDValue LHS = N->getOperand(1);
21894 SDValue RHS = N->getOperand(2);
21896 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
21897 SDValue CondSrc = Cond->getOperand(0);
21898 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
21899 Cond = CondSrc->getOperand(0);
21900 }
21902 MVT VT = N->getSimpleValueType(0);
21903 MVT EltVT = VT.getVectorElementType();
21904 unsigned NumElems = VT.getVectorNumElements();
21905 // There is no blend with immediate in AVX-512.
21906 if (VT.is512BitVector())
21907 return SDValue();
21909 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
21910 return SDValue();
21911 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
21912 return SDValue();
21914 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
21915 return SDValue();
21917 // A vselect where all conditions and data are constants can be optimized into
21918 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
21919 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
21920 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
21921 return SDValue();
21923 unsigned MaskValue = 0;
21924 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
21925 return SDValue();
21927 SmallVector<int, 8> ShuffleMask(NumElems, -1);
21928 for (unsigned i = 0; i < NumElems; ++i) {
21929 // Be sure we emit undef where we can.
21930 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
21931 ShuffleMask[i] = -1;
21932 else
21933 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
21934 }
21936 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
21937 }
21939 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
21940 /// nodes.
21941 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
21942 TargetLowering::DAGCombinerInfo &DCI,
21943 const X86Subtarget *Subtarget) {
21944 SDLoc DL(N);
21945 SDValue Cond = N->getOperand(0);
21946 // Get the LHS/RHS of the select.
21947 SDValue LHS = N->getOperand(1);
21948 SDValue RHS = N->getOperand(2);
21949 EVT VT = LHS.getValueType();
21950 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21952 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
21953 // instructions match the semantics of the common C idiom x<y?x:y but not
21954 // x<=y?x:y, because of how they handle negative zero (which can be
21955 // ignored in unsafe-math mode).
21956 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
21957 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
21958 (Subtarget->hasSSE2() ||
21959 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
21960 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21962 unsigned Opcode = 0;
21963 // Check for x CC y ? x : y.
21964 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21965 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21966 switch (CC) {
21967 default: break;
21968 case ISD::SETULT:
21969 // Converting this to a min would handle NaNs incorrectly, and swapping
21970 // the operands would cause it to handle comparisons between positive
21971 // and negative zero incorrectly.
21972 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21973 if (!DAG.getTarget().Options.UnsafeFPMath &&
21974 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21975 break;
21976 std::swap(LHS, RHS);
21977 }
21978 Opcode = X86ISD::FMIN;
21979 break;
21980 case ISD::SETOLE:
21981 // Converting this to a min would handle comparisons between positive
21982 // and negative zero incorrectly.
21983 if (!DAG.getTarget().Options.UnsafeFPMath &&
21984 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21985 break;
21986 Opcode = X86ISD::FMIN;
21987 break;
21988 case ISD::SETULE:
21989 // Converting this to a min would handle both negative zeros and NaNs
21990 // incorrectly, but we can swap the operands to fix both.
21991 std::swap(LHS, RHS);
21992 case ISD::SETOLT:
21993 case ISD::SETLT:
21994 case ISD::SETLE:
21995 Opcode = X86ISD::FMIN;
21996 break;
21998 case ISD::SETOGE:
21999 // Converting this to a max would handle comparisons between positive
22000 // and negative zero incorrectly.
22001 if (!DAG.getTarget().Options.UnsafeFPMath &&
22002 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22003 break;
22004 Opcode = X86ISD::FMAX;
22005 break;
22006 case ISD::SETUGT:
22007 // Converting this to a max would handle NaNs incorrectly, and swapping
22008 // the operands would cause it to handle comparisons between positive
22009 // and negative zero incorrectly.
22010 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22011 if (!DAG.getTarget().Options.UnsafeFPMath &&
22012 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22013 break;
22014 std::swap(LHS, RHS);
22015 }
22016 Opcode = X86ISD::FMAX;
22017 break;
22018 case ISD::SETUGE:
22019 // Converting this to a max would handle both negative zeros and NaNs
22020 // incorrectly, but we can swap the operands to fix both.
22021 std::swap(LHS, RHS);
22022 case ISD::SETOGT:
22023 case ISD::SETGT:
22024 case ISD::SETGE:
22025 Opcode = X86ISD::FMAX;
22026 break;
22027 }
22028 // Check for x CC y ? y : x -- a min/max with reversed arms.
22029 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22030 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22031 switch (CC) {
22032 default: break;
22033 case ISD::SETOGE:
22034 // Converting this to a min would handle comparisons between positive
22035 // and negative zero incorrectly, and swapping the operands would
22036 // cause it to handle NaNs incorrectly.
22037 if (!DAG.getTarget().Options.UnsafeFPMath &&
22038 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
22039 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22040 break;
22041 std::swap(LHS, RHS);
22042 }
22043 Opcode = X86ISD::FMIN;
22044 break;
22045 case ISD::SETUGT:
22046 // Converting this to a min would handle NaNs incorrectly.
22047 if (!DAG.getTarget().Options.UnsafeFPMath &&
22048 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
22049 break;
22050 Opcode = X86ISD::FMIN;
22051 break;
22052 case ISD::SETUGE:
22053 // Converting this to a min would handle both negative zeros and NaNs
22054 // incorrectly, but we can swap the operands to fix both.
22055 std::swap(LHS, RHS);
22056 case ISD::SETOGT:
22057 case ISD::SETGT:
22058 case ISD::SETGE:
22059 Opcode = X86ISD::FMIN;
22060 break;
22062 case ISD::SETULT:
22063 // Converting this to a max would handle NaNs incorrectly.
22064 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22065 break;
22066 Opcode = X86ISD::FMAX;
22067 break;
22068 case ISD::SETOLE:
22069 // Converting this to a max would handle comparisons between positive
22070 // and negative zero incorrectly, and swapping the operands would
22071 // cause it to handle NaNs incorrectly.
22072 if (!DAG.getTarget().Options.UnsafeFPMath &&
22073 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
22074 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22075 break;
22076 std::swap(LHS, RHS);
22077 }
22078 Opcode = X86ISD::FMAX;
22079 break;
22080 case ISD::SETULE:
22081 // Converting this to a max would handle both negative zeros and NaNs
22082 // incorrectly, but we can swap the operands to fix both.
22083 std::swap(LHS, RHS);
22084 case ISD::SETOLT:
22085 case ISD::SETLT:
22086 case ISD::SETLE:
22087 Opcode = X86ISD::FMAX;
22088 break;
22089 }
22090 }
22092 if (Opcode)
22093 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
22094 }
22096 EVT CondVT = Cond.getValueType();
22097 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
22098 CondVT.getVectorElementType() == MVT::i1) {
22099 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
22100 // lowering on KNL. In this case we convert it to
22101 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
22102 // The same situation for all 128 and 256-bit vectors of i8 and i16.
22103 // Since SKX these selects have a proper lowering.
22104 EVT OpVT = LHS.getValueType();
22105 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
22106 (OpVT.getVectorElementType() == MVT::i8 ||
22107 OpVT.getVectorElementType() == MVT::i16) &&
22108 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
22109 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
22110 DCI.AddToWorklist(Cond.getNode());
22111 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
22112 }
22113 }
22114 // If this is a select between two integer constants, try to do some
22115 // optimizations.
22116 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
22117 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
22118 // Don't do this for crazy integer types.
22119 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
22120 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
22121 // so that TrueC (the true value) is larger than FalseC.
22122 bool NeedsCondInvert = false;
22124 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
22125 // Efficiently invertible.
22126 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
22127 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
22128 isa<ConstantSDNode>(Cond.getOperand(1))))) {
22129 NeedsCondInvert = true;
22130 std::swap(TrueC, FalseC);
22131 }
22133 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
22134 if (FalseC->getAPIntValue() == 0 &&
22135 TrueC->getAPIntValue().isPowerOf2()) {
22136 if (NeedsCondInvert) // Invert the condition if needed.
22137 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22138 DAG.getConstant(1, Cond.getValueType()));
22140 // Zero extend the condition if needed.
22141 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
22143 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22144 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
22145 DAG.getConstant(ShAmt, MVT::i8));
22146 }
22148 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
22149 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22150 if (NeedsCondInvert) // Invert the condition if needed.
22151 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22152 DAG.getConstant(1, Cond.getValueType()));
22154 // Zero extend the condition if needed.
22155 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22156 FalseC->getValueType(0), Cond);
22157 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22158 SDValue(FalseC, 0));
22159 }
22161 // Optimize cases that will turn into an LEA instruction. This requires
22162 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22163 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22164 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22165 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22167 bool isFastMultiplier = false;
22168 if (Diff < 10) {
22169 switch ((unsigned char)Diff) {
22170 default: break;
22171 case 1: // result = add base, cond
22172 case 2: // result = lea base( , cond*2)
22173 case 3: // result = lea base(cond, cond*2)
22174 case 4: // result = lea base( , cond*4)
22175 case 5: // result = lea base(cond, cond*4)
22176 case 8: // result = lea base( , cond*8)
22177 case 9: // result = lea base(cond, cond*8)
22178 isFastMultiplier = true;
22179 break;
22180 }
22181 }
22183 if (isFastMultiplier) {
22184 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22185 if (NeedsCondInvert) // Invert the condition if needed.
22186 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22187 DAG.getConstant(1, Cond.getValueType()));
22189 // Zero extend the condition if needed.
22190 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22191 Cond);
22192 // Scale the condition by the difference.
22193 if (Diff != 1)
22194 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22195 DAG.getConstant(Diff, Cond.getValueType()));
22197 // Add the base if non-zero.
22198 if (FalseC->getAPIntValue() != 0)
22199 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22200 SDValue(FalseC, 0));
22201 return Cond;
22202 }
22203 }
22204 }
22205 }
22207 // Canonicalize max and min:
22208 // (x > y) ? x : y -> (x >= y) ? x : y
22209 // (x < y) ? x : y -> (x <= y) ? x : y
22210 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
22211 // the need for an extra compare
22212 // against zero. e.g.
22213 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
22214 // subl %esi, %edi
22215 // testl %edi, %edi
22216 // movl $0, %eax
22217 // cmovgl %edi, %eax
22218 // =>
22219 // xorl %eax, %eax
22220 // subl %esi, $edi
22221 // cmovsl %eax, %edi
22222 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
22223 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22224 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22225 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22226 switch (CC) {
22227 default: break;
22228 case ISD::SETLT:
22229 case ISD::SETGT: {
22230 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
22231 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
22232 Cond.getOperand(0), Cond.getOperand(1), NewCC);
22233 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
22234 }
22235 }
22236 }
22238 // Early exit check
22239 if (!TLI.isTypeLegal(VT))
22240 return SDValue();
22242 // Match VSELECTs into subs with unsigned saturation.
22243 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
22244 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
22245 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
22246 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
22247 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22249 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
22250 // left side invert the predicate to simplify logic below.
22251 SDValue Other;
22252 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
22253 Other = RHS;
22254 CC = ISD::getSetCCInverse(CC, true);
22255 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
22256 Other = LHS;
22257 }
22259 if (Other.getNode() && Other->getNumOperands() == 2 &&
22260 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
22261 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
22262 SDValue CondRHS = Cond->getOperand(1);
22264 // Look for a general sub with unsigned saturation first.
22265 // x >= y ? x-y : 0 --> subus x, y
22266 // x > y ? x-y : 0 --> subus x, y
22267 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
22268 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
22269 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
22271 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
22272 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
22273 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
22274 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
22275 // If the RHS is a constant we have to reverse the const
22276 // canonicalization.
22277 // x > C-1 ? x+-C : 0 --> subus x, C
22278 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
22279 CondRHSConst->getAPIntValue() ==
22280 (-OpRHSConst->getAPIntValue() - 1))
22281 return DAG.getNode(
22282 X86ISD::SUBUS, DL, VT, OpLHS,
22283 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
22285 // Another special case: If C was a sign bit, the sub has been
22286 // canonicalized into a xor.
22287 // FIXME: Would it be better to use computeKnownBits to determine
22288 // whether it's safe to decanonicalize the xor?
22289 // x s< 0 ? x^C : 0 --> subus x, C
22290 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
22291 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
22292 OpRHSConst->getAPIntValue().isSignBit())
22293 // Note that we have to rebuild the RHS constant here to ensure we
22294 // don't rely on particular values of undef lanes.
22295 return DAG.getNode(
22296 X86ISD::SUBUS, DL, VT, OpLHS,
22297 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
22298 }
22299 }
22300 }
22302 // Try to match a min/max vector operation.
22303 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
22304 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
22305 unsigned Opc = ret.first;
22306 bool NeedSplit = ret.second;
22308 if (Opc && NeedSplit) {
22309 unsigned NumElems = VT.getVectorNumElements();
22310 // Extract the LHS vectors
22311 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
22312 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
22314 // Extract the RHS vectors
22315 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
22316 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
22318 // Create min/max for each subvector
22319 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
22320 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
22322 // Merge the result
22323 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
22324 } else if (Opc)
22325 return DAG.getNode(Opc, DL, VT, LHS, RHS);
22326 }
22328 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
22329 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
22330 // Check if SETCC has already been promoted
22331 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
22332 // Check that condition value type matches vselect operand type
22333 CondVT == VT) {
22335 assert(Cond.getValueType().isVector() &&
22336 "vector select expects a vector selector!");
22338 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
22339 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
22341 if (!TValIsAllOnes && !FValIsAllZeros) {
22342 // Try invert the condition if true value is not all 1s and false value
22343 // is not all 0s.
22344 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
22345 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
22347 if (TValIsAllZeros || FValIsAllOnes) {
22348 SDValue CC = Cond.getOperand(2);
22349 ISD::CondCode NewCC =
22350 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
22351 Cond.getOperand(0).getValueType().isInteger());
22352 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
22353 std::swap(LHS, RHS);
22354 TValIsAllOnes = FValIsAllOnes;
22355 FValIsAllZeros = TValIsAllZeros;
22356 }
22357 }
22359 if (TValIsAllOnes || FValIsAllZeros) {
22360 SDValue Ret;
22362 if (TValIsAllOnes && FValIsAllZeros)
22363 Ret = Cond;
22364 else if (TValIsAllOnes)
22365 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
22366 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
22367 else if (FValIsAllZeros)
22368 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
22369 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
22371 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
22372 }
22373 }
22375 // Try to fold this VSELECT into a MOVSS/MOVSD
22376 if (N->getOpcode() == ISD::VSELECT &&
22377 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
22378 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
22379 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
22380 bool CanFold = false;
22381 unsigned NumElems = Cond.getNumOperands();
22382 SDValue A = LHS;
22383 SDValue B = RHS;
22385 if (isZero(Cond.getOperand(0))) {
22386 CanFold = true;
22388 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
22389 // fold (vselect <0,-1> -> (movsd A, B)
22390 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
22391 CanFold = isAllOnes(Cond.getOperand(i));
22392 } else if (isAllOnes(Cond.getOperand(0))) {
22393 CanFold = true;
22394 std::swap(A, B);
22396 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
22397 // fold (vselect <-1,0> -> (movsd B, A)
22398 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
22399 CanFold = isZero(Cond.getOperand(i));
22400 }
22402 if (CanFold) {
22403 if (VT == MVT::v4i32 || VT == MVT::v4f32)
22404 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
22405 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
22406 }
22408 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
22409 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
22410 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
22411 // (v2i64 (bitcast B)))))
22412 //
22413 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
22414 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
22415 // (v2f64 (bitcast B)))))
22416 //
22417 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
22418 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
22419 // (v2i64 (bitcast A)))))
22420 //
22421 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
22422 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
22423 // (v2f64 (bitcast A)))))
22425 CanFold = (isZero(Cond.getOperand(0)) &&
22426 isZero(Cond.getOperand(1)) &&
22427 isAllOnes(Cond.getOperand(2)) &&
22428 isAllOnes(Cond.getOperand(3)));
22430 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
22431 isAllOnes(Cond.getOperand(1)) &&
22432 isZero(Cond.getOperand(2)) &&
22433 isZero(Cond.getOperand(3))) {
22434 CanFold = true;
22435 std::swap(LHS, RHS);
22436 }
22438 if (CanFold) {
22439 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
22440 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
22441 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
22442 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
22443 NewB, DAG);
22444 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
22445 }
22446 }
22447 }
22448 }
22450 // If we know that this node is legal then we know that it is going to be
22451 // matched by one of the SSE/AVX BLEND instructions. These instructions only
22452 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
22453 // to simplify previous instructions.
22454 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
22455 !DCI.isBeforeLegalize() &&
22456 // We explicitly check against v8i16 and v16i16 because, although
22457 // they're marked as Custom, they might only be legal when Cond is a
22458 // build_vector of constants. This will be taken care in a later
22459 // condition.
22460 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
22461 VT != MVT::v8i16)) {
22462 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
22464 // Don't optimize vector selects that map to mask-registers.
22465 if (BitWidth == 1)
22466 return SDValue();
22468 // Check all uses of that condition operand to check whether it will be
22469 // consumed by non-BLEND instructions, which may depend on all bits are set
22470 // properly.
22471 for (SDNode::use_iterator I = Cond->use_begin(),
22472 E = Cond->use_end(); I != E; ++I)
22473 if (I->getOpcode() != ISD::VSELECT)
22474 // TODO: Add other opcodes eventually lowered into BLEND.
22475 return SDValue();
22477 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
22478 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
22480 APInt KnownZero, KnownOne;
22481 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
22482 DCI.isBeforeLegalizeOps());
22483 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
22484 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
22485 DCI.CommitTargetLoweringOpt(TLO);
22486 }
22488 // We should generate an X86ISD::BLENDI from a vselect if its argument
22489 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
22490 // constants. This specific pattern gets generated when we split a
22491 // selector for a 512 bit vector in a machine without AVX512 (but with
22492 // 256-bit vectors), during legalization:
22493 //
22494 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
22495 //
22496 // Iff we find this pattern and the build_vectors are built from
22497 // constants, we translate the vselect into a shuffle_vector that we
22498 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
22499 if (N->getOpcode() == ISD::VSELECT && !DCI.isBeforeLegalize()) {
22500 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
22501 if (Shuffle.getNode())
22502 return Shuffle;
22503 }
22505 return SDValue();
22506 }
22508 // Check whether a boolean test is testing a boolean value generated by
22509 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
22510 // code.
22511 //
22512 // Simplify the following patterns:
22513 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
22514 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
22515 // to (Op EFLAGS Cond)
22516 //
22517 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
22518 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
22519 // to (Op EFLAGS !Cond)
22520 //
22521 // where Op could be BRCOND or CMOV.
22522 //
22523 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
22524 // Quit if not CMP and SUB with its value result used.
22525 if (Cmp.getOpcode() != X86ISD::CMP &&
22526 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
22527 return SDValue();
22529 // Quit if not used as a boolean value.
22530 if (CC != X86::COND_E && CC != X86::COND_NE)
22531 return SDValue();
22533 // Check CMP operands. One of them should be 0 or 1 and the other should be
22534 // an SetCC or extended from it.
22535 SDValue Op1 = Cmp.getOperand(0);
22536 SDValue Op2 = Cmp.getOperand(1);
22538 SDValue SetCC;
22539 const ConstantSDNode* C = nullptr;
22540 bool needOppositeCond = (CC == X86::COND_E);
22541 bool checkAgainstTrue = false; // Is it a comparison against 1?
22543 if ((C = dyn_cast<ConstantSDNode>(Op1)))
22544 SetCC = Op2;
22545 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
22546 SetCC = Op1;
22547 else // Quit if all operands are not constants.
22548 return SDValue();
22550 if (C->getZExtValue() == 1) {
22551 needOppositeCond = !needOppositeCond;
22552 checkAgainstTrue = true;
22553 } else if (C->getZExtValue() != 0)
22554 // Quit if the constant is neither 0 or 1.
22555 return SDValue();
22557 bool truncatedToBoolWithAnd = false;
22558 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
22559 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
22560 SetCC.getOpcode() == ISD::TRUNCATE ||
22561 SetCC.getOpcode() == ISD::AND) {
22562 if (SetCC.getOpcode() == ISD::AND) {
22563 int OpIdx = -1;
22564 ConstantSDNode *CS;
22565 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
22566 CS->getZExtValue() == 1)
22567 OpIdx = 1;
22568 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
22569 CS->getZExtValue() == 1)
22570 OpIdx = 0;
22571 if (OpIdx == -1)
22572 break;
22573 SetCC = SetCC.getOperand(OpIdx);
22574 truncatedToBoolWithAnd = true;
22575 } else
22576 SetCC = SetCC.getOperand(0);
22577 }
22579 switch (SetCC.getOpcode()) {
22580 case X86ISD::SETCC_CARRY:
22581 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
22582 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
22583 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
22584 // truncated to i1 using 'and'.
22585 if (checkAgainstTrue && !truncatedToBoolWithAnd)
22586 break;
22587 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
22588 "Invalid use of SETCC_CARRY!");
22589 // FALL THROUGH
22590 case X86ISD::SETCC:
22591 // Set the condition code or opposite one if necessary.
22592 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
22593 if (needOppositeCond)
22594 CC = X86::GetOppositeBranchCondition(CC);
22595 return SetCC.getOperand(1);
22596 case X86ISD::CMOV: {
22597 // Check whether false/true value has canonical one, i.e. 0 or 1.
22598 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
22599 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
22600 // Quit if true value is not a constant.
22601 if (!TVal)
22602 return SDValue();
22603 // Quit if false value is not a constant.
22604 if (!FVal) {
22605 SDValue Op = SetCC.getOperand(0);
22606 // Skip 'zext' or 'trunc' node.
22607 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
22608 Op.getOpcode() == ISD::TRUNCATE)
22609 Op = Op.getOperand(0);
22610 // A special case for rdrand/rdseed, where 0 is set if false cond is
22611 // found.
22612 if ((Op.getOpcode() != X86ISD::RDRAND &&
22613 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
22614 return SDValue();
22615 }
22616 // Quit if false value is not the constant 0 or 1.
22617 bool FValIsFalse = true;
22618 if (FVal && FVal->getZExtValue() != 0) {
22619 if (FVal->getZExtValue() != 1)
22620 return SDValue();
22621 // If FVal is 1, opposite cond is needed.
22622 needOppositeCond = !needOppositeCond;
22623 FValIsFalse = false;
22624 }
22625 // Quit if TVal is not the constant opposite of FVal.
22626 if (FValIsFalse && TVal->getZExtValue() != 1)
22627 return SDValue();
22628 if (!FValIsFalse && TVal->getZExtValue() != 0)
22629 return SDValue();
22630 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
22631 if (needOppositeCond)
22632 CC = X86::GetOppositeBranchCondition(CC);
22633 return SetCC.getOperand(3);
22634 }
22635 }
22637 return SDValue();
22638 }
22640 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
22641 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
22642 TargetLowering::DAGCombinerInfo &DCI,
22643 const X86Subtarget *Subtarget) {
22644 SDLoc DL(N);
22646 // If the flag operand isn't dead, don't touch this CMOV.
22647 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
22648 return SDValue();
22650 SDValue FalseOp = N->getOperand(0);
22651 SDValue TrueOp = N->getOperand(1);
22652 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
22653 SDValue Cond = N->getOperand(3);
22655 if (CC == X86::COND_E || CC == X86::COND_NE) {
22656 switch (Cond.getOpcode()) {
22657 default: break;
22658 case X86ISD::BSR:
22659 case X86ISD::BSF:
22660 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
22661 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
22662 return (CC == X86::COND_E) ? FalseOp : TrueOp;
22663 }
22664 }
22666 SDValue Flags;
22668 Flags = checkBoolTestSetCCCombine(Cond, CC);
22669 if (Flags.getNode() &&
22670 // Extra check as FCMOV only supports a subset of X86 cond.
22671 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
22672 SDValue Ops[] = { FalseOp, TrueOp,
22673 DAG.getConstant(CC, MVT::i8), Flags };
22674 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
22675 }
22677 // If this is a select between two integer constants, try to do some
22678 // optimizations. Note that the operands are ordered the opposite of SELECT
22679 // operands.
22680 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
22681 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
22682 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
22683 // larger than FalseC (the false value).
22684 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
22685 CC = X86::GetOppositeBranchCondition(CC);
22686 std::swap(TrueC, FalseC);
22687 std::swap(TrueOp, FalseOp);
22688 }
22690 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
22691 // This is efficient for any integer data type (including i8/i16) and
22692 // shift amount.
22693 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
22694 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22695 DAG.getConstant(CC, MVT::i8), Cond);
22697 // Zero extend the condition if needed.
22698 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
22700 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22701 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
22702 DAG.getConstant(ShAmt, MVT::i8));
22703 if (N->getNumValues() == 2) // Dead flag value?
22704 return DCI.CombineTo(N, Cond, SDValue());
22705 return Cond;
22706 }
22708 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
22709 // for any integer data type, including i8/i16.
22710 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22711 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22712 DAG.getConstant(CC, MVT::i8), Cond);
22714 // Zero extend the condition if needed.
22715 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22716 FalseC->getValueType(0), Cond);
22717 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22718 SDValue(FalseC, 0));
22720 if (N->getNumValues() == 2) // Dead flag value?
22721 return DCI.CombineTo(N, Cond, SDValue());
22722 return Cond;
22723 }
22725 // Optimize cases that will turn into an LEA instruction. This requires
22726 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22727 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22728 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22729 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22731 bool isFastMultiplier = false;
22732 if (Diff < 10) {
22733 switch ((unsigned char)Diff) {
22734 default: break;
22735 case 1: // result = add base, cond
22736 case 2: // result = lea base( , cond*2)
22737 case 3: // result = lea base(cond, cond*2)
22738 case 4: // result = lea base( , cond*4)
22739 case 5: // result = lea base(cond, cond*4)
22740 case 8: // result = lea base( , cond*8)
22741 case 9: // result = lea base(cond, cond*8)
22742 isFastMultiplier = true;
22743 break;
22744 }
22745 }
22747 if (isFastMultiplier) {
22748 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22749 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22750 DAG.getConstant(CC, MVT::i8), Cond);
22751 // Zero extend the condition if needed.
22752 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22753 Cond);
22754 // Scale the condition by the difference.
22755 if (Diff != 1)
22756 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22757 DAG.getConstant(Diff, Cond.getValueType()));
22759 // Add the base if non-zero.
22760 if (FalseC->getAPIntValue() != 0)
22761 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22762 SDValue(FalseC, 0));
22763 if (N->getNumValues() == 2) // Dead flag value?
22764 return DCI.CombineTo(N, Cond, SDValue());
22765 return Cond;
22766 }
22767 }
22768 }
22769 }
22771 // Handle these cases:
22772 // (select (x != c), e, c) -> select (x != c), e, x),
22773 // (select (x == c), c, e) -> select (x == c), x, e)
22774 // where the c is an integer constant, and the "select" is the combination
22775 // of CMOV and CMP.
22776 //
22777 // The rationale for this change is that the conditional-move from a constant
22778 // needs two instructions, however, conditional-move from a register needs
22779 // only one instruction.
22780 //
22781 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
22782 // some instruction-combining opportunities. This opt needs to be
22783 // postponed as late as possible.
22784 //
22785 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
22786 // the DCI.xxxx conditions are provided to postpone the optimization as
22787 // late as possible.
22789 ConstantSDNode *CmpAgainst = nullptr;
22790 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
22791 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
22792 !isa<ConstantSDNode>(Cond.getOperand(0))) {
22794 if (CC == X86::COND_NE &&
22795 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
22796 CC = X86::GetOppositeBranchCondition(CC);
22797 std::swap(TrueOp, FalseOp);
22798 }
22800 if (CC == X86::COND_E &&
22801 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
22802 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
22803 DAG.getConstant(CC, MVT::i8), Cond };
22804 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
22805 }
22806 }
22807 }
22809 return SDValue();
22810 }
22812 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
22813 const X86Subtarget *Subtarget) {
22814 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
22815 switch (IntNo) {
22816 default: return SDValue();
22817 // SSE/AVX/AVX2 blend intrinsics.
22818 case Intrinsic::x86_avx2_pblendvb:
22819 case Intrinsic::x86_avx2_pblendw:
22820 case Intrinsic::x86_avx2_pblendd_128:
22821 case Intrinsic::x86_avx2_pblendd_256:
22822 // Don't try to simplify this intrinsic if we don't have AVX2.
22823 if (!Subtarget->hasAVX2())
22824 return SDValue();
22825 // FALL-THROUGH
22826 case Intrinsic::x86_avx_blend_pd_256:
22827 case Intrinsic::x86_avx_blend_ps_256:
22828 case Intrinsic::x86_avx_blendv_pd_256:
22829 case Intrinsic::x86_avx_blendv_ps_256:
22830 // Don't try to simplify this intrinsic if we don't have AVX.
22831 if (!Subtarget->hasAVX())
22832 return SDValue();
22833 // FALL-THROUGH
22834 case Intrinsic::x86_sse41_pblendw:
22835 case Intrinsic::x86_sse41_blendpd:
22836 case Intrinsic::x86_sse41_blendps:
22837 case Intrinsic::x86_sse41_blendvps:
22838 case Intrinsic::x86_sse41_blendvpd:
22839 case Intrinsic::x86_sse41_pblendvb: {
22840 SDValue Op0 = N->getOperand(1);
22841 SDValue Op1 = N->getOperand(2);
22842 SDValue Mask = N->getOperand(3);
22844 // Don't try to simplify this intrinsic if we don't have SSE4.1.
22845 if (!Subtarget->hasSSE41())
22846 return SDValue();
22848 // fold (blend A, A, Mask) -> A
22849 if (Op0 == Op1)
22850 return Op0;
22851 // fold (blend A, B, allZeros) -> A
22852 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
22853 return Op0;
22854 // fold (blend A, B, allOnes) -> B
22855 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
22856 return Op1;
22858 // Simplify the case where the mask is a constant i32 value.
22859 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
22860 if (C->isNullValue())
22861 return Op0;
22862 if (C->isAllOnesValue())
22863 return Op1;
22864 }
22866 return SDValue();
22867 }
22869 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
22870 case Intrinsic::x86_sse2_psrai_w:
22871 case Intrinsic::x86_sse2_psrai_d:
22872 case Intrinsic::x86_avx2_psrai_w:
22873 case Intrinsic::x86_avx2_psrai_d:
22874 case Intrinsic::x86_sse2_psra_w:
22875 case Intrinsic::x86_sse2_psra_d:
22876 case Intrinsic::x86_avx2_psra_w:
22877 case Intrinsic::x86_avx2_psra_d: {
22878 SDValue Op0 = N->getOperand(1);
22879 SDValue Op1 = N->getOperand(2);
22880 EVT VT = Op0.getValueType();
22881 assert(VT.isVector() && "Expected a vector type!");
22883 if (isa<BuildVectorSDNode>(Op1))
22884 Op1 = Op1.getOperand(0);
22886 if (!isa<ConstantSDNode>(Op1))
22887 return SDValue();
22889 EVT SVT = VT.getVectorElementType();
22890 unsigned SVTBits = SVT.getSizeInBits();
22892 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
22893 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
22894 uint64_t ShAmt = C.getZExtValue();
22896 // Don't try to convert this shift into a ISD::SRA if the shift
22897 // count is bigger than or equal to the element size.
22898 if (ShAmt >= SVTBits)
22899 return SDValue();
22901 // Trivial case: if the shift count is zero, then fold this
22902 // into the first operand.
22903 if (ShAmt == 0)
22904 return Op0;
22906 // Replace this packed shift intrinsic with a target independent
22907 // shift dag node.
22908 SDValue Splat = DAG.getConstant(C, VT);
22909 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
22910 }
22911 }
22912 }
22914 /// PerformMulCombine - Optimize a single multiply with constant into two
22915 /// in order to implement it with two cheaper instructions, e.g.
22916 /// LEA + SHL, LEA + LEA.
22917 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
22918 TargetLowering::DAGCombinerInfo &DCI) {
22919 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
22920 return SDValue();
22922 EVT VT = N->getValueType(0);
22923 if (VT != MVT::i64)
22924 return SDValue();
22926 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
22927 if (!C)
22928 return SDValue();
22929 uint64_t MulAmt = C->getZExtValue();
22930 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
22931 return SDValue();
22933 uint64_t MulAmt1 = 0;
22934 uint64_t MulAmt2 = 0;
22935 if ((MulAmt % 9) == 0) {
22936 MulAmt1 = 9;
22937 MulAmt2 = MulAmt / 9;
22938 } else if ((MulAmt % 5) == 0) {
22939 MulAmt1 = 5;
22940 MulAmt2 = MulAmt / 5;
22941 } else if ((MulAmt % 3) == 0) {
22942 MulAmt1 = 3;
22943 MulAmt2 = MulAmt / 3;
22944 }
22945 if (MulAmt2 &&
22946 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
22947 SDLoc DL(N);
22949 if (isPowerOf2_64(MulAmt2) &&
22950 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
22951 // If second multiplifer is pow2, issue it first. We want the multiply by
22952 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
22953 // is an add.
22954 std::swap(MulAmt1, MulAmt2);
22956 SDValue NewMul;
22957 if (isPowerOf2_64(MulAmt1))
22958 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
22959 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
22960 else
22961 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
22962 DAG.getConstant(MulAmt1, VT));
22964 if (isPowerOf2_64(MulAmt2))
22965 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
22966 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
22967 else
22968 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
22969 DAG.getConstant(MulAmt2, VT));
22971 // Do not add new nodes to DAG combiner worklist.
22972 DCI.CombineTo(N, NewMul, false);
22973 }
22974 return SDValue();
22975 }
22977 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
22978 SDValue N0 = N->getOperand(0);
22979 SDValue N1 = N->getOperand(1);
22980 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
22981 EVT VT = N0.getValueType();
22983 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
22984 // since the result of setcc_c is all zero's or all ones.
22985 if (VT.isInteger() && !VT.isVector() &&
22986 N1C && N0.getOpcode() == ISD::AND &&
22987 N0.getOperand(1).getOpcode() == ISD::Constant) {
22988 SDValue N00 = N0.getOperand(0);
22989 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
22990 ((N00.getOpcode() == ISD::ANY_EXTEND ||
22991 N00.getOpcode() == ISD::ZERO_EXTEND) &&
22992 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
22993 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
22994 APInt ShAmt = N1C->getAPIntValue();
22995 Mask = Mask.shl(ShAmt);
22996 if (Mask != 0)
22997 return DAG.getNode(ISD::AND, SDLoc(N), VT,
22998 N00, DAG.getConstant(Mask, VT));
22999 }
23000 }
23002 // Hardware support for vector shifts is sparse which makes us scalarize the
23003 // vector operations in many cases. Also, on sandybridge ADD is faster than
23004 // shl.
23005 // (shl V, 1) -> add V,V
23006 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
23007 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
23008 assert(N0.getValueType().isVector() && "Invalid vector shift type");
23009 // We shift all of the values by one. In many cases we do not have
23010 // hardware support for this operation. This is better expressed as an ADD
23011 // of two values.
23012 if (N1SplatC->getZExtValue() == 1)
23013 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
23014 }
23016 return SDValue();
23017 }
23019 /// \brief Returns a vector of 0s if the node in input is a vector logical
23020 /// shift by a constant amount which is known to be bigger than or equal
23021 /// to the vector element size in bits.
23022 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
23023 const X86Subtarget *Subtarget) {
23024 EVT VT = N->getValueType(0);
23026 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
23027 (!Subtarget->hasInt256() ||
23028 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
23029 return SDValue();
23031 SDValue Amt = N->getOperand(1);
23032 SDLoc DL(N);
23033 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
23034 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
23035 APInt ShiftAmt = AmtSplat->getAPIntValue();
23036 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
23038 // SSE2/AVX2 logical shifts always return a vector of 0s
23039 // if the shift amount is bigger than or equal to
23040 // the element size. The constant shift amount will be
23041 // encoded as a 8-bit immediate.
23042 if (ShiftAmt.trunc(8).uge(MaxAmount))
23043 return getZeroVector(VT, Subtarget, DAG, DL);
23044 }
23046 return SDValue();
23047 }
23049 /// PerformShiftCombine - Combine shifts.
23050 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
23051 TargetLowering::DAGCombinerInfo &DCI,
23052 const X86Subtarget *Subtarget) {
23053 if (N->getOpcode() == ISD::SHL) {
23054 SDValue V = PerformSHLCombine(N, DAG);
23055 if (V.getNode()) return V;
23056 }
23058 if (N->getOpcode() != ISD::SRA) {
23059 // Try to fold this logical shift into a zero vector.
23060 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
23061 if (V.getNode()) return V;
23062 }
23064 return SDValue();
23065 }
23067 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
23068 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
23069 // and friends. Likewise for OR -> CMPNEQSS.
23070 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
23071 TargetLowering::DAGCombinerInfo &DCI,
23072 const X86Subtarget *Subtarget) {
23073 unsigned opcode;
23075 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
23076 // we're requiring SSE2 for both.
23077 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
23078 SDValue N0 = N->getOperand(0);
23079 SDValue N1 = N->getOperand(1);
23080 SDValue CMP0 = N0->getOperand(1);
23081 SDValue CMP1 = N1->getOperand(1);
23082 SDLoc DL(N);
23084 // The SETCCs should both refer to the same CMP.
23085 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
23086 return SDValue();
23088 SDValue CMP00 = CMP0->getOperand(0);
23089 SDValue CMP01 = CMP0->getOperand(1);
23090 EVT VT = CMP00.getValueType();
23092 if (VT == MVT::f32 || VT == MVT::f64) {
23093 bool ExpectingFlags = false;
23094 // Check for any users that want flags:
23095 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
23096 !ExpectingFlags && UI != UE; ++UI)
23097 switch (UI->getOpcode()) {
23098 default:
23099 case ISD::BR_CC:
23100 case ISD::BRCOND:
23101 case ISD::SELECT:
23102 ExpectingFlags = true;
23103 break;
23104 case ISD::CopyToReg:
23105 case ISD::SIGN_EXTEND:
23106 case ISD::ZERO_EXTEND:
23107 case ISD::ANY_EXTEND:
23108 break;
23109 }
23111 if (!ExpectingFlags) {
23112 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
23113 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
23115 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
23116 X86::CondCode tmp = cc0;
23117 cc0 = cc1;
23118 cc1 = tmp;
23119 }
23121 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
23122 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
23123 // FIXME: need symbolic constants for these magic numbers.
23124 // See X86ATTInstPrinter.cpp:printSSECC().
23125 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
23126 if (Subtarget->hasAVX512()) {
23127 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
23128 CMP01, DAG.getConstant(x86cc, MVT::i8));
23129 if (N->getValueType(0) != MVT::i1)
23130 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
23131 FSetCC);
23132 return FSetCC;
23133 }
23134 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
23135 CMP00.getValueType(), CMP00, CMP01,
23136 DAG.getConstant(x86cc, MVT::i8));
23138 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
23139 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
23141 if (is64BitFP && !Subtarget->is64Bit()) {
23142 // On a 32-bit target, we cannot bitcast the 64-bit float to a
23143 // 64-bit integer, since that's not a legal type. Since
23144 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
23145 // bits, but can do this little dance to extract the lowest 32 bits
23146 // and work with those going forward.
23147 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
23148 OnesOrZeroesF);
23149 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
23150 Vector64);
23151 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
23152 Vector32, DAG.getIntPtrConstant(0));
23153 IntVT = MVT::i32;
23154 }
23156 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
23157 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
23158 DAG.getConstant(1, IntVT));
23159 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
23160 return OneBitOfTruth;
23161 }
23162 }
23163 }
23164 }
23165 return SDValue();
23166 }
23168 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
23169 /// so it can be folded inside ANDNP.
23170 static bool CanFoldXORWithAllOnes(const SDNode *N) {
23171 EVT VT = N->getValueType(0);
23173 // Match direct AllOnes for 128 and 256-bit vectors
23174 if (ISD::isBuildVectorAllOnes(N))
23175 return true;
23177 // Look through a bit convert.
23178 if (N->getOpcode() == ISD::BITCAST)
23179 N = N->getOperand(0).getNode();
23181 // Sometimes the operand may come from a insert_subvector building a 256-bit
23182 // allones vector
23183 if (VT.is256BitVector() &&
23184 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
23185 SDValue V1 = N->getOperand(0);
23186 SDValue V2 = N->getOperand(1);
23188 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
23189 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
23190 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
23191 ISD::isBuildVectorAllOnes(V2.getNode()))
23192 return true;
23193 }
23195 return false;
23196 }
23198 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
23199 // register. In most cases we actually compare or select YMM-sized registers
23200 // and mixing the two types creates horrible code. This method optimizes
23201 // some of the transition sequences.
23202 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
23203 TargetLowering::DAGCombinerInfo &DCI,
23204 const X86Subtarget *Subtarget) {
23205 EVT VT = N->getValueType(0);
23206 if (!VT.is256BitVector())
23207 return SDValue();
23209 assert((N->getOpcode() == ISD::ANY_EXTEND ||
23210 N->getOpcode() == ISD::ZERO_EXTEND ||
23211 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
23213 SDValue Narrow = N->getOperand(0);
23214 EVT NarrowVT = Narrow->getValueType(0);
23215 if (!NarrowVT.is128BitVector())
23216 return SDValue();
23218 if (Narrow->getOpcode() != ISD::XOR &&
23219 Narrow->getOpcode() != ISD::AND &&
23220 Narrow->getOpcode() != ISD::OR)
23221 return SDValue();
23223 SDValue N0 = Narrow->getOperand(0);
23224 SDValue N1 = Narrow->getOperand(1);
23225 SDLoc DL(Narrow);
23227 // The Left side has to be a trunc.
23228 if (N0.getOpcode() != ISD::TRUNCATE)
23229 return SDValue();
23231 // The type of the truncated inputs.
23232 EVT WideVT = N0->getOperand(0)->getValueType(0);
23233 if (WideVT != VT)
23234 return SDValue();
23236 // The right side has to be a 'trunc' or a constant vector.
23237 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
23238 ConstantSDNode *RHSConstSplat = nullptr;
23239 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
23240 RHSConstSplat = RHSBV->getConstantSplatNode();
23241 if (!RHSTrunc && !RHSConstSplat)
23242 return SDValue();
23244 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23246 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
23247 return SDValue();
23249 // Set N0 and N1 to hold the inputs to the new wide operation.
23250 N0 = N0->getOperand(0);
23251 if (RHSConstSplat) {
23252 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
23253 SDValue(RHSConstSplat, 0));
23254 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
23255 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
23256 } else if (RHSTrunc) {
23257 N1 = N1->getOperand(0);
23258 }
23260 // Generate the wide operation.
23261 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
23262 unsigned Opcode = N->getOpcode();
23263 switch (Opcode) {
23264 case ISD::ANY_EXTEND:
23265 return Op;
23266 case ISD::ZERO_EXTEND: {
23267 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
23268 APInt Mask = APInt::getAllOnesValue(InBits);
23269 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
23270 return DAG.getNode(ISD::AND, DL, VT,
23271 Op, DAG.getConstant(Mask, VT));
23272 }
23273 case ISD::SIGN_EXTEND:
23274 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
23275 Op, DAG.getValueType(NarrowVT));
23276 default:
23277 llvm_unreachable("Unexpected opcode");
23278 }
23279 }
23281 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
23282 TargetLowering::DAGCombinerInfo &DCI,
23283 const X86Subtarget *Subtarget) {
23284 EVT VT = N->getValueType(0);
23285 if (DCI.isBeforeLegalizeOps())
23286 return SDValue();
23288 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
23289 if (R.getNode())
23290 return R;
23292 // Create BEXTR instructions
23293 // BEXTR is ((X >> imm) & (2**size-1))
23294 if (VT == MVT::i32 || VT == MVT::i64) {
23295 SDValue N0 = N->getOperand(0);
23296 SDValue N1 = N->getOperand(1);
23297 SDLoc DL(N);
23299 // Check for BEXTR.
23300 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
23301 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
23302 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
23303 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23304 if (MaskNode && ShiftNode) {
23305 uint64_t Mask = MaskNode->getZExtValue();
23306 uint64_t Shift = ShiftNode->getZExtValue();
23307 if (isMask_64(Mask)) {
23308 uint64_t MaskSize = CountPopulation_64(Mask);
23309 if (Shift + MaskSize <= VT.getSizeInBits())
23310 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
23311 DAG.getConstant(Shift | (MaskSize << 8), VT));
23312 }
23313 }
23314 } // BEXTR
23316 return SDValue();
23317 }
23319 // Want to form ANDNP nodes:
23320 // 1) In the hopes of then easily combining them with OR and AND nodes
23321 // to form PBLEND/PSIGN.
23322 // 2) To match ANDN packed intrinsics
23323 if (VT != MVT::v2i64 && VT != MVT::v4i64)
23324 return SDValue();
23326 SDValue N0 = N->getOperand(0);
23327 SDValue N1 = N->getOperand(1);
23328 SDLoc DL(N);
23330 // Check LHS for vnot
23331 if (N0.getOpcode() == ISD::XOR &&
23332 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
23333 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
23334 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
23336 // Check RHS for vnot
23337 if (N1.getOpcode() == ISD::XOR &&
23338 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
23339 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
23340 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
23342 return SDValue();
23343 }
23345 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
23346 TargetLowering::DAGCombinerInfo &DCI,
23347 const X86Subtarget *Subtarget) {
23348 if (DCI.isBeforeLegalizeOps())
23349 return SDValue();
23351 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
23352 if (R.getNode())
23353 return R;
23355 SDValue N0 = N->getOperand(0);
23356 SDValue N1 = N->getOperand(1);
23357 EVT VT = N->getValueType(0);
23359 // look for psign/blend
23360 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
23361 if (!Subtarget->hasSSSE3() ||
23362 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
23363 return SDValue();
23365 // Canonicalize pandn to RHS
23366 if (N0.getOpcode() == X86ISD::ANDNP)
23367 std::swap(N0, N1);
23368 // or (and (m, y), (pandn m, x))
23369 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
23370 SDValue Mask = N1.getOperand(0);
23371 SDValue X = N1.getOperand(1);
23372 SDValue Y;
23373 if (N0.getOperand(0) == Mask)
23374 Y = N0.getOperand(1);
23375 if (N0.getOperand(1) == Mask)
23376 Y = N0.getOperand(0);
23378 // Check to see if the mask appeared in both the AND and ANDNP and
23379 if (!Y.getNode())
23380 return SDValue();
23382 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
23383 // Look through mask bitcast.
23384 if (Mask.getOpcode() == ISD::BITCAST)
23385 Mask = Mask.getOperand(0);
23386 if (X.getOpcode() == ISD::BITCAST)
23387 X = X.getOperand(0);
23388 if (Y.getOpcode() == ISD::BITCAST)
23389 Y = Y.getOperand(0);
23391 EVT MaskVT = Mask.getValueType();
23393 // Validate that the Mask operand is a vector sra node.
23394 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
23395 // there is no psrai.b
23396 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
23397 unsigned SraAmt = ~0;
23398 if (Mask.getOpcode() == ISD::SRA) {
23399 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
23400 if (auto *AmtConst = AmtBV->getConstantSplatNode())
23401 SraAmt = AmtConst->getZExtValue();
23402 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
23403 SDValue SraC = Mask.getOperand(1);
23404 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
23405 }
23406 if ((SraAmt + 1) != EltBits)
23407 return SDValue();
23409 SDLoc DL(N);
23411 // Now we know we at least have a plendvb with the mask val. See if
23412 // we can form a psignb/w/d.
23413 // psign = x.type == y.type == mask.type && y = sub(0, x);
23414 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
23415 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
23416 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
23417 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
23418 "Unsupported VT for PSIGN");
23419 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
23420 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
23421 }
23422 // PBLENDVB only available on SSE 4.1
23423 if (!Subtarget->hasSSE41())
23424 return SDValue();
23426 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
23428 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
23429 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
23430 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
23431 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
23432 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
23433 }
23434 }
23436 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
23437 return SDValue();
23439 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
23440 MachineFunction &MF = DAG.getMachineFunction();
23441 bool OptForSize = MF.getFunction()->getAttributes().
23442 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
23444 // SHLD/SHRD instructions have lower register pressure, but on some
23445 // platforms they have higher latency than the equivalent
23446 // series of shifts/or that would otherwise be generated.
23447 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
23448 // have higher latencies and we are not optimizing for size.
23449 if (!OptForSize && Subtarget->isSHLDSlow())
23450 return SDValue();
23452 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
23453 std::swap(N0, N1);
23454 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
23455 return SDValue();
23456 if (!N0.hasOneUse() || !N1.hasOneUse())
23457 return SDValue();
23459 SDValue ShAmt0 = N0.getOperand(1);
23460 if (ShAmt0.getValueType() != MVT::i8)
23461 return SDValue();
23462 SDValue ShAmt1 = N1.getOperand(1);
23463 if (ShAmt1.getValueType() != MVT::i8)
23464 return SDValue();
23465 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
23466 ShAmt0 = ShAmt0.getOperand(0);
23467 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
23468 ShAmt1 = ShAmt1.getOperand(0);
23470 SDLoc DL(N);
23471 unsigned Opc = X86ISD::SHLD;
23472 SDValue Op0 = N0.getOperand(0);
23473 SDValue Op1 = N1.getOperand(0);
23474 if (ShAmt0.getOpcode() == ISD::SUB) {
23475 Opc = X86ISD::SHRD;
23476 std::swap(Op0, Op1);
23477 std::swap(ShAmt0, ShAmt1);
23478 }
23480 unsigned Bits = VT.getSizeInBits();
23481 if (ShAmt1.getOpcode() == ISD::SUB) {
23482 SDValue Sum = ShAmt1.getOperand(0);
23483 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
23484 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
23485 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
23486 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
23487 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
23488 return DAG.getNode(Opc, DL, VT,
23489 Op0, Op1,
23490 DAG.getNode(ISD::TRUNCATE, DL,
23491 MVT::i8, ShAmt0));
23492 }
23493 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
23494 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
23495 if (ShAmt0C &&
23496 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
23497 return DAG.getNode(Opc, DL, VT,
23498 N0.getOperand(0), N1.getOperand(0),
23499 DAG.getNode(ISD::TRUNCATE, DL,
23500 MVT::i8, ShAmt0));
23501 }
23503 return SDValue();
23504 }
23506 // Generate NEG and CMOV for integer abs.
23507 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
23508 EVT VT = N->getValueType(0);
23510 // Since X86 does not have CMOV for 8-bit integer, we don't convert
23511 // 8-bit integer abs to NEG and CMOV.
23512 if (VT.isInteger() && VT.getSizeInBits() == 8)
23513 return SDValue();
23515 SDValue N0 = N->getOperand(0);
23516 SDValue N1 = N->getOperand(1);
23517 SDLoc DL(N);
23519 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
23520 // and change it to SUB and CMOV.
23521 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
23522 N0.getOpcode() == ISD::ADD &&
23523 N0.getOperand(1) == N1 &&
23524 N1.getOpcode() == ISD::SRA &&
23525 N1.getOperand(0) == N0.getOperand(0))
23526 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
23527 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
23528 // Generate SUB & CMOV.
23529 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
23530 DAG.getConstant(0, VT), N0.getOperand(0));
23532 SDValue Ops[] = { N0.getOperand(0), Neg,
23533 DAG.getConstant(X86::COND_GE, MVT::i8),
23534 SDValue(Neg.getNode(), 1) };
23535 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
23536 }
23537 return SDValue();
23538 }
23540 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
23541 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
23542 TargetLowering::DAGCombinerInfo &DCI,
23543 const X86Subtarget *Subtarget) {
23544 if (DCI.isBeforeLegalizeOps())
23545 return SDValue();
23547 if (Subtarget->hasCMov()) {
23548 SDValue RV = performIntegerAbsCombine(N, DAG);
23549 if (RV.getNode())
23550 return RV;
23551 }
23553 return SDValue();
23554 }
23556 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
23557 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
23558 TargetLowering::DAGCombinerInfo &DCI,
23559 const X86Subtarget *Subtarget) {
23560 LoadSDNode *Ld = cast<LoadSDNode>(N);
23561 EVT RegVT = Ld->getValueType(0);
23562 EVT MemVT = Ld->getMemoryVT();
23563 SDLoc dl(Ld);
23564 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23566 // On Sandybridge unaligned 256bit loads are inefficient.
23567 ISD::LoadExtType Ext = Ld->getExtensionType();
23568 unsigned Alignment = Ld->getAlignment();
23569 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
23570 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
23571 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
23572 unsigned NumElems = RegVT.getVectorNumElements();
23573 if (NumElems < 2)
23574 return SDValue();
23576 SDValue Ptr = Ld->getBasePtr();
23577 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
23579 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
23580 NumElems/2);
23581 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23582 Ld->getPointerInfo(), Ld->isVolatile(),
23583 Ld->isNonTemporal(), Ld->isInvariant(),
23584 Alignment);
23585 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23586 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23587 Ld->getPointerInfo(), Ld->isVolatile(),
23588 Ld->isNonTemporal(), Ld->isInvariant(),
23589 std::min(16U, Alignment));
23590 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
23591 Load1.getValue(1),
23592 Load2.getValue(1));
23594 SDValue NewVec = DAG.getUNDEF(RegVT);
23595 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
23596 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
23597 return DCI.CombineTo(N, NewVec, TF, true);
23598 }
23600 return SDValue();
23601 }
23603 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
23604 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
23605 const X86Subtarget *Subtarget) {
23606 StoreSDNode *St = cast<StoreSDNode>(N);
23607 EVT VT = St->getValue().getValueType();
23608 EVT StVT = St->getMemoryVT();
23609 SDLoc dl(St);
23610 SDValue StoredVal = St->getOperand(1);
23611 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23613 // If we are saving a concatenation of two XMM registers, perform two stores.
23614 // On Sandy Bridge, 256-bit memory operations are executed by two
23615 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
23616 // memory operation.
23617 unsigned Alignment = St->getAlignment();
23618 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
23619 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
23620 StVT == VT && !IsAligned) {
23621 unsigned NumElems = VT.getVectorNumElements();
23622 if (NumElems < 2)
23623 return SDValue();
23625 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
23626 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
23628 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
23629 SDValue Ptr0 = St->getBasePtr();
23630 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
23632 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
23633 St->getPointerInfo(), St->isVolatile(),
23634 St->isNonTemporal(), Alignment);
23635 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
23636 St->getPointerInfo(), St->isVolatile(),
23637 St->isNonTemporal(),
23638 std::min(16U, Alignment));
23639 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
23640 }
23642 // Optimize trunc store (of multiple scalars) to shuffle and store.
23643 // First, pack all of the elements in one place. Next, store to memory
23644 // in fewer chunks.
23645 if (St->isTruncatingStore() && VT.isVector()) {
23646 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23647 unsigned NumElems = VT.getVectorNumElements();
23648 assert(StVT != VT && "Cannot truncate to the same type");
23649 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
23650 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
23652 // From, To sizes and ElemCount must be pow of two
23653 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
23654 // We are going to use the original vector elt for storing.
23655 // Accumulated smaller vector elements must be a multiple of the store size.
23656 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
23658 unsigned SizeRatio = FromSz / ToSz;
23660 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
23662 // Create a type on which we perform the shuffle
23663 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23664 StVT.getScalarType(), NumElems*SizeRatio);
23666 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23668 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
23669 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
23670 for (unsigned i = 0; i != NumElems; ++i)
23671 ShuffleVec[i] = i * SizeRatio;
23673 // Can't shuffle using an illegal type.
23674 if (!TLI.isTypeLegal(WideVecVT))
23675 return SDValue();
23677 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
23678 DAG.getUNDEF(WideVecVT),
23679 &ShuffleVec[0]);
23680 // At this point all of the data is stored at the bottom of the
23681 // register. We now need to save it to mem.
23683 // Find the largest store unit
23684 MVT StoreType = MVT::i8;
23685 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
23686 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
23687 MVT Tp = (MVT::SimpleValueType)tp;
23688 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
23689 StoreType = Tp;
23690 }
23692 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
23693 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
23694 (64 <= NumElems * ToSz))
23695 StoreType = MVT::f64;
23697 // Bitcast the original vector into a vector of store-size units
23698 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
23699 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
23700 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
23701 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
23702 SmallVector<SDValue, 8> Chains;
23703 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
23704 TLI.getPointerTy());
23705 SDValue Ptr = St->getBasePtr();
23707 // Perform one or more big stores into memory.
23708 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
23709 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
23710 StoreType, ShuffWide,
23711 DAG.getIntPtrConstant(i));
23712 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
23713 St->getPointerInfo(), St->isVolatile(),
23714 St->isNonTemporal(), St->getAlignment());
23715 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23716 Chains.push_back(Ch);
23717 }
23719 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
23720 }
23722 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
23723 // the FP state in cases where an emms may be missing.
23724 // A preferable solution to the general problem is to figure out the right
23725 // places to insert EMMS. This qualifies as a quick hack.
23727 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
23728 if (VT.getSizeInBits() != 64)
23729 return SDValue();
23731 const Function *F = DAG.getMachineFunction().getFunction();
23732 bool NoImplicitFloatOps = F->getAttributes().
23733 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
23734 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
23735 && Subtarget->hasSSE2();
23736 if ((VT.isVector() ||
23737 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
23738 isa<LoadSDNode>(St->getValue()) &&
23739 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
23740 St->getChain().hasOneUse() && !St->isVolatile()) {
23741 SDNode* LdVal = St->getValue().getNode();
23742 LoadSDNode *Ld = nullptr;
23743 int TokenFactorIndex = -1;
23744 SmallVector<SDValue, 8> Ops;
23745 SDNode* ChainVal = St->getChain().getNode();
23746 // Must be a store of a load. We currently handle two cases: the load
23747 // is a direct child, and it's under an intervening TokenFactor. It is
23748 // possible to dig deeper under nested TokenFactors.
23749 if (ChainVal == LdVal)
23750 Ld = cast<LoadSDNode>(St->getChain());
23751 else if (St->getValue().hasOneUse() &&
23752 ChainVal->getOpcode() == ISD::TokenFactor) {
23753 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
23754 if (ChainVal->getOperand(i).getNode() == LdVal) {
23755 TokenFactorIndex = i;
23756 Ld = cast<LoadSDNode>(St->getValue());
23757 } else
23758 Ops.push_back(ChainVal->getOperand(i));
23759 }
23760 }
23762 if (!Ld || !ISD::isNormalLoad(Ld))
23763 return SDValue();
23765 // If this is not the MMX case, i.e. we are just turning i64 load/store
23766 // into f64 load/store, avoid the transformation if there are multiple
23767 // uses of the loaded value.
23768 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
23769 return SDValue();
23771 SDLoc LdDL(Ld);
23772 SDLoc StDL(N);
23773 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
23774 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
23775 // pair instead.
23776 if (Subtarget->is64Bit() || F64IsLegal) {
23777 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
23778 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
23779 Ld->getPointerInfo(), Ld->isVolatile(),
23780 Ld->isNonTemporal(), Ld->isInvariant(),
23781 Ld->getAlignment());
23782 SDValue NewChain = NewLd.getValue(1);
23783 if (TokenFactorIndex != -1) {
23784 Ops.push_back(NewChain);
23785 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23786 }
23787 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
23788 St->getPointerInfo(),
23789 St->isVolatile(), St->isNonTemporal(),
23790 St->getAlignment());
23791 }
23793 // Otherwise, lower to two pairs of 32-bit loads / stores.
23794 SDValue LoAddr = Ld->getBasePtr();
23795 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
23796 DAG.getConstant(4, MVT::i32));
23798 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
23799 Ld->getPointerInfo(),
23800 Ld->isVolatile(), Ld->isNonTemporal(),
23801 Ld->isInvariant(), Ld->getAlignment());
23802 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
23803 Ld->getPointerInfo().getWithOffset(4),
23804 Ld->isVolatile(), Ld->isNonTemporal(),
23805 Ld->isInvariant(),
23806 MinAlign(Ld->getAlignment(), 4));
23808 SDValue NewChain = LoLd.getValue(1);
23809 if (TokenFactorIndex != -1) {
23810 Ops.push_back(LoLd);
23811 Ops.push_back(HiLd);
23812 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23813 }
23815 LoAddr = St->getBasePtr();
23816 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
23817 DAG.getConstant(4, MVT::i32));
23819 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
23820 St->getPointerInfo(),
23821 St->isVolatile(), St->isNonTemporal(),
23822 St->getAlignment());
23823 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
23824 St->getPointerInfo().getWithOffset(4),
23825 St->isVolatile(),
23826 St->isNonTemporal(),
23827 MinAlign(St->getAlignment(), 4));
23828 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
23829 }
23830 return SDValue();
23831 }
23833 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
23834 /// and return the operands for the horizontal operation in LHS and RHS. A
23835 /// horizontal operation performs the binary operation on successive elements
23836 /// of its first operand, then on successive elements of its second operand,
23837 /// returning the resulting values in a vector. For example, if
23838 /// A = < float a0, float a1, float a2, float a3 >
23839 /// and
23840 /// B = < float b0, float b1, float b2, float b3 >
23841 /// then the result of doing a horizontal operation on A and B is
23842 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
23843 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
23844 /// A horizontal-op B, for some already available A and B, and if so then LHS is
23845 /// set to A, RHS to B, and the routine returns 'true'.
23846 /// Note that the binary operation should have the property that if one of the
23847 /// operands is UNDEF then the result is UNDEF.
23848 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
23849 // Look for the following pattern: if
23850 // A = < float a0, float a1, float a2, float a3 >
23851 // B = < float b0, float b1, float b2, float b3 >
23852 // and
23853 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
23854 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
23855 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
23856 // which is A horizontal-op B.
23858 // At least one of the operands should be a vector shuffle.
23859 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
23860 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
23861 return false;
23863 MVT VT = LHS.getSimpleValueType();
23865 assert((VT.is128BitVector() || VT.is256BitVector()) &&
23866 "Unsupported vector type for horizontal add/sub");
23868 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
23869 // operate independently on 128-bit lanes.
23870 unsigned NumElts = VT.getVectorNumElements();
23871 unsigned NumLanes = VT.getSizeInBits()/128;
23872 unsigned NumLaneElts = NumElts / NumLanes;
23873 assert((NumLaneElts % 2 == 0) &&
23874 "Vector type should have an even number of elements in each lane");
23875 unsigned HalfLaneElts = NumLaneElts/2;
23877 // View LHS in the form
23878 // LHS = VECTOR_SHUFFLE A, B, LMask
23879 // If LHS is not a shuffle then pretend it is the shuffle
23880 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
23881 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
23882 // type VT.
23883 SDValue A, B;
23884 SmallVector<int, 16> LMask(NumElts);
23885 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23886 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
23887 A = LHS.getOperand(0);
23888 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
23889 B = LHS.getOperand(1);
23890 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
23891 std::copy(Mask.begin(), Mask.end(), LMask.begin());
23892 } else {
23893 if (LHS.getOpcode() != ISD::UNDEF)
23894 A = LHS;
23895 for (unsigned i = 0; i != NumElts; ++i)
23896 LMask[i] = i;
23897 }
23899 // Likewise, view RHS in the form
23900 // RHS = VECTOR_SHUFFLE C, D, RMask
23901 SDValue C, D;
23902 SmallVector<int, 16> RMask(NumElts);
23903 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23904 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
23905 C = RHS.getOperand(0);
23906 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
23907 D = RHS.getOperand(1);
23908 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
23909 std::copy(Mask.begin(), Mask.end(), RMask.begin());
23910 } else {
23911 if (RHS.getOpcode() != ISD::UNDEF)
23912 C = RHS;
23913 for (unsigned i = 0; i != NumElts; ++i)
23914 RMask[i] = i;
23915 }
23917 // Check that the shuffles are both shuffling the same vectors.
23918 if (!(A == C && B == D) && !(A == D && B == C))
23919 return false;
23921 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
23922 if (!A.getNode() && !B.getNode())
23923 return false;
23925 // If A and B occur in reverse order in RHS, then "swap" them (which means
23926 // rewriting the mask).
23927 if (A != C)
23928 CommuteVectorShuffleMask(RMask, NumElts);
23930 // At this point LHS and RHS are equivalent to
23931 // LHS = VECTOR_SHUFFLE A, B, LMask
23932 // RHS = VECTOR_SHUFFLE A, B, RMask
23933 // Check that the masks correspond to performing a horizontal operation.
23934 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
23935 for (unsigned i = 0; i != NumLaneElts; ++i) {
23936 int LIdx = LMask[i+l], RIdx = RMask[i+l];
23938 // Ignore any UNDEF components.
23939 if (LIdx < 0 || RIdx < 0 ||
23940 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
23941 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
23942 continue;
23944 // Check that successive elements are being operated on. If not, this is
23945 // not a horizontal operation.
23946 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
23947 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
23948 if (!(LIdx == Index && RIdx == Index + 1) &&
23949 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
23950 return false;
23951 }
23952 }
23954 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
23955 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
23956 return true;
23957 }
23959 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
23960 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
23961 const X86Subtarget *Subtarget) {
23962 EVT VT = N->getValueType(0);
23963 SDValue LHS = N->getOperand(0);
23964 SDValue RHS = N->getOperand(1);
23966 // Try to synthesize horizontal adds from adds of shuffles.
23967 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23968 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23969 isHorizontalBinOp(LHS, RHS, true))
23970 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
23971 return SDValue();
23972 }
23974 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
23975 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
23976 const X86Subtarget *Subtarget) {
23977 EVT VT = N->getValueType(0);
23978 SDValue LHS = N->getOperand(0);
23979 SDValue RHS = N->getOperand(1);
23981 // Try to synthesize horizontal subs from subs of shuffles.
23982 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23983 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23984 isHorizontalBinOp(LHS, RHS, false))
23985 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
23986 return SDValue();
23987 }
23989 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
23990 /// X86ISD::FXOR nodes.
23991 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
23992 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
23993 // F[X]OR(0.0, x) -> x
23994 // F[X]OR(x, 0.0) -> x
23995 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23996 if (C->getValueAPF().isPosZero())
23997 return N->getOperand(1);
23998 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23999 if (C->getValueAPF().isPosZero())
24000 return N->getOperand(0);
24001 return SDValue();
24002 }
24004 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
24005 /// X86ISD::FMAX nodes.
24006 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
24007 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
24009 // Only perform optimizations if UnsafeMath is used.
24010 if (!DAG.getTarget().Options.UnsafeFPMath)
24011 return SDValue();
24013 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
24014 // into FMINC and FMAXC, which are Commutative operations.
24015 unsigned NewOp = 0;
24016 switch (N->getOpcode()) {
24017 default: llvm_unreachable("unknown opcode");
24018 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
24019 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
24020 }
24022 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
24023 N->getOperand(0), N->getOperand(1));
24024 }
24026 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
24027 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
24028 // FAND(0.0, x) -> 0.0
24029 // FAND(x, 0.0) -> 0.0
24030 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24031 if (C->getValueAPF().isPosZero())
24032 return N->getOperand(0);
24033 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24034 if (C->getValueAPF().isPosZero())
24035 return N->getOperand(1);
24036 return SDValue();
24037 }
24039 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
24040 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
24041 // FANDN(x, 0.0) -> 0.0
24042 // FANDN(0.0, x) -> x
24043 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24044 if (C->getValueAPF().isPosZero())
24045 return N->getOperand(1);
24046 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24047 if (C->getValueAPF().isPosZero())
24048 return N->getOperand(1);
24049 return SDValue();
24050 }
24052 static SDValue PerformBTCombine(SDNode *N,
24053 SelectionDAG &DAG,
24054 TargetLowering::DAGCombinerInfo &DCI) {
24055 // BT ignores high bits in the bit index operand.
24056 SDValue Op1 = N->getOperand(1);
24057 if (Op1.hasOneUse()) {
24058 unsigned BitWidth = Op1.getValueSizeInBits();
24059 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
24060 APInt KnownZero, KnownOne;
24061 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
24062 !DCI.isBeforeLegalizeOps());
24063 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24064 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
24065 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
24066 DCI.CommitTargetLoweringOpt(TLO);
24067 }
24068 return SDValue();
24069 }
24071 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
24072 SDValue Op = N->getOperand(0);
24073 if (Op.getOpcode() == ISD::BITCAST)
24074 Op = Op.getOperand(0);
24075 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
24076 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
24077 VT.getVectorElementType().getSizeInBits() ==
24078 OpVT.getVectorElementType().getSizeInBits()) {
24079 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
24080 }
24081 return SDValue();
24082 }
24084 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
24085 const X86Subtarget *Subtarget) {
24086 EVT VT = N->getValueType(0);
24087 if (!VT.isVector())
24088 return SDValue();
24090 SDValue N0 = N->getOperand(0);
24091 SDValue N1 = N->getOperand(1);
24092 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
24093 SDLoc dl(N);
24095 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
24096 // both SSE and AVX2 since there is no sign-extended shift right
24097 // operation on a vector with 64-bit elements.
24098 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
24099 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
24100 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
24101 N0.getOpcode() == ISD::SIGN_EXTEND)) {
24102 SDValue N00 = N0.getOperand(0);
24104 // EXTLOAD has a better solution on AVX2,
24105 // it may be replaced with X86ISD::VSEXT node.
24106 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
24107 if (!ISD::isNormalLoad(N00.getNode()))
24108 return SDValue();
24110 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
24111 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
24112 N00, N1);
24113 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
24114 }
24115 }
24116 return SDValue();
24117 }
24119 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
24120 TargetLowering::DAGCombinerInfo &DCI,
24121 const X86Subtarget *Subtarget) {
24122 if (!DCI.isBeforeLegalizeOps())
24123 return SDValue();
24125 if (!Subtarget->hasFp256())
24126 return SDValue();
24128 EVT VT = N->getValueType(0);
24129 if (VT.isVector() && VT.getSizeInBits() == 256) {
24130 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24131 if (R.getNode())
24132 return R;
24133 }
24135 return SDValue();
24136 }
24138 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
24139 const X86Subtarget* Subtarget) {
24140 SDLoc dl(N);
24141 EVT VT = N->getValueType(0);
24143 // Let legalize expand this if it isn't a legal type yet.
24144 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
24145 return SDValue();
24147 EVT ScalarVT = VT.getScalarType();
24148 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
24149 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
24150 return SDValue();
24152 SDValue A = N->getOperand(0);
24153 SDValue B = N->getOperand(1);
24154 SDValue C = N->getOperand(2);
24156 bool NegA = (A.getOpcode() == ISD::FNEG);
24157 bool NegB = (B.getOpcode() == ISD::FNEG);
24158 bool NegC = (C.getOpcode() == ISD::FNEG);
24160 // Negative multiplication when NegA xor NegB
24161 bool NegMul = (NegA != NegB);
24162 if (NegA)
24163 A = A.getOperand(0);
24164 if (NegB)
24165 B = B.getOperand(0);
24166 if (NegC)
24167 C = C.getOperand(0);
24169 unsigned Opcode;
24170 if (!NegMul)
24171 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
24172 else
24173 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
24175 return DAG.getNode(Opcode, dl, VT, A, B, C);
24176 }
24178 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
24179 TargetLowering::DAGCombinerInfo &DCI,
24180 const X86Subtarget *Subtarget) {
24181 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
24182 // (and (i32 x86isd::setcc_carry), 1)
24183 // This eliminates the zext. This transformation is necessary because
24184 // ISD::SETCC is always legalized to i8.
24185 SDLoc dl(N);
24186 SDValue N0 = N->getOperand(0);
24187 EVT VT = N->getValueType(0);
24189 if (N0.getOpcode() == ISD::AND &&
24190 N0.hasOneUse() &&
24191 N0.getOperand(0).hasOneUse()) {
24192 SDValue N00 = N0.getOperand(0);
24193 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24194 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24195 if (!C || C->getZExtValue() != 1)
24196 return SDValue();
24197 return DAG.getNode(ISD::AND, dl, VT,
24198 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24199 N00.getOperand(0), N00.getOperand(1)),
24200 DAG.getConstant(1, VT));
24201 }
24202 }
24204 if (N0.getOpcode() == ISD::TRUNCATE &&
24205 N0.hasOneUse() &&
24206 N0.getOperand(0).hasOneUse()) {
24207 SDValue N00 = N0.getOperand(0);
24208 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24209 return DAG.getNode(ISD::AND, dl, VT,
24210 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24211 N00.getOperand(0), N00.getOperand(1)),
24212 DAG.getConstant(1, VT));
24213 }
24214 }
24215 if (VT.is256BitVector()) {
24216 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24217 if (R.getNode())
24218 return R;
24219 }
24221 return SDValue();
24222 }
24224 // Optimize x == -y --> x+y == 0
24225 // x != -y --> x+y != 0
24226 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
24227 const X86Subtarget* Subtarget) {
24228 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
24229 SDValue LHS = N->getOperand(0);
24230 SDValue RHS = N->getOperand(1);
24231 EVT VT = N->getValueType(0);
24232 SDLoc DL(N);
24234 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
24235 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
24236 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
24237 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
24238 LHS.getValueType(), RHS, LHS.getOperand(1));
24239 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
24240 addV, DAG.getConstant(0, addV.getValueType()), CC);
24241 }
24242 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
24243 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
24244 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
24245 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
24246 RHS.getValueType(), LHS, RHS.getOperand(1));
24247 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
24248 addV, DAG.getConstant(0, addV.getValueType()), CC);
24249 }
24251 if (VT.getScalarType() == MVT::i1) {
24252 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
24253 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24254 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
24255 if (!IsSEXT0 && !IsVZero0)
24256 return SDValue();
24257 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
24258 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24259 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
24261 if (!IsSEXT1 && !IsVZero1)
24262 return SDValue();
24264 if (IsSEXT0 && IsVZero1) {
24265 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
24266 if (CC == ISD::SETEQ)
24267 return DAG.getNOT(DL, LHS.getOperand(0), VT);
24268 return LHS.getOperand(0);
24269 }
24270 if (IsSEXT1 && IsVZero0) {
24271 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
24272 if (CC == ISD::SETEQ)
24273 return DAG.getNOT(DL, RHS.getOperand(0), VT);
24274 return RHS.getOperand(0);
24275 }
24276 }
24278 return SDValue();
24279 }
24281 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
24282 const X86Subtarget *Subtarget) {
24283 SDLoc dl(N);
24284 MVT VT = N->getOperand(1)->getSimpleValueType(0);
24285 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
24286 "X86insertps is only defined for v4x32");
24288 SDValue Ld = N->getOperand(1);
24289 if (MayFoldLoad(Ld)) {
24290 // Extract the countS bits from the immediate so we can get the proper
24291 // address when narrowing the vector load to a specific element.
24292 // When the second source op is a memory address, interps doesn't use
24293 // countS and just gets an f32 from that address.
24294 unsigned DestIndex =
24295 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
24296 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
24297 } else
24298 return SDValue();
24300 // Create this as a scalar to vector to match the instruction pattern.
24301 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
24302 // countS bits are ignored when loading from memory on insertps, which
24303 // means we don't need to explicitly set them to 0.
24304 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
24305 LoadScalarToVector, N->getOperand(2));
24306 }
24308 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
24309 // as "sbb reg,reg", since it can be extended without zext and produces
24310 // an all-ones bit which is more useful than 0/1 in some cases.
24311 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
24312 MVT VT) {
24313 if (VT == MVT::i8)
24314 return DAG.getNode(ISD::AND, DL, VT,
24315 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24316 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
24317 DAG.getConstant(1, VT));
24318 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
24319 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
24320 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24321 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
24322 }
24324 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
24325 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
24326 TargetLowering::DAGCombinerInfo &DCI,
24327 const X86Subtarget *Subtarget) {
24328 SDLoc DL(N);
24329 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
24330 SDValue EFLAGS = N->getOperand(1);
24332 if (CC == X86::COND_A) {
24333 // Try to convert COND_A into COND_B in an attempt to facilitate
24334 // materializing "setb reg".
24335 //
24336 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
24337 // cannot take an immediate as its first operand.
24338 //
24339 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
24340 EFLAGS.getValueType().isInteger() &&
24341 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
24342 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
24343 EFLAGS.getNode()->getVTList(),
24344 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
24345 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
24346 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
24347 }
24348 }
24350 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
24351 // a zext and produces an all-ones bit which is more useful than 0/1 in some
24352 // cases.
24353 if (CC == X86::COND_B)
24354 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
24356 SDValue Flags;
24358 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
24359 if (Flags.getNode()) {
24360 SDValue Cond = DAG.getConstant(CC, MVT::i8);
24361 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
24362 }
24364 return SDValue();
24365 }
24367 // Optimize branch condition evaluation.
24368 //
24369 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
24370 TargetLowering::DAGCombinerInfo &DCI,
24371 const X86Subtarget *Subtarget) {
24372 SDLoc DL(N);
24373 SDValue Chain = N->getOperand(0);
24374 SDValue Dest = N->getOperand(1);
24375 SDValue EFLAGS = N->getOperand(3);
24376 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
24378 SDValue Flags;
24380 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
24381 if (Flags.getNode()) {
24382 SDValue Cond = DAG.getConstant(CC, MVT::i8);
24383 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
24384 Flags);
24385 }
24387 return SDValue();
24388 }
24390 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
24391 SelectionDAG &DAG) {
24392 // Take advantage of vector comparisons producing 0 or -1 in each lane to
24393 // optimize away operation when it's from a constant.
24394 //
24395 // The general transformation is:
24396 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
24397 // AND(VECTOR_CMP(x,y), constant2)
24398 // constant2 = UNARYOP(constant)
24400 // Early exit if this isn't a vector operation, the operand of the
24401 // unary operation isn't a bitwise AND, or if the sizes of the operations
24402 // aren't the same.
24403 EVT VT = N->getValueType(0);
24404 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
24405 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
24406 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
24407 return SDValue();
24409 // Now check that the other operand of the AND is a constant. We could
24410 // make the transformation for non-constant splats as well, but it's unclear
24411 // that would be a benefit as it would not eliminate any operations, just
24412 // perform one more step in scalar code before moving to the vector unit.
24413 if (BuildVectorSDNode *BV =
24414 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
24415 // Bail out if the vector isn't a constant.
24416 if (!BV->isConstant())
24417 return SDValue();
24419 // Everything checks out. Build up the new and improved node.
24420 SDLoc DL(N);
24421 EVT IntVT = BV->getValueType(0);
24422 // Create a new constant of the appropriate type for the transformed
24423 // DAG.
24424 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
24425 // The AND node needs bitcasts to/from an integer vector type around it.
24426 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
24427 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
24428 N->getOperand(0)->getOperand(0), MaskConst);
24429 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
24430 return Res;
24431 }
24433 return SDValue();
24434 }
24436 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
24437 const X86TargetLowering *XTLI) {
24438 // First try to optimize away the conversion entirely when it's
24439 // conditionally from a constant. Vectors only.
24440 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
24441 if (Res != SDValue())
24442 return Res;
24444 // Now move on to more general possibilities.
24445 SDValue Op0 = N->getOperand(0);
24446 EVT InVT = Op0->getValueType(0);
24448 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
24449 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
24450 SDLoc dl(N);
24451 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
24452 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
24453 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
24454 }
24456 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
24457 // a 32-bit target where SSE doesn't support i64->FP operations.
24458 if (Op0.getOpcode() == ISD::LOAD) {
24459 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
24460 EVT VT = Ld->getValueType(0);
24461 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
24462 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
24463 !XTLI->getSubtarget()->is64Bit() &&
24464 VT == MVT::i64) {
24465 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
24466 Ld->getChain(), Op0, DAG);
24467 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
24468 return FILDChain;
24469 }
24470 }
24471 return SDValue();
24472 }
24474 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
24475 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
24476 X86TargetLowering::DAGCombinerInfo &DCI) {
24477 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
24478 // the result is either zero or one (depending on the input carry bit).
24479 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
24480 if (X86::isZeroNode(N->getOperand(0)) &&
24481 X86::isZeroNode(N->getOperand(1)) &&
24482 // We don't have a good way to replace an EFLAGS use, so only do this when
24483 // dead right now.
24484 SDValue(N, 1).use_empty()) {
24485 SDLoc DL(N);
24486 EVT VT = N->getValueType(0);
24487 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
24488 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
24489 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
24490 DAG.getConstant(X86::COND_B,MVT::i8),
24491 N->getOperand(2)),
24492 DAG.getConstant(1, VT));
24493 return DCI.CombineTo(N, Res1, CarryOut);
24494 }
24496 return SDValue();
24497 }
24499 // fold (add Y, (sete X, 0)) -> adc 0, Y
24500 // (add Y, (setne X, 0)) -> sbb -1, Y
24501 // (sub (sete X, 0), Y) -> sbb 0, Y
24502 // (sub (setne X, 0), Y) -> adc -1, Y
24503 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
24504 SDLoc DL(N);
24506 // Look through ZExts.
24507 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
24508 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
24509 return SDValue();
24511 SDValue SetCC = Ext.getOperand(0);
24512 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
24513 return SDValue();
24515 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
24516 if (CC != X86::COND_E && CC != X86::COND_NE)
24517 return SDValue();
24519 SDValue Cmp = SetCC.getOperand(1);
24520 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
24521 !X86::isZeroNode(Cmp.getOperand(1)) ||
24522 !Cmp.getOperand(0).getValueType().isInteger())
24523 return SDValue();
24525 SDValue CmpOp0 = Cmp.getOperand(0);
24526 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
24527 DAG.getConstant(1, CmpOp0.getValueType()));
24529 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
24530 if (CC == X86::COND_NE)
24531 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
24532 DL, OtherVal.getValueType(), OtherVal,
24533 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
24534 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
24535 DL, OtherVal.getValueType(), OtherVal,
24536 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
24537 }
24539 /// PerformADDCombine - Do target-specific dag combines on integer adds.
24540 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
24541 const X86Subtarget *Subtarget) {
24542 EVT VT = N->getValueType(0);
24543 SDValue Op0 = N->getOperand(0);
24544 SDValue Op1 = N->getOperand(1);
24546 // Try to synthesize horizontal adds from adds of shuffles.
24547 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24548 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24549 isHorizontalBinOp(Op0, Op1, true))
24550 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
24552 return OptimizeConditionalInDecrement(N, DAG);
24553 }
24555 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
24556 const X86Subtarget *Subtarget) {
24557 SDValue Op0 = N->getOperand(0);
24558 SDValue Op1 = N->getOperand(1);
24560 // X86 can't encode an immediate LHS of a sub. See if we can push the
24561 // negation into a preceding instruction.
24562 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
24563 // If the RHS of the sub is a XOR with one use and a constant, invert the
24564 // immediate. Then add one to the LHS of the sub so we can turn
24565 // X-Y -> X+~Y+1, saving one register.
24566 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
24567 isa<ConstantSDNode>(Op1.getOperand(1))) {
24568 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
24569 EVT VT = Op0.getValueType();
24570 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
24571 Op1.getOperand(0),
24572 DAG.getConstant(~XorC, VT));
24573 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
24574 DAG.getConstant(C->getAPIntValue()+1, VT));
24575 }
24576 }
24578 // Try to synthesize horizontal adds from adds of shuffles.
24579 EVT VT = N->getValueType(0);
24580 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24581 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24582 isHorizontalBinOp(Op0, Op1, true))
24583 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
24585 return OptimizeConditionalInDecrement(N, DAG);
24586 }
24588 /// performVZEXTCombine - Performs build vector combines
24589 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
24590 TargetLowering::DAGCombinerInfo &DCI,
24591 const X86Subtarget *Subtarget) {
24592 // (vzext (bitcast (vzext (x)) -> (vzext x)
24593 SDValue In = N->getOperand(0);
24594 while (In.getOpcode() == ISD::BITCAST)
24595 In = In.getOperand(0);
24597 if (In.getOpcode() != X86ISD::VZEXT)
24598 return SDValue();
24600 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
24601 In.getOperand(0));
24602 }
24604 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
24605 DAGCombinerInfo &DCI) const {
24606 SelectionDAG &DAG = DCI.DAG;
24607 switch (N->getOpcode()) {
24608 default: break;
24609 case ISD::EXTRACT_VECTOR_ELT:
24610 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
24611 case ISD::VSELECT:
24612 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
24613 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
24614 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
24615 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
24616 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
24617 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
24618 case ISD::SHL:
24619 case ISD::SRA:
24620 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
24621 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
24622 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
24623 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
24624 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
24625 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
24626 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
24627 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
24628 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
24629 case X86ISD::FXOR:
24630 case X86ISD::FOR: return PerformFORCombine(N, DAG);
24631 case X86ISD::FMIN:
24632 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
24633 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
24634 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
24635 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
24636 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
24637 case ISD::ANY_EXTEND:
24638 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
24639 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
24640 case ISD::SIGN_EXTEND_INREG:
24641 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
24642 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
24643 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
24644 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
24645 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
24646 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
24647 case X86ISD::SHUFP: // Handle all target specific shuffles
24648 case X86ISD::PALIGNR:
24649 case X86ISD::UNPCKH:
24650 case X86ISD::UNPCKL:
24651 case X86ISD::MOVHLPS:
24652 case X86ISD::MOVLHPS:
24653 case X86ISD::PSHUFB:
24654 case X86ISD::PSHUFD:
24655 case X86ISD::PSHUFHW:
24656 case X86ISD::PSHUFLW:
24657 case X86ISD::MOVSS:
24658 case X86ISD::MOVSD:
24659 case X86ISD::VPERMILPI:
24660 case X86ISD::VPERM2X128:
24661 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
24662 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
24663 case ISD::INTRINSIC_WO_CHAIN:
24664 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
24665 case X86ISD::INSERTPS:
24666 return PerformINSERTPSCombine(N, DAG, Subtarget);
24667 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
24668 }
24670 return SDValue();
24671 }
24673 /// isTypeDesirableForOp - Return true if the target has native support for
24674 /// the specified value type and it is 'desirable' to use the type for the
24675 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
24676 /// instruction encodings are longer and some i16 instructions are slow.
24677 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
24678 if (!isTypeLegal(VT))
24679 return false;
24680 if (VT != MVT::i16)
24681 return true;
24683 switch (Opc) {
24684 default:
24685 return true;
24686 case ISD::LOAD:
24687 case ISD::SIGN_EXTEND:
24688 case ISD::ZERO_EXTEND:
24689 case ISD::ANY_EXTEND:
24690 case ISD::SHL:
24691 case ISD::SRL:
24692 case ISD::SUB:
24693 case ISD::ADD:
24694 case ISD::MUL:
24695 case ISD::AND:
24696 case ISD::OR:
24697 case ISD::XOR:
24698 return false;
24699 }
24700 }
24702 /// IsDesirableToPromoteOp - This method query the target whether it is
24703 /// beneficial for dag combiner to promote the specified node. If true, it
24704 /// should return the desired promotion type by reference.
24705 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
24706 EVT VT = Op.getValueType();
24707 if (VT != MVT::i16)
24708 return false;
24710 bool Promote = false;
24711 bool Commute = false;
24712 switch (Op.getOpcode()) {
24713 default: break;
24714 case ISD::LOAD: {
24715 LoadSDNode *LD = cast<LoadSDNode>(Op);
24716 // If the non-extending load has a single use and it's not live out, then it
24717 // might be folded.
24718 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
24719 Op.hasOneUse()*/) {
24720 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
24721 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
24722 // The only case where we'd want to promote LOAD (rather then it being
24723 // promoted as an operand is when it's only use is liveout.
24724 if (UI->getOpcode() != ISD::CopyToReg)
24725 return false;
24726 }
24727 }
24728 Promote = true;
24729 break;
24730 }
24731 case ISD::SIGN_EXTEND:
24732 case ISD::ZERO_EXTEND:
24733 case ISD::ANY_EXTEND:
24734 Promote = true;
24735 break;
24736 case ISD::SHL:
24737 case ISD::SRL: {
24738 SDValue N0 = Op.getOperand(0);
24739 // Look out for (store (shl (load), x)).
24740 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
24741 return false;
24742 Promote = true;
24743 break;
24744 }
24745 case ISD::ADD:
24746 case ISD::MUL:
24747 case ISD::AND:
24748 case ISD::OR:
24749 case ISD::XOR:
24750 Commute = true;
24751 // fallthrough
24752 case ISD::SUB: {
24753 SDValue N0 = Op.getOperand(0);
24754 SDValue N1 = Op.getOperand(1);
24755 if (!Commute && MayFoldLoad(N1))
24756 return false;
24757 // Avoid disabling potential load folding opportunities.
24758 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
24759 return false;
24760 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
24761 return false;
24762 Promote = true;
24763 }
24764 }
24766 PVT = MVT::i32;
24767 return Promote;
24768 }
24770 //===----------------------------------------------------------------------===//
24771 // X86 Inline Assembly Support
24772 //===----------------------------------------------------------------------===//
24774 namespace {
24775 // Helper to match a string separated by whitespace.
24776 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
24777 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
24779 for (unsigned i = 0, e = args.size(); i != e; ++i) {
24780 StringRef piece(*args[i]);
24781 if (!s.startswith(piece)) // Check if the piece matches.
24782 return false;
24784 s = s.substr(piece.size());
24785 StringRef::size_type pos = s.find_first_not_of(" \t");
24786 if (pos == 0) // We matched a prefix.
24787 return false;
24789 s = s.substr(pos);
24790 }
24792 return s.empty();
24793 }
24794 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
24795 }
24797 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
24799 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
24800 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
24801 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
24802 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
24804 if (AsmPieces.size() == 3)
24805 return true;
24806 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
24807 return true;
24808 }
24809 }
24810 return false;
24811 }
24813 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
24814 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
24816 std::string AsmStr = IA->getAsmString();
24818 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
24819 if (!Ty || Ty->getBitWidth() % 16 != 0)
24820 return false;
24822 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
24823 SmallVector<StringRef, 4> AsmPieces;
24824 SplitString(AsmStr, AsmPieces, ";\n");
24826 switch (AsmPieces.size()) {
24827 default: return false;
24828 case 1:
24829 // FIXME: this should verify that we are targeting a 486 or better. If not,
24830 // we will turn this bswap into something that will be lowered to logical
24831 // ops instead of emitting the bswap asm. For now, we don't support 486 or
24832 // lower so don't worry about this.
24833 // bswap $0
24834 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
24835 matchAsm(AsmPieces[0], "bswapl", "$0") ||
24836 matchAsm(AsmPieces[0], "bswapq", "$0") ||
24837 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
24838 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
24839 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
24840 // No need to check constraints, nothing other than the equivalent of
24841 // "=r,0" would be valid here.
24842 return IntrinsicLowering::LowerToByteSwap(CI);
24843 }
24845 // rorw $$8, ${0:w} --> llvm.bswap.i16
24846 if (CI->getType()->isIntegerTy(16) &&
24847 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24848 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
24849 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
24850 AsmPieces.clear();
24851 const std::string &ConstraintsStr = IA->getConstraintString();
24852 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24853 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24854 if (clobbersFlagRegisters(AsmPieces))
24855 return IntrinsicLowering::LowerToByteSwap(CI);
24856 }
24857 break;
24858 case 3:
24859 if (CI->getType()->isIntegerTy(32) &&
24860 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24861 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
24862 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
24863 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
24864 AsmPieces.clear();
24865 const std::string &ConstraintsStr = IA->getConstraintString();
24866 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24867 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24868 if (clobbersFlagRegisters(AsmPieces))
24869 return IntrinsicLowering::LowerToByteSwap(CI);
24870 }
24872 if (CI->getType()->isIntegerTy(64)) {
24873 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
24874 if (Constraints.size() >= 2 &&
24875 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
24876 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
24877 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
24878 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
24879 matchAsm(AsmPieces[1], "bswap", "%edx") &&
24880 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
24881 return IntrinsicLowering::LowerToByteSwap(CI);
24882 }
24883 }
24884 break;
24885 }
24886 return false;
24887 }
24889 /// getConstraintType - Given a constraint letter, return the type of
24890 /// constraint it is for this target.
24891 X86TargetLowering::ConstraintType
24892 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
24893 if (Constraint.size() == 1) {
24894 switch (Constraint[0]) {
24895 case 'R':
24896 case 'q':
24897 case 'Q':
24898 case 'f':
24899 case 't':
24900 case 'u':
24901 case 'y':
24902 case 'x':
24903 case 'Y':
24904 case 'l':
24905 return C_RegisterClass;
24906 case 'a':
24907 case 'b':
24908 case 'c':
24909 case 'd':
24910 case 'S':
24911 case 'D':
24912 case 'A':
24913 return C_Register;
24914 case 'I':
24915 case 'J':
24916 case 'K':
24917 case 'L':
24918 case 'M':
24919 case 'N':
24920 case 'G':
24921 case 'C':
24922 case 'e':
24923 case 'Z':
24924 return C_Other;
24925 default:
24926 break;
24927 }
24928 }
24929 return TargetLowering::getConstraintType(Constraint);
24930 }
24932 /// Examine constraint type and operand type and determine a weight value.
24933 /// This object must already have been set up with the operand type
24934 /// and the current alternative constraint selected.
24935 TargetLowering::ConstraintWeight
24936 X86TargetLowering::getSingleConstraintMatchWeight(
24937 AsmOperandInfo &info, const char *constraint) const {
24938 ConstraintWeight weight = CW_Invalid;
24939 Value *CallOperandVal = info.CallOperandVal;
24940 // If we don't have a value, we can't do a match,
24941 // but allow it at the lowest weight.
24942 if (!CallOperandVal)
24943 return CW_Default;
24944 Type *type = CallOperandVal->getType();
24945 // Look at the constraint type.
24946 switch (*constraint) {
24947 default:
24948 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
24949 case 'R':
24950 case 'q':
24951 case 'Q':
24952 case 'a':
24953 case 'b':
24954 case 'c':
24955 case 'd':
24956 case 'S':
24957 case 'D':
24958 case 'A':
24959 if (CallOperandVal->getType()->isIntegerTy())
24960 weight = CW_SpecificReg;
24961 break;
24962 case 'f':
24963 case 't':
24964 case 'u':
24965 if (type->isFloatingPointTy())
24966 weight = CW_SpecificReg;
24967 break;
24968 case 'y':
24969 if (type->isX86_MMXTy() && Subtarget->hasMMX())
24970 weight = CW_SpecificReg;
24971 break;
24972 case 'x':
24973 case 'Y':
24974 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
24975 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
24976 weight = CW_Register;
24977 break;
24978 case 'I':
24979 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
24980 if (C->getZExtValue() <= 31)
24981 weight = CW_Constant;
24982 }
24983 break;
24984 case 'J':
24985 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24986 if (C->getZExtValue() <= 63)
24987 weight = CW_Constant;
24988 }
24989 break;
24990 case 'K':
24991 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24992 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
24993 weight = CW_Constant;
24994 }
24995 break;
24996 case 'L':
24997 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24998 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
24999 weight = CW_Constant;
25000 }
25001 break;
25002 case 'M':
25003 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25004 if (C->getZExtValue() <= 3)
25005 weight = CW_Constant;
25006 }
25007 break;
25008 case 'N':
25009 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25010 if (C->getZExtValue() <= 0xff)
25011 weight = CW_Constant;
25012 }
25013 break;
25014 case 'G':
25015 case 'C':
25016 if (dyn_cast<ConstantFP>(CallOperandVal)) {
25017 weight = CW_Constant;
25018 }
25019 break;
25020 case 'e':
25021 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25022 if ((C->getSExtValue() >= -0x80000000LL) &&
25023 (C->getSExtValue() <= 0x7fffffffLL))
25024 weight = CW_Constant;
25025 }
25026 break;
25027 case 'Z':
25028 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25029 if (C->getZExtValue() <= 0xffffffff)
25030 weight = CW_Constant;
25031 }
25032 break;
25033 }
25034 return weight;
25035 }
25037 /// LowerXConstraint - try to replace an X constraint, which matches anything,
25038 /// with another that has more specific requirements based on the type of the
25039 /// corresponding operand.
25040 const char *X86TargetLowering::
25041 LowerXConstraint(EVT ConstraintVT) const {
25042 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
25043 // 'f' like normal targets.
25044 if (ConstraintVT.isFloatingPoint()) {
25045 if (Subtarget->hasSSE2())
25046 return "Y";
25047 if (Subtarget->hasSSE1())
25048 return "x";
25049 }
25051 return TargetLowering::LowerXConstraint(ConstraintVT);
25052 }
25054 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
25055 /// vector. If it is invalid, don't add anything to Ops.
25056 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
25057 std::string &Constraint,
25058 std::vector<SDValue>&Ops,
25059 SelectionDAG &DAG) const {
25060 SDValue Result;
25062 // Only support length 1 constraints for now.
25063 if (Constraint.length() > 1) return;
25065 char ConstraintLetter = Constraint[0];
25066 switch (ConstraintLetter) {
25067 default: break;
25068 case 'I':
25069 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25070 if (C->getZExtValue() <= 31) {
25071 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25072 break;
25073 }
25074 }
25075 return;
25076 case 'J':
25077 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25078 if (C->getZExtValue() <= 63) {
25079 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25080 break;
25081 }
25082 }
25083 return;
25084 case 'K':
25085 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25086 if (isInt<8>(C->getSExtValue())) {
25087 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25088 break;
25089 }
25090 }
25091 return;
25092 case 'N':
25093 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25094 if (C->getZExtValue() <= 255) {
25095 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25096 break;
25097 }
25098 }
25099 return;
25100 case 'e': {
25101 // 32-bit signed value
25102 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25103 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25104 C->getSExtValue())) {
25105 // Widen to 64 bits here to get it sign extended.
25106 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
25107 break;
25108 }
25109 // FIXME gcc accepts some relocatable values here too, but only in certain
25110 // memory models; it's complicated.
25111 }
25112 return;
25113 }
25114 case 'Z': {
25115 // 32-bit unsigned value
25116 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25117 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25118 C->getZExtValue())) {
25119 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25120 break;
25121 }
25122 }
25123 // FIXME gcc accepts some relocatable values here too, but only in certain
25124 // memory models; it's complicated.
25125 return;
25126 }
25127 case 'i': {
25128 // Literal immediates are always ok.
25129 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
25130 // Widen to 64 bits here to get it sign extended.
25131 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
25132 break;
25133 }
25135 // In any sort of PIC mode addresses need to be computed at runtime by
25136 // adding in a register or some sort of table lookup. These can't
25137 // be used as immediates.
25138 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
25139 return;
25141 // If we are in non-pic codegen mode, we allow the address of a global (with
25142 // an optional displacement) to be used with 'i'.
25143 GlobalAddressSDNode *GA = nullptr;
25144 int64_t Offset = 0;
25146 // Match either (GA), (GA+C), (GA+C1+C2), etc.
25147 while (1) {
25148 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
25149 Offset += GA->getOffset();
25150 break;
25151 } else if (Op.getOpcode() == ISD::ADD) {
25152 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25153 Offset += C->getZExtValue();
25154 Op = Op.getOperand(0);
25155 continue;
25156 }
25157 } else if (Op.getOpcode() == ISD::SUB) {
25158 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25159 Offset += -C->getZExtValue();
25160 Op = Op.getOperand(0);
25161 continue;
25162 }
25163 }
25165 // Otherwise, this isn't something we can handle, reject it.
25166 return;
25167 }
25169 const GlobalValue *GV = GA->getGlobal();
25170 // If we require an extra load to get this address, as in PIC mode, we
25171 // can't accept it.
25172 if (isGlobalStubReference(
25173 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
25174 return;
25176 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
25177 GA->getValueType(0), Offset);
25178 break;
25179 }
25180 }
25182 if (Result.getNode()) {
25183 Ops.push_back(Result);
25184 return;
25185 }
25186 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
25187 }
25189 std::pair<unsigned, const TargetRegisterClass*>
25190 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
25191 MVT VT) const {
25192 // First, see if this is a constraint that directly corresponds to an LLVM
25193 // register class.
25194 if (Constraint.size() == 1) {
25195 // GCC Constraint Letters
25196 switch (Constraint[0]) {
25197 default: break;
25198 // TODO: Slight differences here in allocation order and leaving
25199 // RIP in the class. Do they matter any more here than they do
25200 // in the normal allocation?
25201 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
25202 if (Subtarget->is64Bit()) {
25203 if (VT == MVT::i32 || VT == MVT::f32)
25204 return std::make_pair(0U, &X86::GR32RegClass);
25205 if (VT == MVT::i16)
25206 return std::make_pair(0U, &X86::GR16RegClass);
25207 if (VT == MVT::i8 || VT == MVT::i1)
25208 return std::make_pair(0U, &X86::GR8RegClass);
25209 if (VT == MVT::i64 || VT == MVT::f64)
25210 return std::make_pair(0U, &X86::GR64RegClass);
25211 break;
25212 }
25213 // 32-bit fallthrough
25214 case 'Q': // Q_REGS
25215 if (VT == MVT::i32 || VT == MVT::f32)
25216 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
25217 if (VT == MVT::i16)
25218 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
25219 if (VT == MVT::i8 || VT == MVT::i1)
25220 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
25221 if (VT == MVT::i64)
25222 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
25223 break;
25224 case 'r': // GENERAL_REGS
25225 case 'l': // INDEX_REGS
25226 if (VT == MVT::i8 || VT == MVT::i1)
25227 return std::make_pair(0U, &X86::GR8RegClass);
25228 if (VT == MVT::i16)
25229 return std::make_pair(0U, &X86::GR16RegClass);
25230 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
25231 return std::make_pair(0U, &X86::GR32RegClass);
25232 return std::make_pair(0U, &X86::GR64RegClass);
25233 case 'R': // LEGACY_REGS
25234 if (VT == MVT::i8 || VT == MVT::i1)
25235 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
25236 if (VT == MVT::i16)
25237 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
25238 if (VT == MVT::i32 || !Subtarget->is64Bit())
25239 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
25240 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
25241 case 'f': // FP Stack registers.
25242 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
25243 // value to the correct fpstack register class.
25244 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
25245 return std::make_pair(0U, &X86::RFP32RegClass);
25246 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
25247 return std::make_pair(0U, &X86::RFP64RegClass);
25248 return std::make_pair(0U, &X86::RFP80RegClass);
25249 case 'y': // MMX_REGS if MMX allowed.
25250 if (!Subtarget->hasMMX()) break;
25251 return std::make_pair(0U, &X86::VR64RegClass);
25252 case 'Y': // SSE_REGS if SSE2 allowed
25253 if (!Subtarget->hasSSE2()) break;
25254 // FALL THROUGH.
25255 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
25256 if (!Subtarget->hasSSE1()) break;
25258 switch (VT.SimpleTy) {
25259 default: break;
25260 // Scalar SSE types.
25261 case MVT::f32:
25262 case MVT::i32:
25263 return std::make_pair(0U, &X86::FR32RegClass);
25264 case MVT::f64:
25265 case MVT::i64:
25266 return std::make_pair(0U, &X86::FR64RegClass);
25267 // Vector types.
25268 case MVT::v16i8:
25269 case MVT::v8i16:
25270 case MVT::v4i32:
25271 case MVT::v2i64:
25272 case MVT::v4f32:
25273 case MVT::v2f64:
25274 return std::make_pair(0U, &X86::VR128RegClass);
25275 // AVX types.
25276 case MVT::v32i8:
25277 case MVT::v16i16:
25278 case MVT::v8i32:
25279 case MVT::v4i64:
25280 case MVT::v8f32:
25281 case MVT::v4f64:
25282 return std::make_pair(0U, &X86::VR256RegClass);
25283 case MVT::v8f64:
25284 case MVT::v16f32:
25285 case MVT::v16i32:
25286 case MVT::v8i64:
25287 return std::make_pair(0U, &X86::VR512RegClass);
25288 }
25289 break;
25290 }
25291 }
25293 // Use the default implementation in TargetLowering to convert the register
25294 // constraint into a member of a register class.
25295 std::pair<unsigned, const TargetRegisterClass*> Res;
25296 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
25298 // Not found as a standard register?
25299 if (!Res.second) {
25300 // Map st(0) -> st(7) -> ST0
25301 if (Constraint.size() == 7 && Constraint[0] == '{' &&
25302 tolower(Constraint[1]) == 's' &&
25303 tolower(Constraint[2]) == 't' &&
25304 Constraint[3] == '(' &&
25305 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
25306 Constraint[5] == ')' &&
25307 Constraint[6] == '}') {
25309 Res.first = X86::FP0+Constraint[4]-'0';
25310 Res.second = &X86::RFP80RegClass;
25311 return Res;
25312 }
25314 // GCC allows "st(0)" to be called just plain "st".
25315 if (StringRef("{st}").equals_lower(Constraint)) {
25316 Res.first = X86::FP0;
25317 Res.second = &X86::RFP80RegClass;
25318 return Res;
25319 }
25321 // flags -> EFLAGS
25322 if (StringRef("{flags}").equals_lower(Constraint)) {
25323 Res.first = X86::EFLAGS;
25324 Res.second = &X86::CCRRegClass;
25325 return Res;
25326 }
25328 // 'A' means EAX + EDX.
25329 if (Constraint == "A") {
25330 Res.first = X86::EAX;
25331 Res.second = &X86::GR32_ADRegClass;
25332 return Res;
25333 }
25334 return Res;
25335 }
25337 // Otherwise, check to see if this is a register class of the wrong value
25338 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
25339 // turn into {ax},{dx}.
25340 if (Res.second->hasType(VT))
25341 return Res; // Correct type already, nothing to do.
25343 // All of the single-register GCC register classes map their values onto
25344 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
25345 // really want an 8-bit or 32-bit register, map to the appropriate register
25346 // class and return the appropriate register.
25347 if (Res.second == &X86::GR16RegClass) {
25348 if (VT == MVT::i8 || VT == MVT::i1) {
25349 unsigned DestReg = 0;
25350 switch (Res.first) {
25351 default: break;
25352 case X86::AX: DestReg = X86::AL; break;
25353 case X86::DX: DestReg = X86::DL; break;
25354 case X86::CX: DestReg = X86::CL; break;
25355 case X86::BX: DestReg = X86::BL; break;
25356 }
25357 if (DestReg) {
25358 Res.first = DestReg;
25359 Res.second = &X86::GR8RegClass;
25360 }
25361 } else if (VT == MVT::i32 || VT == MVT::f32) {
25362 unsigned DestReg = 0;
25363 switch (Res.first) {
25364 default: break;
25365 case X86::AX: DestReg = X86::EAX; break;
25366 case X86::DX: DestReg = X86::EDX; break;
25367 case X86::CX: DestReg = X86::ECX; break;
25368 case X86::BX: DestReg = X86::EBX; break;
25369 case X86::SI: DestReg = X86::ESI; break;
25370 case X86::DI: DestReg = X86::EDI; break;
25371 case X86::BP: DestReg = X86::EBP; break;
25372 case X86::SP: DestReg = X86::ESP; break;
25373 }
25374 if (DestReg) {
25375 Res.first = DestReg;
25376 Res.second = &X86::GR32RegClass;
25377 }
25378 } else if (VT == MVT::i64 || VT == MVT::f64) {
25379 unsigned DestReg = 0;
25380 switch (Res.first) {
25381 default: break;
25382 case X86::AX: DestReg = X86::RAX; break;
25383 case X86::DX: DestReg = X86::RDX; break;
25384 case X86::CX: DestReg = X86::RCX; break;
25385 case X86::BX: DestReg = X86::RBX; break;
25386 case X86::SI: DestReg = X86::RSI; break;
25387 case X86::DI: DestReg = X86::RDI; break;
25388 case X86::BP: DestReg = X86::RBP; break;
25389 case X86::SP: DestReg = X86::RSP; break;
25390 }
25391 if (DestReg) {
25392 Res.first = DestReg;
25393 Res.second = &X86::GR64RegClass;
25394 }
25395 }
25396 } else if (Res.second == &X86::FR32RegClass ||
25397 Res.second == &X86::FR64RegClass ||
25398 Res.second == &X86::VR128RegClass ||
25399 Res.second == &X86::VR256RegClass ||
25400 Res.second == &X86::FR32XRegClass ||
25401 Res.second == &X86::FR64XRegClass ||
25402 Res.second == &X86::VR128XRegClass ||
25403 Res.second == &X86::VR256XRegClass ||
25404 Res.second == &X86::VR512RegClass) {
25405 // Handle references to XMM physical registers that got mapped into the
25406 // wrong class. This can happen with constraints like {xmm0} where the
25407 // target independent register mapper will just pick the first match it can
25408 // find, ignoring the required type.
25410 if (VT == MVT::f32 || VT == MVT::i32)
25411 Res.second = &X86::FR32RegClass;
25412 else if (VT == MVT::f64 || VT == MVT::i64)
25413 Res.second = &X86::FR64RegClass;
25414 else if (X86::VR128RegClass.hasType(VT))
25415 Res.second = &X86::VR128RegClass;
25416 else if (X86::VR256RegClass.hasType(VT))
25417 Res.second = &X86::VR256RegClass;
25418 else if (X86::VR512RegClass.hasType(VT))
25419 Res.second = &X86::VR512RegClass;
25420 }
25422 return Res;
25423 }
25425 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
25426 Type *Ty) const {
25427 // Scaling factors are not free at all.
25428 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
25429 // will take 2 allocations in the out of order engine instead of 1
25430 // for plain addressing mode, i.e. inst (reg1).
25431 // E.g.,
25432 // vaddps (%rsi,%drx), %ymm0, %ymm1
25433 // Requires two allocations (one for the load, one for the computation)
25434 // whereas:
25435 // vaddps (%rsi), %ymm0, %ymm1
25436 // Requires just 1 allocation, i.e., freeing allocations for other operations
25437 // and having less micro operations to execute.
25438 //
25439 // For some X86 architectures, this is even worse because for instance for
25440 // stores, the complex addressing mode forces the instruction to use the
25441 // "load" ports instead of the dedicated "store" port.
25442 // E.g., on Haswell:
25443 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
25444 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
25445 if (isLegalAddressingMode(AM, Ty))
25446 // Scale represents reg2 * scale, thus account for 1
25447 // as soon as we use a second register.
25448 return AM.Scale != 0;
25449 return -1;
25450 }
25452 bool X86TargetLowering::isTargetFTOL() const {
25453 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();
25454 }