1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
54 #include <bitset>
55 #include <numeric>
56 #include <cctype>
57 using namespace llvm;
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
67 cl::Hidden);
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(false),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
72 cl::Hidden);
74 // Forward declarations.
75 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
76 SDValue V2);
78 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
79 SelectionDAG &DAG, SDLoc dl,
80 unsigned vectorWidth) {
81 assert((vectorWidth == 128 || vectorWidth == 256) &&
82 "Unsupported vector width");
83 EVT VT = Vec.getValueType();
84 EVT ElVT = VT.getVectorElementType();
85 unsigned Factor = VT.getSizeInBits()/vectorWidth;
86 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
87 VT.getVectorNumElements()/Factor);
89 // Extract from UNDEF is UNDEF.
90 if (Vec.getOpcode() == ISD::UNDEF)
91 return DAG.getUNDEF(ResultVT);
93 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
94 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
96 // This is the index of the first element of the vectorWidth-bit chunk
97 // we want.
98 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
99 * ElemsPerChunk);
101 // If the input is a buildvector just emit a smaller one.
102 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
103 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
104 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
105 ElemsPerChunk));
107 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
108 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
109 VecIdx);
111 return Result;
113 }
114 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
115 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
116 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
117 /// instructions or a simple subregister reference. Idx is an index in the
118 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
119 /// lowering EXTRACT_VECTOR_ELT operations easier.
120 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
121 SelectionDAG &DAG, SDLoc dl) {
122 assert((Vec.getValueType().is256BitVector() ||
123 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
124 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
125 }
127 /// Generate a DAG to grab 256-bits from a 512-bit vector.
128 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
129 SelectionDAG &DAG, SDLoc dl) {
130 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
131 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
132 }
134 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
135 unsigned IdxVal, SelectionDAG &DAG,
136 SDLoc dl, unsigned vectorWidth) {
137 assert((vectorWidth == 128 || vectorWidth == 256) &&
138 "Unsupported vector width");
139 // Inserting UNDEF is Result
140 if (Vec.getOpcode() == ISD::UNDEF)
141 return Result;
142 EVT VT = Vec.getValueType();
143 EVT ElVT = VT.getVectorElementType();
144 EVT ResultVT = Result.getValueType();
146 // Insert the relevant vectorWidth bits.
147 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
149 // This is the index of the first element of the vectorWidth-bit chunk
150 // we want.
151 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
152 * ElemsPerChunk);
154 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
155 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
156 VecIdx);
157 }
158 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
159 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
160 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
161 /// simple superregister reference. Idx is an index in the 128 bits
162 /// we want. It need not be aligned to a 128-bit bounday. That makes
163 /// lowering INSERT_VECTOR_ELT operations easier.
164 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
165 unsigned IdxVal, SelectionDAG &DAG,
166 SDLoc dl) {
167 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
168 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
169 }
171 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
172 unsigned IdxVal, SelectionDAG &DAG,
173 SDLoc dl) {
174 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
175 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
176 }
178 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
179 /// instructions. This is used because creating CONCAT_VECTOR nodes of
180 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
181 /// large BUILD_VECTORS.
182 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
183 unsigned NumElems, SelectionDAG &DAG,
184 SDLoc dl) {
185 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
186 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
187 }
189 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
190 unsigned NumElems, SelectionDAG &DAG,
191 SDLoc dl) {
192 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
193 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
194 }
196 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
197 if (TT.isOSBinFormatMachO()) {
198 if (TT.getArch() == Triple::x86_64)
199 return new X86_64MachoTargetObjectFile();
200 return new TargetLoweringObjectFileMachO();
201 }
203 if (TT.isOSLinux())
204 return new X86LinuxTargetObjectFile();
205 if (TT.isOSBinFormatELF())
206 return new TargetLoweringObjectFileELF();
207 if (TT.isKnownWindowsMSVCEnvironment())
208 return new X86WindowsTargetObjectFile();
209 if (TT.isOSBinFormatCOFF())
210 return new TargetLoweringObjectFileCOFF();
211 llvm_unreachable("unknown subtarget type");
212 }
214 // FIXME: This should stop caching the target machine as soon as
215 // we can remove resetOperationActions et al.
216 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
217 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
218 Subtarget = &TM.getSubtarget<X86Subtarget>();
219 X86ScalarSSEf64 = Subtarget->hasSSE2();
220 X86ScalarSSEf32 = Subtarget->hasSSE1();
221 TD = getDataLayout();
223 resetOperationActions();
224 }
226 void X86TargetLowering::resetOperationActions() {
227 const TargetMachine &TM = getTargetMachine();
228 static bool FirstTimeThrough = true;
230 // If none of the target options have changed, then we don't need to reset the
231 // operation actions.
232 if (!FirstTimeThrough && TO == TM.Options) return;
234 if (!FirstTimeThrough) {
235 // Reinitialize the actions.
236 initActions();
237 FirstTimeThrough = false;
238 }
240 TO = TM.Options;
242 // Set up the TargetLowering object.
243 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
245 // X86 is weird, it always uses i8 for shift amounts and setcc results.
246 setBooleanContents(ZeroOrOneBooleanContent);
247 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
248 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
250 // For 64-bit since we have so many registers use the ILP scheduler, for
251 // 32-bit code use the register pressure specific scheduling.
252 // For Atom, always use ILP scheduling.
253 if (Subtarget->isAtom())
254 setSchedulingPreference(Sched::ILP);
255 else if (Subtarget->is64Bit())
256 setSchedulingPreference(Sched::ILP);
257 else
258 setSchedulingPreference(Sched::RegPressure);
259 const X86RegisterInfo *RegInfo =
260 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
261 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
263 // Bypass expensive divides on Atom when compiling with O2
264 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
265 addBypassSlowDiv(32, 8);
266 if (Subtarget->is64Bit())
267 addBypassSlowDiv(64, 16);
268 }
270 if (Subtarget->isTargetKnownWindowsMSVC()) {
271 // Setup Windows compiler runtime calls.
272 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
273 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
274 setLibcallName(RTLIB::SREM_I64, "_allrem");
275 setLibcallName(RTLIB::UREM_I64, "_aullrem");
276 setLibcallName(RTLIB::MUL_I64, "_allmul");
277 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
278 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
279 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
280 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
281 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
283 // The _ftol2 runtime function has an unusual calling conv, which
284 // is modeled by a special pseudo-instruction.
285 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
286 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
287 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
288 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
289 }
291 if (Subtarget->isTargetDarwin()) {
292 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
293 setUseUnderscoreSetJmp(false);
294 setUseUnderscoreLongJmp(false);
295 } else if (Subtarget->isTargetWindowsGNU()) {
296 // MS runtime is weird: it exports _setjmp, but longjmp!
297 setUseUnderscoreSetJmp(true);
298 setUseUnderscoreLongJmp(false);
299 } else {
300 setUseUnderscoreSetJmp(true);
301 setUseUnderscoreLongJmp(true);
302 }
304 // Set up the register classes.
305 addRegisterClass(MVT::i8, &X86::GR8RegClass);
306 addRegisterClass(MVT::i16, &X86::GR16RegClass);
307 addRegisterClass(MVT::i32, &X86::GR32RegClass);
308 if (Subtarget->is64Bit())
309 addRegisterClass(MVT::i64, &X86::GR64RegClass);
311 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
313 // We don't accept any truncstore of integer registers.
314 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
315 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
316 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
317 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
318 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
319 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
321 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
323 // SETOEQ and SETUNE require checking two conditions.
324 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
325 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
326 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
327 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
328 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
329 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
331 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
332 // operation.
333 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
334 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
335 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
337 if (Subtarget->is64Bit()) {
338 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
339 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
340 } else if (!TM.Options.UseSoftFloat) {
341 // We have an algorithm for SSE2->double, and we turn this into a
342 // 64-bit FILD followed by conditional FADD for other targets.
343 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
344 // We have an algorithm for SSE2, and we turn this into a 64-bit
345 // FILD for other targets.
346 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
347 }
349 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
350 // this operation.
351 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
352 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
354 if (!TM.Options.UseSoftFloat) {
355 // SSE has no i16 to fp conversion, only i32
356 if (X86ScalarSSEf32) {
357 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
358 // f32 and f64 cases are Legal, f80 case is not
359 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
360 } else {
361 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
362 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
363 }
364 } else {
365 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
366 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
367 }
369 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
370 // are Legal, f80 is custom lowered.
371 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
372 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
374 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
375 // this operation.
376 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
377 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
379 if (X86ScalarSSEf32) {
380 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
381 // f32 and f64 cases are Legal, f80 case is not
382 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
383 } else {
384 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
385 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
386 }
388 // Handle FP_TO_UINT by promoting the destination to a larger signed
389 // conversion.
390 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
391 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
392 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
394 if (Subtarget->is64Bit()) {
395 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
396 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
397 } else if (!TM.Options.UseSoftFloat) {
398 // Since AVX is a superset of SSE3, only check for SSE here.
399 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
400 // Expand FP_TO_UINT into a select.
401 // FIXME: We would like to use a Custom expander here eventually to do
402 // the optimal thing for SSE vs. the default expansion in the legalizer.
403 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
404 else
405 // With SSE3 we can use fisttpll to convert to a signed i64; without
406 // SSE, we're stuck with a fistpll.
407 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
408 }
410 if (isTargetFTOL()) {
411 // Use the _ftol2 runtime function, which has a pseudo-instruction
412 // to handle its weird calling convention.
413 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
414 }
416 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
417 if (!X86ScalarSSEf64) {
418 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
419 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
420 if (Subtarget->is64Bit()) {
421 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
422 // Without SSE, i64->f64 goes through memory.
423 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
424 }
425 }
427 // Scalar integer divide and remainder are lowered to use operations that
428 // produce two results, to match the available instructions. This exposes
429 // the two-result form to trivial CSE, which is able to combine x/y and x%y
430 // into a single instruction.
431 //
432 // Scalar integer multiply-high is also lowered to use two-result
433 // operations, to match the available instructions. However, plain multiply
434 // (low) operations are left as Legal, as there are single-result
435 // instructions for this in x86. Using the two-result multiply instructions
436 // when both high and low results are needed must be arranged by dagcombine.
437 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
438 MVT VT = IntVTs[i];
439 setOperationAction(ISD::MULHS, VT, Expand);
440 setOperationAction(ISD::MULHU, VT, Expand);
441 setOperationAction(ISD::SDIV, VT, Expand);
442 setOperationAction(ISD::UDIV, VT, Expand);
443 setOperationAction(ISD::SREM, VT, Expand);
444 setOperationAction(ISD::UREM, VT, Expand);
446 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
447 setOperationAction(ISD::ADDC, VT, Custom);
448 setOperationAction(ISD::ADDE, VT, Custom);
449 setOperationAction(ISD::SUBC, VT, Custom);
450 setOperationAction(ISD::SUBE, VT, Custom);
451 }
453 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
454 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
455 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
456 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
457 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
458 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
459 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
460 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
461 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
462 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
463 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
464 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
465 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
466 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
467 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
468 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
469 if (Subtarget->is64Bit())
470 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
471 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
472 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
473 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
474 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
475 setOperationAction(ISD::FREM , MVT::f32 , Expand);
476 setOperationAction(ISD::FREM , MVT::f64 , Expand);
477 setOperationAction(ISD::FREM , MVT::f80 , Expand);
478 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
480 // Promote the i8 variants and force them on up to i32 which has a shorter
481 // encoding.
482 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
483 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
484 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
485 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
486 if (Subtarget->hasBMI()) {
487 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
488 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
489 if (Subtarget->is64Bit())
490 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
491 } else {
492 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
493 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
494 if (Subtarget->is64Bit())
495 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
496 }
498 if (Subtarget->hasLZCNT()) {
499 // When promoting the i8 variants, force them to i32 for a shorter
500 // encoding.
501 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
502 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
503 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
504 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
505 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
506 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
507 if (Subtarget->is64Bit())
508 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
509 } else {
510 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
511 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
512 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
513 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
515 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
516 if (Subtarget->is64Bit()) {
517 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
518 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
519 }
520 }
522 // Special handling for half-precision floating point conversions.
523 // If we don't have F16C support, then lower half float conversions
524 // into library calls.
525 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
526 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
527 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
528 }
530 // There's never any support for operations beyond MVT::f32.
531 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
532 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
533 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
534 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
536 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
537 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
538 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
539 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
541 if (Subtarget->hasPOPCNT()) {
542 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
543 } else {
544 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
545 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
546 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
547 if (Subtarget->is64Bit())
548 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
549 }
551 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
553 if (!Subtarget->hasMOVBE())
554 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
556 // These should be promoted to a larger select which is supported.
557 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
558 // X86 wants to expand cmov itself.
559 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
560 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
561 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
562 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
563 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
564 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
565 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
566 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
567 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
568 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
569 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
570 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
571 if (Subtarget->is64Bit()) {
572 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
573 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
574 }
575 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
576 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
577 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
578 // support continuation, user-level threading, and etc.. As a result, no
579 // other SjLj exception interfaces are implemented and please don't build
580 // your own exception handling based on them.
581 // LLVM/Clang supports zero-cost DWARF exception handling.
582 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
583 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
585 // Darwin ABI issue.
586 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
587 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
588 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
589 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
590 if (Subtarget->is64Bit())
591 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
592 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
593 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
594 if (Subtarget->is64Bit()) {
595 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
596 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
597 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
598 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
599 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
600 }
601 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
602 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
603 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
604 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
605 if (Subtarget->is64Bit()) {
606 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
607 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
608 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
609 }
611 if (Subtarget->hasSSE1())
612 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
614 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
616 // Expand certain atomics
617 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
618 MVT VT = IntVTs[i];
619 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
620 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
621 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
622 }
624 if (Subtarget->hasCmpxchg16b()) {
625 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
626 }
628 // FIXME - use subtarget debug flags
629 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
630 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
631 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
632 }
634 if (Subtarget->is64Bit()) {
635 setExceptionPointerRegister(X86::RAX);
636 setExceptionSelectorRegister(X86::RDX);
637 } else {
638 setExceptionPointerRegister(X86::EAX);
639 setExceptionSelectorRegister(X86::EDX);
640 }
641 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
642 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
644 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
645 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
647 setOperationAction(ISD::TRAP, MVT::Other, Legal);
648 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
650 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
651 setOperationAction(ISD::VASTART , MVT::Other, Custom);
652 setOperationAction(ISD::VAEND , MVT::Other, Expand);
653 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
654 // TargetInfo::X86_64ABIBuiltinVaList
655 setOperationAction(ISD::VAARG , MVT::Other, Custom);
656 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
657 } else {
658 // TargetInfo::CharPtrBuiltinVaList
659 setOperationAction(ISD::VAARG , MVT::Other, Expand);
660 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
661 }
663 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
664 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
666 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
668 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
669 // f32 and f64 use SSE.
670 // Set up the FP register classes.
671 addRegisterClass(MVT::f32, &X86::FR32RegClass);
672 addRegisterClass(MVT::f64, &X86::FR64RegClass);
674 // Use ANDPD to simulate FABS.
675 setOperationAction(ISD::FABS , MVT::f64, Custom);
676 setOperationAction(ISD::FABS , MVT::f32, Custom);
678 // Use XORP to simulate FNEG.
679 setOperationAction(ISD::FNEG , MVT::f64, Custom);
680 setOperationAction(ISD::FNEG , MVT::f32, Custom);
682 // Use ANDPD and ORPD to simulate FCOPYSIGN.
683 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
684 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
686 // Lower this to FGETSIGNx86 plus an AND.
687 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
688 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
690 // We don't support sin/cos/fmod
691 setOperationAction(ISD::FSIN , MVT::f64, Expand);
692 setOperationAction(ISD::FCOS , MVT::f64, Expand);
693 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
694 setOperationAction(ISD::FSIN , MVT::f32, Expand);
695 setOperationAction(ISD::FCOS , MVT::f32, Expand);
696 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
698 // Expand FP immediates into loads from the stack, except for the special
699 // cases we handle.
700 addLegalFPImmediate(APFloat(+0.0)); // xorpd
701 addLegalFPImmediate(APFloat(+0.0f)); // xorps
702 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
703 // Use SSE for f32, x87 for f64.
704 // Set up the FP register classes.
705 addRegisterClass(MVT::f32, &X86::FR32RegClass);
706 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
708 // Use ANDPS to simulate FABS.
709 setOperationAction(ISD::FABS , MVT::f32, Custom);
711 // Use XORP to simulate FNEG.
712 setOperationAction(ISD::FNEG , MVT::f32, Custom);
714 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
716 // Use ANDPS and ORPS to simulate FCOPYSIGN.
717 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
718 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
720 // We don't support sin/cos/fmod
721 setOperationAction(ISD::FSIN , MVT::f32, Expand);
722 setOperationAction(ISD::FCOS , MVT::f32, Expand);
723 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
725 // Special cases we handle for FP constants.
726 addLegalFPImmediate(APFloat(+0.0f)); // xorps
727 addLegalFPImmediate(APFloat(+0.0)); // FLD0
728 addLegalFPImmediate(APFloat(+1.0)); // FLD1
729 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
730 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
732 if (!TM.Options.UnsafeFPMath) {
733 setOperationAction(ISD::FSIN , MVT::f64, Expand);
734 setOperationAction(ISD::FCOS , MVT::f64, Expand);
735 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
736 }
737 } else if (!TM.Options.UseSoftFloat) {
738 // f32 and f64 in x87.
739 // Set up the FP register classes.
740 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
741 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
743 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
744 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
745 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
746 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
748 if (!TM.Options.UnsafeFPMath) {
749 setOperationAction(ISD::FSIN , MVT::f64, Expand);
750 setOperationAction(ISD::FSIN , MVT::f32, Expand);
751 setOperationAction(ISD::FCOS , MVT::f64, Expand);
752 setOperationAction(ISD::FCOS , MVT::f32, Expand);
753 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
754 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
755 }
756 addLegalFPImmediate(APFloat(+0.0)); // FLD0
757 addLegalFPImmediate(APFloat(+1.0)); // FLD1
758 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
759 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
760 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
761 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
762 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
763 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
764 }
766 // We don't support FMA.
767 setOperationAction(ISD::FMA, MVT::f64, Expand);
768 setOperationAction(ISD::FMA, MVT::f32, Expand);
770 // Long double always uses X87.
771 if (!TM.Options.UseSoftFloat) {
772 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
773 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
774 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
775 {
776 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
777 addLegalFPImmediate(TmpFlt); // FLD0
778 TmpFlt.changeSign();
779 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
781 bool ignored;
782 APFloat TmpFlt2(+1.0);
783 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
784 &ignored);
785 addLegalFPImmediate(TmpFlt2); // FLD1
786 TmpFlt2.changeSign();
787 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
788 }
790 if (!TM.Options.UnsafeFPMath) {
791 setOperationAction(ISD::FSIN , MVT::f80, Expand);
792 setOperationAction(ISD::FCOS , MVT::f80, Expand);
793 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
794 }
796 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
797 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
798 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
799 setOperationAction(ISD::FRINT, MVT::f80, Expand);
800 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
801 setOperationAction(ISD::FMA, MVT::f80, Expand);
802 }
804 // Always use a library call for pow.
805 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
806 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
807 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
809 setOperationAction(ISD::FLOG, MVT::f80, Expand);
810 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
811 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
812 setOperationAction(ISD::FEXP, MVT::f80, Expand);
813 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
815 // First set operation action for all vector types to either promote
816 // (for widening) or expand (for scalarization). Then we will selectively
817 // turn on ones that can be effectively codegen'd.
818 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
819 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
820 MVT VT = (MVT::SimpleValueType)i;
821 setOperationAction(ISD::ADD , VT, Expand);
822 setOperationAction(ISD::SUB , VT, Expand);
823 setOperationAction(ISD::FADD, VT, Expand);
824 setOperationAction(ISD::FNEG, VT, Expand);
825 setOperationAction(ISD::FSUB, VT, Expand);
826 setOperationAction(ISD::MUL , VT, Expand);
827 setOperationAction(ISD::FMUL, VT, Expand);
828 setOperationAction(ISD::SDIV, VT, Expand);
829 setOperationAction(ISD::UDIV, VT, Expand);
830 setOperationAction(ISD::FDIV, VT, Expand);
831 setOperationAction(ISD::SREM, VT, Expand);
832 setOperationAction(ISD::UREM, VT, Expand);
833 setOperationAction(ISD::LOAD, VT, Expand);
834 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
835 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
836 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
837 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
838 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
839 setOperationAction(ISD::FABS, VT, Expand);
840 setOperationAction(ISD::FSIN, VT, Expand);
841 setOperationAction(ISD::FSINCOS, VT, Expand);
842 setOperationAction(ISD::FCOS, VT, Expand);
843 setOperationAction(ISD::FSINCOS, VT, Expand);
844 setOperationAction(ISD::FREM, VT, Expand);
845 setOperationAction(ISD::FMA, VT, Expand);
846 setOperationAction(ISD::FPOWI, VT, Expand);
847 setOperationAction(ISD::FSQRT, VT, Expand);
848 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
849 setOperationAction(ISD::FFLOOR, VT, Expand);
850 setOperationAction(ISD::FCEIL, VT, Expand);
851 setOperationAction(ISD::FTRUNC, VT, Expand);
852 setOperationAction(ISD::FRINT, VT, Expand);
853 setOperationAction(ISD::FNEARBYINT, VT, Expand);
854 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
855 setOperationAction(ISD::MULHS, VT, Expand);
856 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
857 setOperationAction(ISD::MULHU, VT, Expand);
858 setOperationAction(ISD::SDIVREM, VT, Expand);
859 setOperationAction(ISD::UDIVREM, VT, Expand);
860 setOperationAction(ISD::FPOW, VT, Expand);
861 setOperationAction(ISD::CTPOP, VT, Expand);
862 setOperationAction(ISD::CTTZ, VT, Expand);
863 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
864 setOperationAction(ISD::CTLZ, VT, Expand);
865 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
866 setOperationAction(ISD::SHL, VT, Expand);
867 setOperationAction(ISD::SRA, VT, Expand);
868 setOperationAction(ISD::SRL, VT, Expand);
869 setOperationAction(ISD::ROTL, VT, Expand);
870 setOperationAction(ISD::ROTR, VT, Expand);
871 setOperationAction(ISD::BSWAP, VT, Expand);
872 setOperationAction(ISD::SETCC, VT, Expand);
873 setOperationAction(ISD::FLOG, VT, Expand);
874 setOperationAction(ISD::FLOG2, VT, Expand);
875 setOperationAction(ISD::FLOG10, VT, Expand);
876 setOperationAction(ISD::FEXP, VT, Expand);
877 setOperationAction(ISD::FEXP2, VT, Expand);
878 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
879 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
880 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
881 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
882 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
883 setOperationAction(ISD::TRUNCATE, VT, Expand);
884 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
885 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
886 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
887 setOperationAction(ISD::VSELECT, VT, Expand);
888 setOperationAction(ISD::SELECT_CC, VT, Expand);
889 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
890 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
891 setTruncStoreAction(VT,
892 (MVT::SimpleValueType)InnerVT, Expand);
893 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
894 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
896 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
897 // we have to deal with them whether we ask for Expansion or not. Setting
898 // Expand causes its own optimisation problems though, so leave them legal.
899 if (VT.getVectorElementType() == MVT::i1)
900 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
901 }
903 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
904 // with -msoft-float, disable use of MMX as well.
905 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
906 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
907 // No operations on x86mmx supported, everything uses intrinsics.
908 }
910 // MMX-sized vectors (other than x86mmx) are expected to be expanded
911 // into smaller operations.
912 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
913 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
914 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
915 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
916 setOperationAction(ISD::AND, MVT::v8i8, Expand);
917 setOperationAction(ISD::AND, MVT::v4i16, Expand);
918 setOperationAction(ISD::AND, MVT::v2i32, Expand);
919 setOperationAction(ISD::AND, MVT::v1i64, Expand);
920 setOperationAction(ISD::OR, MVT::v8i8, Expand);
921 setOperationAction(ISD::OR, MVT::v4i16, Expand);
922 setOperationAction(ISD::OR, MVT::v2i32, Expand);
923 setOperationAction(ISD::OR, MVT::v1i64, Expand);
924 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
925 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
926 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
927 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
928 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
929 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
930 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
931 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
932 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
933 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
934 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
935 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
936 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
937 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
938 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
939 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
940 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
942 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
943 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
945 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
946 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
947 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
948 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
949 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
950 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
951 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
952 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
953 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
954 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
955 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
956 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
957 }
959 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
960 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
962 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
963 // registers cannot be used even for integer operations.
964 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
965 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
966 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
967 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
969 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
970 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
971 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
972 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
973 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
974 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
975 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
976 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
977 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
978 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
979 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
980 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
981 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
982 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
983 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
984 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
985 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
986 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
987 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
988 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
989 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
990 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
992 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
993 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
994 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
995 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
997 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
998 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
999 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1000 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1001 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1003 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
1004 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1005 MVT VT = (MVT::SimpleValueType)i;
1006 // Do not attempt to custom lower non-power-of-2 vectors
1007 if (!isPowerOf2_32(VT.getVectorNumElements()))
1008 continue;
1009 // Do not attempt to custom lower non-128-bit vectors
1010 if (!VT.is128BitVector())
1011 continue;
1012 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1013 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1014 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1015 }
1017 // We support custom legalizing of sext and anyext loads for specific
1018 // memory vector types which we can load as a scalar (or sequence of
1019 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1020 // loads these must work with a single scalar load.
1021 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1022 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1023 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1024 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1025 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1026 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1027 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1028 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1029 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1031 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1032 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1033 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1034 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1035 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1036 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1038 if (Subtarget->is64Bit()) {
1039 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1040 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1041 }
1043 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1044 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1045 MVT VT = (MVT::SimpleValueType)i;
1047 // Do not attempt to promote non-128-bit vectors
1048 if (!VT.is128BitVector())
1049 continue;
1051 setOperationAction(ISD::AND, VT, Promote);
1052 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1053 setOperationAction(ISD::OR, VT, Promote);
1054 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1055 setOperationAction(ISD::XOR, VT, Promote);
1056 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1057 setOperationAction(ISD::LOAD, VT, Promote);
1058 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1059 setOperationAction(ISD::SELECT, VT, Promote);
1060 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1061 }
1063 // Custom lower v2i64 and v2f64 selects.
1064 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1065 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1066 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1067 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1069 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1070 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1072 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1073 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1074 // As there is no 64-bit GPR available, we need build a special custom
1075 // sequence to convert from v2i32 to v2f32.
1076 if (!Subtarget->is64Bit())
1077 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1079 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1080 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1082 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1084 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1085 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1086 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1087 }
1089 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1090 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1091 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1092 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1093 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1094 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1095 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1096 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1097 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1098 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1099 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1101 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1102 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1103 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1104 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1105 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1106 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1107 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1108 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1109 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1110 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1112 // FIXME: Do we need to handle scalar-to-vector here?
1113 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1115 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1116 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1117 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1118 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1119 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1120 // There is no BLENDI for byte vectors. We don't need to custom lower
1121 // some vselects for now.
1122 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1124 // SSE41 brings specific instructions for doing vector sign extend even in
1125 // cases where we don't have SRA.
1126 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1127 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1128 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1130 // i8 and i16 vectors are custom because the source register and source
1131 // source memory operand types are not the same width. f32 vectors are
1132 // custom since the immediate controlling the insert encodes additional
1133 // information.
1134 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1135 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1136 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1137 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1139 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1140 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1142 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1144 // FIXME: these should be Legal, but that's only for the case where
1145 // the index is constant. For now custom expand to deal with that.
1146 if (Subtarget->is64Bit()) {
1147 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1148 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1149 }
1150 }
1152 if (Subtarget->hasSSE2()) {
1153 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1154 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1156 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1157 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1159 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1160 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1162 // In the customized shift lowering, the legal cases in AVX2 will be
1163 // recognized.
1164 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1165 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1167 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1168 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1170 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1171 }
1173 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1174 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1175 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1176 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1177 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1178 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1179 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1181 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1182 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1183 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1185 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1186 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1187 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1188 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1189 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1190 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1191 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1192 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1193 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1194 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1195 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1196 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1198 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1199 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1200 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1201 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1202 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1203 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1204 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1205 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1206 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1207 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1208 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1209 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1211 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1212 // even though v8i16 is a legal type.
1213 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1214 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1215 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1217 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1218 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1219 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1221 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1222 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1224 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1226 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1227 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1229 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1230 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1232 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1233 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1235 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1236 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1237 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1238 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1240 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1241 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1242 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1244 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1245 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1246 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1247 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1249 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1250 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1252 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1253 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1254 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1255 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1256 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1257 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1258 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1259 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1260 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1262 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1263 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1264 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1265 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1266 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1267 setOperationAction(ISD::FMA, MVT::f32, Legal);
1268 setOperationAction(ISD::FMA, MVT::f64, Legal);
1269 }
1271 if (Subtarget->hasInt256()) {
1272 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1273 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1274 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1275 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1277 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1278 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1279 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1280 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1282 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1283 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1284 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1285 // Don't lower v32i8 because there is no 128-bit byte mul
1287 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1288 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1289 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1290 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1292 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1293 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1294 } else {
1295 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1296 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1297 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1298 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1300 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1301 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1302 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1303 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1305 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1306 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1307 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1308 // Don't lower v32i8 because there is no 128-bit byte mul
1309 }
1311 // In the customized shift lowering, the legal cases in AVX2 will be
1312 // recognized.
1313 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1314 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1316 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1317 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1319 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1321 // Custom lower several nodes for 256-bit types.
1322 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1323 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1324 MVT VT = (MVT::SimpleValueType)i;
1326 // Extract subvector is special because the value type
1327 // (result) is 128-bit but the source is 256-bit wide.
1328 if (VT.is128BitVector())
1329 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1331 // Do not attempt to custom lower other non-256-bit vectors
1332 if (!VT.is256BitVector())
1333 continue;
1335 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1336 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1337 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1338 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1339 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1340 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1341 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1342 }
1344 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1345 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1346 MVT VT = (MVT::SimpleValueType)i;
1348 // Do not attempt to promote non-256-bit vectors
1349 if (!VT.is256BitVector())
1350 continue;
1352 setOperationAction(ISD::AND, VT, Promote);
1353 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1354 setOperationAction(ISD::OR, VT, Promote);
1355 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1356 setOperationAction(ISD::XOR, VT, Promote);
1357 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1358 setOperationAction(ISD::LOAD, VT, Promote);
1359 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1360 setOperationAction(ISD::SELECT, VT, Promote);
1361 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1362 }
1363 }
1365 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1366 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1367 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1368 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1369 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1371 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1372 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1373 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1375 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1376 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1377 setOperationAction(ISD::XOR, MVT::i1, Legal);
1378 setOperationAction(ISD::OR, MVT::i1, Legal);
1379 setOperationAction(ISD::AND, MVT::i1, Legal);
1380 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1381 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1382 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1383 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1384 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1385 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1387 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1388 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1389 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1390 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1391 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1392 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1394 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1395 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1396 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1397 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1398 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1399 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1400 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1401 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1403 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1404 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1405 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1406 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1407 if (Subtarget->is64Bit()) {
1408 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1409 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1410 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1411 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1412 }
1413 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1414 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1416 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1417 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1420 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1421 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1422 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1424 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1425 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1426 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1427 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1430 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1431 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1434 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1438 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1439 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1443 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1445 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1446 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1448 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1450 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1451 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1452 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1453 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1454 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1455 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1456 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1457 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1458 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1460 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1461 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1463 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1464 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1466 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1468 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1469 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1471 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1472 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1474 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1475 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1477 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1478 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1479 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1480 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1481 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1482 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1484 if (Subtarget->hasCDI()) {
1485 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1486 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1487 }
1489 // Custom lower several nodes.
1490 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1491 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1492 MVT VT = (MVT::SimpleValueType)i;
1494 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1495 // Extract subvector is special because the value type
1496 // (result) is 256/128-bit but the source is 512-bit wide.
1497 if (VT.is128BitVector() || VT.is256BitVector())
1498 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1500 if (VT.getVectorElementType() == MVT::i1)
1501 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1503 // Do not attempt to custom lower other non-512-bit vectors
1504 if (!VT.is512BitVector())
1505 continue;
1507 if ( EltSize >= 32) {
1508 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1509 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1510 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1511 setOperationAction(ISD::VSELECT, VT, Legal);
1512 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1513 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1514 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1515 }
1516 }
1517 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1518 MVT VT = (MVT::SimpleValueType)i;
1520 // Do not attempt to promote non-256-bit vectors
1521 if (!VT.is512BitVector())
1522 continue;
1524 setOperationAction(ISD::SELECT, VT, Promote);
1525 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1526 }
1527 }// has AVX-512
1529 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1530 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1531 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1533 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1534 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1536 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1537 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1538 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1539 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1541 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1542 const MVT VT = (MVT::SimpleValueType)i;
1544 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1546 // Do not attempt to promote non-256-bit vectors
1547 if (!VT.is512BitVector())
1548 continue;
1550 if ( EltSize < 32) {
1551 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1552 setOperationAction(ISD::VSELECT, VT, Legal);
1553 }
1554 }
1555 }
1557 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1558 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1559 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1561 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1562 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1563 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Legal);
1564 }
1566 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1567 // of this type with custom code.
1568 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1569 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1570 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1571 Custom);
1572 }
1574 // We want to custom lower some of our intrinsics.
1575 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1576 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1577 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1578 if (!Subtarget->is64Bit())
1579 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1581 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1582 // handle type legalization for these operations here.
1583 //
1584 // FIXME: We really should do custom legalization for addition and
1585 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1586 // than generic legalization for 64-bit multiplication-with-overflow, though.
1587 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1588 // Add/Sub/Mul with overflow operations are custom lowered.
1589 MVT VT = IntVTs[i];
1590 setOperationAction(ISD::SADDO, VT, Custom);
1591 setOperationAction(ISD::UADDO, VT, Custom);
1592 setOperationAction(ISD::SSUBO, VT, Custom);
1593 setOperationAction(ISD::USUBO, VT, Custom);
1594 setOperationAction(ISD::SMULO, VT, Custom);
1595 setOperationAction(ISD::UMULO, VT, Custom);
1596 }
1598 // There are no 8-bit 3-address imul/mul instructions
1599 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1600 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1602 if (!Subtarget->is64Bit()) {
1603 // These libcalls are not available in 32-bit.
1604 setLibcallName(RTLIB::SHL_I128, nullptr);
1605 setLibcallName(RTLIB::SRL_I128, nullptr);
1606 setLibcallName(RTLIB::SRA_I128, nullptr);
1607 }
1609 // Combine sin / cos into one node or libcall if possible.
1610 if (Subtarget->hasSinCos()) {
1611 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1612 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1613 if (Subtarget->isTargetDarwin()) {
1614 // For MacOSX, we don't want to the normal expansion of a libcall to
1615 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1616 // traffic.
1617 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1618 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1619 }
1620 }
1622 if (Subtarget->isTargetWin64()) {
1623 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1624 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1625 setOperationAction(ISD::SREM, MVT::i128, Custom);
1626 setOperationAction(ISD::UREM, MVT::i128, Custom);
1627 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1628 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1629 }
1631 // We have target-specific dag combine patterns for the following nodes:
1632 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1633 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1634 setTargetDAGCombine(ISD::VSELECT);
1635 setTargetDAGCombine(ISD::SELECT);
1636 setTargetDAGCombine(ISD::SHL);
1637 setTargetDAGCombine(ISD::SRA);
1638 setTargetDAGCombine(ISD::SRL);
1639 setTargetDAGCombine(ISD::OR);
1640 setTargetDAGCombine(ISD::AND);
1641 setTargetDAGCombine(ISD::ADD);
1642 setTargetDAGCombine(ISD::FADD);
1643 setTargetDAGCombine(ISD::FSUB);
1644 setTargetDAGCombine(ISD::FMA);
1645 setTargetDAGCombine(ISD::SUB);
1646 setTargetDAGCombine(ISD::LOAD);
1647 setTargetDAGCombine(ISD::STORE);
1648 setTargetDAGCombine(ISD::ZERO_EXTEND);
1649 setTargetDAGCombine(ISD::ANY_EXTEND);
1650 setTargetDAGCombine(ISD::SIGN_EXTEND);
1651 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1652 setTargetDAGCombine(ISD::TRUNCATE);
1653 setTargetDAGCombine(ISD::SINT_TO_FP);
1654 setTargetDAGCombine(ISD::SETCC);
1655 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1656 setTargetDAGCombine(ISD::BUILD_VECTOR);
1657 if (Subtarget->is64Bit())
1658 setTargetDAGCombine(ISD::MUL);
1659 setTargetDAGCombine(ISD::XOR);
1661 computeRegisterProperties();
1663 // On Darwin, -Os means optimize for size without hurting performance,
1664 // do not reduce the limit.
1665 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1666 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1667 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1668 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1669 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1670 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1671 setPrefLoopAlignment(4); // 2^4 bytes.
1673 // Predictable cmov don't hurt on atom because it's in-order.
1674 PredictableSelectIsExpensive = !Subtarget->isAtom();
1676 setPrefFunctionAlignment(4); // 2^4 bytes.
1678 verifyIntrinsicTables();
1679 }
1681 // This has so far only been implemented for 64-bit MachO.
1682 bool X86TargetLowering::useLoadStackGuardNode() const {
1683 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1684 Subtarget->is64Bit();
1685 }
1687 TargetLoweringBase::LegalizeTypeAction
1688 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1689 if (ExperimentalVectorWideningLegalization &&
1690 VT.getVectorNumElements() != 1 &&
1691 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1692 return TypeWidenVector;
1694 return TargetLoweringBase::getPreferredVectorAction(VT);
1695 }
1697 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1698 if (!VT.isVector())
1699 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1701 const unsigned NumElts = VT.getVectorNumElements();
1702 const EVT EltVT = VT.getVectorElementType();
1703 if (VT.is512BitVector()) {
1704 if (Subtarget->hasAVX512())
1705 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1706 EltVT == MVT::f32 || EltVT == MVT::f64)
1707 switch(NumElts) {
1708 case 8: return MVT::v8i1;
1709 case 16: return MVT::v16i1;
1710 }
1711 if (Subtarget->hasBWI())
1712 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1713 switch(NumElts) {
1714 case 32: return MVT::v32i1;
1715 case 64: return MVT::v64i1;
1716 }
1717 }
1719 if (VT.is256BitVector() || VT.is128BitVector()) {
1720 if (Subtarget->hasVLX())
1721 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1722 EltVT == MVT::f32 || EltVT == MVT::f64)
1723 switch(NumElts) {
1724 case 2: return MVT::v2i1;
1725 case 4: return MVT::v4i1;
1726 case 8: return MVT::v8i1;
1727 }
1728 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1729 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1730 switch(NumElts) {
1731 case 8: return MVT::v8i1;
1732 case 16: return MVT::v16i1;
1733 case 32: return MVT::v32i1;
1734 }
1735 }
1737 return VT.changeVectorElementTypeToInteger();
1738 }
1740 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1741 /// the desired ByVal argument alignment.
1742 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1743 if (MaxAlign == 16)
1744 return;
1745 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1746 if (VTy->getBitWidth() == 128)
1747 MaxAlign = 16;
1748 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1749 unsigned EltAlign = 0;
1750 getMaxByValAlign(ATy->getElementType(), EltAlign);
1751 if (EltAlign > MaxAlign)
1752 MaxAlign = EltAlign;
1753 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1754 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1755 unsigned EltAlign = 0;
1756 getMaxByValAlign(STy->getElementType(i), EltAlign);
1757 if (EltAlign > MaxAlign)
1758 MaxAlign = EltAlign;
1759 if (MaxAlign == 16)
1760 break;
1761 }
1762 }
1763 }
1765 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1766 /// function arguments in the caller parameter area. For X86, aggregates
1767 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1768 /// are at 4-byte boundaries.
1769 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1770 if (Subtarget->is64Bit()) {
1771 // Max of 8 and alignment of type.
1772 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1773 if (TyAlign > 8)
1774 return TyAlign;
1775 return 8;
1776 }
1778 unsigned Align = 4;
1779 if (Subtarget->hasSSE1())
1780 getMaxByValAlign(Ty, Align);
1781 return Align;
1782 }
1784 /// getOptimalMemOpType - Returns the target specific optimal type for load
1785 /// and store operations as a result of memset, memcpy, and memmove
1786 /// lowering. If DstAlign is zero that means it's safe to destination
1787 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1788 /// means there isn't a need to check it against alignment requirement,
1789 /// probably because the source does not need to be loaded. If 'IsMemset' is
1790 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1791 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1792 /// source is constant so it does not need to be loaded.
1793 /// It returns EVT::Other if the type should be determined using generic
1794 /// target-independent logic.
1795 EVT
1796 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1797 unsigned DstAlign, unsigned SrcAlign,
1798 bool IsMemset, bool ZeroMemset,
1799 bool MemcpyStrSrc,
1800 MachineFunction &MF) const {
1801 const Function *F = MF.getFunction();
1802 if ((!IsMemset || ZeroMemset) &&
1803 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1804 Attribute::NoImplicitFloat)) {
1805 if (Size >= 16 &&
1806 (Subtarget->isUnalignedMemAccessFast() ||
1807 ((DstAlign == 0 || DstAlign >= 16) &&
1808 (SrcAlign == 0 || SrcAlign >= 16)))) {
1809 if (Size >= 32) {
1810 if (Subtarget->hasInt256())
1811 return MVT::v8i32;
1812 if (Subtarget->hasFp256())
1813 return MVT::v8f32;
1814 }
1815 if (Subtarget->hasSSE2())
1816 return MVT::v4i32;
1817 if (Subtarget->hasSSE1())
1818 return MVT::v4f32;
1819 } else if (!MemcpyStrSrc && Size >= 8 &&
1820 !Subtarget->is64Bit() &&
1821 Subtarget->hasSSE2()) {
1822 // Do not use f64 to lower memcpy if source is string constant. It's
1823 // better to use i32 to avoid the loads.
1824 return MVT::f64;
1825 }
1826 }
1827 if (Subtarget->is64Bit() && Size >= 8)
1828 return MVT::i64;
1829 return MVT::i32;
1830 }
1832 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1833 if (VT == MVT::f32)
1834 return X86ScalarSSEf32;
1835 else if (VT == MVT::f64)
1836 return X86ScalarSSEf64;
1837 return true;
1838 }
1840 bool
1841 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1842 unsigned,
1843 unsigned,
1844 bool *Fast) const {
1845 if (Fast)
1846 *Fast = Subtarget->isUnalignedMemAccessFast();
1847 return true;
1848 }
1850 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1851 /// current function. The returned value is a member of the
1852 /// MachineJumpTableInfo::JTEntryKind enum.
1853 unsigned X86TargetLowering::getJumpTableEncoding() const {
1854 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1855 // symbol.
1856 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1857 Subtarget->isPICStyleGOT())
1858 return MachineJumpTableInfo::EK_Custom32;
1860 // Otherwise, use the normal jump table encoding heuristics.
1861 return TargetLowering::getJumpTableEncoding();
1862 }
1864 const MCExpr *
1865 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1866 const MachineBasicBlock *MBB,
1867 unsigned uid,MCContext &Ctx) const{
1868 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1869 Subtarget->isPICStyleGOT());
1870 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1871 // entries.
1872 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1873 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1874 }
1876 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1877 /// jumptable.
1878 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1879 SelectionDAG &DAG) const {
1880 if (!Subtarget->is64Bit())
1881 // This doesn't have SDLoc associated with it, but is not really the
1882 // same as a Register.
1883 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1884 return Table;
1885 }
1887 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1888 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1889 /// MCExpr.
1890 const MCExpr *X86TargetLowering::
1891 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1892 MCContext &Ctx) const {
1893 // X86-64 uses RIP relative addressing based on the jump table label.
1894 if (Subtarget->isPICStyleRIPRel())
1895 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1897 // Otherwise, the reference is relative to the PIC base.
1898 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1899 }
1901 // FIXME: Why this routine is here? Move to RegInfo!
1902 std::pair<const TargetRegisterClass*, uint8_t>
1903 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1904 const TargetRegisterClass *RRC = nullptr;
1905 uint8_t Cost = 1;
1906 switch (VT.SimpleTy) {
1907 default:
1908 return TargetLowering::findRepresentativeClass(VT);
1909 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1910 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1911 break;
1912 case MVT::x86mmx:
1913 RRC = &X86::VR64RegClass;
1914 break;
1915 case MVT::f32: case MVT::f64:
1916 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1917 case MVT::v4f32: case MVT::v2f64:
1918 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1919 case MVT::v4f64:
1920 RRC = &X86::VR128RegClass;
1921 break;
1922 }
1923 return std::make_pair(RRC, Cost);
1924 }
1926 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1927 unsigned &Offset) const {
1928 if (!Subtarget->isTargetLinux())
1929 return false;
1931 if (Subtarget->is64Bit()) {
1932 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1933 Offset = 0x28;
1934 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1935 AddressSpace = 256;
1936 else
1937 AddressSpace = 257;
1938 } else {
1939 // %gs:0x14 on i386
1940 Offset = 0x14;
1941 AddressSpace = 256;
1942 }
1943 return true;
1944 }
1946 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1947 unsigned DestAS) const {
1948 assert(SrcAS != DestAS && "Expected different address spaces!");
1950 return SrcAS < 256 && DestAS < 256;
1951 }
1953 //===----------------------------------------------------------------------===//
1954 // Return Value Calling Convention Implementation
1955 //===----------------------------------------------------------------------===//
1957 #include "X86GenCallingConv.inc"
1959 bool
1960 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1961 MachineFunction &MF, bool isVarArg,
1962 const SmallVectorImpl<ISD::OutputArg> &Outs,
1963 LLVMContext &Context) const {
1964 SmallVector<CCValAssign, 16> RVLocs;
1965 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1966 return CCInfo.CheckReturn(Outs, RetCC_X86);
1967 }
1969 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1970 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1971 return ScratchRegs;
1972 }
1974 SDValue
1975 X86TargetLowering::LowerReturn(SDValue Chain,
1976 CallingConv::ID CallConv, bool isVarArg,
1977 const SmallVectorImpl<ISD::OutputArg> &Outs,
1978 const SmallVectorImpl<SDValue> &OutVals,
1979 SDLoc dl, SelectionDAG &DAG) const {
1980 MachineFunction &MF = DAG.getMachineFunction();
1981 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1983 SmallVector<CCValAssign, 16> RVLocs;
1984 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1985 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1987 SDValue Flag;
1988 SmallVector<SDValue, 6> RetOps;
1989 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1990 // Operand #1 = Bytes To Pop
1991 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1992 MVT::i16));
1994 // Copy the result values into the output registers.
1995 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1996 CCValAssign &VA = RVLocs[i];
1997 assert(VA.isRegLoc() && "Can only return in registers!");
1998 SDValue ValToCopy = OutVals[i];
1999 EVT ValVT = ValToCopy.getValueType();
2001 // Promote values to the appropriate types
2002 if (VA.getLocInfo() == CCValAssign::SExt)
2003 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2004 else if (VA.getLocInfo() == CCValAssign::ZExt)
2005 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2006 else if (VA.getLocInfo() == CCValAssign::AExt)
2007 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2008 else if (VA.getLocInfo() == CCValAssign::BCvt)
2009 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2011 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2012 "Unexpected FP-extend for return value.");
2014 // If this is x86-64, and we disabled SSE, we can't return FP values,
2015 // or SSE or MMX vectors.
2016 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2017 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2018 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2019 report_fatal_error("SSE register return with SSE disabled");
2020 }
2021 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2022 // llvm-gcc has never done it right and no one has noticed, so this
2023 // should be OK for now.
2024 if (ValVT == MVT::f64 &&
2025 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2026 report_fatal_error("SSE2 register return with SSE2 disabled");
2028 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2029 // the RET instruction and handled by the FP Stackifier.
2030 if (VA.getLocReg() == X86::FP0 ||
2031 VA.getLocReg() == X86::FP1) {
2032 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2033 // change the value to the FP stack register class.
2034 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2035 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2036 RetOps.push_back(ValToCopy);
2037 // Don't emit a copytoreg.
2038 continue;
2039 }
2041 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2042 // which is returned in RAX / RDX.
2043 if (Subtarget->is64Bit()) {
2044 if (ValVT == MVT::x86mmx) {
2045 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2046 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2047 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2048 ValToCopy);
2049 // If we don't have SSE2 available, convert to v4f32 so the generated
2050 // register is legal.
2051 if (!Subtarget->hasSSE2())
2052 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2053 }
2054 }
2055 }
2057 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2058 Flag = Chain.getValue(1);
2059 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2060 }
2062 // The x86-64 ABIs require that for returning structs by value we copy
2063 // the sret argument into %rax/%eax (depending on ABI) for the return.
2064 // Win32 requires us to put the sret argument to %eax as well.
2065 // We saved the argument into a virtual register in the entry block,
2066 // so now we copy the value out and into %rax/%eax.
2067 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2068 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2069 MachineFunction &MF = DAG.getMachineFunction();
2070 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2071 unsigned Reg = FuncInfo->getSRetReturnReg();
2072 assert(Reg &&
2073 "SRetReturnReg should have been set in LowerFormalArguments().");
2074 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2076 unsigned RetValReg
2077 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2078 X86::RAX : X86::EAX;
2079 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2080 Flag = Chain.getValue(1);
2082 // RAX/EAX now acts like a return value.
2083 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2084 }
2086 RetOps[0] = Chain; // Update chain.
2088 // Add the flag if we have it.
2089 if (Flag.getNode())
2090 RetOps.push_back(Flag);
2092 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2093 }
2095 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2096 if (N->getNumValues() != 1)
2097 return false;
2098 if (!N->hasNUsesOfValue(1, 0))
2099 return false;
2101 SDValue TCChain = Chain;
2102 SDNode *Copy = *N->use_begin();
2103 if (Copy->getOpcode() == ISD::CopyToReg) {
2104 // If the copy has a glue operand, we conservatively assume it isn't safe to
2105 // perform a tail call.
2106 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2107 return false;
2108 TCChain = Copy->getOperand(0);
2109 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2110 return false;
2112 bool HasRet = false;
2113 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2114 UI != UE; ++UI) {
2115 if (UI->getOpcode() != X86ISD::RET_FLAG)
2116 return false;
2117 // If we are returning more than one value, we can definitely
2118 // not make a tail call see PR19530
2119 if (UI->getNumOperands() > 4)
2120 return false;
2121 if (UI->getNumOperands() == 4 &&
2122 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2123 return false;
2124 HasRet = true;
2125 }
2127 if (!HasRet)
2128 return false;
2130 Chain = TCChain;
2131 return true;
2132 }
2134 EVT
2135 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2136 ISD::NodeType ExtendKind) const {
2137 MVT ReturnMVT;
2138 // TODO: Is this also valid on 32-bit?
2139 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2140 ReturnMVT = MVT::i8;
2141 else
2142 ReturnMVT = MVT::i32;
2144 EVT MinVT = getRegisterType(Context, ReturnMVT);
2145 return VT.bitsLT(MinVT) ? MinVT : VT;
2146 }
2148 /// LowerCallResult - Lower the result values of a call into the
2149 /// appropriate copies out of appropriate physical registers.
2150 ///
2151 SDValue
2152 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2153 CallingConv::ID CallConv, bool isVarArg,
2154 const SmallVectorImpl<ISD::InputArg> &Ins,
2155 SDLoc dl, SelectionDAG &DAG,
2156 SmallVectorImpl<SDValue> &InVals) const {
2158 // Assign locations to each value returned by this call.
2159 SmallVector<CCValAssign, 16> RVLocs;
2160 bool Is64Bit = Subtarget->is64Bit();
2161 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2162 *DAG.getContext());
2163 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2165 // Copy all of the result registers out of their specified physreg.
2166 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2167 CCValAssign &VA = RVLocs[i];
2168 EVT CopyVT = VA.getValVT();
2170 // If this is x86-64, and we disabled SSE, we can't return FP values
2171 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2172 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2173 report_fatal_error("SSE register return with SSE disabled");
2174 }
2176 // If we prefer to use the value in xmm registers, copy it out as f80 and
2177 // use a truncate to move it from fp stack reg to xmm reg.
2178 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2179 isScalarFPTypeInSSEReg(VA.getValVT()))
2180 CopyVT = MVT::f80;
2182 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2183 CopyVT, InFlag).getValue(1);
2184 SDValue Val = Chain.getValue(0);
2186 if (CopyVT != VA.getValVT())
2187 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2188 // This truncation won't change the value.
2189 DAG.getIntPtrConstant(1));
2191 InFlag = Chain.getValue(2);
2192 InVals.push_back(Val);
2193 }
2195 return Chain;
2196 }
2198 //===----------------------------------------------------------------------===//
2199 // C & StdCall & Fast Calling Convention implementation
2200 //===----------------------------------------------------------------------===//
2201 // StdCall calling convention seems to be standard for many Windows' API
2202 // routines and around. It differs from C calling convention just a little:
2203 // callee should clean up the stack, not caller. Symbols should be also
2204 // decorated in some fancy way :) It doesn't support any vector arguments.
2205 // For info on fast calling convention see Fast Calling Convention (tail call)
2206 // implementation LowerX86_32FastCCCallTo.
2208 /// CallIsStructReturn - Determines whether a call uses struct return
2209 /// semantics.
2210 enum StructReturnType {
2211 NotStructReturn,
2212 RegStructReturn,
2213 StackStructReturn
2214 };
2215 static StructReturnType
2216 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2217 if (Outs.empty())
2218 return NotStructReturn;
2220 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2221 if (!Flags.isSRet())
2222 return NotStructReturn;
2223 if (Flags.isInReg())
2224 return RegStructReturn;
2225 return StackStructReturn;
2226 }
2228 /// ArgsAreStructReturn - Determines whether a function uses struct
2229 /// return semantics.
2230 static StructReturnType
2231 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2232 if (Ins.empty())
2233 return NotStructReturn;
2235 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2236 if (!Flags.isSRet())
2237 return NotStructReturn;
2238 if (Flags.isInReg())
2239 return RegStructReturn;
2240 return StackStructReturn;
2241 }
2243 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2244 /// by "Src" to address "Dst" with size and alignment information specified by
2245 /// the specific parameter attribute. The copy will be passed as a byval
2246 /// function parameter.
2247 static SDValue
2248 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2249 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2250 SDLoc dl) {
2251 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2253 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2254 /*isVolatile*/false, /*AlwaysInline=*/true,
2255 MachinePointerInfo(), MachinePointerInfo());
2256 }
2258 /// IsTailCallConvention - Return true if the calling convention is one that
2259 /// supports tail call optimization.
2260 static bool IsTailCallConvention(CallingConv::ID CC) {
2261 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2262 CC == CallingConv::HiPE);
2263 }
2265 /// \brief Return true if the calling convention is a C calling convention.
2266 static bool IsCCallConvention(CallingConv::ID CC) {
2267 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2268 CC == CallingConv::X86_64_SysV);
2269 }
2271 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2272 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2273 return false;
2275 CallSite CS(CI);
2276 CallingConv::ID CalleeCC = CS.getCallingConv();
2277 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2278 return false;
2280 return true;
2281 }
2283 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2284 /// a tailcall target by changing its ABI.
2285 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2286 bool GuaranteedTailCallOpt) {
2287 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2288 }
2290 SDValue
2291 X86TargetLowering::LowerMemArgument(SDValue Chain,
2292 CallingConv::ID CallConv,
2293 const SmallVectorImpl<ISD::InputArg> &Ins,
2294 SDLoc dl, SelectionDAG &DAG,
2295 const CCValAssign &VA,
2296 MachineFrameInfo *MFI,
2297 unsigned i) const {
2298 // Create the nodes corresponding to a load from this parameter slot.
2299 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2300 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2301 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2302 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2303 EVT ValVT;
2305 // If value is passed by pointer we have address passed instead of the value
2306 // itself.
2307 if (VA.getLocInfo() == CCValAssign::Indirect)
2308 ValVT = VA.getLocVT();
2309 else
2310 ValVT = VA.getValVT();
2312 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2313 // changed with more analysis.
2314 // In case of tail call optimization mark all arguments mutable. Since they
2315 // could be overwritten by lowering of arguments in case of a tail call.
2316 if (Flags.isByVal()) {
2317 unsigned Bytes = Flags.getByValSize();
2318 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2319 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2320 return DAG.getFrameIndex(FI, getPointerTy());
2321 } else {
2322 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2323 VA.getLocMemOffset(), isImmutable);
2324 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2325 return DAG.getLoad(ValVT, dl, Chain, FIN,
2326 MachinePointerInfo::getFixedStack(FI),
2327 false, false, false, 0);
2328 }
2329 }
2331 // FIXME: Get this from tablegen.
2332 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2333 const X86Subtarget *Subtarget) {
2334 assert(Subtarget->is64Bit());
2336 if (Subtarget->isCallingConvWin64(CallConv)) {
2337 static const MCPhysReg GPR64ArgRegsWin64[] = {
2338 X86::RCX, X86::RDX, X86::R8, X86::R9
2339 };
2340 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2341 }
2343 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2344 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2345 };
2346 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2347 }
2349 // FIXME: Get this from tablegen.
2350 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2351 CallingConv::ID CallConv,
2352 const X86Subtarget *Subtarget) {
2353 assert(Subtarget->is64Bit());
2354 if (Subtarget->isCallingConvWin64(CallConv)) {
2355 // The XMM registers which might contain var arg parameters are shadowed
2356 // in their paired GPR. So we only need to save the GPR to their home
2357 // slots.
2358 // TODO: __vectorcall will change this.
2359 return None;
2360 }
2362 const Function *Fn = MF.getFunction();
2363 bool NoImplicitFloatOps = Fn->getAttributes().
2364 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2365 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2366 "SSE register cannot be used when SSE is disabled!");
2367 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2368 !Subtarget->hasSSE1())
2369 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2370 // registers.
2371 return None;
2373 static const MCPhysReg XMMArgRegs64Bit[] = {
2374 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2375 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2376 };
2377 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2378 }
2380 SDValue
2381 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2382 CallingConv::ID CallConv,
2383 bool isVarArg,
2384 const SmallVectorImpl<ISD::InputArg> &Ins,
2385 SDLoc dl,
2386 SelectionDAG &DAG,
2387 SmallVectorImpl<SDValue> &InVals)
2388 const {
2389 MachineFunction &MF = DAG.getMachineFunction();
2390 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2392 const Function* Fn = MF.getFunction();
2393 if (Fn->hasExternalLinkage() &&
2394 Subtarget->isTargetCygMing() &&
2395 Fn->getName() == "main")
2396 FuncInfo->setForceFramePointer(true);
2398 MachineFrameInfo *MFI = MF.getFrameInfo();
2399 bool Is64Bit = Subtarget->is64Bit();
2400 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2402 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2403 "Var args not supported with calling convention fastcc, ghc or hipe");
2405 // Assign locations to all of the incoming arguments.
2406 SmallVector<CCValAssign, 16> ArgLocs;
2407 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2409 // Allocate shadow area for Win64
2410 if (IsWin64)
2411 CCInfo.AllocateStack(32, 8);
2413 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2415 unsigned LastVal = ~0U;
2416 SDValue ArgValue;
2417 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2418 CCValAssign &VA = ArgLocs[i];
2419 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2420 // places.
2421 assert(VA.getValNo() != LastVal &&
2422 "Don't support value assigned to multiple locs yet");
2423 (void)LastVal;
2424 LastVal = VA.getValNo();
2426 if (VA.isRegLoc()) {
2427 EVT RegVT = VA.getLocVT();
2428 const TargetRegisterClass *RC;
2429 if (RegVT == MVT::i32)
2430 RC = &X86::GR32RegClass;
2431 else if (Is64Bit && RegVT == MVT::i64)
2432 RC = &X86::GR64RegClass;
2433 else if (RegVT == MVT::f32)
2434 RC = &X86::FR32RegClass;
2435 else if (RegVT == MVT::f64)
2436 RC = &X86::FR64RegClass;
2437 else if (RegVT.is512BitVector())
2438 RC = &X86::VR512RegClass;
2439 else if (RegVT.is256BitVector())
2440 RC = &X86::VR256RegClass;
2441 else if (RegVT.is128BitVector())
2442 RC = &X86::VR128RegClass;
2443 else if (RegVT == MVT::x86mmx)
2444 RC = &X86::VR64RegClass;
2445 else if (RegVT == MVT::i1)
2446 RC = &X86::VK1RegClass;
2447 else if (RegVT == MVT::v8i1)
2448 RC = &X86::VK8RegClass;
2449 else if (RegVT == MVT::v16i1)
2450 RC = &X86::VK16RegClass;
2451 else if (RegVT == MVT::v32i1)
2452 RC = &X86::VK32RegClass;
2453 else if (RegVT == MVT::v64i1)
2454 RC = &X86::VK64RegClass;
2455 else
2456 llvm_unreachable("Unknown argument type!");
2458 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2459 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2461 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2462 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2463 // right size.
2464 if (VA.getLocInfo() == CCValAssign::SExt)
2465 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2466 DAG.getValueType(VA.getValVT()));
2467 else if (VA.getLocInfo() == CCValAssign::ZExt)
2468 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2469 DAG.getValueType(VA.getValVT()));
2470 else if (VA.getLocInfo() == CCValAssign::BCvt)
2471 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2473 if (VA.isExtInLoc()) {
2474 // Handle MMX values passed in XMM regs.
2475 if (RegVT.isVector())
2476 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2477 else
2478 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2479 }
2480 } else {
2481 assert(VA.isMemLoc());
2482 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2483 }
2485 // If value is passed via pointer - do a load.
2486 if (VA.getLocInfo() == CCValAssign::Indirect)
2487 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2488 MachinePointerInfo(), false, false, false, 0);
2490 InVals.push_back(ArgValue);
2491 }
2493 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2494 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2495 // The x86-64 ABIs require that for returning structs by value we copy
2496 // the sret argument into %rax/%eax (depending on ABI) for the return.
2497 // Win32 requires us to put the sret argument to %eax as well.
2498 // Save the argument into a virtual register so that we can access it
2499 // from the return points.
2500 if (Ins[i].Flags.isSRet()) {
2501 unsigned Reg = FuncInfo->getSRetReturnReg();
2502 if (!Reg) {
2503 MVT PtrTy = getPointerTy();
2504 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2505 FuncInfo->setSRetReturnReg(Reg);
2506 }
2507 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2508 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2509 break;
2510 }
2511 }
2512 }
2514 unsigned StackSize = CCInfo.getNextStackOffset();
2515 // Align stack specially for tail calls.
2516 if (FuncIsMadeTailCallSafe(CallConv,
2517 MF.getTarget().Options.GuaranteedTailCallOpt))
2518 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2520 // If the function takes variable number of arguments, make a frame index for
2521 // the start of the first vararg value... for expansion of llvm.va_start. We
2522 // can skip this if there are no va_start calls.
2523 if (MFI->hasVAStart() &&
2524 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2525 CallConv != CallingConv::X86_ThisCall))) {
2526 FuncInfo->setVarArgsFrameIndex(
2527 MFI->CreateFixedObject(1, StackSize, true));
2528 }
2530 // 64-bit calling conventions support varargs and register parameters, so we
2531 // have to do extra work to spill them in the prologue or forward them to
2532 // musttail calls.
2533 if (Is64Bit && isVarArg &&
2534 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2535 // Find the first unallocated argument registers.
2536 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2537 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2538 unsigned NumIntRegs =
2539 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2540 unsigned NumXMMRegs =
2541 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2542 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2543 "SSE register cannot be used when SSE is disabled!");
2545 // Gather all the live in physical registers.
2546 SmallVector<SDValue, 6> LiveGPRs;
2547 SmallVector<SDValue, 8> LiveXMMRegs;
2548 SDValue ALVal;
2549 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2550 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2551 LiveGPRs.push_back(
2552 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2553 }
2554 if (!ArgXMMs.empty()) {
2555 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2556 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2557 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2558 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2559 LiveXMMRegs.push_back(
2560 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2561 }
2562 }
2564 // Store them to the va_list returned by va_start.
2565 if (MFI->hasVAStart()) {
2566 if (IsWin64) {
2567 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2568 // Get to the caller-allocated home save location. Add 8 to account
2569 // for the return address.
2570 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2571 FuncInfo->setRegSaveFrameIndex(
2572 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2573 // Fixup to set vararg frame on shadow area (4 x i64).
2574 if (NumIntRegs < 4)
2575 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2576 } else {
2577 // For X86-64, if there are vararg parameters that are passed via
2578 // registers, then we must store them to their spots on the stack so
2579 // they may be loaded by deferencing the result of va_next.
2580 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2581 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2582 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2583 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2584 }
2586 // Store the integer parameter registers.
2587 SmallVector<SDValue, 8> MemOps;
2588 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2589 getPointerTy());
2590 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2591 for (SDValue Val : LiveGPRs) {
2592 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2593 DAG.getIntPtrConstant(Offset));
2594 SDValue Store =
2595 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2596 MachinePointerInfo::getFixedStack(
2597 FuncInfo->getRegSaveFrameIndex(), Offset),
2598 false, false, 0);
2599 MemOps.push_back(Store);
2600 Offset += 8;
2601 }
2603 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2604 // Now store the XMM (fp + vector) parameter registers.
2605 SmallVector<SDValue, 12> SaveXMMOps;
2606 SaveXMMOps.push_back(Chain);
2607 SaveXMMOps.push_back(ALVal);
2608 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2609 FuncInfo->getRegSaveFrameIndex()));
2610 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2611 FuncInfo->getVarArgsFPOffset()));
2612 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2613 LiveXMMRegs.end());
2614 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2615 MVT::Other, SaveXMMOps));
2616 }
2618 if (!MemOps.empty())
2619 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2620 } else {
2621 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2622 // to the liveout set on a musttail call.
2623 assert(MFI->hasMustTailInVarArgFunc());
2624 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2625 typedef X86MachineFunctionInfo::Forward Forward;
2627 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2628 unsigned VReg =
2629 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2630 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2631 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2632 }
2634 if (!ArgXMMs.empty()) {
2635 unsigned ALVReg =
2636 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2637 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2638 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2640 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2641 unsigned VReg =
2642 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2643 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2644 Forwards.push_back(
2645 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2646 }
2647 }
2648 }
2649 }
2651 // Some CCs need callee pop.
2652 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2653 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2654 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2655 } else {
2656 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2657 // If this is an sret function, the return should pop the hidden pointer.
2658 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2659 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2660 argsAreStructReturn(Ins) == StackStructReturn)
2661 FuncInfo->setBytesToPopOnReturn(4);
2662 }
2664 if (!Is64Bit) {
2665 // RegSaveFrameIndex is X86-64 only.
2666 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2667 if (CallConv == CallingConv::X86_FastCall ||
2668 CallConv == CallingConv::X86_ThisCall)
2669 // fastcc functions can't have varargs.
2670 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2671 }
2673 FuncInfo->setArgumentStackSize(StackSize);
2675 return Chain;
2676 }
2678 SDValue
2679 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2680 SDValue StackPtr, SDValue Arg,
2681 SDLoc dl, SelectionDAG &DAG,
2682 const CCValAssign &VA,
2683 ISD::ArgFlagsTy Flags) const {
2684 unsigned LocMemOffset = VA.getLocMemOffset();
2685 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2686 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2687 if (Flags.isByVal())
2688 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2690 return DAG.getStore(Chain, dl, Arg, PtrOff,
2691 MachinePointerInfo::getStack(LocMemOffset),
2692 false, false, 0);
2693 }
2695 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2696 /// optimization is performed and it is required.
2697 SDValue
2698 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2699 SDValue &OutRetAddr, SDValue Chain,
2700 bool IsTailCall, bool Is64Bit,
2701 int FPDiff, SDLoc dl) const {
2702 // Adjust the Return address stack slot.
2703 EVT VT = getPointerTy();
2704 OutRetAddr = getReturnAddressFrameIndex(DAG);
2706 // Load the "old" Return address.
2707 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2708 false, false, false, 0);
2709 return SDValue(OutRetAddr.getNode(), 1);
2710 }
2712 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2713 /// optimization is performed and it is required (FPDiff!=0).
2714 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2715 SDValue Chain, SDValue RetAddrFrIdx,
2716 EVT PtrVT, unsigned SlotSize,
2717 int FPDiff, SDLoc dl) {
2718 // Store the return address to the appropriate stack slot.
2719 if (!FPDiff) return Chain;
2720 // Calculate the new stack slot for the return address.
2721 int NewReturnAddrFI =
2722 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2723 false);
2724 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2725 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2726 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2727 false, false, 0);
2728 return Chain;
2729 }
2731 SDValue
2732 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2733 SmallVectorImpl<SDValue> &InVals) const {
2734 SelectionDAG &DAG = CLI.DAG;
2735 SDLoc &dl = CLI.DL;
2736 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2737 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2738 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2739 SDValue Chain = CLI.Chain;
2740 SDValue Callee = CLI.Callee;
2741 CallingConv::ID CallConv = CLI.CallConv;
2742 bool &isTailCall = CLI.IsTailCall;
2743 bool isVarArg = CLI.IsVarArg;
2745 MachineFunction &MF = DAG.getMachineFunction();
2746 bool Is64Bit = Subtarget->is64Bit();
2747 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2748 StructReturnType SR = callIsStructReturn(Outs);
2749 bool IsSibcall = false;
2750 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2752 if (MF.getTarget().Options.DisableTailCalls)
2753 isTailCall = false;
2755 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2756 if (IsMustTail) {
2757 // Force this to be a tail call. The verifier rules are enough to ensure
2758 // that we can lower this successfully without moving the return address
2759 // around.
2760 isTailCall = true;
2761 } else if (isTailCall) {
2762 // Check if it's really possible to do a tail call.
2763 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2764 isVarArg, SR != NotStructReturn,
2765 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2766 Outs, OutVals, Ins, DAG);
2768 // Sibcalls are automatically detected tailcalls which do not require
2769 // ABI changes.
2770 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2771 IsSibcall = true;
2773 if (isTailCall)
2774 ++NumTailCalls;
2775 }
2777 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2778 "Var args not supported with calling convention fastcc, ghc or hipe");
2780 // Analyze operands of the call, assigning locations to each operand.
2781 SmallVector<CCValAssign, 16> ArgLocs;
2782 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2784 // Allocate shadow area for Win64
2785 if (IsWin64)
2786 CCInfo.AllocateStack(32, 8);
2788 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2790 // Get a count of how many bytes are to be pushed on the stack.
2791 unsigned NumBytes = CCInfo.getNextStackOffset();
2792 if (IsSibcall)
2793 // This is a sibcall. The memory operands are available in caller's
2794 // own caller's stack.
2795 NumBytes = 0;
2796 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2797 IsTailCallConvention(CallConv))
2798 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2800 int FPDiff = 0;
2801 if (isTailCall && !IsSibcall && !IsMustTail) {
2802 // Lower arguments at fp - stackoffset + fpdiff.
2803 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2805 FPDiff = NumBytesCallerPushed - NumBytes;
2807 // Set the delta of movement of the returnaddr stackslot.
2808 // But only set if delta is greater than previous delta.
2809 if (FPDiff < X86Info->getTCReturnAddrDelta())
2810 X86Info->setTCReturnAddrDelta(FPDiff);
2811 }
2813 unsigned NumBytesToPush = NumBytes;
2814 unsigned NumBytesToPop = NumBytes;
2816 // If we have an inalloca argument, all stack space has already been allocated
2817 // for us and be right at the top of the stack. We don't support multiple
2818 // arguments passed in memory when using inalloca.
2819 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2820 NumBytesToPush = 0;
2821 if (!ArgLocs.back().isMemLoc())
2822 report_fatal_error("cannot use inalloca attribute on a register "
2823 "parameter");
2824 if (ArgLocs.back().getLocMemOffset() != 0)
2825 report_fatal_error("any parameter with the inalloca attribute must be "
2826 "the only memory argument");
2827 }
2829 if (!IsSibcall)
2830 Chain = DAG.getCALLSEQ_START(
2831 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2833 SDValue RetAddrFrIdx;
2834 // Load return address for tail calls.
2835 if (isTailCall && FPDiff)
2836 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2837 Is64Bit, FPDiff, dl);
2839 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2840 SmallVector<SDValue, 8> MemOpChains;
2841 SDValue StackPtr;
2843 // Walk the register/memloc assignments, inserting copies/loads. In the case
2844 // of tail call optimization arguments are handle later.
2845 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2846 DAG.getSubtarget().getRegisterInfo());
2847 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2848 // Skip inalloca arguments, they have already been written.
2849 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2850 if (Flags.isInAlloca())
2851 continue;
2853 CCValAssign &VA = ArgLocs[i];
2854 EVT RegVT = VA.getLocVT();
2855 SDValue Arg = OutVals[i];
2856 bool isByVal = Flags.isByVal();
2858 // Promote the value if needed.
2859 switch (VA.getLocInfo()) {
2860 default: llvm_unreachable("Unknown loc info!");
2861 case CCValAssign::Full: break;
2862 case CCValAssign::SExt:
2863 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2864 break;
2865 case CCValAssign::ZExt:
2866 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2867 break;
2868 case CCValAssign::AExt:
2869 if (RegVT.is128BitVector()) {
2870 // Special case: passing MMX values in XMM registers.
2871 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2872 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2873 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2874 } else
2875 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2876 break;
2877 case CCValAssign::BCvt:
2878 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2879 break;
2880 case CCValAssign::Indirect: {
2881 // Store the argument.
2882 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2883 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2884 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2885 MachinePointerInfo::getFixedStack(FI),
2886 false, false, 0);
2887 Arg = SpillSlot;
2888 break;
2889 }
2890 }
2892 if (VA.isRegLoc()) {
2893 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2894 if (isVarArg && IsWin64) {
2895 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2896 // shadow reg if callee is a varargs function.
2897 unsigned ShadowReg = 0;
2898 switch (VA.getLocReg()) {
2899 case X86::XMM0: ShadowReg = X86::RCX; break;
2900 case X86::XMM1: ShadowReg = X86::RDX; break;
2901 case X86::XMM2: ShadowReg = X86::R8; break;
2902 case X86::XMM3: ShadowReg = X86::R9; break;
2903 }
2904 if (ShadowReg)
2905 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2906 }
2907 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2908 assert(VA.isMemLoc());
2909 if (!StackPtr.getNode())
2910 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2911 getPointerTy());
2912 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2913 dl, DAG, VA, Flags));
2914 }
2915 }
2917 if (!MemOpChains.empty())
2918 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2920 if (Subtarget->isPICStyleGOT()) {
2921 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2922 // GOT pointer.
2923 if (!isTailCall) {
2924 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2925 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2926 } else {
2927 // If we are tail calling and generating PIC/GOT style code load the
2928 // address of the callee into ECX. The value in ecx is used as target of
2929 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2930 // for tail calls on PIC/GOT architectures. Normally we would just put the
2931 // address of GOT into ebx and then call target@PLT. But for tail calls
2932 // ebx would be restored (since ebx is callee saved) before jumping to the
2933 // target@PLT.
2935 // Note: The actual moving to ECX is done further down.
2936 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2937 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2938 !G->getGlobal()->hasProtectedVisibility())
2939 Callee = LowerGlobalAddress(Callee, DAG);
2940 else if (isa<ExternalSymbolSDNode>(Callee))
2941 Callee = LowerExternalSymbol(Callee, DAG);
2942 }
2943 }
2945 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2946 // From AMD64 ABI document:
2947 // For calls that may call functions that use varargs or stdargs
2948 // (prototype-less calls or calls to functions containing ellipsis (...) in
2949 // the declaration) %al is used as hidden argument to specify the number
2950 // of SSE registers used. The contents of %al do not need to match exactly
2951 // the number of registers, but must be an ubound on the number of SSE
2952 // registers used and is in the range 0 - 8 inclusive.
2954 // Count the number of XMM registers allocated.
2955 static const MCPhysReg XMMArgRegs[] = {
2956 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2957 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2958 };
2959 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2960 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2961 && "SSE registers cannot be used when SSE is disabled");
2963 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2964 DAG.getConstant(NumXMMRegs, MVT::i8)));
2965 }
2967 if (Is64Bit && isVarArg && IsMustTail) {
2968 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2969 for (const auto &F : Forwards) {
2970 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2971 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2972 }
2973 }
2975 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2976 // don't need this because the eligibility check rejects calls that require
2977 // shuffling arguments passed in memory.
2978 if (!IsSibcall && isTailCall) {
2979 // Force all the incoming stack arguments to be loaded from the stack
2980 // before any new outgoing arguments are stored to the stack, because the
2981 // outgoing stack slots may alias the incoming argument stack slots, and
2982 // the alias isn't otherwise explicit. This is slightly more conservative
2983 // than necessary, because it means that each store effectively depends
2984 // on every argument instead of just those arguments it would clobber.
2985 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2987 SmallVector<SDValue, 8> MemOpChains2;
2988 SDValue FIN;
2989 int FI = 0;
2990 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2991 CCValAssign &VA = ArgLocs[i];
2992 if (VA.isRegLoc())
2993 continue;
2994 assert(VA.isMemLoc());
2995 SDValue Arg = OutVals[i];
2996 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2997 // Skip inalloca arguments. They don't require any work.
2998 if (Flags.isInAlloca())
2999 continue;
3000 // Create frame index.
3001 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3002 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3003 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3004 FIN = DAG.getFrameIndex(FI, getPointerTy());
3006 if (Flags.isByVal()) {
3007 // Copy relative to framepointer.
3008 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3009 if (!StackPtr.getNode())
3010 StackPtr = DAG.getCopyFromReg(Chain, dl,
3011 RegInfo->getStackRegister(),
3012 getPointerTy());
3013 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3015 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3016 ArgChain,
3017 Flags, DAG, dl));
3018 } else {
3019 // Store relative to framepointer.
3020 MemOpChains2.push_back(
3021 DAG.getStore(ArgChain, dl, Arg, FIN,
3022 MachinePointerInfo::getFixedStack(FI),
3023 false, false, 0));
3024 }
3025 }
3027 if (!MemOpChains2.empty())
3028 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3030 // Store the return address to the appropriate stack slot.
3031 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3032 getPointerTy(), RegInfo->getSlotSize(),
3033 FPDiff, dl);
3034 }
3036 // Build a sequence of copy-to-reg nodes chained together with token chain
3037 // and flag operands which copy the outgoing args into registers.
3038 SDValue InFlag;
3039 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3040 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3041 RegsToPass[i].second, InFlag);
3042 InFlag = Chain.getValue(1);
3043 }
3045 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3046 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3047 // In the 64-bit large code model, we have to make all calls
3048 // through a register, since the call instruction's 32-bit
3049 // pc-relative offset may not be large enough to hold the whole
3050 // address.
3051 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3052 // If the callee is a GlobalAddress node (quite common, every direct call
3053 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3054 // it.
3056 // We should use extra load for direct calls to dllimported functions in
3057 // non-JIT mode.
3058 const GlobalValue *GV = G->getGlobal();
3059 if (!GV->hasDLLImportStorageClass()) {
3060 unsigned char OpFlags = 0;
3061 bool ExtraLoad = false;
3062 unsigned WrapperKind = ISD::DELETED_NODE;
3064 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3065 // external symbols most go through the PLT in PIC mode. If the symbol
3066 // has hidden or protected visibility, or if it is static or local, then
3067 // we don't need to use the PLT - we can directly call it.
3068 if (Subtarget->isTargetELF() &&
3069 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3070 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3071 OpFlags = X86II::MO_PLT;
3072 } else if (Subtarget->isPICStyleStubAny() &&
3073 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3074 (!Subtarget->getTargetTriple().isMacOSX() ||
3075 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3076 // PC-relative references to external symbols should go through $stub,
3077 // unless we're building with the leopard linker or later, which
3078 // automatically synthesizes these stubs.
3079 OpFlags = X86II::MO_DARWIN_STUB;
3080 } else if (Subtarget->isPICStyleRIPRel() &&
3081 isa<Function>(GV) &&
3082 cast<Function>(GV)->getAttributes().
3083 hasAttribute(AttributeSet::FunctionIndex,
3084 Attribute::NonLazyBind)) {
3085 // If the function is marked as non-lazy, generate an indirect call
3086 // which loads from the GOT directly. This avoids runtime overhead
3087 // at the cost of eager binding (and one extra byte of encoding).
3088 OpFlags = X86II::MO_GOTPCREL;
3089 WrapperKind = X86ISD::WrapperRIP;
3090 ExtraLoad = true;
3091 }
3093 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3094 G->getOffset(), OpFlags);
3096 // Add a wrapper if needed.
3097 if (WrapperKind != ISD::DELETED_NODE)
3098 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3099 // Add extra indirection if needed.
3100 if (ExtraLoad)
3101 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3102 MachinePointerInfo::getGOT(),
3103 false, false, false, 0);
3104 }
3105 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3106 unsigned char OpFlags = 0;
3108 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3109 // external symbols should go through the PLT.
3110 if (Subtarget->isTargetELF() &&
3111 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3112 OpFlags = X86II::MO_PLT;
3113 } else if (Subtarget->isPICStyleStubAny() &&
3114 (!Subtarget->getTargetTriple().isMacOSX() ||
3115 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3116 // PC-relative references to external symbols should go through $stub,
3117 // unless we're building with the leopard linker or later, which
3118 // automatically synthesizes these stubs.
3119 OpFlags = X86II::MO_DARWIN_STUB;
3120 }
3122 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3123 OpFlags);
3124 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3125 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3126 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3127 }
3129 // Returns a chain & a flag for retval copy to use.
3130 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3131 SmallVector<SDValue, 8> Ops;
3133 if (!IsSibcall && isTailCall) {
3134 Chain = DAG.getCALLSEQ_END(Chain,
3135 DAG.getIntPtrConstant(NumBytesToPop, true),
3136 DAG.getIntPtrConstant(0, true), InFlag, dl);
3137 InFlag = Chain.getValue(1);
3138 }
3140 Ops.push_back(Chain);
3141 Ops.push_back(Callee);
3143 if (isTailCall)
3144 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3146 // Add argument registers to the end of the list so that they are known live
3147 // into the call.
3148 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3149 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3150 RegsToPass[i].second.getValueType()));
3152 // Add a register mask operand representing the call-preserved registers.
3153 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3154 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3155 assert(Mask && "Missing call preserved mask for calling convention");
3156 Ops.push_back(DAG.getRegisterMask(Mask));
3158 if (InFlag.getNode())
3159 Ops.push_back(InFlag);
3161 if (isTailCall) {
3162 // We used to do:
3163 //// If this is the first return lowered for this function, add the regs
3164 //// to the liveout set for the function.
3165 // This isn't right, although it's probably harmless on x86; liveouts
3166 // should be computed from returns not tail calls. Consider a void
3167 // function making a tail call to a function returning int.
3168 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3169 }
3171 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3172 InFlag = Chain.getValue(1);
3174 // Create the CALLSEQ_END node.
3175 unsigned NumBytesForCalleeToPop;
3176 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3177 DAG.getTarget().Options.GuaranteedTailCallOpt))
3178 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3179 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3180 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3181 SR == StackStructReturn)
3182 // If this is a call to a struct-return function, the callee
3183 // pops the hidden struct pointer, so we have to push it back.
3184 // This is common for Darwin/X86, Linux & Mingw32 targets.
3185 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3186 NumBytesForCalleeToPop = 4;
3187 else
3188 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3190 // Returns a flag for retval copy to use.
3191 if (!IsSibcall) {
3192 Chain = DAG.getCALLSEQ_END(Chain,
3193 DAG.getIntPtrConstant(NumBytesToPop, true),
3194 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3195 true),
3196 InFlag, dl);
3197 InFlag = Chain.getValue(1);
3198 }
3200 // Handle result values, copying them out of physregs into vregs that we
3201 // return.
3202 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3203 Ins, dl, DAG, InVals);
3204 }
3206 //===----------------------------------------------------------------------===//
3207 // Fast Calling Convention (tail call) implementation
3208 //===----------------------------------------------------------------------===//
3210 // Like std call, callee cleans arguments, convention except that ECX is
3211 // reserved for storing the tail called function address. Only 2 registers are
3212 // free for argument passing (inreg). Tail call optimization is performed
3213 // provided:
3214 // * tailcallopt is enabled
3215 // * caller/callee are fastcc
3216 // On X86_64 architecture with GOT-style position independent code only local
3217 // (within module) calls are supported at the moment.
3218 // To keep the stack aligned according to platform abi the function
3219 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3220 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3221 // If a tail called function callee has more arguments than the caller the
3222 // caller needs to make sure that there is room to move the RETADDR to. This is
3223 // achieved by reserving an area the size of the argument delta right after the
3224 // original RETADDR, but before the saved framepointer or the spilled registers
3225 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3226 // stack layout:
3227 // arg1
3228 // arg2
3229 // RETADDR
3230 // [ new RETADDR
3231 // move area ]
3232 // (possible EBP)
3233 // ESI
3234 // EDI
3235 // local1 ..
3237 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3238 /// for a 16 byte align requirement.
3239 unsigned
3240 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3241 SelectionDAG& DAG) const {
3242 MachineFunction &MF = DAG.getMachineFunction();
3243 const TargetMachine &TM = MF.getTarget();
3244 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3245 TM.getSubtargetImpl()->getRegisterInfo());
3246 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3247 unsigned StackAlignment = TFI.getStackAlignment();
3248 uint64_t AlignMask = StackAlignment - 1;
3249 int64_t Offset = StackSize;
3250 unsigned SlotSize = RegInfo->getSlotSize();
3251 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3252 // Number smaller than 12 so just add the difference.
3253 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3254 } else {
3255 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3256 Offset = ((~AlignMask) & Offset) + StackAlignment +
3257 (StackAlignment-SlotSize);
3258 }
3259 return Offset;
3260 }
3262 /// MatchingStackOffset - Return true if the given stack call argument is
3263 /// already available in the same position (relatively) of the caller's
3264 /// incoming argument stack.
3265 static
3266 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3267 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3268 const X86InstrInfo *TII) {
3269 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3270 int FI = INT_MAX;
3271 if (Arg.getOpcode() == ISD::CopyFromReg) {
3272 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3273 if (!TargetRegisterInfo::isVirtualRegister(VR))
3274 return false;
3275 MachineInstr *Def = MRI->getVRegDef(VR);
3276 if (!Def)
3277 return false;
3278 if (!Flags.isByVal()) {
3279 if (!TII->isLoadFromStackSlot(Def, FI))
3280 return false;
3281 } else {
3282 unsigned Opcode = Def->getOpcode();
3283 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3284 Def->getOperand(1).isFI()) {
3285 FI = Def->getOperand(1).getIndex();
3286 Bytes = Flags.getByValSize();
3287 } else
3288 return false;
3289 }
3290 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3291 if (Flags.isByVal())
3292 // ByVal argument is passed in as a pointer but it's now being
3293 // dereferenced. e.g.
3294 // define @foo(%struct.X* %A) {
3295 // tail call @bar(%struct.X* byval %A)
3296 // }
3297 return false;
3298 SDValue Ptr = Ld->getBasePtr();
3299 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3300 if (!FINode)
3301 return false;
3302 FI = FINode->getIndex();
3303 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3304 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3305 FI = FINode->getIndex();
3306 Bytes = Flags.getByValSize();
3307 } else
3308 return false;
3310 assert(FI != INT_MAX);
3311 if (!MFI->isFixedObjectIndex(FI))
3312 return false;
3313 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3314 }
3316 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3317 /// for tail call optimization. Targets which want to do tail call
3318 /// optimization should implement this function.
3319 bool
3320 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3321 CallingConv::ID CalleeCC,
3322 bool isVarArg,
3323 bool isCalleeStructRet,
3324 bool isCallerStructRet,
3325 Type *RetTy,
3326 const SmallVectorImpl<ISD::OutputArg> &Outs,
3327 const SmallVectorImpl<SDValue> &OutVals,
3328 const SmallVectorImpl<ISD::InputArg> &Ins,
3329 SelectionDAG &DAG) const {
3330 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3331 return false;
3333 // If -tailcallopt is specified, make fastcc functions tail-callable.
3334 const MachineFunction &MF = DAG.getMachineFunction();
3335 const Function *CallerF = MF.getFunction();
3337 // If the function return type is x86_fp80 and the callee return type is not,
3338 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3339 // perform a tailcall optimization here.
3340 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3341 return false;
3343 CallingConv::ID CallerCC = CallerF->getCallingConv();
3344 bool CCMatch = CallerCC == CalleeCC;
3345 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3346 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3348 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3349 if (IsTailCallConvention(CalleeCC) && CCMatch)
3350 return true;
3351 return false;
3352 }
3354 // Look for obvious safe cases to perform tail call optimization that do not
3355 // require ABI changes. This is what gcc calls sibcall.
3357 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3358 // emit a special epilogue.
3359 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3360 DAG.getSubtarget().getRegisterInfo());
3361 if (RegInfo->needsStackRealignment(MF))
3362 return false;
3364 // Also avoid sibcall optimization if either caller or callee uses struct
3365 // return semantics.
3366 if (isCalleeStructRet || isCallerStructRet)
3367 return false;
3369 // An stdcall/thiscall caller is expected to clean up its arguments; the
3370 // callee isn't going to do that.
3371 // FIXME: this is more restrictive than needed. We could produce a tailcall
3372 // when the stack adjustment matches. For example, with a thiscall that takes
3373 // only one argument.
3374 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3375 CallerCC == CallingConv::X86_ThisCall))
3376 return false;
3378 // Do not sibcall optimize vararg calls unless all arguments are passed via
3379 // registers.
3380 if (isVarArg && !Outs.empty()) {
3382 // Optimizing for varargs on Win64 is unlikely to be safe without
3383 // additional testing.
3384 if (IsCalleeWin64 || IsCallerWin64)
3385 return false;
3387 SmallVector<CCValAssign, 16> ArgLocs;
3388 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3389 *DAG.getContext());
3391 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3392 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3393 if (!ArgLocs[i].isRegLoc())
3394 return false;
3395 }
3397 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3398 // stack. Therefore, if it's not used by the call it is not safe to optimize
3399 // this into a sibcall.
3400 bool Unused = false;
3401 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3402 if (!Ins[i].Used) {
3403 Unused = true;
3404 break;
3405 }
3406 }
3407 if (Unused) {
3408 SmallVector<CCValAssign, 16> RVLocs;
3409 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3410 *DAG.getContext());
3411 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3412 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3413 CCValAssign &VA = RVLocs[i];
3414 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3415 return false;
3416 }
3417 }
3419 // If the calling conventions do not match, then we'd better make sure the
3420 // results are returned in the same way as what the caller expects.
3421 if (!CCMatch) {
3422 SmallVector<CCValAssign, 16> RVLocs1;
3423 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3424 *DAG.getContext());
3425 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3427 SmallVector<CCValAssign, 16> RVLocs2;
3428 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3429 *DAG.getContext());
3430 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3432 if (RVLocs1.size() != RVLocs2.size())
3433 return false;
3434 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3435 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3436 return false;
3437 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3438 return false;
3439 if (RVLocs1[i].isRegLoc()) {
3440 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3441 return false;
3442 } else {
3443 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3444 return false;
3445 }
3446 }
3447 }
3449 // If the callee takes no arguments then go on to check the results of the
3450 // call.
3451 if (!Outs.empty()) {
3452 // Check if stack adjustment is needed. For now, do not do this if any
3453 // argument is passed on the stack.
3454 SmallVector<CCValAssign, 16> ArgLocs;
3455 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3456 *DAG.getContext());
3458 // Allocate shadow area for Win64
3459 if (IsCalleeWin64)
3460 CCInfo.AllocateStack(32, 8);
3462 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3463 if (CCInfo.getNextStackOffset()) {
3464 MachineFunction &MF = DAG.getMachineFunction();
3465 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3466 return false;
3468 // Check if the arguments are already laid out in the right way as
3469 // the caller's fixed stack objects.
3470 MachineFrameInfo *MFI = MF.getFrameInfo();
3471 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3472 const X86InstrInfo *TII =
3473 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3474 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3475 CCValAssign &VA = ArgLocs[i];
3476 SDValue Arg = OutVals[i];
3477 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3478 if (VA.getLocInfo() == CCValAssign::Indirect)
3479 return false;
3480 if (!VA.isRegLoc()) {
3481 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3482 MFI, MRI, TII))
3483 return false;
3484 }
3485 }
3486 }
3488 // If the tailcall address may be in a register, then make sure it's
3489 // possible to register allocate for it. In 32-bit, the call address can
3490 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3491 // callee-saved registers are restored. These happen to be the same
3492 // registers used to pass 'inreg' arguments so watch out for those.
3493 if (!Subtarget->is64Bit() &&
3494 ((!isa<GlobalAddressSDNode>(Callee) &&
3495 !isa<ExternalSymbolSDNode>(Callee)) ||
3496 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3497 unsigned NumInRegs = 0;
3498 // In PIC we need an extra register to formulate the address computation
3499 // for the callee.
3500 unsigned MaxInRegs =
3501 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3503 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3504 CCValAssign &VA = ArgLocs[i];
3505 if (!VA.isRegLoc())
3506 continue;
3507 unsigned Reg = VA.getLocReg();
3508 switch (Reg) {
3509 default: break;
3510 case X86::EAX: case X86::EDX: case X86::ECX:
3511 if (++NumInRegs == MaxInRegs)
3512 return false;
3513 break;
3514 }
3515 }
3516 }
3517 }
3519 return true;
3520 }
3522 FastISel *
3523 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3524 const TargetLibraryInfo *libInfo) const {
3525 return X86::createFastISel(funcInfo, libInfo);
3526 }
3528 //===----------------------------------------------------------------------===//
3529 // Other Lowering Hooks
3530 //===----------------------------------------------------------------------===//
3532 static bool MayFoldLoad(SDValue Op) {
3533 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3534 }
3536 static bool MayFoldIntoStore(SDValue Op) {
3537 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3538 }
3540 static bool isTargetShuffle(unsigned Opcode) {
3541 switch(Opcode) {
3542 default: return false;
3543 case X86ISD::BLENDI:
3544 case X86ISD::PSHUFB:
3545 case X86ISD::PSHUFD:
3546 case X86ISD::PSHUFHW:
3547 case X86ISD::PSHUFLW:
3548 case X86ISD::SHUFP:
3549 case X86ISD::PALIGNR:
3550 case X86ISD::MOVLHPS:
3551 case X86ISD::MOVLHPD:
3552 case X86ISD::MOVHLPS:
3553 case X86ISD::MOVLPS:
3554 case X86ISD::MOVLPD:
3555 case X86ISD::MOVSHDUP:
3556 case X86ISD::MOVSLDUP:
3557 case X86ISD::MOVDDUP:
3558 case X86ISD::MOVSS:
3559 case X86ISD::MOVSD:
3560 case X86ISD::UNPCKL:
3561 case X86ISD::UNPCKH:
3562 case X86ISD::VPERMILPI:
3563 case X86ISD::VPERM2X128:
3564 case X86ISD::VPERMI:
3565 return true;
3566 }
3567 }
3569 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3570 SDValue V1, SelectionDAG &DAG) {
3571 switch(Opc) {
3572 default: llvm_unreachable("Unknown x86 shuffle node");
3573 case X86ISD::MOVSHDUP:
3574 case X86ISD::MOVSLDUP:
3575 case X86ISD::MOVDDUP:
3576 return DAG.getNode(Opc, dl, VT, V1);
3577 }
3578 }
3580 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3581 SDValue V1, unsigned TargetMask,
3582 SelectionDAG &DAG) {
3583 switch(Opc) {
3584 default: llvm_unreachable("Unknown x86 shuffle node");
3585 case X86ISD::PSHUFD:
3586 case X86ISD::PSHUFHW:
3587 case X86ISD::PSHUFLW:
3588 case X86ISD::VPERMILPI:
3589 case X86ISD::VPERMI:
3590 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3591 }
3592 }
3594 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3595 SDValue V1, SDValue V2, unsigned TargetMask,
3596 SelectionDAG &DAG) {
3597 switch(Opc) {
3598 default: llvm_unreachable("Unknown x86 shuffle node");
3599 case X86ISD::PALIGNR:
3600 case X86ISD::VALIGN:
3601 case X86ISD::SHUFP:
3602 case X86ISD::VPERM2X128:
3603 return DAG.getNode(Opc, dl, VT, V1, V2,
3604 DAG.getConstant(TargetMask, MVT::i8));
3605 }
3606 }
3608 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3609 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3610 switch(Opc) {
3611 default: llvm_unreachable("Unknown x86 shuffle node");
3612 case X86ISD::MOVLHPS:
3613 case X86ISD::MOVLHPD:
3614 case X86ISD::MOVHLPS:
3615 case X86ISD::MOVLPS:
3616 case X86ISD::MOVLPD:
3617 case X86ISD::MOVSS:
3618 case X86ISD::MOVSD:
3619 case X86ISD::UNPCKL:
3620 case X86ISD::UNPCKH:
3621 return DAG.getNode(Opc, dl, VT, V1, V2);
3622 }
3623 }
3625 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3626 MachineFunction &MF = DAG.getMachineFunction();
3627 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3628 DAG.getSubtarget().getRegisterInfo());
3629 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3630 int ReturnAddrIndex = FuncInfo->getRAIndex();
3632 if (ReturnAddrIndex == 0) {
3633 // Set up a frame object for the return address.
3634 unsigned SlotSize = RegInfo->getSlotSize();
3635 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3636 -(int64_t)SlotSize,
3637 false);
3638 FuncInfo->setRAIndex(ReturnAddrIndex);
3639 }
3641 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3642 }
3644 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3645 bool hasSymbolicDisplacement) {
3646 // Offset should fit into 32 bit immediate field.
3647 if (!isInt<32>(Offset))
3648 return false;
3650 // If we don't have a symbolic displacement - we don't have any extra
3651 // restrictions.
3652 if (!hasSymbolicDisplacement)
3653 return true;
3655 // FIXME: Some tweaks might be needed for medium code model.
3656 if (M != CodeModel::Small && M != CodeModel::Kernel)
3657 return false;
3659 // For small code model we assume that latest object is 16MB before end of 31
3660 // bits boundary. We may also accept pretty large negative constants knowing
3661 // that all objects are in the positive half of address space.
3662 if (M == CodeModel::Small && Offset < 16*1024*1024)
3663 return true;
3665 // For kernel code model we know that all object resist in the negative half
3666 // of 32bits address space. We may not accept negative offsets, since they may
3667 // be just off and we may accept pretty large positive ones.
3668 if (M == CodeModel::Kernel && Offset > 0)
3669 return true;
3671 return false;
3672 }
3674 /// isCalleePop - Determines whether the callee is required to pop its
3675 /// own arguments. Callee pop is necessary to support tail calls.
3676 bool X86::isCalleePop(CallingConv::ID CallingConv,
3677 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3678 switch (CallingConv) {
3679 default:
3680 return false;
3681 case CallingConv::X86_StdCall:
3682 case CallingConv::X86_FastCall:
3683 case CallingConv::X86_ThisCall:
3684 return !is64Bit;
3685 case CallingConv::Fast:
3686 case CallingConv::GHC:
3687 case CallingConv::HiPE:
3688 if (IsVarArg)
3689 return false;
3690 return TailCallOpt;
3691 }
3692 }
3694 /// \brief Return true if the condition is an unsigned comparison operation.
3695 static bool isX86CCUnsigned(unsigned X86CC) {
3696 switch (X86CC) {
3697 default: llvm_unreachable("Invalid integer condition!");
3698 case X86::COND_E: return true;
3699 case X86::COND_G: return false;
3700 case X86::COND_GE: return false;
3701 case X86::COND_L: return false;
3702 case X86::COND_LE: return false;
3703 case X86::COND_NE: return true;
3704 case X86::COND_B: return true;
3705 case X86::COND_A: return true;
3706 case X86::COND_BE: return true;
3707 case X86::COND_AE: return true;
3708 }
3709 llvm_unreachable("covered switch fell through?!");
3710 }
3712 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3713 /// specific condition code, returning the condition code and the LHS/RHS of the
3714 /// comparison to make.
3715 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3716 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3717 if (!isFP) {
3718 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3719 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3720 // X > -1 -> X == 0, jump !sign.
3721 RHS = DAG.getConstant(0, RHS.getValueType());
3722 return X86::COND_NS;
3723 }
3724 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3725 // X < 0 -> X == 0, jump on sign.
3726 return X86::COND_S;
3727 }
3728 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3729 // X < 1 -> X <= 0
3730 RHS = DAG.getConstant(0, RHS.getValueType());
3731 return X86::COND_LE;
3732 }
3733 }
3735 switch (SetCCOpcode) {
3736 default: llvm_unreachable("Invalid integer condition!");
3737 case ISD::SETEQ: return X86::COND_E;
3738 case ISD::SETGT: return X86::COND_G;
3739 case ISD::SETGE: return X86::COND_GE;
3740 case ISD::SETLT: return X86::COND_L;
3741 case ISD::SETLE: return X86::COND_LE;
3742 case ISD::SETNE: return X86::COND_NE;
3743 case ISD::SETULT: return X86::COND_B;
3744 case ISD::SETUGT: return X86::COND_A;
3745 case ISD::SETULE: return X86::COND_BE;
3746 case ISD::SETUGE: return X86::COND_AE;
3747 }
3748 }
3750 // First determine if it is required or is profitable to flip the operands.
3752 // If LHS is a foldable load, but RHS is not, flip the condition.
3753 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3754 !ISD::isNON_EXTLoad(RHS.getNode())) {
3755 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3756 std::swap(LHS, RHS);
3757 }
3759 switch (SetCCOpcode) {
3760 default: break;
3761 case ISD::SETOLT:
3762 case ISD::SETOLE:
3763 case ISD::SETUGT:
3764 case ISD::SETUGE:
3765 std::swap(LHS, RHS);
3766 break;
3767 }
3769 // On a floating point condition, the flags are set as follows:
3770 // ZF PF CF op
3771 // 0 | 0 | 0 | X > Y
3772 // 0 | 0 | 1 | X < Y
3773 // 1 | 0 | 0 | X == Y
3774 // 1 | 1 | 1 | unordered
3775 switch (SetCCOpcode) {
3776 default: llvm_unreachable("Condcode should be pre-legalized away");
3777 case ISD::SETUEQ:
3778 case ISD::SETEQ: return X86::COND_E;
3779 case ISD::SETOLT: // flipped
3780 case ISD::SETOGT:
3781 case ISD::SETGT: return X86::COND_A;
3782 case ISD::SETOLE: // flipped
3783 case ISD::SETOGE:
3784 case ISD::SETGE: return X86::COND_AE;
3785 case ISD::SETUGT: // flipped
3786 case ISD::SETULT:
3787 case ISD::SETLT: return X86::COND_B;
3788 case ISD::SETUGE: // flipped
3789 case ISD::SETULE:
3790 case ISD::SETLE: return X86::COND_BE;
3791 case ISD::SETONE:
3792 case ISD::SETNE: return X86::COND_NE;
3793 case ISD::SETUO: return X86::COND_P;
3794 case ISD::SETO: return X86::COND_NP;
3795 case ISD::SETOEQ:
3796 case ISD::SETUNE: return X86::COND_INVALID;
3797 }
3798 }
3800 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3801 /// code. Current x86 isa includes the following FP cmov instructions:
3802 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3803 static bool hasFPCMov(unsigned X86CC) {
3804 switch (X86CC) {
3805 default:
3806 return false;
3807 case X86::COND_B:
3808 case X86::COND_BE:
3809 case X86::COND_E:
3810 case X86::COND_P:
3811 case X86::COND_A:
3812 case X86::COND_AE:
3813 case X86::COND_NE:
3814 case X86::COND_NP:
3815 return true;
3816 }
3817 }
3819 /// isFPImmLegal - Returns true if the target can instruction select the
3820 /// specified FP immediate natively. If false, the legalizer will
3821 /// materialize the FP immediate as a load from a constant pool.
3822 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3823 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3824 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3825 return true;
3826 }
3827 return false;
3828 }
3830 /// \brief Returns true if it is beneficial to convert a load of a constant
3831 /// to just the constant itself.
3832 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3833 Type *Ty) const {
3834 assert(Ty->isIntegerTy());
3836 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3837 if (BitSize == 0 || BitSize > 64)
3838 return false;
3839 return true;
3840 }
3842 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3843 /// the specified range (L, H].
3844 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3845 return (Val < 0) || (Val >= Low && Val < Hi);
3846 }
3848 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3849 /// specified value.
3850 static bool isUndefOrEqual(int Val, int CmpVal) {
3851 return (Val < 0 || Val == CmpVal);
3852 }
3854 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3855 /// from position Pos and ending in Pos+Size, falls within the specified
3856 /// sequential range (L, L+Pos]. or is undef.
3857 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3858 unsigned Pos, unsigned Size, int Low) {
3859 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3860 if (!isUndefOrEqual(Mask[i], Low))
3861 return false;
3862 return true;
3863 }
3865 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3866 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3867 /// the second operand.
3868 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3869 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3870 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3871 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3872 return (Mask[0] < 2 && Mask[1] < 2);
3873 return false;
3874 }
3876 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3877 /// is suitable for input to PSHUFHW.
3878 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3879 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3880 return false;
3882 // Lower quadword copied in order or undef.
3883 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3884 return false;
3886 // Upper quadword shuffled.
3887 for (unsigned i = 4; i != 8; ++i)
3888 if (!isUndefOrInRange(Mask[i], 4, 8))
3889 return false;
3891 if (VT == MVT::v16i16) {
3892 // Lower quadword copied in order or undef.
3893 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3894 return false;
3896 // Upper quadword shuffled.
3897 for (unsigned i = 12; i != 16; ++i)
3898 if (!isUndefOrInRange(Mask[i], 12, 16))
3899 return false;
3900 }
3902 return true;
3903 }
3905 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3906 /// is suitable for input to PSHUFLW.
3907 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3908 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3909 return false;
3911 // Upper quadword copied in order.
3912 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3913 return false;
3915 // Lower quadword shuffled.
3916 for (unsigned i = 0; i != 4; ++i)
3917 if (!isUndefOrInRange(Mask[i], 0, 4))
3918 return false;
3920 if (VT == MVT::v16i16) {
3921 // Upper quadword copied in order.
3922 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3923 return false;
3925 // Lower quadword shuffled.
3926 for (unsigned i = 8; i != 12; ++i)
3927 if (!isUndefOrInRange(Mask[i], 8, 12))
3928 return false;
3929 }
3931 return true;
3932 }
3934 /// \brief Return true if the mask specifies a shuffle of elements that is
3935 /// suitable for input to intralane (palignr) or interlane (valign) vector
3936 /// right-shift.
3937 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3938 unsigned NumElts = VT.getVectorNumElements();
3939 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3940 unsigned NumLaneElts = NumElts/NumLanes;
3942 // Do not handle 64-bit element shuffles with palignr.
3943 if (NumLaneElts == 2)
3944 return false;
3946 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3947 unsigned i;
3948 for (i = 0; i != NumLaneElts; ++i) {
3949 if (Mask[i+l] >= 0)
3950 break;
3951 }
3953 // Lane is all undef, go to next lane
3954 if (i == NumLaneElts)
3955 continue;
3957 int Start = Mask[i+l];
3959 // Make sure its in this lane in one of the sources
3960 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3961 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3962 return false;
3964 // If not lane 0, then we must match lane 0
3965 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3966 return false;
3968 // Correct second source to be contiguous with first source
3969 if (Start >= (int)NumElts)
3970 Start -= NumElts - NumLaneElts;
3972 // Make sure we're shifting in the right direction.
3973 if (Start <= (int)(i+l))
3974 return false;
3976 Start -= i;
3978 // Check the rest of the elements to see if they are consecutive.
3979 for (++i; i != NumLaneElts; ++i) {
3980 int Idx = Mask[i+l];
3982 // Make sure its in this lane
3983 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3984 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3985 return false;
3987 // If not lane 0, then we must match lane 0
3988 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3989 return false;
3991 if (Idx >= (int)NumElts)
3992 Idx -= NumElts - NumLaneElts;
3994 if (!isUndefOrEqual(Idx, Start+i))
3995 return false;
3997 }
3998 }
4000 return true;
4001 }
4003 /// \brief Return true if the node specifies a shuffle of elements that is
4004 /// suitable for input to PALIGNR.
4005 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4006 const X86Subtarget *Subtarget) {
4007 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4008 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4009 VT.is512BitVector())
4010 // FIXME: Add AVX512BW.
4011 return false;
4013 return isAlignrMask(Mask, VT, false);
4014 }
4016 /// \brief Return true if the node specifies a shuffle of elements that is
4017 /// suitable for input to VALIGN.
4018 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4019 const X86Subtarget *Subtarget) {
4020 // FIXME: Add AVX512VL.
4021 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4022 return false;
4023 return isAlignrMask(Mask, VT, true);
4024 }
4026 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4027 /// the two vector operands have swapped position.
4028 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4029 unsigned NumElems) {
4030 for (unsigned i = 0; i != NumElems; ++i) {
4031 int idx = Mask[i];
4032 if (idx < 0)
4033 continue;
4034 else if (idx < (int)NumElems)
4035 Mask[i] = idx + NumElems;
4036 else
4037 Mask[i] = idx - NumElems;
4038 }
4039 }
4041 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4042 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4043 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4044 /// reverse of what x86 shuffles want.
4045 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4047 unsigned NumElems = VT.getVectorNumElements();
4048 unsigned NumLanes = VT.getSizeInBits()/128;
4049 unsigned NumLaneElems = NumElems/NumLanes;
4051 if (NumLaneElems != 2 && NumLaneElems != 4)
4052 return false;
4054 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4055 bool symetricMaskRequired =
4056 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4058 // VSHUFPSY divides the resulting vector into 4 chunks.
4059 // The sources are also splitted into 4 chunks, and each destination
4060 // chunk must come from a different source chunk.
4061 //
4062 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4063 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4064 //
4065 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4066 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4067 //
4068 // VSHUFPDY divides the resulting vector into 4 chunks.
4069 // The sources are also splitted into 4 chunks, and each destination
4070 // chunk must come from a different source chunk.
4071 //
4072 // SRC1 => X3 X2 X1 X0
4073 // SRC2 => Y3 Y2 Y1 Y0
4074 //
4075 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4076 //
4077 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4078 unsigned HalfLaneElems = NumLaneElems/2;
4079 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4080 for (unsigned i = 0; i != NumLaneElems; ++i) {
4081 int Idx = Mask[i+l];
4082 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4083 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4084 return false;
4085 // For VSHUFPSY, the mask of the second half must be the same as the
4086 // first but with the appropriate offsets. This works in the same way as
4087 // VPERMILPS works with masks.
4088 if (!symetricMaskRequired || Idx < 0)
4089 continue;
4090 if (MaskVal[i] < 0) {
4091 MaskVal[i] = Idx - l;
4092 continue;
4093 }
4094 if ((signed)(Idx - l) != MaskVal[i])
4095 return false;
4096 }
4097 }
4099 return true;
4100 }
4102 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4103 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4104 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4105 if (!VT.is128BitVector())
4106 return false;
4108 unsigned NumElems = VT.getVectorNumElements();
4110 if (NumElems != 4)
4111 return false;
4113 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4114 return isUndefOrEqual(Mask[0], 6) &&
4115 isUndefOrEqual(Mask[1], 7) &&
4116 isUndefOrEqual(Mask[2], 2) &&
4117 isUndefOrEqual(Mask[3], 3);
4118 }
4120 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4121 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4122 /// <2, 3, 2, 3>
4123 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4124 if (!VT.is128BitVector())
4125 return false;
4127 unsigned NumElems = VT.getVectorNumElements();
4129 if (NumElems != 4)
4130 return false;
4132 return isUndefOrEqual(Mask[0], 2) &&
4133 isUndefOrEqual(Mask[1], 3) &&
4134 isUndefOrEqual(Mask[2], 2) &&
4135 isUndefOrEqual(Mask[3], 3);
4136 }
4138 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4139 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4140 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4141 if (!VT.is128BitVector())
4142 return false;
4144 unsigned NumElems = VT.getVectorNumElements();
4146 if (NumElems != 2 && NumElems != 4)
4147 return false;
4149 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4150 if (!isUndefOrEqual(Mask[i], i + NumElems))
4151 return false;
4153 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4154 if (!isUndefOrEqual(Mask[i], i))
4155 return false;
4157 return true;
4158 }
4160 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4161 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4162 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4163 if (!VT.is128BitVector())
4164 return false;
4166 unsigned NumElems = VT.getVectorNumElements();
4168 if (NumElems != 2 && NumElems != 4)
4169 return false;
4171 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4172 if (!isUndefOrEqual(Mask[i], i))
4173 return false;
4175 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4176 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4177 return false;
4179 return true;
4180 }
4182 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4183 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4184 /// i. e: If all but one element come from the same vector.
4185 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4186 // TODO: Deal with AVX's VINSERTPS
4187 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4188 return false;
4190 unsigned CorrectPosV1 = 0;
4191 unsigned CorrectPosV2 = 0;
4192 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4193 if (Mask[i] == -1) {
4194 ++CorrectPosV1;
4195 ++CorrectPosV2;
4196 continue;
4197 }
4199 if (Mask[i] == i)
4200 ++CorrectPosV1;
4201 else if (Mask[i] == i + 4)
4202 ++CorrectPosV2;
4203 }
4205 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4206 // We have 3 elements (undefs count as elements from any vector) from one
4207 // vector, and one from another.
4208 return true;
4210 return false;
4211 }
4213 //
4214 // Some special combinations that can be optimized.
4215 //
4216 static
4217 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4218 SelectionDAG &DAG) {
4219 MVT VT = SVOp->getSimpleValueType(0);
4220 SDLoc dl(SVOp);
4222 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4223 return SDValue();
4225 ArrayRef<int> Mask = SVOp->getMask();
4227 // These are the special masks that may be optimized.
4228 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4229 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4230 bool MatchEvenMask = true;
4231 bool MatchOddMask = true;
4232 for (int i=0; i<8; ++i) {
4233 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4234 MatchEvenMask = false;
4235 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4236 MatchOddMask = false;
4237 }
4239 if (!MatchEvenMask && !MatchOddMask)
4240 return SDValue();
4242 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4244 SDValue Op0 = SVOp->getOperand(0);
4245 SDValue Op1 = SVOp->getOperand(1);
4247 if (MatchEvenMask) {
4248 // Shift the second operand right to 32 bits.
4249 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4250 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4251 } else {
4252 // Shift the first operand left to 32 bits.
4253 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4254 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4255 }
4256 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4257 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4258 }
4260 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4261 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4262 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4263 bool HasInt256, bool V2IsSplat = false) {
4265 assert(VT.getSizeInBits() >= 128 &&
4266 "Unsupported vector type for unpckl");
4268 unsigned NumElts = VT.getVectorNumElements();
4269 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4270 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4271 return false;
4273 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4274 "Unsupported vector type for unpckh");
4276 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4277 unsigned NumLanes = VT.getSizeInBits()/128;
4278 unsigned NumLaneElts = NumElts/NumLanes;
4280 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4281 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4282 int BitI = Mask[l+i];
4283 int BitI1 = Mask[l+i+1];
4284 if (!isUndefOrEqual(BitI, j))
4285 return false;
4286 if (V2IsSplat) {
4287 if (!isUndefOrEqual(BitI1, NumElts))
4288 return false;
4289 } else {
4290 if (!isUndefOrEqual(BitI1, j + NumElts))
4291 return false;
4292 }
4293 }
4294 }
4296 return true;
4297 }
4299 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4300 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4301 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4302 bool HasInt256, bool V2IsSplat = false) {
4303 assert(VT.getSizeInBits() >= 128 &&
4304 "Unsupported vector type for unpckh");
4306 unsigned NumElts = VT.getVectorNumElements();
4307 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4308 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4309 return false;
4311 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4312 "Unsupported vector type for unpckh");
4314 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4315 unsigned NumLanes = VT.getSizeInBits()/128;
4316 unsigned NumLaneElts = NumElts/NumLanes;
4318 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4319 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4320 int BitI = Mask[l+i];
4321 int BitI1 = Mask[l+i+1];
4322 if (!isUndefOrEqual(BitI, j))
4323 return false;
4324 if (V2IsSplat) {
4325 if (isUndefOrEqual(BitI1, NumElts))
4326 return false;
4327 } else {
4328 if (!isUndefOrEqual(BitI1, j+NumElts))
4329 return false;
4330 }
4331 }
4332 }
4333 return true;
4334 }
4336 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4337 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4338 /// <0, 0, 1, 1>
4339 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4340 unsigned NumElts = VT.getVectorNumElements();
4341 bool Is256BitVec = VT.is256BitVector();
4343 if (VT.is512BitVector())
4344 return false;
4345 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4346 "Unsupported vector type for unpckh");
4348 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4349 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4350 return false;
4352 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4353 // FIXME: Need a better way to get rid of this, there's no latency difference
4354 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4355 // the former later. We should also remove the "_undef" special mask.
4356 if (NumElts == 4 && Is256BitVec)
4357 return false;
4359 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4360 // independently on 128-bit lanes.
4361 unsigned NumLanes = VT.getSizeInBits()/128;
4362 unsigned NumLaneElts = NumElts/NumLanes;
4364 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4365 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4366 int BitI = Mask[l+i];
4367 int BitI1 = Mask[l+i+1];
4369 if (!isUndefOrEqual(BitI, j))
4370 return false;
4371 if (!isUndefOrEqual(BitI1, j))
4372 return false;
4373 }
4374 }
4376 return true;
4377 }
4379 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4380 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4381 /// <2, 2, 3, 3>
4382 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4383 unsigned NumElts = VT.getVectorNumElements();
4385 if (VT.is512BitVector())
4386 return false;
4388 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4389 "Unsupported vector type for unpckh");
4391 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4392 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4393 return false;
4395 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4396 // independently on 128-bit lanes.
4397 unsigned NumLanes = VT.getSizeInBits()/128;
4398 unsigned NumLaneElts = NumElts/NumLanes;
4400 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4401 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4402 int BitI = Mask[l+i];
4403 int BitI1 = Mask[l+i+1];
4404 if (!isUndefOrEqual(BitI, j))
4405 return false;
4406 if (!isUndefOrEqual(BitI1, j))
4407 return false;
4408 }
4409 }
4410 return true;
4411 }
4413 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4414 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4415 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4416 if (!VT.is512BitVector())
4417 return false;
4419 unsigned NumElts = VT.getVectorNumElements();
4420 unsigned HalfSize = NumElts/2;
4421 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4422 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4423 *Imm = 1;
4424 return true;
4425 }
4426 }
4427 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4428 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4429 *Imm = 0;
4430 return true;
4431 }
4432 }
4433 return false;
4434 }
4436 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4437 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4438 /// MOVSD, and MOVD, i.e. setting the lowest element.
4439 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4440 if (VT.getVectorElementType().getSizeInBits() < 32)
4441 return false;
4442 if (!VT.is128BitVector())
4443 return false;
4445 unsigned NumElts = VT.getVectorNumElements();
4447 if (!isUndefOrEqual(Mask[0], NumElts))
4448 return false;
4450 for (unsigned i = 1; i != NumElts; ++i)
4451 if (!isUndefOrEqual(Mask[i], i))
4452 return false;
4454 return true;
4455 }
4457 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4458 /// as permutations between 128-bit chunks or halves. As an example: this
4459 /// shuffle bellow:
4460 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4461 /// The first half comes from the second half of V1 and the second half from the
4462 /// the second half of V2.
4463 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4464 if (!HasFp256 || !VT.is256BitVector())
4465 return false;
4467 // The shuffle result is divided into half A and half B. In total the two
4468 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4469 // B must come from C, D, E or F.
4470 unsigned HalfSize = VT.getVectorNumElements()/2;
4471 bool MatchA = false, MatchB = false;
4473 // Check if A comes from one of C, D, E, F.
4474 for (unsigned Half = 0; Half != 4; ++Half) {
4475 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4476 MatchA = true;
4477 break;
4478 }
4479 }
4481 // Check if B comes from one of C, D, E, F.
4482 for (unsigned Half = 0; Half != 4; ++Half) {
4483 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4484 MatchB = true;
4485 break;
4486 }
4487 }
4489 return MatchA && MatchB;
4490 }
4492 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4493 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4494 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4495 MVT VT = SVOp->getSimpleValueType(0);
4497 unsigned HalfSize = VT.getVectorNumElements()/2;
4499 unsigned FstHalf = 0, SndHalf = 0;
4500 for (unsigned i = 0; i < HalfSize; ++i) {
4501 if (SVOp->getMaskElt(i) > 0) {
4502 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4503 break;
4504 }
4505 }
4506 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4507 if (SVOp->getMaskElt(i) > 0) {
4508 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4509 break;
4510 }
4511 }
4513 return (FstHalf | (SndHalf << 4));
4514 }
4516 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4517 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4518 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4519 if (EltSize < 32)
4520 return false;
4522 unsigned NumElts = VT.getVectorNumElements();
4523 Imm8 = 0;
4524 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4525 for (unsigned i = 0; i != NumElts; ++i) {
4526 if (Mask[i] < 0)
4527 continue;
4528 Imm8 |= Mask[i] << (i*2);
4529 }
4530 return true;
4531 }
4533 unsigned LaneSize = 4;
4534 SmallVector<int, 4> MaskVal(LaneSize, -1);
4536 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4537 for (unsigned i = 0; i != LaneSize; ++i) {
4538 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4539 return false;
4540 if (Mask[i+l] < 0)
4541 continue;
4542 if (MaskVal[i] < 0) {
4543 MaskVal[i] = Mask[i+l] - l;
4544 Imm8 |= MaskVal[i] << (i*2);
4545 continue;
4546 }
4547 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4548 return false;
4549 }
4550 }
4551 return true;
4552 }
4554 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4555 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4556 /// Note that VPERMIL mask matching is different depending whether theunderlying
4557 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4558 /// to the same elements of the low, but to the higher half of the source.
4559 /// In VPERMILPD the two lanes could be shuffled independently of each other
4560 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4561 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4562 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4563 if (VT.getSizeInBits() < 256 || EltSize < 32)
4564 return false;
4565 bool symetricMaskRequired = (EltSize == 32);
4566 unsigned NumElts = VT.getVectorNumElements();
4568 unsigned NumLanes = VT.getSizeInBits()/128;
4569 unsigned LaneSize = NumElts/NumLanes;
4570 // 2 or 4 elements in one lane
4572 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4573 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4574 for (unsigned i = 0; i != LaneSize; ++i) {
4575 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4576 return false;
4577 if (symetricMaskRequired) {
4578 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4579 ExpectedMaskVal[i] = Mask[i+l] - l;
4580 continue;
4581 }
4582 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4583 return false;
4584 }
4585 }
4586 }
4587 return true;
4588 }
4590 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4591 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4592 /// element of vector 2 and the other elements to come from vector 1 in order.
4593 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4594 bool V2IsSplat = false, bool V2IsUndef = false) {
4595 if (!VT.is128BitVector())
4596 return false;
4598 unsigned NumOps = VT.getVectorNumElements();
4599 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4600 return false;
4602 if (!isUndefOrEqual(Mask[0], 0))
4603 return false;
4605 for (unsigned i = 1; i != NumOps; ++i)
4606 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4607 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4608 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4609 return false;
4611 return true;
4612 }
4614 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4615 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4616 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4617 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4618 const X86Subtarget *Subtarget) {
4619 if (!Subtarget->hasSSE3())
4620 return false;
4622 unsigned NumElems = VT.getVectorNumElements();
4624 if ((VT.is128BitVector() && NumElems != 4) ||
4625 (VT.is256BitVector() && NumElems != 8) ||
4626 (VT.is512BitVector() && NumElems != 16))
4627 return false;
4629 // "i+1" is the value the indexed mask element must have
4630 for (unsigned i = 0; i != NumElems; i += 2)
4631 if (!isUndefOrEqual(Mask[i], i+1) ||
4632 !isUndefOrEqual(Mask[i+1], i+1))
4633 return false;
4635 return true;
4636 }
4638 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4639 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4640 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4641 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4642 const X86Subtarget *Subtarget) {
4643 if (!Subtarget->hasSSE3())
4644 return false;
4646 unsigned NumElems = VT.getVectorNumElements();
4648 if ((VT.is128BitVector() && NumElems != 4) ||
4649 (VT.is256BitVector() && NumElems != 8) ||
4650 (VT.is512BitVector() && NumElems != 16))
4651 return false;
4653 // "i" is the value the indexed mask element must have
4654 for (unsigned i = 0; i != NumElems; i += 2)
4655 if (!isUndefOrEqual(Mask[i], i) ||
4656 !isUndefOrEqual(Mask[i+1], i))
4657 return false;
4659 return true;
4660 }
4662 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4663 /// specifies a shuffle of elements that is suitable for input to 256-bit
4664 /// version of MOVDDUP.
4665 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4666 if (!HasFp256 || !VT.is256BitVector())
4667 return false;
4669 unsigned NumElts = VT.getVectorNumElements();
4670 if (NumElts != 4)
4671 return false;
4673 for (unsigned i = 0; i != NumElts/2; ++i)
4674 if (!isUndefOrEqual(Mask[i], 0))
4675 return false;
4676 for (unsigned i = NumElts/2; i != NumElts; ++i)
4677 if (!isUndefOrEqual(Mask[i], NumElts/2))
4678 return false;
4679 return true;
4680 }
4682 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4683 /// specifies a shuffle of elements that is suitable for input to 128-bit
4684 /// version of MOVDDUP.
4685 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4686 if (!VT.is128BitVector())
4687 return false;
4689 unsigned e = VT.getVectorNumElements() / 2;
4690 for (unsigned i = 0; i != e; ++i)
4691 if (!isUndefOrEqual(Mask[i], i))
4692 return false;
4693 for (unsigned i = 0; i != e; ++i)
4694 if (!isUndefOrEqual(Mask[e+i], i))
4695 return false;
4696 return true;
4697 }
4699 /// isVEXTRACTIndex - Return true if the specified
4700 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4701 /// suitable for instruction that extract 128 or 256 bit vectors
4702 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4703 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4704 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4705 return false;
4707 // The index should be aligned on a vecWidth-bit boundary.
4708 uint64_t Index =
4709 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4711 MVT VT = N->getSimpleValueType(0);
4712 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4713 bool Result = (Index * ElSize) % vecWidth == 0;
4715 return Result;
4716 }
4718 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4719 /// operand specifies a subvector insert that is suitable for input to
4720 /// insertion of 128 or 256-bit subvectors
4721 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4722 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4723 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4724 return false;
4725 // The index should be aligned on a vecWidth-bit boundary.
4726 uint64_t Index =
4727 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4729 MVT VT = N->getSimpleValueType(0);
4730 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4731 bool Result = (Index * ElSize) % vecWidth == 0;
4733 return Result;
4734 }
4736 bool X86::isVINSERT128Index(SDNode *N) {
4737 return isVINSERTIndex(N, 128);
4738 }
4740 bool X86::isVINSERT256Index(SDNode *N) {
4741 return isVINSERTIndex(N, 256);
4742 }
4744 bool X86::isVEXTRACT128Index(SDNode *N) {
4745 return isVEXTRACTIndex(N, 128);
4746 }
4748 bool X86::isVEXTRACT256Index(SDNode *N) {
4749 return isVEXTRACTIndex(N, 256);
4750 }
4752 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4753 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4754 /// Handles 128-bit and 256-bit.
4755 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4756 MVT VT = N->getSimpleValueType(0);
4758 assert((VT.getSizeInBits() >= 128) &&
4759 "Unsupported vector type for PSHUF/SHUFP");
4761 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4762 // independently on 128-bit lanes.
4763 unsigned NumElts = VT.getVectorNumElements();
4764 unsigned NumLanes = VT.getSizeInBits()/128;
4765 unsigned NumLaneElts = NumElts/NumLanes;
4767 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4768 "Only supports 2, 4 or 8 elements per lane");
4770 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4771 unsigned Mask = 0;
4772 for (unsigned i = 0; i != NumElts; ++i) {
4773 int Elt = N->getMaskElt(i);
4774 if (Elt < 0) continue;
4775 Elt &= NumLaneElts - 1;
4776 unsigned ShAmt = (i << Shift) % 8;
4777 Mask |= Elt << ShAmt;
4778 }
4780 return Mask;
4781 }
4783 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4784 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4785 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4786 MVT VT = N->getSimpleValueType(0);
4788 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4789 "Unsupported vector type for PSHUFHW");
4791 unsigned NumElts = VT.getVectorNumElements();
4793 unsigned Mask = 0;
4794 for (unsigned l = 0; l != NumElts; l += 8) {
4795 // 8 nodes per lane, but we only care about the last 4.
4796 for (unsigned i = 0; i < 4; ++i) {
4797 int Elt = N->getMaskElt(l+i+4);
4798 if (Elt < 0) continue;
4799 Elt &= 0x3; // only 2-bits.
4800 Mask |= Elt << (i * 2);
4801 }
4802 }
4804 return Mask;
4805 }
4807 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4808 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4809 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4810 MVT VT = N->getSimpleValueType(0);
4812 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4813 "Unsupported vector type for PSHUFHW");
4815 unsigned NumElts = VT.getVectorNumElements();
4817 unsigned Mask = 0;
4818 for (unsigned l = 0; l != NumElts; l += 8) {
4819 // 8 nodes per lane, but we only care about the first 4.
4820 for (unsigned i = 0; i < 4; ++i) {
4821 int Elt = N->getMaskElt(l+i);
4822 if (Elt < 0) continue;
4823 Elt &= 0x3; // only 2-bits
4824 Mask |= Elt << (i * 2);
4825 }
4826 }
4828 return Mask;
4829 }
4831 /// \brief Return the appropriate immediate to shuffle the specified
4832 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4833 /// VALIGN (if Interlane is true) instructions.
4834 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4835 bool InterLane) {
4836 MVT VT = SVOp->getSimpleValueType(0);
4837 unsigned EltSize = InterLane ? 1 :
4838 VT.getVectorElementType().getSizeInBits() >> 3;
4840 unsigned NumElts = VT.getVectorNumElements();
4841 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4842 unsigned NumLaneElts = NumElts/NumLanes;
4844 int Val = 0;
4845 unsigned i;
4846 for (i = 0; i != NumElts; ++i) {
4847 Val = SVOp->getMaskElt(i);
4848 if (Val >= 0)
4849 break;
4850 }
4851 if (Val >= (int)NumElts)
4852 Val -= NumElts - NumLaneElts;
4854 assert(Val - i > 0 && "PALIGNR imm should be positive");
4855 return (Val - i) * EltSize;
4856 }
4858 /// \brief Return the appropriate immediate to shuffle the specified
4859 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4860 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4861 return getShuffleAlignrImmediate(SVOp, false);
4862 }
4864 /// \brief Return the appropriate immediate to shuffle the specified
4865 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4866 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4867 return getShuffleAlignrImmediate(SVOp, true);
4868 }
4871 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4872 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4873 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4874 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4876 uint64_t Index =
4877 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4879 MVT VecVT = N->getOperand(0).getSimpleValueType();
4880 MVT ElVT = VecVT.getVectorElementType();
4882 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4883 return Index / NumElemsPerChunk;
4884 }
4886 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4887 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4888 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4889 llvm_unreachable("Illegal insert subvector for VINSERT");
4891 uint64_t Index =
4892 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4894 MVT VecVT = N->getSimpleValueType(0);
4895 MVT ElVT = VecVT.getVectorElementType();
4897 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4898 return Index / NumElemsPerChunk;
4899 }
4901 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4902 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4903 /// and VINSERTI128 instructions.
4904 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4905 return getExtractVEXTRACTImmediate(N, 128);
4906 }
4908 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4909 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4910 /// and VINSERTI64x4 instructions.
4911 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4912 return getExtractVEXTRACTImmediate(N, 256);
4913 }
4915 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4916 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4917 /// and VINSERTI128 instructions.
4918 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4919 return getInsertVINSERTImmediate(N, 128);
4920 }
4922 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4923 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4924 /// and VINSERTI64x4 instructions.
4925 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4926 return getInsertVINSERTImmediate(N, 256);
4927 }
4929 /// isZero - Returns true if Elt is a constant integer zero
4930 static bool isZero(SDValue V) {
4931 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4932 return C && C->isNullValue();
4933 }
4935 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4936 /// constant +0.0.
4937 bool X86::isZeroNode(SDValue Elt) {
4938 if (isZero(Elt))
4939 return true;
4940 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4941 return CFP->getValueAPF().isPosZero();
4942 return false;
4943 }
4945 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4946 /// match movhlps. The lower half elements should come from upper half of
4947 /// V1 (and in order), and the upper half elements should come from the upper
4948 /// half of V2 (and in order).
4949 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4950 if (!VT.is128BitVector())
4951 return false;
4952 if (VT.getVectorNumElements() != 4)
4953 return false;
4954 for (unsigned i = 0, e = 2; i != e; ++i)
4955 if (!isUndefOrEqual(Mask[i], i+2))
4956 return false;
4957 for (unsigned i = 2; i != 4; ++i)
4958 if (!isUndefOrEqual(Mask[i], i+4))
4959 return false;
4960 return true;
4961 }
4963 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4964 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4965 /// required.
4966 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4967 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4968 return false;
4969 N = N->getOperand(0).getNode();
4970 if (!ISD::isNON_EXTLoad(N))
4971 return false;
4972 if (LD)
4973 *LD = cast<LoadSDNode>(N);
4974 return true;
4975 }
4977 // Test whether the given value is a vector value which will be legalized
4978 // into a load.
4979 static bool WillBeConstantPoolLoad(SDNode *N) {
4980 if (N->getOpcode() != ISD::BUILD_VECTOR)
4981 return false;
4983 // Check for any non-constant elements.
4984 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4985 switch (N->getOperand(i).getNode()->getOpcode()) {
4986 case ISD::UNDEF:
4987 case ISD::ConstantFP:
4988 case ISD::Constant:
4989 break;
4990 default:
4991 return false;
4992 }
4994 // Vectors of all-zeros and all-ones are materialized with special
4995 // instructions rather than being loaded.
4996 return !ISD::isBuildVectorAllZeros(N) &&
4997 !ISD::isBuildVectorAllOnes(N);
4998 }
5000 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5001 /// match movlp{s|d}. The lower half elements should come from lower half of
5002 /// V1 (and in order), and the upper half elements should come from the upper
5003 /// half of V2 (and in order). And since V1 will become the source of the
5004 /// MOVLP, it must be either a vector load or a scalar load to vector.
5005 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5006 ArrayRef<int> Mask, MVT VT) {
5007 if (!VT.is128BitVector())
5008 return false;
5010 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5011 return false;
5012 // Is V2 is a vector load, don't do this transformation. We will try to use
5013 // load folding shufps op.
5014 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5015 return false;
5017 unsigned NumElems = VT.getVectorNumElements();
5019 if (NumElems != 2 && NumElems != 4)
5020 return false;
5021 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5022 if (!isUndefOrEqual(Mask[i], i))
5023 return false;
5024 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5025 if (!isUndefOrEqual(Mask[i], i+NumElems))
5026 return false;
5027 return true;
5028 }
5030 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5031 /// to an zero vector.
5032 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5033 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5034 SDValue V1 = N->getOperand(0);
5035 SDValue V2 = N->getOperand(1);
5036 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5037 for (unsigned i = 0; i != NumElems; ++i) {
5038 int Idx = N->getMaskElt(i);
5039 if (Idx >= (int)NumElems) {
5040 unsigned Opc = V2.getOpcode();
5041 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5042 continue;
5043 if (Opc != ISD::BUILD_VECTOR ||
5044 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5045 return false;
5046 } else if (Idx >= 0) {
5047 unsigned Opc = V1.getOpcode();
5048 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5049 continue;
5050 if (Opc != ISD::BUILD_VECTOR ||
5051 !X86::isZeroNode(V1.getOperand(Idx)))
5052 return false;
5053 }
5054 }
5055 return true;
5056 }
5058 /// getZeroVector - Returns a vector of specified type with all zero elements.
5059 ///
5060 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5061 SelectionDAG &DAG, SDLoc dl) {
5062 assert(VT.isVector() && "Expected a vector type");
5064 // Always build SSE zero vectors as <4 x i32> bitcasted
5065 // to their dest type. This ensures they get CSE'd.
5066 SDValue Vec;
5067 if (VT.is128BitVector()) { // SSE
5068 if (Subtarget->hasSSE2()) { // SSE2
5069 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5070 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5071 } else { // SSE1
5072 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5073 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5074 }
5075 } else if (VT.is256BitVector()) { // AVX
5076 if (Subtarget->hasInt256()) { // AVX2
5077 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5078 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5079 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5080 } else {
5081 // 256-bit logic and arithmetic instructions in AVX are all
5082 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5083 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5084 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5085 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5086 }
5087 } else if (VT.is512BitVector()) { // AVX-512
5088 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5089 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5090 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5091 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5092 } else if (VT.getScalarType() == MVT::i1) {
5093 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5094 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5095 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5096 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5097 } else
5098 llvm_unreachable("Unexpected vector type");
5100 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5101 }
5103 /// getOnesVector - Returns a vector of specified type with all bits set.
5104 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5105 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5106 /// Then bitcast to their original type, ensuring they get CSE'd.
5107 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5108 SDLoc dl) {
5109 assert(VT.isVector() && "Expected a vector type");
5111 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
5112 SDValue Vec;
5113 if (VT.is256BitVector()) {
5114 if (HasInt256) { // AVX2
5115 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5116 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5117 } else { // AVX
5118 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5119 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5120 }
5121 } else if (VT.is128BitVector()) {
5122 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5123 } else
5124 llvm_unreachable("Unexpected vector type");
5126 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5127 }
5129 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5130 /// that point to V2 points to its first element.
5131 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5132 for (unsigned i = 0; i != NumElems; ++i) {
5133 if (Mask[i] > (int)NumElems) {
5134 Mask[i] = NumElems;
5135 }
5136 }
5137 }
5139 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5140 /// operation of specified width.
5141 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5142 SDValue V2) {
5143 unsigned NumElems = VT.getVectorNumElements();
5144 SmallVector<int, 8> Mask;
5145 Mask.push_back(NumElems);
5146 for (unsigned i = 1; i != NumElems; ++i)
5147 Mask.push_back(i);
5148 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5149 }
5151 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5152 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5153 SDValue V2) {
5154 unsigned NumElems = VT.getVectorNumElements();
5155 SmallVector<int, 8> Mask;
5156 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5157 Mask.push_back(i);
5158 Mask.push_back(i + NumElems);
5159 }
5160 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5161 }
5163 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5164 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5165 SDValue V2) {
5166 unsigned NumElems = VT.getVectorNumElements();
5167 SmallVector<int, 8> Mask;
5168 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5169 Mask.push_back(i + Half);
5170 Mask.push_back(i + NumElems + Half);
5171 }
5172 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5173 }
5175 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5176 // a generic shuffle instruction because the target has no such instructions.
5177 // Generate shuffles which repeat i16 and i8 several times until they can be
5178 // represented by v4f32 and then be manipulated by target suported shuffles.
5179 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5180 MVT VT = V.getSimpleValueType();
5181 int NumElems = VT.getVectorNumElements();
5182 SDLoc dl(V);
5184 while (NumElems > 4) {
5185 if (EltNo < NumElems/2) {
5186 V = getUnpackl(DAG, dl, VT, V, V);
5187 } else {
5188 V = getUnpackh(DAG, dl, VT, V, V);
5189 EltNo -= NumElems/2;
5190 }
5191 NumElems >>= 1;
5192 }
5193 return V;
5194 }
5196 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5197 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5198 MVT VT = V.getSimpleValueType();
5199 SDLoc dl(V);
5201 if (VT.is128BitVector()) {
5202 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5203 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5204 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5205 &SplatMask[0]);
5206 } else if (VT.is256BitVector()) {
5207 // To use VPERMILPS to splat scalars, the second half of indicies must
5208 // refer to the higher part, which is a duplication of the lower one,
5209 // because VPERMILPS can only handle in-lane permutations.
5210 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5211 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5213 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5214 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5215 &SplatMask[0]);
5216 } else
5217 llvm_unreachable("Vector size not supported");
5219 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5220 }
5222 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5223 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5224 MVT SrcVT = SV->getSimpleValueType(0);
5225 SDValue V1 = SV->getOperand(0);
5226 SDLoc dl(SV);
5228 int EltNo = SV->getSplatIndex();
5229 int NumElems = SrcVT.getVectorNumElements();
5230 bool Is256BitVec = SrcVT.is256BitVector();
5232 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5233 "Unknown how to promote splat for type");
5235 // Extract the 128-bit part containing the splat element and update
5236 // the splat element index when it refers to the higher register.
5237 if (Is256BitVec) {
5238 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5239 if (EltNo >= NumElems/2)
5240 EltNo -= NumElems/2;
5241 }
5243 // All i16 and i8 vector types can't be used directly by a generic shuffle
5244 // instruction because the target has no such instruction. Generate shuffles
5245 // which repeat i16 and i8 several times until they fit in i32, and then can
5246 // be manipulated by target suported shuffles.
5247 MVT EltVT = SrcVT.getVectorElementType();
5248 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5249 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5251 // Recreate the 256-bit vector and place the same 128-bit vector
5252 // into the low and high part. This is necessary because we want
5253 // to use VPERM* to shuffle the vectors
5254 if (Is256BitVec) {
5255 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5256 }
5258 return getLegalSplat(DAG, V1, EltNo);
5259 }
5261 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5262 /// vector of zero or undef vector. This produces a shuffle where the low
5263 /// element of V2 is swizzled into the zero/undef vector, landing at element
5264 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5265 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5266 bool IsZero,
5267 const X86Subtarget *Subtarget,
5268 SelectionDAG &DAG) {
5269 MVT VT = V2.getSimpleValueType();
5270 SDValue V1 = IsZero
5271 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5272 unsigned NumElems = VT.getVectorNumElements();
5273 SmallVector<int, 16> MaskVec;
5274 for (unsigned i = 0; i != NumElems; ++i)
5275 // If this is the insertion idx, put the low elt of V2 here.
5276 MaskVec.push_back(i == Idx ? NumElems : i);
5277 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5278 }
5280 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5281 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5282 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5283 /// shuffles which use a single input multiple times, and in those cases it will
5284 /// adjust the mask to only have indices within that single input.
5285 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5286 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5287 unsigned NumElems = VT.getVectorNumElements();
5288 SDValue ImmN;
5290 IsUnary = false;
5291 bool IsFakeUnary = false;
5292 switch(N->getOpcode()) {
5293 case X86ISD::BLENDI:
5294 ImmN = N->getOperand(N->getNumOperands()-1);
5295 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5296 break;
5297 case X86ISD::SHUFP:
5298 ImmN = N->getOperand(N->getNumOperands()-1);
5299 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5300 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5301 break;
5302 case X86ISD::UNPCKH:
5303 DecodeUNPCKHMask(VT, Mask);
5304 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5305 break;
5306 case X86ISD::UNPCKL:
5307 DecodeUNPCKLMask(VT, Mask);
5308 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5309 break;
5310 case X86ISD::MOVHLPS:
5311 DecodeMOVHLPSMask(NumElems, Mask);
5312 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5313 break;
5314 case X86ISD::MOVLHPS:
5315 DecodeMOVLHPSMask(NumElems, Mask);
5316 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5317 break;
5318 case X86ISD::PALIGNR:
5319 ImmN = N->getOperand(N->getNumOperands()-1);
5320 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5321 break;
5322 case X86ISD::PSHUFD:
5323 case X86ISD::VPERMILPI:
5324 ImmN = N->getOperand(N->getNumOperands()-1);
5325 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5326 IsUnary = true;
5327 break;
5328 case X86ISD::PSHUFHW:
5329 ImmN = N->getOperand(N->getNumOperands()-1);
5330 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5331 IsUnary = true;
5332 break;
5333 case X86ISD::PSHUFLW:
5334 ImmN = N->getOperand(N->getNumOperands()-1);
5335 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5336 IsUnary = true;
5337 break;
5338 case X86ISD::PSHUFB: {
5339 IsUnary = true;
5340 SDValue MaskNode = N->getOperand(1);
5341 while (MaskNode->getOpcode() == ISD::BITCAST)
5342 MaskNode = MaskNode->getOperand(0);
5344 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5345 // If we have a build-vector, then things are easy.
5346 EVT VT = MaskNode.getValueType();
5347 assert(VT.isVector() &&
5348 "Can't produce a non-vector with a build_vector!");
5349 if (!VT.isInteger())
5350 return false;
5352 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5354 SmallVector<uint64_t, 32> RawMask;
5355 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5356 SDValue Op = MaskNode->getOperand(i);
5357 if (Op->getOpcode() == ISD::UNDEF) {
5358 RawMask.push_back((uint64_t)SM_SentinelUndef);
5359 continue;
5360 }
5361 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5362 if (!CN)
5363 return false;
5364 APInt MaskElement = CN->getAPIntValue();
5366 // We now have to decode the element which could be any integer size and
5367 // extract each byte of it.
5368 for (int j = 0; j < NumBytesPerElement; ++j) {
5369 // Note that this is x86 and so always little endian: the low byte is
5370 // the first byte of the mask.
5371 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5372 MaskElement = MaskElement.lshr(8);
5373 }
5374 }
5375 DecodePSHUFBMask(RawMask, Mask);
5376 break;
5377 }
5379 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5380 if (!MaskLoad)
5381 return false;
5383 SDValue Ptr = MaskLoad->getBasePtr();
5384 if (Ptr->getOpcode() == X86ISD::Wrapper)
5385 Ptr = Ptr->getOperand(0);
5387 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5388 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5389 return false;
5391 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5392 // FIXME: Support AVX-512 here.
5393 Type *Ty = C->getType();
5394 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5395 Ty->getVectorNumElements() != 32))
5396 return false;
5398 DecodePSHUFBMask(C, Mask);
5399 break;
5400 }
5402 return false;
5403 }
5404 case X86ISD::VPERMI:
5405 ImmN = N->getOperand(N->getNumOperands()-1);
5406 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5407 IsUnary = true;
5408 break;
5409 case X86ISD::MOVSS:
5410 case X86ISD::MOVSD: {
5411 // The index 0 always comes from the first element of the second source,
5412 // this is why MOVSS and MOVSD are used in the first place. The other
5413 // elements come from the other positions of the first source vector
5414 Mask.push_back(NumElems);
5415 for (unsigned i = 1; i != NumElems; ++i) {
5416 Mask.push_back(i);
5417 }
5418 break;
5419 }
5420 case X86ISD::VPERM2X128:
5421 ImmN = N->getOperand(N->getNumOperands()-1);
5422 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5423 if (Mask.empty()) return false;
5424 break;
5425 case X86ISD::MOVSLDUP:
5426 DecodeMOVSLDUPMask(VT, Mask);
5427 break;
5428 case X86ISD::MOVSHDUP:
5429 DecodeMOVSHDUPMask(VT, Mask);
5430 break;
5431 case X86ISD::MOVDDUP:
5432 case X86ISD::MOVLHPD:
5433 case X86ISD::MOVLPD:
5434 case X86ISD::MOVLPS:
5435 // Not yet implemented
5436 return false;
5437 default: llvm_unreachable("unknown target shuffle node");
5438 }
5440 // If we have a fake unary shuffle, the shuffle mask is spread across two
5441 // inputs that are actually the same node. Re-map the mask to always point
5442 // into the first input.
5443 if (IsFakeUnary)
5444 for (int &M : Mask)
5445 if (M >= (int)Mask.size())
5446 M -= Mask.size();
5448 return true;
5449 }
5451 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5452 /// element of the result of the vector shuffle.
5453 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5454 unsigned Depth) {
5455 if (Depth == 6)
5456 return SDValue(); // Limit search depth.
5458 SDValue V = SDValue(N, 0);
5459 EVT VT = V.getValueType();
5460 unsigned Opcode = V.getOpcode();
5462 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5463 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5464 int Elt = SV->getMaskElt(Index);
5466 if (Elt < 0)
5467 return DAG.getUNDEF(VT.getVectorElementType());
5469 unsigned NumElems = VT.getVectorNumElements();
5470 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5471 : SV->getOperand(1);
5472 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5473 }
5475 // Recurse into target specific vector shuffles to find scalars.
5476 if (isTargetShuffle(Opcode)) {
5477 MVT ShufVT = V.getSimpleValueType();
5478 unsigned NumElems = ShufVT.getVectorNumElements();
5479 SmallVector<int, 16> ShuffleMask;
5480 bool IsUnary;
5482 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5483 return SDValue();
5485 int Elt = ShuffleMask[Index];
5486 if (Elt < 0)
5487 return DAG.getUNDEF(ShufVT.getVectorElementType());
5489 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5490 : N->getOperand(1);
5491 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5492 Depth+1);
5493 }
5495 // Actual nodes that may contain scalar elements
5496 if (Opcode == ISD::BITCAST) {
5497 V = V.getOperand(0);
5498 EVT SrcVT = V.getValueType();
5499 unsigned NumElems = VT.getVectorNumElements();
5501 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5502 return SDValue();
5503 }
5505 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5506 return (Index == 0) ? V.getOperand(0)
5507 : DAG.getUNDEF(VT.getVectorElementType());
5509 if (V.getOpcode() == ISD::BUILD_VECTOR)
5510 return V.getOperand(Index);
5512 return SDValue();
5513 }
5515 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5516 /// shuffle operation which come from a consecutively from a zero. The
5517 /// search can start in two different directions, from left or right.
5518 /// We count undefs as zeros until PreferredNum is reached.
5519 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5520 unsigned NumElems, bool ZerosFromLeft,
5521 SelectionDAG &DAG,
5522 unsigned PreferredNum = -1U) {
5523 unsigned NumZeros = 0;
5524 for (unsigned i = 0; i != NumElems; ++i) {
5525 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5526 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5527 if (!Elt.getNode())
5528 break;
5530 if (X86::isZeroNode(Elt))
5531 ++NumZeros;
5532 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5533 NumZeros = std::min(NumZeros + 1, PreferredNum);
5534 else
5535 break;
5536 }
5538 return NumZeros;
5539 }
5541 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5542 /// correspond consecutively to elements from one of the vector operands,
5543 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5544 static
5545 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5546 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5547 unsigned NumElems, unsigned &OpNum) {
5548 bool SeenV1 = false;
5549 bool SeenV2 = false;
5551 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5552 int Idx = SVOp->getMaskElt(i);
5553 // Ignore undef indicies
5554 if (Idx < 0)
5555 continue;
5557 if (Idx < (int)NumElems)
5558 SeenV1 = true;
5559 else
5560 SeenV2 = true;
5562 // Only accept consecutive elements from the same vector
5563 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5564 return false;
5565 }
5567 OpNum = SeenV1 ? 0 : 1;
5568 return true;
5569 }
5571 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5572 /// logical left shift of a vector.
5573 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5574 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5575 unsigned NumElems =
5576 SVOp->getSimpleValueType(0).getVectorNumElements();
5577 unsigned NumZeros = getNumOfConsecutiveZeros(
5578 SVOp, NumElems, false /* check zeros from right */, DAG,
5579 SVOp->getMaskElt(0));
5580 unsigned OpSrc;
5582 if (!NumZeros)
5583 return false;
5585 // Considering the elements in the mask that are not consecutive zeros,
5586 // check if they consecutively come from only one of the source vectors.
5587 //
5588 // V1 = {X, A, B, C} 0
5589 // \ \ \ /
5590 // vector_shuffle V1, V2 <1, 2, 3, X>
5591 //
5592 if (!isShuffleMaskConsecutive(SVOp,
5593 0, // Mask Start Index
5594 NumElems-NumZeros, // Mask End Index(exclusive)
5595 NumZeros, // Where to start looking in the src vector
5596 NumElems, // Number of elements in vector
5597 OpSrc)) // Which source operand ?
5598 return false;
5600 isLeft = false;
5601 ShAmt = NumZeros;
5602 ShVal = SVOp->getOperand(OpSrc);
5603 return true;
5604 }
5606 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5607 /// logical left shift of a vector.
5608 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5609 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5610 unsigned NumElems =
5611 SVOp->getSimpleValueType(0).getVectorNumElements();
5612 unsigned NumZeros = getNumOfConsecutiveZeros(
5613 SVOp, NumElems, true /* check zeros from left */, DAG,
5614 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5615 unsigned OpSrc;
5617 if (!NumZeros)
5618 return false;
5620 // Considering the elements in the mask that are not consecutive zeros,
5621 // check if they consecutively come from only one of the source vectors.
5622 //
5623 // 0 { A, B, X, X } = V2
5624 // / \ / /
5625 // vector_shuffle V1, V2 <X, X, 4, 5>
5626 //
5627 if (!isShuffleMaskConsecutive(SVOp,
5628 NumZeros, // Mask Start Index
5629 NumElems, // Mask End Index(exclusive)
5630 0, // Where to start looking in the src vector
5631 NumElems, // Number of elements in vector
5632 OpSrc)) // Which source operand ?
5633 return false;
5635 isLeft = true;
5636 ShAmt = NumZeros;
5637 ShVal = SVOp->getOperand(OpSrc);
5638 return true;
5639 }
5641 /// isVectorShift - Returns true if the shuffle can be implemented as a
5642 /// logical left or right shift of a vector.
5643 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5644 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5645 // Although the logic below support any bitwidth size, there are no
5646 // shift instructions which handle more than 128-bit vectors.
5647 if (!SVOp->getSimpleValueType(0).is128BitVector())
5648 return false;
5650 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5651 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5652 return true;
5654 return false;
5655 }
5657 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5658 ///
5659 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5660 unsigned NumNonZero, unsigned NumZero,
5661 SelectionDAG &DAG,
5662 const X86Subtarget* Subtarget,
5663 const TargetLowering &TLI) {
5664 if (NumNonZero > 8)
5665 return SDValue();
5667 SDLoc dl(Op);
5668 SDValue V;
5669 bool First = true;
5670 for (unsigned i = 0; i < 16; ++i) {
5671 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5672 if (ThisIsNonZero && First) {
5673 if (NumZero)
5674 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5675 else
5676 V = DAG.getUNDEF(MVT::v8i16);
5677 First = false;
5678 }
5680 if ((i & 1) != 0) {
5681 SDValue ThisElt, LastElt;
5682 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5683 if (LastIsNonZero) {
5684 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5685 MVT::i16, Op.getOperand(i-1));
5686 }
5687 if (ThisIsNonZero) {
5688 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5689 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5690 ThisElt, DAG.getConstant(8, MVT::i8));
5691 if (LastIsNonZero)
5692 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5693 } else
5694 ThisElt = LastElt;
5696 if (ThisElt.getNode())
5697 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5698 DAG.getIntPtrConstant(i/2));
5699 }
5700 }
5702 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5703 }
5705 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5706 ///
5707 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5708 unsigned NumNonZero, unsigned NumZero,
5709 SelectionDAG &DAG,
5710 const X86Subtarget* Subtarget,
5711 const TargetLowering &TLI) {
5712 if (NumNonZero > 4)
5713 return SDValue();
5715 SDLoc dl(Op);
5716 SDValue V;
5717 bool First = true;
5718 for (unsigned i = 0; i < 8; ++i) {
5719 bool isNonZero = (NonZeros & (1 << i)) != 0;
5720 if (isNonZero) {
5721 if (First) {
5722 if (NumZero)
5723 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5724 else
5725 V = DAG.getUNDEF(MVT::v8i16);
5726 First = false;
5727 }
5728 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5729 MVT::v8i16, V, Op.getOperand(i),
5730 DAG.getIntPtrConstant(i));
5731 }
5732 }
5734 return V;
5735 }
5737 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5738 static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
5739 unsigned NonZeros, unsigned NumNonZero,
5740 unsigned NumZero, SelectionDAG &DAG,
5741 const X86Subtarget *Subtarget,
5742 const TargetLowering &TLI) {
5743 // We know there's at least one non-zero element
5744 unsigned FirstNonZeroIdx = 0;
5745 SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5746 while (FirstNonZero.getOpcode() == ISD::UNDEF ||
5747 X86::isZeroNode(FirstNonZero)) {
5748 ++FirstNonZeroIdx;
5749 FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5750 }
5752 if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5753 !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
5754 return SDValue();
5756 SDValue V = FirstNonZero.getOperand(0);
5757 MVT VVT = V.getSimpleValueType();
5758 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
5759 return SDValue();
5761 unsigned FirstNonZeroDst =
5762 cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
5763 unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
5764 unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
5765 unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
5767 for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
5768 SDValue Elem = Op.getOperand(Idx);
5769 if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
5770 continue;
5772 // TODO: What else can be here? Deal with it.
5773 if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5774 return SDValue();
5776 // TODO: Some optimizations are still possible here
5777 // ex: Getting one element from a vector, and the rest from another.
5778 if (Elem.getOperand(0) != V)
5779 return SDValue();
5781 unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
5782 if (Dst == Idx)
5783 ++CorrectIdx;
5784 else if (IncorrectIdx == -1U) {
5785 IncorrectIdx = Idx;
5786 IncorrectDst = Dst;
5787 } else
5788 // There was already one element with an incorrect index.
5789 // We can't optimize this case to an insertps.
5790 return SDValue();
5791 }
5793 if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
5794 SDLoc dl(Op);
5795 EVT VT = Op.getSimpleValueType();
5796 unsigned ElementMoveMask = 0;
5797 if (IncorrectIdx == -1U)
5798 ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
5799 else
5800 ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
5802 SDValue InsertpsMask =
5803 DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
5804 return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
5805 }
5807 return SDValue();
5808 }
5810 /// getVShift - Return a vector logical shift node.
5811 ///
5812 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5813 unsigned NumBits, SelectionDAG &DAG,
5814 const TargetLowering &TLI, SDLoc dl) {
5815 assert(VT.is128BitVector() && "Unknown type for VShift");
5816 EVT ShVT = MVT::v2i64;
5817 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5818 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5819 return DAG.getNode(ISD::BITCAST, dl, VT,
5820 DAG.getNode(Opc, dl, ShVT, SrcOp,
5821 DAG.getConstant(NumBits,
5822 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5823 }
5825 static SDValue
5826 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5828 // Check if the scalar load can be widened into a vector load. And if
5829 // the address is "base + cst" see if the cst can be "absorbed" into
5830 // the shuffle mask.
5831 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5832 SDValue Ptr = LD->getBasePtr();
5833 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5834 return SDValue();
5835 EVT PVT = LD->getValueType(0);
5836 if (PVT != MVT::i32 && PVT != MVT::f32)
5837 return SDValue();
5839 int FI = -1;
5840 int64_t Offset = 0;
5841 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5842 FI = FINode->getIndex();
5843 Offset = 0;
5844 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5845 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5846 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5847 Offset = Ptr.getConstantOperandVal(1);
5848 Ptr = Ptr.getOperand(0);
5849 } else {
5850 return SDValue();
5851 }
5853 // FIXME: 256-bit vector instructions don't require a strict alignment,
5854 // improve this code to support it better.
5855 unsigned RequiredAlign = VT.getSizeInBits()/8;
5856 SDValue Chain = LD->getChain();
5857 // Make sure the stack object alignment is at least 16 or 32.
5858 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5859 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5860 if (MFI->isFixedObjectIndex(FI)) {
5861 // Can't change the alignment. FIXME: It's possible to compute
5862 // the exact stack offset and reference FI + adjust offset instead.
5863 // If someone *really* cares about this. That's the way to implement it.
5864 return SDValue();
5865 } else {
5866 MFI->setObjectAlignment(FI, RequiredAlign);
5867 }
5868 }
5870 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5871 // Ptr + (Offset & ~15).
5872 if (Offset < 0)
5873 return SDValue();
5874 if ((Offset % RequiredAlign) & 3)
5875 return SDValue();
5876 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5877 if (StartOffset)
5878 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5879 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5881 int EltNo = (Offset - StartOffset) >> 2;
5882 unsigned NumElems = VT.getVectorNumElements();
5884 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5885 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5886 LD->getPointerInfo().getWithOffset(StartOffset),
5887 false, false, false, 0);
5889 SmallVector<int, 8> Mask;
5890 for (unsigned i = 0; i != NumElems; ++i)
5891 Mask.push_back(EltNo);
5893 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5894 }
5896 return SDValue();
5897 }
5899 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5900 /// vector of type 'VT', see if the elements can be replaced by a single large
5901 /// load which has the same value as a build_vector whose operands are 'elts'.
5902 ///
5903 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5904 ///
5905 /// FIXME: we'd also like to handle the case where the last elements are zero
5906 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5907 /// There's even a handy isZeroNode for that purpose.
5908 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5909 SDLoc &DL, SelectionDAG &DAG,
5910 bool isAfterLegalize) {
5911 EVT EltVT = VT.getVectorElementType();
5912 unsigned NumElems = Elts.size();
5914 LoadSDNode *LDBase = nullptr;
5915 unsigned LastLoadedElt = -1U;
5917 // For each element in the initializer, see if we've found a load or an undef.
5918 // If we don't find an initial load element, or later load elements are
5919 // non-consecutive, bail out.
5920 for (unsigned i = 0; i < NumElems; ++i) {
5921 SDValue Elt = Elts[i];
5923 if (!Elt.getNode() ||
5924 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5925 return SDValue();
5926 if (!LDBase) {
5927 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5928 return SDValue();
5929 LDBase = cast<LoadSDNode>(Elt.getNode());
5930 LastLoadedElt = i;
5931 continue;
5932 }
5933 if (Elt.getOpcode() == ISD::UNDEF)
5934 continue;
5936 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5937 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5938 return SDValue();
5939 LastLoadedElt = i;
5940 }
5942 // If we have found an entire vector of loads and undefs, then return a large
5943 // load of the entire vector width starting at the base pointer. If we found
5944 // consecutive loads for the low half, generate a vzext_load node.
5945 if (LastLoadedElt == NumElems - 1) {
5947 if (isAfterLegalize &&
5948 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5949 return SDValue();
5951 SDValue NewLd = SDValue();
5953 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5954 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5955 LDBase->getPointerInfo(),
5956 LDBase->isVolatile(), LDBase->isNonTemporal(),
5957 LDBase->isInvariant(), 0);
5958 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5959 LDBase->getPointerInfo(),
5960 LDBase->isVolatile(), LDBase->isNonTemporal(),
5961 LDBase->isInvariant(), LDBase->getAlignment());
5963 if (LDBase->hasAnyUseOfValue(1)) {
5964 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5965 SDValue(LDBase, 1),
5966 SDValue(NewLd.getNode(), 1));
5967 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5968 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5969 SDValue(NewLd.getNode(), 1));
5970 }
5972 return NewLd;
5973 }
5974 if (NumElems == 4 && LastLoadedElt == 1 &&
5975 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5976 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5977 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5978 SDValue ResNode =
5979 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5980 LDBase->getPointerInfo(),
5981 LDBase->getAlignment(),
5982 false/*isVolatile*/, true/*ReadMem*/,
5983 false/*WriteMem*/);
5985 // Make sure the newly-created LOAD is in the same position as LDBase in
5986 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5987 // update uses of LDBase's output chain to use the TokenFactor.
5988 if (LDBase->hasAnyUseOfValue(1)) {
5989 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5990 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5991 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5992 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5993 SDValue(ResNode.getNode(), 1));
5994 }
5996 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5997 }
5998 return SDValue();
5999 }
6001 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6002 /// to generate a splat value for the following cases:
6003 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6004 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6005 /// a scalar load, or a constant.
6006 /// The VBROADCAST node is returned when a pattern is found,
6007 /// or SDValue() otherwise.
6008 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6009 SelectionDAG &DAG) {
6010 // VBROADCAST requires AVX.
6011 // TODO: Splats could be generated for non-AVX CPUs using SSE
6012 // instructions, but there's less potential gain for only 128-bit vectors.
6013 if (!Subtarget->hasAVX())
6014 return SDValue();
6016 MVT VT = Op.getSimpleValueType();
6017 SDLoc dl(Op);
6019 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6020 "Unsupported vector type for broadcast.");
6022 SDValue Ld;
6023 bool ConstSplatVal;
6025 switch (Op.getOpcode()) {
6026 default:
6027 // Unknown pattern found.
6028 return SDValue();
6030 case ISD::BUILD_VECTOR: {
6031 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6032 BitVector UndefElements;
6033 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6035 // We need a splat of a single value to use broadcast, and it doesn't
6036 // make any sense if the value is only in one element of the vector.
6037 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6038 return SDValue();
6040 Ld = Splat;
6041 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6042 Ld.getOpcode() == ISD::ConstantFP);
6044 // Make sure that all of the users of a non-constant load are from the
6045 // BUILD_VECTOR node.
6046 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6047 return SDValue();
6048 break;
6049 }
6051 case ISD::VECTOR_SHUFFLE: {
6052 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6054 // Shuffles must have a splat mask where the first element is
6055 // broadcasted.
6056 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6057 return SDValue();
6059 SDValue Sc = Op.getOperand(0);
6060 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6061 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6063 if (!Subtarget->hasInt256())
6064 return SDValue();
6066 // Use the register form of the broadcast instruction available on AVX2.
6067 if (VT.getSizeInBits() >= 256)
6068 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6069 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6070 }
6072 Ld = Sc.getOperand(0);
6073 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6074 Ld.getOpcode() == ISD::ConstantFP);
6076 // The scalar_to_vector node and the suspected
6077 // load node must have exactly one user.
6078 // Constants may have multiple users.
6080 // AVX-512 has register version of the broadcast
6081 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6082 Ld.getValueType().getSizeInBits() >= 32;
6083 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6084 !hasRegVer))
6085 return SDValue();
6086 break;
6087 }
6088 }
6090 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6091 bool IsGE256 = (VT.getSizeInBits() >= 256);
6093 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6094 // instruction to save 8 or more bytes of constant pool data.
6095 // TODO: If multiple splats are generated to load the same constant,
6096 // it may be detrimental to overall size. There needs to be a way to detect
6097 // that condition to know if this is truly a size win.
6098 const Function *F = DAG.getMachineFunction().getFunction();
6099 bool OptForSize = F->getAttributes().
6100 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6102 // Handle broadcasting a single constant scalar from the constant pool
6103 // into a vector.
6104 // On Sandybridge (no AVX2), it is still better to load a constant vector
6105 // from the constant pool and not to broadcast it from a scalar.
6106 // But override that restriction when optimizing for size.
6107 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6108 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6109 EVT CVT = Ld.getValueType();
6110 assert(!CVT.isVector() && "Must not broadcast a vector type");
6112 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6113 // For size optimization, also splat v2f64 and v2i64, and for size opt
6114 // with AVX2, also splat i8 and i16.
6115 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6116 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6117 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6118 const Constant *C = nullptr;
6119 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6120 C = CI->getConstantIntValue();
6121 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6122 C = CF->getConstantFPValue();
6124 assert(C && "Invalid constant type");
6126 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6127 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6128 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6129 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6130 MachinePointerInfo::getConstantPool(),
6131 false, false, false, Alignment);
6133 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6134 }
6135 }
6137 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6139 // Handle AVX2 in-register broadcasts.
6140 if (!IsLoad && Subtarget->hasInt256() &&
6141 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6142 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6144 // The scalar source must be a normal load.
6145 if (!IsLoad)
6146 return SDValue();
6148 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6149 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6151 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6152 // double since there is no vbroadcastsd xmm
6153 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6154 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6155 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6156 }
6158 // Unsupported broadcast.
6159 return SDValue();
6160 }
6162 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6163 /// underlying vector and index.
6164 ///
6165 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6166 /// index.
6167 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6168 SDValue ExtIdx) {
6169 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6170 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6171 return Idx;
6173 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6174 // lowered this:
6175 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6176 // to:
6177 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6178 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6179 // undef)
6180 // Constant<0>)
6181 // In this case the vector is the extract_subvector expression and the index
6182 // is 2, as specified by the shuffle.
6183 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6184 SDValue ShuffleVec = SVOp->getOperand(0);
6185 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6186 assert(ShuffleVecVT.getVectorElementType() ==
6187 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6189 int ShuffleIdx = SVOp->getMaskElt(Idx);
6190 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6191 ExtractedFromVec = ShuffleVec;
6192 return ShuffleIdx;
6193 }
6194 return Idx;
6195 }
6197 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6198 MVT VT = Op.getSimpleValueType();
6200 // Skip if insert_vec_elt is not supported.
6201 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6202 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6203 return SDValue();
6205 SDLoc DL(Op);
6206 unsigned NumElems = Op.getNumOperands();
6208 SDValue VecIn1;
6209 SDValue VecIn2;
6210 SmallVector<unsigned, 4> InsertIndices;
6211 SmallVector<int, 8> Mask(NumElems, -1);
6213 for (unsigned i = 0; i != NumElems; ++i) {
6214 unsigned Opc = Op.getOperand(i).getOpcode();
6216 if (Opc == ISD::UNDEF)
6217 continue;
6219 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6220 // Quit if more than 1 elements need inserting.
6221 if (InsertIndices.size() > 1)
6222 return SDValue();
6224 InsertIndices.push_back(i);
6225 continue;
6226 }
6228 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6229 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6230 // Quit if non-constant index.
6231 if (!isa<ConstantSDNode>(ExtIdx))
6232 return SDValue();
6233 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6235 // Quit if extracted from vector of different type.
6236 if (ExtractedFromVec.getValueType() != VT)
6237 return SDValue();
6239 if (!VecIn1.getNode())
6240 VecIn1 = ExtractedFromVec;
6241 else if (VecIn1 != ExtractedFromVec) {
6242 if (!VecIn2.getNode())
6243 VecIn2 = ExtractedFromVec;
6244 else if (VecIn2 != ExtractedFromVec)
6245 // Quit if more than 2 vectors to shuffle
6246 return SDValue();
6247 }
6249 if (ExtractedFromVec == VecIn1)
6250 Mask[i] = Idx;
6251 else if (ExtractedFromVec == VecIn2)
6252 Mask[i] = Idx + NumElems;
6253 }
6255 if (!VecIn1.getNode())
6256 return SDValue();
6258 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6259 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6260 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6261 unsigned Idx = InsertIndices[i];
6262 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6263 DAG.getIntPtrConstant(Idx));
6264 }
6266 return NV;
6267 }
6269 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6270 SDValue
6271 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6273 MVT VT = Op.getSimpleValueType();
6274 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6275 "Unexpected type in LowerBUILD_VECTORvXi1!");
6277 SDLoc dl(Op);
6278 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6279 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6280 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6281 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6282 }
6284 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6285 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6286 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6287 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6288 }
6290 bool AllContants = true;
6291 uint64_t Immediate = 0;
6292 int NonConstIdx = -1;
6293 bool IsSplat = true;
6294 unsigned NumNonConsts = 0;
6295 unsigned NumConsts = 0;
6296 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6297 SDValue In = Op.getOperand(idx);
6298 if (In.getOpcode() == ISD::UNDEF)
6299 continue;
6300 if (!isa<ConstantSDNode>(In)) {
6301 AllContants = false;
6302 NonConstIdx = idx;
6303 NumNonConsts++;
6304 }
6305 else {
6306 NumConsts++;
6307 if (cast<ConstantSDNode>(In)->getZExtValue())
6308 Immediate |= (1ULL << idx);
6309 }
6310 if (In != Op.getOperand(0))
6311 IsSplat = false;
6312 }
6314 if (AllContants) {
6315 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6316 DAG.getConstant(Immediate, MVT::i16));
6317 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6318 DAG.getIntPtrConstant(0));
6319 }
6321 if (NumNonConsts == 1 && NonConstIdx != 0) {
6322 SDValue DstVec;
6323 if (NumConsts) {
6324 SDValue VecAsImm = DAG.getConstant(Immediate,
6325 MVT::getIntegerVT(VT.getSizeInBits()));
6326 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6327 }
6328 else
6329 DstVec = DAG.getUNDEF(VT);
6330 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6331 Op.getOperand(NonConstIdx),
6332 DAG.getIntPtrConstant(NonConstIdx));
6333 }
6334 if (!IsSplat && (NonConstIdx != 0))
6335 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6336 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6337 SDValue Select;
6338 if (IsSplat)
6339 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6340 DAG.getConstant(-1, SelectVT),
6341 DAG.getConstant(0, SelectVT));
6342 else
6343 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6344 DAG.getConstant((Immediate | 1), SelectVT),
6345 DAG.getConstant(Immediate, SelectVT));
6346 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6347 }
6349 /// \brief Return true if \p N implements a horizontal binop and return the
6350 /// operands for the horizontal binop into V0 and V1.
6351 ///
6352 /// This is a helper function of PerformBUILD_VECTORCombine.
6353 /// This function checks that the build_vector \p N in input implements a
6354 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6355 /// operation to match.
6356 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6357 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6358 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6359 /// arithmetic sub.
6360 ///
6361 /// This function only analyzes elements of \p N whose indices are
6362 /// in range [BaseIdx, LastIdx).
6363 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6364 SelectionDAG &DAG,
6365 unsigned BaseIdx, unsigned LastIdx,
6366 SDValue &V0, SDValue &V1) {
6367 EVT VT = N->getValueType(0);
6369 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6370 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6371 "Invalid Vector in input!");
6373 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6374 bool CanFold = true;
6375 unsigned ExpectedVExtractIdx = BaseIdx;
6376 unsigned NumElts = LastIdx - BaseIdx;
6377 V0 = DAG.getUNDEF(VT);
6378 V1 = DAG.getUNDEF(VT);
6380 // Check if N implements a horizontal binop.
6381 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6382 SDValue Op = N->getOperand(i + BaseIdx);
6384 // Skip UNDEFs.
6385 if (Op->getOpcode() == ISD::UNDEF) {
6386 // Update the expected vector extract index.
6387 if (i * 2 == NumElts)
6388 ExpectedVExtractIdx = BaseIdx;
6389 ExpectedVExtractIdx += 2;
6390 continue;
6391 }
6393 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6395 if (!CanFold)
6396 break;
6398 SDValue Op0 = Op.getOperand(0);
6399 SDValue Op1 = Op.getOperand(1);
6401 // Try to match the following pattern:
6402 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6403 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6404 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6405 Op0.getOperand(0) == Op1.getOperand(0) &&
6406 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6407 isa<ConstantSDNode>(Op1.getOperand(1)));
6408 if (!CanFold)
6409 break;
6411 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6412 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6414 if (i * 2 < NumElts) {
6415 if (V0.getOpcode() == ISD::UNDEF)
6416 V0 = Op0.getOperand(0);
6417 } else {
6418 if (V1.getOpcode() == ISD::UNDEF)
6419 V1 = Op0.getOperand(0);
6420 if (i * 2 == NumElts)
6421 ExpectedVExtractIdx = BaseIdx;
6422 }
6424 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6425 if (I0 == ExpectedVExtractIdx)
6426 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6427 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6428 // Try to match the following dag sequence:
6429 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6430 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6431 } else
6432 CanFold = false;
6434 ExpectedVExtractIdx += 2;
6435 }
6437 return CanFold;
6438 }
6440 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6441 /// a concat_vector.
6442 ///
6443 /// This is a helper function of PerformBUILD_VECTORCombine.
6444 /// This function expects two 256-bit vectors called V0 and V1.
6445 /// At first, each vector is split into two separate 128-bit vectors.
6446 /// Then, the resulting 128-bit vectors are used to implement two
6447 /// horizontal binary operations.
6448 ///
6449 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6450 ///
6451 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6452 /// the two new horizontal binop.
6453 /// When Mode is set, the first horizontal binop dag node would take as input
6454 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6455 /// horizontal binop dag node would take as input the lower 128-bit of V1
6456 /// and the upper 128-bit of V1.
6457 /// Example:
6458 /// HADD V0_LO, V0_HI
6459 /// HADD V1_LO, V1_HI
6460 ///
6461 /// Otherwise, the first horizontal binop dag node takes as input the lower
6462 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6463 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6464 /// Example:
6465 /// HADD V0_LO, V1_LO
6466 /// HADD V0_HI, V1_HI
6467 ///
6468 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6469 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6470 /// the upper 128-bits of the result.
6471 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6472 SDLoc DL, SelectionDAG &DAG,
6473 unsigned X86Opcode, bool Mode,
6474 bool isUndefLO, bool isUndefHI) {
6475 EVT VT = V0.getValueType();
6476 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6477 "Invalid nodes in input!");
6479 unsigned NumElts = VT.getVectorNumElements();
6480 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6481 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6482 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6483 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6484 EVT NewVT = V0_LO.getValueType();
6486 SDValue LO = DAG.getUNDEF(NewVT);
6487 SDValue HI = DAG.getUNDEF(NewVT);
6489 if (Mode) {
6490 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6491 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6492 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6493 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6494 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6495 } else {
6496 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6497 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6498 V1_LO->getOpcode() != ISD::UNDEF))
6499 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6501 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6502 V1_HI->getOpcode() != ISD::UNDEF))
6503 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6504 }
6506 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6507 }
6509 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6510 /// sequence of 'vadd + vsub + blendi'.
6511 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6512 const X86Subtarget *Subtarget) {
6513 SDLoc DL(BV);
6514 EVT VT = BV->getValueType(0);
6515 unsigned NumElts = VT.getVectorNumElements();
6516 SDValue InVec0 = DAG.getUNDEF(VT);
6517 SDValue InVec1 = DAG.getUNDEF(VT);
6519 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6520 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6522 // Odd-numbered elements in the input build vector are obtained from
6523 // adding two integer/float elements.
6524 // Even-numbered elements in the input build vector are obtained from
6525 // subtracting two integer/float elements.
6526 unsigned ExpectedOpcode = ISD::FSUB;
6527 unsigned NextExpectedOpcode = ISD::FADD;
6528 bool AddFound = false;
6529 bool SubFound = false;
6531 for (unsigned i = 0, e = NumElts; i != e; i++) {
6532 SDValue Op = BV->getOperand(i);
6534 // Skip 'undef' values.
6535 unsigned Opcode = Op.getOpcode();
6536 if (Opcode == ISD::UNDEF) {
6537 std::swap(ExpectedOpcode, NextExpectedOpcode);
6538 continue;
6539 }
6541 // Early exit if we found an unexpected opcode.
6542 if (Opcode != ExpectedOpcode)
6543 return SDValue();
6545 SDValue Op0 = Op.getOperand(0);
6546 SDValue Op1 = Op.getOperand(1);
6548 // Try to match the following pattern:
6549 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6550 // Early exit if we cannot match that sequence.
6551 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6552 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6553 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6554 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6555 Op0.getOperand(1) != Op1.getOperand(1))
6556 return SDValue();
6558 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6559 if (I0 != i)
6560 return SDValue();
6562 // We found a valid add/sub node. Update the information accordingly.
6563 if (i & 1)
6564 AddFound = true;
6565 else
6566 SubFound = true;
6568 // Update InVec0 and InVec1.
6569 if (InVec0.getOpcode() == ISD::UNDEF)
6570 InVec0 = Op0.getOperand(0);
6571 if (InVec1.getOpcode() == ISD::UNDEF)
6572 InVec1 = Op1.getOperand(0);
6574 // Make sure that operands in input to each add/sub node always
6575 // come from a same pair of vectors.
6576 if (InVec0 != Op0.getOperand(0)) {
6577 if (ExpectedOpcode == ISD::FSUB)
6578 return SDValue();
6580 // FADD is commutable. Try to commute the operands
6581 // and then test again.
6582 std::swap(Op0, Op1);
6583 if (InVec0 != Op0.getOperand(0))
6584 return SDValue();
6585 }
6587 if (InVec1 != Op1.getOperand(0))
6588 return SDValue();
6590 // Update the pair of expected opcodes.
6591 std::swap(ExpectedOpcode, NextExpectedOpcode);
6592 }
6594 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6595 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6596 InVec1.getOpcode() != ISD::UNDEF)
6597 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6599 return SDValue();
6600 }
6602 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6603 const X86Subtarget *Subtarget) {
6604 SDLoc DL(N);
6605 EVT VT = N->getValueType(0);
6606 unsigned NumElts = VT.getVectorNumElements();
6607 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6608 SDValue InVec0, InVec1;
6610 // Try to match an ADDSUB.
6611 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6612 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6613 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6614 if (Value.getNode())
6615 return Value;
6616 }
6618 // Try to match horizontal ADD/SUB.
6619 unsigned NumUndefsLO = 0;
6620 unsigned NumUndefsHI = 0;
6621 unsigned Half = NumElts/2;
6623 // Count the number of UNDEF operands in the build_vector in input.
6624 for (unsigned i = 0, e = Half; i != e; ++i)
6625 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6626 NumUndefsLO++;
6628 for (unsigned i = Half, e = NumElts; i != e; ++i)
6629 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6630 NumUndefsHI++;
6632 // Early exit if this is either a build_vector of all UNDEFs or all the
6633 // operands but one are UNDEF.
6634 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6635 return SDValue();
6637 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6638 // Try to match an SSE3 float HADD/HSUB.
6639 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6640 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6642 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6643 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6644 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6645 // Try to match an SSSE3 integer HADD/HSUB.
6646 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6647 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6649 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6650 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6651 }
6653 if (!Subtarget->hasAVX())
6654 return SDValue();
6656 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6657 // Try to match an AVX horizontal add/sub of packed single/double
6658 // precision floating point values from 256-bit vectors.
6659 SDValue InVec2, InVec3;
6660 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6661 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6662 ((InVec0.getOpcode() == ISD::UNDEF ||
6663 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6664 ((InVec1.getOpcode() == ISD::UNDEF ||
6665 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6666 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6668 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6669 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6670 ((InVec0.getOpcode() == ISD::UNDEF ||
6671 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6672 ((InVec1.getOpcode() == ISD::UNDEF ||
6673 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6674 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6675 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6676 // Try to match an AVX2 horizontal add/sub of signed integers.
6677 SDValue InVec2, InVec3;
6678 unsigned X86Opcode;
6679 bool CanFold = true;
6681 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6682 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6683 ((InVec0.getOpcode() == ISD::UNDEF ||
6684 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6685 ((InVec1.getOpcode() == ISD::UNDEF ||
6686 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6687 X86Opcode = X86ISD::HADD;
6688 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6689 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6690 ((InVec0.getOpcode() == ISD::UNDEF ||
6691 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6692 ((InVec1.getOpcode() == ISD::UNDEF ||
6693 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6694 X86Opcode = X86ISD::HSUB;
6695 else
6696 CanFold = false;
6698 if (CanFold) {
6699 // Fold this build_vector into a single horizontal add/sub.
6700 // Do this only if the target has AVX2.
6701 if (Subtarget->hasAVX2())
6702 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6704 // Do not try to expand this build_vector into a pair of horizontal
6705 // add/sub if we can emit a pair of scalar add/sub.
6706 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6707 return SDValue();
6709 // Convert this build_vector into a pair of horizontal binop followed by
6710 // a concat vector.
6711 bool isUndefLO = NumUndefsLO == Half;
6712 bool isUndefHI = NumUndefsHI == Half;
6713 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6714 isUndefLO, isUndefHI);
6715 }
6716 }
6718 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6719 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6720 unsigned X86Opcode;
6721 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6722 X86Opcode = X86ISD::HADD;
6723 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6724 X86Opcode = X86ISD::HSUB;
6725 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6726 X86Opcode = X86ISD::FHADD;
6727 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6728 X86Opcode = X86ISD::FHSUB;
6729 else
6730 return SDValue();
6732 // Don't try to expand this build_vector into a pair of horizontal add/sub
6733 // if we can simply emit a pair of scalar add/sub.
6734 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6735 return SDValue();
6737 // Convert this build_vector into two horizontal add/sub followed by
6738 // a concat vector.
6739 bool isUndefLO = NumUndefsLO == Half;
6740 bool isUndefHI = NumUndefsHI == Half;
6741 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6742 isUndefLO, isUndefHI);
6743 }
6745 return SDValue();
6746 }
6748 SDValue
6749 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6750 SDLoc dl(Op);
6752 MVT VT = Op.getSimpleValueType();
6753 MVT ExtVT = VT.getVectorElementType();
6754 unsigned NumElems = Op.getNumOperands();
6756 // Generate vectors for predicate vectors.
6757 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6758 return LowerBUILD_VECTORvXi1(Op, DAG);
6760 // Vectors containing all zeros can be matched by pxor and xorps later
6761 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6762 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6763 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6764 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6765 return Op;
6767 return getZeroVector(VT, Subtarget, DAG, dl);
6768 }
6770 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6771 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6772 // vpcmpeqd on 256-bit vectors.
6773 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6774 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6775 return Op;
6777 if (!VT.is512BitVector())
6778 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6779 }
6781 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6782 if (Broadcast.getNode())
6783 return Broadcast;
6785 unsigned EVTBits = ExtVT.getSizeInBits();
6787 unsigned NumZero = 0;
6788 unsigned NumNonZero = 0;
6789 unsigned NonZeros = 0;
6790 bool IsAllConstants = true;
6791 SmallSet<SDValue, 8> Values;
6792 for (unsigned i = 0; i < NumElems; ++i) {
6793 SDValue Elt = Op.getOperand(i);
6794 if (Elt.getOpcode() == ISD::UNDEF)
6795 continue;
6796 Values.insert(Elt);
6797 if (Elt.getOpcode() != ISD::Constant &&
6798 Elt.getOpcode() != ISD::ConstantFP)
6799 IsAllConstants = false;
6800 if (X86::isZeroNode(Elt))
6801 NumZero++;
6802 else {
6803 NonZeros |= (1 << i);
6804 NumNonZero++;
6805 }
6806 }
6808 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6809 if (NumNonZero == 0)
6810 return DAG.getUNDEF(VT);
6812 // Special case for single non-zero, non-undef, element.
6813 if (NumNonZero == 1) {
6814 unsigned Idx = countTrailingZeros(NonZeros);
6815 SDValue Item = Op.getOperand(Idx);
6817 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6818 // the value are obviously zero, truncate the value to i32 and do the
6819 // insertion that way. Only do this if the value is non-constant or if the
6820 // value is a constant being inserted into element 0. It is cheaper to do
6821 // a constant pool load than it is to do a movd + shuffle.
6822 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6823 (!IsAllConstants || Idx == 0)) {
6824 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6825 // Handle SSE only.
6826 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6827 EVT VecVT = MVT::v4i32;
6828 unsigned VecElts = 4;
6830 // Truncate the value (which may itself be a constant) to i32, and
6831 // convert it to a vector with movd (S2V+shuffle to zero extend).
6832 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6833 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6835 // If using the new shuffle lowering, just directly insert this.
6836 if (ExperimentalVectorShuffleLowering)
6837 return DAG.getNode(
6838 ISD::BITCAST, dl, VT,
6839 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6841 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6843 // Now we have our 32-bit value zero extended in the low element of
6844 // a vector. If Idx != 0, swizzle it into place.
6845 if (Idx != 0) {
6846 SmallVector<int, 4> Mask;
6847 Mask.push_back(Idx);
6848 for (unsigned i = 1; i != VecElts; ++i)
6849 Mask.push_back(i);
6850 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6851 &Mask[0]);
6852 }
6853 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6854 }
6855 }
6857 // If we have a constant or non-constant insertion into the low element of
6858 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6859 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6860 // depending on what the source datatype is.
6861 if (Idx == 0) {
6862 if (NumZero == 0)
6863 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6865 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6866 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6867 if (VT.is256BitVector() || VT.is512BitVector()) {
6868 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6869 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6870 Item, DAG.getIntPtrConstant(0));
6871 }
6872 assert(VT.is128BitVector() && "Expected an SSE value type!");
6873 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6874 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6875 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6876 }
6878 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6879 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6880 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6881 if (VT.is256BitVector()) {
6882 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6883 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6884 } else {
6885 assert(VT.is128BitVector() && "Expected an SSE value type!");
6886 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6887 }
6888 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6889 }
6890 }
6892 // Is it a vector logical left shift?
6893 if (NumElems == 2 && Idx == 1 &&
6894 X86::isZeroNode(Op.getOperand(0)) &&
6895 !X86::isZeroNode(Op.getOperand(1))) {
6896 unsigned NumBits = VT.getSizeInBits();
6897 return getVShift(true, VT,
6898 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6899 VT, Op.getOperand(1)),
6900 NumBits/2, DAG, *this, dl);
6901 }
6903 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6904 return SDValue();
6906 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6907 // is a non-constant being inserted into an element other than the low one,
6908 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6909 // movd/movss) to move this into the low element, then shuffle it into
6910 // place.
6911 if (EVTBits == 32) {
6912 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6914 // If using the new shuffle lowering, just directly insert this.
6915 if (ExperimentalVectorShuffleLowering)
6916 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6918 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6919 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6920 SmallVector<int, 8> MaskVec;
6921 for (unsigned i = 0; i != NumElems; ++i)
6922 MaskVec.push_back(i == Idx ? 0 : 1);
6923 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6924 }
6925 }
6927 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6928 if (Values.size() == 1) {
6929 if (EVTBits == 32) {
6930 // Instead of a shuffle like this:
6931 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6932 // Check if it's possible to issue this instead.
6933 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6934 unsigned Idx = countTrailingZeros(NonZeros);
6935 SDValue Item = Op.getOperand(Idx);
6936 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6937 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6938 }
6939 return SDValue();
6940 }
6942 // A vector full of immediates; various special cases are already
6943 // handled, so this is best done with a single constant-pool load.
6944 if (IsAllConstants)
6945 return SDValue();
6947 // For AVX-length vectors, build the individual 128-bit pieces and use
6948 // shuffles to put them in place.
6949 if (VT.is256BitVector() || VT.is512BitVector()) {
6950 SmallVector<SDValue, 64> V;
6951 for (unsigned i = 0; i != NumElems; ++i)
6952 V.push_back(Op.getOperand(i));
6954 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6956 // Build both the lower and upper subvector.
6957 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6958 makeArrayRef(&V[0], NumElems/2));
6959 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6960 makeArrayRef(&V[NumElems / 2], NumElems/2));
6962 // Recreate the wider vector with the lower and upper part.
6963 if (VT.is256BitVector())
6964 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6965 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6966 }
6968 // Let legalizer expand 2-wide build_vectors.
6969 if (EVTBits == 64) {
6970 if (NumNonZero == 1) {
6971 // One half is zero or undef.
6972 unsigned Idx = countTrailingZeros(NonZeros);
6973 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6974 Op.getOperand(Idx));
6975 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6976 }
6977 return SDValue();
6978 }
6980 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6981 if (EVTBits == 8 && NumElems == 16) {
6982 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6983 Subtarget, *this);
6984 if (V.getNode()) return V;
6985 }
6987 if (EVTBits == 16 && NumElems == 8) {
6988 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6989 Subtarget, *this);
6990 if (V.getNode()) return V;
6991 }
6993 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6994 if (EVTBits == 32 && NumElems == 4) {
6995 SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
6996 NumZero, DAG, Subtarget, *this);
6997 if (V.getNode())
6998 return V;
6999 }
7001 // If element VT is == 32 bits, turn it into a number of shuffles.
7002 SmallVector<SDValue, 8> V(NumElems);
7003 if (NumElems == 4 && NumZero > 0) {
7004 for (unsigned i = 0; i < 4; ++i) {
7005 bool isZero = !(NonZeros & (1 << i));
7006 if (isZero)
7007 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7008 else
7009 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7010 }
7012 for (unsigned i = 0; i < 2; ++i) {
7013 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7014 default: break;
7015 case 0:
7016 V[i] = V[i*2]; // Must be a zero vector.
7017 break;
7018 case 1:
7019 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7020 break;
7021 case 2:
7022 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7023 break;
7024 case 3:
7025 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7026 break;
7027 }
7028 }
7030 bool Reverse1 = (NonZeros & 0x3) == 2;
7031 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7032 int MaskVec[] = {
7033 Reverse1 ? 1 : 0,
7034 Reverse1 ? 0 : 1,
7035 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7036 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7037 };
7038 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7039 }
7041 if (Values.size() > 1 && VT.is128BitVector()) {
7042 // Check for a build vector of consecutive loads.
7043 for (unsigned i = 0; i < NumElems; ++i)
7044 V[i] = Op.getOperand(i);
7046 // Check for elements which are consecutive loads.
7047 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7048 if (LD.getNode())
7049 return LD;
7051 // Check for a build vector from mostly shuffle plus few inserting.
7052 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7053 if (Sh.getNode())
7054 return Sh;
7056 // For SSE 4.1, use insertps to put the high elements into the low element.
7057 if (getSubtarget()->hasSSE41()) {
7058 SDValue Result;
7059 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7060 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7061 else
7062 Result = DAG.getUNDEF(VT);
7064 for (unsigned i = 1; i < NumElems; ++i) {
7065 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7066 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7067 Op.getOperand(i), DAG.getIntPtrConstant(i));
7068 }
7069 return Result;
7070 }
7072 // Otherwise, expand into a number of unpckl*, start by extending each of
7073 // our (non-undef) elements to the full vector width with the element in the
7074 // bottom slot of the vector (which generates no code for SSE).
7075 for (unsigned i = 0; i < NumElems; ++i) {
7076 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7077 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7078 else
7079 V[i] = DAG.getUNDEF(VT);
7080 }
7082 // Next, we iteratively mix elements, e.g. for v4f32:
7083 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7084 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7085 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7086 unsigned EltStride = NumElems >> 1;
7087 while (EltStride != 0) {
7088 for (unsigned i = 0; i < EltStride; ++i) {
7089 // If V[i+EltStride] is undef and this is the first round of mixing,
7090 // then it is safe to just drop this shuffle: V[i] is already in the
7091 // right place, the one element (since it's the first round) being
7092 // inserted as undef can be dropped. This isn't safe for successive
7093 // rounds because they will permute elements within both vectors.
7094 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7095 EltStride == NumElems/2)
7096 continue;
7098 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7099 }
7100 EltStride >>= 1;
7101 }
7102 return V[0];
7103 }
7104 return SDValue();
7105 }
7107 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7108 // to create 256-bit vectors from two other 128-bit ones.
7109 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7110 SDLoc dl(Op);
7111 MVT ResVT = Op.getSimpleValueType();
7113 assert((ResVT.is256BitVector() ||
7114 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7116 SDValue V1 = Op.getOperand(0);
7117 SDValue V2 = Op.getOperand(1);
7118 unsigned NumElems = ResVT.getVectorNumElements();
7119 if(ResVT.is256BitVector())
7120 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7122 if (Op.getNumOperands() == 4) {
7123 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7124 ResVT.getVectorNumElements()/2);
7125 SDValue V3 = Op.getOperand(2);
7126 SDValue V4 = Op.getOperand(3);
7127 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7128 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7129 }
7130 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7131 }
7133 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7134 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7135 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7136 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7137 Op.getNumOperands() == 4)));
7139 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7140 // from two other 128-bit ones.
7142 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7143 return LowerAVXCONCAT_VECTORS(Op, DAG);
7144 }
7147 //===----------------------------------------------------------------------===//
7148 // Vector shuffle lowering
7149 //
7150 // This is an experimental code path for lowering vector shuffles on x86. It is
7151 // designed to handle arbitrary vector shuffles and blends, gracefully
7152 // degrading performance as necessary. It works hard to recognize idiomatic
7153 // shuffles and lower them to optimal instruction patterns without leaving
7154 // a framework that allows reasonably efficient handling of all vector shuffle
7155 // patterns.
7156 //===----------------------------------------------------------------------===//
7158 /// \brief Tiny helper function to identify a no-op mask.
7159 ///
7160 /// This is a somewhat boring predicate function. It checks whether the mask
7161 /// array input, which is assumed to be a single-input shuffle mask of the kind
7162 /// used by the X86 shuffle instructions (not a fully general
7163 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7164 /// in-place shuffle are 'no-op's.
7165 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7166 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7167 if (Mask[i] != -1 && Mask[i] != i)
7168 return false;
7169 return true;
7170 }
7172 /// \brief Helper function to classify a mask as a single-input mask.
7173 ///
7174 /// This isn't a generic single-input test because in the vector shuffle
7175 /// lowering we canonicalize single inputs to be the first input operand. This
7176 /// means we can more quickly test for a single input by only checking whether
7177 /// an input from the second operand exists. We also assume that the size of
7178 /// mask corresponds to the size of the input vectors which isn't true in the
7179 /// fully general case.
7180 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7181 for (int M : Mask)
7182 if (M >= (int)Mask.size())
7183 return false;
7184 return true;
7185 }
7187 /// \brief Test whether there are elements crossing 128-bit lanes in this
7188 /// shuffle mask.
7189 ///
7190 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7191 /// and we routinely test for these.
7192 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7193 int LaneSize = 128 / VT.getScalarSizeInBits();
7194 int Size = Mask.size();
7195 for (int i = 0; i < Size; ++i)
7196 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7197 return true;
7198 return false;
7199 }
7201 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7202 ///
7203 /// This checks a shuffle mask to see if it is performing the same
7204 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7205 /// that it is also not lane-crossing. It may however involve a blend from the
7206 /// same lane of a second vector.
7207 ///
7208 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7209 /// non-trivial to compute in the face of undef lanes. The representation is
7210 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7211 /// entries from both V1 and V2 inputs to the wider mask.
7212 static bool
7213 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7214 SmallVectorImpl<int> &RepeatedMask) {
7215 int LaneSize = 128 / VT.getScalarSizeInBits();
7216 RepeatedMask.resize(LaneSize, -1);
7217 int Size = Mask.size();
7218 for (int i = 0; i < Size; ++i) {
7219 if (Mask[i] < 0)
7220 continue;
7221 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7222 // This entry crosses lanes, so there is no way to model this shuffle.
7223 return false;
7225 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7226 if (RepeatedMask[i % LaneSize] == -1)
7227 // This is the first non-undef entry in this slot of a 128-bit lane.
7228 RepeatedMask[i % LaneSize] =
7229 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7230 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7231 // Found a mismatch with the repeated mask.
7232 return false;
7233 }
7234 return true;
7235 }
7237 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7238 // 2013 will allow us to use it as a non-type template parameter.
7239 namespace {
7241 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7242 ///
7243 /// See its documentation for details.
7244 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7245 if (Mask.size() != Args.size())
7246 return false;
7247 for (int i = 0, e = Mask.size(); i < e; ++i) {
7248 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7249 if (Mask[i] != -1 && Mask[i] != *Args[i])
7250 return false;
7251 }
7252 return true;
7253 }
7255 } // namespace
7257 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7258 /// arguments.
7259 ///
7260 /// This is a fast way to test a shuffle mask against a fixed pattern:
7261 ///
7262 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7263 ///
7264 /// It returns true if the mask is exactly as wide as the argument list, and
7265 /// each element of the mask is either -1 (signifying undef) or the value given
7266 /// in the argument.
7267 static const VariadicFunction1<
7268 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7270 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7271 ///
7272 /// This helper function produces an 8-bit shuffle immediate corresponding to
7273 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7274 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7275 /// example.
7276 ///
7277 /// NB: We rely heavily on "undef" masks preserving the input lane.
7278 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7279 SelectionDAG &DAG) {
7280 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7281 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7282 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7283 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7284 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7286 unsigned Imm = 0;
7287 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7288 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7289 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7290 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7291 return DAG.getConstant(Imm, MVT::i8);
7292 }
7294 /// \brief Try to emit a blend instruction for a shuffle.
7295 ///
7296 /// This doesn't do any checks for the availability of instructions for blending
7297 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7298 /// be matched in the backend with the type given. What it does check for is
7299 /// that the shuffle mask is in fact a blend.
7300 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7301 SDValue V2, ArrayRef<int> Mask,
7302 const X86Subtarget *Subtarget,
7303 SelectionDAG &DAG) {
7305 unsigned BlendMask = 0;
7306 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7307 if (Mask[i] >= Size) {
7308 if (Mask[i] != i + Size)
7309 return SDValue(); // Shuffled V2 input!
7310 BlendMask |= 1u << i;
7311 continue;
7312 }
7313 if (Mask[i] >= 0 && Mask[i] != i)
7314 return SDValue(); // Shuffled V1 input!
7315 }
7316 switch (VT.SimpleTy) {
7317 case MVT::v2f64:
7318 case MVT::v4f32:
7319 case MVT::v4f64:
7320 case MVT::v8f32:
7321 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7322 DAG.getConstant(BlendMask, MVT::i8));
7324 case MVT::v4i64:
7325 case MVT::v8i32:
7326 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7327 // FALLTHROUGH
7328 case MVT::v2i64:
7329 case MVT::v4i32:
7330 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7331 // that instruction.
7332 if (Subtarget->hasAVX2()) {
7333 // Scale the blend by the number of 32-bit dwords per element.
7334 int Scale = VT.getScalarSizeInBits() / 32;
7335 BlendMask = 0;
7336 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7337 if (Mask[i] >= Size)
7338 for (int j = 0; j < Scale; ++j)
7339 BlendMask |= 1u << (i * Scale + j);
7341 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7342 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7343 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7344 return DAG.getNode(ISD::BITCAST, DL, VT,
7345 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7346 DAG.getConstant(BlendMask, MVT::i8)));
7347 }
7348 // FALLTHROUGH
7349 case MVT::v8i16: {
7350 // For integer shuffles we need to expand the mask and cast the inputs to
7351 // v8i16s prior to blending.
7352 int Scale = 8 / VT.getVectorNumElements();
7353 BlendMask = 0;
7354 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7355 if (Mask[i] >= Size)
7356 for (int j = 0; j < Scale; ++j)
7357 BlendMask |= 1u << (i * Scale + j);
7359 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7360 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7361 return DAG.getNode(ISD::BITCAST, DL, VT,
7362 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7363 DAG.getConstant(BlendMask, MVT::i8)));
7364 }
7366 case MVT::v16i16: {
7367 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7368 SmallVector<int, 8> RepeatedMask;
7369 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7370 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7371 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7372 BlendMask = 0;
7373 for (int i = 0; i < 8; ++i)
7374 if (RepeatedMask[i] >= 16)
7375 BlendMask |= 1u << i;
7376 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7377 DAG.getConstant(BlendMask, MVT::i8));
7378 }
7379 }
7380 // FALLTHROUGH
7381 case MVT::v32i8: {
7382 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7383 // Scale the blend by the number of bytes per element.
7384 int Scale = VT.getScalarSizeInBits() / 8;
7385 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7387 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7388 // mix of LLVM's code generator and the x86 backend. We tell the code
7389 // generator that boolean values in the elements of an x86 vector register
7390 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7391 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7392 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7393 // of the element (the remaining are ignored) and 0 in that high bit would
7394 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7395 // the LLVM model for boolean values in vector elements gets the relevant
7396 // bit set, it is set backwards and over constrained relative to x86's
7397 // actual model.
7398 SDValue VSELECTMask[32];
7399 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7400 for (int j = 0; j < Scale; ++j)
7401 VSELECTMask[Scale * i + j] =
7402 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7403 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8);
7405 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7406 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7407 return DAG.getNode(
7408 ISD::BITCAST, DL, VT,
7409 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8,
7410 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, VSELECTMask),
7411 V1, V2));
7412 }
7414 default:
7415 llvm_unreachable("Not a supported integer vector type!");
7416 }
7417 }
7419 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7420 /// unblended shuffles followed by an unshuffled blend.
7421 ///
7422 /// This matches the extremely common pattern for handling combined
7423 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7424 /// operations.
7425 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7426 SDValue V1,
7427 SDValue V2,
7428 ArrayRef<int> Mask,
7429 SelectionDAG &DAG) {
7430 // Shuffle the input elements into the desired positions in V1 and V2 and
7431 // blend them together.
7432 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7433 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7434 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7435 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7436 if (Mask[i] >= 0 && Mask[i] < Size) {
7437 V1Mask[i] = Mask[i];
7438 BlendMask[i] = i;
7439 } else if (Mask[i] >= Size) {
7440 V2Mask[i] = Mask[i] - Size;
7441 BlendMask[i] = i + Size;
7442 }
7444 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7445 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7446 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7447 }
7449 /// \brief Try to lower a vector shuffle as a byte rotation.
7450 ///
7451 /// We have a generic PALIGNR instruction in x86 that will do an arbitrary
7452 /// byte-rotation of a the concatentation of two vectors. This routine will
7453 /// try to generically lower a vector shuffle through such an instruction. It
7454 /// does not check for the availability of PALIGNR-based lowerings, only the
7455 /// applicability of this strategy to the given mask. This matches shuffle
7456 /// vectors that look like:
7457 ///
7458 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7459 ///
7460 /// Essentially it concatenates V1 and V2, shifts right by some number of
7461 /// elements, and takes the low elements as the result. Note that while this is
7462 /// specified as a *right shift* because x86 is little-endian, it is a *left
7463 /// rotate* of the vector lanes.
7464 ///
7465 /// Note that this only handles 128-bit vector widths currently.
7466 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7467 SDValue V2,
7468 ArrayRef<int> Mask,
7469 SelectionDAG &DAG) {
7470 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7472 // We need to detect various ways of spelling a rotation:
7473 // [11, 12, 13, 14, 15, 0, 1, 2]
7474 // [-1, 12, 13, 14, -1, -1, 1, -1]
7475 // [-1, -1, -1, -1, -1, -1, 1, 2]
7476 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7477 // [-1, 4, 5, 6, -1, -1, 9, -1]
7478 // [-1, 4, 5, 6, -1, -1, -1, -1]
7479 int Rotation = 0;
7480 SDValue Lo, Hi;
7481 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7482 if (Mask[i] == -1)
7483 continue;
7484 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7486 // Based on the mod-Size value of this mask element determine where
7487 // a rotated vector would have started.
7488 int StartIdx = i - (Mask[i] % Size);
7489 if (StartIdx == 0)
7490 // The identity rotation isn't interesting, stop.
7491 return SDValue();
7493 // If we found the tail of a vector the rotation must be the missing
7494 // front. If we found the head of a vector, it must be how much of the head.
7495 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7497 if (Rotation == 0)
7498 Rotation = CandidateRotation;
7499 else if (Rotation != CandidateRotation)
7500 // The rotations don't match, so we can't match this mask.
7501 return SDValue();
7503 // Compute which value this mask is pointing at.
7504 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7506 // Compute which of the two target values this index should be assigned to.
7507 // This reflects whether the high elements are remaining or the low elements
7508 // are remaining.
7509 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7511 // Either set up this value if we've not encountered it before, or check
7512 // that it remains consistent.
7513 if (!TargetV)
7514 TargetV = MaskV;
7515 else if (TargetV != MaskV)
7516 // This may be a rotation, but it pulls from the inputs in some
7517 // unsupported interleaving.
7518 return SDValue();
7519 }
7521 // Check that we successfully analyzed the mask, and normalize the results.
7522 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7523 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7524 if (!Lo)
7525 Lo = Hi;
7526 else if (!Hi)
7527 Hi = Lo;
7529 // Cast the inputs to v16i8 to match PALIGNR.
7530 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7531 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7533 assert(VT.getSizeInBits() == 128 &&
7534 "Rotate-based lowering only supports 128-bit lowering!");
7535 assert(Mask.size() <= 16 &&
7536 "Can shuffle at most 16 bytes in a 128-bit vector!");
7537 // The actual rotate instruction rotates bytes, so we need to scale the
7538 // rotation based on how many bytes are in the vector.
7539 int Scale = 16 / Mask.size();
7541 return DAG.getNode(ISD::BITCAST, DL, VT,
7542 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7543 DAG.getConstant(Rotation * Scale, MVT::i8)));
7544 }
7546 /// \brief Compute whether each element of a shuffle is zeroable.
7547 ///
7548 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7549 /// Either it is an undef element in the shuffle mask, the element of the input
7550 /// referenced is undef, or the element of the input referenced is known to be
7551 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7552 /// as many lanes with this technique as possible to simplify the remaining
7553 /// shuffle.
7554 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7555 SDValue V1, SDValue V2) {
7556 SmallBitVector Zeroable(Mask.size(), false);
7558 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7559 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7561 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7562 int M = Mask[i];
7563 // Handle the easy cases.
7564 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7565 Zeroable[i] = true;
7566 continue;
7567 }
7569 // If this is an index into a build_vector node, dig out the input value and
7570 // use it.
7571 SDValue V = M < Size ? V1 : V2;
7572 if (V.getOpcode() != ISD::BUILD_VECTOR)
7573 continue;
7575 SDValue Input = V.getOperand(M % Size);
7576 // The UNDEF opcode check really should be dead code here, but not quite
7577 // worth asserting on (it isn't invalid, just unexpected).
7578 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7579 Zeroable[i] = true;
7580 }
7582 return Zeroable;
7583 }
7585 /// \brief Lower a vector shuffle as a zero or any extension.
7586 ///
7587 /// Given a specific number of elements, element bit width, and extension
7588 /// stride, produce either a zero or any extension based on the available
7589 /// features of the subtarget.
7590 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7591 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7592 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7593 assert(Scale > 1 && "Need a scale to extend.");
7594 int EltBits = VT.getSizeInBits() / NumElements;
7595 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7596 "Only 8, 16, and 32 bit elements can be extended.");
7597 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7599 // Found a valid zext mask! Try various lowering strategies based on the
7600 // input type and available ISA extensions.
7601 if (Subtarget->hasSSE41()) {
7602 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7603 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7604 NumElements / Scale);
7605 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7606 return DAG.getNode(ISD::BITCAST, DL, VT,
7607 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7608 }
7610 // For any extends we can cheat for larger element sizes and use shuffle
7611 // instructions that can fold with a load and/or copy.
7612 if (AnyExt && EltBits == 32) {
7613 int PSHUFDMask[4] = {0, -1, 1, -1};
7614 return DAG.getNode(
7615 ISD::BITCAST, DL, VT,
7616 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7617 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7618 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7619 }
7620 if (AnyExt && EltBits == 16 && Scale > 2) {
7621 int PSHUFDMask[4] = {0, -1, 0, -1};
7622 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7623 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7624 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7625 int PSHUFHWMask[4] = {1, -1, -1, -1};
7626 return DAG.getNode(
7627 ISD::BITCAST, DL, VT,
7628 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7629 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7630 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7631 }
7633 // If this would require more than 2 unpack instructions to expand, use
7634 // pshufb when available. We can only use more than 2 unpack instructions
7635 // when zero extending i8 elements which also makes it easier to use pshufb.
7636 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7637 assert(NumElements == 16 && "Unexpected byte vector width!");
7638 SDValue PSHUFBMask[16];
7639 for (int i = 0; i < 16; ++i)
7640 PSHUFBMask[i] =
7641 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7642 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7643 return DAG.getNode(ISD::BITCAST, DL, VT,
7644 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7645 DAG.getNode(ISD::BUILD_VECTOR, DL,
7646 MVT::v16i8, PSHUFBMask)));
7647 }
7649 // Otherwise emit a sequence of unpacks.
7650 do {
7651 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7652 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7653 : getZeroVector(InputVT, Subtarget, DAG, DL);
7654 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7655 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7656 Scale /= 2;
7657 EltBits *= 2;
7658 NumElements /= 2;
7659 } while (Scale > 1);
7660 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7661 }
7663 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7664 ///
7665 /// This routine will try to do everything in its power to cleverly lower
7666 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7667 /// check for the profitability of this lowering, it tries to aggressively
7668 /// match this pattern. It will use all of the micro-architectural details it
7669 /// can to emit an efficient lowering. It handles both blends with all-zero
7670 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7671 /// masking out later).
7672 ///
7673 /// The reason we have dedicated lowering for zext-style shuffles is that they
7674 /// are both incredibly common and often quite performance sensitive.
7675 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7676 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7677 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7678 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7680 int Bits = VT.getSizeInBits();
7681 int NumElements = Mask.size();
7683 // Define a helper function to check a particular ext-scale and lower to it if
7684 // valid.
7685 auto Lower = [&](int Scale) -> SDValue {
7686 SDValue InputV;
7687 bool AnyExt = true;
7688 for (int i = 0; i < NumElements; ++i) {
7689 if (Mask[i] == -1)
7690 continue; // Valid anywhere but doesn't tell us anything.
7691 if (i % Scale != 0) {
7692 // Each of the extend elements needs to be zeroable.
7693 if (!Zeroable[i])
7694 return SDValue();
7696 // We no lorger are in the anyext case.
7697 AnyExt = false;
7698 continue;
7699 }
7701 // Each of the base elements needs to be consecutive indices into the
7702 // same input vector.
7703 SDValue V = Mask[i] < NumElements ? V1 : V2;
7704 if (!InputV)
7705 InputV = V;
7706 else if (InputV != V)
7707 return SDValue(); // Flip-flopping inputs.
7709 if (Mask[i] % NumElements != i / Scale)
7710 return SDValue(); // Non-consecutive strided elemenst.
7711 }
7713 // If we fail to find an input, we have a zero-shuffle which should always
7714 // have already been handled.
7715 // FIXME: Maybe handle this here in case during blending we end up with one?
7716 if (!InputV)
7717 return SDValue();
7719 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7720 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7721 };
7723 // The widest scale possible for extending is to a 64-bit integer.
7724 assert(Bits % 64 == 0 &&
7725 "The number of bits in a vector must be divisible by 64 on x86!");
7726 int NumExtElements = Bits / 64;
7728 // Each iteration, try extending the elements half as much, but into twice as
7729 // many elements.
7730 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7731 assert(NumElements % NumExtElements == 0 &&
7732 "The input vector size must be divisble by the extended size.");
7733 if (SDValue V = Lower(NumElements / NumExtElements))
7734 return V;
7735 }
7737 // No viable ext lowering found.
7738 return SDValue();
7739 }
7741 /// \brief Try to lower insertion of a single element into a zero vector.
7742 ///
7743 /// This is a common pattern that we have especially efficient patterns to lower
7744 /// across all subtarget feature sets.
7745 static SDValue lowerVectorShuffleAsElementInsertion(
7746 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7747 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7748 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7750 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7751 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7752 Mask.begin();
7753 if (Mask.size() == 2) {
7754 if (!Zeroable[V2Index ^ 1]) {
7755 // For 2-wide masks we may be able to just invert the inputs. We use an xor
7756 // with 2 to flip from {2,3} to {0,1} and vice versa.
7757 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7758 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
7759 if (Zeroable[V2Index])
7760 return lowerVectorShuffleAsElementInsertion(VT, DL, V2, V1, InverseMask,
7761 Subtarget, DAG);
7762 else
7763 return SDValue();
7764 }
7765 } else {
7766 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7767 if (i != V2Index && !Zeroable[i])
7768 return SDValue(); // Not inserting into a zero vector.
7769 }
7771 // Step over any bitcasts on either input so we can scan the actual
7772 // BUILD_VECTOR nodes.
7773 while (V1.getOpcode() == ISD::BITCAST)
7774 V1 = V1.getOperand(0);
7775 while (V2.getOpcode() == ISD::BITCAST)
7776 V2 = V2.getOperand(0);
7778 // Check for a single input from a SCALAR_TO_VECTOR node.
7779 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7780 // all the smarts here sunk into that routine. However, the current
7781 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7782 // vector shuffle lowering is dead.
7783 if (!((V2.getOpcode() == ISD::SCALAR_TO_VECTOR &&
7784 Mask[V2Index] == (int)Mask.size()) ||
7785 V2.getOpcode() == ISD::BUILD_VECTOR))
7786 return SDValue();
7788 SDValue V2S = V2.getOperand(Mask[V2Index] - Mask.size());
7790 // First, we need to zext the scalar if it is smaller than an i32.
7791 MVT ExtVT = VT;
7792 MVT EltVT = VT.getVectorElementType();
7793 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7794 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7795 // Zero-extend directly to i32.
7796 ExtVT = MVT::v4i32;
7797 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7798 }
7800 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT,
7801 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S));
7802 if (ExtVT != VT)
7803 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7805 if (V2Index != 0) {
7806 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7807 // the desired position. Otherwise it is more efficient to do a vector
7808 // shift left. We know that we can do a vector shift left because all
7809 // the inputs are zero.
7810 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7811 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7812 V2Shuffle[V2Index] = 0;
7813 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7814 } else {
7815 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
7816 V2 = DAG.getNode(
7817 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7818 DAG.getConstant(
7819 V2Index * EltVT.getSizeInBits(),
7820 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7821 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7822 }
7823 }
7824 return V2;
7825 }
7827 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7828 ///
7829 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7830 /// support for floating point shuffles but not integer shuffles. These
7831 /// instructions will incur a domain crossing penalty on some chips though so
7832 /// it is better to avoid lowering through this for integer vectors where
7833 /// possible.
7834 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7835 const X86Subtarget *Subtarget,
7836 SelectionDAG &DAG) {
7837 SDLoc DL(Op);
7838 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7839 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7840 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7841 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7842 ArrayRef<int> Mask = SVOp->getMask();
7843 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7845 if (isSingleInputShuffleMask(Mask)) {
7846 // Straight shuffle of a single input vector. Simulate this by using the
7847 // single input as both of the "inputs" to this instruction..
7848 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7850 if (Subtarget->hasAVX()) {
7851 // If we have AVX, we can use VPERMILPS which will allow folding a load
7852 // into the shuffle.
7853 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7854 DAG.getConstant(SHUFPDMask, MVT::i8));
7855 }
7857 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
7858 DAG.getConstant(SHUFPDMask, MVT::i8));
7859 }
7860 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7861 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7863 // Use dedicated unpack instructions for masks that match their pattern.
7864 if (isShuffleEquivalent(Mask, 0, 2))
7865 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7866 if (isShuffleEquivalent(Mask, 1, 3))
7867 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7869 // If we have a single input, insert that into V1 if we can do so cheaply.
7870 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1)
7871 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7872 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
7873 return Insertion;
7875 if (Subtarget->hasSSE41())
7876 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
7877 Subtarget, DAG))
7878 return Blend;
7880 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7881 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
7882 DAG.getConstant(SHUFPDMask, MVT::i8));
7883 }
7885 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7886 ///
7887 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7888 /// the integer unit to minimize domain crossing penalties. However, for blends
7889 /// it falls back to the floating point shuffle operation with appropriate bit
7890 /// casting.
7891 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7892 const X86Subtarget *Subtarget,
7893 SelectionDAG &DAG) {
7894 SDLoc DL(Op);
7895 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7896 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7897 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7898 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7899 ArrayRef<int> Mask = SVOp->getMask();
7900 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7902 if (isSingleInputShuffleMask(Mask)) {
7903 // Straight shuffle of a single input vector. For everything from SSE2
7904 // onward this has a single fast instruction with no scary immediates.
7905 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7906 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7907 int WidenedMask[4] = {
7908 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7909 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7910 return DAG.getNode(
7911 ISD::BITCAST, DL, MVT::v2i64,
7912 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
7913 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
7914 }
7916 // Use dedicated unpack instructions for masks that match their pattern.
7917 if (isShuffleEquivalent(Mask, 0, 2))
7918 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
7919 if (isShuffleEquivalent(Mask, 1, 3))
7920 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
7922 // If we have a single input from V2 insert that into V1 if we can do so
7923 // cheaply.
7924 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1)
7925 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7926 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
7927 return Insertion;
7929 if (Subtarget->hasSSE41())
7930 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
7931 Subtarget, DAG))
7932 return Blend;
7934 // Try to use rotation instructions if available.
7935 if (Subtarget->hasSSSE3())
7936 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7937 DL, MVT::v2i64, V1, V2, Mask, DAG))
7938 return Rotate;
7940 // We implement this with SHUFPD which is pretty lame because it will likely
7941 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7942 // However, all the alternatives are still more cycles and newer chips don't
7943 // have this problem. It would be really nice if x86 had better shuffles here.
7944 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
7945 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
7946 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7947 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7948 }
7950 /// \brief Lower a vector shuffle using the SHUFPS instruction.
7951 ///
7952 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
7953 /// It makes no assumptions about whether this is the *best* lowering, it simply
7954 /// uses it.
7955 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
7956 ArrayRef<int> Mask, SDValue V1,
7957 SDValue V2, SelectionDAG &DAG) {
7958 SDValue LowV = V1, HighV = V2;
7959 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7961 int NumV2Elements =
7962 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7964 if (NumV2Elements == 1) {
7965 int V2Index =
7966 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7967 Mask.begin();
7969 // Compute the index adjacent to V2Index and in the same half by toggling
7970 // the low bit.
7971 int V2AdjIndex = V2Index ^ 1;
7973 if (Mask[V2AdjIndex] == -1) {
7974 // Handles all the cases where we have a single V2 element and an undef.
7975 // This will only ever happen in the high lanes because we commute the
7976 // vector otherwise.
7977 if (V2Index < 2)
7978 std::swap(LowV, HighV);
7979 NewMask[V2Index] -= 4;
7980 } else {
7981 // Handle the case where the V2 element ends up adjacent to a V1 element.
7982 // To make this work, blend them together as the first step.
7983 int V1Index = V2AdjIndex;
7984 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7985 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
7986 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7988 // Now proceed to reconstruct the final blend as we have the necessary
7989 // high or low half formed.
7990 if (V2Index < 2) {
7991 LowV = V2;
7992 HighV = V1;
7993 } else {
7994 HighV = V2;
7995 }
7996 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7997 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7998 }
7999 } else if (NumV2Elements == 2) {
8000 if (Mask[0] < 4 && Mask[1] < 4) {
8001 // Handle the easy case where we have V1 in the low lanes and V2 in the
8002 // high lanes.
8003 NewMask[2] -= 4;
8004 NewMask[3] -= 4;
8005 } else if (Mask[2] < 4 && Mask[3] < 4) {
8006 // We also handle the reversed case because this utility may get called
8007 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8008 // arrange things in the right direction.
8009 NewMask[0] -= 4;
8010 NewMask[1] -= 4;
8011 HighV = V1;
8012 LowV = V2;
8013 } else {
8014 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8015 // trying to place elements directly, just blend them and set up the final
8016 // shuffle to place them.
8018 // The first two blend mask elements are for V1, the second two are for
8019 // V2.
8020 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8021 Mask[2] < 4 ? Mask[2] : Mask[3],
8022 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8023 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8024 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8025 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8027 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8028 // a blend.
8029 LowV = HighV = V1;
8030 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8031 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8032 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8033 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8034 }
8035 }
8036 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8037 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8038 }
8040 /// \brief Lower 4-lane 32-bit floating point shuffles.
8041 ///
8042 /// Uses instructions exclusively from the floating point unit to minimize
8043 /// domain crossing penalties, as these are sufficient to implement all v4f32
8044 /// shuffles.
8045 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8046 const X86Subtarget *Subtarget,
8047 SelectionDAG &DAG) {
8048 SDLoc DL(Op);
8049 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8050 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8051 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8052 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8053 ArrayRef<int> Mask = SVOp->getMask();
8054 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8056 int NumV2Elements =
8057 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8059 if (NumV2Elements == 0) {
8060 if (Subtarget->hasAVX()) {
8061 // If we have AVX, we can use VPERMILPS which will allow folding a load
8062 // into the shuffle.
8063 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8064 getV4X86ShuffleImm8ForMask(Mask, DAG));
8065 }
8067 // Otherwise, use a straight shuffle of a single input vector. We pass the
8068 // input vector to both operands to simulate this with a SHUFPS.
8069 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8070 getV4X86ShuffleImm8ForMask(Mask, DAG));
8071 }
8073 // Use dedicated unpack instructions for masks that match their pattern.
8074 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8075 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8076 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8077 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8079 // There are special ways we can lower some single-element blends. However, we
8080 // have custom ways we can lower more complex single-element blends below that
8081 // we defer to if both this and BLENDPS fail to match, so restrict this to
8082 // when the V2 input is targeting element 0 of the mask -- that is the fast
8083 // case here.
8084 if (NumV2Elements == 1 && Mask[0] >= 4)
8085 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8086 Mask, Subtarget, DAG))
8087 return V;
8089 if (Subtarget->hasSSE41())
8090 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8091 Subtarget, DAG))
8092 return Blend;
8094 // Check for whether we can use INSERTPS to perform the blend. We only use
8095 // INSERTPS when the V1 elements are already in the correct locations
8096 // because otherwise we can just always use two SHUFPS instructions which
8097 // are much smaller to encode than a SHUFPS and an INSERTPS.
8098 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
8099 int V2Index =
8100 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8101 Mask.begin();
8103 // When using INSERTPS we can zero any lane of the destination. Collect
8104 // the zero inputs into a mask and drop them from the lanes of V1 which
8105 // actually need to be present as inputs to the INSERTPS.
8106 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8108 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
8109 bool InsertNeedsShuffle = false;
8110 unsigned ZMask = 0;
8111 for (int i = 0; i < 4; ++i)
8112 if (i != V2Index) {
8113 if (Zeroable[i]) {
8114 ZMask |= 1 << i;
8115 } else if (Mask[i] != i) {
8116 InsertNeedsShuffle = true;
8117 break;
8118 }
8119 }
8121 // We don't want to use INSERTPS or other insertion techniques if it will
8122 // require shuffling anyways.
8123 if (!InsertNeedsShuffle) {
8124 // If all of V1 is zeroable, replace it with undef.
8125 if ((ZMask | 1 << V2Index) == 0xF)
8126 V1 = DAG.getUNDEF(MVT::v4f32);
8128 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
8129 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8131 // Insert the V2 element into the desired position.
8132 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8133 DAG.getConstant(InsertPSMask, MVT::i8));
8134 }
8135 }
8137 // Otherwise fall back to a SHUFPS lowering strategy.
8138 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8139 }
8141 /// \brief Lower 4-lane i32 vector shuffles.
8142 ///
8143 /// We try to handle these with integer-domain shuffles where we can, but for
8144 /// blends we use the floating point domain blend instructions.
8145 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8146 const X86Subtarget *Subtarget,
8147 SelectionDAG &DAG) {
8148 SDLoc DL(Op);
8149 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8150 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8151 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8152 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8153 ArrayRef<int> Mask = SVOp->getMask();
8154 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8156 int NumV2Elements =
8157 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8159 if (NumV2Elements == 0) {
8160 // Straight shuffle of a single input vector. For everything from SSE2
8161 // onward this has a single fast instruction with no scary immediates.
8162 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8163 // but we aren't actually going to use the UNPCK instruction because doing
8164 // so prevents folding a load into this instruction or making a copy.
8165 const int UnpackLoMask[] = {0, 0, 1, 1};
8166 const int UnpackHiMask[] = {2, 2, 3, 3};
8167 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8168 Mask = UnpackLoMask;
8169 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8170 Mask = UnpackHiMask;
8172 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8173 getV4X86ShuffleImm8ForMask(Mask, DAG));
8174 }
8176 // Whenever we can lower this as a zext, that instruction is strictly faster
8177 // than any alternative.
8178 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8179 Mask, Subtarget, DAG))
8180 return ZExt;
8182 // Use dedicated unpack instructions for masks that match their pattern.
8183 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8184 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8185 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8186 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8188 // There are special ways we can lower some single-element blends.
8189 if (NumV2Elements == 1)
8190 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8191 Mask, Subtarget, DAG))
8192 return V;
8194 if (Subtarget->hasSSE41())
8195 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8196 Subtarget, DAG))
8197 return Blend;
8199 // Try to use rotation instructions if available.
8200 if (Subtarget->hasSSSE3())
8201 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8202 DL, MVT::v4i32, V1, V2, Mask, DAG))
8203 return Rotate;
8205 // We implement this with SHUFPS because it can blend from two vectors.
8206 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8207 // up the inputs, bypassing domain shift penalties that we would encur if we
8208 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8209 // relevant.
8210 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8211 DAG.getVectorShuffle(
8212 MVT::v4f32, DL,
8213 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8214 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8215 }
8217 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8218 /// shuffle lowering, and the most complex part.
8219 ///
8220 /// The lowering strategy is to try to form pairs of input lanes which are
8221 /// targeted at the same half of the final vector, and then use a dword shuffle
8222 /// to place them onto the right half, and finally unpack the paired lanes into
8223 /// their final position.
8224 ///
8225 /// The exact breakdown of how to form these dword pairs and align them on the
8226 /// correct sides is really tricky. See the comments within the function for
8227 /// more of the details.
8228 static SDValue lowerV8I16SingleInputVectorShuffle(
8229 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8230 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8231 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8232 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8233 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8235 SmallVector<int, 4> LoInputs;
8236 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8237 [](int M) { return M >= 0; });
8238 std::sort(LoInputs.begin(), LoInputs.end());
8239 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8240 SmallVector<int, 4> HiInputs;
8241 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8242 [](int M) { return M >= 0; });
8243 std::sort(HiInputs.begin(), HiInputs.end());
8244 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8245 int NumLToL =
8246 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8247 int NumHToL = LoInputs.size() - NumLToL;
8248 int NumLToH =
8249 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8250 int NumHToH = HiInputs.size() - NumLToH;
8251 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8252 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8253 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8254 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8256 // Use dedicated unpack instructions for masks that match their pattern.
8257 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8258 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8259 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8260 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8262 // Try to use rotation instructions if available.
8263 if (Subtarget->hasSSSE3())
8264 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8265 DL, MVT::v8i16, V, V, Mask, DAG))
8266 return Rotate;
8268 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8269 // such inputs we can swap two of the dwords across the half mark and end up
8270 // with <=2 inputs to each half in each half. Once there, we can fall through
8271 // to the generic code below. For example:
8272 //
8273 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8274 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8275 //
8276 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8277 // and an existing 2-into-2 on the other half. In this case we may have to
8278 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8279 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8280 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8281 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8282 // half than the one we target for fixing) will be fixed when we re-enter this
8283 // path. We will also combine away any sequence of PSHUFD instructions that
8284 // result into a single instruction. Here is an example of the tricky case:
8285 //
8286 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8287 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8288 //
8289 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8290 //
8291 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8292 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8293 //
8294 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8295 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8296 //
8297 // The result is fine to be handled by the generic logic.
8298 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8299 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8300 int AOffset, int BOffset) {
8301 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8302 "Must call this with A having 3 or 1 inputs from the A half.");
8303 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8304 "Must call this with B having 1 or 3 inputs from the B half.");
8305 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8306 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8308 // Compute the index of dword with only one word among the three inputs in
8309 // a half by taking the sum of the half with three inputs and subtracting
8310 // the sum of the actual three inputs. The difference is the remaining
8311 // slot.
8312 int ADWord, BDWord;
8313 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8314 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8315 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8316 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8317 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8318 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8319 int TripleNonInputIdx =
8320 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8321 TripleDWord = TripleNonInputIdx / 2;
8323 // We use xor with one to compute the adjacent DWord to whichever one the
8324 // OneInput is in.
8325 OneInputDWord = (OneInput / 2) ^ 1;
8327 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8328 // and BToA inputs. If there is also such a problem with the BToB and AToB
8329 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8330 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8331 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8332 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8333 // Compute how many inputs will be flipped by swapping these DWords. We
8334 // need
8335 // to balance this to ensure we don't form a 3-1 shuffle in the other
8336 // half.
8337 int NumFlippedAToBInputs =
8338 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8339 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8340 int NumFlippedBToBInputs =
8341 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8342 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8343 if ((NumFlippedAToBInputs == 1 &&
8344 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8345 (NumFlippedBToBInputs == 1 &&
8346 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8347 // We choose whether to fix the A half or B half based on whether that
8348 // half has zero flipped inputs. At zero, we may not be able to fix it
8349 // with that half. We also bias towards fixing the B half because that
8350 // will more commonly be the high half, and we have to bias one way.
8351 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8352 ArrayRef<int> Inputs) {
8353 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8354 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8355 PinnedIdx ^ 1) != Inputs.end();
8356 // Determine whether the free index is in the flipped dword or the
8357 // unflipped dword based on where the pinned index is. We use this bit
8358 // in an xor to conditionally select the adjacent dword.
8359 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8360 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8361 FixFreeIdx) != Inputs.end();
8362 if (IsFixIdxInput == IsFixFreeIdxInput)
8363 FixFreeIdx += 1;
8364 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8365 FixFreeIdx) != Inputs.end();
8366 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8367 "We need to be changing the number of flipped inputs!");
8368 int PSHUFHalfMask[] = {0, 1, 2, 3};
8369 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8370 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8371 MVT::v8i16, V,
8372 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8374 for (int &M : Mask)
8375 if (M != -1 && M == FixIdx)
8376 M = FixFreeIdx;
8377 else if (M != -1 && M == FixFreeIdx)
8378 M = FixIdx;
8379 };
8380 if (NumFlippedBToBInputs != 0) {
8381 int BPinnedIdx =
8382 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8383 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8384 } else {
8385 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8386 int APinnedIdx =
8387 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8388 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8389 }
8390 }
8391 }
8393 int PSHUFDMask[] = {0, 1, 2, 3};
8394 PSHUFDMask[ADWord] = BDWord;
8395 PSHUFDMask[BDWord] = ADWord;
8396 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8397 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8398 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8399 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8401 // Adjust the mask to match the new locations of A and B.
8402 for (int &M : Mask)
8403 if (M != -1 && M/2 == ADWord)
8404 M = 2 * BDWord + M % 2;
8405 else if (M != -1 && M/2 == BDWord)
8406 M = 2 * ADWord + M % 2;
8408 // Recurse back into this routine to re-compute state now that this isn't
8409 // a 3 and 1 problem.
8410 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8411 Mask);
8412 };
8413 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8414 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8415 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8416 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8418 // At this point there are at most two inputs to the low and high halves from
8419 // each half. That means the inputs can always be grouped into dwords and
8420 // those dwords can then be moved to the correct half with a dword shuffle.
8421 // We use at most one low and one high word shuffle to collect these paired
8422 // inputs into dwords, and finally a dword shuffle to place them.
8423 int PSHUFLMask[4] = {-1, -1, -1, -1};
8424 int PSHUFHMask[4] = {-1, -1, -1, -1};
8425 int PSHUFDMask[4] = {-1, -1, -1, -1};
8427 // First fix the masks for all the inputs that are staying in their
8428 // original halves. This will then dictate the targets of the cross-half
8429 // shuffles.
8430 auto fixInPlaceInputs =
8431 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8432 MutableArrayRef<int> SourceHalfMask,
8433 MutableArrayRef<int> HalfMask, int HalfOffset) {
8434 if (InPlaceInputs.empty())
8435 return;
8436 if (InPlaceInputs.size() == 1) {
8437 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8438 InPlaceInputs[0] - HalfOffset;
8439 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8440 return;
8441 }
8442 if (IncomingInputs.empty()) {
8443 // Just fix all of the in place inputs.
8444 for (int Input : InPlaceInputs) {
8445 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8446 PSHUFDMask[Input / 2] = Input / 2;
8447 }
8448 return;
8449 }
8451 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8452 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8453 InPlaceInputs[0] - HalfOffset;
8454 // Put the second input next to the first so that they are packed into
8455 // a dword. We find the adjacent index by toggling the low bit.
8456 int AdjIndex = InPlaceInputs[0] ^ 1;
8457 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8458 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8459 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8460 };
8461 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8462 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8464 // Now gather the cross-half inputs and place them into a free dword of
8465 // their target half.
8466 // FIXME: This operation could almost certainly be simplified dramatically to
8467 // look more like the 3-1 fixing operation.
8468 auto moveInputsToRightHalf = [&PSHUFDMask](
8469 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8470 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8471 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8472 int DestOffset) {
8473 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8474 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8475 };
8476 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8477 int Word) {
8478 int LowWord = Word & ~1;
8479 int HighWord = Word | 1;
8480 return isWordClobbered(SourceHalfMask, LowWord) ||
8481 isWordClobbered(SourceHalfMask, HighWord);
8482 };
8484 if (IncomingInputs.empty())
8485 return;
8487 if (ExistingInputs.empty()) {
8488 // Map any dwords with inputs from them into the right half.
8489 for (int Input : IncomingInputs) {
8490 // If the source half mask maps over the inputs, turn those into
8491 // swaps and use the swapped lane.
8492 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8493 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8494 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8495 Input - SourceOffset;
8496 // We have to swap the uses in our half mask in one sweep.
8497 for (int &M : HalfMask)
8498 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8499 M = Input;
8500 else if (M == Input)
8501 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8502 } else {
8503 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8504 Input - SourceOffset &&
8505 "Previous placement doesn't match!");
8506 }
8507 // Note that this correctly re-maps both when we do a swap and when
8508 // we observe the other side of the swap above. We rely on that to
8509 // avoid swapping the members of the input list directly.
8510 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8511 }
8513 // Map the input's dword into the correct half.
8514 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8515 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8516 else
8517 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8518 Input / 2 &&
8519 "Previous placement doesn't match!");
8520 }
8522 // And just directly shift any other-half mask elements to be same-half
8523 // as we will have mirrored the dword containing the element into the
8524 // same position within that half.
8525 for (int &M : HalfMask)
8526 if (M >= SourceOffset && M < SourceOffset + 4) {
8527 M = M - SourceOffset + DestOffset;
8528 assert(M >= 0 && "This should never wrap below zero!");
8529 }
8530 return;
8531 }
8533 // Ensure we have the input in a viable dword of its current half. This
8534 // is particularly tricky because the original position may be clobbered
8535 // by inputs being moved and *staying* in that half.
8536 if (IncomingInputs.size() == 1) {
8537 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8538 int InputFixed = std::find(std::begin(SourceHalfMask),
8539 std::end(SourceHalfMask), -1) -
8540 std::begin(SourceHalfMask) + SourceOffset;
8541 SourceHalfMask[InputFixed - SourceOffset] =
8542 IncomingInputs[0] - SourceOffset;
8543 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8544 InputFixed);
8545 IncomingInputs[0] = InputFixed;
8546 }
8547 } else if (IncomingInputs.size() == 2) {
8548 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8549 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8550 // We have two non-adjacent or clobbered inputs we need to extract from
8551 // the source half. To do this, we need to map them into some adjacent
8552 // dword slot in the source mask.
8553 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8554 IncomingInputs[1] - SourceOffset};
8556 // If there is a free slot in the source half mask adjacent to one of
8557 // the inputs, place the other input in it. We use (Index XOR 1) to
8558 // compute an adjacent index.
8559 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8560 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8561 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8562 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8563 InputsFixed[1] = InputsFixed[0] ^ 1;
8564 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8565 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8566 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8567 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8568 InputsFixed[0] = InputsFixed[1] ^ 1;
8569 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8570 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8571 // The two inputs are in the same DWord but it is clobbered and the
8572 // adjacent DWord isn't used at all. Move both inputs to the free
8573 // slot.
8574 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8575 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8576 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8577 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8578 } else {
8579 // The only way we hit this point is if there is no clobbering
8580 // (because there are no off-half inputs to this half) and there is no
8581 // free slot adjacent to one of the inputs. In this case, we have to
8582 // swap an input with a non-input.
8583 for (int i = 0; i < 4; ++i)
8584 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8585 "We can't handle any clobbers here!");
8586 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8587 "Cannot have adjacent inputs here!");
8589 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8590 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8592 // We also have to update the final source mask in this case because
8593 // it may need to undo the above swap.
8594 for (int &M : FinalSourceHalfMask)
8595 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8596 M = InputsFixed[1] + SourceOffset;
8597 else if (M == InputsFixed[1] + SourceOffset)
8598 M = (InputsFixed[0] ^ 1) + SourceOffset;
8600 InputsFixed[1] = InputsFixed[0] ^ 1;
8601 }
8603 // Point everything at the fixed inputs.
8604 for (int &M : HalfMask)
8605 if (M == IncomingInputs[0])
8606 M = InputsFixed[0] + SourceOffset;
8607 else if (M == IncomingInputs[1])
8608 M = InputsFixed[1] + SourceOffset;
8610 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8611 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8612 }
8613 } else {
8614 llvm_unreachable("Unhandled input size!");
8615 }
8617 // Now hoist the DWord down to the right half.
8618 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8619 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8620 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8621 for (int &M : HalfMask)
8622 for (int Input : IncomingInputs)
8623 if (M == Input)
8624 M = FreeDWord * 2 + Input % 2;
8625 };
8626 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8627 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8628 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8629 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8631 // Now enact all the shuffles we've computed to move the inputs into their
8632 // target half.
8633 if (!isNoopShuffleMask(PSHUFLMask))
8634 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8635 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8636 if (!isNoopShuffleMask(PSHUFHMask))
8637 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8638 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8639 if (!isNoopShuffleMask(PSHUFDMask))
8640 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8641 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8642 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8643 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8645 // At this point, each half should contain all its inputs, and we can then
8646 // just shuffle them into their final position.
8647 assert(std::count_if(LoMask.begin(), LoMask.end(),
8648 [](int M) { return M >= 4; }) == 0 &&
8649 "Failed to lift all the high half inputs to the low mask!");
8650 assert(std::count_if(HiMask.begin(), HiMask.end(),
8651 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8652 "Failed to lift all the low half inputs to the high mask!");
8654 // Do a half shuffle for the low mask.
8655 if (!isNoopShuffleMask(LoMask))
8656 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8657 getV4X86ShuffleImm8ForMask(LoMask, DAG));
8659 // Do a half shuffle with the high mask after shifting its values down.
8660 for (int &M : HiMask)
8661 if (M >= 0)
8662 M -= 4;
8663 if (!isNoopShuffleMask(HiMask))
8664 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8665 getV4X86ShuffleImm8ForMask(HiMask, DAG));
8667 return V;
8668 }
8670 /// \brief Detect whether the mask pattern should be lowered through
8671 /// interleaving.
8672 ///
8673 /// This essentially tests whether viewing the mask as an interleaving of two
8674 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
8675 /// lowering it through interleaving is a significantly better strategy.
8676 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
8677 int NumEvenInputs[2] = {0, 0};
8678 int NumOddInputs[2] = {0, 0};
8679 int NumLoInputs[2] = {0, 0};
8680 int NumHiInputs[2] = {0, 0};
8681 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
8682 if (Mask[i] < 0)
8683 continue;
8685 int InputIdx = Mask[i] >= Size;
8687 if (i < Size / 2)
8688 ++NumLoInputs[InputIdx];
8689 else
8690 ++NumHiInputs[InputIdx];
8692 if ((i % 2) == 0)
8693 ++NumEvenInputs[InputIdx];
8694 else
8695 ++NumOddInputs[InputIdx];
8696 }
8698 // The minimum number of cross-input results for both the interleaved and
8699 // split cases. If interleaving results in fewer cross-input results, return
8700 // true.
8701 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
8702 NumEvenInputs[0] + NumOddInputs[1]);
8703 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
8704 NumLoInputs[0] + NumHiInputs[1]);
8705 return InterleavedCrosses < SplitCrosses;
8706 }
8708 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
8709 ///
8710 /// This strategy only works when the inputs from each vector fit into a single
8711 /// half of that vector, and generally there are not so many inputs as to leave
8712 /// the in-place shuffles required highly constrained (and thus expensive). It
8713 /// shifts all the inputs into a single side of both input vectors and then
8714 /// uses an unpack to interleave these inputs in a single vector. At that
8715 /// point, we will fall back on the generic single input shuffle lowering.
8716 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
8717 SDValue V2,
8718 MutableArrayRef<int> Mask,
8719 const X86Subtarget *Subtarget,
8720 SelectionDAG &DAG) {
8721 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8722 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8723 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
8724 for (int i = 0; i < 8; ++i)
8725 if (Mask[i] >= 0 && Mask[i] < 4)
8726 LoV1Inputs.push_back(i);
8727 else if (Mask[i] >= 4 && Mask[i] < 8)
8728 HiV1Inputs.push_back(i);
8729 else if (Mask[i] >= 8 && Mask[i] < 12)
8730 LoV2Inputs.push_back(i);
8731 else if (Mask[i] >= 12)
8732 HiV2Inputs.push_back(i);
8734 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
8735 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
8736 (void)NumV1Inputs;
8737 (void)NumV2Inputs;
8738 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
8739 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
8740 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
8742 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
8743 HiV1Inputs.size() + HiV2Inputs.size();
8745 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
8746 ArrayRef<int> HiInputs, bool MoveToLo,
8747 int MaskOffset) {
8748 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
8749 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
8750 if (BadInputs.empty())
8751 return V;
8753 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8754 int MoveOffset = MoveToLo ? 0 : 4;
8756 if (GoodInputs.empty()) {
8757 for (int BadInput : BadInputs) {
8758 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
8759 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
8760 }
8761 } else {
8762 if (GoodInputs.size() == 2) {
8763 // If the low inputs are spread across two dwords, pack them into
8764 // a single dword.
8765 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
8766 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
8767 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
8768 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
8769 } else {
8770 // Otherwise pin the good inputs.
8771 for (int GoodInput : GoodInputs)
8772 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
8773 }
8775 if (BadInputs.size() == 2) {
8776 // If we have two bad inputs then there may be either one or two good
8777 // inputs fixed in place. Find a fixed input, and then find the *other*
8778 // two adjacent indices by using modular arithmetic.
8779 int GoodMaskIdx =
8780 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
8781 [](int M) { return M >= 0; }) -
8782 std::begin(MoveMask);
8783 int MoveMaskIdx =
8784 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
8785 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
8786 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
8787 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8788 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
8789 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8790 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
8791 } else {
8792 assert(BadInputs.size() == 1 && "All sizes handled");
8793 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
8794 std::end(MoveMask), -1) -
8795 std::begin(MoveMask);
8796 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8797 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8798 }
8799 }
8801 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8802 MoveMask);
8803 };
8804 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
8805 /*MaskOffset*/ 0);
8806 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
8807 /*MaskOffset*/ 8);
8809 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
8810 // cross-half traffic in the final shuffle.
8812 // Munge the mask to be a single-input mask after the unpack merges the
8813 // results.
8814 for (int &M : Mask)
8815 if (M != -1)
8816 M = 2 * (M % 4) + (M / 8);
8818 return DAG.getVectorShuffle(
8819 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
8820 DL, MVT::v8i16, V1, V2),
8821 DAG.getUNDEF(MVT::v8i16), Mask);
8822 }
8824 /// \brief Generic lowering of 8-lane i16 shuffles.
8825 ///
8826 /// This handles both single-input shuffles and combined shuffle/blends with
8827 /// two inputs. The single input shuffles are immediately delegated to
8828 /// a dedicated lowering routine.
8829 ///
8830 /// The blends are lowered in one of three fundamental ways. If there are few
8831 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8832 /// of the input is significantly cheaper when lowered as an interleaving of
8833 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8834 /// halves of the inputs separately (making them have relatively few inputs)
8835 /// and then concatenate them.
8836 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8837 const X86Subtarget *Subtarget,
8838 SelectionDAG &DAG) {
8839 SDLoc DL(Op);
8840 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8841 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8842 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8843 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8844 ArrayRef<int> OrigMask = SVOp->getMask();
8845 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8846 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8847 MutableArrayRef<int> Mask(MaskStorage);
8849 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8851 // Whenever we can lower this as a zext, that instruction is strictly faster
8852 // than any alternative.
8853 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8854 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
8855 return ZExt;
8857 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8858 auto isV2 = [](int M) { return M >= 8; };
8860 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
8861 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
8863 if (NumV2Inputs == 0)
8864 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
8866 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
8867 "to be V1-input shuffles.");
8869 // There are special ways we can lower some single-element blends.
8870 if (NumV2Inputs == 1)
8871 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
8872 Mask, Subtarget, DAG))
8873 return V;
8875 if (Subtarget->hasSSE41())
8876 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
8877 Subtarget, DAG))
8878 return Blend;
8880 // Try to use rotation instructions if available.
8881 if (Subtarget->hasSSSE3())
8882 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V2, Mask, DAG))
8883 return Rotate;
8885 if (NumV1Inputs + NumV2Inputs <= 4)
8886 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
8888 // Check whether an interleaving lowering is likely to be more efficient.
8889 // This isn't perfect but it is a strong heuristic that tends to work well on
8890 // the kinds of shuffles that show up in practice.
8891 //
8892 // FIXME: Handle 1x, 2x, and 4x interleaving.
8893 if (shouldLowerAsInterleaving(Mask)) {
8894 // FIXME: Figure out whether we should pack these into the low or high
8895 // halves.
8897 int EMask[8], OMask[8];
8898 for (int i = 0; i < 4; ++i) {
8899 EMask[i] = Mask[2*i];
8900 OMask[i] = Mask[2*i + 1];
8901 EMask[i + 4] = -1;
8902 OMask[i + 4] = -1;
8903 }
8905 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
8906 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
8908 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
8909 }
8911 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8912 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8914 for (int i = 0; i < 4; ++i) {
8915 LoBlendMask[i] = Mask[i];
8916 HiBlendMask[i] = Mask[i + 4];
8917 }
8919 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
8920 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
8921 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
8922 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
8924 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8925 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
8926 }
8928 /// \brief Check whether a compaction lowering can be done by dropping even
8929 /// elements and compute how many times even elements must be dropped.
8930 ///
8931 /// This handles shuffles which take every Nth element where N is a power of
8932 /// two. Example shuffle masks:
8933 ///
8934 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
8935 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
8936 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
8937 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
8938 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
8939 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
8940 ///
8941 /// Any of these lanes can of course be undef.
8942 ///
8943 /// This routine only supports N <= 3.
8944 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
8945 /// for larger N.
8946 ///
8947 /// \returns N above, or the number of times even elements must be dropped if
8948 /// there is such a number. Otherwise returns zero.
8949 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
8950 // Figure out whether we're looping over two inputs or just one.
8951 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8953 // The modulus for the shuffle vector entries is based on whether this is
8954 // a single input or not.
8955 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
8956 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
8957 "We should only be called with masks with a power-of-2 size!");
8959 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
8961 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
8962 // and 2^3 simultaneously. This is because we may have ambiguity with
8963 // partially undef inputs.
8964 bool ViableForN[3] = {true, true, true};
8966 for (int i = 0, e = Mask.size(); i < e; ++i) {
8967 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
8968 // want.
8969 if (Mask[i] == -1)
8970 continue;
8972 bool IsAnyViable = false;
8973 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8974 if (ViableForN[j]) {
8975 uint64_t N = j + 1;
8977 // The shuffle mask must be equal to (i * 2^N) % M.
8978 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
8979 IsAnyViable = true;
8980 else
8981 ViableForN[j] = false;
8982 }
8983 // Early exit if we exhaust the possible powers of two.
8984 if (!IsAnyViable)
8985 break;
8986 }
8988 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8989 if (ViableForN[j])
8990 return j + 1;
8992 // Return 0 as there is no viable power of two.
8993 return 0;
8994 }
8996 /// \brief Generic lowering of v16i8 shuffles.
8997 ///
8998 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
8999 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9000 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9001 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9002 /// back together.
9003 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9004 const X86Subtarget *Subtarget,
9005 SelectionDAG &DAG) {
9006 SDLoc DL(Op);
9007 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9008 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9009 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9010 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9011 ArrayRef<int> OrigMask = SVOp->getMask();
9012 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9014 // Try to use rotation instructions if available.
9015 if (Subtarget->hasSSSE3())
9016 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v16i8, V1, V2,
9017 OrigMask, DAG))
9018 return Rotate;
9020 // Try to use a zext lowering.
9021 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9022 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9023 return ZExt;
9025 int MaskStorage[16] = {
9026 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9027 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9028 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9029 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9030 MutableArrayRef<int> Mask(MaskStorage);
9031 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9032 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9034 int NumV2Elements =
9035 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9037 // For single-input shuffles, there are some nicer lowering tricks we can use.
9038 if (NumV2Elements == 0) {
9039 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9040 // Notably, this handles splat and partial-splat shuffles more efficiently.
9041 // However, it only makes sense if the pre-duplication shuffle simplifies
9042 // things significantly. Currently, this means we need to be able to
9043 // express the pre-duplication shuffle as an i16 shuffle.
9044 //
9045 // FIXME: We should check for other patterns which can be widened into an
9046 // i16 shuffle as well.
9047 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9048 for (int i = 0; i < 16; i += 2)
9049 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9050 return false;
9052 return true;
9053 };
9054 auto tryToWidenViaDuplication = [&]() -> SDValue {
9055 if (!canWidenViaDuplication(Mask))
9056 return SDValue();
9057 SmallVector<int, 4> LoInputs;
9058 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9059 [](int M) { return M >= 0 && M < 8; });
9060 std::sort(LoInputs.begin(), LoInputs.end());
9061 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9062 LoInputs.end());
9063 SmallVector<int, 4> HiInputs;
9064 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9065 [](int M) { return M >= 8; });
9066 std::sort(HiInputs.begin(), HiInputs.end());
9067 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9068 HiInputs.end());
9070 bool TargetLo = LoInputs.size() >= HiInputs.size();
9071 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9072 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9074 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9075 SmallDenseMap<int, int, 8> LaneMap;
9076 for (int I : InPlaceInputs) {
9077 PreDupI16Shuffle[I/2] = I/2;
9078 LaneMap[I] = I;
9079 }
9080 int j = TargetLo ? 0 : 4, je = j + 4;
9081 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9082 // Check if j is already a shuffle of this input. This happens when
9083 // there are two adjacent bytes after we move the low one.
9084 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9085 // If we haven't yet mapped the input, search for a slot into which
9086 // we can map it.
9087 while (j < je && PreDupI16Shuffle[j] != -1)
9088 ++j;
9090 if (j == je)
9091 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9092 return SDValue();
9094 // Map this input with the i16 shuffle.
9095 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9096 }
9098 // Update the lane map based on the mapping we ended up with.
9099 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9100 }
9101 V1 = DAG.getNode(
9102 ISD::BITCAST, DL, MVT::v16i8,
9103 DAG.getVectorShuffle(MVT::v8i16, DL,
9104 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9105 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9107 // Unpack the bytes to form the i16s that will be shuffled into place.
9108 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9109 MVT::v16i8, V1, V1);
9111 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9112 for (int i = 0; i < 16; ++i)
9113 if (Mask[i] != -1) {
9114 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9115 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9116 if (PostDupI16Shuffle[i / 2] == -1)
9117 PostDupI16Shuffle[i / 2] = MappedMask;
9118 else
9119 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9120 "Conflicting entrties in the original shuffle!");
9121 }
9122 return DAG.getNode(
9123 ISD::BITCAST, DL, MVT::v16i8,
9124 DAG.getVectorShuffle(MVT::v8i16, DL,
9125 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9126 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9127 };
9128 if (SDValue V = tryToWidenViaDuplication())
9129 return V;
9130 }
9132 // Check whether an interleaving lowering is likely to be more efficient.
9133 // This isn't perfect but it is a strong heuristic that tends to work well on
9134 // the kinds of shuffles that show up in practice.
9135 //
9136 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9137 if (shouldLowerAsInterleaving(Mask)) {
9138 // FIXME: Figure out whether we should pack these into the low or high
9139 // halves.
9141 int EMask[16], OMask[16];
9142 for (int i = 0; i < 8; ++i) {
9143 EMask[i] = Mask[2*i];
9144 OMask[i] = Mask[2*i + 1];
9145 EMask[i + 8] = -1;
9146 OMask[i + 8] = -1;
9147 }
9149 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9150 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9152 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, Evens, Odds);
9153 }
9155 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9156 // with PSHUFB. It is important to do this before we attempt to generate any
9157 // blends but after all of the single-input lowerings. If the single input
9158 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9159 // want to preserve that and we can DAG combine any longer sequences into
9160 // a PSHUFB in the end. But once we start blending from multiple inputs,
9161 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9162 // and there are *very* few patterns that would actually be faster than the
9163 // PSHUFB approach because of its ability to zero lanes.
9164 //
9165 // FIXME: The only exceptions to the above are blends which are exact
9166 // interleavings with direct instructions supporting them. We currently don't
9167 // handle those well here.
9168 if (Subtarget->hasSSSE3()) {
9169 SDValue V1Mask[16];
9170 SDValue V2Mask[16];
9171 for (int i = 0; i < 16; ++i)
9172 if (Mask[i] == -1) {
9173 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9174 } else {
9175 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9176 V2Mask[i] =
9177 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9178 }
9179 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9180 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9181 if (isSingleInputShuffleMask(Mask))
9182 return V1; // Single inputs are easy.
9184 // Otherwise, blend the two.
9185 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9186 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9187 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9188 }
9190 // There are special ways we can lower some single-element blends.
9191 if (NumV2Elements == 1)
9192 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9193 Mask, Subtarget, DAG))
9194 return V;
9196 // Check whether a compaction lowering can be done. This handles shuffles
9197 // which take every Nth element for some even N. See the helper function for
9198 // details.
9199 //
9200 // We special case these as they can be particularly efficiently handled with
9201 // the PACKUSB instruction on x86 and they show up in common patterns of
9202 // rearranging bytes to truncate wide elements.
9203 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9204 // NumEvenDrops is the power of two stride of the elements. Another way of
9205 // thinking about it is that we need to drop the even elements this many
9206 // times to get the original input.
9207 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9209 // First we need to zero all the dropped bytes.
9210 assert(NumEvenDrops <= 3 &&
9211 "No support for dropping even elements more than 3 times.");
9212 // We use the mask type to pick which bytes are preserved based on how many
9213 // elements are dropped.
9214 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9215 SDValue ByteClearMask =
9216 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9217 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9218 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9219 if (!IsSingleInput)
9220 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9222 // Now pack things back together.
9223 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9224 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9225 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9226 for (int i = 1; i < NumEvenDrops; ++i) {
9227 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9228 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9229 }
9231 return Result;
9232 }
9234 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9235 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9236 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9237 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9239 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9240 MutableArrayRef<int> V1HalfBlendMask,
9241 MutableArrayRef<int> V2HalfBlendMask) {
9242 for (int i = 0; i < 8; ++i)
9243 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9244 V1HalfBlendMask[i] = HalfMask[i];
9245 HalfMask[i] = i;
9246 } else if (HalfMask[i] >= 16) {
9247 V2HalfBlendMask[i] = HalfMask[i] - 16;
9248 HalfMask[i] = i + 8;
9249 }
9250 };
9251 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9252 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9254 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9256 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9257 MutableArrayRef<int> HiBlendMask) {
9258 SDValue V1, V2;
9259 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9260 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9261 // i16s.
9262 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9263 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9264 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9265 [](int M) { return M >= 0 && M % 2 == 1; })) {
9266 // Use a mask to drop the high bytes.
9267 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9268 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9269 DAG.getConstant(0x00FF, MVT::v8i16));
9271 // This will be a single vector shuffle instead of a blend so nuke V2.
9272 V2 = DAG.getUNDEF(MVT::v8i16);
9274 // Squash the masks to point directly into V1.
9275 for (int &M : LoBlendMask)
9276 if (M >= 0)
9277 M /= 2;
9278 for (int &M : HiBlendMask)
9279 if (M >= 0)
9280 M /= 2;
9281 } else {
9282 // Otherwise just unpack the low half of V into V1 and the high half into
9283 // V2 so that we can blend them as i16s.
9284 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9285 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9286 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9287 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9288 }
9290 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9291 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9292 return std::make_pair(BlendedLo, BlendedHi);
9293 };
9294 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9295 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9296 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9298 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9299 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9301 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9302 }
9304 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9305 ///
9306 /// This routine breaks down the specific type of 128-bit shuffle and
9307 /// dispatches to the lowering routines accordingly.
9308 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9309 MVT VT, const X86Subtarget *Subtarget,
9310 SelectionDAG &DAG) {
9311 switch (VT.SimpleTy) {
9312 case MVT::v2i64:
9313 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9314 case MVT::v2f64:
9315 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9316 case MVT::v4i32:
9317 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9318 case MVT::v4f32:
9319 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9320 case MVT::v8i16:
9321 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9322 case MVT::v16i8:
9323 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9325 default:
9326 llvm_unreachable("Unimplemented!");
9327 }
9328 }
9330 /// \brief Generic routine to split ector shuffle into half-sized shuffles.
9331 ///
9332 /// This routine just extracts two subvectors, shuffles them independently, and
9333 /// then concatenates them back together. This should work effectively with all
9334 /// AVX vector shuffle types.
9335 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9336 SDValue V2, ArrayRef<int> Mask,
9337 SelectionDAG &DAG) {
9338 assert(VT.getSizeInBits() >= 256 &&
9339 "Only for 256-bit or wider vector shuffles!");
9340 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9341 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9343 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9344 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9346 int NumElements = VT.getVectorNumElements();
9347 int SplitNumElements = NumElements / 2;
9348 MVT ScalarVT = VT.getScalarType();
9349 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9351 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9352 DAG.getIntPtrConstant(0));
9353 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9354 DAG.getIntPtrConstant(SplitNumElements));
9355 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9356 DAG.getIntPtrConstant(0));
9357 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9358 DAG.getIntPtrConstant(SplitNumElements));
9360 // Now create two 4-way blends of these half-width vectors.
9361 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9362 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9363 for (int i = 0; i < SplitNumElements; ++i) {
9364 int M = HalfMask[i];
9365 if (M >= NumElements) {
9366 V2BlendMask.push_back(M - NumElements);
9367 V1BlendMask.push_back(-1);
9368 BlendMask.push_back(SplitNumElements + i);
9369 } else if (M >= 0) {
9370 V2BlendMask.push_back(-1);
9371 V1BlendMask.push_back(M);
9372 BlendMask.push_back(i);
9373 } else {
9374 V2BlendMask.push_back(-1);
9375 V1BlendMask.push_back(-1);
9376 BlendMask.push_back(-1);
9377 }
9378 }
9379 SDValue V1Blend =
9380 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9381 SDValue V2Blend =
9382 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9383 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9384 };
9385 SDValue Lo = HalfBlend(LoMask);
9386 SDValue Hi = HalfBlend(HiMask);
9387 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9388 }
9390 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9391 /// a permutation and blend of those lanes.
9392 ///
9393 /// This essentially blends the out-of-lane inputs to each lane into the lane
9394 /// from a permuted copy of the vector. This lowering strategy results in four
9395 /// instructions in the worst case for a single-input cross lane shuffle which
9396 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9397 /// of. Special cases for each particular shuffle pattern should be handled
9398 /// prior to trying this lowering.
9399 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9400 SDValue V1, SDValue V2,
9401 ArrayRef<int> Mask,
9402 SelectionDAG &DAG) {
9403 // FIXME: This should probably be generalized for 512-bit vectors as well.
9404 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9405 int LaneSize = Mask.size() / 2;
9407 // If there are only inputs from one 128-bit lane, splitting will in fact be
9408 // less expensive. The flags track wether the given lane contains an element
9409 // that crosses to another lane.
9410 bool LaneCrossing[2] = {false, false};
9411 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9412 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9413 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9414 if (!LaneCrossing[0] || !LaneCrossing[1])
9415 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9417 if (isSingleInputShuffleMask(Mask)) {
9418 SmallVector<int, 32> FlippedBlendMask;
9419 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9420 FlippedBlendMask.push_back(
9421 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9422 ? Mask[i]
9423 : Mask[i] % LaneSize +
9424 (i / LaneSize) * LaneSize + Size));
9426 // Flip the vector, and blend the results which should now be in-lane. The
9427 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9428 // 5 for the high source. The value 3 selects the high half of source 2 and
9429 // the value 2 selects the low half of source 2. We only use source 2 to
9430 // allow folding it into a memory operand.
9431 unsigned PERMMask = 3 | 2 << 4;
9432 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9433 V1, DAG.getConstant(PERMMask, MVT::i8));
9434 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9435 }
9437 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9438 // will be handled by the above logic and a blend of the results, much like
9439 // other patterns in AVX.
9440 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9441 }
9443 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9444 ///
9445 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9446 /// isn't available.
9447 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9448 const X86Subtarget *Subtarget,
9449 SelectionDAG &DAG) {
9450 SDLoc DL(Op);
9451 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9452 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9453 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9454 ArrayRef<int> Mask = SVOp->getMask();
9455 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9457 if (isSingleInputShuffleMask(Mask)) {
9458 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
9459 // Non-half-crossing single input shuffles can be lowerid with an
9460 // interleaved permutation.
9461 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9462 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9463 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9464 DAG.getConstant(VPERMILPMask, MVT::i8));
9465 }
9467 // With AVX2 we have direct support for this permutation.
9468 if (Subtarget->hasAVX2())
9469 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
9470 getV4X86ShuffleImm8ForMask(Mask, DAG));
9472 // Otherwise, fall back.
9473 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
9474 DAG);
9475 }
9477 // X86 has dedicated unpack instructions that can handle specific blend
9478 // operations: UNPCKH and UNPCKL.
9479 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9480 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9481 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9482 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9484 // If we have a single input to the zero element, insert that into V1 if we
9485 // can do so cheaply.
9486 int NumV2Elements =
9487 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
9488 if (NumV2Elements == 1 && Mask[0] >= 4)
9489 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
9490 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
9491 return Insertion;
9493 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
9494 Subtarget, DAG))
9495 return Blend;
9497 // Check if the blend happens to exactly fit that of SHUFPD.
9498 if ((Mask[0] == -1 || Mask[0] < 2) &&
9499 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
9500 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
9501 (Mask[3] == -1 || Mask[3] >= 6)) {
9502 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
9503 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
9504 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
9505 DAG.getConstant(SHUFPDMask, MVT::i8));
9506 }
9507 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
9508 (Mask[1] == -1 || Mask[1] < 2) &&
9509 (Mask[2] == -1 || Mask[2] >= 6) &&
9510 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
9511 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
9512 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
9513 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
9514 DAG.getConstant(SHUFPDMask, MVT::i8));
9515 }
9517 // Otherwise fall back on generic blend lowering.
9518 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
9519 Mask, DAG);
9520 }
9522 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9523 ///
9524 /// This routine is only called when we have AVX2 and thus a reasonable
9525 /// instruction set for v4i64 shuffling..
9526 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9527 const X86Subtarget *Subtarget,
9528 SelectionDAG &DAG) {
9529 SDLoc DL(Op);
9530 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9531 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9532 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9533 ArrayRef<int> Mask = SVOp->getMask();
9534 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9535 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9537 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
9538 Subtarget, DAG))
9539 return Blend;
9541 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
9542 // use lower latency instructions that will operate on both 128-bit lanes.
9543 SmallVector<int, 2> RepeatedMask;
9544 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
9545 if (isSingleInputShuffleMask(Mask)) {
9546 int PSHUFDMask[] = {-1, -1, -1, -1};
9547 for (int i = 0; i < 2; ++i)
9548 if (RepeatedMask[i] >= 0) {
9549 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
9550 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
9551 }
9552 return DAG.getNode(
9553 ISD::BITCAST, DL, MVT::v4i64,
9554 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
9555 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
9556 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
9557 }
9559 // Use dedicated unpack instructions for masks that match their pattern.
9560 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9561 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
9562 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9563 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
9564 }
9566 // AVX2 provides a direct instruction for permuting a single input across
9567 // lanes.
9568 if (isSingleInputShuffleMask(Mask))
9569 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
9570 getV4X86ShuffleImm8ForMask(Mask, DAG));
9572 // Otherwise fall back on generic blend lowering.
9573 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
9574 Mask, DAG);
9575 }
9577 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9578 ///
9579 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9580 /// isn't available.
9581 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9582 const X86Subtarget *Subtarget,
9583 SelectionDAG &DAG) {
9584 SDLoc DL(Op);
9585 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9586 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9587 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9588 ArrayRef<int> Mask = SVOp->getMask();
9589 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9591 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
9592 Subtarget, DAG))
9593 return Blend;
9595 // If the shuffle mask is repeated in each 128-bit lane, we have many more
9596 // options to efficiently lower the shuffle.
9597 SmallVector<int, 4> RepeatedMask;
9598 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
9599 assert(RepeatedMask.size() == 4 &&
9600 "Repeated masks must be half the mask width!");
9601 if (isSingleInputShuffleMask(Mask))
9602 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
9603 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
9605 // Use dedicated unpack instructions for masks that match their pattern.
9606 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
9607 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
9608 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
9609 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
9611 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
9612 // have already handled any direct blends. We also need to squash the
9613 // repeated mask into a simulated v4f32 mask.
9614 for (int i = 0; i < 4; ++i)
9615 if (RepeatedMask[i] >= 8)
9616 RepeatedMask[i] -= 4;
9617 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
9618 }
9620 // If we have a single input shuffle with different shuffle patterns in the
9621 // two 128-bit lanes use the variable mask to VPERMILPS.
9622 if (isSingleInputShuffleMask(Mask)) {
9623 SDValue VPermMask[8];
9624 for (int i = 0; i < 8; ++i)
9625 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9626 : DAG.getConstant(Mask[i], MVT::i32);
9627 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
9628 return DAG.getNode(
9629 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
9630 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
9632 if (Subtarget->hasAVX2())
9633 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
9634 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
9635 DAG.getNode(ISD::BUILD_VECTOR, DL,
9636 MVT::v8i32, VPermMask)),
9637 V1);
9639 // Otherwise, fall back.
9640 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
9641 DAG);
9642 }
9644 // Otherwise fall back on generic blend lowering.
9645 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
9646 Mask, DAG);
9647 }
9649 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
9650 ///
9651 /// This routine is only called when we have AVX2 and thus a reasonable
9652 /// instruction set for v8i32 shuffling..
9653 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9654 const X86Subtarget *Subtarget,
9655 SelectionDAG &DAG) {
9656 SDLoc DL(Op);
9657 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9658 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9659 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9660 ArrayRef<int> Mask = SVOp->getMask();
9661 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9662 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
9664 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
9665 Subtarget, DAG))
9666 return Blend;
9668 // If the shuffle mask is repeated in each 128-bit lane we can use more
9669 // efficient instructions that mirror the shuffles across the two 128-bit
9670 // lanes.
9671 SmallVector<int, 4> RepeatedMask;
9672 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
9673 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
9674 if (isSingleInputShuffleMask(Mask))
9675 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
9676 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
9678 // Use dedicated unpack instructions for masks that match their pattern.
9679 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
9680 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
9681 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
9682 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
9683 }
9685 // If the shuffle patterns aren't repeated but it is a single input, directly
9686 // generate a cross-lane VPERMD instruction.
9687 if (isSingleInputShuffleMask(Mask)) {
9688 SDValue VPermMask[8];
9689 for (int i = 0; i < 8; ++i)
9690 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9691 : DAG.getConstant(Mask[i], MVT::i32);
9692 return DAG.getNode(
9693 X86ISD::VPERMV, DL, MVT::v8i32,
9694 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
9695 }
9697 // Otherwise fall back on generic blend lowering.
9698 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
9699 Mask, DAG);
9700 }
9702 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
9703 ///
9704 /// This routine is only called when we have AVX2 and thus a reasonable
9705 /// instruction set for v16i16 shuffling..
9706 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9707 const X86Subtarget *Subtarget,
9708 SelectionDAG &DAG) {
9709 SDLoc DL(Op);
9710 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9711 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9712 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9713 ArrayRef<int> Mask = SVOp->getMask();
9714 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9715 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
9717 // There are no generalized cross-lane shuffle operations available on i16
9718 // element types.
9719 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
9720 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
9721 Mask, DAG);
9723 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
9724 Subtarget, DAG))
9725 return Blend;
9727 // Use dedicated unpack instructions for masks that match their pattern.
9728 if (isShuffleEquivalent(Mask,
9729 // First 128-bit lane:
9730 0, 16, 1, 17, 2, 18, 3, 19,
9731 // Second 128-bit lane:
9732 8, 24, 9, 25, 10, 26, 11, 27))
9733 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
9734 if (isShuffleEquivalent(Mask,
9735 // First 128-bit lane:
9736 4, 20, 5, 21, 6, 22, 7, 23,
9737 // Second 128-bit lane:
9738 12, 28, 13, 29, 14, 30, 15, 31))
9739 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
9741 if (isSingleInputShuffleMask(Mask)) {
9742 SDValue PSHUFBMask[32];
9743 for (int i = 0; i < 16; ++i) {
9744 if (Mask[i] == -1) {
9745 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
9746 continue;
9747 }
9749 int M = i < 8 ? Mask[i] : Mask[i] - 8;
9750 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
9751 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
9752 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
9753 }
9754 return DAG.getNode(
9755 ISD::BITCAST, DL, MVT::v16i16,
9756 DAG.getNode(
9757 X86ISD::PSHUFB, DL, MVT::v32i8,
9758 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
9759 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
9760 }
9762 // Otherwise fall back on generic blend lowering.
9763 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i16, V1, V2,
9764 Mask, DAG);
9765 }
9767 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
9768 ///
9769 /// This routine is only called when we have AVX2 and thus a reasonable
9770 /// instruction set for v32i8 shuffling..
9771 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9772 const X86Subtarget *Subtarget,
9773 SelectionDAG &DAG) {
9774 SDLoc DL(Op);
9775 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9776 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9777 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9778 ArrayRef<int> Mask = SVOp->getMask();
9779 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
9780 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
9782 // There are no generalized cross-lane shuffle operations available on i8
9783 // element types.
9784 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
9785 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
9786 Mask, DAG);
9788 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
9789 Subtarget, DAG))
9790 return Blend;
9792 // Use dedicated unpack instructions for masks that match their pattern.
9793 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
9794 // 256-bit lanes.
9795 if (isShuffleEquivalent(
9796 Mask,
9797 // First 128-bit lane:
9798 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
9799 // Second 128-bit lane:
9800 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
9801 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
9802 if (isShuffleEquivalent(
9803 Mask,
9804 // First 128-bit lane:
9805 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
9806 // Second 128-bit lane:
9807 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
9808 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
9810 if (isSingleInputShuffleMask(Mask)) {
9811 SDValue PSHUFBMask[32];
9812 for (int i = 0; i < 32; ++i)
9813 PSHUFBMask[i] =
9814 Mask[i] < 0
9815 ? DAG.getUNDEF(MVT::i8)
9816 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
9818 return DAG.getNode(
9819 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
9820 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
9821 }
9823 // Otherwise fall back on generic blend lowering.
9824 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v32i8, V1, V2,
9825 Mask, DAG);
9826 }
9828 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
9829 ///
9830 /// This routine either breaks down the specific type of a 256-bit x86 vector
9831 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
9832 /// together based on the available instructions.
9833 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9834 MVT VT, const X86Subtarget *Subtarget,
9835 SelectionDAG &DAG) {
9836 SDLoc DL(Op);
9837 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9838 ArrayRef<int> Mask = SVOp->getMask();
9840 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
9841 // check for those subtargets here and avoid much of the subtarget querying in
9842 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
9843 // ability to manipulate a 256-bit vector with integer types. Since we'll use
9844 // floating point types there eventually, just immediately cast everything to
9845 // a float and operate entirely in that domain.
9846 if (VT.isInteger() && !Subtarget->hasAVX2()) {
9847 int ElementBits = VT.getScalarSizeInBits();
9848 if (ElementBits < 32)
9849 // No floating point type available, decompose into 128-bit vectors.
9850 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9852 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
9853 VT.getVectorNumElements());
9854 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
9855 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
9856 return DAG.getNode(ISD::BITCAST, DL, VT,
9857 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
9858 }
9860 switch (VT.SimpleTy) {
9861 case MVT::v4f64:
9862 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9863 case MVT::v4i64:
9864 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9865 case MVT::v8f32:
9866 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9867 case MVT::v8i32:
9868 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9869 case MVT::v16i16:
9870 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9871 case MVT::v32i8:
9872 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9874 default:
9875 llvm_unreachable("Not a valid 256-bit x86 vector type!");
9876 }
9877 }
9879 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
9880 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9881 const X86Subtarget *Subtarget,
9882 SelectionDAG &DAG) {
9883 SDLoc DL(Op);
9884 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
9885 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
9886 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9887 ArrayRef<int> Mask = SVOp->getMask();
9888 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9890 // FIXME: Implement direct support for this type!
9891 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
9892 }
9894 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
9895 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9896 const X86Subtarget *Subtarget,
9897 SelectionDAG &DAG) {
9898 SDLoc DL(Op);
9899 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
9900 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
9901 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9902 ArrayRef<int> Mask = SVOp->getMask();
9903 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9905 // FIXME: Implement direct support for this type!
9906 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
9907 }
9909 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
9910 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9911 const X86Subtarget *Subtarget,
9912 SelectionDAG &DAG) {
9913 SDLoc DL(Op);
9914 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
9915 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
9916 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9917 ArrayRef<int> Mask = SVOp->getMask();
9918 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9919 assert(Subtarget->hasDQI() && "We can only lower v8i64 with AVX-512-DQI");
9921 // FIXME: Implement direct support for this type!
9922 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
9923 }
9925 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
9926 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9927 const X86Subtarget *Subtarget,
9928 SelectionDAG &DAG) {
9929 SDLoc DL(Op);
9930 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
9931 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
9932 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9933 ArrayRef<int> Mask = SVOp->getMask();
9934 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9935 assert(Subtarget->hasDQI() && "We can only lower v16i32 with AVX-512-DQI!");
9937 // FIXME: Implement direct support for this type!
9938 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
9939 }
9941 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
9942 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9943 const X86Subtarget *Subtarget,
9944 SelectionDAG &DAG) {
9945 SDLoc DL(Op);
9946 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
9947 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
9948 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9949 ArrayRef<int> Mask = SVOp->getMask();
9950 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
9951 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
9953 // FIXME: Implement direct support for this type!
9954 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
9955 }
9957 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
9958 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9959 const X86Subtarget *Subtarget,
9960 SelectionDAG &DAG) {
9961 SDLoc DL(Op);
9962 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
9963 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
9964 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9965 ArrayRef<int> Mask = SVOp->getMask();
9966 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
9967 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
9969 // FIXME: Implement direct support for this type!
9970 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
9971 }
9973 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
9974 ///
9975 /// This routine either breaks down the specific type of a 512-bit x86 vector
9976 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
9977 /// together based on the available instructions.
9978 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9979 MVT VT, const X86Subtarget *Subtarget,
9980 SelectionDAG &DAG) {
9981 SDLoc DL(Op);
9982 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9983 ArrayRef<int> Mask = SVOp->getMask();
9984 assert(Subtarget->hasAVX512() &&
9985 "Cannot lower 512-bit vectors w/ basic ISA!");
9987 // Dispatch to each element type for lowering. If we don't have supprot for
9988 // specific element type shuffles at 512 bits, immediately split them and
9989 // lower them. Each lowering routine of a given type is allowed to assume that
9990 // the requisite ISA extensions for that element type are available.
9991 switch (VT.SimpleTy) {
9992 case MVT::v8f64:
9993 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9994 case MVT::v16f32:
9995 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9996 case MVT::v8i64:
9997 if (Subtarget->hasDQI())
9998 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9999 break;
10000 case MVT::v16i32:
10001 if (Subtarget->hasDQI())
10002 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10003 break;
10004 case MVT::v32i16:
10005 if (Subtarget->hasBWI())
10006 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10007 break;
10008 case MVT::v64i8:
10009 if (Subtarget->hasBWI())
10010 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10011 break;
10013 default:
10014 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10015 }
10017 // Otherwise fall back on splitting.
10018 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10019 }
10021 /// \brief Helper function to test whether a shuffle mask could be
10022 /// simplified by widening the elements being shuffled.
10023 ///
10024 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
10025 /// leaves it in an unspecified state.
10026 ///
10027 /// NOTE: This must handle normal vector shuffle masks and *target* vector
10028 /// shuffle masks. The latter have the special property of a '-2' representing
10029 /// a zero-ed lane of a vector.
10030 static bool canWidenShuffleElements(ArrayRef<int> Mask,
10031 SmallVectorImpl<int> &WidenedMask) {
10032 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
10033 // If both elements are undef, its trivial.
10034 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
10035 WidenedMask.push_back(SM_SentinelUndef);
10036 continue;
10037 }
10039 // Check for an undef mask and a mask value properly aligned to fit with
10040 // a pair of values. If we find such a case, use the non-undef mask's value.
10041 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
10042 WidenedMask.push_back(Mask[i + 1] / 2);
10043 continue;
10044 }
10045 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
10046 WidenedMask.push_back(Mask[i] / 2);
10047 continue;
10048 }
10050 // When zeroing, we need to spread the zeroing across both lanes to widen.
10051 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
10052 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
10053 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
10054 WidenedMask.push_back(SM_SentinelZero);
10055 continue;
10056 }
10057 return false;
10058 }
10060 // Finally check if the two mask values are adjacent and aligned with
10061 // a pair.
10062 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
10063 WidenedMask.push_back(Mask[i] / 2);
10064 continue;
10065 }
10067 // Otherwise we can't safely widen the elements used in this shuffle.
10068 return false;
10069 }
10070 assert(WidenedMask.size() == Mask.size() / 2 &&
10071 "Incorrect size of mask after widening the elements!");
10073 return true;
10074 }
10076 /// \brief Top-level lowering for x86 vector shuffles.
10077 ///
10078 /// This handles decomposition, canonicalization, and lowering of all x86
10079 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10080 /// above in helper routines. The canonicalization attempts to widen shuffles
10081 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10082 /// s.t. only one of the two inputs needs to be tested, etc.
10083 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10084 SelectionDAG &DAG) {
10085 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10086 ArrayRef<int> Mask = SVOp->getMask();
10087 SDValue V1 = Op.getOperand(0);
10088 SDValue V2 = Op.getOperand(1);
10089 MVT VT = Op.getSimpleValueType();
10090 int NumElements = VT.getVectorNumElements();
10091 SDLoc dl(Op);
10093 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10095 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10096 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10097 if (V1IsUndef && V2IsUndef)
10098 return DAG.getUNDEF(VT);
10100 // When we create a shuffle node we put the UNDEF node to second operand,
10101 // but in some cases the first operand may be transformed to UNDEF.
10102 // In this case we should just commute the node.
10103 if (V1IsUndef)
10104 return DAG.getCommutedVectorShuffle(*SVOp);
10106 // Check for non-undef masks pointing at an undef vector and make the masks
10107 // undef as well. This makes it easier to match the shuffle based solely on
10108 // the mask.
10109 if (V2IsUndef)
10110 for (int M : Mask)
10111 if (M >= NumElements) {
10112 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10113 for (int &M : NewMask)
10114 if (M >= NumElements)
10115 M = -1;
10116 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10117 }
10119 // For integer vector shuffles, try to collapse them into a shuffle of fewer
10120 // lanes but wider integers. We cap this to not form integers larger than i64
10121 // but it might be interesting to form i128 integers to handle flipping the
10122 // low and high halves of AVX 256-bit vectors.
10123 SmallVector<int, 16> WidenedMask;
10124 if (VT.isInteger() && VT.getScalarSizeInBits() < 64 &&
10125 canWidenShuffleElements(Mask, WidenedMask)) {
10126 MVT NewVT =
10127 MVT::getVectorVT(MVT::getIntegerVT(VT.getScalarSizeInBits() * 2),
10128 VT.getVectorNumElements() / 2);
10129 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10130 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10131 return DAG.getNode(ISD::BITCAST, dl, VT,
10132 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10133 }
10135 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10136 for (int M : SVOp->getMask())
10137 if (M < 0)
10138 ++NumUndefElements;
10139 else if (M < NumElements)
10140 ++NumV1Elements;
10141 else
10142 ++NumV2Elements;
10144 // Commute the shuffle as needed such that more elements come from V1 than
10145 // V2. This allows us to match the shuffle pattern strictly on how many
10146 // elements come from V1 without handling the symmetric cases.
10147 if (NumV2Elements > NumV1Elements)
10148 return DAG.getCommutedVectorShuffle(*SVOp);
10150 // When the number of V1 and V2 elements are the same, try to minimize the
10151 // number of uses of V2 in the low half of the vector. When that is tied,
10152 // ensure that the sum of indices for V1 is equal to or lower than the sum
10153 // indices for V2.
10154 if (NumV1Elements == NumV2Elements) {
10155 int LowV1Elements = 0, LowV2Elements = 0;
10156 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10157 if (M >= NumElements)
10158 ++LowV2Elements;
10159 else if (M >= 0)
10160 ++LowV1Elements;
10161 if (LowV2Elements > LowV1Elements) {
10162 return DAG.getCommutedVectorShuffle(*SVOp);
10163 } else if (LowV2Elements == LowV1Elements) {
10164 int SumV1Indices = 0, SumV2Indices = 0;
10165 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10166 if (SVOp->getMask()[i] >= NumElements)
10167 SumV2Indices += i;
10168 else if (SVOp->getMask()[i] >= 0)
10169 SumV1Indices += i;
10170 if (SumV2Indices < SumV1Indices)
10171 return DAG.getCommutedVectorShuffle(*SVOp);
10172 }
10173 }
10175 // For each vector width, delegate to a specialized lowering routine.
10176 if (VT.getSizeInBits() == 128)
10177 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10179 if (VT.getSizeInBits() == 256)
10180 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10182 // Force AVX-512 vectors to be scalarized for now.
10183 // FIXME: Implement AVX-512 support!
10184 if (VT.getSizeInBits() == 512)
10185 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10187 llvm_unreachable("Unimplemented!");
10188 }
10191 //===----------------------------------------------------------------------===//
10192 // Legacy vector shuffle lowering
10193 //
10194 // This code is the legacy code handling vector shuffles until the above
10195 // replaces its functionality and performance.
10196 //===----------------------------------------------------------------------===//
10198 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
10199 bool hasInt256, unsigned *MaskOut = nullptr) {
10200 MVT EltVT = VT.getVectorElementType();
10202 // There is no blend with immediate in AVX-512.
10203 if (VT.is512BitVector())
10204 return false;
10206 if (!hasSSE41 || EltVT == MVT::i8)
10207 return false;
10208 if (!hasInt256 && VT == MVT::v16i16)
10209 return false;
10211 unsigned MaskValue = 0;
10212 unsigned NumElems = VT.getVectorNumElements();
10213 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10214 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10215 unsigned NumElemsInLane = NumElems / NumLanes;
10217 // Blend for v16i16 should be symetric for the both lanes.
10218 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10220 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
10221 int EltIdx = MaskVals[i];
10223 if ((EltIdx < 0 || EltIdx == (int)i) &&
10224 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
10225 continue;
10227 if (((unsigned)EltIdx == (i + NumElems)) &&
10228 (SndLaneEltIdx < 0 ||
10229 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
10230 MaskValue |= (1 << i);
10231 else
10232 return false;
10233 }
10235 if (MaskOut)
10236 *MaskOut = MaskValue;
10237 return true;
10238 }
10240 // Try to lower a shuffle node into a simple blend instruction.
10241 // This function assumes isBlendMask returns true for this
10242 // SuffleVectorSDNode
10243 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
10244 unsigned MaskValue,
10245 const X86Subtarget *Subtarget,
10246 SelectionDAG &DAG) {
10247 MVT VT = SVOp->getSimpleValueType(0);
10248 MVT EltVT = VT.getVectorElementType();
10249 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
10250 Subtarget->hasInt256() && "Trying to lower a "
10251 "VECTOR_SHUFFLE to a Blend but "
10252 "with the wrong mask"));
10253 SDValue V1 = SVOp->getOperand(0);
10254 SDValue V2 = SVOp->getOperand(1);
10255 SDLoc dl(SVOp);
10256 unsigned NumElems = VT.getVectorNumElements();
10258 // Convert i32 vectors to floating point if it is not AVX2.
10259 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
10260 MVT BlendVT = VT;
10261 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
10262 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
10263 NumElems);
10264 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
10265 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
10266 }
10268 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
10269 DAG.getConstant(MaskValue, MVT::i32));
10270 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
10271 }
10273 /// In vector type \p VT, return true if the element at index \p InputIdx
10274 /// falls on a different 128-bit lane than \p OutputIdx.
10275 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
10276 unsigned OutputIdx) {
10277 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
10278 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
10279 }
10281 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
10282 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
10283 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
10284 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
10285 /// zero.
10286 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
10287 SelectionDAG &DAG) {
10288 MVT VT = V1.getSimpleValueType();
10289 assert(VT.is128BitVector() || VT.is256BitVector());
10291 MVT EltVT = VT.getVectorElementType();
10292 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
10293 unsigned NumElts = VT.getVectorNumElements();
10295 SmallVector<SDValue, 32> PshufbMask;
10296 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
10297 int InputIdx = MaskVals[OutputIdx];
10298 unsigned InputByteIdx;
10300 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
10301 InputByteIdx = 0x80;
10302 else {
10303 // Cross lane is not allowed.
10304 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
10305 return SDValue();
10306 InputByteIdx = InputIdx * EltSizeInBytes;
10307 // Index is an byte offset within the 128-bit lane.
10308 InputByteIdx &= 0xf;
10309 }
10311 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
10312 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
10313 if (InputByteIdx != 0x80)
10314 ++InputByteIdx;
10315 }
10316 }
10318 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
10319 if (ShufVT != VT)
10320 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
10321 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
10322 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
10323 }
10325 // v8i16 shuffles - Prefer shuffles in the following order:
10326 // 1. [all] pshuflw, pshufhw, optional move
10327 // 2. [ssse3] 1 x pshufb
10328 // 3. [ssse3] 2 x pshufb + 1 x por
10329 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
10330 static SDValue
10331 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
10332 SelectionDAG &DAG) {
10333 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10334 SDValue V1 = SVOp->getOperand(0);
10335 SDValue V2 = SVOp->getOperand(1);
10336 SDLoc dl(SVOp);
10337 SmallVector<int, 8> MaskVals;
10339 // Determine if more than 1 of the words in each of the low and high quadwords
10340 // of the result come from the same quadword of one of the two inputs. Undef
10341 // mask values count as coming from any quadword, for better codegen.
10342 //
10343 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
10344 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
10345 unsigned LoQuad[] = { 0, 0, 0, 0 };
10346 unsigned HiQuad[] = { 0, 0, 0, 0 };
10347 // Indices of quads used.
10348 std::bitset<4> InputQuads;
10349 for (unsigned i = 0; i < 8; ++i) {
10350 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
10351 int EltIdx = SVOp->getMaskElt(i);
10352 MaskVals.push_back(EltIdx);
10353 if (EltIdx < 0) {
10354 ++Quad[0];
10355 ++Quad[1];
10356 ++Quad[2];
10357 ++Quad[3];
10358 continue;
10359 }
10360 ++Quad[EltIdx / 4];
10361 InputQuads.set(EltIdx / 4);
10362 }
10364 int BestLoQuad = -1;
10365 unsigned MaxQuad = 1;
10366 for (unsigned i = 0; i < 4; ++i) {
10367 if (LoQuad[i] > MaxQuad) {
10368 BestLoQuad = i;
10369 MaxQuad = LoQuad[i];
10370 }
10371 }
10373 int BestHiQuad = -1;
10374 MaxQuad = 1;
10375 for (unsigned i = 0; i < 4; ++i) {
10376 if (HiQuad[i] > MaxQuad) {
10377 BestHiQuad = i;
10378 MaxQuad = HiQuad[i];
10379 }
10380 }
10382 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
10383 // of the two input vectors, shuffle them into one input vector so only a
10384 // single pshufb instruction is necessary. If there are more than 2 input
10385 // quads, disable the next transformation since it does not help SSSE3.
10386 bool V1Used = InputQuads[0] || InputQuads[1];
10387 bool V2Used = InputQuads[2] || InputQuads[3];
10388 if (Subtarget->hasSSSE3()) {
10389 if (InputQuads.count() == 2 && V1Used && V2Used) {
10390 BestLoQuad = InputQuads[0] ? 0 : 1;
10391 BestHiQuad = InputQuads[2] ? 2 : 3;
10392 }
10393 if (InputQuads.count() > 2) {
10394 BestLoQuad = -1;
10395 BestHiQuad = -1;
10396 }
10397 }
10399 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
10400 // the shuffle mask. If a quad is scored as -1, that means that it contains
10401 // words from all 4 input quadwords.
10402 SDValue NewV;
10403 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
10404 int MaskV[] = {
10405 BestLoQuad < 0 ? 0 : BestLoQuad,
10406 BestHiQuad < 0 ? 1 : BestHiQuad
10407 };
10408 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
10409 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
10410 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
10411 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
10413 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
10414 // source words for the shuffle, to aid later transformations.
10415 bool AllWordsInNewV = true;
10416 bool InOrder[2] = { true, true };
10417 for (unsigned i = 0; i != 8; ++i) {
10418 int idx = MaskVals[i];
10419 if (idx != (int)i)
10420 InOrder[i/4] = false;
10421 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
10422 continue;
10423 AllWordsInNewV = false;
10424 break;
10425 }
10427 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
10428 if (AllWordsInNewV) {
10429 for (int i = 0; i != 8; ++i) {
10430 int idx = MaskVals[i];
10431 if (idx < 0)
10432 continue;
10433 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
10434 if ((idx != i) && idx < 4)
10435 pshufhw = false;
10436 if ((idx != i) && idx > 3)
10437 pshuflw = false;
10438 }
10439 V1 = NewV;
10440 V2Used = false;
10441 BestLoQuad = 0;
10442 BestHiQuad = 1;
10443 }
10445 // If we've eliminated the use of V2, and the new mask is a pshuflw or
10446 // pshufhw, that's as cheap as it gets. Return the new shuffle.
10447 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
10448 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
10449 unsigned TargetMask = 0;
10450 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
10451 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
10452 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10453 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
10454 getShufflePSHUFLWImmediate(SVOp);
10455 V1 = NewV.getOperand(0);
10456 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
10457 }
10458 }
10460 // Promote splats to a larger type which usually leads to more efficient code.
10461 // FIXME: Is this true if pshufb is available?
10462 if (SVOp->isSplat())
10463 return PromoteSplat(SVOp, DAG);
10465 // If we have SSSE3, and all words of the result are from 1 input vector,
10466 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
10467 // is present, fall back to case 4.
10468 if (Subtarget->hasSSSE3()) {
10469 SmallVector<SDValue,16> pshufbMask;
10471 // If we have elements from both input vectors, set the high bit of the
10472 // shuffle mask element to zero out elements that come from V2 in the V1
10473 // mask, and elements that come from V1 in the V2 mask, so that the two
10474 // results can be OR'd together.
10475 bool TwoInputs = V1Used && V2Used;
10476 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
10477 if (!TwoInputs)
10478 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10480 // Calculate the shuffle mask for the second input, shuffle it, and
10481 // OR it with the first shuffled input.
10482 CommuteVectorShuffleMask(MaskVals, 8);
10483 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
10484 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
10485 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10486 }
10488 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
10489 // and update MaskVals with new element order.
10490 std::bitset<8> InOrder;
10491 if (BestLoQuad >= 0) {
10492 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
10493 for (int i = 0; i != 4; ++i) {
10494 int idx = MaskVals[i];
10495 if (idx < 0) {
10496 InOrder.set(i);
10497 } else if ((idx / 4) == BestLoQuad) {
10498 MaskV[i] = idx & 3;
10499 InOrder.set(i);
10500 }
10501 }
10502 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10503 &MaskV[0]);
10505 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10506 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10507 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
10508 NewV.getOperand(0),
10509 getShufflePSHUFLWImmediate(SVOp), DAG);
10510 }
10511 }
10513 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
10514 // and update MaskVals with the new element order.
10515 if (BestHiQuad >= 0) {
10516 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
10517 for (unsigned i = 4; i != 8; ++i) {
10518 int idx = MaskVals[i];
10519 if (idx < 0) {
10520 InOrder.set(i);
10521 } else if ((idx / 4) == BestHiQuad) {
10522 MaskV[i] = (idx & 3) + 4;
10523 InOrder.set(i);
10524 }
10525 }
10526 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10527 &MaskV[0]);
10529 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10530 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10531 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
10532 NewV.getOperand(0),
10533 getShufflePSHUFHWImmediate(SVOp), DAG);
10534 }
10535 }
10537 // In case BestHi & BestLo were both -1, which means each quadword has a word
10538 // from each of the four input quadwords, calculate the InOrder bitvector now
10539 // before falling through to the insert/extract cleanup.
10540 if (BestLoQuad == -1 && BestHiQuad == -1) {
10541 NewV = V1;
10542 for (int i = 0; i != 8; ++i)
10543 if (MaskVals[i] < 0 || MaskVals[i] == i)
10544 InOrder.set(i);
10545 }
10547 // The other elements are put in the right place using pextrw and pinsrw.
10548 for (unsigned i = 0; i != 8; ++i) {
10549 if (InOrder[i])
10550 continue;
10551 int EltIdx = MaskVals[i];
10552 if (EltIdx < 0)
10553 continue;
10554 SDValue ExtOp = (EltIdx < 8) ?
10555 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
10556 DAG.getIntPtrConstant(EltIdx)) :
10557 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
10558 DAG.getIntPtrConstant(EltIdx - 8));
10559 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
10560 DAG.getIntPtrConstant(i));
10561 }
10562 return NewV;
10563 }
10565 /// \brief v16i16 shuffles
10566 ///
10567 /// FIXME: We only support generation of a single pshufb currently. We can
10568 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
10569 /// well (e.g 2 x pshufb + 1 x por).
10570 static SDValue
10571 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
10572 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10573 SDValue V1 = SVOp->getOperand(0);
10574 SDValue V2 = SVOp->getOperand(1);
10575 SDLoc dl(SVOp);
10577 if (V2.getOpcode() != ISD::UNDEF)
10578 return SDValue();
10580 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10581 return getPSHUFB(MaskVals, V1, dl, DAG);
10582 }
10584 // v16i8 shuffles - Prefer shuffles in the following order:
10585 // 1. [ssse3] 1 x pshufb
10586 // 2. [ssse3] 2 x pshufb + 1 x por
10587 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
10588 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
10589 const X86Subtarget* Subtarget,
10590 SelectionDAG &DAG) {
10591 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10592 SDValue V1 = SVOp->getOperand(0);
10593 SDValue V2 = SVOp->getOperand(1);
10594 SDLoc dl(SVOp);
10595 ArrayRef<int> MaskVals = SVOp->getMask();
10597 // Promote splats to a larger type which usually leads to more efficient code.
10598 // FIXME: Is this true if pshufb is available?
10599 if (SVOp->isSplat())
10600 return PromoteSplat(SVOp, DAG);
10602 // If we have SSSE3, case 1 is generated when all result bytes come from
10603 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
10604 // present, fall back to case 3.
10606 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
10607 if (Subtarget->hasSSSE3()) {
10608 SmallVector<SDValue,16> pshufbMask;
10610 // If all result elements are from one input vector, then only translate
10611 // undef mask values to 0x80 (zero out result) in the pshufb mask.
10612 //
10613 // Otherwise, we have elements from both input vectors, and must zero out
10614 // elements that come from V2 in the first mask, and V1 in the second mask
10615 // so that we can OR them together.
10616 for (unsigned i = 0; i != 16; ++i) {
10617 int EltIdx = MaskVals[i];
10618 if (EltIdx < 0 || EltIdx >= 16)
10619 EltIdx = 0x80;
10620 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10621 }
10622 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
10623 DAG.getNode(ISD::BUILD_VECTOR, dl,
10624 MVT::v16i8, pshufbMask));
10626 // As PSHUFB will zero elements with negative indices, it's safe to ignore
10627 // the 2nd operand if it's undefined or zero.
10628 if (V2.getOpcode() == ISD::UNDEF ||
10629 ISD::isBuildVectorAllZeros(V2.getNode()))
10630 return V1;
10632 // Calculate the shuffle mask for the second input, shuffle it, and
10633 // OR it with the first shuffled input.
10634 pshufbMask.clear();
10635 for (unsigned i = 0; i != 16; ++i) {
10636 int EltIdx = MaskVals[i];
10637 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
10638 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10639 }
10640 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
10641 DAG.getNode(ISD::BUILD_VECTOR, dl,
10642 MVT::v16i8, pshufbMask));
10643 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
10644 }
10646 // No SSSE3 - Calculate in place words and then fix all out of place words
10647 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
10648 // the 16 different words that comprise the two doublequadword input vectors.
10649 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10650 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
10651 SDValue NewV = V1;
10652 for (int i = 0; i != 8; ++i) {
10653 int Elt0 = MaskVals[i*2];
10654 int Elt1 = MaskVals[i*2+1];
10656 // This word of the result is all undef, skip it.
10657 if (Elt0 < 0 && Elt1 < 0)
10658 continue;
10660 // This word of the result is already in the correct place, skip it.
10661 if ((Elt0 == i*2) && (Elt1 == i*2+1))
10662 continue;
10664 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
10665 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
10666 SDValue InsElt;
10668 // If Elt0 and Elt1 are defined, are consecutive, and can be load
10669 // using a single extract together, load it and store it.
10670 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
10671 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
10672 DAG.getIntPtrConstant(Elt1 / 2));
10673 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10674 DAG.getIntPtrConstant(i));
10675 continue;
10676 }
10678 // If Elt1 is defined, extract it from the appropriate source. If the
10679 // source byte is not also odd, shift the extracted word left 8 bits
10680 // otherwise clear the bottom 8 bits if we need to do an or.
10681 if (Elt1 >= 0) {
10682 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
10683 DAG.getIntPtrConstant(Elt1 / 2));
10684 if ((Elt1 & 1) == 0)
10685 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
10686 DAG.getConstant(8,
10687 TLI.getShiftAmountTy(InsElt.getValueType())));
10688 else if (Elt0 >= 0)
10689 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
10690 DAG.getConstant(0xFF00, MVT::i16));
10691 }
10692 // If Elt0 is defined, extract it from the appropriate source. If the
10693 // source byte is not also even, shift the extracted word right 8 bits. If
10694 // Elt1 was also defined, OR the extracted values together before
10695 // inserting them in the result.
10696 if (Elt0 >= 0) {
10697 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
10698 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
10699 if ((Elt0 & 1) != 0)
10700 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
10701 DAG.getConstant(8,
10702 TLI.getShiftAmountTy(InsElt0.getValueType())));
10703 else if (Elt1 >= 0)
10704 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
10705 DAG.getConstant(0x00FF, MVT::i16));
10706 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
10707 : InsElt0;
10708 }
10709 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10710 DAG.getIntPtrConstant(i));
10711 }
10712 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
10713 }
10715 // v32i8 shuffles - Translate to VPSHUFB if possible.
10716 static
10717 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
10718 const X86Subtarget *Subtarget,
10719 SelectionDAG &DAG) {
10720 MVT VT = SVOp->getSimpleValueType(0);
10721 SDValue V1 = SVOp->getOperand(0);
10722 SDValue V2 = SVOp->getOperand(1);
10723 SDLoc dl(SVOp);
10724 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10726 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10727 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
10728 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
10730 // VPSHUFB may be generated if
10731 // (1) one of input vector is undefined or zeroinitializer.
10732 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
10733 // And (2) the mask indexes don't cross the 128-bit lane.
10734 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
10735 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
10736 return SDValue();
10738 if (V1IsAllZero && !V2IsAllZero) {
10739 CommuteVectorShuffleMask(MaskVals, 32);
10740 V1 = V2;
10741 }
10742 return getPSHUFB(MaskVals, V1, dl, DAG);
10743 }
10745 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
10746 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
10747 /// done when every pair / quad of shuffle mask elements point to elements in
10748 /// the right sequence. e.g.
10749 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
10750 static
10751 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
10752 SelectionDAG &DAG) {
10753 MVT VT = SVOp->getSimpleValueType(0);
10754 SDLoc dl(SVOp);
10755 unsigned NumElems = VT.getVectorNumElements();
10756 MVT NewVT;
10757 unsigned Scale;
10758 switch (VT.SimpleTy) {
10759 default: llvm_unreachable("Unexpected!");
10760 case MVT::v2i64:
10761 case MVT::v2f64:
10762 return SDValue(SVOp, 0);
10763 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
10764 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
10765 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
10766 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
10767 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
10768 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
10769 }
10771 SmallVector<int, 8> MaskVec;
10772 for (unsigned i = 0; i != NumElems; i += Scale) {
10773 int StartIdx = -1;
10774 for (unsigned j = 0; j != Scale; ++j) {
10775 int EltIdx = SVOp->getMaskElt(i+j);
10776 if (EltIdx < 0)
10777 continue;
10778 if (StartIdx < 0)
10779 StartIdx = (EltIdx / Scale);
10780 if (EltIdx != (int)(StartIdx*Scale + j))
10781 return SDValue();
10782 }
10783 MaskVec.push_back(StartIdx);
10784 }
10786 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
10787 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
10788 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
10789 }
10791 /// getVZextMovL - Return a zero-extending vector move low node.
10792 ///
10793 static SDValue getVZextMovL(MVT VT, MVT OpVT,
10794 SDValue SrcOp, SelectionDAG &DAG,
10795 const X86Subtarget *Subtarget, SDLoc dl) {
10796 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
10797 LoadSDNode *LD = nullptr;
10798 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
10799 LD = dyn_cast<LoadSDNode>(SrcOp);
10800 if (!LD) {
10801 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
10802 // instead.
10803 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
10804 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
10805 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
10806 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
10807 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
10808 // PR2108
10809 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
10810 return DAG.getNode(ISD::BITCAST, dl, VT,
10811 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
10812 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
10813 OpVT,
10814 SrcOp.getOperand(0)
10815 .getOperand(0))));
10816 }
10817 }
10818 }
10820 return DAG.getNode(ISD::BITCAST, dl, VT,
10821 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
10822 DAG.getNode(ISD::BITCAST, dl,
10823 OpVT, SrcOp)));
10824 }
10826 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
10827 /// which could not be matched by any known target speficic shuffle
10828 static SDValue
10829 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
10831 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
10832 if (NewOp.getNode())
10833 return NewOp;
10835 MVT VT = SVOp->getSimpleValueType(0);
10837 unsigned NumElems = VT.getVectorNumElements();
10838 unsigned NumLaneElems = NumElems / 2;
10840 SDLoc dl(SVOp);
10841 MVT EltVT = VT.getVectorElementType();
10842 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
10843 SDValue Output[2];
10845 SmallVector<int, 16> Mask;
10846 for (unsigned l = 0; l < 2; ++l) {
10847 // Build a shuffle mask for the output, discovering on the fly which
10848 // input vectors to use as shuffle operands (recorded in InputUsed).
10849 // If building a suitable shuffle vector proves too hard, then bail
10850 // out with UseBuildVector set.
10851 bool UseBuildVector = false;
10852 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
10853 unsigned LaneStart = l * NumLaneElems;
10854 for (unsigned i = 0; i != NumLaneElems; ++i) {
10855 // The mask element. This indexes into the input.
10856 int Idx = SVOp->getMaskElt(i+LaneStart);
10857 if (Idx < 0) {
10858 // the mask element does not index into any input vector.
10859 Mask.push_back(-1);
10860 continue;
10861 }
10863 // The input vector this mask element indexes into.
10864 int Input = Idx / NumLaneElems;
10866 // Turn the index into an offset from the start of the input vector.
10867 Idx -= Input * NumLaneElems;
10869 // Find or create a shuffle vector operand to hold this input.
10870 unsigned OpNo;
10871 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
10872 if (InputUsed[OpNo] == Input)
10873 // This input vector is already an operand.
10874 break;
10875 if (InputUsed[OpNo] < 0) {
10876 // Create a new operand for this input vector.
10877 InputUsed[OpNo] = Input;
10878 break;
10879 }
10880 }
10882 if (OpNo >= array_lengthof(InputUsed)) {
10883 // More than two input vectors used! Give up on trying to create a
10884 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
10885 UseBuildVector = true;
10886 break;
10887 }
10889 // Add the mask index for the new shuffle vector.
10890 Mask.push_back(Idx + OpNo * NumLaneElems);
10891 }
10893 if (UseBuildVector) {
10894 SmallVector<SDValue, 16> SVOps;
10895 for (unsigned i = 0; i != NumLaneElems; ++i) {
10896 // The mask element. This indexes into the input.
10897 int Idx = SVOp->getMaskElt(i+LaneStart);
10898 if (Idx < 0) {
10899 SVOps.push_back(DAG.getUNDEF(EltVT));
10900 continue;
10901 }
10903 // The input vector this mask element indexes into.
10904 int Input = Idx / NumElems;
10906 // Turn the index into an offset from the start of the input vector.
10907 Idx -= Input * NumElems;
10909 // Extract the vector element by hand.
10910 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
10911 SVOp->getOperand(Input),
10912 DAG.getIntPtrConstant(Idx)));
10913 }
10915 // Construct the output using a BUILD_VECTOR.
10916 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
10917 } else if (InputUsed[0] < 0) {
10918 // No input vectors were used! The result is undefined.
10919 Output[l] = DAG.getUNDEF(NVT);
10920 } else {
10921 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
10922 (InputUsed[0] % 2) * NumLaneElems,
10923 DAG, dl);
10924 // If only one input was used, use an undefined vector for the other.
10925 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
10926 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
10927 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
10928 // At least one input vector was used. Create a new shuffle vector.
10929 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
10930 }
10932 Mask.clear();
10933 }
10935 // Concatenate the result back
10936 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
10937 }
10939 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
10940 /// 4 elements, and match them with several different shuffle types.
10941 static SDValue
10942 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
10943 SDValue V1 = SVOp->getOperand(0);
10944 SDValue V2 = SVOp->getOperand(1);
10945 SDLoc dl(SVOp);
10946 MVT VT = SVOp->getSimpleValueType(0);
10948 assert(VT.is128BitVector() && "Unsupported vector size");
10950 std::pair<int, int> Locs[4];
10951 int Mask1[] = { -1, -1, -1, -1 };
10952 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
10954 unsigned NumHi = 0;
10955 unsigned NumLo = 0;
10956 for (unsigned i = 0; i != 4; ++i) {
10957 int Idx = PermMask[i];
10958 if (Idx < 0) {
10959 Locs[i] = std::make_pair(-1, -1);
10960 } else {
10961 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
10962 if (Idx < 4) {
10963 Locs[i] = std::make_pair(0, NumLo);
10964 Mask1[NumLo] = Idx;
10965 NumLo++;
10966 } else {
10967 Locs[i] = std::make_pair(1, NumHi);
10968 if (2+NumHi < 4)
10969 Mask1[2+NumHi] = Idx;
10970 NumHi++;
10971 }
10972 }
10973 }
10975 if (NumLo <= 2 && NumHi <= 2) {
10976 // If no more than two elements come from either vector. This can be
10977 // implemented with two shuffles. First shuffle gather the elements.
10978 // The second shuffle, which takes the first shuffle as both of its
10979 // vector operands, put the elements into the right order.
10980 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
10982 int Mask2[] = { -1, -1, -1, -1 };
10984 for (unsigned i = 0; i != 4; ++i)
10985 if (Locs[i].first != -1) {
10986 unsigned Idx = (i < 2) ? 0 : 4;
10987 Idx += Locs[i].first * 2 + Locs[i].second;
10988 Mask2[i] = Idx;
10989 }
10991 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
10992 }
10994 if (NumLo == 3 || NumHi == 3) {
10995 // Otherwise, we must have three elements from one vector, call it X, and
10996 // one element from the other, call it Y. First, use a shufps to build an
10997 // intermediate vector with the one element from Y and the element from X
10998 // that will be in the same half in the final destination (the indexes don't
10999 // matter). Then, use a shufps to build the final vector, taking the half
11000 // containing the element from Y from the intermediate, and the other half
11001 // from X.
11002 if (NumHi == 3) {
11003 // Normalize it so the 3 elements come from V1.
11004 CommuteVectorShuffleMask(PermMask, 4);
11005 std::swap(V1, V2);
11006 }
11008 // Find the element from V2.
11009 unsigned HiIndex;
11010 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
11011 int Val = PermMask[HiIndex];
11012 if (Val < 0)
11013 continue;
11014 if (Val >= 4)
11015 break;
11016 }
11018 Mask1[0] = PermMask[HiIndex];
11019 Mask1[1] = -1;
11020 Mask1[2] = PermMask[HiIndex^1];
11021 Mask1[3] = -1;
11022 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11024 if (HiIndex >= 2) {
11025 Mask1[0] = PermMask[0];
11026 Mask1[1] = PermMask[1];
11027 Mask1[2] = HiIndex & 1 ? 6 : 4;
11028 Mask1[3] = HiIndex & 1 ? 4 : 6;
11029 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11030 }
11032 Mask1[0] = HiIndex & 1 ? 2 : 0;
11033 Mask1[1] = HiIndex & 1 ? 0 : 2;
11034 Mask1[2] = PermMask[2];
11035 Mask1[3] = PermMask[3];
11036 if (Mask1[2] >= 0)
11037 Mask1[2] += 4;
11038 if (Mask1[3] >= 0)
11039 Mask1[3] += 4;
11040 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
11041 }
11043 // Break it into (shuffle shuffle_hi, shuffle_lo).
11044 int LoMask[] = { -1, -1, -1, -1 };
11045 int HiMask[] = { -1, -1, -1, -1 };
11047 int *MaskPtr = LoMask;
11048 unsigned MaskIdx = 0;
11049 unsigned LoIdx = 0;
11050 unsigned HiIdx = 2;
11051 for (unsigned i = 0; i != 4; ++i) {
11052 if (i == 2) {
11053 MaskPtr = HiMask;
11054 MaskIdx = 1;
11055 LoIdx = 0;
11056 HiIdx = 2;
11057 }
11058 int Idx = PermMask[i];
11059 if (Idx < 0) {
11060 Locs[i] = std::make_pair(-1, -1);
11061 } else if (Idx < 4) {
11062 Locs[i] = std::make_pair(MaskIdx, LoIdx);
11063 MaskPtr[LoIdx] = Idx;
11064 LoIdx++;
11065 } else {
11066 Locs[i] = std::make_pair(MaskIdx, HiIdx);
11067 MaskPtr[HiIdx] = Idx;
11068 HiIdx++;
11069 }
11070 }
11072 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
11073 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
11074 int MaskOps[] = { -1, -1, -1, -1 };
11075 for (unsigned i = 0; i != 4; ++i)
11076 if (Locs[i].first != -1)
11077 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
11078 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
11079 }
11081 static bool MayFoldVectorLoad(SDValue V) {
11082 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
11083 V = V.getOperand(0);
11085 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
11086 V = V.getOperand(0);
11087 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
11088 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
11089 // BUILD_VECTOR (load), undef
11090 V = V.getOperand(0);
11092 return MayFoldLoad(V);
11093 }
11095 static
11096 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
11097 MVT VT = Op.getSimpleValueType();
11099 // Canonizalize to v2f64.
11100 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
11101 return DAG.getNode(ISD::BITCAST, dl, VT,
11102 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
11103 V1, DAG));
11104 }
11106 static
11107 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
11108 bool HasSSE2) {
11109 SDValue V1 = Op.getOperand(0);
11110 SDValue V2 = Op.getOperand(1);
11111 MVT VT = Op.getSimpleValueType();
11113 assert(VT != MVT::v2i64 && "unsupported shuffle type");
11115 if (HasSSE2 && VT == MVT::v2f64)
11116 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
11118 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
11119 return DAG.getNode(ISD::BITCAST, dl, VT,
11120 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
11121 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
11122 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
11123 }
11125 static
11126 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
11127 SDValue V1 = Op.getOperand(0);
11128 SDValue V2 = Op.getOperand(1);
11129 MVT VT = Op.getSimpleValueType();
11131 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
11132 "unsupported shuffle type");
11134 if (V2.getOpcode() == ISD::UNDEF)
11135 V2 = V1;
11137 // v4i32 or v4f32
11138 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
11139 }
11141 static
11142 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
11143 SDValue V1 = Op.getOperand(0);
11144 SDValue V2 = Op.getOperand(1);
11145 MVT VT = Op.getSimpleValueType();
11146 unsigned NumElems = VT.getVectorNumElements();
11148 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
11149 // operand of these instructions is only memory, so check if there's a
11150 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
11151 // same masks.
11152 bool CanFoldLoad = false;
11154 // Trivial case, when V2 comes from a load.
11155 if (MayFoldVectorLoad(V2))
11156 CanFoldLoad = true;
11158 // When V1 is a load, it can be folded later into a store in isel, example:
11159 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
11160 // turns into:
11161 // (MOVLPSmr addr:$src1, VR128:$src2)
11162 // So, recognize this potential and also use MOVLPS or MOVLPD
11163 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
11164 CanFoldLoad = true;
11166 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11167 if (CanFoldLoad) {
11168 if (HasSSE2 && NumElems == 2)
11169 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
11171 if (NumElems == 4)
11172 // If we don't care about the second element, proceed to use movss.
11173 if (SVOp->getMaskElt(1) != -1)
11174 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
11175 }
11177 // movl and movlp will both match v2i64, but v2i64 is never matched by
11178 // movl earlier because we make it strict to avoid messing with the movlp load
11179 // folding logic (see the code above getMOVLP call). Match it here then,
11180 // this is horrible, but will stay like this until we move all shuffle
11181 // matching to x86 specific nodes. Note that for the 1st condition all
11182 // types are matched with movsd.
11183 if (HasSSE2) {
11184 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
11185 // as to remove this logic from here, as much as possible
11186 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
11187 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11188 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11189 }
11191 assert(VT != MVT::v4i32 && "unsupported shuffle type");
11193 // Invert the operand order and use SHUFPS to match it.
11194 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
11195 getShuffleSHUFImmediate(SVOp), DAG);
11196 }
11198 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
11199 SelectionDAG &DAG) {
11200 SDLoc dl(Load);
11201 MVT VT = Load->getSimpleValueType(0);
11202 MVT EVT = VT.getVectorElementType();
11203 SDValue Addr = Load->getOperand(1);
11204 SDValue NewAddr = DAG.getNode(
11205 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
11206 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
11208 SDValue NewLoad =
11209 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
11210 DAG.getMachineFunction().getMachineMemOperand(
11211 Load->getMemOperand(), 0, EVT.getStoreSize()));
11212 return NewLoad;
11213 }
11215 // It is only safe to call this function if isINSERTPSMask is true for
11216 // this shufflevector mask.
11217 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
11218 SelectionDAG &DAG) {
11219 // Generate an insertps instruction when inserting an f32 from memory onto a
11220 // v4f32 or when copying a member from one v4f32 to another.
11221 // We also use it for transferring i32 from one register to another,
11222 // since it simply copies the same bits.
11223 // If we're transferring an i32 from memory to a specific element in a
11224 // register, we output a generic DAG that will match the PINSRD
11225 // instruction.
11226 MVT VT = SVOp->getSimpleValueType(0);
11227 MVT EVT = VT.getVectorElementType();
11228 SDValue V1 = SVOp->getOperand(0);
11229 SDValue V2 = SVOp->getOperand(1);
11230 auto Mask = SVOp->getMask();
11231 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
11232 "unsupported vector type for insertps/pinsrd");
11234 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
11235 auto FromV2Predicate = [](const int &i) { return i >= 4; };
11236 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
11238 SDValue From;
11239 SDValue To;
11240 unsigned DestIndex;
11241 if (FromV1 == 1) {
11242 From = V1;
11243 To = V2;
11244 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
11245 Mask.begin();
11247 // If we have 1 element from each vector, we have to check if we're
11248 // changing V1's element's place. If so, we're done. Otherwise, we
11249 // should assume we're changing V2's element's place and behave
11250 // accordingly.
11251 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
11252 assert(DestIndex <= INT32_MAX && "truncated destination index");
11253 if (FromV1 == FromV2 &&
11254 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
11255 From = V2;
11256 To = V1;
11257 DestIndex =
11258 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11259 }
11260 } else {
11261 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
11262 "More than one element from V1 and from V2, or no elements from one "
11263 "of the vectors. This case should not have returned true from "
11264 "isINSERTPSMask");
11265 From = V2;
11266 To = V1;
11267 DestIndex =
11268 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11269 }
11271 // Get an index into the source vector in the range [0,4) (the mask is
11272 // in the range [0,8) because it can address V1 and V2)
11273 unsigned SrcIndex = Mask[DestIndex] % 4;
11274 if (MayFoldLoad(From)) {
11275 // Trivial case, when From comes from a load and is only used by the
11276 // shuffle. Make it use insertps from the vector that we need from that
11277 // load.
11278 SDValue NewLoad =
11279 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
11280 if (!NewLoad.getNode())
11281 return SDValue();
11283 if (EVT == MVT::f32) {
11284 // Create this as a scalar to vector to match the instruction pattern.
11285 SDValue LoadScalarToVector =
11286 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
11287 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
11288 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
11289 InsertpsMask);
11290 } else { // EVT == MVT::i32
11291 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
11292 // instruction, to match the PINSRD instruction, which loads an i32 to a
11293 // certain vector element.
11294 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
11295 DAG.getConstant(DestIndex, MVT::i32));
11296 }
11297 }
11299 // Vector-element-to-vector
11300 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
11301 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
11302 }
11304 // Reduce a vector shuffle to zext.
11305 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
11306 SelectionDAG &DAG) {
11307 // PMOVZX is only available from SSE41.
11308 if (!Subtarget->hasSSE41())
11309 return SDValue();
11311 MVT VT = Op.getSimpleValueType();
11313 // Only AVX2 support 256-bit vector integer extending.
11314 if (!Subtarget->hasInt256() && VT.is256BitVector())
11315 return SDValue();
11317 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11318 SDLoc DL(Op);
11319 SDValue V1 = Op.getOperand(0);
11320 SDValue V2 = Op.getOperand(1);
11321 unsigned NumElems = VT.getVectorNumElements();
11323 // Extending is an unary operation and the element type of the source vector
11324 // won't be equal to or larger than i64.
11325 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
11326 VT.getVectorElementType() == MVT::i64)
11327 return SDValue();
11329 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
11330 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
11331 while ((1U << Shift) < NumElems) {
11332 if (SVOp->getMaskElt(1U << Shift) == 1)
11333 break;
11334 Shift += 1;
11335 // The maximal ratio is 8, i.e. from i8 to i64.
11336 if (Shift > 3)
11337 return SDValue();
11338 }
11340 // Check the shuffle mask.
11341 unsigned Mask = (1U << Shift) - 1;
11342 for (unsigned i = 0; i != NumElems; ++i) {
11343 int EltIdx = SVOp->getMaskElt(i);
11344 if ((i & Mask) != 0 && EltIdx != -1)
11345 return SDValue();
11346 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
11347 return SDValue();
11348 }
11350 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
11351 MVT NeVT = MVT::getIntegerVT(NBits);
11352 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
11354 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
11355 return SDValue();
11357 // Simplify the operand as it's prepared to be fed into shuffle.
11358 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
11359 if (V1.getOpcode() == ISD::BITCAST &&
11360 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
11361 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
11362 V1.getOperand(0).getOperand(0)
11363 .getSimpleValueType().getSizeInBits() == SignificantBits) {
11364 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
11365 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
11366 ConstantSDNode *CIdx =
11367 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
11368 // If it's foldable, i.e. normal load with single use, we will let code
11369 // selection to fold it. Otherwise, we will short the conversion sequence.
11370 if (CIdx && CIdx->getZExtValue() == 0 &&
11371 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
11372 MVT FullVT = V.getSimpleValueType();
11373 MVT V1VT = V1.getSimpleValueType();
11374 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
11375 // The "ext_vec_elt" node is wider than the result node.
11376 // In this case we should extract subvector from V.
11377 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
11378 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
11379 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
11380 FullVT.getVectorNumElements()/Ratio);
11381 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
11382 DAG.getIntPtrConstant(0));
11383 }
11384 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
11385 }
11386 }
11388 return DAG.getNode(ISD::BITCAST, DL, VT,
11389 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
11390 }
11392 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
11393 SelectionDAG &DAG) {
11394 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11395 MVT VT = Op.getSimpleValueType();
11396 SDLoc dl(Op);
11397 SDValue V1 = Op.getOperand(0);
11398 SDValue V2 = Op.getOperand(1);
11400 if (isZeroShuffle(SVOp))
11401 return getZeroVector(VT, Subtarget, DAG, dl);
11403 // Handle splat operations
11404 if (SVOp->isSplat()) {
11405 // Use vbroadcast whenever the splat comes from a foldable load
11406 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
11407 if (Broadcast.getNode())
11408 return Broadcast;
11409 }
11411 // Check integer expanding shuffles.
11412 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
11413 if (NewOp.getNode())
11414 return NewOp;
11416 // If the shuffle can be profitably rewritten as a narrower shuffle, then
11417 // do it!
11418 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
11419 VT == MVT::v32i8) {
11420 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11421 if (NewOp.getNode())
11422 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
11423 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
11424 // FIXME: Figure out a cleaner way to do this.
11425 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
11426 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11427 if (NewOp.getNode()) {
11428 MVT NewVT = NewOp.getSimpleValueType();
11429 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
11430 NewVT, true, false))
11431 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
11432 dl);
11433 }
11434 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
11435 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11436 if (NewOp.getNode()) {
11437 MVT NewVT = NewOp.getSimpleValueType();
11438 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
11439 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
11440 dl);
11441 }
11442 }
11443 }
11444 return SDValue();
11445 }
11447 SDValue
11448 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
11449 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11450 SDValue V1 = Op.getOperand(0);
11451 SDValue V2 = Op.getOperand(1);
11452 MVT VT = Op.getSimpleValueType();
11453 SDLoc dl(Op);
11454 unsigned NumElems = VT.getVectorNumElements();
11455 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
11456 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11457 bool V1IsSplat = false;
11458 bool V2IsSplat = false;
11459 bool HasSSE2 = Subtarget->hasSSE2();
11460 bool HasFp256 = Subtarget->hasFp256();
11461 bool HasInt256 = Subtarget->hasInt256();
11462 MachineFunction &MF = DAG.getMachineFunction();
11463 bool OptForSize = MF.getFunction()->getAttributes().
11464 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
11466 // Check if we should use the experimental vector shuffle lowering. If so,
11467 // delegate completely to that code path.
11468 if (ExperimentalVectorShuffleLowering)
11469 return lowerVectorShuffle(Op, Subtarget, DAG);
11471 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
11473 if (V1IsUndef && V2IsUndef)
11474 return DAG.getUNDEF(VT);
11476 // When we create a shuffle node we put the UNDEF node to second operand,
11477 // but in some cases the first operand may be transformed to UNDEF.
11478 // In this case we should just commute the node.
11479 if (V1IsUndef)
11480 return DAG.getCommutedVectorShuffle(*SVOp);
11482 // Vector shuffle lowering takes 3 steps:
11483 //
11484 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
11485 // narrowing and commutation of operands should be handled.
11486 // 2) Matching of shuffles with known shuffle masks to x86 target specific
11487 // shuffle nodes.
11488 // 3) Rewriting of unmatched masks into new generic shuffle operations,
11489 // so the shuffle can be broken into other shuffles and the legalizer can
11490 // try the lowering again.
11491 //
11492 // The general idea is that no vector_shuffle operation should be left to
11493 // be matched during isel, all of them must be converted to a target specific
11494 // node here.
11496 // Normalize the input vectors. Here splats, zeroed vectors, profitable
11497 // narrowing and commutation of operands should be handled. The actual code
11498 // doesn't include all of those, work in progress...
11499 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
11500 if (NewOp.getNode())
11501 return NewOp;
11503 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
11505 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
11506 // unpckh_undef). Only use pshufd if speed is more important than size.
11507 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11508 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11509 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11510 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11512 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
11513 V2IsUndef && MayFoldVectorLoad(V1))
11514 return getMOVDDup(Op, dl, V1, DAG);
11516 if (isMOVHLPS_v_undef_Mask(M, VT))
11517 return getMOVHighToLow(Op, dl, DAG);
11519 // Use to match splats
11520 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
11521 (VT == MVT::v2f64 || VT == MVT::v2i64))
11522 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11524 if (isPSHUFDMask(M, VT)) {
11525 // The actual implementation will match the mask in the if above and then
11526 // during isel it can match several different instructions, not only pshufd
11527 // as its name says, sad but true, emulate the behavior for now...
11528 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
11529 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
11531 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
11533 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
11534 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
11536 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
11537 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
11538 DAG);
11540 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
11541 TargetMask, DAG);
11542 }
11544 if (isPALIGNRMask(M, VT, Subtarget))
11545 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
11546 getShufflePALIGNRImmediate(SVOp),
11547 DAG);
11549 if (isVALIGNMask(M, VT, Subtarget))
11550 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
11551 getShuffleVALIGNImmediate(SVOp),
11552 DAG);
11554 // Check if this can be converted into a logical shift.
11555 bool isLeft = false;
11556 unsigned ShAmt = 0;
11557 SDValue ShVal;
11558 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
11559 if (isShift && ShVal.hasOneUse()) {
11560 // If the shifted value has multiple uses, it may be cheaper to use
11561 // v_set0 + movlhps or movhlps, etc.
11562 MVT EltVT = VT.getVectorElementType();
11563 ShAmt *= EltVT.getSizeInBits();
11564 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11565 }
11567 if (isMOVLMask(M, VT)) {
11568 if (ISD::isBuildVectorAllZeros(V1.getNode()))
11569 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
11570 if (!isMOVLPMask(M, VT)) {
11571 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
11572 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11574 if (VT == MVT::v4i32 || VT == MVT::v4f32)
11575 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11576 }
11577 }
11579 // FIXME: fold these into legal mask.
11580 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
11581 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
11583 if (isMOVHLPSMask(M, VT))
11584 return getMOVHighToLow(Op, dl, DAG);
11586 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
11587 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
11589 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
11590 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
11592 if (isMOVLPMask(M, VT))
11593 return getMOVLP(Op, dl, DAG, HasSSE2);
11595 if (ShouldXformToMOVHLPS(M, VT) ||
11596 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
11597 return DAG.getCommutedVectorShuffle(*SVOp);
11599 if (isShift) {
11600 // No better options. Use a vshldq / vsrldq.
11601 MVT EltVT = VT.getVectorElementType();
11602 ShAmt *= EltVT.getSizeInBits();
11603 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11604 }
11606 bool Commuted = false;
11607 // FIXME: This should also accept a bitcast of a splat? Be careful, not
11608 // 1,1,1,1 -> v8i16 though.
11609 BitVector UndefElements;
11610 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
11611 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11612 V1IsSplat = true;
11613 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
11614 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11615 V2IsSplat = true;
11617 // Canonicalize the splat or undef, if present, to be on the RHS.
11618 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
11619 CommuteVectorShuffleMask(M, NumElems);
11620 std::swap(V1, V2);
11621 std::swap(V1IsSplat, V2IsSplat);
11622 Commuted = true;
11623 }
11625 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
11626 // Shuffling low element of v1 into undef, just return v1.
11627 if (V2IsUndef)
11628 return V1;
11629 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
11630 // the instruction selector will not match, so get a canonical MOVL with
11631 // swapped operands to undo the commute.
11632 return getMOVL(DAG, dl, VT, V2, V1);
11633 }
11635 if (isUNPCKLMask(M, VT, HasInt256))
11636 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11638 if (isUNPCKHMask(M, VT, HasInt256))
11639 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11641 if (V2IsSplat) {
11642 // Normalize mask so all entries that point to V2 points to its first
11643 // element then try to match unpck{h|l} again. If match, return a
11644 // new vector_shuffle with the corrected mask.p
11645 SmallVector<int, 8> NewMask(M.begin(), M.end());
11646 NormalizeMask(NewMask, NumElems);
11647 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
11648 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11649 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
11650 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11651 }
11653 if (Commuted) {
11654 // Commute is back and try unpck* again.
11655 // FIXME: this seems wrong.
11656 CommuteVectorShuffleMask(M, NumElems);
11657 std::swap(V1, V2);
11658 std::swap(V1IsSplat, V2IsSplat);
11660 if (isUNPCKLMask(M, VT, HasInt256))
11661 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11663 if (isUNPCKHMask(M, VT, HasInt256))
11664 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11665 }
11667 // Normalize the node to match x86 shuffle ops if needed
11668 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
11669 return DAG.getCommutedVectorShuffle(*SVOp);
11671 // The checks below are all present in isShuffleMaskLegal, but they are
11672 // inlined here right now to enable us to directly emit target specific
11673 // nodes, and remove one by one until they don't return Op anymore.
11675 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
11676 SVOp->getSplatIndex() == 0 && V2IsUndef) {
11677 if (VT == MVT::v2f64 || VT == MVT::v2i64)
11678 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11679 }
11681 if (isPSHUFHWMask(M, VT, HasInt256))
11682 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
11683 getShufflePSHUFHWImmediate(SVOp),
11684 DAG);
11686 if (isPSHUFLWMask(M, VT, HasInt256))
11687 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
11688 getShufflePSHUFLWImmediate(SVOp),
11689 DAG);
11691 unsigned MaskValue;
11692 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
11693 &MaskValue))
11694 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
11696 if (isSHUFPMask(M, VT))
11697 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
11698 getShuffleSHUFImmediate(SVOp), DAG);
11700 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11701 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11702 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11703 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11705 //===--------------------------------------------------------------------===//
11706 // Generate target specific nodes for 128 or 256-bit shuffles only
11707 // supported in the AVX instruction set.
11708 //
11710 // Handle VMOVDDUPY permutations
11711 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
11712 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
11714 // Handle VPERMILPS/D* permutations
11715 if (isVPERMILPMask(M, VT)) {
11716 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
11717 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
11718 getShuffleSHUFImmediate(SVOp), DAG);
11719 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
11720 getShuffleSHUFImmediate(SVOp), DAG);
11721 }
11723 unsigned Idx;
11724 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
11725 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
11726 Idx*(NumElems/2), DAG, dl);
11728 // Handle VPERM2F128/VPERM2I128 permutations
11729 if (isVPERM2X128Mask(M, VT, HasFp256))
11730 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
11731 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
11733 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
11734 return getINSERTPS(SVOp, dl, DAG);
11736 unsigned Imm8;
11737 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
11738 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
11740 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
11741 VT.is512BitVector()) {
11742 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
11743 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
11744 SmallVector<SDValue, 16> permclMask;
11745 for (unsigned i = 0; i != NumElems; ++i) {
11746 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
11747 }
11749 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
11750 if (V2IsUndef)
11751 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
11752 return DAG.getNode(X86ISD::VPERMV, dl, VT,
11753 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
11754 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
11755 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
11756 }
11758 //===--------------------------------------------------------------------===//
11759 // Since no target specific shuffle was selected for this generic one,
11760 // lower it into other known shuffles. FIXME: this isn't true yet, but
11761 // this is the plan.
11762 //
11764 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
11765 if (VT == MVT::v8i16) {
11766 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
11767 if (NewOp.getNode())
11768 return NewOp;
11769 }
11771 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
11772 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
11773 if (NewOp.getNode())
11774 return NewOp;
11775 }
11777 if (VT == MVT::v16i8) {
11778 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
11779 if (NewOp.getNode())
11780 return NewOp;
11781 }
11783 if (VT == MVT::v32i8) {
11784 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
11785 if (NewOp.getNode())
11786 return NewOp;
11787 }
11789 // Handle all 128-bit wide vectors with 4 elements, and match them with
11790 // several different shuffle types.
11791 if (NumElems == 4 && VT.is128BitVector())
11792 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
11794 // Handle general 256-bit shuffles
11795 if (VT.is256BitVector())
11796 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
11798 return SDValue();
11799 }
11801 // This function assumes its argument is a BUILD_VECTOR of constants or
11802 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11803 // true.
11804 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11805 unsigned &MaskValue) {
11806 MaskValue = 0;
11807 unsigned NumElems = BuildVector->getNumOperands();
11808 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11809 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11810 unsigned NumElemsInLane = NumElems / NumLanes;
11812 // Blend for v16i16 should be symetric for the both lanes.
11813 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11814 SDValue EltCond = BuildVector->getOperand(i);
11815 SDValue SndLaneEltCond =
11816 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11818 int Lane1Cond = -1, Lane2Cond = -1;
11819 if (isa<ConstantSDNode>(EltCond))
11820 Lane1Cond = !isZero(EltCond);
11821 if (isa<ConstantSDNode>(SndLaneEltCond))
11822 Lane2Cond = !isZero(SndLaneEltCond);
11824 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11825 // Lane1Cond != 0, means we want the first argument.
11826 // Lane1Cond == 0, means we want the second argument.
11827 // The encoding of this argument is 0 for the first argument, 1
11828 // for the second. Therefore, invert the condition.
11829 MaskValue |= !Lane1Cond << i;
11830 else if (Lane1Cond < 0)
11831 MaskValue |= !Lane2Cond << i;
11832 else
11833 return false;
11834 }
11835 return true;
11836 }
11838 /// \brief Try to lower a VSELECT instruction to an immediate-controlled blend
11839 /// instruction.
11840 static SDValue lowerVSELECTtoBLENDI(SDValue Op, const X86Subtarget *Subtarget,
11841 SelectionDAG &DAG) {
11842 SDValue Cond = Op.getOperand(0);
11843 SDValue LHS = Op.getOperand(1);
11844 SDValue RHS = Op.getOperand(2);
11845 SDLoc dl(Op);
11846 MVT VT = Op.getSimpleValueType();
11847 MVT EltVT = VT.getVectorElementType();
11848 unsigned NumElems = VT.getVectorNumElements();
11850 // There is no blend with immediate in AVX-512.
11851 if (VT.is512BitVector())
11852 return SDValue();
11854 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
11855 return SDValue();
11856 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
11857 return SDValue();
11859 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11860 return SDValue();
11862 // Check the mask for BLEND and build the value.
11863 unsigned MaskValue = 0;
11864 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
11865 return SDValue();
11867 // Convert i32 vectors to floating point if it is not AVX2.
11868 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
11869 MVT BlendVT = VT;
11870 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
11871 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
11872 NumElems);
11873 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
11874 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
11875 }
11877 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
11878 DAG.getConstant(MaskValue, MVT::i32));
11879 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
11880 }
11882 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11883 // A vselect where all conditions and data are constants can be optimized into
11884 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11885 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11886 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11887 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11888 return SDValue();
11890 SDValue BlendOp = lowerVSELECTtoBLENDI(Op, Subtarget, DAG);
11891 if (BlendOp.getNode())
11892 return BlendOp;
11894 // Some types for vselect were previously set to Expand, not Legal or
11895 // Custom. Return an empty SDValue so we fall-through to Expand, after
11896 // the Custom lowering phase.
11897 MVT VT = Op.getSimpleValueType();
11898 switch (VT.SimpleTy) {
11899 default:
11900 break;
11901 case MVT::v8i16:
11902 case MVT::v16i16:
11903 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11904 break;
11905 return SDValue();
11906 }
11908 // We couldn't create a "Blend with immediate" node.
11909 // This node should still be legal, but we'll have to emit a blendv*
11910 // instruction.
11911 return Op;
11912 }
11914 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11915 MVT VT = Op.getSimpleValueType();
11916 SDLoc dl(Op);
11918 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11919 return SDValue();
11921 if (VT.getSizeInBits() == 8) {
11922 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11923 Op.getOperand(0), Op.getOperand(1));
11924 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11925 DAG.getValueType(VT));
11926 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11927 }
11929 if (VT.getSizeInBits() == 16) {
11930 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11931 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11932 if (Idx == 0)
11933 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11934 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11935 DAG.getNode(ISD::BITCAST, dl,
11936 MVT::v4i32,
11937 Op.getOperand(0)),
11938 Op.getOperand(1)));
11939 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11940 Op.getOperand(0), Op.getOperand(1));
11941 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11942 DAG.getValueType(VT));
11943 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11944 }
11946 if (VT == MVT::f32) {
11947 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11948 // the result back to FR32 register. It's only worth matching if the
11949 // result has a single use which is a store or a bitcast to i32. And in
11950 // the case of a store, it's not worth it if the index is a constant 0,
11951 // because a MOVSSmr can be used instead, which is smaller and faster.
11952 if (!Op.hasOneUse())
11953 return SDValue();
11954 SDNode *User = *Op.getNode()->use_begin();
11955 if ((User->getOpcode() != ISD::STORE ||
11956 (isa<ConstantSDNode>(Op.getOperand(1)) &&
11957 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
11958 (User->getOpcode() != ISD::BITCAST ||
11959 User->getValueType(0) != MVT::i32))
11960 return SDValue();
11961 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11962 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
11963 Op.getOperand(0)),
11964 Op.getOperand(1));
11965 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
11966 }
11968 if (VT == MVT::i32 || VT == MVT::i64) {
11969 // ExtractPS/pextrq works with constant index.
11970 if (isa<ConstantSDNode>(Op.getOperand(1)))
11971 return Op;
11972 }
11973 return SDValue();
11974 }
11976 /// Extract one bit from mask vector, like v16i1 or v8i1.
11977 /// AVX-512 feature.
11978 SDValue
11979 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
11980 SDValue Vec = Op.getOperand(0);
11981 SDLoc dl(Vec);
11982 MVT VecVT = Vec.getSimpleValueType();
11983 SDValue Idx = Op.getOperand(1);
11984 MVT EltVT = Op.getSimpleValueType();
11986 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
11988 // variable index can't be handled in mask registers,
11989 // extend vector to VR512
11990 if (!isa<ConstantSDNode>(Idx)) {
11991 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11992 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
11993 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
11994 ExtVT.getVectorElementType(), Ext, Idx);
11995 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
11996 }
11998 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11999 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12000 unsigned MaxSift = rc->getSize()*8 - 1;
12001 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
12002 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12003 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
12004 DAG.getConstant(MaxSift, MVT::i8));
12005 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
12006 DAG.getIntPtrConstant(0));
12007 }
12009 SDValue
12010 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
12011 SelectionDAG &DAG) const {
12012 SDLoc dl(Op);
12013 SDValue Vec = Op.getOperand(0);
12014 MVT VecVT = Vec.getSimpleValueType();
12015 SDValue Idx = Op.getOperand(1);
12017 if (Op.getSimpleValueType() == MVT::i1)
12018 return ExtractBitFromMaskVector(Op, DAG);
12020 if (!isa<ConstantSDNode>(Idx)) {
12021 if (VecVT.is512BitVector() ||
12022 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
12023 VecVT.getVectorElementType().getSizeInBits() == 32)) {
12025 MVT MaskEltVT =
12026 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
12027 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
12028 MaskEltVT.getSizeInBits());
12030 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
12031 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
12032 getZeroVector(MaskVT, Subtarget, DAG, dl),
12033 Idx, DAG.getConstant(0, getPointerTy()));
12034 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
12035 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
12036 Perm, DAG.getConstant(0, getPointerTy()));
12037 }
12038 return SDValue();
12039 }
12041 // If this is a 256-bit vector result, first extract the 128-bit vector and
12042 // then extract the element from the 128-bit vector.
12043 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
12045 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12046 // Get the 128-bit vector.
12047 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
12048 MVT EltVT = VecVT.getVectorElementType();
12050 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
12052 //if (IdxVal >= NumElems/2)
12053 // IdxVal -= NumElems/2;
12054 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
12055 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
12056 DAG.getConstant(IdxVal, MVT::i32));
12057 }
12059 assert(VecVT.is128BitVector() && "Unexpected vector length");
12061 if (Subtarget->hasSSE41()) {
12062 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
12063 if (Res.getNode())
12064 return Res;
12065 }
12067 MVT VT = Op.getSimpleValueType();
12068 // TODO: handle v16i8.
12069 if (VT.getSizeInBits() == 16) {
12070 SDValue Vec = Op.getOperand(0);
12071 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12072 if (Idx == 0)
12073 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12074 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12075 DAG.getNode(ISD::BITCAST, dl,
12076 MVT::v4i32, Vec),
12077 Op.getOperand(1)));
12078 // Transform it so it match pextrw which produces a 32-bit result.
12079 MVT EltVT = MVT::i32;
12080 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
12081 Op.getOperand(0), Op.getOperand(1));
12082 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
12083 DAG.getValueType(VT));
12084 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12085 }
12087 if (VT.getSizeInBits() == 32) {
12088 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12089 if (Idx == 0)
12090 return Op;
12092 // SHUFPS the element to the lowest double word, then movss.
12093 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
12094 MVT VVT = Op.getOperand(0).getSimpleValueType();
12095 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12096 DAG.getUNDEF(VVT), Mask);
12097 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12098 DAG.getIntPtrConstant(0));
12099 }
12101 if (VT.getSizeInBits() == 64) {
12102 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
12103 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
12104 // to match extract_elt for f64.
12105 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12106 if (Idx == 0)
12107 return Op;
12109 // UNPCKHPD the element to the lowest double word, then movsd.
12110 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
12111 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
12112 int Mask[2] = { 1, -1 };
12113 MVT VVT = Op.getOperand(0).getSimpleValueType();
12114 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12115 DAG.getUNDEF(VVT), Mask);
12116 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12117 DAG.getIntPtrConstant(0));
12118 }
12120 return SDValue();
12121 }
12123 /// Insert one bit to mask vector, like v16i1 or v8i1.
12124 /// AVX-512 feature.
12125 SDValue
12126 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
12127 SDLoc dl(Op);
12128 SDValue Vec = Op.getOperand(0);
12129 SDValue Elt = Op.getOperand(1);
12130 SDValue Idx = Op.getOperand(2);
12131 MVT VecVT = Vec.getSimpleValueType();
12133 if (!isa<ConstantSDNode>(Idx)) {
12134 // Non constant index. Extend source and destination,
12135 // insert element and then truncate the result.
12136 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12137 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
12138 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
12139 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
12140 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
12141 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
12142 }
12144 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12145 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
12146 if (Vec.getOpcode() == ISD::UNDEF)
12147 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12148 DAG.getConstant(IdxVal, MVT::i8));
12149 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12150 unsigned MaxSift = rc->getSize()*8 - 1;
12151 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12152 DAG.getConstant(MaxSift, MVT::i8));
12153 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
12154 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12155 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
12156 }
12158 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
12159 SelectionDAG &DAG) const {
12160 MVT VT = Op.getSimpleValueType();
12161 MVT EltVT = VT.getVectorElementType();
12163 if (EltVT == MVT::i1)
12164 return InsertBitToMaskVector(Op, DAG);
12166 SDLoc dl(Op);
12167 SDValue N0 = Op.getOperand(0);
12168 SDValue N1 = Op.getOperand(1);
12169 SDValue N2 = Op.getOperand(2);
12170 if (!isa<ConstantSDNode>(N2))
12171 return SDValue();
12172 auto *N2C = cast<ConstantSDNode>(N2);
12173 unsigned IdxVal = N2C->getZExtValue();
12175 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
12176 // into that, and then insert the subvector back into the result.
12177 if (VT.is256BitVector() || VT.is512BitVector()) {
12178 // Get the desired 128-bit vector half.
12179 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
12181 // Insert the element into the desired half.
12182 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
12183 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
12185 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
12186 DAG.getConstant(IdxIn128, MVT::i32));
12188 // Insert the changed part back to the 256-bit vector
12189 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
12190 }
12191 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
12193 if (Subtarget->hasSSE41()) {
12194 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
12195 unsigned Opc;
12196 if (VT == MVT::v8i16) {
12197 Opc = X86ISD::PINSRW;
12198 } else {
12199 assert(VT == MVT::v16i8);
12200 Opc = X86ISD::PINSRB;
12201 }
12203 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
12204 // argument.
12205 if (N1.getValueType() != MVT::i32)
12206 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12207 if (N2.getValueType() != MVT::i32)
12208 N2 = DAG.getIntPtrConstant(IdxVal);
12209 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
12210 }
12212 if (EltVT == MVT::f32) {
12213 // Bits [7:6] of the constant are the source select. This will always be
12214 // zero here. The DAG Combiner may combine an extract_elt index into
12215 // these
12216 // bits. For example (insert (extract, 3), 2) could be matched by
12217 // putting
12218 // the '3' into bits [7:6] of X86ISD::INSERTPS.
12219 // Bits [5:4] of the constant are the destination select. This is the
12220 // value of the incoming immediate.
12221 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
12222 // combine either bitwise AND or insert of float 0.0 to set these bits.
12223 N2 = DAG.getIntPtrConstant(IdxVal << 4);
12224 // Create this as a scalar to vector..
12225 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
12226 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
12227 }
12229 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
12230 // PINSR* works with constant index.
12231 return Op;
12232 }
12233 }
12235 if (EltVT == MVT::i8)
12236 return SDValue();
12238 if (EltVT.getSizeInBits() == 16) {
12239 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
12240 // as its second argument.
12241 if (N1.getValueType() != MVT::i32)
12242 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12243 if (N2.getValueType() != MVT::i32)
12244 N2 = DAG.getIntPtrConstant(IdxVal);
12245 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
12246 }
12247 return SDValue();
12248 }
12250 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
12251 SDLoc dl(Op);
12252 MVT OpVT = Op.getSimpleValueType();
12254 // If this is a 256-bit vector result, first insert into a 128-bit
12255 // vector and then insert into the 256-bit vector.
12256 if (!OpVT.is128BitVector()) {
12257 // Insert into a 128-bit vector.
12258 unsigned SizeFactor = OpVT.getSizeInBits()/128;
12259 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
12260 OpVT.getVectorNumElements() / SizeFactor);
12262 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
12264 // Insert the 128-bit vector.
12265 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
12266 }
12268 if (OpVT == MVT::v1i64 &&
12269 Op.getOperand(0).getValueType() == MVT::i64)
12270 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
12272 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
12273 assert(OpVT.is128BitVector() && "Expected an SSE type!");
12274 return DAG.getNode(ISD::BITCAST, dl, OpVT,
12275 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
12276 }
12278 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
12279 // a simple subregister reference or explicit instructions to grab
12280 // upper bits of a vector.
12281 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12282 SelectionDAG &DAG) {
12283 SDLoc dl(Op);
12284 SDValue In = Op.getOperand(0);
12285 SDValue Idx = Op.getOperand(1);
12286 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12287 MVT ResVT = Op.getSimpleValueType();
12288 MVT InVT = In.getSimpleValueType();
12290 if (Subtarget->hasFp256()) {
12291 if (ResVT.is128BitVector() &&
12292 (InVT.is256BitVector() || InVT.is512BitVector()) &&
12293 isa<ConstantSDNode>(Idx)) {
12294 return Extract128BitVector(In, IdxVal, DAG, dl);
12295 }
12296 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
12297 isa<ConstantSDNode>(Idx)) {
12298 return Extract256BitVector(In, IdxVal, DAG, dl);
12299 }
12300 }
12301 return SDValue();
12302 }
12304 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
12305 // simple superregister reference or explicit instructions to insert
12306 // the upper bits of a vector.
12307 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12308 SelectionDAG &DAG) {
12309 if (Subtarget->hasFp256()) {
12310 SDLoc dl(Op.getNode());
12311 SDValue Vec = Op.getNode()->getOperand(0);
12312 SDValue SubVec = Op.getNode()->getOperand(1);
12313 SDValue Idx = Op.getNode()->getOperand(2);
12315 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
12316 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
12317 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
12318 isa<ConstantSDNode>(Idx)) {
12319 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12320 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
12321 }
12323 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
12324 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
12325 isa<ConstantSDNode>(Idx)) {
12326 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12327 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
12328 }
12329 }
12330 return SDValue();
12331 }
12333 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
12334 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
12335 // one of the above mentioned nodes. It has to be wrapped because otherwise
12336 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
12337 // be used to form addressing mode. These wrapped nodes will be selected
12338 // into MOV32ri.
12339 SDValue
12340 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
12341 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
12343 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12344 // global base reg.
12345 unsigned char OpFlag = 0;
12346 unsigned WrapperKind = X86ISD::Wrapper;
12347 CodeModel::Model M = DAG.getTarget().getCodeModel();
12349 if (Subtarget->isPICStyleRIPRel() &&
12350 (M == CodeModel::Small || M == CodeModel::Kernel))
12351 WrapperKind = X86ISD::WrapperRIP;
12352 else if (Subtarget->isPICStyleGOT())
12353 OpFlag = X86II::MO_GOTOFF;
12354 else if (Subtarget->isPICStyleStubPIC())
12355 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12357 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
12358 CP->getAlignment(),
12359 CP->getOffset(), OpFlag);
12360 SDLoc DL(CP);
12361 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12362 // With PIC, the address is actually $g + Offset.
12363 if (OpFlag) {
12364 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12365 DAG.getNode(X86ISD::GlobalBaseReg,
12366 SDLoc(), getPointerTy()),
12367 Result);
12368 }
12370 return Result;
12371 }
12373 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
12374 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
12376 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12377 // global base reg.
12378 unsigned char OpFlag = 0;
12379 unsigned WrapperKind = X86ISD::Wrapper;
12380 CodeModel::Model M = DAG.getTarget().getCodeModel();
12382 if (Subtarget->isPICStyleRIPRel() &&
12383 (M == CodeModel::Small || M == CodeModel::Kernel))
12384 WrapperKind = X86ISD::WrapperRIP;
12385 else if (Subtarget->isPICStyleGOT())
12386 OpFlag = X86II::MO_GOTOFF;
12387 else if (Subtarget->isPICStyleStubPIC())
12388 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12390 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
12391 OpFlag);
12392 SDLoc DL(JT);
12393 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12395 // With PIC, the address is actually $g + Offset.
12396 if (OpFlag)
12397 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12398 DAG.getNode(X86ISD::GlobalBaseReg,
12399 SDLoc(), getPointerTy()),
12400 Result);
12402 return Result;
12403 }
12405 SDValue
12406 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
12407 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
12409 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12410 // global base reg.
12411 unsigned char OpFlag = 0;
12412 unsigned WrapperKind = X86ISD::Wrapper;
12413 CodeModel::Model M = DAG.getTarget().getCodeModel();
12415 if (Subtarget->isPICStyleRIPRel() &&
12416 (M == CodeModel::Small || M == CodeModel::Kernel)) {
12417 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
12418 OpFlag = X86II::MO_GOTPCREL;
12419 WrapperKind = X86ISD::WrapperRIP;
12420 } else if (Subtarget->isPICStyleGOT()) {
12421 OpFlag = X86II::MO_GOT;
12422 } else if (Subtarget->isPICStyleStubPIC()) {
12423 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
12424 } else if (Subtarget->isPICStyleStubNoDynamic()) {
12425 OpFlag = X86II::MO_DARWIN_NONLAZY;
12426 }
12428 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
12430 SDLoc DL(Op);
12431 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12433 // With PIC, the address is actually $g + Offset.
12434 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
12435 !Subtarget->is64Bit()) {
12436 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12437 DAG.getNode(X86ISD::GlobalBaseReg,
12438 SDLoc(), getPointerTy()),
12439 Result);
12440 }
12442 // For symbols that require a load from a stub to get the address, emit the
12443 // load.
12444 if (isGlobalStubReference(OpFlag))
12445 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
12446 MachinePointerInfo::getGOT(), false, false, false, 0);
12448 return Result;
12449 }
12451 SDValue
12452 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
12453 // Create the TargetBlockAddressAddress node.
12454 unsigned char OpFlags =
12455 Subtarget->ClassifyBlockAddressReference();
12456 CodeModel::Model M = DAG.getTarget().getCodeModel();
12457 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
12458 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
12459 SDLoc dl(Op);
12460 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
12461 OpFlags);
12463 if (Subtarget->isPICStyleRIPRel() &&
12464 (M == CodeModel::Small || M == CodeModel::Kernel))
12465 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12466 else
12467 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12469 // With PIC, the address is actually $g + Offset.
12470 if (isGlobalRelativeToPICBase(OpFlags)) {
12471 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12472 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12473 Result);
12474 }
12476 return Result;
12477 }
12479 SDValue
12480 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
12481 int64_t Offset, SelectionDAG &DAG) const {
12482 // Create the TargetGlobalAddress node, folding in the constant
12483 // offset if it is legal.
12484 unsigned char OpFlags =
12485 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
12486 CodeModel::Model M = DAG.getTarget().getCodeModel();
12487 SDValue Result;
12488 if (OpFlags == X86II::MO_NO_FLAG &&
12489 X86::isOffsetSuitableForCodeModel(Offset, M)) {
12490 // A direct static reference to a global.
12491 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
12492 Offset = 0;
12493 } else {
12494 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
12495 }
12497 if (Subtarget->isPICStyleRIPRel() &&
12498 (M == CodeModel::Small || M == CodeModel::Kernel))
12499 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12500 else
12501 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12503 // With PIC, the address is actually $g + Offset.
12504 if (isGlobalRelativeToPICBase(OpFlags)) {
12505 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12506 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12507 Result);
12508 }
12510 // For globals that require a load from a stub to get the address, emit the
12511 // load.
12512 if (isGlobalStubReference(OpFlags))
12513 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
12514 MachinePointerInfo::getGOT(), false, false, false, 0);
12516 // If there was a non-zero offset that we didn't fold, create an explicit
12517 // addition for it.
12518 if (Offset != 0)
12519 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
12520 DAG.getConstant(Offset, getPointerTy()));
12522 return Result;
12523 }
12525 SDValue
12526 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
12527 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
12528 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
12529 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
12530 }
12532 static SDValue
12533 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
12534 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
12535 unsigned char OperandFlags, bool LocalDynamic = false) {
12536 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12537 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12538 SDLoc dl(GA);
12539 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12540 GA->getValueType(0),
12541 GA->getOffset(),
12542 OperandFlags);
12544 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
12545 : X86ISD::TLSADDR;
12547 if (InFlag) {
12548 SDValue Ops[] = { Chain, TGA, *InFlag };
12549 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12550 } else {
12551 SDValue Ops[] = { Chain, TGA };
12552 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12553 }
12555 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
12556 MFI->setAdjustsStack(true);
12558 SDValue Flag = Chain.getValue(1);
12559 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
12560 }
12562 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
12563 static SDValue
12564 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12565 const EVT PtrVT) {
12566 SDValue InFlag;
12567 SDLoc dl(GA); // ? function entry point might be better
12568 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12569 DAG.getNode(X86ISD::GlobalBaseReg,
12570 SDLoc(), PtrVT), InFlag);
12571 InFlag = Chain.getValue(1);
12573 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
12574 }
12576 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
12577 static SDValue
12578 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12579 const EVT PtrVT) {
12580 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
12581 X86::RAX, X86II::MO_TLSGD);
12582 }
12584 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12585 SelectionDAG &DAG,
12586 const EVT PtrVT,
12587 bool is64Bit) {
12588 SDLoc dl(GA);
12590 // Get the start address of the TLS block for this module.
12591 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
12592 .getInfo<X86MachineFunctionInfo>();
12593 MFI->incNumLocalDynamicTLSAccesses();
12595 SDValue Base;
12596 if (is64Bit) {
12597 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
12598 X86II::MO_TLSLD, /*LocalDynamic=*/true);
12599 } else {
12600 SDValue InFlag;
12601 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12602 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12603 InFlag = Chain.getValue(1);
12604 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12605 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12606 }
12608 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12609 // of Base.
12611 // Build x@dtpoff.
12612 unsigned char OperandFlags = X86II::MO_DTPOFF;
12613 unsigned WrapperKind = X86ISD::Wrapper;
12614 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12615 GA->getValueType(0),
12616 GA->getOffset(), OperandFlags);
12617 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12619 // Add x@dtpoff with the base.
12620 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12621 }
12623 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12624 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12625 const EVT PtrVT, TLSModel::Model model,
12626 bool is64Bit, bool isPIC) {
12627 SDLoc dl(GA);
12629 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12630 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12631 is64Bit ? 257 : 256));
12633 SDValue ThreadPointer =
12634 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
12635 MachinePointerInfo(Ptr), false, false, false, 0);
12637 unsigned char OperandFlags = 0;
12638 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12639 // initialexec.
12640 unsigned WrapperKind = X86ISD::Wrapper;
12641 if (model == TLSModel::LocalExec) {
12642 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12643 } else if (model == TLSModel::InitialExec) {
12644 if (is64Bit) {
12645 OperandFlags = X86II::MO_GOTTPOFF;
12646 WrapperKind = X86ISD::WrapperRIP;
12647 } else {
12648 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12649 }
12650 } else {
12651 llvm_unreachable("Unexpected model");
12652 }
12654 // emit "addl x@ntpoff,%eax" (local exec)
12655 // or "addl x@indntpoff,%eax" (initial exec)
12656 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12657 SDValue TGA =
12658 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12659 GA->getOffset(), OperandFlags);
12660 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12662 if (model == TLSModel::InitialExec) {
12663 if (isPIC && !is64Bit) {
12664 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12665 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12666 Offset);
12667 }
12669 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12670 MachinePointerInfo::getGOT(), false, false, false, 0);
12671 }
12673 // The address of the thread local variable is the add of the thread
12674 // pointer with the offset of the variable.
12675 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12676 }
12678 SDValue
12679 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12681 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12682 const GlobalValue *GV = GA->getGlobal();
12684 if (Subtarget->isTargetELF()) {
12685 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12687 switch (model) {
12688 case TLSModel::GeneralDynamic:
12689 if (Subtarget->is64Bit())
12690 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
12691 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
12692 case TLSModel::LocalDynamic:
12693 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
12694 Subtarget->is64Bit());
12695 case TLSModel::InitialExec:
12696 case TLSModel::LocalExec:
12697 return LowerToTLSExecModel(
12698 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
12699 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
12700 }
12701 llvm_unreachable("Unknown TLS model.");
12702 }
12704 if (Subtarget->isTargetDarwin()) {
12705 // Darwin only has one model of TLS. Lower to that.
12706 unsigned char OpFlag = 0;
12707 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12708 X86ISD::WrapperRIP : X86ISD::Wrapper;
12710 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12711 // global base reg.
12712 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12713 !Subtarget->is64Bit();
12714 if (PIC32)
12715 OpFlag = X86II::MO_TLVP_PIC_BASE;
12716 else
12717 OpFlag = X86II::MO_TLVP;
12718 SDLoc DL(Op);
12719 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12720 GA->getValueType(0),
12721 GA->getOffset(), OpFlag);
12722 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12724 // With PIC32, the address is actually $g + Offset.
12725 if (PIC32)
12726 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12727 DAG.getNode(X86ISD::GlobalBaseReg,
12728 SDLoc(), getPointerTy()),
12729 Offset);
12731 // Lowering the machine isd will make sure everything is in the right
12732 // location.
12733 SDValue Chain = DAG.getEntryNode();
12734 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12735 SDValue Args[] = { Chain, Offset };
12736 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12738 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12739 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12740 MFI->setAdjustsStack(true);
12742 // And our return value (tls address) is in the standard call return value
12743 // location.
12744 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12745 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
12746 Chain.getValue(1));
12747 }
12749 if (Subtarget->isTargetKnownWindowsMSVC() ||
12750 Subtarget->isTargetWindowsGNU()) {
12751 // Just use the implicit TLS architecture
12752 // Need to generate someting similar to:
12753 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12754 // ; from TEB
12755 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12756 // mov rcx, qword [rdx+rcx*8]
12757 // mov eax, .tls$:tlsvar
12758 // [rax+rcx] contains the address
12759 // Windows 64bit: gs:0x58
12760 // Windows 32bit: fs:__tls_array
12762 SDLoc dl(GA);
12763 SDValue Chain = DAG.getEntryNode();
12765 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12766 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12767 // use its literal value of 0x2C.
12768 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12769 ? Type::getInt8PtrTy(*DAG.getContext(),
12770 256)
12771 : Type::getInt32PtrTy(*DAG.getContext(),
12772 257));
12774 SDValue TlsArray =
12775 Subtarget->is64Bit()
12776 ? DAG.getIntPtrConstant(0x58)
12777 : (Subtarget->isTargetWindowsGNU()
12778 ? DAG.getIntPtrConstant(0x2C)
12779 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
12781 SDValue ThreadPointer =
12782 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
12783 MachinePointerInfo(Ptr), false, false, false, 0);
12785 // Load the _tls_index variable
12786 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
12787 if (Subtarget->is64Bit())
12788 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
12789 IDX, MachinePointerInfo(), MVT::i32,
12790 false, false, false, 0);
12791 else
12792 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
12793 false, false, false, 0);
12795 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
12796 getPointerTy());
12797 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
12799 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
12800 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
12801 false, false, false, 0);
12803 // Get the offset of start of .tls section
12804 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12805 GA->getValueType(0),
12806 GA->getOffset(), X86II::MO_SECREL);
12807 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
12809 // The address of the thread local variable is the add of the thread
12810 // pointer with the offset of the variable.
12811 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
12812 }
12814 llvm_unreachable("TLS not implemented for this target.");
12815 }
12817 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12818 /// and take a 2 x i32 value to shift plus a shift amount.
12819 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12820 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12821 MVT VT = Op.getSimpleValueType();
12822 unsigned VTBits = VT.getSizeInBits();
12823 SDLoc dl(Op);
12824 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12825 SDValue ShOpLo = Op.getOperand(0);
12826 SDValue ShOpHi = Op.getOperand(1);
12827 SDValue ShAmt = Op.getOperand(2);
12828 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12829 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12830 // during isel.
12831 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12832 DAG.getConstant(VTBits - 1, MVT::i8));
12833 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12834 DAG.getConstant(VTBits - 1, MVT::i8))
12835 : DAG.getConstant(0, VT);
12837 SDValue Tmp2, Tmp3;
12838 if (Op.getOpcode() == ISD::SHL_PARTS) {
12839 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12840 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12841 } else {
12842 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12843 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12844 }
12846 // If the shift amount is larger or equal than the width of a part we can't
12847 // rely on the results of shld/shrd. Insert a test and select the appropriate
12848 // values for large shift amounts.
12849 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12850 DAG.getConstant(VTBits, MVT::i8));
12851 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12852 AndNode, DAG.getConstant(0, MVT::i8));
12854 SDValue Hi, Lo;
12855 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
12856 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12857 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12859 if (Op.getOpcode() == ISD::SHL_PARTS) {
12860 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12861 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12862 } else {
12863 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12864 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12865 }
12867 SDValue Ops[2] = { Lo, Hi };
12868 return DAG.getMergeValues(Ops, dl);
12869 }
12871 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12872 SelectionDAG &DAG) const {
12873 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
12875 if (SrcVT.isVector())
12876 return SDValue();
12878 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12879 "Unknown SINT_TO_FP to lower!");
12881 // These are really Legal; return the operand so the caller accepts it as
12882 // Legal.
12883 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12884 return Op;
12885 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12886 Subtarget->is64Bit()) {
12887 return Op;
12888 }
12890 SDLoc dl(Op);
12891 unsigned Size = SrcVT.getSizeInBits()/8;
12892 MachineFunction &MF = DAG.getMachineFunction();
12893 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12894 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12895 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12896 StackSlot,
12897 MachinePointerInfo::getFixedStack(SSFI),
12898 false, false, 0);
12899 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12900 }
12902 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12903 SDValue StackSlot,
12904 SelectionDAG &DAG) const {
12905 // Build the FILD
12906 SDLoc DL(Op);
12907 SDVTList Tys;
12908 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12909 if (useSSE)
12910 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12911 else
12912 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12914 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12916 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12917 MachineMemOperand *MMO;
12918 if (FI) {
12919 int SSFI = FI->getIndex();
12920 MMO =
12921 DAG.getMachineFunction()
12922 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12923 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12924 } else {
12925 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12926 StackSlot = StackSlot.getOperand(1);
12927 }
12928 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12929 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12930 X86ISD::FILD, DL,
12931 Tys, Ops, SrcVT, MMO);
12933 if (useSSE) {
12934 Chain = Result.getValue(1);
12935 SDValue InFlag = Result.getValue(2);
12937 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12938 // shouldn't be necessary except that RFP cannot be live across
12939 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12940 MachineFunction &MF = DAG.getMachineFunction();
12941 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12942 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12943 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12944 Tys = DAG.getVTList(MVT::Other);
12945 SDValue Ops[] = {
12946 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12947 };
12948 MachineMemOperand *MMO =
12949 DAG.getMachineFunction()
12950 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12951 MachineMemOperand::MOStore, SSFISize, SSFISize);
12953 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12954 Ops, Op.getValueType(), MMO);
12955 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
12956 MachinePointerInfo::getFixedStack(SSFI),
12957 false, false, false, 0);
12958 }
12960 return Result;
12961 }
12963 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12964 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12965 SelectionDAG &DAG) const {
12966 // This algorithm is not obvious. Here it is what we're trying to output:
12967 /*
12968 movq %rax, %xmm0
12969 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12970 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12971 #ifdef __SSE3__
12972 haddpd %xmm0, %xmm0
12973 #else
12974 pshufd $0x4e, %xmm0, %xmm1
12975 addpd %xmm1, %xmm0
12976 #endif
12977 */
12979 SDLoc dl(Op);
12980 LLVMContext *Context = DAG.getContext();
12982 // Build some magic constants.
12983 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12984 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12985 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
12987 SmallVector<Constant*,2> CV1;
12988 CV1.push_back(
12989 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12990 APInt(64, 0x4330000000000000ULL))));
12991 CV1.push_back(
12992 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12993 APInt(64, 0x4530000000000000ULL))));
12994 Constant *C1 = ConstantVector::get(CV1);
12995 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
12997 // Load the 64-bit value into an XMM register.
12998 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12999 Op.getOperand(0));
13000 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
13001 MachinePointerInfo::getConstantPool(),
13002 false, false, false, 16);
13003 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
13004 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
13005 CLod0);
13007 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
13008 MachinePointerInfo::getConstantPool(),
13009 false, false, false, 16);
13010 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
13011 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
13012 SDValue Result;
13014 if (Subtarget->hasSSE3()) {
13015 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
13016 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
13017 } else {
13018 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
13019 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
13020 S2F, 0x4E, DAG);
13021 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
13022 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
13023 Sub);
13024 }
13026 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
13027 DAG.getIntPtrConstant(0));
13028 }
13030 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
13031 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
13032 SelectionDAG &DAG) const {
13033 SDLoc dl(Op);
13034 // FP constant to bias correct the final result.
13035 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13036 MVT::f64);
13038 // Load the 32-bit value into an XMM register.
13039 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
13040 Op.getOperand(0));
13042 // Zero out the upper parts of the register.
13043 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
13045 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13046 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
13047 DAG.getIntPtrConstant(0));
13049 // Or the load with the bias.
13050 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
13051 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13052 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13053 MVT::v2f64, Load)),
13054 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13055 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13056 MVT::v2f64, Bias)));
13057 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13058 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
13059 DAG.getIntPtrConstant(0));
13061 // Subtract the bias.
13062 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
13064 // Handle final rounding.
13065 EVT DestVT = Op.getValueType();
13067 if (DestVT.bitsLT(MVT::f64))
13068 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
13069 DAG.getIntPtrConstant(0));
13070 if (DestVT.bitsGT(MVT::f64))
13071 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
13073 // Handle final rounding.
13074 return Sub;
13075 }
13077 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
13078 SelectionDAG &DAG) const {
13079 SDValue N0 = Op.getOperand(0);
13080 MVT SVT = N0.getSimpleValueType();
13081 SDLoc dl(Op);
13083 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
13084 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
13085 "Custom UINT_TO_FP is not supported!");
13087 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
13088 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13089 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
13090 }
13092 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
13093 SelectionDAG &DAG) const {
13094 SDValue N0 = Op.getOperand(0);
13095 SDLoc dl(Op);
13097 if (Op.getValueType().isVector())
13098 return lowerUINT_TO_FP_vec(Op, DAG);
13100 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
13101 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
13102 // the optimization here.
13103 if (DAG.SignBitIsZero(N0))
13104 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
13106 MVT SrcVT = N0.getSimpleValueType();
13107 MVT DstVT = Op.getSimpleValueType();
13108 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
13109 return LowerUINT_TO_FP_i64(Op, DAG);
13110 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
13111 return LowerUINT_TO_FP_i32(Op, DAG);
13112 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
13113 return SDValue();
13115 // Make a 64-bit buffer, and use it to build an FILD.
13116 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
13117 if (SrcVT == MVT::i32) {
13118 SDValue WordOff = DAG.getConstant(4, getPointerTy());
13119 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
13120 getPointerTy(), StackSlot, WordOff);
13121 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13122 StackSlot, MachinePointerInfo(),
13123 false, false, 0);
13124 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
13125 OffsetSlot, MachinePointerInfo(),
13126 false, false, 0);
13127 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
13128 return Fild;
13129 }
13131 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
13132 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13133 StackSlot, MachinePointerInfo(),
13134 false, false, 0);
13135 // For i64 source, we need to add the appropriate power of 2 if the input
13136 // was negative. This is the same as the optimization in
13137 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
13138 // we must be careful to do the computation in x87 extended precision, not
13139 // in SSE. (The generic code can't know it's OK to do this, or how to.)
13140 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
13141 MachineMemOperand *MMO =
13142 DAG.getMachineFunction()
13143 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13144 MachineMemOperand::MOLoad, 8, 8);
13146 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
13147 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
13148 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
13149 MVT::i64, MMO);
13151 APInt FF(32, 0x5F800000ULL);
13153 // Check whether the sign bit is set.
13154 SDValue SignSet = DAG.getSetCC(dl,
13155 getSetCCResultType(*DAG.getContext(), MVT::i64),
13156 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
13157 ISD::SETLT);
13159 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
13160 SDValue FudgePtr = DAG.getConstantPool(
13161 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
13162 getPointerTy());
13164 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
13165 SDValue Zero = DAG.getIntPtrConstant(0);
13166 SDValue Four = DAG.getIntPtrConstant(4);
13167 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
13168 Zero, Four);
13169 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
13171 // Load the value out, extending it from f32 to f80.
13172 // FIXME: Avoid the extend by constructing the right constant pool?
13173 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
13174 FudgePtr, MachinePointerInfo::getConstantPool(),
13175 MVT::f32, false, false, false, 4);
13176 // Extend everything to 80 bits to force it to be done on x87.
13177 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
13178 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
13179 }
13181 std::pair<SDValue,SDValue>
13182 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
13183 bool IsSigned, bool IsReplace) const {
13184 SDLoc DL(Op);
13186 EVT DstTy = Op.getValueType();
13188 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
13189 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
13190 DstTy = MVT::i64;
13191 }
13193 assert(DstTy.getSimpleVT() <= MVT::i64 &&
13194 DstTy.getSimpleVT() >= MVT::i16 &&
13195 "Unknown FP_TO_INT to lower!");
13197 // These are really Legal.
13198 if (DstTy == MVT::i32 &&
13199 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13200 return std::make_pair(SDValue(), SDValue());
13201 if (Subtarget->is64Bit() &&
13202 DstTy == MVT::i64 &&
13203 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13204 return std::make_pair(SDValue(), SDValue());
13206 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
13207 // stack slot, or into the FTOL runtime function.
13208 MachineFunction &MF = DAG.getMachineFunction();
13209 unsigned MemSize = DstTy.getSizeInBits()/8;
13210 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13211 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13213 unsigned Opc;
13214 if (!IsSigned && isIntegerTypeFTOL(DstTy))
13215 Opc = X86ISD::WIN_FTOL;
13216 else
13217 switch (DstTy.getSimpleVT().SimpleTy) {
13218 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
13219 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
13220 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
13221 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
13222 }
13224 SDValue Chain = DAG.getEntryNode();
13225 SDValue Value = Op.getOperand(0);
13226 EVT TheVT = Op.getOperand(0).getValueType();
13227 // FIXME This causes a redundant load/store if the SSE-class value is already
13228 // in memory, such as if it is on the callstack.
13229 if (isScalarFPTypeInSSEReg(TheVT)) {
13230 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
13231 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
13232 MachinePointerInfo::getFixedStack(SSFI),
13233 false, false, 0);
13234 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
13235 SDValue Ops[] = {
13236 Chain, StackSlot, DAG.getValueType(TheVT)
13237 };
13239 MachineMemOperand *MMO =
13240 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13241 MachineMemOperand::MOLoad, MemSize, MemSize);
13242 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
13243 Chain = Value.getValue(1);
13244 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13245 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13246 }
13248 MachineMemOperand *MMO =
13249 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13250 MachineMemOperand::MOStore, MemSize, MemSize);
13252 if (Opc != X86ISD::WIN_FTOL) {
13253 // Build the FP_TO_INT*_IN_MEM
13254 SDValue Ops[] = { Chain, Value, StackSlot };
13255 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13256 Ops, DstTy, MMO);
13257 return std::make_pair(FIST, StackSlot);
13258 } else {
13259 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
13260 DAG.getVTList(MVT::Other, MVT::Glue),
13261 Chain, Value);
13262 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
13263 MVT::i32, ftol.getValue(1));
13264 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
13265 MVT::i32, eax.getValue(2));
13266 SDValue Ops[] = { eax, edx };
13267 SDValue pair = IsReplace
13268 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
13269 : DAG.getMergeValues(Ops, DL);
13270 return std::make_pair(pair, SDValue());
13271 }
13272 }
13274 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
13275 const X86Subtarget *Subtarget) {
13276 MVT VT = Op->getSimpleValueType(0);
13277 SDValue In = Op->getOperand(0);
13278 MVT InVT = In.getSimpleValueType();
13279 SDLoc dl(Op);
13281 // Optimize vectors in AVX mode:
13282 //
13283 // v8i16 -> v8i32
13284 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
13285 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
13286 // Concat upper and lower parts.
13287 //
13288 // v4i32 -> v4i64
13289 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
13290 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
13291 // Concat upper and lower parts.
13292 //
13294 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
13295 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
13296 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
13297 return SDValue();
13299 if (Subtarget->hasInt256())
13300 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
13302 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
13303 SDValue Undef = DAG.getUNDEF(InVT);
13304 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
13305 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13306 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13308 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
13309 VT.getVectorNumElements()/2);
13311 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
13312 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
13314 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13315 }
13317 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
13318 SelectionDAG &DAG) {
13319 MVT VT = Op->getSimpleValueType(0);
13320 SDValue In = Op->getOperand(0);
13321 MVT InVT = In.getSimpleValueType();
13322 SDLoc DL(Op);
13323 unsigned int NumElts = VT.getVectorNumElements();
13324 if (NumElts != 8 && NumElts != 16)
13325 return SDValue();
13327 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13328 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
13330 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
13331 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13332 // Now we have only mask extension
13333 assert(InVT.getVectorElementType() == MVT::i1);
13334 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
13335 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
13336 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
13337 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13338 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
13339 MachinePointerInfo::getConstantPool(),
13340 false, false, false, Alignment);
13342 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
13343 if (VT.is512BitVector())
13344 return Brcst;
13345 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
13346 }
13348 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13349 SelectionDAG &DAG) {
13350 if (Subtarget->hasFp256()) {
13351 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
13352 if (Res.getNode())
13353 return Res;
13354 }
13356 return SDValue();
13357 }
13359 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13360 SelectionDAG &DAG) {
13361 SDLoc DL(Op);
13362 MVT VT = Op.getSimpleValueType();
13363 SDValue In = Op.getOperand(0);
13364 MVT SVT = In.getSimpleValueType();
13366 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
13367 return LowerZERO_EXTEND_AVX512(Op, DAG);
13369 if (Subtarget->hasFp256()) {
13370 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
13371 if (Res.getNode())
13372 return Res;
13373 }
13375 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
13376 VT.getVectorNumElements() != SVT.getVectorNumElements());
13377 return SDValue();
13378 }
13380 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
13381 SDLoc DL(Op);
13382 MVT VT = Op.getSimpleValueType();
13383 SDValue In = Op.getOperand(0);
13384 MVT InVT = In.getSimpleValueType();
13386 if (VT == MVT::i1) {
13387 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
13388 "Invalid scalar TRUNCATE operation");
13389 if (InVT.getSizeInBits() >= 32)
13390 return SDValue();
13391 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
13392 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
13393 }
13394 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
13395 "Invalid TRUNCATE operation");
13397 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
13398 if (VT.getVectorElementType().getSizeInBits() >=8)
13399 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13401 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13402 unsigned NumElts = InVT.getVectorNumElements();
13403 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
13404 if (InVT.getSizeInBits() < 512) {
13405 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
13406 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13407 InVT = ExtVT;
13408 }
13410 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
13411 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
13412 SDValue CP = DAG.getConstantPool(C, getPointerTy());
13413 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13414 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
13415 MachinePointerInfo::getConstantPool(),
13416 false, false, false, Alignment);
13417 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
13418 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
13419 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
13420 }
13422 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13423 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13424 if (Subtarget->hasInt256()) {
13425 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13426 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
13427 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13428 ShufMask);
13429 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13430 DAG.getIntPtrConstant(0));
13431 }
13433 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13434 DAG.getIntPtrConstant(0));
13435 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13436 DAG.getIntPtrConstant(2));
13437 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
13438 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
13439 static const int ShufMask[] = {0, 2, 4, 6};
13440 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13441 }
13443 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13444 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13445 if (Subtarget->hasInt256()) {
13446 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
13448 SmallVector<SDValue,32> pshufbMask;
13449 for (unsigned i = 0; i < 2; ++i) {
13450 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
13451 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
13452 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
13453 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
13454 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
13455 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
13456 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
13457 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
13458 for (unsigned j = 0; j < 8; ++j)
13459 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
13460 }
13461 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13462 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13463 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
13465 static const int ShufMask[] = {0, 2, -1, -1};
13466 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13467 &ShufMask[0]);
13468 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13469 DAG.getIntPtrConstant(0));
13470 return DAG.getNode(ISD::BITCAST, DL, VT, In);
13471 }
13473 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13474 DAG.getIntPtrConstant(0));
13476 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13477 DAG.getIntPtrConstant(4));
13479 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
13480 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
13482 // The PSHUFB mask:
13483 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13484 -1, -1, -1, -1, -1, -1, -1, -1};
13486 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13487 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13488 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13490 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
13491 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
13493 // The MOVLHPS Mask:
13494 static const int ShufMask2[] = {0, 1, 4, 5};
13495 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13496 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
13497 }
13499 // Handle truncation of V256 to V128 using shuffles.
13500 if (!VT.is128BitVector() || !InVT.is256BitVector())
13501 return SDValue();
13503 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13505 unsigned NumElems = VT.getVectorNumElements();
13506 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13508 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13509 // Prepare truncation shuffle mask
13510 for (unsigned i = 0; i != NumElems; ++i)
13511 MaskVec[i] = i * 2;
13512 SDValue V = DAG.getVectorShuffle(NVT, DL,
13513 DAG.getNode(ISD::BITCAST, DL, NVT, In),
13514 DAG.getUNDEF(NVT), &MaskVec[0]);
13515 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13516 DAG.getIntPtrConstant(0));
13517 }
13519 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13520 SelectionDAG &DAG) const {
13521 assert(!Op.getSimpleValueType().isVector());
13523 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13524 /*IsSigned=*/ true, /*IsReplace=*/ false);
13525 SDValue FIST = Vals.first, StackSlot = Vals.second;
13526 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13527 if (!FIST.getNode()) return Op;
13529 if (StackSlot.getNode())
13530 // Load the result.
13531 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13532 FIST, StackSlot, MachinePointerInfo(),
13533 false, false, false, 0);
13535 // The node is the result.
13536 return FIST;
13537 }
13539 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13540 SelectionDAG &DAG) const {
13541 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13542 /*IsSigned=*/ false, /*IsReplace=*/ false);
13543 SDValue FIST = Vals.first, StackSlot = Vals.second;
13544 assert(FIST.getNode() && "Unexpected failure");
13546 if (StackSlot.getNode())
13547 // Load the result.
13548 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13549 FIST, StackSlot, MachinePointerInfo(),
13550 false, false, false, 0);
13552 // The node is the result.
13553 return FIST;
13554 }
13556 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13557 SDLoc DL(Op);
13558 MVT VT = Op.getSimpleValueType();
13559 SDValue In = Op.getOperand(0);
13560 MVT SVT = In.getSimpleValueType();
13562 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13564 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13565 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13566 In, DAG.getUNDEF(SVT)));
13567 }
13569 // The only differences between FABS and FNEG are the mask and the logic op.
13570 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13571 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13572 "Wrong opcode for lowering FABS or FNEG.");
13574 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13575 SDLoc dl(Op);
13576 MVT VT = Op.getSimpleValueType();
13577 // Assume scalar op for initialization; update for vector if needed.
13578 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
13579 // generate a 16-byte vector constant and logic op even for the scalar case.
13580 // Using a 16-byte mask allows folding the load of the mask with
13581 // the logic op, so it can save (~4 bytes) on code size.
13582 MVT EltVT = VT;
13583 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
13584 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13585 // decide if we should generate a 16-byte constant mask when we only need 4 or
13586 // 8 bytes for the scalar case.
13587 if (VT.isVector()) {
13588 EltVT = VT.getVectorElementType();
13589 NumElts = VT.getVectorNumElements();
13590 }
13592 unsigned EltBits = EltVT.getSizeInBits();
13593 LLVMContext *Context = DAG.getContext();
13594 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13595 APInt MaskElt =
13596 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13597 Constant *C = ConstantInt::get(*Context, MaskElt);
13598 C = ConstantVector::getSplat(NumElts, C);
13599 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13600 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
13601 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13602 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
13603 MachinePointerInfo::getConstantPool(),
13604 false, false, false, Alignment);
13606 if (VT.isVector()) {
13607 // For a vector, cast operands to a vector type, perform the logic op,
13608 // and cast the result back to the original value type.
13609 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
13610 SDValue Op0Casted = DAG.getNode(ISD::BITCAST, dl, VecVT, Op.getOperand(0));
13611 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
13612 unsigned LogicOp = IsFABS ? ISD::AND : ISD::XOR;
13613 return DAG.getNode(ISD::BITCAST, dl, VT,
13614 DAG.getNode(LogicOp, dl, VecVT, Op0Casted, MaskCasted));
13615 }
13616 // If not vector, then scalar.
13617 unsigned LogicOp = IsFABS ? X86ISD::FAND : X86ISD::FXOR;
13618 return DAG.getNode(LogicOp, dl, VT, Op.getOperand(0), Mask);
13619 }
13621 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13622 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13623 LLVMContext *Context = DAG.getContext();
13624 SDValue Op0 = Op.getOperand(0);
13625 SDValue Op1 = Op.getOperand(1);
13626 SDLoc dl(Op);
13627 MVT VT = Op.getSimpleValueType();
13628 MVT SrcVT = Op1.getSimpleValueType();
13630 // If second operand is smaller, extend it first.
13631 if (SrcVT.bitsLT(VT)) {
13632 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13633 SrcVT = VT;
13634 }
13635 // And if it is bigger, shrink it first.
13636 if (SrcVT.bitsGT(VT)) {
13637 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
13638 SrcVT = VT;
13639 }
13641 // At this point the operands and the result should have the same
13642 // type, and that won't be f80 since that is not custom lowered.
13644 // First get the sign bit of second operand.
13645 SmallVector<Constant*,4> CV;
13646 if (SrcVT == MVT::f64) {
13647 const fltSemantics &Sem = APFloat::IEEEdouble;
13648 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
13649 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
13650 } else {
13651 const fltSemantics &Sem = APFloat::IEEEsingle;
13652 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
13653 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13654 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13655 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13656 }
13657 Constant *C = ConstantVector::get(CV);
13658 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
13659 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
13660 MachinePointerInfo::getConstantPool(),
13661 false, false, false, 16);
13662 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
13664 // Shift sign bit right or left if the two operands have different types.
13665 if (SrcVT.bitsGT(VT)) {
13666 // Op0 is MVT::f32, Op1 is MVT::f64.
13667 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
13668 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
13669 DAG.getConstant(32, MVT::i32));
13670 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
13671 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
13672 DAG.getIntPtrConstant(0));
13673 }
13675 // Clear first operand sign bit.
13676 CV.clear();
13677 if (VT == MVT::f64) {
13678 const fltSemantics &Sem = APFloat::IEEEdouble;
13679 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
13680 APInt(64, ~(1ULL << 63)))));
13681 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
13682 } else {
13683 const fltSemantics &Sem = APFloat::IEEEsingle;
13684 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
13685 APInt(32, ~(1U << 31)))));
13686 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13687 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13688 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13689 }
13690 C = ConstantVector::get(CV);
13691 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
13692 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
13693 MachinePointerInfo::getConstantPool(),
13694 false, false, false, 16);
13695 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
13697 // Or the value with the sign bit.
13698 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
13699 }
13701 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13702 SDValue N0 = Op.getOperand(0);
13703 SDLoc dl(Op);
13704 MVT VT = Op.getSimpleValueType();
13706 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13707 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13708 DAG.getConstant(1, VT));
13709 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
13710 }
13712 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
13713 //
13714 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13715 SelectionDAG &DAG) {
13716 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13718 if (!Subtarget->hasSSE41())
13719 return SDValue();
13721 if (!Op->hasOneUse())
13722 return SDValue();
13724 SDNode *N = Op.getNode();
13725 SDLoc DL(N);
13727 SmallVector<SDValue, 8> Opnds;
13728 DenseMap<SDValue, unsigned> VecInMap;
13729 SmallVector<SDValue, 8> VecIns;
13730 EVT VT = MVT::Other;
13732 // Recognize a special case where a vector is casted into wide integer to
13733 // test all 0s.
13734 Opnds.push_back(N->getOperand(0));
13735 Opnds.push_back(N->getOperand(1));
13737 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13738 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13739 // BFS traverse all OR'd operands.
13740 if (I->getOpcode() == ISD::OR) {
13741 Opnds.push_back(I->getOperand(0));
13742 Opnds.push_back(I->getOperand(1));
13743 // Re-evaluate the number of nodes to be traversed.
13744 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13745 continue;
13746 }
13748 // Quit if a non-EXTRACT_VECTOR_ELT
13749 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13750 return SDValue();
13752 // Quit if without a constant index.
13753 SDValue Idx = I->getOperand(1);
13754 if (!isa<ConstantSDNode>(Idx))
13755 return SDValue();
13757 SDValue ExtractedFromVec = I->getOperand(0);
13758 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13759 if (M == VecInMap.end()) {
13760 VT = ExtractedFromVec.getValueType();
13761 // Quit if not 128/256-bit vector.
13762 if (!VT.is128BitVector() && !VT.is256BitVector())
13763 return SDValue();
13764 // Quit if not the same type.
13765 if (VecInMap.begin() != VecInMap.end() &&
13766 VT != VecInMap.begin()->first.getValueType())
13767 return SDValue();
13768 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13769 VecIns.push_back(ExtractedFromVec);
13770 }
13771 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13772 }
13774 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13775 "Not extracted from 128-/256-bit vector.");
13777 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13779 for (DenseMap<SDValue, unsigned>::const_iterator
13780 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13781 // Quit if not all elements are used.
13782 if (I->second != FullMask)
13783 return SDValue();
13784 }
13786 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13788 // Cast all vectors into TestVT for PTEST.
13789 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13790 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
13792 // If more than one full vectors are evaluated, OR them first before PTEST.
13793 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13794 // Each iteration will OR 2 nodes and append the result until there is only
13795 // 1 node left, i.e. the final OR'd value of all vectors.
13796 SDValue LHS = VecIns[Slot];
13797 SDValue RHS = VecIns[Slot + 1];
13798 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13799 }
13801 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13802 VecIns.back(), VecIns.back());
13803 }
13805 /// \brief return true if \c Op has a use that doesn't just read flags.
13806 static bool hasNonFlagsUse(SDValue Op) {
13807 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13808 ++UI) {
13809 SDNode *User = *UI;
13810 unsigned UOpNo = UI.getOperandNo();
13811 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13812 // Look pass truncate.
13813 UOpNo = User->use_begin().getOperandNo();
13814 User = *User->use_begin();
13815 }
13817 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13818 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13819 return true;
13820 }
13821 return false;
13822 }
13824 /// Emit nodes that will be selected as "test Op0,Op0", or something
13825 /// equivalent.
13826 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13827 SelectionDAG &DAG) const {
13828 if (Op.getValueType() == MVT::i1)
13829 // KORTEST instruction should be selected
13830 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13831 DAG.getConstant(0, Op.getValueType()));
13833 // CF and OF aren't always set the way we want. Determine which
13834 // of these we need.
13835 bool NeedCF = false;
13836 bool NeedOF = false;
13837 switch (X86CC) {
13838 default: break;
13839 case X86::COND_A: case X86::COND_AE:
13840 case X86::COND_B: case X86::COND_BE:
13841 NeedCF = true;
13842 break;
13843 case X86::COND_G: case X86::COND_GE:
13844 case X86::COND_L: case X86::COND_LE:
13845 case X86::COND_O: case X86::COND_NO: {
13846 // Check if we really need to set the
13847 // Overflow flag. If NoSignedWrap is present
13848 // that is not actually needed.
13849 switch (Op->getOpcode()) {
13850 case ISD::ADD:
13851 case ISD::SUB:
13852 case ISD::MUL:
13853 case ISD::SHL: {
13854 const BinaryWithFlagsSDNode *BinNode =
13855 cast<BinaryWithFlagsSDNode>(Op.getNode());
13856 if (BinNode->hasNoSignedWrap())
13857 break;
13858 }
13859 default:
13860 NeedOF = true;
13861 break;
13862 }
13863 break;
13864 }
13865 }
13866 // See if we can use the EFLAGS value from the operand instead of
13867 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13868 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13869 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13870 // Emit a CMP with 0, which is the TEST pattern.
13871 //if (Op.getValueType() == MVT::i1)
13872 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13873 // DAG.getConstant(0, MVT::i1));
13874 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13875 DAG.getConstant(0, Op.getValueType()));
13876 }
13877 unsigned Opcode = 0;
13878 unsigned NumOperands = 0;
13880 // Truncate operations may prevent the merge of the SETCC instruction
13881 // and the arithmetic instruction before it. Attempt to truncate the operands
13882 // of the arithmetic instruction and use a reduced bit-width instruction.
13883 bool NeedTruncation = false;
13884 SDValue ArithOp = Op;
13885 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13886 SDValue Arith = Op->getOperand(0);
13887 // Both the trunc and the arithmetic op need to have one user each.
13888 if (Arith->hasOneUse())
13889 switch (Arith.getOpcode()) {
13890 default: break;
13891 case ISD::ADD:
13892 case ISD::SUB:
13893 case ISD::AND:
13894 case ISD::OR:
13895 case ISD::XOR: {
13896 NeedTruncation = true;
13897 ArithOp = Arith;
13898 }
13899 }
13900 }
13902 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13903 // which may be the result of a CAST. We use the variable 'Op', which is the
13904 // non-casted variable when we check for possible users.
13905 switch (ArithOp.getOpcode()) {
13906 case ISD::ADD:
13907 // Due to an isel shortcoming, be conservative if this add is likely to be
13908 // selected as part of a load-modify-store instruction. When the root node
13909 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13910 // uses of other nodes in the match, such as the ADD in this case. This
13911 // leads to the ADD being left around and reselected, with the result being
13912 // two adds in the output. Alas, even if none our users are stores, that
13913 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13914 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13915 // climbing the DAG back to the root, and it doesn't seem to be worth the
13916 // effort.
13917 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13918 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13919 if (UI->getOpcode() != ISD::CopyToReg &&
13920 UI->getOpcode() != ISD::SETCC &&
13921 UI->getOpcode() != ISD::STORE)
13922 goto default_case;
13924 if (ConstantSDNode *C =
13925 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13926 // An add of one will be selected as an INC.
13927 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
13928 Opcode = X86ISD::INC;
13929 NumOperands = 1;
13930 break;
13931 }
13933 // An add of negative one (subtract of one) will be selected as a DEC.
13934 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
13935 Opcode = X86ISD::DEC;
13936 NumOperands = 1;
13937 break;
13938 }
13939 }
13941 // Otherwise use a regular EFLAGS-setting add.
13942 Opcode = X86ISD::ADD;
13943 NumOperands = 2;
13944 break;
13945 case ISD::SHL:
13946 case ISD::SRL:
13947 // If we have a constant logical shift that's only used in a comparison
13948 // against zero turn it into an equivalent AND. This allows turning it into
13949 // a TEST instruction later.
13950 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
13951 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
13952 EVT VT = Op.getValueType();
13953 unsigned BitWidth = VT.getSizeInBits();
13954 unsigned ShAmt = Op->getConstantOperandVal(1);
13955 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13956 break;
13957 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13958 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13959 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13960 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
13961 break;
13962 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
13963 DAG.getConstant(Mask, VT));
13964 DAG.ReplaceAllUsesWith(Op, New);
13965 Op = New;
13966 }
13967 break;
13969 case ISD::AND:
13970 // If the primary and result isn't used, don't bother using X86ISD::AND,
13971 // because a TEST instruction will be better.
13972 if (!hasNonFlagsUse(Op))
13973 break;
13974 // FALL THROUGH
13975 case ISD::SUB:
13976 case ISD::OR:
13977 case ISD::XOR:
13978 // Due to the ISEL shortcoming noted above, be conservative if this op is
13979 // likely to be selected as part of a load-modify-store instruction.
13980 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13981 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13982 if (UI->getOpcode() == ISD::STORE)
13983 goto default_case;
13985 // Otherwise use a regular EFLAGS-setting instruction.
13986 switch (ArithOp.getOpcode()) {
13987 default: llvm_unreachable("unexpected operator!");
13988 case ISD::SUB: Opcode = X86ISD::SUB; break;
13989 case ISD::XOR: Opcode = X86ISD::XOR; break;
13990 case ISD::AND: Opcode = X86ISD::AND; break;
13991 case ISD::OR: {
13992 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13993 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13994 if (EFLAGS.getNode())
13995 return EFLAGS;
13996 }
13997 Opcode = X86ISD::OR;
13998 break;
13999 }
14000 }
14002 NumOperands = 2;
14003 break;
14004 case X86ISD::ADD:
14005 case X86ISD::SUB:
14006 case X86ISD::INC:
14007 case X86ISD::DEC:
14008 case X86ISD::OR:
14009 case X86ISD::XOR:
14010 case X86ISD::AND:
14011 return SDValue(Op.getNode(), 1);
14012 default:
14013 default_case:
14014 break;
14015 }
14017 // If we found that truncation is beneficial, perform the truncation and
14018 // update 'Op'.
14019 if (NeedTruncation) {
14020 EVT VT = Op.getValueType();
14021 SDValue WideVal = Op->getOperand(0);
14022 EVT WideVT = WideVal.getValueType();
14023 unsigned ConvertedOp = 0;
14024 // Use a target machine opcode to prevent further DAGCombine
14025 // optimizations that may separate the arithmetic operations
14026 // from the setcc node.
14027 switch (WideVal.getOpcode()) {
14028 default: break;
14029 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
14030 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
14031 case ISD::AND: ConvertedOp = X86ISD::AND; break;
14032 case ISD::OR: ConvertedOp = X86ISD::OR; break;
14033 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
14034 }
14036 if (ConvertedOp) {
14037 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14038 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
14039 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
14040 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
14041 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
14042 }
14043 }
14044 }
14046 if (Opcode == 0)
14047 // Emit a CMP with 0, which is the TEST pattern.
14048 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14049 DAG.getConstant(0, Op.getValueType()));
14051 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14052 SmallVector<SDValue, 4> Ops;
14053 for (unsigned i = 0; i != NumOperands; ++i)
14054 Ops.push_back(Op.getOperand(i));
14056 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
14057 DAG.ReplaceAllUsesWith(Op, New);
14058 return SDValue(New.getNode(), 1);
14059 }
14061 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
14062 /// equivalent.
14063 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
14064 SDLoc dl, SelectionDAG &DAG) const {
14065 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
14066 if (C->getAPIntValue() == 0)
14067 return EmitTest(Op0, X86CC, dl, DAG);
14069 if (Op0.getValueType() == MVT::i1)
14070 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
14071 }
14073 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
14074 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
14075 // Do the comparison at i32 if it's smaller, besides the Atom case.
14076 // This avoids subregister aliasing issues. Keep the smaller reference
14077 // if we're optimizing for size, however, as that'll allow better folding
14078 // of memory operations.
14079 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
14080 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
14081 AttributeSet::FunctionIndex, Attribute::MinSize) &&
14082 !Subtarget->isAtom()) {
14083 unsigned ExtendOp =
14084 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
14085 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
14086 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
14087 }
14088 // Use SUB instead of CMP to enable CSE between SUB and CMP.
14089 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
14090 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
14091 Op0, Op1);
14092 return SDValue(Sub.getNode(), 1);
14093 }
14094 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
14095 }
14097 /// Convert a comparison if required by the subtarget.
14098 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
14099 SelectionDAG &DAG) const {
14100 // If the subtarget does not support the FUCOMI instruction, floating-point
14101 // comparisons have to be converted.
14102 if (Subtarget->hasCMov() ||
14103 Cmp.getOpcode() != X86ISD::CMP ||
14104 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
14105 !Cmp.getOperand(1).getValueType().isFloatingPoint())
14106 return Cmp;
14108 // The instruction selector will select an FUCOM instruction instead of
14109 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
14110 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
14111 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
14112 SDLoc dl(Cmp);
14113 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
14114 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
14115 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
14116 DAG.getConstant(8, MVT::i8));
14117 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
14118 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
14119 }
14121 static bool isAllOnes(SDValue V) {
14122 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
14123 return C && C->isAllOnesValue();
14124 }
14126 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
14127 /// if it's possible.
14128 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
14129 SDLoc dl, SelectionDAG &DAG) const {
14130 SDValue Op0 = And.getOperand(0);
14131 SDValue Op1 = And.getOperand(1);
14132 if (Op0.getOpcode() == ISD::TRUNCATE)
14133 Op0 = Op0.getOperand(0);
14134 if (Op1.getOpcode() == ISD::TRUNCATE)
14135 Op1 = Op1.getOperand(0);
14137 SDValue LHS, RHS;
14138 if (Op1.getOpcode() == ISD::SHL)
14139 std::swap(Op0, Op1);
14140 if (Op0.getOpcode() == ISD::SHL) {
14141 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
14142 if (And00C->getZExtValue() == 1) {
14143 // If we looked past a truncate, check that it's only truncating away
14144 // known zeros.
14145 unsigned BitWidth = Op0.getValueSizeInBits();
14146 unsigned AndBitWidth = And.getValueSizeInBits();
14147 if (BitWidth > AndBitWidth) {
14148 APInt Zeros, Ones;
14149 DAG.computeKnownBits(Op0, Zeros, Ones);
14150 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
14151 return SDValue();
14152 }
14153 LHS = Op1;
14154 RHS = Op0.getOperand(1);
14155 }
14156 } else if (Op1.getOpcode() == ISD::Constant) {
14157 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
14158 uint64_t AndRHSVal = AndRHS->getZExtValue();
14159 SDValue AndLHS = Op0;
14161 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
14162 LHS = AndLHS.getOperand(0);
14163 RHS = AndLHS.getOperand(1);
14164 }
14166 // Use BT if the immediate can't be encoded in a TEST instruction.
14167 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
14168 LHS = AndLHS;
14169 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
14170 }
14171 }
14173 if (LHS.getNode()) {
14174 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
14175 // instruction. Since the shift amount is in-range-or-undefined, we know
14176 // that doing a bittest on the i32 value is ok. We extend to i32 because
14177 // the encoding for the i16 version is larger than the i32 version.
14178 // Also promote i16 to i32 for performance / code size reason.
14179 if (LHS.getValueType() == MVT::i8 ||
14180 LHS.getValueType() == MVT::i16)
14181 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
14183 // If the operand types disagree, extend the shift amount to match. Since
14184 // BT ignores high bits (like shifts) we can use anyextend.
14185 if (LHS.getValueType() != RHS.getValueType())
14186 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
14188 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
14189 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
14190 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14191 DAG.getConstant(Cond, MVT::i8), BT);
14192 }
14194 return SDValue();
14195 }
14197 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
14198 /// mask CMPs.
14199 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
14200 SDValue &Op1) {
14201 unsigned SSECC;
14202 bool Swap = false;
14204 // SSE Condition code mapping:
14205 // 0 - EQ
14206 // 1 - LT
14207 // 2 - LE
14208 // 3 - UNORD
14209 // 4 - NEQ
14210 // 5 - NLT
14211 // 6 - NLE
14212 // 7 - ORD
14213 switch (SetCCOpcode) {
14214 default: llvm_unreachable("Unexpected SETCC condition");
14215 case ISD::SETOEQ:
14216 case ISD::SETEQ: SSECC = 0; break;
14217 case ISD::SETOGT:
14218 case ISD::SETGT: Swap = true; // Fallthrough
14219 case ISD::SETLT:
14220 case ISD::SETOLT: SSECC = 1; break;
14221 case ISD::SETOGE:
14222 case ISD::SETGE: Swap = true; // Fallthrough
14223 case ISD::SETLE:
14224 case ISD::SETOLE: SSECC = 2; break;
14225 case ISD::SETUO: SSECC = 3; break;
14226 case ISD::SETUNE:
14227 case ISD::SETNE: SSECC = 4; break;
14228 case ISD::SETULE: Swap = true; // Fallthrough
14229 case ISD::SETUGE: SSECC = 5; break;
14230 case ISD::SETULT: Swap = true; // Fallthrough
14231 case ISD::SETUGT: SSECC = 6; break;
14232 case ISD::SETO: SSECC = 7; break;
14233 case ISD::SETUEQ:
14234 case ISD::SETONE: SSECC = 8; break;
14235 }
14236 if (Swap)
14237 std::swap(Op0, Op1);
14239 return SSECC;
14240 }
14242 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
14243 // ones, and then concatenate the result back.
14244 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
14245 MVT VT = Op.getSimpleValueType();
14247 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
14248 "Unsupported value type for operation");
14250 unsigned NumElems = VT.getVectorNumElements();
14251 SDLoc dl(Op);
14252 SDValue CC = Op.getOperand(2);
14254 // Extract the LHS vectors
14255 SDValue LHS = Op.getOperand(0);
14256 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14257 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14259 // Extract the RHS vectors
14260 SDValue RHS = Op.getOperand(1);
14261 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14262 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14264 // Issue the operation on the smaller types and concatenate the result back
14265 MVT EltVT = VT.getVectorElementType();
14266 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14267 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14268 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
14269 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
14270 }
14272 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14273 const X86Subtarget *Subtarget) {
14274 SDValue Op0 = Op.getOperand(0);
14275 SDValue Op1 = Op.getOperand(1);
14276 SDValue CC = Op.getOperand(2);
14277 MVT VT = Op.getSimpleValueType();
14278 SDLoc dl(Op);
14280 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
14281 Op.getValueType().getScalarType() == MVT::i1 &&
14282 "Cannot set masked compare for this operation");
14284 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14285 unsigned Opc = 0;
14286 bool Unsigned = false;
14287 bool Swap = false;
14288 unsigned SSECC;
14289 switch (SetCCOpcode) {
14290 default: llvm_unreachable("Unexpected SETCC condition");
14291 case ISD::SETNE: SSECC = 4; break;
14292 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14293 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14294 case ISD::SETLT: Swap = true; //fall-through
14295 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14296 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14297 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14298 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14299 case ISD::SETULE: Unsigned = true; //fall-through
14300 case ISD::SETLE: SSECC = 2; break;
14301 }
14303 if (Swap)
14304 std::swap(Op0, Op1);
14305 if (Opc)
14306 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14307 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14308 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14309 DAG.getConstant(SSECC, MVT::i8));
14310 }
14312 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14313 /// operand \p Op1. If non-trivial (for example because it's not constant)
14314 /// return an empty value.
14315 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14316 {
14317 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14318 if (!BV)
14319 return SDValue();
14321 MVT VT = Op1.getSimpleValueType();
14322 MVT EVT = VT.getVectorElementType();
14323 unsigned n = VT.getVectorNumElements();
14324 SmallVector<SDValue, 8> ULTOp1;
14326 for (unsigned i = 0; i < n; ++i) {
14327 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14328 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
14329 return SDValue();
14331 // Avoid underflow.
14332 APInt Val = Elt->getAPIntValue();
14333 if (Val == 0)
14334 return SDValue();
14336 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
14337 }
14339 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14340 }
14342 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14343 SelectionDAG &DAG) {
14344 SDValue Op0 = Op.getOperand(0);
14345 SDValue Op1 = Op.getOperand(1);
14346 SDValue CC = Op.getOperand(2);
14347 MVT VT = Op.getSimpleValueType();
14348 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14349 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14350 SDLoc dl(Op);
14352 if (isFP) {
14353 #ifndef NDEBUG
14354 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14355 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14356 #endif
14358 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14359 unsigned Opc = X86ISD::CMPP;
14360 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14361 assert(VT.getVectorNumElements() <= 16);
14362 Opc = X86ISD::CMPM;
14363 }
14364 // In the two special cases we can't handle, emit two comparisons.
14365 if (SSECC == 8) {
14366 unsigned CC0, CC1;
14367 unsigned CombineOpc;
14368 if (SetCCOpcode == ISD::SETUEQ) {
14369 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14370 } else {
14371 assert(SetCCOpcode == ISD::SETONE);
14372 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14373 }
14375 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14376 DAG.getConstant(CC0, MVT::i8));
14377 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14378 DAG.getConstant(CC1, MVT::i8));
14379 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14380 }
14381 // Handle all other FP comparisons here.
14382 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14383 DAG.getConstant(SSECC, MVT::i8));
14384 }
14386 // Break 256-bit integer vector compare into smaller ones.
14387 if (VT.is256BitVector() && !Subtarget->hasInt256())
14388 return Lower256IntVSETCC(Op, DAG);
14390 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14391 EVT OpVT = Op1.getValueType();
14392 if (Subtarget->hasAVX512()) {
14393 if (Op1.getValueType().is512BitVector() ||
14394 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14395 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14396 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14398 // In AVX-512 architecture setcc returns mask with i1 elements,
14399 // But there is no compare instruction for i8 and i16 elements in KNL.
14400 // We are not talking about 512-bit operands in this case, these
14401 // types are illegal.
14402 if (MaskResult &&
14403 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14404 OpVT.getVectorElementType().getSizeInBits() >= 8))
14405 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14406 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14407 }
14409 // We are handling one of the integer comparisons here. Since SSE only has
14410 // GT and EQ comparisons for integer, swapping operands and multiple
14411 // operations may be required for some comparisons.
14412 unsigned Opc;
14413 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14414 bool Subus = false;
14416 switch (SetCCOpcode) {
14417 default: llvm_unreachable("Unexpected SETCC condition");
14418 case ISD::SETNE: Invert = true;
14419 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14420 case ISD::SETLT: Swap = true;
14421 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14422 case ISD::SETGE: Swap = true;
14423 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14424 Invert = true; break;
14425 case ISD::SETULT: Swap = true;
14426 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14427 FlipSigns = true; break;
14428 case ISD::SETUGE: Swap = true;
14429 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14430 FlipSigns = true; Invert = true; break;
14431 }
14433 // Special case: Use min/max operations for SETULE/SETUGE
14434 MVT VET = VT.getVectorElementType();
14435 bool hasMinMax =
14436 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14437 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14439 if (hasMinMax) {
14440 switch (SetCCOpcode) {
14441 default: break;
14442 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
14443 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
14444 }
14446 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14447 }
14449 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14450 if (!MinMax && hasSubus) {
14451 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14452 // Op0 u<= Op1:
14453 // t = psubus Op0, Op1
14454 // pcmpeq t, <0..0>
14455 switch (SetCCOpcode) {
14456 default: break;
14457 case ISD::SETULT: {
14458 // If the comparison is against a constant we can turn this into a
14459 // setule. With psubus, setule does not require a swap. This is
14460 // beneficial because the constant in the register is no longer
14461 // destructed as the destination so it can be hoisted out of a loop.
14462 // Only do this pre-AVX since vpcmp* is no longer destructive.
14463 if (Subtarget->hasAVX())
14464 break;
14465 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14466 if (ULEOp1.getNode()) {
14467 Op1 = ULEOp1;
14468 Subus = true; Invert = false; Swap = false;
14469 }
14470 break;
14471 }
14472 // Psubus is better than flip-sign because it requires no inversion.
14473 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14474 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14475 }
14477 if (Subus) {
14478 Opc = X86ISD::SUBUS;
14479 FlipSigns = false;
14480 }
14481 }
14483 if (Swap)
14484 std::swap(Op0, Op1);
14486 // Check that the operation in question is available (most are plain SSE2,
14487 // but PCMPGTQ and PCMPEQQ have different requirements).
14488 if (VT == MVT::v2i64) {
14489 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14490 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14492 // First cast everything to the right type.
14493 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
14494 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
14496 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14497 // bits of the inputs before performing those operations. The lower
14498 // compare is always unsigned.
14499 SDValue SB;
14500 if (FlipSigns) {
14501 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
14502 } else {
14503 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
14504 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
14505 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14506 Sign, Zero, Sign, Zero);
14507 }
14508 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14509 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14511 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14512 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14513 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14515 // Create masks for only the low parts/high parts of the 64 bit integers.
14516 static const int MaskHi[] = { 1, 1, 3, 3 };
14517 static const int MaskLo[] = { 0, 0, 2, 2 };
14518 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14519 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14520 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14522 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14523 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14525 if (Invert)
14526 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14528 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
14529 }
14531 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14532 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14533 // pcmpeqd + pshufd + pand.
14534 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14536 // First cast everything to the right type.
14537 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
14538 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
14540 // Do the compare.
14541 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14543 // Make sure the lower and upper halves are both all-ones.
14544 static const int Mask[] = { 1, 0, 3, 2 };
14545 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14546 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14548 if (Invert)
14549 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14551 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
14552 }
14553 }
14555 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14556 // bits of the inputs before performing those operations.
14557 if (FlipSigns) {
14558 EVT EltVT = VT.getVectorElementType();
14559 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
14560 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14561 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14562 }
14564 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14566 // If the logical-not of the result is required, perform that now.
14567 if (Invert)
14568 Result = DAG.getNOT(dl, Result, VT);
14570 if (MinMax)
14571 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14573 if (Subus)
14574 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14575 getZeroVector(VT, Subtarget, DAG, dl));
14577 return Result;
14578 }
14580 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14582 MVT VT = Op.getSimpleValueType();
14584 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14586 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14587 && "SetCC type must be 8-bit or 1-bit integer");
14588 SDValue Op0 = Op.getOperand(0);
14589 SDValue Op1 = Op.getOperand(1);
14590 SDLoc dl(Op);
14591 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14593 // Optimize to BT if possible.
14594 // Lower (X & (1 << N)) == 0 to BT(X, N).
14595 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14596 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14597 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14598 Op1.getOpcode() == ISD::Constant &&
14599 cast<ConstantSDNode>(Op1)->isNullValue() &&
14600 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14601 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
14602 if (NewSetCC.getNode())
14603 return NewSetCC;
14604 }
14606 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14607 // these.
14608 if (Op1.getOpcode() == ISD::Constant &&
14609 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
14610 cast<ConstantSDNode>(Op1)->isNullValue()) &&
14611 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14613 // If the input is a setcc, then reuse the input setcc or use a new one with
14614 // the inverted condition.
14615 if (Op0.getOpcode() == X86ISD::SETCC) {
14616 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14617 bool Invert = (CC == ISD::SETNE) ^
14618 cast<ConstantSDNode>(Op1)->isNullValue();
14619 if (!Invert)
14620 return Op0;
14622 CCode = X86::GetOppositeBranchCondition(CCode);
14623 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14624 DAG.getConstant(CCode, MVT::i8),
14625 Op0.getOperand(1));
14626 if (VT == MVT::i1)
14627 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14628 return SetCC;
14629 }
14630 }
14631 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
14632 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
14633 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14635 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14636 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
14637 }
14639 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14640 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
14641 if (X86CC == X86::COND_INVALID)
14642 return SDValue();
14644 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14645 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14646 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14647 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
14648 if (VT == MVT::i1)
14649 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14650 return SetCC;
14651 }
14653 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14654 static bool isX86LogicalCmp(SDValue Op) {
14655 unsigned Opc = Op.getNode()->getOpcode();
14656 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14657 Opc == X86ISD::SAHF)
14658 return true;
14659 if (Op.getResNo() == 1 &&
14660 (Opc == X86ISD::ADD ||
14661 Opc == X86ISD::SUB ||
14662 Opc == X86ISD::ADC ||
14663 Opc == X86ISD::SBB ||
14664 Opc == X86ISD::SMUL ||
14665 Opc == X86ISD::UMUL ||
14666 Opc == X86ISD::INC ||
14667 Opc == X86ISD::DEC ||
14668 Opc == X86ISD::OR ||
14669 Opc == X86ISD::XOR ||
14670 Opc == X86ISD::AND))
14671 return true;
14673 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14674 return true;
14676 return false;
14677 }
14679 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14680 if (V.getOpcode() != ISD::TRUNCATE)
14681 return false;
14683 SDValue VOp0 = V.getOperand(0);
14684 unsigned InBits = VOp0.getValueSizeInBits();
14685 unsigned Bits = V.getValueSizeInBits();
14686 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14687 }
14689 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14690 bool addTest = true;
14691 SDValue Cond = Op.getOperand(0);
14692 SDValue Op1 = Op.getOperand(1);
14693 SDValue Op2 = Op.getOperand(2);
14694 SDLoc DL(Op);
14695 EVT VT = Op1.getValueType();
14696 SDValue CC;
14698 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14699 // are available. Otherwise fp cmovs get lowered into a less efficient branch
14700 // sequence later on.
14701 if (Cond.getOpcode() == ISD::SETCC &&
14702 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14703 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14704 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
14705 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14706 int SSECC = translateX86FSETCC(
14707 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14709 if (SSECC != 8) {
14710 if (Subtarget->hasAVX512()) {
14711 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14712 DAG.getConstant(SSECC, MVT::i8));
14713 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14714 }
14715 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14716 DAG.getConstant(SSECC, MVT::i8));
14717 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14718 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14719 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14720 }
14721 }
14723 if (Cond.getOpcode() == ISD::SETCC) {
14724 SDValue NewCond = LowerSETCC(Cond, DAG);
14725 if (NewCond.getNode())
14726 Cond = NewCond;
14727 }
14729 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14730 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14731 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14732 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14733 if (Cond.getOpcode() == X86ISD::SETCC &&
14734 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14735 isZero(Cond.getOperand(1).getOperand(1))) {
14736 SDValue Cmp = Cond.getOperand(1);
14738 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14740 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
14741 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14742 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
14744 SDValue CmpOp0 = Cmp.getOperand(0);
14745 // Apply further optimizations for special cases
14746 // (select (x != 0), -1, 0) -> neg & sbb
14747 // (select (x == 0), 0, -1) -> neg & sbb
14748 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
14749 if (YC->isNullValue() &&
14750 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
14751 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14752 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14753 DAG.getConstant(0, CmpOp0.getValueType()),
14754 CmpOp0);
14755 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14756 DAG.getConstant(X86::COND_B, MVT::i8),
14757 SDValue(Neg.getNode(), 1));
14758 return Res;
14759 }
14761 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14762 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
14763 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14765 SDValue Res = // Res = 0 or -1.
14766 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14767 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
14769 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
14770 Res = DAG.getNOT(DL, Res, Res.getValueType());
14772 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
14773 if (!N2C || !N2C->isNullValue())
14774 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14775 return Res;
14776 }
14777 }
14779 // Look past (and (setcc_carry (cmp ...)), 1).
14780 if (Cond.getOpcode() == ISD::AND &&
14781 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14782 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14783 if (C && C->getAPIntValue() == 1)
14784 Cond = Cond.getOperand(0);
14785 }
14787 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14788 // setting operand in place of the X86ISD::SETCC.
14789 unsigned CondOpcode = Cond.getOpcode();
14790 if (CondOpcode == X86ISD::SETCC ||
14791 CondOpcode == X86ISD::SETCC_CARRY) {
14792 CC = Cond.getOperand(0);
14794 SDValue Cmp = Cond.getOperand(1);
14795 unsigned Opc = Cmp.getOpcode();
14796 MVT VT = Op.getSimpleValueType();
14798 bool IllegalFPCMov = false;
14799 if (VT.isFloatingPoint() && !VT.isVector() &&
14800 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14801 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14803 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14804 Opc == X86ISD::BT) { // FIXME
14805 Cond = Cmp;
14806 addTest = false;
14807 }
14808 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14809 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14810 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14811 Cond.getOperand(0).getValueType() != MVT::i8)) {
14812 SDValue LHS = Cond.getOperand(0);
14813 SDValue RHS = Cond.getOperand(1);
14814 unsigned X86Opcode;
14815 unsigned X86Cond;
14816 SDVTList VTs;
14817 switch (CondOpcode) {
14818 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14819 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14820 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14821 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14822 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14823 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14824 default: llvm_unreachable("unexpected overflowing operator");
14825 }
14826 if (CondOpcode == ISD::UMULO)
14827 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14828 MVT::i32);
14829 else
14830 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14832 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14834 if (CondOpcode == ISD::UMULO)
14835 Cond = X86Op.getValue(2);
14836 else
14837 Cond = X86Op.getValue(1);
14839 CC = DAG.getConstant(X86Cond, MVT::i8);
14840 addTest = false;
14841 }
14843 if (addTest) {
14844 // Look pass the truncate if the high bits are known zero.
14845 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14846 Cond = Cond.getOperand(0);
14848 // We know the result of AND is compared against zero. Try to match
14849 // it to BT.
14850 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14851 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
14852 if (NewSetCC.getNode()) {
14853 CC = NewSetCC.getOperand(0);
14854 Cond = NewSetCC.getOperand(1);
14855 addTest = false;
14856 }
14857 }
14858 }
14860 if (addTest) {
14861 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
14862 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14863 }
14865 // a < b ? -1 : 0 -> RES = ~setcc_carry
14866 // a < b ? 0 : -1 -> RES = setcc_carry
14867 // a >= b ? -1 : 0 -> RES = setcc_carry
14868 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14869 if (Cond.getOpcode() == X86ISD::SUB) {
14870 Cond = ConvertCmpIfNecessary(Cond, DAG);
14871 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14873 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14874 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
14875 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14876 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
14877 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
14878 return DAG.getNOT(DL, Res, Res.getValueType());
14879 return Res;
14880 }
14881 }
14883 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14884 // widen the cmov and push the truncate through. This avoids introducing a new
14885 // branch during isel and doesn't add any extensions.
14886 if (Op.getValueType() == MVT::i8 &&
14887 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14888 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14889 if (T1.getValueType() == T2.getValueType() &&
14890 // Blacklist CopyFromReg to avoid partial register stalls.
14891 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14892 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14893 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14894 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14895 }
14896 }
14898 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14899 // condition is true.
14900 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14901 SDValue Ops[] = { Op2, Op1, CC, Cond };
14902 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14903 }
14905 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
14906 MVT VT = Op->getSimpleValueType(0);
14907 SDValue In = Op->getOperand(0);
14908 MVT InVT = In.getSimpleValueType();
14909 SDLoc dl(Op);
14911 unsigned int NumElts = VT.getVectorNumElements();
14912 if (NumElts != 8 && NumElts != 16)
14913 return SDValue();
14915 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
14916 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14918 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14919 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14921 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
14922 Constant *C = ConstantInt::get(*DAG.getContext(),
14923 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
14925 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
14926 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14927 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
14928 MachinePointerInfo::getConstantPool(),
14929 false, false, false, Alignment);
14930 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
14931 if (VT.is512BitVector())
14932 return Brcst;
14933 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
14934 }
14936 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14937 SelectionDAG &DAG) {
14938 MVT VT = Op->getSimpleValueType(0);
14939 SDValue In = Op->getOperand(0);
14940 MVT InVT = In.getSimpleValueType();
14941 SDLoc dl(Op);
14943 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
14944 return LowerSIGN_EXTEND_AVX512(Op, DAG);
14946 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
14947 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
14948 (VT != MVT::v16i16 || InVT != MVT::v16i8))
14949 return SDValue();
14951 if (Subtarget->hasInt256())
14952 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14954 // Optimize vectors in AVX mode
14955 // Sign extend v8i16 to v8i32 and
14956 // v4i32 to v4i64
14957 //
14958 // Divide input vector into two parts
14959 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14960 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14961 // concat the vectors to original VT
14963 unsigned NumElems = InVT.getVectorNumElements();
14964 SDValue Undef = DAG.getUNDEF(InVT);
14966 SmallVector<int,8> ShufMask1(NumElems, -1);
14967 for (unsigned i = 0; i != NumElems/2; ++i)
14968 ShufMask1[i] = i;
14970 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
14972 SmallVector<int,8> ShufMask2(NumElems, -1);
14973 for (unsigned i = 0; i != NumElems/2; ++i)
14974 ShufMask2[i] = i + NumElems/2;
14976 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
14978 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
14979 VT.getVectorNumElements()/2);
14981 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
14982 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
14984 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14985 }
14987 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
14988 // may emit an illegal shuffle but the expansion is still better than scalar
14989 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
14990 // we'll emit a shuffle and a arithmetic shift.
14991 // TODO: It is possible to support ZExt by zeroing the undef values during
14992 // the shuffle phase or after the shuffle.
14993 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
14994 SelectionDAG &DAG) {
14995 MVT RegVT = Op.getSimpleValueType();
14996 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
14997 assert(RegVT.isInteger() &&
14998 "We only custom lower integer vector sext loads.");
15000 // Nothing useful we can do without SSE2 shuffles.
15001 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15003 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15004 SDLoc dl(Ld);
15005 EVT MemVT = Ld->getMemoryVT();
15006 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15007 unsigned RegSz = RegVT.getSizeInBits();
15009 ISD::LoadExtType Ext = Ld->getExtensionType();
15011 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15012 && "Only anyext and sext are currently implemented.");
15013 assert(MemVT != RegVT && "Cannot extend to the same type");
15014 assert(MemVT.isVector() && "Must load a vector from memory");
15016 unsigned NumElems = RegVT.getVectorNumElements();
15017 unsigned MemSz = MemVT.getSizeInBits();
15018 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15020 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15021 // The only way in which we have a legal 256-bit vector result but not the
15022 // integer 256-bit operations needed to directly lower a sextload is if we
15023 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15024 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15025 // correctly legalized. We do this late to allow the canonical form of
15026 // sextload to persist throughout the rest of the DAG combiner -- it wants
15027 // to fold together any extensions it can, and so will fuse a sign_extend
15028 // of an sextload into a sextload targeting a wider value.
15029 SDValue Load;
15030 if (MemSz == 128) {
15031 // Just switch this to a normal load.
15032 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15033 "it must be a legal 128-bit vector "
15034 "type!");
15035 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15036 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15037 Ld->isInvariant(), Ld->getAlignment());
15038 } else {
15039 assert(MemSz < 128 &&
15040 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15041 // Do an sext load to a 128-bit vector type. We want to use the same
15042 // number of elements, but elements half as wide. This will end up being
15043 // recursively lowered by this routine, but will succeed as we definitely
15044 // have all the necessary features if we're using AVX1.
15045 EVT HalfEltVT =
15046 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15047 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15048 Load =
15049 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15050 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15051 Ld->isNonTemporal(), Ld->isInvariant(),
15052 Ld->getAlignment());
15053 }
15055 // Replace chain users with the new chain.
15056 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15057 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15059 // Finally, do a normal sign-extend to the desired register.
15060 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15061 }
15063 // All sizes must be a power of two.
15064 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15065 "Non-power-of-two elements are not custom lowered!");
15067 // Attempt to load the original value using scalar loads.
15068 // Find the largest scalar type that divides the total loaded size.
15069 MVT SclrLoadTy = MVT::i8;
15070 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
15071 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
15072 MVT Tp = (MVT::SimpleValueType)tp;
15073 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15074 SclrLoadTy = Tp;
15075 }
15076 }
15078 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15079 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15080 (64 <= MemSz))
15081 SclrLoadTy = MVT::f64;
15083 // Calculate the number of scalar loads that we need to perform
15084 // in order to load our vector from memory.
15085 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15087 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15088 "Can only lower sext loads with a single scalar load!");
15090 unsigned loadRegZize = RegSz;
15091 if (Ext == ISD::SEXTLOAD && RegSz == 256)
15092 loadRegZize /= 2;
15094 // Represent our vector as a sequence of elements which are the
15095 // largest scalar that we can load.
15096 EVT LoadUnitVecVT = EVT::getVectorVT(
15097 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15099 // Represent the data using the same element type that is stored in
15100 // memory. In practice, we ''widen'' MemVT.
15101 EVT WideVecVT =
15102 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15103 loadRegZize / MemVT.getScalarType().getSizeInBits());
15105 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15106 "Invalid vector type");
15108 // We can't shuffle using an illegal type.
15109 assert(TLI.isTypeLegal(WideVecVT) &&
15110 "We only lower types that form legal widened vector types");
15112 SmallVector<SDValue, 8> Chains;
15113 SDValue Ptr = Ld->getBasePtr();
15114 SDValue Increment =
15115 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
15116 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15118 for (unsigned i = 0; i < NumLoads; ++i) {
15119 // Perform a single load.
15120 SDValue ScalarLoad =
15121 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15122 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15123 Ld->getAlignment());
15124 Chains.push_back(ScalarLoad.getValue(1));
15125 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15126 // another round of DAGCombining.
15127 if (i == 0)
15128 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15129 else
15130 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15131 ScalarLoad, DAG.getIntPtrConstant(i));
15133 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15134 }
15136 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
15138 // Bitcast the loaded value to a vector of the original element type, in
15139 // the size of the target vector type.
15140 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
15141 unsigned SizeRatio = RegSz / MemSz;
15143 if (Ext == ISD::SEXTLOAD) {
15144 // If we have SSE4.1, we can directly emit a VSEXT node.
15145 if (Subtarget->hasSSE41()) {
15146 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
15147 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15148 return Sext;
15149 }
15151 // Otherwise we'll shuffle the small elements in the high bits of the
15152 // larger type and perform an arithmetic shift. If the shift is not legal
15153 // it's better to scalarize.
15154 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
15155 "We can't implement a sext load without an arithmetic right shift!");
15157 // Redistribute the loaded elements into the different locations.
15158 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15159 for (unsigned i = 0; i != NumElems; ++i)
15160 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
15162 SDValue Shuff = DAG.getVectorShuffle(
15163 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15165 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
15167 // Build the arithmetic shift.
15168 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
15169 MemVT.getVectorElementType().getSizeInBits();
15170 Shuff =
15171 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
15173 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15174 return Shuff;
15175 }
15177 // Redistribute the loaded elements into the different locations.
15178 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15179 for (unsigned i = 0; i != NumElems; ++i)
15180 ShuffleVec[i * SizeRatio] = i;
15182 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15183 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15185 // Bitcast to the requested type.
15186 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
15187 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15188 return Shuff;
15189 }
15191 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15192 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15193 // from the AND / OR.
15194 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15195 Opc = Op.getOpcode();
15196 if (Opc != ISD::OR && Opc != ISD::AND)
15197 return false;
15198 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15199 Op.getOperand(0).hasOneUse() &&
15200 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15201 Op.getOperand(1).hasOneUse());
15202 }
15204 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15205 // 1 and that the SETCC node has a single use.
15206 static bool isXor1OfSetCC(SDValue Op) {
15207 if (Op.getOpcode() != ISD::XOR)
15208 return false;
15209 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
15210 if (N1C && N1C->getAPIntValue() == 1) {
15211 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15212 Op.getOperand(0).hasOneUse();
15213 }
15214 return false;
15215 }
15217 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15218 bool addTest = true;
15219 SDValue Chain = Op.getOperand(0);
15220 SDValue Cond = Op.getOperand(1);
15221 SDValue Dest = Op.getOperand(2);
15222 SDLoc dl(Op);
15223 SDValue CC;
15224 bool Inverted = false;
15226 if (Cond.getOpcode() == ISD::SETCC) {
15227 // Check for setcc([su]{add,sub,mul}o == 0).
15228 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15229 isa<ConstantSDNode>(Cond.getOperand(1)) &&
15230 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
15231 Cond.getOperand(0).getResNo() == 1 &&
15232 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15233 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15234 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15235 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15236 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15237 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15238 Inverted = true;
15239 Cond = Cond.getOperand(0);
15240 } else {
15241 SDValue NewCond = LowerSETCC(Cond, DAG);
15242 if (NewCond.getNode())
15243 Cond = NewCond;
15244 }
15245 }
15246 #if 0
15247 // FIXME: LowerXALUO doesn't handle these!!
15248 else if (Cond.getOpcode() == X86ISD::ADD ||
15249 Cond.getOpcode() == X86ISD::SUB ||
15250 Cond.getOpcode() == X86ISD::SMUL ||
15251 Cond.getOpcode() == X86ISD::UMUL)
15252 Cond = LowerXALUO(Cond, DAG);
15253 #endif
15255 // Look pass (and (setcc_carry (cmp ...)), 1).
15256 if (Cond.getOpcode() == ISD::AND &&
15257 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15258 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15259 if (C && C->getAPIntValue() == 1)
15260 Cond = Cond.getOperand(0);
15261 }
15263 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15264 // setting operand in place of the X86ISD::SETCC.
15265 unsigned CondOpcode = Cond.getOpcode();
15266 if (CondOpcode == X86ISD::SETCC ||
15267 CondOpcode == X86ISD::SETCC_CARRY) {
15268 CC = Cond.getOperand(0);
15270 SDValue Cmp = Cond.getOperand(1);
15271 unsigned Opc = Cmp.getOpcode();
15272 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15273 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15274 Cond = Cmp;
15275 addTest = false;
15276 } else {
15277 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15278 default: break;
15279 case X86::COND_O:
15280 case X86::COND_B:
15281 // These can only come from an arithmetic instruction with overflow,
15282 // e.g. SADDO, UADDO.
15283 Cond = Cond.getNode()->getOperand(1);
15284 addTest = false;
15285 break;
15286 }
15287 }
15288 }
15289 CondOpcode = Cond.getOpcode();
15290 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15291 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15292 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15293 Cond.getOperand(0).getValueType() != MVT::i8)) {
15294 SDValue LHS = Cond.getOperand(0);
15295 SDValue RHS = Cond.getOperand(1);
15296 unsigned X86Opcode;
15297 unsigned X86Cond;
15298 SDVTList VTs;
15299 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15300 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15301 // X86ISD::INC).
15302 switch (CondOpcode) {
15303 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15304 case ISD::SADDO:
15305 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15306 if (C->isOne()) {
15307 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15308 break;
15309 }
15310 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15311 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15312 case ISD::SSUBO:
15313 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15314 if (C->isOne()) {
15315 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15316 break;
15317 }
15318 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15319 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15320 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15321 default: llvm_unreachable("unexpected overflowing operator");
15322 }
15323 if (Inverted)
15324 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15325 if (CondOpcode == ISD::UMULO)
15326 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15327 MVT::i32);
15328 else
15329 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15331 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15333 if (CondOpcode == ISD::UMULO)
15334 Cond = X86Op.getValue(2);
15335 else
15336 Cond = X86Op.getValue(1);
15338 CC = DAG.getConstant(X86Cond, MVT::i8);
15339 addTest = false;
15340 } else {
15341 unsigned CondOpc;
15342 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15343 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15344 if (CondOpc == ISD::OR) {
15345 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15346 // two branches instead of an explicit OR instruction with a
15347 // separate test.
15348 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15349 isX86LogicalCmp(Cmp)) {
15350 CC = Cond.getOperand(0).getOperand(0);
15351 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15352 Chain, Dest, CC, Cmp);
15353 CC = Cond.getOperand(1).getOperand(0);
15354 Cond = Cmp;
15355 addTest = false;
15356 }
15357 } else { // ISD::AND
15358 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15359 // two branches instead of an explicit AND instruction with a
15360 // separate test. However, we only do this if this block doesn't
15361 // have a fall-through edge, because this requires an explicit
15362 // jmp when the condition is false.
15363 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15364 isX86LogicalCmp(Cmp) &&
15365 Op.getNode()->hasOneUse()) {
15366 X86::CondCode CCode =
15367 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15368 CCode = X86::GetOppositeBranchCondition(CCode);
15369 CC = DAG.getConstant(CCode, MVT::i8);
15370 SDNode *User = *Op.getNode()->use_begin();
15371 // Look for an unconditional branch following this conditional branch.
15372 // We need this because we need to reverse the successors in order
15373 // to implement FCMP_OEQ.
15374 if (User->getOpcode() == ISD::BR) {
15375 SDValue FalseBB = User->getOperand(1);
15376 SDNode *NewBR =
15377 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15378 assert(NewBR == User);
15379 (void)NewBR;
15380 Dest = FalseBB;
15382 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15383 Chain, Dest, CC, Cmp);
15384 X86::CondCode CCode =
15385 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15386 CCode = X86::GetOppositeBranchCondition(CCode);
15387 CC = DAG.getConstant(CCode, MVT::i8);
15388 Cond = Cmp;
15389 addTest = false;
15390 }
15391 }
15392 }
15393 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15394 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15395 // It should be transformed during dag combiner except when the condition
15396 // is set by a arithmetics with overflow node.
15397 X86::CondCode CCode =
15398 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15399 CCode = X86::GetOppositeBranchCondition(CCode);
15400 CC = DAG.getConstant(CCode, MVT::i8);
15401 Cond = Cond.getOperand(0).getOperand(1);
15402 addTest = false;
15403 } else if (Cond.getOpcode() == ISD::SETCC &&
15404 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15405 // For FCMP_OEQ, we can emit
15406 // two branches instead of an explicit AND instruction with a
15407 // separate test. However, we only do this if this block doesn't
15408 // have a fall-through edge, because this requires an explicit
15409 // jmp when the condition is false.
15410 if (Op.getNode()->hasOneUse()) {
15411 SDNode *User = *Op.getNode()->use_begin();
15412 // Look for an unconditional branch following this conditional branch.
15413 // We need this because we need to reverse the successors in order
15414 // to implement FCMP_OEQ.
15415 if (User->getOpcode() == ISD::BR) {
15416 SDValue FalseBB = User->getOperand(1);
15417 SDNode *NewBR =
15418 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15419 assert(NewBR == User);
15420 (void)NewBR;
15421 Dest = FalseBB;
15423 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15424 Cond.getOperand(0), Cond.getOperand(1));
15425 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15426 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15427 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15428 Chain, Dest, CC, Cmp);
15429 CC = DAG.getConstant(X86::COND_P, MVT::i8);
15430 Cond = Cmp;
15431 addTest = false;
15432 }
15433 }
15434 } else if (Cond.getOpcode() == ISD::SETCC &&
15435 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15436 // For FCMP_UNE, we can emit
15437 // two branches instead of an explicit AND instruction with a
15438 // separate test. However, we only do this if this block doesn't
15439 // have a fall-through edge, because this requires an explicit
15440 // jmp when the condition is false.
15441 if (Op.getNode()->hasOneUse()) {
15442 SDNode *User = *Op.getNode()->use_begin();
15443 // Look for an unconditional branch following this conditional branch.
15444 // We need this because we need to reverse the successors in order
15445 // to implement FCMP_UNE.
15446 if (User->getOpcode() == ISD::BR) {
15447 SDValue FalseBB = User->getOperand(1);
15448 SDNode *NewBR =
15449 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15450 assert(NewBR == User);
15451 (void)NewBR;
15453 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15454 Cond.getOperand(0), Cond.getOperand(1));
15455 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15456 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15457 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15458 Chain, Dest, CC, Cmp);
15459 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
15460 Cond = Cmp;
15461 addTest = false;
15462 Dest = FalseBB;
15463 }
15464 }
15465 }
15466 }
15468 if (addTest) {
15469 // Look pass the truncate if the high bits are known zero.
15470 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15471 Cond = Cond.getOperand(0);
15473 // We know the result of AND is compared against zero. Try to match
15474 // it to BT.
15475 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15476 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
15477 if (NewSetCC.getNode()) {
15478 CC = NewSetCC.getOperand(0);
15479 Cond = NewSetCC.getOperand(1);
15480 addTest = false;
15481 }
15482 }
15483 }
15485 if (addTest) {
15486 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15487 CC = DAG.getConstant(X86Cond, MVT::i8);
15488 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15489 }
15490 Cond = ConvertCmpIfNecessary(Cond, DAG);
15491 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15492 Chain, Dest, CC, Cond);
15493 }
15495 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15496 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15497 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15498 // that the guard pages used by the OS virtual memory manager are allocated in
15499 // correct sequence.
15500 SDValue
15501 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15502 SelectionDAG &DAG) const {
15503 MachineFunction &MF = DAG.getMachineFunction();
15504 bool SplitStack = MF.shouldSplitStack();
15505 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
15506 SplitStack;
15507 SDLoc dl(Op);
15509 if (!Lower) {
15510 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15511 SDNode* Node = Op.getNode();
15513 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15514 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15515 " not tell us which reg is the stack pointer!");
15516 EVT VT = Node->getValueType(0);
15517 SDValue Tmp1 = SDValue(Node, 0);
15518 SDValue Tmp2 = SDValue(Node, 1);
15519 SDValue Tmp3 = Node->getOperand(2);
15520 SDValue Chain = Tmp1.getOperand(0);
15522 // Chain the dynamic stack allocation so that it doesn't modify the stack
15523 // pointer when other instructions are using the stack.
15524 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
15525 SDLoc(Node));
15527 SDValue Size = Tmp2.getOperand(1);
15528 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15529 Chain = SP.getValue(1);
15530 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15531 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
15532 unsigned StackAlign = TFI.getStackAlignment();
15533 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15534 if (Align > StackAlign)
15535 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
15536 DAG.getConstant(-(uint64_t)Align, VT));
15537 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
15539 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
15540 DAG.getIntPtrConstant(0, true), SDValue(),
15541 SDLoc(Node));
15543 SDValue Ops[2] = { Tmp1, Tmp2 };
15544 return DAG.getMergeValues(Ops, dl);
15545 }
15547 // Get the inputs.
15548 SDValue Chain = Op.getOperand(0);
15549 SDValue Size = Op.getOperand(1);
15550 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15551 EVT VT = Op.getNode()->getValueType(0);
15553 bool Is64Bit = Subtarget->is64Bit();
15554 EVT SPTy = getPointerTy();
15556 if (SplitStack) {
15557 MachineRegisterInfo &MRI = MF.getRegInfo();
15559 if (Is64Bit) {
15560 // The 64 bit implementation of segmented stacks needs to clobber both r10
15561 // r11. This makes it impossible to use it along with nested parameters.
15562 const Function *F = MF.getFunction();
15564 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15565 I != E; ++I)
15566 if (I->hasNestAttr())
15567 report_fatal_error("Cannot use segmented stacks with functions that "
15568 "have nested arguments.");
15569 }
15571 const TargetRegisterClass *AddrRegClass =
15572 getRegClassFor(getPointerTy());
15573 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15574 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15575 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15576 DAG.getRegister(Vreg, SPTy));
15577 SDValue Ops1[2] = { Value, Chain };
15578 return DAG.getMergeValues(Ops1, dl);
15579 } else {
15580 SDValue Flag;
15581 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15583 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15584 Flag = Chain.getValue(1);
15585 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15587 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15589 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15590 DAG.getSubtarget().getRegisterInfo());
15591 unsigned SPReg = RegInfo->getStackRegister();
15592 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15593 Chain = SP.getValue(1);
15595 if (Align) {
15596 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15597 DAG.getConstant(-(uint64_t)Align, VT));
15598 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15599 }
15601 SDValue Ops1[2] = { SP, Chain };
15602 return DAG.getMergeValues(Ops1, dl);
15603 }
15604 }
15606 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15607 MachineFunction &MF = DAG.getMachineFunction();
15608 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15610 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15611 SDLoc DL(Op);
15613 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
15614 // vastart just stores the address of the VarArgsFrameIndex slot into the
15615 // memory location argument.
15616 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
15617 getPointerTy());
15618 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15619 MachinePointerInfo(SV), false, false, 0);
15620 }
15622 // __va_list_tag:
15623 // gp_offset (0 - 6 * 8)
15624 // fp_offset (48 - 48 + 8 * 16)
15625 // overflow_arg_area (point to parameters coming in memory).
15626 // reg_save_area
15627 SmallVector<SDValue, 8> MemOps;
15628 SDValue FIN = Op.getOperand(1);
15629 // Store gp_offset
15630 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15631 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15632 MVT::i32),
15633 FIN, MachinePointerInfo(SV), false, false, 0);
15634 MemOps.push_back(Store);
15636 // Store fp_offset
15637 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15638 FIN, DAG.getIntPtrConstant(4));
15639 Store = DAG.getStore(Op.getOperand(0), DL,
15640 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
15641 MVT::i32),
15642 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15643 MemOps.push_back(Store);
15645 // Store ptr to overflow_arg_area
15646 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15647 FIN, DAG.getIntPtrConstant(4));
15648 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
15649 getPointerTy());
15650 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15651 MachinePointerInfo(SV, 8),
15652 false, false, 0);
15653 MemOps.push_back(Store);
15655 // Store ptr to reg_save_area.
15656 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15657 FIN, DAG.getIntPtrConstant(8));
15658 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
15659 getPointerTy());
15660 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
15661 MachinePointerInfo(SV, 16), false, false, 0);
15662 MemOps.push_back(Store);
15663 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15664 }
15666 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15667 assert(Subtarget->is64Bit() &&
15668 "LowerVAARG only handles 64-bit va_arg!");
15669 assert((Subtarget->isTargetLinux() ||
15670 Subtarget->isTargetDarwin()) &&
15671 "Unhandled target in LowerVAARG");
15672 assert(Op.getNode()->getNumOperands() == 4);
15673 SDValue Chain = Op.getOperand(0);
15674 SDValue SrcPtr = Op.getOperand(1);
15675 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15676 unsigned Align = Op.getConstantOperandVal(3);
15677 SDLoc dl(Op);
15679 EVT ArgVT = Op.getNode()->getValueType(0);
15680 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15681 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
15682 uint8_t ArgMode;
15684 // Decide which area this value should be read from.
15685 // TODO: Implement the AMD64 ABI in its entirety. This simple
15686 // selection mechanism works only for the basic types.
15687 if (ArgVT == MVT::f80) {
15688 llvm_unreachable("va_arg for f80 not yet implemented");
15689 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15690 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15691 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15692 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15693 } else {
15694 llvm_unreachable("Unhandled argument type in LowerVAARG");
15695 }
15697 if (ArgMode == 2) {
15698 // Sanity Check: Make sure using fp_offset makes sense.
15699 assert(!DAG.getTarget().Options.UseSoftFloat &&
15700 !(DAG.getMachineFunction()
15701 .getFunction()->getAttributes()
15702 .hasAttribute(AttributeSet::FunctionIndex,
15703 Attribute::NoImplicitFloat)) &&
15704 Subtarget->hasSSE1());
15705 }
15707 // Insert VAARG_64 node into the DAG
15708 // VAARG_64 returns two values: Variable Argument Address, Chain
15709 SmallVector<SDValue, 11> InstOps;
15710 InstOps.push_back(Chain);
15711 InstOps.push_back(SrcPtr);
15712 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
15713 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
15714 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
15715 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
15716 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15717 VTs, InstOps, MVT::i64,
15718 MachinePointerInfo(SV),
15719 /*Align=*/0,
15720 /*Volatile=*/false,
15721 /*ReadMem=*/true,
15722 /*WriteMem=*/true);
15723 Chain = VAARG.getValue(1);
15725 // Load the next argument and return it
15726 return DAG.getLoad(ArgVT, dl,
15727 Chain,
15728 VAARG,
15729 MachinePointerInfo(),
15730 false, false, false, 0);
15731 }
15733 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15734 SelectionDAG &DAG) {
15735 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
15736 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15737 SDValue Chain = Op.getOperand(0);
15738 SDValue DstPtr = Op.getOperand(1);
15739 SDValue SrcPtr = Op.getOperand(2);
15740 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15741 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15742 SDLoc DL(Op);
15744 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15745 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
15746 false,
15747 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15748 }
15750 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15751 // amount is a constant. Takes immediate version of shift as input.
15752 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15753 SDValue SrcOp, uint64_t ShiftAmt,
15754 SelectionDAG &DAG) {
15755 MVT ElementType = VT.getVectorElementType();
15757 // Fold this packed shift into its first operand if ShiftAmt is 0.
15758 if (ShiftAmt == 0)
15759 return SrcOp;
15761 // Check for ShiftAmt >= element width
15762 if (ShiftAmt >= ElementType.getSizeInBits()) {
15763 if (Opc == X86ISD::VSRAI)
15764 ShiftAmt = ElementType.getSizeInBits() - 1;
15765 else
15766 return DAG.getConstant(0, VT);
15767 }
15769 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15770 && "Unknown target vector shift-by-constant node");
15772 // Fold this packed vector shift into a build vector if SrcOp is a
15773 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15774 if (VT == SrcOp.getSimpleValueType() &&
15775 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15776 SmallVector<SDValue, 8> Elts;
15777 unsigned NumElts = SrcOp->getNumOperands();
15778 ConstantSDNode *ND;
15780 switch(Opc) {
15781 default: llvm_unreachable(nullptr);
15782 case X86ISD::VSHLI:
15783 for (unsigned i=0; i!=NumElts; ++i) {
15784 SDValue CurrentOp = SrcOp->getOperand(i);
15785 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15786 Elts.push_back(CurrentOp);
15787 continue;
15788 }
15789 ND = cast<ConstantSDNode>(CurrentOp);
15790 const APInt &C = ND->getAPIntValue();
15791 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
15792 }
15793 break;
15794 case X86ISD::VSRLI:
15795 for (unsigned i=0; i!=NumElts; ++i) {
15796 SDValue CurrentOp = SrcOp->getOperand(i);
15797 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15798 Elts.push_back(CurrentOp);
15799 continue;
15800 }
15801 ND = cast<ConstantSDNode>(CurrentOp);
15802 const APInt &C = ND->getAPIntValue();
15803 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
15804 }
15805 break;
15806 case X86ISD::VSRAI:
15807 for (unsigned i=0; i!=NumElts; ++i) {
15808 SDValue CurrentOp = SrcOp->getOperand(i);
15809 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15810 Elts.push_back(CurrentOp);
15811 continue;
15812 }
15813 ND = cast<ConstantSDNode>(CurrentOp);
15814 const APInt &C = ND->getAPIntValue();
15815 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
15816 }
15817 break;
15818 }
15820 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15821 }
15823 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
15824 }
15826 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15827 // may or may not be a constant. Takes immediate version of shift as input.
15828 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15829 SDValue SrcOp, SDValue ShAmt,
15830 SelectionDAG &DAG) {
15831 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
15833 // Catch shift-by-constant.
15834 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15835 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15836 CShAmt->getZExtValue(), DAG);
15838 // Change opcode to non-immediate version
15839 switch (Opc) {
15840 default: llvm_unreachable("Unknown target vector shift node");
15841 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15842 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15843 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15844 }
15846 // Need to build a vector containing shift amount
15847 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
15848 SDValue ShOps[4];
15849 ShOps[0] = ShAmt;
15850 ShOps[1] = DAG.getConstant(0, MVT::i32);
15851 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
15852 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
15854 // The return type has to be a 128-bit type with the same element
15855 // type as the input type.
15856 MVT EltVT = VT.getVectorElementType();
15857 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15859 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
15860 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15861 }
15863 /// \brief Return (and \p Op, \p Mask) for compare instructions or
15864 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
15865 /// necessary casting for \p Mask when lowering masking intrinsics.
15866 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
15867 SDValue PreservedSrc, SelectionDAG &DAG) {
15868 EVT VT = Op.getValueType();
15869 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
15870 MVT::i1, VT.getVectorNumElements());
15871 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15872 Mask.getValueType().getSizeInBits());
15873 SDLoc dl(Op);
15875 assert(MaskVT.isSimple() && "invalid mask type");
15877 if (isAllOnes(Mask))
15878 return Op;
15880 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
15881 // are extracted by EXTRACT_SUBVECTOR.
15882 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15883 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
15884 DAG.getIntPtrConstant(0));
15886 switch (Op.getOpcode()) {
15887 default: break;
15888 case X86ISD::PCMPEQM:
15889 case X86ISD::PCMPGTM:
15890 case X86ISD::CMPM:
15891 case X86ISD::CMPMU:
15892 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
15893 }
15895 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
15896 }
15898 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
15899 switch (IntNo) {
15900 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15901 case Intrinsic::x86_fma_vfmadd_ps:
15902 case Intrinsic::x86_fma_vfmadd_pd:
15903 case Intrinsic::x86_fma_vfmadd_ps_256:
15904 case Intrinsic::x86_fma_vfmadd_pd_256:
15905 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
15906 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
15907 return X86ISD::FMADD;
15908 case Intrinsic::x86_fma_vfmsub_ps:
15909 case Intrinsic::x86_fma_vfmsub_pd:
15910 case Intrinsic::x86_fma_vfmsub_ps_256:
15911 case Intrinsic::x86_fma_vfmsub_pd_256:
15912 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
15913 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
15914 return X86ISD::FMSUB;
15915 case Intrinsic::x86_fma_vfnmadd_ps:
15916 case Intrinsic::x86_fma_vfnmadd_pd:
15917 case Intrinsic::x86_fma_vfnmadd_ps_256:
15918 case Intrinsic::x86_fma_vfnmadd_pd_256:
15919 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
15920 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
15921 return X86ISD::FNMADD;
15922 case Intrinsic::x86_fma_vfnmsub_ps:
15923 case Intrinsic::x86_fma_vfnmsub_pd:
15924 case Intrinsic::x86_fma_vfnmsub_ps_256:
15925 case Intrinsic::x86_fma_vfnmsub_pd_256:
15926 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
15927 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
15928 return X86ISD::FNMSUB;
15929 case Intrinsic::x86_fma_vfmaddsub_ps:
15930 case Intrinsic::x86_fma_vfmaddsub_pd:
15931 case Intrinsic::x86_fma_vfmaddsub_ps_256:
15932 case Intrinsic::x86_fma_vfmaddsub_pd_256:
15933 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
15934 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
15935 return X86ISD::FMADDSUB;
15936 case Intrinsic::x86_fma_vfmsubadd_ps:
15937 case Intrinsic::x86_fma_vfmsubadd_pd:
15938 case Intrinsic::x86_fma_vfmsubadd_ps_256:
15939 case Intrinsic::x86_fma_vfmsubadd_pd_256:
15940 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
15941 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
15942 return X86ISD::FMSUBADD;
15943 }
15944 }
15946 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
15947 SDLoc dl(Op);
15948 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15950 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
15951 if (IntrData) {
15952 switch(IntrData->Type) {
15953 case INTR_TYPE_1OP:
15954 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
15955 case INTR_TYPE_2OP:
15956 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15957 Op.getOperand(2));
15958 case INTR_TYPE_3OP:
15959 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15960 Op.getOperand(2), Op.getOperand(3));
15961 case CMP_MASK: {
15962 // Comparison intrinsics with masks.
15963 // Example of transformation:
15964 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
15965 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
15966 // (i8 (bitcast
15967 // (v8i1 (insert_subvector undef,
15968 // (v2i1 (and (PCMPEQM %a, %b),
15969 // (extract_subvector
15970 // (v8i1 (bitcast %mask)), 0))), 0))))
15971 EVT VT = Op.getOperand(1).getValueType();
15972 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15973 VT.getVectorNumElements());
15974 SDValue Mask = Op.getOperand(3);
15975 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15976 Mask.getValueType().getSizeInBits());
15977 SDValue Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT,
15978 Op.getOperand(1), Op.getOperand(2));
15979 SDValue CmpMask = getVectorMaskingNode(Cmp, Op.getOperand(3),
15980 DAG.getTargetConstant(0, MaskVT), DAG);
15981 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
15982 DAG.getUNDEF(BitcastVT), CmpMask,
15983 DAG.getIntPtrConstant(0));
15984 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
15985 }
15986 case COMI: { // Comparison intrinsics
15987 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
15988 SDValue LHS = Op.getOperand(1);
15989 SDValue RHS = Op.getOperand(2);
15990 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
15991 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
15992 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
15993 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15994 DAG.getConstant(X86CC, MVT::i8), Cond);
15995 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15996 }
15997 case VSHIFT:
15998 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
15999 Op.getOperand(1), Op.getOperand(2), DAG);
16000 default:
16001 break;
16002 }
16003 }
16005 switch (IntNo) {
16006 default: return SDValue(); // Don't custom lower most intrinsics.
16008 // Arithmetic intrinsics.
16009 case Intrinsic::x86_sse2_pmulu_dq:
16010 case Intrinsic::x86_avx2_pmulu_dq:
16011 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
16012 Op.getOperand(1), Op.getOperand(2));
16014 case Intrinsic::x86_sse41_pmuldq:
16015 case Intrinsic::x86_avx2_pmul_dq:
16016 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
16017 Op.getOperand(1), Op.getOperand(2));
16019 case Intrinsic::x86_sse2_pmulhu_w:
16020 case Intrinsic::x86_avx2_pmulhu_w:
16021 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
16022 Op.getOperand(1), Op.getOperand(2));
16024 case Intrinsic::x86_sse2_pmulh_w:
16025 case Intrinsic::x86_avx2_pmulh_w:
16026 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
16027 Op.getOperand(1), Op.getOperand(2));
16029 // SSE/SSE2/AVX floating point max/min intrinsics.
16030 case Intrinsic::x86_sse_max_ps:
16031 case Intrinsic::x86_sse2_max_pd:
16032 case Intrinsic::x86_avx_max_ps_256:
16033 case Intrinsic::x86_avx_max_pd_256:
16034 case Intrinsic::x86_sse_min_ps:
16035 case Intrinsic::x86_sse2_min_pd:
16036 case Intrinsic::x86_avx_min_ps_256:
16037 case Intrinsic::x86_avx_min_pd_256: {
16038 unsigned Opcode;
16039 switch (IntNo) {
16040 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16041 case Intrinsic::x86_sse_max_ps:
16042 case Intrinsic::x86_sse2_max_pd:
16043 case Intrinsic::x86_avx_max_ps_256:
16044 case Intrinsic::x86_avx_max_pd_256:
16045 Opcode = X86ISD::FMAX;
16046 break;
16047 case Intrinsic::x86_sse_min_ps:
16048 case Intrinsic::x86_sse2_min_pd:
16049 case Intrinsic::x86_avx_min_ps_256:
16050 case Intrinsic::x86_avx_min_pd_256:
16051 Opcode = X86ISD::FMIN;
16052 break;
16053 }
16054 return DAG.getNode(Opcode, dl, Op.getValueType(),
16055 Op.getOperand(1), Op.getOperand(2));
16056 }
16058 // AVX2 variable shift intrinsics
16059 case Intrinsic::x86_avx2_psllv_d:
16060 case Intrinsic::x86_avx2_psllv_q:
16061 case Intrinsic::x86_avx2_psllv_d_256:
16062 case Intrinsic::x86_avx2_psllv_q_256:
16063 case Intrinsic::x86_avx2_psrlv_d:
16064 case Intrinsic::x86_avx2_psrlv_q:
16065 case Intrinsic::x86_avx2_psrlv_d_256:
16066 case Intrinsic::x86_avx2_psrlv_q_256:
16067 case Intrinsic::x86_avx2_psrav_d:
16068 case Intrinsic::x86_avx2_psrav_d_256: {
16069 unsigned Opcode;
16070 switch (IntNo) {
16071 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16072 case Intrinsic::x86_avx2_psllv_d:
16073 case Intrinsic::x86_avx2_psllv_q:
16074 case Intrinsic::x86_avx2_psllv_d_256:
16075 case Intrinsic::x86_avx2_psllv_q_256:
16076 Opcode = ISD::SHL;
16077 break;
16078 case Intrinsic::x86_avx2_psrlv_d:
16079 case Intrinsic::x86_avx2_psrlv_q:
16080 case Intrinsic::x86_avx2_psrlv_d_256:
16081 case Intrinsic::x86_avx2_psrlv_q_256:
16082 Opcode = ISD::SRL;
16083 break;
16084 case Intrinsic::x86_avx2_psrav_d:
16085 case Intrinsic::x86_avx2_psrav_d_256:
16086 Opcode = ISD::SRA;
16087 break;
16088 }
16089 return DAG.getNode(Opcode, dl, Op.getValueType(),
16090 Op.getOperand(1), Op.getOperand(2));
16091 }
16093 case Intrinsic::x86_sse2_packssdw_128:
16094 case Intrinsic::x86_sse2_packsswb_128:
16095 case Intrinsic::x86_avx2_packssdw:
16096 case Intrinsic::x86_avx2_packsswb:
16097 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
16098 Op.getOperand(1), Op.getOperand(2));
16100 case Intrinsic::x86_sse2_packuswb_128:
16101 case Intrinsic::x86_sse41_packusdw:
16102 case Intrinsic::x86_avx2_packuswb:
16103 case Intrinsic::x86_avx2_packusdw:
16104 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
16105 Op.getOperand(1), Op.getOperand(2));
16107 case Intrinsic::x86_ssse3_pshuf_b_128:
16108 case Intrinsic::x86_avx2_pshuf_b:
16109 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
16110 Op.getOperand(1), Op.getOperand(2));
16112 case Intrinsic::x86_sse2_pshuf_d:
16113 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
16114 Op.getOperand(1), Op.getOperand(2));
16116 case Intrinsic::x86_sse2_pshufl_w:
16117 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
16118 Op.getOperand(1), Op.getOperand(2));
16120 case Intrinsic::x86_sse2_pshufh_w:
16121 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
16122 Op.getOperand(1), Op.getOperand(2));
16124 case Intrinsic::x86_ssse3_psign_b_128:
16125 case Intrinsic::x86_ssse3_psign_w_128:
16126 case Intrinsic::x86_ssse3_psign_d_128:
16127 case Intrinsic::x86_avx2_psign_b:
16128 case Intrinsic::x86_avx2_psign_w:
16129 case Intrinsic::x86_avx2_psign_d:
16130 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
16131 Op.getOperand(1), Op.getOperand(2));
16133 case Intrinsic::x86_avx2_permd:
16134 case Intrinsic::x86_avx2_permps:
16135 // Operands intentionally swapped. Mask is last operand to intrinsic,
16136 // but second operand for node/instruction.
16137 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16138 Op.getOperand(2), Op.getOperand(1));
16140 case Intrinsic::x86_avx512_mask_valign_q_512:
16141 case Intrinsic::x86_avx512_mask_valign_d_512:
16142 // Vector source operands are swapped.
16143 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
16144 Op.getValueType(), Op.getOperand(2),
16145 Op.getOperand(1),
16146 Op.getOperand(3)),
16147 Op.getOperand(5), Op.getOperand(4), DAG);
16149 // ptest and testp intrinsics. The intrinsic these come from are designed to
16150 // return an integer value, not just an instruction so lower it to the ptest
16151 // or testp pattern and a setcc for the result.
16152 case Intrinsic::x86_sse41_ptestz:
16153 case Intrinsic::x86_sse41_ptestc:
16154 case Intrinsic::x86_sse41_ptestnzc:
16155 case Intrinsic::x86_avx_ptestz_256:
16156 case Intrinsic::x86_avx_ptestc_256:
16157 case Intrinsic::x86_avx_ptestnzc_256:
16158 case Intrinsic::x86_avx_vtestz_ps:
16159 case Intrinsic::x86_avx_vtestc_ps:
16160 case Intrinsic::x86_avx_vtestnzc_ps:
16161 case Intrinsic::x86_avx_vtestz_pd:
16162 case Intrinsic::x86_avx_vtestc_pd:
16163 case Intrinsic::x86_avx_vtestnzc_pd:
16164 case Intrinsic::x86_avx_vtestz_ps_256:
16165 case Intrinsic::x86_avx_vtestc_ps_256:
16166 case Intrinsic::x86_avx_vtestnzc_ps_256:
16167 case Intrinsic::x86_avx_vtestz_pd_256:
16168 case Intrinsic::x86_avx_vtestc_pd_256:
16169 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16170 bool IsTestPacked = false;
16171 unsigned X86CC;
16172 switch (IntNo) {
16173 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16174 case Intrinsic::x86_avx_vtestz_ps:
16175 case Intrinsic::x86_avx_vtestz_pd:
16176 case Intrinsic::x86_avx_vtestz_ps_256:
16177 case Intrinsic::x86_avx_vtestz_pd_256:
16178 IsTestPacked = true; // Fallthrough
16179 case Intrinsic::x86_sse41_ptestz:
16180 case Intrinsic::x86_avx_ptestz_256:
16181 // ZF = 1
16182 X86CC = X86::COND_E;
16183 break;
16184 case Intrinsic::x86_avx_vtestc_ps:
16185 case Intrinsic::x86_avx_vtestc_pd:
16186 case Intrinsic::x86_avx_vtestc_ps_256:
16187 case Intrinsic::x86_avx_vtestc_pd_256:
16188 IsTestPacked = true; // Fallthrough
16189 case Intrinsic::x86_sse41_ptestc:
16190 case Intrinsic::x86_avx_ptestc_256:
16191 // CF = 1
16192 X86CC = X86::COND_B;
16193 break;
16194 case Intrinsic::x86_avx_vtestnzc_ps:
16195 case Intrinsic::x86_avx_vtestnzc_pd:
16196 case Intrinsic::x86_avx_vtestnzc_ps_256:
16197 case Intrinsic::x86_avx_vtestnzc_pd_256:
16198 IsTestPacked = true; // Fallthrough
16199 case Intrinsic::x86_sse41_ptestnzc:
16200 case Intrinsic::x86_avx_ptestnzc_256:
16201 // ZF and CF = 0
16202 X86CC = X86::COND_A;
16203 break;
16204 }
16206 SDValue LHS = Op.getOperand(1);
16207 SDValue RHS = Op.getOperand(2);
16208 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16209 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16210 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
16211 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16212 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16213 }
16214 case Intrinsic::x86_avx512_kortestz_w:
16215 case Intrinsic::x86_avx512_kortestc_w: {
16216 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16217 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
16218 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
16219 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
16220 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16221 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16222 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16223 }
16225 case Intrinsic::x86_sse42_pcmpistria128:
16226 case Intrinsic::x86_sse42_pcmpestria128:
16227 case Intrinsic::x86_sse42_pcmpistric128:
16228 case Intrinsic::x86_sse42_pcmpestric128:
16229 case Intrinsic::x86_sse42_pcmpistrio128:
16230 case Intrinsic::x86_sse42_pcmpestrio128:
16231 case Intrinsic::x86_sse42_pcmpistris128:
16232 case Intrinsic::x86_sse42_pcmpestris128:
16233 case Intrinsic::x86_sse42_pcmpistriz128:
16234 case Intrinsic::x86_sse42_pcmpestriz128: {
16235 unsigned Opcode;
16236 unsigned X86CC;
16237 switch (IntNo) {
16238 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16239 case Intrinsic::x86_sse42_pcmpistria128:
16240 Opcode = X86ISD::PCMPISTRI;
16241 X86CC = X86::COND_A;
16242 break;
16243 case Intrinsic::x86_sse42_pcmpestria128:
16244 Opcode = X86ISD::PCMPESTRI;
16245 X86CC = X86::COND_A;
16246 break;
16247 case Intrinsic::x86_sse42_pcmpistric128:
16248 Opcode = X86ISD::PCMPISTRI;
16249 X86CC = X86::COND_B;
16250 break;
16251 case Intrinsic::x86_sse42_pcmpestric128:
16252 Opcode = X86ISD::PCMPESTRI;
16253 X86CC = X86::COND_B;
16254 break;
16255 case Intrinsic::x86_sse42_pcmpistrio128:
16256 Opcode = X86ISD::PCMPISTRI;
16257 X86CC = X86::COND_O;
16258 break;
16259 case Intrinsic::x86_sse42_pcmpestrio128:
16260 Opcode = X86ISD::PCMPESTRI;
16261 X86CC = X86::COND_O;
16262 break;
16263 case Intrinsic::x86_sse42_pcmpistris128:
16264 Opcode = X86ISD::PCMPISTRI;
16265 X86CC = X86::COND_S;
16266 break;
16267 case Intrinsic::x86_sse42_pcmpestris128:
16268 Opcode = X86ISD::PCMPESTRI;
16269 X86CC = X86::COND_S;
16270 break;
16271 case Intrinsic::x86_sse42_pcmpistriz128:
16272 Opcode = X86ISD::PCMPISTRI;
16273 X86CC = X86::COND_E;
16274 break;
16275 case Intrinsic::x86_sse42_pcmpestriz128:
16276 Opcode = X86ISD::PCMPESTRI;
16277 X86CC = X86::COND_E;
16278 break;
16279 }
16280 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16281 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16282 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
16283 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16284 DAG.getConstant(X86CC, MVT::i8),
16285 SDValue(PCMP.getNode(), 1));
16286 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16287 }
16289 case Intrinsic::x86_sse42_pcmpistri128:
16290 case Intrinsic::x86_sse42_pcmpestri128: {
16291 unsigned Opcode;
16292 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
16293 Opcode = X86ISD::PCMPISTRI;
16294 else
16295 Opcode = X86ISD::PCMPESTRI;
16297 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16298 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16299 return DAG.getNode(Opcode, dl, VTs, NewOps);
16300 }
16302 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16303 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16304 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16305 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16306 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16307 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16308 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16309 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16310 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16311 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16312 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16313 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
16314 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
16315 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
16316 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
16317 dl, Op.getValueType(),
16318 Op.getOperand(1),
16319 Op.getOperand(2),
16320 Op.getOperand(3)),
16321 Op.getOperand(4), Op.getOperand(1), DAG);
16322 else
16323 return SDValue();
16324 }
16326 case Intrinsic::x86_fma_vfmadd_ps:
16327 case Intrinsic::x86_fma_vfmadd_pd:
16328 case Intrinsic::x86_fma_vfmsub_ps:
16329 case Intrinsic::x86_fma_vfmsub_pd:
16330 case Intrinsic::x86_fma_vfnmadd_ps:
16331 case Intrinsic::x86_fma_vfnmadd_pd:
16332 case Intrinsic::x86_fma_vfnmsub_ps:
16333 case Intrinsic::x86_fma_vfnmsub_pd:
16334 case Intrinsic::x86_fma_vfmaddsub_ps:
16335 case Intrinsic::x86_fma_vfmaddsub_pd:
16336 case Intrinsic::x86_fma_vfmsubadd_ps:
16337 case Intrinsic::x86_fma_vfmsubadd_pd:
16338 case Intrinsic::x86_fma_vfmadd_ps_256:
16339 case Intrinsic::x86_fma_vfmadd_pd_256:
16340 case Intrinsic::x86_fma_vfmsub_ps_256:
16341 case Intrinsic::x86_fma_vfmsub_pd_256:
16342 case Intrinsic::x86_fma_vfnmadd_ps_256:
16343 case Intrinsic::x86_fma_vfnmadd_pd_256:
16344 case Intrinsic::x86_fma_vfnmsub_ps_256:
16345 case Intrinsic::x86_fma_vfnmsub_pd_256:
16346 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16347 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16348 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16349 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16350 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
16351 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
16352 }
16353 }
16355 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16356 SDValue Src, SDValue Mask, SDValue Base,
16357 SDValue Index, SDValue ScaleOp, SDValue Chain,
16358 const X86Subtarget * Subtarget) {
16359 SDLoc dl(Op);
16360 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16361 assert(C && "Invalid scale type");
16362 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16363 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16364 Index.getSimpleValueType().getVectorNumElements());
16365 SDValue MaskInReg;
16366 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16367 if (MaskC)
16368 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16369 else
16370 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16371 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16372 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16373 SDValue Segment = DAG.getRegister(0, MVT::i32);
16374 if (Src.getOpcode() == ISD::UNDEF)
16375 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
16376 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16377 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16378 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16379 return DAG.getMergeValues(RetOps, dl);
16380 }
16382 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16383 SDValue Src, SDValue Mask, SDValue Base,
16384 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16385 SDLoc dl(Op);
16386 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16387 assert(C && "Invalid scale type");
16388 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16389 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16390 SDValue Segment = DAG.getRegister(0, MVT::i32);
16391 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16392 Index.getSimpleValueType().getVectorNumElements());
16393 SDValue MaskInReg;
16394 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16395 if (MaskC)
16396 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16397 else
16398 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16399 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16400 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16401 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16402 return SDValue(Res, 1);
16403 }
16405 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16406 SDValue Mask, SDValue Base, SDValue Index,
16407 SDValue ScaleOp, SDValue Chain) {
16408 SDLoc dl(Op);
16409 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16410 assert(C && "Invalid scale type");
16411 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16412 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16413 SDValue Segment = DAG.getRegister(0, MVT::i32);
16414 EVT MaskVT =
16415 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
16416 SDValue MaskInReg;
16417 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16418 if (MaskC)
16419 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16420 else
16421 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16422 //SDVTList VTs = DAG.getVTList(MVT::Other);
16423 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16424 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
16425 return SDValue(Res, 0);
16426 }
16428 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
16429 // read performance monitor counters (x86_rdpmc).
16430 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
16431 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16432 SmallVectorImpl<SDValue> &Results) {
16433 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16434 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16435 SDValue LO, HI;
16437 // The ECX register is used to select the index of the performance counter
16438 // to read.
16439 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
16440 N->getOperand(2));
16441 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
16443 // Reads the content of a 64-bit performance counter and returns it in the
16444 // registers EDX:EAX.
16445 if (Subtarget->is64Bit()) {
16446 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16447 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16448 LO.getValue(2));
16449 } else {
16450 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16451 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16452 LO.getValue(2));
16453 }
16454 Chain = HI.getValue(1);
16456 if (Subtarget->is64Bit()) {
16457 // The EAX register is loaded with the low-order 32 bits. The EDX register
16458 // is loaded with the supported high-order bits of the counter.
16459 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16460 DAG.getConstant(32, MVT::i8));
16461 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16462 Results.push_back(Chain);
16463 return;
16464 }
16466 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16467 SDValue Ops[] = { LO, HI };
16468 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16469 Results.push_back(Pair);
16470 Results.push_back(Chain);
16471 }
16473 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
16474 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
16475 // also used to custom lower READCYCLECOUNTER nodes.
16476 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
16477 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16478 SmallVectorImpl<SDValue> &Results) {
16479 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16480 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
16481 SDValue LO, HI;
16483 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
16484 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
16485 // and the EAX register is loaded with the low-order 32 bits.
16486 if (Subtarget->is64Bit()) {
16487 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16488 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16489 LO.getValue(2));
16490 } else {
16491 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16492 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16493 LO.getValue(2));
16494 }
16495 SDValue Chain = HI.getValue(1);
16497 if (Opcode == X86ISD::RDTSCP_DAG) {
16498 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16500 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
16501 // the ECX register. Add 'ecx' explicitly to the chain.
16502 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
16503 HI.getValue(2));
16504 // Explicitly store the content of ECX at the location passed in input
16505 // to the 'rdtscp' intrinsic.
16506 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
16507 MachinePointerInfo(), false, false, 0);
16508 }
16510 if (Subtarget->is64Bit()) {
16511 // The EDX register is loaded with the high-order 32 bits of the MSR, and
16512 // the EAX register is loaded with the low-order 32 bits.
16513 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16514 DAG.getConstant(32, MVT::i8));
16515 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16516 Results.push_back(Chain);
16517 return;
16518 }
16520 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16521 SDValue Ops[] = { LO, HI };
16522 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16523 Results.push_back(Pair);
16524 Results.push_back(Chain);
16525 }
16527 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
16528 SelectionDAG &DAG) {
16529 SmallVector<SDValue, 2> Results;
16530 SDLoc DL(Op);
16531 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
16532 Results);
16533 return DAG.getMergeValues(Results, DL);
16534 }
16537 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16538 SelectionDAG &DAG) {
16539 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
16541 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
16542 if (!IntrData)
16543 return SDValue();
16545 SDLoc dl(Op);
16546 switch(IntrData->Type) {
16547 default:
16548 llvm_unreachable("Unknown Intrinsic Type");
16549 break;
16550 case RDSEED:
16551 case RDRAND: {
16552 // Emit the node with the right value type.
16553 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
16554 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16556 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
16557 // Otherwise return the value from Rand, which is always 0, casted to i32.
16558 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
16559 DAG.getConstant(1, Op->getValueType(1)),
16560 DAG.getConstant(X86::COND_B, MVT::i32),
16561 SDValue(Result.getNode(), 1) };
16562 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
16563 DAG.getVTList(Op->getValueType(1), MVT::Glue),
16564 Ops);
16566 // Return { result, isValid, chain }.
16567 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
16568 SDValue(Result.getNode(), 2));
16569 }
16570 case GATHER: {
16571 //gather(v1, mask, index, base, scale);
16572 SDValue Chain = Op.getOperand(0);
16573 SDValue Src = Op.getOperand(2);
16574 SDValue Base = Op.getOperand(3);
16575 SDValue Index = Op.getOperand(4);
16576 SDValue Mask = Op.getOperand(5);
16577 SDValue Scale = Op.getOperand(6);
16578 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
16579 Subtarget);
16580 }
16581 case SCATTER: {
16582 //scatter(base, mask, index, v1, scale);
16583 SDValue Chain = Op.getOperand(0);
16584 SDValue Base = Op.getOperand(2);
16585 SDValue Mask = Op.getOperand(3);
16586 SDValue Index = Op.getOperand(4);
16587 SDValue Src = Op.getOperand(5);
16588 SDValue Scale = Op.getOperand(6);
16589 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
16590 }
16591 case PREFETCH: {
16592 SDValue Hint = Op.getOperand(6);
16593 unsigned HintVal;
16594 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
16595 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
16596 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
16597 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
16598 SDValue Chain = Op.getOperand(0);
16599 SDValue Mask = Op.getOperand(2);
16600 SDValue Index = Op.getOperand(3);
16601 SDValue Base = Op.getOperand(4);
16602 SDValue Scale = Op.getOperand(5);
16603 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
16604 }
16605 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
16606 case RDTSC: {
16607 SmallVector<SDValue, 2> Results;
16608 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
16609 return DAG.getMergeValues(Results, dl);
16610 }
16611 // Read Performance Monitoring Counters.
16612 case RDPMC: {
16613 SmallVector<SDValue, 2> Results;
16614 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
16615 return DAG.getMergeValues(Results, dl);
16616 }
16617 // XTEST intrinsics.
16618 case XTEST: {
16619 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16620 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16621 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16622 DAG.getConstant(X86::COND_NE, MVT::i8),
16623 InTrans);
16624 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
16625 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
16626 Ret, SDValue(InTrans.getNode(), 1));
16627 }
16628 // ADC/ADCX/SBB
16629 case ADX: {
16630 SmallVector<SDValue, 2> Results;
16631 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16632 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
16633 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
16634 DAG.getConstant(-1, MVT::i8));
16635 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
16636 Op.getOperand(4), GenCF.getValue(1));
16637 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
16638 Op.getOperand(5), MachinePointerInfo(),
16639 false, false, 0);
16640 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16641 DAG.getConstant(X86::COND_B, MVT::i8),
16642 Res.getValue(1));
16643 Results.push_back(SetCC);
16644 Results.push_back(Store);
16645 return DAG.getMergeValues(Results, dl);
16646 }
16647 }
16648 }
16650 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
16651 SelectionDAG &DAG) const {
16652 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16653 MFI->setReturnAddressIsTaken(true);
16655 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
16656 return SDValue();
16658 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16659 SDLoc dl(Op);
16660 EVT PtrVT = getPointerTy();
16662 if (Depth > 0) {
16663 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
16664 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16665 DAG.getSubtarget().getRegisterInfo());
16666 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
16667 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16668 DAG.getNode(ISD::ADD, dl, PtrVT,
16669 FrameAddr, Offset),
16670 MachinePointerInfo(), false, false, false, 0);
16671 }
16673 // Just load the return address.
16674 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
16675 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16676 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
16677 }
16679 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
16680 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16681 MFI->setFrameAddressIsTaken(true);
16683 EVT VT = Op.getValueType();
16684 SDLoc dl(Op); // FIXME probably not meaningful
16685 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16686 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16687 DAG.getSubtarget().getRegisterInfo());
16688 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16689 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
16690 (FrameReg == X86::EBP && VT == MVT::i32)) &&
16691 "Invalid Frame Register!");
16692 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
16693 while (Depth--)
16694 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
16695 MachinePointerInfo(),
16696 false, false, false, 0);
16697 return FrameAddr;
16698 }
16700 // FIXME? Maybe this could be a TableGen attribute on some registers and
16701 // this table could be generated automatically from RegInfo.
16702 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
16703 EVT VT) const {
16704 unsigned Reg = StringSwitch<unsigned>(RegName)
16705 .Case("esp", X86::ESP)
16706 .Case("rsp", X86::RSP)
16707 .Default(0);
16708 if (Reg)
16709 return Reg;
16710 report_fatal_error("Invalid register name global variable");
16711 }
16713 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
16714 SelectionDAG &DAG) const {
16715 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16716 DAG.getSubtarget().getRegisterInfo());
16717 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
16718 }
16720 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
16721 SDValue Chain = Op.getOperand(0);
16722 SDValue Offset = Op.getOperand(1);
16723 SDValue Handler = Op.getOperand(2);
16724 SDLoc dl (Op);
16726 EVT PtrVT = getPointerTy();
16727 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16728 DAG.getSubtarget().getRegisterInfo());
16729 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16730 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
16731 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
16732 "Invalid Frame Register!");
16733 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
16734 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
16736 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
16737 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
16738 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
16739 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
16740 false, false, 0);
16741 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
16743 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
16744 DAG.getRegister(StoreAddrReg, PtrVT));
16745 }
16747 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
16748 SelectionDAG &DAG) const {
16749 SDLoc DL(Op);
16750 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
16751 DAG.getVTList(MVT::i32, MVT::Other),
16752 Op.getOperand(0), Op.getOperand(1));
16753 }
16755 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
16756 SelectionDAG &DAG) const {
16757 SDLoc DL(Op);
16758 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
16759 Op.getOperand(0), Op.getOperand(1));
16760 }
16762 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
16763 return Op.getOperand(0);
16764 }
16766 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
16767 SelectionDAG &DAG) const {
16768 SDValue Root = Op.getOperand(0);
16769 SDValue Trmp = Op.getOperand(1); // trampoline
16770 SDValue FPtr = Op.getOperand(2); // nested function
16771 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
16772 SDLoc dl (Op);
16774 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16775 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
16777 if (Subtarget->is64Bit()) {
16778 SDValue OutChains[6];
16780 // Large code-model.
16781 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
16782 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
16784 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
16785 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
16787 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
16789 // Load the pointer to the nested function into R11.
16790 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
16791 SDValue Addr = Trmp;
16792 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16793 Addr, MachinePointerInfo(TrmpAddr),
16794 false, false, 0);
16796 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16797 DAG.getConstant(2, MVT::i64));
16798 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
16799 MachinePointerInfo(TrmpAddr, 2),
16800 false, false, 2);
16802 // Load the 'nest' parameter value into R10.
16803 // R10 is specified in X86CallingConv.td
16804 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
16805 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16806 DAG.getConstant(10, MVT::i64));
16807 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16808 Addr, MachinePointerInfo(TrmpAddr, 10),
16809 false, false, 0);
16811 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16812 DAG.getConstant(12, MVT::i64));
16813 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
16814 MachinePointerInfo(TrmpAddr, 12),
16815 false, false, 2);
16817 // Jump to the nested function.
16818 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
16819 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16820 DAG.getConstant(20, MVT::i64));
16821 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16822 Addr, MachinePointerInfo(TrmpAddr, 20),
16823 false, false, 0);
16825 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
16826 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16827 DAG.getConstant(22, MVT::i64));
16828 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
16829 MachinePointerInfo(TrmpAddr, 22),
16830 false, false, 0);
16832 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16833 } else {
16834 const Function *Func =
16835 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
16836 CallingConv::ID CC = Func->getCallingConv();
16837 unsigned NestReg;
16839 switch (CC) {
16840 default:
16841 llvm_unreachable("Unsupported calling convention");
16842 case CallingConv::C:
16843 case CallingConv::X86_StdCall: {
16844 // Pass 'nest' parameter in ECX.
16845 // Must be kept in sync with X86CallingConv.td
16846 NestReg = X86::ECX;
16848 // Check that ECX wasn't needed by an 'inreg' parameter.
16849 FunctionType *FTy = Func->getFunctionType();
16850 const AttributeSet &Attrs = Func->getAttributes();
16852 if (!Attrs.isEmpty() && !Func->isVarArg()) {
16853 unsigned InRegCount = 0;
16854 unsigned Idx = 1;
16856 for (FunctionType::param_iterator I = FTy->param_begin(),
16857 E = FTy->param_end(); I != E; ++I, ++Idx)
16858 if (Attrs.hasAttribute(Idx, Attribute::InReg))
16859 // FIXME: should only count parameters that are lowered to integers.
16860 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
16862 if (InRegCount > 2) {
16863 report_fatal_error("Nest register in use - reduce number of inreg"
16864 " parameters!");
16865 }
16866 }
16867 break;
16868 }
16869 case CallingConv::X86_FastCall:
16870 case CallingConv::X86_ThisCall:
16871 case CallingConv::Fast:
16872 // Pass 'nest' parameter in EAX.
16873 // Must be kept in sync with X86CallingConv.td
16874 NestReg = X86::EAX;
16875 break;
16876 }
16878 SDValue OutChains[4];
16879 SDValue Addr, Disp;
16881 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16882 DAG.getConstant(10, MVT::i32));
16883 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
16885 // This is storing the opcode for MOV32ri.
16886 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
16887 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
16888 OutChains[0] = DAG.getStore(Root, dl,
16889 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
16890 Trmp, MachinePointerInfo(TrmpAddr),
16891 false, false, 0);
16893 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16894 DAG.getConstant(1, MVT::i32));
16895 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
16896 MachinePointerInfo(TrmpAddr, 1),
16897 false, false, 1);
16899 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
16900 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16901 DAG.getConstant(5, MVT::i32));
16902 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
16903 MachinePointerInfo(TrmpAddr, 5),
16904 false, false, 1);
16906 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16907 DAG.getConstant(6, MVT::i32));
16908 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
16909 MachinePointerInfo(TrmpAddr, 6),
16910 false, false, 1);
16912 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16913 }
16914 }
16916 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
16917 SelectionDAG &DAG) const {
16918 /*
16919 The rounding mode is in bits 11:10 of FPSR, and has the following
16920 settings:
16921 00 Round to nearest
16922 01 Round to -inf
16923 10 Round to +inf
16924 11 Round to 0
16926 FLT_ROUNDS, on the other hand, expects the following:
16927 -1 Undefined
16928 0 Round to 0
16929 1 Round to nearest
16930 2 Round to +inf
16931 3 Round to -inf
16933 To perform the conversion, we do:
16934 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
16935 */
16937 MachineFunction &MF = DAG.getMachineFunction();
16938 const TargetMachine &TM = MF.getTarget();
16939 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
16940 unsigned StackAlignment = TFI.getStackAlignment();
16941 MVT VT = Op.getSimpleValueType();
16942 SDLoc DL(Op);
16944 // Save FP Control Word to stack slot
16945 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
16946 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
16948 MachineMemOperand *MMO =
16949 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
16950 MachineMemOperand::MOStore, 2, 2);
16952 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
16953 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
16954 DAG.getVTList(MVT::Other),
16955 Ops, MVT::i16, MMO);
16957 // Load FP Control Word from stack slot
16958 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
16959 MachinePointerInfo(), false, false, false, 0);
16961 // Transform as necessary
16962 SDValue CWD1 =
16963 DAG.getNode(ISD::SRL, DL, MVT::i16,
16964 DAG.getNode(ISD::AND, DL, MVT::i16,
16965 CWD, DAG.getConstant(0x800, MVT::i16)),
16966 DAG.getConstant(11, MVT::i8));
16967 SDValue CWD2 =
16968 DAG.getNode(ISD::SRL, DL, MVT::i16,
16969 DAG.getNode(ISD::AND, DL, MVT::i16,
16970 CWD, DAG.getConstant(0x400, MVT::i16)),
16971 DAG.getConstant(9, MVT::i8));
16973 SDValue RetVal =
16974 DAG.getNode(ISD::AND, DL, MVT::i16,
16975 DAG.getNode(ISD::ADD, DL, MVT::i16,
16976 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
16977 DAG.getConstant(1, MVT::i16)),
16978 DAG.getConstant(3, MVT::i16));
16980 return DAG.getNode((VT.getSizeInBits() < 16 ?
16981 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
16982 }
16984 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
16985 MVT VT = Op.getSimpleValueType();
16986 EVT OpVT = VT;
16987 unsigned NumBits = VT.getSizeInBits();
16988 SDLoc dl(Op);
16990 Op = Op.getOperand(0);
16991 if (VT == MVT::i8) {
16992 // Zero extend to i32 since there is not an i8 bsr.
16993 OpVT = MVT::i32;
16994 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16995 }
16997 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
16998 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16999 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17001 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17002 SDValue Ops[] = {
17003 Op,
17004 DAG.getConstant(NumBits+NumBits-1, OpVT),
17005 DAG.getConstant(X86::COND_E, MVT::i8),
17006 Op.getValue(1)
17007 };
17008 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17010 // Finally xor with NumBits-1.
17011 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17013 if (VT == MVT::i8)
17014 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17015 return Op;
17016 }
17018 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
17019 MVT VT = Op.getSimpleValueType();
17020 EVT OpVT = VT;
17021 unsigned NumBits = VT.getSizeInBits();
17022 SDLoc dl(Op);
17024 Op = Op.getOperand(0);
17025 if (VT == MVT::i8) {
17026 // Zero extend to i32 since there is not an i8 bsr.
17027 OpVT = MVT::i32;
17028 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17029 }
17031 // Issue a bsr (scan bits in reverse).
17032 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17033 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17035 // And xor with NumBits-1.
17036 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17038 if (VT == MVT::i8)
17039 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17040 return Op;
17041 }
17043 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17044 MVT VT = Op.getSimpleValueType();
17045 unsigned NumBits = VT.getSizeInBits();
17046 SDLoc dl(Op);
17047 Op = Op.getOperand(0);
17049 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17050 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17051 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
17053 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17054 SDValue Ops[] = {
17055 Op,
17056 DAG.getConstant(NumBits, VT),
17057 DAG.getConstant(X86::COND_E, MVT::i8),
17058 Op.getValue(1)
17059 };
17060 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17061 }
17063 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17064 // ones, and then concatenate the result back.
17065 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17066 MVT VT = Op.getSimpleValueType();
17068 assert(VT.is256BitVector() && VT.isInteger() &&
17069 "Unsupported value type for operation");
17071 unsigned NumElems = VT.getVectorNumElements();
17072 SDLoc dl(Op);
17074 // Extract the LHS vectors
17075 SDValue LHS = Op.getOperand(0);
17076 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17077 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17079 // Extract the RHS vectors
17080 SDValue RHS = Op.getOperand(1);
17081 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17082 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17084 MVT EltVT = VT.getVectorElementType();
17085 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17087 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17088 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17089 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17090 }
17092 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17093 assert(Op.getSimpleValueType().is256BitVector() &&
17094 Op.getSimpleValueType().isInteger() &&
17095 "Only handle AVX 256-bit vector integer operation");
17096 return Lower256IntArith(Op, DAG);
17097 }
17099 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17100 assert(Op.getSimpleValueType().is256BitVector() &&
17101 Op.getSimpleValueType().isInteger() &&
17102 "Only handle AVX 256-bit vector integer operation");
17103 return Lower256IntArith(Op, DAG);
17104 }
17106 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17107 SelectionDAG &DAG) {
17108 SDLoc dl(Op);
17109 MVT VT = Op.getSimpleValueType();
17111 // Decompose 256-bit ops into smaller 128-bit ops.
17112 if (VT.is256BitVector() && !Subtarget->hasInt256())
17113 return Lower256IntArith(Op, DAG);
17115 SDValue A = Op.getOperand(0);
17116 SDValue B = Op.getOperand(1);
17118 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
17119 if (VT == MVT::v4i32) {
17120 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
17121 "Should not custom lower when pmuldq is available!");
17123 // Extract the odd parts.
17124 static const int UnpackMask[] = { 1, -1, 3, -1 };
17125 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
17126 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
17128 // Multiply the even parts.
17129 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
17130 // Now multiply odd parts.
17131 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
17133 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
17134 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
17136 // Merge the two vectors back together with a shuffle. This expands into 2
17137 // shuffles.
17138 static const int ShufMask[] = { 0, 4, 2, 6 };
17139 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
17140 }
17142 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
17143 "Only know how to lower V2I64/V4I64/V8I64 multiply");
17145 // Ahi = psrlqi(a, 32);
17146 // Bhi = psrlqi(b, 32);
17147 //
17148 // AloBlo = pmuludq(a, b);
17149 // AloBhi = pmuludq(a, Bhi);
17150 // AhiBlo = pmuludq(Ahi, b);
17152 // AloBhi = psllqi(AloBhi, 32);
17153 // AhiBlo = psllqi(AhiBlo, 32);
17154 // return AloBlo + AloBhi + AhiBlo;
17156 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
17157 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
17159 // Bit cast to 32-bit vectors for MULUDQ
17160 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
17161 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
17162 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
17163 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
17164 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
17165 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
17167 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
17168 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
17169 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
17171 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
17172 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
17174 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
17175 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
17176 }
17178 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
17179 assert(Subtarget->isTargetWin64() && "Unexpected target");
17180 EVT VT = Op.getValueType();
17181 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
17182 "Unexpected return type for lowering");
17184 RTLIB::Libcall LC;
17185 bool isSigned;
17186 switch (Op->getOpcode()) {
17187 default: llvm_unreachable("Unexpected request for libcall!");
17188 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
17189 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
17190 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
17191 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
17192 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
17193 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
17194 }
17196 SDLoc dl(Op);
17197 SDValue InChain = DAG.getEntryNode();
17199 TargetLowering::ArgListTy Args;
17200 TargetLowering::ArgListEntry Entry;
17201 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
17202 EVT ArgVT = Op->getOperand(i).getValueType();
17203 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
17204 "Unexpected argument type for lowering");
17205 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
17206 Entry.Node = StackPtr;
17207 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
17208 false, false, 16);
17209 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17210 Entry.Ty = PointerType::get(ArgTy,0);
17211 Entry.isSExt = false;
17212 Entry.isZExt = false;
17213 Args.push_back(Entry);
17214 }
17216 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
17217 getPointerTy());
17219 TargetLowering::CallLoweringInfo CLI(DAG);
17220 CLI.setDebugLoc(dl).setChain(InChain)
17221 .setCallee(getLibcallCallingConv(LC),
17222 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
17223 Callee, std::move(Args), 0)
17224 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
17226 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
17227 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
17228 }
17230 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
17231 SelectionDAG &DAG) {
17232 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
17233 EVT VT = Op0.getValueType();
17234 SDLoc dl(Op);
17236 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
17237 (VT == MVT::v8i32 && Subtarget->hasInt256()));
17239 // PMULxD operations multiply each even value (starting at 0) of LHS with
17240 // the related value of RHS and produce a widen result.
17241 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17242 // => <2 x i64> <ae|cg>
17243 //
17244 // In other word, to have all the results, we need to perform two PMULxD:
17245 // 1. one with the even values.
17246 // 2. one with the odd values.
17247 // To achieve #2, with need to place the odd values at an even position.
17248 //
17249 // Place the odd value at an even position (basically, shift all values 1
17250 // step to the left):
17251 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
17252 // <a|b|c|d> => <b|undef|d|undef>
17253 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
17254 // <e|f|g|h> => <f|undef|h|undef>
17255 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
17257 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
17258 // ints.
17259 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
17260 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
17261 unsigned Opcode =
17262 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
17263 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17264 // => <2 x i64> <ae|cg>
17265 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
17266 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
17267 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
17268 // => <2 x i64> <bf|dh>
17269 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
17270 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
17272 // Shuffle it back into the right order.
17273 SDValue Highs, Lows;
17274 if (VT == MVT::v8i32) {
17275 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
17276 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17277 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
17278 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17279 } else {
17280 const int HighMask[] = {1, 5, 3, 7};
17281 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17282 const int LowMask[] = {0, 4, 2, 6};
17283 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17284 }
17286 // If we have a signed multiply but no PMULDQ fix up the high parts of a
17287 // unsigned multiply.
17288 if (IsSigned && !Subtarget->hasSSE41()) {
17289 SDValue ShAmt =
17290 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
17291 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
17292 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
17293 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
17294 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
17296 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
17297 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
17298 }
17300 // The first result of MUL_LOHI is actually the low value, followed by the
17301 // high value.
17302 SDValue Ops[] = {Lows, Highs};
17303 return DAG.getMergeValues(Ops, dl);
17304 }
17306 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
17307 const X86Subtarget *Subtarget) {
17308 MVT VT = Op.getSimpleValueType();
17309 SDLoc dl(Op);
17310 SDValue R = Op.getOperand(0);
17311 SDValue Amt = Op.getOperand(1);
17313 // Optimize shl/srl/sra with constant shift amount.
17314 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
17315 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
17316 uint64_t ShiftAmt = ShiftConst->getZExtValue();
17318 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
17319 (Subtarget->hasInt256() &&
17320 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
17321 (Subtarget->hasAVX512() &&
17322 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
17323 if (Op.getOpcode() == ISD::SHL)
17324 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
17325 DAG);
17326 if (Op.getOpcode() == ISD::SRL)
17327 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
17328 DAG);
17329 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
17330 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
17331 DAG);
17332 }
17334 if (VT == MVT::v16i8) {
17335 if (Op.getOpcode() == ISD::SHL) {
17336 // Make a large shift.
17337 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
17338 MVT::v8i16, R, ShiftAmt,
17339 DAG);
17340 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
17341 // Zero out the rightmost bits.
17342 SmallVector<SDValue, 16> V(16,
17343 DAG.getConstant(uint8_t(-1U << ShiftAmt),
17344 MVT::i8));
17345 return DAG.getNode(ISD::AND, dl, VT, SHL,
17346 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17347 }
17348 if (Op.getOpcode() == ISD::SRL) {
17349 // Make a large shift.
17350 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
17351 MVT::v8i16, R, ShiftAmt,
17352 DAG);
17353 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
17354 // Zero out the leftmost bits.
17355 SmallVector<SDValue, 16> V(16,
17356 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
17357 MVT::i8));
17358 return DAG.getNode(ISD::AND, dl, VT, SRL,
17359 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17360 }
17361 if (Op.getOpcode() == ISD::SRA) {
17362 if (ShiftAmt == 7) {
17363 // R s>> 7 === R s< 0
17364 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17365 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17366 }
17368 // R s>> a === ((R u>> a) ^ m) - m
17369 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17370 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
17371 MVT::i8));
17372 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17373 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17374 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17375 return Res;
17376 }
17377 llvm_unreachable("Unknown shift opcode.");
17378 }
17380 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
17381 if (Op.getOpcode() == ISD::SHL) {
17382 // Make a large shift.
17383 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
17384 MVT::v16i16, R, ShiftAmt,
17385 DAG);
17386 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
17387 // Zero out the rightmost bits.
17388 SmallVector<SDValue, 32> V(32,
17389 DAG.getConstant(uint8_t(-1U << ShiftAmt),
17390 MVT::i8));
17391 return DAG.getNode(ISD::AND, dl, VT, SHL,
17392 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17393 }
17394 if (Op.getOpcode() == ISD::SRL) {
17395 // Make a large shift.
17396 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
17397 MVT::v16i16, R, ShiftAmt,
17398 DAG);
17399 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
17400 // Zero out the leftmost bits.
17401 SmallVector<SDValue, 32> V(32,
17402 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
17403 MVT::i8));
17404 return DAG.getNode(ISD::AND, dl, VT, SRL,
17405 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17406 }
17407 if (Op.getOpcode() == ISD::SRA) {
17408 if (ShiftAmt == 7) {
17409 // R s>> 7 === R s< 0
17410 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17411 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17412 }
17414 // R s>> a === ((R u>> a) ^ m) - m
17415 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17416 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
17417 MVT::i8));
17418 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17419 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17420 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17421 return Res;
17422 }
17423 llvm_unreachable("Unknown shift opcode.");
17424 }
17425 }
17426 }
17428 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17429 if (!Subtarget->is64Bit() &&
17430 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
17431 Amt.getOpcode() == ISD::BITCAST &&
17432 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17433 Amt = Amt.getOperand(0);
17434 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17435 VT.getVectorNumElements();
17436 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
17437 uint64_t ShiftAmt = 0;
17438 for (unsigned i = 0; i != Ratio; ++i) {
17439 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
17440 if (!C)
17441 return SDValue();
17442 // 6 == Log2(64)
17443 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
17444 }
17445 // Check remaining shift amounts.
17446 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17447 uint64_t ShAmt = 0;
17448 for (unsigned j = 0; j != Ratio; ++j) {
17449 ConstantSDNode *C =
17450 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
17451 if (!C)
17452 return SDValue();
17453 // 6 == Log2(64)
17454 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
17455 }
17456 if (ShAmt != ShiftAmt)
17457 return SDValue();
17458 }
17459 switch (Op.getOpcode()) {
17460 default:
17461 llvm_unreachable("Unknown shift opcode!");
17462 case ISD::SHL:
17463 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
17464 DAG);
17465 case ISD::SRL:
17466 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
17467 DAG);
17468 case ISD::SRA:
17469 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
17470 DAG);
17471 }
17472 }
17474 return SDValue();
17475 }
17477 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
17478 const X86Subtarget* Subtarget) {
17479 MVT VT = Op.getSimpleValueType();
17480 SDLoc dl(Op);
17481 SDValue R = Op.getOperand(0);
17482 SDValue Amt = Op.getOperand(1);
17484 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
17485 VT == MVT::v4i32 || VT == MVT::v8i16 ||
17486 (Subtarget->hasInt256() &&
17487 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
17488 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
17489 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
17490 SDValue BaseShAmt;
17491 EVT EltVT = VT.getVectorElementType();
17493 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
17494 unsigned NumElts = VT.getVectorNumElements();
17495 unsigned i, j;
17496 for (i = 0; i != NumElts; ++i) {
17497 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
17498 continue;
17499 break;
17500 }
17501 for (j = i; j != NumElts; ++j) {
17502 SDValue Arg = Amt.getOperand(j);
17503 if (Arg.getOpcode() == ISD::UNDEF) continue;
17504 if (Arg != Amt.getOperand(i))
17505 break;
17506 }
17507 if (i != NumElts && j == NumElts)
17508 BaseShAmt = Amt.getOperand(i);
17509 } else {
17510 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
17511 Amt = Amt.getOperand(0);
17512 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
17513 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
17514 SDValue InVec = Amt.getOperand(0);
17515 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
17516 unsigned NumElts = InVec.getValueType().getVectorNumElements();
17517 unsigned i = 0;
17518 for (; i != NumElts; ++i) {
17519 SDValue Arg = InVec.getOperand(i);
17520 if (Arg.getOpcode() == ISD::UNDEF) continue;
17521 BaseShAmt = Arg;
17522 break;
17523 }
17524 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
17525 if (ConstantSDNode *C =
17526 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
17527 unsigned SplatIdx =
17528 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
17529 if (C->getZExtValue() == SplatIdx)
17530 BaseShAmt = InVec.getOperand(1);
17531 }
17532 }
17533 if (!BaseShAmt.getNode())
17534 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
17535 DAG.getIntPtrConstant(0));
17536 }
17537 }
17539 if (BaseShAmt.getNode()) {
17540 if (EltVT.bitsGT(MVT::i32))
17541 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
17542 else if (EltVT.bitsLT(MVT::i32))
17543 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
17545 switch (Op.getOpcode()) {
17546 default:
17547 llvm_unreachable("Unknown shift opcode!");
17548 case ISD::SHL:
17549 switch (VT.SimpleTy) {
17550 default: return SDValue();
17551 case MVT::v2i64:
17552 case MVT::v4i32:
17553 case MVT::v8i16:
17554 case MVT::v4i64:
17555 case MVT::v8i32:
17556 case MVT::v16i16:
17557 case MVT::v16i32:
17558 case MVT::v8i64:
17559 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
17560 }
17561 case ISD::SRA:
17562 switch (VT.SimpleTy) {
17563 default: return SDValue();
17564 case MVT::v4i32:
17565 case MVT::v8i16:
17566 case MVT::v8i32:
17567 case MVT::v16i16:
17568 case MVT::v16i32:
17569 case MVT::v8i64:
17570 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
17571 }
17572 case ISD::SRL:
17573 switch (VT.SimpleTy) {
17574 default: return SDValue();
17575 case MVT::v2i64:
17576 case MVT::v4i32:
17577 case MVT::v8i16:
17578 case MVT::v4i64:
17579 case MVT::v8i32:
17580 case MVT::v16i16:
17581 case MVT::v16i32:
17582 case MVT::v8i64:
17583 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
17584 }
17585 }
17586 }
17587 }
17589 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17590 if (!Subtarget->is64Bit() &&
17591 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
17592 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
17593 Amt.getOpcode() == ISD::BITCAST &&
17594 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17595 Amt = Amt.getOperand(0);
17596 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17597 VT.getVectorNumElements();
17598 std::vector<SDValue> Vals(Ratio);
17599 for (unsigned i = 0; i != Ratio; ++i)
17600 Vals[i] = Amt.getOperand(i);
17601 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17602 for (unsigned j = 0; j != Ratio; ++j)
17603 if (Vals[j] != Amt.getOperand(i + j))
17604 return SDValue();
17605 }
17606 switch (Op.getOpcode()) {
17607 default:
17608 llvm_unreachable("Unknown shift opcode!");
17609 case ISD::SHL:
17610 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
17611 case ISD::SRL:
17612 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
17613 case ISD::SRA:
17614 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
17615 }
17616 }
17618 return SDValue();
17619 }
17621 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
17622 SelectionDAG &DAG) {
17623 MVT VT = Op.getSimpleValueType();
17624 SDLoc dl(Op);
17625 SDValue R = Op.getOperand(0);
17626 SDValue Amt = Op.getOperand(1);
17627 SDValue V;
17629 assert(VT.isVector() && "Custom lowering only for vector shifts!");
17630 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
17632 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
17633 if (V.getNode())
17634 return V;
17636 V = LowerScalarVariableShift(Op, DAG, Subtarget);
17637 if (V.getNode())
17638 return V;
17640 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
17641 return Op;
17642 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
17643 if (Subtarget->hasInt256()) {
17644 if (Op.getOpcode() == ISD::SRL &&
17645 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
17646 VT == MVT::v4i64 || VT == MVT::v8i32))
17647 return Op;
17648 if (Op.getOpcode() == ISD::SHL &&
17649 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
17650 VT == MVT::v4i64 || VT == MVT::v8i32))
17651 return Op;
17652 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
17653 return Op;
17654 }
17656 // If possible, lower this packed shift into a vector multiply instead of
17657 // expanding it into a sequence of scalar shifts.
17658 // Do this only if the vector shift count is a constant build_vector.
17659 if (Op.getOpcode() == ISD::SHL &&
17660 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
17661 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
17662 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17663 SmallVector<SDValue, 8> Elts;
17664 EVT SVT = VT.getScalarType();
17665 unsigned SVTBits = SVT.getSizeInBits();
17666 const APInt &One = APInt(SVTBits, 1);
17667 unsigned NumElems = VT.getVectorNumElements();
17669 for (unsigned i=0; i !=NumElems; ++i) {
17670 SDValue Op = Amt->getOperand(i);
17671 if (Op->getOpcode() == ISD::UNDEF) {
17672 Elts.push_back(Op);
17673 continue;
17674 }
17676 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
17677 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
17678 uint64_t ShAmt = C.getZExtValue();
17679 if (ShAmt >= SVTBits) {
17680 Elts.push_back(DAG.getUNDEF(SVT));
17681 continue;
17682 }
17683 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
17684 }
17685 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
17686 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
17687 }
17689 // Lower SHL with variable shift amount.
17690 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
17691 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
17693 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
17694 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
17695 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
17696 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
17697 }
17699 // If possible, lower this shift as a sequence of two shifts by
17700 // constant plus a MOVSS/MOVSD instead of scalarizing it.
17701 // Example:
17702 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
17703 //
17704 // Could be rewritten as:
17705 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
17706 //
17707 // The advantage is that the two shifts from the example would be
17708 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
17709 // the vector shift into four scalar shifts plus four pairs of vector
17710 // insert/extract.
17711 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
17712 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17713 unsigned TargetOpcode = X86ISD::MOVSS;
17714 bool CanBeSimplified;
17715 // The splat value for the first packed shift (the 'X' from the example).
17716 SDValue Amt1 = Amt->getOperand(0);
17717 // The splat value for the second packed shift (the 'Y' from the example).
17718 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
17719 Amt->getOperand(2);
17721 // See if it is possible to replace this node with a sequence of
17722 // two shifts followed by a MOVSS/MOVSD
17723 if (VT == MVT::v4i32) {
17724 // Check if it is legal to use a MOVSS.
17725 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
17726 Amt2 == Amt->getOperand(3);
17727 if (!CanBeSimplified) {
17728 // Otherwise, check if we can still simplify this node using a MOVSD.
17729 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
17730 Amt->getOperand(2) == Amt->getOperand(3);
17731 TargetOpcode = X86ISD::MOVSD;
17732 Amt2 = Amt->getOperand(2);
17733 }
17734 } else {
17735 // Do similar checks for the case where the machine value type
17736 // is MVT::v8i16.
17737 CanBeSimplified = Amt1 == Amt->getOperand(1);
17738 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
17739 CanBeSimplified = Amt2 == Amt->getOperand(i);
17741 if (!CanBeSimplified) {
17742 TargetOpcode = X86ISD::MOVSD;
17743 CanBeSimplified = true;
17744 Amt2 = Amt->getOperand(4);
17745 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
17746 CanBeSimplified = Amt1 == Amt->getOperand(i);
17747 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
17748 CanBeSimplified = Amt2 == Amt->getOperand(j);
17749 }
17750 }
17752 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
17753 isa<ConstantSDNode>(Amt2)) {
17754 // Replace this node with two shifts followed by a MOVSS/MOVSD.
17755 EVT CastVT = MVT::v4i32;
17756 SDValue Splat1 =
17757 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
17758 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
17759 SDValue Splat2 =
17760 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
17761 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
17762 if (TargetOpcode == X86ISD::MOVSD)
17763 CastVT = MVT::v2i64;
17764 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
17765 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
17766 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
17767 BitCast1, DAG);
17768 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
17769 }
17770 }
17772 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
17773 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
17775 // a = a << 5;
17776 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
17777 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
17779 // Turn 'a' into a mask suitable for VSELECT
17780 SDValue VSelM = DAG.getConstant(0x80, VT);
17781 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17782 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17784 SDValue CM1 = DAG.getConstant(0x0f, VT);
17785 SDValue CM2 = DAG.getConstant(0x3f, VT);
17787 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
17788 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
17789 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
17790 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
17791 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
17793 // a += a
17794 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
17795 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17796 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17798 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
17799 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
17800 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
17801 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
17802 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
17804 // a += a
17805 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
17806 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17807 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17809 // return VSELECT(r, r+r, a);
17810 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
17811 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
17812 return R;
17813 }
17815 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
17816 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
17817 // solution better.
17818 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
17819 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
17820 unsigned ExtOpc =
17821 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
17822 R = DAG.getNode(ExtOpc, dl, NewVT, R);
17823 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
17824 return DAG.getNode(ISD::TRUNCATE, dl, VT,
17825 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
17826 }
17828 // Decompose 256-bit shifts into smaller 128-bit shifts.
17829 if (VT.is256BitVector()) {
17830 unsigned NumElems = VT.getVectorNumElements();
17831 MVT EltVT = VT.getVectorElementType();
17832 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17834 // Extract the two vectors
17835 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
17836 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
17838 // Recreate the shift amount vectors
17839 SDValue Amt1, Amt2;
17840 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
17841 // Constant shift amount
17842 SmallVector<SDValue, 4> Amt1Csts;
17843 SmallVector<SDValue, 4> Amt2Csts;
17844 for (unsigned i = 0; i != NumElems/2; ++i)
17845 Amt1Csts.push_back(Amt->getOperand(i));
17846 for (unsigned i = NumElems/2; i != NumElems; ++i)
17847 Amt2Csts.push_back(Amt->getOperand(i));
17849 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
17850 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
17851 } else {
17852 // Variable shift amount
17853 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
17854 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
17855 }
17857 // Issue new vector shifts for the smaller types
17858 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
17859 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
17861 // Concatenate the result back
17862 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
17863 }
17865 return SDValue();
17866 }
17868 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
17869 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
17870 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
17871 // looks for this combo and may remove the "setcc" instruction if the "setcc"
17872 // has only one use.
17873 SDNode *N = Op.getNode();
17874 SDValue LHS = N->getOperand(0);
17875 SDValue RHS = N->getOperand(1);
17876 unsigned BaseOp = 0;
17877 unsigned Cond = 0;
17878 SDLoc DL(Op);
17879 switch (Op.getOpcode()) {
17880 default: llvm_unreachable("Unknown ovf instruction!");
17881 case ISD::SADDO:
17882 // A subtract of one will be selected as a INC. Note that INC doesn't
17883 // set CF, so we can't do this for UADDO.
17884 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17885 if (C->isOne()) {
17886 BaseOp = X86ISD::INC;
17887 Cond = X86::COND_O;
17888 break;
17889 }
17890 BaseOp = X86ISD::ADD;
17891 Cond = X86::COND_O;
17892 break;
17893 case ISD::UADDO:
17894 BaseOp = X86ISD::ADD;
17895 Cond = X86::COND_B;
17896 break;
17897 case ISD::SSUBO:
17898 // A subtract of one will be selected as a DEC. Note that DEC doesn't
17899 // set CF, so we can't do this for USUBO.
17900 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17901 if (C->isOne()) {
17902 BaseOp = X86ISD::DEC;
17903 Cond = X86::COND_O;
17904 break;
17905 }
17906 BaseOp = X86ISD::SUB;
17907 Cond = X86::COND_O;
17908 break;
17909 case ISD::USUBO:
17910 BaseOp = X86ISD::SUB;
17911 Cond = X86::COND_B;
17912 break;
17913 case ISD::SMULO:
17914 BaseOp = X86ISD::SMUL;
17915 Cond = X86::COND_O;
17916 break;
17917 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
17918 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
17919 MVT::i32);
17920 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
17922 SDValue SetCC =
17923 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17924 DAG.getConstant(X86::COND_O, MVT::i32),
17925 SDValue(Sum.getNode(), 2));
17927 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17928 }
17929 }
17931 // Also sets EFLAGS.
17932 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
17933 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
17935 SDValue SetCC =
17936 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
17937 DAG.getConstant(Cond, MVT::i32),
17938 SDValue(Sum.getNode(), 1));
17940 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17941 }
17943 // Sign extension of the low part of vector elements. This may be used either
17944 // when sign extend instructions are not available or if the vector element
17945 // sizes already match the sign-extended size. If the vector elements are in
17946 // their pre-extended size and sign extend instructions are available, that will
17947 // be handled by LowerSIGN_EXTEND.
17948 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
17949 SelectionDAG &DAG) const {
17950 SDLoc dl(Op);
17951 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
17952 MVT VT = Op.getSimpleValueType();
17954 if (!Subtarget->hasSSE2() || !VT.isVector())
17955 return SDValue();
17957 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
17958 ExtraVT.getScalarType().getSizeInBits();
17960 switch (VT.SimpleTy) {
17961 default: return SDValue();
17962 case MVT::v8i32:
17963 case MVT::v16i16:
17964 if (!Subtarget->hasFp256())
17965 return SDValue();
17966 if (!Subtarget->hasInt256()) {
17967 // needs to be split
17968 unsigned NumElems = VT.getVectorNumElements();
17970 // Extract the LHS vectors
17971 SDValue LHS = Op.getOperand(0);
17972 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17973 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17975 MVT EltVT = VT.getVectorElementType();
17976 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17978 EVT ExtraEltVT = ExtraVT.getVectorElementType();
17979 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
17980 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
17981 ExtraNumElems/2);
17982 SDValue Extra = DAG.getValueType(ExtraVT);
17984 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
17985 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
17987 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
17988 }
17989 // fall through
17990 case MVT::v4i32:
17991 case MVT::v8i16: {
17992 SDValue Op0 = Op.getOperand(0);
17994 // This is a sign extension of some low part of vector elements without
17995 // changing the size of the vector elements themselves:
17996 // Shift-Left + Shift-Right-Algebraic.
17997 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
17998 BitsDiff, DAG);
17999 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
18000 DAG);
18001 }
18002 }
18003 }
18005 /// Returns true if the operand type is exactly twice the native width, and
18006 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18007 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18008 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18009 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
18010 const X86Subtarget &Subtarget =
18011 getTargetMachine().getSubtarget<X86Subtarget>();
18012 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18014 if (OpWidth == 64)
18015 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18016 else if (OpWidth == 128)
18017 return Subtarget.hasCmpxchg16b();
18018 else
18019 return false;
18020 }
18022 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18023 return needsCmpXchgNb(SI->getValueOperand()->getType());
18024 }
18026 // Note: this turns large loads into lock cmpxchg8b/16b.
18027 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18028 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18029 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18030 return needsCmpXchgNb(PTy->getElementType());
18031 }
18033 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18034 const X86Subtarget &Subtarget =
18035 getTargetMachine().getSubtarget<X86Subtarget>();
18036 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18037 const Type *MemType = AI->getType();
18039 // If the operand is too big, we must see if cmpxchg8/16b is available
18040 // and default to library calls otherwise.
18041 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18042 return needsCmpXchgNb(MemType);
18044 AtomicRMWInst::BinOp Op = AI->getOperation();
18045 switch (Op) {
18046 default:
18047 llvm_unreachable("Unknown atomic operation");
18048 case AtomicRMWInst::Xchg:
18049 case AtomicRMWInst::Add:
18050 case AtomicRMWInst::Sub:
18051 // It's better to use xadd, xsub or xchg for these in all cases.
18052 return false;
18053 case AtomicRMWInst::Or:
18054 case AtomicRMWInst::And:
18055 case AtomicRMWInst::Xor:
18056 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18057 // prefix to a normal instruction for these operations.
18058 return !AI->use_empty();
18059 case AtomicRMWInst::Nand:
18060 case AtomicRMWInst::Max:
18061 case AtomicRMWInst::Min:
18062 case AtomicRMWInst::UMax:
18063 case AtomicRMWInst::UMin:
18064 // These always require a non-trivial set of data operations on x86. We must
18065 // use a cmpxchg loop.
18066 return true;
18067 }
18068 }
18070 static bool hasMFENCE(const X86Subtarget& Subtarget) {
18071 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
18072 // no-sse2). There isn't any reason to disable it if the target processor
18073 // supports it.
18074 return Subtarget.hasSSE2() || Subtarget.is64Bit();
18075 }
18077 LoadInst *
18078 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
18079 const X86Subtarget &Subtarget =
18080 getTargetMachine().getSubtarget<X86Subtarget>();
18081 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18082 const Type *MemType = AI->getType();
18083 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
18084 // there is no benefit in turning such RMWs into loads, and it is actually
18085 // harmful as it introduces a mfence.
18086 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18087 return nullptr;
18089 auto Builder = IRBuilder<>(AI);
18090 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
18091 auto SynchScope = AI->getSynchScope();
18092 // We must restrict the ordering to avoid generating loads with Release or
18093 // ReleaseAcquire orderings.
18094 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
18095 auto Ptr = AI->getPointerOperand();
18097 // Before the load we need a fence. Here is an example lifted from
18098 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
18099 // is required:
18100 // Thread 0:
18101 // x.store(1, relaxed);
18102 // r1 = y.fetch_add(0, release);
18103 // Thread 1:
18104 // y.fetch_add(42, acquire);
18105 // r2 = x.load(relaxed);
18106 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
18107 // lowered to just a load without a fence. A mfence flushes the store buffer,
18108 // making the optimization clearly correct.
18109 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
18110 // otherwise, we might be able to be more agressive on relaxed idempotent
18111 // rmw. In practice, they do not look useful, so we don't try to be
18112 // especially clever.
18113 if (SynchScope == SingleThread) {
18114 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
18115 // the IR level, so we must wrap it in an intrinsic.
18116 return nullptr;
18117 } else if (hasMFENCE(Subtarget)) {
18118 Function *MFence = llvm::Intrinsic::getDeclaration(M,
18119 Intrinsic::x86_sse2_mfence);
18120 Builder.CreateCall(MFence);
18121 } else {
18122 // FIXME: it might make sense to use a locked operation here but on a
18123 // different cache-line to prevent cache-line bouncing. In practice it
18124 // is probably a small win, and x86 processors without mfence are rare
18125 // enough that we do not bother.
18126 return nullptr;
18127 }
18129 // Finally we can emit the atomic load.
18130 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
18131 AI->getType()->getPrimitiveSizeInBits());
18132 Loaded->setAtomic(Order, SynchScope);
18133 AI->replaceAllUsesWith(Loaded);
18134 AI->eraseFromParent();
18135 return Loaded;
18136 }
18138 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
18139 SelectionDAG &DAG) {
18140 SDLoc dl(Op);
18141 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
18142 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
18143 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
18144 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
18146 // The only fence that needs an instruction is a sequentially-consistent
18147 // cross-thread fence.
18148 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
18149 if (hasMFENCE(*Subtarget))
18150 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
18152 SDValue Chain = Op.getOperand(0);
18153 SDValue Zero = DAG.getConstant(0, MVT::i32);
18154 SDValue Ops[] = {
18155 DAG.getRegister(X86::ESP, MVT::i32), // Base
18156 DAG.getTargetConstant(1, MVT::i8), // Scale
18157 DAG.getRegister(0, MVT::i32), // Index
18158 DAG.getTargetConstant(0, MVT::i32), // Disp
18159 DAG.getRegister(0, MVT::i32), // Segment.
18160 Zero,
18161 Chain
18162 };
18163 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
18164 return SDValue(Res, 0);
18165 }
18167 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
18168 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
18169 }
18171 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
18172 SelectionDAG &DAG) {
18173 MVT T = Op.getSimpleValueType();
18174 SDLoc DL(Op);
18175 unsigned Reg = 0;
18176 unsigned size = 0;
18177 switch(T.SimpleTy) {
18178 default: llvm_unreachable("Invalid value type!");
18179 case MVT::i8: Reg = X86::AL; size = 1; break;
18180 case MVT::i16: Reg = X86::AX; size = 2; break;
18181 case MVT::i32: Reg = X86::EAX; size = 4; break;
18182 case MVT::i64:
18183 assert(Subtarget->is64Bit() && "Node not type legal!");
18184 Reg = X86::RAX; size = 8;
18185 break;
18186 }
18187 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
18188 Op.getOperand(2), SDValue());
18189 SDValue Ops[] = { cpIn.getValue(0),
18190 Op.getOperand(1),
18191 Op.getOperand(3),
18192 DAG.getTargetConstant(size, MVT::i8),
18193 cpIn.getValue(1) };
18194 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18195 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
18196 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
18197 Ops, T, MMO);
18199 SDValue cpOut =
18200 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
18201 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
18202 MVT::i32, cpOut.getValue(2));
18203 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
18204 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
18206 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
18207 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
18208 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
18209 return SDValue();
18210 }
18212 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
18213 SelectionDAG &DAG) {
18214 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
18215 MVT DstVT = Op.getSimpleValueType();
18217 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
18218 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18219 if (DstVT != MVT::f64)
18220 // This conversion needs to be expanded.
18221 return SDValue();
18223 SDValue InVec = Op->getOperand(0);
18224 SDLoc dl(Op);
18225 unsigned NumElts = SrcVT.getVectorNumElements();
18226 EVT SVT = SrcVT.getVectorElementType();
18228 // Widen the vector in input in the case of MVT::v2i32.
18229 // Example: from MVT::v2i32 to MVT::v4i32.
18230 SmallVector<SDValue, 16> Elts;
18231 for (unsigned i = 0, e = NumElts; i != e; ++i)
18232 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
18233 DAG.getIntPtrConstant(i)));
18235 // Explicitly mark the extra elements as Undef.
18236 SDValue Undef = DAG.getUNDEF(SVT);
18237 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
18238 Elts.push_back(Undef);
18240 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18241 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
18242 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
18243 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
18244 DAG.getIntPtrConstant(0));
18245 }
18247 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
18248 Subtarget->hasMMX() && "Unexpected custom BITCAST");
18249 assert((DstVT == MVT::i64 ||
18250 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
18251 "Unexpected custom BITCAST");
18252 // i64 <=> MMX conversions are Legal.
18253 if (SrcVT==MVT::i64 && DstVT.isVector())
18254 return Op;
18255 if (DstVT==MVT::i64 && SrcVT.isVector())
18256 return Op;
18257 // MMX <=> MMX conversions are Legal.
18258 if (SrcVT.isVector() && DstVT.isVector())
18259 return Op;
18260 // All other conversions need to be expanded.
18261 return SDValue();
18262 }
18264 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
18265 SDNode *Node = Op.getNode();
18266 SDLoc dl(Node);
18267 EVT T = Node->getValueType(0);
18268 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
18269 DAG.getConstant(0, T), Node->getOperand(2));
18270 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
18271 cast<AtomicSDNode>(Node)->getMemoryVT(),
18272 Node->getOperand(0),
18273 Node->getOperand(1), negOp,
18274 cast<AtomicSDNode>(Node)->getMemOperand(),
18275 cast<AtomicSDNode>(Node)->getOrdering(),
18276 cast<AtomicSDNode>(Node)->getSynchScope());
18277 }
18279 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
18280 SDNode *Node = Op.getNode();
18281 SDLoc dl(Node);
18282 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
18284 // Convert seq_cst store -> xchg
18285 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
18286 // FIXME: On 32-bit, store -> fist or movq would be more efficient
18287 // (The only way to get a 16-byte store is cmpxchg16b)
18288 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
18289 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
18290 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
18291 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
18292 cast<AtomicSDNode>(Node)->getMemoryVT(),
18293 Node->getOperand(0),
18294 Node->getOperand(1), Node->getOperand(2),
18295 cast<AtomicSDNode>(Node)->getMemOperand(),
18296 cast<AtomicSDNode>(Node)->getOrdering(),
18297 cast<AtomicSDNode>(Node)->getSynchScope());
18298 return Swap.getValue(1);
18299 }
18300 // Other atomic stores have a simple pattern.
18301 return Op;
18302 }
18304 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
18305 EVT VT = Op.getNode()->getSimpleValueType(0);
18307 // Let legalize expand this if it isn't a legal type yet.
18308 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
18309 return SDValue();
18311 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
18313 unsigned Opc;
18314 bool ExtraOp = false;
18315 switch (Op.getOpcode()) {
18316 default: llvm_unreachable("Invalid code");
18317 case ISD::ADDC: Opc = X86ISD::ADD; break;
18318 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
18319 case ISD::SUBC: Opc = X86ISD::SUB; break;
18320 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
18321 }
18323 if (!ExtraOp)
18324 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18325 Op.getOperand(1));
18326 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18327 Op.getOperand(1), Op.getOperand(2));
18328 }
18330 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
18331 SelectionDAG &DAG) {
18332 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
18334 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
18335 // which returns the values as { float, float } (in XMM0) or
18336 // { double, double } (which is returned in XMM0, XMM1).
18337 SDLoc dl(Op);
18338 SDValue Arg = Op.getOperand(0);
18339 EVT ArgVT = Arg.getValueType();
18340 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18342 TargetLowering::ArgListTy Args;
18343 TargetLowering::ArgListEntry Entry;
18345 Entry.Node = Arg;
18346 Entry.Ty = ArgTy;
18347 Entry.isSExt = false;
18348 Entry.isZExt = false;
18349 Args.push_back(Entry);
18351 bool isF64 = ArgVT == MVT::f64;
18352 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
18353 // the small struct {f32, f32} is returned in (eax, edx). For f64,
18354 // the results are returned via SRet in memory.
18355 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
18356 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18357 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
18359 Type *RetTy = isF64
18360 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
18361 : (Type*)VectorType::get(ArgTy, 4);
18363 TargetLowering::CallLoweringInfo CLI(DAG);
18364 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
18365 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
18367 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
18369 if (isF64)
18370 // Returned in xmm0 and xmm1.
18371 return CallResult.first;
18373 // Returned in bits 0:31 and 32:64 xmm0.
18374 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18375 CallResult.first, DAG.getIntPtrConstant(0));
18376 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18377 CallResult.first, DAG.getIntPtrConstant(1));
18378 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
18379 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
18380 }
18382 /// LowerOperation - Provide custom lowering hooks for some operations.
18383 ///
18384 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
18385 switch (Op.getOpcode()) {
18386 default: llvm_unreachable("Should not custom lower this!");
18387 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
18388 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
18389 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
18390 return LowerCMP_SWAP(Op, Subtarget, DAG);
18391 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
18392 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
18393 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
18394 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
18395 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
18396 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
18397 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
18398 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
18399 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
18400 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
18401 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
18402 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
18403 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
18404 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
18405 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
18406 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
18407 case ISD::SHL_PARTS:
18408 case ISD::SRA_PARTS:
18409 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
18410 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
18411 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
18412 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
18413 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
18414 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
18415 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
18416 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
18417 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
18418 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
18419 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
18420 case ISD::FABS:
18421 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
18422 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
18423 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
18424 case ISD::SETCC: return LowerSETCC(Op, DAG);
18425 case ISD::SELECT: return LowerSELECT(Op, DAG);
18426 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
18427 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
18428 case ISD::VASTART: return LowerVASTART(Op, DAG);
18429 case ISD::VAARG: return LowerVAARG(Op, DAG);
18430 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
18431 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
18432 case ISD::INTRINSIC_VOID:
18433 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
18434 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
18435 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
18436 case ISD::FRAME_TO_ARGS_OFFSET:
18437 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
18438 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
18439 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
18440 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
18441 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
18442 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
18443 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
18444 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
18445 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
18446 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
18447 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
18448 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
18449 case ISD::UMUL_LOHI:
18450 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
18451 case ISD::SRA:
18452 case ISD::SRL:
18453 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
18454 case ISD::SADDO:
18455 case ISD::UADDO:
18456 case ISD::SSUBO:
18457 case ISD::USUBO:
18458 case ISD::SMULO:
18459 case ISD::UMULO: return LowerXALUO(Op, DAG);
18460 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
18461 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
18462 case ISD::ADDC:
18463 case ISD::ADDE:
18464 case ISD::SUBC:
18465 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
18466 case ISD::ADD: return LowerADD(Op, DAG);
18467 case ISD::SUB: return LowerSUB(Op, DAG);
18468 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
18469 }
18470 }
18472 /// ReplaceNodeResults - Replace a node with an illegal result type
18473 /// with a new node built out of custom code.
18474 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
18475 SmallVectorImpl<SDValue>&Results,
18476 SelectionDAG &DAG) const {
18477 SDLoc dl(N);
18478 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18479 switch (N->getOpcode()) {
18480 default:
18481 llvm_unreachable("Do not know how to custom type legalize this operation!");
18482 case ISD::SIGN_EXTEND_INREG:
18483 case ISD::ADDC:
18484 case ISD::ADDE:
18485 case ISD::SUBC:
18486 case ISD::SUBE:
18487 // We don't want to expand or promote these.
18488 return;
18489 case ISD::SDIV:
18490 case ISD::UDIV:
18491 case ISD::SREM:
18492 case ISD::UREM:
18493 case ISD::SDIVREM:
18494 case ISD::UDIVREM: {
18495 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
18496 Results.push_back(V);
18497 return;
18498 }
18499 case ISD::FP_TO_SINT:
18500 case ISD::FP_TO_UINT: {
18501 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
18503 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
18504 return;
18506 std::pair<SDValue,SDValue> Vals =
18507 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
18508 SDValue FIST = Vals.first, StackSlot = Vals.second;
18509 if (FIST.getNode()) {
18510 EVT VT = N->getValueType(0);
18511 // Return a load from the stack slot.
18512 if (StackSlot.getNode())
18513 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
18514 MachinePointerInfo(),
18515 false, false, false, 0));
18516 else
18517 Results.push_back(FIST);
18518 }
18519 return;
18520 }
18521 case ISD::UINT_TO_FP: {
18522 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18523 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
18524 N->getValueType(0) != MVT::v2f32)
18525 return;
18526 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
18527 N->getOperand(0));
18528 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
18529 MVT::f64);
18530 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
18531 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
18532 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
18533 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
18534 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
18535 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
18536 return;
18537 }
18538 case ISD::FP_ROUND: {
18539 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
18540 return;
18541 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
18542 Results.push_back(V);
18543 return;
18544 }
18545 case ISD::INTRINSIC_W_CHAIN: {
18546 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
18547 switch (IntNo) {
18548 default : llvm_unreachable("Do not know how to custom type "
18549 "legalize this intrinsic operation!");
18550 case Intrinsic::x86_rdtsc:
18551 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18552 Results);
18553 case Intrinsic::x86_rdtscp:
18554 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
18555 Results);
18556 case Intrinsic::x86_rdpmc:
18557 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
18558 }
18559 }
18560 case ISD::READCYCLECOUNTER: {
18561 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18562 Results);
18563 }
18564 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
18565 EVT T = N->getValueType(0);
18566 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
18567 bool Regs64bit = T == MVT::i128;
18568 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
18569 SDValue cpInL, cpInH;
18570 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18571 DAG.getConstant(0, HalfT));
18572 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18573 DAG.getConstant(1, HalfT));
18574 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
18575 Regs64bit ? X86::RAX : X86::EAX,
18576 cpInL, SDValue());
18577 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
18578 Regs64bit ? X86::RDX : X86::EDX,
18579 cpInH, cpInL.getValue(1));
18580 SDValue swapInL, swapInH;
18581 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18582 DAG.getConstant(0, HalfT));
18583 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18584 DAG.getConstant(1, HalfT));
18585 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
18586 Regs64bit ? X86::RBX : X86::EBX,
18587 swapInL, cpInH.getValue(1));
18588 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
18589 Regs64bit ? X86::RCX : X86::ECX,
18590 swapInH, swapInL.getValue(1));
18591 SDValue Ops[] = { swapInH.getValue(0),
18592 N->getOperand(1),
18593 swapInH.getValue(1) };
18594 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18595 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
18596 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
18597 X86ISD::LCMPXCHG8_DAG;
18598 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
18599 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
18600 Regs64bit ? X86::RAX : X86::EAX,
18601 HalfT, Result.getValue(1));
18602 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
18603 Regs64bit ? X86::RDX : X86::EDX,
18604 HalfT, cpOutL.getValue(2));
18605 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
18607 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
18608 MVT::i32, cpOutH.getValue(2));
18609 SDValue Success =
18610 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
18611 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
18612 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
18614 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
18615 Results.push_back(Success);
18616 Results.push_back(EFLAGS.getValue(1));
18617 return;
18618 }
18619 case ISD::ATOMIC_SWAP:
18620 case ISD::ATOMIC_LOAD_ADD:
18621 case ISD::ATOMIC_LOAD_SUB:
18622 case ISD::ATOMIC_LOAD_AND:
18623 case ISD::ATOMIC_LOAD_OR:
18624 case ISD::ATOMIC_LOAD_XOR:
18625 case ISD::ATOMIC_LOAD_NAND:
18626 case ISD::ATOMIC_LOAD_MIN:
18627 case ISD::ATOMIC_LOAD_MAX:
18628 case ISD::ATOMIC_LOAD_UMIN:
18629 case ISD::ATOMIC_LOAD_UMAX:
18630 case ISD::ATOMIC_LOAD: {
18631 // Delegate to generic TypeLegalization. Situations we can really handle
18632 // should have already been dealt with by AtomicExpandPass.cpp.
18633 break;
18634 }
18635 case ISD::BITCAST: {
18636 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18637 EVT DstVT = N->getValueType(0);
18638 EVT SrcVT = N->getOperand(0)->getValueType(0);
18640 if (SrcVT != MVT::f64 ||
18641 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
18642 return;
18644 unsigned NumElts = DstVT.getVectorNumElements();
18645 EVT SVT = DstVT.getVectorElementType();
18646 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18647 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
18648 MVT::v2f64, N->getOperand(0));
18649 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
18651 if (ExperimentalVectorWideningLegalization) {
18652 // If we are legalizing vectors by widening, we already have the desired
18653 // legal vector type, just return it.
18654 Results.push_back(ToVecInt);
18655 return;
18656 }
18658 SmallVector<SDValue, 8> Elts;
18659 for (unsigned i = 0, e = NumElts; i != e; ++i)
18660 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
18661 ToVecInt, DAG.getIntPtrConstant(i)));
18663 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
18664 }
18665 }
18666 }
18668 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
18669 switch (Opcode) {
18670 default: return nullptr;
18671 case X86ISD::BSF: return "X86ISD::BSF";
18672 case X86ISD::BSR: return "X86ISD::BSR";
18673 case X86ISD::SHLD: return "X86ISD::SHLD";
18674 case X86ISD::SHRD: return "X86ISD::SHRD";
18675 case X86ISD::FAND: return "X86ISD::FAND";
18676 case X86ISD::FANDN: return "X86ISD::FANDN";
18677 case X86ISD::FOR: return "X86ISD::FOR";
18678 case X86ISD::FXOR: return "X86ISD::FXOR";
18679 case X86ISD::FSRL: return "X86ISD::FSRL";
18680 case X86ISD::FILD: return "X86ISD::FILD";
18681 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
18682 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
18683 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
18684 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
18685 case X86ISD::FLD: return "X86ISD::FLD";
18686 case X86ISD::FST: return "X86ISD::FST";
18687 case X86ISD::CALL: return "X86ISD::CALL";
18688 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
18689 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
18690 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
18691 case X86ISD::BT: return "X86ISD::BT";
18692 case X86ISD::CMP: return "X86ISD::CMP";
18693 case X86ISD::COMI: return "X86ISD::COMI";
18694 case X86ISD::UCOMI: return "X86ISD::UCOMI";
18695 case X86ISD::CMPM: return "X86ISD::CMPM";
18696 case X86ISD::CMPMU: return "X86ISD::CMPMU";
18697 case X86ISD::SETCC: return "X86ISD::SETCC";
18698 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
18699 case X86ISD::FSETCC: return "X86ISD::FSETCC";
18700 case X86ISD::CMOV: return "X86ISD::CMOV";
18701 case X86ISD::BRCOND: return "X86ISD::BRCOND";
18702 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
18703 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
18704 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
18705 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
18706 case X86ISD::Wrapper: return "X86ISD::Wrapper";
18707 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
18708 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
18709 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
18710 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
18711 case X86ISD::PINSRB: return "X86ISD::PINSRB";
18712 case X86ISD::PINSRW: return "X86ISD::PINSRW";
18713 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
18714 case X86ISD::ANDNP: return "X86ISD::ANDNP";
18715 case X86ISD::PSIGN: return "X86ISD::PSIGN";
18716 case X86ISD::BLENDI: return "X86ISD::BLENDI";
18717 case X86ISD::SUBUS: return "X86ISD::SUBUS";
18718 case X86ISD::HADD: return "X86ISD::HADD";
18719 case X86ISD::HSUB: return "X86ISD::HSUB";
18720 case X86ISD::FHADD: return "X86ISD::FHADD";
18721 case X86ISD::FHSUB: return "X86ISD::FHSUB";
18722 case X86ISD::UMAX: return "X86ISD::UMAX";
18723 case X86ISD::UMIN: return "X86ISD::UMIN";
18724 case X86ISD::SMAX: return "X86ISD::SMAX";
18725 case X86ISD::SMIN: return "X86ISD::SMIN";
18726 case X86ISD::FMAX: return "X86ISD::FMAX";
18727 case X86ISD::FMIN: return "X86ISD::FMIN";
18728 case X86ISD::FMAXC: return "X86ISD::FMAXC";
18729 case X86ISD::FMINC: return "X86ISD::FMINC";
18730 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
18731 case X86ISD::FRCP: return "X86ISD::FRCP";
18732 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
18733 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
18734 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
18735 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
18736 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
18737 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
18738 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
18739 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
18740 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
18741 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
18742 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
18743 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
18744 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
18745 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
18746 case X86ISD::VZEXT: return "X86ISD::VZEXT";
18747 case X86ISD::VSEXT: return "X86ISD::VSEXT";
18748 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
18749 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
18750 case X86ISD::VINSERT: return "X86ISD::VINSERT";
18751 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
18752 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
18753 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
18754 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
18755 case X86ISD::VSHL: return "X86ISD::VSHL";
18756 case X86ISD::VSRL: return "X86ISD::VSRL";
18757 case X86ISD::VSRA: return "X86ISD::VSRA";
18758 case X86ISD::VSHLI: return "X86ISD::VSHLI";
18759 case X86ISD::VSRLI: return "X86ISD::VSRLI";
18760 case X86ISD::VSRAI: return "X86ISD::VSRAI";
18761 case X86ISD::CMPP: return "X86ISD::CMPP";
18762 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
18763 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
18764 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
18765 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
18766 case X86ISD::ADD: return "X86ISD::ADD";
18767 case X86ISD::SUB: return "X86ISD::SUB";
18768 case X86ISD::ADC: return "X86ISD::ADC";
18769 case X86ISD::SBB: return "X86ISD::SBB";
18770 case X86ISD::SMUL: return "X86ISD::SMUL";
18771 case X86ISD::UMUL: return "X86ISD::UMUL";
18772 case X86ISD::INC: return "X86ISD::INC";
18773 case X86ISD::DEC: return "X86ISD::DEC";
18774 case X86ISD::OR: return "X86ISD::OR";
18775 case X86ISD::XOR: return "X86ISD::XOR";
18776 case X86ISD::AND: return "X86ISD::AND";
18777 case X86ISD::BEXTR: return "X86ISD::BEXTR";
18778 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
18779 case X86ISD::PTEST: return "X86ISD::PTEST";
18780 case X86ISD::TESTP: return "X86ISD::TESTP";
18781 case X86ISD::TESTM: return "X86ISD::TESTM";
18782 case X86ISD::TESTNM: return "X86ISD::TESTNM";
18783 case X86ISD::KORTEST: return "X86ISD::KORTEST";
18784 case X86ISD::PACKSS: return "X86ISD::PACKSS";
18785 case X86ISD::PACKUS: return "X86ISD::PACKUS";
18786 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
18787 case X86ISD::VALIGN: return "X86ISD::VALIGN";
18788 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
18789 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
18790 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
18791 case X86ISD::SHUFP: return "X86ISD::SHUFP";
18792 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
18793 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
18794 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
18795 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
18796 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
18797 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
18798 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
18799 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
18800 case X86ISD::MOVSD: return "X86ISD::MOVSD";
18801 case X86ISD::MOVSS: return "X86ISD::MOVSS";
18802 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
18803 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
18804 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
18805 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
18806 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
18807 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
18808 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
18809 case X86ISD::VPERMV: return "X86ISD::VPERMV";
18810 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
18811 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
18812 case X86ISD::VPERMI: return "X86ISD::VPERMI";
18813 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
18814 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
18815 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
18816 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
18817 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
18818 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
18819 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
18820 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
18821 case X86ISD::SAHF: return "X86ISD::SAHF";
18822 case X86ISD::RDRAND: return "X86ISD::RDRAND";
18823 case X86ISD::RDSEED: return "X86ISD::RDSEED";
18824 case X86ISD::FMADD: return "X86ISD::FMADD";
18825 case X86ISD::FMSUB: return "X86ISD::FMSUB";
18826 case X86ISD::FNMADD: return "X86ISD::FNMADD";
18827 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
18828 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
18829 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
18830 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
18831 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
18832 case X86ISD::XTEST: return "X86ISD::XTEST";
18833 }
18834 }
18836 // isLegalAddressingMode - Return true if the addressing mode represented
18837 // by AM is legal for this target, for a load/store of the specified type.
18838 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
18839 Type *Ty) const {
18840 // X86 supports extremely general addressing modes.
18841 CodeModel::Model M = getTargetMachine().getCodeModel();
18842 Reloc::Model R = getTargetMachine().getRelocationModel();
18844 // X86 allows a sign-extended 32-bit immediate field as a displacement.
18845 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
18846 return false;
18848 if (AM.BaseGV) {
18849 unsigned GVFlags =
18850 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
18852 // If a reference to this global requires an extra load, we can't fold it.
18853 if (isGlobalStubReference(GVFlags))
18854 return false;
18856 // If BaseGV requires a register for the PIC base, we cannot also have a
18857 // BaseReg specified.
18858 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
18859 return false;
18861 // If lower 4G is not available, then we must use rip-relative addressing.
18862 if ((M != CodeModel::Small || R != Reloc::Static) &&
18863 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
18864 return false;
18865 }
18867 switch (AM.Scale) {
18868 case 0:
18869 case 1:
18870 case 2:
18871 case 4:
18872 case 8:
18873 // These scales always work.
18874 break;
18875 case 3:
18876 case 5:
18877 case 9:
18878 // These scales are formed with basereg+scalereg. Only accept if there is
18879 // no basereg yet.
18880 if (AM.HasBaseReg)
18881 return false;
18882 break;
18883 default: // Other stuff never works.
18884 return false;
18885 }
18887 return true;
18888 }
18890 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
18891 unsigned Bits = Ty->getScalarSizeInBits();
18893 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
18894 // particularly cheaper than those without.
18895 if (Bits == 8)
18896 return false;
18898 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
18899 // variable shifts just as cheap as scalar ones.
18900 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
18901 return false;
18903 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
18904 // fully general vector.
18905 return true;
18906 }
18908 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
18909 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18910 return false;
18911 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
18912 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
18913 return NumBits1 > NumBits2;
18914 }
18916 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
18917 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18918 return false;
18920 if (!isTypeLegal(EVT::getEVT(Ty1)))
18921 return false;
18923 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
18925 // Assuming the caller doesn't have a zeroext or signext return parameter,
18926 // truncation all the way down to i1 is valid.
18927 return true;
18928 }
18930 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
18931 return isInt<32>(Imm);
18932 }
18934 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
18935 // Can also use sub to handle negated immediates.
18936 return isInt<32>(Imm);
18937 }
18939 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
18940 if (!VT1.isInteger() || !VT2.isInteger())
18941 return false;
18942 unsigned NumBits1 = VT1.getSizeInBits();
18943 unsigned NumBits2 = VT2.getSizeInBits();
18944 return NumBits1 > NumBits2;
18945 }
18947 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
18948 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18949 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
18950 }
18952 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
18953 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18954 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
18955 }
18957 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
18958 EVT VT1 = Val.getValueType();
18959 if (isZExtFree(VT1, VT2))
18960 return true;
18962 if (Val.getOpcode() != ISD::LOAD)
18963 return false;
18965 if (!VT1.isSimple() || !VT1.isInteger() ||
18966 !VT2.isSimple() || !VT2.isInteger())
18967 return false;
18969 switch (VT1.getSimpleVT().SimpleTy) {
18970 default: break;
18971 case MVT::i8:
18972 case MVT::i16:
18973 case MVT::i32:
18974 // X86 has 8, 16, and 32-bit zero-extending loads.
18975 return true;
18976 }
18978 return false;
18979 }
18981 bool
18982 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
18983 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
18984 return false;
18986 VT = VT.getScalarType();
18988 if (!VT.isSimple())
18989 return false;
18991 switch (VT.getSimpleVT().SimpleTy) {
18992 case MVT::f32:
18993 case MVT::f64:
18994 return true;
18995 default:
18996 break;
18997 }
18999 return false;
19000 }
19002 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
19003 // i16 instructions are longer (0x66 prefix) and potentially slower.
19004 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
19005 }
19007 /// isShuffleMaskLegal - Targets can use this to indicate that they only
19008 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
19009 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
19010 /// are assumed to be legal.
19011 bool
19012 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
19013 EVT VT) const {
19014 if (!VT.isSimple())
19015 return false;
19017 MVT SVT = VT.getSimpleVT();
19019 // Very little shuffling can be done for 64-bit vectors right now.
19020 if (VT.getSizeInBits() == 64)
19021 return false;
19023 // If this is a single-input shuffle with no 128 bit lane crossings we can
19024 // lower it into pshufb.
19025 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
19026 (SVT.is256BitVector() && Subtarget->hasInt256())) {
19027 bool isLegal = true;
19028 for (unsigned I = 0, E = M.size(); I != E; ++I) {
19029 if (M[I] >= (int)SVT.getVectorNumElements() ||
19030 ShuffleCrosses128bitLane(SVT, I, M[I])) {
19031 isLegal = false;
19032 break;
19033 }
19034 }
19035 if (isLegal)
19036 return true;
19037 }
19039 // FIXME: blends, shifts.
19040 return (SVT.getVectorNumElements() == 2 ||
19041 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
19042 isMOVLMask(M, SVT) ||
19043 isMOVHLPSMask(M, SVT) ||
19044 isSHUFPMask(M, SVT) ||
19045 isPSHUFDMask(M, SVT) ||
19046 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
19047 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
19048 isPALIGNRMask(M, SVT, Subtarget) ||
19049 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
19050 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
19051 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19052 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19053 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()));
19054 }
19056 bool
19057 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
19058 EVT VT) const {
19059 if (!VT.isSimple())
19060 return false;
19062 MVT SVT = VT.getSimpleVT();
19063 unsigned NumElts = SVT.getVectorNumElements();
19064 // FIXME: This collection of masks seems suspect.
19065 if (NumElts == 2)
19066 return true;
19067 if (NumElts == 4 && SVT.is128BitVector()) {
19068 return (isMOVLMask(Mask, SVT) ||
19069 isCommutedMOVLMask(Mask, SVT, true) ||
19070 isSHUFPMask(Mask, SVT) ||
19071 isSHUFPMask(Mask, SVT, /* Commuted */ true));
19072 }
19073 return false;
19074 }
19076 //===----------------------------------------------------------------------===//
19077 // X86 Scheduler Hooks
19078 //===----------------------------------------------------------------------===//
19080 /// Utility function to emit xbegin specifying the start of an RTM region.
19081 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
19082 const TargetInstrInfo *TII) {
19083 DebugLoc DL = MI->getDebugLoc();
19085 const BasicBlock *BB = MBB->getBasicBlock();
19086 MachineFunction::iterator I = MBB;
19087 ++I;
19089 // For the v = xbegin(), we generate
19090 //
19091 // thisMBB:
19092 // xbegin sinkMBB
19093 //
19094 // mainMBB:
19095 // eax = -1
19096 //
19097 // sinkMBB:
19098 // v = eax
19100 MachineBasicBlock *thisMBB = MBB;
19101 MachineFunction *MF = MBB->getParent();
19102 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19103 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19104 MF->insert(I, mainMBB);
19105 MF->insert(I, sinkMBB);
19107 // Transfer the remainder of BB and its successor edges to sinkMBB.
19108 sinkMBB->splice(sinkMBB->begin(), MBB,
19109 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19110 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19112 // thisMBB:
19113 // xbegin sinkMBB
19114 // # fallthrough to mainMBB
19115 // # abortion to sinkMBB
19116 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
19117 thisMBB->addSuccessor(mainMBB);
19118 thisMBB->addSuccessor(sinkMBB);
19120 // mainMBB:
19121 // EAX = -1
19122 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
19123 mainMBB->addSuccessor(sinkMBB);
19125 // sinkMBB:
19126 // EAX is live into the sinkMBB
19127 sinkMBB->addLiveIn(X86::EAX);
19128 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19129 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19130 .addReg(X86::EAX);
19132 MI->eraseFromParent();
19133 return sinkMBB;
19134 }
19136 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
19137 // or XMM0_V32I8 in AVX all of this code can be replaced with that
19138 // in the .td file.
19139 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
19140 const TargetInstrInfo *TII) {
19141 unsigned Opc;
19142 switch (MI->getOpcode()) {
19143 default: llvm_unreachable("illegal opcode!");
19144 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
19145 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
19146 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
19147 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
19148 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
19149 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
19150 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
19151 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
19152 }
19154 DebugLoc dl = MI->getDebugLoc();
19155 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19157 unsigned NumArgs = MI->getNumOperands();
19158 for (unsigned i = 1; i < NumArgs; ++i) {
19159 MachineOperand &Op = MI->getOperand(i);
19160 if (!(Op.isReg() && Op.isImplicit()))
19161 MIB.addOperand(Op);
19162 }
19163 if (MI->hasOneMemOperand())
19164 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19166 BuildMI(*BB, MI, dl,
19167 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19168 .addReg(X86::XMM0);
19170 MI->eraseFromParent();
19171 return BB;
19172 }
19174 // FIXME: Custom handling because TableGen doesn't support multiple implicit
19175 // defs in an instruction pattern
19176 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
19177 const TargetInstrInfo *TII) {
19178 unsigned Opc;
19179 switch (MI->getOpcode()) {
19180 default: llvm_unreachable("illegal opcode!");
19181 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
19182 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
19183 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
19184 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
19185 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
19186 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
19187 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
19188 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
19189 }
19191 DebugLoc dl = MI->getDebugLoc();
19192 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19194 unsigned NumArgs = MI->getNumOperands(); // remove the results
19195 for (unsigned i = 1; i < NumArgs; ++i) {
19196 MachineOperand &Op = MI->getOperand(i);
19197 if (!(Op.isReg() && Op.isImplicit()))
19198 MIB.addOperand(Op);
19199 }
19200 if (MI->hasOneMemOperand())
19201 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19203 BuildMI(*BB, MI, dl,
19204 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19205 .addReg(X86::ECX);
19207 MI->eraseFromParent();
19208 return BB;
19209 }
19211 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
19212 const TargetInstrInfo *TII,
19213 const X86Subtarget* Subtarget) {
19214 DebugLoc dl = MI->getDebugLoc();
19216 // Address into RAX/EAX, other two args into ECX, EDX.
19217 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
19218 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
19219 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
19220 for (int i = 0; i < X86::AddrNumOperands; ++i)
19221 MIB.addOperand(MI->getOperand(i));
19223 unsigned ValOps = X86::AddrNumOperands;
19224 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
19225 .addReg(MI->getOperand(ValOps).getReg());
19226 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
19227 .addReg(MI->getOperand(ValOps+1).getReg());
19229 // The instruction doesn't actually take any operands though.
19230 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
19232 MI->eraseFromParent(); // The pseudo is gone now.
19233 return BB;
19234 }
19236 MachineBasicBlock *
19237 X86TargetLowering::EmitVAARG64WithCustomInserter(
19238 MachineInstr *MI,
19239 MachineBasicBlock *MBB) const {
19240 // Emit va_arg instruction on X86-64.
19242 // Operands to this pseudo-instruction:
19243 // 0 ) Output : destination address (reg)
19244 // 1-5) Input : va_list address (addr, i64mem)
19245 // 6 ) ArgSize : Size (in bytes) of vararg type
19246 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
19247 // 8 ) Align : Alignment of type
19248 // 9 ) EFLAGS (implicit-def)
19250 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
19251 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
19253 unsigned DestReg = MI->getOperand(0).getReg();
19254 MachineOperand &Base = MI->getOperand(1);
19255 MachineOperand &Scale = MI->getOperand(2);
19256 MachineOperand &Index = MI->getOperand(3);
19257 MachineOperand &Disp = MI->getOperand(4);
19258 MachineOperand &Segment = MI->getOperand(5);
19259 unsigned ArgSize = MI->getOperand(6).getImm();
19260 unsigned ArgMode = MI->getOperand(7).getImm();
19261 unsigned Align = MI->getOperand(8).getImm();
19263 // Memory Reference
19264 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
19265 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19266 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19268 // Machine Information
19269 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
19270 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
19271 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
19272 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
19273 DebugLoc DL = MI->getDebugLoc();
19275 // struct va_list {
19276 // i32 gp_offset
19277 // i32 fp_offset
19278 // i64 overflow_area (address)
19279 // i64 reg_save_area (address)
19280 // }
19281 // sizeof(va_list) = 24
19282 // alignment(va_list) = 8
19284 unsigned TotalNumIntRegs = 6;
19285 unsigned TotalNumXMMRegs = 8;
19286 bool UseGPOffset = (ArgMode == 1);
19287 bool UseFPOffset = (ArgMode == 2);
19288 unsigned MaxOffset = TotalNumIntRegs * 8 +
19289 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
19291 /* Align ArgSize to a multiple of 8 */
19292 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
19293 bool NeedsAlign = (Align > 8);
19295 MachineBasicBlock *thisMBB = MBB;
19296 MachineBasicBlock *overflowMBB;
19297 MachineBasicBlock *offsetMBB;
19298 MachineBasicBlock *endMBB;
19300 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
19301 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
19302 unsigned OffsetReg = 0;
19304 if (!UseGPOffset && !UseFPOffset) {
19305 // If we only pull from the overflow region, we don't create a branch.
19306 // We don't need to alter control flow.
19307 OffsetDestReg = 0; // unused
19308 OverflowDestReg = DestReg;
19310 offsetMBB = nullptr;
19311 overflowMBB = thisMBB;
19312 endMBB = thisMBB;
19313 } else {
19314 // First emit code to check if gp_offset (or fp_offset) is below the bound.
19315 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
19316 // If not, pull from overflow_area. (branch to overflowMBB)
19317 //
19318 // thisMBB
19319 // | .
19320 // | .
19321 // offsetMBB overflowMBB
19322 // | .
19323 // | .
19324 // endMBB
19326 // Registers for the PHI in endMBB
19327 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
19328 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
19330 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19331 MachineFunction *MF = MBB->getParent();
19332 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19333 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19334 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19336 MachineFunction::iterator MBBIter = MBB;
19337 ++MBBIter;
19339 // Insert the new basic blocks
19340 MF->insert(MBBIter, offsetMBB);
19341 MF->insert(MBBIter, overflowMBB);
19342 MF->insert(MBBIter, endMBB);
19344 // Transfer the remainder of MBB and its successor edges to endMBB.
19345 endMBB->splice(endMBB->begin(), thisMBB,
19346 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
19347 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
19349 // Make offsetMBB and overflowMBB successors of thisMBB
19350 thisMBB->addSuccessor(offsetMBB);
19351 thisMBB->addSuccessor(overflowMBB);
19353 // endMBB is a successor of both offsetMBB and overflowMBB
19354 offsetMBB->addSuccessor(endMBB);
19355 overflowMBB->addSuccessor(endMBB);
19357 // Load the offset value into a register
19358 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19359 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
19360 .addOperand(Base)
19361 .addOperand(Scale)
19362 .addOperand(Index)
19363 .addDisp(Disp, UseFPOffset ? 4 : 0)
19364 .addOperand(Segment)
19365 .setMemRefs(MMOBegin, MMOEnd);
19367 // Check if there is enough room left to pull this argument.
19368 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
19369 .addReg(OffsetReg)
19370 .addImm(MaxOffset + 8 - ArgSizeA8);
19372 // Branch to "overflowMBB" if offset >= max
19373 // Fall through to "offsetMBB" otherwise
19374 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
19375 .addMBB(overflowMBB);
19376 }
19378 // In offsetMBB, emit code to use the reg_save_area.
19379 if (offsetMBB) {
19380 assert(OffsetReg != 0);
19382 // Read the reg_save_area address.
19383 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
19384 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
19385 .addOperand(Base)
19386 .addOperand(Scale)
19387 .addOperand(Index)
19388 .addDisp(Disp, 16)
19389 .addOperand(Segment)
19390 .setMemRefs(MMOBegin, MMOEnd);
19392 // Zero-extend the offset
19393 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
19394 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
19395 .addImm(0)
19396 .addReg(OffsetReg)
19397 .addImm(X86::sub_32bit);
19399 // Add the offset to the reg_save_area to get the final address.
19400 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
19401 .addReg(OffsetReg64)
19402 .addReg(RegSaveReg);
19404 // Compute the offset for the next argument
19405 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19406 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
19407 .addReg(OffsetReg)
19408 .addImm(UseFPOffset ? 16 : 8);
19410 // Store it back into the va_list.
19411 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
19412 .addOperand(Base)
19413 .addOperand(Scale)
19414 .addOperand(Index)
19415 .addDisp(Disp, UseFPOffset ? 4 : 0)
19416 .addOperand(Segment)
19417 .addReg(NextOffsetReg)
19418 .setMemRefs(MMOBegin, MMOEnd);
19420 // Jump to endMBB
19421 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
19422 .addMBB(endMBB);
19423 }
19425 //
19426 // Emit code to use overflow area
19427 //
19429 // Load the overflow_area address into a register.
19430 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
19431 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
19432 .addOperand(Base)
19433 .addOperand(Scale)
19434 .addOperand(Index)
19435 .addDisp(Disp, 8)
19436 .addOperand(Segment)
19437 .setMemRefs(MMOBegin, MMOEnd);
19439 // If we need to align it, do so. Otherwise, just copy the address
19440 // to OverflowDestReg.
19441 if (NeedsAlign) {
19442 // Align the overflow address
19443 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
19444 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
19446 // aligned_addr = (addr + (align-1)) & ~(align-1)
19447 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
19448 .addReg(OverflowAddrReg)
19449 .addImm(Align-1);
19451 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
19452 .addReg(TmpReg)
19453 .addImm(~(uint64_t)(Align-1));
19454 } else {
19455 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
19456 .addReg(OverflowAddrReg);
19457 }
19459 // Compute the next overflow address after this argument.
19460 // (the overflow address should be kept 8-byte aligned)
19461 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
19462 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
19463 .addReg(OverflowDestReg)
19464 .addImm(ArgSizeA8);
19466 // Store the new overflow address.
19467 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
19468 .addOperand(Base)
19469 .addOperand(Scale)
19470 .addOperand(Index)
19471 .addDisp(Disp, 8)
19472 .addOperand(Segment)
19473 .addReg(NextAddrReg)
19474 .setMemRefs(MMOBegin, MMOEnd);
19476 // If we branched, emit the PHI to the front of endMBB.
19477 if (offsetMBB) {
19478 BuildMI(*endMBB, endMBB->begin(), DL,
19479 TII->get(X86::PHI), DestReg)
19480 .addReg(OffsetDestReg).addMBB(offsetMBB)
19481 .addReg(OverflowDestReg).addMBB(overflowMBB);
19482 }
19484 // Erase the pseudo instruction
19485 MI->eraseFromParent();
19487 return endMBB;
19488 }
19490 MachineBasicBlock *
19491 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
19492 MachineInstr *MI,
19493 MachineBasicBlock *MBB) const {
19494 // Emit code to save XMM registers to the stack. The ABI says that the
19495 // number of registers to save is given in %al, so it's theoretically
19496 // possible to do an indirect jump trick to avoid saving all of them,
19497 // however this code takes a simpler approach and just executes all
19498 // of the stores if %al is non-zero. It's less code, and it's probably
19499 // easier on the hardware branch predictor, and stores aren't all that
19500 // expensive anyway.
19502 // Create the new basic blocks. One block contains all the XMM stores,
19503 // and one block is the final destination regardless of whether any
19504 // stores were performed.
19505 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19506 MachineFunction *F = MBB->getParent();
19507 MachineFunction::iterator MBBIter = MBB;
19508 ++MBBIter;
19509 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
19510 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
19511 F->insert(MBBIter, XMMSaveMBB);
19512 F->insert(MBBIter, EndMBB);
19514 // Transfer the remainder of MBB and its successor edges to EndMBB.
19515 EndMBB->splice(EndMBB->begin(), MBB,
19516 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19517 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
19519 // The original block will now fall through to the XMM save block.
19520 MBB->addSuccessor(XMMSaveMBB);
19521 // The XMMSaveMBB will fall through to the end block.
19522 XMMSaveMBB->addSuccessor(EndMBB);
19524 // Now add the instructions.
19525 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
19526 DebugLoc DL = MI->getDebugLoc();
19528 unsigned CountReg = MI->getOperand(0).getReg();
19529 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
19530 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
19532 if (!Subtarget->isTargetWin64()) {
19533 // If %al is 0, branch around the XMM save block.
19534 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
19535 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
19536 MBB->addSuccessor(EndMBB);
19537 }
19539 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
19540 // that was just emitted, but clearly shouldn't be "saved".
19541 assert((MI->getNumOperands() <= 3 ||
19542 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
19543 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
19544 && "Expected last argument to be EFLAGS");
19545 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
19546 // In the XMM save block, save all the XMM argument registers.
19547 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
19548 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
19549 MachineMemOperand *MMO =
19550 F->getMachineMemOperand(
19551 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
19552 MachineMemOperand::MOStore,
19553 /*Size=*/16, /*Align=*/16);
19554 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
19555 .addFrameIndex(RegSaveFrameIndex)
19556 .addImm(/*Scale=*/1)
19557 .addReg(/*IndexReg=*/0)
19558 .addImm(/*Disp=*/Offset)
19559 .addReg(/*Segment=*/0)
19560 .addReg(MI->getOperand(i).getReg())
19561 .addMemOperand(MMO);
19562 }
19564 MI->eraseFromParent(); // The pseudo instruction is gone now.
19566 return EndMBB;
19567 }
19569 // The EFLAGS operand of SelectItr might be missing a kill marker
19570 // because there were multiple uses of EFLAGS, and ISel didn't know
19571 // which to mark. Figure out whether SelectItr should have had a
19572 // kill marker, and set it if it should. Returns the correct kill
19573 // marker value.
19574 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
19575 MachineBasicBlock* BB,
19576 const TargetRegisterInfo* TRI) {
19577 // Scan forward through BB for a use/def of EFLAGS.
19578 MachineBasicBlock::iterator miI(std::next(SelectItr));
19579 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
19580 const MachineInstr& mi = *miI;
19581 if (mi.readsRegister(X86::EFLAGS))
19582 return false;
19583 if (mi.definesRegister(X86::EFLAGS))
19584 break; // Should have kill-flag - update below.
19585 }
19587 // If we hit the end of the block, check whether EFLAGS is live into a
19588 // successor.
19589 if (miI == BB->end()) {
19590 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
19591 sEnd = BB->succ_end();
19592 sItr != sEnd; ++sItr) {
19593 MachineBasicBlock* succ = *sItr;
19594 if (succ->isLiveIn(X86::EFLAGS))
19595 return false;
19596 }
19597 }
19599 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
19600 // out. SelectMI should have a kill flag on EFLAGS.
19601 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
19602 return true;
19603 }
19605 MachineBasicBlock *
19606 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
19607 MachineBasicBlock *BB) const {
19608 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
19609 DebugLoc DL = MI->getDebugLoc();
19611 // To "insert" a SELECT_CC instruction, we actually have to insert the
19612 // diamond control-flow pattern. The incoming instruction knows the
19613 // destination vreg to set, the condition code register to branch on, the
19614 // true/false values to select between, and a branch opcode to use.
19615 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19616 MachineFunction::iterator It = BB;
19617 ++It;
19619 // thisMBB:
19620 // ...
19621 // TrueVal = ...
19622 // cmpTY ccX, r1, r2
19623 // bCC copy1MBB
19624 // fallthrough --> copy0MBB
19625 MachineBasicBlock *thisMBB = BB;
19626 MachineFunction *F = BB->getParent();
19627 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
19628 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
19629 F->insert(It, copy0MBB);
19630 F->insert(It, sinkMBB);
19632 // If the EFLAGS register isn't dead in the terminator, then claim that it's
19633 // live into the sink and copy blocks.
19634 const TargetRegisterInfo *TRI =
19635 BB->getParent()->getSubtarget().getRegisterInfo();
19636 if (!MI->killsRegister(X86::EFLAGS) &&
19637 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
19638 copy0MBB->addLiveIn(X86::EFLAGS);
19639 sinkMBB->addLiveIn(X86::EFLAGS);
19640 }
19642 // Transfer the remainder of BB and its successor edges to sinkMBB.
19643 sinkMBB->splice(sinkMBB->begin(), BB,
19644 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19645 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
19647 // Add the true and fallthrough blocks as its successors.
19648 BB->addSuccessor(copy0MBB);
19649 BB->addSuccessor(sinkMBB);
19651 // Create the conditional branch instruction.
19652 unsigned Opc =
19653 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
19654 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
19656 // copy0MBB:
19657 // %FalseValue = ...
19658 // # fallthrough to sinkMBB
19659 copy0MBB->addSuccessor(sinkMBB);
19661 // sinkMBB:
19662 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
19663 // ...
19664 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19665 TII->get(X86::PHI), MI->getOperand(0).getReg())
19666 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
19667 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
19669 MI->eraseFromParent(); // The pseudo instruction is gone now.
19670 return sinkMBB;
19671 }
19673 MachineBasicBlock *
19674 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
19675 MachineBasicBlock *BB) const {
19676 MachineFunction *MF = BB->getParent();
19677 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19678 DebugLoc DL = MI->getDebugLoc();
19679 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19681 assert(MF->shouldSplitStack());
19683 const bool Is64Bit = Subtarget->is64Bit();
19684 const bool IsLP64 = Subtarget->isTarget64BitLP64();
19686 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
19687 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
19689 // BB:
19690 // ... [Till the alloca]
19691 // If stacklet is not large enough, jump to mallocMBB
19692 //
19693 // bumpMBB:
19694 // Allocate by subtracting from RSP
19695 // Jump to continueMBB
19696 //
19697 // mallocMBB:
19698 // Allocate by call to runtime
19699 //
19700 // continueMBB:
19701 // ...
19702 // [rest of original BB]
19703 //
19705 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19706 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19707 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19709 MachineRegisterInfo &MRI = MF->getRegInfo();
19710 const TargetRegisterClass *AddrRegClass =
19711 getRegClassFor(getPointerTy());
19713 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19714 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19715 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
19716 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
19717 sizeVReg = MI->getOperand(1).getReg(),
19718 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
19720 MachineFunction::iterator MBBIter = BB;
19721 ++MBBIter;
19723 MF->insert(MBBIter, bumpMBB);
19724 MF->insert(MBBIter, mallocMBB);
19725 MF->insert(MBBIter, continueMBB);
19727 continueMBB->splice(continueMBB->begin(), BB,
19728 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19729 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
19731 // Add code to the main basic block to check if the stack limit has been hit,
19732 // and if so, jump to mallocMBB otherwise to bumpMBB.
19733 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
19734 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
19735 .addReg(tmpSPVReg).addReg(sizeVReg);
19736 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
19737 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
19738 .addReg(SPLimitVReg);
19739 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
19741 // bumpMBB simply decreases the stack pointer, since we know the current
19742 // stacklet has enough space.
19743 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
19744 .addReg(SPLimitVReg);
19745 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
19746 .addReg(SPLimitVReg);
19747 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
19749 // Calls into a routine in libgcc to allocate more space from the heap.
19750 const uint32_t *RegMask = MF->getTarget()
19751 .getSubtargetImpl()
19752 ->getRegisterInfo()
19753 ->getCallPreservedMask(CallingConv::C);
19754 if (IsLP64) {
19755 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
19756 .addReg(sizeVReg);
19757 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19758 .addExternalSymbol("__morestack_allocate_stack_space")
19759 .addRegMask(RegMask)
19760 .addReg(X86::RDI, RegState::Implicit)
19761 .addReg(X86::RAX, RegState::ImplicitDefine);
19762 } else if (Is64Bit) {
19763 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
19764 .addReg(sizeVReg);
19765 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19766 .addExternalSymbol("__morestack_allocate_stack_space")
19767 .addRegMask(RegMask)
19768 .addReg(X86::EDI, RegState::Implicit)
19769 .addReg(X86::EAX, RegState::ImplicitDefine);
19770 } else {
19771 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
19772 .addImm(12);
19773 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
19774 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
19775 .addExternalSymbol("__morestack_allocate_stack_space")
19776 .addRegMask(RegMask)
19777 .addReg(X86::EAX, RegState::ImplicitDefine);
19778 }
19780 if (!Is64Bit)
19781 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
19782 .addImm(16);
19784 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
19785 .addReg(IsLP64 ? X86::RAX : X86::EAX);
19786 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
19788 // Set up the CFG correctly.
19789 BB->addSuccessor(bumpMBB);
19790 BB->addSuccessor(mallocMBB);
19791 mallocMBB->addSuccessor(continueMBB);
19792 bumpMBB->addSuccessor(continueMBB);
19794 // Take care of the PHI nodes.
19795 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
19796 MI->getOperand(0).getReg())
19797 .addReg(mallocPtrVReg).addMBB(mallocMBB)
19798 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
19800 // Delete the original pseudo instruction.
19801 MI->eraseFromParent();
19803 // And we're done.
19804 return continueMBB;
19805 }
19807 MachineBasicBlock *
19808 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
19809 MachineBasicBlock *BB) const {
19810 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
19811 DebugLoc DL = MI->getDebugLoc();
19813 assert(!Subtarget->isTargetMacho());
19815 // The lowering is pretty easy: we're just emitting the call to _alloca. The
19816 // non-trivial part is impdef of ESP.
19818 if (Subtarget->isTargetWin64()) {
19819 if (Subtarget->isTargetCygMing()) {
19820 // ___chkstk(Mingw64):
19821 // Clobbers R10, R11, RAX and EFLAGS.
19822 // Updates RSP.
19823 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
19824 .addExternalSymbol("___chkstk")
19825 .addReg(X86::RAX, RegState::Implicit)
19826 .addReg(X86::RSP, RegState::Implicit)
19827 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
19828 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
19829 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19830 } else {
19831 // __chkstk(MSVCRT): does not update stack pointer.
19832 // Clobbers R10, R11 and EFLAGS.
19833 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
19834 .addExternalSymbol("__chkstk")
19835 .addReg(X86::RAX, RegState::Implicit)
19836 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19837 // RAX has the offset to be subtracted from RSP.
19838 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
19839 .addReg(X86::RSP)
19840 .addReg(X86::RAX);
19841 }
19842 } else {
19843 const char *StackProbeSymbol =
19844 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
19846 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
19847 .addExternalSymbol(StackProbeSymbol)
19848 .addReg(X86::EAX, RegState::Implicit)
19849 .addReg(X86::ESP, RegState::Implicit)
19850 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
19851 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
19852 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19853 }
19855 MI->eraseFromParent(); // The pseudo instruction is gone now.
19856 return BB;
19857 }
19859 MachineBasicBlock *
19860 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
19861 MachineBasicBlock *BB) const {
19862 // This is pretty easy. We're taking the value that we received from
19863 // our load from the relocation, sticking it in either RDI (x86-64)
19864 // or EAX and doing an indirect call. The return value will then
19865 // be in the normal return register.
19866 MachineFunction *F = BB->getParent();
19867 const X86InstrInfo *TII =
19868 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
19869 DebugLoc DL = MI->getDebugLoc();
19871 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
19872 assert(MI->getOperand(3).isGlobal() && "This should be a global");
19874 // Get a register mask for the lowered call.
19875 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
19876 // proper register mask.
19877 const uint32_t *RegMask = F->getTarget()
19878 .getSubtargetImpl()
19879 ->getRegisterInfo()
19880 ->getCallPreservedMask(CallingConv::C);
19881 if (Subtarget->is64Bit()) {
19882 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19883 TII->get(X86::MOV64rm), X86::RDI)
19884 .addReg(X86::RIP)
19885 .addImm(0).addReg(0)
19886 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19887 MI->getOperand(3).getTargetFlags())
19888 .addReg(0);
19889 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
19890 addDirectMem(MIB, X86::RDI);
19891 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
19892 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
19893 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19894 TII->get(X86::MOV32rm), X86::EAX)
19895 .addReg(0)
19896 .addImm(0).addReg(0)
19897 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19898 MI->getOperand(3).getTargetFlags())
19899 .addReg(0);
19900 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19901 addDirectMem(MIB, X86::EAX);
19902 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19903 } else {
19904 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19905 TII->get(X86::MOV32rm), X86::EAX)
19906 .addReg(TII->getGlobalBaseReg(F))
19907 .addImm(0).addReg(0)
19908 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19909 MI->getOperand(3).getTargetFlags())
19910 .addReg(0);
19911 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19912 addDirectMem(MIB, X86::EAX);
19913 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19914 }
19916 MI->eraseFromParent(); // The pseudo instruction is gone now.
19917 return BB;
19918 }
19920 MachineBasicBlock *
19921 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
19922 MachineBasicBlock *MBB) const {
19923 DebugLoc DL = MI->getDebugLoc();
19924 MachineFunction *MF = MBB->getParent();
19925 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19926 MachineRegisterInfo &MRI = MF->getRegInfo();
19928 const BasicBlock *BB = MBB->getBasicBlock();
19929 MachineFunction::iterator I = MBB;
19930 ++I;
19932 // Memory Reference
19933 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19934 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19936 unsigned DstReg;
19937 unsigned MemOpndSlot = 0;
19939 unsigned CurOp = 0;
19941 DstReg = MI->getOperand(CurOp++).getReg();
19942 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
19943 assert(RC->hasType(MVT::i32) && "Invalid destination!");
19944 unsigned mainDstReg = MRI.createVirtualRegister(RC);
19945 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
19947 MemOpndSlot = CurOp;
19949 MVT PVT = getPointerTy();
19950 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19951 "Invalid Pointer Size!");
19953 // For v = setjmp(buf), we generate
19954 //
19955 // thisMBB:
19956 // buf[LabelOffset] = restoreMBB
19957 // SjLjSetup restoreMBB
19958 //
19959 // mainMBB:
19960 // v_main = 0
19961 //
19962 // sinkMBB:
19963 // v = phi(main, restore)
19964 //
19965 // restoreMBB:
19966 // v_restore = 1
19968 MachineBasicBlock *thisMBB = MBB;
19969 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19970 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19971 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
19972 MF->insert(I, mainMBB);
19973 MF->insert(I, sinkMBB);
19974 MF->push_back(restoreMBB);
19976 MachineInstrBuilder MIB;
19978 // Transfer the remainder of BB and its successor edges to sinkMBB.
19979 sinkMBB->splice(sinkMBB->begin(), MBB,
19980 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19981 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19983 // thisMBB:
19984 unsigned PtrStoreOpc = 0;
19985 unsigned LabelReg = 0;
19986 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19987 Reloc::Model RM = MF->getTarget().getRelocationModel();
19988 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
19989 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
19991 // Prepare IP either in reg or imm.
19992 if (!UseImmLabel) {
19993 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
19994 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
19995 LabelReg = MRI.createVirtualRegister(PtrRC);
19996 if (Subtarget->is64Bit()) {
19997 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
19998 .addReg(X86::RIP)
19999 .addImm(0)
20000 .addReg(0)
20001 .addMBB(restoreMBB)
20002 .addReg(0);
20003 } else {
20004 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
20005 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
20006 .addReg(XII->getGlobalBaseReg(MF))
20007 .addImm(0)
20008 .addReg(0)
20009 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
20010 .addReg(0);
20011 }
20012 } else
20013 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
20014 // Store IP
20015 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
20016 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20017 if (i == X86::AddrDisp)
20018 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
20019 else
20020 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
20021 }
20022 if (!UseImmLabel)
20023 MIB.addReg(LabelReg);
20024 else
20025 MIB.addMBB(restoreMBB);
20026 MIB.setMemRefs(MMOBegin, MMOEnd);
20027 // Setup
20028 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
20029 .addMBB(restoreMBB);
20031 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20032 MF->getSubtarget().getRegisterInfo());
20033 MIB.addRegMask(RegInfo->getNoPreservedMask());
20034 thisMBB->addSuccessor(mainMBB);
20035 thisMBB->addSuccessor(restoreMBB);
20037 // mainMBB:
20038 // EAX = 0
20039 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
20040 mainMBB->addSuccessor(sinkMBB);
20042 // sinkMBB:
20043 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20044 TII->get(X86::PHI), DstReg)
20045 .addReg(mainDstReg).addMBB(mainMBB)
20046 .addReg(restoreDstReg).addMBB(restoreMBB);
20048 // restoreMBB:
20049 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
20050 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
20051 restoreMBB->addSuccessor(sinkMBB);
20053 MI->eraseFromParent();
20054 return sinkMBB;
20055 }
20057 MachineBasicBlock *
20058 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
20059 MachineBasicBlock *MBB) const {
20060 DebugLoc DL = MI->getDebugLoc();
20061 MachineFunction *MF = MBB->getParent();
20062 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20063 MachineRegisterInfo &MRI = MF->getRegInfo();
20065 // Memory Reference
20066 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20067 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20069 MVT PVT = getPointerTy();
20070 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20071 "Invalid Pointer Size!");
20073 const TargetRegisterClass *RC =
20074 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
20075 unsigned Tmp = MRI.createVirtualRegister(RC);
20076 // Since FP is only updated here but NOT referenced, it's treated as GPR.
20077 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20078 MF->getSubtarget().getRegisterInfo());
20079 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
20080 unsigned SP = RegInfo->getStackRegister();
20082 MachineInstrBuilder MIB;
20084 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20085 const int64_t SPOffset = 2 * PVT.getStoreSize();
20087 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
20088 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
20090 // Reload FP
20091 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
20092 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
20093 MIB.addOperand(MI->getOperand(i));
20094 MIB.setMemRefs(MMOBegin, MMOEnd);
20095 // Reload IP
20096 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
20097 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20098 if (i == X86::AddrDisp)
20099 MIB.addDisp(MI->getOperand(i), LabelOffset);
20100 else
20101 MIB.addOperand(MI->getOperand(i));
20102 }
20103 MIB.setMemRefs(MMOBegin, MMOEnd);
20104 // Reload SP
20105 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
20106 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20107 if (i == X86::AddrDisp)
20108 MIB.addDisp(MI->getOperand(i), SPOffset);
20109 else
20110 MIB.addOperand(MI->getOperand(i));
20111 }
20112 MIB.setMemRefs(MMOBegin, MMOEnd);
20113 // Jump
20114 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
20116 MI->eraseFromParent();
20117 return MBB;
20118 }
20120 // Replace 213-type (isel default) FMA3 instructions with 231-type for
20121 // accumulator loops. Writing back to the accumulator allows the coalescer
20122 // to remove extra copies in the loop.
20123 MachineBasicBlock *
20124 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
20125 MachineBasicBlock *MBB) const {
20126 MachineOperand &AddendOp = MI->getOperand(3);
20128 // Bail out early if the addend isn't a register - we can't switch these.
20129 if (!AddendOp.isReg())
20130 return MBB;
20132 MachineFunction &MF = *MBB->getParent();
20133 MachineRegisterInfo &MRI = MF.getRegInfo();
20135 // Check whether the addend is defined by a PHI:
20136 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
20137 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
20138 if (!AddendDef.isPHI())
20139 return MBB;
20141 // Look for the following pattern:
20142 // loop:
20143 // %addend = phi [%entry, 0], [%loop, %result]
20144 // ...
20145 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
20147 // Replace with:
20148 // loop:
20149 // %addend = phi [%entry, 0], [%loop, %result]
20150 // ...
20151 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
20153 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
20154 assert(AddendDef.getOperand(i).isReg());
20155 MachineOperand PHISrcOp = AddendDef.getOperand(i);
20156 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
20157 if (&PHISrcInst == MI) {
20158 // Found a matching instruction.
20159 unsigned NewFMAOpc = 0;
20160 switch (MI->getOpcode()) {
20161 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
20162 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
20163 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
20164 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
20165 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
20166 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
20167 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
20168 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
20169 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
20170 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
20171 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
20172 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
20173 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
20174 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
20175 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
20176 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
20177 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
20178 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
20179 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
20180 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
20181 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
20182 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
20183 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
20184 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
20185 default: llvm_unreachable("Unrecognized FMA variant.");
20186 }
20188 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
20189 MachineInstrBuilder MIB =
20190 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
20191 .addOperand(MI->getOperand(0))
20192 .addOperand(MI->getOperand(3))
20193 .addOperand(MI->getOperand(2))
20194 .addOperand(MI->getOperand(1));
20195 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
20196 MI->eraseFromParent();
20197 }
20198 }
20200 return MBB;
20201 }
20203 MachineBasicBlock *
20204 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
20205 MachineBasicBlock *BB) const {
20206 switch (MI->getOpcode()) {
20207 default: llvm_unreachable("Unexpected instr type to insert");
20208 case X86::TAILJMPd64:
20209 case X86::TAILJMPr64:
20210 case X86::TAILJMPm64:
20211 llvm_unreachable("TAILJMP64 would not be touched here.");
20212 case X86::TCRETURNdi64:
20213 case X86::TCRETURNri64:
20214 case X86::TCRETURNmi64:
20215 return BB;
20216 case X86::WIN_ALLOCA:
20217 return EmitLoweredWinAlloca(MI, BB);
20218 case X86::SEG_ALLOCA_32:
20219 case X86::SEG_ALLOCA_64:
20220 return EmitLoweredSegAlloca(MI, BB);
20221 case X86::TLSCall_32:
20222 case X86::TLSCall_64:
20223 return EmitLoweredTLSCall(MI, BB);
20224 case X86::CMOV_GR8:
20225 case X86::CMOV_FR32:
20226 case X86::CMOV_FR64:
20227 case X86::CMOV_V4F32:
20228 case X86::CMOV_V2F64:
20229 case X86::CMOV_V2I64:
20230 case X86::CMOV_V8F32:
20231 case X86::CMOV_V4F64:
20232 case X86::CMOV_V4I64:
20233 case X86::CMOV_V16F32:
20234 case X86::CMOV_V8F64:
20235 case X86::CMOV_V8I64:
20236 case X86::CMOV_GR16:
20237 case X86::CMOV_GR32:
20238 case X86::CMOV_RFP32:
20239 case X86::CMOV_RFP64:
20240 case X86::CMOV_RFP80:
20241 return EmitLoweredSelect(MI, BB);
20243 case X86::FP32_TO_INT16_IN_MEM:
20244 case X86::FP32_TO_INT32_IN_MEM:
20245 case X86::FP32_TO_INT64_IN_MEM:
20246 case X86::FP64_TO_INT16_IN_MEM:
20247 case X86::FP64_TO_INT32_IN_MEM:
20248 case X86::FP64_TO_INT64_IN_MEM:
20249 case X86::FP80_TO_INT16_IN_MEM:
20250 case X86::FP80_TO_INT32_IN_MEM:
20251 case X86::FP80_TO_INT64_IN_MEM: {
20252 MachineFunction *F = BB->getParent();
20253 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
20254 DebugLoc DL = MI->getDebugLoc();
20256 // Change the floating point control register to use "round towards zero"
20257 // mode when truncating to an integer value.
20258 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
20259 addFrameReference(BuildMI(*BB, MI, DL,
20260 TII->get(X86::FNSTCW16m)), CWFrameIdx);
20262 // Load the old value of the high byte of the control word...
20263 unsigned OldCW =
20264 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
20265 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
20266 CWFrameIdx);
20268 // Set the high part to be round to zero...
20269 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
20270 .addImm(0xC7F);
20272 // Reload the modified control word now...
20273 addFrameReference(BuildMI(*BB, MI, DL,
20274 TII->get(X86::FLDCW16m)), CWFrameIdx);
20276 // Restore the memory image of control word to original value
20277 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
20278 .addReg(OldCW);
20280 // Get the X86 opcode to use.
20281 unsigned Opc;
20282 switch (MI->getOpcode()) {
20283 default: llvm_unreachable("illegal opcode!");
20284 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
20285 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
20286 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
20287 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
20288 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
20289 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
20290 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
20291 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
20292 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
20293 }
20295 X86AddressMode AM;
20296 MachineOperand &Op = MI->getOperand(0);
20297 if (Op.isReg()) {
20298 AM.BaseType = X86AddressMode::RegBase;
20299 AM.Base.Reg = Op.getReg();
20300 } else {
20301 AM.BaseType = X86AddressMode::FrameIndexBase;
20302 AM.Base.FrameIndex = Op.getIndex();
20303 }
20304 Op = MI->getOperand(1);
20305 if (Op.isImm())
20306 AM.Scale = Op.getImm();
20307 Op = MI->getOperand(2);
20308 if (Op.isImm())
20309 AM.IndexReg = Op.getImm();
20310 Op = MI->getOperand(3);
20311 if (Op.isGlobal()) {
20312 AM.GV = Op.getGlobal();
20313 } else {
20314 AM.Disp = Op.getImm();
20315 }
20316 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
20317 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
20319 // Reload the original control word now.
20320 addFrameReference(BuildMI(*BB, MI, DL,
20321 TII->get(X86::FLDCW16m)), CWFrameIdx);
20323 MI->eraseFromParent(); // The pseudo instruction is gone now.
20324 return BB;
20325 }
20326 // String/text processing lowering.
20327 case X86::PCMPISTRM128REG:
20328 case X86::VPCMPISTRM128REG:
20329 case X86::PCMPISTRM128MEM:
20330 case X86::VPCMPISTRM128MEM:
20331 case X86::PCMPESTRM128REG:
20332 case X86::VPCMPESTRM128REG:
20333 case X86::PCMPESTRM128MEM:
20334 case X86::VPCMPESTRM128MEM:
20335 assert(Subtarget->hasSSE42() &&
20336 "Target must have SSE4.2 or AVX features enabled");
20337 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20339 // String/text processing lowering.
20340 case X86::PCMPISTRIREG:
20341 case X86::VPCMPISTRIREG:
20342 case X86::PCMPISTRIMEM:
20343 case X86::VPCMPISTRIMEM:
20344 case X86::PCMPESTRIREG:
20345 case X86::VPCMPESTRIREG:
20346 case X86::PCMPESTRIMEM:
20347 case X86::VPCMPESTRIMEM:
20348 assert(Subtarget->hasSSE42() &&
20349 "Target must have SSE4.2 or AVX features enabled");
20350 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20352 // Thread synchronization.
20353 case X86::MONITOR:
20354 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
20355 Subtarget);
20357 // xbegin
20358 case X86::XBEGIN:
20359 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20361 case X86::VASTART_SAVE_XMM_REGS:
20362 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
20364 case X86::VAARG_64:
20365 return EmitVAARG64WithCustomInserter(MI, BB);
20367 case X86::EH_SjLj_SetJmp32:
20368 case X86::EH_SjLj_SetJmp64:
20369 return emitEHSjLjSetJmp(MI, BB);
20371 case X86::EH_SjLj_LongJmp32:
20372 case X86::EH_SjLj_LongJmp64:
20373 return emitEHSjLjLongJmp(MI, BB);
20375 case TargetOpcode::STACKMAP:
20376 case TargetOpcode::PATCHPOINT:
20377 return emitPatchPoint(MI, BB);
20379 case X86::VFMADDPDr213r:
20380 case X86::VFMADDPSr213r:
20381 case X86::VFMADDSDr213r:
20382 case X86::VFMADDSSr213r:
20383 case X86::VFMSUBPDr213r:
20384 case X86::VFMSUBPSr213r:
20385 case X86::VFMSUBSDr213r:
20386 case X86::VFMSUBSSr213r:
20387 case X86::VFNMADDPDr213r:
20388 case X86::VFNMADDPSr213r:
20389 case X86::VFNMADDSDr213r:
20390 case X86::VFNMADDSSr213r:
20391 case X86::VFNMSUBPDr213r:
20392 case X86::VFNMSUBPSr213r:
20393 case X86::VFNMSUBSDr213r:
20394 case X86::VFNMSUBSSr213r:
20395 case X86::VFMADDPDr213rY:
20396 case X86::VFMADDPSr213rY:
20397 case X86::VFMSUBPDr213rY:
20398 case X86::VFMSUBPSr213rY:
20399 case X86::VFNMADDPDr213rY:
20400 case X86::VFNMADDPSr213rY:
20401 case X86::VFNMSUBPDr213rY:
20402 case X86::VFNMSUBPSr213rY:
20403 return emitFMA3Instr(MI, BB);
20404 }
20405 }
20407 //===----------------------------------------------------------------------===//
20408 // X86 Optimization Hooks
20409 //===----------------------------------------------------------------------===//
20411 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
20412 APInt &KnownZero,
20413 APInt &KnownOne,
20414 const SelectionDAG &DAG,
20415 unsigned Depth) const {
20416 unsigned BitWidth = KnownZero.getBitWidth();
20417 unsigned Opc = Op.getOpcode();
20418 assert((Opc >= ISD::BUILTIN_OP_END ||
20419 Opc == ISD::INTRINSIC_WO_CHAIN ||
20420 Opc == ISD::INTRINSIC_W_CHAIN ||
20421 Opc == ISD::INTRINSIC_VOID) &&
20422 "Should use MaskedValueIsZero if you don't know whether Op"
20423 " is a target node!");
20425 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
20426 switch (Opc) {
20427 default: break;
20428 case X86ISD::ADD:
20429 case X86ISD::SUB:
20430 case X86ISD::ADC:
20431 case X86ISD::SBB:
20432 case X86ISD::SMUL:
20433 case X86ISD::UMUL:
20434 case X86ISD::INC:
20435 case X86ISD::DEC:
20436 case X86ISD::OR:
20437 case X86ISD::XOR:
20438 case X86ISD::AND:
20439 // These nodes' second result is a boolean.
20440 if (Op.getResNo() == 0)
20441 break;
20442 // Fallthrough
20443 case X86ISD::SETCC:
20444 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
20445 break;
20446 case ISD::INTRINSIC_WO_CHAIN: {
20447 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
20448 unsigned NumLoBits = 0;
20449 switch (IntId) {
20450 default: break;
20451 case Intrinsic::x86_sse_movmsk_ps:
20452 case Intrinsic::x86_avx_movmsk_ps_256:
20453 case Intrinsic::x86_sse2_movmsk_pd:
20454 case Intrinsic::x86_avx_movmsk_pd_256:
20455 case Intrinsic::x86_mmx_pmovmskb:
20456 case Intrinsic::x86_sse2_pmovmskb_128:
20457 case Intrinsic::x86_avx2_pmovmskb: {
20458 // High bits of movmskp{s|d}, pmovmskb are known zero.
20459 switch (IntId) {
20460 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
20461 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
20462 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
20463 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
20464 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
20465 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
20466 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
20467 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
20468 }
20469 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
20470 break;
20471 }
20472 }
20473 break;
20474 }
20475 }
20476 }
20478 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
20479 SDValue Op,
20480 const SelectionDAG &,
20481 unsigned Depth) const {
20482 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
20483 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
20484 return Op.getValueType().getScalarType().getSizeInBits();
20486 // Fallback case.
20487 return 1;
20488 }
20490 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
20491 /// node is a GlobalAddress + offset.
20492 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
20493 const GlobalValue* &GA,
20494 int64_t &Offset) const {
20495 if (N->getOpcode() == X86ISD::Wrapper) {
20496 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
20497 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
20498 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
20499 return true;
20500 }
20501 }
20502 return TargetLowering::isGAPlusOffset(N, GA, Offset);
20503 }
20505 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
20506 /// same as extracting the high 128-bit part of 256-bit vector and then
20507 /// inserting the result into the low part of a new 256-bit vector
20508 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
20509 EVT VT = SVOp->getValueType(0);
20510 unsigned NumElems = VT.getVectorNumElements();
20512 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20513 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
20514 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20515 SVOp->getMaskElt(j) >= 0)
20516 return false;
20518 return true;
20519 }
20521 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
20522 /// same as extracting the low 128-bit part of 256-bit vector and then
20523 /// inserting the result into the high part of a new 256-bit vector
20524 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
20525 EVT VT = SVOp->getValueType(0);
20526 unsigned NumElems = VT.getVectorNumElements();
20528 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20529 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
20530 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20531 SVOp->getMaskElt(j) >= 0)
20532 return false;
20534 return true;
20535 }
20537 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
20538 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
20539 TargetLowering::DAGCombinerInfo &DCI,
20540 const X86Subtarget* Subtarget) {
20541 SDLoc dl(N);
20542 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20543 SDValue V1 = SVOp->getOperand(0);
20544 SDValue V2 = SVOp->getOperand(1);
20545 EVT VT = SVOp->getValueType(0);
20546 unsigned NumElems = VT.getVectorNumElements();
20548 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
20549 V2.getOpcode() == ISD::CONCAT_VECTORS) {
20550 //
20551 // 0,0,0,...
20552 // |
20553 // V UNDEF BUILD_VECTOR UNDEF
20554 // \ / \ /
20555 // CONCAT_VECTOR CONCAT_VECTOR
20556 // \ /
20557 // \ /
20558 // RESULT: V + zero extended
20559 //
20560 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
20561 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
20562 V1.getOperand(1).getOpcode() != ISD::UNDEF)
20563 return SDValue();
20565 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
20566 return SDValue();
20568 // To match the shuffle mask, the first half of the mask should
20569 // be exactly the first vector, and all the rest a splat with the
20570 // first element of the second one.
20571 for (unsigned i = 0; i != NumElems/2; ++i)
20572 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
20573 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
20574 return SDValue();
20576 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
20577 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
20578 if (Ld->hasNUsesOfValue(1, 0)) {
20579 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
20580 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
20581 SDValue ResNode =
20582 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
20583 Ld->getMemoryVT(),
20584 Ld->getPointerInfo(),
20585 Ld->getAlignment(),
20586 false/*isVolatile*/, true/*ReadMem*/,
20587 false/*WriteMem*/);
20589 // Make sure the newly-created LOAD is in the same position as Ld in
20590 // terms of dependency. We create a TokenFactor for Ld and ResNode,
20591 // and update uses of Ld's output chain to use the TokenFactor.
20592 if (Ld->hasAnyUseOfValue(1)) {
20593 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
20594 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
20595 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
20596 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
20597 SDValue(ResNode.getNode(), 1));
20598 }
20600 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
20601 }
20602 }
20604 // Emit a zeroed vector and insert the desired subvector on its
20605 // first half.
20606 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
20607 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
20608 return DCI.CombineTo(N, InsV);
20609 }
20611 //===--------------------------------------------------------------------===//
20612 // Combine some shuffles into subvector extracts and inserts:
20613 //
20615 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20616 if (isShuffleHigh128VectorInsertLow(SVOp)) {
20617 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
20618 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
20619 return DCI.CombineTo(N, InsV);
20620 }
20622 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20623 if (isShuffleLow128VectorInsertHigh(SVOp)) {
20624 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
20625 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
20626 return DCI.CombineTo(N, InsV);
20627 }
20629 return SDValue();
20630 }
20632 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
20633 /// possible.
20634 ///
20635 /// This is the leaf of the recursive combinine below. When we have found some
20636 /// chain of single-use x86 shuffle instructions and accumulated the combined
20637 /// shuffle mask represented by them, this will try to pattern match that mask
20638 /// into either a single instruction if there is a special purpose instruction
20639 /// for this operation, or into a PSHUFB instruction which is a fully general
20640 /// instruction but should only be used to replace chains over a certain depth.
20641 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
20642 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
20643 TargetLowering::DAGCombinerInfo &DCI,
20644 const X86Subtarget *Subtarget) {
20645 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
20647 // Find the operand that enters the chain. Note that multiple uses are OK
20648 // here, we're not going to remove the operand we find.
20649 SDValue Input = Op.getOperand(0);
20650 while (Input.getOpcode() == ISD::BITCAST)
20651 Input = Input.getOperand(0);
20653 MVT VT = Input.getSimpleValueType();
20654 MVT RootVT = Root.getSimpleValueType();
20655 SDLoc DL(Root);
20657 // Just remove no-op shuffle masks.
20658 if (Mask.size() == 1) {
20659 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
20660 /*AddTo*/ true);
20661 return true;
20662 }
20664 // Use the float domain if the operand type is a floating point type.
20665 bool FloatDomain = VT.isFloatingPoint();
20667 // For floating point shuffles, we don't have free copies in the shuffle
20668 // instructions or the ability to load as part of the instruction, so
20669 // canonicalize their shuffles to UNPCK or MOV variants.
20670 //
20671 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
20672 // vectors because it can have a load folded into it that UNPCK cannot. This
20673 // doesn't preclude something switching to the shorter encoding post-RA.
20674 if (FloatDomain) {
20675 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
20676 bool Lo = Mask.equals(0, 0);
20677 unsigned Shuffle;
20678 MVT ShuffleVT;
20679 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
20680 // is no slower than UNPCKLPD but has the option to fold the input operand
20681 // into even an unaligned memory load.
20682 if (Lo && Subtarget->hasSSE3()) {
20683 Shuffle = X86ISD::MOVDDUP;
20684 ShuffleVT = MVT::v2f64;
20685 } else {
20686 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
20687 // than the UNPCK variants.
20688 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
20689 ShuffleVT = MVT::v4f32;
20690 }
20691 if (Depth == 1 && Root->getOpcode() == Shuffle)
20692 return false; // Nothing to do!
20693 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20694 DCI.AddToWorklist(Op.getNode());
20695 if (Shuffle == X86ISD::MOVDDUP)
20696 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20697 else
20698 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20699 DCI.AddToWorklist(Op.getNode());
20700 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20701 /*AddTo*/ true);
20702 return true;
20703 }
20704 if (Subtarget->hasSSE3() &&
20705 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
20706 bool Lo = Mask.equals(0, 0, 2, 2);
20707 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
20708 MVT ShuffleVT = MVT::v4f32;
20709 if (Depth == 1 && Root->getOpcode() == Shuffle)
20710 return false; // Nothing to do!
20711 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20712 DCI.AddToWorklist(Op.getNode());
20713 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20714 DCI.AddToWorklist(Op.getNode());
20715 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20716 /*AddTo*/ true);
20717 return true;
20718 }
20719 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
20720 bool Lo = Mask.equals(0, 0, 1, 1);
20721 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20722 MVT ShuffleVT = MVT::v4f32;
20723 if (Depth == 1 && Root->getOpcode() == Shuffle)
20724 return false; // Nothing to do!
20725 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20726 DCI.AddToWorklist(Op.getNode());
20727 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20728 DCI.AddToWorklist(Op.getNode());
20729 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20730 /*AddTo*/ true);
20731 return true;
20732 }
20733 }
20735 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
20736 // variants as none of these have single-instruction variants that are
20737 // superior to the UNPCK formulation.
20738 if (!FloatDomain &&
20739 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
20740 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
20741 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
20742 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
20743 15))) {
20744 bool Lo = Mask[0] == 0;
20745 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20746 if (Depth == 1 && Root->getOpcode() == Shuffle)
20747 return false; // Nothing to do!
20748 MVT ShuffleVT;
20749 switch (Mask.size()) {
20750 case 8:
20751 ShuffleVT = MVT::v8i16;
20752 break;
20753 case 16:
20754 ShuffleVT = MVT::v16i8;
20755 break;
20756 default:
20757 llvm_unreachable("Impossible mask size!");
20758 };
20759 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20760 DCI.AddToWorklist(Op.getNode());
20761 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20762 DCI.AddToWorklist(Op.getNode());
20763 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20764 /*AddTo*/ true);
20765 return true;
20766 }
20768 // Don't try to re-form single instruction chains under any circumstances now
20769 // that we've done encoding canonicalization for them.
20770 if (Depth < 2)
20771 return false;
20773 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
20774 // can replace them with a single PSHUFB instruction profitably. Intel's
20775 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
20776 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
20777 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
20778 SmallVector<SDValue, 16> PSHUFBMask;
20779 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
20780 int Ratio = 16 / Mask.size();
20781 for (unsigned i = 0; i < 16; ++i) {
20782 if (Mask[i / Ratio] == SM_SentinelUndef) {
20783 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
20784 continue;
20785 }
20786 int M = Mask[i / Ratio] != SM_SentinelZero
20787 ? Ratio * Mask[i / Ratio] + i % Ratio
20788 : 255;
20789 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
20790 }
20791 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
20792 DCI.AddToWorklist(Op.getNode());
20793 SDValue PSHUFBMaskOp =
20794 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
20795 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
20796 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
20797 DCI.AddToWorklist(Op.getNode());
20798 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20799 /*AddTo*/ true);
20800 return true;
20801 }
20803 // Failed to find any combines.
20804 return false;
20805 }
20807 /// \brief Fully generic combining of x86 shuffle instructions.
20808 ///
20809 /// This should be the last combine run over the x86 shuffle instructions. Once
20810 /// they have been fully optimized, this will recursively consider all chains
20811 /// of single-use shuffle instructions, build a generic model of the cumulative
20812 /// shuffle operation, and check for simpler instructions which implement this
20813 /// operation. We use this primarily for two purposes:
20814 ///
20815 /// 1) Collapse generic shuffles to specialized single instructions when
20816 /// equivalent. In most cases, this is just an encoding size win, but
20817 /// sometimes we will collapse multiple generic shuffles into a single
20818 /// special-purpose shuffle.
20819 /// 2) Look for sequences of shuffle instructions with 3 or more total
20820 /// instructions, and replace them with the slightly more expensive SSSE3
20821 /// PSHUFB instruction if available. We do this as the last combining step
20822 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
20823 /// a suitable short sequence of other instructions. The PHUFB will either
20824 /// use a register or have to read from memory and so is slightly (but only
20825 /// slightly) more expensive than the other shuffle instructions.
20826 ///
20827 /// Because this is inherently a quadratic operation (for each shuffle in
20828 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
20829 /// This should never be an issue in practice as the shuffle lowering doesn't
20830 /// produce sequences of more than 8 instructions.
20831 ///
20832 /// FIXME: We will currently miss some cases where the redundant shuffling
20833 /// would simplify under the threshold for PSHUFB formation because of
20834 /// combine-ordering. To fix this, we should do the redundant instruction
20835 /// combining in this recursive walk.
20836 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
20837 ArrayRef<int> RootMask,
20838 int Depth, bool HasPSHUFB,
20839 SelectionDAG &DAG,
20840 TargetLowering::DAGCombinerInfo &DCI,
20841 const X86Subtarget *Subtarget) {
20842 // Bound the depth of our recursive combine because this is ultimately
20843 // quadratic in nature.
20844 if (Depth > 8)
20845 return false;
20847 // Directly rip through bitcasts to find the underlying operand.
20848 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
20849 Op = Op.getOperand(0);
20851 MVT VT = Op.getSimpleValueType();
20852 if (!VT.isVector())
20853 return false; // Bail if we hit a non-vector.
20854 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
20855 // version should be added.
20856 if (VT.getSizeInBits() != 128)
20857 return false;
20859 assert(Root.getSimpleValueType().isVector() &&
20860 "Shuffles operate on vector types!");
20861 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
20862 "Can only combine shuffles of the same vector register size.");
20864 if (!isTargetShuffle(Op.getOpcode()))
20865 return false;
20866 SmallVector<int, 16> OpMask;
20867 bool IsUnary;
20868 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
20869 // We only can combine unary shuffles which we can decode the mask for.
20870 if (!HaveMask || !IsUnary)
20871 return false;
20873 assert(VT.getVectorNumElements() == OpMask.size() &&
20874 "Different mask size from vector size!");
20875 assert(((RootMask.size() > OpMask.size() &&
20876 RootMask.size() % OpMask.size() == 0) ||
20877 (OpMask.size() > RootMask.size() &&
20878 OpMask.size() % RootMask.size() == 0) ||
20879 OpMask.size() == RootMask.size()) &&
20880 "The smaller number of elements must divide the larger.");
20881 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
20882 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
20883 assert(((RootRatio == 1 && OpRatio == 1) ||
20884 (RootRatio == 1) != (OpRatio == 1)) &&
20885 "Must not have a ratio for both incoming and op masks!");
20887 SmallVector<int, 16> Mask;
20888 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
20890 // Merge this shuffle operation's mask into our accumulated mask. Note that
20891 // this shuffle's mask will be the first applied to the input, followed by the
20892 // root mask to get us all the way to the root value arrangement. The reason
20893 // for this order is that we are recursing up the operation chain.
20894 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
20895 int RootIdx = i / RootRatio;
20896 if (RootMask[RootIdx] < 0) {
20897 // This is a zero or undef lane, we're done.
20898 Mask.push_back(RootMask[RootIdx]);
20899 continue;
20900 }
20902 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
20903 int OpIdx = RootMaskedIdx / OpRatio;
20904 if (OpMask[OpIdx] < 0) {
20905 // The incoming lanes are zero or undef, it doesn't matter which ones we
20906 // are using.
20907 Mask.push_back(OpMask[OpIdx]);
20908 continue;
20909 }
20911 // Ok, we have non-zero lanes, map them through.
20912 Mask.push_back(OpMask[OpIdx] * OpRatio +
20913 RootMaskedIdx % OpRatio);
20914 }
20916 // See if we can recurse into the operand to combine more things.
20917 switch (Op.getOpcode()) {
20918 case X86ISD::PSHUFB:
20919 HasPSHUFB = true;
20920 case X86ISD::PSHUFD:
20921 case X86ISD::PSHUFHW:
20922 case X86ISD::PSHUFLW:
20923 if (Op.getOperand(0).hasOneUse() &&
20924 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20925 HasPSHUFB, DAG, DCI, Subtarget))
20926 return true;
20927 break;
20929 case X86ISD::UNPCKL:
20930 case X86ISD::UNPCKH:
20931 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
20932 // We can't check for single use, we have to check that this shuffle is the only user.
20933 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
20934 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20935 HasPSHUFB, DAG, DCI, Subtarget))
20936 return true;
20937 break;
20938 }
20940 // Minor canonicalization of the accumulated shuffle mask to make it easier
20941 // to match below. All this does is detect masks with squential pairs of
20942 // elements, and shrink them to the half-width mask. It does this in a loop
20943 // so it will reduce the size of the mask to the minimal width mask which
20944 // performs an equivalent shuffle.
20945 SmallVector<int, 16> WidenedMask;
20946 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
20947 Mask = std::move(WidenedMask);
20948 WidenedMask.clear();
20949 }
20951 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
20952 Subtarget);
20953 }
20955 /// \brief Get the PSHUF-style mask from PSHUF node.
20956 ///
20957 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
20958 /// PSHUF-style masks that can be reused with such instructions.
20959 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
20960 SmallVector<int, 4> Mask;
20961 bool IsUnary;
20962 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
20963 (void)HaveMask;
20964 assert(HaveMask);
20966 switch (N.getOpcode()) {
20967 case X86ISD::PSHUFD:
20968 return Mask;
20969 case X86ISD::PSHUFLW:
20970 Mask.resize(4);
20971 return Mask;
20972 case X86ISD::PSHUFHW:
20973 Mask.erase(Mask.begin(), Mask.begin() + 4);
20974 for (int &M : Mask)
20975 M -= 4;
20976 return Mask;
20977 default:
20978 llvm_unreachable("No valid shuffle instruction found!");
20979 }
20980 }
20982 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
20983 ///
20984 /// We walk up the chain and look for a combinable shuffle, skipping over
20985 /// shuffles that we could hoist this shuffle's transformation past without
20986 /// altering anything.
20987 static SDValue
20988 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
20989 SelectionDAG &DAG,
20990 TargetLowering::DAGCombinerInfo &DCI) {
20991 assert(N.getOpcode() == X86ISD::PSHUFD &&
20992 "Called with something other than an x86 128-bit half shuffle!");
20993 SDLoc DL(N);
20995 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
20996 // of the shuffles in the chain so that we can form a fresh chain to replace
20997 // this one.
20998 SmallVector<SDValue, 8> Chain;
20999 SDValue V = N.getOperand(0);
21000 for (; V.hasOneUse(); V = V.getOperand(0)) {
21001 switch (V.getOpcode()) {
21002 default:
21003 return SDValue(); // Nothing combined!
21005 case ISD::BITCAST:
21006 // Skip bitcasts as we always know the type for the target specific
21007 // instructions.
21008 continue;
21010 case X86ISD::PSHUFD:
21011 // Found another dword shuffle.
21012 break;
21014 case X86ISD::PSHUFLW:
21015 // Check that the low words (being shuffled) are the identity in the
21016 // dword shuffle, and the high words are self-contained.
21017 if (Mask[0] != 0 || Mask[1] != 1 ||
21018 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
21019 return SDValue();
21021 Chain.push_back(V);
21022 continue;
21024 case X86ISD::PSHUFHW:
21025 // Check that the high words (being shuffled) are the identity in the
21026 // dword shuffle, and the low words are self-contained.
21027 if (Mask[2] != 2 || Mask[3] != 3 ||
21028 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
21029 return SDValue();
21031 Chain.push_back(V);
21032 continue;
21034 case X86ISD::UNPCKL:
21035 case X86ISD::UNPCKH:
21036 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
21037 // shuffle into a preceding word shuffle.
21038 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
21039 return SDValue();
21041 // Search for a half-shuffle which we can combine with.
21042 unsigned CombineOp =
21043 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
21044 if (V.getOperand(0) != V.getOperand(1) ||
21045 !V->isOnlyUserOf(V.getOperand(0).getNode()))
21046 return SDValue();
21047 Chain.push_back(V);
21048 V = V.getOperand(0);
21049 do {
21050 switch (V.getOpcode()) {
21051 default:
21052 return SDValue(); // Nothing to combine.
21054 case X86ISD::PSHUFLW:
21055 case X86ISD::PSHUFHW:
21056 if (V.getOpcode() == CombineOp)
21057 break;
21059 Chain.push_back(V);
21061 // Fallthrough!
21062 case ISD::BITCAST:
21063 V = V.getOperand(0);
21064 continue;
21065 }
21066 break;
21067 } while (V.hasOneUse());
21068 break;
21069 }
21070 // Break out of the loop if we break out of the switch.
21071 break;
21072 }
21074 if (!V.hasOneUse())
21075 // We fell out of the loop without finding a viable combining instruction.
21076 return SDValue();
21078 // Merge this node's mask and our incoming mask.
21079 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21080 for (int &M : Mask)
21081 M = VMask[M];
21082 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
21083 getV4X86ShuffleImm8ForMask(Mask, DAG));
21085 // Rebuild the chain around this new shuffle.
21086 while (!Chain.empty()) {
21087 SDValue W = Chain.pop_back_val();
21089 if (V.getValueType() != W.getOperand(0).getValueType())
21090 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
21092 switch (W.getOpcode()) {
21093 default:
21094 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
21096 case X86ISD::UNPCKL:
21097 case X86ISD::UNPCKH:
21098 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
21099 break;
21101 case X86ISD::PSHUFD:
21102 case X86ISD::PSHUFLW:
21103 case X86ISD::PSHUFHW:
21104 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
21105 break;
21106 }
21107 }
21108 if (V.getValueType() != N.getValueType())
21109 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
21111 // Return the new chain to replace N.
21112 return V;
21113 }
21115 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
21116 ///
21117 /// We walk up the chain, skipping shuffles of the other half and looking
21118 /// through shuffles which switch halves trying to find a shuffle of the same
21119 /// pair of dwords.
21120 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
21121 SelectionDAG &DAG,
21122 TargetLowering::DAGCombinerInfo &DCI) {
21123 assert(
21124 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
21125 "Called with something other than an x86 128-bit half shuffle!");
21126 SDLoc DL(N);
21127 unsigned CombineOpcode = N.getOpcode();
21129 // Walk up a single-use chain looking for a combinable shuffle.
21130 SDValue V = N.getOperand(0);
21131 for (; V.hasOneUse(); V = V.getOperand(0)) {
21132 switch (V.getOpcode()) {
21133 default:
21134 return false; // Nothing combined!
21136 case ISD::BITCAST:
21137 // Skip bitcasts as we always know the type for the target specific
21138 // instructions.
21139 continue;
21141 case X86ISD::PSHUFLW:
21142 case X86ISD::PSHUFHW:
21143 if (V.getOpcode() == CombineOpcode)
21144 break;
21146 // Other-half shuffles are no-ops.
21147 continue;
21148 }
21149 // Break out of the loop if we break out of the switch.
21150 break;
21151 }
21153 if (!V.hasOneUse())
21154 // We fell out of the loop without finding a viable combining instruction.
21155 return false;
21157 // Combine away the bottom node as its shuffle will be accumulated into
21158 // a preceding shuffle.
21159 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21161 // Record the old value.
21162 SDValue Old = V;
21164 // Merge this node's mask and our incoming mask (adjusted to account for all
21165 // the pshufd instructions encountered).
21166 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21167 for (int &M : Mask)
21168 M = VMask[M];
21169 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
21170 getV4X86ShuffleImm8ForMask(Mask, DAG));
21172 // Check that the shuffles didn't cancel each other out. If not, we need to
21173 // combine to the new one.
21174 if (Old != V)
21175 // Replace the combinable shuffle with the combined one, updating all users
21176 // so that we re-evaluate the chain here.
21177 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
21179 return true;
21180 }
21182 /// \brief Try to combine x86 target specific shuffles.
21183 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
21184 TargetLowering::DAGCombinerInfo &DCI,
21185 const X86Subtarget *Subtarget) {
21186 SDLoc DL(N);
21187 MVT VT = N.getSimpleValueType();
21188 SmallVector<int, 4> Mask;
21190 switch (N.getOpcode()) {
21191 case X86ISD::PSHUFD:
21192 case X86ISD::PSHUFLW:
21193 case X86ISD::PSHUFHW:
21194 Mask = getPSHUFShuffleMask(N);
21195 assert(Mask.size() == 4);
21196 break;
21197 default:
21198 return SDValue();
21199 }
21201 // Nuke no-op shuffles that show up after combining.
21202 if (isNoopShuffleMask(Mask))
21203 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21205 // Look for simplifications involving one or two shuffle instructions.
21206 SDValue V = N.getOperand(0);
21207 switch (N.getOpcode()) {
21208 default:
21209 break;
21210 case X86ISD::PSHUFLW:
21211 case X86ISD::PSHUFHW:
21212 assert(VT == MVT::v8i16);
21213 (void)VT;
21215 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
21216 return SDValue(); // We combined away this shuffle, so we're done.
21218 // See if this reduces to a PSHUFD which is no more expensive and can
21219 // combine with more operations. Note that it has to at least flip the
21220 // dwords as otherwise it would have been removed as a no-op.
21221 if (Mask[0] == 2 && Mask[1] == 3 && Mask[2] == 0 && Mask[3] == 1) {
21222 int DMask[] = {0, 1, 2, 3};
21223 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
21224 DMask[DOffset + 0] = DOffset + 1;
21225 DMask[DOffset + 1] = DOffset + 0;
21226 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
21227 DCI.AddToWorklist(V.getNode());
21228 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
21229 getV4X86ShuffleImm8ForMask(DMask, DAG));
21230 DCI.AddToWorklist(V.getNode());
21231 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
21232 }
21234 // Look for shuffle patterns which can be implemented as a single unpack.
21235 // FIXME: This doesn't handle the location of the PSHUFD generically, and
21236 // only works when we have a PSHUFD followed by two half-shuffles.
21237 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
21238 (V.getOpcode() == X86ISD::PSHUFLW ||
21239 V.getOpcode() == X86ISD::PSHUFHW) &&
21240 V.getOpcode() != N.getOpcode() &&
21241 V.hasOneUse()) {
21242 SDValue D = V.getOperand(0);
21243 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
21244 D = D.getOperand(0);
21245 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
21246 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21247 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
21248 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21249 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21250 int WordMask[8];
21251 for (int i = 0; i < 4; ++i) {
21252 WordMask[i + NOffset] = Mask[i] + NOffset;
21253 WordMask[i + VOffset] = VMask[i] + VOffset;
21254 }
21255 // Map the word mask through the DWord mask.
21256 int MappedMask[8];
21257 for (int i = 0; i < 8; ++i)
21258 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
21259 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
21260 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
21261 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
21262 std::begin(UnpackLoMask)) ||
21263 std::equal(std::begin(MappedMask), std::end(MappedMask),
21264 std::begin(UnpackHiMask))) {
21265 // We can replace all three shuffles with an unpack.
21266 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
21267 DCI.AddToWorklist(V.getNode());
21268 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
21269 : X86ISD::UNPCKH,
21270 DL, MVT::v8i16, V, V);
21271 }
21272 }
21273 }
21275 break;
21277 case X86ISD::PSHUFD:
21278 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
21279 return NewN;
21281 break;
21282 }
21284 return SDValue();
21285 }
21287 /// \brief Try to combine a shuffle into a target-specific add-sub node.
21288 ///
21289 /// We combine this directly on the abstract vector shuffle nodes so it is
21290 /// easier to generically match. We also insert dummy vector shuffle nodes for
21291 /// the operands which explicitly discard the lanes which are unused by this
21292 /// operation to try to flow through the rest of the combiner the fact that
21293 /// they're unused.
21294 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
21295 SDLoc DL(N);
21296 EVT VT = N->getValueType(0);
21298 // We only handle target-independent shuffles.
21299 // FIXME: It would be easy and harmless to use the target shuffle mask
21300 // extraction tool to support more.
21301 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
21302 return SDValue();
21304 auto *SVN = cast<ShuffleVectorSDNode>(N);
21305 ArrayRef<int> Mask = SVN->getMask();
21306 SDValue V1 = N->getOperand(0);
21307 SDValue V2 = N->getOperand(1);
21309 // We require the first shuffle operand to be the SUB node, and the second to
21310 // be the ADD node.
21311 // FIXME: We should support the commuted patterns.
21312 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
21313 return SDValue();
21315 // If there are other uses of these operations we can't fold them.
21316 if (!V1->hasOneUse() || !V2->hasOneUse())
21317 return SDValue();
21319 // Ensure that both operations have the same operands. Note that we can
21320 // commute the FADD operands.
21321 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
21322 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
21323 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
21324 return SDValue();
21326 // We're looking for blends between FADD and FSUB nodes. We insist on these
21327 // nodes being lined up in a specific expected pattern.
21328 if (!(isShuffleEquivalent(Mask, 0, 3) ||
21329 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
21330 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
21331 return SDValue();
21333 // Only specific types are legal at this point, assert so we notice if and
21334 // when these change.
21335 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
21336 VT == MVT::v4f64) &&
21337 "Unknown vector type encountered!");
21339 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
21340 }
21342 /// PerformShuffleCombine - Performs several different shuffle combines.
21343 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
21344 TargetLowering::DAGCombinerInfo &DCI,
21345 const X86Subtarget *Subtarget) {
21346 SDLoc dl(N);
21347 SDValue N0 = N->getOperand(0);
21348 SDValue N1 = N->getOperand(1);
21349 EVT VT = N->getValueType(0);
21351 // Don't create instructions with illegal types after legalize types has run.
21352 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21353 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
21354 return SDValue();
21356 // If we have legalized the vector types, look for blends of FADD and FSUB
21357 // nodes that we can fuse into an ADDSUB node.
21358 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
21359 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
21360 return AddSub;
21362 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
21363 if (Subtarget->hasFp256() && VT.is256BitVector() &&
21364 N->getOpcode() == ISD::VECTOR_SHUFFLE)
21365 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
21367 // During Type Legalization, when promoting illegal vector types,
21368 // the backend might introduce new shuffle dag nodes and bitcasts.
21369 //
21370 // This code performs the following transformation:
21371 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
21372 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
21373 //
21374 // We do this only if both the bitcast and the BINOP dag nodes have
21375 // one use. Also, perform this transformation only if the new binary
21376 // operation is legal. This is to avoid introducing dag nodes that
21377 // potentially need to be further expanded (or custom lowered) into a
21378 // less optimal sequence of dag nodes.
21379 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
21380 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
21381 N0.getOpcode() == ISD::BITCAST) {
21382 SDValue BC0 = N0.getOperand(0);
21383 EVT SVT = BC0.getValueType();
21384 unsigned Opcode = BC0.getOpcode();
21385 unsigned NumElts = VT.getVectorNumElements();
21387 if (BC0.hasOneUse() && SVT.isVector() &&
21388 SVT.getVectorNumElements() * 2 == NumElts &&
21389 TLI.isOperationLegal(Opcode, VT)) {
21390 bool CanFold = false;
21391 switch (Opcode) {
21392 default : break;
21393 case ISD::ADD :
21394 case ISD::FADD :
21395 case ISD::SUB :
21396 case ISD::FSUB :
21397 case ISD::MUL :
21398 case ISD::FMUL :
21399 CanFold = true;
21400 }
21402 unsigned SVTNumElts = SVT.getVectorNumElements();
21403 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21404 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
21405 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
21406 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
21407 CanFold = SVOp->getMaskElt(i) < 0;
21409 if (CanFold) {
21410 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
21411 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
21412 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
21413 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
21414 }
21415 }
21416 }
21418 // Only handle 128 wide vector from here on.
21419 if (!VT.is128BitVector())
21420 return SDValue();
21422 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
21423 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
21424 // consecutive, non-overlapping, and in the right order.
21425 SmallVector<SDValue, 16> Elts;
21426 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
21427 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
21429 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
21430 if (LD.getNode())
21431 return LD;
21433 if (isTargetShuffle(N->getOpcode())) {
21434 SDValue Shuffle =
21435 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
21436 if (Shuffle.getNode())
21437 return Shuffle;
21439 // Try recursively combining arbitrary sequences of x86 shuffle
21440 // instructions into higher-order shuffles. We do this after combining
21441 // specific PSHUF instruction sequences into their minimal form so that we
21442 // can evaluate how many specialized shuffle instructions are involved in
21443 // a particular chain.
21444 SmallVector<int, 1> NonceMask; // Just a placeholder.
21445 NonceMask.push_back(0);
21446 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
21447 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
21448 DCI, Subtarget))
21449 return SDValue(); // This routine will use CombineTo to replace N.
21450 }
21452 return SDValue();
21453 }
21455 /// PerformTruncateCombine - Converts truncate operation to
21456 /// a sequence of vector shuffle operations.
21457 /// It is possible when we truncate 256-bit vector to 128-bit vector
21458 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
21459 TargetLowering::DAGCombinerInfo &DCI,
21460 const X86Subtarget *Subtarget) {
21461 return SDValue();
21462 }
21464 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
21465 /// specific shuffle of a load can be folded into a single element load.
21466 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
21467 /// shuffles have been customed lowered so we need to handle those here.
21468 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
21469 TargetLowering::DAGCombinerInfo &DCI) {
21470 if (DCI.isBeforeLegalizeOps())
21471 return SDValue();
21473 SDValue InVec = N->getOperand(0);
21474 SDValue EltNo = N->getOperand(1);
21476 if (!isa<ConstantSDNode>(EltNo))
21477 return SDValue();
21479 EVT VT = InVec.getValueType();
21481 if (InVec.getOpcode() == ISD::BITCAST) {
21482 // Don't duplicate a load with other uses.
21483 if (!InVec.hasOneUse())
21484 return SDValue();
21485 EVT BCVT = InVec.getOperand(0).getValueType();
21486 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
21487 return SDValue();
21488 InVec = InVec.getOperand(0);
21489 }
21491 if (!isTargetShuffle(InVec.getOpcode()))
21492 return SDValue();
21494 // Don't duplicate a load with other uses.
21495 if (!InVec.hasOneUse())
21496 return SDValue();
21498 SmallVector<int, 16> ShuffleMask;
21499 bool UnaryShuffle;
21500 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
21501 UnaryShuffle))
21502 return SDValue();
21504 // Select the input vector, guarding against out of range extract vector.
21505 unsigned NumElems = VT.getVectorNumElements();
21506 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
21507 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
21508 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
21509 : InVec.getOperand(1);
21511 // If inputs to shuffle are the same for both ops, then allow 2 uses
21512 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
21514 if (LdNode.getOpcode() == ISD::BITCAST) {
21515 // Don't duplicate a load with other uses.
21516 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
21517 return SDValue();
21519 AllowedUses = 1; // only allow 1 load use if we have a bitcast
21520 LdNode = LdNode.getOperand(0);
21521 }
21523 if (!ISD::isNormalLoad(LdNode.getNode()))
21524 return SDValue();
21526 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
21528 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
21529 return SDValue();
21531 EVT EltVT = N->getValueType(0);
21532 // If there's a bitcast before the shuffle, check if the load type and
21533 // alignment is valid.
21534 unsigned Align = LN0->getAlignment();
21535 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21536 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
21537 EltVT.getTypeForEVT(*DAG.getContext()));
21539 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
21540 return SDValue();
21542 // All checks match so transform back to vector_shuffle so that DAG combiner
21543 // can finish the job
21544 SDLoc dl(N);
21546 // Create shuffle node taking into account the case that its a unary shuffle
21547 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
21548 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
21549 InVec.getOperand(0), Shuffle,
21550 &ShuffleMask[0]);
21551 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
21552 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
21553 EltNo);
21554 }
21556 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
21557 /// generation and convert it from being a bunch of shuffles and extracts
21558 /// to a simple store and scalar loads to extract the elements.
21559 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
21560 TargetLowering::DAGCombinerInfo &DCI) {
21561 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
21562 if (NewOp.getNode())
21563 return NewOp;
21565 SDValue InputVector = N->getOperand(0);
21567 // Detect whether we are trying to convert from mmx to i32 and the bitcast
21568 // from mmx to v2i32 has a single usage.
21569 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
21570 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
21571 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
21572 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
21573 N->getValueType(0),
21574 InputVector.getNode()->getOperand(0));
21576 // Only operate on vectors of 4 elements, where the alternative shuffling
21577 // gets to be more expensive.
21578 if (InputVector.getValueType() != MVT::v4i32)
21579 return SDValue();
21581 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
21582 // single use which is a sign-extend or zero-extend, and all elements are
21583 // used.
21584 SmallVector<SDNode *, 4> Uses;
21585 unsigned ExtractedElements = 0;
21586 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
21587 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
21588 if (UI.getUse().getResNo() != InputVector.getResNo())
21589 return SDValue();
21591 SDNode *Extract = *UI;
21592 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
21593 return SDValue();
21595 if (Extract->getValueType(0) != MVT::i32)
21596 return SDValue();
21597 if (!Extract->hasOneUse())
21598 return SDValue();
21599 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
21600 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
21601 return SDValue();
21602 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
21603 return SDValue();
21605 // Record which element was extracted.
21606 ExtractedElements |=
21607 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
21609 Uses.push_back(Extract);
21610 }
21612 // If not all the elements were used, this may not be worthwhile.
21613 if (ExtractedElements != 15)
21614 return SDValue();
21616 // Ok, we've now decided to do the transformation.
21617 SDLoc dl(InputVector);
21619 // Store the value to a temporary stack slot.
21620 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
21621 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
21622 MachinePointerInfo(), false, false, 0);
21624 // Replace each use (extract) with a load of the appropriate element.
21625 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
21626 UE = Uses.end(); UI != UE; ++UI) {
21627 SDNode *Extract = *UI;
21629 // cOMpute the element's address.
21630 SDValue Idx = Extract->getOperand(1);
21631 unsigned EltSize =
21632 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
21633 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
21634 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21635 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
21637 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
21638 StackPtr, OffsetVal);
21640 // Load the scalar.
21641 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
21642 ScalarAddr, MachinePointerInfo(),
21643 false, false, false, 0);
21645 // Replace the exact with the load.
21646 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
21647 }
21649 // The replacement was made in place; don't return anything.
21650 return SDValue();
21651 }
21653 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
21654 static std::pair<unsigned, bool>
21655 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
21656 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
21657 if (!VT.isVector())
21658 return std::make_pair(0, false);
21660 bool NeedSplit = false;
21661 switch (VT.getSimpleVT().SimpleTy) {
21662 default: return std::make_pair(0, false);
21663 case MVT::v32i8:
21664 case MVT::v16i16:
21665 case MVT::v8i32:
21666 if (!Subtarget->hasAVX2())
21667 NeedSplit = true;
21668 if (!Subtarget->hasAVX())
21669 return std::make_pair(0, false);
21670 break;
21671 case MVT::v16i8:
21672 case MVT::v8i16:
21673 case MVT::v4i32:
21674 if (!Subtarget->hasSSE2())
21675 return std::make_pair(0, false);
21676 }
21678 // SSE2 has only a small subset of the operations.
21679 bool hasUnsigned = Subtarget->hasSSE41() ||
21680 (Subtarget->hasSSE2() && VT == MVT::v16i8);
21681 bool hasSigned = Subtarget->hasSSE41() ||
21682 (Subtarget->hasSSE2() && VT == MVT::v8i16);
21684 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21686 unsigned Opc = 0;
21687 // Check for x CC y ? x : y.
21688 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21689 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21690 switch (CC) {
21691 default: break;
21692 case ISD::SETULT:
21693 case ISD::SETULE:
21694 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
21695 case ISD::SETUGT:
21696 case ISD::SETUGE:
21697 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
21698 case ISD::SETLT:
21699 case ISD::SETLE:
21700 Opc = hasSigned ? X86ISD::SMIN : 0; break;
21701 case ISD::SETGT:
21702 case ISD::SETGE:
21703 Opc = hasSigned ? X86ISD::SMAX : 0; break;
21704 }
21705 // Check for x CC y ? y : x -- a min/max with reversed arms.
21706 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21707 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21708 switch (CC) {
21709 default: break;
21710 case ISD::SETULT:
21711 case ISD::SETULE:
21712 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
21713 case ISD::SETUGT:
21714 case ISD::SETUGE:
21715 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
21716 case ISD::SETLT:
21717 case ISD::SETLE:
21718 Opc = hasSigned ? X86ISD::SMAX : 0; break;
21719 case ISD::SETGT:
21720 case ISD::SETGE:
21721 Opc = hasSigned ? X86ISD::SMIN : 0; break;
21722 }
21723 }
21725 return std::make_pair(Opc, NeedSplit);
21726 }
21728 static SDValue
21729 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
21730 const X86Subtarget *Subtarget) {
21731 SDLoc dl(N);
21732 SDValue Cond = N->getOperand(0);
21733 SDValue LHS = N->getOperand(1);
21734 SDValue RHS = N->getOperand(2);
21736 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
21737 SDValue CondSrc = Cond->getOperand(0);
21738 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
21739 Cond = CondSrc->getOperand(0);
21740 }
21742 MVT VT = N->getSimpleValueType(0);
21743 MVT EltVT = VT.getVectorElementType();
21744 unsigned NumElems = VT.getVectorNumElements();
21745 // There is no blend with immediate in AVX-512.
21746 if (VT.is512BitVector())
21747 return SDValue();
21749 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
21750 return SDValue();
21751 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
21752 return SDValue();
21754 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
21755 return SDValue();
21757 // A vselect where all conditions and data are constants can be optimized into
21758 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
21759 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
21760 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
21761 return SDValue();
21763 unsigned MaskValue = 0;
21764 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
21765 return SDValue();
21767 SmallVector<int, 8> ShuffleMask(NumElems, -1);
21768 for (unsigned i = 0; i < NumElems; ++i) {
21769 // Be sure we emit undef where we can.
21770 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
21771 ShuffleMask[i] = -1;
21772 else
21773 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
21774 }
21776 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
21777 }
21779 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
21780 /// nodes.
21781 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
21782 TargetLowering::DAGCombinerInfo &DCI,
21783 const X86Subtarget *Subtarget) {
21784 SDLoc DL(N);
21785 SDValue Cond = N->getOperand(0);
21786 // Get the LHS/RHS of the select.
21787 SDValue LHS = N->getOperand(1);
21788 SDValue RHS = N->getOperand(2);
21789 EVT VT = LHS.getValueType();
21790 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21792 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
21793 // instructions match the semantics of the common C idiom x<y?x:y but not
21794 // x<=y?x:y, because of how they handle negative zero (which can be
21795 // ignored in unsafe-math mode).
21796 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
21797 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
21798 (Subtarget->hasSSE2() ||
21799 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
21800 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21802 unsigned Opcode = 0;
21803 // Check for x CC y ? x : y.
21804 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21805 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21806 switch (CC) {
21807 default: break;
21808 case ISD::SETULT:
21809 // Converting this to a min would handle NaNs incorrectly, and swapping
21810 // the operands would cause it to handle comparisons between positive
21811 // and negative zero incorrectly.
21812 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21813 if (!DAG.getTarget().Options.UnsafeFPMath &&
21814 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21815 break;
21816 std::swap(LHS, RHS);
21817 }
21818 Opcode = X86ISD::FMIN;
21819 break;
21820 case ISD::SETOLE:
21821 // Converting this to a min would handle comparisons between positive
21822 // and negative zero incorrectly.
21823 if (!DAG.getTarget().Options.UnsafeFPMath &&
21824 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21825 break;
21826 Opcode = X86ISD::FMIN;
21827 break;
21828 case ISD::SETULE:
21829 // Converting this to a min would handle both negative zeros and NaNs
21830 // incorrectly, but we can swap the operands to fix both.
21831 std::swap(LHS, RHS);
21832 case ISD::SETOLT:
21833 case ISD::SETLT:
21834 case ISD::SETLE:
21835 Opcode = X86ISD::FMIN;
21836 break;
21838 case ISD::SETOGE:
21839 // Converting this to a max would handle comparisons between positive
21840 // and negative zero incorrectly.
21841 if (!DAG.getTarget().Options.UnsafeFPMath &&
21842 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21843 break;
21844 Opcode = X86ISD::FMAX;
21845 break;
21846 case ISD::SETUGT:
21847 // Converting this to a max would handle NaNs incorrectly, and swapping
21848 // the operands would cause it to handle comparisons between positive
21849 // and negative zero incorrectly.
21850 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21851 if (!DAG.getTarget().Options.UnsafeFPMath &&
21852 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21853 break;
21854 std::swap(LHS, RHS);
21855 }
21856 Opcode = X86ISD::FMAX;
21857 break;
21858 case ISD::SETUGE:
21859 // Converting this to a max would handle both negative zeros and NaNs
21860 // incorrectly, but we can swap the operands to fix both.
21861 std::swap(LHS, RHS);
21862 case ISD::SETOGT:
21863 case ISD::SETGT:
21864 case ISD::SETGE:
21865 Opcode = X86ISD::FMAX;
21866 break;
21867 }
21868 // Check for x CC y ? y : x -- a min/max with reversed arms.
21869 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21870 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21871 switch (CC) {
21872 default: break;
21873 case ISD::SETOGE:
21874 // Converting this to a min would handle comparisons between positive
21875 // and negative zero incorrectly, and swapping the operands would
21876 // cause it to handle NaNs incorrectly.
21877 if (!DAG.getTarget().Options.UnsafeFPMath &&
21878 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
21879 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21880 break;
21881 std::swap(LHS, RHS);
21882 }
21883 Opcode = X86ISD::FMIN;
21884 break;
21885 case ISD::SETUGT:
21886 // Converting this to a min would handle NaNs incorrectly.
21887 if (!DAG.getTarget().Options.UnsafeFPMath &&
21888 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
21889 break;
21890 Opcode = X86ISD::FMIN;
21891 break;
21892 case ISD::SETUGE:
21893 // Converting this to a min would handle both negative zeros and NaNs
21894 // incorrectly, but we can swap the operands to fix both.
21895 std::swap(LHS, RHS);
21896 case ISD::SETOGT:
21897 case ISD::SETGT:
21898 case ISD::SETGE:
21899 Opcode = X86ISD::FMIN;
21900 break;
21902 case ISD::SETULT:
21903 // Converting this to a max would handle NaNs incorrectly.
21904 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21905 break;
21906 Opcode = X86ISD::FMAX;
21907 break;
21908 case ISD::SETOLE:
21909 // Converting this to a max would handle comparisons between positive
21910 // and negative zero incorrectly, and swapping the operands would
21911 // cause it to handle NaNs incorrectly.
21912 if (!DAG.getTarget().Options.UnsafeFPMath &&
21913 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
21914 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21915 break;
21916 std::swap(LHS, RHS);
21917 }
21918 Opcode = X86ISD::FMAX;
21919 break;
21920 case ISD::SETULE:
21921 // Converting this to a max would handle both negative zeros and NaNs
21922 // incorrectly, but we can swap the operands to fix both.
21923 std::swap(LHS, RHS);
21924 case ISD::SETOLT:
21925 case ISD::SETLT:
21926 case ISD::SETLE:
21927 Opcode = X86ISD::FMAX;
21928 break;
21929 }
21930 }
21932 if (Opcode)
21933 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
21934 }
21936 EVT CondVT = Cond.getValueType();
21937 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
21938 CondVT.getVectorElementType() == MVT::i1) {
21939 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
21940 // lowering on KNL. In this case we convert it to
21941 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
21942 // The same situation for all 128 and 256-bit vectors of i8 and i16.
21943 // Since SKX these selects have a proper lowering.
21944 EVT OpVT = LHS.getValueType();
21945 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
21946 (OpVT.getVectorElementType() == MVT::i8 ||
21947 OpVT.getVectorElementType() == MVT::i16) &&
21948 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
21949 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
21950 DCI.AddToWorklist(Cond.getNode());
21951 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
21952 }
21953 }
21954 // If this is a select between two integer constants, try to do some
21955 // optimizations.
21956 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
21957 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
21958 // Don't do this for crazy integer types.
21959 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
21960 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
21961 // so that TrueC (the true value) is larger than FalseC.
21962 bool NeedsCondInvert = false;
21964 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
21965 // Efficiently invertible.
21966 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
21967 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
21968 isa<ConstantSDNode>(Cond.getOperand(1))))) {
21969 NeedsCondInvert = true;
21970 std::swap(TrueC, FalseC);
21971 }
21973 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
21974 if (FalseC->getAPIntValue() == 0 &&
21975 TrueC->getAPIntValue().isPowerOf2()) {
21976 if (NeedsCondInvert) // Invert the condition if needed.
21977 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21978 DAG.getConstant(1, Cond.getValueType()));
21980 // Zero extend the condition if needed.
21981 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
21983 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21984 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
21985 DAG.getConstant(ShAmt, MVT::i8));
21986 }
21988 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
21989 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21990 if (NeedsCondInvert) // Invert the condition if needed.
21991 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21992 DAG.getConstant(1, Cond.getValueType()));
21994 // Zero extend the condition if needed.
21995 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21996 FalseC->getValueType(0), Cond);
21997 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21998 SDValue(FalseC, 0));
21999 }
22001 // Optimize cases that will turn into an LEA instruction. This requires
22002 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22003 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22004 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22005 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22007 bool isFastMultiplier = false;
22008 if (Diff < 10) {
22009 switch ((unsigned char)Diff) {
22010 default: break;
22011 case 1: // result = add base, cond
22012 case 2: // result = lea base( , cond*2)
22013 case 3: // result = lea base(cond, cond*2)
22014 case 4: // result = lea base( , cond*4)
22015 case 5: // result = lea base(cond, cond*4)
22016 case 8: // result = lea base( , cond*8)
22017 case 9: // result = lea base(cond, cond*8)
22018 isFastMultiplier = true;
22019 break;
22020 }
22021 }
22023 if (isFastMultiplier) {
22024 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22025 if (NeedsCondInvert) // Invert the condition if needed.
22026 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22027 DAG.getConstant(1, Cond.getValueType()));
22029 // Zero extend the condition if needed.
22030 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22031 Cond);
22032 // Scale the condition by the difference.
22033 if (Diff != 1)
22034 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22035 DAG.getConstant(Diff, Cond.getValueType()));
22037 // Add the base if non-zero.
22038 if (FalseC->getAPIntValue() != 0)
22039 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22040 SDValue(FalseC, 0));
22041 return Cond;
22042 }
22043 }
22044 }
22045 }
22047 // Canonicalize max and min:
22048 // (x > y) ? x : y -> (x >= y) ? x : y
22049 // (x < y) ? x : y -> (x <= y) ? x : y
22050 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
22051 // the need for an extra compare
22052 // against zero. e.g.
22053 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
22054 // subl %esi, %edi
22055 // testl %edi, %edi
22056 // movl $0, %eax
22057 // cmovgl %edi, %eax
22058 // =>
22059 // xorl %eax, %eax
22060 // subl %esi, $edi
22061 // cmovsl %eax, %edi
22062 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
22063 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22064 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22065 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22066 switch (CC) {
22067 default: break;
22068 case ISD::SETLT:
22069 case ISD::SETGT: {
22070 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
22071 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
22072 Cond.getOperand(0), Cond.getOperand(1), NewCC);
22073 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
22074 }
22075 }
22076 }
22078 // Early exit check
22079 if (!TLI.isTypeLegal(VT))
22080 return SDValue();
22082 // Match VSELECTs into subs with unsigned saturation.
22083 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
22084 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
22085 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
22086 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
22087 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22089 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
22090 // left side invert the predicate to simplify logic below.
22091 SDValue Other;
22092 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
22093 Other = RHS;
22094 CC = ISD::getSetCCInverse(CC, true);
22095 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
22096 Other = LHS;
22097 }
22099 if (Other.getNode() && Other->getNumOperands() == 2 &&
22100 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
22101 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
22102 SDValue CondRHS = Cond->getOperand(1);
22104 // Look for a general sub with unsigned saturation first.
22105 // x >= y ? x-y : 0 --> subus x, y
22106 // x > y ? x-y : 0 --> subus x, y
22107 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
22108 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
22109 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
22111 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
22112 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
22113 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
22114 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
22115 // If the RHS is a constant we have to reverse the const
22116 // canonicalization.
22117 // x > C-1 ? x+-C : 0 --> subus x, C
22118 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
22119 CondRHSConst->getAPIntValue() ==
22120 (-OpRHSConst->getAPIntValue() - 1))
22121 return DAG.getNode(
22122 X86ISD::SUBUS, DL, VT, OpLHS,
22123 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
22125 // Another special case: If C was a sign bit, the sub has been
22126 // canonicalized into a xor.
22127 // FIXME: Would it be better to use computeKnownBits to determine
22128 // whether it's safe to decanonicalize the xor?
22129 // x s< 0 ? x^C : 0 --> subus x, C
22130 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
22131 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
22132 OpRHSConst->getAPIntValue().isSignBit())
22133 // Note that we have to rebuild the RHS constant here to ensure we
22134 // don't rely on particular values of undef lanes.
22135 return DAG.getNode(
22136 X86ISD::SUBUS, DL, VT, OpLHS,
22137 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
22138 }
22139 }
22140 }
22142 // Try to match a min/max vector operation.
22143 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
22144 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
22145 unsigned Opc = ret.first;
22146 bool NeedSplit = ret.second;
22148 if (Opc && NeedSplit) {
22149 unsigned NumElems = VT.getVectorNumElements();
22150 // Extract the LHS vectors
22151 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
22152 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
22154 // Extract the RHS vectors
22155 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
22156 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
22158 // Create min/max for each subvector
22159 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
22160 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
22162 // Merge the result
22163 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
22164 } else if (Opc)
22165 return DAG.getNode(Opc, DL, VT, LHS, RHS);
22166 }
22168 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
22169 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
22170 // Check if SETCC has already been promoted
22171 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
22172 // Check that condition value type matches vselect operand type
22173 CondVT == VT) {
22175 assert(Cond.getValueType().isVector() &&
22176 "vector select expects a vector selector!");
22178 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
22179 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
22181 if (!TValIsAllOnes && !FValIsAllZeros) {
22182 // Try invert the condition if true value is not all 1s and false value
22183 // is not all 0s.
22184 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
22185 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
22187 if (TValIsAllZeros || FValIsAllOnes) {
22188 SDValue CC = Cond.getOperand(2);
22189 ISD::CondCode NewCC =
22190 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
22191 Cond.getOperand(0).getValueType().isInteger());
22192 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
22193 std::swap(LHS, RHS);
22194 TValIsAllOnes = FValIsAllOnes;
22195 FValIsAllZeros = TValIsAllZeros;
22196 }
22197 }
22199 if (TValIsAllOnes || FValIsAllZeros) {
22200 SDValue Ret;
22202 if (TValIsAllOnes && FValIsAllZeros)
22203 Ret = Cond;
22204 else if (TValIsAllOnes)
22205 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
22206 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
22207 else if (FValIsAllZeros)
22208 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
22209 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
22211 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
22212 }
22213 }
22215 // Try to fold this VSELECT into a MOVSS/MOVSD
22216 if (N->getOpcode() == ISD::VSELECT &&
22217 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
22218 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
22219 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
22220 bool CanFold = false;
22221 unsigned NumElems = Cond.getNumOperands();
22222 SDValue A = LHS;
22223 SDValue B = RHS;
22225 if (isZero(Cond.getOperand(0))) {
22226 CanFold = true;
22228 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
22229 // fold (vselect <0,-1> -> (movsd A, B)
22230 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
22231 CanFold = isAllOnes(Cond.getOperand(i));
22232 } else if (isAllOnes(Cond.getOperand(0))) {
22233 CanFold = true;
22234 std::swap(A, B);
22236 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
22237 // fold (vselect <-1,0> -> (movsd B, A)
22238 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
22239 CanFold = isZero(Cond.getOperand(i));
22240 }
22242 if (CanFold) {
22243 if (VT == MVT::v4i32 || VT == MVT::v4f32)
22244 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
22245 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
22246 }
22248 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
22249 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
22250 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
22251 // (v2i64 (bitcast B)))))
22252 //
22253 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
22254 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
22255 // (v2f64 (bitcast B)))))
22256 //
22257 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
22258 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
22259 // (v2i64 (bitcast A)))))
22260 //
22261 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
22262 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
22263 // (v2f64 (bitcast A)))))
22265 CanFold = (isZero(Cond.getOperand(0)) &&
22266 isZero(Cond.getOperand(1)) &&
22267 isAllOnes(Cond.getOperand(2)) &&
22268 isAllOnes(Cond.getOperand(3)));
22270 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
22271 isAllOnes(Cond.getOperand(1)) &&
22272 isZero(Cond.getOperand(2)) &&
22273 isZero(Cond.getOperand(3))) {
22274 CanFold = true;
22275 std::swap(LHS, RHS);
22276 }
22278 if (CanFold) {
22279 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
22280 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
22281 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
22282 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
22283 NewB, DAG);
22284 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
22285 }
22286 }
22287 }
22288 }
22290 // If we know that this node is legal then we know that it is going to be
22291 // matched by one of the SSE/AVX BLEND instructions. These instructions only
22292 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
22293 // to simplify previous instructions.
22294 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
22295 !DCI.isBeforeLegalize() &&
22296 // We explicitly check against v8i16 and v16i16 because, although
22297 // they're marked as Custom, they might only be legal when Cond is a
22298 // build_vector of constants. This will be taken care in a later
22299 // condition.
22300 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
22301 VT != MVT::v8i16)) {
22302 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
22304 // Don't optimize vector selects that map to mask-registers.
22305 if (BitWidth == 1)
22306 return SDValue();
22308 // Check all uses of that condition operand to check whether it will be
22309 // consumed by non-BLEND instructions, which may depend on all bits are set
22310 // properly.
22311 for (SDNode::use_iterator I = Cond->use_begin(),
22312 E = Cond->use_end(); I != E; ++I)
22313 if (I->getOpcode() != ISD::VSELECT)
22314 // TODO: Add other opcodes eventually lowered into BLEND.
22315 return SDValue();
22317 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
22318 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
22320 APInt KnownZero, KnownOne;
22321 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
22322 DCI.isBeforeLegalizeOps());
22323 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
22324 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
22325 DCI.CommitTargetLoweringOpt(TLO);
22326 }
22328 // We should generate an X86ISD::BLENDI from a vselect if its argument
22329 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
22330 // constants. This specific pattern gets generated when we split a
22331 // selector for a 512 bit vector in a machine without AVX512 (but with
22332 // 256-bit vectors), during legalization:
22333 //
22334 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
22335 //
22336 // Iff we find this pattern and the build_vectors are built from
22337 // constants, we translate the vselect into a shuffle_vector that we
22338 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
22339 if (N->getOpcode() == ISD::VSELECT && !DCI.isBeforeLegalize()) {
22340 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
22341 if (Shuffle.getNode())
22342 return Shuffle;
22343 }
22345 return SDValue();
22346 }
22348 // Check whether a boolean test is testing a boolean value generated by
22349 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
22350 // code.
22351 //
22352 // Simplify the following patterns:
22353 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
22354 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
22355 // to (Op EFLAGS Cond)
22356 //
22357 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
22358 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
22359 // to (Op EFLAGS !Cond)
22360 //
22361 // where Op could be BRCOND or CMOV.
22362 //
22363 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
22364 // Quit if not CMP and SUB with its value result used.
22365 if (Cmp.getOpcode() != X86ISD::CMP &&
22366 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
22367 return SDValue();
22369 // Quit if not used as a boolean value.
22370 if (CC != X86::COND_E && CC != X86::COND_NE)
22371 return SDValue();
22373 // Check CMP operands. One of them should be 0 or 1 and the other should be
22374 // an SetCC or extended from it.
22375 SDValue Op1 = Cmp.getOperand(0);
22376 SDValue Op2 = Cmp.getOperand(1);
22378 SDValue SetCC;
22379 const ConstantSDNode* C = nullptr;
22380 bool needOppositeCond = (CC == X86::COND_E);
22381 bool checkAgainstTrue = false; // Is it a comparison against 1?
22383 if ((C = dyn_cast<ConstantSDNode>(Op1)))
22384 SetCC = Op2;
22385 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
22386 SetCC = Op1;
22387 else // Quit if all operands are not constants.
22388 return SDValue();
22390 if (C->getZExtValue() == 1) {
22391 needOppositeCond = !needOppositeCond;
22392 checkAgainstTrue = true;
22393 } else if (C->getZExtValue() != 0)
22394 // Quit if the constant is neither 0 or 1.
22395 return SDValue();
22397 bool truncatedToBoolWithAnd = false;
22398 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
22399 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
22400 SetCC.getOpcode() == ISD::TRUNCATE ||
22401 SetCC.getOpcode() == ISD::AND) {
22402 if (SetCC.getOpcode() == ISD::AND) {
22403 int OpIdx = -1;
22404 ConstantSDNode *CS;
22405 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
22406 CS->getZExtValue() == 1)
22407 OpIdx = 1;
22408 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
22409 CS->getZExtValue() == 1)
22410 OpIdx = 0;
22411 if (OpIdx == -1)
22412 break;
22413 SetCC = SetCC.getOperand(OpIdx);
22414 truncatedToBoolWithAnd = true;
22415 } else
22416 SetCC = SetCC.getOperand(0);
22417 }
22419 switch (SetCC.getOpcode()) {
22420 case X86ISD::SETCC_CARRY:
22421 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
22422 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
22423 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
22424 // truncated to i1 using 'and'.
22425 if (checkAgainstTrue && !truncatedToBoolWithAnd)
22426 break;
22427 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
22428 "Invalid use of SETCC_CARRY!");
22429 // FALL THROUGH
22430 case X86ISD::SETCC:
22431 // Set the condition code or opposite one if necessary.
22432 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
22433 if (needOppositeCond)
22434 CC = X86::GetOppositeBranchCondition(CC);
22435 return SetCC.getOperand(1);
22436 case X86ISD::CMOV: {
22437 // Check whether false/true value has canonical one, i.e. 0 or 1.
22438 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
22439 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
22440 // Quit if true value is not a constant.
22441 if (!TVal)
22442 return SDValue();
22443 // Quit if false value is not a constant.
22444 if (!FVal) {
22445 SDValue Op = SetCC.getOperand(0);
22446 // Skip 'zext' or 'trunc' node.
22447 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
22448 Op.getOpcode() == ISD::TRUNCATE)
22449 Op = Op.getOperand(0);
22450 // A special case for rdrand/rdseed, where 0 is set if false cond is
22451 // found.
22452 if ((Op.getOpcode() != X86ISD::RDRAND &&
22453 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
22454 return SDValue();
22455 }
22456 // Quit if false value is not the constant 0 or 1.
22457 bool FValIsFalse = true;
22458 if (FVal && FVal->getZExtValue() != 0) {
22459 if (FVal->getZExtValue() != 1)
22460 return SDValue();
22461 // If FVal is 1, opposite cond is needed.
22462 needOppositeCond = !needOppositeCond;
22463 FValIsFalse = false;
22464 }
22465 // Quit if TVal is not the constant opposite of FVal.
22466 if (FValIsFalse && TVal->getZExtValue() != 1)
22467 return SDValue();
22468 if (!FValIsFalse && TVal->getZExtValue() != 0)
22469 return SDValue();
22470 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
22471 if (needOppositeCond)
22472 CC = X86::GetOppositeBranchCondition(CC);
22473 return SetCC.getOperand(3);
22474 }
22475 }
22477 return SDValue();
22478 }
22480 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
22481 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
22482 TargetLowering::DAGCombinerInfo &DCI,
22483 const X86Subtarget *Subtarget) {
22484 SDLoc DL(N);
22486 // If the flag operand isn't dead, don't touch this CMOV.
22487 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
22488 return SDValue();
22490 SDValue FalseOp = N->getOperand(0);
22491 SDValue TrueOp = N->getOperand(1);
22492 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
22493 SDValue Cond = N->getOperand(3);
22495 if (CC == X86::COND_E || CC == X86::COND_NE) {
22496 switch (Cond.getOpcode()) {
22497 default: break;
22498 case X86ISD::BSR:
22499 case X86ISD::BSF:
22500 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
22501 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
22502 return (CC == X86::COND_E) ? FalseOp : TrueOp;
22503 }
22504 }
22506 SDValue Flags;
22508 Flags = checkBoolTestSetCCCombine(Cond, CC);
22509 if (Flags.getNode() &&
22510 // Extra check as FCMOV only supports a subset of X86 cond.
22511 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
22512 SDValue Ops[] = { FalseOp, TrueOp,
22513 DAG.getConstant(CC, MVT::i8), Flags };
22514 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
22515 }
22517 // If this is a select between two integer constants, try to do some
22518 // optimizations. Note that the operands are ordered the opposite of SELECT
22519 // operands.
22520 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
22521 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
22522 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
22523 // larger than FalseC (the false value).
22524 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
22525 CC = X86::GetOppositeBranchCondition(CC);
22526 std::swap(TrueC, FalseC);
22527 std::swap(TrueOp, FalseOp);
22528 }
22530 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
22531 // This is efficient for any integer data type (including i8/i16) and
22532 // shift amount.
22533 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
22534 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22535 DAG.getConstant(CC, MVT::i8), Cond);
22537 // Zero extend the condition if needed.
22538 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
22540 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22541 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
22542 DAG.getConstant(ShAmt, MVT::i8));
22543 if (N->getNumValues() == 2) // Dead flag value?
22544 return DCI.CombineTo(N, Cond, SDValue());
22545 return Cond;
22546 }
22548 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
22549 // for any integer data type, including i8/i16.
22550 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22551 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22552 DAG.getConstant(CC, MVT::i8), Cond);
22554 // Zero extend the condition if needed.
22555 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22556 FalseC->getValueType(0), Cond);
22557 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22558 SDValue(FalseC, 0));
22560 if (N->getNumValues() == 2) // Dead flag value?
22561 return DCI.CombineTo(N, Cond, SDValue());
22562 return Cond;
22563 }
22565 // Optimize cases that will turn into an LEA instruction. This requires
22566 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22567 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22568 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22569 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22571 bool isFastMultiplier = false;
22572 if (Diff < 10) {
22573 switch ((unsigned char)Diff) {
22574 default: break;
22575 case 1: // result = add base, cond
22576 case 2: // result = lea base( , cond*2)
22577 case 3: // result = lea base(cond, cond*2)
22578 case 4: // result = lea base( , cond*4)
22579 case 5: // result = lea base(cond, cond*4)
22580 case 8: // result = lea base( , cond*8)
22581 case 9: // result = lea base(cond, cond*8)
22582 isFastMultiplier = true;
22583 break;
22584 }
22585 }
22587 if (isFastMultiplier) {
22588 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22589 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22590 DAG.getConstant(CC, MVT::i8), Cond);
22591 // Zero extend the condition if needed.
22592 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22593 Cond);
22594 // Scale the condition by the difference.
22595 if (Diff != 1)
22596 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22597 DAG.getConstant(Diff, Cond.getValueType()));
22599 // Add the base if non-zero.
22600 if (FalseC->getAPIntValue() != 0)
22601 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22602 SDValue(FalseC, 0));
22603 if (N->getNumValues() == 2) // Dead flag value?
22604 return DCI.CombineTo(N, Cond, SDValue());
22605 return Cond;
22606 }
22607 }
22608 }
22609 }
22611 // Handle these cases:
22612 // (select (x != c), e, c) -> select (x != c), e, x),
22613 // (select (x == c), c, e) -> select (x == c), x, e)
22614 // where the c is an integer constant, and the "select" is the combination
22615 // of CMOV and CMP.
22616 //
22617 // The rationale for this change is that the conditional-move from a constant
22618 // needs two instructions, however, conditional-move from a register needs
22619 // only one instruction.
22620 //
22621 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
22622 // some instruction-combining opportunities. This opt needs to be
22623 // postponed as late as possible.
22624 //
22625 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
22626 // the DCI.xxxx conditions are provided to postpone the optimization as
22627 // late as possible.
22629 ConstantSDNode *CmpAgainst = nullptr;
22630 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
22631 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
22632 !isa<ConstantSDNode>(Cond.getOperand(0))) {
22634 if (CC == X86::COND_NE &&
22635 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
22636 CC = X86::GetOppositeBranchCondition(CC);
22637 std::swap(TrueOp, FalseOp);
22638 }
22640 if (CC == X86::COND_E &&
22641 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
22642 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
22643 DAG.getConstant(CC, MVT::i8), Cond };
22644 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
22645 }
22646 }
22647 }
22649 return SDValue();
22650 }
22652 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
22653 const X86Subtarget *Subtarget) {
22654 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
22655 switch (IntNo) {
22656 default: return SDValue();
22657 // SSE/AVX/AVX2 blend intrinsics.
22658 case Intrinsic::x86_avx2_pblendvb:
22659 case Intrinsic::x86_avx2_pblendw:
22660 case Intrinsic::x86_avx2_pblendd_128:
22661 case Intrinsic::x86_avx2_pblendd_256:
22662 // Don't try to simplify this intrinsic if we don't have AVX2.
22663 if (!Subtarget->hasAVX2())
22664 return SDValue();
22665 // FALL-THROUGH
22666 case Intrinsic::x86_avx_blend_pd_256:
22667 case Intrinsic::x86_avx_blend_ps_256:
22668 case Intrinsic::x86_avx_blendv_pd_256:
22669 case Intrinsic::x86_avx_blendv_ps_256:
22670 // Don't try to simplify this intrinsic if we don't have AVX.
22671 if (!Subtarget->hasAVX())
22672 return SDValue();
22673 // FALL-THROUGH
22674 case Intrinsic::x86_sse41_pblendw:
22675 case Intrinsic::x86_sse41_blendpd:
22676 case Intrinsic::x86_sse41_blendps:
22677 case Intrinsic::x86_sse41_blendvps:
22678 case Intrinsic::x86_sse41_blendvpd:
22679 case Intrinsic::x86_sse41_pblendvb: {
22680 SDValue Op0 = N->getOperand(1);
22681 SDValue Op1 = N->getOperand(2);
22682 SDValue Mask = N->getOperand(3);
22684 // Don't try to simplify this intrinsic if we don't have SSE4.1.
22685 if (!Subtarget->hasSSE41())
22686 return SDValue();
22688 // fold (blend A, A, Mask) -> A
22689 if (Op0 == Op1)
22690 return Op0;
22691 // fold (blend A, B, allZeros) -> A
22692 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
22693 return Op0;
22694 // fold (blend A, B, allOnes) -> B
22695 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
22696 return Op1;
22698 // Simplify the case where the mask is a constant i32 value.
22699 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
22700 if (C->isNullValue())
22701 return Op0;
22702 if (C->isAllOnesValue())
22703 return Op1;
22704 }
22706 return SDValue();
22707 }
22709 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
22710 case Intrinsic::x86_sse2_psrai_w:
22711 case Intrinsic::x86_sse2_psrai_d:
22712 case Intrinsic::x86_avx2_psrai_w:
22713 case Intrinsic::x86_avx2_psrai_d:
22714 case Intrinsic::x86_sse2_psra_w:
22715 case Intrinsic::x86_sse2_psra_d:
22716 case Intrinsic::x86_avx2_psra_w:
22717 case Intrinsic::x86_avx2_psra_d: {
22718 SDValue Op0 = N->getOperand(1);
22719 SDValue Op1 = N->getOperand(2);
22720 EVT VT = Op0.getValueType();
22721 assert(VT.isVector() && "Expected a vector type!");
22723 if (isa<BuildVectorSDNode>(Op1))
22724 Op1 = Op1.getOperand(0);
22726 if (!isa<ConstantSDNode>(Op1))
22727 return SDValue();
22729 EVT SVT = VT.getVectorElementType();
22730 unsigned SVTBits = SVT.getSizeInBits();
22732 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
22733 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
22734 uint64_t ShAmt = C.getZExtValue();
22736 // Don't try to convert this shift into a ISD::SRA if the shift
22737 // count is bigger than or equal to the element size.
22738 if (ShAmt >= SVTBits)
22739 return SDValue();
22741 // Trivial case: if the shift count is zero, then fold this
22742 // into the first operand.
22743 if (ShAmt == 0)
22744 return Op0;
22746 // Replace this packed shift intrinsic with a target independent
22747 // shift dag node.
22748 SDValue Splat = DAG.getConstant(C, VT);
22749 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
22750 }
22751 }
22752 }
22754 /// PerformMulCombine - Optimize a single multiply with constant into two
22755 /// in order to implement it with two cheaper instructions, e.g.
22756 /// LEA + SHL, LEA + LEA.
22757 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
22758 TargetLowering::DAGCombinerInfo &DCI) {
22759 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
22760 return SDValue();
22762 EVT VT = N->getValueType(0);
22763 if (VT != MVT::i64)
22764 return SDValue();
22766 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
22767 if (!C)
22768 return SDValue();
22769 uint64_t MulAmt = C->getZExtValue();
22770 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
22771 return SDValue();
22773 uint64_t MulAmt1 = 0;
22774 uint64_t MulAmt2 = 0;
22775 if ((MulAmt % 9) == 0) {
22776 MulAmt1 = 9;
22777 MulAmt2 = MulAmt / 9;
22778 } else if ((MulAmt % 5) == 0) {
22779 MulAmt1 = 5;
22780 MulAmt2 = MulAmt / 5;
22781 } else if ((MulAmt % 3) == 0) {
22782 MulAmt1 = 3;
22783 MulAmt2 = MulAmt / 3;
22784 }
22785 if (MulAmt2 &&
22786 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
22787 SDLoc DL(N);
22789 if (isPowerOf2_64(MulAmt2) &&
22790 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
22791 // If second multiplifer is pow2, issue it first. We want the multiply by
22792 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
22793 // is an add.
22794 std::swap(MulAmt1, MulAmt2);
22796 SDValue NewMul;
22797 if (isPowerOf2_64(MulAmt1))
22798 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
22799 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
22800 else
22801 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
22802 DAG.getConstant(MulAmt1, VT));
22804 if (isPowerOf2_64(MulAmt2))
22805 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
22806 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
22807 else
22808 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
22809 DAG.getConstant(MulAmt2, VT));
22811 // Do not add new nodes to DAG combiner worklist.
22812 DCI.CombineTo(N, NewMul, false);
22813 }
22814 return SDValue();
22815 }
22817 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
22818 SDValue N0 = N->getOperand(0);
22819 SDValue N1 = N->getOperand(1);
22820 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
22821 EVT VT = N0.getValueType();
22823 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
22824 // since the result of setcc_c is all zero's or all ones.
22825 if (VT.isInteger() && !VT.isVector() &&
22826 N1C && N0.getOpcode() == ISD::AND &&
22827 N0.getOperand(1).getOpcode() == ISD::Constant) {
22828 SDValue N00 = N0.getOperand(0);
22829 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
22830 ((N00.getOpcode() == ISD::ANY_EXTEND ||
22831 N00.getOpcode() == ISD::ZERO_EXTEND) &&
22832 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
22833 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
22834 APInt ShAmt = N1C->getAPIntValue();
22835 Mask = Mask.shl(ShAmt);
22836 if (Mask != 0)
22837 return DAG.getNode(ISD::AND, SDLoc(N), VT,
22838 N00, DAG.getConstant(Mask, VT));
22839 }
22840 }
22842 // Hardware support for vector shifts is sparse which makes us scalarize the
22843 // vector operations in many cases. Also, on sandybridge ADD is faster than
22844 // shl.
22845 // (shl V, 1) -> add V,V
22846 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
22847 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
22848 assert(N0.getValueType().isVector() && "Invalid vector shift type");
22849 // We shift all of the values by one. In many cases we do not have
22850 // hardware support for this operation. This is better expressed as an ADD
22851 // of two values.
22852 if (N1SplatC->getZExtValue() == 1)
22853 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
22854 }
22856 return SDValue();
22857 }
22859 /// \brief Returns a vector of 0s if the node in input is a vector logical
22860 /// shift by a constant amount which is known to be bigger than or equal
22861 /// to the vector element size in bits.
22862 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
22863 const X86Subtarget *Subtarget) {
22864 EVT VT = N->getValueType(0);
22866 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
22867 (!Subtarget->hasInt256() ||
22868 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
22869 return SDValue();
22871 SDValue Amt = N->getOperand(1);
22872 SDLoc DL(N);
22873 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
22874 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
22875 APInt ShiftAmt = AmtSplat->getAPIntValue();
22876 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
22878 // SSE2/AVX2 logical shifts always return a vector of 0s
22879 // if the shift amount is bigger than or equal to
22880 // the element size. The constant shift amount will be
22881 // encoded as a 8-bit immediate.
22882 if (ShiftAmt.trunc(8).uge(MaxAmount))
22883 return getZeroVector(VT, Subtarget, DAG, DL);
22884 }
22886 return SDValue();
22887 }
22889 /// PerformShiftCombine - Combine shifts.
22890 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
22891 TargetLowering::DAGCombinerInfo &DCI,
22892 const X86Subtarget *Subtarget) {
22893 if (N->getOpcode() == ISD::SHL) {
22894 SDValue V = PerformSHLCombine(N, DAG);
22895 if (V.getNode()) return V;
22896 }
22898 if (N->getOpcode() != ISD::SRA) {
22899 // Try to fold this logical shift into a zero vector.
22900 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
22901 if (V.getNode()) return V;
22902 }
22904 return SDValue();
22905 }
22907 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
22908 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
22909 // and friends. Likewise for OR -> CMPNEQSS.
22910 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
22911 TargetLowering::DAGCombinerInfo &DCI,
22912 const X86Subtarget *Subtarget) {
22913 unsigned opcode;
22915 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
22916 // we're requiring SSE2 for both.
22917 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
22918 SDValue N0 = N->getOperand(0);
22919 SDValue N1 = N->getOperand(1);
22920 SDValue CMP0 = N0->getOperand(1);
22921 SDValue CMP1 = N1->getOperand(1);
22922 SDLoc DL(N);
22924 // The SETCCs should both refer to the same CMP.
22925 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
22926 return SDValue();
22928 SDValue CMP00 = CMP0->getOperand(0);
22929 SDValue CMP01 = CMP0->getOperand(1);
22930 EVT VT = CMP00.getValueType();
22932 if (VT == MVT::f32 || VT == MVT::f64) {
22933 bool ExpectingFlags = false;
22934 // Check for any users that want flags:
22935 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
22936 !ExpectingFlags && UI != UE; ++UI)
22937 switch (UI->getOpcode()) {
22938 default:
22939 case ISD::BR_CC:
22940 case ISD::BRCOND:
22941 case ISD::SELECT:
22942 ExpectingFlags = true;
22943 break;
22944 case ISD::CopyToReg:
22945 case ISD::SIGN_EXTEND:
22946 case ISD::ZERO_EXTEND:
22947 case ISD::ANY_EXTEND:
22948 break;
22949 }
22951 if (!ExpectingFlags) {
22952 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
22953 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
22955 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
22956 X86::CondCode tmp = cc0;
22957 cc0 = cc1;
22958 cc1 = tmp;
22959 }
22961 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
22962 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
22963 // FIXME: need symbolic constants for these magic numbers.
22964 // See X86ATTInstPrinter.cpp:printSSECC().
22965 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
22966 if (Subtarget->hasAVX512()) {
22967 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
22968 CMP01, DAG.getConstant(x86cc, MVT::i8));
22969 if (N->getValueType(0) != MVT::i1)
22970 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
22971 FSetCC);
22972 return FSetCC;
22973 }
22974 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
22975 CMP00.getValueType(), CMP00, CMP01,
22976 DAG.getConstant(x86cc, MVT::i8));
22978 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
22979 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
22981 if (is64BitFP && !Subtarget->is64Bit()) {
22982 // On a 32-bit target, we cannot bitcast the 64-bit float to a
22983 // 64-bit integer, since that's not a legal type. Since
22984 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
22985 // bits, but can do this little dance to extract the lowest 32 bits
22986 // and work with those going forward.
22987 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
22988 OnesOrZeroesF);
22989 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
22990 Vector64);
22991 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
22992 Vector32, DAG.getIntPtrConstant(0));
22993 IntVT = MVT::i32;
22994 }
22996 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
22997 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
22998 DAG.getConstant(1, IntVT));
22999 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
23000 return OneBitOfTruth;
23001 }
23002 }
23003 }
23004 }
23005 return SDValue();
23006 }
23008 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
23009 /// so it can be folded inside ANDNP.
23010 static bool CanFoldXORWithAllOnes(const SDNode *N) {
23011 EVT VT = N->getValueType(0);
23013 // Match direct AllOnes for 128 and 256-bit vectors
23014 if (ISD::isBuildVectorAllOnes(N))
23015 return true;
23017 // Look through a bit convert.
23018 if (N->getOpcode() == ISD::BITCAST)
23019 N = N->getOperand(0).getNode();
23021 // Sometimes the operand may come from a insert_subvector building a 256-bit
23022 // allones vector
23023 if (VT.is256BitVector() &&
23024 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
23025 SDValue V1 = N->getOperand(0);
23026 SDValue V2 = N->getOperand(1);
23028 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
23029 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
23030 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
23031 ISD::isBuildVectorAllOnes(V2.getNode()))
23032 return true;
23033 }
23035 return false;
23036 }
23038 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
23039 // register. In most cases we actually compare or select YMM-sized registers
23040 // and mixing the two types creates horrible code. This method optimizes
23041 // some of the transition sequences.
23042 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
23043 TargetLowering::DAGCombinerInfo &DCI,
23044 const X86Subtarget *Subtarget) {
23045 EVT VT = N->getValueType(0);
23046 if (!VT.is256BitVector())
23047 return SDValue();
23049 assert((N->getOpcode() == ISD::ANY_EXTEND ||
23050 N->getOpcode() == ISD::ZERO_EXTEND ||
23051 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
23053 SDValue Narrow = N->getOperand(0);
23054 EVT NarrowVT = Narrow->getValueType(0);
23055 if (!NarrowVT.is128BitVector())
23056 return SDValue();
23058 if (Narrow->getOpcode() != ISD::XOR &&
23059 Narrow->getOpcode() != ISD::AND &&
23060 Narrow->getOpcode() != ISD::OR)
23061 return SDValue();
23063 SDValue N0 = Narrow->getOperand(0);
23064 SDValue N1 = Narrow->getOperand(1);
23065 SDLoc DL(Narrow);
23067 // The Left side has to be a trunc.
23068 if (N0.getOpcode() != ISD::TRUNCATE)
23069 return SDValue();
23071 // The type of the truncated inputs.
23072 EVT WideVT = N0->getOperand(0)->getValueType(0);
23073 if (WideVT != VT)
23074 return SDValue();
23076 // The right side has to be a 'trunc' or a constant vector.
23077 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
23078 ConstantSDNode *RHSConstSplat = nullptr;
23079 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
23080 RHSConstSplat = RHSBV->getConstantSplatNode();
23081 if (!RHSTrunc && !RHSConstSplat)
23082 return SDValue();
23084 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23086 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
23087 return SDValue();
23089 // Set N0 and N1 to hold the inputs to the new wide operation.
23090 N0 = N0->getOperand(0);
23091 if (RHSConstSplat) {
23092 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
23093 SDValue(RHSConstSplat, 0));
23094 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
23095 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
23096 } else if (RHSTrunc) {
23097 N1 = N1->getOperand(0);
23098 }
23100 // Generate the wide operation.
23101 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
23102 unsigned Opcode = N->getOpcode();
23103 switch (Opcode) {
23104 case ISD::ANY_EXTEND:
23105 return Op;
23106 case ISD::ZERO_EXTEND: {
23107 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
23108 APInt Mask = APInt::getAllOnesValue(InBits);
23109 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
23110 return DAG.getNode(ISD::AND, DL, VT,
23111 Op, DAG.getConstant(Mask, VT));
23112 }
23113 case ISD::SIGN_EXTEND:
23114 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
23115 Op, DAG.getValueType(NarrowVT));
23116 default:
23117 llvm_unreachable("Unexpected opcode");
23118 }
23119 }
23121 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
23122 TargetLowering::DAGCombinerInfo &DCI,
23123 const X86Subtarget *Subtarget) {
23124 EVT VT = N->getValueType(0);
23125 if (DCI.isBeforeLegalizeOps())
23126 return SDValue();
23128 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
23129 if (R.getNode())
23130 return R;
23132 // Create BEXTR instructions
23133 // BEXTR is ((X >> imm) & (2**size-1))
23134 if (VT == MVT::i32 || VT == MVT::i64) {
23135 SDValue N0 = N->getOperand(0);
23136 SDValue N1 = N->getOperand(1);
23137 SDLoc DL(N);
23139 // Check for BEXTR.
23140 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
23141 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
23142 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
23143 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23144 if (MaskNode && ShiftNode) {
23145 uint64_t Mask = MaskNode->getZExtValue();
23146 uint64_t Shift = ShiftNode->getZExtValue();
23147 if (isMask_64(Mask)) {
23148 uint64_t MaskSize = CountPopulation_64(Mask);
23149 if (Shift + MaskSize <= VT.getSizeInBits())
23150 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
23151 DAG.getConstant(Shift | (MaskSize << 8), VT));
23152 }
23153 }
23154 } // BEXTR
23156 return SDValue();
23157 }
23159 // Want to form ANDNP nodes:
23160 // 1) In the hopes of then easily combining them with OR and AND nodes
23161 // to form PBLEND/PSIGN.
23162 // 2) To match ANDN packed intrinsics
23163 if (VT != MVT::v2i64 && VT != MVT::v4i64)
23164 return SDValue();
23166 SDValue N0 = N->getOperand(0);
23167 SDValue N1 = N->getOperand(1);
23168 SDLoc DL(N);
23170 // Check LHS for vnot
23171 if (N0.getOpcode() == ISD::XOR &&
23172 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
23173 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
23174 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
23176 // Check RHS for vnot
23177 if (N1.getOpcode() == ISD::XOR &&
23178 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
23179 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
23180 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
23182 return SDValue();
23183 }
23185 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
23186 TargetLowering::DAGCombinerInfo &DCI,
23187 const X86Subtarget *Subtarget) {
23188 if (DCI.isBeforeLegalizeOps())
23189 return SDValue();
23191 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
23192 if (R.getNode())
23193 return R;
23195 SDValue N0 = N->getOperand(0);
23196 SDValue N1 = N->getOperand(1);
23197 EVT VT = N->getValueType(0);
23199 // look for psign/blend
23200 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
23201 if (!Subtarget->hasSSSE3() ||
23202 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
23203 return SDValue();
23205 // Canonicalize pandn to RHS
23206 if (N0.getOpcode() == X86ISD::ANDNP)
23207 std::swap(N0, N1);
23208 // or (and (m, y), (pandn m, x))
23209 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
23210 SDValue Mask = N1.getOperand(0);
23211 SDValue X = N1.getOperand(1);
23212 SDValue Y;
23213 if (N0.getOperand(0) == Mask)
23214 Y = N0.getOperand(1);
23215 if (N0.getOperand(1) == Mask)
23216 Y = N0.getOperand(0);
23218 // Check to see if the mask appeared in both the AND and ANDNP and
23219 if (!Y.getNode())
23220 return SDValue();
23222 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
23223 // Look through mask bitcast.
23224 if (Mask.getOpcode() == ISD::BITCAST)
23225 Mask = Mask.getOperand(0);
23226 if (X.getOpcode() == ISD::BITCAST)
23227 X = X.getOperand(0);
23228 if (Y.getOpcode() == ISD::BITCAST)
23229 Y = Y.getOperand(0);
23231 EVT MaskVT = Mask.getValueType();
23233 // Validate that the Mask operand is a vector sra node.
23234 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
23235 // there is no psrai.b
23236 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
23237 unsigned SraAmt = ~0;
23238 if (Mask.getOpcode() == ISD::SRA) {
23239 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
23240 if (auto *AmtConst = AmtBV->getConstantSplatNode())
23241 SraAmt = AmtConst->getZExtValue();
23242 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
23243 SDValue SraC = Mask.getOperand(1);
23244 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
23245 }
23246 if ((SraAmt + 1) != EltBits)
23247 return SDValue();
23249 SDLoc DL(N);
23251 // Now we know we at least have a plendvb with the mask val. See if
23252 // we can form a psignb/w/d.
23253 // psign = x.type == y.type == mask.type && y = sub(0, x);
23254 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
23255 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
23256 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
23257 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
23258 "Unsupported VT for PSIGN");
23259 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
23260 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
23261 }
23262 // PBLENDVB only available on SSE 4.1
23263 if (!Subtarget->hasSSE41())
23264 return SDValue();
23266 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
23268 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
23269 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
23270 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
23271 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
23272 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
23273 }
23274 }
23276 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
23277 return SDValue();
23279 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
23280 MachineFunction &MF = DAG.getMachineFunction();
23281 bool OptForSize = MF.getFunction()->getAttributes().
23282 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
23284 // SHLD/SHRD instructions have lower register pressure, but on some
23285 // platforms they have higher latency than the equivalent
23286 // series of shifts/or that would otherwise be generated.
23287 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
23288 // have higher latencies and we are not optimizing for size.
23289 if (!OptForSize && Subtarget->isSHLDSlow())
23290 return SDValue();
23292 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
23293 std::swap(N0, N1);
23294 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
23295 return SDValue();
23296 if (!N0.hasOneUse() || !N1.hasOneUse())
23297 return SDValue();
23299 SDValue ShAmt0 = N0.getOperand(1);
23300 if (ShAmt0.getValueType() != MVT::i8)
23301 return SDValue();
23302 SDValue ShAmt1 = N1.getOperand(1);
23303 if (ShAmt1.getValueType() != MVT::i8)
23304 return SDValue();
23305 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
23306 ShAmt0 = ShAmt0.getOperand(0);
23307 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
23308 ShAmt1 = ShAmt1.getOperand(0);
23310 SDLoc DL(N);
23311 unsigned Opc = X86ISD::SHLD;
23312 SDValue Op0 = N0.getOperand(0);
23313 SDValue Op1 = N1.getOperand(0);
23314 if (ShAmt0.getOpcode() == ISD::SUB) {
23315 Opc = X86ISD::SHRD;
23316 std::swap(Op0, Op1);
23317 std::swap(ShAmt0, ShAmt1);
23318 }
23320 unsigned Bits = VT.getSizeInBits();
23321 if (ShAmt1.getOpcode() == ISD::SUB) {
23322 SDValue Sum = ShAmt1.getOperand(0);
23323 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
23324 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
23325 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
23326 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
23327 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
23328 return DAG.getNode(Opc, DL, VT,
23329 Op0, Op1,
23330 DAG.getNode(ISD::TRUNCATE, DL,
23331 MVT::i8, ShAmt0));
23332 }
23333 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
23334 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
23335 if (ShAmt0C &&
23336 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
23337 return DAG.getNode(Opc, DL, VT,
23338 N0.getOperand(0), N1.getOperand(0),
23339 DAG.getNode(ISD::TRUNCATE, DL,
23340 MVT::i8, ShAmt0));
23341 }
23343 return SDValue();
23344 }
23346 // Generate NEG and CMOV for integer abs.
23347 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
23348 EVT VT = N->getValueType(0);
23350 // Since X86 does not have CMOV for 8-bit integer, we don't convert
23351 // 8-bit integer abs to NEG and CMOV.
23352 if (VT.isInteger() && VT.getSizeInBits() == 8)
23353 return SDValue();
23355 SDValue N0 = N->getOperand(0);
23356 SDValue N1 = N->getOperand(1);
23357 SDLoc DL(N);
23359 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
23360 // and change it to SUB and CMOV.
23361 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
23362 N0.getOpcode() == ISD::ADD &&
23363 N0.getOperand(1) == N1 &&
23364 N1.getOpcode() == ISD::SRA &&
23365 N1.getOperand(0) == N0.getOperand(0))
23366 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
23367 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
23368 // Generate SUB & CMOV.
23369 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
23370 DAG.getConstant(0, VT), N0.getOperand(0));
23372 SDValue Ops[] = { N0.getOperand(0), Neg,
23373 DAG.getConstant(X86::COND_GE, MVT::i8),
23374 SDValue(Neg.getNode(), 1) };
23375 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
23376 }
23377 return SDValue();
23378 }
23380 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
23381 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
23382 TargetLowering::DAGCombinerInfo &DCI,
23383 const X86Subtarget *Subtarget) {
23384 if (DCI.isBeforeLegalizeOps())
23385 return SDValue();
23387 if (Subtarget->hasCMov()) {
23388 SDValue RV = performIntegerAbsCombine(N, DAG);
23389 if (RV.getNode())
23390 return RV;
23391 }
23393 return SDValue();
23394 }
23396 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
23397 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
23398 TargetLowering::DAGCombinerInfo &DCI,
23399 const X86Subtarget *Subtarget) {
23400 LoadSDNode *Ld = cast<LoadSDNode>(N);
23401 EVT RegVT = Ld->getValueType(0);
23402 EVT MemVT = Ld->getMemoryVT();
23403 SDLoc dl(Ld);
23404 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23406 // On Sandybridge unaligned 256bit loads are inefficient.
23407 ISD::LoadExtType Ext = Ld->getExtensionType();
23408 unsigned Alignment = Ld->getAlignment();
23409 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
23410 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
23411 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
23412 unsigned NumElems = RegVT.getVectorNumElements();
23413 if (NumElems < 2)
23414 return SDValue();
23416 SDValue Ptr = Ld->getBasePtr();
23417 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
23419 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
23420 NumElems/2);
23421 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23422 Ld->getPointerInfo(), Ld->isVolatile(),
23423 Ld->isNonTemporal(), Ld->isInvariant(),
23424 Alignment);
23425 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23426 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23427 Ld->getPointerInfo(), Ld->isVolatile(),
23428 Ld->isNonTemporal(), Ld->isInvariant(),
23429 std::min(16U, Alignment));
23430 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
23431 Load1.getValue(1),
23432 Load2.getValue(1));
23434 SDValue NewVec = DAG.getUNDEF(RegVT);
23435 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
23436 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
23437 return DCI.CombineTo(N, NewVec, TF, true);
23438 }
23440 return SDValue();
23441 }
23443 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
23444 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
23445 const X86Subtarget *Subtarget) {
23446 StoreSDNode *St = cast<StoreSDNode>(N);
23447 EVT VT = St->getValue().getValueType();
23448 EVT StVT = St->getMemoryVT();
23449 SDLoc dl(St);
23450 SDValue StoredVal = St->getOperand(1);
23451 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23453 // If we are saving a concatenation of two XMM registers, perform two stores.
23454 // On Sandy Bridge, 256-bit memory operations are executed by two
23455 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
23456 // memory operation.
23457 unsigned Alignment = St->getAlignment();
23458 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
23459 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
23460 StVT == VT && !IsAligned) {
23461 unsigned NumElems = VT.getVectorNumElements();
23462 if (NumElems < 2)
23463 return SDValue();
23465 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
23466 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
23468 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
23469 SDValue Ptr0 = St->getBasePtr();
23470 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
23472 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
23473 St->getPointerInfo(), St->isVolatile(),
23474 St->isNonTemporal(), Alignment);
23475 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
23476 St->getPointerInfo(), St->isVolatile(),
23477 St->isNonTemporal(),
23478 std::min(16U, Alignment));
23479 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
23480 }
23482 // Optimize trunc store (of multiple scalars) to shuffle and store.
23483 // First, pack all of the elements in one place. Next, store to memory
23484 // in fewer chunks.
23485 if (St->isTruncatingStore() && VT.isVector()) {
23486 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23487 unsigned NumElems = VT.getVectorNumElements();
23488 assert(StVT != VT && "Cannot truncate to the same type");
23489 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
23490 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
23492 // From, To sizes and ElemCount must be pow of two
23493 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
23494 // We are going to use the original vector elt for storing.
23495 // Accumulated smaller vector elements must be a multiple of the store size.
23496 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
23498 unsigned SizeRatio = FromSz / ToSz;
23500 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
23502 // Create a type on which we perform the shuffle
23503 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23504 StVT.getScalarType(), NumElems*SizeRatio);
23506 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23508 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
23509 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
23510 for (unsigned i = 0; i != NumElems; ++i)
23511 ShuffleVec[i] = i * SizeRatio;
23513 // Can't shuffle using an illegal type.
23514 if (!TLI.isTypeLegal(WideVecVT))
23515 return SDValue();
23517 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
23518 DAG.getUNDEF(WideVecVT),
23519 &ShuffleVec[0]);
23520 // At this point all of the data is stored at the bottom of the
23521 // register. We now need to save it to mem.
23523 // Find the largest store unit
23524 MVT StoreType = MVT::i8;
23525 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
23526 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
23527 MVT Tp = (MVT::SimpleValueType)tp;
23528 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
23529 StoreType = Tp;
23530 }
23532 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
23533 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
23534 (64 <= NumElems * ToSz))
23535 StoreType = MVT::f64;
23537 // Bitcast the original vector into a vector of store-size units
23538 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
23539 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
23540 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
23541 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
23542 SmallVector<SDValue, 8> Chains;
23543 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
23544 TLI.getPointerTy());
23545 SDValue Ptr = St->getBasePtr();
23547 // Perform one or more big stores into memory.
23548 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
23549 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
23550 StoreType, ShuffWide,
23551 DAG.getIntPtrConstant(i));
23552 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
23553 St->getPointerInfo(), St->isVolatile(),
23554 St->isNonTemporal(), St->getAlignment());
23555 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23556 Chains.push_back(Ch);
23557 }
23559 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
23560 }
23562 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
23563 // the FP state in cases where an emms may be missing.
23564 // A preferable solution to the general problem is to figure out the right
23565 // places to insert EMMS. This qualifies as a quick hack.
23567 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
23568 if (VT.getSizeInBits() != 64)
23569 return SDValue();
23571 const Function *F = DAG.getMachineFunction().getFunction();
23572 bool NoImplicitFloatOps = F->getAttributes().
23573 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
23574 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
23575 && Subtarget->hasSSE2();
23576 if ((VT.isVector() ||
23577 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
23578 isa<LoadSDNode>(St->getValue()) &&
23579 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
23580 St->getChain().hasOneUse() && !St->isVolatile()) {
23581 SDNode* LdVal = St->getValue().getNode();
23582 LoadSDNode *Ld = nullptr;
23583 int TokenFactorIndex = -1;
23584 SmallVector<SDValue, 8> Ops;
23585 SDNode* ChainVal = St->getChain().getNode();
23586 // Must be a store of a load. We currently handle two cases: the load
23587 // is a direct child, and it's under an intervening TokenFactor. It is
23588 // possible to dig deeper under nested TokenFactors.
23589 if (ChainVal == LdVal)
23590 Ld = cast<LoadSDNode>(St->getChain());
23591 else if (St->getValue().hasOneUse() &&
23592 ChainVal->getOpcode() == ISD::TokenFactor) {
23593 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
23594 if (ChainVal->getOperand(i).getNode() == LdVal) {
23595 TokenFactorIndex = i;
23596 Ld = cast<LoadSDNode>(St->getValue());
23597 } else
23598 Ops.push_back(ChainVal->getOperand(i));
23599 }
23600 }
23602 if (!Ld || !ISD::isNormalLoad(Ld))
23603 return SDValue();
23605 // If this is not the MMX case, i.e. we are just turning i64 load/store
23606 // into f64 load/store, avoid the transformation if there are multiple
23607 // uses of the loaded value.
23608 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
23609 return SDValue();
23611 SDLoc LdDL(Ld);
23612 SDLoc StDL(N);
23613 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
23614 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
23615 // pair instead.
23616 if (Subtarget->is64Bit() || F64IsLegal) {
23617 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
23618 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
23619 Ld->getPointerInfo(), Ld->isVolatile(),
23620 Ld->isNonTemporal(), Ld->isInvariant(),
23621 Ld->getAlignment());
23622 SDValue NewChain = NewLd.getValue(1);
23623 if (TokenFactorIndex != -1) {
23624 Ops.push_back(NewChain);
23625 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23626 }
23627 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
23628 St->getPointerInfo(),
23629 St->isVolatile(), St->isNonTemporal(),
23630 St->getAlignment());
23631 }
23633 // Otherwise, lower to two pairs of 32-bit loads / stores.
23634 SDValue LoAddr = Ld->getBasePtr();
23635 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
23636 DAG.getConstant(4, MVT::i32));
23638 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
23639 Ld->getPointerInfo(),
23640 Ld->isVolatile(), Ld->isNonTemporal(),
23641 Ld->isInvariant(), Ld->getAlignment());
23642 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
23643 Ld->getPointerInfo().getWithOffset(4),
23644 Ld->isVolatile(), Ld->isNonTemporal(),
23645 Ld->isInvariant(),
23646 MinAlign(Ld->getAlignment(), 4));
23648 SDValue NewChain = LoLd.getValue(1);
23649 if (TokenFactorIndex != -1) {
23650 Ops.push_back(LoLd);
23651 Ops.push_back(HiLd);
23652 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23653 }
23655 LoAddr = St->getBasePtr();
23656 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
23657 DAG.getConstant(4, MVT::i32));
23659 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
23660 St->getPointerInfo(),
23661 St->isVolatile(), St->isNonTemporal(),
23662 St->getAlignment());
23663 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
23664 St->getPointerInfo().getWithOffset(4),
23665 St->isVolatile(),
23666 St->isNonTemporal(),
23667 MinAlign(St->getAlignment(), 4));
23668 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
23669 }
23670 return SDValue();
23671 }
23673 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
23674 /// and return the operands for the horizontal operation in LHS and RHS. A
23675 /// horizontal operation performs the binary operation on successive elements
23676 /// of its first operand, then on successive elements of its second operand,
23677 /// returning the resulting values in a vector. For example, if
23678 /// A = < float a0, float a1, float a2, float a3 >
23679 /// and
23680 /// B = < float b0, float b1, float b2, float b3 >
23681 /// then the result of doing a horizontal operation on A and B is
23682 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
23683 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
23684 /// A horizontal-op B, for some already available A and B, and if so then LHS is
23685 /// set to A, RHS to B, and the routine returns 'true'.
23686 /// Note that the binary operation should have the property that if one of the
23687 /// operands is UNDEF then the result is UNDEF.
23688 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
23689 // Look for the following pattern: if
23690 // A = < float a0, float a1, float a2, float a3 >
23691 // B = < float b0, float b1, float b2, float b3 >
23692 // and
23693 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
23694 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
23695 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
23696 // which is A horizontal-op B.
23698 // At least one of the operands should be a vector shuffle.
23699 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
23700 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
23701 return false;
23703 MVT VT = LHS.getSimpleValueType();
23705 assert((VT.is128BitVector() || VT.is256BitVector()) &&
23706 "Unsupported vector type for horizontal add/sub");
23708 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
23709 // operate independently on 128-bit lanes.
23710 unsigned NumElts = VT.getVectorNumElements();
23711 unsigned NumLanes = VT.getSizeInBits()/128;
23712 unsigned NumLaneElts = NumElts / NumLanes;
23713 assert((NumLaneElts % 2 == 0) &&
23714 "Vector type should have an even number of elements in each lane");
23715 unsigned HalfLaneElts = NumLaneElts/2;
23717 // View LHS in the form
23718 // LHS = VECTOR_SHUFFLE A, B, LMask
23719 // If LHS is not a shuffle then pretend it is the shuffle
23720 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
23721 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
23722 // type VT.
23723 SDValue A, B;
23724 SmallVector<int, 16> LMask(NumElts);
23725 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23726 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
23727 A = LHS.getOperand(0);
23728 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
23729 B = LHS.getOperand(1);
23730 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
23731 std::copy(Mask.begin(), Mask.end(), LMask.begin());
23732 } else {
23733 if (LHS.getOpcode() != ISD::UNDEF)
23734 A = LHS;
23735 for (unsigned i = 0; i != NumElts; ++i)
23736 LMask[i] = i;
23737 }
23739 // Likewise, view RHS in the form
23740 // RHS = VECTOR_SHUFFLE C, D, RMask
23741 SDValue C, D;
23742 SmallVector<int, 16> RMask(NumElts);
23743 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23744 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
23745 C = RHS.getOperand(0);
23746 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
23747 D = RHS.getOperand(1);
23748 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
23749 std::copy(Mask.begin(), Mask.end(), RMask.begin());
23750 } else {
23751 if (RHS.getOpcode() != ISD::UNDEF)
23752 C = RHS;
23753 for (unsigned i = 0; i != NumElts; ++i)
23754 RMask[i] = i;
23755 }
23757 // Check that the shuffles are both shuffling the same vectors.
23758 if (!(A == C && B == D) && !(A == D && B == C))
23759 return false;
23761 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
23762 if (!A.getNode() && !B.getNode())
23763 return false;
23765 // If A and B occur in reverse order in RHS, then "swap" them (which means
23766 // rewriting the mask).
23767 if (A != C)
23768 CommuteVectorShuffleMask(RMask, NumElts);
23770 // At this point LHS and RHS are equivalent to
23771 // LHS = VECTOR_SHUFFLE A, B, LMask
23772 // RHS = VECTOR_SHUFFLE A, B, RMask
23773 // Check that the masks correspond to performing a horizontal operation.
23774 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
23775 for (unsigned i = 0; i != NumLaneElts; ++i) {
23776 int LIdx = LMask[i+l], RIdx = RMask[i+l];
23778 // Ignore any UNDEF components.
23779 if (LIdx < 0 || RIdx < 0 ||
23780 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
23781 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
23782 continue;
23784 // Check that successive elements are being operated on. If not, this is
23785 // not a horizontal operation.
23786 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
23787 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
23788 if (!(LIdx == Index && RIdx == Index + 1) &&
23789 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
23790 return false;
23791 }
23792 }
23794 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
23795 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
23796 return true;
23797 }
23799 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
23800 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
23801 const X86Subtarget *Subtarget) {
23802 EVT VT = N->getValueType(0);
23803 SDValue LHS = N->getOperand(0);
23804 SDValue RHS = N->getOperand(1);
23806 // Try to synthesize horizontal adds from adds of shuffles.
23807 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23808 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23809 isHorizontalBinOp(LHS, RHS, true))
23810 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
23811 return SDValue();
23812 }
23814 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
23815 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
23816 const X86Subtarget *Subtarget) {
23817 EVT VT = N->getValueType(0);
23818 SDValue LHS = N->getOperand(0);
23819 SDValue RHS = N->getOperand(1);
23821 // Try to synthesize horizontal subs from subs of shuffles.
23822 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23823 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23824 isHorizontalBinOp(LHS, RHS, false))
23825 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
23826 return SDValue();
23827 }
23829 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
23830 /// X86ISD::FXOR nodes.
23831 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
23832 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
23833 // F[X]OR(0.0, x) -> x
23834 // F[X]OR(x, 0.0) -> x
23835 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23836 if (C->getValueAPF().isPosZero())
23837 return N->getOperand(1);
23838 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23839 if (C->getValueAPF().isPosZero())
23840 return N->getOperand(0);
23841 return SDValue();
23842 }
23844 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
23845 /// X86ISD::FMAX nodes.
23846 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
23847 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
23849 // Only perform optimizations if UnsafeMath is used.
23850 if (!DAG.getTarget().Options.UnsafeFPMath)
23851 return SDValue();
23853 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
23854 // into FMINC and FMAXC, which are Commutative operations.
23855 unsigned NewOp = 0;
23856 switch (N->getOpcode()) {
23857 default: llvm_unreachable("unknown opcode");
23858 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
23859 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
23860 }
23862 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
23863 N->getOperand(0), N->getOperand(1));
23864 }
23866 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
23867 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
23868 // FAND(0.0, x) -> 0.0
23869 // FAND(x, 0.0) -> 0.0
23870 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23871 if (C->getValueAPF().isPosZero())
23872 return N->getOperand(0);
23873 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23874 if (C->getValueAPF().isPosZero())
23875 return N->getOperand(1);
23876 return SDValue();
23877 }
23879 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
23880 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
23881 // FANDN(x, 0.0) -> 0.0
23882 // FANDN(0.0, x) -> x
23883 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23884 if (C->getValueAPF().isPosZero())
23885 return N->getOperand(1);
23886 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23887 if (C->getValueAPF().isPosZero())
23888 return N->getOperand(1);
23889 return SDValue();
23890 }
23892 static SDValue PerformBTCombine(SDNode *N,
23893 SelectionDAG &DAG,
23894 TargetLowering::DAGCombinerInfo &DCI) {
23895 // BT ignores high bits in the bit index operand.
23896 SDValue Op1 = N->getOperand(1);
23897 if (Op1.hasOneUse()) {
23898 unsigned BitWidth = Op1.getValueSizeInBits();
23899 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
23900 APInt KnownZero, KnownOne;
23901 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
23902 !DCI.isBeforeLegalizeOps());
23903 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23904 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
23905 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
23906 DCI.CommitTargetLoweringOpt(TLO);
23907 }
23908 return SDValue();
23909 }
23911 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
23912 SDValue Op = N->getOperand(0);
23913 if (Op.getOpcode() == ISD::BITCAST)
23914 Op = Op.getOperand(0);
23915 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
23916 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
23917 VT.getVectorElementType().getSizeInBits() ==
23918 OpVT.getVectorElementType().getSizeInBits()) {
23919 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
23920 }
23921 return SDValue();
23922 }
23924 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
23925 const X86Subtarget *Subtarget) {
23926 EVT VT = N->getValueType(0);
23927 if (!VT.isVector())
23928 return SDValue();
23930 SDValue N0 = N->getOperand(0);
23931 SDValue N1 = N->getOperand(1);
23932 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
23933 SDLoc dl(N);
23935 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
23936 // both SSE and AVX2 since there is no sign-extended shift right
23937 // operation on a vector with 64-bit elements.
23938 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
23939 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
23940 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
23941 N0.getOpcode() == ISD::SIGN_EXTEND)) {
23942 SDValue N00 = N0.getOperand(0);
23944 // EXTLOAD has a better solution on AVX2,
23945 // it may be replaced with X86ISD::VSEXT node.
23946 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
23947 if (!ISD::isNormalLoad(N00.getNode()))
23948 return SDValue();
23950 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
23951 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
23952 N00, N1);
23953 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
23954 }
23955 }
23956 return SDValue();
23957 }
23959 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
23960 TargetLowering::DAGCombinerInfo &DCI,
23961 const X86Subtarget *Subtarget) {
23962 if (!DCI.isBeforeLegalizeOps())
23963 return SDValue();
23965 if (!Subtarget->hasFp256())
23966 return SDValue();
23968 EVT VT = N->getValueType(0);
23969 if (VT.isVector() && VT.getSizeInBits() == 256) {
23970 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23971 if (R.getNode())
23972 return R;
23973 }
23975 return SDValue();
23976 }
23978 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
23979 const X86Subtarget* Subtarget) {
23980 SDLoc dl(N);
23981 EVT VT = N->getValueType(0);
23983 // Let legalize expand this if it isn't a legal type yet.
23984 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
23985 return SDValue();
23987 EVT ScalarVT = VT.getScalarType();
23988 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
23989 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
23990 return SDValue();
23992 SDValue A = N->getOperand(0);
23993 SDValue B = N->getOperand(1);
23994 SDValue C = N->getOperand(2);
23996 bool NegA = (A.getOpcode() == ISD::FNEG);
23997 bool NegB = (B.getOpcode() == ISD::FNEG);
23998 bool NegC = (C.getOpcode() == ISD::FNEG);
24000 // Negative multiplication when NegA xor NegB
24001 bool NegMul = (NegA != NegB);
24002 if (NegA)
24003 A = A.getOperand(0);
24004 if (NegB)
24005 B = B.getOperand(0);
24006 if (NegC)
24007 C = C.getOperand(0);
24009 unsigned Opcode;
24010 if (!NegMul)
24011 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
24012 else
24013 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
24015 return DAG.getNode(Opcode, dl, VT, A, B, C);
24016 }
24018 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
24019 TargetLowering::DAGCombinerInfo &DCI,
24020 const X86Subtarget *Subtarget) {
24021 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
24022 // (and (i32 x86isd::setcc_carry), 1)
24023 // This eliminates the zext. This transformation is necessary because
24024 // ISD::SETCC is always legalized to i8.
24025 SDLoc dl(N);
24026 SDValue N0 = N->getOperand(0);
24027 EVT VT = N->getValueType(0);
24029 if (N0.getOpcode() == ISD::AND &&
24030 N0.hasOneUse() &&
24031 N0.getOperand(0).hasOneUse()) {
24032 SDValue N00 = N0.getOperand(0);
24033 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24034 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24035 if (!C || C->getZExtValue() != 1)
24036 return SDValue();
24037 return DAG.getNode(ISD::AND, dl, VT,
24038 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24039 N00.getOperand(0), N00.getOperand(1)),
24040 DAG.getConstant(1, VT));
24041 }
24042 }
24044 if (N0.getOpcode() == ISD::TRUNCATE &&
24045 N0.hasOneUse() &&
24046 N0.getOperand(0).hasOneUse()) {
24047 SDValue N00 = N0.getOperand(0);
24048 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24049 return DAG.getNode(ISD::AND, dl, VT,
24050 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24051 N00.getOperand(0), N00.getOperand(1)),
24052 DAG.getConstant(1, VT));
24053 }
24054 }
24055 if (VT.is256BitVector()) {
24056 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24057 if (R.getNode())
24058 return R;
24059 }
24061 return SDValue();
24062 }
24064 // Optimize x == -y --> x+y == 0
24065 // x != -y --> x+y != 0
24066 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
24067 const X86Subtarget* Subtarget) {
24068 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
24069 SDValue LHS = N->getOperand(0);
24070 SDValue RHS = N->getOperand(1);
24071 EVT VT = N->getValueType(0);
24072 SDLoc DL(N);
24074 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
24075 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
24076 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
24077 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
24078 LHS.getValueType(), RHS, LHS.getOperand(1));
24079 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
24080 addV, DAG.getConstant(0, addV.getValueType()), CC);
24081 }
24082 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
24083 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
24084 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
24085 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
24086 RHS.getValueType(), LHS, RHS.getOperand(1));
24087 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
24088 addV, DAG.getConstant(0, addV.getValueType()), CC);
24089 }
24091 if (VT.getScalarType() == MVT::i1) {
24092 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
24093 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24094 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
24095 if (!IsSEXT0 && !IsVZero0)
24096 return SDValue();
24097 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
24098 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24099 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
24101 if (!IsSEXT1 && !IsVZero1)
24102 return SDValue();
24104 if (IsSEXT0 && IsVZero1) {
24105 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
24106 if (CC == ISD::SETEQ)
24107 return DAG.getNOT(DL, LHS.getOperand(0), VT);
24108 return LHS.getOperand(0);
24109 }
24110 if (IsSEXT1 && IsVZero0) {
24111 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
24112 if (CC == ISD::SETEQ)
24113 return DAG.getNOT(DL, RHS.getOperand(0), VT);
24114 return RHS.getOperand(0);
24115 }
24116 }
24118 return SDValue();
24119 }
24121 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
24122 const X86Subtarget *Subtarget) {
24123 SDLoc dl(N);
24124 MVT VT = N->getOperand(1)->getSimpleValueType(0);
24125 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
24126 "X86insertps is only defined for v4x32");
24128 SDValue Ld = N->getOperand(1);
24129 if (MayFoldLoad(Ld)) {
24130 // Extract the countS bits from the immediate so we can get the proper
24131 // address when narrowing the vector load to a specific element.
24132 // When the second source op is a memory address, interps doesn't use
24133 // countS and just gets an f32 from that address.
24134 unsigned DestIndex =
24135 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
24136 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
24137 } else
24138 return SDValue();
24140 // Create this as a scalar to vector to match the instruction pattern.
24141 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
24142 // countS bits are ignored when loading from memory on insertps, which
24143 // means we don't need to explicitly set them to 0.
24144 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
24145 LoadScalarToVector, N->getOperand(2));
24146 }
24148 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
24149 // as "sbb reg,reg", since it can be extended without zext and produces
24150 // an all-ones bit which is more useful than 0/1 in some cases.
24151 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
24152 MVT VT) {
24153 if (VT == MVT::i8)
24154 return DAG.getNode(ISD::AND, DL, VT,
24155 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24156 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
24157 DAG.getConstant(1, VT));
24158 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
24159 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
24160 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24161 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
24162 }
24164 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
24165 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
24166 TargetLowering::DAGCombinerInfo &DCI,
24167 const X86Subtarget *Subtarget) {
24168 SDLoc DL(N);
24169 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
24170 SDValue EFLAGS = N->getOperand(1);
24172 if (CC == X86::COND_A) {
24173 // Try to convert COND_A into COND_B in an attempt to facilitate
24174 // materializing "setb reg".
24175 //
24176 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
24177 // cannot take an immediate as its first operand.
24178 //
24179 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
24180 EFLAGS.getValueType().isInteger() &&
24181 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
24182 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
24183 EFLAGS.getNode()->getVTList(),
24184 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
24185 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
24186 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
24187 }
24188 }
24190 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
24191 // a zext and produces an all-ones bit which is more useful than 0/1 in some
24192 // cases.
24193 if (CC == X86::COND_B)
24194 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
24196 SDValue Flags;
24198 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
24199 if (Flags.getNode()) {
24200 SDValue Cond = DAG.getConstant(CC, MVT::i8);
24201 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
24202 }
24204 return SDValue();
24205 }
24207 // Optimize branch condition evaluation.
24208 //
24209 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
24210 TargetLowering::DAGCombinerInfo &DCI,
24211 const X86Subtarget *Subtarget) {
24212 SDLoc DL(N);
24213 SDValue Chain = N->getOperand(0);
24214 SDValue Dest = N->getOperand(1);
24215 SDValue EFLAGS = N->getOperand(3);
24216 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
24218 SDValue Flags;
24220 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
24221 if (Flags.getNode()) {
24222 SDValue Cond = DAG.getConstant(CC, MVT::i8);
24223 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
24224 Flags);
24225 }
24227 return SDValue();
24228 }
24230 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
24231 SelectionDAG &DAG) {
24232 // Take advantage of vector comparisons producing 0 or -1 in each lane to
24233 // optimize away operation when it's from a constant.
24234 //
24235 // The general transformation is:
24236 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
24237 // AND(VECTOR_CMP(x,y), constant2)
24238 // constant2 = UNARYOP(constant)
24240 // Early exit if this isn't a vector operation, the operand of the
24241 // unary operation isn't a bitwise AND, or if the sizes of the operations
24242 // aren't the same.
24243 EVT VT = N->getValueType(0);
24244 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
24245 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
24246 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
24247 return SDValue();
24249 // Now check that the other operand of the AND is a constant. We could
24250 // make the transformation for non-constant splats as well, but it's unclear
24251 // that would be a benefit as it would not eliminate any operations, just
24252 // perform one more step in scalar code before moving to the vector unit.
24253 if (BuildVectorSDNode *BV =
24254 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
24255 // Bail out if the vector isn't a constant.
24256 if (!BV->isConstant())
24257 return SDValue();
24259 // Everything checks out. Build up the new and improved node.
24260 SDLoc DL(N);
24261 EVT IntVT = BV->getValueType(0);
24262 // Create a new constant of the appropriate type for the transformed
24263 // DAG.
24264 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
24265 // The AND node needs bitcasts to/from an integer vector type around it.
24266 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
24267 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
24268 N->getOperand(0)->getOperand(0), MaskConst);
24269 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
24270 return Res;
24271 }
24273 return SDValue();
24274 }
24276 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
24277 const X86TargetLowering *XTLI) {
24278 // First try to optimize away the conversion entirely when it's
24279 // conditionally from a constant. Vectors only.
24280 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
24281 if (Res != SDValue())
24282 return Res;
24284 // Now move on to more general possibilities.
24285 SDValue Op0 = N->getOperand(0);
24286 EVT InVT = Op0->getValueType(0);
24288 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
24289 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
24290 SDLoc dl(N);
24291 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
24292 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
24293 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
24294 }
24296 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
24297 // a 32-bit target where SSE doesn't support i64->FP operations.
24298 if (Op0.getOpcode() == ISD::LOAD) {
24299 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
24300 EVT VT = Ld->getValueType(0);
24301 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
24302 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
24303 !XTLI->getSubtarget()->is64Bit() &&
24304 VT == MVT::i64) {
24305 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
24306 Ld->getChain(), Op0, DAG);
24307 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
24308 return FILDChain;
24309 }
24310 }
24311 return SDValue();
24312 }
24314 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
24315 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
24316 X86TargetLowering::DAGCombinerInfo &DCI) {
24317 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
24318 // the result is either zero or one (depending on the input carry bit).
24319 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
24320 if (X86::isZeroNode(N->getOperand(0)) &&
24321 X86::isZeroNode(N->getOperand(1)) &&
24322 // We don't have a good way to replace an EFLAGS use, so only do this when
24323 // dead right now.
24324 SDValue(N, 1).use_empty()) {
24325 SDLoc DL(N);
24326 EVT VT = N->getValueType(0);
24327 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
24328 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
24329 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
24330 DAG.getConstant(X86::COND_B,MVT::i8),
24331 N->getOperand(2)),
24332 DAG.getConstant(1, VT));
24333 return DCI.CombineTo(N, Res1, CarryOut);
24334 }
24336 return SDValue();
24337 }
24339 // fold (add Y, (sete X, 0)) -> adc 0, Y
24340 // (add Y, (setne X, 0)) -> sbb -1, Y
24341 // (sub (sete X, 0), Y) -> sbb 0, Y
24342 // (sub (setne X, 0), Y) -> adc -1, Y
24343 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
24344 SDLoc DL(N);
24346 // Look through ZExts.
24347 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
24348 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
24349 return SDValue();
24351 SDValue SetCC = Ext.getOperand(0);
24352 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
24353 return SDValue();
24355 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
24356 if (CC != X86::COND_E && CC != X86::COND_NE)
24357 return SDValue();
24359 SDValue Cmp = SetCC.getOperand(1);
24360 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
24361 !X86::isZeroNode(Cmp.getOperand(1)) ||
24362 !Cmp.getOperand(0).getValueType().isInteger())
24363 return SDValue();
24365 SDValue CmpOp0 = Cmp.getOperand(0);
24366 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
24367 DAG.getConstant(1, CmpOp0.getValueType()));
24369 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
24370 if (CC == X86::COND_NE)
24371 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
24372 DL, OtherVal.getValueType(), OtherVal,
24373 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
24374 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
24375 DL, OtherVal.getValueType(), OtherVal,
24376 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
24377 }
24379 /// PerformADDCombine - Do target-specific dag combines on integer adds.
24380 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
24381 const X86Subtarget *Subtarget) {
24382 EVT VT = N->getValueType(0);
24383 SDValue Op0 = N->getOperand(0);
24384 SDValue Op1 = N->getOperand(1);
24386 // Try to synthesize horizontal adds from adds of shuffles.
24387 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24388 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24389 isHorizontalBinOp(Op0, Op1, true))
24390 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
24392 return OptimizeConditionalInDecrement(N, DAG);
24393 }
24395 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
24396 const X86Subtarget *Subtarget) {
24397 SDValue Op0 = N->getOperand(0);
24398 SDValue Op1 = N->getOperand(1);
24400 // X86 can't encode an immediate LHS of a sub. See if we can push the
24401 // negation into a preceding instruction.
24402 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
24403 // If the RHS of the sub is a XOR with one use and a constant, invert the
24404 // immediate. Then add one to the LHS of the sub so we can turn
24405 // X-Y -> X+~Y+1, saving one register.
24406 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
24407 isa<ConstantSDNode>(Op1.getOperand(1))) {
24408 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
24409 EVT VT = Op0.getValueType();
24410 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
24411 Op1.getOperand(0),
24412 DAG.getConstant(~XorC, VT));
24413 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
24414 DAG.getConstant(C->getAPIntValue()+1, VT));
24415 }
24416 }
24418 // Try to synthesize horizontal adds from adds of shuffles.
24419 EVT VT = N->getValueType(0);
24420 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24421 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24422 isHorizontalBinOp(Op0, Op1, true))
24423 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
24425 return OptimizeConditionalInDecrement(N, DAG);
24426 }
24428 /// performVZEXTCombine - Performs build vector combines
24429 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
24430 TargetLowering::DAGCombinerInfo &DCI,
24431 const X86Subtarget *Subtarget) {
24432 // (vzext (bitcast (vzext (x)) -> (vzext x)
24433 SDValue In = N->getOperand(0);
24434 while (In.getOpcode() == ISD::BITCAST)
24435 In = In.getOperand(0);
24437 if (In.getOpcode() != X86ISD::VZEXT)
24438 return SDValue();
24440 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
24441 In.getOperand(0));
24442 }
24444 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
24445 DAGCombinerInfo &DCI) const {
24446 SelectionDAG &DAG = DCI.DAG;
24447 switch (N->getOpcode()) {
24448 default: break;
24449 case ISD::EXTRACT_VECTOR_ELT:
24450 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
24451 case ISD::VSELECT:
24452 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
24453 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
24454 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
24455 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
24456 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
24457 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
24458 case ISD::SHL:
24459 case ISD::SRA:
24460 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
24461 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
24462 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
24463 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
24464 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
24465 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
24466 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
24467 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
24468 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
24469 case X86ISD::FXOR:
24470 case X86ISD::FOR: return PerformFORCombine(N, DAG);
24471 case X86ISD::FMIN:
24472 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
24473 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
24474 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
24475 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
24476 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
24477 case ISD::ANY_EXTEND:
24478 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
24479 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
24480 case ISD::SIGN_EXTEND_INREG:
24481 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
24482 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
24483 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
24484 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
24485 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
24486 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
24487 case X86ISD::SHUFP: // Handle all target specific shuffles
24488 case X86ISD::PALIGNR:
24489 case X86ISD::UNPCKH:
24490 case X86ISD::UNPCKL:
24491 case X86ISD::MOVHLPS:
24492 case X86ISD::MOVLHPS:
24493 case X86ISD::PSHUFB:
24494 case X86ISD::PSHUFD:
24495 case X86ISD::PSHUFHW:
24496 case X86ISD::PSHUFLW:
24497 case X86ISD::MOVSS:
24498 case X86ISD::MOVSD:
24499 case X86ISD::VPERMILPI:
24500 case X86ISD::VPERM2X128:
24501 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
24502 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
24503 case ISD::INTRINSIC_WO_CHAIN:
24504 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
24505 case X86ISD::INSERTPS:
24506 return PerformINSERTPSCombine(N, DAG, Subtarget);
24507 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
24508 }
24510 return SDValue();
24511 }
24513 /// isTypeDesirableForOp - Return true if the target has native support for
24514 /// the specified value type and it is 'desirable' to use the type for the
24515 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
24516 /// instruction encodings are longer and some i16 instructions are slow.
24517 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
24518 if (!isTypeLegal(VT))
24519 return false;
24520 if (VT != MVT::i16)
24521 return true;
24523 switch (Opc) {
24524 default:
24525 return true;
24526 case ISD::LOAD:
24527 case ISD::SIGN_EXTEND:
24528 case ISD::ZERO_EXTEND:
24529 case ISD::ANY_EXTEND:
24530 case ISD::SHL:
24531 case ISD::SRL:
24532 case ISD::SUB:
24533 case ISD::ADD:
24534 case ISD::MUL:
24535 case ISD::AND:
24536 case ISD::OR:
24537 case ISD::XOR:
24538 return false;
24539 }
24540 }
24542 /// IsDesirableToPromoteOp - This method query the target whether it is
24543 /// beneficial for dag combiner to promote the specified node. If true, it
24544 /// should return the desired promotion type by reference.
24545 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
24546 EVT VT = Op.getValueType();
24547 if (VT != MVT::i16)
24548 return false;
24550 bool Promote = false;
24551 bool Commute = false;
24552 switch (Op.getOpcode()) {
24553 default: break;
24554 case ISD::LOAD: {
24555 LoadSDNode *LD = cast<LoadSDNode>(Op);
24556 // If the non-extending load has a single use and it's not live out, then it
24557 // might be folded.
24558 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
24559 Op.hasOneUse()*/) {
24560 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
24561 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
24562 // The only case where we'd want to promote LOAD (rather then it being
24563 // promoted as an operand is when it's only use is liveout.
24564 if (UI->getOpcode() != ISD::CopyToReg)
24565 return false;
24566 }
24567 }
24568 Promote = true;
24569 break;
24570 }
24571 case ISD::SIGN_EXTEND:
24572 case ISD::ZERO_EXTEND:
24573 case ISD::ANY_EXTEND:
24574 Promote = true;
24575 break;
24576 case ISD::SHL:
24577 case ISD::SRL: {
24578 SDValue N0 = Op.getOperand(0);
24579 // Look out for (store (shl (load), x)).
24580 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
24581 return false;
24582 Promote = true;
24583 break;
24584 }
24585 case ISD::ADD:
24586 case ISD::MUL:
24587 case ISD::AND:
24588 case ISD::OR:
24589 case ISD::XOR:
24590 Commute = true;
24591 // fallthrough
24592 case ISD::SUB: {
24593 SDValue N0 = Op.getOperand(0);
24594 SDValue N1 = Op.getOperand(1);
24595 if (!Commute && MayFoldLoad(N1))
24596 return false;
24597 // Avoid disabling potential load folding opportunities.
24598 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
24599 return false;
24600 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
24601 return false;
24602 Promote = true;
24603 }
24604 }
24606 PVT = MVT::i32;
24607 return Promote;
24608 }
24610 //===----------------------------------------------------------------------===//
24611 // X86 Inline Assembly Support
24612 //===----------------------------------------------------------------------===//
24614 namespace {
24615 // Helper to match a string separated by whitespace.
24616 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
24617 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
24619 for (unsigned i = 0, e = args.size(); i != e; ++i) {
24620 StringRef piece(*args[i]);
24621 if (!s.startswith(piece)) // Check if the piece matches.
24622 return false;
24624 s = s.substr(piece.size());
24625 StringRef::size_type pos = s.find_first_not_of(" \t");
24626 if (pos == 0) // We matched a prefix.
24627 return false;
24629 s = s.substr(pos);
24630 }
24632 return s.empty();
24633 }
24634 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
24635 }
24637 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
24639 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
24640 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
24641 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
24642 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
24644 if (AsmPieces.size() == 3)
24645 return true;
24646 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
24647 return true;
24648 }
24649 }
24650 return false;
24651 }
24653 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
24654 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
24656 std::string AsmStr = IA->getAsmString();
24658 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
24659 if (!Ty || Ty->getBitWidth() % 16 != 0)
24660 return false;
24662 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
24663 SmallVector<StringRef, 4> AsmPieces;
24664 SplitString(AsmStr, AsmPieces, ";\n");
24666 switch (AsmPieces.size()) {
24667 default: return false;
24668 case 1:
24669 // FIXME: this should verify that we are targeting a 486 or better. If not,
24670 // we will turn this bswap into something that will be lowered to logical
24671 // ops instead of emitting the bswap asm. For now, we don't support 486 or
24672 // lower so don't worry about this.
24673 // bswap $0
24674 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
24675 matchAsm(AsmPieces[0], "bswapl", "$0") ||
24676 matchAsm(AsmPieces[0], "bswapq", "$0") ||
24677 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
24678 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
24679 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
24680 // No need to check constraints, nothing other than the equivalent of
24681 // "=r,0" would be valid here.
24682 return IntrinsicLowering::LowerToByteSwap(CI);
24683 }
24685 // rorw $$8, ${0:w} --> llvm.bswap.i16
24686 if (CI->getType()->isIntegerTy(16) &&
24687 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24688 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
24689 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
24690 AsmPieces.clear();
24691 const std::string &ConstraintsStr = IA->getConstraintString();
24692 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24693 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24694 if (clobbersFlagRegisters(AsmPieces))
24695 return IntrinsicLowering::LowerToByteSwap(CI);
24696 }
24697 break;
24698 case 3:
24699 if (CI->getType()->isIntegerTy(32) &&
24700 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24701 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
24702 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
24703 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
24704 AsmPieces.clear();
24705 const std::string &ConstraintsStr = IA->getConstraintString();
24706 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24707 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24708 if (clobbersFlagRegisters(AsmPieces))
24709 return IntrinsicLowering::LowerToByteSwap(CI);
24710 }
24712 if (CI->getType()->isIntegerTy(64)) {
24713 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
24714 if (Constraints.size() >= 2 &&
24715 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
24716 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
24717 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
24718 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
24719 matchAsm(AsmPieces[1], "bswap", "%edx") &&
24720 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
24721 return IntrinsicLowering::LowerToByteSwap(CI);
24722 }
24723 }
24724 break;
24725 }
24726 return false;
24727 }
24729 /// getConstraintType - Given a constraint letter, return the type of
24730 /// constraint it is for this target.
24731 X86TargetLowering::ConstraintType
24732 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
24733 if (Constraint.size() == 1) {
24734 switch (Constraint[0]) {
24735 case 'R':
24736 case 'q':
24737 case 'Q':
24738 case 'f':
24739 case 't':
24740 case 'u':
24741 case 'y':
24742 case 'x':
24743 case 'Y':
24744 case 'l':
24745 return C_RegisterClass;
24746 case 'a':
24747 case 'b':
24748 case 'c':
24749 case 'd':
24750 case 'S':
24751 case 'D':
24752 case 'A':
24753 return C_Register;
24754 case 'I':
24755 case 'J':
24756 case 'K':
24757 case 'L':
24758 case 'M':
24759 case 'N':
24760 case 'G':
24761 case 'C':
24762 case 'e':
24763 case 'Z':
24764 return C_Other;
24765 default:
24766 break;
24767 }
24768 }
24769 return TargetLowering::getConstraintType(Constraint);
24770 }
24772 /// Examine constraint type and operand type and determine a weight value.
24773 /// This object must already have been set up with the operand type
24774 /// and the current alternative constraint selected.
24775 TargetLowering::ConstraintWeight
24776 X86TargetLowering::getSingleConstraintMatchWeight(
24777 AsmOperandInfo &info, const char *constraint) const {
24778 ConstraintWeight weight = CW_Invalid;
24779 Value *CallOperandVal = info.CallOperandVal;
24780 // If we don't have a value, we can't do a match,
24781 // but allow it at the lowest weight.
24782 if (!CallOperandVal)
24783 return CW_Default;
24784 Type *type = CallOperandVal->getType();
24785 // Look at the constraint type.
24786 switch (*constraint) {
24787 default:
24788 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
24789 case 'R':
24790 case 'q':
24791 case 'Q':
24792 case 'a':
24793 case 'b':
24794 case 'c':
24795 case 'd':
24796 case 'S':
24797 case 'D':
24798 case 'A':
24799 if (CallOperandVal->getType()->isIntegerTy())
24800 weight = CW_SpecificReg;
24801 break;
24802 case 'f':
24803 case 't':
24804 case 'u':
24805 if (type->isFloatingPointTy())
24806 weight = CW_SpecificReg;
24807 break;
24808 case 'y':
24809 if (type->isX86_MMXTy() && Subtarget->hasMMX())
24810 weight = CW_SpecificReg;
24811 break;
24812 case 'x':
24813 case 'Y':
24814 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
24815 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
24816 weight = CW_Register;
24817 break;
24818 case 'I':
24819 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
24820 if (C->getZExtValue() <= 31)
24821 weight = CW_Constant;
24822 }
24823 break;
24824 case 'J':
24825 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24826 if (C->getZExtValue() <= 63)
24827 weight = CW_Constant;
24828 }
24829 break;
24830 case 'K':
24831 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24832 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
24833 weight = CW_Constant;
24834 }
24835 break;
24836 case 'L':
24837 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24838 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
24839 weight = CW_Constant;
24840 }
24841 break;
24842 case 'M':
24843 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24844 if (C->getZExtValue() <= 3)
24845 weight = CW_Constant;
24846 }
24847 break;
24848 case 'N':
24849 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24850 if (C->getZExtValue() <= 0xff)
24851 weight = CW_Constant;
24852 }
24853 break;
24854 case 'G':
24855 case 'C':
24856 if (dyn_cast<ConstantFP>(CallOperandVal)) {
24857 weight = CW_Constant;
24858 }
24859 break;
24860 case 'e':
24861 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24862 if ((C->getSExtValue() >= -0x80000000LL) &&
24863 (C->getSExtValue() <= 0x7fffffffLL))
24864 weight = CW_Constant;
24865 }
24866 break;
24867 case 'Z':
24868 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24869 if (C->getZExtValue() <= 0xffffffff)
24870 weight = CW_Constant;
24871 }
24872 break;
24873 }
24874 return weight;
24875 }
24877 /// LowerXConstraint - try to replace an X constraint, which matches anything,
24878 /// with another that has more specific requirements based on the type of the
24879 /// corresponding operand.
24880 const char *X86TargetLowering::
24881 LowerXConstraint(EVT ConstraintVT) const {
24882 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
24883 // 'f' like normal targets.
24884 if (ConstraintVT.isFloatingPoint()) {
24885 if (Subtarget->hasSSE2())
24886 return "Y";
24887 if (Subtarget->hasSSE1())
24888 return "x";
24889 }
24891 return TargetLowering::LowerXConstraint(ConstraintVT);
24892 }
24894 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
24895 /// vector. If it is invalid, don't add anything to Ops.
24896 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
24897 std::string &Constraint,
24898 std::vector<SDValue>&Ops,
24899 SelectionDAG &DAG) const {
24900 SDValue Result;
24902 // Only support length 1 constraints for now.
24903 if (Constraint.length() > 1) return;
24905 char ConstraintLetter = Constraint[0];
24906 switch (ConstraintLetter) {
24907 default: break;
24908 case 'I':
24909 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24910 if (C->getZExtValue() <= 31) {
24911 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24912 break;
24913 }
24914 }
24915 return;
24916 case 'J':
24917 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24918 if (C->getZExtValue() <= 63) {
24919 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24920 break;
24921 }
24922 }
24923 return;
24924 case 'K':
24925 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24926 if (isInt<8>(C->getSExtValue())) {
24927 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24928 break;
24929 }
24930 }
24931 return;
24932 case 'N':
24933 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24934 if (C->getZExtValue() <= 255) {
24935 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24936 break;
24937 }
24938 }
24939 return;
24940 case 'e': {
24941 // 32-bit signed value
24942 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24943 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24944 C->getSExtValue())) {
24945 // Widen to 64 bits here to get it sign extended.
24946 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
24947 break;
24948 }
24949 // FIXME gcc accepts some relocatable values here too, but only in certain
24950 // memory models; it's complicated.
24951 }
24952 return;
24953 }
24954 case 'Z': {
24955 // 32-bit unsigned value
24956 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24957 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24958 C->getZExtValue())) {
24959 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24960 break;
24961 }
24962 }
24963 // FIXME gcc accepts some relocatable values here too, but only in certain
24964 // memory models; it's complicated.
24965 return;
24966 }
24967 case 'i': {
24968 // Literal immediates are always ok.
24969 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
24970 // Widen to 64 bits here to get it sign extended.
24971 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
24972 break;
24973 }
24975 // In any sort of PIC mode addresses need to be computed at runtime by
24976 // adding in a register or some sort of table lookup. These can't
24977 // be used as immediates.
24978 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
24979 return;
24981 // If we are in non-pic codegen mode, we allow the address of a global (with
24982 // an optional displacement) to be used with 'i'.
24983 GlobalAddressSDNode *GA = nullptr;
24984 int64_t Offset = 0;
24986 // Match either (GA), (GA+C), (GA+C1+C2), etc.
24987 while (1) {
24988 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
24989 Offset += GA->getOffset();
24990 break;
24991 } else if (Op.getOpcode() == ISD::ADD) {
24992 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24993 Offset += C->getZExtValue();
24994 Op = Op.getOperand(0);
24995 continue;
24996 }
24997 } else if (Op.getOpcode() == ISD::SUB) {
24998 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24999 Offset += -C->getZExtValue();
25000 Op = Op.getOperand(0);
25001 continue;
25002 }
25003 }
25005 // Otherwise, this isn't something we can handle, reject it.
25006 return;
25007 }
25009 const GlobalValue *GV = GA->getGlobal();
25010 // If we require an extra load to get this address, as in PIC mode, we
25011 // can't accept it.
25012 if (isGlobalStubReference(
25013 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
25014 return;
25016 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
25017 GA->getValueType(0), Offset);
25018 break;
25019 }
25020 }
25022 if (Result.getNode()) {
25023 Ops.push_back(Result);
25024 return;
25025 }
25026 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
25027 }
25029 std::pair<unsigned, const TargetRegisterClass*>
25030 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
25031 MVT VT) const {
25032 // First, see if this is a constraint that directly corresponds to an LLVM
25033 // register class.
25034 if (Constraint.size() == 1) {
25035 // GCC Constraint Letters
25036 switch (Constraint[0]) {
25037 default: break;
25038 // TODO: Slight differences here in allocation order and leaving
25039 // RIP in the class. Do they matter any more here than they do
25040 // in the normal allocation?
25041 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
25042 if (Subtarget->is64Bit()) {
25043 if (VT == MVT::i32 || VT == MVT::f32)
25044 return std::make_pair(0U, &X86::GR32RegClass);
25045 if (VT == MVT::i16)
25046 return std::make_pair(0U, &X86::GR16RegClass);
25047 if (VT == MVT::i8 || VT == MVT::i1)
25048 return std::make_pair(0U, &X86::GR8RegClass);
25049 if (VT == MVT::i64 || VT == MVT::f64)
25050 return std::make_pair(0U, &X86::GR64RegClass);
25051 break;
25052 }
25053 // 32-bit fallthrough
25054 case 'Q': // Q_REGS
25055 if (VT == MVT::i32 || VT == MVT::f32)
25056 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
25057 if (VT == MVT::i16)
25058 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
25059 if (VT == MVT::i8 || VT == MVT::i1)
25060 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
25061 if (VT == MVT::i64)
25062 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
25063 break;
25064 case 'r': // GENERAL_REGS
25065 case 'l': // INDEX_REGS
25066 if (VT == MVT::i8 || VT == MVT::i1)
25067 return std::make_pair(0U, &X86::GR8RegClass);
25068 if (VT == MVT::i16)
25069 return std::make_pair(0U, &X86::GR16RegClass);
25070 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
25071 return std::make_pair(0U, &X86::GR32RegClass);
25072 return std::make_pair(0U, &X86::GR64RegClass);
25073 case 'R': // LEGACY_REGS
25074 if (VT == MVT::i8 || VT == MVT::i1)
25075 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
25076 if (VT == MVT::i16)
25077 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
25078 if (VT == MVT::i32 || !Subtarget->is64Bit())
25079 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
25080 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
25081 case 'f': // FP Stack registers.
25082 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
25083 // value to the correct fpstack register class.
25084 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
25085 return std::make_pair(0U, &X86::RFP32RegClass);
25086 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
25087 return std::make_pair(0U, &X86::RFP64RegClass);
25088 return std::make_pair(0U, &X86::RFP80RegClass);
25089 case 'y': // MMX_REGS if MMX allowed.
25090 if (!Subtarget->hasMMX()) break;
25091 return std::make_pair(0U, &X86::VR64RegClass);
25092 case 'Y': // SSE_REGS if SSE2 allowed
25093 if (!Subtarget->hasSSE2()) break;
25094 // FALL THROUGH.
25095 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
25096 if (!Subtarget->hasSSE1()) break;
25098 switch (VT.SimpleTy) {
25099 default: break;
25100 // Scalar SSE types.
25101 case MVT::f32:
25102 case MVT::i32:
25103 return std::make_pair(0U, &X86::FR32RegClass);
25104 case MVT::f64:
25105 case MVT::i64:
25106 return std::make_pair(0U, &X86::FR64RegClass);
25107 // Vector types.
25108 case MVT::v16i8:
25109 case MVT::v8i16:
25110 case MVT::v4i32:
25111 case MVT::v2i64:
25112 case MVT::v4f32:
25113 case MVT::v2f64:
25114 return std::make_pair(0U, &X86::VR128RegClass);
25115 // AVX types.
25116 case MVT::v32i8:
25117 case MVT::v16i16:
25118 case MVT::v8i32:
25119 case MVT::v4i64:
25120 case MVT::v8f32:
25121 case MVT::v4f64:
25122 return std::make_pair(0U, &X86::VR256RegClass);
25123 case MVT::v8f64:
25124 case MVT::v16f32:
25125 case MVT::v16i32:
25126 case MVT::v8i64:
25127 return std::make_pair(0U, &X86::VR512RegClass);
25128 }
25129 break;
25130 }
25131 }
25133 // Use the default implementation in TargetLowering to convert the register
25134 // constraint into a member of a register class.
25135 std::pair<unsigned, const TargetRegisterClass*> Res;
25136 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
25138 // Not found as a standard register?
25139 if (!Res.second) {
25140 // Map st(0) -> st(7) -> ST0
25141 if (Constraint.size() == 7 && Constraint[0] == '{' &&
25142 tolower(Constraint[1]) == 's' &&
25143 tolower(Constraint[2]) == 't' &&
25144 Constraint[3] == '(' &&
25145 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
25146 Constraint[5] == ')' &&
25147 Constraint[6] == '}') {
25149 Res.first = X86::FP0+Constraint[4]-'0';
25150 Res.second = &X86::RFP80RegClass;
25151 return Res;
25152 }
25154 // GCC allows "st(0)" to be called just plain "st".
25155 if (StringRef("{st}").equals_lower(Constraint)) {
25156 Res.first = X86::FP0;
25157 Res.second = &X86::RFP80RegClass;
25158 return Res;
25159 }
25161 // flags -> EFLAGS
25162 if (StringRef("{flags}").equals_lower(Constraint)) {
25163 Res.first = X86::EFLAGS;
25164 Res.second = &X86::CCRRegClass;
25165 return Res;
25166 }
25168 // 'A' means EAX + EDX.
25169 if (Constraint == "A") {
25170 Res.first = X86::EAX;
25171 Res.second = &X86::GR32_ADRegClass;
25172 return Res;
25173 }
25174 return Res;
25175 }
25177 // Otherwise, check to see if this is a register class of the wrong value
25178 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
25179 // turn into {ax},{dx}.
25180 if (Res.second->hasType(VT))
25181 return Res; // Correct type already, nothing to do.
25183 // All of the single-register GCC register classes map their values onto
25184 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
25185 // really want an 8-bit or 32-bit register, map to the appropriate register
25186 // class and return the appropriate register.
25187 if (Res.second == &X86::GR16RegClass) {
25188 if (VT == MVT::i8 || VT == MVT::i1) {
25189 unsigned DestReg = 0;
25190 switch (Res.first) {
25191 default: break;
25192 case X86::AX: DestReg = X86::AL; break;
25193 case X86::DX: DestReg = X86::DL; break;
25194 case X86::CX: DestReg = X86::CL; break;
25195 case X86::BX: DestReg = X86::BL; break;
25196 }
25197 if (DestReg) {
25198 Res.first = DestReg;
25199 Res.second = &X86::GR8RegClass;
25200 }
25201 } else if (VT == MVT::i32 || VT == MVT::f32) {
25202 unsigned DestReg = 0;
25203 switch (Res.first) {
25204 default: break;
25205 case X86::AX: DestReg = X86::EAX; break;
25206 case X86::DX: DestReg = X86::EDX; break;
25207 case X86::CX: DestReg = X86::ECX; break;
25208 case X86::BX: DestReg = X86::EBX; break;
25209 case X86::SI: DestReg = X86::ESI; break;
25210 case X86::DI: DestReg = X86::EDI; break;
25211 case X86::BP: DestReg = X86::EBP; break;
25212 case X86::SP: DestReg = X86::ESP; break;
25213 }
25214 if (DestReg) {
25215 Res.first = DestReg;
25216 Res.second = &X86::GR32RegClass;
25217 }
25218 } else if (VT == MVT::i64 || VT == MVT::f64) {
25219 unsigned DestReg = 0;
25220 switch (Res.first) {
25221 default: break;
25222 case X86::AX: DestReg = X86::RAX; break;
25223 case X86::DX: DestReg = X86::RDX; break;
25224 case X86::CX: DestReg = X86::RCX; break;
25225 case X86::BX: DestReg = X86::RBX; break;
25226 case X86::SI: DestReg = X86::RSI; break;
25227 case X86::DI: DestReg = X86::RDI; break;
25228 case X86::BP: DestReg = X86::RBP; break;
25229 case X86::SP: DestReg = X86::RSP; break;
25230 }
25231 if (DestReg) {
25232 Res.first = DestReg;
25233 Res.second = &X86::GR64RegClass;
25234 }
25235 }
25236 } else if (Res.second == &X86::FR32RegClass ||
25237 Res.second == &X86::FR64RegClass ||
25238 Res.second == &X86::VR128RegClass ||
25239 Res.second == &X86::VR256RegClass ||
25240 Res.second == &X86::FR32XRegClass ||
25241 Res.second == &X86::FR64XRegClass ||
25242 Res.second == &X86::VR128XRegClass ||
25243 Res.second == &X86::VR256XRegClass ||
25244 Res.second == &X86::VR512RegClass) {
25245 // Handle references to XMM physical registers that got mapped into the
25246 // wrong class. This can happen with constraints like {xmm0} where the
25247 // target independent register mapper will just pick the first match it can
25248 // find, ignoring the required type.
25250 if (VT == MVT::f32 || VT == MVT::i32)
25251 Res.second = &X86::FR32RegClass;
25252 else if (VT == MVT::f64 || VT == MVT::i64)
25253 Res.second = &X86::FR64RegClass;
25254 else if (X86::VR128RegClass.hasType(VT))
25255 Res.second = &X86::VR128RegClass;
25256 else if (X86::VR256RegClass.hasType(VT))
25257 Res.second = &X86::VR256RegClass;
25258 else if (X86::VR512RegClass.hasType(VT))
25259 Res.second = &X86::VR512RegClass;
25260 }
25262 return Res;
25263 }
25265 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
25266 Type *Ty) const {
25267 // Scaling factors are not free at all.
25268 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
25269 // will take 2 allocations in the out of order engine instead of 1
25270 // for plain addressing mode, i.e. inst (reg1).
25271 // E.g.,
25272 // vaddps (%rsi,%drx), %ymm0, %ymm1
25273 // Requires two allocations (one for the load, one for the computation)
25274 // whereas:
25275 // vaddps (%rsi), %ymm0, %ymm1
25276 // Requires just 1 allocation, i.e., freeing allocations for other operations
25277 // and having less micro operations to execute.
25278 //
25279 // For some X86 architectures, this is even worse because for instance for
25280 // stores, the complex addressing mode forces the instruction to use the
25281 // "load" ports instead of the dedicated "store" port.
25282 // E.g., on Haswell:
25283 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
25284 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
25285 if (isLegalAddressingMode(AM, Ty))
25286 // Scale represents reg2 * scale, thus account for 1
25287 // as soon as we use a second register.
25288 return AM.Scale != 0;
25289 return -1;
25290 }
25292 bool X86TargetLowering::isTargetFTOL() const {
25293 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();
25294 }